// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from stm32wb05.svd, see https://github.com/tinygo-org/stm32-svd

//go:build stm32 && stm32wb05

/*
// STM32WB05
*/

package stm32

import (
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "STM32WB05"
	CPU          = "CM0+"
	FPUPresent   = false
	NVICPrioBits = 2
)

// Interrupt numbers.
const (
	// 4kb addressable space
	IRQ_FLASH = 0

	IRQ_RCC = 1

	IRQ_PVD = 2

	// I2C address block description
	IRQ_I2C1 = 3

	// SPI address block description
	IRQ_SPI3 = 7

	IRQ_USART = 8

	IRQ_LPUART = 9

	IRQ_TIM2 = 10

	IRQ_RTC = 11

	IRQ_ADC = 12

	IRQ_PKA = 13

	IRQ_GPIOA = 15

	IRQ_GPIOB = 16

	IRQ_DMA = 17

	IRQ_RADIO_TXRX = 18

	IRQ_RADIO_ERROR = 20

	IRQ_RADIO_CPU_WKUP = 23

	IRQ_RADIO_TXRX_WKUP = 24

	IRQ_TIM16 = 26

	IRQ_TIM17 = 27

	IRQ_TRNG = 28

	// Highest interrupt number on this device.
	IRQ_max = 28
)

// Pseudo function call that is replaced by the compiler with the actual
// functions registered through interrupt.New.
//
//go:linkname callHandlers runtime/interrupt.callHandlers
func callHandlers(num int)

//export FLASH_IRQHandler
func interruptFLASH() {
	callHandlers(IRQ_FLASH)
}

//export RCC_IRQHandler
func interruptRCC() {
	callHandlers(IRQ_RCC)
}

//export PVD_IRQHandler
func interruptPVD() {
	callHandlers(IRQ_PVD)
}

//export I2C1_IRQHandler
func interruptI2C1() {
	callHandlers(IRQ_I2C1)
}

//export SPI3_IRQHandler
func interruptSPI3() {
	callHandlers(IRQ_SPI3)
}

//export USART_IRQHandler
func interruptUSART() {
	callHandlers(IRQ_USART)
}

//export LPUART_IRQHandler
func interruptLPUART() {
	callHandlers(IRQ_LPUART)
}

//export TIM2_IRQHandler
func interruptTIM2() {
	callHandlers(IRQ_TIM2)
}

//export RTC_IRQHandler
func interruptRTC() {
	callHandlers(IRQ_RTC)
}

//export ADC_IRQHandler
func interruptADC() {
	callHandlers(IRQ_ADC)
}

//export PKA_IRQHandler
func interruptPKA() {
	callHandlers(IRQ_PKA)
}

//export GPIOA_IRQHandler
func interruptGPIOA() {
	callHandlers(IRQ_GPIOA)
}

//export GPIOB_IRQHandler
func interruptGPIOB() {
	callHandlers(IRQ_GPIOB)
}

//export DMA_IRQHandler
func interruptDMA() {
	callHandlers(IRQ_DMA)
}

//export RADIO_TXRX_IRQHandler
func interruptRADIO_TXRX() {
	callHandlers(IRQ_RADIO_TXRX)
}

//export RADIO_ERROR_IRQHandler
func interruptRADIO_ERROR() {
	callHandlers(IRQ_RADIO_ERROR)
}

//export RADIO_CPU_WKUP_IRQHandler
func interruptRADIO_CPU_WKUP() {
	callHandlers(IRQ_RADIO_CPU_WKUP)
}

//export RADIO_TXRX_WKUP_IRQHandler
func interruptRADIO_TXRX_WKUP() {
	callHandlers(IRQ_RADIO_TXRX_WKUP)
}

//export TIM16_IRQHandler
func interruptTIM16() {
	callHandlers(IRQ_TIM16)
}

//export TIM17_IRQHandler
func interruptTIM17() {
	callHandlers(IRQ_TIM17)
}

//export TRNG_IRQHandler
func interruptTRNG() {
	callHandlers(IRQ_TRNG)
}

// Peripherals.
var (
	ADC = (*ADC_Type)(unsafe.Pointer(uintptr(0x41006000)))

	// CRC address block description
	CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x48200000)))

	DMA = (*DMA_Type)(unsafe.Pointer(uintptr(0x48700000)))

	DMAMUX = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x48800000)))

	GPIOA = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48000000)))

	GPIOB = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48100000)))

	IWDG = (*IWDG_Type)(unsafe.Pointer(uintptr(0x40003000)))

	LPUART = (*LPUART_Type)(unsafe.Pointer(uintptr(0x41005000)))

	// 4kb addressable space
	FLASH_CTRL = (*FLASH_CTRL_Type)(unsafe.Pointer(uintptr(0x40001000)))

	PKA = (*PKA_Type)(unsafe.Pointer(uintptr(0x48300000)))

	PWRC = (*PWRC_Type)(unsafe.Pointer(uintptr(0x48500000)))

	RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x48600000)))

	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x40004000)))

	SYSTEM_CTRL = (*SYSTEM_CTRL_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// I2C address block description
	I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x41000000)))

	RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x48400000)))

	// SPI address block description
	SPI3 = (*SPI_Type)(unsafe.Pointer(uintptr(0x41007000)))

	TIM2 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40002000)))

	TIM16 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40005000)))

	TIM17 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40006000)))

	USART = (*USART_Type)(unsafe.Pointer(uintptr(0x41004000)))

	BLUE = (*BLUE_Type)(unsafe.Pointer(uintptr(0x60000000)))

	GLOBALSTATMACH = (*GLOBALSTATMACH_Type)(unsafe.Pointer(uintptr(0x200000c0)))

	RADIO_CONTROL = (*RADIO_CONTROL_Type)(unsafe.Pointer(uintptr(0x60001000)))

	RADIO = (*RADIO_Type)(unsafe.Pointer(uintptr(0x60001500)))

	RRM = (*RRM_Type)(unsafe.Pointer(uintptr(0x60001400)))

	WAKEUP = (*WAKEUP_Type)(unsafe.Pointer(uintptr(0x60001800)))
)

type ADC_Type struct {
	VERSION_ID volatile.Register32 // 0x0
	CONF       volatile.Register32 // 0x4
	CTRL       volatile.Register32 // 0x8
	_          [8]byte
	SWITCH     volatile.Register32 // 0x14
	_          [4]byte
	DS_CONF    volatile.Register32 // 0x1C
	SEQ_1      volatile.Register32 // 0x20
	SEQ_2      volatile.Register32 // 0x24
	COMP_1     volatile.Register32 // 0x28
	COMP_2     volatile.Register32 // 0x2C
	COMP_3     volatile.Register32 // 0x30
	COMP_4     volatile.Register32 // 0x34
	COMP_SEL   volatile.Register32 // 0x38
	WD_TH      volatile.Register32 // 0x3C
	WD_CONF    volatile.Register32 // 0x40
	DS_DATAOUT volatile.Register32 // 0x44
	_          [4]byte
	IRQ_STATUS volatile.Register32 // 0x4C
	IRQ_ENABLE volatile.Register32 // 0x50
}

// ADC.VERSION_ID: VERSION_ID register
func (o *ADC_Type) SetVERSION_ID(value uint32) {
	volatile.StoreUint32(&o.VERSION_ID.Reg, volatile.LoadUint32(&o.VERSION_ID.Reg)&^(0xff)|value)
}
func (o *ADC_Type) GetVERSION_ID() uint32 {
	return volatile.LoadUint32(&o.VERSION_ID.Reg) & 0xff
}

// ADC.CONF: CONF register
func (o *ADC_Type) SetCONF_CONT(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCONF_CONT() uint32 {
	return volatile.LoadUint32(&o.CONF.Reg) & 0x1
}
func (o *ADC_Type) SetCONF_SEQUENCE(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCONF_SEQUENCE() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCONF_SEQ_LEN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x3c)|value<<2)
}
func (o *ADC_Type) GetCONF_SEQ_LEN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x3c) >> 2
}
func (o *ADC_Type) SetCONF_SMPS_SYNCHRO_ENA(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetCONF_SMPS_SYNCHRO_ENA() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetCONF_SAMPLE_RATE_LSB(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x600)|value<<9)
}
func (o *ADC_Type) GetCONF_SAMPLE_RATE_LSB() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x600) >> 9
}
func (o *ADC_Type) SetCONF_SAMPLE_RATE(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x1800)|value<<11)
}
func (o *ADC_Type) GetCONF_SAMPLE_RATE() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x1800) >> 11
}
func (o *ADC_Type) SetCONF_DMA_DS_ENA(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCONF_DMA_DS_ENA() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCONF_OVR_DS_CFG(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCONF_OVR_DS_CFG() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetCONF_BIT_INVERT_SN(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetCONF_BIT_INVERT_SN() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetCONF_BIT_INVERT_DIFF(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetCONF_BIT_INVERT_DIFF() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetCONF_ADC_CONT_1V2(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetCONF_ADC_CONT_1V2() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0x80000) >> 19
}
func (o *ADC_Type) SetCONF_SAMPLE_RATE_MSB(value uint32) {
	volatile.StoreUint32(&o.CONF.Reg, volatile.LoadUint32(&o.CONF.Reg)&^(0xe00000)|value<<21)
}
func (o *ADC_Type) GetCONF_SAMPLE_RATE_MSB() uint32 {
	return (volatile.LoadUint32(&o.CONF.Reg) & 0xe00000) >> 21
}

// ADC.CTRL: CTRL register
func (o *ADC_Type) SetCTRL_ADC_ON_OFF(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCTRL_ADC_ON_OFF() uint32 {
	return volatile.LoadUint32(&o.CTRL.Reg) & 0x1
}
func (o *ADC_Type) SetCTRL_START_CONV(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCTRL_START_CONV() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCTRL_STOP_OP_MODE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCTRL_STOP_OP_MODE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCTRL_TEST_MODE(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCTRL_TEST_MODE() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCTRL_ADC_LDO_ENA(value uint32) {
	volatile.StoreUint32(&o.CTRL.Reg, volatile.LoadUint32(&o.CTRL.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCTRL_ADC_LDO_ENA() uint32 {
	return (volatile.LoadUint32(&o.CTRL.Reg) & 0x20) >> 5
}

// ADC.SWITCH: SWITCH register
func (o *ADC_Type) SetSWITCH_SE_VIN_0(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0x3)|value)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_0() uint32 {
	return volatile.LoadUint32(&o.SWITCH.Reg) & 0x3
}
func (o *ADC_Type) SetSWITCH_SE_VIN_1(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0xc)|value<<2)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_1() uint32 {
	return (volatile.LoadUint32(&o.SWITCH.Reg) & 0xc) >> 2
}
func (o *ADC_Type) SetSWITCH_SE_VIN_2(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0x30)|value<<4)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_2() uint32 {
	return (volatile.LoadUint32(&o.SWITCH.Reg) & 0x30) >> 4
}
func (o *ADC_Type) SetSWITCH_SE_VIN_3(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0xc0)|value<<6)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_3() uint32 {
	return (volatile.LoadUint32(&o.SWITCH.Reg) & 0xc0) >> 6
}
func (o *ADC_Type) SetSWITCH_SE_VIN_4(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0x300)|value<<8)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_4() uint32 {
	return (volatile.LoadUint32(&o.SWITCH.Reg) & 0x300) >> 8
}
func (o *ADC_Type) SetSWITCH_SE_VIN_5(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0xc00)|value<<10)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_5() uint32 {
	return (volatile.LoadUint32(&o.SWITCH.Reg) & 0xc00) >> 10
}
func (o *ADC_Type) SetSWITCH_SE_VIN_6(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0x3000)|value<<12)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_6() uint32 {
	return (volatile.LoadUint32(&o.SWITCH.Reg) & 0x3000) >> 12
}
func (o *ADC_Type) SetSWITCH_SE_VIN_7(value uint32) {
	volatile.StoreUint32(&o.SWITCH.Reg, volatile.LoadUint32(&o.SWITCH.Reg)&^(0xc000)|value<<14)
}
func (o *ADC_Type) GetSWITCH_SE_VIN_7() uint32 {
	return (volatile.LoadUint32(&o.SWITCH.Reg) & 0xc000) >> 14
}

// ADC.DS_CONF: DS_CONF register
func (o *ADC_Type) SetDS_CONF_DS_RATIO(value uint32) {
	volatile.StoreUint32(&o.DS_CONF.Reg, volatile.LoadUint32(&o.DS_CONF.Reg)&^(0x7)|value)
}
func (o *ADC_Type) GetDS_CONF_DS_RATIO() uint32 {
	return volatile.LoadUint32(&o.DS_CONF.Reg) & 0x7
}
func (o *ADC_Type) SetDS_CONF_DS_WIDTH(value uint32) {
	volatile.StoreUint32(&o.DS_CONF.Reg, volatile.LoadUint32(&o.DS_CONF.Reg)&^(0x38)|value<<3)
}
func (o *ADC_Type) GetDS_CONF_DS_WIDTH() uint32 {
	return (volatile.LoadUint32(&o.DS_CONF.Reg) & 0x38) >> 3
}

// ADC.SEQ_1: SEQ_1 register
func (o *ADC_Type) SetSEQ_1_SEQ0(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf)|value)
}
func (o *ADC_Type) GetSEQ_1_SEQ0() uint32 {
	return volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf
}
func (o *ADC_Type) SetSEQ_1_SEQ1(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf0)|value<<4)
}
func (o *ADC_Type) GetSEQ_1_SEQ1() uint32 {
	return (volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf0) >> 4
}
func (o *ADC_Type) SetSEQ_1_SEQ2(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf00)|value<<8)
}
func (o *ADC_Type) GetSEQ_1_SEQ2() uint32 {
	return (volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf00) >> 8
}
func (o *ADC_Type) SetSEQ_1_SEQ3(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf000)|value<<12)
}
func (o *ADC_Type) GetSEQ_1_SEQ3() uint32 {
	return (volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf000) >> 12
}
func (o *ADC_Type) SetSEQ_1_SEQ4(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf0000)|value<<16)
}
func (o *ADC_Type) GetSEQ_1_SEQ4() uint32 {
	return (volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf0000) >> 16
}
func (o *ADC_Type) SetSEQ_1_SEQ5(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf00000)|value<<20)
}
func (o *ADC_Type) GetSEQ_1_SEQ5() uint32 {
	return (volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf00000) >> 20
}
func (o *ADC_Type) SetSEQ_1_SEQ6(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf000000)|value<<24)
}
func (o *ADC_Type) GetSEQ_1_SEQ6() uint32 {
	return (volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf000000) >> 24
}
func (o *ADC_Type) SetSEQ_1_SEQ7(value uint32) {
	volatile.StoreUint32(&o.SEQ_1.Reg, volatile.LoadUint32(&o.SEQ_1.Reg)&^(0xf0000000)|value<<28)
}
func (o *ADC_Type) GetSEQ_1_SEQ7() uint32 {
	return (volatile.LoadUint32(&o.SEQ_1.Reg) & 0xf0000000) >> 28
}

// ADC.SEQ_2: SEQ_2 register
func (o *ADC_Type) SetSEQ_2_SEQ8(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf)|value)
}
func (o *ADC_Type) GetSEQ_2_SEQ8() uint32 {
	return volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf
}
func (o *ADC_Type) SetSEQ_2_SEQ9(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf0)|value<<4)
}
func (o *ADC_Type) GetSEQ_2_SEQ9() uint32 {
	return (volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf0) >> 4
}
func (o *ADC_Type) SetSEQ_2_SEQ10(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf00)|value<<8)
}
func (o *ADC_Type) GetSEQ_2_SEQ10() uint32 {
	return (volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf00) >> 8
}
func (o *ADC_Type) SetSEQ_2_SEQ11(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf000)|value<<12)
}
func (o *ADC_Type) GetSEQ_2_SEQ11() uint32 {
	return (volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf000) >> 12
}
func (o *ADC_Type) SetSEQ_2_SEQ12(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf0000)|value<<16)
}
func (o *ADC_Type) GetSEQ_2_SEQ12() uint32 {
	return (volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf0000) >> 16
}
func (o *ADC_Type) SetSEQ_2_SEQ13(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf00000)|value<<20)
}
func (o *ADC_Type) GetSEQ_2_SEQ13() uint32 {
	return (volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf00000) >> 20
}
func (o *ADC_Type) SetSEQ_2_SEQ14(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf000000)|value<<24)
}
func (o *ADC_Type) GetSEQ_2_SEQ14() uint32 {
	return (volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf000000) >> 24
}
func (o *ADC_Type) SetSEQ_2_SEQ15(value uint32) {
	volatile.StoreUint32(&o.SEQ_2.Reg, volatile.LoadUint32(&o.SEQ_2.Reg)&^(0xf0000000)|value<<28)
}
func (o *ADC_Type) GetSEQ_2_SEQ15() uint32 {
	return (volatile.LoadUint32(&o.SEQ_2.Reg) & 0xf0000000) >> 28
}

// ADC.COMP_1: COMP_1 register
func (o *ADC_Type) SetCOMP_1_GAIN1(value uint32) {
	volatile.StoreUint32(&o.COMP_1.Reg, volatile.LoadUint32(&o.COMP_1.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetCOMP_1_GAIN1() uint32 {
	return volatile.LoadUint32(&o.COMP_1.Reg) & 0xfff
}
func (o *ADC_Type) SetCOMP_1_OFFSET1(value uint32) {
	volatile.StoreUint32(&o.COMP_1.Reg, volatile.LoadUint32(&o.COMP_1.Reg)&^(0xff000)|value<<12)
}
func (o *ADC_Type) GetCOMP_1_OFFSET1() uint32 {
	return (volatile.LoadUint32(&o.COMP_1.Reg) & 0xff000) >> 12
}

// ADC.COMP_2: COMP_2 register
func (o *ADC_Type) SetCOMP_2_GAIN2(value uint32) {
	volatile.StoreUint32(&o.COMP_2.Reg, volatile.LoadUint32(&o.COMP_2.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetCOMP_2_GAIN2() uint32 {
	return volatile.LoadUint32(&o.COMP_2.Reg) & 0xfff
}
func (o *ADC_Type) SetCOMP_2_OFFSET2(value uint32) {
	volatile.StoreUint32(&o.COMP_2.Reg, volatile.LoadUint32(&o.COMP_2.Reg)&^(0xff000)|value<<12)
}
func (o *ADC_Type) GetCOMP_2_OFFSET2() uint32 {
	return (volatile.LoadUint32(&o.COMP_2.Reg) & 0xff000) >> 12
}

// ADC.COMP_3: COMP_3 register
func (o *ADC_Type) SetCOMP_3_GAIN3(value uint32) {
	volatile.StoreUint32(&o.COMP_3.Reg, volatile.LoadUint32(&o.COMP_3.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetCOMP_3_GAIN3() uint32 {
	return volatile.LoadUint32(&o.COMP_3.Reg) & 0xfff
}
func (o *ADC_Type) SetCOMP_3_OFFSET3(value uint32) {
	volatile.StoreUint32(&o.COMP_3.Reg, volatile.LoadUint32(&o.COMP_3.Reg)&^(0xff000)|value<<12)
}
func (o *ADC_Type) GetCOMP_3_OFFSET3() uint32 {
	return (volatile.LoadUint32(&o.COMP_3.Reg) & 0xff000) >> 12
}

// ADC.COMP_4: COMP_4 register
func (o *ADC_Type) SetCOMP_4_GAIN4(value uint32) {
	volatile.StoreUint32(&o.COMP_4.Reg, volatile.LoadUint32(&o.COMP_4.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetCOMP_4_GAIN4() uint32 {
	return volatile.LoadUint32(&o.COMP_4.Reg) & 0xfff
}
func (o *ADC_Type) SetCOMP_4_OFFSET4(value uint32) {
	volatile.StoreUint32(&o.COMP_4.Reg, volatile.LoadUint32(&o.COMP_4.Reg)&^(0xff000)|value<<12)
}
func (o *ADC_Type) GetCOMP_4_OFFSET4() uint32 {
	return (volatile.LoadUint32(&o.COMP_4.Reg) & 0xff000) >> 12
}

// ADC.COMP_SEL: COMP_SEL register
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN0(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0x3)|value)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN0() uint32 {
	return volatile.LoadUint32(&o.COMP_SEL.Reg) & 0x3
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN1(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0xc)|value<<2)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN1() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0xc) >> 2
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN2(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0x30)|value<<4)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN2() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0x30) >> 4
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN3(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0xc0)|value<<6)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN3() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0xc0) >> 6
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN4(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0x300)|value<<8)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN4() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0x300) >> 8
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN5(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0xc00)|value<<10)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN5() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0xc00) >> 10
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN6(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0x3000)|value<<12)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN6() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0x3000) >> 12
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN7(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0xc000)|value<<14)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN7() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0xc000) >> 14
}
func (o *ADC_Type) SetCOMP_SEL_OFFSET_GAIN8(value uint32) {
	volatile.StoreUint32(&o.COMP_SEL.Reg, volatile.LoadUint32(&o.COMP_SEL.Reg)&^(0x30000)|value<<16)
}
func (o *ADC_Type) GetCOMP_SEL_OFFSET_GAIN8() uint32 {
	return (volatile.LoadUint32(&o.COMP_SEL.Reg) & 0x30000) >> 16
}

// ADC.WD_TH: WD_TH register
func (o *ADC_Type) SetWD_TH_WD_LT(value uint32) {
	volatile.StoreUint32(&o.WD_TH.Reg, volatile.LoadUint32(&o.WD_TH.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetWD_TH_WD_LT() uint32 {
	return volatile.LoadUint32(&o.WD_TH.Reg) & 0xfff
}
func (o *ADC_Type) SetWD_TH_WD_HT(value uint32) {
	volatile.StoreUint32(&o.WD_TH.Reg, volatile.LoadUint32(&o.WD_TH.Reg)&^(0xfff0000)|value<<16)
}
func (o *ADC_Type) GetWD_TH_WD_HT() uint32 {
	return (volatile.LoadUint32(&o.WD_TH.Reg) & 0xfff0000) >> 16
}

// ADC.WD_CONF: WD_CONF register
func (o *ADC_Type) SetWD_CONF_AWD_CHX(value uint32) {
	volatile.StoreUint32(&o.WD_CONF.Reg, volatile.LoadUint32(&o.WD_CONF.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetWD_CONF_AWD_CHX() uint32 {
	return volatile.LoadUint32(&o.WD_CONF.Reg) & 0xffff
}

// ADC.DS_DATAOUT: DS_DATAOUT register
func (o *ADC_Type) SetDS_DATAOUT_DS_DATA(value uint32) {
	volatile.StoreUint32(&o.DS_DATAOUT.Reg, volatile.LoadUint32(&o.DS_DATAOUT.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetDS_DATAOUT_DS_DATA() uint32 {
	return volatile.LoadUint32(&o.DS_DATAOUT.Reg) & 0xffff
}

// ADC.IRQ_STATUS: IRQ_STATUS register
func (o *ADC_Type) SetIRQ_STATUS_EOC_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_STATUS.Reg, volatile.LoadUint32(&o.IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIRQ_STATUS_EOC_IRQ() uint32 {
	return volatile.LoadUint32(&o.IRQ_STATUS.Reg) & 0x1
}
func (o *ADC_Type) SetIRQ_STATUS_EODS_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_STATUS.Reg, volatile.LoadUint32(&o.IRQ_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIRQ_STATUS_EODS_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_STATUS.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIRQ_STATUS_EOS_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_STATUS.Reg, volatile.LoadUint32(&o.IRQ_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIRQ_STATUS_EOS_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_STATUS.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIRQ_STATUS_AWD_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_STATUS.Reg, volatile.LoadUint32(&o.IRQ_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIRQ_STATUS_AWD_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_STATUS.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIRQ_STATUS_OVR_DS_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_STATUS.Reg, volatile.LoadUint32(&o.IRQ_STATUS.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetIRQ_STATUS_OVR_DS_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_STATUS.Reg) & 0x20) >> 5
}

// ADC.IRQ_ENABLE: IRQ_ENABLE register
func (o *ADC_Type) SetIRQ_ENABLE_EOC_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENABLE.Reg, volatile.LoadUint32(&o.IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIRQ_ENABLE_EOC_IRQ() uint32 {
	return volatile.LoadUint32(&o.IRQ_ENABLE.Reg) & 0x1
}
func (o *ADC_Type) SetIRQ_ENABLE_EODS_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENABLE.Reg, volatile.LoadUint32(&o.IRQ_ENABLE.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIRQ_ENABLE_EODS_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_ENABLE.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIRQ_ENABLE_EOS_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENABLE.Reg, volatile.LoadUint32(&o.IRQ_ENABLE.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIRQ_ENABLE_EOS_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_ENABLE.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIRQ_ENABLE_AWD_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENABLE.Reg, volatile.LoadUint32(&o.IRQ_ENABLE.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIRQ_ENABLE_AWD_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_ENABLE.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIRQ_ENABLE_OVR_DS_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENABLE.Reg, volatile.LoadUint32(&o.IRQ_ENABLE.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetIRQ_ENABLE_OVR_DS_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_ENABLE.Reg) & 0x20) >> 5
}

// CRC address block description
type CRC_Type struct {
	DR   volatile.Register32 // 0x0
	IDR  volatile.Register32 // 0x4
	CR   volatile.Register32 // 0x8
	_    [4]byte
	INIT volatile.Register32 // 0x10
	POL  volatile.Register32 // 0x14
}

// CRC.DR: CRC data register
func (o *CRC_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *CRC_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// CRC.IDR: CRC independent data register
func (o *CRC_Type) SetIDR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, value)
}
func (o *CRC_Type) GetIDR() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg)
}

// CRC.CR: CRC control register
func (o *CRC_Type) SetCR_RESET(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *CRC_Type) GetCR_RESET() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *CRC_Type) SetCR_POLYSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x18)|value<<3)
}
func (o *CRC_Type) GetCR_POLYSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x18) >> 3
}
func (o *CRC_Type) SetCR_REV_IN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x60)|value<<5)
}
func (o *CRC_Type) GetCR_REV_IN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x60) >> 5
}
func (o *CRC_Type) SetCR_REV_OUT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *CRC_Type) GetCR_REV_OUT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}

// CRC.INIT: CRC initial value
func (o *CRC_Type) SetINIT(value uint32) {
	volatile.StoreUint32(&o.INIT.Reg, value)
}
func (o *CRC_Type) GetINIT() uint32 {
	return volatile.LoadUint32(&o.INIT.Reg)
}

// CRC.POL: CRC polynomial
func (o *CRC_Type) SetPOL(value uint32) {
	volatile.StoreUint32(&o.POL.Reg, value)
}
func (o *CRC_Type) GetPOL() uint32 {
	return volatile.LoadUint32(&o.POL.Reg)
}

type DMA_Type struct {
	ISR  volatile.Register32 // 0x0
	IFCR volatile.Register32 // 0x4
	CH   [8]DMA_CH_Type      // 0x8
}

// DMA.ISR: DMA_ISR register
func (o *DMA_Type) SetISR_GIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_Type) GetISR_GIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *DMA_Type) SetISR_GIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *DMA_Type) GetISR_GIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *DMA_Type) SetISR_GIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *DMA_Type) GetISR_GIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *DMA_Type) SetISR_GIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_Type) GetISR_GIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *DMA_Type) SetISR_GIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA_Type) GetISR_GIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100000) >> 20
}
func (o *DMA_Type) SetISR_GIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *DMA_Type) GetISR_GIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *DMA_Type) SetISR_GIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000000)|value<<28)
}
func (o *DMA_Type) GetISR_GIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000000) >> 28
}
func (o *DMA_Type) SetISR_GIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<32)
}
func (o *DMA_Type) GetISR_GIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 32
}
func (o *DMA_Type) SetISR_TCIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_Type) GetISR_TCIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *DMA_Type) SetISR_TCIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *DMA_Type) GetISR_TCIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *DMA_Type) SetISR_TCIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *DMA_Type) GetISR_TCIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *DMA_Type) SetISR_TCIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *DMA_Type) GetISR_TCIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *DMA_Type) SetISR_TCIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA_Type) GetISR_TCIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *DMA_Type) SetISR_TCIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *DMA_Type) GetISR_TCIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *DMA_Type) SetISR_TCIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000000)|value<<29)
}
func (o *DMA_Type) GetISR_TCIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000000) >> 29
}
func (o *DMA_Type) SetISR_TCIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<33)
}
func (o *DMA_Type) GetISR_TCIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 33
}
func (o *DMA_Type) SetISR_HTIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_Type) GetISR_HTIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *DMA_Type) SetISR_HTIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *DMA_Type) GetISR_HTIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *DMA_Type) SetISR_HTIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_Type) GetISR_HTIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *DMA_Type) SetISR_HTIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *DMA_Type) GetISR_HTIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *DMA_Type) SetISR_HTIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *DMA_Type) GetISR_HTIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *DMA_Type) SetISR_HTIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *DMA_Type) GetISR_HTIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *DMA_Type) SetISR_HTIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000000)|value<<30)
}
func (o *DMA_Type) GetISR_HTIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000000) >> 30
}
func (o *DMA_Type) SetISR_HTIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<34)
}
func (o *DMA_Type) GetISR_HTIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 34
}
func (o *DMA_Type) SetISR_TEIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_Type) GetISR_TEIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *DMA_Type) SetISR_TEIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *DMA_Type) GetISR_TEIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *DMA_Type) SetISR_TEIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *DMA_Type) GetISR_TEIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *DMA_Type) SetISR_TEIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *DMA_Type) GetISR_TEIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *DMA_Type) SetISR_TEIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *DMA_Type) GetISR_TEIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *DMA_Type) SetISR_TEIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *DMA_Type) GetISR_TEIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *DMA_Type) SetISR_TEIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000000)|value<<31)
}
func (o *DMA_Type) GetISR_TEIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000000) >> 31
}
func (o *DMA_Type) SetISR_TEIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<35)
}
func (o *DMA_Type) GetISR_TEIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 35
}

// DMA.IFCR: DMA_IFCR register
func (o *DMA_Type) SetIFCR_CGIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_Type) GetIFCR_CGIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10) >> 4
}
func (o *DMA_Type) SetIFCR_CGIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x100)|value<<8)
}
func (o *DMA_Type) GetIFCR_CGIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x100) >> 8
}
func (o *DMA_Type) SetIFCR_CGIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x1000)|value<<12)
}
func (o *DMA_Type) GetIFCR_CGIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x1000) >> 12
}
func (o *DMA_Type) SetIFCR_CGIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_Type) GetIFCR_CGIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10000) >> 16
}
func (o *DMA_Type) SetIFCR_CGIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA_Type) GetIFCR_CGIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x100000) >> 20
}
func (o *DMA_Type) SetIFCR_CGIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x1000000)|value<<24)
}
func (o *DMA_Type) GetIFCR_CGIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x1000000) >> 24
}
func (o *DMA_Type) SetIFCR_CGIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10000000)|value<<28)
}
func (o *DMA_Type) GetIFCR_CGIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10000000) >> 28
}
func (o *DMA_Type) SetIFCR_CGIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<32)
}
func (o *DMA_Type) GetIFCR_CGIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 32
}
func (o *DMA_Type) SetIFCR_CTCIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_Type) GetIFCR_CTCIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20) >> 5
}
func (o *DMA_Type) SetIFCR_CTCIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x200)|value<<9)
}
func (o *DMA_Type) GetIFCR_CTCIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x200) >> 9
}
func (o *DMA_Type) SetIFCR_CTCIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x2000)|value<<13)
}
func (o *DMA_Type) GetIFCR_CTCIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x2000) >> 13
}
func (o *DMA_Type) SetIFCR_CTCIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20000)|value<<17)
}
func (o *DMA_Type) GetIFCR_CTCIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20000) >> 17
}
func (o *DMA_Type) SetIFCR_CTCIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA_Type) GetIFCR_CTCIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x200000) >> 21
}
func (o *DMA_Type) SetIFCR_CTCIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x2000000)|value<<25)
}
func (o *DMA_Type) GetIFCR_CTCIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x2000000) >> 25
}
func (o *DMA_Type) SetIFCR_CTCIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20000000)|value<<29)
}
func (o *DMA_Type) GetIFCR_CTCIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20000000) >> 29
}
func (o *DMA_Type) SetIFCR_CTCIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<33)
}
func (o *DMA_Type) GetIFCR_CTCIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 33
}
func (o *DMA_Type) SetIFCR_CHTIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_Type) GetIFCR_CHTIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40) >> 6
}
func (o *DMA_Type) SetIFCR_CHTIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x400)|value<<10)
}
func (o *DMA_Type) GetIFCR_CHTIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x400) >> 10
}
func (o *DMA_Type) SetIFCR_CHTIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_Type) GetIFCR_CHTIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x4000) >> 14
}
func (o *DMA_Type) SetIFCR_CHTIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40000)|value<<18)
}
func (o *DMA_Type) GetIFCR_CHTIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40000) >> 18
}
func (o *DMA_Type) SetIFCR_CHTIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x400000)|value<<22)
}
func (o *DMA_Type) GetIFCR_CHTIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x400000) >> 22
}
func (o *DMA_Type) SetIFCR_CHTIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x4000000)|value<<26)
}
func (o *DMA_Type) GetIFCR_CHTIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x4000000) >> 26
}
func (o *DMA_Type) SetIFCR_CHTIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40000000)|value<<30)
}
func (o *DMA_Type) GetIFCR_CHTIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40000000) >> 30
}
func (o *DMA_Type) SetIFCR_CHTIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<34)
}
func (o *DMA_Type) GetIFCR_CHTIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 34
}
func (o *DMA_Type) SetIFCR_CTEIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_Type) GetIFCR_CTEIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80) >> 7
}
func (o *DMA_Type) SetIFCR_CTEIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x800)|value<<11)
}
func (o *DMA_Type) GetIFCR_CTEIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x800) >> 11
}
func (o *DMA_Type) SetIFCR_CTEIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8000)|value<<15)
}
func (o *DMA_Type) GetIFCR_CTEIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8000) >> 15
}
func (o *DMA_Type) SetIFCR_CTEIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80000)|value<<19)
}
func (o *DMA_Type) GetIFCR_CTEIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80000) >> 19
}
func (o *DMA_Type) SetIFCR_CTEIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x800000)|value<<23)
}
func (o *DMA_Type) GetIFCR_CTEIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x800000) >> 23
}
func (o *DMA_Type) SetIFCR_CTEIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8000000)|value<<27)
}
func (o *DMA_Type) GetIFCR_CTEIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8000000) >> 27
}
func (o *DMA_Type) SetIFCR_CTEIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80000000)|value<<31)
}
func (o *DMA_Type) GetIFCR_CTEIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80000000) >> 31
}
func (o *DMA_Type) SetIFCR_CTEIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<35)
}
func (o *DMA_Type) GetIFCR_CTEIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 35
}

// Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers
type DMA_CH_Type struct {
	CR   volatile.Register32 // 0x8
	NDTR volatile.Register32 // 0xC
	PAR  volatile.Register32 // 0x10
	MAR  volatile.Register32 // 0x14
	_    [4]byte
}

// DMA_CH.CR: DMA_CCRx register
func (o *DMA_CH_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DMA_CH_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *DMA_CH_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DMA_CH_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DMA_CH_Type) SetCR_HTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DMA_CH_Type) GetCR_HTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *DMA_CH_Type) SetCR_TEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *DMA_CH_Type) GetCR_TEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *DMA_CH_Type) SetCR_DIR(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_CH_Type) GetCR_DIR() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *DMA_CH_Type) SetCR_CIRC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_CH_Type) GetCR_CIRC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *DMA_CH_Type) SetCR_PINC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_CH_Type) GetCR_PINC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *DMA_CH_Type) SetCR_MINC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_CH_Type) GetCR_MINC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *DMA_CH_Type) SetCR_PSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x300)|value<<8)
}
func (o *DMA_CH_Type) GetCR_PSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x300) >> 8
}
func (o *DMA_CH_Type) SetCR_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00)|value<<10)
}
func (o *DMA_CH_Type) GetCR_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00) >> 10
}
func (o *DMA_CH_Type) SetCR_PL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3000)|value<<12)
}
func (o *DMA_CH_Type) GetCR_PL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3000) >> 12
}
func (o *DMA_CH_Type) SetCR_MEM2MEM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_CH_Type) GetCR_MEM2MEM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}

// DMA_CH.NDTR: DMA_CNDTRx register
func (o *DMA_CH_Type) SetNDTR_NDT(value uint32) {
	volatile.StoreUint32(&o.NDTR.Reg, volatile.LoadUint32(&o.NDTR.Reg)&^(0xffff)|value)
}
func (o *DMA_CH_Type) GetNDTR_NDT() uint32 {
	return volatile.LoadUint32(&o.NDTR.Reg) & 0xffff
}

// DMA_CH.PAR: DMA_CPARx register
func (o *DMA_CH_Type) SetPAR(value uint32) {
	volatile.StoreUint32(&o.PAR.Reg, value)
}
func (o *DMA_CH_Type) GetPAR() uint32 {
	return volatile.LoadUint32(&o.PAR.Reg)
}

// DMA_CH.MAR: DMA_CMARx register
func (o *DMA_CH_Type) SetMAR(value uint32) {
	volatile.StoreUint32(&o.MAR.Reg, value)
}
func (o *DMA_CH_Type) GetMAR() uint32 {
	return volatile.LoadUint32(&o.MAR.Reg)
}

type DMAMUX_Type struct {
	C0CR volatile.Register32 // 0x0
	C1CR volatile.Register32 // 0x4
	C2CR volatile.Register32 // 0x8
	C3CR volatile.Register32 // 0xC
	C4CR volatile.Register32 // 0x10
	C5CR volatile.Register32 // 0x14
	C6CR volatile.Register32 // 0x18
	C7CR volatile.Register32 // 0x1C
}

// DMAMUX.C0CR: CxCR register
func (o *DMAMUX_Type) SetC0CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C0CR.Reg, volatile.LoadUint32(&o.C0CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC0CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C0CR.Reg) & 0x1f
}

// DMAMUX.C1CR: CxCR register
func (o *DMAMUX_Type) SetC1CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C1CR.Reg, volatile.LoadUint32(&o.C1CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC1CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C1CR.Reg) & 0x1f
}

// DMAMUX.C2CR: CxCR register
func (o *DMAMUX_Type) SetC2CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C2CR.Reg, volatile.LoadUint32(&o.C2CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC2CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C2CR.Reg) & 0x1f
}

// DMAMUX.C3CR: CxCR register
func (o *DMAMUX_Type) SetC3CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C3CR.Reg, volatile.LoadUint32(&o.C3CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC3CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C3CR.Reg) & 0x1f
}

// DMAMUX.C4CR: CxCR register
func (o *DMAMUX_Type) SetC4CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C4CR.Reg, volatile.LoadUint32(&o.C4CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC4CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C4CR.Reg) & 0x1f
}

// DMAMUX.C5CR: CxCR register
func (o *DMAMUX_Type) SetC5CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C5CR.Reg, volatile.LoadUint32(&o.C5CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC5CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C5CR.Reg) & 0x1f
}

// DMAMUX.C6CR: CxCR register
func (o *DMAMUX_Type) SetC6CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C6CR.Reg, volatile.LoadUint32(&o.C6CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC6CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C6CR.Reg) & 0x1f
}

// DMAMUX.C7CR: CxCR register
func (o *DMAMUX_Type) SetC7CR_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.C7CR.Reg, volatile.LoadUint32(&o.C7CR.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetC7CR_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.C7CR.Reg) & 0x1f
}

type GPIO_Type struct {
	MODER   volatile.Register32 // 0x0
	OTYPER  volatile.Register32 // 0x4
	OSPEEDR volatile.Register32 // 0x8
	PUPDR   volatile.Register32 // 0xC
	IDR     volatile.Register32 // 0x10
	ODR     volatile.Register32 // 0x14
	BSRR    volatile.Register32 // 0x18
	LCKR    volatile.Register32 // 0x1C
	AFRL    volatile.Register32 // 0x20
	AFRH    volatile.Register32 // 0x24
	BRR     volatile.Register32 // 0x28
}

// GPIO.MODER: MODER register
func (o *GPIO_Type) SetMODER_MODE0(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetMODER_MODE0() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetMODER_MODE1(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetMODER_MODE1() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetMODER_MODE2(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetMODER_MODE2() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetMODER_MODE3(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetMODER_MODE3() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetMODER_MODE4(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetMODER_MODE4() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetMODER_MODE5(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetMODER_MODE5() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetMODER_MODE6(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetMODER_MODE6() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetMODER_MODE7(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetMODER_MODE7() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetMODER_MODE8(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetMODER_MODE8() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetMODER_MODE9(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetMODER_MODE9() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetMODER_MODE10(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetMODER_MODE10() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetMODER_MODE11(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetMODER_MODE11() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000000) >> 24
}

// GPIO.OTYPER: OTYPER register
func (o *GPIO_Type) SetOTYPER_OT0(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetOTYPER_OT0() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetOTYPER_OT1(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetOTYPER_OT1() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetOTYPER_OT2(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetOTYPER_OT2() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetOTYPER_OT3(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetOTYPER_OT3() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetOTYPER_OT4(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetOTYPER_OT4() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetOTYPER_OT5(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetOTYPER_OT5() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetOTYPER_OT6(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetOTYPER_OT6() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetOTYPER_OT7(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetOTYPER_OT7() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetOTYPER_OT8(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetOTYPER_OT8() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetOTYPER_OT9(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetOTYPER_OT9() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetOTYPER_OT10(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetOTYPER_OT10() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetOTYPER_OT11(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetOTYPER_OT11() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x1000) >> 12
}

// GPIO.OSPEEDR: OSPEEDR register
func (o *GPIO_Type) SetOSPEEDR_OSPEED0(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED0() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED1(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED1() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED2(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED2() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED3(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED3() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED4(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED4() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED5(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED5() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED6(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED6() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED7(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED7() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED8(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED8() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED9(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED9() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED10(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED10() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED11(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED11() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000000) >> 24
}

// GPIO.PUPDR: PUPDR register
func (o *GPIO_Type) SetPUPDR_PUPD0(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetPUPDR_PUPD0() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetPUPDR_PUPD1(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetPUPDR_PUPD1() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetPUPDR_PUPD2(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetPUPDR_PUPD2() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetPUPDR_PUPD3(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetPUPDR_PUPD3() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetPUPDR_PUPD4(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetPUPDR_PUPD4() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetPUPDR_PUPD5(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetPUPDR_PUPD5() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetPUPDR_PUPD6(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetPUPDR_PUPD6() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetPUPDR_PUPD7(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetPUPDR_PUPD7() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetPUPDR_PUPD8(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetPUPDR_PUPD8() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetPUPDR_PUPD9(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetPUPDR_PUPD9() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetPUPDR_PUPD10(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetPUPDR_PUPD10() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetPUPDR_PUPD11(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetPUPDR_PUPD11() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000000) >> 24
}

// GPIO.IDR: IDR register
func (o *GPIO_Type) SetIDR_ID0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetIDR_ID0() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetIDR_ID1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetIDR_ID1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetIDR_ID2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetIDR_ID2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetIDR_ID3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetIDR_ID3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetIDR_ID4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetIDR_ID4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetIDR_ID5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetIDR_ID5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetIDR_ID6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetIDR_ID6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetIDR_ID7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetIDR_ID7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetIDR_ID8(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetIDR_ID8() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetIDR_ID9(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetIDR_ID9() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetIDR_ID10(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetIDR_ID10() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetIDR_ID11(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetIDR_ID11() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}

// GPIO.ODR: ODR register
func (o *GPIO_Type) SetODR_OD0(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetODR_OD0() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetODR_OD1(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetODR_OD1() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetODR_OD2(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetODR_OD2() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetODR_OD3(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetODR_OD3() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetODR_OD4(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetODR_OD4() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetODR_OD5(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetODR_OD5() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetODR_OD6(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetODR_OD6() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetODR_OD7(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetODR_OD7() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetODR_OD8(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetODR_OD8() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetODR_OD9(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetODR_OD9() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetODR_OD10(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetODR_OD10() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetODR_OD11(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetODR_OD11() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x1000) >> 12
}

// GPIO.BSRR: BSRR register
func (o *GPIO_Type) SetBSRR_BS0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBSRR_BS0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBSRR_BS1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBSRR_BS1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBSRR_BS2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBSRR_BS2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBSRR_BS3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBSRR_BS3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBSRR_BS4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBSRR_BS4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBSRR_BS5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBSRR_BS5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBSRR_BS6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBSRR_BS6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBSRR_BS7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBSRR_BS7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBSRR_BS8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBSRR_BS8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBSRR_BS9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBSRR_BS9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBSRR_BS10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBSRR_BS10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBSRR_BS11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBSRR_BS11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetBSRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000)|value<<17)
}
func (o *GPIO_Type) GetBSRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000) >> 17
}
func (o *GPIO_Type) SetBSRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000)|value<<18)
}
func (o *GPIO_Type) GetBSRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000) >> 18
}
func (o *GPIO_Type) SetBSRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000)|value<<19)
}
func (o *GPIO_Type) GetBSRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000) >> 19
}
func (o *GPIO_Type) SetBSRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100000)|value<<20)
}
func (o *GPIO_Type) GetBSRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100000) >> 20
}
func (o *GPIO_Type) SetBSRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200000)|value<<21)
}
func (o *GPIO_Type) GetBSRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200000) >> 21
}
func (o *GPIO_Type) SetBSRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400000)|value<<22)
}
func (o *GPIO_Type) GetBSRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400000) >> 22
}
func (o *GPIO_Type) SetBSRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800000)|value<<23)
}
func (o *GPIO_Type) GetBSRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800000) >> 23
}
func (o *GPIO_Type) SetBSRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIO_Type) GetBSRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000000) >> 24
}
func (o *GPIO_Type) SetBSRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000000)|value<<25)
}
func (o *GPIO_Type) GetBSRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000000) >> 25
}
func (o *GPIO_Type) SetBSRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000000)|value<<26)
}
func (o *GPIO_Type) GetBSRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000000) >> 26
}
func (o *GPIO_Type) SetBSRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000000)|value<<27)
}
func (o *GPIO_Type) GetBSRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000000) >> 27
}
func (o *GPIO_Type) SetBSRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000000)|value<<28)
}
func (o *GPIO_Type) GetBSRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000000) >> 28
}

// GPIO.LCKR: LCKR register
func (o *GPIO_Type) SetLCKR_LCK0(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetLCKR_LCK0() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetLCKR_LCK1(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetLCKR_LCK1() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetLCKR_LCK2(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetLCKR_LCK2() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetLCKR_LCK3(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetLCKR_LCK3() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetLCKR_LCK4(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetLCKR_LCK4() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetLCKR_LCK5(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetLCKR_LCK5() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetLCKR_LCK6(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetLCKR_LCK6() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetLCKR_LCK7(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetLCKR_LCK7() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetLCKR_LCK8(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetLCKR_LCK8() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetLCKR_LCK9(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetLCKR_LCK9() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetLCKR_LCK10(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetLCKR_LCK10() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetLCKR_LCK11(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetLCKR_LCK11() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetLCKR_LCKK(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetLCKR_LCKK() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10000) >> 16
}

// GPIO.AFRL: AFRL register
func (o *GPIO_Type) SetAFRL_AFSEL0(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRL_AFSEL0() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRL_AFSEL1(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRL_AFSEL1() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRL_AFSEL2(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRL_AFSEL2() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRL_AFSEL3(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRL_AFSEL3() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0000) >> 16
}

// GPIO.AFRH: AFRH register
func (o *GPIO_Type) SetAFRH_AFSEL8(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRH_AFSEL8() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRH_AFSEL9(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRH_AFSEL9() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRH_AFSEL10(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRH_AFSEL10() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRH_AFSEL11(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRH_AFSEL11() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0000) >> 16
}

// GPIO.BRR: BRR register
func (o *GPIO_Type) SetBRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x1000) >> 12
}

type IWDG_Type struct {
	KR   volatile.Register32 // 0x0
	PR   volatile.Register32 // 0x4
	RLR  volatile.Register32 // 0x8
	SR   volatile.Register32 // 0xC
	WINR volatile.Register32 // 0x10
}

// IWDG.KR: IWDG_KR register
func (o *IWDG_Type) SetKR_KEY(value uint32) {
	volatile.StoreUint32(&o.KR.Reg, volatile.LoadUint32(&o.KR.Reg)&^(0xffff)|value)
}
func (o *IWDG_Type) GetKR_KEY() uint32 {
	return volatile.LoadUint32(&o.KR.Reg) & 0xffff
}

// IWDG.PR: IWDG_PR register
func (o *IWDG_Type) SetPR(value uint32) {
	volatile.StoreUint32(&o.PR.Reg, volatile.LoadUint32(&o.PR.Reg)&^(0x7)|value)
}
func (o *IWDG_Type) GetPR() uint32 {
	return volatile.LoadUint32(&o.PR.Reg) & 0x7
}

// IWDG.RLR: IWDG_RLR register
func (o *IWDG_Type) SetRLR_RL(value uint32) {
	volatile.StoreUint32(&o.RLR.Reg, volatile.LoadUint32(&o.RLR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetRLR_RL() uint32 {
	return volatile.LoadUint32(&o.RLR.Reg) & 0xfff
}

// IWDG.SR: IWDG_SR register
func (o *IWDG_Type) SetSR_PVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *IWDG_Type) GetSR_PVU() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *IWDG_Type) SetSR_RVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *IWDG_Type) GetSR_RVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *IWDG_Type) SetSR_WVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *IWDG_Type) GetSR_WVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}

// IWDG.WINR: IWDG_WINR register
func (o *IWDG_Type) SetWINR_WIN(value uint32) {
	volatile.StoreUint32(&o.WINR.Reg, volatile.LoadUint32(&o.WINR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetWINR_WIN() uint32 {
	return volatile.LoadUint32(&o.WINR.Reg) & 0xfff
}

type LPUART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	_     [8]byte
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// LPUART.CR1: CR1 register
func (o *LPUART_Type) SetCR1_UE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetCR1_UE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *LPUART_Type) SetCR1_UESM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetCR1_UESM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *LPUART_Type) SetCR1_RE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetCR1_RE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetCR1_TE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetCR1_TE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetCR1_IDLEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetCR1_IDLEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetCR1_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *LPUART_Type) GetCR1_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *LPUART_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetCR1_TXEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *LPUART_Type) GetCR1_TXEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *LPUART_Type) SetCR1_PEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *LPUART_Type) GetCR1_PEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *LPUART_Type) SetCR1_PS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetCR1_PS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetCR1_PCE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *LPUART_Type) GetCR1_PCE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *LPUART_Type) SetCR1_WAKE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *LPUART_Type) GetCR1_WAKE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *LPUART_Type) SetCR1_M0(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *LPUART_Type) GetCR1_M0() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *LPUART_Type) SetCR1_MME(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *LPUART_Type) GetCR1_MME() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *LPUART_Type) SetCR1_CMIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *LPUART_Type) GetCR1_CMIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *LPUART_Type) SetCR1_DEDT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *LPUART_Type) GetCR1_DEDT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1f0000) >> 16
}
func (o *LPUART_Type) SetCR1_DEAT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x3e00000)|value<<21)
}
func (o *LPUART_Type) GetCR1_DEAT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x3e00000) >> 21
}
func (o *LPUART_Type) SetCR1_M1(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000000)|value<<28)
}
func (o *LPUART_Type) GetCR1_M1() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000000) >> 28
}
func (o *LPUART_Type) SetCR1_FIFOEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000000)|value<<29)
}
func (o *LPUART_Type) GetCR1_FIFOEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000000) >> 29
}
func (o *LPUART_Type) SetCR1_TXFEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *LPUART_Type) GetCR1_TXFEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *LPUART_Type) SetCR1_RXFFIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000000)|value<<31)
}
func (o *LPUART_Type) GetCR1_RXFFIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000000) >> 31
}

// LPUART.CR2: CR2 register
func (o *LPUART_Type) SetCR2_ADDM7(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetCR2_ADDM7() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3000)|value<<12)
}
func (o *LPUART_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x3000) >> 12
}
func (o *LPUART_Type) SetCR2_SWAP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *LPUART_Type) GetCR2_SWAP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *LPUART_Type) SetCR2_RXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *LPUART_Type) GetCR2_RXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *LPUART_Type) SetCR2_TXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *LPUART_Type) GetCR2_TXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *LPUART_Type) SetCR2_DATAINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *LPUART_Type) GetCR2_DATAINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *LPUART_Type) SetCR2_MSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000)|value<<19)
}
func (o *LPUART_Type) GetCR2_MSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000) >> 19
}
func (o *LPUART_Type) SetCR2_ADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff000000)|value<<24)
}
func (o *LPUART_Type) GetCR2_ADD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff000000) >> 24
}

// LPUART.CR3: CR3 register
func (o *LPUART_Type) SetCR3_EIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetCR3_EIE() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *LPUART_Type) SetCR3_HDSEL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetCR3_HDSEL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetCR3_DMAR(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetCR3_DMAR() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetCR3_DMAT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *LPUART_Type) GetCR3_DMAT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *LPUART_Type) SetCR3_RTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *LPUART_Type) GetCR3_RTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *LPUART_Type) SetCR3_CTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetCR3_CTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetCR3_CTSIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *LPUART_Type) GetCR3_CTSIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *LPUART_Type) SetCR3_OVRDIS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *LPUART_Type) GetCR3_OVRDIS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}
func (o *LPUART_Type) SetCR3_DDRE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *LPUART_Type) GetCR3_DDRE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *LPUART_Type) SetCR3_DEM(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *LPUART_Type) GetCR3_DEM() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *LPUART_Type) SetCR3_DEP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *LPUART_Type) GetCR3_DEP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}
func (o *LPUART_Type) SetCR3_WUS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x300000)|value<<20)
}
func (o *LPUART_Type) GetCR3_WUS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x300000) >> 20
}
func (o *LPUART_Type) SetCR3_WUFIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400000)|value<<22)
}
func (o *LPUART_Type) GetCR3_WUFIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400000) >> 22
}
func (o *LPUART_Type) SetCR3_TXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800000)|value<<23)
}
func (o *LPUART_Type) GetCR3_TXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800000) >> 23
}
func (o *LPUART_Type) SetCR3_RXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe000000)|value<<25)
}
func (o *LPUART_Type) GetCR3_RXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe000000) >> 25
}
func (o *LPUART_Type) SetCR3_RXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10000000)|value<<28)
}
func (o *LPUART_Type) GetCR3_RXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10000000) >> 28
}
func (o *LPUART_Type) SetCR3_TXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000000)|value<<29)
}
func (o *LPUART_Type) GetCR3_TXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000000) >> 29
}

// LPUART.BRR: BRR register
func (o *LPUART_Type) SetBRR(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0xfffff)|value)
}
func (o *LPUART_Type) GetBRR() uint32 {
	return volatile.LoadUint32(&o.BRR.Reg) & 0xfffff
}

// LPUART.RQR: RQR register
func (o *LPUART_Type) SetRQR_SBKRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetRQR_SBKRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x2) >> 1
}
func (o *LPUART_Type) SetRQR_MMRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetRQR_MMRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetRQR_RXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetRQR_RXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetRQR_TXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetRQR_TXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x10) >> 4
}

// LPUART.ISR: ISR register
func (o *LPUART_Type) SetISR_PE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetISR_PE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *LPUART_Type) SetISR_FE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetISR_FE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *LPUART_Type) SetISR_NF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetISR_NF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetISR_ORE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetISR_ORE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetISR_IDLE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetISR_IDLE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetISR_RXNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *LPUART_Type) GetISR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *LPUART_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetISR_TXE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *LPUART_Type) GetISR_TXE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *LPUART_Type) SetISR_CTSIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetISR_CTSIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetISR_CTS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *LPUART_Type) GetISR_CTS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *LPUART_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *LPUART_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *LPUART_Type) SetISR_CMF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *LPUART_Type) GetISR_CMF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *LPUART_Type) SetISR_SBKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *LPUART_Type) GetISR_SBKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *LPUART_Type) SetISR_RWU(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *LPUART_Type) GetISR_RWU() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *LPUART_Type) SetISR_WUF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100000)|value<<20)
}
func (o *LPUART_Type) GetISR_WUF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100000) >> 20
}
func (o *LPUART_Type) SetISR_TEACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *LPUART_Type) GetISR_TEACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *LPUART_Type) SetISR_REACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *LPUART_Type) GetISR_REACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *LPUART_Type) SetISR_TXFE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *LPUART_Type) GetISR_TXFE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *LPUART_Type) SetISR_RXFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *LPUART_Type) GetISR_RXFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *LPUART_Type) SetISR_RXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *LPUART_Type) GetISR_RXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *LPUART_Type) SetISR_TXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *LPUART_Type) GetISR_TXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}

// LPUART.ICR: ICR register
func (o *LPUART_Type) SetICR_PECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetICR_PECF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *LPUART_Type) SetICR_FECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetICR_FECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *LPUART_Type) SetICR_NECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetICR_NECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetICR_ORECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetICR_ORECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetICR_IDLECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetICR_IDLECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetICR_TCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetICR_TCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetICR_CTSCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetICR_CTSCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetICR_CMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20000)|value<<17)
}
func (o *LPUART_Type) GetICR_CMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20000) >> 17
}
func (o *LPUART_Type) SetICR_WUCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100000)|value<<20)
}
func (o *LPUART_Type) GetICR_WUCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100000) >> 20
}

// LPUART.RDR: RDR register
func (o *LPUART_Type) SetRDR(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0x1ff)|value)
}
func (o *LPUART_Type) GetRDR() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg) & 0x1ff
}

// LPUART.TDR: TDR register
func (o *LPUART_Type) SetTDR(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0x1ff)|value)
}
func (o *LPUART_Type) GetTDR() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg) & 0x1ff
}

// LPUART.PRESC: PRESC register
func (o *LPUART_Type) SetPRESC_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.PRESC.Reg, volatile.LoadUint32(&o.PRESC.Reg)&^(0xf)|value)
}
func (o *LPUART_Type) GetPRESC_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.PRESC.Reg) & 0xf
}

// 4kb addressable space
type FLASH_CTRL_Type struct {
	COMMAND   volatile.Register32 // 0x0
	CONFIG    volatile.Register32 // 0x4
	IRQSTAT   volatile.Register32 // 0x8
	IRQMASK   volatile.Register32 // 0xC
	IRQRAW    volatile.Register32 // 0x10
	SIZE      volatile.Register32 // 0x14
	ADDRESS   volatile.Register32 // 0x18
	_         [8]byte
	LFSRVAL   volatile.Register32 // 0x24
	_         [12]byte
	PAGEPROT0 volatile.Register32 // 0x34
	PAGEPROT1 volatile.Register32 // 0x38
	_         [4]byte
	DATA0     volatile.Register32 // 0x40
	DATA1     volatile.Register32 // 0x44
	DATA2     volatile.Register32 // 0x48
	DATA3     volatile.Register32 // 0x4C
}

// FLASH_CTRL.COMMAND: COMMAND register
func (o *FLASH_CTRL_Type) SetCOMMAND(value uint32) {
	volatile.StoreUint32(&o.COMMAND.Reg, volatile.LoadUint32(&o.COMMAND.Reg)&^(0xff)|value)
}
func (o *FLASH_CTRL_Type) GetCOMMAND() uint32 {
	return volatile.LoadUint32(&o.COMMAND.Reg) & 0xff
}

// FLASH_CTRL.CONFIG: CONFIG register
func (o *FLASH_CTRL_Type) SetCONFIG_REMAP(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x2)|value<<1)
}
func (o *FLASH_CTRL_Type) GetCONFIG_REMAP() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x2) >> 1
}
func (o *FLASH_CTRL_Type) SetCONFIG_DIS_GROUP_WRITE(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x4)|value<<2)
}
func (o *FLASH_CTRL_Type) GetCONFIG_DIS_GROUP_WRITE() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x4) >> 2
}
func (o *FLASH_CTRL_Type) SetCONFIG_WAIT_STATE(value uint32) {
	volatile.StoreUint32(&o.CONFIG.Reg, volatile.LoadUint32(&o.CONFIG.Reg)&^(0x30)|value<<4)
}
func (o *FLASH_CTRL_Type) GetCONFIG_WAIT_STATE() uint32 {
	return (volatile.LoadUint32(&o.CONFIG.Reg) & 0x30) >> 4
}

// FLASH_CTRL.IRQSTAT: IRQSTAT register
func (o *FLASH_CTRL_Type) SetIRQSTAT_CMDDONE_MIS(value uint32) {
	volatile.StoreUint32(&o.IRQSTAT.Reg, volatile.LoadUint32(&o.IRQSTAT.Reg)&^(0x1)|value)
}
func (o *FLASH_CTRL_Type) GetIRQSTAT_CMDDONE_MIS() uint32 {
	return volatile.LoadUint32(&o.IRQSTAT.Reg) & 0x1
}
func (o *FLASH_CTRL_Type) SetIRQSTAT_CMDSTART_MIS(value uint32) {
	volatile.StoreUint32(&o.IRQSTAT.Reg, volatile.LoadUint32(&o.IRQSTAT.Reg)&^(0x2)|value<<1)
}
func (o *FLASH_CTRL_Type) GetIRQSTAT_CMDSTART_MIS() uint32 {
	return (volatile.LoadUint32(&o.IRQSTAT.Reg) & 0x2) >> 1
}
func (o *FLASH_CTRL_Type) SetIRQSTAT_CMDBUSYERR_MIS(value uint32) {
	volatile.StoreUint32(&o.IRQSTAT.Reg, volatile.LoadUint32(&o.IRQSTAT.Reg)&^(0x4)|value<<2)
}
func (o *FLASH_CTRL_Type) GetIRQSTAT_CMDBUSYERR_MIS() uint32 {
	return (volatile.LoadUint32(&o.IRQSTAT.Reg) & 0x4) >> 2
}
func (o *FLASH_CTRL_Type) SetIRQSTAT_ILLCMD_MIS(value uint32) {
	volatile.StoreUint32(&o.IRQSTAT.Reg, volatile.LoadUint32(&o.IRQSTAT.Reg)&^(0x8)|value<<3)
}
func (o *FLASH_CTRL_Type) GetIRQSTAT_ILLCMD_MIS() uint32 {
	return (volatile.LoadUint32(&o.IRQSTAT.Reg) & 0x8) >> 3
}
func (o *FLASH_CTRL_Type) SetIRQSTAT_READOK_MIS(value uint32) {
	volatile.StoreUint32(&o.IRQSTAT.Reg, volatile.LoadUint32(&o.IRQSTAT.Reg)&^(0x10)|value<<4)
}
func (o *FLASH_CTRL_Type) GetIRQSTAT_READOK_MIS() uint32 {
	return (volatile.LoadUint32(&o.IRQSTAT.Reg) & 0x10) >> 4
}
func (o *FLASH_CTRL_Type) SetIRQSTAT_FNREADY_MIS(value uint32) {
	volatile.StoreUint32(&o.IRQSTAT.Reg, volatile.LoadUint32(&o.IRQSTAT.Reg)&^(0x20)|value<<5)
}
func (o *FLASH_CTRL_Type) GetIRQSTAT_FNREADY_MIS() uint32 {
	return (volatile.LoadUint32(&o.IRQSTAT.Reg) & 0x20) >> 5
}

// FLASH_CTRL.IRQMASK: IRQMASK register
func (o *FLASH_CTRL_Type) SetIRQMASK_CMDDONEM(value uint32) {
	volatile.StoreUint32(&o.IRQMASK.Reg, volatile.LoadUint32(&o.IRQMASK.Reg)&^(0x1)|value)
}
func (o *FLASH_CTRL_Type) GetIRQMASK_CMDDONEM() uint32 {
	return volatile.LoadUint32(&o.IRQMASK.Reg) & 0x1
}
func (o *FLASH_CTRL_Type) SetIRQMASK_CMDSTARTM(value uint32) {
	volatile.StoreUint32(&o.IRQMASK.Reg, volatile.LoadUint32(&o.IRQMASK.Reg)&^(0x2)|value<<1)
}
func (o *FLASH_CTRL_Type) GetIRQMASK_CMDSTARTM() uint32 {
	return (volatile.LoadUint32(&o.IRQMASK.Reg) & 0x2) >> 1
}
func (o *FLASH_CTRL_Type) SetIRQMASK_CMDBUSYERRM(value uint32) {
	volatile.StoreUint32(&o.IRQMASK.Reg, volatile.LoadUint32(&o.IRQMASK.Reg)&^(0x4)|value<<2)
}
func (o *FLASH_CTRL_Type) GetIRQMASK_CMDBUSYERRM() uint32 {
	return (volatile.LoadUint32(&o.IRQMASK.Reg) & 0x4) >> 2
}
func (o *FLASH_CTRL_Type) SetIRQMASK_ILLCMDM(value uint32) {
	volatile.StoreUint32(&o.IRQMASK.Reg, volatile.LoadUint32(&o.IRQMASK.Reg)&^(0x8)|value<<3)
}
func (o *FLASH_CTRL_Type) GetIRQMASK_ILLCMDM() uint32 {
	return (volatile.LoadUint32(&o.IRQMASK.Reg) & 0x8) >> 3
}
func (o *FLASH_CTRL_Type) SetIRQMASK_READOKM(value uint32) {
	volatile.StoreUint32(&o.IRQMASK.Reg, volatile.LoadUint32(&o.IRQMASK.Reg)&^(0x10)|value<<4)
}
func (o *FLASH_CTRL_Type) GetIRQMASK_READOKM() uint32 {
	return (volatile.LoadUint32(&o.IRQMASK.Reg) & 0x10) >> 4
}
func (o *FLASH_CTRL_Type) SetIRQMASK_FNREADYM(value uint32) {
	volatile.StoreUint32(&o.IRQMASK.Reg, volatile.LoadUint32(&o.IRQMASK.Reg)&^(0x20)|value<<5)
}
func (o *FLASH_CTRL_Type) GetIRQMASK_FNREADYM() uint32 {
	return (volatile.LoadUint32(&o.IRQMASK.Reg) & 0x20) >> 5
}

// FLASH_CTRL.IRQRAW: IRQRAW register
func (o *FLASH_CTRL_Type) SetIRQRAW_CMDDONE_RIS(value uint32) {
	volatile.StoreUint32(&o.IRQRAW.Reg, volatile.LoadUint32(&o.IRQRAW.Reg)&^(0x1)|value)
}
func (o *FLASH_CTRL_Type) GetIRQRAW_CMDDONE_RIS() uint32 {
	return volatile.LoadUint32(&o.IRQRAW.Reg) & 0x1
}
func (o *FLASH_CTRL_Type) SetIRQRAW_CMDSTART_RIS(value uint32) {
	volatile.StoreUint32(&o.IRQRAW.Reg, volatile.LoadUint32(&o.IRQRAW.Reg)&^(0x2)|value<<1)
}
func (o *FLASH_CTRL_Type) GetIRQRAW_CMDSTART_RIS() uint32 {
	return (volatile.LoadUint32(&o.IRQRAW.Reg) & 0x2) >> 1
}
func (o *FLASH_CTRL_Type) SetIRQRAW_CMDBUSYERR_RIS(value uint32) {
	volatile.StoreUint32(&o.IRQRAW.Reg, volatile.LoadUint32(&o.IRQRAW.Reg)&^(0x4)|value<<2)
}
func (o *FLASH_CTRL_Type) GetIRQRAW_CMDBUSYERR_RIS() uint32 {
	return (volatile.LoadUint32(&o.IRQRAW.Reg) & 0x4) >> 2
}
func (o *FLASH_CTRL_Type) SetIRQRAW_ILLCMD_RIS(value uint32) {
	volatile.StoreUint32(&o.IRQRAW.Reg, volatile.LoadUint32(&o.IRQRAW.Reg)&^(0x8)|value<<3)
}
func (o *FLASH_CTRL_Type) GetIRQRAW_ILLCMD_RIS() uint32 {
	return (volatile.LoadUint32(&o.IRQRAW.Reg) & 0x8) >> 3
}
func (o *FLASH_CTRL_Type) SetIRQRAW_READOK_RIS(value uint32) {
	volatile.StoreUint32(&o.IRQRAW.Reg, volatile.LoadUint32(&o.IRQRAW.Reg)&^(0x10)|value<<4)
}
func (o *FLASH_CTRL_Type) GetIRQRAW_READOK_RIS() uint32 {
	return (volatile.LoadUint32(&o.IRQRAW.Reg) & 0x10) >> 4
}
func (o *FLASH_CTRL_Type) SetIRQRAW_CMDSLEEPERR_RIS(value uint32) {
	volatile.StoreUint32(&o.IRQRAW.Reg, volatile.LoadUint32(&o.IRQRAW.Reg)&^(0x20)|value<<5)
}
func (o *FLASH_CTRL_Type) GetIRQRAW_CMDSLEEPERR_RIS() uint32 {
	return (volatile.LoadUint32(&o.IRQRAW.Reg) & 0x20) >> 5
}

// FLASH_CTRL.SIZE: SIZE register
func (o *FLASH_CTRL_Type) SetSIZE_FLASH_SIZE(value uint32) {
	volatile.StoreUint32(&o.SIZE.Reg, volatile.LoadUint32(&o.SIZE.Reg)&^(0x1ffff)|value)
}
func (o *FLASH_CTRL_Type) GetSIZE_FLASH_SIZE() uint32 {
	return volatile.LoadUint32(&o.SIZE.Reg) & 0x1ffff
}
func (o *FLASH_CTRL_Type) SetSIZE_RAM_SIZE(value uint32) {
	volatile.StoreUint32(&o.SIZE.Reg, volatile.LoadUint32(&o.SIZE.Reg)&^(0x20000)|value<<17)
}
func (o *FLASH_CTRL_Type) GetSIZE_RAM_SIZE() uint32 {
	return (volatile.LoadUint32(&o.SIZE.Reg) & 0x20000) >> 17
}
func (o *FLASH_CTRL_Type) SetSIZE_FLASH_SECURE(value uint32) {
	volatile.StoreUint32(&o.SIZE.Reg, volatile.LoadUint32(&o.SIZE.Reg)&^(0x80000)|value<<19)
}
func (o *FLASH_CTRL_Type) GetSIZE_FLASH_SECURE() uint32 {
	return (volatile.LoadUint32(&o.SIZE.Reg) & 0x80000) >> 19
}
func (o *FLASH_CTRL_Type) SetSIZE_JTAG_DISABLE(value uint32) {
	volatile.StoreUint32(&o.SIZE.Reg, volatile.LoadUint32(&o.SIZE.Reg)&^(0x100000)|value<<20)
}
func (o *FLASH_CTRL_Type) GetSIZE_JTAG_DISABLE() uint32 {
	return (volatile.LoadUint32(&o.SIZE.Reg) & 0x100000) >> 20
}
func (o *FLASH_CTRL_Type) SetSIZE_PACKAGE_SIZE(value uint32) {
	volatile.StoreUint32(&o.SIZE.Reg, volatile.LoadUint32(&o.SIZE.Reg)&^(0x600000)|value<<21)
}
func (o *FLASH_CTRL_Type) GetSIZE_PACKAGE_SIZE() uint32 {
	return (volatile.LoadUint32(&o.SIZE.Reg) & 0x600000) >> 21
}

// FLASH_CTRL.ADDRESS: ADDRESS register
func (o *FLASH_CTRL_Type) SetADDRESS_YADDR(value uint32) {
	volatile.StoreUint32(&o.ADDRESS.Reg, volatile.LoadUint32(&o.ADDRESS.Reg)&^(0x3f)|value)
}
func (o *FLASH_CTRL_Type) GetADDRESS_YADDR() uint32 {
	return volatile.LoadUint32(&o.ADDRESS.Reg) & 0x3f
}
func (o *FLASH_CTRL_Type) SetADDRESS_XADDR(value uint32) {
	volatile.StoreUint32(&o.ADDRESS.Reg, volatile.LoadUint32(&o.ADDRESS.Reg)&^(0xffc0)|value<<6)
}
func (o *FLASH_CTRL_Type) GetADDRESS_XADDR() uint32 {
	return (volatile.LoadUint32(&o.ADDRESS.Reg) & 0xffc0) >> 6
}

// FLASH_CTRL.LFSRVAL: LFSRVAL register
func (o *FLASH_CTRL_Type) SetLFSRVAL(value uint32) {
	volatile.StoreUint32(&o.LFSRVAL.Reg, value)
}
func (o *FLASH_CTRL_Type) GetLFSRVAL() uint32 {
	return volatile.LoadUint32(&o.LFSRVAL.Reg)
}

// FLASH_CTRL.PAGEPROT0: PAGEPROT0 register
func (o *FLASH_CTRL_Type) SetPAGEPROT0_SEGSIZE0(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT0.Reg, volatile.LoadUint32(&o.PAGEPROT0.Reg)&^(0x7f)|value)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT0_SEGSIZE0() uint32 {
	return volatile.LoadUint32(&o.PAGEPROT0.Reg) & 0x7f
}
func (o *FLASH_CTRL_Type) SetPAGEPROT0_SEGOFFSET0(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT0.Reg, volatile.LoadUint32(&o.PAGEPROT0.Reg)&^(0x7f00)|value<<8)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT0_SEGOFFSET0() uint32 {
	return (volatile.LoadUint32(&o.PAGEPROT0.Reg) & 0x7f00) >> 8
}
func (o *FLASH_CTRL_Type) SetPAGEPROT0_SEGSIZE1(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT0.Reg, volatile.LoadUint32(&o.PAGEPROT0.Reg)&^(0x7f0000)|value<<16)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT0_SEGSIZE1() uint32 {
	return (volatile.LoadUint32(&o.PAGEPROT0.Reg) & 0x7f0000) >> 16
}
func (o *FLASH_CTRL_Type) SetPAGEPROT0_SEGOFFSET1(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT0.Reg, volatile.LoadUint32(&o.PAGEPROT0.Reg)&^(0x7f000000)|value<<24)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT0_SEGOFFSET1() uint32 {
	return (volatile.LoadUint32(&o.PAGEPROT0.Reg) & 0x7f000000) >> 24
}

// FLASH_CTRL.PAGEPROT1: PAGEPROT1 register
func (o *FLASH_CTRL_Type) SetPAGEPROT1_SEGSIZE2(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT1.Reg, volatile.LoadUint32(&o.PAGEPROT1.Reg)&^(0x7f)|value)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT1_SEGSIZE2() uint32 {
	return volatile.LoadUint32(&o.PAGEPROT1.Reg) & 0x7f
}
func (o *FLASH_CTRL_Type) SetPAGEPROT1_SEGOFFSET2(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT1.Reg, volatile.LoadUint32(&o.PAGEPROT1.Reg)&^(0x7f00)|value<<8)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT1_SEGOFFSET2() uint32 {
	return (volatile.LoadUint32(&o.PAGEPROT1.Reg) & 0x7f00) >> 8
}
func (o *FLASH_CTRL_Type) SetPAGEPROT1_SEGSIZE3(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT1.Reg, volatile.LoadUint32(&o.PAGEPROT1.Reg)&^(0x7f0000)|value<<16)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT1_SEGSIZE3() uint32 {
	return (volatile.LoadUint32(&o.PAGEPROT1.Reg) & 0x7f0000) >> 16
}
func (o *FLASH_CTRL_Type) SetPAGEPROT1_SEGOFFSET3(value uint32) {
	volatile.StoreUint32(&o.PAGEPROT1.Reg, volatile.LoadUint32(&o.PAGEPROT1.Reg)&^(0x7f000000)|value<<24)
}
func (o *FLASH_CTRL_Type) GetPAGEPROT1_SEGOFFSET3() uint32 {
	return (volatile.LoadUint32(&o.PAGEPROT1.Reg) & 0x7f000000) >> 24
}

// FLASH_CTRL.DATA0: DATA0 register
func (o *FLASH_CTRL_Type) SetDATA0(value uint32) {
	volatile.StoreUint32(&o.DATA0.Reg, value)
}
func (o *FLASH_CTRL_Type) GetDATA0() uint32 {
	return volatile.LoadUint32(&o.DATA0.Reg)
}

// FLASH_CTRL.DATA1: DATA1 register
func (o *FLASH_CTRL_Type) SetDATA1(value uint32) {
	volatile.StoreUint32(&o.DATA1.Reg, value)
}
func (o *FLASH_CTRL_Type) GetDATA1() uint32 {
	return volatile.LoadUint32(&o.DATA1.Reg)
}

// FLASH_CTRL.DATA2: DATA2 register
func (o *FLASH_CTRL_Type) SetDATA2(value uint32) {
	volatile.StoreUint32(&o.DATA2.Reg, value)
}
func (o *FLASH_CTRL_Type) GetDATA2() uint32 {
	return volatile.LoadUint32(&o.DATA2.Reg)
}

// FLASH_CTRL.DATA3: DATA3 register
func (o *FLASH_CTRL_Type) SetDATA3(value uint32) {
	volatile.StoreUint32(&o.DATA3.Reg, value)
}
func (o *FLASH_CTRL_Type) GetDATA3() uint32 {
	return volatile.LoadUint32(&o.DATA3.Reg)
}

type PKA_Type struct {
	CR    volatile.Register32 // 0x0
	SR    volatile.Register32 // 0x4
	CLRFR volatile.Register32 // 0x8
}

// PKA.CR: PKA_CR register
func (o *PKA_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *PKA_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *PKA_Type) SetCR_START(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *PKA_Type) GetCR_START() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *PKA_Type) SetCR_SECLVL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *PKA_Type) GetCR_SECLVL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *PKA_Type) SetCR_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3f00)|value<<8)
}
func (o *PKA_Type) GetCR_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3f00) >> 8
}
func (o *PKA_Type) SetCR_PROCENDIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *PKA_Type) GetCR_PROCENDIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *PKA_Type) SetCR_RAMERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *PKA_Type) GetCR_RAMERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *PKA_Type) SetCR_ADDRERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *PKA_Type) GetCR_ADDRERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}

// PKA.SR: PKA_SR register
func (o *PKA_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *PKA_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *PKA_Type) SetSR_PROCENDF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *PKA_Type) GetSR_PROCENDF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *PKA_Type) SetSR_RAMERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000)|value<<19)
}
func (o *PKA_Type) GetSR_RAMERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000) >> 19
}
func (o *PKA_Type) SetSR_ADDRERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *PKA_Type) GetSR_ADDRERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}

// PKA.CLRFR: PKA_CLRFR register
func (o *PKA_Type) SetCLRFR_PROCENDFC(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x20000)|value<<17)
}
func (o *PKA_Type) GetCLRFR_PROCENDFC() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x20000) >> 17
}
func (o *PKA_Type) SetCLRFR_RAMERRFC(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x80000)|value<<19)
}
func (o *PKA_Type) GetCLRFR_RAMERRFC() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x80000) >> 19
}
func (o *PKA_Type) SetCLRFR_ADDRERRFC(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x100000)|value<<20)
}
func (o *PKA_Type) GetCLRFR_ADDRERRFC() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x100000) >> 20
}

type PWRC_Type struct {
	CR1    volatile.Register32 // 0x0
	CR2    volatile.Register32 // 0x4
	CR3    volatile.Register32 // 0x8
	CR4    volatile.Register32 // 0xC
	SR1    volatile.Register32 // 0x10
	SR2    volatile.Register32 // 0x14
	_      [4]byte
	CR5    volatile.Register32 // 0x1C
	PUCRA  volatile.Register32 // 0x20
	PDCRA  volatile.Register32 // 0x24
	PUCRB  volatile.Register32 // 0x28
	PDCRB  volatile.Register32 // 0x2C
	CR6    volatile.Register32 // 0x30
	CR7    volatile.Register32 // 0x34
	SR3    volatile.Register32 // 0x38
	_      [72]byte
	DBGR   volatile.Register32 // 0x84
	EXTSRR volatile.Register32 // 0x88
}

// PWRC.CR1: CR1 register
func (o *PWRC_Type) SetCR1_LPMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetCR1_LPMS() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *PWRC_Type) SetCR1_ENSDNBOR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetCR1_ENSDNBOR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetCR1_IBIAS_RUN_AUTO(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetCR1_IBIAS_RUN_AUTO() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetCR1_IBIAS_RUN_STATE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *PWRC_Type) GetCR1_IBIAS_RUN_STATE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *PWRC_Type) SetCR1_APC(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetCR1_APC() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetCR1_ENBORH(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetCR1_ENBORH() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetCR1_SELBORH(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xc0)|value<<6)
}
func (o *PWRC_Type) GetCR1_SELBORH() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xc0) >> 6
}
func (o *PWRC_Type) SetCR1_ENBORL(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *PWRC_Type) GetCR1_ENBORL() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}

// PWRC.CR2: CR2 register
func (o *PWRC_Type) SetCR2_PVDE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetCR2_PVDE() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *PWRC_Type) SetCR2_PVDLS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xe)|value<<1)
}
func (o *PWRC_Type) GetCR2_PVDLS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xe) >> 1
}
func (o *PWRC_Type) SetCR2_DBGRET(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetCR2_DBGRET() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetCR2_RAMRET1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetCR2_RAMRET1() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetCR2_GPIORET(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100)|value<<8)
}
func (o *PWRC_Type) GetCR2_GPIORET() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100) >> 8
}
func (o *PWRC_Type) SetCR2_ENTS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200)|value<<9)
}
func (o *PWRC_Type) GetCR2_ENTS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200) >> 9
}

// PWRC.CR3: CR3 register
func (o *PWRC_Type) SetCR3_EWU0(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetCR3_EWU0() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *PWRC_Type) SetCR3_EWU1(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetCR3_EWU1() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetCR3_EWU2(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetCR3_EWU2() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetCR3_EWU3(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *PWRC_Type) GetCR3_EWU3() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *PWRC_Type) SetCR3_EWU4(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetCR3_EWU4() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetCR3_EWU5(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetCR3_EWU5() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetCR3_EWU6(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *PWRC_Type) GetCR3_EWU6() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *PWRC_Type) SetCR3_EWU7(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *PWRC_Type) GetCR3_EWU7() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *PWRC_Type) SetCR3_EWU8(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *PWRC_Type) GetCR3_EWU8() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *PWRC_Type) SetCR3_EWU9(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x200)|value<<9)
}
func (o *PWRC_Type) GetCR3_EWU9() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x200) >> 9
}
func (o *PWRC_Type) SetCR3_EWU10(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *PWRC_Type) GetCR3_EWU10() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *PWRC_Type) SetCR3_EWU11(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800)|value<<11)
}
func (o *PWRC_Type) GetCR3_EWU11() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800) >> 11
}
func (o *PWRC_Type) SetCR3_EWBLE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *PWRC_Type) GetCR3_EWBLE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}
func (o *PWRC_Type) SetCR3_EWBLEHCPU(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *PWRC_Type) GetCR3_EWBLEHCPU() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *PWRC_Type) SetCR3_EIWL2(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *PWRC_Type) GetCR3_EIWL2() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *PWRC_Type) SetCR3_EIWL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *PWRC_Type) GetCR3_EIWL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}

// PWRC.CR4: CR4 register
func (o *PWRC_Type) SetCR4_WUP0(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetCR4_WUP0() uint32 {
	return volatile.LoadUint32(&o.CR4.Reg) & 0x1
}
func (o *PWRC_Type) SetCR4_WUP1(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetCR4_WUP1() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetCR4_WUP2(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetCR4_WUP2() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetCR4_WUP3(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x8)|value<<3)
}
func (o *PWRC_Type) GetCR4_WUP3() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x8) >> 3
}
func (o *PWRC_Type) SetCR4_WUP4(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetCR4_WUP4() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetCR4_WUP5(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetCR4_WUP5() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetCR4_WUP6(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x40)|value<<6)
}
func (o *PWRC_Type) GetCR4_WUP6() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x40) >> 6
}
func (o *PWRC_Type) SetCR4_WUP7(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x80)|value<<7)
}
func (o *PWRC_Type) GetCR4_WUP7() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x80) >> 7
}
func (o *PWRC_Type) SetCR4_WUP8(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x100)|value<<8)
}
func (o *PWRC_Type) GetCR4_WUP8() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x100) >> 8
}
func (o *PWRC_Type) SetCR4_WUP9(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x200)|value<<9)
}
func (o *PWRC_Type) GetCR4_WUP9() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x200) >> 9
}
func (o *PWRC_Type) SetCR4_WUP10(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x400)|value<<10)
}
func (o *PWRC_Type) GetCR4_WUP10() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x400) >> 10
}
func (o *PWRC_Type) SetCR4_WUP11(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x800)|value<<11)
}
func (o *PWRC_Type) GetCR4_WUP11() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x800) >> 11
}

// PWRC.SR1: SR1 register
func (o *PWRC_Type) SetSR1_WUF0(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetSR1_WUF0() uint32 {
	return volatile.LoadUint32(&o.SR1.Reg) & 0x1
}
func (o *PWRC_Type) SetSR1_WUF1(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetSR1_WUF1() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetSR1_WUF2(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetSR1_WUF2() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetSR1_WUF3(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8)|value<<3)
}
func (o *PWRC_Type) GetSR1_WUF3() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8) >> 3
}
func (o *PWRC_Type) SetSR1_WUF4(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetSR1_WUF4() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetSR1_WUF5(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetSR1_WUF5() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetSR1_WUF6(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x40)|value<<6)
}
func (o *PWRC_Type) GetSR1_WUF6() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x40) >> 6
}
func (o *PWRC_Type) SetSR1_WUF7(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x80)|value<<7)
}
func (o *PWRC_Type) GetSR1_WUF7() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x80) >> 7
}
func (o *PWRC_Type) SetSR1_WUF8(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x100)|value<<8)
}
func (o *PWRC_Type) GetSR1_WUF8() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x100) >> 8
}
func (o *PWRC_Type) SetSR1_WUF9(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x200)|value<<9)
}
func (o *PWRC_Type) GetSR1_WUF9() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x200) >> 9
}
func (o *PWRC_Type) SetSR1_WUF10(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x400)|value<<10)
}
func (o *PWRC_Type) GetSR1_WUF10() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x400) >> 10
}
func (o *PWRC_Type) SetSR1_WUF11(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x800)|value<<11)
}
func (o *PWRC_Type) GetSR1_WUF11() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x800) >> 11
}
func (o *PWRC_Type) SetSR1_WBLEF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1000)|value<<12)
}
func (o *PWRC_Type) GetSR1_WBLEF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x1000) >> 12
}
func (o *PWRC_Type) SetSR1_WBLEHCPUF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2000)|value<<13)
}
func (o *PWRC_Type) GetSR1_WBLEHCPUF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2000) >> 13
}
func (o *PWRC_Type) SetSR1_IWUF2(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x4000)|value<<14)
}
func (o *PWRC_Type) GetSR1_IWUF2() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x4000) >> 14
}
func (o *PWRC_Type) SetSR1_IWUF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8000)|value<<15)
}
func (o *PWRC_Type) GetSR1_IWUF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8000) >> 15
}

// PWRC.SR2: SR2 register
func (o *PWRC_Type) SetSR2_SMPSBYPR(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetSR2_SMPSBYPR() uint32 {
	return volatile.LoadUint32(&o.SR2.Reg) & 0x1
}
func (o *PWRC_Type) SetSR2_SMPSENR(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetSR2_SMPSENR() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetSR2_SMPSRDY(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetSR2_SMPSRDY() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetSR2_IOBOOTVAL2(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0xf0)|value<<4)
}
func (o *PWRC_Type) GetSR2_IOBOOTVAL2() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0xf0) >> 4
}
func (o *PWRC_Type) SetSR2_REGLPS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x100)|value<<8)
}
func (o *PWRC_Type) GetSR2_REGLPS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x100) >> 8
}
func (o *PWRC_Type) SetSR2_REGMS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x200)|value<<9)
}
func (o *PWRC_Type) GetSR2_REGMS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x200) >> 9
}
func (o *PWRC_Type) SetSR2_PVDO(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x800)|value<<11)
}
func (o *PWRC_Type) GetSR2_PVDO() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x800) >> 11
}
func (o *PWRC_Type) SetSR2_IOBOOTVAL(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0xf000)|value<<12)
}
func (o *PWRC_Type) GetSR2_IOBOOTVAL() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0xf000) >> 12
}

// PWRC.CR5: CR5 register
func (o *PWRC_Type) SetCR5_SMPSLVL(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0xf)|value)
}
func (o *PWRC_Type) GetCR5_SMPSLVL() uint32 {
	return volatile.LoadUint32(&o.CR5.Reg) & 0xf
}
func (o *PWRC_Type) SetCR5_SMPSBOMSEL(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x30)|value<<4)
}
func (o *PWRC_Type) GetCR5_SMPSBOMSEL() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x30) >> 4
}
func (o *PWRC_Type) SetCR5_SMPSFRDY(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x80)|value<<7)
}
func (o *PWRC_Type) GetCR5_SMPSFRDY() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x80) >> 7
}
func (o *PWRC_Type) SetCR5_SMPSLPOPEN(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x100)|value<<8)
}
func (o *PWRC_Type) GetCR5_SMPSLPOPEN() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x100) >> 8
}
func (o *PWRC_Type) SetCR5_SMPSFBYP(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x200)|value<<9)
}
func (o *PWRC_Type) GetCR5_SMPSFBYP() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x200) >> 9
}
func (o *PWRC_Type) SetCR5_NOSMPS(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x400)|value<<10)
}
func (o *PWRC_Type) GetCR5_NOSMPS() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x400) >> 10
}
func (o *PWRC_Type) SetCR5_SMPS_ENA_DCM(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x800)|value<<11)
}
func (o *PWRC_Type) GetCR5_SMPS_ENA_DCM() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x800) >> 11
}
func (o *PWRC_Type) SetCR5_CLKDETR_DISABLE(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x1000)|value<<12)
}
func (o *PWRC_Type) GetCR5_CLKDETR_DISABLE() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x1000) >> 12
}
func (o *PWRC_Type) SetCR5_SMPS_PRECH_CUR_SEL(value uint32) {
	volatile.StoreUint32(&o.CR5.Reg, volatile.LoadUint32(&o.CR5.Reg)&^(0x6000)|value<<13)
}
func (o *PWRC_Type) GetCR5_SMPS_PRECH_CUR_SEL() uint32 {
	return (volatile.LoadUint32(&o.CR5.Reg) & 0x6000) >> 13
}

// PWRC.PUCRA: PUCRA register
func (o *PWRC_Type) SetPUCRA_PU(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0xffff)|value)
}
func (o *PWRC_Type) GetPUCRA_PU() uint32 {
	return volatile.LoadUint32(&o.PUCRA.Reg) & 0xffff
}

// PWRC.PDCRA: PDCRA register
func (o *PWRC_Type) SetPDCRA_PD(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0xffff)|value)
}
func (o *PWRC_Type) GetPDCRA_PD() uint32 {
	return volatile.LoadUint32(&o.PDCRA.Reg) & 0xffff
}

// PWRC.PUCRB: PUCRB register
func (o *PWRC_Type) SetPUCRB_PU(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0xffff)|value)
}
func (o *PWRC_Type) GetPUCRB_PU() uint32 {
	return volatile.LoadUint32(&o.PUCRB.Reg) & 0xffff
}

// PWRC.PDCRB: PDCRB register
func (o *PWRC_Type) SetPDCRB_PD(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0xffff)|value)
}
func (o *PWRC_Type) GetPDCRB_PD() uint32 {
	return volatile.LoadUint32(&o.PDCRB.Reg) & 0xffff
}

// PWRC.CR6: CR6 register
func (o *PWRC_Type) SetCR6_EWU12(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetCR6_EWU12() uint32 {
	return volatile.LoadUint32(&o.CR6.Reg) & 0x1
}
func (o *PWRC_Type) SetCR6_EWU13(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetCR6_EWU13() uint32 {
	return (volatile.LoadUint32(&o.CR6.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetCR6_EWU14(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetCR6_EWU14() uint32 {
	return (volatile.LoadUint32(&o.CR6.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetCR6_EWU15(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x8)|value<<3)
}
func (o *PWRC_Type) GetCR6_EWU15() uint32 {
	return (volatile.LoadUint32(&o.CR6.Reg) & 0x8) >> 3
}
func (o *PWRC_Type) SetCR6_EWU16(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetCR6_EWU16() uint32 {
	return (volatile.LoadUint32(&o.CR6.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetCR6_EWU17(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetCR6_EWU17() uint32 {
	return (volatile.LoadUint32(&o.CR6.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetCR6_EWU18(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x40)|value<<6)
}
func (o *PWRC_Type) GetCR6_EWU18() uint32 {
	return (volatile.LoadUint32(&o.CR6.Reg) & 0x40) >> 6
}
func (o *PWRC_Type) SetCR6_EWU19(value uint32) {
	volatile.StoreUint32(&o.CR6.Reg, volatile.LoadUint32(&o.CR6.Reg)&^(0x80)|value<<7)
}
func (o *PWRC_Type) GetCR6_EWU19() uint32 {
	return (volatile.LoadUint32(&o.CR6.Reg) & 0x80) >> 7
}

// PWRC.CR7: CR7 register
func (o *PWRC_Type) SetCR7_WUP12(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetCR7_WUP12() uint32 {
	return volatile.LoadUint32(&o.CR7.Reg) & 0x1
}
func (o *PWRC_Type) SetCR7_WUP13(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetCR7_WUP13() uint32 {
	return (volatile.LoadUint32(&o.CR7.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetCR7_WUP14(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetCR7_WUP14() uint32 {
	return (volatile.LoadUint32(&o.CR7.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetCR7_WUP15(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x8)|value<<3)
}
func (o *PWRC_Type) GetCR7_WUP15() uint32 {
	return (volatile.LoadUint32(&o.CR7.Reg) & 0x8) >> 3
}
func (o *PWRC_Type) SetCR7_WUP16(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetCR7_WUP16() uint32 {
	return (volatile.LoadUint32(&o.CR7.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetCR7_WUP17(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetCR7_WUP17() uint32 {
	return (volatile.LoadUint32(&o.CR7.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetCR7_WUP18(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x40)|value<<6)
}
func (o *PWRC_Type) GetCR7_WUP18() uint32 {
	return (volatile.LoadUint32(&o.CR7.Reg) & 0x40) >> 6
}
func (o *PWRC_Type) SetCR7_WUP19(value uint32) {
	volatile.StoreUint32(&o.CR7.Reg, volatile.LoadUint32(&o.CR7.Reg)&^(0x80)|value<<7)
}
func (o *PWRC_Type) GetCR7_WUP19() uint32 {
	return (volatile.LoadUint32(&o.CR7.Reg) & 0x80) >> 7
}

// PWRC.SR3: SR3 register
func (o *PWRC_Type) SetSR3_WUF12(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetSR3_WUF12() uint32 {
	return volatile.LoadUint32(&o.SR3.Reg) & 0x1
}
func (o *PWRC_Type) SetSR3_WUF13(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x2)|value<<1)
}
func (o *PWRC_Type) GetSR3_WUF13() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x2) >> 1
}
func (o *PWRC_Type) SetSR3_WUF14(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x4)|value<<2)
}
func (o *PWRC_Type) GetSR3_WUF14() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x4) >> 2
}
func (o *PWRC_Type) SetSR3_WUF15(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x8)|value<<3)
}
func (o *PWRC_Type) GetSR3_WUF15() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x8) >> 3
}
func (o *PWRC_Type) SetSR3_WUF16(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x10)|value<<4)
}
func (o *PWRC_Type) GetSR3_WUF16() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x10) >> 4
}
func (o *PWRC_Type) SetSR3_WUF17(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x20)|value<<5)
}
func (o *PWRC_Type) GetSR3_WUF17() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x20) >> 5
}
func (o *PWRC_Type) SetSR3_WUF18(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x40)|value<<6)
}
func (o *PWRC_Type) GetSR3_WUF18() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x40) >> 6
}
func (o *PWRC_Type) SetSR3_WUF19(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x80)|value<<7)
}
func (o *PWRC_Type) GetSR3_WUF19() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x80) >> 7
}

// PWRC.DBGR: DBGR register
func (o *PWRC_Type) SetDBGR_DEEPSTOP2(value uint32) {
	volatile.StoreUint32(&o.DBGR.Reg, volatile.LoadUint32(&o.DBGR.Reg)&^(0x1)|value)
}
func (o *PWRC_Type) GetDBGR_DEEPSTOP2() uint32 {
	return volatile.LoadUint32(&o.DBGR.Reg) & 0x1
}
func (o *PWRC_Type) SetDBGR_DIS_PRECH(value uint32) {
	volatile.StoreUint32(&o.DBGR.Reg, volatile.LoadUint32(&o.DBGR.Reg)&^(0xe000)|value<<13)
}
func (o *PWRC_Type) GetDBGR_DIS_PRECH() uint32 {
	return (volatile.LoadUint32(&o.DBGR.Reg) & 0xe000) >> 13
}

// PWRC.EXTSRR: EXTSRR register
func (o *PWRC_Type) SetEXTSRR_DEEPSTOPF(value uint32) {
	volatile.StoreUint32(&o.EXTSRR.Reg, volatile.LoadUint32(&o.EXTSRR.Reg)&^(0x200)|value<<9)
}
func (o *PWRC_Type) GetEXTSRR_DEEPSTOPF() uint32 {
	return (volatile.LoadUint32(&o.EXTSRR.Reg) & 0x200) >> 9
}
func (o *PWRC_Type) SetEXTSRR_RFPHASEF(value uint32) {
	volatile.StoreUint32(&o.EXTSRR.Reg, volatile.LoadUint32(&o.EXTSRR.Reg)&^(0x400)|value<<10)
}
func (o *PWRC_Type) GetEXTSRR_RFPHASEF() uint32 {
	return (volatile.LoadUint32(&o.EXTSRR.Reg) & 0x400) >> 10
}

type RNG_Type struct {
	CR  volatile.Register32 // 0x0
	SR  volatile.Register32 // 0x4
	VAL volatile.Register32 // 0x8
}

// RNG.CR: RNG_CR register
func (o *RNG_Type) SetCR_RNG_DIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *RNG_Type) GetCR_RNG_DIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *RNG_Type) SetCR_TST_CLK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RNG_Type) GetCR_TST_CLK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}

// RNG.SR: RNG_SR register
func (o *RNG_Type) SetSR_RNGRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *RNG_Type) GetSR_RNGRDY() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *RNG_Type) SetSR_REVCLK(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *RNG_Type) GetSR_REVCLK() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *RNG_Type) SetSR_FAULT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RNG_Type) GetSR_FAULT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}

// RNG.VAL: RNG_VAL register
func (o *RNG_Type) SetVAL_RANDOM_VALUE(value uint32) {
	volatile.StoreUint32(&o.VAL.Reg, volatile.LoadUint32(&o.VAL.Reg)&^(0xffff)|value)
}
func (o *RNG_Type) GetVAL_RANDOM_VALUE() uint32 {
	return volatile.LoadUint32(&o.VAL.Reg) & 0xffff
}

type RTC_Type struct {
	TR       volatile.Register32 // 0x0
	DR       volatile.Register32 // 0x4
	CR       volatile.Register32 // 0x8
	ISR      volatile.Register32 // 0xC
	PRER     volatile.Register32 // 0x10
	WUTR     volatile.Register32 // 0x14
	_        [4]byte
	ALRMAR   volatile.Register32 // 0x1C
	_        [4]byte
	WPR      volatile.Register32 // 0x24
	SSR      volatile.Register32 // 0x28
	SHIFTR   volatile.Register32 // 0x2C
	_        [12]byte
	CALR     volatile.Register32 // 0x3C
	_        [4]byte
	ALRMASSR volatile.Register32 // 0x44
	_        [8]byte
	BKP0R    volatile.Register32 // 0x50
	BKP1R    volatile.Register32 // 0x54
}

// RTC.TR: RTC_TR register
func (o *RTC_Type) SetTR_SU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetTR_SU() uint32 {
	return volatile.LoadUint32(&o.TR.Reg) & 0xf
}
func (o *RTC_Type) SetTR_ST(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetTR_ST() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetTR_MNU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetTR_MNU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetTR_MNT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetTR_MNT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetTR_HU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetTR_HU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetTR_HT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetTR_HT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetTR_PM(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetTR_PM() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x400000) >> 22
}

// RTC.DR: RTC_DR register
func (o *RTC_Type) SetDR_DU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetDR_DU() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xf
}
func (o *RTC_Type) SetDR_DT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x30)|value<<4)
}
func (o *RTC_Type) GetDR_DT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x30) >> 4
}
func (o *RTC_Type) SetDR_MU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetDR_MU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetDR_MT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_Type) GetDR_MT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x1000) >> 12
}
func (o *RTC_Type) SetDR_WDU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xe000)|value<<13)
}
func (o *RTC_Type) GetDR_WDU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xe000) >> 13
}
func (o *RTC_Type) SetDR_YU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetDR_YU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetDR_YT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00000)|value<<20)
}
func (o *RTC_Type) GetDR_YT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00000) >> 20
}

// RTC.CR: RTC_CR register
func (o *RTC_Type) SetCR_WUCKSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7)|value)
}
func (o *RTC_Type) GetCR_WUCKSEL() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x7
}
func (o *RTC_Type) SetCR_BYPSHAD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetCR_BYPSHAD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetCR_FMT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetCR_FMT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetCR_ALRAE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *RTC_Type) GetCR_ALRAE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *RTC_Type) SetCR_WUTE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetCR_WUTE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetCR_ALRAIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_Type) GetCR_ALRAIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *RTC_Type) SetCR_WUTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCR_WUTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCR_ADD1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetCR_ADD1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RTC_Type) SetCR_SUB1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RTC_Type) GetCR_SUB1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *RTC_Type) SetCR_BKP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *RTC_Type) GetCR_BKP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *RTC_Type) SetCR_COSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *RTC_Type) GetCR_COSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *RTC_Type) SetCR_POL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *RTC_Type) GetCR_POL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *RTC_Type) SetCR_OSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x600000)|value<<21)
}
func (o *RTC_Type) GetCR_OSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x600000) >> 21
}
func (o *RTC_Type) SetCR_COE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetCR_COE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800000) >> 23
}

// RTC.ISR: RTC_ISR register
func (o *RTC_Type) SetISR_ALRAWF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetISR_ALRAWF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *RTC_Type) SetISR_WUTWF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetISR_WUTWF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetISR_SHPF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetISR_SHPF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetISR_INITS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetISR_INITS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetISR_RSF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetISR_RSF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetISR_INITF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetISR_INITF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetISR_INIT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetISR_INIT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetISR_ALRAF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *RTC_Type) GetISR_ALRAF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *RTC_Type) SetISR_WUTF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetISR_WUTF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetISR_RECALPF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetISR_RECALPF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}

// RTC.PRER: RTC_PRER register
func (o *RTC_Type) SetPRER_PREDIV_S(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetPRER_PREDIV_S() uint32 {
	return volatile.LoadUint32(&o.PRER.Reg) & 0x7fff
}
func (o *RTC_Type) SetPRER_PREDIV_A(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7f0000)|value<<16)
}
func (o *RTC_Type) GetPRER_PREDIV_A() uint32 {
	return (volatile.LoadUint32(&o.PRER.Reg) & 0x7f0000) >> 16
}

// RTC.WUTR: RTC_WUTR register
func (o *RTC_Type) SetWUTR_WUT(value uint32) {
	volatile.StoreUint32(&o.WUTR.Reg, volatile.LoadUint32(&o.WUTR.Reg)&^(0xffff)|value)
}
func (o *RTC_Type) GetWUTR_WUT() uint32 {
	return volatile.LoadUint32(&o.WUTR.Reg) & 0xffff
}

// RTC.ALRMAR: RTC_ALRMAR register
func (o *RTC_Type) SetALRMAR_SU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetALRMAR_SU() uint32 {
	return volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf
}
func (o *RTC_Type) SetALRMAR_ST(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetALRMAR_ST() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetALRMAR_MSK1(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetALRMAR_MSK1() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetALRMAR_MNU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetALRMAR_MNU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetALRMAR_MNT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetALRMAR_MNT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetALRMAR_MSK2(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetALRMAR_MSK2() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetALRMAR_HU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetALRMAR_HU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetALRMAR_HT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetALRMAR_HT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetALRMAR_PM(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetALRMAR_PM() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetALRMAR_MSK3(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetALRMAR_MSK3() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetALRMAR_DU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMAR_DU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMAR_DT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x30000000)|value<<28)
}
func (o *RTC_Type) GetALRMAR_DT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x30000000) >> 28
}
func (o *RTC_Type) SetALRMAR_WDSEL(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetALRMAR_WDSEL() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetALRMAR_MSK4(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMAR_MSK4() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80000000) >> 31
}

// RTC.WPR: RTC_WPR register
func (o *RTC_Type) SetWPR_KEY(value uint32) {
	volatile.StoreUint32(&o.WPR.Reg, volatile.LoadUint32(&o.WPR.Reg)&^(0xff)|value)
}
func (o *RTC_Type) GetWPR_KEY() uint32 {
	return volatile.LoadUint32(&o.WPR.Reg) & 0xff
}

// RTC.SSR: RTC_SSR register
func (o *RTC_Type) SetSSR_SS(value uint32) {
	volatile.StoreUint32(&o.SSR.Reg, volatile.LoadUint32(&o.SSR.Reg)&^(0xffff)|value)
}
func (o *RTC_Type) GetSSR_SS() uint32 {
	return volatile.LoadUint32(&o.SSR.Reg) & 0xffff
}

// RTC.SHIFTR: RTC_SHIFTR register
func (o *RTC_Type) SetSHIFTR_SUBFS(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetSHIFTR_SUBFS() uint32 {
	return volatile.LoadUint32(&o.SHIFTR.Reg) & 0x7fff
}
func (o *RTC_Type) SetSHIFTR_ADD1S(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetSHIFTR_ADD1S() uint32 {
	return (volatile.LoadUint32(&o.SHIFTR.Reg) & 0x80000000) >> 31
}

// RTC.CALR: RTC_CALR register
func (o *RTC_Type) SetCALR_CALM(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x1ff)|value)
}
func (o *RTC_Type) GetCALR_CALM() uint32 {
	return volatile.LoadUint32(&o.CALR.Reg) & 0x1ff
}
func (o *RTC_Type) SetCALR_CALW16(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetCALR_CALW16() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetCALR_CALW8(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCALR_CALW8() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCALR_CALP(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetCALR_CALP() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x8000) >> 15
}

// RTC.ALRMASSR: RTC_ALRMASSR register
func (o *RTC_Type) SetALRMASSR_SS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetALRMASSR_SS() uint32 {
	return volatile.LoadUint32(&o.ALRMASSR.Reg) & 0x7fff
}
func (o *RTC_Type) SetALRMASSR_MASKSS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMASSR_MASKSS() uint32 {
	return (volatile.LoadUint32(&o.ALRMASSR.Reg) & 0xf000000) >> 24
}

// RTC.BKP0R: RTC_BKP0R register
func (o *RTC_Type) SetBKP0R(value uint32) {
	volatile.StoreUint32(&o.BKP0R.Reg, value)
}
func (o *RTC_Type) GetBKP0R() uint32 {
	return volatile.LoadUint32(&o.BKP0R.Reg)
}

// RTC.BKP1R: RTC_BKP1R register
func (o *RTC_Type) SetBKP1R(value uint32) {
	volatile.StoreUint32(&o.BKP1R.Reg, value)
}
func (o *RTC_Type) GetBKP1R() uint32 {
	return volatile.LoadUint32(&o.BKP1R.Reg)
}

type SYSTEM_CTRL_Type struct {
	DIE_ID       volatile.Register32 // 0x0
	JTAG_ID      volatile.Register32 // 0x4
	I2C_FMP_CTRL volatile.Register32 // 0x8
	IO_DTR       volatile.Register32 // 0xC
	IO_IBER      volatile.Register32 // 0x10
	IO_IEVR      volatile.Register32 // 0x14
	IO_IER       volatile.Register32 // 0x18
	IO_ISCR      volatile.Register32 // 0x1C
	PWRC_IER     volatile.Register32 // 0x20
	PWRC_ISCR    volatile.Register32 // 0x24
	_            [4]byte
	BLERXTX_DTR  volatile.Register32 // 0x2C
	BLERXTX_IBER volatile.Register32 // 0x30
	BLERXTX_IEVR volatile.Register32 // 0x34
	BLERXTX_IER  volatile.Register32 // 0x38
	BLERXTX_ISCR volatile.Register8  // 0x3C
}

// SYSTEM_CTRL.DIE_ID: DIE_ID register
func (o *SYSTEM_CTRL_Type) SetDIE_ID_REVISION(value uint32) {
	volatile.StoreUint32(&o.DIE_ID.Reg, volatile.LoadUint32(&o.DIE_ID.Reg)&^(0xf)|value)
}
func (o *SYSTEM_CTRL_Type) GetDIE_ID_REVISION() uint32 {
	return volatile.LoadUint32(&o.DIE_ID.Reg) & 0xf
}
func (o *SYSTEM_CTRL_Type) SetDIE_ID_VERSION(value uint32) {
	volatile.StoreUint32(&o.DIE_ID.Reg, volatile.LoadUint32(&o.DIE_ID.Reg)&^(0xf0)|value<<4)
}
func (o *SYSTEM_CTRL_Type) GetDIE_ID_VERSION() uint32 {
	return (volatile.LoadUint32(&o.DIE_ID.Reg) & 0xf0) >> 4
}
func (o *SYSTEM_CTRL_Type) SetDIE_ID_PRODUCT(value uint32) {
	volatile.StoreUint32(&o.DIE_ID.Reg, volatile.LoadUint32(&o.DIE_ID.Reg)&^(0xf00)|value<<8)
}
func (o *SYSTEM_CTRL_Type) GetDIE_ID_PRODUCT() uint32 {
	return (volatile.LoadUint32(&o.DIE_ID.Reg) & 0xf00) >> 8
}

// SYSTEM_CTRL.JTAG_ID: JTAG_ID register
func (o *SYSTEM_CTRL_Type) SetJTAG_ID_MANUF_ID(value uint32) {
	volatile.StoreUint32(&o.JTAG_ID.Reg, volatile.LoadUint32(&o.JTAG_ID.Reg)&^(0xffe)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetJTAG_ID_MANUF_ID() uint32 {
	return (volatile.LoadUint32(&o.JTAG_ID.Reg) & 0xffe) >> 1
}
func (o *SYSTEM_CTRL_Type) SetJTAG_ID_PART_NUMBER(value uint32) {
	volatile.StoreUint32(&o.JTAG_ID.Reg, volatile.LoadUint32(&o.JTAG_ID.Reg)&^(0xffff000)|value<<12)
}
func (o *SYSTEM_CTRL_Type) GetJTAG_ID_PART_NUMBER() uint32 {
	return (volatile.LoadUint32(&o.JTAG_ID.Reg) & 0xffff000) >> 12
}
func (o *SYSTEM_CTRL_Type) SetJTAG_ID_VERSION_NUMBER(value uint32) {
	volatile.StoreUint32(&o.JTAG_ID.Reg, volatile.LoadUint32(&o.JTAG_ID.Reg)&^(0xf0000000)|value<<28)
}
func (o *SYSTEM_CTRL_Type) GetJTAG_ID_VERSION_NUMBER() uint32 {
	return (volatile.LoadUint32(&o.JTAG_ID.Reg) & 0xf0000000) >> 28
}

// SYSTEM_CTRL.I2C_FMP_CTRL: I2C_FMP_CTRL register
func (o *SYSTEM_CTRL_Type) SetI2C_FMP_CTRL_I2C1_PA0_FMP(value uint32) {
	volatile.StoreUint32(&o.I2C_FMP_CTRL.Reg, volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetI2C_FMP_CTRL_I2C1_PA0_FMP() uint32 {
	return volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetI2C_FMP_CTRL_I2C1_PA1_FMP(value uint32) {
	volatile.StoreUint32(&o.I2C_FMP_CTRL.Reg, volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetI2C_FMP_CTRL_I2C1_PA1_FMP() uint32 {
	return (volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetI2C_FMP_CTRL_I2C1_PB6_FMP(value uint32) {
	volatile.StoreUint32(&o.I2C_FMP_CTRL.Reg, volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetI2C_FMP_CTRL_I2C1_PB6_FMP() uint32 {
	return (volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg) & 0x4) >> 2
}
func (o *SYSTEM_CTRL_Type) SetI2C_FMP_CTRL_I2C1_PB7_FMP(value uint32) {
	volatile.StoreUint32(&o.I2C_FMP_CTRL.Reg, volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg)&^(0x8)|value<<3)
}
func (o *SYSTEM_CTRL_Type) GetI2C_FMP_CTRL_I2C1_PB7_FMP() uint32 {
	return (volatile.LoadUint32(&o.I2C_FMP_CTRL.Reg) & 0x8) >> 3
}

// SYSTEM_CTRL.IO_DTR: IO_DTR register
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA0_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA0_DT() uint32 {
	return volatile.LoadUint32(&o.IO_DTR.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA1_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA1_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA2_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA2_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x4) >> 2
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA3_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x8)|value<<3)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA3_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x8) >> 3
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA8_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x100)|value<<8)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA8_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x100) >> 8
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA9_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x200)|value<<9)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA9_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x200) >> 9
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA10_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x400)|value<<10)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA10_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x400) >> 10
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PA11_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x800)|value<<11)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PA11_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x800) >> 11
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB0_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB0_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x10000) >> 16
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB1_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x20000)|value<<17)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB1_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x20000) >> 17
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB2_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x40000)|value<<18)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB2_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x40000) >> 18
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB3_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x80000)|value<<19)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB3_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x80000) >> 19
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB4_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x100000)|value<<20)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB4_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x100000) >> 20
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB5_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x200000)|value<<21)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB5_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x200000) >> 21
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB6_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x400000)|value<<22)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB6_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x400000) >> 22
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB7_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x800000)|value<<23)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB7_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x800000) >> 23
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB12_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB12_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x10000000) >> 28
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB13_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB13_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x20000000) >> 29
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB14_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB14_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x40000000) >> 30
}
func (o *SYSTEM_CTRL_Type) SetIO_DTR_PB15_DT(value uint32) {
	volatile.StoreUint32(&o.IO_DTR.Reg, volatile.LoadUint32(&o.IO_DTR.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTEM_CTRL_Type) GetIO_DTR_PB15_DT() uint32 {
	return (volatile.LoadUint32(&o.IO_DTR.Reg) & 0x80000000) >> 31
}

// SYSTEM_CTRL.IO_IBER: IO_IBER register
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA0_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA0_IBE() uint32 {
	return volatile.LoadUint32(&o.IO_IBER.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA1_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA1_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA2_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA2_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x4) >> 2
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA3_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x8)|value<<3)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA3_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x8) >> 3
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA8_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x100)|value<<8)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA8_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x100) >> 8
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA9_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x200)|value<<9)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA9_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x200) >> 9
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA10_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x400)|value<<10)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA10_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x400) >> 10
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PA11_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x800)|value<<11)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PA11_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x800) >> 11
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB0_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x10000)|value<<16)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB0_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x10000) >> 16
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB1_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x20000)|value<<17)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB1_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x20000) >> 17
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB2_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x40000)|value<<18)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB2_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x40000) >> 18
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB3_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x80000)|value<<19)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB3_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x80000) >> 19
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB4_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x100000)|value<<20)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB4_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x100000) >> 20
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB5_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x200000)|value<<21)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB5_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x200000) >> 21
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB6_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x400000)|value<<22)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB6_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x400000) >> 22
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB7_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x800000)|value<<23)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB7_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x800000) >> 23
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB12_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB12_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x10000000) >> 28
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB13_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB13_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x20000000) >> 29
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB14_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB14_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x40000000) >> 30
}
func (o *SYSTEM_CTRL_Type) SetIO_IBER_PB15_IBE(value uint32) {
	volatile.StoreUint32(&o.IO_IBER.Reg, volatile.LoadUint32(&o.IO_IBER.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTEM_CTRL_Type) GetIO_IBER_PB15_IBE() uint32 {
	return (volatile.LoadUint32(&o.IO_IBER.Reg) & 0x80000000) >> 31
}

// SYSTEM_CTRL.IO_IEVR: IO_IEVR register
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA0_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA0_IEV() uint32 {
	return volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA1_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA1_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA2_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA2_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x4) >> 2
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA3_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x8)|value<<3)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA3_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x8) >> 3
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA8_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x100)|value<<8)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA8_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x100) >> 8
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA9_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x200)|value<<9)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA9_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x200) >> 9
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA10_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x400)|value<<10)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA10_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x400) >> 10
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PA11_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x800)|value<<11)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PA11_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x800) >> 11
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB0_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB0_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x10000) >> 16
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB1_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x20000)|value<<17)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB1_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x20000) >> 17
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB2_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x40000)|value<<18)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB2_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x40000) >> 18
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB3_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x80000)|value<<19)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB3_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x80000) >> 19
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB4_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x100000)|value<<20)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB4_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x100000) >> 20
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB5_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x200000)|value<<21)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB5_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x200000) >> 21
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB6_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x400000)|value<<22)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB6_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x400000) >> 22
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB7_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x800000)|value<<23)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB7_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x800000) >> 23
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB12_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB12_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x10000000) >> 28
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB13_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB13_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x20000000) >> 29
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB14_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB14_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x40000000) >> 30
}
func (o *SYSTEM_CTRL_Type) SetIO_IEVR_PB15_IEV(value uint32) {
	volatile.StoreUint32(&o.IO_IEVR.Reg, volatile.LoadUint32(&o.IO_IEVR.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTEM_CTRL_Type) GetIO_IEVR_PB15_IEV() uint32 {
	return (volatile.LoadUint32(&o.IO_IEVR.Reg) & 0x80000000) >> 31
}

// SYSTEM_CTRL.IO_IER: IO_IER register
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA0_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA0_IE() uint32 {
	return volatile.LoadUint32(&o.IO_IER.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA1_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA1_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA2_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA2_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x4) >> 2
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA3_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x8)|value<<3)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA3_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x8) >> 3
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA8_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x100)|value<<8)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA8_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x100) >> 8
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA9_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x200)|value<<9)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA9_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x200) >> 9
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA10_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x400)|value<<10)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA10_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x400) >> 10
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PA11_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x800)|value<<11)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PA11_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x800) >> 11
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB0_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x10000)|value<<16)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB0_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x10000) >> 16
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB1_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x20000)|value<<17)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB1_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x20000) >> 17
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB2_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x40000)|value<<18)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB2_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x40000) >> 18
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB3_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x80000)|value<<19)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB3_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x80000) >> 19
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB4_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x100000)|value<<20)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB4_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x100000) >> 20
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB5_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x200000)|value<<21)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB5_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x200000) >> 21
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB6_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x400000)|value<<22)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB6_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x400000) >> 22
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB7_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x800000)|value<<23)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB7_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x800000) >> 23
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB12_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB12_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x10000000) >> 28
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB13_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB13_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x20000000) >> 29
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB14_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB14_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x40000000) >> 30
}
func (o *SYSTEM_CTRL_Type) SetIO_IER_PB15_IE(value uint32) {
	volatile.StoreUint32(&o.IO_IER.Reg, volatile.LoadUint32(&o.IO_IER.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTEM_CTRL_Type) GetIO_IER_PB15_IE() uint32 {
	return (volatile.LoadUint32(&o.IO_IER.Reg) & 0x80000000) >> 31
}

// SYSTEM_CTRL.IO_ISCR: IO_ISCR register
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA0_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA0_ISC() uint32 {
	return volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA1_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA1_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA2_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA2_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x4) >> 2
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA3_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x8)|value<<3)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA3_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x8) >> 3
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA8_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x100)|value<<8)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA8_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x100) >> 8
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA9_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x200)|value<<9)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA9_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x200) >> 9
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA10_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x400)|value<<10)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA10_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x400) >> 10
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PA11_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x800)|value<<11)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PA11_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x800) >> 11
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB0_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB0_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x10000) >> 16
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB1_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x20000)|value<<17)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB1_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x20000) >> 17
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB2_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x40000)|value<<18)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB2_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x40000) >> 18
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB3_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x80000)|value<<19)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB3_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x80000) >> 19
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB4_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x100000)|value<<20)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB4_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x100000) >> 20
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB5_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x200000)|value<<21)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB5_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x200000) >> 21
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB6_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x400000)|value<<22)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB6_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x400000) >> 22
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB7_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x800000)|value<<23)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB7_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x800000) >> 23
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB12_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB12_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x10000000) >> 28
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB13_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB13_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x20000000) >> 29
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB14_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB14_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x40000000) >> 30
}
func (o *SYSTEM_CTRL_Type) SetIO_ISCR_PB15_ISC(value uint32) {
	volatile.StoreUint32(&o.IO_ISCR.Reg, volatile.LoadUint32(&o.IO_ISCR.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSTEM_CTRL_Type) GetIO_ISCR_PB15_ISC() uint32 {
	return (volatile.LoadUint32(&o.IO_ISCR.Reg) & 0x80000000) >> 31
}

// SYSTEM_CTRL.PWRC_IER: PWRC_IER register
func (o *SYSTEM_CTRL_Type) SetPWRC_IER_BORH_IE(value uint32) {
	volatile.StoreUint32(&o.PWRC_IER.Reg, volatile.LoadUint32(&o.PWRC_IER.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetPWRC_IER_BORH_IE() uint32 {
	return volatile.LoadUint32(&o.PWRC_IER.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetPWRC_IER_PVD_IE(value uint32) {
	volatile.StoreUint32(&o.PWRC_IER.Reg, volatile.LoadUint32(&o.PWRC_IER.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetPWRC_IER_PVD_IE() uint32 {
	return (volatile.LoadUint32(&o.PWRC_IER.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetPWRC_IER_WKUP_IE(value uint32) {
	volatile.StoreUint32(&o.PWRC_IER.Reg, volatile.LoadUint32(&o.PWRC_IER.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetPWRC_IER_WKUP_IE() uint32 {
	return (volatile.LoadUint32(&o.PWRC_IER.Reg) & 0x4) >> 2
}

// SYSTEM_CTRL.PWRC_ISCR: PWRC_ISCR register
func (o *SYSTEM_CTRL_Type) SetPWRC_ISCR_BORH_ISC(value uint32) {
	volatile.StoreUint32(&o.PWRC_ISCR.Reg, volatile.LoadUint32(&o.PWRC_ISCR.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetPWRC_ISCR_BORH_ISC() uint32 {
	return volatile.LoadUint32(&o.PWRC_ISCR.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetPWRC_ISCR_PVD_ISC(value uint32) {
	volatile.StoreUint32(&o.PWRC_ISCR.Reg, volatile.LoadUint32(&o.PWRC_ISCR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetPWRC_ISCR_PVD_ISC() uint32 {
	return (volatile.LoadUint32(&o.PWRC_ISCR.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetPWRC_ISCR_WKUP_ISC(value uint32) {
	volatile.StoreUint32(&o.PWRC_ISCR.Reg, volatile.LoadUint32(&o.PWRC_ISCR.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetPWRC_ISCR_WKUP_ISC() uint32 {
	return (volatile.LoadUint32(&o.PWRC_ISCR.Reg) & 0x4) >> 2
}

// SYSTEM_CTRL.BLERXTX_DTR: BLERXTX_DTR register
func (o *SYSTEM_CTRL_Type) SetBLERXTX_DTR_TX_DT(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_DTR.Reg, volatile.LoadUint32(&o.BLERXTX_DTR.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_DTR_TX_DT() uint32 {
	return volatile.LoadUint32(&o.BLERXTX_DTR.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetBLERXTX_DTR_RX_DT(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_DTR.Reg, volatile.LoadUint32(&o.BLERXTX_DTR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_DTR_RX_DT() uint32 {
	return (volatile.LoadUint32(&o.BLERXTX_DTR.Reg) & 0x2) >> 1
}

// SYSTEM_CTRL.BLERXTX_IBER: BLERXTX_IBER register
func (o *SYSTEM_CTRL_Type) SetBLERXTX_IBER_TX_IBE(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_IBER.Reg, volatile.LoadUint32(&o.BLERXTX_IBER.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_IBER_TX_IBE() uint32 {
	return volatile.LoadUint32(&o.BLERXTX_IBER.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetBLERXTX_IBER_RX_IBE(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_IBER.Reg, volatile.LoadUint32(&o.BLERXTX_IBER.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_IBER_RX_IBE() uint32 {
	return (volatile.LoadUint32(&o.BLERXTX_IBER.Reg) & 0x2) >> 1
}

// SYSTEM_CTRL.BLERXTX_IEVR: BLERXTX_IEVR register
func (o *SYSTEM_CTRL_Type) SetBLERXTX_IEVR_TX_IEV(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_IEVR.Reg, volatile.LoadUint32(&o.BLERXTX_IEVR.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_IEVR_TX_IEV() uint32 {
	return volatile.LoadUint32(&o.BLERXTX_IEVR.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetBLERXTX_IEVR_RX_IEV(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_IEVR.Reg, volatile.LoadUint32(&o.BLERXTX_IEVR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_IEVR_RX_IEV() uint32 {
	return (volatile.LoadUint32(&o.BLERXTX_IEVR.Reg) & 0x2) >> 1
}

// SYSTEM_CTRL.BLERXTX_IER: BLERXTX_IER register
func (o *SYSTEM_CTRL_Type) SetBLERXTX_IER_TX_IE(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_IER.Reg, volatile.LoadUint32(&o.BLERXTX_IER.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_IER_TX_IE() uint32 {
	return volatile.LoadUint32(&o.BLERXTX_IER.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetBLERXTX_IER_RX_IE(value uint32) {
	volatile.StoreUint32(&o.BLERXTX_IER.Reg, volatile.LoadUint32(&o.BLERXTX_IER.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_IER_RX_IE() uint32 {
	return (volatile.LoadUint32(&o.BLERXTX_IER.Reg) & 0x2) >> 1
}

// SYSTEM_CTRL.BLERXTX_ISCR: BLERXTX_ISCR register
func (o *SYSTEM_CTRL_Type) SetBLERXTX_ISCR_TX_ISC(value uint8) {
	volatile.StoreUint8(&o.BLERXTX_ISCR.Reg, volatile.LoadUint8(&o.BLERXTX_ISCR.Reg)&^(0x1)|value)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_ISCR_TX_ISC() uint8 {
	return volatile.LoadUint8(&o.BLERXTX_ISCR.Reg) & 0x1
}
func (o *SYSTEM_CTRL_Type) SetBLERXTX_ISCR_RX_ISC(value uint8) {
	volatile.StoreUint8(&o.BLERXTX_ISCR.Reg, volatile.LoadUint8(&o.BLERXTX_ISCR.Reg)&^(0x2)|value<<1)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_ISCR_RX_ISC() uint8 {
	return (volatile.LoadUint8(&o.BLERXTX_ISCR.Reg) & 0x2) >> 1
}
func (o *SYSTEM_CTRL_Type) SetBLERXTX_ISCR_TX_ISEDGE(value uint8) {
	volatile.StoreUint8(&o.BLERXTX_ISCR.Reg, volatile.LoadUint8(&o.BLERXTX_ISCR.Reg)&^(0x4)|value<<2)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_ISCR_TX_ISEDGE() uint8 {
	return (volatile.LoadUint8(&o.BLERXTX_ISCR.Reg) & 0x4) >> 2
}
func (o *SYSTEM_CTRL_Type) SetBLERXTX_ISCR_RX_ISEDGE(value uint8) {
	volatile.StoreUint8(&o.BLERXTX_ISCR.Reg, volatile.LoadUint8(&o.BLERXTX_ISCR.Reg)&^(0x8)|value<<3)
}
func (o *SYSTEM_CTRL_Type) GetBLERXTX_ISCR_RX_ISEDGE() uint8 {
	return (volatile.LoadUint8(&o.BLERXTX_ISCR.Reg) & 0x8) >> 3
}

// I2C address block description
type I2C_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	OAR1     volatile.Register32 // 0x8
	OAR2     volatile.Register32 // 0xC
	TIMINGR  volatile.Register32 // 0x10
	TIMEOUTR volatile.Register32 // 0x14
	ISR      volatile.Register32 // 0x18
	ICR      volatile.Register32 // 0x1C
	PECR     volatile.Register32 // 0x20
	RXDR     volatile.Register32 // 0x24
	TXDR     volatile.Register32 // 0x28
}

// I2C.CR1: I2C control register 1
func (o *I2C_Type) SetCR1_PE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetCR1_PE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *I2C_Type) SetCR1_TXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetCR1_TXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetCR1_RXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetCR1_RXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetCR1_ADDRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetCR1_ADDRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetCR1_NACKIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetCR1_NACKIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetCR1_STOPIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetCR1_STOPIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetCR1_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetCR1_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetCR1_DNF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xf00)|value<<8)
}
func (o *I2C_Type) GetCR1_DNF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xf00) >> 8
}
func (o *I2C_Type) SetCR1_ANFOFF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR1_ANFOFF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR1_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR1_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR1_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR1_RXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR1_SBC(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetCR1_SBC() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetCR1_NOSTRETCH(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetCR1_NOSTRETCH() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetCR1_WUPEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetCR1_WUPEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *I2C_Type) SetCR1_GCEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000)|value<<19)
}
func (o *I2C_Type) GetCR1_GCEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000) >> 19
}
func (o *I2C_Type) SetCR1_SMBHEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100000)|value<<20)
}
func (o *I2C_Type) GetCR1_SMBHEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100000) >> 20
}
func (o *I2C_Type) SetCR1_SMBDEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200000)|value<<21)
}
func (o *I2C_Type) GetCR1_SMBDEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200000) >> 21
}
func (o *I2C_Type) SetCR1_ALERTEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400000)|value<<22)
}
func (o *I2C_Type) GetCR1_ALERTEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400000) >> 22
}
func (o *I2C_Type) SetCR1_PECEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800000)|value<<23)
}
func (o *I2C_Type) GetCR1_PECEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800000) >> 23
}

// I2C.CR2: I2C control register 2
func (o *I2C_Type) SetCR2_SADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetCR2_SADD() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x3ff
}
func (o *I2C_Type) SetCR2_RD_WRN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetCR2_RD_WRN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetCR2_ADD10(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetCR2_ADD10() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetCR2_HEAD10R(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR2_HEAD10R() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR2_START(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetCR2_START() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR2_NACK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR2_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR2_NBYTES(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff0000)|value<<16)
}
func (o *I2C_Type) GetCR2_NBYTES() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff0000) >> 16
}
func (o *I2C_Type) SetCR2_RELOAD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000000)|value<<24)
}
func (o *I2C_Type) GetCR2_RELOAD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000000) >> 24
}
func (o *I2C_Type) SetCR2_AUTOEND(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *I2C_Type) GetCR2_AUTOEND() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *I2C_Type) SetCR2_PECBYTE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000000)|value<<26)
}
func (o *I2C_Type) GetCR2_PECBYTE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000000) >> 26
}

// I2C.OAR1: I2C own address 1 register
func (o *I2C_Type) SetOAR1_OA1(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetOAR1_OA1() uint32 {
	return volatile.LoadUint32(&o.OAR1.Reg) & 0x3ff
}
func (o *I2C_Type) SetOAR1_OA1MODE(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetOAR1_OA1MODE() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetOAR1_OA1EN(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR1_OA1EN() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x8000) >> 15
}

// I2C.OAR2: I2C own address 2 register
func (o *I2C_Type) SetOAR2_OA2(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0xfe)|value<<1)
}
func (o *I2C_Type) GetOAR2_OA2() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0xfe) >> 1
}
func (o *I2C_Type) SetOAR2_OA2MSK(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x700)|value<<8)
}
func (o *I2C_Type) GetOAR2_OA2MSK() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x700) >> 8
}
func (o *I2C_Type) SetOAR2_OA2EN(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR2_OA2EN() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x8000) >> 15
}

// I2C.TIMINGR: I2C timing register
func (o *I2C_Type) SetTIMINGR_SCLL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTIMINGR_SCLL() uint32 {
	return volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff
}
func (o *I2C_Type) SetTIMINGR_SCLH(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff00)|value<<8)
}
func (o *I2C_Type) GetTIMINGR_SCLH() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff00) >> 8
}
func (o *I2C_Type) SetTIMINGR_SDADEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000)|value<<16)
}
func (o *I2C_Type) GetTIMINGR_SDADEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000) >> 16
}
func (o *I2C_Type) SetTIMINGR_SCLDEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf00000)|value<<20)
}
func (o *I2C_Type) GetTIMINGR_SCLDEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf00000) >> 20
}
func (o *I2C_Type) SetTIMINGR_PRESC(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000000)|value<<28)
}
func (o *I2C_Type) GetTIMINGR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000000) >> 28
}

// I2C.TIMEOUTR: I2C timeout register
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTA(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff)|value)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTA() uint32 {
	return volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff
}
func (o *I2C_Type) SetTIMEOUTR_TIDLE(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetTIMEOUTR_TIDLE() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetTIMEOUTR_TIMOUTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetTIMEOUTR_TIMOUTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTB(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff0000)|value<<16)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTB() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff0000) >> 16
}
func (o *I2C_Type) SetTIMEOUTR_TEXTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetTIMEOUTR_TEXTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x80000000) >> 31
}

// I2C.ISR: I2C interrupt and status register
func (o *I2C_Type) SetISR_TXE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetISR_TXE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *I2C_Type) SetISR_TXIS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetISR_TXIS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetISR_RXNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetISR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetISR_ADDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetISR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetISR_NACKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetISR_NACKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetISR_STOPF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetISR_STOPF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetISR_TCR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetISR_TCR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetISR_BERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetISR_BERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetISR_ARLO(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetISR_ARLO() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetISR_OVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetISR_OVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetISR_PECERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetISR_PECERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetISR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetISR_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetISR_ALERT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetISR_ALERT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetISR_DIR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetISR_DIR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetISR_ADDCODE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xfe0000)|value<<17)
}
func (o *I2C_Type) GetISR_ADDCODE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xfe0000) >> 17
}

// I2C.ICR: I2C interrupt clear register
func (o *I2C_Type) SetICR_ADDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetICR_ADDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetICR_NACKCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetICR_NACKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetICR_STOPCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetICR_STOPCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetICR_BERRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetICR_BERRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetICR_ARLOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetICR_ARLOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetICR_OVRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetICR_OVRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetICR_PECCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetICR_PECCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetICR_TIMOUTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetICR_TIMOUTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetICR_ALERTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetICR_ALERTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}

// I2C.PECR: I2C PEC register
func (o *I2C_Type) SetPECR_PEC(value uint32) {
	volatile.StoreUint32(&o.PECR.Reg, volatile.LoadUint32(&o.PECR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetPECR_PEC() uint32 {
	return volatile.LoadUint32(&o.PECR.Reg) & 0xff
}

// I2C.RXDR: I2C receive data register
func (o *I2C_Type) SetRXDR_RXDATA(value uint32) {
	volatile.StoreUint32(&o.RXDR.Reg, volatile.LoadUint32(&o.RXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetRXDR_RXDATA() uint32 {
	return volatile.LoadUint32(&o.RXDR.Reg) & 0xff
}

// I2C.TXDR: I2C transmit data register
func (o *I2C_Type) SetTXDR_TXDATA(value uint32) {
	volatile.StoreUint32(&o.TXDR.Reg, volatile.LoadUint32(&o.TXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTXDR_TXDATA() uint32 {
	return volatile.LoadUint32(&o.TXDR.Reg) & 0xff
}

type RCC_Type struct {
	CR        volatile.Register32 // 0x0
	_         [4]byte
	CFGR      volatile.Register32 // 0x8
	_         [12]byte
	CIER      volatile.Register32 // 0x18
	CIFR      volatile.Register32 // 0x1C
	CSCMDR    volatile.Register32 // 0x20
	_         [12]byte
	AHBRSTR   volatile.Register32 // 0x30
	APB0RSTR  volatile.Register32 // 0x34
	APB1RSTR  volatile.Register32 // 0x38
	_         [4]byte
	APB2RSTR  volatile.Register32 // 0x40
	_         [12]byte
	AHBENR    volatile.Register32 // 0x50
	APB0ENR   volatile.Register32 // 0x54
	APB1ENR   volatile.Register32 // 0x58
	_         [4]byte
	APB2ENR   volatile.Register32 // 0x60
	_         [48]byte
	CSR       volatile.Register32 // 0x94
	RFSWHSECR volatile.Register32 // 0x98
	RFHSECR   volatile.Register32 // 0x9C
}

// RCC.CR: CR register
func (o *RCC_Type) SetCR_LSION(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCR_LSION() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCR_LSIRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCR_LSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCR_LSEON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCR_LSEON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCR_LSERDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCR_LSERDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCR_LSEBYP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCR_LSEBYP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCR_LOCKDET_NSTOP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x380)|value<<7)
}
func (o *RCC_Type) GetCR_LOCKDET_NSTOP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x380) >> 7
}
func (o *RCC_Type) SetCR_HSIRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCR_HSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetCR_HSEPLLBUFON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetCR_HSEPLLBUFON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetCR_HSIPLLON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetCR_HSIPLLON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetCR_HSIPLLRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetCR_HSIPLLRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetCR_FMRAT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetCR_FMRAT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetCR_HSEON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetCR_HSEON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetCR_HSERDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetCR_HSERDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}

// RCC.CFGR: CFGR register
func (o *RCC_Type) SetCFGR_SMPSINV(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCFGR_SMPSINV() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0x1
}
func (o *RCC_Type) SetCFGR_HSESEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCFGR_HSESEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCFGR_STOPHSI(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCFGR_STOPHSI() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCFGR_HSESEL_STATUS(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCFGR_HSESEL_STATUS() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCFGR_CLKSYSDIV(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xe0)|value<<5)
}
func (o *RCC_Type) GetCFGR_CLKSYSDIV() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xe0) >> 5
}
func (o *RCC_Type) SetCFGR_CLKSYSDIV_STATUS(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x700)|value<<8)
}
func (o *RCC_Type) GetCFGR_CLKSYSDIV_STATUS() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x700) >> 8
}
func (o *RCC_Type) SetCFGR_SMPSDIV(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetCFGR_SMPSDIV() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetCFGR_LPUCLKSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetCFGR_LPUCLKSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetCFGR_CLKSLOWSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x18000)|value<<15)
}
func (o *RCC_Type) GetCFGR_CLKSLOWSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x18000) >> 15
}
func (o *RCC_Type) SetCFGR_IOBOOSTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetCFGR_IOBOOSTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetCFGR_IOBOOSTCLKEXTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetCFGR_IOBOOSTCLKEXTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetCFGR_LCOEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetCFGR_LCOEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetCFGR_SPI3I2SCLKSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xc00000)|value<<22)
}
func (o *RCC_Type) GetCFGR_SPI3I2SCLKSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xc00000) >> 22
}
func (o *RCC_Type) SetCFGR_LCOSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x3000000)|value<<24)
}
func (o *RCC_Type) GetCFGR_LCOSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x3000000) >> 24
}
func (o *RCC_Type) SetCFGR_MCOSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1c000000)|value<<26)
}
func (o *RCC_Type) GetCFGR_MCOSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x1c000000) >> 26
}
func (o *RCC_Type) SetCFGR_CCOPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xe0000000)|value<<29)
}
func (o *RCC_Type) GetCFGR_CCOPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xe0000000) >> 29
}

// RCC.CIER: CIER register
func (o *RCC_Type) SetCIER_LSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIER_LSIRDYIE() uint32 {
	return volatile.LoadUint32(&o.CIER.Reg) & 0x1
}
func (o *RCC_Type) SetCIER_LSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIER_LSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIER_HSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIER_HSIRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIER_HSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIER_HSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIER_HSIPLLRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIER_HSIPLLRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCIER_HSIPLLUNLOCKDETIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCIER_HSIPLLUNLOCKDETIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCIER_RTCRSTIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCIER_RTCRSTIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCIER_WDGRSTIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCIER_WDGRSTIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCIER_LPURSTIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCIER_LPURSTIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x200) >> 9
}

// RCC.CIFR: CIFR register
func (o *RCC_Type) SetCIFR_LSIRDYIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIFR_LSIRDYIF() uint32 {
	return volatile.LoadUint32(&o.CIFR.Reg) & 0x1
}
func (o *RCC_Type) SetCIFR_LSERDYIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIFR_LSERDYIF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIFR_HSIRDYIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIFR_HSIRDYIF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIFR_HSERDYIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIFR_HSERDYIF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIFR_HSIPLLRDYIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIFR_HSIPLLRDYIF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCIFR_HSIPLLUNLOCKDETIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCIFR_HSIPLLUNLOCKDETIF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCIFR_RTCRSTIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCIFR_RTCRSTIF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCIFR_WDGRSTIF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCIFR_WDGRSTIF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCIFR_LPURSTF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCIFR_LPURSTF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x200) >> 9
}

// RCC.CSCMDR: CSCMDR register
func (o *RCC_Type) SetCSCMDR_REQUEST(value uint32) {
	volatile.StoreUint32(&o.CSCMDR.Reg, volatile.LoadUint32(&o.CSCMDR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCSCMDR_REQUEST() uint32 {
	return volatile.LoadUint32(&o.CSCMDR.Reg) & 0x1
}
func (o *RCC_Type) SetCSCMDR_CLKSYSDIV_REQ(value uint32) {
	volatile.StoreUint32(&o.CSCMDR.Reg, volatile.LoadUint32(&o.CSCMDR.Reg)&^(0xe)|value<<1)
}
func (o *RCC_Type) GetCSCMDR_CLKSYSDIV_REQ() uint32 {
	return (volatile.LoadUint32(&o.CSCMDR.Reg) & 0xe) >> 1
}
func (o *RCC_Type) SetCSCMDR_STATUS(value uint32) {
	volatile.StoreUint32(&o.CSCMDR.Reg, volatile.LoadUint32(&o.CSCMDR.Reg)&^(0x30)|value<<4)
}
func (o *RCC_Type) GetCSCMDR_STATUS() uint32 {
	return (volatile.LoadUint32(&o.CSCMDR.Reg) & 0x30) >> 4
}
func (o *RCC_Type) SetCSCMDR_EOFSEQ_IE(value uint32) {
	volatile.StoreUint32(&o.CSCMDR.Reg, volatile.LoadUint32(&o.CSCMDR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCSCMDR_EOFSEQ_IE() uint32 {
	return (volatile.LoadUint32(&o.CSCMDR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCSCMDR_EOFSEQ_IRQ(value uint32) {
	volatile.StoreUint32(&o.CSCMDR.Reg, volatile.LoadUint32(&o.CSCMDR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCSCMDR_EOFSEQ_IRQ() uint32 {
	return (volatile.LoadUint32(&o.CSCMDR.Reg) & 0x80) >> 7
}

// RCC.AHBRSTR: AHBRSTR register
func (o *RCC_Type) SetAHBRSTR_DMARST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHBRSTR_DMARST() uint32 {
	return volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAHBRSTR_GPIOARST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHBRSTR_GPIOARST() uint32 {
	return (volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHBRSTR_GPIOBRST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHBRSTR_GPIOBRST() uint32 {
	return (volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHBRSTR_CRCRST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHBRSTR_CRCRST() uint32 {
	return (volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHBRSTR_PKARST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHBRSTR_PKARST() uint32 {
	return (volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHBRSTR_RNGRST(value uint32) {
	volatile.StoreUint32(&o.AHBRSTR.Reg, volatile.LoadUint32(&o.AHBRSTR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHBRSTR_RNGRST() uint32 {
	return (volatile.LoadUint32(&o.AHBRSTR.Reg) & 0x40000) >> 18
}

// RCC.APB0RSTR: APB0RSTR register
func (o *RCC_Type) SetAPB0RSTR_TIM1RST(value uint32) {
	volatile.StoreUint32(&o.APB0RSTR.Reg, volatile.LoadUint32(&o.APB0RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB0RSTR_TIM1RST() uint32 {
	return volatile.LoadUint32(&o.APB0RSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAPB0RSTR_TIM16RST(value uint32) {
	volatile.StoreUint32(&o.APB0RSTR.Reg, volatile.LoadUint32(&o.APB0RSTR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB0RSTR_TIM16RST() uint32 {
	return (volatile.LoadUint32(&o.APB0RSTR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB0RSTR_TIM17RST(value uint32) {
	volatile.StoreUint32(&o.APB0RSTR.Reg, volatile.LoadUint32(&o.APB0RSTR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB0RSTR_TIM17RST() uint32 {
	return (volatile.LoadUint32(&o.APB0RSTR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB0RSTR_SYSCFGRST(value uint32) {
	volatile.StoreUint32(&o.APB0RSTR.Reg, volatile.LoadUint32(&o.APB0RSTR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAPB0RSTR_SYSCFGRST() uint32 {
	return (volatile.LoadUint32(&o.APB0RSTR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAPB0RSTR_RTCRST(value uint32) {
	volatile.StoreUint32(&o.APB0RSTR.Reg, volatile.LoadUint32(&o.APB0RSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB0RSTR_RTCRST() uint32 {
	return (volatile.LoadUint32(&o.APB0RSTR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB0RSTR_WDRST(value uint32) {
	volatile.StoreUint32(&o.APB0RSTR.Reg, volatile.LoadUint32(&o.APB0RSTR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB0RSTR_WDRST() uint32 {
	return (volatile.LoadUint32(&o.APB0RSTR.Reg) & 0x4000) >> 14
}

// RCC.APB1RSTR: APB1RSTR register
func (o *RCC_Type) SetAPB1RSTR_AUXADCRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR.Reg, volatile.LoadUint32(&o.APB1RSTR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1RSTR_AUXADCRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1RSTR_LPUARTRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR.Reg, volatile.LoadUint32(&o.APB1RSTR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAPB1RSTR_LPUARTRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAPB1RSTR_USARTRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR.Reg, volatile.LoadUint32(&o.APB1RSTR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAPB1RSTR_USARTRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAPB1RSTR_SPI3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR.Reg, volatile.LoadUint32(&o.APB1RSTR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1RSTR_SPI3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1RSTR_I2C21RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR.Reg, volatile.LoadUint32(&o.APB1RSTR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1RSTR_I2C21RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR.Reg) & 0x200000) >> 21
}

// RCC.APB2RSTR: APB2RSTR register
func (o *RCC_Type) SetAPB2RSTR_BLERST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB2RSTR_BLERST() uint32 {
	return volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x1
}

// RCC.AHBENR: AHBENR register
func (o *RCC_Type) SetAHBENR_DMAEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHBENR_DMAEN() uint32 {
	return volatile.LoadUint32(&o.AHBENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHBENR_GPIOAEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHBENR_GPIOAEN() uint32 {
	return (volatile.LoadUint32(&o.AHBENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHBENR_GPIOBEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHBENR_GPIOBEN() uint32 {
	return (volatile.LoadUint32(&o.AHBENR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHBENR_CRCEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHBENR_CRCEN() uint32 {
	return (volatile.LoadUint32(&o.AHBENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHBENR_PKAEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHBENR_PKAEN() uint32 {
	return (volatile.LoadUint32(&o.AHBENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHBENR_RNGEN(value uint32) {
	volatile.StoreUint32(&o.AHBENR.Reg, volatile.LoadUint32(&o.AHBENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHBENR_RNGEN() uint32 {
	return (volatile.LoadUint32(&o.AHBENR.Reg) & 0x40000) >> 18
}

// RCC.APB0ENR: APB0ENR register
func (o *RCC_Type) SetAPB0ENR_TIM2EN(value uint32) {
	volatile.StoreUint32(&o.APB0ENR.Reg, volatile.LoadUint32(&o.APB0ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB0ENR_TIM2EN() uint32 {
	return volatile.LoadUint32(&o.APB0ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAPB0ENR_TIM16EN(value uint32) {
	volatile.StoreUint32(&o.APB0ENR.Reg, volatile.LoadUint32(&o.APB0ENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB0ENR_TIM16EN() uint32 {
	return (volatile.LoadUint32(&o.APB0ENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB0ENR_TIM17EN(value uint32) {
	volatile.StoreUint32(&o.APB0ENR.Reg, volatile.LoadUint32(&o.APB0ENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB0ENR_TIM17EN() uint32 {
	return (volatile.LoadUint32(&o.APB0ENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB0ENR_SYSCFGEN(value uint32) {
	volatile.StoreUint32(&o.APB0ENR.Reg, volatile.LoadUint32(&o.APB0ENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAPB0ENR_SYSCFGEN() uint32 {
	return (volatile.LoadUint32(&o.APB0ENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAPB0ENR_RTCEN(value uint32) {
	volatile.StoreUint32(&o.APB0ENR.Reg, volatile.LoadUint32(&o.APB0ENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB0ENR_RTCEN() uint32 {
	return (volatile.LoadUint32(&o.APB0ENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB0ENR_WDGEN(value uint32) {
	volatile.StoreUint32(&o.APB0ENR.Reg, volatile.LoadUint32(&o.APB0ENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB0ENR_WDGEN() uint32 {
	return (volatile.LoadUint32(&o.APB0ENR.Reg) & 0x4000) >> 14
}

// RCC.APB1ENR: APB1ENR register
func (o *RCC_Type) SetAPB1ENR_ADCDIGEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR.Reg, volatile.LoadUint32(&o.APB1ENR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1ENR_ADCDIGEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1ENR_ADCANAEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR.Reg, volatile.LoadUint32(&o.APB1ENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1ENR_ADCANAEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1ENR_LPUARTEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR.Reg, volatile.LoadUint32(&o.APB1ENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAPB1ENR_LPUARTEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAPB1ENR_USART1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR.Reg, volatile.LoadUint32(&o.APB1ENR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAPB1ENR_USART1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAPB1ENR_SPI3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR.Reg, volatile.LoadUint32(&o.APB1ENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1ENR_SPI3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1ENR_I2C1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR.Reg, volatile.LoadUint32(&o.APB1ENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1ENR_I2C1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR.Reg) & 0x200000) >> 21
}

// RCC.APB2ENR: APB2ENR register
func (o *RCC_Type) SetAPB2ENR_MRBLEEN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB2ENR_MRBLEEN() uint32 {
	return volatile.LoadUint32(&o.APB2ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAPB2ENR_CLKBLEDIV(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB2ENR_CLKBLEDIV() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x4) >> 2
}

// RCC.CSR: CSR register
func (o *RCC_Type) SetCSR_RMVF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetCSR_RMVF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetCSR_PADRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetCSR_PADRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetCSR_PORRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetCSR_PORRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetCSR_SFTRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetCSR_SFTRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetCSR_WDGRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetCSR_WDGRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetCSR_LOCKUPRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetCSR_LOCKUPRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40000000) >> 30
}

// RCC.RFSWHSECR: RFSWHSECR register
func (o *RCC_Type) SetRFSWHSECR_SATRG(value uint32) {
	volatile.StoreUint32(&o.RFSWHSECR.Reg, volatile.LoadUint32(&o.RFSWHSECR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetRFSWHSECR_SATRG() uint32 {
	return (volatile.LoadUint32(&o.RFSWHSECR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetRFSWHSECR_GMC(value uint32) {
	volatile.StoreUint32(&o.RFSWHSECR.Reg, volatile.LoadUint32(&o.RFSWHSECR.Reg)&^(0x70)|value<<4)
}
func (o *RCC_Type) GetRFSWHSECR_GMC() uint32 {
	return (volatile.LoadUint32(&o.RFSWHSECR.Reg) & 0x70) >> 4
}
func (o *RCC_Type) SetRFSWHSECR_SWXOTUNEEN(value uint32) {
	volatile.StoreUint32(&o.RFSWHSECR.Reg, volatile.LoadUint32(&o.RFSWHSECR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetRFSWHSECR_SWXOTUNEEN() uint32 {
	return (volatile.LoadUint32(&o.RFSWHSECR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetRFSWHSECR_SWXOTUNE(value uint32) {
	volatile.StoreUint32(&o.RFSWHSECR.Reg, volatile.LoadUint32(&o.RFSWHSECR.Reg)&^(0x3f00)|value<<8)
}
func (o *RCC_Type) GetRFSWHSECR_SWXOTUNE() uint32 {
	return (volatile.LoadUint32(&o.RFSWHSECR.Reg) & 0x3f00) >> 8
}

// RCC.RFHSECR: RFHSECR register
func (o *RCC_Type) SetRFHSECR_XOTUNE(value uint32) {
	volatile.StoreUint32(&o.RFHSECR.Reg, volatile.LoadUint32(&o.RFHSECR.Reg)&^(0x3f)|value)
}
func (o *RCC_Type) GetRFHSECR_XOTUNE() uint32 {
	return volatile.LoadUint32(&o.RFHSECR.Reg) & 0x3f
}

// SPI address block description
type SPI_Type struct {
	CR1     volatile.Register16 // 0x0
	_       [2]byte
	CR2     volatile.Register16 // 0x4
	_       [2]byte
	SR      volatile.Register16 // 0x8
	_       [2]byte
	DR      volatile.Register16 // 0xC
	_       [2]byte
	CRCPR   volatile.Register16 // 0x10
	_       [2]byte
	RXCRCR  volatile.Register16 // 0x14
	_       [2]byte
	TXCRCR  volatile.Register16 // 0x18
	_       [2]byte
	I2SCFGR volatile.Register16 // 0x1C
	_       [2]byte
	I2SPR   volatile.Register16 // 0x20
}

// SPI.CR1: SPI control register 1
func (o *SPI_Type) SetCR1_CPHA(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR1_CPHA() uint16 {
	return volatile.LoadUint16(&o.CR1.Reg) & 0x1
}
func (o *SPI_Type) SetCR1_CPOL(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCR1_CPOL() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCR1_MSTR(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetCR1_MSTR() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetCR1_BR(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x38)|value<<3)
}
func (o *SPI_Type) GetCR1_BR() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x38) >> 3
}
func (o *SPI_Type) SetCR1_SPE(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetCR1_SPE() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetCR1_LSBFIRST(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetCR1_LSBFIRST() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetCR1_SSI(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetCR1_SSI() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetCR1_SSM(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetCR1_SSM() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetCR1_RXONLY(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetCR1_RXONLY() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x400) >> 10
}
func (o *SPI_Type) SetCR1_CRCL(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetCR1_CRCL() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetCR1_CRCNEXT(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetCR1_CRCNEXT() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetCR1_CRCEN(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCR1_CRCEN() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCR1_BIDIOE(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCR1_BIDIOE() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *SPI_Type) SetCR1_BIDIMODE(value uint16) {
	volatile.StoreUint16(&o.CR1.Reg, volatile.LoadUint16(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *SPI_Type) GetCR1_BIDIMODE() uint16 {
	return (volatile.LoadUint16(&o.CR1.Reg) & 0x8000) >> 15
}

// SPI.CR2: SPI control register 2
func (o *SPI_Type) SetCR2_RXDMAEN(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR2_RXDMAEN() uint16 {
	return volatile.LoadUint16(&o.CR2.Reg) & 0x1
}
func (o *SPI_Type) SetCR2_TXDMAEN(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCR2_TXDMAEN() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCR2_SSOE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetCR2_SSOE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetCR2_NSSP(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetCR2_NSSP() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetCR2_FRF(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetCR2_FRF() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetCR2_ERRIE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetCR2_ERRIE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetCR2_RXNEIE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetCR2_RXNEIE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetCR2_TXEIE(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetCR2_TXEIE() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetCR2_DS(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0xf00)|value<<8)
}
func (o *SPI_Type) GetCR2_DS() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0xf00) >> 8
}
func (o *SPI_Type) SetCR2_FRXTH(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetCR2_FRXTH() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetCR2_LDMA_RX(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCR2_LDMA_RX() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCR2_LDMA_TX(value uint16) {
	volatile.StoreUint16(&o.CR2.Reg, volatile.LoadUint16(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCR2_LDMA_TX() uint16 {
	return (volatile.LoadUint16(&o.CR2.Reg) & 0x4000) >> 14
}

// SPI.SR: SPI status register
func (o *SPI_Type) SetSR_RXNE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetSR_RXNE() uint16 {
	return volatile.LoadUint16(&o.SR.Reg) & 0x1
}
func (o *SPI_Type) SetSR_TXE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetSR_TXE() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetSR_CHSIDE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetSR_CHSIDE() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetSR_UDR(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetSR_UDR() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetSR_CRCERR(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetSR_CRCERR() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetSR_MODF(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetSR_MODF() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetSR_OVR(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetSR_OVR() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetSR_BSY(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetSR_BSY() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetSR_FRE(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetSR_FRE() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetSR_FRLVL(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x600)|value<<9)
}
func (o *SPI_Type) GetSR_FRLVL() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x600) >> 9
}
func (o *SPI_Type) SetSR_FTLVL(value uint16) {
	volatile.StoreUint16(&o.SR.Reg, volatile.LoadUint16(&o.SR.Reg)&^(0x1800)|value<<11)
}
func (o *SPI_Type) GetSR_FTLVL() uint16 {
	return (volatile.LoadUint16(&o.SR.Reg) & 0x1800) >> 11
}

// SPI.DR: SPI data register
func (o *SPI_Type) SetDR(value uint16) {
	volatile.StoreUint16(&o.DR.Reg, value)
}
func (o *SPI_Type) GetDR() uint16 {
	return volatile.LoadUint16(&o.DR.Reg)
}

// SPI.CRCPR: SPI CRC polynomial register
func (o *SPI_Type) SetCRCPR(value uint16) {
	volatile.StoreUint16(&o.CRCPR.Reg, value)
}
func (o *SPI_Type) GetCRCPR() uint16 {
	return volatile.LoadUint16(&o.CRCPR.Reg)
}

// SPI.RXCRCR: SPI Rx CRC register
func (o *SPI_Type) SetRXCRCR(value uint16) {
	volatile.StoreUint16(&o.RXCRCR.Reg, value)
}
func (o *SPI_Type) GetRXCRCR() uint16 {
	return volatile.LoadUint16(&o.RXCRCR.Reg)
}

// SPI.TXCRCR: SPI Tx CRC register
func (o *SPI_Type) SetTXCRCR(value uint16) {
	volatile.StoreUint16(&o.TXCRCR.Reg, value)
}
func (o *SPI_Type) GetTXCRCR() uint16 {
	return volatile.LoadUint16(&o.TXCRCR.Reg)
}

// SPI.I2SCFGR: SPIx_I2S configuration register
func (o *SPI_Type) SetI2SCFGR_CHLEN(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetI2SCFGR_CHLEN() uint16 {
	return volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x1
}
func (o *SPI_Type) SetI2SCFGR_DATLEN(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x6)|value<<1)
}
func (o *SPI_Type) GetI2SCFGR_DATLEN() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x6) >> 1
}
func (o *SPI_Type) SetI2SCFGR_CKPOL(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetI2SCFGR_CKPOL() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetI2SCFGR_I2SSTD(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x30)|value<<4)
}
func (o *SPI_Type) GetI2SCFGR_I2SSTD() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x30) >> 4
}
func (o *SPI_Type) SetI2SCFGR_PCMSYNC(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetI2SCFGR_PCMSYNC() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetI2SCFGR_I2SCFG(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x300)|value<<8)
}
func (o *SPI_Type) GetI2SCFGR_I2SCFG() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x300) >> 8
}
func (o *SPI_Type) SetI2SCFGR_I2SE(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetI2SCFGR_I2SE() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x400) >> 10
}
func (o *SPI_Type) SetI2SCFGR_I2SMOD(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetI2SCFGR_I2SMOD() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetI2SCFGR_ASTRTEN(value uint16) {
	volatile.StoreUint16(&o.I2SCFGR.Reg, volatile.LoadUint16(&o.I2SCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetI2SCFGR_ASTRTEN() uint16 {
	return (volatile.LoadUint16(&o.I2SCFGR.Reg) & 0x1000) >> 12
}

// SPI.I2SPR: SPIx_I2S prescaler register
func (o *SPI_Type) SetI2SPR_I2SDIV(value uint16) {
	volatile.StoreUint16(&o.I2SPR.Reg, volatile.LoadUint16(&o.I2SPR.Reg)&^(0xff)|value)
}
func (o *SPI_Type) GetI2SPR_I2SDIV() uint16 {
	return volatile.LoadUint16(&o.I2SPR.Reg) & 0xff
}
func (o *SPI_Type) SetI2SPR_ODD(value uint16) {
	volatile.StoreUint16(&o.I2SPR.Reg, volatile.LoadUint16(&o.I2SPR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetI2SPR_ODD() uint16 {
	return (volatile.LoadUint16(&o.I2SPR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetI2SPR_MCKOE(value uint16) {
	volatile.StoreUint16(&o.I2SPR.Reg, volatile.LoadUint16(&o.I2SPR.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetI2SPR_MCKOE() uint16 {
	return (volatile.LoadUint16(&o.I2SPR.Reg) & 0x200) >> 9
}

type TIM_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	SMCR         volatile.Register32 // 0x8
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	CCMR2_Output volatile.Register32 // 0x1C
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	CCR2         volatile.Register32 // 0x38
	CCR3         volatile.Register32 // 0x3C
	CCR4         volatile.Register32 // 0x40
	_            [4]byte
	DCR          volatile.Register32 // 0x48
	DMAR         volatile.Register32 // 0x4C
	_            [24]byte
	TISEL        volatile.Register32 // 0x68
}

// TIM.CR1: CR1 register
func (o *TIM_Type) SetCR1_CEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetCR1_CEN() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *TIM_Type) SetCR1_UDIS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetCR1_UDIS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetCR1_URS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetCR1_URS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetCR1_OPM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR1_OPM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR1_DIR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCR1_DIR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCR1_CMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x60)|value<<5)
}
func (o *TIM_Type) GetCR1_CMS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x60) >> 5
}
func (o *TIM_Type) SetCR1_ARPE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR1_ARPE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCR1_CKD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCR1_CKD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCR1_UIF_REMAP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCR1_UIF_REMAP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}

// TIM.CR2: CR2 register
func (o *TIM_Type) SetCR2_CCDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR2_CCDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR2_MMS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetCR2_MMS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetCR2_TI1S(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR2_TI1S() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}

// TIM.SMCR: SMCR register
func (o *TIM_Type) SetSMCR_SMS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x7)|value)
}
func (o *TIM_Type) GetSMCR_SMS() uint32 {
	return volatile.LoadUint32(&o.SMCR.Reg) & 0x7
}
func (o *TIM_Type) SetSMCR_OCCS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetSMCR_OCCS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetSMCR_TS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetSMCR_TS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetSMCR_MSM(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetSMCR_MSM() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetSMCR_ETF(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0xf00)|value<<8)
}
func (o *TIM_Type) GetSMCR_ETF() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0xf00) >> 8
}
func (o *TIM_Type) SetSMCR_ETPS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x3000)|value<<12)
}
func (o *TIM_Type) GetSMCR_ETPS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x3000) >> 12
}
func (o *TIM_Type) SetSMCR_ECE(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetSMCR_ECE() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetSMCR_ETP(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetSMCR_ETP() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetSMCR_SMS_3(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetSMCR_SMS_3() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetSMCR_TS2(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x300000)|value<<20)
}
func (o *TIM_Type) GetSMCR_TS2() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x300000) >> 20
}

// TIM.DIER: DIER register
func (o *TIM_Type) SetDIER_UIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetDIER_UIE() uint32 {
	return volatile.LoadUint32(&o.DIER.Reg) & 0x1
}
func (o *TIM_Type) SetDIER_CC1IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetDIER_CC1IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetDIER_CC2IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetDIER_CC2IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetDIER_CC3IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetDIER_CC3IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetDIER_CC4IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetDIER_CC4IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetDIER_TIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetDIER_TIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetDIER_UDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetDIER_UDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetDIER_CC1DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetDIER_CC1DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetDIER_CC2DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetDIER_CC2DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetDIER_CC3DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetDIER_CC3DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetDIER_CC4DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetDIER_CC4DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetDIER_TDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetDIER_TDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4000) >> 14
}

// TIM.SR: SR register
func (o *TIM_Type) SetSR_UIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetSR_UIF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *TIM_Type) SetSR_CC1IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetSR_CC1IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetSR_CC2IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetSR_CC2IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetSR_CC3IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetSR_CC3IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetSR_CC4IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetSR_CC4IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetSR_TIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetSR_TIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetSR_CC1OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetSR_CC1OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetSR_CC2OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetSR_CC2OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetSR_CC3OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetSR_CC3OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetSR_CC4OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetSR_CC4OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}

// TIM.EGR: EGR register
func (o *TIM_Type) SetEGR_UG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetEGR_UG() uint32 {
	return volatile.LoadUint32(&o.EGR.Reg) & 0x1
}
func (o *TIM_Type) SetEGR_CC1G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetEGR_CC1G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetEGR_CC2G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetEGR_CC2G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetEGR_CC3G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetEGR_CC3G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetEGR_CC4G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetEGR_CC4G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetEGR_TG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetEGR_TG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x40) >> 6
}

// TIM.CCMR1_Output: CCMR1 register
func (o *TIM_Type) SetCCMR1_Output_CC1S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR1_Output_CC1S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR1_Output_CC2S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR1_Output_CC2S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x30000) >> 16
}
func (o *TIM_Type) SetCCMR1_Output_OC1FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR1_Output_OC1FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR1_Output_OC2FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR1_Output_OC2FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR1_Output_OC1PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR1_Output_OC1PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR1_Output_OC2PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR1_Output_OC2PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR1_Output_OC1M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR1_Output_OC2M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR1_Output_OC1CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR1_Output_OC1CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR1_Output_OC2CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR1_Output_OC2CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR1_Output_OC1M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR1_Output_OC2M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x0) >> 32
}

// TIM.CCMR2_Output: CCMR2 register
func (o *TIM_Type) SetCCMR2_Output_CC3S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR2_Output_CC3S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR2_Output_CC4S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR2_Output_CC4S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x30000) >> 16
}
func (o *TIM_Type) SetCCMR2_Output_OC3FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR2_Output_OC3FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR2_Output_OC4FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR2_Output_OC4FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR2_Output_OC3PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR2_Output_OC3PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR2_Output_OC4PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR2_Output_OC4PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR2_Output_OC3M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR2_Output_OC4M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR2_Output_OC3CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR2_Output_OC3CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR2_Output_OC4CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR2_Output_OC4CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR2_Output_OC3M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR2_Output_OC4M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x0) >> 32
}

// TIM.CCER: CCER register
func (o *TIM_Type) SetCCER_CC1E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCCER_CC1E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCCER_CC2E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetCCER_CC2E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetCCER_CC3E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCCER_CC3E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCCER_CC4E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetCCER_CC4E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetCCER_CC1P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetCCER_CC1P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetCCER_CC2P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetCCER_CC2P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetCCER_CC3P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetCCER_CC3P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetCCER_CC4P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetCCER_CC4P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20000) >> 17
}
func (o *TIM_Type) SetCCER_CC1NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCCER_CC1NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCCER_CC2NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCER_CC2NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCER_CC3NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCER_CC3NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCER_CC4NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCER_CC4NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80000) >> 19
}

// TIM.CNT: CNT register
func (o *TIM_Type) SetCNT(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCNT() uint32 {
	return volatile.LoadUint32(&o.CNT.Reg) & 0xffff
}
func (o *TIM_Type) SetCNT_UIF_CPY(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0x80000000)|value<<31)
}
func (o *TIM_Type) GetCNT_UIF_CPY() uint32 {
	return (volatile.LoadUint32(&o.CNT.Reg) & 0x80000000) >> 31
}

// TIM.PSC: PSC register
func (o *TIM_Type) SetPSC(value uint32) {
	volatile.StoreUint32(&o.PSC.Reg, volatile.LoadUint32(&o.PSC.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetPSC() uint32 {
	return volatile.LoadUint32(&o.PSC.Reg) & 0xffff
}

// TIM.ARR: ARR register
func (o *TIM_Type) SetARR(value uint32) {
	volatile.StoreUint32(&o.ARR.Reg, volatile.LoadUint32(&o.ARR.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetARR() uint32 {
	return volatile.LoadUint32(&o.ARR.Reg) & 0xffff
}

// TIM.RCR: RCR register
func (o *TIM_Type) SetRCR_REP(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xff)|value)
}
func (o *TIM_Type) GetRCR_REP() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xff
}

// TIM.CCR1: capture/compare register
func (o *TIM_Type) SetCCR1_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR1_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0xffff
}

// TIM.CCR2: capture/compare register
func (o *TIM_Type) SetCCR2_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR2_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0xffff
}

// TIM.CCR3: capture/compare register
func (o *TIM_Type) SetCCR3_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR3_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR3.Reg) & 0xffff
}

// TIM.CCR4: capture/compare register
func (o *TIM_Type) SetCCR4_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR4_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR4.Reg) & 0xffff
}

// TIM.DCR: DCR register
func (o *TIM_Type) SetDCR_DBA(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f)|value)
}
func (o *TIM_Type) GetDCR_DBA() uint32 {
	return volatile.LoadUint32(&o.DCR.Reg) & 0x1f
}
func (o *TIM_Type) SetDCR_DBL(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f00)|value<<8)
}
func (o *TIM_Type) GetDCR_DBL() uint32 {
	return (volatile.LoadUint32(&o.DCR.Reg) & 0x1f00) >> 8
}

// TIM.DMAR: DMAR register
func (o *TIM_Type) SetDMAR_DMAB(value uint32) {
	volatile.StoreUint32(&o.DMAR.Reg, volatile.LoadUint32(&o.DMAR.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetDMAR_DMAB() uint32 {
	return volatile.LoadUint32(&o.DMAR.Reg) & 0xffff
}

// TIM.TISEL: TISEL register
func (o *TIM_Type) SetTISEL_TI1SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf)|value)
}
func (o *TIM_Type) GetTISEL_TI1SEL() uint32 {
	return volatile.LoadUint32(&o.TISEL.Reg) & 0xf
}
func (o *TIM_Type) SetTISEL_TI2SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf00)|value<<8)
}
func (o *TIM_Type) GetTISEL_TI2SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf00) >> 8
}
func (o *TIM_Type) SetTISEL_TI3SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf0000)|value<<16)
}
func (o *TIM_Type) GetTISEL_TI3SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf0000) >> 16
}
func (o *TIM_Type) SetTISEL_TI4SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf000000)|value<<24)
}
func (o *TIM_Type) GetTISEL_TI4SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf000000) >> 24
}

type USART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// USART.CR1: CR1 register
func (o *USART_Type) SetCR1_UE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR1_UE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *USART_Type) SetCR1_RE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR1_RE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR1_TE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR1_TE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR1_IDLEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR1_IDLEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR1_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR1_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR1_TXEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR1_TXEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR1_PEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR1_PEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR1_PS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR1_PS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR1_PCE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR1_PCE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR1_WAKE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR1_WAKE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR1_M0(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR1_M0() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR1_MME(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR1_MME() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR1_CMIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR1_CMIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR1_OVER8(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR1_OVER8() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR1_DEDT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *USART_Type) GetCR1_DEDT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1f0000) >> 16
}
func (o *USART_Type) SetCR1_DEAT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x3e00000)|value<<21)
}
func (o *USART_Type) GetCR1_DEAT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x3e00000) >> 21
}
func (o *USART_Type) SetCR1_RTOIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetCR1_RTOIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetCR1_EOBIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetCR1_EOBIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000000) >> 27
}
func (o *USART_Type) SetCR1_M1(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR1_M1() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR1_FIFOEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000000)|value<<29)
}
func (o *USART_Type) GetCR1_FIFOEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000000) >> 29
}
func (o *USART_Type) SetCR1_TXFEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *USART_Type) GetCR1_TXFEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *USART_Type) SetCR1_RXFFIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000000)|value<<31)
}
func (o *USART_Type) GetCR1_RXFFIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000000) >> 31
}

// USART.CR2: CR2 register
func (o *USART_Type) SetCR2_SLVEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR2_SLVEN() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *USART_Type) SetCR2_DIS_NSS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR2_DIS_NSS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR2_ADDM7(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR2_ADDM7() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR2_LBDL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR2_LBDL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR2_LBDIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR2_LBDIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR2_LBCL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR2_LBCL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR2_CPHA(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR2_CPHA() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR2_CPOL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR2_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR2_CLKEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR2_CLKEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3000)|value<<12)
}
func (o *USART_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x3000) >> 12
}
func (o *USART_Type) SetCR2_LINEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR2_LINEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR2_SWAP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR2_SWAP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR2_RXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetCR2_RXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetCR2_TXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetCR2_TXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetCR2_DATAINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetCR2_DATAINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetCR2_MSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetCR2_MSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetCR2_ABREN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetCR2_ABREN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetCR2_ABRMOD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x600000)|value<<21)
}
func (o *USART_Type) GetCR2_ABRMOD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x600000) >> 21
}
func (o *USART_Type) SetCR2_RTOEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR2_RTOEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR2_ADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetCR2_ADD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff000000) >> 24
}

// USART.CR3: CR3 register
func (o *USART_Type) SetCR3_EIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR3_EIE() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *USART_Type) SetCR3_IREN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCR3_IREN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCR3_IRLP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR3_IRLP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR3_HDSEL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR3_HDSEL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR3_NACK(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR3_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR3_SCEN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR3_SCEN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR3_DMAR(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR3_DMAR() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR3_DMAT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR3_DMAT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR3_RTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR3_RTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR3_CTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR3_CTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR3_CTSIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR3_CTSIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR3_ONEBIT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR3_ONEBIT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR3_OVRDIS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR3_OVRDIS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR3_DDRE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR3_DDRE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR3_DEM(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR3_DEM() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR3_DEP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR3_DEP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR3_SCARCNT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000)|value<<17)
}
func (o *USART_Type) GetCR3_SCARCNT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000) >> 17
}
func (o *USART_Type) SetCR3_TXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR3_TXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR3_TCBGTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetCR3_TCBGTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetCR3_RXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe000000)|value<<25)
}
func (o *USART_Type) GetCR3_RXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe000000) >> 25
}
func (o *USART_Type) SetCR3_RXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR3_RXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR3_TXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000000)|value<<29)
}
func (o *USART_Type) GetCR3_TXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000000) >> 29
}

// USART.BRR: BRR register
func (o *USART_Type) SetBRR(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetBRR() uint32 {
	return volatile.LoadUint32(&o.BRR.Reg) & 0xffff
}

// USART.GTPR: GTPR register
func (o *USART_Type) SetGTPR_PSC(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetGTPR_PSC() uint32 {
	return volatile.LoadUint32(&o.GTPR.Reg) & 0xff
}
func (o *USART_Type) SetGTPR_GT(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff00)|value<<8)
}
func (o *USART_Type) GetGTPR_GT() uint32 {
	return (volatile.LoadUint32(&o.GTPR.Reg) & 0xff00) >> 8
}

// USART.RTOR: RTOR register
func (o *USART_Type) SetRTOR_RTO(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xffffff)|value)
}
func (o *USART_Type) GetRTOR_RTO() uint32 {
	return volatile.LoadUint32(&o.RTOR.Reg) & 0xffffff
}
func (o *USART_Type) SetRTOR_BLEN(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetRTOR_BLEN() uint32 {
	return (volatile.LoadUint32(&o.RTOR.Reg) & 0xff000000) >> 24
}

// USART.RQR: RQR register
func (o *USART_Type) SetRQR_ABRRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetRQR_ABRRQ() uint32 {
	return volatile.LoadUint32(&o.RQR.Reg) & 0x1
}
func (o *USART_Type) SetRQR_SBKRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetRQR_SBKRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetRQR_MMRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetRQR_MMRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetRQR_RXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetRQR_RXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetRQR_TXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetRQR_TXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x10) >> 4
}

// USART.ISR: ISR register
func (o *USART_Type) SetISR_PE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetISR_PE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *USART_Type) SetISR_FE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetISR_FE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetISR_NF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetISR_NF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetISR_ORE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetISR_ORE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetISR_IDLE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetISR_IDLE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetISR_RXNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetISR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetISR_TXE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetISR_TXE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetISR_LBDF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetISR_LBDF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetISR_CTSIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetISR_CTSIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetISR_CTS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetISR_CTS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetISR_RTOF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetISR_RTOF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetISR_EOBF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetISR_EOBF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetISR_UDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetISR_UDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetISR_ABRE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetISR_ABRE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetISR_ABRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetISR_ABRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetISR_CMF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetISR_CMF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetISR_SBKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetISR_SBKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetISR_RWU(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetISR_RWU() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetISR_TEACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *USART_Type) GetISR_TEACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *USART_Type) SetISR_REACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *USART_Type) GetISR_REACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *USART_Type) SetISR_TXFE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetISR_TXFE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetISR_RXFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetISR_RXFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetISR_TCBGT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *USART_Type) GetISR_TCBGT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *USART_Type) SetISR_RXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetISR_RXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetISR_TXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetISR_TXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}

// USART.ICR: ICR register
func (o *USART_Type) SetICR_PECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetICR_PECF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *USART_Type) SetICR_FECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetICR_FECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetICR_NECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetICR_NECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetICR_ORECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetICR_ORECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetICR_IDLECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetICR_IDLECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetICR_TXFECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetICR_TXFECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetICR_TCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetICR_TCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetICR_TCBGTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetICR_TCBGTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetICR_LBDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetICR_LBDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetICR_CTSCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetICR_CTSCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetICR_RTOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetICR_RTOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetICR_EOBCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetICR_EOBCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetICR_UDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetICR_UDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetICR_CMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetICR_CMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20000) >> 17
}

// USART.RDR: RDR register
func (o *USART_Type) SetRDR(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetRDR() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg) & 0x1ff
}

// USART.TDR: TDR register
func (o *USART_Type) SetTDR(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetTDR() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg) & 0x1ff
}

// USART.PRESC: PRESC register
func (o *USART_Type) SetPRESC_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.PRESC.Reg, volatile.LoadUint32(&o.PRESC.Reg)&^(0xf)|value)
}
func (o *USART_Type) GetPRESC_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.PRESC.Reg) & 0xf
}

type BLUE_Type struct {
	_                    [4]byte
	INTERRUPT1REG        volatile.Register32 // 0x4
	INTERRUPT2REG        volatile.Register32 // 0x8
	TIMEOUTDESTREG       volatile.Register32 // 0xC
	TIMEOUTREG           volatile.Register32 // 0x10
	TIMERCAPTUREREG      volatile.Register32 // 0x14
	CMDREG               volatile.Register32 // 0x18
	STATUSREG            volatile.Register32 // 0x1C
	INTERRUPT1ENABLEREG  volatile.Register32 // 0x20
	INTERRUPT1LATENCYREG volatile.Register32 // 0x24
	MANAESKEY0REG        volatile.Register32 // 0x28
	MANAESKEY1REG        volatile.Register32 // 0x2C
	MANAESKEY2REG        volatile.Register32 // 0x30
	MANAESKEY3REG        volatile.Register32 // 0x34
	MANAESCLEARTEXT0REG  volatile.Register32 // 0x38
	MANAESCLEARTEXT1REG  volatile.Register32 // 0x3C
	MANAESCLEARTEXT2REG  volatile.Register32 // 0x40
	MANAESCLEARTEXT3REG  volatile.Register32 // 0x44
	MANAESCIPHERTEXT0REG volatile.Register32 // 0x48
	MANAESCIPHERTEXT1REG volatile.Register32 // 0x4C
	MANAESCIPHERTEXT2REG volatile.Register32 // 0x50
	MANAESCIPHERTEXT3REG volatile.Register32 // 0x54
	MANAESCMDREG         volatile.Register32 // 0x58
	MANAESSTATREG        volatile.Register32 // 0x5C
	AESLEPRIVPOINTERREG  volatile.Register32 // 0x60
	AESLEPRIVHASHREG     volatile.Register32 // 0x64
	AESLEPRIVPRANDREG    volatile.Register32 // 0x68
	AESLEPRIVCMDREG      volatile.Register32 // 0x6C
	AESLEPRIVSTATREG     volatile.Register32 // 0x70
	_                    [8]byte
	STATUS2REG           volatile.Register32 // 0x7C
}

// BLUE.INTERRUPT1REG: INTERRUPT1REG register
func (o *BLUE_Type) SetINTERRUPT1REG_ADDPOINTERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x10)|value<<4)
}
func (o *BLUE_Type) GetINTERRUPT1REG_ADDPOINTERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x10) >> 4
}
func (o *BLUE_Type) SetINTERRUPT1REG_RXOVERFLOWERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x20)|value<<5)
}
func (o *BLUE_Type) GetINTERRUPT1REG_RXOVERFLOWERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x20) >> 5
}
func (o *BLUE_Type) SetINTERRUPT1REG_SEQDONE(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x80)|value<<7)
}
func (o *BLUE_Type) GetINTERRUPT1REG_SEQDONE() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x80) >> 7
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXERROR_0(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x100)|value<<8)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXERROR_0() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x100) >> 8
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXERROR_1(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x200)|value<<9)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXERROR_1() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x200) >> 9
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXERROR_2(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x400)|value<<10)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXERROR_2() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x400) >> 10
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXERROR_3(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x800)|value<<11)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXERROR_3() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x800) >> 11
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXERROR_4(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x1000)|value<<12)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXERROR_4() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x1000) >> 12
}
func (o *BLUE_Type) SetINTERRUPT1REG_ENCERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x2000)|value<<13)
}
func (o *BLUE_Type) GetINTERRUPT1REG_ENCERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x2000) >> 13
}
func (o *BLUE_Type) SetINTERRUPT1REG_ALLTABLEREADYERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x4000)|value<<14)
}
func (o *BLUE_Type) GetINTERRUPT1REG_ALLTABLEREADYERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x4000) >> 14
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXDATAREADYERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x8000)|value<<15)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXDATAREADYERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x8000) >> 15
}
func (o *BLUE_Type) SetINTERRUPT1REG_NOACTIVELERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x10000)|value<<16)
}
func (o *BLUE_Type) GetINTERRUPT1REG_NOACTIVELERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x10000) >> 16
}
func (o *BLUE_Type) SetINTERRUPT1REG_RCVLENGTHERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x40000)|value<<18)
}
func (o *BLUE_Type) GetINTERRUPT1REG_RCVLENGTHERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x40000) >> 18
}
func (o *BLUE_Type) SetINTERRUPT1REG_SEMATIMEOUTERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x80000)|value<<19)
}
func (o *BLUE_Type) GetINTERRUPT1REG_SEMATIMEOUTERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x80000) >> 19
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXRXSKIP(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x200000)|value<<21)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXRXSKIP() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x200000) >> 21
}
func (o *BLUE_Type) SetINTERRUPT1REG_ACTIVE2ERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x400000)|value<<22)
}
func (o *BLUE_Type) GetINTERRUPT1REG_ACTIVE2ERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x400000) >> 22
}
func (o *BLUE_Type) SetINTERRUPT1REG_CONFIGERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x800000)|value<<23)
}
func (o *BLUE_Type) GetINTERRUPT1REG_CONFIGERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x800000) >> 23
}
func (o *BLUE_Type) SetINTERRUPT1REG_TXOK(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x1000000)|value<<24)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TXOK() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x1000000) >> 24
}
func (o *BLUE_Type) SetINTERRUPT1REG_DONE(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x2000000)|value<<25)
}
func (o *BLUE_Type) GetINTERRUPT1REG_DONE() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x2000000) >> 25
}
func (o *BLUE_Type) SetINTERRUPT1REG_RCVTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x4000000)|value<<26)
}
func (o *BLUE_Type) GetINTERRUPT1REG_RCVTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x4000000) >> 26
}
func (o *BLUE_Type) SetINTERRUPT1REG_RCVNOMD(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x8000000)|value<<27)
}
func (o *BLUE_Type) GetINTERRUPT1REG_RCVNOMD() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x8000000) >> 27
}
func (o *BLUE_Type) SetINTERRUPT1REG_RCVCMD(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x10000000)|value<<28)
}
func (o *BLUE_Type) GetINTERRUPT1REG_RCVCMD() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x10000000) >> 28
}
func (o *BLUE_Type) SetINTERRUPT1REG_TIMECAPTURETRIG(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x20000000)|value<<29)
}
func (o *BLUE_Type) GetINTERRUPT1REG_TIMECAPTURETRIG() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x20000000) >> 29
}
func (o *BLUE_Type) SetINTERRUPT1REG_RCVCRCERR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x40000000)|value<<30)
}
func (o *BLUE_Type) GetINTERRUPT1REG_RCVCRCERR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x40000000) >> 30
}
func (o *BLUE_Type) SetINTERRUPT1REG_RCVOK(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1REG.Reg, volatile.LoadUint32(&o.INTERRUPT1REG.Reg)&^(0x80000000)|value<<31)
}
func (o *BLUE_Type) GetINTERRUPT1REG_RCVOK() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1REG.Reg) & 0x80000000) >> 31
}

// BLUE.INTERRUPT2REG: INTERRUPT2REG register
func (o *BLUE_Type) SetINTERRUPT2REG_AESMANENCINT(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT2REG.Reg, volatile.LoadUint32(&o.INTERRUPT2REG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetINTERRUPT2REG_AESMANENCINT() uint32 {
	return volatile.LoadUint32(&o.INTERRUPT2REG.Reg) & 0x1
}
func (o *BLUE_Type) SetINTERRUPT2REG_AESLEPRIVINT(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT2REG.Reg, volatile.LoadUint32(&o.INTERRUPT2REG.Reg)&^(0x2)|value<<1)
}
func (o *BLUE_Type) GetINTERRUPT2REG_AESLEPRIVINT() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT2REG.Reg) & 0x2) >> 1
}

// BLUE.TIMEOUTDESTREG: TIMEOUTDESTREG register
func (o *BLUE_Type) SetTIMEOUTDESTREG_DESTINATION(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTDESTREG.Reg, volatile.LoadUint32(&o.TIMEOUTDESTREG.Reg)&^(0x3)|value)
}
func (o *BLUE_Type) GetTIMEOUTDESTREG_DESTINATION() uint32 {
	return volatile.LoadUint32(&o.TIMEOUTDESTREG.Reg) & 0x3
}

// BLUE.TIMEOUTREG: TIMEOUTREG register
func (o *BLUE_Type) SetTIMEOUTREG(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTREG.Reg, value)
}
func (o *BLUE_Type) GetTIMEOUTREG() uint32 {
	return volatile.LoadUint32(&o.TIMEOUTREG.Reg)
}

// BLUE.TIMERCAPTUREREG: TIMERCAPTUREREG register
func (o *BLUE_Type) SetTIMERCAPTUREREG(value uint32) {
	volatile.StoreUint32(&o.TIMERCAPTUREREG.Reg, value)
}
func (o *BLUE_Type) GetTIMERCAPTUREREG() uint32 {
	return volatile.LoadUint32(&o.TIMERCAPTUREREG.Reg)
}

// BLUE.CMDREG: CMDREG register
func (o *BLUE_Type) SetCMDREG_TXRXSKIP(value uint32) {
	volatile.StoreUint32(&o.CMDREG.Reg, volatile.LoadUint32(&o.CMDREG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetCMDREG_TXRXSKIP() uint32 {
	return volatile.LoadUint32(&o.CMDREG.Reg) & 0x1
}
func (o *BLUE_Type) SetCMDREG_CLEARSEMAREQ(value uint32) {
	volatile.StoreUint32(&o.CMDREG.Reg, volatile.LoadUint32(&o.CMDREG.Reg)&^(0x8)|value<<3)
}
func (o *BLUE_Type) GetCMDREG_CLEARSEMAREQ() uint32 {
	return (volatile.LoadUint32(&o.CMDREG.Reg) & 0x8) >> 3
}

// BLUE.STATUSREG: STATUSREG register
func (o *BLUE_Type) SetSTATUSREG_AESONFLYBUSY(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetSTATUSREG_AESONFLYBUSY() uint32 {
	return volatile.LoadUint32(&o.STATUSREG.Reg) & 0x1
}
func (o *BLUE_Type) SetSTATUSREG_NOTSUPPORTED_FUNCTION(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x8)|value<<3)
}
func (o *BLUE_Type) GetSTATUSREG_NOTSUPPORTED_FUNCTION() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x8) >> 3
}
func (o *BLUE_Type) SetSTATUSREG_ADDPOINTERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x10)|value<<4)
}
func (o *BLUE_Type) GetSTATUSREG_ADDPOINTERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x10) >> 4
}
func (o *BLUE_Type) SetSTATUSREG_RXOVERFLOWERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x20)|value<<5)
}
func (o *BLUE_Type) GetSTATUSREG_RXOVERFLOWERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x20) >> 5
}
func (o *BLUE_Type) SetSTATUSREG_PREVTRANSMIT(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x40)|value<<6)
}
func (o *BLUE_Type) GetSTATUSREG_PREVTRANSMIT() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x40) >> 6
}
func (o *BLUE_Type) SetSTATUSREG_SEQDONE(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x80)|value<<7)
}
func (o *BLUE_Type) GetSTATUSREG_SEQDONE() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x80) >> 7
}
func (o *BLUE_Type) SetSTATUSREG_TXERROR_0(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x100)|value<<8)
}
func (o *BLUE_Type) GetSTATUSREG_TXERROR_0() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x100) >> 8
}
func (o *BLUE_Type) SetSTATUSREG_TXERROR_1(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x200)|value<<9)
}
func (o *BLUE_Type) GetSTATUSREG_TXERROR_1() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x200) >> 9
}
func (o *BLUE_Type) SetSTATUSREG_TXERROR_2(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x400)|value<<10)
}
func (o *BLUE_Type) GetSTATUSREG_TXERROR_2() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x400) >> 10
}
func (o *BLUE_Type) SetSTATUSREG_TXERROR_3(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x800)|value<<11)
}
func (o *BLUE_Type) GetSTATUSREG_TXERROR_3() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x800) >> 11
}
func (o *BLUE_Type) SetSTATUSREG_TXERROR_4(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x1000)|value<<12)
}
func (o *BLUE_Type) GetSTATUSREG_TXERROR_4() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x1000) >> 12
}
func (o *BLUE_Type) SetSTATUSREG_ENCERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x2000)|value<<13)
}
func (o *BLUE_Type) GetSTATUSREG_ENCERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x2000) >> 13
}
func (o *BLUE_Type) SetSTATUSREG_ALLTABLEREADYERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x4000)|value<<14)
}
func (o *BLUE_Type) GetSTATUSREG_ALLTABLEREADYERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x4000) >> 14
}
func (o *BLUE_Type) SetSTATUSREG_TXDATAREADYERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x8000)|value<<15)
}
func (o *BLUE_Type) GetSTATUSREG_TXDATAREADYERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x8000) >> 15
}
func (o *BLUE_Type) SetSTATUSREG_NOACTIVELERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x10000)|value<<16)
}
func (o *BLUE_Type) GetSTATUSREG_NOACTIVELERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x10000) >> 16
}
func (o *BLUE_Type) SetSTATUSREG_RCVLENGTHERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x40000)|value<<18)
}
func (o *BLUE_Type) GetSTATUSREG_RCVLENGTHERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x40000) >> 18
}
func (o *BLUE_Type) SetSTATUSREG_SEMATIMEOUTERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x80000)|value<<19)
}
func (o *BLUE_Type) GetSTATUSREG_SEMATIMEOUTERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x80000) >> 19
}
func (o *BLUE_Type) SetSTATUSREG_TXRXSKIP(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x200000)|value<<21)
}
func (o *BLUE_Type) GetSTATUSREG_TXRXSKIP() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x200000) >> 21
}
func (o *BLUE_Type) SetSTATUSREG_ACTIVE2ERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x400000)|value<<22)
}
func (o *BLUE_Type) GetSTATUSREG_ACTIVE2ERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x400000) >> 22
}
func (o *BLUE_Type) SetSTATUSREG_CONFIGERROR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x800000)|value<<23)
}
func (o *BLUE_Type) GetSTATUSREG_CONFIGERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x800000) >> 23
}
func (o *BLUE_Type) SetSTATUSREG_TXOK(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x1000000)|value<<24)
}
func (o *BLUE_Type) GetSTATUSREG_TXOK() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x1000000) >> 24
}
func (o *BLUE_Type) SetSTATUSREG_DONE(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x2000000)|value<<25)
}
func (o *BLUE_Type) GetSTATUSREG_DONE() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x2000000) >> 25
}
func (o *BLUE_Type) SetSTATUSREG_RCVTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x4000000)|value<<26)
}
func (o *BLUE_Type) GetSTATUSREG_RCVTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x4000000) >> 26
}
func (o *BLUE_Type) SetSTATUSREG_RCVNOMD(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x8000000)|value<<27)
}
func (o *BLUE_Type) GetSTATUSREG_RCVNOMD() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x8000000) >> 27
}
func (o *BLUE_Type) SetSTATUSREG_RCVCMD(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x10000000)|value<<28)
}
func (o *BLUE_Type) GetSTATUSREG_RCVCMD() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x10000000) >> 28
}
func (o *BLUE_Type) SetSTATUSREG_TIMECAPTURETRIG(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x20000000)|value<<29)
}
func (o *BLUE_Type) GetSTATUSREG_TIMECAPTURETRIG() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x20000000) >> 29
}
func (o *BLUE_Type) SetSTATUSREG_RCVCRCERR(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x40000000)|value<<30)
}
func (o *BLUE_Type) GetSTATUSREG_RCVCRCERR() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x40000000) >> 30
}
func (o *BLUE_Type) SetSTATUSREG_RCVOK(value uint32) {
	volatile.StoreUint32(&o.STATUSREG.Reg, volatile.LoadUint32(&o.STATUSREG.Reg)&^(0x80000000)|value<<31)
}
func (o *BLUE_Type) GetSTATUSREG_RCVOK() uint32 {
	return (volatile.LoadUint32(&o.STATUSREG.Reg) & 0x80000000) >> 31
}

// BLUE.INTERRUPT1ENABLEREG: INTERRUPT1ENABLEREG register
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_ADDPOINTERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x10)|value<<4)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_ADDPOINTERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x10) >> 4
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_RXOVERFLOWERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x20)|value<<5)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_RXOVERFLOWERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x20) >> 5
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_SEQDONE(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x80)|value<<7)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_SEQDONE() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x80) >> 7
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXERROR_0(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x100)|value<<8)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXERROR_0() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x100) >> 8
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXERROR_1(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x200)|value<<9)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXERROR_1() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x200) >> 9
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXERROR_2(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x400)|value<<10)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXERROR_2() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x400) >> 10
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXERROR_3(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x800)|value<<11)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXERROR_3() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x800) >> 11
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXERROR_4(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x1000)|value<<12)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXERROR_4() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x1000) >> 12
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_ENCERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x2000)|value<<13)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_ENCERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x2000) >> 13
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_ALLTABLEREADYERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x4000)|value<<14)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_ALLTABLEREADYERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x4000) >> 14
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXDATAREADYERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x8000)|value<<15)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXDATAREADYERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x8000) >> 15
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_NOACTIVELERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x10000)|value<<16)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_NOACTIVELERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x10000) >> 16
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_RCVLENGTHERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x40000)|value<<18)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_RCVLENGTHERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x40000) >> 18
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_SEMATIMEOUTERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x80000)|value<<19)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_SEMATIMEOUTERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x80000) >> 19
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXRXSKIP(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x200000)|value<<21)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXRXSKIP() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x200000) >> 21
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_ACTIVE2ERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x400000)|value<<22)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_ACTIVE2ERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x400000) >> 22
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_CONFIGERROR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x800000)|value<<23)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_CONFIGERROR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x800000) >> 23
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TXOK(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x1000000)|value<<24)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TXOK() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x1000000) >> 24
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_DONE(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x2000000)|value<<25)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_DONE() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x2000000) >> 25
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_RCVTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x4000000)|value<<26)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_RCVTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x4000000) >> 26
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_RCVNOMD(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x8000000)|value<<27)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_RCVNOMD() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x8000000) >> 27
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_RCVCMD(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x10000000)|value<<28)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_RCVCMD() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x10000000) >> 28
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_TIMECAPTURETRIG(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x20000000)|value<<29)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_TIMECAPTURETRIG() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x20000000) >> 29
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_RCVCRCERR(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x40000000)|value<<30)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_RCVCRCERR() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x40000000) >> 30
}
func (o *BLUE_Type) SetINTERRUPT1ENABLEREG_RCVOK(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1ENABLEREG.Reg, volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg)&^(0x80000000)|value<<31)
}
func (o *BLUE_Type) GetINTERRUPT1ENABLEREG_RCVOK() uint32 {
	return (volatile.LoadUint32(&o.INTERRUPT1ENABLEREG.Reg) & 0x80000000) >> 31
}

// BLUE.INTERRUPT1LATENCYREG: INTERRUPT1LATENCYREG register
func (o *BLUE_Type) SetINTERRUPT1LATENCYREG_INTERRUPT1LATENCY(value uint32) {
	volatile.StoreUint32(&o.INTERRUPT1LATENCYREG.Reg, volatile.LoadUint32(&o.INTERRUPT1LATENCYREG.Reg)&^(0xff)|value)
}
func (o *BLUE_Type) GetINTERRUPT1LATENCYREG_INTERRUPT1LATENCY() uint32 {
	return volatile.LoadUint32(&o.INTERRUPT1LATENCYREG.Reg) & 0xff
}

// BLUE.MANAESKEY0REG: MANAESKEY0REG register
func (o *BLUE_Type) SetMANAESKEY0REG(value uint32) {
	volatile.StoreUint32(&o.MANAESKEY0REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESKEY0REG() uint32 {
	return volatile.LoadUint32(&o.MANAESKEY0REG.Reg)
}

// BLUE.MANAESKEY1REG: MANAESKEY1REG register
func (o *BLUE_Type) SetMANAESKEY1REG(value uint32) {
	volatile.StoreUint32(&o.MANAESKEY1REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESKEY1REG() uint32 {
	return volatile.LoadUint32(&o.MANAESKEY1REG.Reg)
}

// BLUE.MANAESKEY2REG: MANAESKEY2REG register
func (o *BLUE_Type) SetMANAESKEY2REG(value uint32) {
	volatile.StoreUint32(&o.MANAESKEY2REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESKEY2REG() uint32 {
	return volatile.LoadUint32(&o.MANAESKEY2REG.Reg)
}

// BLUE.MANAESKEY3REG: MANAESKEY3REG register
func (o *BLUE_Type) SetMANAESKEY3REG(value uint32) {
	volatile.StoreUint32(&o.MANAESKEY3REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESKEY3REG() uint32 {
	return volatile.LoadUint32(&o.MANAESKEY3REG.Reg)
}

// BLUE.MANAESCLEARTEXT0REG: MANAESCLEARTEXT0REG register
func (o *BLUE_Type) SetMANAESCLEARTEXT0REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCLEARTEXT0REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCLEARTEXT0REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCLEARTEXT0REG.Reg)
}

// BLUE.MANAESCLEARTEXT1REG: MANAESCLEARTEXT1REG register
func (o *BLUE_Type) SetMANAESCLEARTEXT1REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCLEARTEXT1REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCLEARTEXT1REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCLEARTEXT1REG.Reg)
}

// BLUE.MANAESCLEARTEXT2REG: MANAESCLEARTEXT2REG register
func (o *BLUE_Type) SetMANAESCLEARTEXT2REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCLEARTEXT2REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCLEARTEXT2REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCLEARTEXT2REG.Reg)
}

// BLUE.MANAESCLEARTEXT3REG: MANAESCLEARTEXT3REG register
func (o *BLUE_Type) SetMANAESCLEARTEXT3REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCLEARTEXT3REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCLEARTEXT3REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCLEARTEXT3REG.Reg)
}

// BLUE.MANAESCIPHERTEXT0REG: MANAESCIPHERTEXT0REG register
func (o *BLUE_Type) SetMANAESCIPHERTEXT0REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCIPHERTEXT0REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCIPHERTEXT0REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCIPHERTEXT0REG.Reg)
}

// BLUE.MANAESCIPHERTEXT1REG: MANAESCIPHERTEXT1REG register
func (o *BLUE_Type) SetMANAESCIPHERTEXT1REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCIPHERTEXT1REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCIPHERTEXT1REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCIPHERTEXT1REG.Reg)
}

// BLUE.MANAESCIPHERTEXT2REG: MANAESCIPHERTEXT2REG register
func (o *BLUE_Type) SetMANAESCIPHERTEXT2REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCIPHERTEXT2REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCIPHERTEXT2REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCIPHERTEXT2REG.Reg)
}

// BLUE.MANAESCIPHERTEXT3REG: MANAESCIPHERTEXT3REG register
func (o *BLUE_Type) SetMANAESCIPHERTEXT3REG(value uint32) {
	volatile.StoreUint32(&o.MANAESCIPHERTEXT3REG.Reg, value)
}
func (o *BLUE_Type) GetMANAESCIPHERTEXT3REG() uint32 {
	return volatile.LoadUint32(&o.MANAESCIPHERTEXT3REG.Reg)
}

// BLUE.MANAESCMDREG: MANAESCMDREG register
func (o *BLUE_Type) SetMANAESCMDREG_START(value uint32) {
	volatile.StoreUint32(&o.MANAESCMDREG.Reg, volatile.LoadUint32(&o.MANAESCMDREG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetMANAESCMDREG_START() uint32 {
	return volatile.LoadUint32(&o.MANAESCMDREG.Reg) & 0x1
}
func (o *BLUE_Type) SetMANAESCMDREG_INTENA(value uint32) {
	volatile.StoreUint32(&o.MANAESCMDREG.Reg, volatile.LoadUint32(&o.MANAESCMDREG.Reg)&^(0x2)|value<<1)
}
func (o *BLUE_Type) GetMANAESCMDREG_INTENA() uint32 {
	return (volatile.LoadUint32(&o.MANAESCMDREG.Reg) & 0x2) >> 1
}

// BLUE.MANAESSTATREG: MANAESSTATREG register
func (o *BLUE_Type) SetMANAESSTATREG_BUSY(value uint32) {
	volatile.StoreUint32(&o.MANAESSTATREG.Reg, volatile.LoadUint32(&o.MANAESSTATREG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetMANAESSTATREG_BUSY() uint32 {
	return volatile.LoadUint32(&o.MANAESSTATREG.Reg) & 0x1
}

// BLUE.AESLEPRIVPOINTERREG: AESLEPRIVPOINTERREG register
func (o *BLUE_Type) SetAESLEPRIVPOINTERREG_POINTER(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVPOINTERREG.Reg, volatile.LoadUint32(&o.AESLEPRIVPOINTERREG.Reg)&^(0xffffff)|value)
}
func (o *BLUE_Type) GetAESLEPRIVPOINTERREG_POINTER() uint32 {
	return volatile.LoadUint32(&o.AESLEPRIVPOINTERREG.Reg) & 0xffffff
}

// BLUE.AESLEPRIVHASHREG: AESLEPRIVHASHREG register
func (o *BLUE_Type) SetAESLEPRIVHASHREG_HASH(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVHASHREG.Reg, volatile.LoadUint32(&o.AESLEPRIVHASHREG.Reg)&^(0xffffff)|value)
}
func (o *BLUE_Type) GetAESLEPRIVHASHREG_HASH() uint32 {
	return volatile.LoadUint32(&o.AESLEPRIVHASHREG.Reg) & 0xffffff
}

// BLUE.AESLEPRIVPRANDREG: AESLEPRIVPRANDREG register
func (o *BLUE_Type) SetAESLEPRIVPRANDREG_PRAND(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVPRANDREG.Reg, volatile.LoadUint32(&o.AESLEPRIVPRANDREG.Reg)&^(0xffffff)|value)
}
func (o *BLUE_Type) GetAESLEPRIVPRANDREG_PRAND() uint32 {
	return volatile.LoadUint32(&o.AESLEPRIVPRANDREG.Reg) & 0xffffff
}

// BLUE.AESLEPRIVCMDREG: AESLEPRIVCMDREG register
func (o *BLUE_Type) SetAESLEPRIVCMDREG_START(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVCMDREG.Reg, volatile.LoadUint32(&o.AESLEPRIVCMDREG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetAESLEPRIVCMDREG_START() uint32 {
	return volatile.LoadUint32(&o.AESLEPRIVCMDREG.Reg) & 0x1
}
func (o *BLUE_Type) SetAESLEPRIVCMDREG_INTENA(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVCMDREG.Reg, volatile.LoadUint32(&o.AESLEPRIVCMDREG.Reg)&^(0x2)|value<<1)
}
func (o *BLUE_Type) GetAESLEPRIVCMDREG_INTENA() uint32 {
	return (volatile.LoadUint32(&o.AESLEPRIVCMDREG.Reg) & 0x2) >> 1
}
func (o *BLUE_Type) SetAESLEPRIVCMDREG_NBKEYS(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVCMDREG.Reg, volatile.LoadUint32(&o.AESLEPRIVCMDREG.Reg)&^(0x3fc)|value<<2)
}
func (o *BLUE_Type) GetAESLEPRIVCMDREG_NBKEYS() uint32 {
	return (volatile.LoadUint32(&o.AESLEPRIVCMDREG.Reg) & 0x3fc) >> 2
}

// BLUE.AESLEPRIVSTATREG: AESLEPRIVSTATREG register
func (o *BLUE_Type) SetAESLEPRIVSTATREG_BUSY(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVSTATREG.Reg, volatile.LoadUint32(&o.AESLEPRIVSTATREG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetAESLEPRIVSTATREG_BUSY() uint32 {
	return volatile.LoadUint32(&o.AESLEPRIVSTATREG.Reg) & 0x1
}
func (o *BLUE_Type) SetAESLEPRIVSTATREG_KEYFND(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVSTATREG.Reg, volatile.LoadUint32(&o.AESLEPRIVSTATREG.Reg)&^(0x2)|value<<1)
}
func (o *BLUE_Type) GetAESLEPRIVSTATREG_KEYFND() uint32 {
	return (volatile.LoadUint32(&o.AESLEPRIVSTATREG.Reg) & 0x2) >> 1
}
func (o *BLUE_Type) SetAESLEPRIVSTATREG_KEYFNDINDEX(value uint32) {
	volatile.StoreUint32(&o.AESLEPRIVSTATREG.Reg, volatile.LoadUint32(&o.AESLEPRIVSTATREG.Reg)&^(0x3fc)|value<<2)
}
func (o *BLUE_Type) GetAESLEPRIVSTATREG_KEYFNDINDEX() uint32 {
	return (volatile.LoadUint32(&o.AESLEPRIVSTATREG.Reg) & 0x3fc) >> 2
}

// BLUE.STATUS2REG: STATUS2REG register
func (o *BLUE_Type) SetSTATUS2REG_IQSAMPLESREADY(value uint32) {
	volatile.StoreUint32(&o.STATUS2REG.Reg, volatile.LoadUint32(&o.STATUS2REG.Reg)&^(0x1)|value)
}
func (o *BLUE_Type) GetSTATUS2REG_IQSAMPLESREADY() uint32 {
	return volatile.LoadUint32(&o.STATUS2REG.Reg) & 0x1
}
func (o *BLUE_Type) SetSTATUS2REG_IQSAMPLESNUMBER(value uint32) {
	volatile.StoreUint32(&o.STATUS2REG.Reg, volatile.LoadUint32(&o.STATUS2REG.Reg)&^(0xfe)|value<<1)
}
func (o *BLUE_Type) GetSTATUS2REG_IQSAMPLESNUMBER() uint32 {
	return (volatile.LoadUint32(&o.STATUS2REG.Reg) & 0xfe) >> 1
}
func (o *BLUE_Type) SetSTATUS2REG_IQSAMPLESMISSINGERROR(value uint32) {
	volatile.StoreUint32(&o.STATUS2REG.Reg, volatile.LoadUint32(&o.STATUS2REG.Reg)&^(0x20000000)|value<<29)
}
func (o *BLUE_Type) GetSTATUS2REG_IQSAMPLESMISSINGERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUS2REG.Reg) & 0x20000000) >> 29
}
func (o *BLUE_Type) SetSTATUS2REG_ANTENNASWITCHINGPATTERNACCESSERROR(value uint32) {
	volatile.StoreUint32(&o.STATUS2REG.Reg, volatile.LoadUint32(&o.STATUS2REG.Reg)&^(0x40000000)|value<<30)
}
func (o *BLUE_Type) GetSTATUS2REG_ANTENNASWITCHINGPATTERNACCESSERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUS2REG.Reg) & 0x40000000) >> 30
}
func (o *BLUE_Type) SetSTATUS2REG_ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR(value uint32) {
	volatile.StoreUint32(&o.STATUS2REG.Reg, volatile.LoadUint32(&o.STATUS2REG.Reg)&^(0x80000000)|value<<31)
}
func (o *BLUE_Type) GetSTATUS2REG_ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR() uint32 {
	return (volatile.LoadUint32(&o.STATUS2REG.Reg) & 0x80000000) >> 31
}

type GLOBALSTATMACH_Type struct {
	WORD0 volatile.Register32 // 0x0
	WORD1 volatile.Register32 // 0x4
	WORD2 volatile.Register32 // 0x8
	WORD3 volatile.Register32 // 0xC
	WORD4 volatile.Register32 // 0x10
	WORD5 volatile.Register32 // 0x14
	WORD6 volatile.Register32 // 0x18
}

// GLOBALSTATMACH.WORD0: WORD0 register
func (o *GLOBALSTATMACH_Type) SetWORD0(value uint32) {
	volatile.StoreUint32(&o.WORD0.Reg, value)
}
func (o *GLOBALSTATMACH_Type) GetWORD0() uint32 {
	return volatile.LoadUint32(&o.WORD0.Reg)
}

// GLOBALSTATMACH.WORD1: WORD1 register
func (o *GLOBALSTATMACH_Type) SetWORD1_CurStMachNum(value uint32) {
	volatile.StoreUint32(&o.WORD1.Reg, volatile.LoadUint32(&o.WORD1.Reg)&^(0x7f)|value)
}
func (o *GLOBALSTATMACH_Type) GetWORD1_CurStMachNum() uint32 {
	return volatile.LoadUint32(&o.WORD1.Reg) & 0x7f
}
func (o *GLOBALSTATMACH_Type) SetWORD1_Active(value uint32) {
	volatile.StoreUint32(&o.WORD1.Reg, volatile.LoadUint32(&o.WORD1.Reg)&^(0x80)|value<<7)
}
func (o *GLOBALSTATMACH_Type) GetWORD1_Active() uint32 {
	return (volatile.LoadUint32(&o.WORD1.Reg) & 0x80) >> 7
}
func (o *GLOBALSTATMACH_Type) SetWORD1_WakeupInitDelay(value uint32) {
	volatile.StoreUint32(&o.WORD1.Reg, volatile.LoadUint32(&o.WORD1.Reg)&^(0xff00)|value<<8)
}
func (o *GLOBALSTATMACH_Type) GetWORD1_WakeupInitDelay() uint32 {
	return (volatile.LoadUint32(&o.WORD1.Reg) & 0xff00) >> 8
}
func (o *GLOBALSTATMACH_Type) SetWORD1_Timer12InitDelayCal(value uint32) {
	volatile.StoreUint32(&o.WORD1.Reg, volatile.LoadUint32(&o.WORD1.Reg)&^(0xff0000)|value<<16)
}
func (o *GLOBALSTATMACH_Type) GetWORD1_Timer12InitDelayCal() uint32 {
	return (volatile.LoadUint32(&o.WORD1.Reg) & 0xff0000) >> 16
}
func (o *GLOBALSTATMACH_Type) SetWORD1_Timer2InitDelayNoCal(value uint32) {
	volatile.StoreUint32(&o.WORD1.Reg, volatile.LoadUint32(&o.WORD1.Reg)&^(0xff000000)|value<<24)
}
func (o *GLOBALSTATMACH_Type) GetWORD1_Timer2InitDelayNoCal() uint32 {
	return (volatile.LoadUint32(&o.WORD1.Reg) & 0xff000000) >> 24
}

// GLOBALSTATMACH.WORD2: WORD2 register
func (o *GLOBALSTATMACH_Type) SetWORD2_TransmitCalDelayChk(value uint32) {
	volatile.StoreUint32(&o.WORD2.Reg, volatile.LoadUint32(&o.WORD2.Reg)&^(0xff)|value)
}
func (o *GLOBALSTATMACH_Type) GetWORD2_TransmitCalDelayChk() uint32 {
	return volatile.LoadUint32(&o.WORD2.Reg) & 0xff
}
func (o *GLOBALSTATMACH_Type) SetWORD2_TransmitNoCalDelayChk(value uint32) {
	volatile.StoreUint32(&o.WORD2.Reg, volatile.LoadUint32(&o.WORD2.Reg)&^(0xff00)|value<<8)
}
func (o *GLOBALSTATMACH_Type) GetWORD2_TransmitNoCalDelayChk() uint32 {
	return (volatile.LoadUint32(&o.WORD2.Reg) & 0xff00) >> 8
}
func (o *GLOBALSTATMACH_Type) SetWORD2_ReceiveCalDelayChk(value uint32) {
	volatile.StoreUint32(&o.WORD2.Reg, volatile.LoadUint32(&o.WORD2.Reg)&^(0xff0000)|value<<16)
}
func (o *GLOBALSTATMACH_Type) GetWORD2_ReceiveCalDelayChk() uint32 {
	return (volatile.LoadUint32(&o.WORD2.Reg) & 0xff0000) >> 16
}
func (o *GLOBALSTATMACH_Type) SetWORD2_ReceiveNoCalDelayChk(value uint32) {
	volatile.StoreUint32(&o.WORD2.Reg, volatile.LoadUint32(&o.WORD2.Reg)&^(0xff000000)|value<<24)
}
func (o *GLOBALSTATMACH_Type) GetWORD2_ReceiveNoCalDelayChk() uint32 {
	return (volatile.LoadUint32(&o.WORD2.Reg) & 0xff000000) >> 24
}

// GLOBALSTATMACH.WORD3: WORD3 register
func (o *GLOBALSTATMACH_Type) SetWORD3_ConfigEndDuration(value uint32) {
	volatile.StoreUint32(&o.WORD3.Reg, volatile.LoadUint32(&o.WORD3.Reg)&^(0xff)|value)
}
func (o *GLOBALSTATMACH_Type) GetWORD3_ConfigEndDuration() uint32 {
	return volatile.LoadUint32(&o.WORD3.Reg) & 0xff
}
func (o *GLOBALSTATMACH_Type) SetWORD3_TxdataReadyCheck(value uint32) {
	volatile.StoreUint32(&o.WORD3.Reg, volatile.LoadUint32(&o.WORD3.Reg)&^(0xff00)|value<<8)
}
func (o *GLOBALSTATMACH_Type) GetWORD3_TxdataReadyCheck() uint32 {
	return (volatile.LoadUint32(&o.WORD3.Reg) & 0xff00) >> 8
}
func (o *GLOBALSTATMACH_Type) SetWORD3_TxdelayStart(value uint32) {
	volatile.StoreUint32(&o.WORD3.Reg, volatile.LoadUint32(&o.WORD3.Reg)&^(0xff0000)|value<<16)
}
func (o *GLOBALSTATMACH_Type) GetWORD3_TxdelayStart() uint32 {
	return (volatile.LoadUint32(&o.WORD3.Reg) & 0xff0000) >> 16
}
func (o *GLOBALSTATMACH_Type) SetWORD3_TxdelayEnd(value uint32) {
	volatile.StoreUint32(&o.WORD3.Reg, volatile.LoadUint32(&o.WORD3.Reg)&^(0x3f000000)|value<<24)
}
func (o *GLOBALSTATMACH_Type) GetWORD3_TxdelayEnd() uint32 {
	return (volatile.LoadUint32(&o.WORD3.Reg) & 0x3f000000) >> 24
}
func (o *GLOBALSTATMACH_Type) SetWORD3_TimeCaptureSel(value uint32) {
	volatile.StoreUint32(&o.WORD3.Reg, volatile.LoadUint32(&o.WORD3.Reg)&^(0x40000000)|value<<30)
}
func (o *GLOBALSTATMACH_Type) GetWORD3_TimeCaptureSel() uint32 {
	return (volatile.LoadUint32(&o.WORD3.Reg) & 0x40000000) >> 30
}
func (o *GLOBALSTATMACH_Type) SetWORD3_TimeCapture(value uint32) {
	volatile.StoreUint32(&o.WORD3.Reg, volatile.LoadUint32(&o.WORD3.Reg)&^(0x80000000)|value<<31)
}
func (o *GLOBALSTATMACH_Type) GetWORD3_TimeCapture() uint32 {
	return (volatile.LoadUint32(&o.WORD3.Reg) & 0x80000000) >> 31
}

// GLOBALSTATMACH.WORD4: WORD4 register
func (o *GLOBALSTATMACH_Type) SetWORD4_TxReadyTimeout(value uint32) {
	volatile.StoreUint32(&o.WORD4.Reg, volatile.LoadUint32(&o.WORD4.Reg)&^(0xff)|value)
}
func (o *GLOBALSTATMACH_Type) GetWORD4_TxReadyTimeout() uint32 {
	return volatile.LoadUint32(&o.WORD4.Reg) & 0xff
}
func (o *GLOBALSTATMACH_Type) SetWORD4_RcvTimeout(value uint32) {
	volatile.StoreUint32(&o.WORD4.Reg, volatile.LoadUint32(&o.WORD4.Reg)&^(0xfffff00)|value<<8)
}
func (o *GLOBALSTATMACH_Type) GetWORD4_RcvTimeout() uint32 {
	return (volatile.LoadUint32(&o.WORD4.Reg) & 0xfffff00) >> 8
}

// GLOBALSTATMACH.WORD5: WORD5 register
func (o *GLOBALSTATMACH_Type) SetWORD5_AutoTxRxskipEn(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x1)|value)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_AutoTxRxskipEn() uint32 {
	return volatile.LoadUint32(&o.WORD5.Reg) & 0x1
}
func (o *GLOBALSTATMACH_Type) SetWORD5_ChkFlagAutoClearEna(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x4)|value<<2)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_ChkFlagAutoClearEna() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x4) >> 2
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntAddPointError(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x100000)|value<<20)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntAddPointError() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x100000) >> 20
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntAllTableReadyError(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x200000)|value<<21)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntAllTableReadyError() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x200000) >> 21
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntTxDataReadyError(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x400000)|value<<22)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntTxDataReadyError() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x400000) >> 22
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntNoActiveLError(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x800000)|value<<23)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntNoActiveLError() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x800000) >> 23
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntRcvLengthError(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x2000000)|value<<25)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntRcvLengthError() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x2000000) >> 25
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntSemaTimeoutError(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x4000000)|value<<26)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntSemaTimeoutError() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x4000000) >> 26
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntSeqDone(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x10000000)|value<<28)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntSeqDone() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x10000000) >> 28
}
func (o *GLOBALSTATMACH_Type) SetWORD5_INTTXRXSKIP(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x20000000)|value<<29)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_INTTXRXSKIP() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x20000000) >> 29
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntActive2Err(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x40000000)|value<<30)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntActive2Err() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x40000000) >> 30
}
func (o *GLOBALSTATMACH_Type) SetWORD5_IntConfigError(value uint32) {
	volatile.StoreUint32(&o.WORD5.Reg, volatile.LoadUint32(&o.WORD5.Reg)&^(0x80000000)|value<<31)
}
func (o *GLOBALSTATMACH_Type) GetWORD5_IntConfigError() uint32 {
	return (volatile.LoadUint32(&o.WORD5.Reg) & 0x80000000) >> 31
}

// GLOBALSTATMACH.WORD6: WORD6 register
func (o *GLOBALSTATMACH_Type) SetWORD6_DefaultAntennaID(value uint32) {
	volatile.StoreUint32(&o.WORD6.Reg, volatile.LoadUint32(&o.WORD6.Reg)&^(0x7f)|value)
}
func (o *GLOBALSTATMACH_Type) GetWORD6_DefaultAntennaID() uint32 {
	return volatile.LoadUint32(&o.WORD6.Reg) & 0x7f
}

type RADIO_CONTROL_Type struct {
	ID                 volatile.Register32 // 0x0
	CLK32COUNT_REG     volatile.Register32 // 0x4
	CLK32PERIOD_REG    volatile.Register32 // 0x8
	CLK32FREQUENCY_REG volatile.Register32 // 0xC
	IRQ_STATUS         volatile.Register32 // 0x10
	IRQ_ENABLE         volatile.Register32 // 0x14
}

// RADIO_CONTROL.ID: RADIO_CONTROL_ID register
func (o *RADIO_CONTROL_Type) SetID_REVISION(value uint32) {
	volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0xf0)|value<<4)
}
func (o *RADIO_CONTROL_Type) GetID_REVISION() uint32 {
	return (volatile.LoadUint32(&o.ID.Reg) & 0xf0) >> 4
}
func (o *RADIO_CONTROL_Type) SetID_VERSION(value uint32) {
	volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0xf00)|value<<8)
}
func (o *RADIO_CONTROL_Type) GetID_VERSION() uint32 {
	return (volatile.LoadUint32(&o.ID.Reg) & 0xf00) >> 8
}
func (o *RADIO_CONTROL_Type) SetID_PRODUCT(value uint32) {
	volatile.StoreUint32(&o.ID.Reg, volatile.LoadUint32(&o.ID.Reg)&^(0xf000)|value<<12)
}
func (o *RADIO_CONTROL_Type) GetID_PRODUCT() uint32 {
	return (volatile.LoadUint32(&o.ID.Reg) & 0xf000) >> 12
}

// RADIO_CONTROL.CLK32COUNT_REG: CLK32COUNT_REG register
func (o *RADIO_CONTROL_Type) SetCLK32COUNT_REG_SLOW_COUNT(value uint32) {
	volatile.StoreUint32(&o.CLK32COUNT_REG.Reg, volatile.LoadUint32(&o.CLK32COUNT_REG.Reg)&^(0x1ff)|value)
}
func (o *RADIO_CONTROL_Type) GetCLK32COUNT_REG_SLOW_COUNT() uint32 {
	return volatile.LoadUint32(&o.CLK32COUNT_REG.Reg) & 0x1ff
}

// RADIO_CONTROL.CLK32PERIOD_REG: CLK32PERIOD_REG register
func (o *RADIO_CONTROL_Type) SetCLK32PERIOD_REG_SLOW_PERIOD(value uint32) {
	volatile.StoreUint32(&o.CLK32PERIOD_REG.Reg, volatile.LoadUint32(&o.CLK32PERIOD_REG.Reg)&^(0x7ffff)|value)
}
func (o *RADIO_CONTROL_Type) GetCLK32PERIOD_REG_SLOW_PERIOD() uint32 {
	return volatile.LoadUint32(&o.CLK32PERIOD_REG.Reg) & 0x7ffff
}

// RADIO_CONTROL.CLK32FREQUENCY_REG: CLK32FREQUENCY_REG register
func (o *RADIO_CONTROL_Type) SetCLK32FREQUENCY_REG_SLOW_FREQUENCY(value uint32) {
	volatile.StoreUint32(&o.CLK32FREQUENCY_REG.Reg, volatile.LoadUint32(&o.CLK32FREQUENCY_REG.Reg)&^(0x7ffffff)|value)
}
func (o *RADIO_CONTROL_Type) GetCLK32FREQUENCY_REG_SLOW_FREQUENCY() uint32 {
	return volatile.LoadUint32(&o.CLK32FREQUENCY_REG.Reg) & 0x7ffffff
}

// RADIO_CONTROL.IRQ_STATUS: RADIO_CONTROL_IRQ_STATUS register
func (o *RADIO_CONTROL_Type) SetIRQ_STATUS_SLOW_CLK_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_STATUS.Reg, volatile.LoadUint32(&o.IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *RADIO_CONTROL_Type) GetIRQ_STATUS_SLOW_CLK_IRQ() uint32 {
	return volatile.LoadUint32(&o.IRQ_STATUS.Reg) & 0x1
}
func (o *RADIO_CONTROL_Type) SetIRQ_STATUS_RADIO_FSM_IRQ(value uint32) {
	volatile.StoreUint32(&o.IRQ_STATUS.Reg, volatile.LoadUint32(&o.IRQ_STATUS.Reg)&^(0x3f00)|value<<8)
}
func (o *RADIO_CONTROL_Type) GetIRQ_STATUS_RADIO_FSM_IRQ() uint32 {
	return (volatile.LoadUint32(&o.IRQ_STATUS.Reg) & 0x3f00) >> 8
}

// RADIO_CONTROL.IRQ_ENABLE: RADIO_CONTROL_IRQ_ENABLE register
func (o *RADIO_CONTROL_Type) SetIRQ_ENABLE_SLOW_CLK_IRQ_MASK(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENABLE.Reg, volatile.LoadUint32(&o.IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *RADIO_CONTROL_Type) GetIRQ_ENABLE_SLOW_CLK_IRQ_MASK() uint32 {
	return volatile.LoadUint32(&o.IRQ_ENABLE.Reg) & 0x1
}
func (o *RADIO_CONTROL_Type) SetIRQ_ENABLE_RADIO_FSM_IRQ_MASK(value uint32) {
	volatile.StoreUint32(&o.IRQ_ENABLE.Reg, volatile.LoadUint32(&o.IRQ_ENABLE.Reg)&^(0x3f00)|value<<8)
}
func (o *RADIO_CONTROL_Type) GetIRQ_ENABLE_RADIO_FSM_IRQ_MASK() uint32 {
	return (volatile.LoadUint32(&o.IRQ_ENABLE.Reg) & 0x3f00) >> 8
}

type RADIO_Type struct {
	AA0_DIG_USR         volatile.Register32 // 0x0
	AA1_DIG_USR         volatile.Register32 // 0x4
	AA2_DIG_USR         volatile.Register32 // 0x8
	AA3_DIG_USR         volatile.Register32 // 0xC
	DEM_MOD_DIG_USR     volatile.Register32 // 0x10
	FSM_USR             volatile.Register32 // 0x14
	PHYCTRL_DIG_USR     volatile.Register32 // 0x18
	_                   [44]byte
	AFC1_DIG_ENG        volatile.Register32 // 0x48
	_                   [8]byte
	CR0_DIG_ENG         volatile.Register32 // 0x54
	_                   [16]byte
	CR0_LR              volatile.Register32 // 0x68
	VIT_CONF_DIG_ENG    volatile.Register32 // 0x6C
	_                   [20]byte
	LR_PD_THR_DIG_ENG   volatile.Register32 // 0x84
	LR_RSSI_THR_DIG_ENG volatile.Register32 // 0x88
	LR_AAC_THR_DIG_ENG  volatile.Register32 // 0x8C
	_                   [24]byte
	SYNTHCAL0_DIG_ENG   volatile.Register32 // 0xA8
	_                   [68]byte
	DTB5_DIG_ENG        volatile.Register32 // 0xF0
	_                   [84]byte
	RXADC_ANA_USR       volatile.Register32 // 0x148
	_                   [8]byte
	LDO_ANA_ENG         volatile.Register32 // 0x154
	_                   [28]byte
	CBIAS0_ANA_ENG      volatile.Register32 // 0x174
	CBIAS1_ANA_ENG      volatile.Register32 // 0x178
	_                   [4]byte
	SYNTHCAL0_DIG_OUT   volatile.Register32 // 0x180
	SYNTHCAL1_DIG_OUT   volatile.Register32 // 0x184
	SYNTHCAL2_DIG_OUT   volatile.Register32 // 0x188
	SYNTHCAL3_DIG_OUT   volatile.Register32 // 0x18C
	SYNTHCAL4_DIG_OUT   volatile.Register32 // 0x190
	SYNTHCAL5_DIG_OUT   volatile.Register32 // 0x194
	FSM_STATUS_DIG_OUT  volatile.Register32 // 0x198
	_                   [8]byte
	RSSI0_DIG_OUT       volatile.Register32 // 0x1A4
	RSSI1_DIG_OUT       volatile.Register32 // 0x1A8
	AGC_DIG_OUT         volatile.Register32 // 0x1AC
	DEMOD_DIG_OUT       volatile.Register32 // 0x1B0
	_                   [8]byte
	AGC2_ANA_TST        volatile.Register32 // 0x1BC
	AGC0_DIG_ENG        volatile.Register32 // 0x1C0
	AGC1_DIG_ENG        volatile.Register32 // 0x1C4
	_                   [32]byte
	AGC10_DIG_ENG       volatile.Register32 // 0x1E8
	AGC11_DIG_ENG       volatile.Register32 // 0x1EC
	AGC12_DIG_ENG       volatile.Register32 // 0x1F0
	AGC13_DIG_ENG       volatile.Register32 // 0x1F4
	AGC14_DIG_ENG       volatile.Register32 // 0x1F8
	AGC15_DIG_ENG       volatile.Register32 // 0x1FC
	AGC16_DIG_ENG       volatile.Register32 // 0x200
	AGC17_DIG_ENG       volatile.Register32 // 0x204
	AGC18_DIG_ENG       volatile.Register32 // 0x208
	AGC19_DIG_ENG       volatile.Register32 // 0x20C
	_                   [20]byte
	RXADC_HW_TRIM_OUT   volatile.Register32 // 0x224
	CBIAS0_HW_TRIM_OUT  volatile.Register32 // 0x228
	_                   [4]byte
	AGC_HW_TRIM_OUT     volatile.Register32 // 0x230
	_                   [8]byte
	DEMOD_IQ2_DIG_TST   volatile.Register32 // 0x23C
	ANTSW0_DIG_USR      volatile.Register32 // 0x240
	ANTSW1_DIG_USR      volatile.Register32 // 0x244
	ANTSW2_DIG_USR      volatile.Register32 // 0x248
	ANTSW3_DIG_USR      volatile.Register32 // 0x24C
}

// RADIO.AA0_DIG_USR: AA0_DIG_USR register
func (o *RADIO_Type) SetAA0_DIG_USR_AA_7_0(value uint32) {
	volatile.StoreUint32(&o.AA0_DIG_USR.Reg, volatile.LoadUint32(&o.AA0_DIG_USR.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetAA0_DIG_USR_AA_7_0() uint32 {
	return volatile.LoadUint32(&o.AA0_DIG_USR.Reg) & 0xff
}

// RADIO.AA1_DIG_USR: AA1_DIG_USR register
func (o *RADIO_Type) SetAA1_DIG_USR_AA_15_8(value uint32) {
	volatile.StoreUint32(&o.AA1_DIG_USR.Reg, volatile.LoadUint32(&o.AA1_DIG_USR.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetAA1_DIG_USR_AA_15_8() uint32 {
	return volatile.LoadUint32(&o.AA1_DIG_USR.Reg) & 0xff
}

// RADIO.AA2_DIG_USR: AA2_DIG_USR register
func (o *RADIO_Type) SetAA2_DIG_USR_AA_23_16(value uint32) {
	volatile.StoreUint32(&o.AA2_DIG_USR.Reg, volatile.LoadUint32(&o.AA2_DIG_USR.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetAA2_DIG_USR_AA_23_16() uint32 {
	return volatile.LoadUint32(&o.AA2_DIG_USR.Reg) & 0xff
}

// RADIO.AA3_DIG_USR: AA3_DIG_USR register
func (o *RADIO_Type) SetAA3_DIG_USR_AA_31_24(value uint32) {
	volatile.StoreUint32(&o.AA3_DIG_USR.Reg, volatile.LoadUint32(&o.AA3_DIG_USR.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetAA3_DIG_USR_AA_31_24() uint32 {
	return volatile.LoadUint32(&o.AA3_DIG_USR.Reg) & 0xff
}

// RADIO.DEM_MOD_DIG_USR: DEM_MOD_DIG_USR register
func (o *RADIO_Type) SetDEM_MOD_DIG_USR_CHANNEL_NUM(value uint32) {
	volatile.StoreUint32(&o.DEM_MOD_DIG_USR.Reg, volatile.LoadUint32(&o.DEM_MOD_DIG_USR.Reg)&^(0xfe)|value<<1)
}
func (o *RADIO_Type) GetDEM_MOD_DIG_USR_CHANNEL_NUM() uint32 {
	return (volatile.LoadUint32(&o.DEM_MOD_DIG_USR.Reg) & 0xfe) >> 1
}

// RADIO.FSM_USR: RADIO_FSM_USR register
func (o *RADIO_Type) SetFSM_USR_EN_CALIB_CBP(value uint32) {
	volatile.StoreUint32(&o.FSM_USR.Reg, volatile.LoadUint32(&o.FSM_USR.Reg)&^(0x2)|value<<1)
}
func (o *RADIO_Type) GetFSM_USR_EN_CALIB_CBP() uint32 {
	return (volatile.LoadUint32(&o.FSM_USR.Reg) & 0x2) >> 1
}
func (o *RADIO_Type) SetFSM_USR_EN_CALIB_SYNTH(value uint32) {
	volatile.StoreUint32(&o.FSM_USR.Reg, volatile.LoadUint32(&o.FSM_USR.Reg)&^(0x4)|value<<2)
}
func (o *RADIO_Type) GetFSM_USR_EN_CALIB_SYNTH() uint32 {
	return (volatile.LoadUint32(&o.FSM_USR.Reg) & 0x4) >> 2
}
func (o *RADIO_Type) SetFSM_USR_PA_POWER(value uint32) {
	volatile.StoreUint32(&o.FSM_USR.Reg, volatile.LoadUint32(&o.FSM_USR.Reg)&^(0xf8)|value<<3)
}
func (o *RADIO_Type) GetFSM_USR_PA_POWER() uint32 {
	return (volatile.LoadUint32(&o.FSM_USR.Reg) & 0xf8) >> 3
}

// RADIO.PHYCTRL_DIG_USR: PHYCTRL_DIG_USR register
func (o *RADIO_Type) SetPHYCTRL_DIG_USR_RXTXPHY(value uint32) {
	volatile.StoreUint32(&o.PHYCTRL_DIG_USR.Reg, volatile.LoadUint32(&o.PHYCTRL_DIG_USR.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetPHYCTRL_DIG_USR_RXTXPHY() uint32 {
	return volatile.LoadUint32(&o.PHYCTRL_DIG_USR.Reg) & 0x7
}

// RADIO.AFC1_DIG_ENG: AFC1_DIG_ENG register
func (o *RADIO_Type) SetAFC1_DIG_ENG_AFC_DELAY_AFTER(value uint32) {
	volatile.StoreUint32(&o.AFC1_DIG_ENG.Reg, volatile.LoadUint32(&o.AFC1_DIG_ENG.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetAFC1_DIG_ENG_AFC_DELAY_AFTER() uint32 {
	return volatile.LoadUint32(&o.AFC1_DIG_ENG.Reg) & 0xf
}
func (o *RADIO_Type) SetAFC1_DIG_ENG_AFC_DELAY_BEFORE(value uint32) {
	volatile.StoreUint32(&o.AFC1_DIG_ENG.Reg, volatile.LoadUint32(&o.AFC1_DIG_ENG.Reg)&^(0xf0)|value<<4)
}
func (o *RADIO_Type) GetAFC1_DIG_ENG_AFC_DELAY_BEFORE() uint32 {
	return (volatile.LoadUint32(&o.AFC1_DIG_ENG.Reg) & 0xf0) >> 4
}

// RADIO.CR0_DIG_ENG: CR0_DIG_ENG register
func (o *RADIO_Type) SetCR0_DIG_ENG_CR_GAIN_AFTER(value uint32) {
	volatile.StoreUint32(&o.CR0_DIG_ENG.Reg, volatile.LoadUint32(&o.CR0_DIG_ENG.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetCR0_DIG_ENG_CR_GAIN_AFTER() uint32 {
	return volatile.LoadUint32(&o.CR0_DIG_ENG.Reg) & 0xf
}
func (o *RADIO_Type) SetCR0_DIG_ENG_CR_GAIN_BEFORE(value uint32) {
	volatile.StoreUint32(&o.CR0_DIG_ENG.Reg, volatile.LoadUint32(&o.CR0_DIG_ENG.Reg)&^(0xf0)|value<<4)
}
func (o *RADIO_Type) GetCR0_DIG_ENG_CR_GAIN_BEFORE() uint32 {
	return (volatile.LoadUint32(&o.CR0_DIG_ENG.Reg) & 0xf0) >> 4
}

// RADIO.CR0_LR: CR0_LR register
func (o *RADIO_Type) SetCR0_LR_CR_LR_GAIN_AFTER(value uint32) {
	volatile.StoreUint32(&o.CR0_LR.Reg, volatile.LoadUint32(&o.CR0_LR.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetCR0_LR_CR_LR_GAIN_AFTER() uint32 {
	return volatile.LoadUint32(&o.CR0_LR.Reg) & 0xf
}
func (o *RADIO_Type) SetCR0_LR_CR_LR_GAIN_BEFORE(value uint32) {
	volatile.StoreUint32(&o.CR0_LR.Reg, volatile.LoadUint32(&o.CR0_LR.Reg)&^(0xf0)|value<<4)
}
func (o *RADIO_Type) GetCR0_LR_CR_LR_GAIN_BEFORE() uint32 {
	return (volatile.LoadUint32(&o.CR0_LR.Reg) & 0xf0) >> 4
}

// RADIO.VIT_CONF_DIG_ENG: VIT_CONF_DIG_ENG register
func (o *RADIO_Type) SetVIT_CONF_DIG_ENG_VIT_EN(value uint32) {
	volatile.StoreUint32(&o.VIT_CONF_DIG_ENG.Reg, volatile.LoadUint32(&o.VIT_CONF_DIG_ENG.Reg)&^(0x1)|value)
}
func (o *RADIO_Type) GetVIT_CONF_DIG_ENG_VIT_EN() uint32 {
	return volatile.LoadUint32(&o.VIT_CONF_DIG_ENG.Reg) & 0x1
}
func (o *RADIO_Type) SetVIT_CONF_DIG_ENG_SPARE(value uint32) {
	volatile.StoreUint32(&o.VIT_CONF_DIG_ENG.Reg, volatile.LoadUint32(&o.VIT_CONF_DIG_ENG.Reg)&^(0xfc)|value<<2)
}
func (o *RADIO_Type) GetVIT_CONF_DIG_ENG_SPARE() uint32 {
	return (volatile.LoadUint32(&o.VIT_CONF_DIG_ENG.Reg) & 0xfc) >> 2
}

// RADIO.LR_PD_THR_DIG_ENG: LR_PD_THR_DIG_ENG register
func (o *RADIO_Type) SetLR_PD_THR_DIG_ENG_LR_PD_THR(value uint32) {
	volatile.StoreUint32(&o.LR_PD_THR_DIG_ENG.Reg, volatile.LoadUint32(&o.LR_PD_THR_DIG_ENG.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetLR_PD_THR_DIG_ENG_LR_PD_THR() uint32 {
	return volatile.LoadUint32(&o.LR_PD_THR_DIG_ENG.Reg) & 0xff
}

// RADIO.LR_RSSI_THR_DIG_ENG: LR_RSSI_THR_DIG_ENG register
func (o *RADIO_Type) SetLR_RSSI_THR_DIG_ENG_LR_RSSI_THR(value uint32) {
	volatile.StoreUint32(&o.LR_RSSI_THR_DIG_ENG.Reg, volatile.LoadUint32(&o.LR_RSSI_THR_DIG_ENG.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetLR_RSSI_THR_DIG_ENG_LR_RSSI_THR() uint32 {
	return volatile.LoadUint32(&o.LR_RSSI_THR_DIG_ENG.Reg) & 0xff
}

// RADIO.LR_AAC_THR_DIG_ENG: LR_AAC_THR_DIG_ENG register
func (o *RADIO_Type) SetLR_AAC_THR_DIG_ENG_LR_AAC_THR(value uint32) {
	volatile.StoreUint32(&o.LR_AAC_THR_DIG_ENG.Reg, volatile.LoadUint32(&o.LR_AAC_THR_DIG_ENG.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetLR_AAC_THR_DIG_ENG_LR_AAC_THR() uint32 {
	return volatile.LoadUint32(&o.LR_AAC_THR_DIG_ENG.Reg) & 0xff
}

// RADIO.SYNTHCAL0_DIG_ENG: SYNTHCAL0_DIG_ENG register
func (o *RADIO_Type) SetSYNTHCAL0_DIG_ENG_SYNTHCAL_DEBUG_BUS_SEL(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL0_DIG_ENG.Reg, volatile.LoadUint32(&o.SYNTHCAL0_DIG_ENG.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetSYNTHCAL0_DIG_ENG_SYNTHCAL_DEBUG_BUS_SEL() uint32 {
	return volatile.LoadUint32(&o.SYNTHCAL0_DIG_ENG.Reg) & 0xf
}
func (o *RADIO_Type) SetSYNTHCAL0_DIG_ENG_SYNTH_IF_FREQ_CAL(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL0_DIG_ENG.Reg, volatile.LoadUint32(&o.SYNTHCAL0_DIG_ENG.Reg)&^(0xc0)|value<<6)
}
func (o *RADIO_Type) GetSYNTHCAL0_DIG_ENG_SYNTH_IF_FREQ_CAL() uint32 {
	return (volatile.LoadUint32(&o.SYNTHCAL0_DIG_ENG.Reg) & 0xc0) >> 6
}

// RADIO.DTB5_DIG_ENG: DTB5_DIG_ENG register
func (o *RADIO_Type) SetDTB5_DIG_ENG_RXTX_START_SEL(value uint32) {
	volatile.StoreUint32(&o.DTB5_DIG_ENG.Reg, volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg)&^(0x1)|value)
}
func (o *RADIO_Type) GetDTB5_DIG_ENG_RXTX_START_SEL() uint32 {
	return volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg) & 0x1
}
func (o *RADIO_Type) SetDTB5_DIG_ENG_TX_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.DTB5_DIG_ENG.Reg, volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg)&^(0x2)|value<<1)
}
func (o *RADIO_Type) GetDTB5_DIG_ENG_TX_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg) & 0x2) >> 1
}
func (o *RADIO_Type) SetDTB5_DIG_ENG_RX_ACTIVE(value uint32) {
	volatile.StoreUint32(&o.DTB5_DIG_ENG.Reg, volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg)&^(0x4)|value<<2)
}
func (o *RADIO_Type) GetDTB5_DIG_ENG_RX_ACTIVE() uint32 {
	return (volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg) & 0x4) >> 2
}
func (o *RADIO_Type) SetDTB5_DIG_ENG_INITIALIZE(value uint32) {
	volatile.StoreUint32(&o.DTB5_DIG_ENG.Reg, volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetDTB5_DIG_ENG_INITIALIZE() uint32 {
	return (volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetDTB5_DIG_ENG_PORT_SELECTED_EN(value uint32) {
	volatile.StoreUint32(&o.DTB5_DIG_ENG.Reg, volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg)&^(0x10)|value<<4)
}
func (o *RADIO_Type) GetDTB5_DIG_ENG_PORT_SELECTED_EN() uint32 {
	return (volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg) & 0x10) >> 4
}
func (o *RADIO_Type) SetDTB5_DIG_ENG_PORT_SELECTED_0(value uint32) {
	volatile.StoreUint32(&o.DTB5_DIG_ENG.Reg, volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg)&^(0x20)|value<<5)
}
func (o *RADIO_Type) GetDTB5_DIG_ENG_PORT_SELECTED_0() uint32 {
	return (volatile.LoadUint32(&o.DTB5_DIG_ENG.Reg) & 0x20) >> 5
}

// RADIO.RXADC_ANA_USR: RXADC_ANA_USR register
func (o *RADIO_Type) SetRXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I(value uint32) {
	volatile.StoreUint32(&o.RXADC_ANA_USR.Reg, volatile.LoadUint32(&o.RXADC_ANA_USR.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetRXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I() uint32 {
	return volatile.LoadUint32(&o.RXADC_ANA_USR.Reg) & 0x7
}
func (o *RADIO_Type) SetRXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q(value uint32) {
	volatile.StoreUint32(&o.RXADC_ANA_USR.Reg, volatile.LoadUint32(&o.RXADC_ANA_USR.Reg)&^(0x38)|value<<3)
}
func (o *RADIO_Type) GetRXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q() uint32 {
	return (volatile.LoadUint32(&o.RXADC_ANA_USR.Reg) & 0x38) >> 3
}
func (o *RADIO_Type) SetRXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL(value uint32) {
	volatile.StoreUint32(&o.RXADC_ANA_USR.Reg, volatile.LoadUint32(&o.RXADC_ANA_USR.Reg)&^(0x40)|value<<6)
}
func (o *RADIO_Type) GetRXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL() uint32 {
	return (volatile.LoadUint32(&o.RXADC_ANA_USR.Reg) & 0x40) >> 6
}
func (o *RADIO_Type) SetRXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL(value uint32) {
	volatile.StoreUint32(&o.RXADC_ANA_USR.Reg, volatile.LoadUint32(&o.RXADC_ANA_USR.Reg)&^(0x80)|value<<7)
}
func (o *RADIO_Type) GetRXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL() uint32 {
	return (volatile.LoadUint32(&o.RXADC_ANA_USR.Reg) & 0x80) >> 7
}

// RADIO.LDO_ANA_ENG: LDO_ANA_ENG register
func (o *RADIO_Type) SetLDO_ANA_ENG_RFD_RF_REG_BYPASS(value uint32) {
	volatile.StoreUint32(&o.LDO_ANA_ENG.Reg, volatile.LoadUint32(&o.LDO_ANA_ENG.Reg)&^(0x1)|value)
}
func (o *RADIO_Type) GetLDO_ANA_ENG_RFD_RF_REG_BYPASS() uint32 {
	return volatile.LoadUint32(&o.LDO_ANA_ENG.Reg) & 0x1
}

// RADIO.CBIAS0_ANA_ENG: CBIAS0_ANA_ENG register
func (o *RADIO_Type) SetCBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM(value uint32) {
	volatile.StoreUint32(&o.CBIAS0_ANA_ENG.Reg, volatile.LoadUint32(&o.CBIAS0_ANA_ENG.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetCBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM() uint32 {
	return volatile.LoadUint32(&o.CBIAS0_ANA_ENG.Reg) & 0xf
}
func (o *RADIO_Type) SetCBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM(value uint32) {
	volatile.StoreUint32(&o.CBIAS0_ANA_ENG.Reg, volatile.LoadUint32(&o.CBIAS0_ANA_ENG.Reg)&^(0xf0)|value<<4)
}
func (o *RADIO_Type) GetCBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM() uint32 {
	return (volatile.LoadUint32(&o.CBIAS0_ANA_ENG.Reg) & 0xf0) >> 4
}

// RADIO.CBIAS1_ANA_ENG: CBIAS1_ANA_ENG register
func (o *RADIO_Type) SetCBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL(value uint32) {
	volatile.StoreUint32(&o.CBIAS1_ANA_ENG.Reg, volatile.LoadUint32(&o.CBIAS1_ANA_ENG.Reg)&^(0x80)|value<<7)
}
func (o *RADIO_Type) GetCBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL() uint32 {
	return (volatile.LoadUint32(&o.CBIAS1_ANA_ENG.Reg) & 0x80) >> 7
}

// RADIO.SYNTHCAL0_DIG_OUT: SYNTHCAL0_DIG_OUT register
func (o *RADIO_Type) SetSYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL0_DIG_OUT.Reg, volatile.LoadUint32(&o.SYNTHCAL0_DIG_OUT.Reg)&^(0x7f)|value)
}
func (o *RADIO_Type) GetSYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0() uint32 {
	return volatile.LoadUint32(&o.SYNTHCAL0_DIG_OUT.Reg) & 0x7f
}

// RADIO.SYNTHCAL1_DIG_OUT: SYNTHCAL1_DIG_OUT register
func (o *RADIO_Type) SetSYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL1_DIG_OUT.Reg, volatile.LoadUint32(&o.SYNTHCAL1_DIG_OUT.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetSYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7() uint32 {
	return volatile.LoadUint32(&o.SYNTHCAL1_DIG_OUT.Reg) & 0xf
}

// RADIO.SYNTHCAL2_DIG_OUT: SYNTHCAL2_DIG_OUT register
func (o *RADIO_Type) SetSYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL2_DIG_OUT.Reg, volatile.LoadUint32(&o.SYNTHCAL2_DIG_OUT.Reg)&^(0x7f)|value)
}
func (o *RADIO_Type) GetSYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT() uint32 {
	return volatile.LoadUint32(&o.SYNTHCAL2_DIG_OUT.Reg) & 0x7f
}

// RADIO.SYNTHCAL3_DIG_OUT: SYNTHCAL3_DIG_OUT register
func (o *RADIO_Type) SetSYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL3_DIG_OUT.Reg, volatile.LoadUint32(&o.SYNTHCAL3_DIG_OUT.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetSYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS() uint32 {
	return volatile.LoadUint32(&o.SYNTHCAL3_DIG_OUT.Reg) & 0xff
}

// RADIO.SYNTHCAL4_DIG_OUT: SYNTHCAL4_DIG_OUT register
func (o *RADIO_Type) SetSYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL4_DIG_OUT.Reg, volatile.LoadUint32(&o.SYNTHCAL4_DIG_OUT.Reg)&^(0x3f)|value)
}
func (o *RADIO_Type) GetSYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT() uint32 {
	return volatile.LoadUint32(&o.SYNTHCAL4_DIG_OUT.Reg) & 0x3f
}

// RADIO.SYNTHCAL5_DIG_OUT: SYNTHCAL5_DIG_OUT register
func (o *RADIO_Type) SetSYNTHCAL5_DIG_OUT_CBP_CALIB_WORD(value uint32) {
	volatile.StoreUint32(&o.SYNTHCAL5_DIG_OUT.Reg, volatile.LoadUint32(&o.SYNTHCAL5_DIG_OUT.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetSYNTHCAL5_DIG_OUT_CBP_CALIB_WORD() uint32 {
	return volatile.LoadUint32(&o.SYNTHCAL5_DIG_OUT.Reg) & 0xf
}

// RADIO.FSM_STATUS_DIG_OUT: FSM_STATUS_DIG_OUT register
func (o *RADIO_Type) SetFSM_STATUS_DIG_OUT_STATUS(value uint32) {
	volatile.StoreUint32(&o.FSM_STATUS_DIG_OUT.Reg, volatile.LoadUint32(&o.FSM_STATUS_DIG_OUT.Reg)&^(0x1f)|value)
}
func (o *RADIO_Type) GetFSM_STATUS_DIG_OUT_STATUS() uint32 {
	return volatile.LoadUint32(&o.FSM_STATUS_DIG_OUT.Reg) & 0x1f
}
func (o *RADIO_Type) SetFSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR(value uint32) {
	volatile.StoreUint32(&o.FSM_STATUS_DIG_OUT.Reg, volatile.LoadUint32(&o.FSM_STATUS_DIG_OUT.Reg)&^(0x80)|value<<7)
}
func (o *RADIO_Type) GetFSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR() uint32 {
	return (volatile.LoadUint32(&o.FSM_STATUS_DIG_OUT.Reg) & 0x80) >> 7
}

// RADIO.RSSI0_DIG_OUT: RSSI0_DIG_OUT register
func (o *RADIO_Type) SetRSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0(value uint32) {
	volatile.StoreUint32(&o.RSSI0_DIG_OUT.Reg, volatile.LoadUint32(&o.RSSI0_DIG_OUT.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetRSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0() uint32 {
	return volatile.LoadUint32(&o.RSSI0_DIG_OUT.Reg) & 0xff
}

// RADIO.RSSI1_DIG_OUT: RSSI1_DIG_OUT register
func (o *RADIO_Type) SetRSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8(value uint32) {
	volatile.StoreUint32(&o.RSSI1_DIG_OUT.Reg, volatile.LoadUint32(&o.RSSI1_DIG_OUT.Reg)&^(0xff)|value)
}
func (o *RADIO_Type) GetRSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8() uint32 {
	return volatile.LoadUint32(&o.RSSI1_DIG_OUT.Reg) & 0xff
}

// RADIO.AGC_DIG_OUT: AGC_DIG_OUT register
func (o *RADIO_Type) SetAGC_DIG_OUT_AGC_ATT_OUT(value uint32) {
	volatile.StoreUint32(&o.AGC_DIG_OUT.Reg, volatile.LoadUint32(&o.AGC_DIG_OUT.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetAGC_DIG_OUT_AGC_ATT_OUT() uint32 {
	return volatile.LoadUint32(&o.AGC_DIG_OUT.Reg) & 0xf
}

// RADIO.DEMOD_DIG_OUT: DEMOD_DIG_OUT register
func (o *RADIO_Type) SetDEMOD_DIG_OUT_CI_FIELD(value uint32) {
	volatile.StoreUint32(&o.DEMOD_DIG_OUT.Reg, volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg)&^(0x3)|value)
}
func (o *RADIO_Type) GetDEMOD_DIG_OUT_CI_FIELD() uint32 {
	return volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg) & 0x3
}
func (o *RADIO_Type) SetDEMOD_DIG_OUT_AAC_FOUND(value uint32) {
	volatile.StoreUint32(&o.DEMOD_DIG_OUT.Reg, volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg)&^(0x4)|value<<2)
}
func (o *RADIO_Type) GetDEMOD_DIG_OUT_AAC_FOUND() uint32 {
	return (volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg) & 0x4) >> 2
}
func (o *RADIO_Type) SetDEMOD_DIG_OUT_PD_FOUND(value uint32) {
	volatile.StoreUint32(&o.DEMOD_DIG_OUT.Reg, volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetDEMOD_DIG_OUT_PD_FOUND() uint32 {
	return (volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetDEMOD_DIG_OUT_RX_END(value uint32) {
	volatile.StoreUint32(&o.DEMOD_DIG_OUT.Reg, volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg)&^(0x10)|value<<4)
}
func (o *RADIO_Type) GetDEMOD_DIG_OUT_RX_END() uint32 {
	return (volatile.LoadUint32(&o.DEMOD_DIG_OUT.Reg) & 0x10) >> 4
}

// RADIO.AGC2_ANA_TST: AGC2_ANA_TST register
func (o *RADIO_Type) SetAGC2_ANA_TST_AGC2_ANA_TST_SEL(value uint32) {
	volatile.StoreUint32(&o.AGC2_ANA_TST.Reg, volatile.LoadUint32(&o.AGC2_ANA_TST.Reg)&^(0x1)|value)
}
func (o *RADIO_Type) GetAGC2_ANA_TST_AGC2_ANA_TST_SEL() uint32 {
	return volatile.LoadUint32(&o.AGC2_ANA_TST.Reg) & 0x1
}
func (o *RADIO_Type) SetAGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM(value uint32) {
	volatile.StoreUint32(&o.AGC2_ANA_TST.Reg, volatile.LoadUint32(&o.AGC2_ANA_TST.Reg)&^(0xe)|value<<1)
}
func (o *RADIO_Type) GetAGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM() uint32 {
	return (volatile.LoadUint32(&o.AGC2_ANA_TST.Reg) & 0xe) >> 1
}

// RADIO.AGC0_DIG_ENG: AGC0_DIG_ENG register
func (o *RADIO_Type) SetAGC0_DIG_ENG_AGC_THR_HIGH(value uint32) {
	volatile.StoreUint32(&o.AGC0_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC0_DIG_ENG.Reg)&^(0x3f)|value)
}
func (o *RADIO_Type) GetAGC0_DIG_ENG_AGC_THR_HIGH() uint32 {
	return volatile.LoadUint32(&o.AGC0_DIG_ENG.Reg) & 0x3f
}
func (o *RADIO_Type) SetAGC0_DIG_ENG_AGC_ENABLE(value uint32) {
	volatile.StoreUint32(&o.AGC0_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC0_DIG_ENG.Reg)&^(0x40)|value<<6)
}
func (o *RADIO_Type) GetAGC0_DIG_ENG_AGC_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.AGC0_DIG_ENG.Reg) & 0x40) >> 6
}

// RADIO.AGC1_DIG_ENG: AGC1_DIG_ENG register
func (o *RADIO_Type) SetAGC1_DIG_ENG_AGC_THR_LOW_6(value uint32) {
	volatile.StoreUint32(&o.AGC1_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC1_DIG_ENG.Reg)&^(0x3f)|value)
}
func (o *RADIO_Type) GetAGC1_DIG_ENG_AGC_THR_LOW_6() uint32 {
	return volatile.LoadUint32(&o.AGC1_DIG_ENG.Reg) & 0x3f
}
func (o *RADIO_Type) SetAGC1_DIG_ENG_AGC_AUTOLOCK(value uint32) {
	volatile.StoreUint32(&o.AGC1_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC1_DIG_ENG.Reg)&^(0x40)|value<<6)
}
func (o *RADIO_Type) GetAGC1_DIG_ENG_AGC_AUTOLOCK() uint32 {
	return (volatile.LoadUint32(&o.AGC1_DIG_ENG.Reg) & 0x40) >> 6
}
func (o *RADIO_Type) SetAGC1_DIG_ENG_AGC_LOCK_SYNC(value uint32) {
	volatile.StoreUint32(&o.AGC1_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC1_DIG_ENG.Reg)&^(0x80)|value<<7)
}
func (o *RADIO_Type) GetAGC1_DIG_ENG_AGC_LOCK_SYNC() uint32 {
	return (volatile.LoadUint32(&o.AGC1_DIG_ENG.Reg) & 0x80) >> 7
}

// RADIO.AGC10_DIG_ENG: AGC10_DIG_ENG register
func (o *RADIO_Type) SetAGC10_DIG_ENG_ATT_IF_0(value uint32) {
	volatile.StoreUint32(&o.AGC10_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC10_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC10_DIG_ENG_ATT_IF_0() uint32 {
	return volatile.LoadUint32(&o.AGC10_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC10_DIG_ENG_ATT_LNA_0(value uint32) {
	volatile.StoreUint32(&o.AGC10_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC10_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC10_DIG_ENG_ATT_LNA_0() uint32 {
	return (volatile.LoadUint32(&o.AGC10_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC10_DIG_ENG_ATT_ANT_0(value uint32) {
	volatile.StoreUint32(&o.AGC10_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC10_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC10_DIG_ENG_ATT_ANT_0() uint32 {
	return (volatile.LoadUint32(&o.AGC10_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC11_DIG_ENG: AGC11_DIG_ENG register
func (o *RADIO_Type) SetAGC11_DIG_ENG_ATT_IF_1(value uint32) {
	volatile.StoreUint32(&o.AGC11_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC11_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC11_DIG_ENG_ATT_IF_1() uint32 {
	return volatile.LoadUint32(&o.AGC11_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC11_DIG_ENG_ATT_LNA_1(value uint32) {
	volatile.StoreUint32(&o.AGC11_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC11_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC11_DIG_ENG_ATT_LNA_1() uint32 {
	return (volatile.LoadUint32(&o.AGC11_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC11_DIG_ENG_ATT_ANT_1(value uint32) {
	volatile.StoreUint32(&o.AGC11_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC11_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC11_DIG_ENG_ATT_ANT_1() uint32 {
	return (volatile.LoadUint32(&o.AGC11_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC12_DIG_ENG: AGC12_DIG_ENG register
func (o *RADIO_Type) SetAGC12_DIG_ENG_ATT_IF_2(value uint32) {
	volatile.StoreUint32(&o.AGC12_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC12_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC12_DIG_ENG_ATT_IF_2() uint32 {
	return volatile.LoadUint32(&o.AGC12_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC12_DIG_ENG_ATT_LNA_2(value uint32) {
	volatile.StoreUint32(&o.AGC12_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC12_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC12_DIG_ENG_ATT_LNA_2() uint32 {
	return (volatile.LoadUint32(&o.AGC12_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC12_DIG_ENG_ATT_ANT_2(value uint32) {
	volatile.StoreUint32(&o.AGC12_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC12_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC12_DIG_ENG_ATT_ANT_2() uint32 {
	return (volatile.LoadUint32(&o.AGC12_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC13_DIG_ENG: AGC13_DIG_ENG register
func (o *RADIO_Type) SetAGC13_DIG_ENG_ATT_IF_3(value uint32) {
	volatile.StoreUint32(&o.AGC13_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC13_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC13_DIG_ENG_ATT_IF_3() uint32 {
	return volatile.LoadUint32(&o.AGC13_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC13_DIG_ENG_ATT_LNA_3(value uint32) {
	volatile.StoreUint32(&o.AGC13_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC13_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC13_DIG_ENG_ATT_LNA_3() uint32 {
	return (volatile.LoadUint32(&o.AGC13_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC13_DIG_ENG_ATT_ANT_3(value uint32) {
	volatile.StoreUint32(&o.AGC13_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC13_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC13_DIG_ENG_ATT_ANT_3() uint32 {
	return (volatile.LoadUint32(&o.AGC13_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC14_DIG_ENG: AGC14_DIG_ENG register
func (o *RADIO_Type) SetAGC14_DIG_ENG_ATT_IF_4(value uint32) {
	volatile.StoreUint32(&o.AGC14_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC14_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC14_DIG_ENG_ATT_IF_4() uint32 {
	return volatile.LoadUint32(&o.AGC14_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC14_DIG_ENG_ATT_LNA_4(value uint32) {
	volatile.StoreUint32(&o.AGC14_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC14_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC14_DIG_ENG_ATT_LNA_4() uint32 {
	return (volatile.LoadUint32(&o.AGC14_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC14_DIG_ENG_ATT_ANT_4(value uint32) {
	volatile.StoreUint32(&o.AGC14_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC14_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC14_DIG_ENG_ATT_ANT_4() uint32 {
	return (volatile.LoadUint32(&o.AGC14_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC15_DIG_ENG: AGC15_DIG_ENG register
func (o *RADIO_Type) SetAGC15_DIG_ENG_ATT_IF_5(value uint32) {
	volatile.StoreUint32(&o.AGC15_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC15_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC15_DIG_ENG_ATT_IF_5() uint32 {
	return volatile.LoadUint32(&o.AGC15_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC15_DIG_ENG_ATT_LNA_5(value uint32) {
	volatile.StoreUint32(&o.AGC15_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC15_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC15_DIG_ENG_ATT_LNA_5() uint32 {
	return (volatile.LoadUint32(&o.AGC15_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC15_DIG_ENG_ATT_ANT_5(value uint32) {
	volatile.StoreUint32(&o.AGC15_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC15_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC15_DIG_ENG_ATT_ANT_5() uint32 {
	return (volatile.LoadUint32(&o.AGC15_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC16_DIG_ENG: AGC16_DIG_ENG register
func (o *RADIO_Type) SetAGC16_DIG_ENG_ATT_IF_6(value uint32) {
	volatile.StoreUint32(&o.AGC16_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC16_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC16_DIG_ENG_ATT_IF_6() uint32 {
	return volatile.LoadUint32(&o.AGC16_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC16_DIG_ENG_ATT_LNA_6(value uint32) {
	volatile.StoreUint32(&o.AGC16_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC16_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC16_DIG_ENG_ATT_LNA_6() uint32 {
	return (volatile.LoadUint32(&o.AGC16_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC16_DIG_ENG_ATT_ANT_6(value uint32) {
	volatile.StoreUint32(&o.AGC16_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC16_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC16_DIG_ENG_ATT_ANT_6() uint32 {
	return (volatile.LoadUint32(&o.AGC16_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC17_DIG_ENG: AGC17_DIG_ENG register
func (o *RADIO_Type) SetAGC17_DIG_ENG_ATT_IF_7(value uint32) {
	volatile.StoreUint32(&o.AGC17_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC17_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC17_DIG_ENG_ATT_IF_7() uint32 {
	return volatile.LoadUint32(&o.AGC17_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC17_DIG_ENG_ATT_LNA_7(value uint32) {
	volatile.StoreUint32(&o.AGC17_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC17_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC17_DIG_ENG_ATT_LNA_7() uint32 {
	return (volatile.LoadUint32(&o.AGC17_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC17_DIG_ENG_ATT_ANT_7(value uint32) {
	volatile.StoreUint32(&o.AGC17_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC17_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC17_DIG_ENG_ATT_ANT_7() uint32 {
	return (volatile.LoadUint32(&o.AGC17_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC18_DIG_ENG: AGC18_DIG_ENG register
func (o *RADIO_Type) SetAGC18_DIG_ENG_ATT_IF_8(value uint32) {
	volatile.StoreUint32(&o.AGC18_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC18_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC18_DIG_ENG_ATT_IF_8() uint32 {
	return volatile.LoadUint32(&o.AGC18_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC18_DIG_ENG_ATT_LNA_8(value uint32) {
	volatile.StoreUint32(&o.AGC18_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC18_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC18_DIG_ENG_ATT_LNA_8() uint32 {
	return (volatile.LoadUint32(&o.AGC18_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC18_DIG_ENG_ATT_ANT_8(value uint32) {
	volatile.StoreUint32(&o.AGC18_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC18_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC18_DIG_ENG_ATT_ANT_8() uint32 {
	return (volatile.LoadUint32(&o.AGC18_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.AGC19_DIG_ENG: AGC19_DIG_ENG register
func (o *RADIO_Type) SetAGC19_DIG_ENG_ATT_IF_9(value uint32) {
	volatile.StoreUint32(&o.AGC19_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC19_DIG_ENG.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetAGC19_DIG_ENG_ATT_IF_9() uint32 {
	return volatile.LoadUint32(&o.AGC19_DIG_ENG.Reg) & 0x7
}
func (o *RADIO_Type) SetAGC19_DIG_ENG_ATT_LNA_9(value uint32) {
	volatile.StoreUint32(&o.AGC19_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC19_DIG_ENG.Reg)&^(0x8)|value<<3)
}
func (o *RADIO_Type) GetAGC19_DIG_ENG_ATT_LNA_9() uint32 {
	return (volatile.LoadUint32(&o.AGC19_DIG_ENG.Reg) & 0x8) >> 3
}
func (o *RADIO_Type) SetAGC19_DIG_ENG_ATT_ANT_9(value uint32) {
	volatile.StoreUint32(&o.AGC19_DIG_ENG.Reg, volatile.LoadUint32(&o.AGC19_DIG_ENG.Reg)&^(0x30)|value<<4)
}
func (o *RADIO_Type) GetAGC19_DIG_ENG_ATT_ANT_9() uint32 {
	return (volatile.LoadUint32(&o.AGC19_DIG_ENG.Reg) & 0x30) >> 4
}

// RADIO.RXADC_HW_TRIM_OUT: RXADC_HW_TRIM_OUT register
func (o *RADIO_Type) SetRXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I(value uint32) {
	volatile.StoreUint32(&o.RXADC_HW_TRIM_OUT.Reg, volatile.LoadUint32(&o.RXADC_HW_TRIM_OUT.Reg)&^(0x7)|value)
}
func (o *RADIO_Type) GetRXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I() uint32 {
	return volatile.LoadUint32(&o.RXADC_HW_TRIM_OUT.Reg) & 0x7
}
func (o *RADIO_Type) SetRXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q(value uint32) {
	volatile.StoreUint32(&o.RXADC_HW_TRIM_OUT.Reg, volatile.LoadUint32(&o.RXADC_HW_TRIM_OUT.Reg)&^(0x38)|value<<3)
}
func (o *RADIO_Type) GetRXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q() uint32 {
	return (volatile.LoadUint32(&o.RXADC_HW_TRIM_OUT.Reg) & 0x38) >> 3
}

// RADIO.CBIAS0_HW_TRIM_OUT: CBIAS0_HW_TRIM_OUT register
func (o *RADIO_Type) SetCBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM(value uint32) {
	volatile.StoreUint32(&o.CBIAS0_HW_TRIM_OUT.Reg, volatile.LoadUint32(&o.CBIAS0_HW_TRIM_OUT.Reg)&^(0xf)|value)
}
func (o *RADIO_Type) GetCBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM() uint32 {
	return volatile.LoadUint32(&o.CBIAS0_HW_TRIM_OUT.Reg) & 0xf
}
func (o *RADIO_Type) SetCBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM(value uint32) {
	volatile.StoreUint32(&o.CBIAS0_HW_TRIM_OUT.Reg, volatile.LoadUint32(&o.CBIAS0_HW_TRIM_OUT.Reg)&^(0xf0)|value<<4)
}
func (o *RADIO_Type) GetCBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM() uint32 {
	return (volatile.LoadUint32(&o.CBIAS0_HW_TRIM_OUT.Reg) & 0xf0) >> 4
}

// RADIO.AGC_HW_TRIM_OUT: AGC_HW_TRIM_OUT register
func (o *RADIO_Type) SetAGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM(value uint32) {
	volatile.StoreUint32(&o.AGC_HW_TRIM_OUT.Reg, volatile.LoadUint32(&o.AGC_HW_TRIM_OUT.Reg)&^(0xe)|value<<1)
}
func (o *RADIO_Type) GetAGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM() uint32 {
	return (volatile.LoadUint32(&o.AGC_HW_TRIM_OUT.Reg) & 0xe) >> 1
}

// RADIO.DEMOD_IQ2_DIG_TST: DEMOD_IQ2_DIG_TST register
func (o *RADIO_Type) SetDEMOD_IQ2_DIG_TST_EXTCFG_SAMPLING_TIME(value uint32) {
	volatile.StoreUint32(&o.DEMOD_IQ2_DIG_TST.Reg, volatile.LoadUint32(&o.DEMOD_IQ2_DIG_TST.Reg)&^(0x3)|value)
}
func (o *RADIO_Type) GetDEMOD_IQ2_DIG_TST_EXTCFG_SAMPLING_TIME() uint32 {
	return volatile.LoadUint32(&o.DEMOD_IQ2_DIG_TST.Reg) & 0x3
}
func (o *RADIO_Type) SetDEMOD_IQ2_DIG_TST_EXTCFG_TRIG_SELECTION(value uint32) {
	volatile.StoreUint32(&o.DEMOD_IQ2_DIG_TST.Reg, volatile.LoadUint32(&o.DEMOD_IQ2_DIG_TST.Reg)&^(0xc)|value<<2)
}
func (o *RADIO_Type) GetDEMOD_IQ2_DIG_TST_EXTCFG_TRIG_SELECTION() uint32 {
	return (volatile.LoadUint32(&o.DEMOD_IQ2_DIG_TST.Reg) & 0xc) >> 2
}

// RADIO.ANTSW0_DIG_USR: ANTSW0_DIG_USR register
func (o *RADIO_Type) SetANTSW0_DIG_USR_RX_TIME_TO_SAMPLE(value uint32) {
	volatile.StoreUint32(&o.ANTSW0_DIG_USR.Reg, volatile.LoadUint32(&o.ANTSW0_DIG_USR.Reg)&^(0x7f)|value)
}
func (o *RADIO_Type) GetANTSW0_DIG_USR_RX_TIME_TO_SAMPLE() uint32 {
	return volatile.LoadUint32(&o.ANTSW0_DIG_USR.Reg) & 0x7f
}

// RADIO.ANTSW1_DIG_USR: ANTSW1_DIG_USR register
func (o *RADIO_Type) SetANTSW1_DIG_USR_RX_TIME_TO_SWITCH(value uint32) {
	volatile.StoreUint32(&o.ANTSW1_DIG_USR.Reg, volatile.LoadUint32(&o.ANTSW1_DIG_USR.Reg)&^(0x3f)|value)
}
func (o *RADIO_Type) GetANTSW1_DIG_USR_RX_TIME_TO_SWITCH() uint32 {
	return volatile.LoadUint32(&o.ANTSW1_DIG_USR.Reg) & 0x3f
}

// RADIO.ANTSW2_DIG_USR: ANTSW2_DIG_USR register
func (o *RADIO_Type) SetANTSW2_DIG_USR_TX_TIME_TO_SWITCH(value uint32) {
	volatile.StoreUint32(&o.ANTSW2_DIG_USR.Reg, volatile.LoadUint32(&o.ANTSW2_DIG_USR.Reg)&^(0x7f)|value)
}
func (o *RADIO_Type) GetANTSW2_DIG_USR_TX_TIME_TO_SWITCH() uint32 {
	return volatile.LoadUint32(&o.ANTSW2_DIG_USR.Reg) & 0x7f
}

// RADIO.ANTSW3_DIG_USR: ANTSW3_DIG_USR register
func (o *RADIO_Type) SetANTSW3_DIG_USR_TX_TIME_TO_SWITCH_2M(value uint32) {
	volatile.StoreUint32(&o.ANTSW3_DIG_USR.Reg, volatile.LoadUint32(&o.ANTSW3_DIG_USR.Reg)&^(0x7f)|value)
}
func (o *RADIO_Type) GetANTSW3_DIG_USR_TX_TIME_TO_SWITCH_2M() uint32 {
	return volatile.LoadUint32(&o.ANTSW3_DIG_USR.Reg) & 0x7f
}

type RRM_Type struct {
	_                  [16]byte
	UDRA_CTRL0         volatile.Register32 // 0x10
	UDRA_IRQ_ENABLE    volatile.Register32 // 0x14
	UDRA_IRQ_STATUS    volatile.Register32 // 0x18
	UDRA_RADIO_CFG_PTR volatile.Register32 // 0x1C
	SEMA_IRQ_ENABLE    volatile.Register32 // 0x20
	SEMA_IRQ_STATUS    volatile.Register32 // 0x24
	BLE_IRQ_ENABLE     volatile.Register32 // 0x28
	BLE_IRQ_STATUS     volatile.Register32 // 0x2C
	_                  [48]byte
	VP_CPU_CMD_BUS     volatile.Register32 // 0x60
	VP_CPU_SEMA_BUS    volatile.Register32 // 0x64
	VP_CPU_IRQ_ENABLE  volatile.Register32 // 0x68
	VP_CPU_IRQ_STATUS  volatile.Register32 // 0x6C
}

// RRM.UDRA_CTRL0: UDRA_CTRL0 register
func (o *RRM_Type) SetUDRA_CTRL0_RELOAD_RDCFGPTR(value uint32) {
	volatile.StoreUint32(&o.UDRA_CTRL0.Reg, volatile.LoadUint32(&o.UDRA_CTRL0.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetUDRA_CTRL0_RELOAD_RDCFGPTR() uint32 {
	return volatile.LoadUint32(&o.UDRA_CTRL0.Reg) & 0x1
}

// RRM.UDRA_IRQ_ENABLE: UDRA_IRQ_ENABLE register
func (o *RRM_Type) SetUDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED(value uint32) {
	volatile.StoreUint32(&o.UDRA_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.UDRA_IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetUDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED() uint32 {
	return volatile.LoadUint32(&o.UDRA_IRQ_ENABLE.Reg) & 0x1
}
func (o *RRM_Type) SetUDRA_IRQ_ENABLE_CMD_START(value uint32) {
	volatile.StoreUint32(&o.UDRA_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.UDRA_IRQ_ENABLE.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetUDRA_IRQ_ENABLE_CMD_START() uint32 {
	return (volatile.LoadUint32(&o.UDRA_IRQ_ENABLE.Reg) & 0x2) >> 1
}
func (o *RRM_Type) SetUDRA_IRQ_ENABLE_CMD_END(value uint32) {
	volatile.StoreUint32(&o.UDRA_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.UDRA_IRQ_ENABLE.Reg)&^(0x4)|value<<2)
}
func (o *RRM_Type) GetUDRA_IRQ_ENABLE_CMD_END() uint32 {
	return (volatile.LoadUint32(&o.UDRA_IRQ_ENABLE.Reg) & 0x4) >> 2
}

// RRM.UDRA_IRQ_STATUS: UDRA_IRQ_STATUS register
func (o *RRM_Type) SetUDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED(value uint32) {
	volatile.StoreUint32(&o.UDRA_IRQ_STATUS.Reg, volatile.LoadUint32(&o.UDRA_IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetUDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED() uint32 {
	return volatile.LoadUint32(&o.UDRA_IRQ_STATUS.Reg) & 0x1
}
func (o *RRM_Type) SetUDRA_IRQ_STATUS_CMD_STARD(value uint32) {
	volatile.StoreUint32(&o.UDRA_IRQ_STATUS.Reg, volatile.LoadUint32(&o.UDRA_IRQ_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetUDRA_IRQ_STATUS_CMD_STARD() uint32 {
	return (volatile.LoadUint32(&o.UDRA_IRQ_STATUS.Reg) & 0x2) >> 1
}
func (o *RRM_Type) SetUDRA_IRQ_STATUS_CMD_END(value uint32) {
	volatile.StoreUint32(&o.UDRA_IRQ_STATUS.Reg, volatile.LoadUint32(&o.UDRA_IRQ_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *RRM_Type) GetUDRA_IRQ_STATUS_CMD_END() uint32 {
	return (volatile.LoadUint32(&o.UDRA_IRQ_STATUS.Reg) & 0x4) >> 2
}

// RRM.UDRA_RADIO_CFG_PTR: UDRA_RADIO_CFG_PTR register
func (o *RRM_Type) SetUDRA_RADIO_CFG_PTR(value uint32) {
	volatile.StoreUint32(&o.UDRA_RADIO_CFG_PTR.Reg, value)
}
func (o *RRM_Type) GetUDRA_RADIO_CFG_PTR() uint32 {
	return volatile.LoadUint32(&o.UDRA_RADIO_CFG_PTR.Reg)
}

// RRM.SEMA_IRQ_ENABLE: SEMA_IRQ_ENABLE register
func (o *RRM_Type) SetSEMA_IRQ_ENABLE_LOCK(value uint32) {
	volatile.StoreUint32(&o.SEMA_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.SEMA_IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetSEMA_IRQ_ENABLE_LOCK() uint32 {
	return volatile.LoadUint32(&o.SEMA_IRQ_ENABLE.Reg) & 0x1
}
func (o *RRM_Type) SetSEMA_IRQ_ENABLE_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.SEMA_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.SEMA_IRQ_ENABLE.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetSEMA_IRQ_ENABLE_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.SEMA_IRQ_ENABLE.Reg) & 0x2) >> 1
}

// RRM.SEMA_IRQ_STATUS: SEMA_IRQ_STATUS register
func (o *RRM_Type) SetSEMA_IRQ_STATUS_LOCK(value uint32) {
	volatile.StoreUint32(&o.SEMA_IRQ_STATUS.Reg, volatile.LoadUint32(&o.SEMA_IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetSEMA_IRQ_STATUS_LOCK() uint32 {
	return volatile.LoadUint32(&o.SEMA_IRQ_STATUS.Reg) & 0x1
}
func (o *RRM_Type) SetSEMA_IRQ_STATUS_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.SEMA_IRQ_STATUS.Reg, volatile.LoadUint32(&o.SEMA_IRQ_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetSEMA_IRQ_STATUS_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.SEMA_IRQ_STATUS.Reg) & 0x2) >> 1
}

// RRM.BLE_IRQ_ENABLE: BLE_IRQ_ENABLE register
func (o *RRM_Type) SetBLE_IRQ_ENABLE_PORT_GRANT(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetBLE_IRQ_ENABLE_PORT_GRANT() uint32 {
	return volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg) & 0x1
}
func (o *RRM_Type) SetBLE_IRQ_ENABLE_PORT_RELEASE(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetBLE_IRQ_ENABLE_PORT_RELEASE() uint32 {
	return (volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg) & 0x2) >> 1
}
func (o *RRM_Type) SetBLE_IRQ_ENABLE_PORT_CMD_START(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg)&^(0x8)|value<<3)
}
func (o *RRM_Type) GetBLE_IRQ_ENABLE_PORT_CMD_START() uint32 {
	return (volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg) & 0x8) >> 3
}
func (o *RRM_Type) SetBLE_IRQ_ENABLE_PORT_CMD_END(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg)&^(0x10)|value<<4)
}
func (o *RRM_Type) GetBLE_IRQ_ENABLE_PORT_CMD_END() uint32 {
	return (volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg) & 0x10) >> 4
}

// RRM.BLE_IRQ_STATUS: BLE_IRQ_STATUS register
func (o *RRM_Type) SetBLE_IRQ_STATUS_PORT_GRANT(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_STATUS.Reg, volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetBLE_IRQ_STATUS_PORT_GRANT() uint32 {
	return volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg) & 0x1
}
func (o *RRM_Type) SetBLE_IRQ_STATUS_PORT_RELEASE(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_STATUS.Reg, volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetBLE_IRQ_STATUS_PORT_RELEASE() uint32 {
	return (volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg) & 0x2) >> 1
}
func (o *RRM_Type) SetBLE_IRQ_STATUS_CMD_START(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_STATUS.Reg, volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *RRM_Type) GetBLE_IRQ_STATUS_CMD_START() uint32 {
	return (volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg) & 0x8) >> 3
}
func (o *RRM_Type) SetBLE_IRQ_STATUS_CMD_END(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_STATUS.Reg, volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *RRM_Type) GetBLE_IRQ_STATUS_CMD_END() uint32 {
	return (volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg) & 0x10) >> 4
}

// RRM.VP_CPU_CMD_BUS: VP_CPU_CMD_BUS register
func (o *RRM_Type) SetVP_CPU_CMD_BUS_COMMAND(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_CMD_BUS.Reg, volatile.LoadUint32(&o.VP_CPU_CMD_BUS.Reg)&^(0x7)|value)
}
func (o *RRM_Type) GetVP_CPU_CMD_BUS_COMMAND() uint32 {
	return volatile.LoadUint32(&o.VP_CPU_CMD_BUS.Reg) & 0x7
}
func (o *RRM_Type) SetVP_CPU_CMD_BUS_COMMAND_REQ(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_CMD_BUS.Reg, volatile.LoadUint32(&o.VP_CPU_CMD_BUS.Reg)&^(0x8)|value<<3)
}
func (o *RRM_Type) GetVP_CPU_CMD_BUS_COMMAND_REQ() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_CMD_BUS.Reg) & 0x8) >> 3
}

// RRM.VP_CPU_SEMA_BUS: VP_CPU_SEMA_BUS register
func (o *RRM_Type) SetVP_CPU_SEMA_BUS_TAKE_PRIO(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_SEMA_BUS.Reg, volatile.LoadUint32(&o.VP_CPU_SEMA_BUS.Reg)&^(0x7)|value)
}
func (o *RRM_Type) GetVP_CPU_SEMA_BUS_TAKE_PRIO() uint32 {
	return volatile.LoadUint32(&o.VP_CPU_SEMA_BUS.Reg) & 0x7
}
func (o *RRM_Type) SetVP_CPU_SEMA_BUS_TAKE_REQ(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_SEMA_BUS.Reg, volatile.LoadUint32(&o.VP_CPU_SEMA_BUS.Reg)&^(0x8)|value<<3)
}
func (o *RRM_Type) GetVP_CPU_SEMA_BUS_TAKE_REQ() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_SEMA_BUS.Reg) & 0x8) >> 3
}

// RRM.VP_CPU_IRQ_ENABLE: VP_CPU_IRQ_ENABLE register
func (o *RRM_Type) SetVP_CPU_IRQ_ENABLE_PORT_GRANT(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetVP_CPU_IRQ_ENABLE_PORT_GRANT() uint32 {
	return volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg) & 0x1
}
func (o *RRM_Type) SetVP_CPU_IRQ_ENABLE_PORT_RELEASE(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetVP_CPU_IRQ_ENABLE_PORT_RELEASE() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg) & 0x2) >> 1
}
func (o *RRM_Type) SetVP_CPU_IRQ_ENABLE_PORT_CMD_START(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg)&^(0x8)|value<<3)
}
func (o *RRM_Type) GetVP_CPU_IRQ_ENABLE_PORT_CMD_START() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg) & 0x8) >> 3
}
func (o *RRM_Type) SetVP_CPU_IRQ_ENABLE_PORT_CMD_END(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg)&^(0x10)|value<<4)
}
func (o *RRM_Type) GetVP_CPU_IRQ_ENABLE_PORT_CMD_END() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_IRQ_ENABLE.Reg) & 0x10) >> 4
}

// RRM.VP_CPU_IRQ_STATUS: VP_CPU_IRQ_STATUS register
func (o *RRM_Type) SetVP_CPU_IRQ_STATUS_PORT_GRANT(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_STATUS.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *RRM_Type) GetVP_CPU_IRQ_STATUS_PORT_GRANT() uint32 {
	return volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg) & 0x1
}
func (o *RRM_Type) SetVP_CPU_IRQ_STATUS_PORT_RELEASE(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_STATUS.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg)&^(0x2)|value<<1)
}
func (o *RRM_Type) GetVP_CPU_IRQ_STATUS_PORT_RELEASE() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg) & 0x2) >> 1
}
func (o *RRM_Type) SetVP_CPU_IRQ_STATUS_PORT_PREEMPT(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_STATUS.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg)&^(0x4)|value<<2)
}
func (o *RRM_Type) GetVP_CPU_IRQ_STATUS_PORT_PREEMPT() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg) & 0x4) >> 2
}
func (o *RRM_Type) SetVP_CPU_IRQ_STATUS_CMD_START(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_STATUS.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg)&^(0x8)|value<<3)
}
func (o *RRM_Type) GetVP_CPU_IRQ_STATUS_CMD_START() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg) & 0x8) >> 3
}
func (o *RRM_Type) SetVP_CPU_IRQ_STATUS_CMD_END(value uint32) {
	volatile.StoreUint32(&o.VP_CPU_IRQ_STATUS.Reg, volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg)&^(0x10)|value<<4)
}
func (o *RRM_Type) GetVP_CPU_IRQ_STATUS_CMD_END() uint32 {
	return (volatile.LoadUint32(&o.VP_CPU_IRQ_STATUS.Reg) & 0x10) >> 4
}

type WAKEUP_Type struct {
	_                       [8]byte
	OFFSET                  volatile.Register32 // 0x8
	_                       [4]byte
	ABSOLUTE_TIME           volatile.Register32 // 0x10
	MINIMUM_PERIOD_LENGTH   volatile.Register32 // 0x14
	AVERAGE_PERIOD_LENGTH   volatile.Register32 // 0x18
	MAXIMUM_PERIOD_LENGTH   volatile.Register32 // 0x1C
	STATISTICS_RESTART      volatile.Register32 // 0x20
	BLUE_WAKEUP_TIME        volatile.Register32 // 0x24
	BLUE_SLEEP_REQUEST_MODE volatile.Register32 // 0x28
	CM0_WAKEUP_TIME         volatile.Register32 // 0x2C
	CM0_SLEEP_REQUEST_MODE  volatile.Register32 // 0x30
	_                       [12]byte
	BLE_IRQ_ENABLE          volatile.Register32 // 0x40
	BLE_IRQ_STATUS          volatile.Register32 // 0x44
	CM0_IRQ_ENABLE          volatile.Register32 // 0x48
	CM0_IRQ_STATUS          volatile.Register32 // 0x4C
}

// WAKEUP.OFFSET: WAKEUP_OFFSET register
func (o *WAKEUP_Type) SetOFFSET_WAKEUP_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFFSET.Reg, volatile.LoadUint32(&o.OFFSET.Reg)&^(0xff)|value)
}
func (o *WAKEUP_Type) GetOFFSET_WAKEUP_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFFSET.Reg) & 0xff
}

// WAKEUP.ABSOLUTE_TIME: ABSOLUTE_TIME register
func (o *WAKEUP_Type) SetABSOLUTE_TIME(value uint32) {
	volatile.StoreUint32(&o.ABSOLUTE_TIME.Reg, value)
}
func (o *WAKEUP_Type) GetABSOLUTE_TIME() uint32 {
	return volatile.LoadUint32(&o.ABSOLUTE_TIME.Reg)
}

// WAKEUP.MINIMUM_PERIOD_LENGTH: MINIMUM_PERIOD_LENGTH register
func (o *WAKEUP_Type) SetMINIMUM_PERIOD_LENGTH_LENGTH(value uint32) {
	volatile.StoreUint32(&o.MINIMUM_PERIOD_LENGTH.Reg, volatile.LoadUint32(&o.MINIMUM_PERIOD_LENGTH.Reg)&^(0x3ff0)|value<<4)
}
func (o *WAKEUP_Type) GetMINIMUM_PERIOD_LENGTH_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.MINIMUM_PERIOD_LENGTH.Reg) & 0x3ff0) >> 4
}

// WAKEUP.AVERAGE_PERIOD_LENGTH: AVERAGE_PERIOD_LENGTH register
func (o *WAKEUP_Type) SetAVERAGE_PERIOD_LENGTH_LENGTH_FRACT(value uint32) {
	volatile.StoreUint32(&o.AVERAGE_PERIOD_LENGTH.Reg, volatile.LoadUint32(&o.AVERAGE_PERIOD_LENGTH.Reg)&^(0xf)|value)
}
func (o *WAKEUP_Type) GetAVERAGE_PERIOD_LENGTH_LENGTH_FRACT() uint32 {
	return volatile.LoadUint32(&o.AVERAGE_PERIOD_LENGTH.Reg) & 0xf
}
func (o *WAKEUP_Type) SetAVERAGE_PERIOD_LENGTH_LENGTH_INT(value uint32) {
	volatile.StoreUint32(&o.AVERAGE_PERIOD_LENGTH.Reg, volatile.LoadUint32(&o.AVERAGE_PERIOD_LENGTH.Reg)&^(0x3ff0)|value<<4)
}
func (o *WAKEUP_Type) GetAVERAGE_PERIOD_LENGTH_LENGTH_INT() uint32 {
	return (volatile.LoadUint32(&o.AVERAGE_PERIOD_LENGTH.Reg) & 0x3ff0) >> 4
}
func (o *WAKEUP_Type) SetAVERAGE_PERIOD_LENGTH_AVERAGE_COUNT(value uint32) {
	volatile.StoreUint32(&o.AVERAGE_PERIOD_LENGTH.Reg, volatile.LoadUint32(&o.AVERAGE_PERIOD_LENGTH.Reg)&^(0xff000000)|value<<24)
}
func (o *WAKEUP_Type) GetAVERAGE_PERIOD_LENGTH_AVERAGE_COUNT() uint32 {
	return (volatile.LoadUint32(&o.AVERAGE_PERIOD_LENGTH.Reg) & 0xff000000) >> 24
}

// WAKEUP.MAXIMUM_PERIOD_LENGTH: MAXIMUM_PERIOD_LENGTH register
func (o *WAKEUP_Type) SetMAXIMUM_PERIOD_LENGTH_LENGTH(value uint32) {
	volatile.StoreUint32(&o.MAXIMUM_PERIOD_LENGTH.Reg, volatile.LoadUint32(&o.MAXIMUM_PERIOD_LENGTH.Reg)&^(0x3ff0)|value<<4)
}
func (o *WAKEUP_Type) GetMAXIMUM_PERIOD_LENGTH_LENGTH() uint32 {
	return (volatile.LoadUint32(&o.MAXIMUM_PERIOD_LENGTH.Reg) & 0x3ff0) >> 4
}

// WAKEUP.STATISTICS_RESTART: STATISTICS_RESTART register
func (o *WAKEUP_Type) SetSTATISTICS_RESTART_CLR_MIN_MAX(value uint32) {
	volatile.StoreUint32(&o.STATISTICS_RESTART.Reg, volatile.LoadUint32(&o.STATISTICS_RESTART.Reg)&^(0x1)|value)
}
func (o *WAKEUP_Type) GetSTATISTICS_RESTART_CLR_MIN_MAX() uint32 {
	return volatile.LoadUint32(&o.STATISTICS_RESTART.Reg) & 0x1
}
func (o *WAKEUP_Type) SetSTATISTICS_RESTART_CLR_AVR(value uint32) {
	volatile.StoreUint32(&o.STATISTICS_RESTART.Reg, volatile.LoadUint32(&o.STATISTICS_RESTART.Reg)&^(0x2)|value<<1)
}
func (o *WAKEUP_Type) GetSTATISTICS_RESTART_CLR_AVR() uint32 {
	return (volatile.LoadUint32(&o.STATISTICS_RESTART.Reg) & 0x2) >> 1
}

// WAKEUP.BLUE_WAKEUP_TIME: BLUE_WAKEUP_TIME register
func (o *WAKEUP_Type) SetBLUE_WAKEUP_TIME(value uint32) {
	volatile.StoreUint32(&o.BLUE_WAKEUP_TIME.Reg, value)
}
func (o *WAKEUP_Type) GetBLUE_WAKEUP_TIME() uint32 {
	return volatile.LoadUint32(&o.BLUE_WAKEUP_TIME.Reg)
}

// WAKEUP.BLUE_SLEEP_REQUEST_MODE: BLUE_SLEEP_REQUEST_MODE register
func (o *WAKEUP_Type) SetBLUE_SLEEP_REQUEST_MODE_SLEEP_EN(value uint32) {
	volatile.StoreUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg, volatile.LoadUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg)&^(0x20000000)|value<<29)
}
func (o *WAKEUP_Type) GetBLUE_SLEEP_REQUEST_MODE_SLEEP_EN() uint32 {
	return (volatile.LoadUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg) & 0x20000000) >> 29
}
func (o *WAKEUP_Type) SetBLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg, volatile.LoadUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg)&^(0x40000000)|value<<30)
}
func (o *WAKEUP_Type) GetBLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg) & 0x40000000) >> 30
}
func (o *WAKEUP_Type) SetBLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING(value uint32) {
	volatile.StoreUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg, volatile.LoadUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg)&^(0x80000000)|value<<31)
}
func (o *WAKEUP_Type) GetBLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING() uint32 {
	return (volatile.LoadUint32(&o.BLUE_SLEEP_REQUEST_MODE.Reg) & 0x80000000) >> 31
}

// WAKEUP.CM0_WAKEUP_TIME: CM0_WAKEUP_TIME register
func (o *WAKEUP_Type) SetCM0_WAKEUP_TIME_WAKEUP_TIME(value uint32) {
	volatile.StoreUint32(&o.CM0_WAKEUP_TIME.Reg, volatile.LoadUint32(&o.CM0_WAKEUP_TIME.Reg)&^(0xfffffff0)|value<<4)
}
func (o *WAKEUP_Type) GetCM0_WAKEUP_TIME_WAKEUP_TIME() uint32 {
	return (volatile.LoadUint32(&o.CM0_WAKEUP_TIME.Reg) & 0xfffffff0) >> 4
}

// WAKEUP.CM0_SLEEP_REQUEST_MODE: CM0_SLEEP_REQUEST_MODE register
func (o *WAKEUP_Type) SetCM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN(value uint32) {
	volatile.StoreUint32(&o.CM0_SLEEP_REQUEST_MODE.Reg, volatile.LoadUint32(&o.CM0_SLEEP_REQUEST_MODE.Reg)&^(0x40000000)|value<<30)
}
func (o *WAKEUP_Type) GetCM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN() uint32 {
	return (volatile.LoadUint32(&o.CM0_SLEEP_REQUEST_MODE.Reg) & 0x40000000) >> 30
}
func (o *WAKEUP_Type) SetCM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING(value uint32) {
	volatile.StoreUint32(&o.CM0_SLEEP_REQUEST_MODE.Reg, volatile.LoadUint32(&o.CM0_SLEEP_REQUEST_MODE.Reg)&^(0x80000000)|value<<31)
}
func (o *WAKEUP_Type) GetCM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING() uint32 {
	return (volatile.LoadUint32(&o.CM0_SLEEP_REQUEST_MODE.Reg) & 0x80000000) >> 31
}

// WAKEUP.BLE_IRQ_ENABLE: WAKEUP_BLE_IRQ_ENABLE register
func (o *WAKEUP_Type) SetBLE_IRQ_ENABLE_WAKEUP_IT(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *WAKEUP_Type) GetBLE_IRQ_ENABLE_WAKEUP_IT() uint32 {
	return volatile.LoadUint32(&o.BLE_IRQ_ENABLE.Reg) & 0x1
}

// WAKEUP.BLE_IRQ_STATUS: WAKEUP_BLE_IRQ_STATUS register
func (o *WAKEUP_Type) SetBLE_IRQ_STATUS_WAKEUP_IT(value uint32) {
	volatile.StoreUint32(&o.BLE_IRQ_STATUS.Reg, volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *WAKEUP_Type) GetBLE_IRQ_STATUS_WAKEUP_IT() uint32 {
	return volatile.LoadUint32(&o.BLE_IRQ_STATUS.Reg) & 0x1
}

// WAKEUP.CM0_IRQ_ENABLE: WAKEUP_CM0_IRQ_ENABLE register
func (o *WAKEUP_Type) SetCM0_IRQ_ENABLE_WAKEUP_IT(value uint32) {
	volatile.StoreUint32(&o.CM0_IRQ_ENABLE.Reg, volatile.LoadUint32(&o.CM0_IRQ_ENABLE.Reg)&^(0x1)|value)
}
func (o *WAKEUP_Type) GetCM0_IRQ_ENABLE_WAKEUP_IT() uint32 {
	return volatile.LoadUint32(&o.CM0_IRQ_ENABLE.Reg) & 0x1
}

// WAKEUP.CM0_IRQ_STATUS: WAKEUP_CM0_IRQ_STATUS register
func (o *WAKEUP_Type) SetCM0_IRQ_STATUS_WAKEUP_IT(value uint32) {
	volatile.StoreUint32(&o.CM0_IRQ_STATUS.Reg, volatile.LoadUint32(&o.CM0_IRQ_STATUS.Reg)&^(0x1)|value)
}
func (o *WAKEUP_Type) GetCM0_IRQ_STATUS_WAKEUP_IT() uint32 {
	return volatile.LoadUint32(&o.CM0_IRQ_STATUS.Reg) & 0x1
}

// Constants for ADC
const (
	// VERSION_ID: VERSION_ID register
	// Position of VERSION_ID field.
	ADC_VERSION_ID_VERSION_ID_Pos = 0x0
	// Bit mask of VERSION_ID field.
	ADC_VERSION_ID_VERSION_ID_Msk = 0xff

	// CONF: CONF register
	// Position of CONT field.
	ADC_CONF_CONT_Pos = 0x0
	// Bit mask of CONT field.
	ADC_CONF_CONT_Msk = 0x1
	// Bit CONT.
	ADC_CONF_CONT = 0x1
	// Position of SEQUENCE field.
	ADC_CONF_SEQUENCE_Pos = 0x1
	// Bit mask of SEQUENCE field.
	ADC_CONF_SEQUENCE_Msk = 0x2
	// Bit SEQUENCE.
	ADC_CONF_SEQUENCE = 0x2
	// Position of SEQ_LEN field.
	ADC_CONF_SEQ_LEN_Pos = 0x2
	// Bit mask of SEQ_LEN field.
	ADC_CONF_SEQ_LEN_Msk = 0x3c
	// Position of SMPS_SYNCHRO_ENA field.
	ADC_CONF_SMPS_SYNCHRO_ENA_Pos = 0x6
	// Bit mask of SMPS_SYNCHRO_ENA field.
	ADC_CONF_SMPS_SYNCHRO_ENA_Msk = 0x40
	// Bit SMPS_SYNCHRO_ENA.
	ADC_CONF_SMPS_SYNCHRO_ENA = 0x40
	// Position of SAMPLE_RATE_LSB field.
	ADC_CONF_SAMPLE_RATE_LSB_Pos = 0x9
	// Bit mask of SAMPLE_RATE_LSB field.
	ADC_CONF_SAMPLE_RATE_LSB_Msk = 0x600
	// Position of SAMPLE_RATE field.
	ADC_CONF_SAMPLE_RATE_Pos = 0xb
	// Bit mask of SAMPLE_RATE field.
	ADC_CONF_SAMPLE_RATE_Msk = 0x1800
	// Position of DMA_DS_ENA field.
	ADC_CONF_DMA_DS_ENA_Pos = 0xd
	// Bit mask of DMA_DS_ENA field.
	ADC_CONF_DMA_DS_ENA_Msk = 0x2000
	// Bit DMA_DS_ENA.
	ADC_CONF_DMA_DS_ENA = 0x2000
	// Position of OVR_DS_CFG field.
	ADC_CONF_OVR_DS_CFG_Pos = 0xf
	// Bit mask of OVR_DS_CFG field.
	ADC_CONF_OVR_DS_CFG_Msk = 0x8000
	// Bit OVR_DS_CFG.
	ADC_CONF_OVR_DS_CFG = 0x8000
	// Position of BIT_INVERT_SN field.
	ADC_CONF_BIT_INVERT_SN_Pos = 0x11
	// Bit mask of BIT_INVERT_SN field.
	ADC_CONF_BIT_INVERT_SN_Msk = 0x20000
	// Bit BIT_INVERT_SN.
	ADC_CONF_BIT_INVERT_SN = 0x20000
	// Position of BIT_INVERT_DIFF field.
	ADC_CONF_BIT_INVERT_DIFF_Pos = 0x12
	// Bit mask of BIT_INVERT_DIFF field.
	ADC_CONF_BIT_INVERT_DIFF_Msk = 0x40000
	// Bit BIT_INVERT_DIFF.
	ADC_CONF_BIT_INVERT_DIFF = 0x40000
	// Position of ADC_CONT_1V2 field.
	ADC_CONF_ADC_CONT_1V2_Pos = 0x13
	// Bit mask of ADC_CONT_1V2 field.
	ADC_CONF_ADC_CONT_1V2_Msk = 0x80000
	// Bit ADC_CONT_1V2.
	ADC_CONF_ADC_CONT_1V2 = 0x80000
	// Position of SAMPLE_RATE_MSB field.
	ADC_CONF_SAMPLE_RATE_MSB_Pos = 0x15
	// Bit mask of SAMPLE_RATE_MSB field.
	ADC_CONF_SAMPLE_RATE_MSB_Msk = 0xe00000

	// CTRL: CTRL register
	// Position of ADC_ON_OFF field.
	ADC_CTRL_ADC_ON_OFF_Pos = 0x0
	// Bit mask of ADC_ON_OFF field.
	ADC_CTRL_ADC_ON_OFF_Msk = 0x1
	// Bit ADC_ON_OFF.
	ADC_CTRL_ADC_ON_OFF = 0x1
	// Position of START_CONV field.
	ADC_CTRL_START_CONV_Pos = 0x1
	// Bit mask of START_CONV field.
	ADC_CTRL_START_CONV_Msk = 0x2
	// Bit START_CONV.
	ADC_CTRL_START_CONV = 0x2
	// Position of STOP_OP_MODE field.
	ADC_CTRL_STOP_OP_MODE_Pos = 0x2
	// Bit mask of STOP_OP_MODE field.
	ADC_CTRL_STOP_OP_MODE_Msk = 0x4
	// Bit STOP_OP_MODE.
	ADC_CTRL_STOP_OP_MODE = 0x4
	// Position of TEST_MODE field.
	ADC_CTRL_TEST_MODE_Pos = 0x4
	// Bit mask of TEST_MODE field.
	ADC_CTRL_TEST_MODE_Msk = 0x10
	// Bit TEST_MODE.
	ADC_CTRL_TEST_MODE = 0x10
	// Position of ADC_LDO_ENA field.
	ADC_CTRL_ADC_LDO_ENA_Pos = 0x5
	// Bit mask of ADC_LDO_ENA field.
	ADC_CTRL_ADC_LDO_ENA_Msk = 0x20
	// Bit ADC_LDO_ENA.
	ADC_CTRL_ADC_LDO_ENA = 0x20

	// SWITCH: SWITCH register
	// Position of SE_VIN_0 field.
	ADC_SWITCH_SE_VIN_0_Pos = 0x0
	// Bit mask of SE_VIN_0 field.
	ADC_SWITCH_SE_VIN_0_Msk = 0x3
	// Position of SE_VIN_1 field.
	ADC_SWITCH_SE_VIN_1_Pos = 0x2
	// Bit mask of SE_VIN_1 field.
	ADC_SWITCH_SE_VIN_1_Msk = 0xc
	// Position of SE_VIN_2 field.
	ADC_SWITCH_SE_VIN_2_Pos = 0x4
	// Bit mask of SE_VIN_2 field.
	ADC_SWITCH_SE_VIN_2_Msk = 0x30
	// Position of SE_VIN_3 field.
	ADC_SWITCH_SE_VIN_3_Pos = 0x6
	// Bit mask of SE_VIN_3 field.
	ADC_SWITCH_SE_VIN_3_Msk = 0xc0
	// Position of SE_VIN_4 field.
	ADC_SWITCH_SE_VIN_4_Pos = 0x8
	// Bit mask of SE_VIN_4 field.
	ADC_SWITCH_SE_VIN_4_Msk = 0x300
	// Position of SE_VIN_5 field.
	ADC_SWITCH_SE_VIN_5_Pos = 0xa
	// Bit mask of SE_VIN_5 field.
	ADC_SWITCH_SE_VIN_5_Msk = 0xc00
	// Position of SE_VIN_6 field.
	ADC_SWITCH_SE_VIN_6_Pos = 0xc
	// Bit mask of SE_VIN_6 field.
	ADC_SWITCH_SE_VIN_6_Msk = 0x3000
	// Position of SE_VIN_7 field.
	ADC_SWITCH_SE_VIN_7_Pos = 0xe
	// Bit mask of SE_VIN_7 field.
	ADC_SWITCH_SE_VIN_7_Msk = 0xc000

	// DS_CONF: DS_CONF register
	// Position of DS_RATIO field.
	ADC_DS_CONF_DS_RATIO_Pos = 0x0
	// Bit mask of DS_RATIO field.
	ADC_DS_CONF_DS_RATIO_Msk = 0x7
	// Position of DS_WIDTH field.
	ADC_DS_CONF_DS_WIDTH_Pos = 0x3
	// Bit mask of DS_WIDTH field.
	ADC_DS_CONF_DS_WIDTH_Msk = 0x38

	// SEQ_1: SEQ_1 register
	// Position of SEQ0 field.
	ADC_SEQ_1_SEQ0_Pos = 0x0
	// Bit mask of SEQ0 field.
	ADC_SEQ_1_SEQ0_Msk = 0xf
	// Position of SEQ1 field.
	ADC_SEQ_1_SEQ1_Pos = 0x4
	// Bit mask of SEQ1 field.
	ADC_SEQ_1_SEQ1_Msk = 0xf0
	// Position of SEQ2 field.
	ADC_SEQ_1_SEQ2_Pos = 0x8
	// Bit mask of SEQ2 field.
	ADC_SEQ_1_SEQ2_Msk = 0xf00
	// Position of SEQ3 field.
	ADC_SEQ_1_SEQ3_Pos = 0xc
	// Bit mask of SEQ3 field.
	ADC_SEQ_1_SEQ3_Msk = 0xf000
	// Position of SEQ4 field.
	ADC_SEQ_1_SEQ4_Pos = 0x10
	// Bit mask of SEQ4 field.
	ADC_SEQ_1_SEQ4_Msk = 0xf0000
	// Position of SEQ5 field.
	ADC_SEQ_1_SEQ5_Pos = 0x14
	// Bit mask of SEQ5 field.
	ADC_SEQ_1_SEQ5_Msk = 0xf00000
	// Position of SEQ6 field.
	ADC_SEQ_1_SEQ6_Pos = 0x18
	// Bit mask of SEQ6 field.
	ADC_SEQ_1_SEQ6_Msk = 0xf000000
	// Position of SEQ7 field.
	ADC_SEQ_1_SEQ7_Pos = 0x1c
	// Bit mask of SEQ7 field.
	ADC_SEQ_1_SEQ7_Msk = 0xf0000000

	// SEQ_2: SEQ_2 register
	// Position of SEQ8 field.
	ADC_SEQ_2_SEQ8_Pos = 0x0
	// Bit mask of SEQ8 field.
	ADC_SEQ_2_SEQ8_Msk = 0xf
	// Position of SEQ9 field.
	ADC_SEQ_2_SEQ9_Pos = 0x4
	// Bit mask of SEQ9 field.
	ADC_SEQ_2_SEQ9_Msk = 0xf0
	// Position of SEQ10 field.
	ADC_SEQ_2_SEQ10_Pos = 0x8
	// Bit mask of SEQ10 field.
	ADC_SEQ_2_SEQ10_Msk = 0xf00
	// Position of SEQ11 field.
	ADC_SEQ_2_SEQ11_Pos = 0xc
	// Bit mask of SEQ11 field.
	ADC_SEQ_2_SEQ11_Msk = 0xf000
	// Position of SEQ12 field.
	ADC_SEQ_2_SEQ12_Pos = 0x10
	// Bit mask of SEQ12 field.
	ADC_SEQ_2_SEQ12_Msk = 0xf0000
	// Position of SEQ13 field.
	ADC_SEQ_2_SEQ13_Pos = 0x14
	// Bit mask of SEQ13 field.
	ADC_SEQ_2_SEQ13_Msk = 0xf00000
	// Position of SEQ14 field.
	ADC_SEQ_2_SEQ14_Pos = 0x18
	// Bit mask of SEQ14 field.
	ADC_SEQ_2_SEQ14_Msk = 0xf000000
	// Position of SEQ15 field.
	ADC_SEQ_2_SEQ15_Pos = 0x1c
	// Bit mask of SEQ15 field.
	ADC_SEQ_2_SEQ15_Msk = 0xf0000000

	// COMP_1: COMP_1 register
	// Position of GAIN1 field.
	ADC_COMP_1_GAIN1_Pos = 0x0
	// Bit mask of GAIN1 field.
	ADC_COMP_1_GAIN1_Msk = 0xfff
	// Position of OFFSET1 field.
	ADC_COMP_1_OFFSET1_Pos = 0xc
	// Bit mask of OFFSET1 field.
	ADC_COMP_1_OFFSET1_Msk = 0xff000

	// COMP_2: COMP_2 register
	// Position of GAIN2 field.
	ADC_COMP_2_GAIN2_Pos = 0x0
	// Bit mask of GAIN2 field.
	ADC_COMP_2_GAIN2_Msk = 0xfff
	// Position of OFFSET2 field.
	ADC_COMP_2_OFFSET2_Pos = 0xc
	// Bit mask of OFFSET2 field.
	ADC_COMP_2_OFFSET2_Msk = 0xff000

	// COMP_3: COMP_3 register
	// Position of GAIN3 field.
	ADC_COMP_3_GAIN3_Pos = 0x0
	// Bit mask of GAIN3 field.
	ADC_COMP_3_GAIN3_Msk = 0xfff
	// Position of OFFSET3 field.
	ADC_COMP_3_OFFSET3_Pos = 0xc
	// Bit mask of OFFSET3 field.
	ADC_COMP_3_OFFSET3_Msk = 0xff000

	// COMP_4: COMP_4 register
	// Position of GAIN4 field.
	ADC_COMP_4_GAIN4_Pos = 0x0
	// Bit mask of GAIN4 field.
	ADC_COMP_4_GAIN4_Msk = 0xfff
	// Position of OFFSET4 field.
	ADC_COMP_4_OFFSET4_Pos = 0xc
	// Bit mask of OFFSET4 field.
	ADC_COMP_4_OFFSET4_Msk = 0xff000

	// COMP_SEL: COMP_SEL register
	// Position of OFFSET_GAIN0 field.
	ADC_COMP_SEL_OFFSET_GAIN0_Pos = 0x0
	// Bit mask of OFFSET_GAIN0 field.
	ADC_COMP_SEL_OFFSET_GAIN0_Msk = 0x3
	// Position of OFFSET_GAIN1 field.
	ADC_COMP_SEL_OFFSET_GAIN1_Pos = 0x2
	// Bit mask of OFFSET_GAIN1 field.
	ADC_COMP_SEL_OFFSET_GAIN1_Msk = 0xc
	// Position of OFFSET_GAIN2 field.
	ADC_COMP_SEL_OFFSET_GAIN2_Pos = 0x4
	// Bit mask of OFFSET_GAIN2 field.
	ADC_COMP_SEL_OFFSET_GAIN2_Msk = 0x30
	// Position of OFFSET_GAIN3 field.
	ADC_COMP_SEL_OFFSET_GAIN3_Pos = 0x6
	// Bit mask of OFFSET_GAIN3 field.
	ADC_COMP_SEL_OFFSET_GAIN3_Msk = 0xc0
	// Position of OFFSET_GAIN4 field.
	ADC_COMP_SEL_OFFSET_GAIN4_Pos = 0x8
	// Bit mask of OFFSET_GAIN4 field.
	ADC_COMP_SEL_OFFSET_GAIN4_Msk = 0x300
	// Position of OFFSET_GAIN5 field.
	ADC_COMP_SEL_OFFSET_GAIN5_Pos = 0xa
	// Bit mask of OFFSET_GAIN5 field.
	ADC_COMP_SEL_OFFSET_GAIN5_Msk = 0xc00
	// Position of OFFSET_GAIN6 field.
	ADC_COMP_SEL_OFFSET_GAIN6_Pos = 0xc
	// Bit mask of OFFSET_GAIN6 field.
	ADC_COMP_SEL_OFFSET_GAIN6_Msk = 0x3000
	// Position of OFFSET_GAIN7 field.
	ADC_COMP_SEL_OFFSET_GAIN7_Pos = 0xe
	// Bit mask of OFFSET_GAIN7 field.
	ADC_COMP_SEL_OFFSET_GAIN7_Msk = 0xc000
	// Position of OFFSET_GAIN8 field.
	ADC_COMP_SEL_OFFSET_GAIN8_Pos = 0x10
	// Bit mask of OFFSET_GAIN8 field.
	ADC_COMP_SEL_OFFSET_GAIN8_Msk = 0x30000

	// WD_TH: WD_TH register
	// Position of WD_LT field.
	ADC_WD_TH_WD_LT_Pos = 0x0
	// Bit mask of WD_LT field.
	ADC_WD_TH_WD_LT_Msk = 0xfff
	// Position of WD_HT field.
	ADC_WD_TH_WD_HT_Pos = 0x10
	// Bit mask of WD_HT field.
	ADC_WD_TH_WD_HT_Msk = 0xfff0000

	// WD_CONF: WD_CONF register
	// Position of AWD_CHX field.
	ADC_WD_CONF_AWD_CHX_Pos = 0x0
	// Bit mask of AWD_CHX field.
	ADC_WD_CONF_AWD_CHX_Msk = 0xffff

	// DS_DATAOUT: DS_DATAOUT register
	// Position of DS_DATA field.
	ADC_DS_DATAOUT_DS_DATA_Pos = 0x0
	// Bit mask of DS_DATA field.
	ADC_DS_DATAOUT_DS_DATA_Msk = 0xffff

	// IRQ_STATUS: IRQ_STATUS register
	// Position of EOC_IRQ field.
	ADC_IRQ_STATUS_EOC_IRQ_Pos = 0x0
	// Bit mask of EOC_IRQ field.
	ADC_IRQ_STATUS_EOC_IRQ_Msk = 0x1
	// Bit EOC_IRQ.
	ADC_IRQ_STATUS_EOC_IRQ = 0x1
	// Position of EODS_IRQ field.
	ADC_IRQ_STATUS_EODS_IRQ_Pos = 0x1
	// Bit mask of EODS_IRQ field.
	ADC_IRQ_STATUS_EODS_IRQ_Msk = 0x2
	// Bit EODS_IRQ.
	ADC_IRQ_STATUS_EODS_IRQ = 0x2
	// Position of EOS_IRQ field.
	ADC_IRQ_STATUS_EOS_IRQ_Pos = 0x3
	// Bit mask of EOS_IRQ field.
	ADC_IRQ_STATUS_EOS_IRQ_Msk = 0x8
	// Bit EOS_IRQ.
	ADC_IRQ_STATUS_EOS_IRQ = 0x8
	// Position of AWD_IRQ field.
	ADC_IRQ_STATUS_AWD_IRQ_Pos = 0x4
	// Bit mask of AWD_IRQ field.
	ADC_IRQ_STATUS_AWD_IRQ_Msk = 0x10
	// Bit AWD_IRQ.
	ADC_IRQ_STATUS_AWD_IRQ = 0x10
	// Position of OVR_DS_IRQ field.
	ADC_IRQ_STATUS_OVR_DS_IRQ_Pos = 0x5
	// Bit mask of OVR_DS_IRQ field.
	ADC_IRQ_STATUS_OVR_DS_IRQ_Msk = 0x20
	// Bit OVR_DS_IRQ.
	ADC_IRQ_STATUS_OVR_DS_IRQ = 0x20

	// IRQ_ENABLE: IRQ_ENABLE register
	// Position of EOC_IRQ field.
	ADC_IRQ_ENABLE_EOC_IRQ_Pos = 0x0
	// Bit mask of EOC_IRQ field.
	ADC_IRQ_ENABLE_EOC_IRQ_Msk = 0x1
	// Bit EOC_IRQ.
	ADC_IRQ_ENABLE_EOC_IRQ = 0x1
	// Position of EODS_IRQ field.
	ADC_IRQ_ENABLE_EODS_IRQ_Pos = 0x1
	// Bit mask of EODS_IRQ field.
	ADC_IRQ_ENABLE_EODS_IRQ_Msk = 0x2
	// Bit EODS_IRQ.
	ADC_IRQ_ENABLE_EODS_IRQ = 0x2
	// Position of EOS_IRQ field.
	ADC_IRQ_ENABLE_EOS_IRQ_Pos = 0x3
	// Bit mask of EOS_IRQ field.
	ADC_IRQ_ENABLE_EOS_IRQ_Msk = 0x8
	// Bit EOS_IRQ.
	ADC_IRQ_ENABLE_EOS_IRQ = 0x8
	// Position of AWD_IRQ field.
	ADC_IRQ_ENABLE_AWD_IRQ_Pos = 0x4
	// Bit mask of AWD_IRQ field.
	ADC_IRQ_ENABLE_AWD_IRQ_Msk = 0x10
	// Bit AWD_IRQ.
	ADC_IRQ_ENABLE_AWD_IRQ = 0x10
	// Position of OVR_DS_IRQ field.
	ADC_IRQ_ENABLE_OVR_DS_IRQ_Pos = 0x5
	// Bit mask of OVR_DS_IRQ field.
	ADC_IRQ_ENABLE_OVR_DS_IRQ_Msk = 0x20
	// Bit OVR_DS_IRQ.
	ADC_IRQ_ENABLE_OVR_DS_IRQ = 0x20
)

// Constants for CRC: CRC address block description
const (
	// DR: CRC data register
	// Position of DR field.
	CRC_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	CRC_DR_DR_Msk = 0xffffffff

	// DR8: Data register - byte sized
	// Position of DR8 field.
	CRC_DR8_DR8_Pos = 0x0
	// Bit mask of DR8 field.
	CRC_DR8_DR8_Msk = 0xff

	// DR16: Data register - half-word sized
	// Position of DR16 field.
	CRC_DR16_DR16_Pos = 0x0
	// Bit mask of DR16 field.
	CRC_DR16_DR16_Msk = 0xffff

	// IDR: CRC independent data register
	// Position of IDR field.
	CRC_IDR_IDR_Pos = 0x0
	// Bit mask of IDR field.
	CRC_IDR_IDR_Msk = 0xffffffff

	// CR: CRC control register
	// Position of RESET field.
	CRC_CR_RESET_Pos = 0x0
	// Bit mask of RESET field.
	CRC_CR_RESET_Msk = 0x1
	// Bit RESET.
	CRC_CR_RESET = 0x1
	// Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
	CRC_CR_RESET_Reset = 0x1
	// Position of POLYSIZE field.
	CRC_CR_POLYSIZE_Pos = 0x3
	// Bit mask of POLYSIZE field.
	CRC_CR_POLYSIZE_Msk = 0x18
	// 32-bit polynomial
	CRC_CR_POLYSIZE_Polysize32 = 0x0
	// 16-bit polynomial
	CRC_CR_POLYSIZE_Polysize16 = 0x1
	// 8-bit polynomial
	CRC_CR_POLYSIZE_Polysize8 = 0x2
	// 7-bit polynomial
	CRC_CR_POLYSIZE_Polysize7 = 0x3
	// Position of REV_IN field.
	CRC_CR_REV_IN_Pos = 0x5
	// Bit mask of REV_IN field.
	CRC_CR_REV_IN_Msk = 0x60
	// Bit order not affected
	CRC_CR_REV_IN_Normal = 0x0
	// Bit reversal done by byte
	CRC_CR_REV_IN_Byte = 0x1
	// Bit reversal done by half-word
	CRC_CR_REV_IN_HalfWord = 0x2
	// Bit reversal done by word
	CRC_CR_REV_IN_Word = 0x3
	// Position of REV_OUT field.
	CRC_CR_REV_OUT_Pos = 0x7
	// Bit mask of REV_OUT field.
	CRC_CR_REV_OUT_Msk = 0x80
	// Bit REV_OUT.
	CRC_CR_REV_OUT = 0x80
	// Bit order not affected
	CRC_CR_REV_OUT_Normal = 0x0
	// Bit reversed output
	CRC_CR_REV_OUT_Reversed = 0x1

	// INIT: CRC initial value
	// Position of INIT field.
	CRC_INIT_INIT_Pos = 0x0
	// Bit mask of INIT field.
	CRC_INIT_INIT_Msk = 0xffffffff

	// POL: CRC polynomial
	// Position of POL field.
	CRC_POL_POL_Pos = 0x0
	// Bit mask of POL field.
	CRC_POL_POL_Msk = 0xffffffff
)

// Constants for DMA
const (
	// ISR: DMA_ISR register
	// Position of GIF1 field.
	DMA_ISR_GIF1_Pos = 0x4
	// Bit mask of GIF1 field.
	DMA_ISR_GIF1_Msk = 0x10
	// Bit GIF1.
	DMA_ISR_GIF1 = 0x10
	// No transfer error, half event, complete event
	DMA_ISR_GIF1_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF1_Event = 0x1
	// Position of GIF2 field.
	DMA_ISR_GIF2_Pos = 0x8
	// Bit mask of GIF2 field.
	DMA_ISR_GIF2_Msk = 0x100
	// Bit GIF2.
	DMA_ISR_GIF2 = 0x100
	// No transfer error, half event, complete event
	DMA_ISR_GIF2_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF2_Event = 0x1
	// Position of GIF3 field.
	DMA_ISR_GIF3_Pos = 0xc
	// Bit mask of GIF3 field.
	DMA_ISR_GIF3_Msk = 0x1000
	// Bit GIF3.
	DMA_ISR_GIF3 = 0x1000
	// No transfer error, half event, complete event
	DMA_ISR_GIF3_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF3_Event = 0x1
	// Position of GIF4 field.
	DMA_ISR_GIF4_Pos = 0x10
	// Bit mask of GIF4 field.
	DMA_ISR_GIF4_Msk = 0x10000
	// Bit GIF4.
	DMA_ISR_GIF4 = 0x10000
	// No transfer error, half event, complete event
	DMA_ISR_GIF4_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF4_Event = 0x1
	// Position of GIF5 field.
	DMA_ISR_GIF5_Pos = 0x14
	// Bit mask of GIF5 field.
	DMA_ISR_GIF5_Msk = 0x100000
	// Bit GIF5.
	DMA_ISR_GIF5 = 0x100000
	// No transfer error, half event, complete event
	DMA_ISR_GIF5_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF5_Event = 0x1
	// Position of GIF6 field.
	DMA_ISR_GIF6_Pos = 0x18
	// Bit mask of GIF6 field.
	DMA_ISR_GIF6_Msk = 0x1000000
	// Bit GIF6.
	DMA_ISR_GIF6 = 0x1000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF6_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF6_Event = 0x1
	// Position of GIF7 field.
	DMA_ISR_GIF7_Pos = 0x1c
	// Bit mask of GIF7 field.
	DMA_ISR_GIF7_Msk = 0x10000000
	// Bit GIF7.
	DMA_ISR_GIF7 = 0x10000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF7_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF7_Event = 0x1
	// Position of GIF8 field.
	DMA_ISR_GIF8_Pos = 0x20
	// Bit mask of GIF8 field.
	DMA_ISR_GIF8_Msk = 0x100000000
	// Bit GIF8.
	DMA_ISR_GIF8 = 0x100000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF8_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF8_Event = 0x1
	// Position of TCIF1 field.
	DMA_ISR_TCIF1_Pos = 0x5
	// Bit mask of TCIF1 field.
	DMA_ISR_TCIF1_Msk = 0x20
	// Bit TCIF1.
	DMA_ISR_TCIF1 = 0x20
	// No transfer complete event
	DMA_ISR_TCIF1_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF1_Complete = 0x1
	// Position of TCIF2 field.
	DMA_ISR_TCIF2_Pos = 0x9
	// Bit mask of TCIF2 field.
	DMA_ISR_TCIF2_Msk = 0x200
	// Bit TCIF2.
	DMA_ISR_TCIF2 = 0x200
	// No transfer complete event
	DMA_ISR_TCIF2_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF2_Complete = 0x1
	// Position of TCIF3 field.
	DMA_ISR_TCIF3_Pos = 0xd
	// Bit mask of TCIF3 field.
	DMA_ISR_TCIF3_Msk = 0x2000
	// Bit TCIF3.
	DMA_ISR_TCIF3 = 0x2000
	// No transfer complete event
	DMA_ISR_TCIF3_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF3_Complete = 0x1
	// Position of TCIF4 field.
	DMA_ISR_TCIF4_Pos = 0x11
	// Bit mask of TCIF4 field.
	DMA_ISR_TCIF4_Msk = 0x20000
	// Bit TCIF4.
	DMA_ISR_TCIF4 = 0x20000
	// No transfer complete event
	DMA_ISR_TCIF4_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF4_Complete = 0x1
	// Position of TCIF5 field.
	DMA_ISR_TCIF5_Pos = 0x15
	// Bit mask of TCIF5 field.
	DMA_ISR_TCIF5_Msk = 0x200000
	// Bit TCIF5.
	DMA_ISR_TCIF5 = 0x200000
	// No transfer complete event
	DMA_ISR_TCIF5_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF5_Complete = 0x1
	// Position of TCIF6 field.
	DMA_ISR_TCIF6_Pos = 0x19
	// Bit mask of TCIF6 field.
	DMA_ISR_TCIF6_Msk = 0x2000000
	// Bit TCIF6.
	DMA_ISR_TCIF6 = 0x2000000
	// No transfer complete event
	DMA_ISR_TCIF6_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF6_Complete = 0x1
	// Position of TCIF7 field.
	DMA_ISR_TCIF7_Pos = 0x1d
	// Bit mask of TCIF7 field.
	DMA_ISR_TCIF7_Msk = 0x20000000
	// Bit TCIF7.
	DMA_ISR_TCIF7 = 0x20000000
	// No transfer complete event
	DMA_ISR_TCIF7_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF7_Complete = 0x1
	// Position of TCIF8 field.
	DMA_ISR_TCIF8_Pos = 0x21
	// Bit mask of TCIF8 field.
	DMA_ISR_TCIF8_Msk = 0x200000000
	// Bit TCIF8.
	DMA_ISR_TCIF8 = 0x200000000
	// No transfer complete event
	DMA_ISR_TCIF8_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF8_Complete = 0x1
	// Position of HTIF1 field.
	DMA_ISR_HTIF1_Pos = 0x6
	// Bit mask of HTIF1 field.
	DMA_ISR_HTIF1_Msk = 0x40
	// Bit HTIF1.
	DMA_ISR_HTIF1 = 0x40
	// No half transfer event
	DMA_ISR_HTIF1_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF1_Half = 0x1
	// Position of HTIF2 field.
	DMA_ISR_HTIF2_Pos = 0xa
	// Bit mask of HTIF2 field.
	DMA_ISR_HTIF2_Msk = 0x400
	// Bit HTIF2.
	DMA_ISR_HTIF2 = 0x400
	// No half transfer event
	DMA_ISR_HTIF2_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF2_Half = 0x1
	// Position of HTIF3 field.
	DMA_ISR_HTIF3_Pos = 0xe
	// Bit mask of HTIF3 field.
	DMA_ISR_HTIF3_Msk = 0x4000
	// Bit HTIF3.
	DMA_ISR_HTIF3 = 0x4000
	// No half transfer event
	DMA_ISR_HTIF3_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF3_Half = 0x1
	// Position of HTIF4 field.
	DMA_ISR_HTIF4_Pos = 0x12
	// Bit mask of HTIF4 field.
	DMA_ISR_HTIF4_Msk = 0x40000
	// Bit HTIF4.
	DMA_ISR_HTIF4 = 0x40000
	// No half transfer event
	DMA_ISR_HTIF4_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF4_Half = 0x1
	// Position of HTIF5 field.
	DMA_ISR_HTIF5_Pos = 0x16
	// Bit mask of HTIF5 field.
	DMA_ISR_HTIF5_Msk = 0x400000
	// Bit HTIF5.
	DMA_ISR_HTIF5 = 0x400000
	// No half transfer event
	DMA_ISR_HTIF5_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF5_Half = 0x1
	// Position of HTIF6 field.
	DMA_ISR_HTIF6_Pos = 0x1a
	// Bit mask of HTIF6 field.
	DMA_ISR_HTIF6_Msk = 0x4000000
	// Bit HTIF6.
	DMA_ISR_HTIF6 = 0x4000000
	// No half transfer event
	DMA_ISR_HTIF6_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF6_Half = 0x1
	// Position of HTIF7 field.
	DMA_ISR_HTIF7_Pos = 0x1e
	// Bit mask of HTIF7 field.
	DMA_ISR_HTIF7_Msk = 0x40000000
	// Bit HTIF7.
	DMA_ISR_HTIF7 = 0x40000000
	// No half transfer event
	DMA_ISR_HTIF7_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF7_Half = 0x1
	// Position of HTIF8 field.
	DMA_ISR_HTIF8_Pos = 0x22
	// Bit mask of HTIF8 field.
	DMA_ISR_HTIF8_Msk = 0x400000000
	// Bit HTIF8.
	DMA_ISR_HTIF8 = 0x400000000
	// No half transfer event
	DMA_ISR_HTIF8_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF8_Half = 0x1
	// Position of TEIF1 field.
	DMA_ISR_TEIF1_Pos = 0x7
	// Bit mask of TEIF1 field.
	DMA_ISR_TEIF1_Msk = 0x80
	// Bit TEIF1.
	DMA_ISR_TEIF1 = 0x80
	// No transfer error
	DMA_ISR_TEIF1_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF1_Error = 0x1
	// Position of TEIF2 field.
	DMA_ISR_TEIF2_Pos = 0xb
	// Bit mask of TEIF2 field.
	DMA_ISR_TEIF2_Msk = 0x800
	// Bit TEIF2.
	DMA_ISR_TEIF2 = 0x800
	// No transfer error
	DMA_ISR_TEIF2_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF2_Error = 0x1
	// Position of TEIF3 field.
	DMA_ISR_TEIF3_Pos = 0xf
	// Bit mask of TEIF3 field.
	DMA_ISR_TEIF3_Msk = 0x8000
	// Bit TEIF3.
	DMA_ISR_TEIF3 = 0x8000
	// No transfer error
	DMA_ISR_TEIF3_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF3_Error = 0x1
	// Position of TEIF4 field.
	DMA_ISR_TEIF4_Pos = 0x13
	// Bit mask of TEIF4 field.
	DMA_ISR_TEIF4_Msk = 0x80000
	// Bit TEIF4.
	DMA_ISR_TEIF4 = 0x80000
	// No transfer error
	DMA_ISR_TEIF4_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF4_Error = 0x1
	// Position of TEIF5 field.
	DMA_ISR_TEIF5_Pos = 0x17
	// Bit mask of TEIF5 field.
	DMA_ISR_TEIF5_Msk = 0x800000
	// Bit TEIF5.
	DMA_ISR_TEIF5 = 0x800000
	// No transfer error
	DMA_ISR_TEIF5_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF5_Error = 0x1
	// Position of TEIF6 field.
	DMA_ISR_TEIF6_Pos = 0x1b
	// Bit mask of TEIF6 field.
	DMA_ISR_TEIF6_Msk = 0x8000000
	// Bit TEIF6.
	DMA_ISR_TEIF6 = 0x8000000
	// No transfer error
	DMA_ISR_TEIF6_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF6_Error = 0x1
	// Position of TEIF7 field.
	DMA_ISR_TEIF7_Pos = 0x1f
	// Bit mask of TEIF7 field.
	DMA_ISR_TEIF7_Msk = 0x80000000
	// Bit TEIF7.
	DMA_ISR_TEIF7 = 0x80000000
	// No transfer error
	DMA_ISR_TEIF7_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF7_Error = 0x1
	// Position of TEIF8 field.
	DMA_ISR_TEIF8_Pos = 0x23
	// Bit mask of TEIF8 field.
	DMA_ISR_TEIF8_Msk = 0x800000000
	// Bit TEIF8.
	DMA_ISR_TEIF8 = 0x800000000
	// No transfer error
	DMA_ISR_TEIF8_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF8_Error = 0x1

	// IFCR: DMA_IFCR register
	// Position of CGIF1 field.
	DMA_IFCR_CGIF1_Pos = 0x4
	// Bit mask of CGIF1 field.
	DMA_IFCR_CGIF1_Msk = 0x10
	// Bit CGIF1.
	DMA_IFCR_CGIF1 = 0x10
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF1_Clear = 0x1
	// Position of CGIF2 field.
	DMA_IFCR_CGIF2_Pos = 0x8
	// Bit mask of CGIF2 field.
	DMA_IFCR_CGIF2_Msk = 0x100
	// Bit CGIF2.
	DMA_IFCR_CGIF2 = 0x100
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF2_Clear = 0x1
	// Position of CGIF3 field.
	DMA_IFCR_CGIF3_Pos = 0xc
	// Bit mask of CGIF3 field.
	DMA_IFCR_CGIF3_Msk = 0x1000
	// Bit CGIF3.
	DMA_IFCR_CGIF3 = 0x1000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF3_Clear = 0x1
	// Position of CGIF4 field.
	DMA_IFCR_CGIF4_Pos = 0x10
	// Bit mask of CGIF4 field.
	DMA_IFCR_CGIF4_Msk = 0x10000
	// Bit CGIF4.
	DMA_IFCR_CGIF4 = 0x10000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF4_Clear = 0x1
	// Position of CGIF5 field.
	DMA_IFCR_CGIF5_Pos = 0x14
	// Bit mask of CGIF5 field.
	DMA_IFCR_CGIF5_Msk = 0x100000
	// Bit CGIF5.
	DMA_IFCR_CGIF5 = 0x100000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF5_Clear = 0x1
	// Position of CGIF6 field.
	DMA_IFCR_CGIF6_Pos = 0x18
	// Bit mask of CGIF6 field.
	DMA_IFCR_CGIF6_Msk = 0x1000000
	// Bit CGIF6.
	DMA_IFCR_CGIF6 = 0x1000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF6_Clear = 0x1
	// Position of CGIF7 field.
	DMA_IFCR_CGIF7_Pos = 0x1c
	// Bit mask of CGIF7 field.
	DMA_IFCR_CGIF7_Msk = 0x10000000
	// Bit CGIF7.
	DMA_IFCR_CGIF7 = 0x10000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF7_Clear = 0x1
	// Position of CGIF8 field.
	DMA_IFCR_CGIF8_Pos = 0x20
	// Bit mask of CGIF8 field.
	DMA_IFCR_CGIF8_Msk = 0x100000000
	// Bit CGIF8.
	DMA_IFCR_CGIF8 = 0x100000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF8_Clear = 0x1
	// Position of CTCIF1 field.
	DMA_IFCR_CTCIF1_Pos = 0x5
	// Bit mask of CTCIF1 field.
	DMA_IFCR_CTCIF1_Msk = 0x20
	// Bit CTCIF1.
	DMA_IFCR_CTCIF1 = 0x20
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF1_Clear = 0x1
	// Position of CTCIF2 field.
	DMA_IFCR_CTCIF2_Pos = 0x9
	// Bit mask of CTCIF2 field.
	DMA_IFCR_CTCIF2_Msk = 0x200
	// Bit CTCIF2.
	DMA_IFCR_CTCIF2 = 0x200
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF2_Clear = 0x1
	// Position of CTCIF3 field.
	DMA_IFCR_CTCIF3_Pos = 0xd
	// Bit mask of CTCIF3 field.
	DMA_IFCR_CTCIF3_Msk = 0x2000
	// Bit CTCIF3.
	DMA_IFCR_CTCIF3 = 0x2000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF3_Clear = 0x1
	// Position of CTCIF4 field.
	DMA_IFCR_CTCIF4_Pos = 0x11
	// Bit mask of CTCIF4 field.
	DMA_IFCR_CTCIF4_Msk = 0x20000
	// Bit CTCIF4.
	DMA_IFCR_CTCIF4 = 0x20000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF4_Clear = 0x1
	// Position of CTCIF5 field.
	DMA_IFCR_CTCIF5_Pos = 0x15
	// Bit mask of CTCIF5 field.
	DMA_IFCR_CTCIF5_Msk = 0x200000
	// Bit CTCIF5.
	DMA_IFCR_CTCIF5 = 0x200000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF5_Clear = 0x1
	// Position of CTCIF6 field.
	DMA_IFCR_CTCIF6_Pos = 0x19
	// Bit mask of CTCIF6 field.
	DMA_IFCR_CTCIF6_Msk = 0x2000000
	// Bit CTCIF6.
	DMA_IFCR_CTCIF6 = 0x2000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF6_Clear = 0x1
	// Position of CTCIF7 field.
	DMA_IFCR_CTCIF7_Pos = 0x1d
	// Bit mask of CTCIF7 field.
	DMA_IFCR_CTCIF7_Msk = 0x20000000
	// Bit CTCIF7.
	DMA_IFCR_CTCIF7 = 0x20000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF7_Clear = 0x1
	// Position of CTCIF8 field.
	DMA_IFCR_CTCIF8_Pos = 0x21
	// Bit mask of CTCIF8 field.
	DMA_IFCR_CTCIF8_Msk = 0x200000000
	// Bit CTCIF8.
	DMA_IFCR_CTCIF8 = 0x200000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF8_Clear = 0x1
	// Position of CHTIF1 field.
	DMA_IFCR_CHTIF1_Pos = 0x6
	// Bit mask of CHTIF1 field.
	DMA_IFCR_CHTIF1_Msk = 0x40
	// Bit CHTIF1.
	DMA_IFCR_CHTIF1 = 0x40
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF1_Clear = 0x1
	// Position of CHTIF2 field.
	DMA_IFCR_CHTIF2_Pos = 0xa
	// Bit mask of CHTIF2 field.
	DMA_IFCR_CHTIF2_Msk = 0x400
	// Bit CHTIF2.
	DMA_IFCR_CHTIF2 = 0x400
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF2_Clear = 0x1
	// Position of CHTIF3 field.
	DMA_IFCR_CHTIF3_Pos = 0xe
	// Bit mask of CHTIF3 field.
	DMA_IFCR_CHTIF3_Msk = 0x4000
	// Bit CHTIF3.
	DMA_IFCR_CHTIF3 = 0x4000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF3_Clear = 0x1
	// Position of CHTIF4 field.
	DMA_IFCR_CHTIF4_Pos = 0x12
	// Bit mask of CHTIF4 field.
	DMA_IFCR_CHTIF4_Msk = 0x40000
	// Bit CHTIF4.
	DMA_IFCR_CHTIF4 = 0x40000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF4_Clear = 0x1
	// Position of CHTIF5 field.
	DMA_IFCR_CHTIF5_Pos = 0x16
	// Bit mask of CHTIF5 field.
	DMA_IFCR_CHTIF5_Msk = 0x400000
	// Bit CHTIF5.
	DMA_IFCR_CHTIF5 = 0x400000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF5_Clear = 0x1
	// Position of CHTIF6 field.
	DMA_IFCR_CHTIF6_Pos = 0x1a
	// Bit mask of CHTIF6 field.
	DMA_IFCR_CHTIF6_Msk = 0x4000000
	// Bit CHTIF6.
	DMA_IFCR_CHTIF6 = 0x4000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF6_Clear = 0x1
	// Position of CHTIF7 field.
	DMA_IFCR_CHTIF7_Pos = 0x1e
	// Bit mask of CHTIF7 field.
	DMA_IFCR_CHTIF7_Msk = 0x40000000
	// Bit CHTIF7.
	DMA_IFCR_CHTIF7 = 0x40000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF7_Clear = 0x1
	// Position of CHTIF8 field.
	DMA_IFCR_CHTIF8_Pos = 0x22
	// Bit mask of CHTIF8 field.
	DMA_IFCR_CHTIF8_Msk = 0x400000000
	// Bit CHTIF8.
	DMA_IFCR_CHTIF8 = 0x400000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF8_Clear = 0x1
	// Position of CTEIF1 field.
	DMA_IFCR_CTEIF1_Pos = 0x7
	// Bit mask of CTEIF1 field.
	DMA_IFCR_CTEIF1_Msk = 0x80
	// Bit CTEIF1.
	DMA_IFCR_CTEIF1 = 0x80
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF1_Clear = 0x1
	// Position of CTEIF2 field.
	DMA_IFCR_CTEIF2_Pos = 0xb
	// Bit mask of CTEIF2 field.
	DMA_IFCR_CTEIF2_Msk = 0x800
	// Bit CTEIF2.
	DMA_IFCR_CTEIF2 = 0x800
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF2_Clear = 0x1
	// Position of CTEIF3 field.
	DMA_IFCR_CTEIF3_Pos = 0xf
	// Bit mask of CTEIF3 field.
	DMA_IFCR_CTEIF3_Msk = 0x8000
	// Bit CTEIF3.
	DMA_IFCR_CTEIF3 = 0x8000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF3_Clear = 0x1
	// Position of CTEIF4 field.
	DMA_IFCR_CTEIF4_Pos = 0x13
	// Bit mask of CTEIF4 field.
	DMA_IFCR_CTEIF4_Msk = 0x80000
	// Bit CTEIF4.
	DMA_IFCR_CTEIF4 = 0x80000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF4_Clear = 0x1
	// Position of CTEIF5 field.
	DMA_IFCR_CTEIF5_Pos = 0x17
	// Bit mask of CTEIF5 field.
	DMA_IFCR_CTEIF5_Msk = 0x800000
	// Bit CTEIF5.
	DMA_IFCR_CTEIF5 = 0x800000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF5_Clear = 0x1
	// Position of CTEIF6 field.
	DMA_IFCR_CTEIF6_Pos = 0x1b
	// Bit mask of CTEIF6 field.
	DMA_IFCR_CTEIF6_Msk = 0x8000000
	// Bit CTEIF6.
	DMA_IFCR_CTEIF6 = 0x8000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF6_Clear = 0x1
	// Position of CTEIF7 field.
	DMA_IFCR_CTEIF7_Pos = 0x1f
	// Bit mask of CTEIF7 field.
	DMA_IFCR_CTEIF7_Msk = 0x80000000
	// Bit CTEIF7.
	DMA_IFCR_CTEIF7 = 0x80000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF7_Clear = 0x1
	// Position of CTEIF8 field.
	DMA_IFCR_CTEIF8_Pos = 0x23
	// Bit mask of CTEIF8 field.
	DMA_IFCR_CTEIF8_Msk = 0x800000000
	// Bit CTEIF8.
	DMA_IFCR_CTEIF8 = 0x800000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF8_Clear = 0x1

	// CH.CR: DMA_CCRx register
	// Position of EN field.
	DMA_CH_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA_CH_CR_EN_Msk = 0x1
	// Bit EN.
	DMA_CH_CR_EN = 0x1
	// Channel disabled
	DMA_CH_CR_EN_Disabled = 0x0
	// Channel enabled
	DMA_CH_CR_EN_Enabled = 0x1
	// Position of TCIE field.
	DMA_CH_CR_TCIE_Pos = 0x1
	// Bit mask of TCIE field.
	DMA_CH_CR_TCIE_Msk = 0x2
	// Bit TCIE.
	DMA_CH_CR_TCIE = 0x2
	// Transfer Complete interrupt disabled
	DMA_CH_CR_TCIE_Disabled = 0x0
	// Transfer Complete interrupt enabled
	DMA_CH_CR_TCIE_Enabled = 0x1
	// Position of HTIE field.
	DMA_CH_CR_HTIE_Pos = 0x2
	// Bit mask of HTIE field.
	DMA_CH_CR_HTIE_Msk = 0x4
	// Bit HTIE.
	DMA_CH_CR_HTIE = 0x4
	// Half Transfer interrupt disabled
	DMA_CH_CR_HTIE_Disabled = 0x0
	// Half Transfer interrupt enabled
	DMA_CH_CR_HTIE_Enabled = 0x1
	// Position of TEIE field.
	DMA_CH_CR_TEIE_Pos = 0x3
	// Bit mask of TEIE field.
	DMA_CH_CR_TEIE_Msk = 0x8
	// Bit TEIE.
	DMA_CH_CR_TEIE = 0x8
	// Transfer Error interrupt disabled
	DMA_CH_CR_TEIE_Disabled = 0x0
	// Transfer Error interrupt enabled
	DMA_CH_CR_TEIE_Enabled = 0x1
	// Position of DIR field.
	DMA_CH_CR_DIR_Pos = 0x4
	// Bit mask of DIR field.
	DMA_CH_CR_DIR_Msk = 0x10
	// Bit DIR.
	DMA_CH_CR_DIR = 0x10
	// Read from peripheral
	DMA_CH_CR_DIR_FromPeripheral = 0x0
	// Read from memory
	DMA_CH_CR_DIR_FromMemory = 0x1
	// Position of CIRC field.
	DMA_CH_CR_CIRC_Pos = 0x5
	// Bit mask of CIRC field.
	DMA_CH_CR_CIRC_Msk = 0x20
	// Bit CIRC.
	DMA_CH_CR_CIRC = 0x20
	// Circular buffer disabled
	DMA_CH_CR_CIRC_Disabled = 0x0
	// Circular buffer enabled
	DMA_CH_CR_CIRC_Enabled = 0x1
	// Position of PINC field.
	DMA_CH_CR_PINC_Pos = 0x6
	// Bit mask of PINC field.
	DMA_CH_CR_PINC_Msk = 0x40
	// Bit PINC.
	DMA_CH_CR_PINC = 0x40
	// Increment mode disabled
	DMA_CH_CR_PINC_Disabled = 0x0
	// Increment mode enabled
	DMA_CH_CR_PINC_Enabled = 0x1
	// Position of MINC field.
	DMA_CH_CR_MINC_Pos = 0x7
	// Bit mask of MINC field.
	DMA_CH_CR_MINC_Msk = 0x80
	// Bit MINC.
	DMA_CH_CR_MINC = 0x80
	// Increment mode disabled
	DMA_CH_CR_MINC_Disabled = 0x0
	// Increment mode enabled
	DMA_CH_CR_MINC_Enabled = 0x1
	// Position of PSIZE field.
	DMA_CH_CR_PSIZE_Pos = 0x8
	// Bit mask of PSIZE field.
	DMA_CH_CR_PSIZE_Msk = 0x300
	// 8-bit size
	DMA_CH_CR_PSIZE_Bits8 = 0x0
	// 16-bit size
	DMA_CH_CR_PSIZE_Bits16 = 0x1
	// 32-bit size
	DMA_CH_CR_PSIZE_Bits32 = 0x2
	// Position of MSIZE field.
	DMA_CH_CR_MSIZE_Pos = 0xa
	// Bit mask of MSIZE field.
	DMA_CH_CR_MSIZE_Msk = 0xc00
	// 8-bit size
	DMA_CH_CR_MSIZE_Bits8 = 0x0
	// 16-bit size
	DMA_CH_CR_MSIZE_Bits16 = 0x1
	// 32-bit size
	DMA_CH_CR_MSIZE_Bits32 = 0x2
	// Position of PL field.
	DMA_CH_CR_PL_Pos = 0xc
	// Bit mask of PL field.
	DMA_CH_CR_PL_Msk = 0x3000
	// Low priority
	DMA_CH_CR_PL_Low = 0x0
	// Medium priority
	DMA_CH_CR_PL_Medium = 0x1
	// High priority
	DMA_CH_CR_PL_High = 0x2
	// Very high priority
	DMA_CH_CR_PL_VeryHigh = 0x3
	// Position of MEM2MEM field.
	DMA_CH_CR_MEM2MEM_Pos = 0xe
	// Bit mask of MEM2MEM field.
	DMA_CH_CR_MEM2MEM_Msk = 0x4000
	// Bit MEM2MEM.
	DMA_CH_CR_MEM2MEM = 0x4000
	// Memory to memory mode disabled
	DMA_CH_CR_MEM2MEM_Disabled = 0x0
	// Memory to memory mode enabled
	DMA_CH_CR_MEM2MEM_Enabled = 0x1

	// CH.NDTR: DMA_CNDTRx register
	// Position of NDT field.
	DMA_CH_NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA_CH_NDTR_NDT_Msk = 0xffff

	// CH.PAR: DMA_CPARx register
	// Position of PA field.
	DMA_CH_PAR_PA_Pos = 0x0
	// Bit mask of PA field.
	DMA_CH_PAR_PA_Msk = 0xffffffff

	// CH.MAR: DMA_CMARx register
	// Position of MA field.
	DMA_CH_MAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA_CH_MAR_MA_Msk = 0xffffffff
)

// Constants for DMAMUX
const (
	// C0CR: CxCR register
	// Position of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Msk = 0x1f
	// SPI3_RX
	DMAMUX_CCR_DMAREQ_ID_Spi3Rx = 0x2
	// SPI3_TX
	DMAMUX_CCR_DMAREQ_ID_Spi3Tx = 0x3
	// I2C1_RX
	DMAMUX_CCR_DMAREQ_ID_I2c1Rx = 0x8
	// I2C1_TX
	DMAMUX_CCR_DMAREQ_ID_I2c1Tx = 0x9
	// USART_RX
	DMAMUX_CCR_DMAREQ_ID_UsartRx = 0xc
	// USART_TX
	DMAMUX_CCR_DMAREQ_ID_UsartTx = 0xd
	// LPUART_RX
	DMAMUX_CCR_DMAREQ_ID_LpuartRx = 0xe
	// LPUART_TX
	DMAMUX_CCR_DMAREQ_ID_LpuartTx = 0xf
	// ADC_CH0 (DS channel)
	DMAMUX_CCR_DMAREQ_ID_AdcCh0 = 0x10
	// TIM2_CH1
	DMAMUX_CCR_DMAREQ_ID_Tim2Ch1 = 0x12
	// TIM2_CH2
	DMAMUX_CCR_DMAREQ_ID_Tim2Ch2 = 0x13
	// TIM2_CH3
	DMAMUX_CCR_DMAREQ_ID_Tim2Ch3 = 0x14
	// TIM2_CH4
	DMAMUX_CCR_DMAREQ_ID_Tim2Ch4 = 0x15
	// TIM2_UP
	DMAMUX_CCR_DMAREQ_ID_Tim2Up = 0x16
	// TIM16_CH1
	DMAMUX_CCR_DMAREQ_ID_Tim16Ch1 = 0x17
	// TIM16_UP
	DMAMUX_CCR_DMAREQ_ID_Tim16Up = 0x18
	// TIM17_CH1
	DMAMUX_CCR_DMAREQ_ID_Tim17Ch1 = 0x19
	// TIM17_UP
	DMAMUX_CCR_DMAREQ_ID_Tim17Up = 0x1a
)

// Constants for GPIOA
const (
	// MODER: MODER register
	// Position of MODE0 field.
	GPIO_MODER_MODE0_Pos = 0x2
	// Bit mask of MODE0 field.
	GPIO_MODER_MODE0_Msk = 0xc
	// Input mode
	GPIO_MODER_MODE0_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE0_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE0_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE0_Analog = 0x3
	// Position of MODE1 field.
	GPIO_MODER_MODE1_Pos = 0x4
	// Bit mask of MODE1 field.
	GPIO_MODER_MODE1_Msk = 0x30
	// Input mode
	GPIO_MODER_MODE1_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE1_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE1_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE1_Analog = 0x3
	// Position of MODE2 field.
	GPIO_MODER_MODE2_Pos = 0x6
	// Bit mask of MODE2 field.
	GPIO_MODER_MODE2_Msk = 0xc0
	// Input mode
	GPIO_MODER_MODE2_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE2_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE2_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE2_Analog = 0x3
	// Position of MODE3 field.
	GPIO_MODER_MODE3_Pos = 0x8
	// Bit mask of MODE3 field.
	GPIO_MODER_MODE3_Msk = 0x300
	// Input mode
	GPIO_MODER_MODE3_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE3_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE3_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE3_Analog = 0x3
	// Position of MODE4 field.
	GPIO_MODER_MODE4_Pos = 0xa
	// Bit mask of MODE4 field.
	GPIO_MODER_MODE4_Msk = 0xc00
	// Input mode
	GPIO_MODER_MODE4_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE4_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE4_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE4_Analog = 0x3
	// Position of MODE5 field.
	GPIO_MODER_MODE5_Pos = 0xc
	// Bit mask of MODE5 field.
	GPIO_MODER_MODE5_Msk = 0x3000
	// Input mode
	GPIO_MODER_MODE5_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE5_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE5_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE5_Analog = 0x3
	// Position of MODE6 field.
	GPIO_MODER_MODE6_Pos = 0xe
	// Bit mask of MODE6 field.
	GPIO_MODER_MODE6_Msk = 0xc000
	// Input mode
	GPIO_MODER_MODE6_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE6_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE6_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE6_Analog = 0x3
	// Position of MODE7 field.
	GPIO_MODER_MODE7_Pos = 0x10
	// Bit mask of MODE7 field.
	GPIO_MODER_MODE7_Msk = 0x30000
	// Input mode
	GPIO_MODER_MODE7_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE7_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE7_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE7_Analog = 0x3
	// Position of MODE8 field.
	GPIO_MODER_MODE8_Pos = 0x12
	// Bit mask of MODE8 field.
	GPIO_MODER_MODE8_Msk = 0xc0000
	// Input mode
	GPIO_MODER_MODE8_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE8_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE8_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE8_Analog = 0x3
	// Position of MODE9 field.
	GPIO_MODER_MODE9_Pos = 0x14
	// Bit mask of MODE9 field.
	GPIO_MODER_MODE9_Msk = 0x300000
	// Input mode
	GPIO_MODER_MODE9_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE9_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE9_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE9_Analog = 0x3
	// Position of MODE10 field.
	GPIO_MODER_MODE10_Pos = 0x16
	// Bit mask of MODE10 field.
	GPIO_MODER_MODE10_Msk = 0xc00000
	// Input mode
	GPIO_MODER_MODE10_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE10_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE10_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE10_Analog = 0x3
	// Position of MODE11 field.
	GPIO_MODER_MODE11_Pos = 0x18
	// Bit mask of MODE11 field.
	GPIO_MODER_MODE11_Msk = 0x3000000
	// Input mode
	GPIO_MODER_MODE11_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE11_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE11_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE11_Analog = 0x3

	// OTYPER: OTYPER register
	// Position of OT0 field.
	GPIO_OTYPER_OT0_Pos = 0x1
	// Bit mask of OT0 field.
	GPIO_OTYPER_OT0_Msk = 0x2
	// Bit OT0.
	GPIO_OTYPER_OT0 = 0x2
	// Output push-pull (reset state)
	GPIO_OTYPER_OT0_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT0_OpenDrain = 0x1
	// Position of OT1 field.
	GPIO_OTYPER_OT1_Pos = 0x2
	// Bit mask of OT1 field.
	GPIO_OTYPER_OT1_Msk = 0x4
	// Bit OT1.
	GPIO_OTYPER_OT1 = 0x4
	// Output push-pull (reset state)
	GPIO_OTYPER_OT1_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT1_OpenDrain = 0x1
	// Position of OT2 field.
	GPIO_OTYPER_OT2_Pos = 0x3
	// Bit mask of OT2 field.
	GPIO_OTYPER_OT2_Msk = 0x8
	// Bit OT2.
	GPIO_OTYPER_OT2 = 0x8
	// Output push-pull (reset state)
	GPIO_OTYPER_OT2_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT2_OpenDrain = 0x1
	// Position of OT3 field.
	GPIO_OTYPER_OT3_Pos = 0x4
	// Bit mask of OT3 field.
	GPIO_OTYPER_OT3_Msk = 0x10
	// Bit OT3.
	GPIO_OTYPER_OT3 = 0x10
	// Output push-pull (reset state)
	GPIO_OTYPER_OT3_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT3_OpenDrain = 0x1
	// Position of OT4 field.
	GPIO_OTYPER_OT4_Pos = 0x5
	// Bit mask of OT4 field.
	GPIO_OTYPER_OT4_Msk = 0x20
	// Bit OT4.
	GPIO_OTYPER_OT4 = 0x20
	// Output push-pull (reset state)
	GPIO_OTYPER_OT4_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT4_OpenDrain = 0x1
	// Position of OT5 field.
	GPIO_OTYPER_OT5_Pos = 0x6
	// Bit mask of OT5 field.
	GPIO_OTYPER_OT5_Msk = 0x40
	// Bit OT5.
	GPIO_OTYPER_OT5 = 0x40
	// Output push-pull (reset state)
	GPIO_OTYPER_OT5_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT5_OpenDrain = 0x1
	// Position of OT6 field.
	GPIO_OTYPER_OT6_Pos = 0x7
	// Bit mask of OT6 field.
	GPIO_OTYPER_OT6_Msk = 0x80
	// Bit OT6.
	GPIO_OTYPER_OT6 = 0x80
	// Output push-pull (reset state)
	GPIO_OTYPER_OT6_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT6_OpenDrain = 0x1
	// Position of OT7 field.
	GPIO_OTYPER_OT7_Pos = 0x8
	// Bit mask of OT7 field.
	GPIO_OTYPER_OT7_Msk = 0x100
	// Bit OT7.
	GPIO_OTYPER_OT7 = 0x100
	// Output push-pull (reset state)
	GPIO_OTYPER_OT7_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT7_OpenDrain = 0x1
	// Position of OT8 field.
	GPIO_OTYPER_OT8_Pos = 0x9
	// Bit mask of OT8 field.
	GPIO_OTYPER_OT8_Msk = 0x200
	// Bit OT8.
	GPIO_OTYPER_OT8 = 0x200
	// Output push-pull (reset state)
	GPIO_OTYPER_OT8_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT8_OpenDrain = 0x1
	// Position of OT9 field.
	GPIO_OTYPER_OT9_Pos = 0xa
	// Bit mask of OT9 field.
	GPIO_OTYPER_OT9_Msk = 0x400
	// Bit OT9.
	GPIO_OTYPER_OT9 = 0x400
	// Output push-pull (reset state)
	GPIO_OTYPER_OT9_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT9_OpenDrain = 0x1
	// Position of OT10 field.
	GPIO_OTYPER_OT10_Pos = 0xb
	// Bit mask of OT10 field.
	GPIO_OTYPER_OT10_Msk = 0x800
	// Bit OT10.
	GPIO_OTYPER_OT10 = 0x800
	// Output push-pull (reset state)
	GPIO_OTYPER_OT10_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT10_OpenDrain = 0x1
	// Position of OT11 field.
	GPIO_OTYPER_OT11_Pos = 0xc
	// Bit mask of OT11 field.
	GPIO_OTYPER_OT11_Msk = 0x1000
	// Bit OT11.
	GPIO_OTYPER_OT11 = 0x1000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT11_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT11_OpenDrain = 0x1

	// OSPEEDR: OSPEEDR register
	// Position of OSPEED0 field.
	GPIO_OSPEEDR_OSPEED0_Pos = 0x2
	// Bit mask of OSPEED0 field.
	GPIO_OSPEEDR_OSPEED0_Msk = 0xc
	// Low speed
	GPIO_OSPEEDR_OSPEED0_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED0_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED0_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED0_VeryHighSpeed = 0x3
	// Position of OSPEED1 field.
	GPIO_OSPEEDR_OSPEED1_Pos = 0x4
	// Bit mask of OSPEED1 field.
	GPIO_OSPEEDR_OSPEED1_Msk = 0x30
	// Low speed
	GPIO_OSPEEDR_OSPEED1_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED1_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED1_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED1_VeryHighSpeed = 0x3
	// Position of OSPEED2 field.
	GPIO_OSPEEDR_OSPEED2_Pos = 0x6
	// Bit mask of OSPEED2 field.
	GPIO_OSPEEDR_OSPEED2_Msk = 0xc0
	// Low speed
	GPIO_OSPEEDR_OSPEED2_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED2_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED2_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED2_VeryHighSpeed = 0x3
	// Position of OSPEED3 field.
	GPIO_OSPEEDR_OSPEED3_Pos = 0x8
	// Bit mask of OSPEED3 field.
	GPIO_OSPEEDR_OSPEED3_Msk = 0x300
	// Low speed
	GPIO_OSPEEDR_OSPEED3_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED3_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED3_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED3_VeryHighSpeed = 0x3
	// Position of OSPEED4 field.
	GPIO_OSPEEDR_OSPEED4_Pos = 0xa
	// Bit mask of OSPEED4 field.
	GPIO_OSPEEDR_OSPEED4_Msk = 0xc00
	// Low speed
	GPIO_OSPEEDR_OSPEED4_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED4_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED4_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED4_VeryHighSpeed = 0x3
	// Position of OSPEED5 field.
	GPIO_OSPEEDR_OSPEED5_Pos = 0xc
	// Bit mask of OSPEED5 field.
	GPIO_OSPEEDR_OSPEED5_Msk = 0x3000
	// Low speed
	GPIO_OSPEEDR_OSPEED5_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED5_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED5_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED5_VeryHighSpeed = 0x3
	// Position of OSPEED6 field.
	GPIO_OSPEEDR_OSPEED6_Pos = 0xe
	// Bit mask of OSPEED6 field.
	GPIO_OSPEEDR_OSPEED6_Msk = 0xc000
	// Low speed
	GPIO_OSPEEDR_OSPEED6_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED6_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED6_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED6_VeryHighSpeed = 0x3
	// Position of OSPEED7 field.
	GPIO_OSPEEDR_OSPEED7_Pos = 0x10
	// Bit mask of OSPEED7 field.
	GPIO_OSPEEDR_OSPEED7_Msk = 0x30000
	// Low speed
	GPIO_OSPEEDR_OSPEED7_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED7_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED7_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED7_VeryHighSpeed = 0x3
	// Position of OSPEED8 field.
	GPIO_OSPEEDR_OSPEED8_Pos = 0x12
	// Bit mask of OSPEED8 field.
	GPIO_OSPEEDR_OSPEED8_Msk = 0xc0000
	// Low speed
	GPIO_OSPEEDR_OSPEED8_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED8_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED8_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED8_VeryHighSpeed = 0x3
	// Position of OSPEED9 field.
	GPIO_OSPEEDR_OSPEED9_Pos = 0x14
	// Bit mask of OSPEED9 field.
	GPIO_OSPEEDR_OSPEED9_Msk = 0x300000
	// Low speed
	GPIO_OSPEEDR_OSPEED9_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED9_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED9_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED9_VeryHighSpeed = 0x3
	// Position of OSPEED10 field.
	GPIO_OSPEEDR_OSPEED10_Pos = 0x16
	// Bit mask of OSPEED10 field.
	GPIO_OSPEEDR_OSPEED10_Msk = 0xc00000
	// Low speed
	GPIO_OSPEEDR_OSPEED10_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED10_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED10_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED10_VeryHighSpeed = 0x3
	// Position of OSPEED11 field.
	GPIO_OSPEEDR_OSPEED11_Pos = 0x18
	// Bit mask of OSPEED11 field.
	GPIO_OSPEEDR_OSPEED11_Msk = 0x3000000
	// Low speed
	GPIO_OSPEEDR_OSPEED11_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED11_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED11_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED11_VeryHighSpeed = 0x3

	// PUPDR: PUPDR register
	// Position of PUPD0 field.
	GPIO_PUPDR_PUPD0_Pos = 0x2
	// Bit mask of PUPD0 field.
	GPIO_PUPDR_PUPD0_Msk = 0xc
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD0_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD0_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD0_PullDown = 0x2
	// Position of PUPD1 field.
	GPIO_PUPDR_PUPD1_Pos = 0x4
	// Bit mask of PUPD1 field.
	GPIO_PUPDR_PUPD1_Msk = 0x30
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD1_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD1_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD1_PullDown = 0x2
	// Position of PUPD2 field.
	GPIO_PUPDR_PUPD2_Pos = 0x6
	// Bit mask of PUPD2 field.
	GPIO_PUPDR_PUPD2_Msk = 0xc0
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD2_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD2_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD2_PullDown = 0x2
	// Position of PUPD3 field.
	GPIO_PUPDR_PUPD3_Pos = 0x8
	// Bit mask of PUPD3 field.
	GPIO_PUPDR_PUPD3_Msk = 0x300
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD3_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD3_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD3_PullDown = 0x2
	// Position of PUPD4 field.
	GPIO_PUPDR_PUPD4_Pos = 0xa
	// Bit mask of PUPD4 field.
	GPIO_PUPDR_PUPD4_Msk = 0xc00
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD4_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD4_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD4_PullDown = 0x2
	// Position of PUPD5 field.
	GPIO_PUPDR_PUPD5_Pos = 0xc
	// Bit mask of PUPD5 field.
	GPIO_PUPDR_PUPD5_Msk = 0x3000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD5_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD5_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD5_PullDown = 0x2
	// Position of PUPD6 field.
	GPIO_PUPDR_PUPD6_Pos = 0xe
	// Bit mask of PUPD6 field.
	GPIO_PUPDR_PUPD6_Msk = 0xc000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD6_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD6_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD6_PullDown = 0x2
	// Position of PUPD7 field.
	GPIO_PUPDR_PUPD7_Pos = 0x10
	// Bit mask of PUPD7 field.
	GPIO_PUPDR_PUPD7_Msk = 0x30000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD7_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD7_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD7_PullDown = 0x2
	// Position of PUPD8 field.
	GPIO_PUPDR_PUPD8_Pos = 0x12
	// Bit mask of PUPD8 field.
	GPIO_PUPDR_PUPD8_Msk = 0xc0000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD8_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD8_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD8_PullDown = 0x2
	// Position of PUPD9 field.
	GPIO_PUPDR_PUPD9_Pos = 0x14
	// Bit mask of PUPD9 field.
	GPIO_PUPDR_PUPD9_Msk = 0x300000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD9_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD9_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD9_PullDown = 0x2
	// Position of PUPD10 field.
	GPIO_PUPDR_PUPD10_Pos = 0x16
	// Bit mask of PUPD10 field.
	GPIO_PUPDR_PUPD10_Msk = 0xc00000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD10_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD10_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD10_PullDown = 0x2
	// Position of PUPD11 field.
	GPIO_PUPDR_PUPD11_Pos = 0x18
	// Bit mask of PUPD11 field.
	GPIO_PUPDR_PUPD11_Msk = 0x3000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD11_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD11_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD11_PullDown = 0x2

	// IDR: IDR register
	// Position of ID0 field.
	GPIO_IDR_ID0_Pos = 0x1
	// Bit mask of ID0 field.
	GPIO_IDR_ID0_Msk = 0x2
	// Bit ID0.
	GPIO_IDR_ID0 = 0x2
	// Input is logic low
	GPIO_IDR_ID0_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID0_High = 0x1
	// Position of ID1 field.
	GPIO_IDR_ID1_Pos = 0x2
	// Bit mask of ID1 field.
	GPIO_IDR_ID1_Msk = 0x4
	// Bit ID1.
	GPIO_IDR_ID1 = 0x4
	// Input is logic low
	GPIO_IDR_ID1_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID1_High = 0x1
	// Position of ID2 field.
	GPIO_IDR_ID2_Pos = 0x3
	// Bit mask of ID2 field.
	GPIO_IDR_ID2_Msk = 0x8
	// Bit ID2.
	GPIO_IDR_ID2 = 0x8
	// Input is logic low
	GPIO_IDR_ID2_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID2_High = 0x1
	// Position of ID3 field.
	GPIO_IDR_ID3_Pos = 0x4
	// Bit mask of ID3 field.
	GPIO_IDR_ID3_Msk = 0x10
	// Bit ID3.
	GPIO_IDR_ID3 = 0x10
	// Input is logic low
	GPIO_IDR_ID3_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID3_High = 0x1
	// Position of ID4 field.
	GPIO_IDR_ID4_Pos = 0x5
	// Bit mask of ID4 field.
	GPIO_IDR_ID4_Msk = 0x20
	// Bit ID4.
	GPIO_IDR_ID4 = 0x20
	// Input is logic low
	GPIO_IDR_ID4_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID4_High = 0x1
	// Position of ID5 field.
	GPIO_IDR_ID5_Pos = 0x6
	// Bit mask of ID5 field.
	GPIO_IDR_ID5_Msk = 0x40
	// Bit ID5.
	GPIO_IDR_ID5 = 0x40
	// Input is logic low
	GPIO_IDR_ID5_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID5_High = 0x1
	// Position of ID6 field.
	GPIO_IDR_ID6_Pos = 0x7
	// Bit mask of ID6 field.
	GPIO_IDR_ID6_Msk = 0x80
	// Bit ID6.
	GPIO_IDR_ID6 = 0x80
	// Input is logic low
	GPIO_IDR_ID6_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID6_High = 0x1
	// Position of ID7 field.
	GPIO_IDR_ID7_Pos = 0x8
	// Bit mask of ID7 field.
	GPIO_IDR_ID7_Msk = 0x100
	// Bit ID7.
	GPIO_IDR_ID7 = 0x100
	// Input is logic low
	GPIO_IDR_ID7_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID7_High = 0x1
	// Position of ID8 field.
	GPIO_IDR_ID8_Pos = 0x9
	// Bit mask of ID8 field.
	GPIO_IDR_ID8_Msk = 0x200
	// Bit ID8.
	GPIO_IDR_ID8 = 0x200
	// Input is logic low
	GPIO_IDR_ID8_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID8_High = 0x1
	// Position of ID9 field.
	GPIO_IDR_ID9_Pos = 0xa
	// Bit mask of ID9 field.
	GPIO_IDR_ID9_Msk = 0x400
	// Bit ID9.
	GPIO_IDR_ID9 = 0x400
	// Input is logic low
	GPIO_IDR_ID9_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID9_High = 0x1
	// Position of ID10 field.
	GPIO_IDR_ID10_Pos = 0xb
	// Bit mask of ID10 field.
	GPIO_IDR_ID10_Msk = 0x800
	// Bit ID10.
	GPIO_IDR_ID10 = 0x800
	// Input is logic low
	GPIO_IDR_ID10_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID10_High = 0x1
	// Position of ID11 field.
	GPIO_IDR_ID11_Pos = 0xc
	// Bit mask of ID11 field.
	GPIO_IDR_ID11_Msk = 0x1000
	// Bit ID11.
	GPIO_IDR_ID11 = 0x1000
	// Input is logic low
	GPIO_IDR_ID11_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID11_High = 0x1

	// ODR: ODR register
	// Position of OD0 field.
	GPIO_ODR_OD0_Pos = 0x1
	// Bit mask of OD0 field.
	GPIO_ODR_OD0_Msk = 0x2
	// Bit OD0.
	GPIO_ODR_OD0 = 0x2
	// Set output to logic low
	GPIO_ODR_OD0_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD0_High = 0x1
	// Position of OD1 field.
	GPIO_ODR_OD1_Pos = 0x2
	// Bit mask of OD1 field.
	GPIO_ODR_OD1_Msk = 0x4
	// Bit OD1.
	GPIO_ODR_OD1 = 0x4
	// Set output to logic low
	GPIO_ODR_OD1_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD1_High = 0x1
	// Position of OD2 field.
	GPIO_ODR_OD2_Pos = 0x3
	// Bit mask of OD2 field.
	GPIO_ODR_OD2_Msk = 0x8
	// Bit OD2.
	GPIO_ODR_OD2 = 0x8
	// Set output to logic low
	GPIO_ODR_OD2_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD2_High = 0x1
	// Position of OD3 field.
	GPIO_ODR_OD3_Pos = 0x4
	// Bit mask of OD3 field.
	GPIO_ODR_OD3_Msk = 0x10
	// Bit OD3.
	GPIO_ODR_OD3 = 0x10
	// Set output to logic low
	GPIO_ODR_OD3_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD3_High = 0x1
	// Position of OD4 field.
	GPIO_ODR_OD4_Pos = 0x5
	// Bit mask of OD4 field.
	GPIO_ODR_OD4_Msk = 0x20
	// Bit OD4.
	GPIO_ODR_OD4 = 0x20
	// Set output to logic low
	GPIO_ODR_OD4_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD4_High = 0x1
	// Position of OD5 field.
	GPIO_ODR_OD5_Pos = 0x6
	// Bit mask of OD5 field.
	GPIO_ODR_OD5_Msk = 0x40
	// Bit OD5.
	GPIO_ODR_OD5 = 0x40
	// Set output to logic low
	GPIO_ODR_OD5_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD5_High = 0x1
	// Position of OD6 field.
	GPIO_ODR_OD6_Pos = 0x7
	// Bit mask of OD6 field.
	GPIO_ODR_OD6_Msk = 0x80
	// Bit OD6.
	GPIO_ODR_OD6 = 0x80
	// Set output to logic low
	GPIO_ODR_OD6_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD6_High = 0x1
	// Position of OD7 field.
	GPIO_ODR_OD7_Pos = 0x8
	// Bit mask of OD7 field.
	GPIO_ODR_OD7_Msk = 0x100
	// Bit OD7.
	GPIO_ODR_OD7 = 0x100
	// Set output to logic low
	GPIO_ODR_OD7_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD7_High = 0x1
	// Position of OD8 field.
	GPIO_ODR_OD8_Pos = 0x9
	// Bit mask of OD8 field.
	GPIO_ODR_OD8_Msk = 0x200
	// Bit OD8.
	GPIO_ODR_OD8 = 0x200
	// Set output to logic low
	GPIO_ODR_OD8_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD8_High = 0x1
	// Position of OD9 field.
	GPIO_ODR_OD9_Pos = 0xa
	// Bit mask of OD9 field.
	GPIO_ODR_OD9_Msk = 0x400
	// Bit OD9.
	GPIO_ODR_OD9 = 0x400
	// Set output to logic low
	GPIO_ODR_OD9_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD9_High = 0x1
	// Position of OD10 field.
	GPIO_ODR_OD10_Pos = 0xb
	// Bit mask of OD10 field.
	GPIO_ODR_OD10_Msk = 0x800
	// Bit OD10.
	GPIO_ODR_OD10 = 0x800
	// Set output to logic low
	GPIO_ODR_OD10_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD10_High = 0x1
	// Position of OD11 field.
	GPIO_ODR_OD11_Pos = 0xc
	// Bit mask of OD11 field.
	GPIO_ODR_OD11_Msk = 0x1000
	// Bit OD11.
	GPIO_ODR_OD11 = 0x1000
	// Set output to logic low
	GPIO_ODR_OD11_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD11_High = 0x1

	// BSRR: BSRR register
	// Position of BS0 field.
	GPIO_BSRR_BS0_Pos = 0x1
	// Bit mask of BS0 field.
	GPIO_BSRR_BS0_Msk = 0x2
	// Bit BS0.
	GPIO_BSRR_BS0 = 0x2
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS0_Set = 0x1
	// Position of BS1 field.
	GPIO_BSRR_BS1_Pos = 0x2
	// Bit mask of BS1 field.
	GPIO_BSRR_BS1_Msk = 0x4
	// Bit BS1.
	GPIO_BSRR_BS1 = 0x4
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS1_Set = 0x1
	// Position of BS2 field.
	GPIO_BSRR_BS2_Pos = 0x3
	// Bit mask of BS2 field.
	GPIO_BSRR_BS2_Msk = 0x8
	// Bit BS2.
	GPIO_BSRR_BS2 = 0x8
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS2_Set = 0x1
	// Position of BS3 field.
	GPIO_BSRR_BS3_Pos = 0x4
	// Bit mask of BS3 field.
	GPIO_BSRR_BS3_Msk = 0x10
	// Bit BS3.
	GPIO_BSRR_BS3 = 0x10
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS3_Set = 0x1
	// Position of BS4 field.
	GPIO_BSRR_BS4_Pos = 0x5
	// Bit mask of BS4 field.
	GPIO_BSRR_BS4_Msk = 0x20
	// Bit BS4.
	GPIO_BSRR_BS4 = 0x20
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS4_Set = 0x1
	// Position of BS5 field.
	GPIO_BSRR_BS5_Pos = 0x6
	// Bit mask of BS5 field.
	GPIO_BSRR_BS5_Msk = 0x40
	// Bit BS5.
	GPIO_BSRR_BS5 = 0x40
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS5_Set = 0x1
	// Position of BS6 field.
	GPIO_BSRR_BS6_Pos = 0x7
	// Bit mask of BS6 field.
	GPIO_BSRR_BS6_Msk = 0x80
	// Bit BS6.
	GPIO_BSRR_BS6 = 0x80
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS6_Set = 0x1
	// Position of BS7 field.
	GPIO_BSRR_BS7_Pos = 0x8
	// Bit mask of BS7 field.
	GPIO_BSRR_BS7_Msk = 0x100
	// Bit BS7.
	GPIO_BSRR_BS7 = 0x100
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS7_Set = 0x1
	// Position of BS8 field.
	GPIO_BSRR_BS8_Pos = 0x9
	// Bit mask of BS8 field.
	GPIO_BSRR_BS8_Msk = 0x200
	// Bit BS8.
	GPIO_BSRR_BS8 = 0x200
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS8_Set = 0x1
	// Position of BS9 field.
	GPIO_BSRR_BS9_Pos = 0xa
	// Bit mask of BS9 field.
	GPIO_BSRR_BS9_Msk = 0x400
	// Bit BS9.
	GPIO_BSRR_BS9 = 0x400
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS9_Set = 0x1
	// Position of BS10 field.
	GPIO_BSRR_BS10_Pos = 0xb
	// Bit mask of BS10 field.
	GPIO_BSRR_BS10_Msk = 0x800
	// Bit BS10.
	GPIO_BSRR_BS10 = 0x800
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS10_Set = 0x1
	// Position of BS11 field.
	GPIO_BSRR_BS11_Pos = 0xc
	// Bit mask of BS11 field.
	GPIO_BSRR_BS11_Msk = 0x1000
	// Bit BS11.
	GPIO_BSRR_BS11 = 0x1000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS11_Set = 0x1
	// Position of BR0 field.
	GPIO_BSRR_BR0_Pos = 0x11
	// Bit mask of BR0 field.
	GPIO_BSRR_BR0_Msk = 0x20000
	// Bit BR0.
	GPIO_BSRR_BR0 = 0x20000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BSRR_BR1_Pos = 0x12
	// Bit mask of BR1 field.
	GPIO_BSRR_BR1_Msk = 0x40000
	// Bit BR1.
	GPIO_BSRR_BR1 = 0x40000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BSRR_BR2_Pos = 0x13
	// Bit mask of BR2 field.
	GPIO_BSRR_BR2_Msk = 0x80000
	// Bit BR2.
	GPIO_BSRR_BR2 = 0x80000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BSRR_BR3_Pos = 0x14
	// Bit mask of BR3 field.
	GPIO_BSRR_BR3_Msk = 0x100000
	// Bit BR3.
	GPIO_BSRR_BR3 = 0x100000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BSRR_BR4_Pos = 0x15
	// Bit mask of BR4 field.
	GPIO_BSRR_BR4_Msk = 0x200000
	// Bit BR4.
	GPIO_BSRR_BR4 = 0x200000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BSRR_BR5_Pos = 0x16
	// Bit mask of BR5 field.
	GPIO_BSRR_BR5_Msk = 0x400000
	// Bit BR5.
	GPIO_BSRR_BR5 = 0x400000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BSRR_BR6_Pos = 0x17
	// Bit mask of BR6 field.
	GPIO_BSRR_BR6_Msk = 0x800000
	// Bit BR6.
	GPIO_BSRR_BR6 = 0x800000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BSRR_BR7_Pos = 0x18
	// Bit mask of BR7 field.
	GPIO_BSRR_BR7_Msk = 0x1000000
	// Bit BR7.
	GPIO_BSRR_BR7 = 0x1000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BSRR_BR8_Pos = 0x19
	// Bit mask of BR8 field.
	GPIO_BSRR_BR8_Msk = 0x2000000
	// Bit BR8.
	GPIO_BSRR_BR8 = 0x2000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BSRR_BR9_Pos = 0x1a
	// Bit mask of BR9 field.
	GPIO_BSRR_BR9_Msk = 0x4000000
	// Bit BR9.
	GPIO_BSRR_BR9 = 0x4000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BSRR_BR10_Pos = 0x1b
	// Bit mask of BR10 field.
	GPIO_BSRR_BR10_Msk = 0x8000000
	// Bit BR10.
	GPIO_BSRR_BR10 = 0x8000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BSRR_BR11_Pos = 0x1c
	// Bit mask of BR11 field.
	GPIO_BSRR_BR11_Msk = 0x10000000
	// Bit BR11.
	GPIO_BSRR_BR11 = 0x10000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR11_Reset = 0x1

	// LCKR: LCKR register
	// Position of LCK0 field.
	GPIO_LCKR_LCK0_Pos = 0x1
	// Bit mask of LCK0 field.
	GPIO_LCKR_LCK0_Msk = 0x2
	// Bit LCK0.
	GPIO_LCKR_LCK0 = 0x2
	// Port configuration not locked
	GPIO_LCKR_LCK0_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK0_Locked = 0x1
	// Position of LCK1 field.
	GPIO_LCKR_LCK1_Pos = 0x2
	// Bit mask of LCK1 field.
	GPIO_LCKR_LCK1_Msk = 0x4
	// Bit LCK1.
	GPIO_LCKR_LCK1 = 0x4
	// Port configuration not locked
	GPIO_LCKR_LCK1_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK1_Locked = 0x1
	// Position of LCK2 field.
	GPIO_LCKR_LCK2_Pos = 0x3
	// Bit mask of LCK2 field.
	GPIO_LCKR_LCK2_Msk = 0x8
	// Bit LCK2.
	GPIO_LCKR_LCK2 = 0x8
	// Port configuration not locked
	GPIO_LCKR_LCK2_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK2_Locked = 0x1
	// Position of LCK3 field.
	GPIO_LCKR_LCK3_Pos = 0x4
	// Bit mask of LCK3 field.
	GPIO_LCKR_LCK3_Msk = 0x10
	// Bit LCK3.
	GPIO_LCKR_LCK3 = 0x10
	// Port configuration not locked
	GPIO_LCKR_LCK3_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK3_Locked = 0x1
	// Position of LCK4 field.
	GPIO_LCKR_LCK4_Pos = 0x5
	// Bit mask of LCK4 field.
	GPIO_LCKR_LCK4_Msk = 0x20
	// Bit LCK4.
	GPIO_LCKR_LCK4 = 0x20
	// Port configuration not locked
	GPIO_LCKR_LCK4_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK4_Locked = 0x1
	// Position of LCK5 field.
	GPIO_LCKR_LCK5_Pos = 0x6
	// Bit mask of LCK5 field.
	GPIO_LCKR_LCK5_Msk = 0x40
	// Bit LCK5.
	GPIO_LCKR_LCK5 = 0x40
	// Port configuration not locked
	GPIO_LCKR_LCK5_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK5_Locked = 0x1
	// Position of LCK6 field.
	GPIO_LCKR_LCK6_Pos = 0x7
	// Bit mask of LCK6 field.
	GPIO_LCKR_LCK6_Msk = 0x80
	// Bit LCK6.
	GPIO_LCKR_LCK6 = 0x80
	// Port configuration not locked
	GPIO_LCKR_LCK6_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK6_Locked = 0x1
	// Position of LCK7 field.
	GPIO_LCKR_LCK7_Pos = 0x8
	// Bit mask of LCK7 field.
	GPIO_LCKR_LCK7_Msk = 0x100
	// Bit LCK7.
	GPIO_LCKR_LCK7 = 0x100
	// Port configuration not locked
	GPIO_LCKR_LCK7_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK7_Locked = 0x1
	// Position of LCK8 field.
	GPIO_LCKR_LCK8_Pos = 0x9
	// Bit mask of LCK8 field.
	GPIO_LCKR_LCK8_Msk = 0x200
	// Bit LCK8.
	GPIO_LCKR_LCK8 = 0x200
	// Port configuration not locked
	GPIO_LCKR_LCK8_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK8_Locked = 0x1
	// Position of LCK9 field.
	GPIO_LCKR_LCK9_Pos = 0xa
	// Bit mask of LCK9 field.
	GPIO_LCKR_LCK9_Msk = 0x400
	// Bit LCK9.
	GPIO_LCKR_LCK9 = 0x400
	// Port configuration not locked
	GPIO_LCKR_LCK9_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK9_Locked = 0x1
	// Position of LCK10 field.
	GPIO_LCKR_LCK10_Pos = 0xb
	// Bit mask of LCK10 field.
	GPIO_LCKR_LCK10_Msk = 0x800
	// Bit LCK10.
	GPIO_LCKR_LCK10 = 0x800
	// Port configuration not locked
	GPIO_LCKR_LCK10_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK10_Locked = 0x1
	// Position of LCK11 field.
	GPIO_LCKR_LCK11_Pos = 0xc
	// Bit mask of LCK11 field.
	GPIO_LCKR_LCK11_Msk = 0x1000
	// Bit LCK11.
	GPIO_LCKR_LCK11 = 0x1000
	// Port configuration not locked
	GPIO_LCKR_LCK11_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK11_Locked = 0x1
	// Position of LCKK field.
	GPIO_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIO_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIO_LCKR_LCKK = 0x10000
	// Port configuration lock key not active
	GPIO_LCKR_LCKK_NotActive = 0x0
	// Port configuration lock key active
	GPIO_LCKR_LCKK_Active = 0x1

	// AFRL: AFRL register
	// Position of AFSEL0 field.
	GPIO_AFRL_AFSEL0_Pos = 0x4
	// Bit mask of AFSEL0 field.
	GPIO_AFRL_AFSEL0_Msk = 0xf0
	// AF0
	GPIO_AFRL_AFSEL0_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL0_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL0_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL0_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL0_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL0_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL0_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL0_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL0_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL0_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL0_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL0_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL0_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL0_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL0_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL0_AF15 = 0xf
	// Position of AFSEL1 field.
	GPIO_AFRL_AFSEL1_Pos = 0x8
	// Bit mask of AFSEL1 field.
	GPIO_AFRL_AFSEL1_Msk = 0xf00
	// AF0
	GPIO_AFRL_AFSEL1_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL1_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL1_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL1_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL1_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL1_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL1_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL1_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL1_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL1_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL1_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL1_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL1_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL1_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL1_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL1_AF15 = 0xf
	// Position of AFSEL2 field.
	GPIO_AFRL_AFSEL2_Pos = 0xc
	// Bit mask of AFSEL2 field.
	GPIO_AFRL_AFSEL2_Msk = 0xf000
	// AF0
	GPIO_AFRL_AFSEL2_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL2_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL2_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL2_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL2_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL2_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL2_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL2_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL2_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL2_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL2_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL2_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL2_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL2_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL2_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL2_AF15 = 0xf
	// Position of AFSEL3 field.
	GPIO_AFRL_AFSEL3_Pos = 0x10
	// Bit mask of AFSEL3 field.
	GPIO_AFRL_AFSEL3_Msk = 0xf0000
	// AF0
	GPIO_AFRL_AFSEL3_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL3_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL3_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL3_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL3_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL3_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL3_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL3_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL3_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL3_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL3_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL3_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL3_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL3_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL3_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL3_AF15 = 0xf

	// AFRH: AFRH register
	// Position of AFSEL8 field.
	GPIO_AFRH_AFSEL8_Pos = 0x4
	// Bit mask of AFSEL8 field.
	GPIO_AFRH_AFSEL8_Msk = 0xf0
	// AF0
	GPIO_AFRH_AFSEL8_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL8_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL8_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL8_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL8_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL8_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL8_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL8_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL8_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL8_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL8_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL8_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL8_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL8_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL8_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL8_AF15 = 0xf
	// Position of AFSEL9 field.
	GPIO_AFRH_AFSEL9_Pos = 0x8
	// Bit mask of AFSEL9 field.
	GPIO_AFRH_AFSEL9_Msk = 0xf00
	// AF0
	GPIO_AFRH_AFSEL9_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL9_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL9_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL9_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL9_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL9_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL9_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL9_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL9_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL9_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL9_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL9_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL9_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL9_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL9_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL9_AF15 = 0xf
	// Position of AFSEL10 field.
	GPIO_AFRH_AFSEL10_Pos = 0xc
	// Bit mask of AFSEL10 field.
	GPIO_AFRH_AFSEL10_Msk = 0xf000
	// AF0
	GPIO_AFRH_AFSEL10_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL10_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL10_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL10_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL10_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL10_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL10_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL10_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL10_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL10_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL10_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL10_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL10_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL10_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL10_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL10_AF15 = 0xf
	// Position of AFSEL11 field.
	GPIO_AFRH_AFSEL11_Pos = 0x10
	// Bit mask of AFSEL11 field.
	GPIO_AFRH_AFSEL11_Msk = 0xf0000
	// AF0
	GPIO_AFRH_AFSEL11_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL11_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL11_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL11_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL11_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL11_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL11_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL11_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL11_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL11_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL11_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL11_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL11_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL11_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL11_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL11_AF15 = 0xf

	// BRR: BRR register
	// Position of BR0 field.
	GPIO_BRR_BR0_Pos = 0x1
	// Bit mask of BR0 field.
	GPIO_BRR_BR0_Msk = 0x2
	// Bit BR0.
	GPIO_BRR_BR0 = 0x2
	// No action on the corresponding ODx bit
	GPIO_BRR_BR0_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BRR_BR1_Pos = 0x2
	// Bit mask of BR1 field.
	GPIO_BRR_BR1_Msk = 0x4
	// Bit BR1.
	GPIO_BRR_BR1 = 0x4
	// No action on the corresponding ODx bit
	GPIO_BRR_BR1_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BRR_BR2_Pos = 0x3
	// Bit mask of BR2 field.
	GPIO_BRR_BR2_Msk = 0x8
	// Bit BR2.
	GPIO_BRR_BR2 = 0x8
	// No action on the corresponding ODx bit
	GPIO_BRR_BR2_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BRR_BR3_Pos = 0x4
	// Bit mask of BR3 field.
	GPIO_BRR_BR3_Msk = 0x10
	// Bit BR3.
	GPIO_BRR_BR3 = 0x10
	// No action on the corresponding ODx bit
	GPIO_BRR_BR3_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BRR_BR4_Pos = 0x5
	// Bit mask of BR4 field.
	GPIO_BRR_BR4_Msk = 0x20
	// Bit BR4.
	GPIO_BRR_BR4 = 0x20
	// No action on the corresponding ODx bit
	GPIO_BRR_BR4_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BRR_BR5_Pos = 0x6
	// Bit mask of BR5 field.
	GPIO_BRR_BR5_Msk = 0x40
	// Bit BR5.
	GPIO_BRR_BR5 = 0x40
	// No action on the corresponding ODx bit
	GPIO_BRR_BR5_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BRR_BR6_Pos = 0x7
	// Bit mask of BR6 field.
	GPIO_BRR_BR6_Msk = 0x80
	// Bit BR6.
	GPIO_BRR_BR6 = 0x80
	// No action on the corresponding ODx bit
	GPIO_BRR_BR6_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BRR_BR7_Pos = 0x8
	// Bit mask of BR7 field.
	GPIO_BRR_BR7_Msk = 0x100
	// Bit BR7.
	GPIO_BRR_BR7 = 0x100
	// No action on the corresponding ODx bit
	GPIO_BRR_BR7_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BRR_BR8_Pos = 0x9
	// Bit mask of BR8 field.
	GPIO_BRR_BR8_Msk = 0x200
	// Bit BR8.
	GPIO_BRR_BR8 = 0x200
	// No action on the corresponding ODx bit
	GPIO_BRR_BR8_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BRR_BR9_Pos = 0xa
	// Bit mask of BR9 field.
	GPIO_BRR_BR9_Msk = 0x400
	// Bit BR9.
	GPIO_BRR_BR9 = 0x400
	// No action on the corresponding ODx bit
	GPIO_BRR_BR9_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BRR_BR10_Pos = 0xb
	// Bit mask of BR10 field.
	GPIO_BRR_BR10_Msk = 0x800
	// Bit BR10.
	GPIO_BRR_BR10 = 0x800
	// No action on the corresponding ODx bit
	GPIO_BRR_BR10_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BRR_BR11_Pos = 0xc
	// Bit mask of BR11 field.
	GPIO_BRR_BR11_Msk = 0x1000
	// Bit BR11.
	GPIO_BRR_BR11 = 0x1000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR11_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR11_Reset = 0x1
)

// Constants for IWDG
const (
	// KR: IWDG_KR register
	// Position of KEY field.
	IWDG_KR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	IWDG_KR_KEY_Msk = 0xffff
	// Enable access to PR, RLR and WINR registers
	IWDG_KR_KEY_Unlock = 0x5555
	// Feed watchdog with RLR register value
	IWDG_KR_KEY_Feed = 0xaaaa
	// Start the watchdog
	IWDG_KR_KEY_Start = 0xcccc

	// PR: IWDG_PR register
	// Position of PR field.
	IWDG_PR_PR_Pos = 0x0
	// Bit mask of PR field.
	IWDG_PR_PR_Msk = 0x7
	// Divider /4
	IWDG_PR_PR_DivideBy4 = 0x0
	// Divider /8
	IWDG_PR_PR_DivideBy8 = 0x1
	// Divider /16
	IWDG_PR_PR_DivideBy16 = 0x2
	// Divider /32
	IWDG_PR_PR_DivideBy32 = 0x3
	// Divider /64
	IWDG_PR_PR_DivideBy64 = 0x4
	// Divider /128
	IWDG_PR_PR_DivideBy128 = 0x5
	// Divider /256
	IWDG_PR_PR_DivideBy256 = 0x6

	// RLR: IWDG_RLR register
	// Position of RL field.
	IWDG_RLR_RL_Pos = 0x0
	// Bit mask of RL field.
	IWDG_RLR_RL_Msk = 0xfff

	// SR: IWDG_SR register
	// Position of PVU field.
	IWDG_SR_PVU_Pos = 0x0
	// Bit mask of PVU field.
	IWDG_SR_PVU_Msk = 0x1
	// Bit PVU.
	IWDG_SR_PVU = 0x1
	// Position of RVU field.
	IWDG_SR_RVU_Pos = 0x1
	// Bit mask of RVU field.
	IWDG_SR_RVU_Msk = 0x2
	// Bit RVU.
	IWDG_SR_RVU = 0x2
	// Position of WVU field.
	IWDG_SR_WVU_Pos = 0x2
	// Bit mask of WVU field.
	IWDG_SR_WVU_Msk = 0x4
	// Bit WVU.
	IWDG_SR_WVU = 0x4

	// WINR: IWDG_WINR register
	// Position of WIN field.
	IWDG_WINR_WIN_Pos = 0x0
	// Bit mask of WIN field.
	IWDG_WINR_WIN_Msk = 0xfff
)

// Constants for LPUART
const (
	// CR1: CR1 register
	// Position of UE field.
	LPUART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	LPUART_CR1_UE_Msk = 0x1
	// Bit UE.
	LPUART_CR1_UE = 0x1
	// UART is disabled
	LPUART_CR1_UE_Disabled = 0x0
	// UART is enabled
	LPUART_CR1_UE_Enabled = 0x1
	// Position of UESM field.
	LPUART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	LPUART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	LPUART_CR1_UESM = 0x2
	// Position of RE field.
	LPUART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	LPUART_CR1_RE_Msk = 0x4
	// Bit RE.
	LPUART_CR1_RE = 0x4
	// Receiver is disabled
	LPUART_CR1_RE_Disabled = 0x0
	// Receiver is enabled
	LPUART_CR1_RE_Enabled = 0x1
	// Position of TE field.
	LPUART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	LPUART_CR1_TE_Msk = 0x8
	// Bit TE.
	LPUART_CR1_TE = 0x8
	// Transmitter is disabled
	LPUART_CR1_TE_Disabled = 0x0
	// Transmitter is enabled
	LPUART_CR1_TE_Enabled = 0x1
	// Position of IDLEIE field.
	LPUART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	LPUART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	LPUART_CR1_IDLEIE = 0x10
	// Interrupt is disabled
	LPUART_CR1_IDLEIE_Disabled = 0x0
	// Interrupt is generated whenever IDLE=1 in the ISR register
	LPUART_CR1_IDLEIE_Enabled = 0x1
	// Position of RXNEIE field.
	LPUART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	LPUART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	LPUART_CR1_RXNEIE = 0x20
	// Interrupt is disabled
	LPUART_CR1_RXNEIE_Disabled = 0x0
	// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
	LPUART_CR1_RXNEIE_Enabled = 0x1
	// Position of TCIE field.
	LPUART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	LPUART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	LPUART_CR1_TCIE = 0x40
	// Interrupt is disabled
	LPUART_CR1_TCIE_Disabled = 0x0
	// Interrupt is generated whenever TC=1 in the ISR register
	LPUART_CR1_TCIE_Enabled = 0x1
	// Position of TXEIE field.
	LPUART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	LPUART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	LPUART_CR1_TXEIE = 0x80
	// Interrupt is disabled
	LPUART_CR1_TXEIE_Disabled = 0x0
	// Interrupt is generated whenever TXE=1 in the ISR register
	LPUART_CR1_TXEIE_Enabled = 0x1
	// Position of PEIE field.
	LPUART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	LPUART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	LPUART_CR1_PEIE = 0x100
	// Interrupt is disabled
	LPUART_CR1_PEIE_Disabled = 0x0
	// Interrupt is generated whenever PE=1 in the ISR register
	LPUART_CR1_PEIE_Enabled = 0x1
	// Position of PS field.
	LPUART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	LPUART_CR1_PS_Msk = 0x200
	// Bit PS.
	LPUART_CR1_PS = 0x200
	// Even parity
	LPUART_CR1_PS_Even = 0x0
	// Odd parity
	LPUART_CR1_PS_Odd = 0x1
	// Position of PCE field.
	LPUART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	LPUART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	LPUART_CR1_PCE = 0x400
	// Parity control disabled
	LPUART_CR1_PCE_Disabled = 0x0
	// Parity control enabled
	LPUART_CR1_PCE_Enabled = 0x1
	// Position of WAKE field.
	LPUART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	LPUART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	LPUART_CR1_WAKE = 0x800
	// Idle line
	LPUART_CR1_WAKE_Idle = 0x0
	// Address mask
	LPUART_CR1_WAKE_Address = 0x1
	// Position of M0 field.
	LPUART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	LPUART_CR1_M0_Msk = 0x1000
	// Bit M0.
	LPUART_CR1_M0 = 0x1000
	// 1 start bit, 8 data bits, n stop bits
	LPUART_CR1_M0_Bit8 = 0x0
	// 1 start bit, 9 data bits, n stop bits
	LPUART_CR1_M0_Bit9 = 0x1
	// Position of MME field.
	LPUART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	LPUART_CR1_MME_Msk = 0x2000
	// Bit MME.
	LPUART_CR1_MME = 0x2000
	// Receiver in active mode permanently
	LPUART_CR1_MME_Disabled = 0x0
	// Receiver can switch between mute mode and active mode
	LPUART_CR1_MME_Enabled = 0x1
	// Position of CMIE field.
	LPUART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	LPUART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	LPUART_CR1_CMIE = 0x4000
	// Interrupt is disabled
	LPUART_CR1_CMIE_Disabled = 0x0
	// Interrupt is generated when the CMF bit is set in the ISR register
	LPUART_CR1_CMIE_Enabled = 0x1
	// Position of DEDT field.
	LPUART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	LPUART_CR1_DEDT_Msk = 0x1f0000
	// Position of DEAT field.
	LPUART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	LPUART_CR1_DEAT_Msk = 0x3e00000
	// Position of M1 field.
	LPUART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	LPUART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	LPUART_CR1_M1 = 0x10000000
	// Use M0 to set the data bits
	LPUART_CR1_M1_M0 = 0x0
	// 1 start bit, 7 data bits, n stop bits
	LPUART_CR1_M1_Bit7 = 0x1
	// Position of FIFOEN field.
	LPUART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	LPUART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	LPUART_CR1_FIFOEN = 0x20000000
	// FIFO mode is disabled
	LPUART_CR1_FIFOEN_Disabled = 0x0
	// FIFO mode is enabled
	LPUART_CR1_FIFOEN_Enabled = 0x1
	// Position of TXFEIE field.
	LPUART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	LPUART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	LPUART_CR1_TXFEIE = 0x40000000
	// Interrupt inhibited
	LPUART_CR1_TXFEIE_Disabled = 0x0
	// USART interrupt generated when TXFE = 1 in the USART_ISR register
	LPUART_CR1_TXFEIE_Enabled = 0x1
	// Position of RXFFIE field.
	LPUART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	LPUART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	LPUART_CR1_RXFFIE = 0x80000000
	// Interrupt inhibited
	LPUART_CR1_RXFFIE_Disabled = 0x0
	// USART interrupt generated when RXFF = 1 in the USART_ISR register
	LPUART_CR1_RXFFIE_Enabled = 0x1

	// CR2: CR2 register
	// Position of ADDM7 field.
	LPUART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	LPUART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	LPUART_CR2_ADDM7 = 0x10
	// 4-bit address detection
	LPUART_CR2_ADDM7_Bit4 = 0x0
	// 7-bit address detection
	LPUART_CR2_ADDM7_Bit7 = 0x1
	// Position of STOP field.
	LPUART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	LPUART_CR2_STOP_Msk = 0x3000
	// 1 stop bit
	LPUART_CR2_STOP_Stop1 = 0x0
	// 2 stop bit
	LPUART_CR2_STOP_Stop2 = 0x2
	// Position of SWAP field.
	LPUART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	LPUART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	LPUART_CR2_SWAP = 0x8000
	// TX/RX pins are used as defined in standard pinout
	LPUART_CR2_SWAP_Standard = 0x0
	// The TX and RX pins functions are swapped
	LPUART_CR2_SWAP_Swapped = 0x1
	// Position of RXINV field.
	LPUART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	LPUART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	LPUART_CR2_RXINV = 0x10000
	// RX pin signal works using the standard logic levels
	LPUART_CR2_RXINV_Standard = 0x0
	// RX pin signal values are inverted
	LPUART_CR2_RXINV_Inverted = 0x1
	// Position of TXINV field.
	LPUART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	LPUART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	LPUART_CR2_TXINV = 0x20000
	// TX pin signal works using the standard logic levels
	LPUART_CR2_TXINV_Standard = 0x0
	// TX pin signal values are inverted
	LPUART_CR2_TXINV_Inverted = 0x1
	// Position of DATAINV field.
	LPUART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	LPUART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	LPUART_CR2_DATAINV = 0x40000
	// Logical data from the data register are send/received in positive/direct logic
	LPUART_CR2_DATAINV_Positive = 0x0
	// Logical data from the data register are send/received in negative/inverse logic
	LPUART_CR2_DATAINV_Negative = 0x1
	// Position of MSBFIRST field.
	LPUART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	LPUART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	LPUART_CR2_MSBFIRST = 0x80000
	// data is transmitted/received with data bit 0 first, following the start bit
	LPUART_CR2_MSBFIRST_LSB = 0x0
	// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
	LPUART_CR2_MSBFIRST_MSB = 0x1
	// Position of ADD field.
	LPUART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	LPUART_CR2_ADD_Msk = 0xff000000

	// CR3: CR3 register
	// Position of EIE field.
	LPUART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	LPUART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	LPUART_CR3_EIE = 0x1
	// Interrupt is inhibited
	LPUART_CR3_EIE_Disabled = 0x0
	// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
	LPUART_CR3_EIE_Enabled = 0x1
	// Position of HDSEL field.
	LPUART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	LPUART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	LPUART_CR3_HDSEL = 0x8
	// Half duplex mode is not selected
	LPUART_CR3_HDSEL_NotSelected = 0x0
	// Half duplex mode is selected
	LPUART_CR3_HDSEL_Selected = 0x1
	// Position of DMAR field.
	LPUART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	LPUART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	LPUART_CR3_DMAR = 0x40
	// DMA mode is disabled for reception
	LPUART_CR3_DMAR_Disabled = 0x0
	// DMA mode is enabled for reception
	LPUART_CR3_DMAR_Enabled = 0x1
	// Position of DMAT field.
	LPUART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	LPUART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	LPUART_CR3_DMAT = 0x80
	// DMA mode is disabled for transmission
	LPUART_CR3_DMAT_Disabled = 0x0
	// DMA mode is enabled for transmission
	LPUART_CR3_DMAT_Enabled = 0x1
	// Position of RTSE field.
	LPUART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	LPUART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	LPUART_CR3_RTSE = 0x100
	// RTS hardware flow control disabled
	LPUART_CR3_RTSE_Disabled = 0x0
	// RTS output enabled, data is only requested when there is space in the receive buffer
	LPUART_CR3_RTSE_Enabled = 0x1
	// Position of CTSE field.
	LPUART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	LPUART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	LPUART_CR3_CTSE = 0x200
	// CTS hardware flow control disabled
	LPUART_CR3_CTSE_Disabled = 0x0
	// CTS mode enabled, data is only transmitted when the CTS input is asserted
	LPUART_CR3_CTSE_Enabled = 0x1
	// Position of CTSIE field.
	LPUART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	LPUART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	LPUART_CR3_CTSIE = 0x400
	// Interrupt is inhibited
	LPUART_CR3_CTSIE_Disabled = 0x0
	// An interrupt is generated whenever CTSIF=1 in the ISR register
	LPUART_CR3_CTSIE_Enabled = 0x1
	// Position of OVRDIS field.
	LPUART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	LPUART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	LPUART_CR3_OVRDIS = 0x1000
	// Overrun Error Flag, ORE, is set when received data is not read before receiving new data
	LPUART_CR3_OVRDIS_Enabled = 0x0
	// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
	LPUART_CR3_OVRDIS_Disabled = 0x1
	// Position of DDRE field.
	LPUART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	LPUART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	LPUART_CR3_DDRE = 0x2000
	// DMA is not disabled in case of reception error
	LPUART_CR3_DDRE_NotDisabled = 0x0
	// DMA is disabled following a reception error
	LPUART_CR3_DDRE_Disabled = 0x1
	// Position of DEM field.
	LPUART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	LPUART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	LPUART_CR3_DEM = 0x4000
	// DE function is disabled
	LPUART_CR3_DEM_Disabled = 0x0
	// The DE signal is output on the RTS pin
	LPUART_CR3_DEM_Enabled = 0x1
	// Position of DEP field.
	LPUART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	LPUART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	LPUART_CR3_DEP = 0x8000
	// DE signal is active high
	LPUART_CR3_DEP_High = 0x0
	// DE signal is active low
	LPUART_CR3_DEP_Low = 0x1
	// Position of WUS field.
	LPUART_CR3_WUS_Pos = 0x14
	// Bit mask of WUS field.
	LPUART_CR3_WUS_Msk = 0x300000
	// Position of WUFIE field.
	LPUART_CR3_WUFIE_Pos = 0x16
	// Bit mask of WUFIE field.
	LPUART_CR3_WUFIE_Msk = 0x400000
	// Bit WUFIE.
	LPUART_CR3_WUFIE = 0x400000
	// Position of TXFTIE field.
	LPUART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	LPUART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	LPUART_CR3_TXFTIE = 0x800000
	// Interrupt inhibited
	LPUART_CR3_TXFTIE_Disabled = 0x0
	// USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
	LPUART_CR3_TXFTIE_Enabled = 0x1
	// Position of RXFTCFG field.
	LPUART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	LPUART_CR3_RXFTCFG_Msk = 0xe000000
	// RXFIFO reaches 1/8 of its depth
	LPUART_CR3_RXFTCFG_Depth_1_8 = 0x0
	// RXFIFO reaches 1/4 of its depth
	LPUART_CR3_RXFTCFG_Depth_1_4 = 0x1
	// RXFIFO reaches 1/2 of its depth
	LPUART_CR3_RXFTCFG_Depth_1_2 = 0x2
	// RXFIFO reaches 3/4 of its depth
	LPUART_CR3_RXFTCFG_Depth_3_4 = 0x3
	// RXFIFO reaches 7/8 of its depth
	LPUART_CR3_RXFTCFG_Depth_7_8 = 0x4
	// RXFIFO becomes full
	LPUART_CR3_RXFTCFG_Full = 0x5
	// Position of RXFTIE field.
	LPUART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	LPUART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	LPUART_CR3_RXFTIE = 0x10000000
	// Interrupt inhibited
	LPUART_CR3_RXFTIE_Disabled = 0x0
	// USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
	LPUART_CR3_RXFTIE_Enabled = 0x1
	// Position of TXFTCFG field.
	LPUART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	LPUART_CR3_TXFTCFG_Msk = 0xe0000000
	// TXFIFO reaches 1/8 of its depth
	LPUART_CR3_TXFTCFG_Depth_1_8 = 0x0
	// TXFIFO reaches 1/4 of its depth
	LPUART_CR3_TXFTCFG_Depth_1_4 = 0x1
	// TXFIFO reaches 1/2 of its depth
	LPUART_CR3_TXFTCFG_Depth_1_2 = 0x2
	// TXFIFO reaches 3/4 of its depth
	LPUART_CR3_TXFTCFG_Depth_3_4 = 0x3
	// TXFIFO reaches 7/8 of its depth
	LPUART_CR3_TXFTCFG_Depth_7_8 = 0x4
	// TXFIFO becomes empty
	LPUART_CR3_TXFTCFG_Empty = 0x5

	// BRR: BRR register
	// Position of BRR field.
	LPUART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	LPUART_BRR_BRR_Msk = 0xfffff

	// RQR: RQR register
	// Position of SBKRQ field.
	LPUART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	LPUART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	LPUART_RQR_SBKRQ = 0x2
	// sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
	LPUART_RQR_SBKRQ_Break = 0x1
	// Position of MMRQ field.
	LPUART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	LPUART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	LPUART_RQR_MMRQ = 0x4
	// Puts the USART in mute mode and sets the RWU flag
	LPUART_RQR_MMRQ_Mute = 0x1
	// Position of RXFRQ field.
	LPUART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	LPUART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	LPUART_RQR_RXFRQ = 0x8
	// clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
	LPUART_RQR_RXFRQ_Discard = 0x1
	// Position of TXFRQ field.
	LPUART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	LPUART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	LPUART_RQR_TXFRQ = 0x10
	// Set the TXE flags. This allows to discard the transmit data
	LPUART_RQR_TXFRQ_Discard = 0x1

	// ISR: ISR register
	// Position of PE field.
	LPUART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	LPUART_ISR_PE_Msk = 0x1
	// Bit PE.
	LPUART_ISR_PE = 0x1
	// No parity error
	LPUART_ISR_PE_NoError = 0x0
	// Parity error
	LPUART_ISR_PE_Error = 0x1
	// Position of FE field.
	LPUART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	LPUART_ISR_FE_Msk = 0x2
	// Bit FE.
	LPUART_ISR_FE = 0x2
	// No Framing error is detected
	LPUART_ISR_FE_NoError = 0x0
	// Framing error or break character is detected
	LPUART_ISR_FE_Error = 0x1
	// Position of NF field.
	LPUART_ISR_NF_Pos = 0x2
	// Bit mask of NF field.
	LPUART_ISR_NF_Msk = 0x4
	// Bit NF.
	LPUART_ISR_NF = 0x4
	// No noise is detected
	LPUART_ISR_NF_NoNoise = 0x0
	// Noise is detected
	LPUART_ISR_NF_Noise = 0x1
	// Position of ORE field.
	LPUART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	LPUART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	LPUART_ISR_ORE = 0x8
	// No Overrun error
	LPUART_ISR_ORE_NoOverrun = 0x0
	// Overrun error is detected
	LPUART_ISR_ORE_Overrun = 0x1
	// Position of IDLE field.
	LPUART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	LPUART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	LPUART_ISR_IDLE = 0x10
	// No Idle Line is detected
	LPUART_ISR_IDLE_NoIdle = 0x0
	// Idle Line is detected
	LPUART_ISR_IDLE_Idle = 0x1
	// Position of RXNE field.
	LPUART_ISR_RXNE_Pos = 0x5
	// Bit mask of RXNE field.
	LPUART_ISR_RXNE_Msk = 0x20
	// Bit RXNE.
	LPUART_ISR_RXNE = 0x20
	// Data is not received
	LPUART_ISR_RXNE_NoData = 0x0
	// Received data is ready to be read
	LPUART_ISR_RXNE_DataReady = 0x1
	// Position of TC field.
	LPUART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	LPUART_ISR_TC_Msk = 0x40
	// Bit TC.
	LPUART_ISR_TC = 0x40
	// Transmission is not complete
	LPUART_ISR_TC_TxNotComplete = 0x0
	// Transmission is complete
	LPUART_ISR_TC_TxComplete = 0x1
	// Position of TXE field.
	LPUART_ISR_TXE_Pos = 0x7
	// Bit mask of TXE field.
	LPUART_ISR_TXE_Msk = 0x80
	// Bit TXE.
	LPUART_ISR_TXE = 0x80
	// Transmit FIFO is full
	LPUART_ISR_TXE_Full = 0x0
	// Transmit FIFO is not full
	LPUART_ISR_TXE_NotFull = 0x1
	// Position of CTSIF field.
	LPUART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	LPUART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	LPUART_ISR_CTSIF = 0x200
	// No change occurred on the CTS status line
	LPUART_ISR_CTSIF_NotChanged = 0x0
	// A change occurred on the CTS status line
	LPUART_ISR_CTSIF_Changed = 0x1
	// Position of CTS field.
	LPUART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	LPUART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	LPUART_ISR_CTS = 0x400
	// CTS line set
	LPUART_ISR_CTS_Set = 0x0
	// CTS line reset
	LPUART_ISR_CTS_Reset = 0x1
	// Position of BUSY field.
	LPUART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	LPUART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	LPUART_ISR_BUSY = 0x10000
	// USART is idle (no reception)
	LPUART_ISR_BUSY_Idle = 0x0
	// Reception on going
	LPUART_ISR_BUSY_Busy = 0x1
	// Position of CMF field.
	LPUART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	LPUART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	LPUART_ISR_CMF = 0x20000
	// No Character match detected
	LPUART_ISR_CMF_NoMatch = 0x0
	// Character match detected
	LPUART_ISR_CMF_Match = 0x1
	// Position of SBKF field.
	LPUART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	LPUART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	LPUART_ISR_SBKF = 0x40000
	// No break character transmitted
	LPUART_ISR_SBKF_NoBreak = 0x0
	// Break character transmitted
	LPUART_ISR_SBKF_Break = 0x1
	// Position of RWU field.
	LPUART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	LPUART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	LPUART_ISR_RWU = 0x80000
	// Position of WUF field.
	LPUART_ISR_WUF_Pos = 0x14
	// Bit mask of WUF field.
	LPUART_ISR_WUF_Msk = 0x100000
	// Bit WUF.
	LPUART_ISR_WUF = 0x100000
	// Position of TEACK field.
	LPUART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	LPUART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	LPUART_ISR_TEACK = 0x200000
	// Position of REACK field.
	LPUART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	LPUART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	LPUART_ISR_REACK = 0x400000
	// Position of TXFE field.
	LPUART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	LPUART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	LPUART_ISR_TXFE = 0x800000
	// TXFIFO not empty.
	LPUART_ISR_TXFE_NotEmpty = 0x0
	// TXFIFO empty.
	LPUART_ISR_TXFE_Empty = 0x1
	// Position of RXFF field.
	LPUART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	LPUART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	LPUART_ISR_RXFF = 0x1000000
	// RXFIFO not full.
	LPUART_ISR_RXFF_NotFull = 0x0
	// RXFIFO Full.
	LPUART_ISR_RXFF_Full = 0x1
	// Position of RXFT field.
	LPUART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	LPUART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	LPUART_ISR_RXFT = 0x4000000
	// Receive FIFO does not reach the programmed threshold.
	LPUART_ISR_RXFT_NotReached = 0x0
	// Receive FIFO reached the programmed threshold.
	LPUART_ISR_RXFT_Reached = 0x1
	// Position of TXFT field.
	LPUART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	LPUART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	LPUART_ISR_TXFT = 0x8000000
	// TXFIFO does not reach the programmed threshold.
	LPUART_ISR_TXFT_NotReached = 0x0
	// TXFIFO reached the programmed threshold.
	LPUART_ISR_TXFT_Reached = 0x1

	// ICR: ICR register
	// Position of PECF field.
	LPUART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	LPUART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	LPUART_ICR_PECF = 0x1
	// Clears the PE flag in the ISR register
	LPUART_ICR_PECF_Clear = 0x1
	// Position of FECF field.
	LPUART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	LPUART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	LPUART_ICR_FECF = 0x2
	// Clears the FE flag in the ISR register
	LPUART_ICR_FECF_Clear = 0x1
	// Position of NECF field.
	LPUART_ICR_NECF_Pos = 0x2
	// Bit mask of NECF field.
	LPUART_ICR_NECF_Msk = 0x4
	// Bit NECF.
	LPUART_ICR_NECF = 0x4
	// Clears the NF flag in the ISR register
	LPUART_ICR_NECF_Clear = 0x1
	// Position of ORECF field.
	LPUART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	LPUART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	LPUART_ICR_ORECF = 0x8
	// Clears the ORE flag in the ISR register
	LPUART_ICR_ORECF_Clear = 0x1
	// Position of IDLECF field.
	LPUART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	LPUART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	LPUART_ICR_IDLECF = 0x10
	// Clears the IDLE flag in the ISR register
	LPUART_ICR_IDLECF_Clear = 0x1
	// Position of TCCF field.
	LPUART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	LPUART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	LPUART_ICR_TCCF = 0x40
	// Clears the TC flag in the ISR register
	LPUART_ICR_TCCF_Clear = 0x1
	// Position of CTSCF field.
	LPUART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	LPUART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	LPUART_ICR_CTSCF = 0x200
	// Clears the CTSIF flag in the ISR register
	LPUART_ICR_CTSCF_Clear = 0x1
	// Position of CMCF field.
	LPUART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	LPUART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	LPUART_ICR_CMCF = 0x20000
	// Clears the CMF flag in the ISR register
	LPUART_ICR_CMCF_Clear = 0x1
	// Position of WUCF field.
	LPUART_ICR_WUCF_Pos = 0x14
	// Bit mask of WUCF field.
	LPUART_ICR_WUCF_Msk = 0x100000
	// Bit WUCF.
	LPUART_ICR_WUCF = 0x100000

	// RDR: RDR register
	// Position of RDR field.
	LPUART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	LPUART_RDR_RDR_Msk = 0x1ff

	// TDR: TDR register
	// Position of TDR field.
	LPUART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	LPUART_TDR_TDR_Msk = 0x1ff

	// PRESC: PRESC register
	// Position of PRESCALER field.
	LPUART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	LPUART_PRESC_PRESCALER_Msk = 0xf
	// /1
	LPUART_PRESC_PRESCALER_Div1 = 0x0
	// /2
	LPUART_PRESC_PRESCALER_Div2 = 0x1
	// /4
	LPUART_PRESC_PRESCALER_Div4 = 0x2
	// /6
	LPUART_PRESC_PRESCALER_Div6 = 0x3
	// /8
	LPUART_PRESC_PRESCALER_Div8 = 0x4
	// /10
	LPUART_PRESC_PRESCALER_Div10 = 0x5
	// /12
	LPUART_PRESC_PRESCALER_Div12 = 0x6
	// /16
	LPUART_PRESC_PRESCALER_Div16 = 0x7
	// /32
	LPUART_PRESC_PRESCALER_Div32 = 0x8
	// /64
	LPUART_PRESC_PRESCALER_Div64 = 0x9
	// /128
	LPUART_PRESC_PRESCALER_Div128 = 0xa
	// /256
	LPUART_PRESC_PRESCALER_Div256 = 0xb
)

// Constants for FLASH_CTRL: 4kb addressable space
const (
	// COMMAND: COMMAND register
	// Position of COMMAND field.
	FLASH_CTRL_COMMAND_COMMAND_Pos = 0x0
	// Bit mask of COMMAND field.
	FLASH_CTRL_COMMAND_COMMAND_Msk = 0xff

	// CONFIG: CONFIG register
	// Position of REMAP field.
	FLASH_CTRL_CONFIG_REMAP_Pos = 0x1
	// Bit mask of REMAP field.
	FLASH_CTRL_CONFIG_REMAP_Msk = 0x2
	// Bit REMAP.
	FLASH_CTRL_CONFIG_REMAP = 0x2
	// Position of DIS_GROUP_WRITE field.
	FLASH_CTRL_CONFIG_DIS_GROUP_WRITE_Pos = 0x2
	// Bit mask of DIS_GROUP_WRITE field.
	FLASH_CTRL_CONFIG_DIS_GROUP_WRITE_Msk = 0x4
	// Bit DIS_GROUP_WRITE.
	FLASH_CTRL_CONFIG_DIS_GROUP_WRITE = 0x4
	// Position of WAIT_STATE field.
	FLASH_CTRL_CONFIG_WAIT_STATE_Pos = 0x4
	// Bit mask of WAIT_STATE field.
	FLASH_CTRL_CONFIG_WAIT_STATE_Msk = 0x30

	// IRQSTAT: IRQSTAT register
	// Position of CMDDONE_MIS field.
	FLASH_CTRL_IRQSTAT_CMDDONE_MIS_Pos = 0x0
	// Bit mask of CMDDONE_MIS field.
	FLASH_CTRL_IRQSTAT_CMDDONE_MIS_Msk = 0x1
	// Bit CMDDONE_MIS.
	FLASH_CTRL_IRQSTAT_CMDDONE_MIS = 0x1
	// Position of CMDSTART_MIS field.
	FLASH_CTRL_IRQSTAT_CMDSTART_MIS_Pos = 0x1
	// Bit mask of CMDSTART_MIS field.
	FLASH_CTRL_IRQSTAT_CMDSTART_MIS_Msk = 0x2
	// Bit CMDSTART_MIS.
	FLASH_CTRL_IRQSTAT_CMDSTART_MIS = 0x2
	// Position of CMDBUSYERR_MIS field.
	FLASH_CTRL_IRQSTAT_CMDBUSYERR_MIS_Pos = 0x2
	// Bit mask of CMDBUSYERR_MIS field.
	FLASH_CTRL_IRQSTAT_CMDBUSYERR_MIS_Msk = 0x4
	// Bit CMDBUSYERR_MIS.
	FLASH_CTRL_IRQSTAT_CMDBUSYERR_MIS = 0x4
	// Position of ILLCMD_MIS field.
	FLASH_CTRL_IRQSTAT_ILLCMD_MIS_Pos = 0x3
	// Bit mask of ILLCMD_MIS field.
	FLASH_CTRL_IRQSTAT_ILLCMD_MIS_Msk = 0x8
	// Bit ILLCMD_MIS.
	FLASH_CTRL_IRQSTAT_ILLCMD_MIS = 0x8
	// Position of READOK_MIS field.
	FLASH_CTRL_IRQSTAT_READOK_MIS_Pos = 0x4
	// Bit mask of READOK_MIS field.
	FLASH_CTRL_IRQSTAT_READOK_MIS_Msk = 0x10
	// Bit READOK_MIS.
	FLASH_CTRL_IRQSTAT_READOK_MIS = 0x10
	// Position of FNREADY_MIS field.
	FLASH_CTRL_IRQSTAT_FNREADY_MIS_Pos = 0x5
	// Bit mask of FNREADY_MIS field.
	FLASH_CTRL_IRQSTAT_FNREADY_MIS_Msk = 0x20
	// Bit FNREADY_MIS.
	FLASH_CTRL_IRQSTAT_FNREADY_MIS = 0x20

	// IRQMASK: IRQMASK register
	// Position of CMDDONEM field.
	FLASH_CTRL_IRQMASK_CMDDONEM_Pos = 0x0
	// Bit mask of CMDDONEM field.
	FLASH_CTRL_IRQMASK_CMDDONEM_Msk = 0x1
	// Bit CMDDONEM.
	FLASH_CTRL_IRQMASK_CMDDONEM = 0x1
	// Position of CMDSTARTM field.
	FLASH_CTRL_IRQMASK_CMDSTARTM_Pos = 0x1
	// Bit mask of CMDSTARTM field.
	FLASH_CTRL_IRQMASK_CMDSTARTM_Msk = 0x2
	// Bit CMDSTARTM.
	FLASH_CTRL_IRQMASK_CMDSTARTM = 0x2
	// Position of CMDBUSYERRM field.
	FLASH_CTRL_IRQMASK_CMDBUSYERRM_Pos = 0x2
	// Bit mask of CMDBUSYERRM field.
	FLASH_CTRL_IRQMASK_CMDBUSYERRM_Msk = 0x4
	// Bit CMDBUSYERRM.
	FLASH_CTRL_IRQMASK_CMDBUSYERRM = 0x4
	// Position of ILLCMDM field.
	FLASH_CTRL_IRQMASK_ILLCMDM_Pos = 0x3
	// Bit mask of ILLCMDM field.
	FLASH_CTRL_IRQMASK_ILLCMDM_Msk = 0x8
	// Bit ILLCMDM.
	FLASH_CTRL_IRQMASK_ILLCMDM = 0x8
	// Position of READOKM field.
	FLASH_CTRL_IRQMASK_READOKM_Pos = 0x4
	// Bit mask of READOKM field.
	FLASH_CTRL_IRQMASK_READOKM_Msk = 0x10
	// Bit READOKM.
	FLASH_CTRL_IRQMASK_READOKM = 0x10
	// Position of FNREADYM field.
	FLASH_CTRL_IRQMASK_FNREADYM_Pos = 0x5
	// Bit mask of FNREADYM field.
	FLASH_CTRL_IRQMASK_FNREADYM_Msk = 0x20
	// Bit FNREADYM.
	FLASH_CTRL_IRQMASK_FNREADYM = 0x20

	// IRQRAW: IRQRAW register
	// Position of CMDDONE_RIS field.
	FLASH_CTRL_IRQRAW_CMDDONE_RIS_Pos = 0x0
	// Bit mask of CMDDONE_RIS field.
	FLASH_CTRL_IRQRAW_CMDDONE_RIS_Msk = 0x1
	// Bit CMDDONE_RIS.
	FLASH_CTRL_IRQRAW_CMDDONE_RIS = 0x1
	// Position of CMDSTART_RIS field.
	FLASH_CTRL_IRQRAW_CMDSTART_RIS_Pos = 0x1
	// Bit mask of CMDSTART_RIS field.
	FLASH_CTRL_IRQRAW_CMDSTART_RIS_Msk = 0x2
	// Bit CMDSTART_RIS.
	FLASH_CTRL_IRQRAW_CMDSTART_RIS = 0x2
	// Position of CMDBUSYERR_RIS field.
	FLASH_CTRL_IRQRAW_CMDBUSYERR_RIS_Pos = 0x2
	// Bit mask of CMDBUSYERR_RIS field.
	FLASH_CTRL_IRQRAW_CMDBUSYERR_RIS_Msk = 0x4
	// Bit CMDBUSYERR_RIS.
	FLASH_CTRL_IRQRAW_CMDBUSYERR_RIS = 0x4
	// Position of ILLCMD_RIS field.
	FLASH_CTRL_IRQRAW_ILLCMD_RIS_Pos = 0x3
	// Bit mask of ILLCMD_RIS field.
	FLASH_CTRL_IRQRAW_ILLCMD_RIS_Msk = 0x8
	// Bit ILLCMD_RIS.
	FLASH_CTRL_IRQRAW_ILLCMD_RIS = 0x8
	// Position of READOK_RIS field.
	FLASH_CTRL_IRQRAW_READOK_RIS_Pos = 0x4
	// Bit mask of READOK_RIS field.
	FLASH_CTRL_IRQRAW_READOK_RIS_Msk = 0x10
	// Bit READOK_RIS.
	FLASH_CTRL_IRQRAW_READOK_RIS = 0x10
	// Position of CMDSLEEPERR_RIS field.
	FLASH_CTRL_IRQRAW_CMDSLEEPERR_RIS_Pos = 0x5
	// Bit mask of CMDSLEEPERR_RIS field.
	FLASH_CTRL_IRQRAW_CMDSLEEPERR_RIS_Msk = 0x20
	// Bit CMDSLEEPERR_RIS.
	FLASH_CTRL_IRQRAW_CMDSLEEPERR_RIS = 0x20

	// SIZE: SIZE register
	// Position of FLASH_SIZE field.
	FLASH_CTRL_SIZE_FLASH_SIZE_Pos = 0x0
	// Bit mask of FLASH_SIZE field.
	FLASH_CTRL_SIZE_FLASH_SIZE_Msk = 0x1ffff
	// Position of RAM_SIZE field.
	FLASH_CTRL_SIZE_RAM_SIZE_Pos = 0x11
	// Bit mask of RAM_SIZE field.
	FLASH_CTRL_SIZE_RAM_SIZE_Msk = 0x20000
	// Bit RAM_SIZE.
	FLASH_CTRL_SIZE_RAM_SIZE = 0x20000
	// Position of FLASH_SECURE field.
	FLASH_CTRL_SIZE_FLASH_SECURE_Pos = 0x13
	// Bit mask of FLASH_SECURE field.
	FLASH_CTRL_SIZE_FLASH_SECURE_Msk = 0x80000
	// Bit FLASH_SECURE.
	FLASH_CTRL_SIZE_FLASH_SECURE = 0x80000
	// Position of JTAG_DISABLE field.
	FLASH_CTRL_SIZE_JTAG_DISABLE_Pos = 0x14
	// Bit mask of JTAG_DISABLE field.
	FLASH_CTRL_SIZE_JTAG_DISABLE_Msk = 0x100000
	// Bit JTAG_DISABLE.
	FLASH_CTRL_SIZE_JTAG_DISABLE = 0x100000
	// Position of PACKAGE_SIZE field.
	FLASH_CTRL_SIZE_PACKAGE_SIZE_Pos = 0x15
	// Bit mask of PACKAGE_SIZE field.
	FLASH_CTRL_SIZE_PACKAGE_SIZE_Msk = 0x600000

	// ADDRESS: ADDRESS register
	// Position of YADDR field.
	FLASH_CTRL_ADDRESS_YADDR_Pos = 0x0
	// Bit mask of YADDR field.
	FLASH_CTRL_ADDRESS_YADDR_Msk = 0x3f
	// Position of XADDR field.
	FLASH_CTRL_ADDRESS_XADDR_Pos = 0x6
	// Bit mask of XADDR field.
	FLASH_CTRL_ADDRESS_XADDR_Msk = 0xffc0

	// LFSRVAL: LFSRVAL register
	// Position of LFSRVAL field.
	FLASH_CTRL_LFSRVAL_LFSRVAL_Pos = 0x0
	// Bit mask of LFSRVAL field.
	FLASH_CTRL_LFSRVAL_LFSRVAL_Msk = 0xffffffff

	// PAGEPROT0: PAGEPROT0 register
	// Position of SEGSIZE0 field.
	FLASH_CTRL_PAGEPROT0_SEGSIZE0_Pos = 0x0
	// Bit mask of SEGSIZE0 field.
	FLASH_CTRL_PAGEPROT0_SEGSIZE0_Msk = 0x7f
	// Position of SEGOFFSET0 field.
	FLASH_CTRL_PAGEPROT0_SEGOFFSET0_Pos = 0x8
	// Bit mask of SEGOFFSET0 field.
	FLASH_CTRL_PAGEPROT0_SEGOFFSET0_Msk = 0x7f00
	// Position of SEGSIZE1 field.
	FLASH_CTRL_PAGEPROT0_SEGSIZE1_Pos = 0x10
	// Bit mask of SEGSIZE1 field.
	FLASH_CTRL_PAGEPROT0_SEGSIZE1_Msk = 0x7f0000
	// Position of SEGOFFSET1 field.
	FLASH_CTRL_PAGEPROT0_SEGOFFSET1_Pos = 0x18
	// Bit mask of SEGOFFSET1 field.
	FLASH_CTRL_PAGEPROT0_SEGOFFSET1_Msk = 0x7f000000

	// PAGEPROT1: PAGEPROT1 register
	// Position of SEGSIZE2 field.
	FLASH_CTRL_PAGEPROT1_SEGSIZE2_Pos = 0x0
	// Bit mask of SEGSIZE2 field.
	FLASH_CTRL_PAGEPROT1_SEGSIZE2_Msk = 0x7f
	// Position of SEGOFFSET2 field.
	FLASH_CTRL_PAGEPROT1_SEGOFFSET2_Pos = 0x8
	// Bit mask of SEGOFFSET2 field.
	FLASH_CTRL_PAGEPROT1_SEGOFFSET2_Msk = 0x7f00
	// Position of SEGSIZE3 field.
	FLASH_CTRL_PAGEPROT1_SEGSIZE3_Pos = 0x10
	// Bit mask of SEGSIZE3 field.
	FLASH_CTRL_PAGEPROT1_SEGSIZE3_Msk = 0x7f0000
	// Position of SEGOFFSET3 field.
	FLASH_CTRL_PAGEPROT1_SEGOFFSET3_Pos = 0x18
	// Bit mask of SEGOFFSET3 field.
	FLASH_CTRL_PAGEPROT1_SEGOFFSET3_Msk = 0x7f000000

	// DATA0: DATA0 register
	// Position of DATA0 field.
	FLASH_CTRL_DATA0_DATA0_Pos = 0x0
	// Bit mask of DATA0 field.
	FLASH_CTRL_DATA0_DATA0_Msk = 0xffffffff

	// DATA1: DATA1 register
	// Position of DATA1 field.
	FLASH_CTRL_DATA1_DATA1_Pos = 0x0
	// Bit mask of DATA1 field.
	FLASH_CTRL_DATA1_DATA1_Msk = 0xffffffff

	// DATA2: DATA2 register
	// Position of DATA2 field.
	FLASH_CTRL_DATA2_DATA2_Pos = 0x0
	// Bit mask of DATA2 field.
	FLASH_CTRL_DATA2_DATA2_Msk = 0xffffffff

	// DATA3: DATA3 register
	// Position of DATA3 field.
	FLASH_CTRL_DATA3_DATA3_Pos = 0x0
	// Bit mask of DATA3 field.
	FLASH_CTRL_DATA3_DATA3_Msk = 0xffffffff
)

// Constants for PKA
const (
	// CR: PKA_CR register
	// Position of EN field.
	PKA_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	PKA_CR_EN_Msk = 0x1
	// Bit EN.
	PKA_CR_EN = 0x1
	// Position of START field.
	PKA_CR_START_Pos = 0x1
	// Bit mask of START field.
	PKA_CR_START_Msk = 0x2
	// Bit START.
	PKA_CR_START = 0x2
	// Position of SECLVL field.
	PKA_CR_SECLVL_Pos = 0x2
	// Bit mask of SECLVL field.
	PKA_CR_SECLVL_Msk = 0x4
	// Bit SECLVL.
	PKA_CR_SECLVL = 0x4
	// Position of MODE field.
	PKA_CR_MODE_Pos = 0x8
	// Bit mask of MODE field.
	PKA_CR_MODE_Msk = 0x3f00
	// Position of PROCENDIE field.
	PKA_CR_PROCENDIE_Pos = 0x11
	// Bit mask of PROCENDIE field.
	PKA_CR_PROCENDIE_Msk = 0x20000
	// Bit PROCENDIE.
	PKA_CR_PROCENDIE = 0x20000
	// Position of RAMERRIE field.
	PKA_CR_RAMERRIE_Pos = 0x13
	// Bit mask of RAMERRIE field.
	PKA_CR_RAMERRIE_Msk = 0x80000
	// Bit RAMERRIE.
	PKA_CR_RAMERRIE = 0x80000
	// Position of ADDRERRIE field.
	PKA_CR_ADDRERRIE_Pos = 0x14
	// Bit mask of ADDRERRIE field.
	PKA_CR_ADDRERRIE_Msk = 0x100000
	// Bit ADDRERRIE.
	PKA_CR_ADDRERRIE = 0x100000

	// SR: PKA_SR register
	// Position of BUSY field.
	PKA_SR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	PKA_SR_BUSY_Msk = 0x10000
	// Bit BUSY.
	PKA_SR_BUSY = 0x10000
	// Position of PROCENDF field.
	PKA_SR_PROCENDF_Pos = 0x11
	// Bit mask of PROCENDF field.
	PKA_SR_PROCENDF_Msk = 0x20000
	// Bit PROCENDF.
	PKA_SR_PROCENDF = 0x20000
	// Position of RAMERRF field.
	PKA_SR_RAMERRF_Pos = 0x13
	// Bit mask of RAMERRF field.
	PKA_SR_RAMERRF_Msk = 0x80000
	// Bit RAMERRF.
	PKA_SR_RAMERRF = 0x80000
	// Position of ADDRERRF field.
	PKA_SR_ADDRERRF_Pos = 0x14
	// Bit mask of ADDRERRF field.
	PKA_SR_ADDRERRF_Msk = 0x100000
	// Bit ADDRERRF.
	PKA_SR_ADDRERRF = 0x100000

	// CLRFR: PKA_CLRFR register
	// Position of PROCENDFC field.
	PKA_CLRFR_PROCENDFC_Pos = 0x11
	// Bit mask of PROCENDFC field.
	PKA_CLRFR_PROCENDFC_Msk = 0x20000
	// Bit PROCENDFC.
	PKA_CLRFR_PROCENDFC = 0x20000
	// Position of RAMERRFC field.
	PKA_CLRFR_RAMERRFC_Pos = 0x13
	// Bit mask of RAMERRFC field.
	PKA_CLRFR_RAMERRFC_Msk = 0x80000
	// Bit RAMERRFC.
	PKA_CLRFR_RAMERRFC = 0x80000
	// Position of ADDRERRFC field.
	PKA_CLRFR_ADDRERRFC_Pos = 0x14
	// Bit mask of ADDRERRFC field.
	PKA_CLRFR_ADDRERRFC_Msk = 0x100000
	// Bit ADDRERRFC.
	PKA_CLRFR_ADDRERRFC = 0x100000
)

// Constants for PWRC
const (
	// CR1: CR1 register
	// Position of LPMS field.
	PWRC_CR1_LPMS_Pos = 0x0
	// Bit mask of LPMS field.
	PWRC_CR1_LPMS_Msk = 0x1
	// Bit LPMS.
	PWRC_CR1_LPMS = 0x1
	// Position of ENSDNBOR field.
	PWRC_CR1_ENSDNBOR_Pos = 0x1
	// Bit mask of ENSDNBOR field.
	PWRC_CR1_ENSDNBOR_Msk = 0x2
	// Bit ENSDNBOR.
	PWRC_CR1_ENSDNBOR = 0x2
	// Position of IBIAS_RUN_AUTO field.
	PWRC_CR1_IBIAS_RUN_AUTO_Pos = 0x2
	// Bit mask of IBIAS_RUN_AUTO field.
	PWRC_CR1_IBIAS_RUN_AUTO_Msk = 0x4
	// Bit IBIAS_RUN_AUTO.
	PWRC_CR1_IBIAS_RUN_AUTO = 0x4
	// Position of IBIAS_RUN_STATE field.
	PWRC_CR1_IBIAS_RUN_STATE_Pos = 0x3
	// Bit mask of IBIAS_RUN_STATE field.
	PWRC_CR1_IBIAS_RUN_STATE_Msk = 0x8
	// Bit IBIAS_RUN_STATE.
	PWRC_CR1_IBIAS_RUN_STATE = 0x8
	// Position of APC field.
	PWRC_CR1_APC_Pos = 0x4
	// Bit mask of APC field.
	PWRC_CR1_APC_Msk = 0x10
	// Bit APC.
	PWRC_CR1_APC = 0x10
	// Position of ENBORH field.
	PWRC_CR1_ENBORH_Pos = 0x5
	// Bit mask of ENBORH field.
	PWRC_CR1_ENBORH_Msk = 0x20
	// Bit ENBORH.
	PWRC_CR1_ENBORH = 0x20
	// Position of SELBORH field.
	PWRC_CR1_SELBORH_Pos = 0x6
	// Bit mask of SELBORH field.
	PWRC_CR1_SELBORH_Msk = 0xc0
	// Position of ENBORL field.
	PWRC_CR1_ENBORL_Pos = 0x8
	// Bit mask of ENBORL field.
	PWRC_CR1_ENBORL_Msk = 0x100
	// Bit ENBORL.
	PWRC_CR1_ENBORL = 0x100

	// CR2: CR2 register
	// Position of PVDE field.
	PWRC_CR2_PVDE_Pos = 0x0
	// Bit mask of PVDE field.
	PWRC_CR2_PVDE_Msk = 0x1
	// Bit PVDE.
	PWRC_CR2_PVDE = 0x1
	// Position of PVDLS field.
	PWRC_CR2_PVDLS_Pos = 0x1
	// Bit mask of PVDLS field.
	PWRC_CR2_PVDLS_Msk = 0xe
	// Position of DBGRET field.
	PWRC_CR2_DBGRET_Pos = 0x4
	// Bit mask of DBGRET field.
	PWRC_CR2_DBGRET_Msk = 0x10
	// Bit DBGRET.
	PWRC_CR2_DBGRET = 0x10
	// Position of RAMRET1 field.
	PWRC_CR2_RAMRET1_Pos = 0x5
	// Bit mask of RAMRET1 field.
	PWRC_CR2_RAMRET1_Msk = 0x20
	// Bit RAMRET1.
	PWRC_CR2_RAMRET1 = 0x20
	// Position of GPIORET field.
	PWRC_CR2_GPIORET_Pos = 0x8
	// Bit mask of GPIORET field.
	PWRC_CR2_GPIORET_Msk = 0x100
	// Bit GPIORET.
	PWRC_CR2_GPIORET = 0x100
	// Position of ENTS field.
	PWRC_CR2_ENTS_Pos = 0x9
	// Bit mask of ENTS field.
	PWRC_CR2_ENTS_Msk = 0x200
	// Bit ENTS.
	PWRC_CR2_ENTS = 0x200

	// CR3: CR3 register
	// Position of EWU0 field.
	PWRC_CR3_EWU0_Pos = 0x0
	// Bit mask of EWU0 field.
	PWRC_CR3_EWU0_Msk = 0x1
	// Bit EWU0.
	PWRC_CR3_EWU0 = 0x1
	// Position of EWU1 field.
	PWRC_CR3_EWU1_Pos = 0x1
	// Bit mask of EWU1 field.
	PWRC_CR3_EWU1_Msk = 0x2
	// Bit EWU1.
	PWRC_CR3_EWU1 = 0x2
	// Position of EWU2 field.
	PWRC_CR3_EWU2_Pos = 0x2
	// Bit mask of EWU2 field.
	PWRC_CR3_EWU2_Msk = 0x4
	// Bit EWU2.
	PWRC_CR3_EWU2 = 0x4
	// Position of EWU3 field.
	PWRC_CR3_EWU3_Pos = 0x3
	// Bit mask of EWU3 field.
	PWRC_CR3_EWU3_Msk = 0x8
	// Bit EWU3.
	PWRC_CR3_EWU3 = 0x8
	// Position of EWU4 field.
	PWRC_CR3_EWU4_Pos = 0x4
	// Bit mask of EWU4 field.
	PWRC_CR3_EWU4_Msk = 0x10
	// Bit EWU4.
	PWRC_CR3_EWU4 = 0x10
	// Position of EWU5 field.
	PWRC_CR3_EWU5_Pos = 0x5
	// Bit mask of EWU5 field.
	PWRC_CR3_EWU5_Msk = 0x20
	// Bit EWU5.
	PWRC_CR3_EWU5 = 0x20
	// Position of EWU6 field.
	PWRC_CR3_EWU6_Pos = 0x6
	// Bit mask of EWU6 field.
	PWRC_CR3_EWU6_Msk = 0x40
	// Bit EWU6.
	PWRC_CR3_EWU6 = 0x40
	// Position of EWU7 field.
	PWRC_CR3_EWU7_Pos = 0x7
	// Bit mask of EWU7 field.
	PWRC_CR3_EWU7_Msk = 0x80
	// Bit EWU7.
	PWRC_CR3_EWU7 = 0x80
	// Position of EWU8 field.
	PWRC_CR3_EWU8_Pos = 0x8
	// Bit mask of EWU8 field.
	PWRC_CR3_EWU8_Msk = 0x100
	// Bit EWU8.
	PWRC_CR3_EWU8 = 0x100
	// Position of EWU9 field.
	PWRC_CR3_EWU9_Pos = 0x9
	// Bit mask of EWU9 field.
	PWRC_CR3_EWU9_Msk = 0x200
	// Bit EWU9.
	PWRC_CR3_EWU9 = 0x200
	// Position of EWU10 field.
	PWRC_CR3_EWU10_Pos = 0xa
	// Bit mask of EWU10 field.
	PWRC_CR3_EWU10_Msk = 0x400
	// Bit EWU10.
	PWRC_CR3_EWU10 = 0x400
	// Position of EWU11 field.
	PWRC_CR3_EWU11_Pos = 0xb
	// Bit mask of EWU11 field.
	PWRC_CR3_EWU11_Msk = 0x800
	// Bit EWU11.
	PWRC_CR3_EWU11 = 0x800
	// Position of EWBLE field.
	PWRC_CR3_EWBLE_Pos = 0xc
	// Bit mask of EWBLE field.
	PWRC_CR3_EWBLE_Msk = 0x1000
	// Bit EWBLE.
	PWRC_CR3_EWBLE = 0x1000
	// Position of EWBLEHCPU field.
	PWRC_CR3_EWBLEHCPU_Pos = 0xd
	// Bit mask of EWBLEHCPU field.
	PWRC_CR3_EWBLEHCPU_Msk = 0x2000
	// Bit EWBLEHCPU.
	PWRC_CR3_EWBLEHCPU = 0x2000
	// Position of EIWL2 field.
	PWRC_CR3_EIWL2_Pos = 0xe
	// Bit mask of EIWL2 field.
	PWRC_CR3_EIWL2_Msk = 0x4000
	// Bit EIWL2.
	PWRC_CR3_EIWL2 = 0x4000
	// Position of EIWL field.
	PWRC_CR3_EIWL_Pos = 0xf
	// Bit mask of EIWL field.
	PWRC_CR3_EIWL_Msk = 0x8000
	// Bit EIWL.
	PWRC_CR3_EIWL = 0x8000

	// CR4: CR4 register
	// Position of WUP0 field.
	PWRC_CR4_WUP0_Pos = 0x0
	// Bit mask of WUP0 field.
	PWRC_CR4_WUP0_Msk = 0x1
	// Bit WUP0.
	PWRC_CR4_WUP0 = 0x1
	// Position of WUP1 field.
	PWRC_CR4_WUP1_Pos = 0x1
	// Bit mask of WUP1 field.
	PWRC_CR4_WUP1_Msk = 0x2
	// Bit WUP1.
	PWRC_CR4_WUP1 = 0x2
	// Position of WUP2 field.
	PWRC_CR4_WUP2_Pos = 0x2
	// Bit mask of WUP2 field.
	PWRC_CR4_WUP2_Msk = 0x4
	// Bit WUP2.
	PWRC_CR4_WUP2 = 0x4
	// Position of WUP3 field.
	PWRC_CR4_WUP3_Pos = 0x3
	// Bit mask of WUP3 field.
	PWRC_CR4_WUP3_Msk = 0x8
	// Bit WUP3.
	PWRC_CR4_WUP3 = 0x8
	// Position of WUP4 field.
	PWRC_CR4_WUP4_Pos = 0x4
	// Bit mask of WUP4 field.
	PWRC_CR4_WUP4_Msk = 0x10
	// Bit WUP4.
	PWRC_CR4_WUP4 = 0x10
	// Position of WUP5 field.
	PWRC_CR4_WUP5_Pos = 0x5
	// Bit mask of WUP5 field.
	PWRC_CR4_WUP5_Msk = 0x20
	// Bit WUP5.
	PWRC_CR4_WUP5 = 0x20
	// Position of WUP6 field.
	PWRC_CR4_WUP6_Pos = 0x6
	// Bit mask of WUP6 field.
	PWRC_CR4_WUP6_Msk = 0x40
	// Bit WUP6.
	PWRC_CR4_WUP6 = 0x40
	// Position of WUP7 field.
	PWRC_CR4_WUP7_Pos = 0x7
	// Bit mask of WUP7 field.
	PWRC_CR4_WUP7_Msk = 0x80
	// Bit WUP7.
	PWRC_CR4_WUP7 = 0x80
	// Position of WUP8 field.
	PWRC_CR4_WUP8_Pos = 0x8
	// Bit mask of WUP8 field.
	PWRC_CR4_WUP8_Msk = 0x100
	// Bit WUP8.
	PWRC_CR4_WUP8 = 0x100
	// Position of WUP9 field.
	PWRC_CR4_WUP9_Pos = 0x9
	// Bit mask of WUP9 field.
	PWRC_CR4_WUP9_Msk = 0x200
	// Bit WUP9.
	PWRC_CR4_WUP9 = 0x200
	// Position of WUP10 field.
	PWRC_CR4_WUP10_Pos = 0xa
	// Bit mask of WUP10 field.
	PWRC_CR4_WUP10_Msk = 0x400
	// Bit WUP10.
	PWRC_CR4_WUP10 = 0x400
	// Position of WUP11 field.
	PWRC_CR4_WUP11_Pos = 0xb
	// Bit mask of WUP11 field.
	PWRC_CR4_WUP11_Msk = 0x800
	// Bit WUP11.
	PWRC_CR4_WUP11 = 0x800

	// SR1: SR1 register
	// Position of WUF0 field.
	PWRC_SR1_WUF0_Pos = 0x0
	// Bit mask of WUF0 field.
	PWRC_SR1_WUF0_Msk = 0x1
	// Bit WUF0.
	PWRC_SR1_WUF0 = 0x1
	// Position of WUF1 field.
	PWRC_SR1_WUF1_Pos = 0x1
	// Bit mask of WUF1 field.
	PWRC_SR1_WUF1_Msk = 0x2
	// Bit WUF1.
	PWRC_SR1_WUF1 = 0x2
	// Position of WUF2 field.
	PWRC_SR1_WUF2_Pos = 0x2
	// Bit mask of WUF2 field.
	PWRC_SR1_WUF2_Msk = 0x4
	// Bit WUF2.
	PWRC_SR1_WUF2 = 0x4
	// Position of WUF3 field.
	PWRC_SR1_WUF3_Pos = 0x3
	// Bit mask of WUF3 field.
	PWRC_SR1_WUF3_Msk = 0x8
	// Bit WUF3.
	PWRC_SR1_WUF3 = 0x8
	// Position of WUF4 field.
	PWRC_SR1_WUF4_Pos = 0x4
	// Bit mask of WUF4 field.
	PWRC_SR1_WUF4_Msk = 0x10
	// Bit WUF4.
	PWRC_SR1_WUF4 = 0x10
	// Position of WUF5 field.
	PWRC_SR1_WUF5_Pos = 0x5
	// Bit mask of WUF5 field.
	PWRC_SR1_WUF5_Msk = 0x20
	// Bit WUF5.
	PWRC_SR1_WUF5 = 0x20
	// Position of WUF6 field.
	PWRC_SR1_WUF6_Pos = 0x6
	// Bit mask of WUF6 field.
	PWRC_SR1_WUF6_Msk = 0x40
	// Bit WUF6.
	PWRC_SR1_WUF6 = 0x40
	// Position of WUF7 field.
	PWRC_SR1_WUF7_Pos = 0x7
	// Bit mask of WUF7 field.
	PWRC_SR1_WUF7_Msk = 0x80
	// Bit WUF7.
	PWRC_SR1_WUF7 = 0x80
	// Position of WUF8 field.
	PWRC_SR1_WUF8_Pos = 0x8
	// Bit mask of WUF8 field.
	PWRC_SR1_WUF8_Msk = 0x100
	// Bit WUF8.
	PWRC_SR1_WUF8 = 0x100
	// Position of WUF9 field.
	PWRC_SR1_WUF9_Pos = 0x9
	// Bit mask of WUF9 field.
	PWRC_SR1_WUF9_Msk = 0x200
	// Bit WUF9.
	PWRC_SR1_WUF9 = 0x200
	// Position of WUF10 field.
	PWRC_SR1_WUF10_Pos = 0xa
	// Bit mask of WUF10 field.
	PWRC_SR1_WUF10_Msk = 0x400
	// Bit WUF10.
	PWRC_SR1_WUF10 = 0x400
	// Position of WUF11 field.
	PWRC_SR1_WUF11_Pos = 0xb
	// Bit mask of WUF11 field.
	PWRC_SR1_WUF11_Msk = 0x800
	// Bit WUF11.
	PWRC_SR1_WUF11 = 0x800
	// Position of WBLEF field.
	PWRC_SR1_WBLEF_Pos = 0xc
	// Bit mask of WBLEF field.
	PWRC_SR1_WBLEF_Msk = 0x1000
	// Bit WBLEF.
	PWRC_SR1_WBLEF = 0x1000
	// Position of WBLEHCPUF field.
	PWRC_SR1_WBLEHCPUF_Pos = 0xd
	// Bit mask of WBLEHCPUF field.
	PWRC_SR1_WBLEHCPUF_Msk = 0x2000
	// Bit WBLEHCPUF.
	PWRC_SR1_WBLEHCPUF = 0x2000
	// Position of IWUF2 field.
	PWRC_SR1_IWUF2_Pos = 0xe
	// Bit mask of IWUF2 field.
	PWRC_SR1_IWUF2_Msk = 0x4000
	// Bit IWUF2.
	PWRC_SR1_IWUF2 = 0x4000
	// Position of IWUF field.
	PWRC_SR1_IWUF_Pos = 0xf
	// Bit mask of IWUF field.
	PWRC_SR1_IWUF_Msk = 0x8000
	// Bit IWUF.
	PWRC_SR1_IWUF = 0x8000

	// SR2: SR2 register
	// Position of SMPSBYPR field.
	PWRC_SR2_SMPSBYPR_Pos = 0x0
	// Bit mask of SMPSBYPR field.
	PWRC_SR2_SMPSBYPR_Msk = 0x1
	// Bit SMPSBYPR.
	PWRC_SR2_SMPSBYPR = 0x1
	// Position of SMPSENR field.
	PWRC_SR2_SMPSENR_Pos = 0x1
	// Bit mask of SMPSENR field.
	PWRC_SR2_SMPSENR_Msk = 0x2
	// Bit SMPSENR.
	PWRC_SR2_SMPSENR = 0x2
	// Position of SMPSRDY field.
	PWRC_SR2_SMPSRDY_Pos = 0x2
	// Bit mask of SMPSRDY field.
	PWRC_SR2_SMPSRDY_Msk = 0x4
	// Bit SMPSRDY.
	PWRC_SR2_SMPSRDY = 0x4
	// Position of IOBOOTVAL2 field.
	PWRC_SR2_IOBOOTVAL2_Pos = 0x4
	// Bit mask of IOBOOTVAL2 field.
	PWRC_SR2_IOBOOTVAL2_Msk = 0xf0
	// Position of REGLPS field.
	PWRC_SR2_REGLPS_Pos = 0x8
	// Bit mask of REGLPS field.
	PWRC_SR2_REGLPS_Msk = 0x100
	// Bit REGLPS.
	PWRC_SR2_REGLPS = 0x100
	// Position of REGMS field.
	PWRC_SR2_REGMS_Pos = 0x9
	// Bit mask of REGMS field.
	PWRC_SR2_REGMS_Msk = 0x200
	// Bit REGMS.
	PWRC_SR2_REGMS = 0x200
	// Position of PVDO field.
	PWRC_SR2_PVDO_Pos = 0xb
	// Bit mask of PVDO field.
	PWRC_SR2_PVDO_Msk = 0x800
	// Bit PVDO.
	PWRC_SR2_PVDO = 0x800
	// Position of IOBOOTVAL field.
	PWRC_SR2_IOBOOTVAL_Pos = 0xc
	// Bit mask of IOBOOTVAL field.
	PWRC_SR2_IOBOOTVAL_Msk = 0xf000

	// CR5: CR5 register
	// Position of SMPSLVL field.
	PWRC_CR5_SMPSLVL_Pos = 0x0
	// Bit mask of SMPSLVL field.
	PWRC_CR5_SMPSLVL_Msk = 0xf
	// Position of SMPSBOMSEL field.
	PWRC_CR5_SMPSBOMSEL_Pos = 0x4
	// Bit mask of SMPSBOMSEL field.
	PWRC_CR5_SMPSBOMSEL_Msk = 0x30
	// Position of SMPSFRDY field.
	PWRC_CR5_SMPSFRDY_Pos = 0x7
	// Bit mask of SMPSFRDY field.
	PWRC_CR5_SMPSFRDY_Msk = 0x80
	// Bit SMPSFRDY.
	PWRC_CR5_SMPSFRDY = 0x80
	// Position of SMPSLPOPEN field.
	PWRC_CR5_SMPSLPOPEN_Pos = 0x8
	// Bit mask of SMPSLPOPEN field.
	PWRC_CR5_SMPSLPOPEN_Msk = 0x100
	// Bit SMPSLPOPEN.
	PWRC_CR5_SMPSLPOPEN = 0x100
	// Position of SMPSFBYP field.
	PWRC_CR5_SMPSFBYP_Pos = 0x9
	// Bit mask of SMPSFBYP field.
	PWRC_CR5_SMPSFBYP_Msk = 0x200
	// Bit SMPSFBYP.
	PWRC_CR5_SMPSFBYP = 0x200
	// Position of NOSMPS field.
	PWRC_CR5_NOSMPS_Pos = 0xa
	// Bit mask of NOSMPS field.
	PWRC_CR5_NOSMPS_Msk = 0x400
	// Bit NOSMPS.
	PWRC_CR5_NOSMPS = 0x400
	// Position of SMPS_ENA_DCM field.
	PWRC_CR5_SMPS_ENA_DCM_Pos = 0xb
	// Bit mask of SMPS_ENA_DCM field.
	PWRC_CR5_SMPS_ENA_DCM_Msk = 0x800
	// Bit SMPS_ENA_DCM.
	PWRC_CR5_SMPS_ENA_DCM = 0x800
	// Position of CLKDETR_DISABLE field.
	PWRC_CR5_CLKDETR_DISABLE_Pos = 0xc
	// Bit mask of CLKDETR_DISABLE field.
	PWRC_CR5_CLKDETR_DISABLE_Msk = 0x1000
	// Bit CLKDETR_DISABLE.
	PWRC_CR5_CLKDETR_DISABLE = 0x1000
	// Position of SMPS_PRECH_CUR_SEL field.
	PWRC_CR5_SMPS_PRECH_CUR_SEL_Pos = 0xd
	// Bit mask of SMPS_PRECH_CUR_SEL field.
	PWRC_CR5_SMPS_PRECH_CUR_SEL_Msk = 0x6000

	// PUCRA: PUCRA register
	// Position of PU field.
	PWRC_PUCRA_PU_Pos = 0x0
	// Bit mask of PU field.
	PWRC_PUCRA_PU_Msk = 0xffff

	// PDCRA: PDCRA register
	// Position of PD field.
	PWRC_PDCRA_PD_Pos = 0x0
	// Bit mask of PD field.
	PWRC_PDCRA_PD_Msk = 0xffff

	// PUCRB: PUCRB register
	// Position of PU field.
	PWRC_PUCRB_PU_Pos = 0x0
	// Bit mask of PU field.
	PWRC_PUCRB_PU_Msk = 0xffff

	// PDCRB: PDCRB register
	// Position of PD field.
	PWRC_PDCRB_PD_Pos = 0x0
	// Bit mask of PD field.
	PWRC_PDCRB_PD_Msk = 0xffff

	// CR6: CR6 register
	// Position of EWU12 field.
	PWRC_CR6_EWU12_Pos = 0x0
	// Bit mask of EWU12 field.
	PWRC_CR6_EWU12_Msk = 0x1
	// Bit EWU12.
	PWRC_CR6_EWU12 = 0x1
	// Position of EWU13 field.
	PWRC_CR6_EWU13_Pos = 0x1
	// Bit mask of EWU13 field.
	PWRC_CR6_EWU13_Msk = 0x2
	// Bit EWU13.
	PWRC_CR6_EWU13 = 0x2
	// Position of EWU14 field.
	PWRC_CR6_EWU14_Pos = 0x2
	// Bit mask of EWU14 field.
	PWRC_CR6_EWU14_Msk = 0x4
	// Bit EWU14.
	PWRC_CR6_EWU14 = 0x4
	// Position of EWU15 field.
	PWRC_CR6_EWU15_Pos = 0x3
	// Bit mask of EWU15 field.
	PWRC_CR6_EWU15_Msk = 0x8
	// Bit EWU15.
	PWRC_CR6_EWU15 = 0x8
	// Position of EWU16 field.
	PWRC_CR6_EWU16_Pos = 0x4
	// Bit mask of EWU16 field.
	PWRC_CR6_EWU16_Msk = 0x10
	// Bit EWU16.
	PWRC_CR6_EWU16 = 0x10
	// Position of EWU17 field.
	PWRC_CR6_EWU17_Pos = 0x5
	// Bit mask of EWU17 field.
	PWRC_CR6_EWU17_Msk = 0x20
	// Bit EWU17.
	PWRC_CR6_EWU17 = 0x20
	// Position of EWU18 field.
	PWRC_CR6_EWU18_Pos = 0x6
	// Bit mask of EWU18 field.
	PWRC_CR6_EWU18_Msk = 0x40
	// Bit EWU18.
	PWRC_CR6_EWU18 = 0x40
	// Position of EWU19 field.
	PWRC_CR6_EWU19_Pos = 0x7
	// Bit mask of EWU19 field.
	PWRC_CR6_EWU19_Msk = 0x80
	// Bit EWU19.
	PWRC_CR6_EWU19 = 0x80

	// CR7: CR7 register
	// Position of WUP12 field.
	PWRC_CR7_WUP12_Pos = 0x0
	// Bit mask of WUP12 field.
	PWRC_CR7_WUP12_Msk = 0x1
	// Bit WUP12.
	PWRC_CR7_WUP12 = 0x1
	// Position of WUP13 field.
	PWRC_CR7_WUP13_Pos = 0x1
	// Bit mask of WUP13 field.
	PWRC_CR7_WUP13_Msk = 0x2
	// Bit WUP13.
	PWRC_CR7_WUP13 = 0x2
	// Position of WUP14 field.
	PWRC_CR7_WUP14_Pos = 0x2
	// Bit mask of WUP14 field.
	PWRC_CR7_WUP14_Msk = 0x4
	// Bit WUP14.
	PWRC_CR7_WUP14 = 0x4
	// Position of WUP15 field.
	PWRC_CR7_WUP15_Pos = 0x3
	// Bit mask of WUP15 field.
	PWRC_CR7_WUP15_Msk = 0x8
	// Bit WUP15.
	PWRC_CR7_WUP15 = 0x8
	// Position of WUP16 field.
	PWRC_CR7_WUP16_Pos = 0x4
	// Bit mask of WUP16 field.
	PWRC_CR7_WUP16_Msk = 0x10
	// Bit WUP16.
	PWRC_CR7_WUP16 = 0x10
	// Position of WUP17 field.
	PWRC_CR7_WUP17_Pos = 0x5
	// Bit mask of WUP17 field.
	PWRC_CR7_WUP17_Msk = 0x20
	// Bit WUP17.
	PWRC_CR7_WUP17 = 0x20
	// Position of WUP18 field.
	PWRC_CR7_WUP18_Pos = 0x6
	// Bit mask of WUP18 field.
	PWRC_CR7_WUP18_Msk = 0x40
	// Bit WUP18.
	PWRC_CR7_WUP18 = 0x40
	// Position of WUP19 field.
	PWRC_CR7_WUP19_Pos = 0x7
	// Bit mask of WUP19 field.
	PWRC_CR7_WUP19_Msk = 0x80
	// Bit WUP19.
	PWRC_CR7_WUP19 = 0x80

	// SR3: SR3 register
	// Position of WUF12 field.
	PWRC_SR3_WUF12_Pos = 0x0
	// Bit mask of WUF12 field.
	PWRC_SR3_WUF12_Msk = 0x1
	// Bit WUF12.
	PWRC_SR3_WUF12 = 0x1
	// Position of WUF13 field.
	PWRC_SR3_WUF13_Pos = 0x1
	// Bit mask of WUF13 field.
	PWRC_SR3_WUF13_Msk = 0x2
	// Bit WUF13.
	PWRC_SR3_WUF13 = 0x2
	// Position of WUF14 field.
	PWRC_SR3_WUF14_Pos = 0x2
	// Bit mask of WUF14 field.
	PWRC_SR3_WUF14_Msk = 0x4
	// Bit WUF14.
	PWRC_SR3_WUF14 = 0x4
	// Position of WUF15 field.
	PWRC_SR3_WUF15_Pos = 0x3
	// Bit mask of WUF15 field.
	PWRC_SR3_WUF15_Msk = 0x8
	// Bit WUF15.
	PWRC_SR3_WUF15 = 0x8
	// Position of WUF16 field.
	PWRC_SR3_WUF16_Pos = 0x4
	// Bit mask of WUF16 field.
	PWRC_SR3_WUF16_Msk = 0x10
	// Bit WUF16.
	PWRC_SR3_WUF16 = 0x10
	// Position of WUF17 field.
	PWRC_SR3_WUF17_Pos = 0x5
	// Bit mask of WUF17 field.
	PWRC_SR3_WUF17_Msk = 0x20
	// Bit WUF17.
	PWRC_SR3_WUF17 = 0x20
	// Position of WUF18 field.
	PWRC_SR3_WUF18_Pos = 0x6
	// Bit mask of WUF18 field.
	PWRC_SR3_WUF18_Msk = 0x40
	// Bit WUF18.
	PWRC_SR3_WUF18 = 0x40
	// Position of WUF19 field.
	PWRC_SR3_WUF19_Pos = 0x7
	// Bit mask of WUF19 field.
	PWRC_SR3_WUF19_Msk = 0x80
	// Bit WUF19.
	PWRC_SR3_WUF19 = 0x80

	// DBGR: DBGR register
	// Position of DEEPSTOP2 field.
	PWRC_DBGR_DEEPSTOP2_Pos = 0x0
	// Bit mask of DEEPSTOP2 field.
	PWRC_DBGR_DEEPSTOP2_Msk = 0x1
	// Bit DEEPSTOP2.
	PWRC_DBGR_DEEPSTOP2 = 0x1
	// Position of DIS_PRECH field.
	PWRC_DBGR_DIS_PRECH_Pos = 0xd
	// Bit mask of DIS_PRECH field.
	PWRC_DBGR_DIS_PRECH_Msk = 0xe000

	// EXTSRR: EXTSRR register
	// Position of DEEPSTOPF field.
	PWRC_EXTSRR_DEEPSTOPF_Pos = 0x9
	// Bit mask of DEEPSTOPF field.
	PWRC_EXTSRR_DEEPSTOPF_Msk = 0x200
	// Bit DEEPSTOPF.
	PWRC_EXTSRR_DEEPSTOPF = 0x200
	// Position of RFPHASEF field.
	PWRC_EXTSRR_RFPHASEF_Pos = 0xa
	// Bit mask of RFPHASEF field.
	PWRC_EXTSRR_RFPHASEF_Msk = 0x400
	// Bit RFPHASEF.
	PWRC_EXTSRR_RFPHASEF = 0x400
)

// Constants for RNG
const (
	// CR: RNG_CR register
	// Position of RNG_DIS field.
	RNG_CR_RNG_DIS_Pos = 0x2
	// Bit mask of RNG_DIS field.
	RNG_CR_RNG_DIS_Msk = 0x4
	// Bit RNG_DIS.
	RNG_CR_RNG_DIS = 0x4
	// Position of TST_CLK field.
	RNG_CR_TST_CLK_Pos = 0x3
	// Bit mask of TST_CLK field.
	RNG_CR_TST_CLK_Msk = 0x8
	// Bit TST_CLK.
	RNG_CR_TST_CLK = 0x8

	// SR: RNG_SR register
	// Position of RNGRDY field.
	RNG_SR_RNGRDY_Pos = 0x0
	// Bit mask of RNGRDY field.
	RNG_SR_RNGRDY_Msk = 0x1
	// Bit RNGRDY.
	RNG_SR_RNGRDY = 0x1
	// Position of REVCLK field.
	RNG_SR_REVCLK_Pos = 0x1
	// Bit mask of REVCLK field.
	RNG_SR_REVCLK_Msk = 0x2
	// Bit REVCLK.
	RNG_SR_REVCLK = 0x2
	// Position of FAULT field.
	RNG_SR_FAULT_Pos = 0x2
	// Bit mask of FAULT field.
	RNG_SR_FAULT_Msk = 0x4
	// Bit FAULT.
	RNG_SR_FAULT = 0x4

	// VAL: RNG_VAL register
	// Position of RANDOM_VALUE field.
	RNG_VAL_RANDOM_VALUE_Pos = 0x0
	// Bit mask of RANDOM_VALUE field.
	RNG_VAL_RANDOM_VALUE_Msk = 0xffff
)

// Constants for RTC
const (
	// TR: RTC_TR register
	// Position of SU field.
	RTC_TR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_TR_SU_Msk = 0xf
	// Position of ST field.
	RTC_TR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_TR_ST_Msk = 0x70
	// Position of MNU field.
	RTC_TR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_TR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_TR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_TR_MNT_Msk = 0x7000
	// Position of HU field.
	RTC_TR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_TR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_TR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_TR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_TR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_TR_PM_Msk = 0x400000
	// Bit PM.
	RTC_TR_PM = 0x400000

	// DR: RTC_DR register
	// Position of DU field.
	RTC_DR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_DR_DU_Msk = 0xf
	// Position of DT field.
	RTC_DR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_DR_DT_Msk = 0x30
	// Position of MU field.
	RTC_DR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_DR_MU_Msk = 0xf00
	// Position of MT field.
	RTC_DR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_DR_MT_Msk = 0x1000
	// Bit MT.
	RTC_DR_MT = 0x1000
	// Position of WDU field.
	RTC_DR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_DR_WDU_Msk = 0xe000
	// Position of YU field.
	RTC_DR_YU_Pos = 0x10
	// Bit mask of YU field.
	RTC_DR_YU_Msk = 0xf0000
	// Position of YT field.
	RTC_DR_YT_Pos = 0x14
	// Bit mask of YT field.
	RTC_DR_YT_Msk = 0xf00000

	// CR: RTC_CR register
	// Position of WUCKSEL field.
	RTC_CR_WUCKSEL_Pos = 0x0
	// Bit mask of WUCKSEL field.
	RTC_CR_WUCKSEL_Msk = 0x7
	// Position of BYPSHAD field.
	RTC_CR_BYPSHAD_Pos = 0x5
	// Bit mask of BYPSHAD field.
	RTC_CR_BYPSHAD_Msk = 0x20
	// Bit BYPSHAD.
	RTC_CR_BYPSHAD = 0x20
	// Position of FMT field.
	RTC_CR_FMT_Pos = 0x6
	// Bit mask of FMT field.
	RTC_CR_FMT_Msk = 0x40
	// Bit FMT.
	RTC_CR_FMT = 0x40
	// Position of ALRAE field.
	RTC_CR_ALRAE_Pos = 0x8
	// Bit mask of ALRAE field.
	RTC_CR_ALRAE_Msk = 0x100
	// Bit ALRAE.
	RTC_CR_ALRAE = 0x100
	// Position of WUTE field.
	RTC_CR_WUTE_Pos = 0xa
	// Bit mask of WUTE field.
	RTC_CR_WUTE_Msk = 0x400
	// Bit WUTE.
	RTC_CR_WUTE = 0x400
	// Position of ALRAIE field.
	RTC_CR_ALRAIE_Pos = 0xc
	// Bit mask of ALRAIE field.
	RTC_CR_ALRAIE_Msk = 0x1000
	// Bit ALRAIE.
	RTC_CR_ALRAIE = 0x1000
	// Position of WUTIE field.
	RTC_CR_WUTIE_Pos = 0xe
	// Bit mask of WUTIE field.
	RTC_CR_WUTIE_Msk = 0x4000
	// Bit WUTIE.
	RTC_CR_WUTIE = 0x4000
	// Position of ADD1H field.
	RTC_CR_ADD1H_Pos = 0x10
	// Bit mask of ADD1H field.
	RTC_CR_ADD1H_Msk = 0x10000
	// Bit ADD1H.
	RTC_CR_ADD1H = 0x10000
	// Position of SUB1H field.
	RTC_CR_SUB1H_Pos = 0x11
	// Bit mask of SUB1H field.
	RTC_CR_SUB1H_Msk = 0x20000
	// Bit SUB1H.
	RTC_CR_SUB1H = 0x20000
	// Position of BKP field.
	RTC_CR_BKP_Pos = 0x12
	// Bit mask of BKP field.
	RTC_CR_BKP_Msk = 0x40000
	// Bit BKP.
	RTC_CR_BKP = 0x40000
	// Position of COSEL field.
	RTC_CR_COSEL_Pos = 0x13
	// Bit mask of COSEL field.
	RTC_CR_COSEL_Msk = 0x80000
	// Bit COSEL.
	RTC_CR_COSEL = 0x80000
	// Position of POL field.
	RTC_CR_POL_Pos = 0x14
	// Bit mask of POL field.
	RTC_CR_POL_Msk = 0x100000
	// Bit POL.
	RTC_CR_POL = 0x100000
	// Position of OSEL field.
	RTC_CR_OSEL_Pos = 0x15
	// Bit mask of OSEL field.
	RTC_CR_OSEL_Msk = 0x600000
	// Position of COE field.
	RTC_CR_COE_Pos = 0x17
	// Bit mask of COE field.
	RTC_CR_COE_Msk = 0x800000
	// Bit COE.
	RTC_CR_COE = 0x800000

	// ISR: RTC_ISR register
	// Position of ALRAWF field.
	RTC_ISR_ALRAWF_Pos = 0x0
	// Bit mask of ALRAWF field.
	RTC_ISR_ALRAWF_Msk = 0x1
	// Bit ALRAWF.
	RTC_ISR_ALRAWF = 0x1
	// Position of WUTWF field.
	RTC_ISR_WUTWF_Pos = 0x2
	// Bit mask of WUTWF field.
	RTC_ISR_WUTWF_Msk = 0x4
	// Bit WUTWF.
	RTC_ISR_WUTWF = 0x4
	// Position of SHPF field.
	RTC_ISR_SHPF_Pos = 0x3
	// Bit mask of SHPF field.
	RTC_ISR_SHPF_Msk = 0x8
	// Bit SHPF.
	RTC_ISR_SHPF = 0x8
	// Position of INITS field.
	RTC_ISR_INITS_Pos = 0x4
	// Bit mask of INITS field.
	RTC_ISR_INITS_Msk = 0x10
	// Bit INITS.
	RTC_ISR_INITS = 0x10
	// Position of RSF field.
	RTC_ISR_RSF_Pos = 0x5
	// Bit mask of RSF field.
	RTC_ISR_RSF_Msk = 0x20
	// Bit RSF.
	RTC_ISR_RSF = 0x20
	// Position of INITF field.
	RTC_ISR_INITF_Pos = 0x6
	// Bit mask of INITF field.
	RTC_ISR_INITF_Msk = 0x40
	// Bit INITF.
	RTC_ISR_INITF = 0x40
	// Position of INIT field.
	RTC_ISR_INIT_Pos = 0x7
	// Bit mask of INIT field.
	RTC_ISR_INIT_Msk = 0x80
	// Bit INIT.
	RTC_ISR_INIT = 0x80
	// Position of ALRAF field.
	RTC_ISR_ALRAF_Pos = 0x8
	// Bit mask of ALRAF field.
	RTC_ISR_ALRAF_Msk = 0x100
	// Bit ALRAF.
	RTC_ISR_ALRAF = 0x100
	// Position of WUTF field.
	RTC_ISR_WUTF_Pos = 0xa
	// Bit mask of WUTF field.
	RTC_ISR_WUTF_Msk = 0x400
	// Bit WUTF.
	RTC_ISR_WUTF = 0x400
	// Position of RECALPF field.
	RTC_ISR_RECALPF_Pos = 0x10
	// Bit mask of RECALPF field.
	RTC_ISR_RECALPF_Msk = 0x10000
	// Bit RECALPF.
	RTC_ISR_RECALPF = 0x10000

	// PRER: RTC_PRER register
	// Position of PREDIV_S field.
	RTC_PRER_PREDIV_S_Pos = 0x0
	// Bit mask of PREDIV_S field.
	RTC_PRER_PREDIV_S_Msk = 0x7fff
	// Position of PREDIV_A field.
	RTC_PRER_PREDIV_A_Pos = 0x10
	// Bit mask of PREDIV_A field.
	RTC_PRER_PREDIV_A_Msk = 0x7f0000

	// WUTR: RTC_WUTR register
	// Position of WUT field.
	RTC_WUTR_WUT_Pos = 0x0
	// Bit mask of WUT field.
	RTC_WUTR_WUT_Msk = 0xffff

	// ALRMAR: RTC_ALRMAR register
	// Position of SU field.
	RTC_ALRMAR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_ALRMAR_SU_Msk = 0xf
	// Position of ST field.
	RTC_ALRMAR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_ALRMAR_ST_Msk = 0x70
	// Position of MSK1 field.
	RTC_ALRMAR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_ALRMAR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_ALRMAR_MSK1 = 0x80
	// Position of MNU field.
	RTC_ALRMAR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_ALRMAR_MNU_Msk = 0xf00
	// Position of MNT field.
	RTC_ALRMAR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_ALRMAR_MNT_Msk = 0x7000
	// Position of MSK2 field.
	RTC_ALRMAR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_ALRMAR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_ALRMAR_MSK2 = 0x8000
	// Position of HU field.
	RTC_ALRMAR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_ALRMAR_HU_Msk = 0xf0000
	// Position of HT field.
	RTC_ALRMAR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_ALRMAR_HT_Msk = 0x300000
	// Position of PM field.
	RTC_ALRMAR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_ALRMAR_PM_Msk = 0x400000
	// Bit PM.
	RTC_ALRMAR_PM = 0x400000
	// Position of MSK3 field.
	RTC_ALRMAR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_ALRMAR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_ALRMAR_MSK3 = 0x800000
	// Position of DU field.
	RTC_ALRMAR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_ALRMAR_DU_Msk = 0xf000000
	// Position of DT field.
	RTC_ALRMAR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_ALRMAR_DT_Msk = 0x30000000
	// Position of WDSEL field.
	RTC_ALRMAR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_ALRMAR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_ALRMAR_WDSEL = 0x40000000
	// Position of MSK4 field.
	RTC_ALRMAR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_ALRMAR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_ALRMAR_MSK4 = 0x80000000

	// WPR: RTC_WPR register
	// Position of KEY field.
	RTC_WPR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	RTC_WPR_KEY_Msk = 0xff

	// SSR: RTC_SSR register
	// Position of SS field.
	RTC_SSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_SSR_SS_Msk = 0xffff

	// SHIFTR: RTC_SHIFTR register
	// Position of SUBFS field.
	RTC_SHIFTR_SUBFS_Pos = 0x0
	// Bit mask of SUBFS field.
	RTC_SHIFTR_SUBFS_Msk = 0x7fff
	// Position of ADD1S field.
	RTC_SHIFTR_ADD1S_Pos = 0x1f
	// Bit mask of ADD1S field.
	RTC_SHIFTR_ADD1S_Msk = 0x80000000
	// Bit ADD1S.
	RTC_SHIFTR_ADD1S = 0x80000000

	// CALR: RTC_CALR register
	// Position of CALM field.
	RTC_CALR_CALM_Pos = 0x0
	// Bit mask of CALM field.
	RTC_CALR_CALM_Msk = 0x1ff
	// Position of CALW16 field.
	RTC_CALR_CALW16_Pos = 0xd
	// Bit mask of CALW16 field.
	RTC_CALR_CALW16_Msk = 0x2000
	// Bit CALW16.
	RTC_CALR_CALW16 = 0x2000
	// Position of CALW8 field.
	RTC_CALR_CALW8_Pos = 0xe
	// Bit mask of CALW8 field.
	RTC_CALR_CALW8_Msk = 0x4000
	// Bit CALW8.
	RTC_CALR_CALW8 = 0x4000
	// Position of CALP field.
	RTC_CALR_CALP_Pos = 0xf
	// Bit mask of CALP field.
	RTC_CALR_CALP_Msk = 0x8000
	// Bit CALP.
	RTC_CALR_CALP = 0x8000

	// ALRMASSR: RTC_ALRMASSR register
	// Position of SS field.
	RTC_ALRMASSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_ALRMASSR_SS_Msk = 0x7fff
	// Position of MASKSS field.
	RTC_ALRMASSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_ALRMASSR_MASKSS_Msk = 0xf000000

	// BKP0R: RTC_BKP0R register
	// Position of BKP field.
	RTC_BKP0R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	RTC_BKP0R_BKP_Msk = 0xffffffff

	// BKP1R: RTC_BKP1R register
	// Position of BKP field.
	RTC_BKP1R_BKP_Pos = 0x0
	// Bit mask of BKP field.
	RTC_BKP1R_BKP_Msk = 0xffffffff
)

// Constants for SYSTEM_CTRL
const (
	// DIE_ID: DIE_ID register
	// Position of REVISION field.
	SYSTEM_CTRL_DIE_ID_REVISION_Pos = 0x0
	// Bit mask of REVISION field.
	SYSTEM_CTRL_DIE_ID_REVISION_Msk = 0xf
	// Position of VERSION field.
	SYSTEM_CTRL_DIE_ID_VERSION_Pos = 0x4
	// Bit mask of VERSION field.
	SYSTEM_CTRL_DIE_ID_VERSION_Msk = 0xf0
	// Position of PRODUCT field.
	SYSTEM_CTRL_DIE_ID_PRODUCT_Pos = 0x8
	// Bit mask of PRODUCT field.
	SYSTEM_CTRL_DIE_ID_PRODUCT_Msk = 0xf00

	// JTAG_ID: JTAG_ID register
	// Position of MANUF_ID field.
	SYSTEM_CTRL_JTAG_ID_MANUF_ID_Pos = 0x1
	// Bit mask of MANUF_ID field.
	SYSTEM_CTRL_JTAG_ID_MANUF_ID_Msk = 0xffe
	// Position of PART_NUMBER field.
	SYSTEM_CTRL_JTAG_ID_PART_NUMBER_Pos = 0xc
	// Bit mask of PART_NUMBER field.
	SYSTEM_CTRL_JTAG_ID_PART_NUMBER_Msk = 0xffff000
	// Position of VERSION_NUMBER field.
	SYSTEM_CTRL_JTAG_ID_VERSION_NUMBER_Pos = 0x1c
	// Bit mask of VERSION_NUMBER field.
	SYSTEM_CTRL_JTAG_ID_VERSION_NUMBER_Msk = 0xf0000000

	// I2C_FMP_CTRL: I2C_FMP_CTRL register
	// Position of I2C1_PA0_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PA0_FMP_Pos = 0x0
	// Bit mask of I2C1_PA0_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PA0_FMP_Msk = 0x1
	// Bit I2C1_PA0_FMP.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PA0_FMP = 0x1
	// Position of I2C1_PA1_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PA1_FMP_Pos = 0x1
	// Bit mask of I2C1_PA1_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PA1_FMP_Msk = 0x2
	// Bit I2C1_PA1_FMP.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PA1_FMP = 0x2
	// Position of I2C1_PB6_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PB6_FMP_Pos = 0x2
	// Bit mask of I2C1_PB6_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PB6_FMP_Msk = 0x4
	// Bit I2C1_PB6_FMP.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PB6_FMP = 0x4
	// Position of I2C1_PB7_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PB7_FMP_Pos = 0x3
	// Bit mask of I2C1_PB7_FMP field.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PB7_FMP_Msk = 0x8
	// Bit I2C1_PB7_FMP.
	SYSTEM_CTRL_I2C_FMP_CTRL_I2C1_PB7_FMP = 0x8

	// IO_DTR: IO_DTR register
	// Position of PA0_DT field.
	SYSTEM_CTRL_IO_DTR_PA0_DT_Pos = 0x0
	// Bit mask of PA0_DT field.
	SYSTEM_CTRL_IO_DTR_PA0_DT_Msk = 0x1
	// Bit PA0_DT.
	SYSTEM_CTRL_IO_DTR_PA0_DT = 0x1
	// Position of PA1_DT field.
	SYSTEM_CTRL_IO_DTR_PA1_DT_Pos = 0x1
	// Bit mask of PA1_DT field.
	SYSTEM_CTRL_IO_DTR_PA1_DT_Msk = 0x2
	// Bit PA1_DT.
	SYSTEM_CTRL_IO_DTR_PA1_DT = 0x2
	// Position of PA2_DT field.
	SYSTEM_CTRL_IO_DTR_PA2_DT_Pos = 0x2
	// Bit mask of PA2_DT field.
	SYSTEM_CTRL_IO_DTR_PA2_DT_Msk = 0x4
	// Bit PA2_DT.
	SYSTEM_CTRL_IO_DTR_PA2_DT = 0x4
	// Position of PA3_DT field.
	SYSTEM_CTRL_IO_DTR_PA3_DT_Pos = 0x3
	// Bit mask of PA3_DT field.
	SYSTEM_CTRL_IO_DTR_PA3_DT_Msk = 0x8
	// Bit PA3_DT.
	SYSTEM_CTRL_IO_DTR_PA3_DT = 0x8
	// Position of PA8_DT field.
	SYSTEM_CTRL_IO_DTR_PA8_DT_Pos = 0x8
	// Bit mask of PA8_DT field.
	SYSTEM_CTRL_IO_DTR_PA8_DT_Msk = 0x100
	// Bit PA8_DT.
	SYSTEM_CTRL_IO_DTR_PA8_DT = 0x100
	// Position of PA9_DT field.
	SYSTEM_CTRL_IO_DTR_PA9_DT_Pos = 0x9
	// Bit mask of PA9_DT field.
	SYSTEM_CTRL_IO_DTR_PA9_DT_Msk = 0x200
	// Bit PA9_DT.
	SYSTEM_CTRL_IO_DTR_PA9_DT = 0x200
	// Position of PA10_DT field.
	SYSTEM_CTRL_IO_DTR_PA10_DT_Pos = 0xa
	// Bit mask of PA10_DT field.
	SYSTEM_CTRL_IO_DTR_PA10_DT_Msk = 0x400
	// Bit PA10_DT.
	SYSTEM_CTRL_IO_DTR_PA10_DT = 0x400
	// Position of PA11_DT field.
	SYSTEM_CTRL_IO_DTR_PA11_DT_Pos = 0xb
	// Bit mask of PA11_DT field.
	SYSTEM_CTRL_IO_DTR_PA11_DT_Msk = 0x800
	// Bit PA11_DT.
	SYSTEM_CTRL_IO_DTR_PA11_DT = 0x800
	// Position of PB0_DT field.
	SYSTEM_CTRL_IO_DTR_PB0_DT_Pos = 0x10
	// Bit mask of PB0_DT field.
	SYSTEM_CTRL_IO_DTR_PB0_DT_Msk = 0x10000
	// Bit PB0_DT.
	SYSTEM_CTRL_IO_DTR_PB0_DT = 0x10000
	// Position of PB1_DT field.
	SYSTEM_CTRL_IO_DTR_PB1_DT_Pos = 0x11
	// Bit mask of PB1_DT field.
	SYSTEM_CTRL_IO_DTR_PB1_DT_Msk = 0x20000
	// Bit PB1_DT.
	SYSTEM_CTRL_IO_DTR_PB1_DT = 0x20000
	// Position of PB2_DT field.
	SYSTEM_CTRL_IO_DTR_PB2_DT_Pos = 0x12
	// Bit mask of PB2_DT field.
	SYSTEM_CTRL_IO_DTR_PB2_DT_Msk = 0x40000
	// Bit PB2_DT.
	SYSTEM_CTRL_IO_DTR_PB2_DT = 0x40000
	// Position of PB3_DT field.
	SYSTEM_CTRL_IO_DTR_PB3_DT_Pos = 0x13
	// Bit mask of PB3_DT field.
	SYSTEM_CTRL_IO_DTR_PB3_DT_Msk = 0x80000
	// Bit PB3_DT.
	SYSTEM_CTRL_IO_DTR_PB3_DT = 0x80000
	// Position of PB4_DT field.
	SYSTEM_CTRL_IO_DTR_PB4_DT_Pos = 0x14
	// Bit mask of PB4_DT field.
	SYSTEM_CTRL_IO_DTR_PB4_DT_Msk = 0x100000
	// Bit PB4_DT.
	SYSTEM_CTRL_IO_DTR_PB4_DT = 0x100000
	// Position of PB5_DT field.
	SYSTEM_CTRL_IO_DTR_PB5_DT_Pos = 0x15
	// Bit mask of PB5_DT field.
	SYSTEM_CTRL_IO_DTR_PB5_DT_Msk = 0x200000
	// Bit PB5_DT.
	SYSTEM_CTRL_IO_DTR_PB5_DT = 0x200000
	// Position of PB6_DT field.
	SYSTEM_CTRL_IO_DTR_PB6_DT_Pos = 0x16
	// Bit mask of PB6_DT field.
	SYSTEM_CTRL_IO_DTR_PB6_DT_Msk = 0x400000
	// Bit PB6_DT.
	SYSTEM_CTRL_IO_DTR_PB6_DT = 0x400000
	// Position of PB7_DT field.
	SYSTEM_CTRL_IO_DTR_PB7_DT_Pos = 0x17
	// Bit mask of PB7_DT field.
	SYSTEM_CTRL_IO_DTR_PB7_DT_Msk = 0x800000
	// Bit PB7_DT.
	SYSTEM_CTRL_IO_DTR_PB7_DT = 0x800000
	// Position of PB12_DT field.
	SYSTEM_CTRL_IO_DTR_PB12_DT_Pos = 0x1c
	// Bit mask of PB12_DT field.
	SYSTEM_CTRL_IO_DTR_PB12_DT_Msk = 0x10000000
	// Bit PB12_DT.
	SYSTEM_CTRL_IO_DTR_PB12_DT = 0x10000000
	// Position of PB13_DT field.
	SYSTEM_CTRL_IO_DTR_PB13_DT_Pos = 0x1d
	// Bit mask of PB13_DT field.
	SYSTEM_CTRL_IO_DTR_PB13_DT_Msk = 0x20000000
	// Bit PB13_DT.
	SYSTEM_CTRL_IO_DTR_PB13_DT = 0x20000000
	// Position of PB14_DT field.
	SYSTEM_CTRL_IO_DTR_PB14_DT_Pos = 0x1e
	// Bit mask of PB14_DT field.
	SYSTEM_CTRL_IO_DTR_PB14_DT_Msk = 0x40000000
	// Bit PB14_DT.
	SYSTEM_CTRL_IO_DTR_PB14_DT = 0x40000000
	// Position of PB15_DT field.
	SYSTEM_CTRL_IO_DTR_PB15_DT_Pos = 0x1f
	// Bit mask of PB15_DT field.
	SYSTEM_CTRL_IO_DTR_PB15_DT_Msk = 0x80000000
	// Bit PB15_DT.
	SYSTEM_CTRL_IO_DTR_PB15_DT = 0x80000000

	// IO_IBER: IO_IBER register
	// Position of PA0_IBE field.
	SYSTEM_CTRL_IO_IBER_PA0_IBE_Pos = 0x0
	// Bit mask of PA0_IBE field.
	SYSTEM_CTRL_IO_IBER_PA0_IBE_Msk = 0x1
	// Bit PA0_IBE.
	SYSTEM_CTRL_IO_IBER_PA0_IBE = 0x1
	// Position of PA1_IBE field.
	SYSTEM_CTRL_IO_IBER_PA1_IBE_Pos = 0x1
	// Bit mask of PA1_IBE field.
	SYSTEM_CTRL_IO_IBER_PA1_IBE_Msk = 0x2
	// Bit PA1_IBE.
	SYSTEM_CTRL_IO_IBER_PA1_IBE = 0x2
	// Position of PA2_IBE field.
	SYSTEM_CTRL_IO_IBER_PA2_IBE_Pos = 0x2
	// Bit mask of PA2_IBE field.
	SYSTEM_CTRL_IO_IBER_PA2_IBE_Msk = 0x4
	// Bit PA2_IBE.
	SYSTEM_CTRL_IO_IBER_PA2_IBE = 0x4
	// Position of PA3_IBE field.
	SYSTEM_CTRL_IO_IBER_PA3_IBE_Pos = 0x3
	// Bit mask of PA3_IBE field.
	SYSTEM_CTRL_IO_IBER_PA3_IBE_Msk = 0x8
	// Bit PA3_IBE.
	SYSTEM_CTRL_IO_IBER_PA3_IBE = 0x8
	// Position of PA8_IBE field.
	SYSTEM_CTRL_IO_IBER_PA8_IBE_Pos = 0x8
	// Bit mask of PA8_IBE field.
	SYSTEM_CTRL_IO_IBER_PA8_IBE_Msk = 0x100
	// Bit PA8_IBE.
	SYSTEM_CTRL_IO_IBER_PA8_IBE = 0x100
	// Position of PA9_IBE field.
	SYSTEM_CTRL_IO_IBER_PA9_IBE_Pos = 0x9
	// Bit mask of PA9_IBE field.
	SYSTEM_CTRL_IO_IBER_PA9_IBE_Msk = 0x200
	// Bit PA9_IBE.
	SYSTEM_CTRL_IO_IBER_PA9_IBE = 0x200
	// Position of PA10_IBE field.
	SYSTEM_CTRL_IO_IBER_PA10_IBE_Pos = 0xa
	// Bit mask of PA10_IBE field.
	SYSTEM_CTRL_IO_IBER_PA10_IBE_Msk = 0x400
	// Bit PA10_IBE.
	SYSTEM_CTRL_IO_IBER_PA10_IBE = 0x400
	// Position of PA11_IBE field.
	SYSTEM_CTRL_IO_IBER_PA11_IBE_Pos = 0xb
	// Bit mask of PA11_IBE field.
	SYSTEM_CTRL_IO_IBER_PA11_IBE_Msk = 0x800
	// Bit PA11_IBE.
	SYSTEM_CTRL_IO_IBER_PA11_IBE = 0x800
	// Position of PB0_IBE field.
	SYSTEM_CTRL_IO_IBER_PB0_IBE_Pos = 0x10
	// Bit mask of PB0_IBE field.
	SYSTEM_CTRL_IO_IBER_PB0_IBE_Msk = 0x10000
	// Bit PB0_IBE.
	SYSTEM_CTRL_IO_IBER_PB0_IBE = 0x10000
	// Position of PB1_IBE field.
	SYSTEM_CTRL_IO_IBER_PB1_IBE_Pos = 0x11
	// Bit mask of PB1_IBE field.
	SYSTEM_CTRL_IO_IBER_PB1_IBE_Msk = 0x20000
	// Bit PB1_IBE.
	SYSTEM_CTRL_IO_IBER_PB1_IBE = 0x20000
	// Position of PB2_IBE field.
	SYSTEM_CTRL_IO_IBER_PB2_IBE_Pos = 0x12
	// Bit mask of PB2_IBE field.
	SYSTEM_CTRL_IO_IBER_PB2_IBE_Msk = 0x40000
	// Bit PB2_IBE.
	SYSTEM_CTRL_IO_IBER_PB2_IBE = 0x40000
	// Position of PB3_IBE field.
	SYSTEM_CTRL_IO_IBER_PB3_IBE_Pos = 0x13
	// Bit mask of PB3_IBE field.
	SYSTEM_CTRL_IO_IBER_PB3_IBE_Msk = 0x80000
	// Bit PB3_IBE.
	SYSTEM_CTRL_IO_IBER_PB3_IBE = 0x80000
	// Position of PB4_IBE field.
	SYSTEM_CTRL_IO_IBER_PB4_IBE_Pos = 0x14
	// Bit mask of PB4_IBE field.
	SYSTEM_CTRL_IO_IBER_PB4_IBE_Msk = 0x100000
	// Bit PB4_IBE.
	SYSTEM_CTRL_IO_IBER_PB4_IBE = 0x100000
	// Position of PB5_IBE field.
	SYSTEM_CTRL_IO_IBER_PB5_IBE_Pos = 0x15
	// Bit mask of PB5_IBE field.
	SYSTEM_CTRL_IO_IBER_PB5_IBE_Msk = 0x200000
	// Bit PB5_IBE.
	SYSTEM_CTRL_IO_IBER_PB5_IBE = 0x200000
	// Position of PB6_IBE field.
	SYSTEM_CTRL_IO_IBER_PB6_IBE_Pos = 0x16
	// Bit mask of PB6_IBE field.
	SYSTEM_CTRL_IO_IBER_PB6_IBE_Msk = 0x400000
	// Bit PB6_IBE.
	SYSTEM_CTRL_IO_IBER_PB6_IBE = 0x400000
	// Position of PB7_IBE field.
	SYSTEM_CTRL_IO_IBER_PB7_IBE_Pos = 0x17
	// Bit mask of PB7_IBE field.
	SYSTEM_CTRL_IO_IBER_PB7_IBE_Msk = 0x800000
	// Bit PB7_IBE.
	SYSTEM_CTRL_IO_IBER_PB7_IBE = 0x800000
	// Position of PB12_IBE field.
	SYSTEM_CTRL_IO_IBER_PB12_IBE_Pos = 0x1c
	// Bit mask of PB12_IBE field.
	SYSTEM_CTRL_IO_IBER_PB12_IBE_Msk = 0x10000000
	// Bit PB12_IBE.
	SYSTEM_CTRL_IO_IBER_PB12_IBE = 0x10000000
	// Position of PB13_IBE field.
	SYSTEM_CTRL_IO_IBER_PB13_IBE_Pos = 0x1d
	// Bit mask of PB13_IBE field.
	SYSTEM_CTRL_IO_IBER_PB13_IBE_Msk = 0x20000000
	// Bit PB13_IBE.
	SYSTEM_CTRL_IO_IBER_PB13_IBE = 0x20000000
	// Position of PB14_IBE field.
	SYSTEM_CTRL_IO_IBER_PB14_IBE_Pos = 0x1e
	// Bit mask of PB14_IBE field.
	SYSTEM_CTRL_IO_IBER_PB14_IBE_Msk = 0x40000000
	// Bit PB14_IBE.
	SYSTEM_CTRL_IO_IBER_PB14_IBE = 0x40000000
	// Position of PB15_IBE field.
	SYSTEM_CTRL_IO_IBER_PB15_IBE_Pos = 0x1f
	// Bit mask of PB15_IBE field.
	SYSTEM_CTRL_IO_IBER_PB15_IBE_Msk = 0x80000000
	// Bit PB15_IBE.
	SYSTEM_CTRL_IO_IBER_PB15_IBE = 0x80000000

	// IO_IEVR: IO_IEVR register
	// Position of PA0_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA0_IEV_Pos = 0x0
	// Bit mask of PA0_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA0_IEV_Msk = 0x1
	// Bit PA0_IEV.
	SYSTEM_CTRL_IO_IEVR_PA0_IEV = 0x1
	// Position of PA1_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA1_IEV_Pos = 0x1
	// Bit mask of PA1_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA1_IEV_Msk = 0x2
	// Bit PA1_IEV.
	SYSTEM_CTRL_IO_IEVR_PA1_IEV = 0x2
	// Position of PA2_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA2_IEV_Pos = 0x2
	// Bit mask of PA2_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA2_IEV_Msk = 0x4
	// Bit PA2_IEV.
	SYSTEM_CTRL_IO_IEVR_PA2_IEV = 0x4
	// Position of PA3_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA3_IEV_Pos = 0x3
	// Bit mask of PA3_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA3_IEV_Msk = 0x8
	// Bit PA3_IEV.
	SYSTEM_CTRL_IO_IEVR_PA3_IEV = 0x8
	// Position of PA8_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA8_IEV_Pos = 0x8
	// Bit mask of PA8_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA8_IEV_Msk = 0x100
	// Bit PA8_IEV.
	SYSTEM_CTRL_IO_IEVR_PA8_IEV = 0x100
	// Position of PA9_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA9_IEV_Pos = 0x9
	// Bit mask of PA9_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA9_IEV_Msk = 0x200
	// Bit PA9_IEV.
	SYSTEM_CTRL_IO_IEVR_PA9_IEV = 0x200
	// Position of PA10_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA10_IEV_Pos = 0xa
	// Bit mask of PA10_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA10_IEV_Msk = 0x400
	// Bit PA10_IEV.
	SYSTEM_CTRL_IO_IEVR_PA10_IEV = 0x400
	// Position of PA11_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA11_IEV_Pos = 0xb
	// Bit mask of PA11_IEV field.
	SYSTEM_CTRL_IO_IEVR_PA11_IEV_Msk = 0x800
	// Bit PA11_IEV.
	SYSTEM_CTRL_IO_IEVR_PA11_IEV = 0x800
	// Position of PB0_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB0_IEV_Pos = 0x10
	// Bit mask of PB0_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB0_IEV_Msk = 0x10000
	// Bit PB0_IEV.
	SYSTEM_CTRL_IO_IEVR_PB0_IEV = 0x10000
	// Position of PB1_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB1_IEV_Pos = 0x11
	// Bit mask of PB1_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB1_IEV_Msk = 0x20000
	// Bit PB1_IEV.
	SYSTEM_CTRL_IO_IEVR_PB1_IEV = 0x20000
	// Position of PB2_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB2_IEV_Pos = 0x12
	// Bit mask of PB2_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB2_IEV_Msk = 0x40000
	// Bit PB2_IEV.
	SYSTEM_CTRL_IO_IEVR_PB2_IEV = 0x40000
	// Position of PB3_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB3_IEV_Pos = 0x13
	// Bit mask of PB3_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB3_IEV_Msk = 0x80000
	// Bit PB3_IEV.
	SYSTEM_CTRL_IO_IEVR_PB3_IEV = 0x80000
	// Position of PB4_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB4_IEV_Pos = 0x14
	// Bit mask of PB4_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB4_IEV_Msk = 0x100000
	// Bit PB4_IEV.
	SYSTEM_CTRL_IO_IEVR_PB4_IEV = 0x100000
	// Position of PB5_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB5_IEV_Pos = 0x15
	// Bit mask of PB5_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB5_IEV_Msk = 0x200000
	// Bit PB5_IEV.
	SYSTEM_CTRL_IO_IEVR_PB5_IEV = 0x200000
	// Position of PB6_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB6_IEV_Pos = 0x16
	// Bit mask of PB6_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB6_IEV_Msk = 0x400000
	// Bit PB6_IEV.
	SYSTEM_CTRL_IO_IEVR_PB6_IEV = 0x400000
	// Position of PB7_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB7_IEV_Pos = 0x17
	// Bit mask of PB7_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB7_IEV_Msk = 0x800000
	// Bit PB7_IEV.
	SYSTEM_CTRL_IO_IEVR_PB7_IEV = 0x800000
	// Position of PB12_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB12_IEV_Pos = 0x1c
	// Bit mask of PB12_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB12_IEV_Msk = 0x10000000
	// Bit PB12_IEV.
	SYSTEM_CTRL_IO_IEVR_PB12_IEV = 0x10000000
	// Position of PB13_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB13_IEV_Pos = 0x1d
	// Bit mask of PB13_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB13_IEV_Msk = 0x20000000
	// Bit PB13_IEV.
	SYSTEM_CTRL_IO_IEVR_PB13_IEV = 0x20000000
	// Position of PB14_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB14_IEV_Pos = 0x1e
	// Bit mask of PB14_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB14_IEV_Msk = 0x40000000
	// Bit PB14_IEV.
	SYSTEM_CTRL_IO_IEVR_PB14_IEV = 0x40000000
	// Position of PB15_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB15_IEV_Pos = 0x1f
	// Bit mask of PB15_IEV field.
	SYSTEM_CTRL_IO_IEVR_PB15_IEV_Msk = 0x80000000
	// Bit PB15_IEV.
	SYSTEM_CTRL_IO_IEVR_PB15_IEV = 0x80000000

	// IO_IER: IO_IER register
	// Position of PA0_IE field.
	SYSTEM_CTRL_IO_IER_PA0_IE_Pos = 0x0
	// Bit mask of PA0_IE field.
	SYSTEM_CTRL_IO_IER_PA0_IE_Msk = 0x1
	// Bit PA0_IE.
	SYSTEM_CTRL_IO_IER_PA0_IE = 0x1
	// Position of PA1_IE field.
	SYSTEM_CTRL_IO_IER_PA1_IE_Pos = 0x1
	// Bit mask of PA1_IE field.
	SYSTEM_CTRL_IO_IER_PA1_IE_Msk = 0x2
	// Bit PA1_IE.
	SYSTEM_CTRL_IO_IER_PA1_IE = 0x2
	// Position of PA2_IE field.
	SYSTEM_CTRL_IO_IER_PA2_IE_Pos = 0x2
	// Bit mask of PA2_IE field.
	SYSTEM_CTRL_IO_IER_PA2_IE_Msk = 0x4
	// Bit PA2_IE.
	SYSTEM_CTRL_IO_IER_PA2_IE = 0x4
	// Position of PA3_IE field.
	SYSTEM_CTRL_IO_IER_PA3_IE_Pos = 0x3
	// Bit mask of PA3_IE field.
	SYSTEM_CTRL_IO_IER_PA3_IE_Msk = 0x8
	// Bit PA3_IE.
	SYSTEM_CTRL_IO_IER_PA3_IE = 0x8
	// Position of PA8_IE field.
	SYSTEM_CTRL_IO_IER_PA8_IE_Pos = 0x8
	// Bit mask of PA8_IE field.
	SYSTEM_CTRL_IO_IER_PA8_IE_Msk = 0x100
	// Bit PA8_IE.
	SYSTEM_CTRL_IO_IER_PA8_IE = 0x100
	// Position of PA9_IE field.
	SYSTEM_CTRL_IO_IER_PA9_IE_Pos = 0x9
	// Bit mask of PA9_IE field.
	SYSTEM_CTRL_IO_IER_PA9_IE_Msk = 0x200
	// Bit PA9_IE.
	SYSTEM_CTRL_IO_IER_PA9_IE = 0x200
	// Position of PA10_IE field.
	SYSTEM_CTRL_IO_IER_PA10_IE_Pos = 0xa
	// Bit mask of PA10_IE field.
	SYSTEM_CTRL_IO_IER_PA10_IE_Msk = 0x400
	// Bit PA10_IE.
	SYSTEM_CTRL_IO_IER_PA10_IE = 0x400
	// Position of PA11_IE field.
	SYSTEM_CTRL_IO_IER_PA11_IE_Pos = 0xb
	// Bit mask of PA11_IE field.
	SYSTEM_CTRL_IO_IER_PA11_IE_Msk = 0x800
	// Bit PA11_IE.
	SYSTEM_CTRL_IO_IER_PA11_IE = 0x800
	// Position of PB0_IE field.
	SYSTEM_CTRL_IO_IER_PB0_IE_Pos = 0x10
	// Bit mask of PB0_IE field.
	SYSTEM_CTRL_IO_IER_PB0_IE_Msk = 0x10000
	// Bit PB0_IE.
	SYSTEM_CTRL_IO_IER_PB0_IE = 0x10000
	// Position of PB1_IE field.
	SYSTEM_CTRL_IO_IER_PB1_IE_Pos = 0x11
	// Bit mask of PB1_IE field.
	SYSTEM_CTRL_IO_IER_PB1_IE_Msk = 0x20000
	// Bit PB1_IE.
	SYSTEM_CTRL_IO_IER_PB1_IE = 0x20000
	// Position of PB2_IE field.
	SYSTEM_CTRL_IO_IER_PB2_IE_Pos = 0x12
	// Bit mask of PB2_IE field.
	SYSTEM_CTRL_IO_IER_PB2_IE_Msk = 0x40000
	// Bit PB2_IE.
	SYSTEM_CTRL_IO_IER_PB2_IE = 0x40000
	// Position of PB3_IE field.
	SYSTEM_CTRL_IO_IER_PB3_IE_Pos = 0x13
	// Bit mask of PB3_IE field.
	SYSTEM_CTRL_IO_IER_PB3_IE_Msk = 0x80000
	// Bit PB3_IE.
	SYSTEM_CTRL_IO_IER_PB3_IE = 0x80000
	// Position of PB4_IE field.
	SYSTEM_CTRL_IO_IER_PB4_IE_Pos = 0x14
	// Bit mask of PB4_IE field.
	SYSTEM_CTRL_IO_IER_PB4_IE_Msk = 0x100000
	// Bit PB4_IE.
	SYSTEM_CTRL_IO_IER_PB4_IE = 0x100000
	// Position of PB5_IE field.
	SYSTEM_CTRL_IO_IER_PB5_IE_Pos = 0x15
	// Bit mask of PB5_IE field.
	SYSTEM_CTRL_IO_IER_PB5_IE_Msk = 0x200000
	// Bit PB5_IE.
	SYSTEM_CTRL_IO_IER_PB5_IE = 0x200000
	// Position of PB6_IE field.
	SYSTEM_CTRL_IO_IER_PB6_IE_Pos = 0x16
	// Bit mask of PB6_IE field.
	SYSTEM_CTRL_IO_IER_PB6_IE_Msk = 0x400000
	// Bit PB6_IE.
	SYSTEM_CTRL_IO_IER_PB6_IE = 0x400000
	// Position of PB7_IE field.
	SYSTEM_CTRL_IO_IER_PB7_IE_Pos = 0x17
	// Bit mask of PB7_IE field.
	SYSTEM_CTRL_IO_IER_PB7_IE_Msk = 0x800000
	// Bit PB7_IE.
	SYSTEM_CTRL_IO_IER_PB7_IE = 0x800000
	// Position of PB12_IE field.
	SYSTEM_CTRL_IO_IER_PB12_IE_Pos = 0x1c
	// Bit mask of PB12_IE field.
	SYSTEM_CTRL_IO_IER_PB12_IE_Msk = 0x10000000
	// Bit PB12_IE.
	SYSTEM_CTRL_IO_IER_PB12_IE = 0x10000000
	// Position of PB13_IE field.
	SYSTEM_CTRL_IO_IER_PB13_IE_Pos = 0x1d
	// Bit mask of PB13_IE field.
	SYSTEM_CTRL_IO_IER_PB13_IE_Msk = 0x20000000
	// Bit PB13_IE.
	SYSTEM_CTRL_IO_IER_PB13_IE = 0x20000000
	// Position of PB14_IE field.
	SYSTEM_CTRL_IO_IER_PB14_IE_Pos = 0x1e
	// Bit mask of PB14_IE field.
	SYSTEM_CTRL_IO_IER_PB14_IE_Msk = 0x40000000
	// Bit PB14_IE.
	SYSTEM_CTRL_IO_IER_PB14_IE = 0x40000000
	// Position of PB15_IE field.
	SYSTEM_CTRL_IO_IER_PB15_IE_Pos = 0x1f
	// Bit mask of PB15_IE field.
	SYSTEM_CTRL_IO_IER_PB15_IE_Msk = 0x80000000
	// Bit PB15_IE.
	SYSTEM_CTRL_IO_IER_PB15_IE = 0x80000000

	// IO_ISCR: IO_ISCR register
	// Position of PA0_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA0_ISC_Pos = 0x0
	// Bit mask of PA0_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA0_ISC_Msk = 0x1
	// Bit PA0_ISC.
	SYSTEM_CTRL_IO_ISCR_PA0_ISC = 0x1
	// Position of PA1_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA1_ISC_Pos = 0x1
	// Bit mask of PA1_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA1_ISC_Msk = 0x2
	// Bit PA1_ISC.
	SYSTEM_CTRL_IO_ISCR_PA1_ISC = 0x2
	// Position of PA2_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA2_ISC_Pos = 0x2
	// Bit mask of PA2_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA2_ISC_Msk = 0x4
	// Bit PA2_ISC.
	SYSTEM_CTRL_IO_ISCR_PA2_ISC = 0x4
	// Position of PA3_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA3_ISC_Pos = 0x3
	// Bit mask of PA3_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA3_ISC_Msk = 0x8
	// Bit PA3_ISC.
	SYSTEM_CTRL_IO_ISCR_PA3_ISC = 0x8
	// Position of PA8_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA8_ISC_Pos = 0x8
	// Bit mask of PA8_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA8_ISC_Msk = 0x100
	// Bit PA8_ISC.
	SYSTEM_CTRL_IO_ISCR_PA8_ISC = 0x100
	// Position of PA9_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA9_ISC_Pos = 0x9
	// Bit mask of PA9_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA9_ISC_Msk = 0x200
	// Bit PA9_ISC.
	SYSTEM_CTRL_IO_ISCR_PA9_ISC = 0x200
	// Position of PA10_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA10_ISC_Pos = 0xa
	// Bit mask of PA10_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA10_ISC_Msk = 0x400
	// Bit PA10_ISC.
	SYSTEM_CTRL_IO_ISCR_PA10_ISC = 0x400
	// Position of PA11_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA11_ISC_Pos = 0xb
	// Bit mask of PA11_ISC field.
	SYSTEM_CTRL_IO_ISCR_PA11_ISC_Msk = 0x800
	// Bit PA11_ISC.
	SYSTEM_CTRL_IO_ISCR_PA11_ISC = 0x800
	// Position of PB0_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB0_ISC_Pos = 0x10
	// Bit mask of PB0_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB0_ISC_Msk = 0x10000
	// Bit PB0_ISC.
	SYSTEM_CTRL_IO_ISCR_PB0_ISC = 0x10000
	// Position of PB1_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB1_ISC_Pos = 0x11
	// Bit mask of PB1_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB1_ISC_Msk = 0x20000
	// Bit PB1_ISC.
	SYSTEM_CTRL_IO_ISCR_PB1_ISC = 0x20000
	// Position of PB2_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB2_ISC_Pos = 0x12
	// Bit mask of PB2_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB2_ISC_Msk = 0x40000
	// Bit PB2_ISC.
	SYSTEM_CTRL_IO_ISCR_PB2_ISC = 0x40000
	// Position of PB3_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB3_ISC_Pos = 0x13
	// Bit mask of PB3_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB3_ISC_Msk = 0x80000
	// Bit PB3_ISC.
	SYSTEM_CTRL_IO_ISCR_PB3_ISC = 0x80000
	// Position of PB4_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB4_ISC_Pos = 0x14
	// Bit mask of PB4_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB4_ISC_Msk = 0x100000
	// Bit PB4_ISC.
	SYSTEM_CTRL_IO_ISCR_PB4_ISC = 0x100000
	// Position of PB5_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB5_ISC_Pos = 0x15
	// Bit mask of PB5_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB5_ISC_Msk = 0x200000
	// Bit PB5_ISC.
	SYSTEM_CTRL_IO_ISCR_PB5_ISC = 0x200000
	// Position of PB6_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB6_ISC_Pos = 0x16
	// Bit mask of PB6_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB6_ISC_Msk = 0x400000
	// Bit PB6_ISC.
	SYSTEM_CTRL_IO_ISCR_PB6_ISC = 0x400000
	// Position of PB7_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB7_ISC_Pos = 0x17
	// Bit mask of PB7_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB7_ISC_Msk = 0x800000
	// Bit PB7_ISC.
	SYSTEM_CTRL_IO_ISCR_PB7_ISC = 0x800000
	// Position of PB12_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB12_ISC_Pos = 0x1c
	// Bit mask of PB12_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB12_ISC_Msk = 0x10000000
	// Bit PB12_ISC.
	SYSTEM_CTRL_IO_ISCR_PB12_ISC = 0x10000000
	// Position of PB13_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB13_ISC_Pos = 0x1d
	// Bit mask of PB13_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB13_ISC_Msk = 0x20000000
	// Bit PB13_ISC.
	SYSTEM_CTRL_IO_ISCR_PB13_ISC = 0x20000000
	// Position of PB14_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB14_ISC_Pos = 0x1e
	// Bit mask of PB14_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB14_ISC_Msk = 0x40000000
	// Bit PB14_ISC.
	SYSTEM_CTRL_IO_ISCR_PB14_ISC = 0x40000000
	// Position of PB15_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB15_ISC_Pos = 0x1f
	// Bit mask of PB15_ISC field.
	SYSTEM_CTRL_IO_ISCR_PB15_ISC_Msk = 0x80000000
	// Bit PB15_ISC.
	SYSTEM_CTRL_IO_ISCR_PB15_ISC = 0x80000000

	// PWRC_IER: PWRC_IER register
	// Position of BORH_IE field.
	SYSTEM_CTRL_PWRC_IER_BORH_IE_Pos = 0x0
	// Bit mask of BORH_IE field.
	SYSTEM_CTRL_PWRC_IER_BORH_IE_Msk = 0x1
	// Bit BORH_IE.
	SYSTEM_CTRL_PWRC_IER_BORH_IE = 0x1
	// Position of PVD_IE field.
	SYSTEM_CTRL_PWRC_IER_PVD_IE_Pos = 0x1
	// Bit mask of PVD_IE field.
	SYSTEM_CTRL_PWRC_IER_PVD_IE_Msk = 0x2
	// Bit PVD_IE.
	SYSTEM_CTRL_PWRC_IER_PVD_IE = 0x2
	// Position of WKUP_IE field.
	SYSTEM_CTRL_PWRC_IER_WKUP_IE_Pos = 0x2
	// Bit mask of WKUP_IE field.
	SYSTEM_CTRL_PWRC_IER_WKUP_IE_Msk = 0x4
	// Bit WKUP_IE.
	SYSTEM_CTRL_PWRC_IER_WKUP_IE = 0x4

	// PWRC_ISCR: PWRC_ISCR register
	// Position of BORH_ISC field.
	SYSTEM_CTRL_PWRC_ISCR_BORH_ISC_Pos = 0x0
	// Bit mask of BORH_ISC field.
	SYSTEM_CTRL_PWRC_ISCR_BORH_ISC_Msk = 0x1
	// Bit BORH_ISC.
	SYSTEM_CTRL_PWRC_ISCR_BORH_ISC = 0x1
	// Position of PVD_ISC field.
	SYSTEM_CTRL_PWRC_ISCR_PVD_ISC_Pos = 0x1
	// Bit mask of PVD_ISC field.
	SYSTEM_CTRL_PWRC_ISCR_PVD_ISC_Msk = 0x2
	// Bit PVD_ISC.
	SYSTEM_CTRL_PWRC_ISCR_PVD_ISC = 0x2
	// Position of WKUP_ISC field.
	SYSTEM_CTRL_PWRC_ISCR_WKUP_ISC_Pos = 0x2
	// Bit mask of WKUP_ISC field.
	SYSTEM_CTRL_PWRC_ISCR_WKUP_ISC_Msk = 0x4
	// Bit WKUP_ISC.
	SYSTEM_CTRL_PWRC_ISCR_WKUP_ISC = 0x4

	// BLERXTX_DTR: BLERXTX_DTR register
	// Position of TX_DT field.
	SYSTEM_CTRL_BLERXTX_DTR_TX_DT_Pos = 0x0
	// Bit mask of TX_DT field.
	SYSTEM_CTRL_BLERXTX_DTR_TX_DT_Msk = 0x1
	// Bit TX_DT.
	SYSTEM_CTRL_BLERXTX_DTR_TX_DT = 0x1
	// Position of RX_DT field.
	SYSTEM_CTRL_BLERXTX_DTR_RX_DT_Pos = 0x1
	// Bit mask of RX_DT field.
	SYSTEM_CTRL_BLERXTX_DTR_RX_DT_Msk = 0x2
	// Bit RX_DT.
	SYSTEM_CTRL_BLERXTX_DTR_RX_DT = 0x2

	// BLERXTX_IBER: BLERXTX_IBER register
	// Position of TX_IBE field.
	SYSTEM_CTRL_BLERXTX_IBER_TX_IBE_Pos = 0x0
	// Bit mask of TX_IBE field.
	SYSTEM_CTRL_BLERXTX_IBER_TX_IBE_Msk = 0x1
	// Bit TX_IBE.
	SYSTEM_CTRL_BLERXTX_IBER_TX_IBE = 0x1
	// Position of RX_IBE field.
	SYSTEM_CTRL_BLERXTX_IBER_RX_IBE_Pos = 0x1
	// Bit mask of RX_IBE field.
	SYSTEM_CTRL_BLERXTX_IBER_RX_IBE_Msk = 0x2
	// Bit RX_IBE.
	SYSTEM_CTRL_BLERXTX_IBER_RX_IBE = 0x2

	// BLERXTX_IEVR: BLERXTX_IEVR register
	// Position of TX_IEV field.
	SYSTEM_CTRL_BLERXTX_IEVR_TX_IEV_Pos = 0x0
	// Bit mask of TX_IEV field.
	SYSTEM_CTRL_BLERXTX_IEVR_TX_IEV_Msk = 0x1
	// Bit TX_IEV.
	SYSTEM_CTRL_BLERXTX_IEVR_TX_IEV = 0x1
	// Position of RX_IEV field.
	SYSTEM_CTRL_BLERXTX_IEVR_RX_IEV_Pos = 0x1
	// Bit mask of RX_IEV field.
	SYSTEM_CTRL_BLERXTX_IEVR_RX_IEV_Msk = 0x2
	// Bit RX_IEV.
	SYSTEM_CTRL_BLERXTX_IEVR_RX_IEV = 0x2

	// BLERXTX_IER: BLERXTX_IER register
	// Position of TX_IE field.
	SYSTEM_CTRL_BLERXTX_IER_TX_IE_Pos = 0x0
	// Bit mask of TX_IE field.
	SYSTEM_CTRL_BLERXTX_IER_TX_IE_Msk = 0x1
	// Bit TX_IE.
	SYSTEM_CTRL_BLERXTX_IER_TX_IE = 0x1
	// Position of RX_IE field.
	SYSTEM_CTRL_BLERXTX_IER_RX_IE_Pos = 0x1
	// Bit mask of RX_IE field.
	SYSTEM_CTRL_BLERXTX_IER_RX_IE_Msk = 0x2
	// Bit RX_IE.
	SYSTEM_CTRL_BLERXTX_IER_RX_IE = 0x2

	// BLERXTX_ISCR: BLERXTX_ISCR register
	// Position of TX_ISC field.
	SYSTEM_CTRL_BLERXTX_ISCR_TX_ISC_Pos = 0x0
	// Bit mask of TX_ISC field.
	SYSTEM_CTRL_BLERXTX_ISCR_TX_ISC_Msk = 0x1
	// Bit TX_ISC.
	SYSTEM_CTRL_BLERXTX_ISCR_TX_ISC = 0x1
	// Position of RX_ISC field.
	SYSTEM_CTRL_BLERXTX_ISCR_RX_ISC_Pos = 0x1
	// Bit mask of RX_ISC field.
	SYSTEM_CTRL_BLERXTX_ISCR_RX_ISC_Msk = 0x2
	// Bit RX_ISC.
	SYSTEM_CTRL_BLERXTX_ISCR_RX_ISC = 0x2
	// Position of TX_ISEDGE field.
	SYSTEM_CTRL_BLERXTX_ISCR_TX_ISEDGE_Pos = 0x2
	// Bit mask of TX_ISEDGE field.
	SYSTEM_CTRL_BLERXTX_ISCR_TX_ISEDGE_Msk = 0x4
	// Bit TX_ISEDGE.
	SYSTEM_CTRL_BLERXTX_ISCR_TX_ISEDGE = 0x4
	// Position of RX_ISEDGE field.
	SYSTEM_CTRL_BLERXTX_ISCR_RX_ISEDGE_Pos = 0x3
	// Bit mask of RX_ISEDGE field.
	SYSTEM_CTRL_BLERXTX_ISCR_RX_ISEDGE_Msk = 0x8
	// Bit RX_ISEDGE.
	SYSTEM_CTRL_BLERXTX_ISCR_RX_ISEDGE = 0x8
)

// Constants for I2C1: I2C address block description
const (
	// CR1: I2C control register 1
	// Position of PE field.
	I2C_CR1_PE_Pos = 0x0
	// Bit mask of PE field.
	I2C_CR1_PE_Msk = 0x1
	// Bit PE.
	I2C_CR1_PE = 0x1
	// Peripheral disabled
	I2C_CR1_PE_Disabled = 0x0
	// Peripheral enabled
	I2C_CR1_PE_Enabled = 0x1
	// Position of TXIE field.
	I2C_CR1_TXIE_Pos = 0x1
	// Bit mask of TXIE field.
	I2C_CR1_TXIE_Msk = 0x2
	// Bit TXIE.
	I2C_CR1_TXIE = 0x2
	// Transmit (TXIS) interrupt disabled
	I2C_CR1_TXIE_Disabled = 0x0
	// Transmit (TXIS) interrupt enabled
	I2C_CR1_TXIE_Enabled = 0x1
	// Position of RXIE field.
	I2C_CR1_RXIE_Pos = 0x2
	// Bit mask of RXIE field.
	I2C_CR1_RXIE_Msk = 0x4
	// Bit RXIE.
	I2C_CR1_RXIE = 0x4
	// Receive (RXNE) interrupt disabled
	I2C_CR1_RXIE_Disabled = 0x0
	// Receive (RXNE) interrupt enabled
	I2C_CR1_RXIE_Enabled = 0x1
	// Position of ADDRIE field.
	I2C_CR1_ADDRIE_Pos = 0x3
	// Bit mask of ADDRIE field.
	I2C_CR1_ADDRIE_Msk = 0x8
	// Bit ADDRIE.
	I2C_CR1_ADDRIE = 0x8
	// Address match (ADDR) interrupts disabled
	I2C_CR1_ADDRIE_Disabled = 0x0
	// Address match (ADDR) interrupts enabled
	I2C_CR1_ADDRIE_Enabled = 0x1
	// Position of NACKIE field.
	I2C_CR1_NACKIE_Pos = 0x4
	// Bit mask of NACKIE field.
	I2C_CR1_NACKIE_Msk = 0x10
	// Bit NACKIE.
	I2C_CR1_NACKIE = 0x10
	// Not acknowledge (NACKF) received interrupts disabled
	I2C_CR1_NACKIE_Disabled = 0x0
	// Not acknowledge (NACKF) received interrupts enabled
	I2C_CR1_NACKIE_Enabled = 0x1
	// Position of STOPIE field.
	I2C_CR1_STOPIE_Pos = 0x5
	// Bit mask of STOPIE field.
	I2C_CR1_STOPIE_Msk = 0x20
	// Bit STOPIE.
	I2C_CR1_STOPIE = 0x20
	// Stop detection (STOPF) interrupt disabled
	I2C_CR1_STOPIE_Disabled = 0x0
	// Stop detection (STOPF) interrupt enabled
	I2C_CR1_STOPIE_Enabled = 0x1
	// Position of TCIE field.
	I2C_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	I2C_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	I2C_CR1_TCIE = 0x40
	// Transfer Complete interrupt disabled
	I2C_CR1_TCIE_Disabled = 0x0
	// Transfer Complete interrupt enabled
	I2C_CR1_TCIE_Enabled = 0x1
	// Position of ERRIE field.
	I2C_CR1_ERRIE_Pos = 0x7
	// Bit mask of ERRIE field.
	I2C_CR1_ERRIE_Msk = 0x80
	// Bit ERRIE.
	I2C_CR1_ERRIE = 0x80
	// Error detection interrupts disabled
	I2C_CR1_ERRIE_Disabled = 0x0
	// Error detection interrupts enabled
	I2C_CR1_ERRIE_Enabled = 0x1
	// Position of DNF field.
	I2C_CR1_DNF_Pos = 0x8
	// Bit mask of DNF field.
	I2C_CR1_DNF_Msk = 0xf00
	// Digital filter disabled
	I2C_CR1_DNF_NoFilter = 0x0
	// Digital filter enabled and filtering capability up to 1 tI2CCLK
	I2C_CR1_DNF_Filter1 = 0x1
	// Digital filter enabled and filtering capability up to 2 tI2CCLK
	I2C_CR1_DNF_Filter2 = 0x2
	// Digital filter enabled and filtering capability up to 3 tI2CCLK
	I2C_CR1_DNF_Filter3 = 0x3
	// Digital filter enabled and filtering capability up to 4 tI2CCLK
	I2C_CR1_DNF_Filter4 = 0x4
	// Digital filter enabled and filtering capability up to 5 tI2CCLK
	I2C_CR1_DNF_Filter5 = 0x5
	// Digital filter enabled and filtering capability up to 6 tI2CCLK
	I2C_CR1_DNF_Filter6 = 0x6
	// Digital filter enabled and filtering capability up to 7 tI2CCLK
	I2C_CR1_DNF_Filter7 = 0x7
	// Digital filter enabled and filtering capability up to 8 tI2CCLK
	I2C_CR1_DNF_Filter8 = 0x8
	// Digital filter enabled and filtering capability up to 9 tI2CCLK
	I2C_CR1_DNF_Filter9 = 0x9
	// Digital filter enabled and filtering capability up to 10 tI2CCLK
	I2C_CR1_DNF_Filter10 = 0xa
	// Digital filter enabled and filtering capability up to 11 tI2CCLK
	I2C_CR1_DNF_Filter11 = 0xb
	// Digital filter enabled and filtering capability up to 12 tI2CCLK
	I2C_CR1_DNF_Filter12 = 0xc
	// Digital filter enabled and filtering capability up to 13 tI2CCLK
	I2C_CR1_DNF_Filter13 = 0xd
	// Digital filter enabled and filtering capability up to 14 tI2CCLK
	I2C_CR1_DNF_Filter14 = 0xe
	// Digital filter enabled and filtering capability up to 15 tI2CCLK
	I2C_CR1_DNF_Filter15 = 0xf
	// Position of ANFOFF field.
	I2C_CR1_ANFOFF_Pos = 0xc
	// Bit mask of ANFOFF field.
	I2C_CR1_ANFOFF_Msk = 0x1000
	// Bit ANFOFF.
	I2C_CR1_ANFOFF = 0x1000
	// Analog noise filter enabled
	I2C_CR1_ANFOFF_Enabled = 0x0
	// Analog noise filter disabled
	I2C_CR1_ANFOFF_Disabled = 0x1
	// Position of TXDMAEN field.
	I2C_CR1_TXDMAEN_Pos = 0xe
	// Bit mask of TXDMAEN field.
	I2C_CR1_TXDMAEN_Msk = 0x4000
	// Bit TXDMAEN.
	I2C_CR1_TXDMAEN = 0x4000
	// DMA mode disabled for transmission
	I2C_CR1_TXDMAEN_Disabled = 0x0
	// DMA mode enabled for transmission
	I2C_CR1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	I2C_CR1_RXDMAEN_Pos = 0xf
	// Bit mask of RXDMAEN field.
	I2C_CR1_RXDMAEN_Msk = 0x8000
	// Bit RXDMAEN.
	I2C_CR1_RXDMAEN = 0x8000
	// DMA mode disabled for reception
	I2C_CR1_RXDMAEN_Disabled = 0x0
	// DMA mode enabled for reception
	I2C_CR1_RXDMAEN_Enabled = 0x1
	// Position of SBC field.
	I2C_CR1_SBC_Pos = 0x10
	// Bit mask of SBC field.
	I2C_CR1_SBC_Msk = 0x10000
	// Bit SBC.
	I2C_CR1_SBC = 0x10000
	// Slave byte control disabled
	I2C_CR1_SBC_Disabled = 0x0
	// Slave byte control enabled
	I2C_CR1_SBC_Enabled = 0x1
	// Position of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Pos = 0x11
	// Bit mask of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Msk = 0x20000
	// Bit NOSTRETCH.
	I2C_CR1_NOSTRETCH = 0x20000
	// Clock stretching enabled
	I2C_CR1_NOSTRETCH_Enabled = 0x0
	// Clock stretching disabled
	I2C_CR1_NOSTRETCH_Disabled = 0x1
	// Position of WUPEN field.
	I2C_CR1_WUPEN_Pos = 0x12
	// Bit mask of WUPEN field.
	I2C_CR1_WUPEN_Msk = 0x40000
	// Bit WUPEN.
	I2C_CR1_WUPEN = 0x40000
	// Wakeup from Stop mode disabled
	I2C_CR1_WUPEN_Disabled = 0x0
	// Wakeup from Stop mode enabled
	I2C_CR1_WUPEN_Enabled = 0x1
	// Position of GCEN field.
	I2C_CR1_GCEN_Pos = 0x13
	// Bit mask of GCEN field.
	I2C_CR1_GCEN_Msk = 0x80000
	// Bit GCEN.
	I2C_CR1_GCEN = 0x80000
	// General call disabled. Address 0b00000000 is NACKed
	I2C_CR1_GCEN_Disabled = 0x0
	// General call enabled. Address 0b00000000 is ACKed
	I2C_CR1_GCEN_Enabled = 0x1
	// Position of SMBHEN field.
	I2C_CR1_SMBHEN_Pos = 0x14
	// Bit mask of SMBHEN field.
	I2C_CR1_SMBHEN_Msk = 0x100000
	// Bit SMBHEN.
	I2C_CR1_SMBHEN = 0x100000
	// Host address disabled. Address 0b0001000x is NACKed
	I2C_CR1_SMBHEN_Disabled = 0x0
	// Host address enabled. Address 0b0001000x is ACKed
	I2C_CR1_SMBHEN_Enabled = 0x1
	// Position of SMBDEN field.
	I2C_CR1_SMBDEN_Pos = 0x15
	// Bit mask of SMBDEN field.
	I2C_CR1_SMBDEN_Msk = 0x200000
	// Bit SMBDEN.
	I2C_CR1_SMBDEN = 0x200000
	// Device default address disabled. Address 0b1100001x is NACKed
	I2C_CR1_SMBDEN_Disabled = 0x0
	// Device default address enabled. Address 0b1100001x is ACKed
	I2C_CR1_SMBDEN_Enabled = 0x1
	// Position of ALERTEN field.
	I2C_CR1_ALERTEN_Pos = 0x16
	// Bit mask of ALERTEN field.
	I2C_CR1_ALERTEN_Msk = 0x400000
	// Bit ALERTEN.
	I2C_CR1_ALERTEN = 0x400000
	// In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
	I2C_CR1_ALERTEN_Disabled = 0x0
	// In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
	I2C_CR1_ALERTEN_Enabled = 0x1
	// Position of PECEN field.
	I2C_CR1_PECEN_Pos = 0x17
	// Bit mask of PECEN field.
	I2C_CR1_PECEN_Msk = 0x800000
	// Bit PECEN.
	I2C_CR1_PECEN = 0x800000
	// PEC calculation disabled
	I2C_CR1_PECEN_Disabled = 0x0
	// PEC calculation enabled
	I2C_CR1_PECEN_Enabled = 0x1

	// CR2: I2C control register 2
	// Position of SADD field.
	I2C_CR2_SADD_Pos = 0x0
	// Bit mask of SADD field.
	I2C_CR2_SADD_Msk = 0x3ff
	// Position of RD_WRN field.
	I2C_CR2_RD_WRN_Pos = 0xa
	// Bit mask of RD_WRN field.
	I2C_CR2_RD_WRN_Msk = 0x400
	// Bit RD_WRN.
	I2C_CR2_RD_WRN = 0x400
	// Master requests a write transfer
	I2C_CR2_RD_WRN_Write = 0x0
	// Master requests a read transfer
	I2C_CR2_RD_WRN_Read = 0x1
	// Position of ADD10 field.
	I2C_CR2_ADD10_Pos = 0xb
	// Bit mask of ADD10 field.
	I2C_CR2_ADD10_Msk = 0x800
	// Bit ADD10.
	I2C_CR2_ADD10 = 0x800
	// The master operates in 7-bit addressing mode
	I2C_CR2_ADD10_Bit7 = 0x0
	// The master operates in 10-bit addressing mode
	I2C_CR2_ADD10_Bit10 = 0x1
	// Position of HEAD10R field.
	I2C_CR2_HEAD10R_Pos = 0xc
	// Bit mask of HEAD10R field.
	I2C_CR2_HEAD10R_Msk = 0x1000
	// Bit HEAD10R.
	I2C_CR2_HEAD10R = 0x1000
	// The master sends the complete 10 bit slave address read sequence
	I2C_CR2_HEAD10R_Complete = 0x0
	// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
	I2C_CR2_HEAD10R_Partial = 0x1
	// Position of START field.
	I2C_CR2_START_Pos = 0xd
	// Bit mask of START field.
	I2C_CR2_START_Msk = 0x2000
	// Bit START.
	I2C_CR2_START = 0x2000
	// No Start generation
	I2C_CR2_START_NoStart = 0x0
	// Restart/Start generation
	I2C_CR2_START_Start = 0x1
	// Position of STOP field.
	I2C_CR2_STOP_Pos = 0xe
	// Bit mask of STOP field.
	I2C_CR2_STOP_Msk = 0x4000
	// Bit STOP.
	I2C_CR2_STOP = 0x4000
	// No Stop generation
	I2C_CR2_STOP_NoStop = 0x0
	// Stop generation after current byte transfer
	I2C_CR2_STOP_Stop = 0x1
	// Position of NACK field.
	I2C_CR2_NACK_Pos = 0xf
	// Bit mask of NACK field.
	I2C_CR2_NACK_Msk = 0x8000
	// Bit NACK.
	I2C_CR2_NACK = 0x8000
	// an ACK is sent after current received byte
	I2C_CR2_NACK_Ack = 0x0
	// a NACK is sent after current received byte
	I2C_CR2_NACK_Nack = 0x1
	// Position of NBYTES field.
	I2C_CR2_NBYTES_Pos = 0x10
	// Bit mask of NBYTES field.
	I2C_CR2_NBYTES_Msk = 0xff0000
	// Position of RELOAD field.
	I2C_CR2_RELOAD_Pos = 0x18
	// Bit mask of RELOAD field.
	I2C_CR2_RELOAD_Msk = 0x1000000
	// Bit RELOAD.
	I2C_CR2_RELOAD = 0x1000000
	// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
	I2C_CR2_RELOAD_Completed = 0x0
	// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
	I2C_CR2_RELOAD_NotCompleted = 0x1
	// Position of AUTOEND field.
	I2C_CR2_AUTOEND_Pos = 0x19
	// Bit mask of AUTOEND field.
	I2C_CR2_AUTOEND_Msk = 0x2000000
	// Bit AUTOEND.
	I2C_CR2_AUTOEND = 0x2000000
	// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
	I2C_CR2_AUTOEND_Software = 0x0
	// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
	I2C_CR2_AUTOEND_Automatic = 0x1
	// Position of PECBYTE field.
	I2C_CR2_PECBYTE_Pos = 0x1a
	// Bit mask of PECBYTE field.
	I2C_CR2_PECBYTE_Msk = 0x4000000
	// Bit PECBYTE.
	I2C_CR2_PECBYTE = 0x4000000
	// No PEC transfer
	I2C_CR2_PECBYTE_NoPec = 0x0
	// PEC transmission/reception is requested
	I2C_CR2_PECBYTE_Pec = 0x1

	// OAR1: I2C own address 1 register
	// Position of OA1 field.
	I2C_OAR1_OA1_Pos = 0x0
	// Bit mask of OA1 field.
	I2C_OAR1_OA1_Msk = 0x3ff
	// Position of OA1MODE field.
	I2C_OAR1_OA1MODE_Pos = 0xa
	// Bit mask of OA1MODE field.
	I2C_OAR1_OA1MODE_Msk = 0x400
	// Bit OA1MODE.
	I2C_OAR1_OA1MODE = 0x400
	// Own address 1 is a 7-bit address
	I2C_OAR1_OA1MODE_Bit7 = 0x0
	// Own address 1 is a 10-bit address
	I2C_OAR1_OA1MODE_Bit10 = 0x1
	// Position of OA1EN field.
	I2C_OAR1_OA1EN_Pos = 0xf
	// Bit mask of OA1EN field.
	I2C_OAR1_OA1EN_Msk = 0x8000
	// Bit OA1EN.
	I2C_OAR1_OA1EN = 0x8000
	// Own address 1 disabled. The received slave address OA1 is NACKed
	I2C_OAR1_OA1EN_Disabled = 0x0
	// Own address 1 enabled. The received slave address OA1 is ACKed
	I2C_OAR1_OA1EN_Enabled = 0x1

	// OAR2: I2C own address 2 register
	// Position of OA2 field.
	I2C_OAR2_OA2_Pos = 0x1
	// Bit mask of OA2 field.
	I2C_OAR2_OA2_Msk = 0xfe
	// Position of OA2MSK field.
	I2C_OAR2_OA2MSK_Pos = 0x8
	// Bit mask of OA2MSK field.
	I2C_OAR2_OA2MSK_Msk = 0x700
	// No mask
	I2C_OAR2_OA2MSK_NoMask = 0x0
	// OA2[1] is masked and don’t care. Only OA2[7:2] are compared
	I2C_OAR2_OA2MSK_Mask1 = 0x1
	// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
	I2C_OAR2_OA2MSK_Mask2 = 0x2
	// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
	I2C_OAR2_OA2MSK_Mask3 = 0x3
	// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
	I2C_OAR2_OA2MSK_Mask4 = 0x4
	// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
	I2C_OAR2_OA2MSK_Mask5 = 0x5
	// OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
	I2C_OAR2_OA2MSK_Mask6 = 0x6
	// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
	I2C_OAR2_OA2MSK_Mask7 = 0x7
	// Position of OA2EN field.
	I2C_OAR2_OA2EN_Pos = 0xf
	// Bit mask of OA2EN field.
	I2C_OAR2_OA2EN_Msk = 0x8000
	// Bit OA2EN.
	I2C_OAR2_OA2EN = 0x8000
	// Own address 2 disabled. The received slave address OA2 is NACKed
	I2C_OAR2_OA2EN_Disabled = 0x0
	// Own address 2 enabled. The received slave address OA2 is ACKed
	I2C_OAR2_OA2EN_Enabled = 0x1

	// TIMINGR: I2C timing register
	// Position of SCLL field.
	I2C_TIMINGR_SCLL_Pos = 0x0
	// Bit mask of SCLL field.
	I2C_TIMINGR_SCLL_Msk = 0xff
	// Position of SCLH field.
	I2C_TIMINGR_SCLH_Pos = 0x8
	// Bit mask of SCLH field.
	I2C_TIMINGR_SCLH_Msk = 0xff00
	// Position of SDADEL field.
	I2C_TIMINGR_SDADEL_Pos = 0x10
	// Bit mask of SDADEL field.
	I2C_TIMINGR_SDADEL_Msk = 0xf0000
	// Position of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Pos = 0x14
	// Bit mask of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Msk = 0xf00000
	// Position of PRESC field.
	I2C_TIMINGR_PRESC_Pos = 0x1c
	// Bit mask of PRESC field.
	I2C_TIMINGR_PRESC_Msk = 0xf0000000

	// TIMEOUTR: I2C timeout register
	// Position of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0
	// Bit mask of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff
	// Position of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Pos = 0xc
	// Bit mask of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Msk = 0x1000
	// Bit TIDLE.
	I2C_TIMEOUTR_TIDLE = 0x1000
	// TIMEOUTA is used to detect SCL low timeout
	I2C_TIMEOUTR_TIDLE_Disabled = 0x0
	// TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
	I2C_TIMEOUTR_TIDLE_Enabled = 0x1
	// Position of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf
	// Bit mask of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000
	// Bit TIMOUTEN.
	I2C_TIMEOUTR_TIMOUTEN = 0x8000
	// SCL timeout detection is disabled
	I2C_TIMEOUTR_TIMOUTEN_Disabled = 0x0
	// SCL timeout detection is enabled
	I2C_TIMEOUTR_TIMOUTEN_Enabled = 0x1
	// Position of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10
	// Bit mask of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000
	// Position of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Pos = 0x1f
	// Bit mask of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Msk = 0x80000000
	// Bit TEXTEN.
	I2C_TIMEOUTR_TEXTEN = 0x80000000
	// Extended clock timeout detection is disabled
	I2C_TIMEOUTR_TEXTEN_Disabled = 0x0
	// Extended clock timeout detection is enabled
	I2C_TIMEOUTR_TEXTEN_Enabled = 0x1

	// ISR: I2C interrupt and status register
	// Position of TXE field.
	I2C_ISR_TXE_Pos = 0x0
	// Bit mask of TXE field.
	I2C_ISR_TXE_Msk = 0x1
	// Bit TXE.
	I2C_ISR_TXE = 0x1
	// TXDR register not empty
	I2C_ISR_TXE_NotEmpty = 0x0
	// TXDR register empty
	I2C_ISR_TXE_Empty = 0x1
	// Flush the transmit data register
	I2C_ISR_TXE_Flush = 0x1
	// Position of TXIS field.
	I2C_ISR_TXIS_Pos = 0x1
	// Bit mask of TXIS field.
	I2C_ISR_TXIS_Msk = 0x2
	// Bit TXIS.
	I2C_ISR_TXIS = 0x2
	// The TXDR register is not empty
	I2C_ISR_TXIS_NotEmpty = 0x0
	// The TXDR register is empty and the data to be transmitted must be written in the TXDR register
	I2C_ISR_TXIS_Empty = 0x1
	// Generate a TXIS event
	I2C_ISR_TXIS_Trigger = 0x1
	// Position of RXNE field.
	I2C_ISR_RXNE_Pos = 0x2
	// Bit mask of RXNE field.
	I2C_ISR_RXNE_Msk = 0x4
	// Bit RXNE.
	I2C_ISR_RXNE = 0x4
	// The RXDR register is empty
	I2C_ISR_RXNE_Empty = 0x0
	// Received data is copied into the RXDR register, and is ready to be read
	I2C_ISR_RXNE_NotEmpty = 0x1
	// Position of ADDR field.
	I2C_ISR_ADDR_Pos = 0x3
	// Bit mask of ADDR field.
	I2C_ISR_ADDR_Msk = 0x8
	// Bit ADDR.
	I2C_ISR_ADDR = 0x8
	// Adress mismatched or not received
	I2C_ISR_ADDR_NotMatch = 0x0
	// Received slave address matched with one of the enabled slave addresses
	I2C_ISR_ADDR_Match = 0x1
	// Position of NACKF field.
	I2C_ISR_NACKF_Pos = 0x4
	// Bit mask of NACKF field.
	I2C_ISR_NACKF_Msk = 0x10
	// Bit NACKF.
	I2C_ISR_NACKF = 0x10
	// No NACK has been received
	I2C_ISR_NACKF_NoNack = 0x0
	// NACK has been received
	I2C_ISR_NACKF_Nack = 0x1
	// Position of STOPF field.
	I2C_ISR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	I2C_ISR_STOPF_Msk = 0x20
	// Bit STOPF.
	I2C_ISR_STOPF = 0x20
	// No Stop condition detected
	I2C_ISR_STOPF_NoStop = 0x0
	// Stop condition detected
	I2C_ISR_STOPF_Stop = 0x1
	// Position of TC field.
	I2C_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	I2C_ISR_TC_Msk = 0x40
	// Bit TC.
	I2C_ISR_TC = 0x40
	// Transfer is not complete
	I2C_ISR_TC_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TC_Complete = 0x1
	// Position of TCR field.
	I2C_ISR_TCR_Pos = 0x7
	// Bit mask of TCR field.
	I2C_ISR_TCR_Msk = 0x80
	// Bit TCR.
	I2C_ISR_TCR = 0x80
	// Transfer is not complete
	I2C_ISR_TCR_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TCR_Complete = 0x1
	// Position of BERR field.
	I2C_ISR_BERR_Pos = 0x8
	// Bit mask of BERR field.
	I2C_ISR_BERR_Msk = 0x100
	// Bit BERR.
	I2C_ISR_BERR = 0x100
	// No bus error
	I2C_ISR_BERR_NoError = 0x0
	// Misplaced Start and Stop condition is detected
	I2C_ISR_BERR_Error = 0x1
	// Position of ARLO field.
	I2C_ISR_ARLO_Pos = 0x9
	// Bit mask of ARLO field.
	I2C_ISR_ARLO_Msk = 0x200
	// Bit ARLO.
	I2C_ISR_ARLO = 0x200
	// No arbitration lost
	I2C_ISR_ARLO_NotLost = 0x0
	// Arbitration lost
	I2C_ISR_ARLO_Lost = 0x1
	// Position of OVR field.
	I2C_ISR_OVR_Pos = 0xa
	// Bit mask of OVR field.
	I2C_ISR_OVR_Msk = 0x400
	// Bit OVR.
	I2C_ISR_OVR = 0x400
	// No overrun/underrun error occurs
	I2C_ISR_OVR_NoOverrun = 0x0
	// slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
	I2C_ISR_OVR_Overrun = 0x1
	// Position of PECERR field.
	I2C_ISR_PECERR_Pos = 0xb
	// Bit mask of PECERR field.
	I2C_ISR_PECERR_Msk = 0x800
	// Bit PECERR.
	I2C_ISR_PECERR = 0x800
	// Received PEC does match with PEC register
	I2C_ISR_PECERR_Match = 0x0
	// Received PEC does not match with PEC register
	I2C_ISR_PECERR_NoMatch = 0x1
	// Position of TIMEOUT field.
	I2C_ISR_TIMEOUT_Pos = 0xc
	// Bit mask of TIMEOUT field.
	I2C_ISR_TIMEOUT_Msk = 0x1000
	// Bit TIMEOUT.
	I2C_ISR_TIMEOUT = 0x1000
	// No timeout occured
	I2C_ISR_TIMEOUT_NoTimeout = 0x0
	// Timeout occured
	I2C_ISR_TIMEOUT_Timeout = 0x1
	// Position of ALERT field.
	I2C_ISR_ALERT_Pos = 0xd
	// Bit mask of ALERT field.
	I2C_ISR_ALERT_Msk = 0x2000
	// Bit ALERT.
	I2C_ISR_ALERT = 0x2000
	// SMBA alert is not detected
	I2C_ISR_ALERT_NoAlert = 0x0
	// SMBA alert event is detected on SMBA pin
	I2C_ISR_ALERT_Alert = 0x1
	// Position of BUSY field.
	I2C_ISR_BUSY_Pos = 0xf
	// Bit mask of BUSY field.
	I2C_ISR_BUSY_Msk = 0x8000
	// Bit BUSY.
	I2C_ISR_BUSY = 0x8000
	// No communication is in progress on the bus
	I2C_ISR_BUSY_NotBusy = 0x0
	// A communication is in progress on the bus
	I2C_ISR_BUSY_Busy = 0x1
	// Position of DIR field.
	I2C_ISR_DIR_Pos = 0x10
	// Bit mask of DIR field.
	I2C_ISR_DIR_Msk = 0x10000
	// Bit DIR.
	I2C_ISR_DIR = 0x10000
	// Write transfer, slave enters receiver mode
	I2C_ISR_DIR_Write = 0x0
	// Read transfer, slave enters transmitter mode
	I2C_ISR_DIR_Read = 0x1
	// Position of ADDCODE field.
	I2C_ISR_ADDCODE_Pos = 0x11
	// Bit mask of ADDCODE field.
	I2C_ISR_ADDCODE_Msk = 0xfe0000

	// ICR: I2C interrupt clear register
	// Position of ADDRCF field.
	I2C_ICR_ADDRCF_Pos = 0x3
	// Bit mask of ADDRCF field.
	I2C_ICR_ADDRCF_Msk = 0x8
	// Bit ADDRCF.
	I2C_ICR_ADDRCF = 0x8
	// Clears the ADDR flag in ISR register
	I2C_ICR_ADDRCF_Clear = 0x1
	// Position of NACKCF field.
	I2C_ICR_NACKCF_Pos = 0x4
	// Bit mask of NACKCF field.
	I2C_ICR_NACKCF_Msk = 0x10
	// Bit NACKCF.
	I2C_ICR_NACKCF = 0x10
	// Clears the NACK flag in ISR register
	I2C_ICR_NACKCF_Clear = 0x1
	// Position of STOPCF field.
	I2C_ICR_STOPCF_Pos = 0x5
	// Bit mask of STOPCF field.
	I2C_ICR_STOPCF_Msk = 0x20
	// Bit STOPCF.
	I2C_ICR_STOPCF = 0x20
	// Clears the STOP flag in ISR register
	I2C_ICR_STOPCF_Clear = 0x1
	// Position of BERRCF field.
	I2C_ICR_BERRCF_Pos = 0x8
	// Bit mask of BERRCF field.
	I2C_ICR_BERRCF_Msk = 0x100
	// Bit BERRCF.
	I2C_ICR_BERRCF = 0x100
	// Clears the BERR flag in ISR register
	I2C_ICR_BERRCF_Clear = 0x1
	// Position of ARLOCF field.
	I2C_ICR_ARLOCF_Pos = 0x9
	// Bit mask of ARLOCF field.
	I2C_ICR_ARLOCF_Msk = 0x200
	// Bit ARLOCF.
	I2C_ICR_ARLOCF = 0x200
	// Clears the ARLO flag in ISR register
	I2C_ICR_ARLOCF_Clear = 0x1
	// Position of OVRCF field.
	I2C_ICR_OVRCF_Pos = 0xa
	// Bit mask of OVRCF field.
	I2C_ICR_OVRCF_Msk = 0x400
	// Bit OVRCF.
	I2C_ICR_OVRCF = 0x400
	// Clears the OVR flag in ISR register
	I2C_ICR_OVRCF_Clear = 0x1
	// Position of PECCF field.
	I2C_ICR_PECCF_Pos = 0xb
	// Bit mask of PECCF field.
	I2C_ICR_PECCF_Msk = 0x800
	// Bit PECCF.
	I2C_ICR_PECCF = 0x800
	// Clears the PEC flag in ISR register
	I2C_ICR_PECCF_Clear = 0x1
	// Position of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Pos = 0xc
	// Bit mask of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Msk = 0x1000
	// Bit TIMOUTCF.
	I2C_ICR_TIMOUTCF = 0x1000
	// Clears the TIMOUT flag in ISR register
	I2C_ICR_TIMOUTCF_Clear = 0x1
	// Position of ALERTCF field.
	I2C_ICR_ALERTCF_Pos = 0xd
	// Bit mask of ALERTCF field.
	I2C_ICR_ALERTCF_Msk = 0x2000
	// Bit ALERTCF.
	I2C_ICR_ALERTCF = 0x2000
	// Clears the ALERT flag in ISR register
	I2C_ICR_ALERTCF_Clear = 0x1

	// PECR: I2C PEC register
	// Position of PEC field.
	I2C_PECR_PEC_Pos = 0x0
	// Bit mask of PEC field.
	I2C_PECR_PEC_Msk = 0xff

	// RXDR: I2C receive data register
	// Position of RXDATA field.
	I2C_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	I2C_RXDR_RXDATA_Msk = 0xff

	// TXDR: I2C transmit data register
	// Position of TXDATA field.
	I2C_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	I2C_TXDR_TXDATA_Msk = 0xff
)

// Constants for RCC
const (
	// CR: CR register
	// Position of LSION field.
	RCC_CR_LSION_Pos = 0x2
	// Bit mask of LSION field.
	RCC_CR_LSION_Msk = 0x4
	// Bit LSION.
	RCC_CR_LSION = 0x4
	// Position of LSIRDY field.
	RCC_CR_LSIRDY_Pos = 0x3
	// Bit mask of LSIRDY field.
	RCC_CR_LSIRDY_Msk = 0x8
	// Bit LSIRDY.
	RCC_CR_LSIRDY = 0x8
	// Position of LSEON field.
	RCC_CR_LSEON_Pos = 0x4
	// Bit mask of LSEON field.
	RCC_CR_LSEON_Msk = 0x10
	// Bit LSEON.
	RCC_CR_LSEON = 0x10
	// Position of LSERDY field.
	RCC_CR_LSERDY_Pos = 0x5
	// Bit mask of LSERDY field.
	RCC_CR_LSERDY_Msk = 0x20
	// Bit LSERDY.
	RCC_CR_LSERDY = 0x20
	// Position of LSEBYP field.
	RCC_CR_LSEBYP_Pos = 0x6
	// Bit mask of LSEBYP field.
	RCC_CR_LSEBYP_Msk = 0x40
	// Bit LSEBYP.
	RCC_CR_LSEBYP = 0x40
	// Position of LOCKDET_NSTOP field.
	RCC_CR_LOCKDET_NSTOP_Pos = 0x7
	// Bit mask of LOCKDET_NSTOP field.
	RCC_CR_LOCKDET_NSTOP_Msk = 0x380
	// Position of HSIRDY field.
	RCC_CR_HSIRDY_Pos = 0xa
	// Bit mask of HSIRDY field.
	RCC_CR_HSIRDY_Msk = 0x400
	// Bit HSIRDY.
	RCC_CR_HSIRDY = 0x400
	// Position of HSEPLLBUFON field.
	RCC_CR_HSEPLLBUFON_Pos = 0xc
	// Bit mask of HSEPLLBUFON field.
	RCC_CR_HSEPLLBUFON_Msk = 0x1000
	// Bit HSEPLLBUFON.
	RCC_CR_HSEPLLBUFON = 0x1000
	// Position of HSIPLLON field.
	RCC_CR_HSIPLLON_Pos = 0xd
	// Bit mask of HSIPLLON field.
	RCC_CR_HSIPLLON_Msk = 0x2000
	// Bit HSIPLLON.
	RCC_CR_HSIPLLON = 0x2000
	// Position of HSIPLLRDY field.
	RCC_CR_HSIPLLRDY_Pos = 0xe
	// Bit mask of HSIPLLRDY field.
	RCC_CR_HSIPLLRDY_Msk = 0x4000
	// Bit HSIPLLRDY.
	RCC_CR_HSIPLLRDY = 0x4000
	// Position of FMRAT field.
	RCC_CR_FMRAT_Pos = 0xf
	// Bit mask of FMRAT field.
	RCC_CR_FMRAT_Msk = 0x8000
	// Bit FMRAT.
	RCC_CR_FMRAT = 0x8000
	// Position of HSEON field.
	RCC_CR_HSEON_Pos = 0x10
	// Bit mask of HSEON field.
	RCC_CR_HSEON_Msk = 0x10000
	// Bit HSEON.
	RCC_CR_HSEON = 0x10000
	// Position of HSERDY field.
	RCC_CR_HSERDY_Pos = 0x11
	// Bit mask of HSERDY field.
	RCC_CR_HSERDY_Msk = 0x20000
	// Bit HSERDY.
	RCC_CR_HSERDY = 0x20000

	// CFGR: CFGR register
	// Position of SMPSINV field.
	RCC_CFGR_SMPSINV_Pos = 0x0
	// Bit mask of SMPSINV field.
	RCC_CFGR_SMPSINV_Msk = 0x1
	// Bit SMPSINV.
	RCC_CFGR_SMPSINV = 0x1
	// Position of HSESEL field.
	RCC_CFGR_HSESEL_Pos = 0x1
	// Bit mask of HSESEL field.
	RCC_CFGR_HSESEL_Msk = 0x2
	// Bit HSESEL.
	RCC_CFGR_HSESEL = 0x2
	// Position of STOPHSI field.
	RCC_CFGR_STOPHSI_Pos = 0x2
	// Bit mask of STOPHSI field.
	RCC_CFGR_STOPHSI_Msk = 0x4
	// Bit STOPHSI.
	RCC_CFGR_STOPHSI = 0x4
	// Position of HSESEL_STATUS field.
	RCC_CFGR_HSESEL_STATUS_Pos = 0x3
	// Bit mask of HSESEL_STATUS field.
	RCC_CFGR_HSESEL_STATUS_Msk = 0x8
	// Bit HSESEL_STATUS.
	RCC_CFGR_HSESEL_STATUS = 0x8
	// Position of CLKSYSDIV field.
	RCC_CFGR_CLKSYSDIV_Pos = 0x5
	// Bit mask of CLKSYSDIV field.
	RCC_CFGR_CLKSYSDIV_Msk = 0xe0
	// Position of CLKSYSDIV_STATUS field.
	RCC_CFGR_CLKSYSDIV_STATUS_Pos = 0x8
	// Bit mask of CLKSYSDIV_STATUS field.
	RCC_CFGR_CLKSYSDIV_STATUS_Msk = 0x700
	// Position of SMPSDIV field.
	RCC_CFGR_SMPSDIV_Pos = 0xc
	// Bit mask of SMPSDIV field.
	RCC_CFGR_SMPSDIV_Msk = 0x1000
	// Bit SMPSDIV.
	RCC_CFGR_SMPSDIV = 0x1000
	// Position of LPUCLKSEL field.
	RCC_CFGR_LPUCLKSEL_Pos = 0xd
	// Bit mask of LPUCLKSEL field.
	RCC_CFGR_LPUCLKSEL_Msk = 0x2000
	// Bit LPUCLKSEL.
	RCC_CFGR_LPUCLKSEL = 0x2000
	// Position of CLKSLOWSEL field.
	RCC_CFGR_CLKSLOWSEL_Pos = 0xf
	// Bit mask of CLKSLOWSEL field.
	RCC_CFGR_CLKSLOWSEL_Msk = 0x18000
	// Position of IOBOOSTEN field.
	RCC_CFGR_IOBOOSTEN_Pos = 0x11
	// Bit mask of IOBOOSTEN field.
	RCC_CFGR_IOBOOSTEN_Msk = 0x20000
	// Bit IOBOOSTEN.
	RCC_CFGR_IOBOOSTEN = 0x20000
	// Position of IOBOOSTCLKEXTEN field.
	RCC_CFGR_IOBOOSTCLKEXTEN_Pos = 0x12
	// Bit mask of IOBOOSTCLKEXTEN field.
	RCC_CFGR_IOBOOSTCLKEXTEN_Msk = 0x40000
	// Bit IOBOOSTCLKEXTEN.
	RCC_CFGR_IOBOOSTCLKEXTEN = 0x40000
	// Position of LCOEN field.
	RCC_CFGR_LCOEN_Pos = 0x13
	// Bit mask of LCOEN field.
	RCC_CFGR_LCOEN_Msk = 0x80000
	// Bit LCOEN.
	RCC_CFGR_LCOEN = 0x80000
	// Position of SPI3I2SCLKSEL field.
	RCC_CFGR_SPI3I2SCLKSEL_Pos = 0x16
	// Bit mask of SPI3I2SCLKSEL field.
	RCC_CFGR_SPI3I2SCLKSEL_Msk = 0xc00000
	// Position of LCOSEL field.
	RCC_CFGR_LCOSEL_Pos = 0x18
	// Bit mask of LCOSEL field.
	RCC_CFGR_LCOSEL_Msk = 0x3000000
	// Position of MCOSEL field.
	RCC_CFGR_MCOSEL_Pos = 0x1a
	// Bit mask of MCOSEL field.
	RCC_CFGR_MCOSEL_Msk = 0x1c000000
	// Position of CCOPRE field.
	RCC_CFGR_CCOPRE_Pos = 0x1d
	// Bit mask of CCOPRE field.
	RCC_CFGR_CCOPRE_Msk = 0xe0000000

	// CIER: CIER register
	// Position of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Pos = 0x0
	// Bit mask of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Msk = 0x1
	// Bit LSIRDYIE.
	RCC_CIER_LSIRDYIE = 0x1
	// Position of LSERDYIE field.
	RCC_CIER_LSERDYIE_Pos = 0x1
	// Bit mask of LSERDYIE field.
	RCC_CIER_LSERDYIE_Msk = 0x2
	// Bit LSERDYIE.
	RCC_CIER_LSERDYIE = 0x2
	// Position of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Pos = 0x3
	// Bit mask of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Msk = 0x8
	// Bit HSIRDYIE.
	RCC_CIER_HSIRDYIE = 0x8
	// Position of HSERDYIE field.
	RCC_CIER_HSERDYIE_Pos = 0x4
	// Bit mask of HSERDYIE field.
	RCC_CIER_HSERDYIE_Msk = 0x10
	// Bit HSERDYIE.
	RCC_CIER_HSERDYIE = 0x10
	// Position of HSIPLLRDYIE field.
	RCC_CIER_HSIPLLRDYIE_Pos = 0x5
	// Bit mask of HSIPLLRDYIE field.
	RCC_CIER_HSIPLLRDYIE_Msk = 0x20
	// Bit HSIPLLRDYIE.
	RCC_CIER_HSIPLLRDYIE = 0x20
	// Position of HSIPLLUNLOCKDETIE field.
	RCC_CIER_HSIPLLUNLOCKDETIE_Pos = 0x6
	// Bit mask of HSIPLLUNLOCKDETIE field.
	RCC_CIER_HSIPLLUNLOCKDETIE_Msk = 0x40
	// Bit HSIPLLUNLOCKDETIE.
	RCC_CIER_HSIPLLUNLOCKDETIE = 0x40
	// Position of RTCRSTIE field.
	RCC_CIER_RTCRSTIE_Pos = 0x7
	// Bit mask of RTCRSTIE field.
	RCC_CIER_RTCRSTIE_Msk = 0x80
	// Bit RTCRSTIE.
	RCC_CIER_RTCRSTIE = 0x80
	// Position of WDGRSTIE field.
	RCC_CIER_WDGRSTIE_Pos = 0x8
	// Bit mask of WDGRSTIE field.
	RCC_CIER_WDGRSTIE_Msk = 0x100
	// Bit WDGRSTIE.
	RCC_CIER_WDGRSTIE = 0x100
	// Position of LPURSTIE field.
	RCC_CIER_LPURSTIE_Pos = 0x9
	// Bit mask of LPURSTIE field.
	RCC_CIER_LPURSTIE_Msk = 0x200
	// Bit LPURSTIE.
	RCC_CIER_LPURSTIE = 0x200

	// CIFR: CIFR register
	// Position of LSIRDYIF field.
	RCC_CIFR_LSIRDYIF_Pos = 0x0
	// Bit mask of LSIRDYIF field.
	RCC_CIFR_LSIRDYIF_Msk = 0x1
	// Bit LSIRDYIF.
	RCC_CIFR_LSIRDYIF = 0x1
	// Position of LSERDYIF field.
	RCC_CIFR_LSERDYIF_Pos = 0x1
	// Bit mask of LSERDYIF field.
	RCC_CIFR_LSERDYIF_Msk = 0x2
	// Bit LSERDYIF.
	RCC_CIFR_LSERDYIF = 0x2
	// Position of HSIRDYIF field.
	RCC_CIFR_HSIRDYIF_Pos = 0x3
	// Bit mask of HSIRDYIF field.
	RCC_CIFR_HSIRDYIF_Msk = 0x8
	// Bit HSIRDYIF.
	RCC_CIFR_HSIRDYIF = 0x8
	// Position of HSERDYIF field.
	RCC_CIFR_HSERDYIF_Pos = 0x4
	// Bit mask of HSERDYIF field.
	RCC_CIFR_HSERDYIF_Msk = 0x10
	// Bit HSERDYIF.
	RCC_CIFR_HSERDYIF = 0x10
	// Position of HSIPLLRDYIF field.
	RCC_CIFR_HSIPLLRDYIF_Pos = 0x5
	// Bit mask of HSIPLLRDYIF field.
	RCC_CIFR_HSIPLLRDYIF_Msk = 0x20
	// Bit HSIPLLRDYIF.
	RCC_CIFR_HSIPLLRDYIF = 0x20
	// Position of HSIPLLUNLOCKDETIF field.
	RCC_CIFR_HSIPLLUNLOCKDETIF_Pos = 0x6
	// Bit mask of HSIPLLUNLOCKDETIF field.
	RCC_CIFR_HSIPLLUNLOCKDETIF_Msk = 0x40
	// Bit HSIPLLUNLOCKDETIF.
	RCC_CIFR_HSIPLLUNLOCKDETIF = 0x40
	// Position of RTCRSTIF field.
	RCC_CIFR_RTCRSTIF_Pos = 0x7
	// Bit mask of RTCRSTIF field.
	RCC_CIFR_RTCRSTIF_Msk = 0x80
	// Bit RTCRSTIF.
	RCC_CIFR_RTCRSTIF = 0x80
	// Position of WDGRSTIF field.
	RCC_CIFR_WDGRSTIF_Pos = 0x8
	// Bit mask of WDGRSTIF field.
	RCC_CIFR_WDGRSTIF_Msk = 0x100
	// Bit WDGRSTIF.
	RCC_CIFR_WDGRSTIF = 0x100
	// Position of LPURSTF field.
	RCC_CIFR_LPURSTF_Pos = 0x9
	// Bit mask of LPURSTF field.
	RCC_CIFR_LPURSTF_Msk = 0x200
	// Bit LPURSTF.
	RCC_CIFR_LPURSTF = 0x200

	// CSCMDR: CSCMDR register
	// Position of REQUEST field.
	RCC_CSCMDR_REQUEST_Pos = 0x0
	// Bit mask of REQUEST field.
	RCC_CSCMDR_REQUEST_Msk = 0x1
	// Bit REQUEST.
	RCC_CSCMDR_REQUEST = 0x1
	// Position of CLKSYSDIV_REQ field.
	RCC_CSCMDR_CLKSYSDIV_REQ_Pos = 0x1
	// Bit mask of CLKSYSDIV_REQ field.
	RCC_CSCMDR_CLKSYSDIV_REQ_Msk = 0xe
	// Position of STATUS field.
	RCC_CSCMDR_STATUS_Pos = 0x4
	// Bit mask of STATUS field.
	RCC_CSCMDR_STATUS_Msk = 0x30
	// Position of EOFSEQ_IE field.
	RCC_CSCMDR_EOFSEQ_IE_Pos = 0x6
	// Bit mask of EOFSEQ_IE field.
	RCC_CSCMDR_EOFSEQ_IE_Msk = 0x40
	// Bit EOFSEQ_IE.
	RCC_CSCMDR_EOFSEQ_IE = 0x40
	// Position of EOFSEQ_IRQ field.
	RCC_CSCMDR_EOFSEQ_IRQ_Pos = 0x7
	// Bit mask of EOFSEQ_IRQ field.
	RCC_CSCMDR_EOFSEQ_IRQ_Msk = 0x80
	// Bit EOFSEQ_IRQ.
	RCC_CSCMDR_EOFSEQ_IRQ = 0x80

	// AHBRSTR: AHBRSTR register
	// Position of DMARST field.
	RCC_AHBRSTR_DMARST_Pos = 0x0
	// Bit mask of DMARST field.
	RCC_AHBRSTR_DMARST_Msk = 0x1
	// Bit DMARST.
	RCC_AHBRSTR_DMARST = 0x1
	// Position of GPIOARST field.
	RCC_AHBRSTR_GPIOARST_Pos = 0x2
	// Bit mask of GPIOARST field.
	RCC_AHBRSTR_GPIOARST_Msk = 0x4
	// Bit GPIOARST.
	RCC_AHBRSTR_GPIOARST = 0x4
	// Position of GPIOBRST field.
	RCC_AHBRSTR_GPIOBRST_Pos = 0x3
	// Bit mask of GPIOBRST field.
	RCC_AHBRSTR_GPIOBRST_Msk = 0x8
	// Bit GPIOBRST.
	RCC_AHBRSTR_GPIOBRST = 0x8
	// Position of CRCRST field.
	RCC_AHBRSTR_CRCRST_Pos = 0xc
	// Bit mask of CRCRST field.
	RCC_AHBRSTR_CRCRST_Msk = 0x1000
	// Bit CRCRST.
	RCC_AHBRSTR_CRCRST = 0x1000
	// Position of PKARST field.
	RCC_AHBRSTR_PKARST_Pos = 0x10
	// Bit mask of PKARST field.
	RCC_AHBRSTR_PKARST_Msk = 0x10000
	// Bit PKARST.
	RCC_AHBRSTR_PKARST = 0x10000
	// Position of RNGRST field.
	RCC_AHBRSTR_RNGRST_Pos = 0x12
	// Bit mask of RNGRST field.
	RCC_AHBRSTR_RNGRST_Msk = 0x40000
	// Bit RNGRST.
	RCC_AHBRSTR_RNGRST = 0x40000

	// APB0RSTR: APB0RSTR register
	// Position of TIM1RST field.
	RCC_APB0RSTR_TIM1RST_Pos = 0x0
	// Bit mask of TIM1RST field.
	RCC_APB0RSTR_TIM1RST_Msk = 0x1
	// Bit TIM1RST.
	RCC_APB0RSTR_TIM1RST = 0x1
	// Position of TIM16RST field.
	RCC_APB0RSTR_TIM16RST_Pos = 0x1
	// Bit mask of TIM16RST field.
	RCC_APB0RSTR_TIM16RST_Msk = 0x2
	// Bit TIM16RST.
	RCC_APB0RSTR_TIM16RST = 0x2
	// Position of TIM17RST field.
	RCC_APB0RSTR_TIM17RST_Pos = 0x2
	// Bit mask of TIM17RST field.
	RCC_APB0RSTR_TIM17RST_Msk = 0x4
	// Bit TIM17RST.
	RCC_APB0RSTR_TIM17RST = 0x4
	// Position of SYSCFGRST field.
	RCC_APB0RSTR_SYSCFGRST_Pos = 0x8
	// Bit mask of SYSCFGRST field.
	RCC_APB0RSTR_SYSCFGRST_Msk = 0x100
	// Bit SYSCFGRST.
	RCC_APB0RSTR_SYSCFGRST = 0x100
	// Position of RTCRST field.
	RCC_APB0RSTR_RTCRST_Pos = 0xc
	// Bit mask of RTCRST field.
	RCC_APB0RSTR_RTCRST_Msk = 0x1000
	// Bit RTCRST.
	RCC_APB0RSTR_RTCRST = 0x1000
	// Position of WDRST field.
	RCC_APB0RSTR_WDRST_Pos = 0xe
	// Bit mask of WDRST field.
	RCC_APB0RSTR_WDRST_Msk = 0x4000
	// Bit WDRST.
	RCC_APB0RSTR_WDRST = 0x4000

	// APB1RSTR: APB1RSTR register
	// Position of AUXADCRST field.
	RCC_APB1RSTR_AUXADCRST_Pos = 0x4
	// Bit mask of AUXADCRST field.
	RCC_APB1RSTR_AUXADCRST_Msk = 0x10
	// Bit AUXADCRST.
	RCC_APB1RSTR_AUXADCRST = 0x10
	// Position of LPUARTRST field.
	RCC_APB1RSTR_LPUARTRST_Pos = 0x8
	// Bit mask of LPUARTRST field.
	RCC_APB1RSTR_LPUARTRST_Msk = 0x100
	// Bit LPUARTRST.
	RCC_APB1RSTR_LPUARTRST = 0x100
	// Position of USARTRST field.
	RCC_APB1RSTR_USARTRST_Pos = 0xa
	// Bit mask of USARTRST field.
	RCC_APB1RSTR_USARTRST_Msk = 0x400
	// Bit USARTRST.
	RCC_APB1RSTR_USARTRST = 0x400
	// Position of SPI3RST field.
	RCC_APB1RSTR_SPI3RST_Pos = 0xe
	// Bit mask of SPI3RST field.
	RCC_APB1RSTR_SPI3RST_Msk = 0x4000
	// Bit SPI3RST.
	RCC_APB1RSTR_SPI3RST = 0x4000
	// Position of I2C21RST field.
	RCC_APB1RSTR_I2C21RST_Pos = 0x15
	// Bit mask of I2C21RST field.
	RCC_APB1RSTR_I2C21RST_Msk = 0x200000
	// Bit I2C21RST.
	RCC_APB1RSTR_I2C21RST = 0x200000

	// APB2RSTR: APB2RSTR register
	// Position of BLERST field.
	RCC_APB2RSTR_BLERST_Pos = 0x0
	// Bit mask of BLERST field.
	RCC_APB2RSTR_BLERST_Msk = 0x1
	// Bit BLERST.
	RCC_APB2RSTR_BLERST = 0x1

	// AHBENR: AHBENR register
	// Position of DMAEN field.
	RCC_AHBENR_DMAEN_Pos = 0x0
	// Bit mask of DMAEN field.
	RCC_AHBENR_DMAEN_Msk = 0x1
	// Bit DMAEN.
	RCC_AHBENR_DMAEN = 0x1
	// Position of GPIOAEN field.
	RCC_AHBENR_GPIOAEN_Pos = 0x2
	// Bit mask of GPIOAEN field.
	RCC_AHBENR_GPIOAEN_Msk = 0x4
	// Bit GPIOAEN.
	RCC_AHBENR_GPIOAEN = 0x4
	// Position of GPIOBEN field.
	RCC_AHBENR_GPIOBEN_Pos = 0x3
	// Bit mask of GPIOBEN field.
	RCC_AHBENR_GPIOBEN_Msk = 0x8
	// Bit GPIOBEN.
	RCC_AHBENR_GPIOBEN = 0x8
	// Position of CRCEN field.
	RCC_AHBENR_CRCEN_Pos = 0xc
	// Bit mask of CRCEN field.
	RCC_AHBENR_CRCEN_Msk = 0x1000
	// Bit CRCEN.
	RCC_AHBENR_CRCEN = 0x1000
	// Position of PKAEN field.
	RCC_AHBENR_PKAEN_Pos = 0x10
	// Bit mask of PKAEN field.
	RCC_AHBENR_PKAEN_Msk = 0x10000
	// Bit PKAEN.
	RCC_AHBENR_PKAEN = 0x10000
	// Position of RNGEN field.
	RCC_AHBENR_RNGEN_Pos = 0x12
	// Bit mask of RNGEN field.
	RCC_AHBENR_RNGEN_Msk = 0x40000
	// Bit RNGEN.
	RCC_AHBENR_RNGEN = 0x40000

	// APB0ENR: APB0ENR register
	// Position of TIM2EN field.
	RCC_APB0ENR_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_APB0ENR_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_APB0ENR_TIM2EN = 0x1
	// Position of TIM16EN field.
	RCC_APB0ENR_TIM16EN_Pos = 0x1
	// Bit mask of TIM16EN field.
	RCC_APB0ENR_TIM16EN_Msk = 0x2
	// Bit TIM16EN.
	RCC_APB0ENR_TIM16EN = 0x2
	// Position of TIM17EN field.
	RCC_APB0ENR_TIM17EN_Pos = 0x2
	// Bit mask of TIM17EN field.
	RCC_APB0ENR_TIM17EN_Msk = 0x4
	// Bit TIM17EN.
	RCC_APB0ENR_TIM17EN = 0x4
	// Position of SYSCFGEN field.
	RCC_APB0ENR_SYSCFGEN_Pos = 0x8
	// Bit mask of SYSCFGEN field.
	RCC_APB0ENR_SYSCFGEN_Msk = 0x100
	// Bit SYSCFGEN.
	RCC_APB0ENR_SYSCFGEN = 0x100
	// Position of RTCEN field.
	RCC_APB0ENR_RTCEN_Pos = 0xc
	// Bit mask of RTCEN field.
	RCC_APB0ENR_RTCEN_Msk = 0x1000
	// Bit RTCEN.
	RCC_APB0ENR_RTCEN = 0x1000
	// Position of WDGEN field.
	RCC_APB0ENR_WDGEN_Pos = 0xe
	// Bit mask of WDGEN field.
	RCC_APB0ENR_WDGEN_Msk = 0x4000
	// Bit WDGEN.
	RCC_APB0ENR_WDGEN = 0x4000

	// APB1ENR: APB1ENR register
	// Position of ADCDIGEN field.
	RCC_APB1ENR_ADCDIGEN_Pos = 0x4
	// Bit mask of ADCDIGEN field.
	RCC_APB1ENR_ADCDIGEN_Msk = 0x10
	// Bit ADCDIGEN.
	RCC_APB1ENR_ADCDIGEN = 0x10
	// Position of ADCANAEN field.
	RCC_APB1ENR_ADCANAEN_Pos = 0x5
	// Bit mask of ADCANAEN field.
	RCC_APB1ENR_ADCANAEN_Msk = 0x20
	// Bit ADCANAEN.
	RCC_APB1ENR_ADCANAEN = 0x20
	// Position of LPUARTEN field.
	RCC_APB1ENR_LPUARTEN_Pos = 0x8
	// Bit mask of LPUARTEN field.
	RCC_APB1ENR_LPUARTEN_Msk = 0x100
	// Bit LPUARTEN.
	RCC_APB1ENR_LPUARTEN = 0x100
	// Position of USART1EN field.
	RCC_APB1ENR_USART1EN_Pos = 0xa
	// Bit mask of USART1EN field.
	RCC_APB1ENR_USART1EN_Msk = 0x400
	// Bit USART1EN.
	RCC_APB1ENR_USART1EN = 0x400
	// Position of SPI3EN field.
	RCC_APB1ENR_SPI3EN_Pos = 0xe
	// Bit mask of SPI3EN field.
	RCC_APB1ENR_SPI3EN_Msk = 0x4000
	// Bit SPI3EN.
	RCC_APB1ENR_SPI3EN = 0x4000
	// Position of I2C1EN field.
	RCC_APB1ENR_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_APB1ENR_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_APB1ENR_I2C1EN = 0x200000

	// APB2ENR: APB2ENR register
	// Position of MRBLEEN field.
	RCC_APB2ENR_MRBLEEN_Pos = 0x0
	// Bit mask of MRBLEEN field.
	RCC_APB2ENR_MRBLEEN_Msk = 0x1
	// Bit MRBLEEN.
	RCC_APB2ENR_MRBLEEN = 0x1
	// Position of CLKBLEDIV field.
	RCC_APB2ENR_CLKBLEDIV_Pos = 0x2
	// Bit mask of CLKBLEDIV field.
	RCC_APB2ENR_CLKBLEDIV_Msk = 0x4
	// Bit CLKBLEDIV.
	RCC_APB2ENR_CLKBLEDIV = 0x4

	// CSR: CSR register
	// Position of RMVF field.
	RCC_CSR_RMVF_Pos = 0x17
	// Bit mask of RMVF field.
	RCC_CSR_RMVF_Msk = 0x800000
	// Bit RMVF.
	RCC_CSR_RMVF = 0x800000
	// Position of PADRSTF field.
	RCC_CSR_PADRSTF_Pos = 0x1a
	// Bit mask of PADRSTF field.
	RCC_CSR_PADRSTF_Msk = 0x4000000
	// Bit PADRSTF.
	RCC_CSR_PADRSTF = 0x4000000
	// Position of PORRSTF field.
	RCC_CSR_PORRSTF_Pos = 0x1b
	// Bit mask of PORRSTF field.
	RCC_CSR_PORRSTF_Msk = 0x8000000
	// Bit PORRSTF.
	RCC_CSR_PORRSTF = 0x8000000
	// Position of SFTRSTF field.
	RCC_CSR_SFTRSTF_Pos = 0x1c
	// Bit mask of SFTRSTF field.
	RCC_CSR_SFTRSTF_Msk = 0x10000000
	// Bit SFTRSTF.
	RCC_CSR_SFTRSTF = 0x10000000
	// Position of WDGRSTF field.
	RCC_CSR_WDGRSTF_Pos = 0x1d
	// Bit mask of WDGRSTF field.
	RCC_CSR_WDGRSTF_Msk = 0x20000000
	// Bit WDGRSTF.
	RCC_CSR_WDGRSTF = 0x20000000
	// Position of LOCKUPRSTF field.
	RCC_CSR_LOCKUPRSTF_Pos = 0x1e
	// Bit mask of LOCKUPRSTF field.
	RCC_CSR_LOCKUPRSTF_Msk = 0x40000000
	// Bit LOCKUPRSTF.
	RCC_CSR_LOCKUPRSTF = 0x40000000

	// RFSWHSECR: RFSWHSECR register
	// Position of SATRG field.
	RCC_RFSWHSECR_SATRG_Pos = 0x3
	// Bit mask of SATRG field.
	RCC_RFSWHSECR_SATRG_Msk = 0x8
	// Bit SATRG.
	RCC_RFSWHSECR_SATRG = 0x8
	// Position of GMC field.
	RCC_RFSWHSECR_GMC_Pos = 0x4
	// Bit mask of GMC field.
	RCC_RFSWHSECR_GMC_Msk = 0x70
	// Position of SWXOTUNEEN field.
	RCC_RFSWHSECR_SWXOTUNEEN_Pos = 0x7
	// Bit mask of SWXOTUNEEN field.
	RCC_RFSWHSECR_SWXOTUNEEN_Msk = 0x80
	// Bit SWXOTUNEEN.
	RCC_RFSWHSECR_SWXOTUNEEN = 0x80
	// Position of SWXOTUNE field.
	RCC_RFSWHSECR_SWXOTUNE_Pos = 0x8
	// Bit mask of SWXOTUNE field.
	RCC_RFSWHSECR_SWXOTUNE_Msk = 0x3f00

	// RFHSECR: RFHSECR register
	// Position of XOTUNE field.
	RCC_RFHSECR_XOTUNE_Pos = 0x0
	// Bit mask of XOTUNE field.
	RCC_RFHSECR_XOTUNE_Msk = 0x3f
)

// Constants for SPI3: SPI address block description
const (
	// CR1: SPI control register 1
	// Position of CPHA field.
	SPI_CR1_CPHA_Pos = 0x0
	// Bit mask of CPHA field.
	SPI_CR1_CPHA_Msk = 0x1
	// Bit CPHA.
	SPI_CR1_CPHA = 0x1
	// The first clock transition is the first data capture edge
	SPI_CR1_CPHA_FirstEdge = 0x0
	// The second clock transition is the first data capture edge
	SPI_CR1_CPHA_SecondEdge = 0x1
	// Position of CPOL field.
	SPI_CR1_CPOL_Pos = 0x1
	// Bit mask of CPOL field.
	SPI_CR1_CPOL_Msk = 0x2
	// Bit CPOL.
	SPI_CR1_CPOL = 0x2
	// CK to 0 when idle
	SPI_CR1_CPOL_IdleLow = 0x0
	// CK to 1 when idle
	SPI_CR1_CPOL_IdleHigh = 0x1
	// Position of MSTR field.
	SPI_CR1_MSTR_Pos = 0x2
	// Bit mask of MSTR field.
	SPI_CR1_MSTR_Msk = 0x4
	// Bit MSTR.
	SPI_CR1_MSTR = 0x4
	// Slave configuration
	SPI_CR1_MSTR_Slave = 0x0
	// Master configuration
	SPI_CR1_MSTR_Master = 0x1
	// Position of BR field.
	SPI_CR1_BR_Pos = 0x3
	// Bit mask of BR field.
	SPI_CR1_BR_Msk = 0x38
	// f_PCLK / 2
	SPI_CR1_BR_Div2 = 0x0
	// f_PCLK / 4
	SPI_CR1_BR_Div4 = 0x1
	// f_PCLK / 8
	SPI_CR1_BR_Div8 = 0x2
	// f_PCLK / 16
	SPI_CR1_BR_Div16 = 0x3
	// f_PCLK / 32
	SPI_CR1_BR_Div32 = 0x4
	// f_PCLK / 64
	SPI_CR1_BR_Div64 = 0x5
	// f_PCLK / 128
	SPI_CR1_BR_Div128 = 0x6
	// f_PCLK / 256
	SPI_CR1_BR_Div256 = 0x7
	// Position of SPE field.
	SPI_CR1_SPE_Pos = 0x6
	// Bit mask of SPE field.
	SPI_CR1_SPE_Msk = 0x40
	// Bit SPE.
	SPI_CR1_SPE = 0x40
	// Peripheral disabled
	SPI_CR1_SPE_Disabled = 0x0
	// Peripheral enabled
	SPI_CR1_SPE_Enabled = 0x1
	// Position of LSBFIRST field.
	SPI_CR1_LSBFIRST_Pos = 0x7
	// Bit mask of LSBFIRST field.
	SPI_CR1_LSBFIRST_Msk = 0x80
	// Bit LSBFIRST.
	SPI_CR1_LSBFIRST = 0x80
	// Data is transmitted/received with the MSB first
	SPI_CR1_LSBFIRST_MSBFirst = 0x0
	// Data is transmitted/received with the LSB first
	SPI_CR1_LSBFIRST_LSBFirst = 0x1
	// Position of SSI field.
	SPI_CR1_SSI_Pos = 0x8
	// Bit mask of SSI field.
	SPI_CR1_SSI_Msk = 0x100
	// Bit SSI.
	SPI_CR1_SSI = 0x100
	// 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
	SPI_CR1_SSI_SlaveSelected = 0x0
	// 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
	SPI_CR1_SSI_SlaveNotSelected = 0x1
	// Position of SSM field.
	SPI_CR1_SSM_Pos = 0x9
	// Bit mask of SSM field.
	SPI_CR1_SSM_Msk = 0x200
	// Bit SSM.
	SPI_CR1_SSM = 0x200
	// Software slave management disabled
	SPI_CR1_SSM_Disabled = 0x0
	// Software slave management enabled
	SPI_CR1_SSM_Enabled = 0x1
	// Position of RXONLY field.
	SPI_CR1_RXONLY_Pos = 0xa
	// Bit mask of RXONLY field.
	SPI_CR1_RXONLY_Msk = 0x400
	// Bit RXONLY.
	SPI_CR1_RXONLY = 0x400
	// Full duplex (Transmit and receive)
	SPI_CR1_RXONLY_FullDuplex = 0x0
	// Output disabled (Receive-only mode)
	SPI_CR1_RXONLY_OutputDisabled = 0x1
	// Position of CRCL field.
	SPI_CR1_CRCL_Pos = 0xb
	// Bit mask of CRCL field.
	SPI_CR1_CRCL_Msk = 0x800
	// Bit CRCL.
	SPI_CR1_CRCL = 0x800
	// 8-bit CRC length
	SPI_CR1_CRCL_EightBit = 0x0
	// 16-bit CRC length
	SPI_CR1_CRCL_SixteenBit = 0x1
	// Position of CRCNEXT field.
	SPI_CR1_CRCNEXT_Pos = 0xc
	// Bit mask of CRCNEXT field.
	SPI_CR1_CRCNEXT_Msk = 0x1000
	// Bit CRCNEXT.
	SPI_CR1_CRCNEXT = 0x1000
	// Next transmit value is from Tx buffer
	SPI_CR1_CRCNEXT_TxBuffer = 0x0
	// Next transmit value is from Tx CRC register
	SPI_CR1_CRCNEXT_CRC = 0x1
	// Position of CRCEN field.
	SPI_CR1_CRCEN_Pos = 0xd
	// Bit mask of CRCEN field.
	SPI_CR1_CRCEN_Msk = 0x2000
	// Bit CRCEN.
	SPI_CR1_CRCEN = 0x2000
	// CRC calculation disabled
	SPI_CR1_CRCEN_Disabled = 0x0
	// CRC calculation enabled
	SPI_CR1_CRCEN_Enabled = 0x1
	// Position of BIDIOE field.
	SPI_CR1_BIDIOE_Pos = 0xe
	// Bit mask of BIDIOE field.
	SPI_CR1_BIDIOE_Msk = 0x4000
	// Bit BIDIOE.
	SPI_CR1_BIDIOE = 0x4000
	// Output disabled (receive-only mode)
	SPI_CR1_BIDIOE_OutputDisabled = 0x0
	// Output enabled (transmit-only mode)
	SPI_CR1_BIDIOE_OutputEnabled = 0x1
	// Position of BIDIMODE field.
	SPI_CR1_BIDIMODE_Pos = 0xf
	// Bit mask of BIDIMODE field.
	SPI_CR1_BIDIMODE_Msk = 0x8000
	// Bit BIDIMODE.
	SPI_CR1_BIDIMODE = 0x8000
	// 2-line unidirectional data mode selected
	SPI_CR1_BIDIMODE_Unidirectional = 0x0
	// 1-line bidirectional data mode selected
	SPI_CR1_BIDIMODE_Bidirectional = 0x1

	// CR2: SPI control register 2
	// Position of RXDMAEN field.
	SPI_CR2_RXDMAEN_Pos = 0x0
	// Bit mask of RXDMAEN field.
	SPI_CR2_RXDMAEN_Msk = 0x1
	// Bit RXDMAEN.
	SPI_CR2_RXDMAEN = 0x1
	// Rx buffer DMA disabled
	SPI_CR2_RXDMAEN_Disabled = 0x0
	// Rx buffer DMA enabled
	SPI_CR2_RXDMAEN_Enabled = 0x1
	// Position of TXDMAEN field.
	SPI_CR2_TXDMAEN_Pos = 0x1
	// Bit mask of TXDMAEN field.
	SPI_CR2_TXDMAEN_Msk = 0x2
	// Bit TXDMAEN.
	SPI_CR2_TXDMAEN = 0x2
	// Tx buffer DMA disabled
	SPI_CR2_TXDMAEN_Disabled = 0x0
	// Tx buffer DMA enabled
	SPI_CR2_TXDMAEN_Enabled = 0x1
	// Position of SSOE field.
	SPI_CR2_SSOE_Pos = 0x2
	// Bit mask of SSOE field.
	SPI_CR2_SSOE_Msk = 0x4
	// Bit SSOE.
	SPI_CR2_SSOE = 0x4
	// SS output is disabled in master mode
	SPI_CR2_SSOE_Disabled = 0x0
	// SS output is enabled in master mode
	SPI_CR2_SSOE_Enabled = 0x1
	// Position of NSSP field.
	SPI_CR2_NSSP_Pos = 0x3
	// Bit mask of NSSP field.
	SPI_CR2_NSSP_Msk = 0x8
	// Bit NSSP.
	SPI_CR2_NSSP = 0x8
	// No NSS pulse
	SPI_CR2_NSSP_NoPulse = 0x0
	// NSS pulse generated
	SPI_CR2_NSSP_PulseGenerated = 0x1
	// Position of FRF field.
	SPI_CR2_FRF_Pos = 0x4
	// Bit mask of FRF field.
	SPI_CR2_FRF_Msk = 0x10
	// Bit FRF.
	SPI_CR2_FRF = 0x10
	// SPI Motorola mode
	SPI_CR2_FRF_Motorola = 0x0
	// SPI TI mode
	SPI_CR2_FRF_TI = 0x1
	// Position of ERRIE field.
	SPI_CR2_ERRIE_Pos = 0x5
	// Bit mask of ERRIE field.
	SPI_CR2_ERRIE_Msk = 0x20
	// Bit ERRIE.
	SPI_CR2_ERRIE = 0x20
	// Error interrupt masked
	SPI_CR2_ERRIE_Masked = 0x0
	// Error interrupt not masked
	SPI_CR2_ERRIE_NotMasked = 0x1
	// Position of RXNEIE field.
	SPI_CR2_RXNEIE_Pos = 0x6
	// Bit mask of RXNEIE field.
	SPI_CR2_RXNEIE_Msk = 0x40
	// Bit RXNEIE.
	SPI_CR2_RXNEIE = 0x40
	// RXE interrupt masked
	SPI_CR2_RXNEIE_Masked = 0x0
	// RXE interrupt not masked
	SPI_CR2_RXNEIE_NotMasked = 0x1
	// Position of TXEIE field.
	SPI_CR2_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	SPI_CR2_TXEIE_Msk = 0x80
	// Bit TXEIE.
	SPI_CR2_TXEIE = 0x80
	// TXE interrupt masked
	SPI_CR2_TXEIE_Masked = 0x0
	// TXE interrupt not masked
	SPI_CR2_TXEIE_NotMasked = 0x1
	// Position of DS field.
	SPI_CR2_DS_Pos = 0x8
	// Bit mask of DS field.
	SPI_CR2_DS_Msk = 0xf00
	// 4-bit
	SPI_CR2_DS_FourBit = 0x3
	// 5-bit
	SPI_CR2_DS_FiveBit = 0x4
	// 6-bit
	SPI_CR2_DS_SixBit = 0x5
	// 7-bit
	SPI_CR2_DS_SevenBit = 0x6
	// 8-bit
	SPI_CR2_DS_EightBit = 0x7
	// 9-bit
	SPI_CR2_DS_NineBit = 0x8
	// 10-bit
	SPI_CR2_DS_TenBit = 0x9
	// 11-bit
	SPI_CR2_DS_ElevenBit = 0xa
	// 12-bit
	SPI_CR2_DS_TwelveBit = 0xb
	// 13-bit
	SPI_CR2_DS_ThirteenBit = 0xc
	// 14-bit
	SPI_CR2_DS_FourteenBit = 0xd
	// 15-bit
	SPI_CR2_DS_FifteenBit = 0xe
	// 16-bit
	SPI_CR2_DS_SixteenBit = 0xf
	// Position of FRXTH field.
	SPI_CR2_FRXTH_Pos = 0xc
	// Bit mask of FRXTH field.
	SPI_CR2_FRXTH_Msk = 0x1000
	// Bit FRXTH.
	SPI_CR2_FRXTH = 0x1000
	// RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
	SPI_CR2_FRXTH_Half = 0x0
	// RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
	SPI_CR2_FRXTH_Quarter = 0x1
	// Position of LDMA_RX field.
	SPI_CR2_LDMA_RX_Pos = 0xd
	// Bit mask of LDMA_RX field.
	SPI_CR2_LDMA_RX_Msk = 0x2000
	// Bit LDMA_RX.
	SPI_CR2_LDMA_RX = 0x2000
	// Number of data to transfer for receive is even
	SPI_CR2_LDMA_RX_Even = 0x0
	// Number of data to transfer for receive is odd
	SPI_CR2_LDMA_RX_Odd = 0x1
	// Position of LDMA_TX field.
	SPI_CR2_LDMA_TX_Pos = 0xe
	// Bit mask of LDMA_TX field.
	SPI_CR2_LDMA_TX_Msk = 0x4000
	// Bit LDMA_TX.
	SPI_CR2_LDMA_TX = 0x4000
	// Number of data to transfer for transmit is even
	SPI_CR2_LDMA_TX_Even = 0x0
	// Number of data to transfer for transmit is odd
	SPI_CR2_LDMA_TX_Odd = 0x1

	// SR: SPI status register
	// Position of RXNE field.
	SPI_SR_RXNE_Pos = 0x0
	// Bit mask of RXNE field.
	SPI_SR_RXNE_Msk = 0x1
	// Bit RXNE.
	SPI_SR_RXNE = 0x1
	// Rx buffer empty
	SPI_SR_RXNE_Empty = 0x0
	// Rx buffer not empty
	SPI_SR_RXNE_NotEmpty = 0x1
	// Position of TXE field.
	SPI_SR_TXE_Pos = 0x1
	// Bit mask of TXE field.
	SPI_SR_TXE_Msk = 0x2
	// Bit TXE.
	SPI_SR_TXE = 0x2
	// Tx buffer not empty
	SPI_SR_TXE_NotEmpty = 0x0
	// Tx buffer empty
	SPI_SR_TXE_Empty = 0x1
	// Position of CHSIDE field.
	SPI_SR_CHSIDE_Pos = 0x2
	// Bit mask of CHSIDE field.
	SPI_SR_CHSIDE_Msk = 0x4
	// Bit CHSIDE.
	SPI_SR_CHSIDE = 0x4
	// Channel left has to be transmitted or has been received
	SPI_SR_CHSIDE_Left = 0x0
	// Channel right has to be transmitted or has been received
	SPI_SR_CHSIDE_Right = 0x1
	// Position of UDR field.
	SPI_SR_UDR_Pos = 0x3
	// Bit mask of UDR field.
	SPI_SR_UDR_Msk = 0x8
	// Bit UDR.
	SPI_SR_UDR = 0x8
	// No underrun occurred
	SPI_SR_UDR_NoUnderrun = 0x0
	// Underrun occurred
	SPI_SR_UDR_Underrun = 0x1
	// Position of CRCERR field.
	SPI_SR_CRCERR_Pos = 0x4
	// Bit mask of CRCERR field.
	SPI_SR_CRCERR_Msk = 0x10
	// Bit CRCERR.
	SPI_SR_CRCERR = 0x10
	// CRC value received matches the SPIx_RXCRCR value
	SPI_SR_CRCERR_Match = 0x0
	// CRC value received does not match the SPIx_RXCRCR value
	SPI_SR_CRCERR_NoMatch = 0x1
	// Clear flag
	SPI_SR_CRCERR_Clear = 0x0
	// Position of MODF field.
	SPI_SR_MODF_Pos = 0x5
	// Bit mask of MODF field.
	SPI_SR_MODF_Msk = 0x20
	// Bit MODF.
	SPI_SR_MODF = 0x20
	// No mode fault occurred
	SPI_SR_MODF_NoFault = 0x0
	// Mode fault occurred
	SPI_SR_MODF_Fault = 0x1
	// Position of OVR field.
	SPI_SR_OVR_Pos = 0x6
	// Bit mask of OVR field.
	SPI_SR_OVR_Msk = 0x40
	// Bit OVR.
	SPI_SR_OVR = 0x40
	// No overrun occurred
	SPI_SR_OVR_NoOverrun = 0x0
	// Overrun occurred
	SPI_SR_OVR_Overrun = 0x1
	// Position of BSY field.
	SPI_SR_BSY_Pos = 0x7
	// Bit mask of BSY field.
	SPI_SR_BSY_Msk = 0x80
	// Bit BSY.
	SPI_SR_BSY = 0x80
	// SPI not busy
	SPI_SR_BSY_NotBusy = 0x0
	// SPI busy
	SPI_SR_BSY_Busy = 0x1
	// Position of FRE field.
	SPI_SR_FRE_Pos = 0x8
	// Bit mask of FRE field.
	SPI_SR_FRE_Msk = 0x100
	// Bit FRE.
	SPI_SR_FRE = 0x100
	// No frame format error
	SPI_SR_FRE_NoError = 0x0
	// A frame format error occurred
	SPI_SR_FRE_Error = 0x1
	// Position of FRLVL field.
	SPI_SR_FRLVL_Pos = 0x9
	// Bit mask of FRLVL field.
	SPI_SR_FRLVL_Msk = 0x600
	// Rx FIFO Empty
	SPI_SR_FRLVL_Empty = 0x0
	// Rx 1/4 FIFO
	SPI_SR_FRLVL_Quarter = 0x1
	// Rx 1/2 FIFO
	SPI_SR_FRLVL_Half = 0x2
	// Rx FIFO full
	SPI_SR_FRLVL_Full = 0x3
	// Position of FTLVL field.
	SPI_SR_FTLVL_Pos = 0xb
	// Bit mask of FTLVL field.
	SPI_SR_FTLVL_Msk = 0x1800
	// Tx FIFO Empty
	SPI_SR_FTLVL_Empty = 0x0
	// Tx 1/4 FIFO
	SPI_SR_FTLVL_Quarter = 0x1
	// Tx 1/2 FIFO
	SPI_SR_FTLVL_Half = 0x2
	// Tx FIFO full
	SPI_SR_FTLVL_Full = 0x3

	// DR: SPI data register
	// Position of DR field.
	SPI_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	SPI_DR_DR_Msk = 0xffff

	// DR8: Direct 8-bit access to data register
	// Position of DR field.
	SPI_DR8_DR_Pos = 0x0
	// Bit mask of DR field.
	SPI_DR8_DR_Msk = 0xff

	// CRCPR: SPI CRC polynomial register
	// Position of CRCPOLY field.
	SPI_CRCPR_CRCPOLY_Pos = 0x0
	// Bit mask of CRCPOLY field.
	SPI_CRCPR_CRCPOLY_Msk = 0xffff

	// RXCRCR: SPI Rx CRC register
	// Position of RXCRC field.
	SPI_RXCRCR_RXCRC_Pos = 0x0
	// Bit mask of RXCRC field.
	SPI_RXCRCR_RXCRC_Msk = 0xffff

	// TXCRCR: SPI Tx CRC register
	// Position of TXCRC field.
	SPI_TXCRCR_TXCRC_Pos = 0x0
	// Bit mask of TXCRC field.
	SPI_TXCRCR_TXCRC_Msk = 0xffff

	// I2SCFGR: SPIx_I2S configuration register
	// Position of CHLEN field.
	SPI_I2SCFGR_CHLEN_Pos = 0x0
	// Bit mask of CHLEN field.
	SPI_I2SCFGR_CHLEN_Msk = 0x1
	// Bit CHLEN.
	SPI_I2SCFGR_CHLEN = 0x1
	// 16-bit wide
	SPI_I2SCFGR_CHLEN_SixteenBit = 0x0
	// 32-bit wide
	SPI_I2SCFGR_CHLEN_ThirtyTwoBit = 0x1
	// Position of DATLEN field.
	SPI_I2SCFGR_DATLEN_Pos = 0x1
	// Bit mask of DATLEN field.
	SPI_I2SCFGR_DATLEN_Msk = 0x6
	// 16-bit data length
	SPI_I2SCFGR_DATLEN_SixteenBit = 0x0
	// 24-bit data length
	SPI_I2SCFGR_DATLEN_TwentyFourBit = 0x1
	// 32-bit data length
	SPI_I2SCFGR_DATLEN_ThirtyTwoBit = 0x2
	// Position of CKPOL field.
	SPI_I2SCFGR_CKPOL_Pos = 0x3
	// Bit mask of CKPOL field.
	SPI_I2SCFGR_CKPOL_Msk = 0x8
	// Bit CKPOL.
	SPI_I2SCFGR_CKPOL = 0x8
	// I2S clock inactive state is low level
	SPI_I2SCFGR_CKPOL_IdleLow = 0x0
	// I2S clock inactive state is high level
	SPI_I2SCFGR_CKPOL_IdleHigh = 0x1
	// Position of I2SSTD field.
	SPI_I2SCFGR_I2SSTD_Pos = 0x4
	// Bit mask of I2SSTD field.
	SPI_I2SCFGR_I2SSTD_Msk = 0x30
	// I2S Philips standard
	SPI_I2SCFGR_I2SSTD_Philips = 0x0
	// MSB justified standard
	SPI_I2SCFGR_I2SSTD_MSB = 0x1
	// LSB justified standard
	SPI_I2SCFGR_I2SSTD_LSB = 0x2
	// PCM standard
	SPI_I2SCFGR_I2SSTD_PCM = 0x3
	// Position of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC_Pos = 0x7
	// Bit mask of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC_Msk = 0x80
	// Bit PCMSYNC.
	SPI_I2SCFGR_PCMSYNC = 0x80
	// Short frame synchronisation
	SPI_I2SCFGR_PCMSYNC_Short = 0x0
	// Long frame synchronisation
	SPI_I2SCFGR_PCMSYNC_Long = 0x1
	// Position of I2SCFG field.
	SPI_I2SCFGR_I2SCFG_Pos = 0x8
	// Bit mask of I2SCFG field.
	SPI_I2SCFGR_I2SCFG_Msk = 0x300
	// Slave - transmit
	SPI_I2SCFGR_I2SCFG_SlaveTx = 0x0
	// Slave - receive
	SPI_I2SCFGR_I2SCFG_SlaveRx = 0x1
	// Master - transmit
	SPI_I2SCFGR_I2SCFG_MasterTx = 0x2
	// Master - receive
	SPI_I2SCFGR_I2SCFG_MasterRx = 0x3
	// Position of I2SE field.
	SPI_I2SCFGR_I2SE_Pos = 0xa
	// Bit mask of I2SE field.
	SPI_I2SCFGR_I2SE_Msk = 0x400
	// Bit I2SE.
	SPI_I2SCFGR_I2SE = 0x400
	// I2S peripheral is disabled
	SPI_I2SCFGR_I2SE_Disabled = 0x0
	// I2S peripheral is enabled
	SPI_I2SCFGR_I2SE_Enabled = 0x1
	// Position of I2SMOD field.
	SPI_I2SCFGR_I2SMOD_Pos = 0xb
	// Bit mask of I2SMOD field.
	SPI_I2SCFGR_I2SMOD_Msk = 0x800
	// Bit I2SMOD.
	SPI_I2SCFGR_I2SMOD = 0x800
	// SPI mode is selected
	SPI_I2SCFGR_I2SMOD_SPIMode = 0x0
	// I2S mode is selected
	SPI_I2SCFGR_I2SMOD_I2SMode = 0x1
	// Position of ASTRTEN field.
	SPI_I2SCFGR_ASTRTEN_Pos = 0xc
	// Bit mask of ASTRTEN field.
	SPI_I2SCFGR_ASTRTEN_Msk = 0x1000
	// Bit ASTRTEN.
	SPI_I2SCFGR_ASTRTEN = 0x1000
	// Asynchronous start disabled
	SPI_I2SCFGR_ASTRTEN_AsyncStartDisabled = 0x0
	// Asynchronous start enabled
	SPI_I2SCFGR_ASTRTEN_AsyncStartEnabled = 0x1

	// I2SPR: SPIx_I2S prescaler register
	// Position of I2SDIV field.
	SPI_I2SPR_I2SDIV_Pos = 0x0
	// Bit mask of I2SDIV field.
	SPI_I2SPR_I2SDIV_Msk = 0xff
	// Position of ODD field.
	SPI_I2SPR_ODD_Pos = 0x8
	// Bit mask of ODD field.
	SPI_I2SPR_ODD_Msk = 0x100
	// Bit ODD.
	SPI_I2SPR_ODD = 0x100
	// Real divider value is I2SDIV * 2
	SPI_I2SPR_ODD_Even = 0x0
	// Real divider value is (I2SDIV * 2) + 1
	SPI_I2SPR_ODD_Odd = 0x1
	// Position of MCKOE field.
	SPI_I2SPR_MCKOE_Pos = 0x9
	// Bit mask of MCKOE field.
	SPI_I2SPR_MCKOE_Msk = 0x200
	// Bit MCKOE.
	SPI_I2SPR_MCKOE = 0x200
	// Master clock output is disabled
	SPI_I2SPR_MCKOE_Disabled = 0x0
	// Master clock output is enabled
	SPI_I2SPR_MCKOE_Enabled = 0x1
)

// Constants for TIM2
const (
	// CR1: CR1 register
	// Position of CEN field.
	TIM_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM_CR1_CEN = 0x1
	// Counter disabled
	TIM_CR1_CEN_Disabled = 0x0
	// Counter enabled
	TIM_CR1_CEN_Enabled = 0x1
	// Position of UDIS field.
	TIM_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM_CR1_UDIS = 0x2
	// Update event enabled
	TIM_CR1_UDIS_Enabled = 0x0
	// Update event disabled
	TIM_CR1_UDIS_Disabled = 0x1
	// Position of URS field.
	TIM_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM_CR1_URS = 0x4
	// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
	TIM_CR1_URS_AnyEvent = 0x0
	// Only counter overflow/underflow generates an update interrupt or DMA request
	TIM_CR1_URS_CounterOnly = 0x1
	// Position of OPM field.
	TIM_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM_CR1_OPM = 0x8
	// Counter is not stopped at update event
	TIM_CR1_OPM_Disabled = 0x0
	// Counter stops counting at the next update event (clearing the CEN bit)
	TIM_CR1_OPM_Enabled = 0x1
	// Position of DIR field.
	TIM_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM_CR1_DIR = 0x10
	// Counter used as upcounter
	TIM_CR1_DIR_Up = 0x0
	// Counter used as downcounter
	TIM_CR1_DIR_Down = 0x1
	// Position of CMS field.
	TIM_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM_CR1_CMS_Msk = 0x60
	// The counter counts up or down depending on the direction bit
	TIM_CR1_CMS_EdgeAligned = 0x0
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
	TIM_CR1_CMS_CenterAligned1 = 0x1
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
	TIM_CR1_CMS_CenterAligned2 = 0x2
	// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
	TIM_CR1_CMS_CenterAligned3 = 0x3
	// Position of ARPE field.
	TIM_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM_CR1_ARPE = 0x80
	// TIMx_APRR register is not buffered
	TIM_CR1_ARPE_Disabled = 0x0
	// TIMx_APRR register is buffered
	TIM_CR1_ARPE_Enabled = 0x1
	// Position of CKD field.
	TIM_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM_CR1_CKD_Msk = 0x300
	// t_DTS = t_CK_INT
	TIM_CR1_CKD_Div1 = 0x0
	// t_DTS = 2 × t_CK_INT
	TIM_CR1_CKD_Div2 = 0x1
	// t_DTS = 4 × t_CK_INT
	TIM_CR1_CKD_Div4 = 0x2
	// Position of UIF_REMAP field.
	TIM_CR1_UIF_REMAP_Pos = 0xb
	// Bit mask of UIF_REMAP field.
	TIM_CR1_UIF_REMAP_Msk = 0x800
	// Bit UIF_REMAP.
	TIM_CR1_UIF_REMAP = 0x800

	// CR2: CR2 register
	// Position of CCDS field.
	TIM_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM_CR2_CCDS = 0x8
	// CCx DMA request sent when CCx event occurs
	TIM_CR2_CCDS_OnCompare = 0x0
	// CCx DMA request sent when update event occurs
	TIM_CR2_CCDS_OnUpdate = 0x1
	// Position of MMS field.
	TIM_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM_CR2_MMS_Msk = 0x70
	// Position of TI1S field.
	TIM_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM_CR2_TI1S = 0x80
	// The TIMx_CH1 pin is connected to TI1 input
	TIM_CR2_TI1S_Normal = 0x0
	// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
	TIM_CR2_TI1S_XOR = 0x1

	// SMCR: SMCR register
	// Position of SMS field.
	TIM_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM_SMCR_SMS_Msk = 0x7
	// Position of OCCS field.
	TIM_SMCR_OCCS_Pos = 0x3
	// Bit mask of OCCS field.
	TIM_SMCR_OCCS_Msk = 0x8
	// Bit OCCS.
	TIM_SMCR_OCCS = 0x8
	// Position of TS field.
	TIM_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM_SMCR_TS_Msk = 0x70
	// Position of MSM field.
	TIM_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM_SMCR_MSM = 0x80
	// No action
	TIM_SMCR_MSM_NoSync = 0x0
	// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
	TIM_SMCR_MSM_Sync = 0x1
	// Position of ETF field.
	TIM_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM_SMCR_ETF_Msk = 0xf00
	// No filter, sampling is done at fDTS
	TIM_SMCR_ETF_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_SMCR_ETF_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_SMCR_ETF_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_SMCR_ETF_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_SMCR_ETF_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_SMCR_ETF_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_SMCR_ETF_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_SMCR_ETF_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_SMCR_ETF_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_SMCR_ETF_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_SMCR_ETF_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_SMCR_ETF_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_SMCR_ETF_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_SMCR_ETF_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_SMCR_ETF_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_SMCR_ETF_FDTS_Div32_N8 = 0xf
	// Position of ETPS field.
	TIM_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM_SMCR_ETPS_Msk = 0x3000
	// Prescaler OFF
	TIM_SMCR_ETPS_Div1 = 0x0
	// ETRP frequency divided by 2
	TIM_SMCR_ETPS_Div2 = 0x1
	// ETRP frequency divided by 4
	TIM_SMCR_ETPS_Div4 = 0x2
	// ETRP frequency divided by 8
	TIM_SMCR_ETPS_Div8 = 0x3
	// Position of ECE field.
	TIM_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM_SMCR_ECE = 0x4000
	// External clock mode 2 disabled
	TIM_SMCR_ECE_Disabled = 0x0
	// External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
	TIM_SMCR_ECE_Enabled = 0x1
	// Position of ETP field.
	TIM_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM_SMCR_ETP = 0x8000
	// ETR is noninverted, active at high level or rising edge
	TIM_SMCR_ETP_NotInverted = 0x0
	// ETR is inverted, active at low level or falling edge
	TIM_SMCR_ETP_Inverted = 0x1
	// Position of SMS_3 field.
	TIM_SMCR_SMS_3_Pos = 0x10
	// Bit mask of SMS_3 field.
	TIM_SMCR_SMS_3_Msk = 0x10000
	// Bit SMS_3.
	TIM_SMCR_SMS_3 = 0x10000
	// Position of TS2 field.
	TIM_SMCR_TS2_Pos = 0x14
	// Bit mask of TS2 field.
	TIM_SMCR_TS2_Msk = 0x300000

	// DIER: DIER register
	// Position of UIE field.
	TIM_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM_DIER_UIE = 0x1
	// Update interrupt disabled
	TIM_DIER_UIE_Disabled = 0x0
	// Update interrupt enabled
	TIM_DIER_UIE_Enabled = 0x1
	// Position of CC1IE field.
	TIM_DIER_CC1IE_Pos = 0x2
	// Bit mask of CC1IE field.
	TIM_DIER_CC1IE_Msk = 0x4
	// Bit CC1IE.
	TIM_DIER_CC1IE = 0x4
	// CCx interrupt disabled
	TIM_DIER_CC1IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC1IE_Enabled = 0x1
	// Position of CC2IE field.
	TIM_DIER_CC2IE_Pos = 0x3
	// Bit mask of CC2IE field.
	TIM_DIER_CC2IE_Msk = 0x8
	// Bit CC2IE.
	TIM_DIER_CC2IE = 0x8
	// CCx interrupt disabled
	TIM_DIER_CC2IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC2IE_Enabled = 0x1
	// Position of CC3IE field.
	TIM_DIER_CC3IE_Pos = 0x4
	// Bit mask of CC3IE field.
	TIM_DIER_CC3IE_Msk = 0x10
	// Bit CC3IE.
	TIM_DIER_CC3IE = 0x10
	// CCx interrupt disabled
	TIM_DIER_CC3IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC3IE_Enabled = 0x1
	// Position of CC4IE field.
	TIM_DIER_CC4IE_Pos = 0x5
	// Bit mask of CC4IE field.
	TIM_DIER_CC4IE_Msk = 0x20
	// Bit CC4IE.
	TIM_DIER_CC4IE = 0x20
	// CCx interrupt disabled
	TIM_DIER_CC4IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC4IE_Enabled = 0x1
	// Position of TIE field.
	TIM_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM_DIER_TIE = 0x40
	// Trigger interrupt disabled
	TIM_DIER_TIE_Disabled = 0x0
	// Trigger interrupt enabled
	TIM_DIER_TIE_Enabled = 0x1
	// Position of UDE field.
	TIM_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM_DIER_UDE = 0x100
	// Update DMA request disabled
	TIM_DIER_UDE_Disabled = 0x0
	// Update DMA request enabled
	TIM_DIER_UDE_Enabled = 0x1
	// Position of CC1DE field.
	TIM_DIER_CC1DE_Pos = 0xa
	// Bit mask of CC1DE field.
	TIM_DIER_CC1DE_Msk = 0x400
	// Bit CC1DE.
	TIM_DIER_CC1DE = 0x400
	// CCx DMA request disabled
	TIM_DIER_CC1DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC1DE_Enabled = 0x1
	// Position of CC2DE field.
	TIM_DIER_CC2DE_Pos = 0xb
	// Bit mask of CC2DE field.
	TIM_DIER_CC2DE_Msk = 0x800
	// Bit CC2DE.
	TIM_DIER_CC2DE = 0x800
	// CCx DMA request disabled
	TIM_DIER_CC2DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC2DE_Enabled = 0x1
	// Position of CC3DE field.
	TIM_DIER_CC3DE_Pos = 0xc
	// Bit mask of CC3DE field.
	TIM_DIER_CC3DE_Msk = 0x1000
	// Bit CC3DE.
	TIM_DIER_CC3DE = 0x1000
	// CCx DMA request disabled
	TIM_DIER_CC3DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC3DE_Enabled = 0x1
	// Position of CC4DE field.
	TIM_DIER_CC4DE_Pos = 0xd
	// Bit mask of CC4DE field.
	TIM_DIER_CC4DE_Msk = 0x2000
	// Bit CC4DE.
	TIM_DIER_CC4DE = 0x2000
	// CCx DMA request disabled
	TIM_DIER_CC4DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC4DE_Enabled = 0x1
	// Position of TDE field.
	TIM_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM_DIER_TDE = 0x4000
	// Trigger DMA request disabled
	TIM_DIER_TDE_Disabled = 0x0
	// Trigger DMA request enabled
	TIM_DIER_TDE_Enabled = 0x1

	// SR: SR register
	// Position of UIF field.
	TIM_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM_SR_UIF = 0x1
	// No update occurred
	TIM_SR_UIF_NoUpdateOccurred = 0x0
	// Update interrupt pending
	TIM_SR_UIF_UpdatePending = 0x1
	// Clear flag
	TIM_SR_UIF_Clear = 0x0
	// Position of CC1IF field.
	TIM_SR_CC1IF_Pos = 0x2
	// Bit mask of CC1IF field.
	TIM_SR_CC1IF_Msk = 0x4
	// Bit CC1IF.
	TIM_SR_CC1IF = 0x4
	// No campture/compare has been detected
	TIM_SR_CC1IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC1IF_Match = 0x1
	// Clear flag
	TIM_SR_CC1IF_Clear = 0x0
	// Position of CC2IF field.
	TIM_SR_CC2IF_Pos = 0x3
	// Bit mask of CC2IF field.
	TIM_SR_CC2IF_Msk = 0x8
	// Bit CC2IF.
	TIM_SR_CC2IF = 0x8
	// No campture/compare has been detected
	TIM_SR_CC2IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC2IF_Match = 0x1
	// Clear flag
	TIM_SR_CC2IF_Clear = 0x0
	// Position of CC3IF field.
	TIM_SR_CC3IF_Pos = 0x4
	// Bit mask of CC3IF field.
	TIM_SR_CC3IF_Msk = 0x10
	// Bit CC3IF.
	TIM_SR_CC3IF = 0x10
	// No campture/compare has been detected
	TIM_SR_CC3IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC3IF_Match = 0x1
	// Clear flag
	TIM_SR_CC3IF_Clear = 0x0
	// Position of CC4IF field.
	TIM_SR_CC4IF_Pos = 0x5
	// Bit mask of CC4IF field.
	TIM_SR_CC4IF_Msk = 0x20
	// Bit CC4IF.
	TIM_SR_CC4IF = 0x20
	// No campture/compare has been detected
	TIM_SR_CC4IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC4IF_Match = 0x1
	// Clear flag
	TIM_SR_CC4IF_Clear = 0x0
	// Position of TIF field.
	TIM_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM_SR_TIF = 0x40
	// No trigger event occurred
	TIM_SR_TIF_NoTrigger = 0x0
	// Trigger interrupt pending
	TIM_SR_TIF_Trigger = 0x1
	// Clear flag
	TIM_SR_TIF_Clear = 0x0
	// Position of CC1OF field.
	TIM_SR_CC1OF_Pos = 0xa
	// Bit mask of CC1OF field.
	TIM_SR_CC1OF_Msk = 0x400
	// Bit CC1OF.
	TIM_SR_CC1OF = 0x400
	// No overcapture has been detected
	TIM_SR_CC1OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC1OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC1OF_Clear = 0x0
	// Position of CC2OF field.
	TIM_SR_CC2OF_Pos = 0xb
	// Bit mask of CC2OF field.
	TIM_SR_CC2OF_Msk = 0x800
	// Bit CC2OF.
	TIM_SR_CC2OF = 0x800
	// No overcapture has been detected
	TIM_SR_CC2OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC2OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC2OF_Clear = 0x0
	// Position of CC3OF field.
	TIM_SR_CC3OF_Pos = 0xc
	// Bit mask of CC3OF field.
	TIM_SR_CC3OF_Msk = 0x1000
	// Bit CC3OF.
	TIM_SR_CC3OF = 0x1000
	// No overcapture has been detected
	TIM_SR_CC3OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC3OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC3OF_Clear = 0x0
	// Position of CC4OF field.
	TIM_SR_CC4OF_Pos = 0xd
	// Bit mask of CC4OF field.
	TIM_SR_CC4OF_Msk = 0x2000
	// Bit CC4OF.
	TIM_SR_CC4OF = 0x2000
	// No overcapture has been detected
	TIM_SR_CC4OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC4OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC4OF_Clear = 0x0

	// EGR: EGR register
	// Position of UG field.
	TIM_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM_EGR_UG = 0x1
	// Re-initializes the timer counter and generates an update of the registers.
	TIM_EGR_UG_Update = 0x1
	// Position of CC1G field.
	TIM_EGR_CC1G_Pos = 0x2
	// Bit mask of CC1G field.
	TIM_EGR_CC1G_Msk = 0x4
	// Bit CC1G.
	TIM_EGR_CC1G = 0x4
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC1G_Trigger = 0x1
	// Position of CC2G field.
	TIM_EGR_CC2G_Pos = 0x3
	// Bit mask of CC2G field.
	TIM_EGR_CC2G_Msk = 0x8
	// Bit CC2G.
	TIM_EGR_CC2G = 0x8
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC2G_Trigger = 0x1
	// Position of CC3G field.
	TIM_EGR_CC3G_Pos = 0x4
	// Bit mask of CC3G field.
	TIM_EGR_CC3G_Msk = 0x10
	// Bit CC3G.
	TIM_EGR_CC3G = 0x10
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC3G_Trigger = 0x1
	// Position of CC4G field.
	TIM_EGR_CC4G_Pos = 0x5
	// Bit mask of CC4G field.
	TIM_EGR_CC4G_Msk = 0x20
	// Bit CC4G.
	TIM_EGR_CC4G = 0x20
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC4G_Trigger = 0x1
	// Position of TG field.
	TIM_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM_EGR_TG = 0x40
	// The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
	TIM_EGR_TG_Trigger = 0x1

	// CCMR1_Output: CCMR1 register
	// Position of CC1S field.
	TIM_CCMR1_Output_CC1S_Pos = 0x8
	// Bit mask of CC1S field.
	TIM_CCMR1_Output_CC1S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC1S_Output = 0x0
	// Position of CC2S field.
	TIM_CCMR1_Output_CC2S_Pos = 0x10
	// Bit mask of CC2S field.
	TIM_CCMR1_Output_CC2S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC2S_Output = 0x0
	// Position of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Pos = 0xa
	// Bit mask of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Msk = 0x400
	// Bit OC1FE.
	TIM_CCMR1_Output_OC1FE = 0x400
	// Fast output disabled
	TIM_CCMR1_Output_OC1FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC1FE_Enabled = 0x1
	// Position of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Pos = 0x12
	// Bit mask of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Msk = 0x40000
	// Bit OC2FE.
	TIM_CCMR1_Output_OC2FE = 0x40000
	// Fast output disabled
	TIM_CCMR1_Output_OC2FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC2FE_Enabled = 0x1
	// Position of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Pos = 0xb
	// Bit mask of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Msk = 0x800
	// Bit OC1PE.
	TIM_CCMR1_Output_OC1PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC1PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC1PE_Enabled = 0x1
	// Position of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Pos = 0x13
	// Bit mask of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Msk = 0x80000
	// Bit OC2PE.
	TIM_CCMR1_Output_OC2PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC2PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC2PE_Enabled = 0x1
	// Position of OC1M field.
	TIM_CCMR1_Output_OC1M_Pos = 0xc
	// Bit mask of OC1M field.
	TIM_CCMR1_Output_OC1M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC1M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC1M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC1M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC1M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC1M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC1M_PwmMode2 = 0x7
	// Position of OC2M field.
	TIM_CCMR1_Output_OC2M_Pos = 0x14
	// Bit mask of OC2M field.
	TIM_CCMR1_Output_OC2M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC2M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC2M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC2M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC2M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC2M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC2M_PwmMode2 = 0x7
	// Position of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Pos = 0xf
	// Bit mask of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Msk = 0x8000
	// Bit OC1CE.
	TIM_CCMR1_Output_OC1CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR1_Output_OC1CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR1_Output_OC1CE_Enabled = 0x1
	// Position of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Pos = 0x17
	// Bit mask of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Msk = 0x800000
	// Bit OC2CE.
	TIM_CCMR1_Output_OC2CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR1_Output_OC2CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR1_Output_OC2CE_Enabled = 0x1
	// Position of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Pos = 0x18
	// Bit mask of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Msk = 0x1000000
	// Bit OC1M_3.
	TIM_CCMR1_Output_OC1M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC1M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC1M_3_Extended = 0x1
	// Position of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Pos = 0x20
	// Bit mask of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Msk = 0x100000000
	// Bit OC2M_3.
	TIM_CCMR1_Output_OC2M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC2M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC2M_3_Extended = 0x1

	// CCMR1_Input
	// Position of CC1S field.
	TIM_CCMR1_Input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM_CCMR1_Input_CC1S_Msk = 0x3
	// CC1 channel is configured as input, IC1 is mapped on TI1
	TIM_CCMR1_Input_CC1S_TI1 = 0x1
	// CC1 channel is configured as input, IC1 is mapped on TI2
	TIM_CCMR1_Input_CC1S_TI2 = 0x2
	// CC1 channel is configured as input, IC1 is mapped on TRC
	TIM_CCMR1_Input_CC1S_TRC = 0x3
	// Position of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Pos = 0xa
	// Bit mask of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC1PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC1PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC1PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC1PSC_EightEvents = 0x3
	// Position of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Pos = 0x12
	// Bit mask of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC2PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC2PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC2PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC2PSC_EightEvents = 0x3
	// Position of IC1F field.
	TIM_CCMR1_Input_IC1F_Pos = 0xc
	// Bit mask of IC1F field.
	TIM_CCMR1_Input_IC1F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC1F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC1F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC1F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC1F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N8 = 0xf
	// Position of IC2F field.
	TIM_CCMR1_Input_IC2F_Pos = 0x14
	// Bit mask of IC2F field.
	TIM_CCMR1_Input_IC2F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC2F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC2F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC2F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC2F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N8 = 0xf
	// Position of CC2S field.
	TIM_CCMR1_Input_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM_CCMR1_Input_CC2S_Msk = 0x300
	// CC2 channel is configured as input, IC2 is mapped on TI2
	TIM_CCMR1_Input_CC2S_TI2 = 0x1
	// CC2 channel is configured as input, IC2 is mapped on TI1
	TIM_CCMR1_Input_CC2S_TI1 = 0x2
	// CC2 channel is configured as input, IC2 is mapped on TRC
	TIM_CCMR1_Input_CC2S_TRC = 0x3

	// CCMR2_Output: CCMR2 register
	// Position of CC3S field.
	TIM_CCMR2_Output_CC3S_Pos = 0x8
	// Bit mask of CC3S field.
	TIM_CCMR2_Output_CC3S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC3S_Output = 0x0
	// Position of CC4S field.
	TIM_CCMR2_Output_CC4S_Pos = 0x10
	// Bit mask of CC4S field.
	TIM_CCMR2_Output_CC4S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC4S_Output = 0x0
	// Position of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Pos = 0xa
	// Bit mask of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Msk = 0x400
	// Bit OC3FE.
	TIM_CCMR2_Output_OC3FE = 0x400
	// Fast output disabled
	TIM_CCMR2_Output_OC3FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC3FE_Enabled = 0x1
	// Position of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Pos = 0x12
	// Bit mask of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Msk = 0x40000
	// Bit OC4FE.
	TIM_CCMR2_Output_OC4FE = 0x40000
	// Fast output disabled
	TIM_CCMR2_Output_OC4FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC4FE_Enabled = 0x1
	// Position of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Pos = 0xb
	// Bit mask of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Msk = 0x800
	// Bit OC3PE.
	TIM_CCMR2_Output_OC3PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC3PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC3PE_Enabled = 0x1
	// Position of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Pos = 0x13
	// Bit mask of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Msk = 0x80000
	// Bit OC4PE.
	TIM_CCMR2_Output_OC4PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC4PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC4PE_Enabled = 0x1
	// Position of OC3M field.
	TIM_CCMR2_Output_OC3M_Pos = 0xc
	// Bit mask of OC3M field.
	TIM_CCMR2_Output_OC3M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC3M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC3M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC3M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC3M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC3M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC3M_PwmMode2 = 0x7
	// Position of OC4M field.
	TIM_CCMR2_Output_OC4M_Pos = 0x14
	// Bit mask of OC4M field.
	TIM_CCMR2_Output_OC4M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC4M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC4M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC4M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC4M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC4M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC4M_PwmMode2 = 0x7
	// Position of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Pos = 0xf
	// Bit mask of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Msk = 0x8000
	// Bit OC3CE.
	TIM_CCMR2_Output_OC3CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR2_Output_OC3CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR2_Output_OC3CE_Enabled = 0x1
	// Position of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Pos = 0x17
	// Bit mask of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Msk = 0x800000
	// Bit OC4CE.
	TIM_CCMR2_Output_OC4CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR2_Output_OC4CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR2_Output_OC4CE_Enabled = 0x1
	// Position of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Pos = 0x18
	// Bit mask of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Msk = 0x1000000
	// Bit OC3M_3.
	TIM_CCMR2_Output_OC3M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC3M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC3M_3_Extended = 0x1
	// Position of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Pos = 0x20
	// Bit mask of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Msk = 0x100000000
	// Bit OC4M_3.
	TIM_CCMR2_Output_OC4M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC4M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC4M_3_Extended = 0x1

	// CCMR2_Input
	// Position of CC3S field.
	TIM_CCMR2_Input_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM_CCMR2_Input_CC3S_Msk = 0x3
	// CC3 channel is configured as input, IC3 is mapped on TI3
	TIM_CCMR2_Input_CC3S_TI3 = 0x1
	// CC3 channel is configured as input, IC3 is mapped on TI4
	TIM_CCMR2_Input_CC3S_TI4 = 0x2
	// CC3 channel is configured as input, IC3 is mapped on TRC
	TIM_CCMR2_Input_CC3S_TRC = 0x3
	// Position of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Pos = 0xa
	// Bit mask of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC3PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC3PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC3PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC3PSC_EightEvents = 0x3
	// Position of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Pos = 0x12
	// Bit mask of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC4PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC4PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC4PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC4PSC_EightEvents = 0x3
	// Position of IC3F field.
	TIM_CCMR2_Input_IC3F_Pos = 0xc
	// Bit mask of IC3F field.
	TIM_CCMR2_Input_IC3F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC3F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC3F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC3F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC3F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N8 = 0xf
	// Position of IC4F field.
	TIM_CCMR2_Input_IC4F_Pos = 0x14
	// Bit mask of IC4F field.
	TIM_CCMR2_Input_IC4F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC4F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC4F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC4F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC4F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N8 = 0xf
	// Position of CC4S field.
	TIM_CCMR2_Input_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM_CCMR2_Input_CC4S_Msk = 0x300
	// CC4 channel is configured as input, IC4 is mapped on TI4
	TIM_CCMR2_Input_CC4S_TI4 = 0x1
	// CC4 channel is configured as input, IC4 is mapped on TI3
	TIM_CCMR2_Input_CC4S_TI3 = 0x2
	// CC4 channel is configured as input, IC4 is mapped on TRC
	TIM_CCMR2_Input_CC4S_TRC = 0x3

	// CCER: CCER register
	// Position of CC1E field.
	TIM_CCER_CC1E_Pos = 0x4
	// Bit mask of CC1E field.
	TIM_CCER_CC1E_Msk = 0x10
	// Bit CC1E.
	TIM_CCER_CC1E = 0x10
	// Capture disabled
	TIM_CCER_CC1E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC1E_Enabled = 0x1
	// Position of CC2E field.
	TIM_CCER_CC2E_Pos = 0x8
	// Bit mask of CC2E field.
	TIM_CCER_CC2E_Msk = 0x100
	// Bit CC2E.
	TIM_CCER_CC2E = 0x100
	// Capture disabled
	TIM_CCER_CC2E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC2E_Enabled = 0x1
	// Position of CC3E field.
	TIM_CCER_CC3E_Pos = 0xc
	// Bit mask of CC3E field.
	TIM_CCER_CC3E_Msk = 0x1000
	// Bit CC3E.
	TIM_CCER_CC3E = 0x1000
	// Capture disabled
	TIM_CCER_CC3E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC3E_Enabled = 0x1
	// Position of CC4E field.
	TIM_CCER_CC4E_Pos = 0x10
	// Bit mask of CC4E field.
	TIM_CCER_CC4E_Msk = 0x10000
	// Bit CC4E.
	TIM_CCER_CC4E = 0x10000
	// Capture disabled
	TIM_CCER_CC4E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC4E_Enabled = 0x1
	// Position of CC1P field.
	TIM_CCER_CC1P_Pos = 0x5
	// Bit mask of CC1P field.
	TIM_CCER_CC1P_Msk = 0x20
	// Bit CC1P.
	TIM_CCER_CC1P = 0x20
	// Noninverted/rising edge
	TIM_CCER_CC1P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC1P_FallingEdge = 0x1
	// Position of CC2P field.
	TIM_CCER_CC2P_Pos = 0x9
	// Bit mask of CC2P field.
	TIM_CCER_CC2P_Msk = 0x200
	// Bit CC2P.
	TIM_CCER_CC2P = 0x200
	// Noninverted/rising edge
	TIM_CCER_CC2P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC2P_FallingEdge = 0x1
	// Position of CC3P field.
	TIM_CCER_CC3P_Pos = 0xd
	// Bit mask of CC3P field.
	TIM_CCER_CC3P_Msk = 0x2000
	// Bit CC3P.
	TIM_CCER_CC3P = 0x2000
	// Noninverted/rising edge
	TIM_CCER_CC3P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC3P_FallingEdge = 0x1
	// Position of CC4P field.
	TIM_CCER_CC4P_Pos = 0x11
	// Bit mask of CC4P field.
	TIM_CCER_CC4P_Msk = 0x20000
	// Bit CC4P.
	TIM_CCER_CC4P = 0x20000
	// Noninverted/rising edge
	TIM_CCER_CC4P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC4P_FallingEdge = 0x1
	// Position of CC1NP field.
	TIM_CCER_CC1NP_Pos = 0x7
	// Bit mask of CC1NP field.
	TIM_CCER_CC1NP_Msk = 0x80
	// Bit CC1NP.
	TIM_CCER_CC1NP = 0x80
	// Position of CC2NP field.
	TIM_CCER_CC2NP_Pos = 0xb
	// Bit mask of CC2NP field.
	TIM_CCER_CC2NP_Msk = 0x800
	// Bit CC2NP.
	TIM_CCER_CC2NP = 0x800
	// Position of CC3NP field.
	TIM_CCER_CC3NP_Pos = 0xf
	// Bit mask of CC3NP field.
	TIM_CCER_CC3NP_Msk = 0x8000
	// Bit CC3NP.
	TIM_CCER_CC3NP = 0x8000
	// Position of CC4NP field.
	TIM_CCER_CC4NP_Pos = 0x13
	// Bit mask of CC4NP field.
	TIM_CCER_CC4NP_Msk = 0x80000
	// Bit CC4NP.
	TIM_CCER_CC4NP = 0x80000

	// CNT: CNT register
	// Position of CNT field.
	TIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT_CNT_Msk = 0xffff
	// Position of UIF_CPY field.
	TIM_CNT_UIF_CPY_Pos = 0x1f
	// Bit mask of UIF_CPY field.
	TIM_CNT_UIF_CPY_Msk = 0x80000000
	// Bit UIF_CPY.
	TIM_CNT_UIF_CPY = 0x80000000

	// CNT32: 32-bit counter register
	// Position of CNT field.
	TIM_CNT32_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT32_CNT_Msk = 0xffffffff

	// PSC: PSC register
	// Position of PSC field.
	TIM_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM_PSC_PSC_Msk = 0xffff

	// ARR: ARR register
	// Position of ARR field.
	TIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM_ARR_ARR_Msk = 0xffff

	// RCR: RCR register
	// Position of REP field.
	TIM_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM_RCR_REP_Msk = 0xff

	// CCR1: capture/compare register
	// Position of CCR field.
	TIM_CCR_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR_CCR_Msk = 0xffff

	// DCR: DCR register
	// Position of DBA field.
	TIM_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM_DCR_DBA_Msk = 0x1f
	// Position of DBL field.
	TIM_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM_DCR_DBL_Msk = 0x1f00

	// DMAR: DMAR register
	// Position of DMAB field.
	TIM_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM_DMAR_DMAB_Msk = 0xffff

	// TISEL: TISEL register
	// Position of TI1SEL field.
	TIM_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM_TISEL_TI1SEL_Msk = 0xf
	// Position of TI2SEL field.
	TIM_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIM_TISEL_TI2SEL_Msk = 0xf00
	// Position of TI3SEL field.
	TIM_TISEL_TI3SEL_Pos = 0x10
	// Bit mask of TI3SEL field.
	TIM_TISEL_TI3SEL_Msk = 0xf0000
	// Position of TI4SEL field.
	TIM_TISEL_TI4SEL_Pos = 0x18
	// Bit mask of TI4SEL field.
	TIM_TISEL_TI4SEL_Msk = 0xf000000
)

// Constants for USART
const (
	// CR1: CR1 register
	// Position of UE field.
	USART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	USART_CR1_UE_Msk = 0x1
	// Bit UE.
	USART_CR1_UE = 0x1
	// UART is disabled
	USART_CR1_UE_Disabled = 0x0
	// UART is enabled
	USART_CR1_UE_Enabled = 0x1
	// Position of RE field.
	USART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	USART_CR1_RE_Msk = 0x4
	// Bit RE.
	USART_CR1_RE = 0x4
	// Receiver is disabled
	USART_CR1_RE_Disabled = 0x0
	// Receiver is enabled
	USART_CR1_RE_Enabled = 0x1
	// Position of TE field.
	USART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	USART_CR1_TE_Msk = 0x8
	// Bit TE.
	USART_CR1_TE = 0x8
	// Transmitter is disabled
	USART_CR1_TE_Disabled = 0x0
	// Transmitter is enabled
	USART_CR1_TE_Enabled = 0x1
	// Position of IDLEIE field.
	USART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	USART_CR1_IDLEIE = 0x10
	// Interrupt is disabled
	USART_CR1_IDLEIE_Disabled = 0x0
	// Interrupt is generated whenever IDLE=1 in the ISR register
	USART_CR1_IDLEIE_Enabled = 0x1
	// Position of RXNEIE field.
	USART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	USART_CR1_RXNEIE = 0x20
	// Interrupt is disabled
	USART_CR1_RXNEIE_Disabled = 0x0
	// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
	USART_CR1_RXNEIE_Enabled = 0x1
	// Position of TCIE field.
	USART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	USART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	USART_CR1_TCIE = 0x40
	// Interrupt is disabled
	USART_CR1_TCIE_Disabled = 0x0
	// Interrupt is generated whenever TC=1 in the ISR register
	USART_CR1_TCIE_Enabled = 0x1
	// Position of TXEIE field.
	USART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	USART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	USART_CR1_TXEIE = 0x80
	// Interrupt is disabled
	USART_CR1_TXEIE_Disabled = 0x0
	// Interrupt is generated whenever TXE=1 in the ISR register
	USART_CR1_TXEIE_Enabled = 0x1
	// Position of PEIE field.
	USART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	USART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	USART_CR1_PEIE = 0x100
	// Interrupt is disabled
	USART_CR1_PEIE_Disabled = 0x0
	// Interrupt is generated whenever PE=1 in the ISR register
	USART_CR1_PEIE_Enabled = 0x1
	// Position of PS field.
	USART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	USART_CR1_PS_Msk = 0x200
	// Bit PS.
	USART_CR1_PS = 0x200
	// Even parity
	USART_CR1_PS_Even = 0x0
	// Odd parity
	USART_CR1_PS_Odd = 0x1
	// Position of PCE field.
	USART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	USART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	USART_CR1_PCE = 0x400
	// Parity control disabled
	USART_CR1_PCE_Disabled = 0x0
	// Parity control enabled
	USART_CR1_PCE_Enabled = 0x1
	// Position of WAKE field.
	USART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	USART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	USART_CR1_WAKE = 0x800
	// Idle line
	USART_CR1_WAKE_Idle = 0x0
	// Address mask
	USART_CR1_WAKE_Address = 0x1
	// Position of M0 field.
	USART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	USART_CR1_M0_Msk = 0x1000
	// Bit M0.
	USART_CR1_M0 = 0x1000
	// 1 start bit, 8 data bits, n stop bits
	USART_CR1_M0_Bit8 = 0x0
	// 1 start bit, 9 data bits, n stop bits
	USART_CR1_M0_Bit9 = 0x1
	// Position of MME field.
	USART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	USART_CR1_MME_Msk = 0x2000
	// Bit MME.
	USART_CR1_MME = 0x2000
	// Receiver in active mode permanently
	USART_CR1_MME_Disabled = 0x0
	// Receiver can switch between mute mode and active mode
	USART_CR1_MME_Enabled = 0x1
	// Position of CMIE field.
	USART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	USART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	USART_CR1_CMIE = 0x4000
	// Interrupt is disabled
	USART_CR1_CMIE_Disabled = 0x0
	// Interrupt is generated when the CMF bit is set in the ISR register
	USART_CR1_CMIE_Enabled = 0x1
	// Position of OVER8 field.
	USART_CR1_OVER8_Pos = 0xf
	// Bit mask of OVER8 field.
	USART_CR1_OVER8_Msk = 0x8000
	// Bit OVER8.
	USART_CR1_OVER8 = 0x8000
	// Oversampling by 16
	USART_CR1_OVER8_Oversampling16 = 0x0
	// Oversampling by 8
	USART_CR1_OVER8_Oversampling8 = 0x1
	// Position of DEDT field.
	USART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	USART_CR1_DEDT_Msk = 0x1f0000
	// Position of DEAT field.
	USART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	USART_CR1_DEAT_Msk = 0x3e00000
	// Position of RTOIE field.
	USART_CR1_RTOIE_Pos = 0x1a
	// Bit mask of RTOIE field.
	USART_CR1_RTOIE_Msk = 0x4000000
	// Bit RTOIE.
	USART_CR1_RTOIE = 0x4000000
	// Interrupt is inhibited
	USART_CR1_RTOIE_Disabled = 0x0
	// An USART interrupt is generated when the RTOF bit is set in the ISR register
	USART_CR1_RTOIE_Enabled = 0x1
	// Position of EOBIE field.
	USART_CR1_EOBIE_Pos = 0x1b
	// Bit mask of EOBIE field.
	USART_CR1_EOBIE_Msk = 0x8000000
	// Bit EOBIE.
	USART_CR1_EOBIE = 0x8000000
	// Interrupt is inhibited
	USART_CR1_EOBIE_Disabled = 0x0
	// A USART interrupt is generated when the EOBF flag is set in the ISR register
	USART_CR1_EOBIE_Enabled = 0x1
	// Position of M1 field.
	USART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	USART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	USART_CR1_M1 = 0x10000000
	// Use M0 to set the data bits
	USART_CR1_M1_M0 = 0x0
	// 1 start bit, 7 data bits, n stop bits
	USART_CR1_M1_Bit7 = 0x1
	// Position of FIFOEN field.
	USART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	USART_CR1_FIFOEN = 0x20000000
	// FIFO mode is disabled
	USART_CR1_FIFOEN_Disabled = 0x0
	// FIFO mode is enabled
	USART_CR1_FIFOEN_Enabled = 0x1
	// Position of TXFEIE field.
	USART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	USART_CR1_TXFEIE = 0x40000000
	// Interrupt inhibited
	USART_CR1_TXFEIE_Disabled = 0x0
	// USART interrupt generated when TXFE = 1 in the USART_ISR register
	USART_CR1_TXFEIE_Enabled = 0x1
	// Position of RXFFIE field.
	USART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	USART_CR1_RXFFIE = 0x80000000
	// Interrupt inhibited
	USART_CR1_RXFFIE_Disabled = 0x0
	// USART interrupt generated when RXFF = 1 in the USART_ISR register
	USART_CR1_RXFFIE_Enabled = 0x1

	// CR2: CR2 register
	// Position of SLVEN field.
	USART_CR2_SLVEN_Pos = 0x0
	// Bit mask of SLVEN field.
	USART_CR2_SLVEN_Msk = 0x1
	// Bit SLVEN.
	USART_CR2_SLVEN = 0x1
	// Slave mode disabled
	USART_CR2_SLVEN_Disabled = 0x0
	// Slave mode enabled
	USART_CR2_SLVEN_Enabled = 0x1
	// Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Pos = 0x3
	// Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk = 0x8
	// Bit DIS_NSS.
	USART_CR2_DIS_NSS = 0x8
	// SPI slave selection depends on NSS input pin
	USART_CR2_DIS_NSS_Disabled = 0x0
	// SPI slave is always selected and NSS input pin is ignored
	USART_CR2_DIS_NSS_Enabled = 0x1
	// Position of ADDM7 field.
	USART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	USART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	USART_CR2_ADDM7 = 0x10
	// 4-bit address detection
	USART_CR2_ADDM7_Bit4 = 0x0
	// 7-bit address detection
	USART_CR2_ADDM7_Bit7 = 0x1
	// Position of LBDL field.
	USART_CR2_LBDL_Pos = 0x5
	// Bit mask of LBDL field.
	USART_CR2_LBDL_Msk = 0x20
	// Bit LBDL.
	USART_CR2_LBDL = 0x20
	// 10-bit break detection
	USART_CR2_LBDL_Bit10 = 0x0
	// 11-bit break detection
	USART_CR2_LBDL_Bit11 = 0x1
	// Position of LBDIE field.
	USART_CR2_LBDIE_Pos = 0x6
	// Bit mask of LBDIE field.
	USART_CR2_LBDIE_Msk = 0x40
	// Bit LBDIE.
	USART_CR2_LBDIE = 0x40
	// Interrupt is inhibited
	USART_CR2_LBDIE_Disabled = 0x0
	// An interrupt is generated whenever LBDF=1 in the ISR register
	USART_CR2_LBDIE_Enabled = 0x1
	// Position of LBCL field.
	USART_CR2_LBCL_Pos = 0x8
	// Bit mask of LBCL field.
	USART_CR2_LBCL_Msk = 0x100
	// Bit LBCL.
	USART_CR2_LBCL = 0x100
	// The clock pulse of the last data bit is not output to the CK pin
	USART_CR2_LBCL_NotOutput = 0x0
	// The clock pulse of the last data bit is output to the CK pin
	USART_CR2_LBCL_Output = 0x1
	// Position of CPHA field.
	USART_CR2_CPHA_Pos = 0x9
	// Bit mask of CPHA field.
	USART_CR2_CPHA_Msk = 0x200
	// Bit CPHA.
	USART_CR2_CPHA = 0x200
	// The first clock transition is the first data capture edge
	USART_CR2_CPHA_First = 0x0
	// The second clock transition is the first data capture edge
	USART_CR2_CPHA_Second = 0x1
	// Position of CPOL field.
	USART_CR2_CPOL_Pos = 0xa
	// Bit mask of CPOL field.
	USART_CR2_CPOL_Msk = 0x400
	// Bit CPOL.
	USART_CR2_CPOL = 0x400
	// Steady low value on CK pin outside transmission window
	USART_CR2_CPOL_Low = 0x0
	// Steady high value on CK pin outside transmission window
	USART_CR2_CPOL_High = 0x1
	// Position of CLKEN field.
	USART_CR2_CLKEN_Pos = 0xb
	// Bit mask of CLKEN field.
	USART_CR2_CLKEN_Msk = 0x800
	// Bit CLKEN.
	USART_CR2_CLKEN = 0x800
	// CK pin disabled
	USART_CR2_CLKEN_Disabled = 0x0
	// CK pin enabled
	USART_CR2_CLKEN_Enabled = 0x1
	// Position of STOP field.
	USART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	USART_CR2_STOP_Msk = 0x3000
	// 1 stop bit
	USART_CR2_STOP_Stop1 = 0x0
	// 0.5 stop bit
	USART_CR2_STOP_Stop0p5 = 0x1
	// 2 stop bit
	USART_CR2_STOP_Stop2 = 0x2
	// 1.5 stop bit
	USART_CR2_STOP_Stop1p5 = 0x3
	// Position of LINEN field.
	USART_CR2_LINEN_Pos = 0xe
	// Bit mask of LINEN field.
	USART_CR2_LINEN_Msk = 0x4000
	// Bit LINEN.
	USART_CR2_LINEN = 0x4000
	// LIN mode disabled
	USART_CR2_LINEN_Disabled = 0x0
	// LIN mode enabled
	USART_CR2_LINEN_Enabled = 0x1
	// Position of SWAP field.
	USART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	USART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	USART_CR2_SWAP = 0x8000
	// TX/RX pins are used as defined in standard pinout
	USART_CR2_SWAP_Standard = 0x0
	// The TX and RX pins functions are swapped
	USART_CR2_SWAP_Swapped = 0x1
	// Position of RXINV field.
	USART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	USART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	USART_CR2_RXINV = 0x10000
	// RX pin signal works using the standard logic levels
	USART_CR2_RXINV_Standard = 0x0
	// RX pin signal values are inverted
	USART_CR2_RXINV_Inverted = 0x1
	// Position of TXINV field.
	USART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	USART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	USART_CR2_TXINV = 0x20000
	// TX pin signal works using the standard logic levels
	USART_CR2_TXINV_Standard = 0x0
	// TX pin signal values are inverted
	USART_CR2_TXINV_Inverted = 0x1
	// Position of DATAINV field.
	USART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	USART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	USART_CR2_DATAINV = 0x40000
	// Logical data from the data register are send/received in positive/direct logic
	USART_CR2_DATAINV_Positive = 0x0
	// Logical data from the data register are send/received in negative/inverse logic
	USART_CR2_DATAINV_Negative = 0x1
	// Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	USART_CR2_MSBFIRST = 0x80000
	// data is transmitted/received with data bit 0 first, following the start bit
	USART_CR2_MSBFIRST_LSB = 0x0
	// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
	USART_CR2_MSBFIRST_MSB = 0x1
	// Position of ABREN field.
	USART_CR2_ABREN_Pos = 0x14
	// Bit mask of ABREN field.
	USART_CR2_ABREN_Msk = 0x100000
	// Bit ABREN.
	USART_CR2_ABREN = 0x100000
	// Auto baud rate detection is disabled
	USART_CR2_ABREN_Disabled = 0x0
	// Auto baud rate detection is enabled
	USART_CR2_ABREN_Enabled = 0x1
	// Position of ABRMOD field.
	USART_CR2_ABRMOD_Pos = 0x15
	// Bit mask of ABRMOD field.
	USART_CR2_ABRMOD_Msk = 0x600000
	// Measurement of the start bit is used to detect the baud rate
	USART_CR2_ABRMOD_Start = 0x0
	// Falling edge to falling edge measurement
	USART_CR2_ABRMOD_Edge = 0x1
	// 0x7F frame detection
	USART_CR2_ABRMOD_Frame7F = 0x2
	// 0x55 frame detection
	USART_CR2_ABRMOD_Frame55 = 0x3
	// Position of RTOEN field.
	USART_CR2_RTOEN_Pos = 0x17
	// Bit mask of RTOEN field.
	USART_CR2_RTOEN_Msk = 0x800000
	// Bit RTOEN.
	USART_CR2_RTOEN = 0x800000
	// Receiver timeout feature disabled
	USART_CR2_RTOEN_Disabled = 0x0
	// Receiver timeout feature enabled
	USART_CR2_RTOEN_Enabled = 0x1
	// Position of ADD field.
	USART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	USART_CR2_ADD_Msk = 0xff000000

	// CR3: CR3 register
	// Position of EIE field.
	USART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	USART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	USART_CR3_EIE = 0x1
	// Interrupt is inhibited
	USART_CR3_EIE_Disabled = 0x0
	// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
	USART_CR3_EIE_Enabled = 0x1
	// Position of IREN field.
	USART_CR3_IREN_Pos = 0x1
	// Bit mask of IREN field.
	USART_CR3_IREN_Msk = 0x2
	// Bit IREN.
	USART_CR3_IREN = 0x2
	// IrDA disabled
	USART_CR3_IREN_Disabled = 0x0
	// IrDA enabled
	USART_CR3_IREN_Enabled = 0x1
	// Position of IRLP field.
	USART_CR3_IRLP_Pos = 0x2
	// Bit mask of IRLP field.
	USART_CR3_IRLP_Msk = 0x4
	// Bit IRLP.
	USART_CR3_IRLP = 0x4
	// Normal mode
	USART_CR3_IRLP_Normal = 0x0
	// Low-power mode
	USART_CR3_IRLP_LowPower = 0x1
	// Position of HDSEL field.
	USART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	USART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	USART_CR3_HDSEL = 0x8
	// Half duplex mode is not selected
	USART_CR3_HDSEL_NotSelected = 0x0
	// Half duplex mode is selected
	USART_CR3_HDSEL_Selected = 0x1
	// Position of NACK field.
	USART_CR3_NACK_Pos = 0x4
	// Bit mask of NACK field.
	USART_CR3_NACK_Msk = 0x10
	// Bit NACK.
	USART_CR3_NACK = 0x10
	// NACK transmission in case of parity error is disabled
	USART_CR3_NACK_Disabled = 0x0
	// NACK transmission during parity error is enabled
	USART_CR3_NACK_Enabled = 0x1
	// Position of SCEN field.
	USART_CR3_SCEN_Pos = 0x5
	// Bit mask of SCEN field.
	USART_CR3_SCEN_Msk = 0x20
	// Bit SCEN.
	USART_CR3_SCEN = 0x20
	// Smartcard Mode disabled
	USART_CR3_SCEN_Disabled = 0x0
	// Smartcard Mode enabled
	USART_CR3_SCEN_Enabled = 0x1
	// Position of DMAR field.
	USART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	USART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	USART_CR3_DMAR = 0x40
	// DMA mode is disabled for reception
	USART_CR3_DMAR_Disabled = 0x0
	// DMA mode is enabled for reception
	USART_CR3_DMAR_Enabled = 0x1
	// Position of DMAT field.
	USART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	USART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	USART_CR3_DMAT = 0x80
	// DMA mode is disabled for transmission
	USART_CR3_DMAT_Disabled = 0x0
	// DMA mode is enabled for transmission
	USART_CR3_DMAT_Enabled = 0x1
	// Position of RTSE field.
	USART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	USART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	USART_CR3_RTSE = 0x100
	// RTS hardware flow control disabled
	USART_CR3_RTSE_Disabled = 0x0
	// RTS output enabled, data is only requested when there is space in the receive buffer
	USART_CR3_RTSE_Enabled = 0x1
	// Position of CTSE field.
	USART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	USART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	USART_CR3_CTSE = 0x200
	// CTS hardware flow control disabled
	USART_CR3_CTSE_Disabled = 0x0
	// CTS mode enabled, data is only transmitted when the CTS input is asserted
	USART_CR3_CTSE_Enabled = 0x1
	// Position of CTSIE field.
	USART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	USART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	USART_CR3_CTSIE = 0x400
	// Interrupt is inhibited
	USART_CR3_CTSIE_Disabled = 0x0
	// An interrupt is generated whenever CTSIF=1 in the ISR register
	USART_CR3_CTSIE_Enabled = 0x1
	// Position of ONEBIT field.
	USART_CR3_ONEBIT_Pos = 0xb
	// Bit mask of ONEBIT field.
	USART_CR3_ONEBIT_Msk = 0x800
	// Bit ONEBIT.
	USART_CR3_ONEBIT = 0x800
	// Three sample bit method
	USART_CR3_ONEBIT_Sample3 = 0x0
	// One sample bit method
	USART_CR3_ONEBIT_Sample1 = 0x1
	// Position of OVRDIS field.
	USART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	USART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	USART_CR3_OVRDIS = 0x1000
	// Overrun Error Flag, ORE, is set when received data is not read before receiving new data
	USART_CR3_OVRDIS_Enabled = 0x0
	// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
	USART_CR3_OVRDIS_Disabled = 0x1
	// Position of DDRE field.
	USART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	USART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	USART_CR3_DDRE = 0x2000
	// DMA is not disabled in case of reception error
	USART_CR3_DDRE_NotDisabled = 0x0
	// DMA is disabled following a reception error
	USART_CR3_DDRE_Disabled = 0x1
	// Position of DEM field.
	USART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	USART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	USART_CR3_DEM = 0x4000
	// DE function is disabled
	USART_CR3_DEM_Disabled = 0x0
	// The DE signal is output on the RTS pin
	USART_CR3_DEM_Enabled = 0x1
	// Position of DEP field.
	USART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	USART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	USART_CR3_DEP = 0x8000
	// DE signal is active high
	USART_CR3_DEP_High = 0x0
	// DE signal is active low
	USART_CR3_DEP_Low = 0x1
	// Position of SCARCNT field.
	USART_CR3_SCARCNT_Pos = 0x11
	// Bit mask of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000
	// Position of TXFTIE field.
	USART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	USART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	USART_CR3_TXFTIE = 0x800000
	// Interrupt inhibited
	USART_CR3_TXFTIE_Disabled = 0x0
	// USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
	USART_CR3_TXFTIE_Enabled = 0x1
	// Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Pos = 0x18
	// Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000
	// Bit TCBGTIE.
	USART_CR3_TCBGTIE = 0x1000000
	// Interrupt inhibited
	USART_CR3_TCBGTIE_Disabled = 0x0
	// USART interrupt generated whenever TCBGT=1 in the USART_ISR register
	USART_CR3_TCBGTIE_Enabled = 0x1
	// Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000
	// RXFIFO reaches 1/8 of its depth
	USART_CR3_RXFTCFG_Depth_1_8 = 0x0
	// RXFIFO reaches 1/4 of its depth
	USART_CR3_RXFTCFG_Depth_1_4 = 0x1
	// RXFIFO reaches 1/2 of its depth
	USART_CR3_RXFTCFG_Depth_1_2 = 0x2
	// RXFIFO reaches 3/4 of its depth
	USART_CR3_RXFTCFG_Depth_3_4 = 0x3
	// RXFIFO reaches 7/8 of its depth
	USART_CR3_RXFTCFG_Depth_7_8 = 0x4
	// RXFIFO becomes full
	USART_CR3_RXFTCFG_Full = 0x5
	// Position of RXFTIE field.
	USART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	USART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	USART_CR3_RXFTIE = 0x10000000
	// Interrupt inhibited
	USART_CR3_RXFTIE_Disabled = 0x0
	// USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
	USART_CR3_RXFTIE_Enabled = 0x1
	// Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000
	// TXFIFO reaches 1/8 of its depth
	USART_CR3_TXFTCFG_Depth_1_8 = 0x0
	// TXFIFO reaches 1/4 of its depth
	USART_CR3_TXFTCFG_Depth_1_4 = 0x1
	// TXFIFO reaches 1/2 of its depth
	USART_CR3_TXFTCFG_Depth_1_2 = 0x2
	// TXFIFO reaches 3/4 of its depth
	USART_CR3_TXFTCFG_Depth_3_4 = 0x3
	// TXFIFO reaches 7/8 of its depth
	USART_CR3_TXFTCFG_Depth_7_8 = 0x4
	// TXFIFO becomes empty
	USART_CR3_TXFTCFG_Empty = 0x5

	// BRR: BRR register
	// Position of BRR field.
	USART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	USART_BRR_BRR_Msk = 0xffff

	// GTPR: GTPR register
	// Position of PSC field.
	USART_GTPR_PSC_Pos = 0x0
	// Bit mask of PSC field.
	USART_GTPR_PSC_Msk = 0xff
	// Position of GT field.
	USART_GTPR_GT_Pos = 0x8
	// Bit mask of GT field.
	USART_GTPR_GT_Msk = 0xff00

	// RTOR: RTOR register
	// Position of RTO field.
	USART_RTOR_RTO_Pos = 0x0
	// Bit mask of RTO field.
	USART_RTOR_RTO_Msk = 0xffffff
	// Position of BLEN field.
	USART_RTOR_BLEN_Pos = 0x18
	// Bit mask of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000

	// RQR: RQR register
	// Position of ABRRQ field.
	USART_RQR_ABRRQ_Pos = 0x0
	// Bit mask of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1
	// Bit ABRRQ.
	USART_RQR_ABRRQ = 0x1
	// resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
	USART_RQR_ABRRQ_Request = 0x1
	// Position of SBKRQ field.
	USART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	USART_RQR_SBKRQ = 0x2
	// sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
	USART_RQR_SBKRQ_Break = 0x1
	// Position of MMRQ field.
	USART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	USART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	USART_RQR_MMRQ = 0x4
	// Puts the USART in mute mode and sets the RWU flag
	USART_RQR_MMRQ_Mute = 0x1
	// Position of RXFRQ field.
	USART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	USART_RQR_RXFRQ = 0x8
	// clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
	USART_RQR_RXFRQ_Discard = 0x1
	// Position of TXFRQ field.
	USART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	USART_RQR_TXFRQ = 0x10
	// Set the TXE flags. This allows to discard the transmit data
	USART_RQR_TXFRQ_Discard = 0x1

	// ISR: ISR register
	// Position of PE field.
	USART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	USART_ISR_PE_Msk = 0x1
	// Bit PE.
	USART_ISR_PE = 0x1
	// No parity error
	USART_ISR_PE_NoError = 0x0
	// Parity error
	USART_ISR_PE_Error = 0x1
	// Position of FE field.
	USART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	USART_ISR_FE_Msk = 0x2
	// Bit FE.
	USART_ISR_FE = 0x2
	// No Framing error is detected
	USART_ISR_FE_NoError = 0x0
	// Framing error or break character is detected
	USART_ISR_FE_Error = 0x1
	// Position of NF field.
	USART_ISR_NF_Pos = 0x2
	// Bit mask of NF field.
	USART_ISR_NF_Msk = 0x4
	// Bit NF.
	USART_ISR_NF = 0x4
	// No noise is detected
	USART_ISR_NF_NoNoise = 0x0
	// Noise is detected
	USART_ISR_NF_Noise = 0x1
	// Position of ORE field.
	USART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	USART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	USART_ISR_ORE = 0x8
	// No Overrun error
	USART_ISR_ORE_NoOverrun = 0x0
	// Overrun error is detected
	USART_ISR_ORE_Overrun = 0x1
	// Position of IDLE field.
	USART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	USART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	USART_ISR_IDLE = 0x10
	// No Idle Line is detected
	USART_ISR_IDLE_NoIdle = 0x0
	// Idle Line is detected
	USART_ISR_IDLE_Idle = 0x1
	// Position of RXNE field.
	USART_ISR_RXNE_Pos = 0x5
	// Bit mask of RXNE field.
	USART_ISR_RXNE_Msk = 0x20
	// Bit RXNE.
	USART_ISR_RXNE = 0x20
	// Data is not received
	USART_ISR_RXNE_NoData = 0x0
	// Received data is ready to be read
	USART_ISR_RXNE_DataReady = 0x1
	// Position of TC field.
	USART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	USART_ISR_TC_Msk = 0x40
	// Bit TC.
	USART_ISR_TC = 0x40
	// Transmission is not complete
	USART_ISR_TC_TxNotComplete = 0x0
	// Transmission is complete
	USART_ISR_TC_TxComplete = 0x1
	// Position of TXE field.
	USART_ISR_TXE_Pos = 0x7
	// Bit mask of TXE field.
	USART_ISR_TXE_Msk = 0x80
	// Bit TXE.
	USART_ISR_TXE = 0x80
	// Bit TXFNF. (added by gen-device-svd)
	USART_ISR_TXFNF = 0x80
	// Transmit FIFO is full
	USART_ISR_TXE_Full = 0x0
	// Transmit FIFO is not full
	USART_ISR_TXE_NotFull = 0x1
	// Position of LBDF field.
	USART_ISR_LBDF_Pos = 0x8
	// Bit mask of LBDF field.
	USART_ISR_LBDF_Msk = 0x100
	// Bit LBDF.
	USART_ISR_LBDF = 0x100
	// LIN break not detected
	USART_ISR_LBDF_NotDetected = 0x0
	// LIN break detected
	USART_ISR_LBDF_Detected = 0x1
	// Position of CTSIF field.
	USART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	USART_ISR_CTSIF = 0x200
	// No change occurred on the CTS status line
	USART_ISR_CTSIF_NotChanged = 0x0
	// A change occurred on the CTS status line
	USART_ISR_CTSIF_Changed = 0x1
	// Position of CTS field.
	USART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	USART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	USART_ISR_CTS = 0x400
	// CTS line set
	USART_ISR_CTS_Set = 0x0
	// CTS line reset
	USART_ISR_CTS_Reset = 0x1
	// Position of RTOF field.
	USART_ISR_RTOF_Pos = 0xb
	// Bit mask of RTOF field.
	USART_ISR_RTOF_Msk = 0x800
	// Bit RTOF.
	USART_ISR_RTOF = 0x800
	// Timeout value not reached
	USART_ISR_RTOF_NotReached = 0x0
	// Timeout value reached without any data reception
	USART_ISR_RTOF_Reached = 0x1
	// Position of EOBF field.
	USART_ISR_EOBF_Pos = 0xc
	// Bit mask of EOBF field.
	USART_ISR_EOBF_Msk = 0x1000
	// Bit EOBF.
	USART_ISR_EOBF = 0x1000
	// End of Block not reached
	USART_ISR_EOBF_NotReached = 0x0
	// End of Block (number of characters) reached
	USART_ISR_EOBF_Reached = 0x1
	// Position of UDR field.
	USART_ISR_UDR_Pos = 0xd
	// Bit mask of UDR field.
	USART_ISR_UDR_Msk = 0x2000
	// Bit UDR.
	USART_ISR_UDR = 0x2000
	// No underrun error
	USART_ISR_UDR_NoUnderrun = 0x0
	// underrun error
	USART_ISR_UDR_Underrun = 0x1
	// Position of ABRE field.
	USART_ISR_ABRE_Pos = 0xe
	// Bit mask of ABRE field.
	USART_ISR_ABRE_Msk = 0x4000
	// Bit ABRE.
	USART_ISR_ABRE = 0x4000
	// Position of ABRF field.
	USART_ISR_ABRF_Pos = 0xf
	// Bit mask of ABRF field.
	USART_ISR_ABRF_Msk = 0x8000
	// Bit ABRF.
	USART_ISR_ABRF = 0x8000
	// Position of BUSY field.
	USART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	USART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	USART_ISR_BUSY = 0x10000
	// USART is idle (no reception)
	USART_ISR_BUSY_Idle = 0x0
	// Reception on going
	USART_ISR_BUSY_Busy = 0x1
	// Position of CMF field.
	USART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	USART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	USART_ISR_CMF = 0x20000
	// No Character match detected
	USART_ISR_CMF_NoMatch = 0x0
	// Character match detected
	USART_ISR_CMF_Match = 0x1
	// Position of SBKF field.
	USART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	USART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	USART_ISR_SBKF = 0x40000
	// No break character transmitted
	USART_ISR_SBKF_NoBreak = 0x0
	// Break character transmitted
	USART_ISR_SBKF_Break = 0x1
	// Position of RWU field.
	USART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	USART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	USART_ISR_RWU = 0x80000
	// Position of TEACK field.
	USART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	USART_ISR_TEACK = 0x200000
	// Position of REACK field.
	USART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	USART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	USART_ISR_REACK = 0x400000
	// Position of TXFE field.
	USART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	USART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	USART_ISR_TXFE = 0x800000
	// TXFIFO not empty.
	USART_ISR_TXFE_NotEmpty = 0x0
	// TXFIFO empty.
	USART_ISR_TXFE_Empty = 0x1
	// Position of RXFF field.
	USART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	USART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	USART_ISR_RXFF = 0x1000000
	// RXFIFO not full.
	USART_ISR_RXFF_NotFull = 0x0
	// RXFIFO Full.
	USART_ISR_RXFF_Full = 0x1
	// Position of TCBGT field.
	USART_ISR_TCBGT_Pos = 0x19
	// Bit mask of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000
	// Bit TCBGT.
	USART_ISR_TCBGT = 0x2000000
	// Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
	USART_ISR_TCBGT_NotCompleted = 0x0
	// Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
	USART_ISR_TCBGT_Completed = 0x1
	// Position of RXFT field.
	USART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	USART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	USART_ISR_RXFT = 0x4000000
	// Receive FIFO does not reach the programmed threshold.
	USART_ISR_RXFT_NotReached = 0x0
	// Receive FIFO reached the programmed threshold.
	USART_ISR_RXFT_Reached = 0x1
	// Position of TXFT field.
	USART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	USART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	USART_ISR_TXFT = 0x8000000
	// TXFIFO does not reach the programmed threshold.
	USART_ISR_TXFT_NotReached = 0x0
	// TXFIFO reached the programmed threshold.
	USART_ISR_TXFT_Reached = 0x1

	// ICR: ICR register
	// Position of PECF field.
	USART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	USART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	USART_ICR_PECF = 0x1
	// Clears the PE flag in the ISR register
	USART_ICR_PECF_Clear = 0x1
	// Position of FECF field.
	USART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	USART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	USART_ICR_FECF = 0x2
	// Clears the FE flag in the ISR register
	USART_ICR_FECF_Clear = 0x1
	// Position of NECF field.
	USART_ICR_NECF_Pos = 0x2
	// Bit mask of NECF field.
	USART_ICR_NECF_Msk = 0x4
	// Bit NECF.
	USART_ICR_NECF = 0x4
	// Clears the NF flag in the ISR register
	USART_ICR_NECF_Clear = 0x1
	// Position of ORECF field.
	USART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	USART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	USART_ICR_ORECF = 0x8
	// Clears the ORE flag in the ISR register
	USART_ICR_ORECF_Clear = 0x1
	// Position of IDLECF field.
	USART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	USART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	USART_ICR_IDLECF = 0x10
	// Clears the IDLE flag in the ISR register
	USART_ICR_IDLECF_Clear = 0x1
	// Position of TXFECF field.
	USART_ICR_TXFECF_Pos = 0x5
	// Bit mask of TXFECF field.
	USART_ICR_TXFECF_Msk = 0x20
	// Bit TXFECF.
	USART_ICR_TXFECF = 0x20
	// Clear the TXFE flag in the ISR register
	USART_ICR_TXFECF_Clear = 0x1
	// Position of TCCF field.
	USART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	USART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	USART_ICR_TCCF = 0x40
	// Clears the TC flag in the ISR register
	USART_ICR_TCCF_Clear = 0x1
	// Position of TCBGTCF field.
	USART_ICR_TCBGTCF_Pos = 0x7
	// Bit mask of TCBGTCF field.
	USART_ICR_TCBGTCF_Msk = 0x80
	// Bit TCBGTCF.
	USART_ICR_TCBGTCF = 0x80
	// Clear the TCBGT flag in the ISR register
	USART_ICR_TCBGTCF_Clear = 0x1
	// Position of LBDCF field.
	USART_ICR_LBDCF_Pos = 0x8
	// Bit mask of LBDCF field.
	USART_ICR_LBDCF_Msk = 0x100
	// Bit LBDCF.
	USART_ICR_LBDCF = 0x100
	// Clears the LBDF flag in the ISR register
	USART_ICR_LBDCF_Clear = 0x1
	// Position of CTSCF field.
	USART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	USART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	USART_ICR_CTSCF = 0x200
	// Clears the CTSIF flag in the ISR register
	USART_ICR_CTSCF_Clear = 0x1
	// Position of RTOCF field.
	USART_ICR_RTOCF_Pos = 0xb
	// Bit mask of RTOCF field.
	USART_ICR_RTOCF_Msk = 0x800
	// Bit RTOCF.
	USART_ICR_RTOCF = 0x800
	// Clears the RTOF flag in the ISR register
	USART_ICR_RTOCF_Clear = 0x1
	// Position of EOBCF field.
	USART_ICR_EOBCF_Pos = 0xc
	// Bit mask of EOBCF field.
	USART_ICR_EOBCF_Msk = 0x1000
	// Bit EOBCF.
	USART_ICR_EOBCF = 0x1000
	// Clears the EOBF flag in the ISR register
	USART_ICR_EOBCF_Clear = 0x1
	// Position of UDRCF field.
	USART_ICR_UDRCF_Pos = 0xd
	// Bit mask of UDRCF field.
	USART_ICR_UDRCF_Msk = 0x2000
	// Bit UDRCF.
	USART_ICR_UDRCF = 0x2000
	// Clear the UDR flag in the ISR register
	USART_ICR_UDRCF_Clear = 0x1
	// Position of CMCF field.
	USART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	USART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	USART_ICR_CMCF = 0x20000
	// Clears the CMF flag in the ISR register
	USART_ICR_CMCF_Clear = 0x1

	// RDR: RDR register
	// Position of RDR field.
	USART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	USART_RDR_RDR_Msk = 0x1ff

	// TDR: TDR register
	// Position of TDR field.
	USART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	USART_TDR_TDR_Msk = 0x1ff

	// PRESC: PRESC register
	// Position of PRESCALER field.
	USART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf
	// Input clock divided by 1
	USART_PRESC_PRESCALER_Div1 = 0x0
	// Input clock divided by 2
	USART_PRESC_PRESCALER_Div2 = 0x1
	// Input clock divided by 4
	USART_PRESC_PRESCALER_Div4 = 0x2
	// Input clock divided by 6
	USART_PRESC_PRESCALER_Div6 = 0x3
	// Input clock divided by 8
	USART_PRESC_PRESCALER_Div8 = 0x4
	// Input clock divided by 10
	USART_PRESC_PRESCALER_Div10 = 0x5
	// Input clock divided by 12
	USART_PRESC_PRESCALER_Div12 = 0x6
	// Input clock divided by 16
	USART_PRESC_PRESCALER_Div16 = 0x7
	// Input clock divided by 32
	USART_PRESC_PRESCALER_Div32 = 0x8
	// Input clock divided by 64
	USART_PRESC_PRESCALER_Div64 = 0x9
	// Input clock divided by 128
	USART_PRESC_PRESCALER_Div128 = 0xa
	// Input clock divided by 256
	USART_PRESC_PRESCALER_Div256 = 0xb
)

// Constants for BLUE
const (
	// INTERRUPT1REG: INTERRUPT1REG register
	// Position of ADDPOINTERROR field.
	BLUE_INTERRUPT1REG_ADDPOINTERROR_Pos = 0x4
	// Bit mask of ADDPOINTERROR field.
	BLUE_INTERRUPT1REG_ADDPOINTERROR_Msk = 0x10
	// Bit ADDPOINTERROR.
	BLUE_INTERRUPT1REG_ADDPOINTERROR = 0x10
	// Position of RXOVERFLOWERROR field.
	BLUE_INTERRUPT1REG_RXOVERFLOWERROR_Pos = 0x5
	// Bit mask of RXOVERFLOWERROR field.
	BLUE_INTERRUPT1REG_RXOVERFLOWERROR_Msk = 0x20
	// Bit RXOVERFLOWERROR.
	BLUE_INTERRUPT1REG_RXOVERFLOWERROR = 0x20
	// Position of SEQDONE field.
	BLUE_INTERRUPT1REG_SEQDONE_Pos = 0x7
	// Bit mask of SEQDONE field.
	BLUE_INTERRUPT1REG_SEQDONE_Msk = 0x80
	// Bit SEQDONE.
	BLUE_INTERRUPT1REG_SEQDONE = 0x80
	// Position of TXERROR_0 field.
	BLUE_INTERRUPT1REG_TXERROR_0_Pos = 0x8
	// Bit mask of TXERROR_0 field.
	BLUE_INTERRUPT1REG_TXERROR_0_Msk = 0x100
	// Bit TXERROR_0.
	BLUE_INTERRUPT1REG_TXERROR_0 = 0x100
	// Position of TXERROR_1 field.
	BLUE_INTERRUPT1REG_TXERROR_1_Pos = 0x9
	// Bit mask of TXERROR_1 field.
	BLUE_INTERRUPT1REG_TXERROR_1_Msk = 0x200
	// Bit TXERROR_1.
	BLUE_INTERRUPT1REG_TXERROR_1 = 0x200
	// Position of TXERROR_2 field.
	BLUE_INTERRUPT1REG_TXERROR_2_Pos = 0xa
	// Bit mask of TXERROR_2 field.
	BLUE_INTERRUPT1REG_TXERROR_2_Msk = 0x400
	// Bit TXERROR_2.
	BLUE_INTERRUPT1REG_TXERROR_2 = 0x400
	// Position of TXERROR_3 field.
	BLUE_INTERRUPT1REG_TXERROR_3_Pos = 0xb
	// Bit mask of TXERROR_3 field.
	BLUE_INTERRUPT1REG_TXERROR_3_Msk = 0x800
	// Bit TXERROR_3.
	BLUE_INTERRUPT1REG_TXERROR_3 = 0x800
	// Position of TXERROR_4 field.
	BLUE_INTERRUPT1REG_TXERROR_4_Pos = 0xc
	// Bit mask of TXERROR_4 field.
	BLUE_INTERRUPT1REG_TXERROR_4_Msk = 0x1000
	// Bit TXERROR_4.
	BLUE_INTERRUPT1REG_TXERROR_4 = 0x1000
	// Position of ENCERROR field.
	BLUE_INTERRUPT1REG_ENCERROR_Pos = 0xd
	// Bit mask of ENCERROR field.
	BLUE_INTERRUPT1REG_ENCERROR_Msk = 0x2000
	// Bit ENCERROR.
	BLUE_INTERRUPT1REG_ENCERROR = 0x2000
	// Position of ALLTABLEREADYERROR field.
	BLUE_INTERRUPT1REG_ALLTABLEREADYERROR_Pos = 0xe
	// Bit mask of ALLTABLEREADYERROR field.
	BLUE_INTERRUPT1REG_ALLTABLEREADYERROR_Msk = 0x4000
	// Bit ALLTABLEREADYERROR.
	BLUE_INTERRUPT1REG_ALLTABLEREADYERROR = 0x4000
	// Position of TXDATAREADYERROR field.
	BLUE_INTERRUPT1REG_TXDATAREADYERROR_Pos = 0xf
	// Bit mask of TXDATAREADYERROR field.
	BLUE_INTERRUPT1REG_TXDATAREADYERROR_Msk = 0x8000
	// Bit TXDATAREADYERROR.
	BLUE_INTERRUPT1REG_TXDATAREADYERROR = 0x8000
	// Position of NOACTIVELERROR field.
	BLUE_INTERRUPT1REG_NOACTIVELERROR_Pos = 0x10
	// Bit mask of NOACTIVELERROR field.
	BLUE_INTERRUPT1REG_NOACTIVELERROR_Msk = 0x10000
	// Bit NOACTIVELERROR.
	BLUE_INTERRUPT1REG_NOACTIVELERROR = 0x10000
	// Position of RCVLENGTHERROR field.
	BLUE_INTERRUPT1REG_RCVLENGTHERROR_Pos = 0x12
	// Bit mask of RCVLENGTHERROR field.
	BLUE_INTERRUPT1REG_RCVLENGTHERROR_Msk = 0x40000
	// Bit RCVLENGTHERROR.
	BLUE_INTERRUPT1REG_RCVLENGTHERROR = 0x40000
	// Position of SEMATIMEOUTERROR field.
	BLUE_INTERRUPT1REG_SEMATIMEOUTERROR_Pos = 0x13
	// Bit mask of SEMATIMEOUTERROR field.
	BLUE_INTERRUPT1REG_SEMATIMEOUTERROR_Msk = 0x80000
	// Bit SEMATIMEOUTERROR.
	BLUE_INTERRUPT1REG_SEMATIMEOUTERROR = 0x80000
	// Position of TXRXSKIP field.
	BLUE_INTERRUPT1REG_TXRXSKIP_Pos = 0x15
	// Bit mask of TXRXSKIP field.
	BLUE_INTERRUPT1REG_TXRXSKIP_Msk = 0x200000
	// Bit TXRXSKIP.
	BLUE_INTERRUPT1REG_TXRXSKIP = 0x200000
	// Position of ACTIVE2ERROR field.
	BLUE_INTERRUPT1REG_ACTIVE2ERROR_Pos = 0x16
	// Bit mask of ACTIVE2ERROR field.
	BLUE_INTERRUPT1REG_ACTIVE2ERROR_Msk = 0x400000
	// Bit ACTIVE2ERROR.
	BLUE_INTERRUPT1REG_ACTIVE2ERROR = 0x400000
	// Position of CONFIGERROR field.
	BLUE_INTERRUPT1REG_CONFIGERROR_Pos = 0x17
	// Bit mask of CONFIGERROR field.
	BLUE_INTERRUPT1REG_CONFIGERROR_Msk = 0x800000
	// Bit CONFIGERROR.
	BLUE_INTERRUPT1REG_CONFIGERROR = 0x800000
	// Position of TXOK field.
	BLUE_INTERRUPT1REG_TXOK_Pos = 0x18
	// Bit mask of TXOK field.
	BLUE_INTERRUPT1REG_TXOK_Msk = 0x1000000
	// Bit TXOK.
	BLUE_INTERRUPT1REG_TXOK = 0x1000000
	// Position of DONE field.
	BLUE_INTERRUPT1REG_DONE_Pos = 0x19
	// Bit mask of DONE field.
	BLUE_INTERRUPT1REG_DONE_Msk = 0x2000000
	// Bit DONE.
	BLUE_INTERRUPT1REG_DONE = 0x2000000
	// Position of RCVTIMEOUT field.
	BLUE_INTERRUPT1REG_RCVTIMEOUT_Pos = 0x1a
	// Bit mask of RCVTIMEOUT field.
	BLUE_INTERRUPT1REG_RCVTIMEOUT_Msk = 0x4000000
	// Bit RCVTIMEOUT.
	BLUE_INTERRUPT1REG_RCVTIMEOUT = 0x4000000
	// Position of RCVNOMD field.
	BLUE_INTERRUPT1REG_RCVNOMD_Pos = 0x1b
	// Bit mask of RCVNOMD field.
	BLUE_INTERRUPT1REG_RCVNOMD_Msk = 0x8000000
	// Bit RCVNOMD.
	BLUE_INTERRUPT1REG_RCVNOMD = 0x8000000
	// Position of RCVCMD field.
	BLUE_INTERRUPT1REG_RCVCMD_Pos = 0x1c
	// Bit mask of RCVCMD field.
	BLUE_INTERRUPT1REG_RCVCMD_Msk = 0x10000000
	// Bit RCVCMD.
	BLUE_INTERRUPT1REG_RCVCMD = 0x10000000
	// Position of TIMECAPTURETRIG field.
	BLUE_INTERRUPT1REG_TIMECAPTURETRIG_Pos = 0x1d
	// Bit mask of TIMECAPTURETRIG field.
	BLUE_INTERRUPT1REG_TIMECAPTURETRIG_Msk = 0x20000000
	// Bit TIMECAPTURETRIG.
	BLUE_INTERRUPT1REG_TIMECAPTURETRIG = 0x20000000
	// Position of RCVCRCERR field.
	BLUE_INTERRUPT1REG_RCVCRCERR_Pos = 0x1e
	// Bit mask of RCVCRCERR field.
	BLUE_INTERRUPT1REG_RCVCRCERR_Msk = 0x40000000
	// Bit RCVCRCERR.
	BLUE_INTERRUPT1REG_RCVCRCERR = 0x40000000
	// Position of RCVOK field.
	BLUE_INTERRUPT1REG_RCVOK_Pos = 0x1f
	// Bit mask of RCVOK field.
	BLUE_INTERRUPT1REG_RCVOK_Msk = 0x80000000
	// Bit RCVOK.
	BLUE_INTERRUPT1REG_RCVOK = 0x80000000

	// INTERRUPT2REG: INTERRUPT2REG register
	// Position of AESMANENCINT field.
	BLUE_INTERRUPT2REG_AESMANENCINT_Pos = 0x0
	// Bit mask of AESMANENCINT field.
	BLUE_INTERRUPT2REG_AESMANENCINT_Msk = 0x1
	// Bit AESMANENCINT.
	BLUE_INTERRUPT2REG_AESMANENCINT = 0x1
	// Position of AESLEPRIVINT field.
	BLUE_INTERRUPT2REG_AESLEPRIVINT_Pos = 0x1
	// Bit mask of AESLEPRIVINT field.
	BLUE_INTERRUPT2REG_AESLEPRIVINT_Msk = 0x2
	// Bit AESLEPRIVINT.
	BLUE_INTERRUPT2REG_AESLEPRIVINT = 0x2

	// TIMEOUTDESTREG: TIMEOUTDESTREG register
	// Position of DESTINATION field.
	BLUE_TIMEOUTDESTREG_DESTINATION_Pos = 0x0
	// Bit mask of DESTINATION field.
	BLUE_TIMEOUTDESTREG_DESTINATION_Msk = 0x3

	// TIMEOUTREG: TIMEOUTREG register
	// Position of TIMEOUT field.
	BLUE_TIMEOUTREG_TIMEOUT_Pos = 0x0
	// Bit mask of TIMEOUT field.
	BLUE_TIMEOUTREG_TIMEOUT_Msk = 0xffffffff

	// TIMERCAPTUREREG: TIMERCAPTUREREG register
	// Position of TIMERCAPTURE field.
	BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Pos = 0x0
	// Bit mask of TIMERCAPTURE field.
	BLUE_TIMERCAPTUREREG_TIMERCAPTURE_Msk = 0xffffffff

	// CMDREG: CMDREG register
	// Position of TXRXSKIP field.
	BLUE_CMDREG_TXRXSKIP_Pos = 0x0
	// Bit mask of TXRXSKIP field.
	BLUE_CMDREG_TXRXSKIP_Msk = 0x1
	// Bit TXRXSKIP.
	BLUE_CMDREG_TXRXSKIP = 0x1
	// Position of CLEARSEMAREQ field.
	BLUE_CMDREG_CLEARSEMAREQ_Pos = 0x3
	// Bit mask of CLEARSEMAREQ field.
	BLUE_CMDREG_CLEARSEMAREQ_Msk = 0x8
	// Bit CLEARSEMAREQ.
	BLUE_CMDREG_CLEARSEMAREQ = 0x8

	// STATUSREG: STATUSREG register
	// Position of AESONFLYBUSY field.
	BLUE_STATUSREG_AESONFLYBUSY_Pos = 0x0
	// Bit mask of AESONFLYBUSY field.
	BLUE_STATUSREG_AESONFLYBUSY_Msk = 0x1
	// Bit AESONFLYBUSY.
	BLUE_STATUSREG_AESONFLYBUSY = 0x1
	// Position of NOTSUPPORTED_FUNCTION field.
	BLUE_STATUSREG_NOTSUPPORTED_FUNCTION_Pos = 0x3
	// Bit mask of NOTSUPPORTED_FUNCTION field.
	BLUE_STATUSREG_NOTSUPPORTED_FUNCTION_Msk = 0x8
	// Bit NOTSUPPORTED_FUNCTION.
	BLUE_STATUSREG_NOTSUPPORTED_FUNCTION = 0x8
	// Position of ADDPOINTERROR field.
	BLUE_STATUSREG_ADDPOINTERROR_Pos = 0x4
	// Bit mask of ADDPOINTERROR field.
	BLUE_STATUSREG_ADDPOINTERROR_Msk = 0x10
	// Bit ADDPOINTERROR.
	BLUE_STATUSREG_ADDPOINTERROR = 0x10
	// Position of RXOVERFLOWERROR field.
	BLUE_STATUSREG_RXOVERFLOWERROR_Pos = 0x5
	// Bit mask of RXOVERFLOWERROR field.
	BLUE_STATUSREG_RXOVERFLOWERROR_Msk = 0x20
	// Bit RXOVERFLOWERROR.
	BLUE_STATUSREG_RXOVERFLOWERROR = 0x20
	// Position of PREVTRANSMIT field.
	BLUE_STATUSREG_PREVTRANSMIT_Pos = 0x6
	// Bit mask of PREVTRANSMIT field.
	BLUE_STATUSREG_PREVTRANSMIT_Msk = 0x40
	// Bit PREVTRANSMIT.
	BLUE_STATUSREG_PREVTRANSMIT = 0x40
	// Position of SEQDONE field.
	BLUE_STATUSREG_SEQDONE_Pos = 0x7
	// Bit mask of SEQDONE field.
	BLUE_STATUSREG_SEQDONE_Msk = 0x80
	// Bit SEQDONE.
	BLUE_STATUSREG_SEQDONE = 0x80
	// Position of TXERROR_0 field.
	BLUE_STATUSREG_TXERROR_0_Pos = 0x8
	// Bit mask of TXERROR_0 field.
	BLUE_STATUSREG_TXERROR_0_Msk = 0x100
	// Bit TXERROR_0.
	BLUE_STATUSREG_TXERROR_0 = 0x100
	// Position of TXERROR_1 field.
	BLUE_STATUSREG_TXERROR_1_Pos = 0x9
	// Bit mask of TXERROR_1 field.
	BLUE_STATUSREG_TXERROR_1_Msk = 0x200
	// Bit TXERROR_1.
	BLUE_STATUSREG_TXERROR_1 = 0x200
	// Position of TXERROR_2 field.
	BLUE_STATUSREG_TXERROR_2_Pos = 0xa
	// Bit mask of TXERROR_2 field.
	BLUE_STATUSREG_TXERROR_2_Msk = 0x400
	// Bit TXERROR_2.
	BLUE_STATUSREG_TXERROR_2 = 0x400
	// Position of TXERROR_3 field.
	BLUE_STATUSREG_TXERROR_3_Pos = 0xb
	// Bit mask of TXERROR_3 field.
	BLUE_STATUSREG_TXERROR_3_Msk = 0x800
	// Bit TXERROR_3.
	BLUE_STATUSREG_TXERROR_3 = 0x800
	// Position of TXERROR_4 field.
	BLUE_STATUSREG_TXERROR_4_Pos = 0xc
	// Bit mask of TXERROR_4 field.
	BLUE_STATUSREG_TXERROR_4_Msk = 0x1000
	// Bit TXERROR_4.
	BLUE_STATUSREG_TXERROR_4 = 0x1000
	// Position of ENCERROR field.
	BLUE_STATUSREG_ENCERROR_Pos = 0xd
	// Bit mask of ENCERROR field.
	BLUE_STATUSREG_ENCERROR_Msk = 0x2000
	// Bit ENCERROR.
	BLUE_STATUSREG_ENCERROR = 0x2000
	// Position of ALLTABLEREADYERROR field.
	BLUE_STATUSREG_ALLTABLEREADYERROR_Pos = 0xe
	// Bit mask of ALLTABLEREADYERROR field.
	BLUE_STATUSREG_ALLTABLEREADYERROR_Msk = 0x4000
	// Bit ALLTABLEREADYERROR.
	BLUE_STATUSREG_ALLTABLEREADYERROR = 0x4000
	// Position of TXDATAREADYERROR field.
	BLUE_STATUSREG_TXDATAREADYERROR_Pos = 0xf
	// Bit mask of TXDATAREADYERROR field.
	BLUE_STATUSREG_TXDATAREADYERROR_Msk = 0x8000
	// Bit TXDATAREADYERROR.
	BLUE_STATUSREG_TXDATAREADYERROR = 0x8000
	// Position of NOACTIVELERROR field.
	BLUE_STATUSREG_NOACTIVELERROR_Pos = 0x10
	// Bit mask of NOACTIVELERROR field.
	BLUE_STATUSREG_NOACTIVELERROR_Msk = 0x10000
	// Bit NOACTIVELERROR.
	BLUE_STATUSREG_NOACTIVELERROR = 0x10000
	// Position of RCVLENGTHERROR field.
	BLUE_STATUSREG_RCVLENGTHERROR_Pos = 0x12
	// Bit mask of RCVLENGTHERROR field.
	BLUE_STATUSREG_RCVLENGTHERROR_Msk = 0x40000
	// Bit RCVLENGTHERROR.
	BLUE_STATUSREG_RCVLENGTHERROR = 0x40000
	// Position of SEMATIMEOUTERROR field.
	BLUE_STATUSREG_SEMATIMEOUTERROR_Pos = 0x13
	// Bit mask of SEMATIMEOUTERROR field.
	BLUE_STATUSREG_SEMATIMEOUTERROR_Msk = 0x80000
	// Bit SEMATIMEOUTERROR.
	BLUE_STATUSREG_SEMATIMEOUTERROR = 0x80000
	// Position of TXRXSKIP field.
	BLUE_STATUSREG_TXRXSKIP_Pos = 0x15
	// Bit mask of TXRXSKIP field.
	BLUE_STATUSREG_TXRXSKIP_Msk = 0x200000
	// Bit TXRXSKIP.
	BLUE_STATUSREG_TXRXSKIP = 0x200000
	// Position of ACTIVE2ERROR field.
	BLUE_STATUSREG_ACTIVE2ERROR_Pos = 0x16
	// Bit mask of ACTIVE2ERROR field.
	BLUE_STATUSREG_ACTIVE2ERROR_Msk = 0x400000
	// Bit ACTIVE2ERROR.
	BLUE_STATUSREG_ACTIVE2ERROR = 0x400000
	// Position of CONFIGERROR field.
	BLUE_STATUSREG_CONFIGERROR_Pos = 0x17
	// Bit mask of CONFIGERROR field.
	BLUE_STATUSREG_CONFIGERROR_Msk = 0x800000
	// Bit CONFIGERROR.
	BLUE_STATUSREG_CONFIGERROR = 0x800000
	// Position of TXOK field.
	BLUE_STATUSREG_TXOK_Pos = 0x18
	// Bit mask of TXOK field.
	BLUE_STATUSREG_TXOK_Msk = 0x1000000
	// Bit TXOK.
	BLUE_STATUSREG_TXOK = 0x1000000
	// Position of DONE field.
	BLUE_STATUSREG_DONE_Pos = 0x19
	// Bit mask of DONE field.
	BLUE_STATUSREG_DONE_Msk = 0x2000000
	// Bit DONE.
	BLUE_STATUSREG_DONE = 0x2000000
	// Position of RCVTIMEOUT field.
	BLUE_STATUSREG_RCVTIMEOUT_Pos = 0x1a
	// Bit mask of RCVTIMEOUT field.
	BLUE_STATUSREG_RCVTIMEOUT_Msk = 0x4000000
	// Bit RCVTIMEOUT.
	BLUE_STATUSREG_RCVTIMEOUT = 0x4000000
	// Position of RCVNOMD field.
	BLUE_STATUSREG_RCVNOMD_Pos = 0x1b
	// Bit mask of RCVNOMD field.
	BLUE_STATUSREG_RCVNOMD_Msk = 0x8000000
	// Bit RCVNOMD.
	BLUE_STATUSREG_RCVNOMD = 0x8000000
	// Position of RCVCMD field.
	BLUE_STATUSREG_RCVCMD_Pos = 0x1c
	// Bit mask of RCVCMD field.
	BLUE_STATUSREG_RCVCMD_Msk = 0x10000000
	// Bit RCVCMD.
	BLUE_STATUSREG_RCVCMD = 0x10000000
	// Position of TIMECAPTURETRIG field.
	BLUE_STATUSREG_TIMECAPTURETRIG_Pos = 0x1d
	// Bit mask of TIMECAPTURETRIG field.
	BLUE_STATUSREG_TIMECAPTURETRIG_Msk = 0x20000000
	// Bit TIMECAPTURETRIG.
	BLUE_STATUSREG_TIMECAPTURETRIG = 0x20000000
	// Position of RCVCRCERR field.
	BLUE_STATUSREG_RCVCRCERR_Pos = 0x1e
	// Bit mask of RCVCRCERR field.
	BLUE_STATUSREG_RCVCRCERR_Msk = 0x40000000
	// Bit RCVCRCERR.
	BLUE_STATUSREG_RCVCRCERR = 0x40000000
	// Position of RCVOK field.
	BLUE_STATUSREG_RCVOK_Pos = 0x1f
	// Bit mask of RCVOK field.
	BLUE_STATUSREG_RCVOK_Msk = 0x80000000
	// Bit RCVOK.
	BLUE_STATUSREG_RCVOK = 0x80000000

	// INTERRUPT1ENABLEREG: INTERRUPT1ENABLEREG register
	// Position of ADDPOINTERROR field.
	BLUE_INTERRUPT1ENABLEREG_ADDPOINTERROR_Pos = 0x4
	// Bit mask of ADDPOINTERROR field.
	BLUE_INTERRUPT1ENABLEREG_ADDPOINTERROR_Msk = 0x10
	// Bit ADDPOINTERROR.
	BLUE_INTERRUPT1ENABLEREG_ADDPOINTERROR = 0x10
	// Position of RXOVERFLOWERROR field.
	BLUE_INTERRUPT1ENABLEREG_RXOVERFLOWERROR_Pos = 0x5
	// Bit mask of RXOVERFLOWERROR field.
	BLUE_INTERRUPT1ENABLEREG_RXOVERFLOWERROR_Msk = 0x20
	// Bit RXOVERFLOWERROR.
	BLUE_INTERRUPT1ENABLEREG_RXOVERFLOWERROR = 0x20
	// Position of SEQDONE field.
	BLUE_INTERRUPT1ENABLEREG_SEQDONE_Pos = 0x7
	// Bit mask of SEQDONE field.
	BLUE_INTERRUPT1ENABLEREG_SEQDONE_Msk = 0x80
	// Bit SEQDONE.
	BLUE_INTERRUPT1ENABLEREG_SEQDONE = 0x80
	// Position of TXERROR_0 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_0_Pos = 0x8
	// Bit mask of TXERROR_0 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_0_Msk = 0x100
	// Bit TXERROR_0.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_0 = 0x100
	// Position of TXERROR_1 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_1_Pos = 0x9
	// Bit mask of TXERROR_1 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_1_Msk = 0x200
	// Bit TXERROR_1.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_1 = 0x200
	// Position of TXERROR_2 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_2_Pos = 0xa
	// Bit mask of TXERROR_2 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_2_Msk = 0x400
	// Bit TXERROR_2.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_2 = 0x400
	// Position of TXERROR_3 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_3_Pos = 0xb
	// Bit mask of TXERROR_3 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_3_Msk = 0x800
	// Bit TXERROR_3.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_3 = 0x800
	// Position of TXERROR_4 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_4_Pos = 0xc
	// Bit mask of TXERROR_4 field.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_4_Msk = 0x1000
	// Bit TXERROR_4.
	BLUE_INTERRUPT1ENABLEREG_TXERROR_4 = 0x1000
	// Position of ENCERROR field.
	BLUE_INTERRUPT1ENABLEREG_ENCERROR_Pos = 0xd
	// Bit mask of ENCERROR field.
	BLUE_INTERRUPT1ENABLEREG_ENCERROR_Msk = 0x2000
	// Bit ENCERROR.
	BLUE_INTERRUPT1ENABLEREG_ENCERROR = 0x2000
	// Position of ALLTABLEREADYERROR field.
	BLUE_INTERRUPT1ENABLEREG_ALLTABLEREADYERROR_Pos = 0xe
	// Bit mask of ALLTABLEREADYERROR field.
	BLUE_INTERRUPT1ENABLEREG_ALLTABLEREADYERROR_Msk = 0x4000
	// Bit ALLTABLEREADYERROR.
	BLUE_INTERRUPT1ENABLEREG_ALLTABLEREADYERROR = 0x4000
	// Position of TXDATAREADYERROR field.
	BLUE_INTERRUPT1ENABLEREG_TXDATAREADYERROR_Pos = 0xf
	// Bit mask of TXDATAREADYERROR field.
	BLUE_INTERRUPT1ENABLEREG_TXDATAREADYERROR_Msk = 0x8000
	// Bit TXDATAREADYERROR.
	BLUE_INTERRUPT1ENABLEREG_TXDATAREADYERROR = 0x8000
	// Position of NOACTIVELERROR field.
	BLUE_INTERRUPT1ENABLEREG_NOACTIVELERROR_Pos = 0x10
	// Bit mask of NOACTIVELERROR field.
	BLUE_INTERRUPT1ENABLEREG_NOACTIVELERROR_Msk = 0x10000
	// Bit NOACTIVELERROR.
	BLUE_INTERRUPT1ENABLEREG_NOACTIVELERROR = 0x10000
	// Position of RCVLENGTHERROR field.
	BLUE_INTERRUPT1ENABLEREG_RCVLENGTHERROR_Pos = 0x12
	// Bit mask of RCVLENGTHERROR field.
	BLUE_INTERRUPT1ENABLEREG_RCVLENGTHERROR_Msk = 0x40000
	// Bit RCVLENGTHERROR.
	BLUE_INTERRUPT1ENABLEREG_RCVLENGTHERROR = 0x40000
	// Position of SEMATIMEOUTERROR field.
	BLUE_INTERRUPT1ENABLEREG_SEMATIMEOUTERROR_Pos = 0x13
	// Bit mask of SEMATIMEOUTERROR field.
	BLUE_INTERRUPT1ENABLEREG_SEMATIMEOUTERROR_Msk = 0x80000
	// Bit SEMATIMEOUTERROR.
	BLUE_INTERRUPT1ENABLEREG_SEMATIMEOUTERROR = 0x80000
	// Position of TXRXSKIP field.
	BLUE_INTERRUPT1ENABLEREG_TXRXSKIP_Pos = 0x15
	// Bit mask of TXRXSKIP field.
	BLUE_INTERRUPT1ENABLEREG_TXRXSKIP_Msk = 0x200000
	// Bit TXRXSKIP.
	BLUE_INTERRUPT1ENABLEREG_TXRXSKIP = 0x200000
	// Position of ACTIVE2ERROR field.
	BLUE_INTERRUPT1ENABLEREG_ACTIVE2ERROR_Pos = 0x16
	// Bit mask of ACTIVE2ERROR field.
	BLUE_INTERRUPT1ENABLEREG_ACTIVE2ERROR_Msk = 0x400000
	// Bit ACTIVE2ERROR.
	BLUE_INTERRUPT1ENABLEREG_ACTIVE2ERROR = 0x400000
	// Position of CONFIGERROR field.
	BLUE_INTERRUPT1ENABLEREG_CONFIGERROR_Pos = 0x17
	// Bit mask of CONFIGERROR field.
	BLUE_INTERRUPT1ENABLEREG_CONFIGERROR_Msk = 0x800000
	// Bit CONFIGERROR.
	BLUE_INTERRUPT1ENABLEREG_CONFIGERROR = 0x800000
	// Position of TXOK field.
	BLUE_INTERRUPT1ENABLEREG_TXOK_Pos = 0x18
	// Bit mask of TXOK field.
	BLUE_INTERRUPT1ENABLEREG_TXOK_Msk = 0x1000000
	// Bit TXOK.
	BLUE_INTERRUPT1ENABLEREG_TXOK = 0x1000000
	// Position of DONE field.
	BLUE_INTERRUPT1ENABLEREG_DONE_Pos = 0x19
	// Bit mask of DONE field.
	BLUE_INTERRUPT1ENABLEREG_DONE_Msk = 0x2000000
	// Bit DONE.
	BLUE_INTERRUPT1ENABLEREG_DONE = 0x2000000
	// Position of RCVTIMEOUT field.
	BLUE_INTERRUPT1ENABLEREG_RCVTIMEOUT_Pos = 0x1a
	// Bit mask of RCVTIMEOUT field.
	BLUE_INTERRUPT1ENABLEREG_RCVTIMEOUT_Msk = 0x4000000
	// Bit RCVTIMEOUT.
	BLUE_INTERRUPT1ENABLEREG_RCVTIMEOUT = 0x4000000
	// Position of RCVNOMD field.
	BLUE_INTERRUPT1ENABLEREG_RCVNOMD_Pos = 0x1b
	// Bit mask of RCVNOMD field.
	BLUE_INTERRUPT1ENABLEREG_RCVNOMD_Msk = 0x8000000
	// Bit RCVNOMD.
	BLUE_INTERRUPT1ENABLEREG_RCVNOMD = 0x8000000
	// Position of RCVCMD field.
	BLUE_INTERRUPT1ENABLEREG_RCVCMD_Pos = 0x1c
	// Bit mask of RCVCMD field.
	BLUE_INTERRUPT1ENABLEREG_RCVCMD_Msk = 0x10000000
	// Bit RCVCMD.
	BLUE_INTERRUPT1ENABLEREG_RCVCMD = 0x10000000
	// Position of TIMECAPTURETRIG field.
	BLUE_INTERRUPT1ENABLEREG_TIMECAPTURETRIG_Pos = 0x1d
	// Bit mask of TIMECAPTURETRIG field.
	BLUE_INTERRUPT1ENABLEREG_TIMECAPTURETRIG_Msk = 0x20000000
	// Bit TIMECAPTURETRIG.
	BLUE_INTERRUPT1ENABLEREG_TIMECAPTURETRIG = 0x20000000
	// Position of RCVCRCERR field.
	BLUE_INTERRUPT1ENABLEREG_RCVCRCERR_Pos = 0x1e
	// Bit mask of RCVCRCERR field.
	BLUE_INTERRUPT1ENABLEREG_RCVCRCERR_Msk = 0x40000000
	// Bit RCVCRCERR.
	BLUE_INTERRUPT1ENABLEREG_RCVCRCERR = 0x40000000
	// Position of RCVOK field.
	BLUE_INTERRUPT1ENABLEREG_RCVOK_Pos = 0x1f
	// Bit mask of RCVOK field.
	BLUE_INTERRUPT1ENABLEREG_RCVOK_Msk = 0x80000000
	// Bit RCVOK.
	BLUE_INTERRUPT1ENABLEREG_RCVOK = 0x80000000

	// INTERRUPT1LATENCYREG: INTERRUPT1LATENCYREG register
	// Position of INTERRUPT1LATENCY field.
	BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Pos = 0x0
	// Bit mask of INTERRUPT1LATENCY field.
	BLUE_INTERRUPT1LATENCYREG_INTERRUPT1LATENCY_Msk = 0xff

	// MANAESKEY0REG: MANAESKEY0REG register
	// Position of MANAESKEY_31_0 field.
	BLUE_MANAESKEY0REG_MANAESKEY_31_0_Pos = 0x0
	// Bit mask of MANAESKEY_31_0 field.
	BLUE_MANAESKEY0REG_MANAESKEY_31_0_Msk = 0xffffffff

	// MANAESKEY1REG: MANAESKEY1REG register
	// Position of MANAESKEY_63_32 field.
	BLUE_MANAESKEY1REG_MANAESKEY_63_32_Pos = 0x0
	// Bit mask of MANAESKEY_63_32 field.
	BLUE_MANAESKEY1REG_MANAESKEY_63_32_Msk = 0xffffffff

	// MANAESKEY2REG: MANAESKEY2REG register
	// Position of MANAESKEY_95_64 field.
	BLUE_MANAESKEY2REG_MANAESKEY_95_64_Pos = 0x0
	// Bit mask of MANAESKEY_95_64 field.
	BLUE_MANAESKEY2REG_MANAESKEY_95_64_Msk = 0xffffffff

	// MANAESKEY3REG: MANAESKEY3REG register
	// Position of MANAESKEY_127_96 field.
	BLUE_MANAESKEY3REG_MANAESKEY_127_96_Pos = 0x0
	// Bit mask of MANAESKEY_127_96 field.
	BLUE_MANAESKEY3REG_MANAESKEY_127_96_Msk = 0xffffffff

	// MANAESCLEARTEXT0REG: MANAESCLEARTEXT0REG register
	// Position of AES field.
	BLUE_MANAESCLEARTEXT0REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCLEARTEXT0REG_AES_Msk = 0xffffffff

	// MANAESCLEARTEXT1REG: MANAESCLEARTEXT1REG register
	// Position of AES field.
	BLUE_MANAESCLEARTEXT1REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCLEARTEXT1REG_AES_Msk = 0xffffffff

	// MANAESCLEARTEXT2REG: MANAESCLEARTEXT2REG register
	// Position of AES field.
	BLUE_MANAESCLEARTEXT2REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCLEARTEXT2REG_AES_Msk = 0xffffffff

	// MANAESCLEARTEXT3REG: MANAESCLEARTEXT3REG register
	// Position of AES field.
	BLUE_MANAESCLEARTEXT3REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCLEARTEXT3REG_AES_Msk = 0xffffffff

	// MANAESCIPHERTEXT0REG: MANAESCIPHERTEXT0REG register
	// Position of AES field.
	BLUE_MANAESCIPHERTEXT0REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCIPHERTEXT0REG_AES_Msk = 0xffffffff

	// MANAESCIPHERTEXT1REG: MANAESCIPHERTEXT1REG register
	// Position of AES field.
	BLUE_MANAESCIPHERTEXT1REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCIPHERTEXT1REG_AES_Msk = 0xffffffff

	// MANAESCIPHERTEXT2REG: MANAESCIPHERTEXT2REG register
	// Position of AES field.
	BLUE_MANAESCIPHERTEXT2REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCIPHERTEXT2REG_AES_Msk = 0xffffffff

	// MANAESCIPHERTEXT3REG: MANAESCIPHERTEXT3REG register
	// Position of AES field.
	BLUE_MANAESCIPHERTEXT3REG_AES_Pos = 0x0
	// Bit mask of AES field.
	BLUE_MANAESCIPHERTEXT3REG_AES_Msk = 0xffffffff

	// MANAESCMDREG: MANAESCMDREG register
	// Position of START field.
	BLUE_MANAESCMDREG_START_Pos = 0x0
	// Bit mask of START field.
	BLUE_MANAESCMDREG_START_Msk = 0x1
	// Bit START.
	BLUE_MANAESCMDREG_START = 0x1
	// Position of INTENA field.
	BLUE_MANAESCMDREG_INTENA_Pos = 0x1
	// Bit mask of INTENA field.
	BLUE_MANAESCMDREG_INTENA_Msk = 0x2
	// Bit INTENA.
	BLUE_MANAESCMDREG_INTENA = 0x2

	// MANAESSTATREG: MANAESSTATREG register
	// Position of BUSY field.
	BLUE_MANAESSTATREG_BUSY_Pos = 0x0
	// Bit mask of BUSY field.
	BLUE_MANAESSTATREG_BUSY_Msk = 0x1
	// Bit BUSY.
	BLUE_MANAESSTATREG_BUSY = 0x1

	// AESLEPRIVPOINTERREG: AESLEPRIVPOINTERREG register
	// Position of POINTER field.
	BLUE_AESLEPRIVPOINTERREG_POINTER_Pos = 0x0
	// Bit mask of POINTER field.
	BLUE_AESLEPRIVPOINTERREG_POINTER_Msk = 0xffffff

	// AESLEPRIVHASHREG: AESLEPRIVHASHREG register
	// Position of HASH field.
	BLUE_AESLEPRIVHASHREG_HASH_Pos = 0x0
	// Bit mask of HASH field.
	BLUE_AESLEPRIVHASHREG_HASH_Msk = 0xffffff

	// AESLEPRIVPRANDREG: AESLEPRIVPRANDREG register
	// Position of PRAND field.
	BLUE_AESLEPRIVPRANDREG_PRAND_Pos = 0x0
	// Bit mask of PRAND field.
	BLUE_AESLEPRIVPRANDREG_PRAND_Msk = 0xffffff

	// AESLEPRIVCMDREG: AESLEPRIVCMDREG register
	// Position of START field.
	BLUE_AESLEPRIVCMDREG_START_Pos = 0x0
	// Bit mask of START field.
	BLUE_AESLEPRIVCMDREG_START_Msk = 0x1
	// Bit START.
	BLUE_AESLEPRIVCMDREG_START = 0x1
	// Position of INTENA field.
	BLUE_AESLEPRIVCMDREG_INTENA_Pos = 0x1
	// Bit mask of INTENA field.
	BLUE_AESLEPRIVCMDREG_INTENA_Msk = 0x2
	// Bit INTENA.
	BLUE_AESLEPRIVCMDREG_INTENA = 0x2
	// Position of NBKEYS field.
	BLUE_AESLEPRIVCMDREG_NBKEYS_Pos = 0x2
	// Bit mask of NBKEYS field.
	BLUE_AESLEPRIVCMDREG_NBKEYS_Msk = 0x3fc

	// AESLEPRIVSTATREG: AESLEPRIVSTATREG register
	// Position of BUSY field.
	BLUE_AESLEPRIVSTATREG_BUSY_Pos = 0x0
	// Bit mask of BUSY field.
	BLUE_AESLEPRIVSTATREG_BUSY_Msk = 0x1
	// Bit BUSY.
	BLUE_AESLEPRIVSTATREG_BUSY = 0x1
	// Position of KEYFND field.
	BLUE_AESLEPRIVSTATREG_KEYFND_Pos = 0x1
	// Bit mask of KEYFND field.
	BLUE_AESLEPRIVSTATREG_KEYFND_Msk = 0x2
	// Bit KEYFND.
	BLUE_AESLEPRIVSTATREG_KEYFND = 0x2
	// Position of KEYFNDINDEX field.
	BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Pos = 0x2
	// Bit mask of KEYFNDINDEX field.
	BLUE_AESLEPRIVSTATREG_KEYFNDINDEX_Msk = 0x3fc

	// STATUS2REG: STATUS2REG register
	// Position of IQSAMPLESREADY field.
	BLUE_STATUS2REG_IQSAMPLESREADY_Pos = 0x0
	// Bit mask of IQSAMPLESREADY field.
	BLUE_STATUS2REG_IQSAMPLESREADY_Msk = 0x1
	// Bit IQSAMPLESREADY.
	BLUE_STATUS2REG_IQSAMPLESREADY = 0x1
	// Position of IQSAMPLESNUMBER field.
	BLUE_STATUS2REG_IQSAMPLESNUMBER_Pos = 0x1
	// Bit mask of IQSAMPLESNUMBER field.
	BLUE_STATUS2REG_IQSAMPLESNUMBER_Msk = 0xfe
	// Position of IQSAMPLESMISSINGERROR field.
	BLUE_STATUS2REG_IQSAMPLESMISSINGERROR_Pos = 0x1d
	// Bit mask of IQSAMPLESMISSINGERROR field.
	BLUE_STATUS2REG_IQSAMPLESMISSINGERROR_Msk = 0x20000000
	// Bit IQSAMPLESMISSINGERROR.
	BLUE_STATUS2REG_IQSAMPLESMISSINGERROR = 0x20000000
	// Position of ANTENNASWITCHINGPATTERNACCESSERROR field.
	BLUE_STATUS2REG_ANTENNASWITCHINGPATTERNACCESSERROR_Pos = 0x1e
	// Bit mask of ANTENNASWITCHINGPATTERNACCESSERROR field.
	BLUE_STATUS2REG_ANTENNASWITCHINGPATTERNACCESSERROR_Msk = 0x40000000
	// Bit ANTENNASWITCHINGPATTERNACCESSERROR.
	BLUE_STATUS2REG_ANTENNASWITCHINGPATTERNACCESSERROR = 0x40000000
	// Position of ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR field.
	BLUE_STATUS2REG_ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR_Pos = 0x1f
	// Bit mask of ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR field.
	BLUE_STATUS2REG_ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR_Msk = 0x80000000
	// Bit ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR.
	BLUE_STATUS2REG_ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR = 0x80000000
)

// Constants for GLOBALSTATMACH
const (
	// WORD0: WORD0 register
	// Position of RadioConfigPtr field.
	GLOBALSTATMACH_WORD0_RadioConfigPtr_Pos = 0x0
	// Bit mask of RadioConfigPtr field.
	GLOBALSTATMACH_WORD0_RadioConfigPtr_Msk = 0xffffffff

	// WORD1: WORD1 register
	// Position of CurStMachNum field.
	GLOBALSTATMACH_WORD1_CurStMachNum_Pos = 0x0
	// Bit mask of CurStMachNum field.
	GLOBALSTATMACH_WORD1_CurStMachNum_Msk = 0x7f
	// Position of Active field.
	GLOBALSTATMACH_WORD1_Active_Pos = 0x7
	// Bit mask of Active field.
	GLOBALSTATMACH_WORD1_Active_Msk = 0x80
	// Bit Active.
	GLOBALSTATMACH_WORD1_Active = 0x80
	// Position of WakeupInitDelay field.
	GLOBALSTATMACH_WORD1_WakeupInitDelay_Pos = 0x8
	// Bit mask of WakeupInitDelay field.
	GLOBALSTATMACH_WORD1_WakeupInitDelay_Msk = 0xff00
	// Position of Timer12InitDelayCal field.
	GLOBALSTATMACH_WORD1_Timer12InitDelayCal_Pos = 0x10
	// Bit mask of Timer12InitDelayCal field.
	GLOBALSTATMACH_WORD1_Timer12InitDelayCal_Msk = 0xff0000
	// Position of Timer2InitDelayNoCal field.
	GLOBALSTATMACH_WORD1_Timer2InitDelayNoCal_Pos = 0x18
	// Bit mask of Timer2InitDelayNoCal field.
	GLOBALSTATMACH_WORD1_Timer2InitDelayNoCal_Msk = 0xff000000

	// WORD2: WORD2 register
	// Position of TransmitCalDelayChk field.
	GLOBALSTATMACH_WORD2_TransmitCalDelayChk_Pos = 0x0
	// Bit mask of TransmitCalDelayChk field.
	GLOBALSTATMACH_WORD2_TransmitCalDelayChk_Msk = 0xff
	// Position of TransmitNoCalDelayChk field.
	GLOBALSTATMACH_WORD2_TransmitNoCalDelayChk_Pos = 0x8
	// Bit mask of TransmitNoCalDelayChk field.
	GLOBALSTATMACH_WORD2_TransmitNoCalDelayChk_Msk = 0xff00
	// Position of ReceiveCalDelayChk field.
	GLOBALSTATMACH_WORD2_ReceiveCalDelayChk_Pos = 0x10
	// Bit mask of ReceiveCalDelayChk field.
	GLOBALSTATMACH_WORD2_ReceiveCalDelayChk_Msk = 0xff0000
	// Position of ReceiveNoCalDelayChk field.
	GLOBALSTATMACH_WORD2_ReceiveNoCalDelayChk_Pos = 0x18
	// Bit mask of ReceiveNoCalDelayChk field.
	GLOBALSTATMACH_WORD2_ReceiveNoCalDelayChk_Msk = 0xff000000

	// WORD3: WORD3 register
	// Position of ConfigEndDuration field.
	GLOBALSTATMACH_WORD3_ConfigEndDuration_Pos = 0x0
	// Bit mask of ConfigEndDuration field.
	GLOBALSTATMACH_WORD3_ConfigEndDuration_Msk = 0xff
	// Position of TxdataReadyCheck field.
	GLOBALSTATMACH_WORD3_TxdataReadyCheck_Pos = 0x8
	// Bit mask of TxdataReadyCheck field.
	GLOBALSTATMACH_WORD3_TxdataReadyCheck_Msk = 0xff00
	// Position of TxdelayStart field.
	GLOBALSTATMACH_WORD3_TxdelayStart_Pos = 0x10
	// Bit mask of TxdelayStart field.
	GLOBALSTATMACH_WORD3_TxdelayStart_Msk = 0xff0000
	// Position of TxdelayEnd field.
	GLOBALSTATMACH_WORD3_TxdelayEnd_Pos = 0x18
	// Bit mask of TxdelayEnd field.
	GLOBALSTATMACH_WORD3_TxdelayEnd_Msk = 0x3f000000
	// Position of TimeCaptureSel field.
	GLOBALSTATMACH_WORD3_TimeCaptureSel_Pos = 0x1e
	// Bit mask of TimeCaptureSel field.
	GLOBALSTATMACH_WORD3_TimeCaptureSel_Msk = 0x40000000
	// Bit TimeCaptureSel.
	GLOBALSTATMACH_WORD3_TimeCaptureSel = 0x40000000
	// Position of TimeCapture field.
	GLOBALSTATMACH_WORD3_TimeCapture_Pos = 0x1f
	// Bit mask of TimeCapture field.
	GLOBALSTATMACH_WORD3_TimeCapture_Msk = 0x80000000
	// Bit TimeCapture.
	GLOBALSTATMACH_WORD3_TimeCapture = 0x80000000

	// WORD4: WORD4 register
	// Position of TxReadyTimeout field.
	GLOBALSTATMACH_WORD4_TxReadyTimeout_Pos = 0x0
	// Bit mask of TxReadyTimeout field.
	GLOBALSTATMACH_WORD4_TxReadyTimeout_Msk = 0xff
	// Position of RcvTimeout field.
	GLOBALSTATMACH_WORD4_RcvTimeout_Pos = 0x8
	// Bit mask of RcvTimeout field.
	GLOBALSTATMACH_WORD4_RcvTimeout_Msk = 0xfffff00

	// WORD5: WORD5 register
	// Position of AutoTxRxskipEn field.
	GLOBALSTATMACH_WORD5_AutoTxRxskipEn_Pos = 0x0
	// Bit mask of AutoTxRxskipEn field.
	GLOBALSTATMACH_WORD5_AutoTxRxskipEn_Msk = 0x1
	// Bit AutoTxRxskipEn.
	GLOBALSTATMACH_WORD5_AutoTxRxskipEn = 0x1
	// Position of ChkFlagAutoClearEna field.
	GLOBALSTATMACH_WORD5_ChkFlagAutoClearEna_Pos = 0x2
	// Bit mask of ChkFlagAutoClearEna field.
	GLOBALSTATMACH_WORD5_ChkFlagAutoClearEna_Msk = 0x4
	// Bit ChkFlagAutoClearEna.
	GLOBALSTATMACH_WORD5_ChkFlagAutoClearEna = 0x4
	// Position of IntAddPointError field.
	GLOBALSTATMACH_WORD5_IntAddPointError_Pos = 0x14
	// Bit mask of IntAddPointError field.
	GLOBALSTATMACH_WORD5_IntAddPointError_Msk = 0x100000
	// Bit IntAddPointError.
	GLOBALSTATMACH_WORD5_IntAddPointError = 0x100000
	// Position of IntAllTableReadyError field.
	GLOBALSTATMACH_WORD5_IntAllTableReadyError_Pos = 0x15
	// Bit mask of IntAllTableReadyError field.
	GLOBALSTATMACH_WORD5_IntAllTableReadyError_Msk = 0x200000
	// Bit IntAllTableReadyError.
	GLOBALSTATMACH_WORD5_IntAllTableReadyError = 0x200000
	// Position of IntTxDataReadyError field.
	GLOBALSTATMACH_WORD5_IntTxDataReadyError_Pos = 0x16
	// Bit mask of IntTxDataReadyError field.
	GLOBALSTATMACH_WORD5_IntTxDataReadyError_Msk = 0x400000
	// Bit IntTxDataReadyError.
	GLOBALSTATMACH_WORD5_IntTxDataReadyError = 0x400000
	// Position of IntNoActiveLError field.
	GLOBALSTATMACH_WORD5_IntNoActiveLError_Pos = 0x17
	// Bit mask of IntNoActiveLError field.
	GLOBALSTATMACH_WORD5_IntNoActiveLError_Msk = 0x800000
	// Bit IntNoActiveLError.
	GLOBALSTATMACH_WORD5_IntNoActiveLError = 0x800000
	// Position of IntRcvLengthError field.
	GLOBALSTATMACH_WORD5_IntRcvLengthError_Pos = 0x19
	// Bit mask of IntRcvLengthError field.
	GLOBALSTATMACH_WORD5_IntRcvLengthError_Msk = 0x2000000
	// Bit IntRcvLengthError.
	GLOBALSTATMACH_WORD5_IntRcvLengthError = 0x2000000
	// Position of IntSemaTimeoutError field.
	GLOBALSTATMACH_WORD5_IntSemaTimeoutError_Pos = 0x1a
	// Bit mask of IntSemaTimeoutError field.
	GLOBALSTATMACH_WORD5_IntSemaTimeoutError_Msk = 0x4000000
	// Bit IntSemaTimeoutError.
	GLOBALSTATMACH_WORD5_IntSemaTimeoutError = 0x4000000
	// Position of IntSeqDone field.
	GLOBALSTATMACH_WORD5_IntSeqDone_Pos = 0x1c
	// Bit mask of IntSeqDone field.
	GLOBALSTATMACH_WORD5_IntSeqDone_Msk = 0x10000000
	// Bit IntSeqDone.
	GLOBALSTATMACH_WORD5_IntSeqDone = 0x10000000
	// Position of INTTXRXSKIP field.
	GLOBALSTATMACH_WORD5_INTTXRXSKIP_Pos = 0x1d
	// Bit mask of INTTXRXSKIP field.
	GLOBALSTATMACH_WORD5_INTTXRXSKIP_Msk = 0x20000000
	// Bit INTTXRXSKIP.
	GLOBALSTATMACH_WORD5_INTTXRXSKIP = 0x20000000
	// Position of IntActive2Err field.
	GLOBALSTATMACH_WORD5_IntActive2Err_Pos = 0x1e
	// Bit mask of IntActive2Err field.
	GLOBALSTATMACH_WORD5_IntActive2Err_Msk = 0x40000000
	// Bit IntActive2Err.
	GLOBALSTATMACH_WORD5_IntActive2Err = 0x40000000
	// Position of IntConfigError field.
	GLOBALSTATMACH_WORD5_IntConfigError_Pos = 0x1f
	// Bit mask of IntConfigError field.
	GLOBALSTATMACH_WORD5_IntConfigError_Msk = 0x80000000
	// Bit IntConfigError.
	GLOBALSTATMACH_WORD5_IntConfigError = 0x80000000

	// WORD6: WORD6 register
	// Position of DefaultAntennaID field.
	GLOBALSTATMACH_WORD6_DefaultAntennaID_Pos = 0x0
	// Bit mask of DefaultAntennaID field.
	GLOBALSTATMACH_WORD6_DefaultAntennaID_Msk = 0x7f
)

// Constants for RADIO_CONTROL
const (
	// ID: RADIO_CONTROL_ID register
	// Position of REVISION field.
	RADIO_CONTROL_ID_REVISION_Pos = 0x4
	// Bit mask of REVISION field.
	RADIO_CONTROL_ID_REVISION_Msk = 0xf0
	// Position of VERSION field.
	RADIO_CONTROL_ID_VERSION_Pos = 0x8
	// Bit mask of VERSION field.
	RADIO_CONTROL_ID_VERSION_Msk = 0xf00
	// Position of PRODUCT field.
	RADIO_CONTROL_ID_PRODUCT_Pos = 0xc
	// Bit mask of PRODUCT field.
	RADIO_CONTROL_ID_PRODUCT_Msk = 0xf000

	// CLK32COUNT_REG: CLK32COUNT_REG register
	// Position of SLOW_COUNT field.
	RADIO_CONTROL_CLK32COUNT_REG_SLOW_COUNT_Pos = 0x0
	// Bit mask of SLOW_COUNT field.
	RADIO_CONTROL_CLK32COUNT_REG_SLOW_COUNT_Msk = 0x1ff

	// CLK32PERIOD_REG: CLK32PERIOD_REG register
	// Position of SLOW_PERIOD field.
	RADIO_CONTROL_CLK32PERIOD_REG_SLOW_PERIOD_Pos = 0x0
	// Bit mask of SLOW_PERIOD field.
	RADIO_CONTROL_CLK32PERIOD_REG_SLOW_PERIOD_Msk = 0x7ffff

	// CLK32FREQUENCY_REG: CLK32FREQUENCY_REG register
	// Position of SLOW_FREQUENCY field.
	RADIO_CONTROL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Pos = 0x0
	// Bit mask of SLOW_FREQUENCY field.
	RADIO_CONTROL_CLK32FREQUENCY_REG_SLOW_FREQUENCY_Msk = 0x7ffffff

	// IRQ_STATUS: RADIO_CONTROL_IRQ_STATUS register
	// Position of SLOW_CLK_IRQ field.
	RADIO_CONTROL_IRQ_STATUS_SLOW_CLK_IRQ_Pos = 0x0
	// Bit mask of SLOW_CLK_IRQ field.
	RADIO_CONTROL_IRQ_STATUS_SLOW_CLK_IRQ_Msk = 0x1
	// Bit SLOW_CLK_IRQ.
	RADIO_CONTROL_IRQ_STATUS_SLOW_CLK_IRQ = 0x1
	// Position of RADIO_FSM_IRQ field.
	RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Pos = 0x8
	// Bit mask of RADIO_FSM_IRQ field.
	RADIO_CONTROL_IRQ_STATUS_RADIO_FSM_IRQ_Msk = 0x3f00

	// IRQ_ENABLE: RADIO_CONTROL_IRQ_ENABLE register
	// Position of SLOW_CLK_IRQ_MASK field.
	RADIO_CONTROL_IRQ_ENABLE_SLOW_CLK_IRQ_MASK_Pos = 0x0
	// Bit mask of SLOW_CLK_IRQ_MASK field.
	RADIO_CONTROL_IRQ_ENABLE_SLOW_CLK_IRQ_MASK_Msk = 0x1
	// Bit SLOW_CLK_IRQ_MASK.
	RADIO_CONTROL_IRQ_ENABLE_SLOW_CLK_IRQ_MASK = 0x1
	// Position of RADIO_FSM_IRQ_MASK field.
	RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Pos = 0x8
	// Bit mask of RADIO_FSM_IRQ_MASK field.
	RADIO_CONTROL_IRQ_ENABLE_RADIO_FSM_IRQ_MASK_Msk = 0x3f00
)

// Constants for RADIO
const (
	// AA0_DIG_USR: AA0_DIG_USR register
	// Position of AA_7_0 field.
	RADIO_AA0_DIG_USR_AA_7_0_Pos = 0x0
	// Bit mask of AA_7_0 field.
	RADIO_AA0_DIG_USR_AA_7_0_Msk = 0xff

	// AA1_DIG_USR: AA1_DIG_USR register
	// Position of AA_15_8 field.
	RADIO_AA1_DIG_USR_AA_15_8_Pos = 0x0
	// Bit mask of AA_15_8 field.
	RADIO_AA1_DIG_USR_AA_15_8_Msk = 0xff

	// AA2_DIG_USR: AA2_DIG_USR register
	// Position of AA_23_16 field.
	RADIO_AA2_DIG_USR_AA_23_16_Pos = 0x0
	// Bit mask of AA_23_16 field.
	RADIO_AA2_DIG_USR_AA_23_16_Msk = 0xff

	// AA3_DIG_USR: AA3_DIG_USR register
	// Position of AA_31_24 field.
	RADIO_AA3_DIG_USR_AA_31_24_Pos = 0x0
	// Bit mask of AA_31_24 field.
	RADIO_AA3_DIG_USR_AA_31_24_Msk = 0xff

	// DEM_MOD_DIG_USR: DEM_MOD_DIG_USR register
	// Position of CHANNEL_NUM field.
	RADIO_DEM_MOD_DIG_USR_CHANNEL_NUM_Pos = 0x1
	// Bit mask of CHANNEL_NUM field.
	RADIO_DEM_MOD_DIG_USR_CHANNEL_NUM_Msk = 0xfe

	// FSM_USR: RADIO_FSM_USR register
	// Position of EN_CALIB_CBP field.
	RADIO_FSM_USR_EN_CALIB_CBP_Pos = 0x1
	// Bit mask of EN_CALIB_CBP field.
	RADIO_FSM_USR_EN_CALIB_CBP_Msk = 0x2
	// Bit EN_CALIB_CBP.
	RADIO_FSM_USR_EN_CALIB_CBP = 0x2
	// Position of EN_CALIB_SYNTH field.
	RADIO_FSM_USR_EN_CALIB_SYNTH_Pos = 0x2
	// Bit mask of EN_CALIB_SYNTH field.
	RADIO_FSM_USR_EN_CALIB_SYNTH_Msk = 0x4
	// Bit EN_CALIB_SYNTH.
	RADIO_FSM_USR_EN_CALIB_SYNTH = 0x4
	// Position of PA_POWER field.
	RADIO_FSM_USR_PA_POWER_Pos = 0x3
	// Bit mask of PA_POWER field.
	RADIO_FSM_USR_PA_POWER_Msk = 0xf8

	// PHYCTRL_DIG_USR: PHYCTRL_DIG_USR register
	// Position of RXTXPHY field.
	RADIO_PHYCTRL_DIG_USR_RXTXPHY_Pos = 0x0
	// Bit mask of RXTXPHY field.
	RADIO_PHYCTRL_DIG_USR_RXTXPHY_Msk = 0x7

	// AFC1_DIG_ENG: AFC1_DIG_ENG register
	// Position of AFC_DELAY_AFTER field.
	RADIO_AFC1_DIG_ENG_AFC_DELAY_AFTER_Pos = 0x0
	// Bit mask of AFC_DELAY_AFTER field.
	RADIO_AFC1_DIG_ENG_AFC_DELAY_AFTER_Msk = 0xf
	// Position of AFC_DELAY_BEFORE field.
	RADIO_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Pos = 0x4
	// Bit mask of AFC_DELAY_BEFORE field.
	RADIO_AFC1_DIG_ENG_AFC_DELAY_BEFORE_Msk = 0xf0

	// CR0_DIG_ENG: CR0_DIG_ENG register
	// Position of CR_GAIN_AFTER field.
	RADIO_CR0_DIG_ENG_CR_GAIN_AFTER_Pos = 0x0
	// Bit mask of CR_GAIN_AFTER field.
	RADIO_CR0_DIG_ENG_CR_GAIN_AFTER_Msk = 0xf
	// Position of CR_GAIN_BEFORE field.
	RADIO_CR0_DIG_ENG_CR_GAIN_BEFORE_Pos = 0x4
	// Bit mask of CR_GAIN_BEFORE field.
	RADIO_CR0_DIG_ENG_CR_GAIN_BEFORE_Msk = 0xf0

	// CR0_LR: CR0_LR register
	// Position of CR_LR_GAIN_AFTER field.
	RADIO_CR0_LR_CR_LR_GAIN_AFTER_Pos = 0x0
	// Bit mask of CR_LR_GAIN_AFTER field.
	RADIO_CR0_LR_CR_LR_GAIN_AFTER_Msk = 0xf
	// Position of CR_LR_GAIN_BEFORE field.
	RADIO_CR0_LR_CR_LR_GAIN_BEFORE_Pos = 0x4
	// Bit mask of CR_LR_GAIN_BEFORE field.
	RADIO_CR0_LR_CR_LR_GAIN_BEFORE_Msk = 0xf0

	// VIT_CONF_DIG_ENG: VIT_CONF_DIG_ENG register
	// Position of VIT_EN field.
	RADIO_VIT_CONF_DIG_ENG_VIT_EN_Pos = 0x0
	// Bit mask of VIT_EN field.
	RADIO_VIT_CONF_DIG_ENG_VIT_EN_Msk = 0x1
	// Bit VIT_EN.
	RADIO_VIT_CONF_DIG_ENG_VIT_EN = 0x1
	// Position of SPARE field.
	RADIO_VIT_CONF_DIG_ENG_SPARE_Pos = 0x2
	// Bit mask of SPARE field.
	RADIO_VIT_CONF_DIG_ENG_SPARE_Msk = 0xfc

	// LR_PD_THR_DIG_ENG: LR_PD_THR_DIG_ENG register
	// Position of LR_PD_THR field.
	RADIO_LR_PD_THR_DIG_ENG_LR_PD_THR_Pos = 0x0
	// Bit mask of LR_PD_THR field.
	RADIO_LR_PD_THR_DIG_ENG_LR_PD_THR_Msk = 0xff

	// LR_RSSI_THR_DIG_ENG: LR_RSSI_THR_DIG_ENG register
	// Position of LR_RSSI_THR field.
	RADIO_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Pos = 0x0
	// Bit mask of LR_RSSI_THR field.
	RADIO_LR_RSSI_THR_DIG_ENG_LR_RSSI_THR_Msk = 0xff

	// LR_AAC_THR_DIG_ENG: LR_AAC_THR_DIG_ENG register
	// Position of LR_AAC_THR field.
	RADIO_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Pos = 0x0
	// Bit mask of LR_AAC_THR field.
	RADIO_LR_AAC_THR_DIG_ENG_LR_AAC_THR_Msk = 0xff

	// SYNTHCAL0_DIG_ENG: SYNTHCAL0_DIG_ENG register
	// Position of SYNTHCAL_DEBUG_BUS_SEL field.
	RADIO_SYNTHCAL0_DIG_ENG_SYNTHCAL_DEBUG_BUS_SEL_Pos = 0x0
	// Bit mask of SYNTHCAL_DEBUG_BUS_SEL field.
	RADIO_SYNTHCAL0_DIG_ENG_SYNTHCAL_DEBUG_BUS_SEL_Msk = 0xf
	// Position of SYNTH_IF_FREQ_CAL field.
	RADIO_SYNTHCAL0_DIG_ENG_SYNTH_IF_FREQ_CAL_Pos = 0x6
	// Bit mask of SYNTH_IF_FREQ_CAL field.
	RADIO_SYNTHCAL0_DIG_ENG_SYNTH_IF_FREQ_CAL_Msk = 0xc0

	// DTB5_DIG_ENG: DTB5_DIG_ENG register
	// Position of RXTX_START_SEL field.
	RADIO_DTB5_DIG_ENG_RXTX_START_SEL_Pos = 0x0
	// Bit mask of RXTX_START_SEL field.
	RADIO_DTB5_DIG_ENG_RXTX_START_SEL_Msk = 0x1
	// Bit RXTX_START_SEL.
	RADIO_DTB5_DIG_ENG_RXTX_START_SEL = 0x1
	// Position of TX_ACTIVE field.
	RADIO_DTB5_DIG_ENG_TX_ACTIVE_Pos = 0x1
	// Bit mask of TX_ACTIVE field.
	RADIO_DTB5_DIG_ENG_TX_ACTIVE_Msk = 0x2
	// Bit TX_ACTIVE.
	RADIO_DTB5_DIG_ENG_TX_ACTIVE = 0x2
	// Position of RX_ACTIVE field.
	RADIO_DTB5_DIG_ENG_RX_ACTIVE_Pos = 0x2
	// Bit mask of RX_ACTIVE field.
	RADIO_DTB5_DIG_ENG_RX_ACTIVE_Msk = 0x4
	// Bit RX_ACTIVE.
	RADIO_DTB5_DIG_ENG_RX_ACTIVE = 0x4
	// Position of INITIALIZE field.
	RADIO_DTB5_DIG_ENG_INITIALIZE_Pos = 0x3
	// Bit mask of INITIALIZE field.
	RADIO_DTB5_DIG_ENG_INITIALIZE_Msk = 0x8
	// Bit INITIALIZE.
	RADIO_DTB5_DIG_ENG_INITIALIZE = 0x8
	// Position of PORT_SELECTED_EN field.
	RADIO_DTB5_DIG_ENG_PORT_SELECTED_EN_Pos = 0x4
	// Bit mask of PORT_SELECTED_EN field.
	RADIO_DTB5_DIG_ENG_PORT_SELECTED_EN_Msk = 0x10
	// Bit PORT_SELECTED_EN.
	RADIO_DTB5_DIG_ENG_PORT_SELECTED_EN = 0x10
	// Position of PORT_SELECTED_0 field.
	RADIO_DTB5_DIG_ENG_PORT_SELECTED_0_Pos = 0x5
	// Bit mask of PORT_SELECTED_0 field.
	RADIO_DTB5_DIG_ENG_PORT_SELECTED_0_Msk = 0x20
	// Bit PORT_SELECTED_0.
	RADIO_DTB5_DIG_ENG_PORT_SELECTED_0 = 0x20

	// RXADC_ANA_USR: RXADC_ANA_USR register
	// Position of RFD_RXADC_DELAYTRIM_I field.
	RADIO_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Pos = 0x0
	// Bit mask of RFD_RXADC_DELAYTRIM_I field.
	RADIO_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_I_Msk = 0x7
	// Position of RFD_RXADC_DELAYTRIM_Q field.
	RADIO_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Pos = 0x3
	// Bit mask of RFD_RXADC_DELAYTRIM_Q field.
	RADIO_RXADC_ANA_USR_RFD_RXADC_DELAYTRIM_Q_Msk = 0x38
	// Position of RXADC_DELAYTRIM_I_TST_SEL field.
	RADIO_RXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL_Pos = 0x6
	// Bit mask of RXADC_DELAYTRIM_I_TST_SEL field.
	RADIO_RXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL_Msk = 0x40
	// Bit RXADC_DELAYTRIM_I_TST_SEL.
	RADIO_RXADC_ANA_USR_RXADC_DELAYTRIM_I_TST_SEL = 0x40
	// Position of RXADC_DELAYTRIM_Q_TST_SEL field.
	RADIO_RXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL_Pos = 0x7
	// Bit mask of RXADC_DELAYTRIM_Q_TST_SEL field.
	RADIO_RXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL_Msk = 0x80
	// Bit RXADC_DELAYTRIM_Q_TST_SEL.
	RADIO_RXADC_ANA_USR_RXADC_DELAYTRIM_Q_TST_SEL = 0x80

	// LDO_ANA_ENG: LDO_ANA_ENG register
	// Position of RFD_RF_REG_BYPASS field.
	RADIO_LDO_ANA_ENG_RFD_RF_REG_BYPASS_Pos = 0x0
	// Bit mask of RFD_RF_REG_BYPASS field.
	RADIO_LDO_ANA_ENG_RFD_RF_REG_BYPASS_Msk = 0x1
	// Bit RFD_RF_REG_BYPASS.
	RADIO_LDO_ANA_ENG_RFD_RF_REG_BYPASS = 0x1

	// CBIAS0_ANA_ENG: CBIAS0_ANA_ENG register
	// Position of RFD_CBIAS_IBIAS_TRIM field.
	RADIO_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Pos = 0x0
	// Bit mask of RFD_CBIAS_IBIAS_TRIM field.
	RADIO_CBIAS0_ANA_ENG_RFD_CBIAS_IBIAS_TRIM_Msk = 0xf
	// Position of RFD_CBIAS_IPTAT_TRIM field.
	RADIO_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Pos = 0x4
	// Bit mask of RFD_CBIAS_IPTAT_TRIM field.
	RADIO_CBIAS0_ANA_ENG_RFD_CBIAS_IPTAT_TRIM_Msk = 0xf0

	// CBIAS1_ANA_ENG: CBIAS1_ANA_ENG register
	// Position of CBIAS0_TRIM_TST_SEL field.
	RADIO_CBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL_Pos = 0x7
	// Bit mask of CBIAS0_TRIM_TST_SEL field.
	RADIO_CBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL_Msk = 0x80
	// Bit CBIAS0_TRIM_TST_SEL.
	RADIO_CBIAS1_ANA_ENG_CBIAS0_TRIM_TST_SEL = 0x80

	// SYNTHCAL0_DIG_OUT: SYNTHCAL0_DIG_OUT register
	// Position of VCO_CALAMP_OUT_6_0 field.
	RADIO_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Pos = 0x0
	// Bit mask of VCO_CALAMP_OUT_6_0 field.
	RADIO_SYNTHCAL0_DIG_OUT_VCO_CALAMP_OUT_6_0_Msk = 0x7f

	// SYNTHCAL1_DIG_OUT: SYNTHCAL1_DIG_OUT register
	// Position of VCO_CALAMP_OUT_10_7 field.
	RADIO_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Pos = 0x0
	// Bit mask of VCO_CALAMP_OUT_10_7 field.
	RADIO_SYNTHCAL1_DIG_OUT_VCO_CALAMP_OUT_10_7_Msk = 0xf

	// SYNTHCAL2_DIG_OUT: SYNTHCAL2_DIG_OUT register
	// Position of VCO_CALFREQ_OUT field.
	RADIO_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Pos = 0x0
	// Bit mask of VCO_CALFREQ_OUT field.
	RADIO_SYNTHCAL2_DIG_OUT_VCO_CALFREQ_OUT_Msk = 0x7f

	// SYNTHCAL3_DIG_OUT: SYNTHCAL3_DIG_OUT register
	// Position of SYNTHCAL_DEBUG_BUS field.
	RADIO_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Pos = 0x0
	// Bit mask of SYNTHCAL_DEBUG_BUS field.
	RADIO_SYNTHCAL3_DIG_OUT_SYNTHCAL_DEBUG_BUS_Msk = 0xff

	// SYNTHCAL4_DIG_OUT: SYNTHCAL4_DIG_OUT register
	// Position of MOD_REF_DAC_WORD_OUT field.
	RADIO_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Pos = 0x0
	// Bit mask of MOD_REF_DAC_WORD_OUT field.
	RADIO_SYNTHCAL4_DIG_OUT_MOD_REF_DAC_WORD_OUT_Msk = 0x3f

	// SYNTHCAL5_DIG_OUT: SYNTHCAL5_DIG_OUT register
	// Position of CBP_CALIB_WORD field.
	RADIO_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Pos = 0x0
	// Bit mask of CBP_CALIB_WORD field.
	RADIO_SYNTHCAL5_DIG_OUT_CBP_CALIB_WORD_Msk = 0xf

	// FSM_STATUS_DIG_OUT: FSM_STATUS_DIG_OUT register
	// Position of STATUS field.
	RADIO_FSM_STATUS_DIG_OUT_STATUS_Pos = 0x0
	// Bit mask of STATUS field.
	RADIO_FSM_STATUS_DIG_OUT_STATUS_Msk = 0x1f
	// Position of SYNTH_CAL_ERROR field.
	RADIO_FSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR_Pos = 0x7
	// Bit mask of SYNTH_CAL_ERROR field.
	RADIO_FSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR_Msk = 0x80
	// Bit SYNTH_CAL_ERROR.
	RADIO_FSM_STATUS_DIG_OUT_SYNTH_CAL_ERROR = 0x80

	// RSSI0_DIG_OUT: RSSI0_DIG_OUT register
	// Position of RSSI_MEAS_OUT_7_0 field.
	RADIO_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Pos = 0x0
	// Bit mask of RSSI_MEAS_OUT_7_0 field.
	RADIO_RSSI0_DIG_OUT_RSSI_MEAS_OUT_7_0_Msk = 0xff

	// RSSI1_DIG_OUT: RSSI1_DIG_OUT register
	// Position of RSSI_MEAS_OUT_15_8 field.
	RADIO_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Pos = 0x0
	// Bit mask of RSSI_MEAS_OUT_15_8 field.
	RADIO_RSSI1_DIG_OUT_RSSI_MEAS_OUT_15_8_Msk = 0xff

	// AGC_DIG_OUT: AGC_DIG_OUT register
	// Position of AGC_ATT_OUT field.
	RADIO_AGC_DIG_OUT_AGC_ATT_OUT_Pos = 0x0
	// Bit mask of AGC_ATT_OUT field.
	RADIO_AGC_DIG_OUT_AGC_ATT_OUT_Msk = 0xf

	// DEMOD_DIG_OUT: DEMOD_DIG_OUT register
	// Position of CI_FIELD field.
	RADIO_DEMOD_DIG_OUT_CI_FIELD_Pos = 0x0
	// Bit mask of CI_FIELD field.
	RADIO_DEMOD_DIG_OUT_CI_FIELD_Msk = 0x3
	// Position of AAC_FOUND field.
	RADIO_DEMOD_DIG_OUT_AAC_FOUND_Pos = 0x2
	// Bit mask of AAC_FOUND field.
	RADIO_DEMOD_DIG_OUT_AAC_FOUND_Msk = 0x4
	// Bit AAC_FOUND.
	RADIO_DEMOD_DIG_OUT_AAC_FOUND = 0x4
	// Position of PD_FOUND field.
	RADIO_DEMOD_DIG_OUT_PD_FOUND_Pos = 0x3
	// Bit mask of PD_FOUND field.
	RADIO_DEMOD_DIG_OUT_PD_FOUND_Msk = 0x8
	// Bit PD_FOUND.
	RADIO_DEMOD_DIG_OUT_PD_FOUND = 0x8
	// Position of RX_END field.
	RADIO_DEMOD_DIG_OUT_RX_END_Pos = 0x4
	// Bit mask of RX_END field.
	RADIO_DEMOD_DIG_OUT_RX_END_Msk = 0x10
	// Bit RX_END.
	RADIO_DEMOD_DIG_OUT_RX_END = 0x10

	// AGC2_ANA_TST: AGC2_ANA_TST register
	// Position of AGC2_ANA_TST_SEL field.
	RADIO_AGC2_ANA_TST_AGC2_ANA_TST_SEL_Pos = 0x0
	// Bit mask of AGC2_ANA_TST_SEL field.
	RADIO_AGC2_ANA_TST_AGC2_ANA_TST_SEL_Msk = 0x1
	// Bit AGC2_ANA_TST_SEL.
	RADIO_AGC2_ANA_TST_AGC2_ANA_TST_SEL = 0x1
	// Position of AGC_ANTENNAE_USR_TRIM field.
	RADIO_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Pos = 0x1
	// Bit mask of AGC_ANTENNAE_USR_TRIM field.
	RADIO_AGC2_ANA_TST_AGC_ANTENNAE_USR_TRIM_Msk = 0xe

	// AGC0_DIG_ENG: AGC0_DIG_ENG register
	// Position of AGC_THR_HIGH field.
	RADIO_AGC0_DIG_ENG_AGC_THR_HIGH_Pos = 0x0
	// Bit mask of AGC_THR_HIGH field.
	RADIO_AGC0_DIG_ENG_AGC_THR_HIGH_Msk = 0x3f
	// Position of AGC_ENABLE field.
	RADIO_AGC0_DIG_ENG_AGC_ENABLE_Pos = 0x6
	// Bit mask of AGC_ENABLE field.
	RADIO_AGC0_DIG_ENG_AGC_ENABLE_Msk = 0x40
	// Bit AGC_ENABLE.
	RADIO_AGC0_DIG_ENG_AGC_ENABLE = 0x40

	// AGC1_DIG_ENG: AGC1_DIG_ENG register
	// Position of AGC_THR_LOW_6 field.
	RADIO_AGC1_DIG_ENG_AGC_THR_LOW_6_Pos = 0x0
	// Bit mask of AGC_THR_LOW_6 field.
	RADIO_AGC1_DIG_ENG_AGC_THR_LOW_6_Msk = 0x3f
	// Position of AGC_AUTOLOCK field.
	RADIO_AGC1_DIG_ENG_AGC_AUTOLOCK_Pos = 0x6
	// Bit mask of AGC_AUTOLOCK field.
	RADIO_AGC1_DIG_ENG_AGC_AUTOLOCK_Msk = 0x40
	// Bit AGC_AUTOLOCK.
	RADIO_AGC1_DIG_ENG_AGC_AUTOLOCK = 0x40
	// Position of AGC_LOCK_SYNC field.
	RADIO_AGC1_DIG_ENG_AGC_LOCK_SYNC_Pos = 0x7
	// Bit mask of AGC_LOCK_SYNC field.
	RADIO_AGC1_DIG_ENG_AGC_LOCK_SYNC_Msk = 0x80
	// Bit AGC_LOCK_SYNC.
	RADIO_AGC1_DIG_ENG_AGC_LOCK_SYNC = 0x80

	// AGC10_DIG_ENG: AGC10_DIG_ENG register
	// Position of ATT_IF_0 field.
	RADIO_AGC10_DIG_ENG_ATT_IF_0_Pos = 0x0
	// Bit mask of ATT_IF_0 field.
	RADIO_AGC10_DIG_ENG_ATT_IF_0_Msk = 0x7
	// Position of ATT_LNA_0 field.
	RADIO_AGC10_DIG_ENG_ATT_LNA_0_Pos = 0x3
	// Bit mask of ATT_LNA_0 field.
	RADIO_AGC10_DIG_ENG_ATT_LNA_0_Msk = 0x8
	// Bit ATT_LNA_0.
	RADIO_AGC10_DIG_ENG_ATT_LNA_0 = 0x8
	// Position of ATT_ANT_0 field.
	RADIO_AGC10_DIG_ENG_ATT_ANT_0_Pos = 0x4
	// Bit mask of ATT_ANT_0 field.
	RADIO_AGC10_DIG_ENG_ATT_ANT_0_Msk = 0x30

	// AGC11_DIG_ENG: AGC11_DIG_ENG register
	// Position of ATT_IF_1 field.
	RADIO_AGC11_DIG_ENG_ATT_IF_1_Pos = 0x0
	// Bit mask of ATT_IF_1 field.
	RADIO_AGC11_DIG_ENG_ATT_IF_1_Msk = 0x7
	// Position of ATT_LNA_1 field.
	RADIO_AGC11_DIG_ENG_ATT_LNA_1_Pos = 0x3
	// Bit mask of ATT_LNA_1 field.
	RADIO_AGC11_DIG_ENG_ATT_LNA_1_Msk = 0x8
	// Bit ATT_LNA_1.
	RADIO_AGC11_DIG_ENG_ATT_LNA_1 = 0x8
	// Position of ATT_ANT_1 field.
	RADIO_AGC11_DIG_ENG_ATT_ANT_1_Pos = 0x4
	// Bit mask of ATT_ANT_1 field.
	RADIO_AGC11_DIG_ENG_ATT_ANT_1_Msk = 0x30

	// AGC12_DIG_ENG: AGC12_DIG_ENG register
	// Position of ATT_IF_2 field.
	RADIO_AGC12_DIG_ENG_ATT_IF_2_Pos = 0x0
	// Bit mask of ATT_IF_2 field.
	RADIO_AGC12_DIG_ENG_ATT_IF_2_Msk = 0x7
	// Position of ATT_LNA_2 field.
	RADIO_AGC12_DIG_ENG_ATT_LNA_2_Pos = 0x3
	// Bit mask of ATT_LNA_2 field.
	RADIO_AGC12_DIG_ENG_ATT_LNA_2_Msk = 0x8
	// Bit ATT_LNA_2.
	RADIO_AGC12_DIG_ENG_ATT_LNA_2 = 0x8
	// Position of ATT_ANT_2 field.
	RADIO_AGC12_DIG_ENG_ATT_ANT_2_Pos = 0x4
	// Bit mask of ATT_ANT_2 field.
	RADIO_AGC12_DIG_ENG_ATT_ANT_2_Msk = 0x30

	// AGC13_DIG_ENG: AGC13_DIG_ENG register
	// Position of ATT_IF_3 field.
	RADIO_AGC13_DIG_ENG_ATT_IF_3_Pos = 0x0
	// Bit mask of ATT_IF_3 field.
	RADIO_AGC13_DIG_ENG_ATT_IF_3_Msk = 0x7
	// Position of ATT_LNA_3 field.
	RADIO_AGC13_DIG_ENG_ATT_LNA_3_Pos = 0x3
	// Bit mask of ATT_LNA_3 field.
	RADIO_AGC13_DIG_ENG_ATT_LNA_3_Msk = 0x8
	// Bit ATT_LNA_3.
	RADIO_AGC13_DIG_ENG_ATT_LNA_3 = 0x8
	// Position of ATT_ANT_3 field.
	RADIO_AGC13_DIG_ENG_ATT_ANT_3_Pos = 0x4
	// Bit mask of ATT_ANT_3 field.
	RADIO_AGC13_DIG_ENG_ATT_ANT_3_Msk = 0x30

	// AGC14_DIG_ENG: AGC14_DIG_ENG register
	// Position of ATT_IF_4 field.
	RADIO_AGC14_DIG_ENG_ATT_IF_4_Pos = 0x0
	// Bit mask of ATT_IF_4 field.
	RADIO_AGC14_DIG_ENG_ATT_IF_4_Msk = 0x7
	// Position of ATT_LNA_4 field.
	RADIO_AGC14_DIG_ENG_ATT_LNA_4_Pos = 0x3
	// Bit mask of ATT_LNA_4 field.
	RADIO_AGC14_DIG_ENG_ATT_LNA_4_Msk = 0x8
	// Bit ATT_LNA_4.
	RADIO_AGC14_DIG_ENG_ATT_LNA_4 = 0x8
	// Position of ATT_ANT_4 field.
	RADIO_AGC14_DIG_ENG_ATT_ANT_4_Pos = 0x4
	// Bit mask of ATT_ANT_4 field.
	RADIO_AGC14_DIG_ENG_ATT_ANT_4_Msk = 0x30

	// AGC15_DIG_ENG: AGC15_DIG_ENG register
	// Position of ATT_IF_5 field.
	RADIO_AGC15_DIG_ENG_ATT_IF_5_Pos = 0x0
	// Bit mask of ATT_IF_5 field.
	RADIO_AGC15_DIG_ENG_ATT_IF_5_Msk = 0x7
	// Position of ATT_LNA_5 field.
	RADIO_AGC15_DIG_ENG_ATT_LNA_5_Pos = 0x3
	// Bit mask of ATT_LNA_5 field.
	RADIO_AGC15_DIG_ENG_ATT_LNA_5_Msk = 0x8
	// Bit ATT_LNA_5.
	RADIO_AGC15_DIG_ENG_ATT_LNA_5 = 0x8
	// Position of ATT_ANT_5 field.
	RADIO_AGC15_DIG_ENG_ATT_ANT_5_Pos = 0x4
	// Bit mask of ATT_ANT_5 field.
	RADIO_AGC15_DIG_ENG_ATT_ANT_5_Msk = 0x30

	// AGC16_DIG_ENG: AGC16_DIG_ENG register
	// Position of ATT_IF_6 field.
	RADIO_AGC16_DIG_ENG_ATT_IF_6_Pos = 0x0
	// Bit mask of ATT_IF_6 field.
	RADIO_AGC16_DIG_ENG_ATT_IF_6_Msk = 0x7
	// Position of ATT_LNA_6 field.
	RADIO_AGC16_DIG_ENG_ATT_LNA_6_Pos = 0x3
	// Bit mask of ATT_LNA_6 field.
	RADIO_AGC16_DIG_ENG_ATT_LNA_6_Msk = 0x8
	// Bit ATT_LNA_6.
	RADIO_AGC16_DIG_ENG_ATT_LNA_6 = 0x8
	// Position of ATT_ANT_6 field.
	RADIO_AGC16_DIG_ENG_ATT_ANT_6_Pos = 0x4
	// Bit mask of ATT_ANT_6 field.
	RADIO_AGC16_DIG_ENG_ATT_ANT_6_Msk = 0x30

	// AGC17_DIG_ENG: AGC17_DIG_ENG register
	// Position of ATT_IF_7 field.
	RADIO_AGC17_DIG_ENG_ATT_IF_7_Pos = 0x0
	// Bit mask of ATT_IF_7 field.
	RADIO_AGC17_DIG_ENG_ATT_IF_7_Msk = 0x7
	// Position of ATT_LNA_7 field.
	RADIO_AGC17_DIG_ENG_ATT_LNA_7_Pos = 0x3
	// Bit mask of ATT_LNA_7 field.
	RADIO_AGC17_DIG_ENG_ATT_LNA_7_Msk = 0x8
	// Bit ATT_LNA_7.
	RADIO_AGC17_DIG_ENG_ATT_LNA_7 = 0x8
	// Position of ATT_ANT_7 field.
	RADIO_AGC17_DIG_ENG_ATT_ANT_7_Pos = 0x4
	// Bit mask of ATT_ANT_7 field.
	RADIO_AGC17_DIG_ENG_ATT_ANT_7_Msk = 0x30

	// AGC18_DIG_ENG: AGC18_DIG_ENG register
	// Position of ATT_IF_8 field.
	RADIO_AGC18_DIG_ENG_ATT_IF_8_Pos = 0x0
	// Bit mask of ATT_IF_8 field.
	RADIO_AGC18_DIG_ENG_ATT_IF_8_Msk = 0x7
	// Position of ATT_LNA_8 field.
	RADIO_AGC18_DIG_ENG_ATT_LNA_8_Pos = 0x3
	// Bit mask of ATT_LNA_8 field.
	RADIO_AGC18_DIG_ENG_ATT_LNA_8_Msk = 0x8
	// Bit ATT_LNA_8.
	RADIO_AGC18_DIG_ENG_ATT_LNA_8 = 0x8
	// Position of ATT_ANT_8 field.
	RADIO_AGC18_DIG_ENG_ATT_ANT_8_Pos = 0x4
	// Bit mask of ATT_ANT_8 field.
	RADIO_AGC18_DIG_ENG_ATT_ANT_8_Msk = 0x30

	// AGC19_DIG_ENG: AGC19_DIG_ENG register
	// Position of ATT_IF_9 field.
	RADIO_AGC19_DIG_ENG_ATT_IF_9_Pos = 0x0
	// Bit mask of ATT_IF_9 field.
	RADIO_AGC19_DIG_ENG_ATT_IF_9_Msk = 0x7
	// Position of ATT_LNA_9 field.
	RADIO_AGC19_DIG_ENG_ATT_LNA_9_Pos = 0x3
	// Bit mask of ATT_LNA_9 field.
	RADIO_AGC19_DIG_ENG_ATT_LNA_9_Msk = 0x8
	// Bit ATT_LNA_9.
	RADIO_AGC19_DIG_ENG_ATT_LNA_9 = 0x8
	// Position of ATT_ANT_9 field.
	RADIO_AGC19_DIG_ENG_ATT_ANT_9_Pos = 0x4
	// Bit mask of ATT_ANT_9 field.
	RADIO_AGC19_DIG_ENG_ATT_ANT_9_Msk = 0x30

	// RXADC_HW_TRIM_OUT: RXADC_HW_TRIM_OUT register
	// Position of HW_RXADC_DELAYTRIM_I field.
	RADIO_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Pos = 0x0
	// Bit mask of HW_RXADC_DELAYTRIM_I field.
	RADIO_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_I_Msk = 0x7
	// Position of HW_RXADC_DELAYTRIM_Q field.
	RADIO_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Pos = 0x3
	// Bit mask of HW_RXADC_DELAYTRIM_Q field.
	RADIO_RXADC_HW_TRIM_OUT_HW_RXADC_DELAYTRIM_Q_Msk = 0x38

	// CBIAS0_HW_TRIM_OUT: CBIAS0_HW_TRIM_OUT register
	// Position of HW_CBIAS_IBIAS_TRIM field.
	RADIO_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Pos = 0x0
	// Bit mask of HW_CBIAS_IBIAS_TRIM field.
	RADIO_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IBIAS_TRIM_Msk = 0xf
	// Position of HW_CBIAS_IPTAT_TRIM field.
	RADIO_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Pos = 0x4
	// Bit mask of HW_CBIAS_IPTAT_TRIM field.
	RADIO_CBIAS0_HW_TRIM_OUT_HW_CBIAS_IPTAT_TRIM_Msk = 0xf0

	// AGC_HW_TRIM_OUT: AGC_HW_TRIM_OUT register
	// Position of HW_AGC_ANTENNAE_TRIM field.
	RADIO_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Pos = 0x1
	// Bit mask of HW_AGC_ANTENNAE_TRIM field.
	RADIO_AGC_HW_TRIM_OUT_HW_AGC_ANTENNAE_TRIM_Msk = 0xe

	// DEMOD_IQ2_DIG_TST: DEMOD_IQ2_DIG_TST register
	// Position of EXTCFG_SAMPLING_TIME field.
	RADIO_DEMOD_IQ2_DIG_TST_EXTCFG_SAMPLING_TIME_Pos = 0x0
	// Bit mask of EXTCFG_SAMPLING_TIME field.
	RADIO_DEMOD_IQ2_DIG_TST_EXTCFG_SAMPLING_TIME_Msk = 0x3
	// Position of EXTCFG_TRIG_SELECTION field.
	RADIO_DEMOD_IQ2_DIG_TST_EXTCFG_TRIG_SELECTION_Pos = 0x2
	// Bit mask of EXTCFG_TRIG_SELECTION field.
	RADIO_DEMOD_IQ2_DIG_TST_EXTCFG_TRIG_SELECTION_Msk = 0xc

	// ANTSW0_DIG_USR: ANTSW0_DIG_USR register
	// Position of RX_TIME_TO_SAMPLE field.
	RADIO_ANTSW0_DIG_USR_RX_TIME_TO_SAMPLE_Pos = 0x0
	// Bit mask of RX_TIME_TO_SAMPLE field.
	RADIO_ANTSW0_DIG_USR_RX_TIME_TO_SAMPLE_Msk = 0x7f

	// ANTSW1_DIG_USR: ANTSW1_DIG_USR register
	// Position of RX_TIME_TO_SWITCH field.
	RADIO_ANTSW1_DIG_USR_RX_TIME_TO_SWITCH_Pos = 0x0
	// Bit mask of RX_TIME_TO_SWITCH field.
	RADIO_ANTSW1_DIG_USR_RX_TIME_TO_SWITCH_Msk = 0x3f

	// ANTSW2_DIG_USR: ANTSW2_DIG_USR register
	// Position of TX_TIME_TO_SWITCH field.
	RADIO_ANTSW2_DIG_USR_TX_TIME_TO_SWITCH_Pos = 0x0
	// Bit mask of TX_TIME_TO_SWITCH field.
	RADIO_ANTSW2_DIG_USR_TX_TIME_TO_SWITCH_Msk = 0x7f

	// ANTSW3_DIG_USR: ANTSW3_DIG_USR register
	// Position of TX_TIME_TO_SWITCH_2M field.
	RADIO_ANTSW3_DIG_USR_TX_TIME_TO_SWITCH_2M_Pos = 0x0
	// Bit mask of TX_TIME_TO_SWITCH_2M field.
	RADIO_ANTSW3_DIG_USR_TX_TIME_TO_SWITCH_2M_Msk = 0x7f
)

// Constants for RRM
const (
	// UDRA_CTRL0: UDRA_CTRL0 register
	// Position of RELOAD_RDCFGPTR field.
	RRM_UDRA_CTRL0_RELOAD_RDCFGPTR_Pos = 0x0
	// Bit mask of RELOAD_RDCFGPTR field.
	RRM_UDRA_CTRL0_RELOAD_RDCFGPTR_Msk = 0x1
	// Bit RELOAD_RDCFGPTR.
	RRM_UDRA_CTRL0_RELOAD_RDCFGPTR = 0x1

	// UDRA_IRQ_ENABLE: UDRA_IRQ_ENABLE register
	// Position of RADIO_CFG_PTR_RELOADED field.
	RRM_UDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED_Pos = 0x0
	// Bit mask of RADIO_CFG_PTR_RELOADED field.
	RRM_UDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED_Msk = 0x1
	// Bit RADIO_CFG_PTR_RELOADED.
	RRM_UDRA_IRQ_ENABLE_RADIO_CFG_PTR_RELOADED = 0x1
	// Position of CMD_START field.
	RRM_UDRA_IRQ_ENABLE_CMD_START_Pos = 0x1
	// Bit mask of CMD_START field.
	RRM_UDRA_IRQ_ENABLE_CMD_START_Msk = 0x2
	// Bit CMD_START.
	RRM_UDRA_IRQ_ENABLE_CMD_START = 0x2
	// Position of CMD_END field.
	RRM_UDRA_IRQ_ENABLE_CMD_END_Pos = 0x2
	// Bit mask of CMD_END field.
	RRM_UDRA_IRQ_ENABLE_CMD_END_Msk = 0x4
	// Bit CMD_END.
	RRM_UDRA_IRQ_ENABLE_CMD_END = 0x4

	// UDRA_IRQ_STATUS: UDRA_IRQ_STATUS register
	// Position of RADIO_CFG_PTR_RELOADED field.
	RRM_UDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED_Pos = 0x0
	// Bit mask of RADIO_CFG_PTR_RELOADED field.
	RRM_UDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED_Msk = 0x1
	// Bit RADIO_CFG_PTR_RELOADED.
	RRM_UDRA_IRQ_STATUS_RADIO_CFG_PTR_RELOADED = 0x1
	// Position of CMD_STARD field.
	RRM_UDRA_IRQ_STATUS_CMD_STARD_Pos = 0x1
	// Bit mask of CMD_STARD field.
	RRM_UDRA_IRQ_STATUS_CMD_STARD_Msk = 0x2
	// Bit CMD_STARD.
	RRM_UDRA_IRQ_STATUS_CMD_STARD = 0x2
	// Position of CMD_END field.
	RRM_UDRA_IRQ_STATUS_CMD_END_Pos = 0x2
	// Bit mask of CMD_END field.
	RRM_UDRA_IRQ_STATUS_CMD_END_Msk = 0x4
	// Bit CMD_END.
	RRM_UDRA_IRQ_STATUS_CMD_END = 0x4

	// UDRA_RADIO_CFG_PTR: UDRA_RADIO_CFG_PTR register
	// Position of RADIO_CONFIG_ADDRESS field.
	RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Pos = 0x0
	// Bit mask of RADIO_CONFIG_ADDRESS field.
	RRM_UDRA_RADIO_CFG_PTR_RADIO_CONFIG_ADDRESS_Msk = 0xffffffff

	// SEMA_IRQ_ENABLE: SEMA_IRQ_ENABLE register
	// Position of LOCK field.
	RRM_SEMA_IRQ_ENABLE_LOCK_Pos = 0x0
	// Bit mask of LOCK field.
	RRM_SEMA_IRQ_ENABLE_LOCK_Msk = 0x1
	// Bit LOCK.
	RRM_SEMA_IRQ_ENABLE_LOCK = 0x1
	// Position of UNLOCK field.
	RRM_SEMA_IRQ_ENABLE_UNLOCK_Pos = 0x1
	// Bit mask of UNLOCK field.
	RRM_SEMA_IRQ_ENABLE_UNLOCK_Msk = 0x2
	// Bit UNLOCK.
	RRM_SEMA_IRQ_ENABLE_UNLOCK = 0x2

	// SEMA_IRQ_STATUS: SEMA_IRQ_STATUS register
	// Position of LOCK field.
	RRM_SEMA_IRQ_STATUS_LOCK_Pos = 0x0
	// Bit mask of LOCK field.
	RRM_SEMA_IRQ_STATUS_LOCK_Msk = 0x1
	// Bit LOCK.
	RRM_SEMA_IRQ_STATUS_LOCK = 0x1
	// Position of UNLOCK field.
	RRM_SEMA_IRQ_STATUS_UNLOCK_Pos = 0x1
	// Bit mask of UNLOCK field.
	RRM_SEMA_IRQ_STATUS_UNLOCK_Msk = 0x2
	// Bit UNLOCK.
	RRM_SEMA_IRQ_STATUS_UNLOCK = 0x2

	// BLE_IRQ_ENABLE: BLE_IRQ_ENABLE register
	// Position of PORT_GRANT field.
	RRM_BLE_IRQ_ENABLE_PORT_GRANT_Pos = 0x0
	// Bit mask of PORT_GRANT field.
	RRM_BLE_IRQ_ENABLE_PORT_GRANT_Msk = 0x1
	// Bit PORT_GRANT.
	RRM_BLE_IRQ_ENABLE_PORT_GRANT = 0x1
	// Position of PORT_RELEASE field.
	RRM_BLE_IRQ_ENABLE_PORT_RELEASE_Pos = 0x1
	// Bit mask of PORT_RELEASE field.
	RRM_BLE_IRQ_ENABLE_PORT_RELEASE_Msk = 0x2
	// Bit PORT_RELEASE.
	RRM_BLE_IRQ_ENABLE_PORT_RELEASE = 0x2
	// Position of PORT_CMD_START field.
	RRM_BLE_IRQ_ENABLE_PORT_CMD_START_Pos = 0x3
	// Bit mask of PORT_CMD_START field.
	RRM_BLE_IRQ_ENABLE_PORT_CMD_START_Msk = 0x8
	// Bit PORT_CMD_START.
	RRM_BLE_IRQ_ENABLE_PORT_CMD_START = 0x8
	// Position of PORT_CMD_END field.
	RRM_BLE_IRQ_ENABLE_PORT_CMD_END_Pos = 0x4
	// Bit mask of PORT_CMD_END field.
	RRM_BLE_IRQ_ENABLE_PORT_CMD_END_Msk = 0x10
	// Bit PORT_CMD_END.
	RRM_BLE_IRQ_ENABLE_PORT_CMD_END = 0x10

	// BLE_IRQ_STATUS: BLE_IRQ_STATUS register
	// Position of PORT_GRANT field.
	RRM_BLE_IRQ_STATUS_PORT_GRANT_Pos = 0x0
	// Bit mask of PORT_GRANT field.
	RRM_BLE_IRQ_STATUS_PORT_GRANT_Msk = 0x1
	// Bit PORT_GRANT.
	RRM_BLE_IRQ_STATUS_PORT_GRANT = 0x1
	// Position of PORT_RELEASE field.
	RRM_BLE_IRQ_STATUS_PORT_RELEASE_Pos = 0x1
	// Bit mask of PORT_RELEASE field.
	RRM_BLE_IRQ_STATUS_PORT_RELEASE_Msk = 0x2
	// Bit PORT_RELEASE.
	RRM_BLE_IRQ_STATUS_PORT_RELEASE = 0x2
	// Position of CMD_START field.
	RRM_BLE_IRQ_STATUS_CMD_START_Pos = 0x3
	// Bit mask of CMD_START field.
	RRM_BLE_IRQ_STATUS_CMD_START_Msk = 0x8
	// Bit CMD_START.
	RRM_BLE_IRQ_STATUS_CMD_START = 0x8
	// Position of CMD_END field.
	RRM_BLE_IRQ_STATUS_CMD_END_Pos = 0x4
	// Bit mask of CMD_END field.
	RRM_BLE_IRQ_STATUS_CMD_END_Msk = 0x10
	// Bit CMD_END.
	RRM_BLE_IRQ_STATUS_CMD_END = 0x10

	// VP_CPU_CMD_BUS: VP_CPU_CMD_BUS register
	// Position of COMMAND field.
	RRM_VP_CPU_CMD_BUS_COMMAND_Pos = 0x0
	// Bit mask of COMMAND field.
	RRM_VP_CPU_CMD_BUS_COMMAND_Msk = 0x7
	// Position of COMMAND_REQ field.
	RRM_VP_CPU_CMD_BUS_COMMAND_REQ_Pos = 0x3
	// Bit mask of COMMAND_REQ field.
	RRM_VP_CPU_CMD_BUS_COMMAND_REQ_Msk = 0x8
	// Bit COMMAND_REQ.
	RRM_VP_CPU_CMD_BUS_COMMAND_REQ = 0x8

	// VP_CPU_SEMA_BUS: VP_CPU_SEMA_BUS register
	// Position of TAKE_PRIO field.
	RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Pos = 0x0
	// Bit mask of TAKE_PRIO field.
	RRM_VP_CPU_SEMA_BUS_TAKE_PRIO_Msk = 0x7
	// Position of TAKE_REQ field.
	RRM_VP_CPU_SEMA_BUS_TAKE_REQ_Pos = 0x3
	// Bit mask of TAKE_REQ field.
	RRM_VP_CPU_SEMA_BUS_TAKE_REQ_Msk = 0x8
	// Bit TAKE_REQ.
	RRM_VP_CPU_SEMA_BUS_TAKE_REQ = 0x8

	// VP_CPU_IRQ_ENABLE: VP_CPU_IRQ_ENABLE register
	// Position of PORT_GRANT field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_GRANT_Pos = 0x0
	// Bit mask of PORT_GRANT field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_GRANT_Msk = 0x1
	// Bit PORT_GRANT.
	RRM_VP_CPU_IRQ_ENABLE_PORT_GRANT = 0x1
	// Position of PORT_RELEASE field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_RELEASE_Pos = 0x1
	// Bit mask of PORT_RELEASE field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_RELEASE_Msk = 0x2
	// Bit PORT_RELEASE.
	RRM_VP_CPU_IRQ_ENABLE_PORT_RELEASE = 0x2
	// Position of PORT_CMD_START field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_START_Pos = 0x3
	// Bit mask of PORT_CMD_START field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_START_Msk = 0x8
	// Bit PORT_CMD_START.
	RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_START = 0x8
	// Position of PORT_CMD_END field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_END_Pos = 0x4
	// Bit mask of PORT_CMD_END field.
	RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_END_Msk = 0x10
	// Bit PORT_CMD_END.
	RRM_VP_CPU_IRQ_ENABLE_PORT_CMD_END = 0x10

	// VP_CPU_IRQ_STATUS: VP_CPU_IRQ_STATUS register
	// Position of PORT_GRANT field.
	RRM_VP_CPU_IRQ_STATUS_PORT_GRANT_Pos = 0x0
	// Bit mask of PORT_GRANT field.
	RRM_VP_CPU_IRQ_STATUS_PORT_GRANT_Msk = 0x1
	// Bit PORT_GRANT.
	RRM_VP_CPU_IRQ_STATUS_PORT_GRANT = 0x1
	// Position of PORT_RELEASE field.
	RRM_VP_CPU_IRQ_STATUS_PORT_RELEASE_Pos = 0x1
	// Bit mask of PORT_RELEASE field.
	RRM_VP_CPU_IRQ_STATUS_PORT_RELEASE_Msk = 0x2
	// Bit PORT_RELEASE.
	RRM_VP_CPU_IRQ_STATUS_PORT_RELEASE = 0x2
	// Position of PORT_PREEMPT field.
	RRM_VP_CPU_IRQ_STATUS_PORT_PREEMPT_Pos = 0x2
	// Bit mask of PORT_PREEMPT field.
	RRM_VP_CPU_IRQ_STATUS_PORT_PREEMPT_Msk = 0x4
	// Bit PORT_PREEMPT.
	RRM_VP_CPU_IRQ_STATUS_PORT_PREEMPT = 0x4
	// Position of CMD_START field.
	RRM_VP_CPU_IRQ_STATUS_CMD_START_Pos = 0x3
	// Bit mask of CMD_START field.
	RRM_VP_CPU_IRQ_STATUS_CMD_START_Msk = 0x8
	// Bit CMD_START.
	RRM_VP_CPU_IRQ_STATUS_CMD_START = 0x8
	// Position of CMD_END field.
	RRM_VP_CPU_IRQ_STATUS_CMD_END_Pos = 0x4
	// Bit mask of CMD_END field.
	RRM_VP_CPU_IRQ_STATUS_CMD_END_Msk = 0x10
	// Bit CMD_END.
	RRM_VP_CPU_IRQ_STATUS_CMD_END = 0x10
)

// Constants for WAKEUP
const (
	// OFFSET: WAKEUP_OFFSET register
	// Position of WAKEUP_OFFSET field.
	WAKEUP_OFFSET_WAKEUP_OFFSET_Pos = 0x0
	// Bit mask of WAKEUP_OFFSET field.
	WAKEUP_OFFSET_WAKEUP_OFFSET_Msk = 0xff

	// ABSOLUTE_TIME: ABSOLUTE_TIME register
	// Position of ABSOLUTE_TIME field.
	WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Pos = 0x0
	// Bit mask of ABSOLUTE_TIME field.
	WAKEUP_ABSOLUTE_TIME_ABSOLUTE_TIME_Msk = 0xffffffff

	// MINIMUM_PERIOD_LENGTH: MINIMUM_PERIOD_LENGTH register
	// Position of LENGTH field.
	WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	WAKEUP_MINIMUM_PERIOD_LENGTH_LENGTH_Msk = 0x3ff0

	// AVERAGE_PERIOD_LENGTH: AVERAGE_PERIOD_LENGTH register
	// Position of LENGTH_FRACT field.
	WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Pos = 0x0
	// Bit mask of LENGTH_FRACT field.
	WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_FRACT_Msk = 0xf
	// Position of LENGTH_INT field.
	WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Pos = 0x4
	// Bit mask of LENGTH_INT field.
	WAKEUP_AVERAGE_PERIOD_LENGTH_LENGTH_INT_Msk = 0x3ff0
	// Position of AVERAGE_COUNT field.
	WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Pos = 0x18
	// Bit mask of AVERAGE_COUNT field.
	WAKEUP_AVERAGE_PERIOD_LENGTH_AVERAGE_COUNT_Msk = 0xff000000

	// MAXIMUM_PERIOD_LENGTH: MAXIMUM_PERIOD_LENGTH register
	// Position of LENGTH field.
	WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Pos = 0x4
	// Bit mask of LENGTH field.
	WAKEUP_MAXIMUM_PERIOD_LENGTH_LENGTH_Msk = 0x3ff0

	// STATISTICS_RESTART: STATISTICS_RESTART register
	// Position of CLR_MIN_MAX field.
	WAKEUP_STATISTICS_RESTART_CLR_MIN_MAX_Pos = 0x0
	// Bit mask of CLR_MIN_MAX field.
	WAKEUP_STATISTICS_RESTART_CLR_MIN_MAX_Msk = 0x1
	// Bit CLR_MIN_MAX.
	WAKEUP_STATISTICS_RESTART_CLR_MIN_MAX = 0x1
	// Position of CLR_AVR field.
	WAKEUP_STATISTICS_RESTART_CLR_AVR_Pos = 0x1
	// Bit mask of CLR_AVR field.
	WAKEUP_STATISTICS_RESTART_CLR_AVR_Msk = 0x2
	// Bit CLR_AVR.
	WAKEUP_STATISTICS_RESTART_CLR_AVR = 0x2

	// BLUE_WAKEUP_TIME: BLUE_WAKEUP_TIME register
	// Position of WAKEUP_TIME field.
	WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Pos = 0x0
	// Bit mask of WAKEUP_TIME field.
	WAKEUP_BLUE_WAKEUP_TIME_WAKEUP_TIME_Msk = 0xffffffff

	// BLUE_SLEEP_REQUEST_MODE: BLUE_SLEEP_REQUEST_MODE register
	// Position of SLEEP_EN field.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN_Pos = 0x1d
	// Bit mask of SLEEP_EN field.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN_Msk = 0x20000000
	// Bit SLEEP_EN.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_EN = 0x20000000
	// Position of BLE_WAKEUP_EN field.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN_Pos = 0x1e
	// Bit mask of BLE_WAKEUP_EN field.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN_Msk = 0x40000000
	// Bit BLE_WAKEUP_EN.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_BLE_WAKEUP_EN = 0x40000000
	// Position of FORCE_SLEEPING field.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Pos = 0x1f
	// Bit mask of FORCE_SLEEPING field.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Msk = 0x80000000
	// Bit FORCE_SLEEPING.
	WAKEUP_BLUE_SLEEP_REQUEST_MODE_FORCE_SLEEPING = 0x80000000

	// CM0_WAKEUP_TIME: CM0_WAKEUP_TIME register
	// Position of WAKEUP_TIME field.
	WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Pos = 0x4
	// Bit mask of WAKEUP_TIME field.
	WAKEUP_CM0_WAKEUP_TIME_WAKEUP_TIME_Msk = 0xfffffff0

	// CM0_SLEEP_REQUEST_MODE: CM0_SLEEP_REQUEST_MODE register
	// Position of CPU_WAKEUP_EN field.
	WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN_Pos = 0x1e
	// Bit mask of CPU_WAKEUP_EN field.
	WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN_Msk = 0x40000000
	// Bit CPU_WAKEUP_EN.
	WAKEUP_CM0_SLEEP_REQUEST_MODE_CPU_WAKEUP_EN = 0x40000000
	// Position of FORCE_SLEEPING field.
	WAKEUP_CM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Pos = 0x1f
	// Bit mask of FORCE_SLEEPING field.
	WAKEUP_CM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING_Msk = 0x80000000
	// Bit FORCE_SLEEPING.
	WAKEUP_CM0_SLEEP_REQUEST_MODE_FORCE_SLEEPING = 0x80000000

	// BLE_IRQ_ENABLE: WAKEUP_BLE_IRQ_ENABLE register
	// Position of WAKEUP_IT field.
	WAKEUP_BLE_IRQ_ENABLE_WAKEUP_IT_Pos = 0x0
	// Bit mask of WAKEUP_IT field.
	WAKEUP_BLE_IRQ_ENABLE_WAKEUP_IT_Msk = 0x1
	// Bit WAKEUP_IT.
	WAKEUP_BLE_IRQ_ENABLE_WAKEUP_IT = 0x1

	// BLE_IRQ_STATUS: WAKEUP_BLE_IRQ_STATUS register
	// Position of WAKEUP_IT field.
	WAKEUP_BLE_IRQ_STATUS_WAKEUP_IT_Pos = 0x0
	// Bit mask of WAKEUP_IT field.
	WAKEUP_BLE_IRQ_STATUS_WAKEUP_IT_Msk = 0x1
	// Bit WAKEUP_IT.
	WAKEUP_BLE_IRQ_STATUS_WAKEUP_IT = 0x1

	// CM0_IRQ_ENABLE: WAKEUP_CM0_IRQ_ENABLE register
	// Position of WAKEUP_IT field.
	WAKEUP_CM0_IRQ_ENABLE_WAKEUP_IT_Pos = 0x0
	// Bit mask of WAKEUP_IT field.
	WAKEUP_CM0_IRQ_ENABLE_WAKEUP_IT_Msk = 0x1
	// Bit WAKEUP_IT.
	WAKEUP_CM0_IRQ_ENABLE_WAKEUP_IT = 0x1

	// CM0_IRQ_STATUS: WAKEUP_CM0_IRQ_STATUS register
	// Position of WAKEUP_IT field.
	WAKEUP_CM0_IRQ_STATUS_WAKEUP_IT_Pos = 0x0
	// Bit mask of WAKEUP_IT field.
	WAKEUP_CM0_IRQ_STATUS_WAKEUP_IT_Msk = 0x1
	// Bit WAKEUP_IT.
	WAKEUP_CM0_IRQ_STATUS_WAKEUP_IT = 0x1
)
