// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from stm32u5a5.svd, see https://github.com/tinygo-org/stm32-svd

//go:build stm32 && stm32u5a5

/*
// STM32U5A5
*/

package stm32

import (
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "STM32U5A5"
	CPU          = "CM33"
	FPUPresent   = true
	NVICPrioBits = 4
)

// Interrupt numbers.
const (
	// System window watchdog
	IRQ_WWDG = 0

	// External interrupt/event controller
	IRQ_PVD_PVM = 1

	// Real-time clock
	IRQ_RTC = 2

	// Real-time clock
	IRQ_RTC_S = 3

	// Tamper and backup registers
	IRQ_TAMP = 4

	// RAMCFG
	IRQ_RAMCFG = 5

	// Flash
	IRQ_FLASH = 6

	// Flash
	IRQ_FLASH_S = 7

	// GTZC1_MPCBB1
	IRQ_GTZC = 8

	// Reset and clock control
	IRQ_RCC = 9

	// Reset and clock control
	IRQ_RCC_S = 10

	// External interrupt/event controller
	IRQ_EXTI0 = 11

	// External interrupt/event controller
	IRQ_EXTI1 = 12

	// External interrupt/event controller
	IRQ_EXTI2 = 13

	// External interrupt/event controller
	IRQ_EXTI3 = 14

	// External interrupt/event controller
	IRQ_EXTI4 = 15

	// External interrupt/event controller
	IRQ_EXTI5 = 16

	// External interrupt/event controller
	IRQ_EXTI6 = 17

	// External interrupt/event controller
	IRQ_EXTI7 = 18

	// External interrupt/event controller
	IRQ_EXTI8 = 19

	// External interrupt/event controller
	IRQ_EXTI9 = 20

	// External interrupt/event controller
	IRQ_EXTI10 = 21

	// External interrupt/event controller
	IRQ_EXTI11 = 22

	// External interrupt/event controller
	IRQ_EXTI12 = 23

	// External interrupt/event controller
	IRQ_EXTI13 = 24

	// External interrupt/event controller
	IRQ_EXTI14 = 25

	// External interrupt/event controller
	IRQ_EXTI15 = 26

	// Independent watchdog
	IRQ_IWDG = 27

	// Secure AES coprocessor
	IRQ_SAES = 28

	// GPDMA1
	IRQ_GPDMA1_CH0 = 29

	// GPDMA1
	IRQ_GPDMA1_CH1 = 30

	// GPDMA1
	IRQ_GPDMA1_CH2 = 31

	// GPDMA1
	IRQ_GPDMA1_CH3 = 32

	// GPDMA1
	IRQ_GPDMA1_CH4 = 33

	// GPDMA1
	IRQ_GPDMA1_CH5 = 34

	// GPDMA1
	IRQ_GPDMA1_CH6 = 35

	// GPDMA1
	IRQ_GPDMA1_CH7 = 36

	// ADC1
	IRQ_ADC12 = 37

	// Digital-to-analog converter
	IRQ_DAC1 = 38

	// FDCAN1_RAM
	IRQ_FDCAN1_IT0 = 39

	// FDCAN1_RAM
	IRQ_FDCAN1_IT1 = 40

	// Advanced-timers
	IRQ_TIM1_BRK = 41

	// Advanced-timers
	IRQ_TIM1_UP = 42

	// Advanced-timers
	IRQ_TIM1_TRG_COM = 43

	// Advanced-timers
	IRQ_TIM1_CC = 44

	// General-purpose-timers
	IRQ_TIM2 = 45

	IRQ_TIM3 = 46

	IRQ_TIM4 = 47

	IRQ_TIM5 = 48

	// General-purpose-timers
	IRQ_TIM6 = 49

	IRQ_TIM7 = 50

	IRQ_TIM8_BRK = 51

	IRQ_TIM8_UP = 52

	IRQ_TIM8_TRG_COM = 53

	IRQ_TIM8_CC = 54

	// Inter-integrated circuit
	IRQ_I2C1_EV = 55

	// Inter-integrated circuit
	IRQ_I2C1_ER = 56

	IRQ_I2C2_EV = 57

	IRQ_I2C2_ER = 58

	// Serial peripheral interface
	IRQ_SPI1 = 59

	IRQ_SPI2 = 60

	// Universal synchronous asynchronous receiver transmitter
	IRQ_USART1 = 61

	IRQ_USART2 = 62

	IRQ_USART3 = 63

	IRQ_UART4 = 64

	IRQ_UART5 = 65

	// Universal synchronous asynchronous receiver transmitter
	IRQ_LPUART1 = 66

	// Low power timer
	IRQ_LPTIM1 = 67

	IRQ_LPTIM2 = 68

	// General purpose timers
	IRQ_TIM15 = 69

	// General purpose timers
	IRQ_TIM16 = 70

	IRQ_TIM17 = 71

	// Comparator
	IRQ_COMP = 72

	// OTG_HS
	IRQ_OTG_HS = 73

	// Clock recovery system
	IRQ_CRS = 74

	// FMC
	IRQ_FMC = 75

	// OctoSPI
	IRQ_OCTOSPI1 = 76

	// Power control
	IRQ_PWR_S3WU = 77

	// Secure digital input/output MultiMediaCard interface
	IRQ_SDMMC1 = 78

	IRQ_SDMMC2 = 79

	// GPDMA1
	IRQ_GPDMA1_CH8 = 80

	// GPDMA1
	IRQ_GPDMA1_CH9 = 81

	// GPDMA1
	IRQ_GPDMA1_CH10 = 82

	// GPDMA1
	IRQ_GPDMA1_CH11 = 83

	// GPDMA1
	IRQ_GPDMA1_CH12 = 84

	// GPDMA1
	IRQ_GPDMA1_CH13 = 85

	// GPDMA1
	IRQ_GPDMA1_CH14 = 86

	// GPDMA1
	IRQ_GPDMA1_CH15 = 87

	IRQ_I2C3_EV = 88

	IRQ_I2C3_ER = 89

	// Serial audio interface
	IRQ_SAI1 = 90

	IRQ_SAI2 = 91

	// Touch sensing controller
	IRQ_TSC = 92

	// Advanced encryption standard hardware accelerator
	IRQ_AES = 93

	// Random number generator
	IRQ_RNG = 94

	// External interrupt/event controller
	IRQ_FPU = 95

	// Hash processor
	IRQ_HASH = 96

	// Private key accelerator
	IRQ_PKA = 97

	IRQ_LPTIM3 = 98

	IRQ_SPI3 = 99

	IRQ_I2C4_ER = 100

	IRQ_I2C4_EV = 101

	// Multi-function digital filter
	IRQ_MDF1_FLT0 = 102

	// Multi-function digital filter
	IRQ_MDF1_FLT1 = 103

	// Multi-function digital filter
	IRQ_MDF1_FLT2 = 104

	// Multi-function digital filter
	IRQ_MDF1_FLT3 = 105

	// USB Power Delivery interface
	IRQ_UCPD1 = 106

	// ICache
	IRQ_ICACHE = 107

	// On-The-Fly Decryption engine
	IRQ_OTFDEC1 = 108

	IRQ_OTFDEC2 = 109

	// Low power timer
	IRQ_LPTIM4 = 110

	// DCACHE1
	IRQ_DCACHE1 = 111

	// ADF1
	IRQ_ADF1_FLT0 = 112

	// ADC4
	IRQ_ADC4 = 113

	// LPDMA1
	IRQ_LPDMA1_CH0 = 114

	// LPDMA1
	IRQ_LPDMA1_CH1 = 115

	// LPDMA1
	IRQ_LPDMA1_CH2 = 116

	// LPDMA1
	IRQ_LPDMA1_CH3 = 117

	// DMA2D controller
	IRQ_DMA2D = 118

	// Digital camera interface
	IRQ_DCMI_PSSI = 119

	IRQ_OCTOSPI2 = 120

	// Multi-function digital filter
	IRQ_MDF1_FLT4 = 121

	// Multi-function digital filter
	IRQ_MDF1_FLT5 = 122

	// CORDIC Co-processor
	IRQ_CORDIC = 123

	// Filter Math Accelerator
	IRQ_FMAC = 124

	// External interrupt/event controller
	IRQ_LSECSSD = 125

	IRQ_USART6 = 126

	IRQ_I2C5_ER = 127

	IRQ_I2C5_EV = 128

	IRQ_I2C6_ER = 129

	IRQ_I2C6_EV = 130

	// External interrupt/event controller
	IRQ_GPU2D_IRQ = 132

	// External interrupt/event controller
	IRQ_GPU2D_IRQSYS = 133

	// Highest interrupt number on this device.
	IRQ_max = 133
)

// Pseudo function call that is replaced by the compiler with the actual
// functions registered through interrupt.New.
//
//go:linkname callHandlers runtime/interrupt.callHandlers
func callHandlers(num int)

//export WWDG_IRQHandler
func interruptWWDG() {
	callHandlers(IRQ_WWDG)
}

//export PVD_PVM_IRQHandler
func interruptPVD_PVM() {
	callHandlers(IRQ_PVD_PVM)
}

//export RTC_IRQHandler
func interruptRTC() {
	callHandlers(IRQ_RTC)
}

//export RTC_S_IRQHandler
func interruptRTC_S() {
	callHandlers(IRQ_RTC_S)
}

//export TAMP_IRQHandler
func interruptTAMP() {
	callHandlers(IRQ_TAMP)
}

//export RAMCFG_IRQHandler
func interruptRAMCFG() {
	callHandlers(IRQ_RAMCFG)
}

//export FLASH_IRQHandler
func interruptFLASH() {
	callHandlers(IRQ_FLASH)
}

//export FLASH_S_IRQHandler
func interruptFLASH_S() {
	callHandlers(IRQ_FLASH_S)
}

//export GTZC_IRQHandler
func interruptGTZC() {
	callHandlers(IRQ_GTZC)
}

//export RCC_IRQHandler
func interruptRCC() {
	callHandlers(IRQ_RCC)
}

//export RCC_S_IRQHandler
func interruptRCC_S() {
	callHandlers(IRQ_RCC_S)
}

//export EXTI0_IRQHandler
func interruptEXTI0() {
	callHandlers(IRQ_EXTI0)
}

//export EXTI1_IRQHandler
func interruptEXTI1() {
	callHandlers(IRQ_EXTI1)
}

//export EXTI2_IRQHandler
func interruptEXTI2() {
	callHandlers(IRQ_EXTI2)
}

//export EXTI3_IRQHandler
func interruptEXTI3() {
	callHandlers(IRQ_EXTI3)
}

//export EXTI4_IRQHandler
func interruptEXTI4() {
	callHandlers(IRQ_EXTI4)
}

//export EXTI5_IRQHandler
func interruptEXTI5() {
	callHandlers(IRQ_EXTI5)
}

//export EXTI6_IRQHandler
func interruptEXTI6() {
	callHandlers(IRQ_EXTI6)
}

//export EXTI7_IRQHandler
func interruptEXTI7() {
	callHandlers(IRQ_EXTI7)
}

//export EXTI8_IRQHandler
func interruptEXTI8() {
	callHandlers(IRQ_EXTI8)
}

//export EXTI9_IRQHandler
func interruptEXTI9() {
	callHandlers(IRQ_EXTI9)
}

//export EXTI10_IRQHandler
func interruptEXTI10() {
	callHandlers(IRQ_EXTI10)
}

//export EXTI11_IRQHandler
func interruptEXTI11() {
	callHandlers(IRQ_EXTI11)
}

//export EXTI12_IRQHandler
func interruptEXTI12() {
	callHandlers(IRQ_EXTI12)
}

//export EXTI13_IRQHandler
func interruptEXTI13() {
	callHandlers(IRQ_EXTI13)
}

//export EXTI14_IRQHandler
func interruptEXTI14() {
	callHandlers(IRQ_EXTI14)
}

//export EXTI15_IRQHandler
func interruptEXTI15() {
	callHandlers(IRQ_EXTI15)
}

//export IWDG_IRQHandler
func interruptIWDG() {
	callHandlers(IRQ_IWDG)
}

//export SAES_IRQHandler
func interruptSAES() {
	callHandlers(IRQ_SAES)
}

//export GPDMA1_CH0_IRQHandler
func interruptGPDMA1_CH0() {
	callHandlers(IRQ_GPDMA1_CH0)
}

//export GPDMA1_CH1_IRQHandler
func interruptGPDMA1_CH1() {
	callHandlers(IRQ_GPDMA1_CH1)
}

//export GPDMA1_CH2_IRQHandler
func interruptGPDMA1_CH2() {
	callHandlers(IRQ_GPDMA1_CH2)
}

//export GPDMA1_CH3_IRQHandler
func interruptGPDMA1_CH3() {
	callHandlers(IRQ_GPDMA1_CH3)
}

//export GPDMA1_CH4_IRQHandler
func interruptGPDMA1_CH4() {
	callHandlers(IRQ_GPDMA1_CH4)
}

//export GPDMA1_CH5_IRQHandler
func interruptGPDMA1_CH5() {
	callHandlers(IRQ_GPDMA1_CH5)
}

//export GPDMA1_CH6_IRQHandler
func interruptGPDMA1_CH6() {
	callHandlers(IRQ_GPDMA1_CH6)
}

//export GPDMA1_CH7_IRQHandler
func interruptGPDMA1_CH7() {
	callHandlers(IRQ_GPDMA1_CH7)
}

//export ADC12_IRQHandler
func interruptADC12() {
	callHandlers(IRQ_ADC12)
}

//export DAC1_IRQHandler
func interruptDAC1() {
	callHandlers(IRQ_DAC1)
}

//export FDCAN1_IT0_IRQHandler
func interruptFDCAN1_IT0() {
	callHandlers(IRQ_FDCAN1_IT0)
}

//export FDCAN1_IT1_IRQHandler
func interruptFDCAN1_IT1() {
	callHandlers(IRQ_FDCAN1_IT1)
}

//export TIM1_BRK_IRQHandler
func interruptTIM1_BRK() {
	callHandlers(IRQ_TIM1_BRK)
}

//export TIM1_UP_IRQHandler
func interruptTIM1_UP() {
	callHandlers(IRQ_TIM1_UP)
}

//export TIM1_TRG_COM_IRQHandler
func interruptTIM1_TRG_COM() {
	callHandlers(IRQ_TIM1_TRG_COM)
}

//export TIM1_CC_IRQHandler
func interruptTIM1_CC() {
	callHandlers(IRQ_TIM1_CC)
}

//export TIM2_IRQHandler
func interruptTIM2() {
	callHandlers(IRQ_TIM2)
}

//export TIM3_IRQHandler
func interruptTIM3() {
	callHandlers(IRQ_TIM3)
}

//export TIM4_IRQHandler
func interruptTIM4() {
	callHandlers(IRQ_TIM4)
}

//export TIM5_IRQHandler
func interruptTIM5() {
	callHandlers(IRQ_TIM5)
}

//export TIM6_IRQHandler
func interruptTIM6() {
	callHandlers(IRQ_TIM6)
}

//export TIM7_IRQHandler
func interruptTIM7() {
	callHandlers(IRQ_TIM7)
}

//export TIM8_BRK_IRQHandler
func interruptTIM8_BRK() {
	callHandlers(IRQ_TIM8_BRK)
}

//export TIM8_UP_IRQHandler
func interruptTIM8_UP() {
	callHandlers(IRQ_TIM8_UP)
}

//export TIM8_TRG_COM_IRQHandler
func interruptTIM8_TRG_COM() {
	callHandlers(IRQ_TIM8_TRG_COM)
}

//export TIM8_CC_IRQHandler
func interruptTIM8_CC() {
	callHandlers(IRQ_TIM8_CC)
}

//export I2C1_EV_IRQHandler
func interruptI2C1_EV() {
	callHandlers(IRQ_I2C1_EV)
}

//export I2C1_ER_IRQHandler
func interruptI2C1_ER() {
	callHandlers(IRQ_I2C1_ER)
}

//export I2C2_EV_IRQHandler
func interruptI2C2_EV() {
	callHandlers(IRQ_I2C2_EV)
}

//export I2C2_ER_IRQHandler
func interruptI2C2_ER() {
	callHandlers(IRQ_I2C2_ER)
}

//export SPI1_IRQHandler
func interruptSPI1() {
	callHandlers(IRQ_SPI1)
}

//export SPI2_IRQHandler
func interruptSPI2() {
	callHandlers(IRQ_SPI2)
}

//export USART1_IRQHandler
func interruptUSART1() {
	callHandlers(IRQ_USART1)
}

//export USART2_IRQHandler
func interruptUSART2() {
	callHandlers(IRQ_USART2)
}

//export USART3_IRQHandler
func interruptUSART3() {
	callHandlers(IRQ_USART3)
}

//export UART4_IRQHandler
func interruptUART4() {
	callHandlers(IRQ_UART4)
}

//export UART5_IRQHandler
func interruptUART5() {
	callHandlers(IRQ_UART5)
}

//export LPUART1_IRQHandler
func interruptLPUART1() {
	callHandlers(IRQ_LPUART1)
}

//export LPTIM1_IRQHandler
func interruptLPTIM1() {
	callHandlers(IRQ_LPTIM1)
}

//export LPTIM2_IRQHandler
func interruptLPTIM2() {
	callHandlers(IRQ_LPTIM2)
}

//export TIM15_IRQHandler
func interruptTIM15() {
	callHandlers(IRQ_TIM15)
}

//export TIM16_IRQHandler
func interruptTIM16() {
	callHandlers(IRQ_TIM16)
}

//export TIM17_IRQHandler
func interruptTIM17() {
	callHandlers(IRQ_TIM17)
}

//export COMP_IRQHandler
func interruptCOMP() {
	callHandlers(IRQ_COMP)
}

//export OTG_HS_IRQHandler
func interruptOTG_HS() {
	callHandlers(IRQ_OTG_HS)
}

//export CRS_IRQHandler
func interruptCRS() {
	callHandlers(IRQ_CRS)
}

//export FMC_IRQHandler
func interruptFMC() {
	callHandlers(IRQ_FMC)
}

//export OCTOSPI1_IRQHandler
func interruptOCTOSPI1() {
	callHandlers(IRQ_OCTOSPI1)
}

//export PWR_S3WU_IRQHandler
func interruptPWR_S3WU() {
	callHandlers(IRQ_PWR_S3WU)
}

//export SDMMC1_IRQHandler
func interruptSDMMC1() {
	callHandlers(IRQ_SDMMC1)
}

//export SDMMC2_IRQHandler
func interruptSDMMC2() {
	callHandlers(IRQ_SDMMC2)
}

//export GPDMA1_CH8_IRQHandler
func interruptGPDMA1_CH8() {
	callHandlers(IRQ_GPDMA1_CH8)
}

//export GPDMA1_CH9_IRQHandler
func interruptGPDMA1_CH9() {
	callHandlers(IRQ_GPDMA1_CH9)
}

//export GPDMA1_CH10_IRQHandler
func interruptGPDMA1_CH10() {
	callHandlers(IRQ_GPDMA1_CH10)
}

//export GPDMA1_CH11_IRQHandler
func interruptGPDMA1_CH11() {
	callHandlers(IRQ_GPDMA1_CH11)
}

//export GPDMA1_CH12_IRQHandler
func interruptGPDMA1_CH12() {
	callHandlers(IRQ_GPDMA1_CH12)
}

//export GPDMA1_CH13_IRQHandler
func interruptGPDMA1_CH13() {
	callHandlers(IRQ_GPDMA1_CH13)
}

//export GPDMA1_CH14_IRQHandler
func interruptGPDMA1_CH14() {
	callHandlers(IRQ_GPDMA1_CH14)
}

//export GPDMA1_CH15_IRQHandler
func interruptGPDMA1_CH15() {
	callHandlers(IRQ_GPDMA1_CH15)
}

//export I2C3_EV_IRQHandler
func interruptI2C3_EV() {
	callHandlers(IRQ_I2C3_EV)
}

//export I2C3_ER_IRQHandler
func interruptI2C3_ER() {
	callHandlers(IRQ_I2C3_ER)
}

//export SAI1_IRQHandler
func interruptSAI1() {
	callHandlers(IRQ_SAI1)
}

//export SAI2_IRQHandler
func interruptSAI2() {
	callHandlers(IRQ_SAI2)
}

//export TSC_IRQHandler
func interruptTSC() {
	callHandlers(IRQ_TSC)
}

//export AES_IRQHandler
func interruptAES() {
	callHandlers(IRQ_AES)
}

//export RNG_IRQHandler
func interruptRNG() {
	callHandlers(IRQ_RNG)
}

//export FPU_IRQHandler
func interruptFPU() {
	callHandlers(IRQ_FPU)
}

//export HASH_IRQHandler
func interruptHASH() {
	callHandlers(IRQ_HASH)
}

//export PKA_IRQHandler
func interruptPKA() {
	callHandlers(IRQ_PKA)
}

//export LPTIM3_IRQHandler
func interruptLPTIM3() {
	callHandlers(IRQ_LPTIM3)
}

//export SPI3_IRQHandler
func interruptSPI3() {
	callHandlers(IRQ_SPI3)
}

//export I2C4_ER_IRQHandler
func interruptI2C4_ER() {
	callHandlers(IRQ_I2C4_ER)
}

//export I2C4_EV_IRQHandler
func interruptI2C4_EV() {
	callHandlers(IRQ_I2C4_EV)
}

//export MDF1_FLT0_IRQHandler
func interruptMDF1_FLT0() {
	callHandlers(IRQ_MDF1_FLT0)
}

//export MDF1_FLT1_IRQHandler
func interruptMDF1_FLT1() {
	callHandlers(IRQ_MDF1_FLT1)
}

//export MDF1_FLT2_IRQHandler
func interruptMDF1_FLT2() {
	callHandlers(IRQ_MDF1_FLT2)
}

//export MDF1_FLT3_IRQHandler
func interruptMDF1_FLT3() {
	callHandlers(IRQ_MDF1_FLT3)
}

//export UCPD1_IRQHandler
func interruptUCPD1() {
	callHandlers(IRQ_UCPD1)
}

//export ICACHE_IRQHandler
func interruptICACHE() {
	callHandlers(IRQ_ICACHE)
}

//export OTFDEC1_IRQHandler
func interruptOTFDEC1() {
	callHandlers(IRQ_OTFDEC1)
}

//export OTFDEC2_IRQHandler
func interruptOTFDEC2() {
	callHandlers(IRQ_OTFDEC2)
}

//export LPTIM4_IRQHandler
func interruptLPTIM4() {
	callHandlers(IRQ_LPTIM4)
}

//export DCACHE1_IRQHandler
func interruptDCACHE1() {
	callHandlers(IRQ_DCACHE1)
}

//export ADF1_FLT0_IRQHandler
func interruptADF1_FLT0() {
	callHandlers(IRQ_ADF1_FLT0)
}

//export ADC4_IRQHandler
func interruptADC4() {
	callHandlers(IRQ_ADC4)
}

//export LPDMA1_CH0_IRQHandler
func interruptLPDMA1_CH0() {
	callHandlers(IRQ_LPDMA1_CH0)
}

//export LPDMA1_CH1_IRQHandler
func interruptLPDMA1_CH1() {
	callHandlers(IRQ_LPDMA1_CH1)
}

//export LPDMA1_CH2_IRQHandler
func interruptLPDMA1_CH2() {
	callHandlers(IRQ_LPDMA1_CH2)
}

//export LPDMA1_CH3_IRQHandler
func interruptLPDMA1_CH3() {
	callHandlers(IRQ_LPDMA1_CH3)
}

//export DMA2D_IRQHandler
func interruptDMA2D() {
	callHandlers(IRQ_DMA2D)
}

//export DCMI_PSSI_IRQHandler
func interruptDCMI_PSSI() {
	callHandlers(IRQ_DCMI_PSSI)
}

//export OCTOSPI2_IRQHandler
func interruptOCTOSPI2() {
	callHandlers(IRQ_OCTOSPI2)
}

//export MDF1_FLT4_IRQHandler
func interruptMDF1_FLT4() {
	callHandlers(IRQ_MDF1_FLT4)
}

//export MDF1_FLT5_IRQHandler
func interruptMDF1_FLT5() {
	callHandlers(IRQ_MDF1_FLT5)
}

//export CORDIC_IRQHandler
func interruptCORDIC() {
	callHandlers(IRQ_CORDIC)
}

//export FMAC_IRQHandler
func interruptFMAC() {
	callHandlers(IRQ_FMAC)
}

//export LSECSSD_IRQHandler
func interruptLSECSSD() {
	callHandlers(IRQ_LSECSSD)
}

//export USART6_IRQHandler
func interruptUSART6() {
	callHandlers(IRQ_USART6)
}

//export I2C5_ER_IRQHandler
func interruptI2C5_ER() {
	callHandlers(IRQ_I2C5_ER)
}

//export I2C5_EV_IRQHandler
func interruptI2C5_EV() {
	callHandlers(IRQ_I2C5_EV)
}

//export I2C6_ER_IRQHandler
func interruptI2C6_ER() {
	callHandlers(IRQ_I2C6_ER)
}

//export I2C6_EV_IRQHandler
func interruptI2C6_EV() {
	callHandlers(IRQ_I2C6_EV)
}

//export GPU2D_IRQ_IRQHandler
func interruptGPU2D_IRQ() {
	callHandlers(IRQ_GPU2D_IRQ)
}

//export GPU2D_IRQSYS_IRQHandler
func interruptGPU2D_IRQSYS() {
	callHandlers(IRQ_GPU2D_IRQSYS)
}

// Peripherals.
var (
	// ADC1
	ADC1 = (*ADC_Type)(unsafe.Pointer(uintptr(0x42028000)))

	// ADC1
	SEC_ADC1 = (*ADC_Type)(unsafe.Pointer(uintptr(0x52028000)))

	// ADC1
	ADC2 = (*ADC_Type)(unsafe.Pointer(uintptr(0x42028100)))

	// ADC1
	SEC_ADC2 = (*ADC_Type)(unsafe.Pointer(uintptr(0x52028100)))

	// ADC4
	ADC4 = (*ADC_Type)(unsafe.Pointer(uintptr(0x46021000)))

	// Analog-to-Digital Converter
	ADC12_Common = (*ADC_Type)(unsafe.Pointer(uintptr(0x42028300)))

	// Analog-to-Digital Converter
	SEC_ADC12_Common = (*ADC_Type)(unsafe.Pointer(uintptr(0x52028300)))

	// ADC4
	SEC_ADC4 = (*ADC_Type)(unsafe.Pointer(uintptr(0x56021000)))

	// ADF1
	ADF1 = (*ADF_Type)(unsafe.Pointer(uintptr(0x46024000)))

	// ADF1
	SEC_ADF1 = (*ADF_Type)(unsafe.Pointer(uintptr(0x56024000)))

	// Advanced encryption standard hardware accelerator
	AES = (*AES_Type)(unsafe.Pointer(uintptr(0x420c0000)))

	// Advanced encryption standard hardware accelerator
	SEC_AES = (*AES_Type)(unsafe.Pointer(uintptr(0x520c0000)))

	// Comparator
	COMP = (*COMP_Type)(unsafe.Pointer(uintptr(0x46005400)))

	// Comparator
	SEC_COMP = (*COMP_Type)(unsafe.Pointer(uintptr(0x56005400)))

	// CORDIC Co-processor
	CORDIC = (*CORDIC_Type)(unsafe.Pointer(uintptr(0x40021000)))

	// CORDIC Co-processor
	SEC_CORDIC = (*CORDIC_Type)(unsafe.Pointer(uintptr(0x50021000)))

	// Cyclic redundancy check calculation unit
	CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x40023000)))

	// Cyclic redundancy check calculation unit
	SEC_CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x50023000)))

	// Clock recovery system
	CRS = (*CRS_Type)(unsafe.Pointer(uintptr(0x40006000)))

	// Clock recovery system
	SEC_CRS = (*CRS_Type)(unsafe.Pointer(uintptr(0x50006000)))

	// Digital-to-analog converter
	DAC1 = (*DAC_Type)(unsafe.Pointer(uintptr(0x46021800)))

	// Digital-to-analog converter
	SEC_DAC1 = (*DAC_Type)(unsafe.Pointer(uintptr(0x56021800)))

	// MCU debug component
	DBGMCU = (*DBGMCU_Type)(unsafe.Pointer(uintptr(0xe0044000)))

	// DCACHE1
	DCACHE1 = (*DCACHE_Type)(unsafe.Pointer(uintptr(0x40031400)))

	// DCACHE1
	SEC_DCACHE1 = (*DCACHE_Type)(unsafe.Pointer(uintptr(0x50031400)))

	// Digital camera interface
	DCMI = (*DCMI_Type)(unsafe.Pointer(uintptr(0x4202c000)))

	// Digital camera interface
	SEC_DCMI = (*DCMI_Type)(unsafe.Pointer(uintptr(0x5202c000)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	DLYBOS1 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x420cf000)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	SEC_DLYBOS1 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x520cf000)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	DLYBOS2 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x420cf400)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	SEC_DLYBOS2 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x520cf400)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	DLYBSD1 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x420c8400)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	SEC_DLYBSD1 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x520c8400)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	DLYBSD2 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x420c8800)))

	// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
	SEC_DLYBSD2 = (*DLYB_Type)(unsafe.Pointer(uintptr(0x520c8800)))

	// DMA2D controller
	DMA2D = (*DMA2D_Type)(unsafe.Pointer(uintptr(0x4002b000)))

	// DMA2D controller
	SEC_DMA2D = (*DMA2D_Type)(unsafe.Pointer(uintptr(0x5002b000)))

	// External interrupt/event controller
	EXTI = (*EXTI_Type)(unsafe.Pointer(uintptr(0x46022000)))

	// External interrupt/event controller
	SEC_EXTI = (*EXTI_Type)(unsafe.Pointer(uintptr(0x56022000)))

	// FDCAN1_RAM
	FDCAN1_RAM = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000ac00)))

	// FDCAN1_RAM
	SEC_FDCAN1_RAM = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x5000ac00)))

	// FDCAN1_RAM
	FDCAN1 = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a400)))

	// FDCAN1_RAM
	SEC_FDCAN1 = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x5000a400)))

	// Flash
	FLASH = (*Flash_Type)(unsafe.Pointer(uintptr(0x40022000)))

	// Flash
	SEC_FLASH = (*Flash_Type)(unsafe.Pointer(uintptr(0x50022000)))

	// Filter Math Accelerator
	FMAC = (*FMAC_Type)(unsafe.Pointer(uintptr(0x40021400)))

	// Filter Math Accelerator
	SEC_FMAC = (*FMAC_Type)(unsafe.Pointer(uintptr(0x50021400)))

	// FMC
	FMC = (*FMC_Type)(unsafe.Pointer(uintptr(0x420d0400)))

	// FMC
	SEC_FMC = (*FMC_Type)(unsafe.Pointer(uintptr(0x520d0400)))

	// GPDMA1
	GPDMA1 = (*GPDMA_Type)(unsafe.Pointer(uintptr(0x40020000)))

	// GPDMA1
	SEC_GPDMA1 = (*GPDMA_Type)(unsafe.Pointer(uintptr(0x50020000)))

	// General-purpose I/Os
	GPIOA = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020000)))

	// General-purpose I/Os
	SEC_GPIOA = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020000)))

	// General-purpose I/Os
	GPIOB = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020400)))

	// General-purpose I/Os
	SEC_GPIOB = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020400)))

	// General-purpose I/Os
	GPIOC = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020800)))

	// General-purpose I/Os
	SEC_GPIOC = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020800)))

	// General-purpose I/Os
	GPIOD = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020c00)))

	// General-purpose I/Os
	SEC_GPIOD = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020c00)))

	// General-purpose I/Os
	GPIOE = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021000)))

	// General-purpose I/Os
	SEC_GPIOE = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021000)))

	// General-purpose I/Os
	GPIOF = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021400)))

	// General-purpose I/Os
	SEC_GPIOF = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021400)))

	// General-purpose I/Os
	GPIOG = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021800)))

	// General-purpose I/Os
	SEC_GPIOG = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021800)))

	// General-purpose I/Os
	GPIOH = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021c00)))

	// General-purpose I/Os
	SEC_GPIOH = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021c00)))

	// General-purpose I/Os
	GPIOI = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42022000)))

	// General-purpose I/Os
	SEC_GPIOI = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52022000)))

	// General-purpose I/Os
	GPIOJ = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42022400)))

	// General-purpose I/Os
	SEC_GPIOJ = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52022400)))

	// GTZC1_TZIC
	GTZC1_TZIC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40032800)))

	// GTZC1_MPCBB1
	GTZC1_MPCBB1 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40032c00)))

	// GTZC1_MPCBB1
	SEC_GTZC1_MPCBB1 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50032c00)))

	// GTZC1_MPCBB2
	GTZC1_MPCBB2 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40033000)))

	// GTZC1_MPCBB2
	SEC_GTZC1_MPCBB2 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50033000)))

	// GTZC1_MPCBB3
	GTZC1_MPCBB3 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40033400)))

	// GTZC1_MPCBB3
	SEC_GTZC1_MPCBB3 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50033400)))

	// GTZC1_MPCBB5
	GTZC1_MPCBB5 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40033800)))

	// GTZC1_MPCBB5
	SEC_GTZC1_MPCBB5 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50033800)))

	// GTZC1_TZIC
	SEC_GTZC1_TZIC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50032800)))

	// GTZC1_TZSC
	GTZC1_TZSC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40032400)))

	// GTZC1_TZSC
	SEC_GTZC1_TZSC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50032400)))

	// GTZC2_MPCBB4
	GTZC2_MPCBB4 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x46023800)))

	// GTZC2_MPCBB4
	SEC_GTZC2_MPCBB4 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x56023800)))

	// GTZC2_TZIC
	GTZC2_TZIC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x46023400)))

	// GTZC2_TZIC
	SEC_GTZC2_TZIC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x56023400)))

	// GTZC2_TZSC
	GTZC2_TZSC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x46023000)))

	// GTZC2_TZSC
	SEC_GTZC2_TZSC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x56023000)))

	// Hash processor
	HASH = (*HASH_Type)(unsafe.Pointer(uintptr(0x420c0400)))

	// Hash processor
	SEC_HASH = (*HASH_Type)(unsafe.Pointer(uintptr(0x520c0400)))

	// Inter-integrated circuit
	I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005400)))

	// Inter-integrated circuit
	SEC_I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50005400)))

	// Inter-integrated circuit
	I2C2 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005800)))

	// Inter-integrated circuit
	SEC_I2C2 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50005800)))

	// Inter-integrated circuit
	I2C3 = (*I2C_Type)(unsafe.Pointer(uintptr(0x46002800)))

	// Inter-integrated circuit
	SEC_I2C3 = (*I2C_Type)(unsafe.Pointer(uintptr(0x56002800)))

	// Inter-integrated circuit
	I2C4 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40008400)))

	// Inter-integrated circuit
	SEC_I2C4 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50008400)))

	// Inter-integrated circuit
	I2C5 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40009800)))

	// Inter-integrated circuit
	SEC_I2C5 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50009800)))

	// Inter-integrated circuit
	I2C6 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40009c00)))

	// Inter-integrated circuit
	SEC_I2C6 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50009c00)))

	// ICache
	ICACHE = (*ICache_Type)(unsafe.Pointer(uintptr(0x40030400)))

	// ICache
	SEC_ICache = (*ICache_Type)(unsafe.Pointer(uintptr(0x50030400)))

	// Independent watchdog
	IWDG = (*IWDG_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Independent watchdog
	SEC_IWDG = (*IWDG_Type)(unsafe.Pointer(uintptr(0x50003000)))

	// LPDMA1
	LPDMA1 = (*LPDMA_Type)(unsafe.Pointer(uintptr(0x46025000)))

	// LPDMA1
	SEC_LPDMA1 = (*LPDMA_Type)(unsafe.Pointer(uintptr(0x56025000)))

	// LPGPIO1
	LPGPIO1 = (*LPGPIO_Type)(unsafe.Pointer(uintptr(0x46020000)))

	// LPGPIO1
	SEC_LPGPIO1 = (*LPGPIO_Type)(unsafe.Pointer(uintptr(0x56020000)))

	// Low power timer
	LPTIM1 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x46004400)))

	// Low power timer
	SEC_LPTIM1 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x56004400)))

	// Low power timer
	LPTIM2 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x40009400)))

	// Low power timer
	SEC_LPTIM2 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x50009400)))

	// Low power timer
	LPTIM3 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x46004800)))

	// Low power timer
	SEC_LPTIM3 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x56004800)))

	// Low power timer
	LPTIM4 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x46004c00)))

	// Low power timer
	SEC_LPTIM4 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x56004c00)))

	// Universal synchronous asynchronous receiver transmitter
	LPUART1 = (*LPUART_Type)(unsafe.Pointer(uintptr(0x46002400)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_LPUART1 = (*LPUART_Type)(unsafe.Pointer(uintptr(0x56002400)))

	// Multi-function digital filter
	MDF1 = (*MDF_Type)(unsafe.Pointer(uintptr(0x40025000)))

	// Multi-function digital filter
	SEC_MDF1 = (*MDF_Type)(unsafe.Pointer(uintptr(0x50025000)))

	// OctoSPI
	OCTOSPI1 = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x420d1400)))

	// OctoSPI
	SEC_OCTOSPI1 = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x520d1400)))

	// OctoSPI
	OCTOSPI2 = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x420d2400)))

	// OctoSPI
	SEC_OCTOSPI2 = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x520d2400)))

	// OCTOSPI I/O manager
	OCTOSPIM = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x420c4000)))

	// OCTOSPI I/O manager
	SEC_OCTOSPIM = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x520c4000)))

	// Operational amplifiers
	OPAMP = (*OPAMP_Type)(unsafe.Pointer(uintptr(0x46005000)))

	// Operational amplifiers
	SEC_OPAMP = (*OPAMP_Type)(unsafe.Pointer(uintptr(0x56005000)))

	// On-The-Fly Decryption engine
	OTFDEC1 = (*OTFDEC_Type)(unsafe.Pointer(uintptr(0x420c5000)))

	// On-The-Fly Decryption engine
	SEC_OTFDEC1 = (*OTFDEC_Type)(unsafe.Pointer(uintptr(0x520c5000)))

	// On-The-Fly Decryption engine
	OTFDEC2 = (*OTFDEC_Type)(unsafe.Pointer(uintptr(0x420c5400)))

	// On-The-Fly Decryption engine
	SEC_OTFDEC2 = (*OTFDEC_Type)(unsafe.Pointer(uintptr(0x520c5400)))

	// OTG_HS
	OTG_HS = (*OTG_HS_Type)(unsafe.Pointer(uintptr(0x42040000)))

	// OTG_HS
	SEC_OTG_HS = (*OTG_HS_Type)(unsafe.Pointer(uintptr(0x52040000)))

	// Private key accelerator
	PKA = (*PKA_Type)(unsafe.Pointer(uintptr(0x420c2000)))

	// Private key accelerator
	SEC_PKA = (*PKA_Type)(unsafe.Pointer(uintptr(0x520c2000)))

	// PSSI
	PSSI = (*PSSI_Type)(unsafe.Pointer(uintptr(0x4202c400)))

	// PSSI
	SEC_PSSI = (*PSSI_Type)(unsafe.Pointer(uintptr(0x5202c400)))

	// Power control
	PWR = (*PWR_Type)(unsafe.Pointer(uintptr(0x46020800)))

	// Power control
	SEC_PWR = (*PWR_Type)(unsafe.Pointer(uintptr(0x56020800)))

	// RAMCFG
	RAMCFG = (*RAMCFG_Type)(unsafe.Pointer(uintptr(0x40026000)))

	// RAMCFG
	SEC_RAMCFG = (*RAMCFG_Type)(unsafe.Pointer(uintptr(0x50026000)))

	// Reset and clock control
	RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x46020c00)))

	// Reset and clock control
	SEC_RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x56020c00)))

	// Random number generator
	RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x420c0800)))

	// Random number generator
	SEC_RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x520c0800)))

	// Real-time clock
	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x46007800)))

	// Real-time clock
	SEC_RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x56007800)))

	// Secure AES coprocessor
	SAES = (*SAES_Type)(unsafe.Pointer(uintptr(0x420c0c00)))

	// Secure AES coprocessor
	SEC_SAES = (*SAES_Type)(unsafe.Pointer(uintptr(0x520c0c00)))

	// Serial audio interface
	SAI1 = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015400)))

	// Serial audio interface
	SEC_SAI1 = (*SAI_Type)(unsafe.Pointer(uintptr(0x50015400)))

	// Serial audio interface
	SAI2 = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015800)))

	// Serial audio interface
	SEC_SAI2 = (*SAI_Type)(unsafe.Pointer(uintptr(0x50015800)))

	// Secure digital input/output MultiMediaCard interface
	SDMMC1 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x420c8000)))

	// Secure digital input/output MultiMediaCard interface
	SEC_SDMMC1 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x520c8000)))

	// Secure digital input/output MultiMediaCard interface
	SDMMC2 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x420c8c00)))

	// Secure digital input/output MultiMediaCard interface
	SEC_SDMMC2 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x520c8c00)))

	// Serial peripheral interface
	SPI1 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013000)))

	// Serial peripheral interface
	SEC_SPI1 = (*SPI_Type)(unsafe.Pointer(uintptr(0x50013000)))

	// Serial peripheral interface
	SPI2 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// Serial peripheral interface
	SEC_SPI2 = (*SPI_Type)(unsafe.Pointer(uintptr(0x50003800)))

	// Serial peripheral interface
	SPI3 = (*SPI_Type)(unsafe.Pointer(uintptr(0x46002000)))

	// Serial peripheral interface
	SEC_SPI3 = (*SPI_Type)(unsafe.Pointer(uintptr(0x56002000)))

	// System configuration controller
	SYSCFG = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x46000400)))

	// System configuration controller
	SEC_SYSCFG = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x56000400)))

	// Tamper and backup registers
	TAMP = (*TAMP_Type)(unsafe.Pointer(uintptr(0x46007c00)))

	// Tamper and backup registers
	SEC_TAMP = (*TAMP_Type)(unsafe.Pointer(uintptr(0x56007c00)))

	// Advanced-timers
	TIM1 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40012c00)))

	// Advanced-timers
	SEC_TIM1 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50012c00)))

	// General-purpose-timers
	TIM2 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// General-purpose-timers
	SEC_TIM2 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000000)))

	// General-purpose-timers
	TIM3 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000400)))

	// General-purpose-timers
	SEC_TIM3 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000400)))

	// General-purpose-timers
	TIM4 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000800)))

	// General-purpose-timers
	SEC_TIM4 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000800)))

	// General-purpose-timers
	TIM5 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000c00)))

	// General-purpose-timers
	SEC_TIM5 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000c00)))

	// General purpose timers
	TIM15 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014000)))

	// General-purpose-timers
	TIM6 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001000)))

	// General-purpose-timers
	SEC_TIM6 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50001000)))

	// General-purpose-timers
	TIM7 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001400)))

	// General-purpose-timers
	SEC_TIM7 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50001400)))

	// Advanced-timers
	TIM8 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40013400)))

	// Advanced-timers
	SEC_TIM8 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50013400)))

	// General purpose timers
	SEC_TIM15 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50014000)))

	// General purpose timers
	TIM16 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014400)))

	// General purpose timers
	SEC_TIM16 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50014400)))

	// General purpose timers
	TIM17 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014800)))

	// General purpose timers
	SEC_TIM17 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50014800)))

	// Touch sensing controller
	TSC = (*TSC_Type)(unsafe.Pointer(uintptr(0x40024000)))

	// Touch sensing controller
	SEC_TSC = (*TSC_Type)(unsafe.Pointer(uintptr(0x50024000)))

	// USB Power Delivery interface
	UCPD1 = (*UCPD_Type)(unsafe.Pointer(uintptr(0x4000dc00)))

	// USB Power Delivery interface
	SEC_UCPD1 = (*UCPD_Type)(unsafe.Pointer(uintptr(0x5000dc00)))

	// Universal synchronous asynchronous receiver transmitter
	USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x40013800)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x50013800)))

	// Universal synchronous asynchronous receiver transmitter
	USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004400)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x50004400)))

	// Universal synchronous asynchronous receiver transmitter
	USART3 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004800)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_USART3 = (*USART_Type)(unsafe.Pointer(uintptr(0x50004800)))

	// Universal synchronous asynchronous receiver transmitter
	UART4 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004c00)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_UART4 = (*USART_Type)(unsafe.Pointer(uintptr(0x50004c00)))

	// Universal synchronous asynchronous receiver transmitter
	UART5 = (*USART_Type)(unsafe.Pointer(uintptr(0x40005000)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_UART5 = (*USART_Type)(unsafe.Pointer(uintptr(0x50005000)))

	// Universal synchronous asynchronous receiver transmitter
	USART6 = (*USART_Type)(unsafe.Pointer(uintptr(0x40006400)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_USART6 = (*USART_Type)(unsafe.Pointer(uintptr(0x50006400)))

	// Voltage reference buffer
	VREFBUF = (*VREF_Type)(unsafe.Pointer(uintptr(0x46007400)))

	// Voltage reference buffer
	SEC_VREFBUF = (*VREF_Type)(unsafe.Pointer(uintptr(0x56007400)))

	// System window watchdog
	WWDG = (*WWDG_Type)(unsafe.Pointer(uintptr(0x40002c00)))

	// System window watchdog
	SEC_WWDG = (*WWDG_Type)(unsafe.Pointer(uintptr(0x50002c00)))

	// Debug Control Block
	DCB = (*DCB_Type)(unsafe.Pointer(uintptr(0xe000ee08)))
)

// ADC1
type ADC_Type struct {
	ISR      volatile.Register32 // 0x0
	IER      volatile.Register32 // 0x4
	CR       volatile.Register32 // 0x8
	CFGR1    volatile.Register32 // 0xC
	CFGR2    volatile.Register32 // 0x10
	SMPR1    volatile.Register32 // 0x14
	SMPR2    volatile.Register32 // 0x18
	PCSEL    volatile.Register32 // 0x1C
	_        [16]byte
	SQR1     volatile.Register32 // 0x30
	SQR2     volatile.Register32 // 0x34
	SQR3     volatile.Register32 // 0x38
	SQR4     volatile.Register32 // 0x3C
	DR       volatile.Register32 // 0x40
	_        [8]byte
	JSQR     volatile.Register32 // 0x4C
	_        [16]byte
	OFR1     volatile.Register32 // 0x60
	OFR2     volatile.Register32 // 0x64
	OFR3     volatile.Register32 // 0x68
	OFR4     volatile.Register32 // 0x6C
	GCOMP    volatile.Register32 // 0x70
	_        [12]byte
	JDR1     volatile.Register32 // 0x80
	JDR2     volatile.Register32 // 0x84
	JDR3     volatile.Register32 // 0x88
	JDR4     volatile.Register32 // 0x8C
	_        [16]byte
	AWD2CR   volatile.Register32 // 0xA0
	AWD3CR   volatile.Register32 // 0xA4
	LTR1     volatile.Register32 // 0xA8
	HTR1     volatile.Register32 // 0xAC
	LTR2     volatile.Register32 // 0xB0
	HTR2     volatile.Register32 // 0xB4
	LTR3     volatile.Register32 // 0xB8
	HTR3     volatile.Register32 // 0xBC
	DIFSEL   volatile.Register32 // 0xC0
	CALFACT  volatile.Register32 // 0xC4
	CALFACT2 volatile.Register32 // 0xC8
}

// ADC.ISR: ADC interrupt and status register
func (o *ADC_Type) SetISR_LDORDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetISR_LDORDY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetISR_AWD1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetISR_AWD1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetISR_AWD2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetISR_AWD2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetISR_AWD3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetISR_AWD3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetISR_JEOS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetISR_JEOS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetISR_JEOC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetISR_JEOC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetISR_OVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetISR_OVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetISR_EOS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetISR_EOS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetISR_EOC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetISR_EOC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetISR_EOSMP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetISR_EOSMP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetISR_ADRDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetISR_ADRDY() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// ADC.IER: ADC interrupt enable register
func (o *ADC_Type) SetIER_AWD1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetIER_AWD1IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetIER_AWD2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetIER_AWD2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetIER_AWD3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetIER_AWD3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetIER_JEOSIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetIER_JEOSIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetIER_JEOCIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetIER_JEOCIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetIER_OVRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIER_OVRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIER_EOSIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIER_EOSIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIER_EOCIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetIER_EOCIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetIER_EOSMPIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIER_EOSMPIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIER_ADRDYIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIER_ADRDYIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}

// ADC.CR: ADC control register
func (o *ADC_Type) SetCR_ADCAL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetCR_ADCAL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetCR_DEEPPWD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetCR_DEEPPWD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetCR_ADVREGEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetCR_ADVREGEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetCR_CALINDEX(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf000000)|value<<24)
}
func (o *ADC_Type) GetCR_CALINDEX() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf000000) >> 24
}
func (o *ADC_Type) SetCR_ADCALLIN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetCR_ADCALLIN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetCR_JADSTP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCR_JADSTP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCR_ADSTP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCR_ADSTP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCR_JADSTART(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetCR_JADSTART() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetCR_ADSTART(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCR_ADSTART() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCR_ADDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCR_ADDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCR_ADEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCR_ADEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// ADC.CFGR1: ADC configuration register
func (o *ADC_Type) SetCFGR1_AWD1CH(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetCFGR1_AWD1CH() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x7c000000) >> 26
}
func (o *ADC_Type) SetCFGR1_JAUTO(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetCFGR1_JAUTO() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetCFGR1_JAWD1EN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetCFGR1_JAWD1EN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetCFGR1_AWD1EN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetCFGR1_AWD1EN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetCFGR1_AWD1SGL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Type) GetCFGR1_AWD1SGL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x400000) >> 22
}
func (o *ADC_Type) SetCFGR1_JDISCEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Type) GetCFGR1_JDISCEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100000) >> 20
}
func (o *ADC_Type) SetCFGR1_DISCNUM(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xe0000)|value<<17)
}
func (o *ADC_Type) GetCFGR1_DISCNUM() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xe0000) >> 17
}
func (o *ADC_Type) SetCFGR1_DISCEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetCFGR1_DISCEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetCFGR1_AUTDLY(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCFGR1_AUTDLY() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCFGR1_CONT(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCFGR1_CONT() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCFGR1_OVRMOD(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCFGR1_OVRMOD() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCFGR1_EXTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xc00)|value<<10)
}
func (o *ADC_Type) GetCFGR1_EXTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xc00) >> 10
}
func (o *ADC_Type) SetCFGR1_EXTSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3e0)|value<<5)
}
func (o *ADC_Type) GetCFGR1_EXTSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x3e0) >> 5
}
func (o *ADC_Type) SetCFGR1_RES(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xc)|value<<2)
}
func (o *ADC_Type) GetCFGR1_RES() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xc) >> 2
}
func (o *ADC_Type) SetCFGR1_DMNGT(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3)|value)
}
func (o *ADC_Type) GetCFGR1_DMNGT() uint32 {
	return volatile.LoadUint32(&o.CFGR1.Reg) & 0x3
}

// ADC.CFGR2: ADC configuration register 2
func (o *ADC_Type) SetCFGR2_LSHIFT(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0xf0000000)|value<<28)
}
func (o *ADC_Type) GetCFGR2_LSHIFT() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0xf0000000) >> 28
}
func (o *ADC_Type) SetCFGR2_LFTRIG(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x8000000)|value<<27)
}
func (o *ADC_Type) GetCFGR2_LFTRIG() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x8000000) >> 27
}
func (o *ADC_Type) SetCFGR2_OSR(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x3ff0000)|value<<16)
}
func (o *ADC_Type) GetCFGR2_OSR() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x3ff0000) >> 16
}
func (o *ADC_Type) SetCFGR2_SMPTRIG(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetCFGR2_SMPTRIG() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetCFGR2_SWTRIG(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCFGR2_SWTRIG() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCFGR2_BULB(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCFGR2_BULB() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCFGR2_ROVSM(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCFGR2_ROVSM() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCFGR2_TROVS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCFGR2_TROVS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCFGR2_OVSS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1e0)|value<<5)
}
func (o *ADC_Type) GetCFGR2_OVSS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x1e0) >> 5
}
func (o *ADC_Type) SetCFGR2_JOVSE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCFGR2_JOVSE() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCFGR2_ROVSE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCFGR2_ROVSE() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}

// ADC.SMPR1: ADC sample time register 1
func (o *ADC_Type) SetSMPR1_SMP0(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x38)|value<<3)
}
func (o *ADC_Type) GetSMPR1_SMP0() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x38) >> 3
}
func (o *ADC_Type) SetSMPR1_SMP1(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x1c0)|value<<6)
}
func (o *ADC_Type) GetSMPR1_SMP1() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x1c0) >> 6
}
func (o *ADC_Type) SetSMPR1_SMP2(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0xe00)|value<<9)
}
func (o *ADC_Type) GetSMPR1_SMP2() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0xe00) >> 9
}
func (o *ADC_Type) SetSMPR1_SMP3(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x7000)|value<<12)
}
func (o *ADC_Type) GetSMPR1_SMP3() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x7000) >> 12
}
func (o *ADC_Type) SetSMPR1_SMP4(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x38000)|value<<15)
}
func (o *ADC_Type) GetSMPR1_SMP4() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x38000) >> 15
}
func (o *ADC_Type) SetSMPR1_SMP5(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x1c0000)|value<<18)
}
func (o *ADC_Type) GetSMPR1_SMP5() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x1c0000) >> 18
}
func (o *ADC_Type) SetSMPR1_SMP6(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0xe00000)|value<<21)
}
func (o *ADC_Type) GetSMPR1_SMP6() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0xe00000) >> 21
}
func (o *ADC_Type) SetSMPR1_SMP7(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x7000000)|value<<24)
}
func (o *ADC_Type) GetSMPR1_SMP7() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x7000000) >> 24
}
func (o *ADC_Type) SetSMPR1_SMP8(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x38000000)|value<<27)
}
func (o *ADC_Type) GetSMPR1_SMP8() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x38000000) >> 27
}
func (o *ADC_Type) SetSMPR1_SMP9(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSMPR1_SMP9() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0xc0000000) >> 30
}

// ADC.SMPR2: ADC sample time register 2
func (o *ADC_Type) SetSMPR2_SMP10(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x38)|value<<3)
}
func (o *ADC_Type) GetSMPR2_SMP10() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x38) >> 3
}
func (o *ADC_Type) SetSMPR2_SMP11(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x1c0)|value<<6)
}
func (o *ADC_Type) GetSMPR2_SMP11() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x1c0) >> 6
}
func (o *ADC_Type) SetSMPR2_SMP12(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0xe00)|value<<9)
}
func (o *ADC_Type) GetSMPR2_SMP12() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0xe00) >> 9
}
func (o *ADC_Type) SetSMPR2_SMP13(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x7000)|value<<12)
}
func (o *ADC_Type) GetSMPR2_SMP13() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x7000) >> 12
}
func (o *ADC_Type) SetSMPR2_SMP14(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x38000)|value<<15)
}
func (o *ADC_Type) GetSMPR2_SMP14() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x38000) >> 15
}
func (o *ADC_Type) SetSMPR2_SMP15(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x1c0000)|value<<18)
}
func (o *ADC_Type) GetSMPR2_SMP15() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x1c0000) >> 18
}
func (o *ADC_Type) SetSMPR2_SMP16(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0xe00000)|value<<21)
}
func (o *ADC_Type) GetSMPR2_SMP16() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0xe00000) >> 21
}
func (o *ADC_Type) SetSMPR2_SMP17(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x7000000)|value<<24)
}
func (o *ADC_Type) GetSMPR2_SMP17() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x7000000) >> 24
}
func (o *ADC_Type) SetSMPR2_SMP18(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x38000000)|value<<27)
}
func (o *ADC_Type) GetSMPR2_SMP18() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x38000000) >> 27
}
func (o *ADC_Type) SetSMPR2_SMP19(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSMPR2_SMP19() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0xc0000000) >> 30
}

// ADC.PCSEL: ADC channel preselection register
func (o *ADC_Type) SetPCSEL_PCSEL0(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetPCSEL_PCSEL0() uint32 {
	return volatile.LoadUint32(&o.PCSEL.Reg) & 0x1
}
func (o *ADC_Type) SetPCSEL_PCSEL19(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetPCSEL_PCSEL19() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x80000) >> 19
}
func (o *ADC_Type) SetPCSEL_PCSEL18(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetPCSEL_PCSEL18() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetPCSEL_PCSEL17(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetPCSEL_PCSEL17() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetPCSEL_PCSEL16(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetPCSEL_PCSEL16() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetPCSEL_PCSEL15(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetPCSEL_PCSEL15() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetPCSEL_PCSEL14(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetPCSEL_PCSEL14() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetPCSEL_PCSEL13(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetPCSEL_PCSEL13() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetPCSEL_PCSEL12(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetPCSEL_PCSEL12() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetPCSEL_PCSEL11(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetPCSEL_PCSEL11() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetPCSEL_PCSEL10(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetPCSEL_PCSEL10() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetPCSEL_PCSEL9(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetPCSEL_PCSEL9() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetPCSEL_PCSEL8(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetPCSEL_PCSEL8() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetPCSEL_PCSEL7(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetPCSEL_PCSEL7() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetPCSEL_PCSEL6(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetPCSEL_PCSEL6() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetPCSEL_PCSEL5(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetPCSEL_PCSEL5() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetPCSEL_PCSEL4(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetPCSEL_PCSEL4() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetPCSEL_PCSEL3(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetPCSEL_PCSEL3() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetPCSEL_PCSEL2(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetPCSEL_PCSEL2() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetPCSEL_PCSEL1(value uint32) {
	volatile.StoreUint32(&o.PCSEL.Reg, volatile.LoadUint32(&o.PCSEL.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetPCSEL_PCSEL1() uint32 {
	return (volatile.LoadUint32(&o.PCSEL.Reg) & 0x2) >> 1
}

// ADC.SQR1: ADC regular sequence register 1
func (o *ADC_Type) SetSQR1_SQ1(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR1_SQ1() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0x1f000) >> 12
}
func (o *ADC_Type) SetSQR1_SQ2(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0x7c0000)|value<<18)
}
func (o *ADC_Type) GetSQR1_SQ2() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0x7c0000) >> 18
}
func (o *ADC_Type) SetSQR1_SQ3(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0x1f000000)|value<<24)
}
func (o *ADC_Type) GetSQR1_SQ3() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0x1f000000) >> 24
}
func (o *ADC_Type) SetSQR1_SQ4(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSQR1_SQ4() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0xc0000000) >> 30
}
func (o *ADC_Type) SetSQR1_L(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0xf)|value)
}
func (o *ADC_Type) GetSQR1_L() uint32 {
	return volatile.LoadUint32(&o.SQR1.Reg) & 0xf
}

// ADC.SQR2: ADC regular sequence register 2
func (o *ADC_Type) SetSQR2_SQ5(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x7c0)|value<<6)
}
func (o *ADC_Type) GetSQR2_SQ5() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x7c0) >> 6
}
func (o *ADC_Type) SetSQR2_SQ6(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR2_SQ6() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x1f000) >> 12
}
func (o *ADC_Type) SetSQR2_SQ7(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x7c0000)|value<<18)
}
func (o *ADC_Type) GetSQR2_SQ7() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x7c0000) >> 18
}
func (o *ADC_Type) SetSQR2_SQ8(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x1f000000)|value<<24)
}
func (o *ADC_Type) GetSQR2_SQ8() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x1f000000) >> 24
}
func (o *ADC_Type) SetSQR2_SQ9(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSQR2_SQ9() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0xc0000000) >> 30
}

// ADC.SQR3: ADC regular sequence register 3
func (o *ADC_Type) SetSQR3_SQ10(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x7c0)|value<<6)
}
func (o *ADC_Type) GetSQR3_SQ10() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x7c0) >> 6
}
func (o *ADC_Type) SetSQR3_SQ11(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR3_SQ11() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x1f000) >> 12
}
func (o *ADC_Type) SetSQR3_SQ12(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x7c0000)|value<<18)
}
func (o *ADC_Type) GetSQR3_SQ12() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x7c0000) >> 18
}
func (o *ADC_Type) SetSQR3_SQ13(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x1f000000)|value<<24)
}
func (o *ADC_Type) GetSQR3_SQ13() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x1f000000) >> 24
}
func (o *ADC_Type) SetSQR3_SQ14(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSQR3_SQ14() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0xc0000000) >> 30
}

// ADC.SQR4: ADC regular sequence register 4
func (o *ADC_Type) SetSQR4_SQ15(value uint32) {
	volatile.StoreUint32(&o.SQR4.Reg, volatile.LoadUint32(&o.SQR4.Reg)&^(0x7c0)|value<<6)
}
func (o *ADC_Type) GetSQR4_SQ15() uint32 {
	return (volatile.LoadUint32(&o.SQR4.Reg) & 0x7c0) >> 6
}
func (o *ADC_Type) SetSQR4_SQ16(value uint32) {
	volatile.StoreUint32(&o.SQR4.Reg, volatile.LoadUint32(&o.SQR4.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR4_SQ16() uint32 {
	return (volatile.LoadUint32(&o.SQR4.Reg) & 0x1f000) >> 12
}

// ADC.DR: ADC regular Data Register
func (o *ADC_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *ADC_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// ADC.JSQR: ADC injected sequence register
func (o *ADC_Type) SetJSQR_JSQ1(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0xf8000)|value<<15)
}
func (o *ADC_Type) GetJSQR_JSQ1() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0xf8000) >> 15
}
func (o *ADC_Type) SetJSQR_JSQ2(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x3e00000)|value<<21)
}
func (o *ADC_Type) GetJSQR_JSQ2() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x3e00000) >> 21
}
func (o *ADC_Type) SetJSQR_JSQ3(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0xf8000000)|value<<27)
}
func (o *ADC_Type) GetJSQR_JSQ3() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0xf8000000) >> 27
}
func (o *ADC_Type) SetJSQR_JSQ4(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x0)|value<<33)
}
func (o *ADC_Type) GetJSQR_JSQ4() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x0) >> 33
}
func (o *ADC_Type) SetJSQR_JEXTEN(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x180)|value<<7)
}
func (o *ADC_Type) GetJSQR_JEXTEN() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x180) >> 7
}
func (o *ADC_Type) SetJSQR_JEXTSEL(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x7c)|value<<2)
}
func (o *ADC_Type) GetJSQR_JEXTSEL() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x7c) >> 2
}
func (o *ADC_Type) SetJSQR_JL(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x3)|value)
}
func (o *ADC_Type) GetJSQR_JL() uint32 {
	return volatile.LoadUint32(&o.JSQR.Reg) & 0x3
}

// ADC.OFR1: ADC offset register
func (o *ADC_Type) SetOFR1_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0xf8000000)|value<<27)
}
func (o *ADC_Type) GetOFR1_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR1.Reg) & 0xf8000000) >> 27
}
func (o *ADC_Type) SetOFR1_SSAT(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetOFR1_SSAT() uint32 {
	return (volatile.LoadUint32(&o.OFR1.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetOFR1_USAT(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetOFR1_USAT() uint32 {
	return (volatile.LoadUint32(&o.OFR1.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetOFR1_POSOFF(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetOFR1_POSOFF() uint32 {
	return (volatile.LoadUint32(&o.OFR1.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetOFR1_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetOFR1_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR1.Reg) & 0xffffff
}

// ADC.OFR2: ADC offset register
func (o *ADC_Type) SetOFR2_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0xf8000000)|value<<27)
}
func (o *ADC_Type) GetOFR2_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR2.Reg) & 0xf8000000) >> 27
}
func (o *ADC_Type) SetOFR2_SSAT(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetOFR2_SSAT() uint32 {
	return (volatile.LoadUint32(&o.OFR2.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetOFR2_USAT(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetOFR2_USAT() uint32 {
	return (volatile.LoadUint32(&o.OFR2.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetOFR2_POSOFF(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetOFR2_POSOFF() uint32 {
	return (volatile.LoadUint32(&o.OFR2.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetOFR2_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetOFR2_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR2.Reg) & 0xffffff
}

// ADC.OFR3: ADC offset register
func (o *ADC_Type) SetOFR3_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0xf8000000)|value<<27)
}
func (o *ADC_Type) GetOFR3_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR3.Reg) & 0xf8000000) >> 27
}
func (o *ADC_Type) SetOFR3_SSAT(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetOFR3_SSAT() uint32 {
	return (volatile.LoadUint32(&o.OFR3.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetOFR3_USAT(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetOFR3_USAT() uint32 {
	return (volatile.LoadUint32(&o.OFR3.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetOFR3_POSOFF(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetOFR3_POSOFF() uint32 {
	return (volatile.LoadUint32(&o.OFR3.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetOFR3_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetOFR3_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR3.Reg) & 0xffffff
}

// ADC.OFR4: ADC offset register
func (o *ADC_Type) SetOFR4_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0xf8000000)|value<<27)
}
func (o *ADC_Type) GetOFR4_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR4.Reg) & 0xf8000000) >> 27
}
func (o *ADC_Type) SetOFR4_SSAT(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Type) GetOFR4_SSAT() uint32 {
	return (volatile.LoadUint32(&o.OFR4.Reg) & 0x4000000) >> 26
}
func (o *ADC_Type) SetOFR4_USAT(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetOFR4_USAT() uint32 {
	return (volatile.LoadUint32(&o.OFR4.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetOFR4_POSOFF(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetOFR4_POSOFF() uint32 {
	return (volatile.LoadUint32(&o.OFR4.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetOFR4_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0xffffff)|value)
}
func (o *ADC_Type) GetOFR4_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR4.Reg) & 0xffffff
}

// ADC.GCOMP: ADC gain compensation register
func (o *ADC_Type) SetGCOMP(value uint32) {
	volatile.StoreUint32(&o.GCOMP.Reg, volatile.LoadUint32(&o.GCOMP.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetGCOMP() uint32 {
	return (volatile.LoadUint32(&o.GCOMP.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetGCOMP_GCOMPCOEFF(value uint32) {
	volatile.StoreUint32(&o.GCOMP.Reg, volatile.LoadUint32(&o.GCOMP.Reg)&^(0x3fff)|value)
}
func (o *ADC_Type) GetGCOMP_GCOMPCOEFF() uint32 {
	return volatile.LoadUint32(&o.GCOMP.Reg) & 0x3fff
}

// ADC.JDR1: ADC injected data register
func (o *ADC_Type) SetJDR1(value uint32) {
	volatile.StoreUint32(&o.JDR1.Reg, value)
}
func (o *ADC_Type) GetJDR1() uint32 {
	return volatile.LoadUint32(&o.JDR1.Reg)
}

// ADC.JDR2: ADC injected data register
func (o *ADC_Type) SetJDR2(value uint32) {
	volatile.StoreUint32(&o.JDR2.Reg, value)
}
func (o *ADC_Type) GetJDR2() uint32 {
	return volatile.LoadUint32(&o.JDR2.Reg)
}

// ADC.JDR3: ADC injected data register
func (o *ADC_Type) SetJDR3(value uint32) {
	volatile.StoreUint32(&o.JDR3.Reg, value)
}
func (o *ADC_Type) GetJDR3() uint32 {
	return volatile.LoadUint32(&o.JDR3.Reg)
}

// ADC.JDR4: ADC injected data register
func (o *ADC_Type) SetJDR4(value uint32) {
	volatile.StoreUint32(&o.JDR4.Reg, value)
}
func (o *ADC_Type) GetJDR4() uint32 {
	return volatile.LoadUint32(&o.JDR4.Reg)
}

// ADC.AWD2CR: ADC analog watchdog 2 configuration register
func (o *ADC_Type) SetAWD2CR_AWD2CH0(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH0() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetAWD2CR_AWD2CH1(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH1() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetAWD2CR_AWD2CH2(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH2() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetAWD2CR_AWD2CH3(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH3() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetAWD2CR_AWD2CH4(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH4() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetAWD2CR_AWD2CH5(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH5() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetAWD2CR_AWD2CH6(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH6() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetAWD2CR_AWD2CH7(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH7() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetAWD2CR_AWD2CH8(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH8() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetAWD2CR_AWD2CH9(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH9() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetAWD2CR_AWD2CH10(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH10() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetAWD2CR_AWD2CH11(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH11() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetAWD2CR_AWD2CH12(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH12() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetAWD2CR_AWD2CH13(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH13() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetAWD2CR_AWD2CH14(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH14() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetAWD2CR_AWD2CH15(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH15() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetAWD2CR_AWD2CH16(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH16() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetAWD2CR_AWD2CH17(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH17() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetAWD2CR_AWD2CH18(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH18() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x80000) >> 19
}
func (o *ADC_Type) SetAWD2CR_AWD2CH19(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH19() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x100000) >> 20
}

// ADC.AWD3CR: ADC analog watchdog 3 configuration register
func (o *ADC_Type) SetAWD3CR_AWD3CH0(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH0() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetAWD3CR_AWD3CH1(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH1() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetAWD3CR_AWD3CH2(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH2() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetAWD3CR_AWD3CH3(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH3() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetAWD3CR_AWD3CH4(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH4() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetAWD3CR_AWD3CH5(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH5() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetAWD3CR_AWD3CH6(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH6() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetAWD3CR_AWD3CH7(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH7() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetAWD3CR_AWD3CH8(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH8() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetAWD3CR_AWD3CH9(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH9() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetAWD3CR_AWD3CH10(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH10() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetAWD3CR_AWD3CH11(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH11() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetAWD3CR_AWD3CH12(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH12() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetAWD3CR_AWD3CH13(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH13() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetAWD3CR_AWD3CH14(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH14() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetAWD3CR_AWD3CH15(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH15() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetAWD3CR_AWD3CH16(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH16() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetAWD3CR_AWD3CH17(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH17() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetAWD3CR_AWD3CH18(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH18() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x80000) >> 19
}
func (o *ADC_Type) SetAWD3CR_AWD3CH19(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH19() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x100000) >> 20
}

// ADC.LTR1: ADC watchdog threshold register 1
func (o *ADC_Type) SetLTR1(value uint32) {
	volatile.StoreUint32(&o.LTR1.Reg, volatile.LoadUint32(&o.LTR1.Reg)&^(0x1ffffff)|value)
}
func (o *ADC_Type) GetLTR1() uint32 {
	return volatile.LoadUint32(&o.LTR1.Reg) & 0x1ffffff
}

// ADC.HTR1: ADC watchdog threshold register 1
func (o *ADC_Type) SetHTR1_AWDFILT1(value uint32) {
	volatile.StoreUint32(&o.HTR1.Reg, volatile.LoadUint32(&o.HTR1.Reg)&^(0xe0000000)|value<<29)
}
func (o *ADC_Type) GetHTR1_AWDFILT1() uint32 {
	return (volatile.LoadUint32(&o.HTR1.Reg) & 0xe0000000) >> 29
}
func (o *ADC_Type) SetHTR1(value uint32) {
	volatile.StoreUint32(&o.HTR1.Reg, volatile.LoadUint32(&o.HTR1.Reg)&^(0x1ffffff)|value)
}
func (o *ADC_Type) GetHTR1() uint32 {
	return volatile.LoadUint32(&o.HTR1.Reg) & 0x1ffffff
}

// ADC.LTR2: ADC watchdog lower threshold register 2
func (o *ADC_Type) SetLTR2(value uint32) {
	volatile.StoreUint32(&o.LTR2.Reg, volatile.LoadUint32(&o.LTR2.Reg)&^(0x1ffffff)|value)
}
func (o *ADC_Type) GetLTR2() uint32 {
	return volatile.LoadUint32(&o.LTR2.Reg) & 0x1ffffff
}

// ADC.HTR2: ADC watchdog higher threshold register 2
func (o *ADC_Type) SetHTR2(value uint32) {
	volatile.StoreUint32(&o.HTR2.Reg, volatile.LoadUint32(&o.HTR2.Reg)&^(0x1ffffff)|value)
}
func (o *ADC_Type) GetHTR2() uint32 {
	return volatile.LoadUint32(&o.HTR2.Reg) & 0x1ffffff
}

// ADC.LTR3: ADC watchdog lower threshold register 3
func (o *ADC_Type) SetLTR3(value uint32) {
	volatile.StoreUint32(&o.LTR3.Reg, volatile.LoadUint32(&o.LTR3.Reg)&^(0x1ffffff)|value)
}
func (o *ADC_Type) GetLTR3() uint32 {
	return volatile.LoadUint32(&o.LTR3.Reg) & 0x1ffffff
}

// ADC.HTR3: ADC watchdog higher threshold register 3
func (o *ADC_Type) SetHTR3(value uint32) {
	volatile.StoreUint32(&o.HTR3.Reg, volatile.LoadUint32(&o.HTR3.Reg)&^(0x1ffffff)|value)
}
func (o *ADC_Type) GetHTR3() uint32 {
	return volatile.LoadUint32(&o.HTR3.Reg) & 0x1ffffff
}

// ADC.DIFSEL: ADC differential mode selection register
func (o *ADC_Type) SetDIFSEL_DIFSEL0(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL0() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetDIFSEL_DIFSEL1(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL1() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetDIFSEL_DIFSEL2(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL2() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetDIFSEL_DIFSEL3(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL3() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetDIFSEL_DIFSEL4(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL4() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetDIFSEL_DIFSEL5(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL5() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetDIFSEL_DIFSEL6(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL6() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetDIFSEL_DIFSEL7(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL7() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetDIFSEL_DIFSEL8(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL8() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetDIFSEL_DIFSEL9(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL9() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetDIFSEL_DIFSEL10(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL10() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetDIFSEL_DIFSEL11(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL11() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetDIFSEL_DIFSEL12(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL12() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetDIFSEL_DIFSEL13(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL13() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetDIFSEL_DIFSEL14(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL14() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetDIFSEL_DIFSEL15(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL15() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetDIFSEL_DIFSEL16(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL16() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetDIFSEL_DIFSEL17(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL17() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetDIFSEL_DIFSEL18(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL18() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x80000) >> 19
}
func (o *ADC_Type) SetDIFSEL_DIFSEL19(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL19() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x100000) >> 20
}

// ADC.CALFACT: ADC user control register
func (o *ADC_Type) SetCALFACT_CAPTURE_COEF(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetCALFACT_CAPTURE_COEF() uint32 {
	return (volatile.LoadUint32(&o.CALFACT.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetCALFACT_LATCH_COEF(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetCALFACT_LATCH_COEF() uint32 {
	return (volatile.LoadUint32(&o.CALFACT.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetCALFACT_VALIDITY(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetCALFACT_VALIDITY() uint32 {
	return (volatile.LoadUint32(&o.CALFACT.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetCALFACT_I_APB_DATA(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0xff00)|value<<8)
}
func (o *ADC_Type) GetCALFACT_I_APB_DATA() uint32 {
	return (volatile.LoadUint32(&o.CALFACT.Reg) & 0xff00) >> 8
}
func (o *ADC_Type) SetCALFACT_I_APB_ADDR(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0xff)|value)
}
func (o *ADC_Type) GetCALFACT_I_APB_ADDR() uint32 {
	return volatile.LoadUint32(&o.CALFACT.Reg) & 0xff
}

// ADC.CALFACT2: ADC calibration factor register
func (o *ADC_Type) SetCALFACT2(value uint32) {
	volatile.StoreUint32(&o.CALFACT2.Reg, value)
}
func (o *ADC_Type) GetCALFACT2() uint32 {
	return volatile.LoadUint32(&o.CALFACT2.Reg)
}

// ADF1
type ADF_Type struct {
	GCR       volatile.Register32 // 0x0
	CKGCR     volatile.Register32 // 0x4
	_         [120]byte
	SITF0CR   volatile.Register32 // 0x80
	BSMX0CR   volatile.Register32 // 0x84
	DFLT0CR   volatile.Register32 // 0x88
	DFLT0CICR volatile.Register32 // 0x8C
	DFLT0RSFR volatile.Register32 // 0x90
	_         [16]byte
	DLY0CR    volatile.Register32 // 0xA4
	_         [4]byte
	DFLT0IER  volatile.Register32 // 0xAC
	DFLT0ISR  volatile.Register32 // 0xB0
	_         [4]byte
	SADCR     volatile.Register32 // 0xB8
	SADCFGR   volatile.Register32 // 0xBC
	SADSDLVR  volatile.Register32 // 0xC0
	SADANLVR  volatile.Register32 // 0xC4
	_         [40]byte
	DFLT0DR   volatile.Register32 // 0xF0
}

// ADF.GCR: ADF Global Control Register
func (o *ADF_Type) SetGCR_TRGO(value uint32) {
	volatile.StoreUint32(&o.GCR.Reg, volatile.LoadUint32(&o.GCR.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetGCR_TRGO() uint32 {
	return volatile.LoadUint32(&o.GCR.Reg) & 0x1
}

// ADF.CKGCR: ADF clock generator control register
func (o *ADF_Type) SetCKGCR_CKGACTIVE(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADF_Type) GetCKGCR_CKGACTIVE() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x80000000) >> 31
}
func (o *ADF_Type) SetCKGCR_PROCDIV(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x7f000000)|value<<24)
}
func (o *ADF_Type) GetCKGCR_PROCDIV() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x7f000000) >> 24
}
func (o *ADF_Type) SetCKGCR_CCKDIV(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0xf0000)|value<<16)
}
func (o *ADF_Type) GetCKGCR_CCKDIV() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0xf0000) >> 16
}
func (o *ADF_Type) SetCKGCR_TRGSRC(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0xf000)|value<<12)
}
func (o *ADF_Type) GetCKGCR_TRGSRC() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0xf000) >> 12
}
func (o *ADF_Type) SetCKGCR_TRGSENS(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x100)|value<<8)
}
func (o *ADF_Type) GetCKGCR_TRGSENS() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x100) >> 8
}
func (o *ADF_Type) SetCKGCR_CCK1DIR(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x40)|value<<6)
}
func (o *ADF_Type) GetCKGCR_CCK1DIR() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x40) >> 6
}
func (o *ADF_Type) SetCKGCR_CCK0DIR(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x20)|value<<5)
}
func (o *ADF_Type) GetCKGCR_CCK0DIR() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x20) >> 5
}
func (o *ADF_Type) SetCKGCR_CKGMOD(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x10)|value<<4)
}
func (o *ADF_Type) GetCKGCR_CKGMOD() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x10) >> 4
}
func (o *ADF_Type) SetCKGCR_CCK1EN(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x4)|value<<2)
}
func (o *ADF_Type) GetCKGCR_CCK1EN() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x4) >> 2
}
func (o *ADF_Type) SetCKGCR_CCK0EN(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x2)|value<<1)
}
func (o *ADF_Type) GetCKGCR_CCK0EN() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x2) >> 1
}
func (o *ADF_Type) SetCKGCR_CKGDEN(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetCKGCR_CKGDEN() uint32 {
	return volatile.LoadUint32(&o.CKGCR.Reg) & 0x1
}

// ADF.SITF0CR: ADF serial interface control register 0
func (o *ADF_Type) SetSITF0CR_SITFACTIVE(value uint32) {
	volatile.StoreUint32(&o.SITF0CR.Reg, volatile.LoadUint32(&o.SITF0CR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADF_Type) GetSITF0CR_SITFACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SITF0CR.Reg) & 0x80000000) >> 31
}
func (o *ADF_Type) SetSITF0CR_STH(value uint32) {
	volatile.StoreUint32(&o.SITF0CR.Reg, volatile.LoadUint32(&o.SITF0CR.Reg)&^(0x1f00)|value<<8)
}
func (o *ADF_Type) GetSITF0CR_STH() uint32 {
	return (volatile.LoadUint32(&o.SITF0CR.Reg) & 0x1f00) >> 8
}
func (o *ADF_Type) SetSITF0CR_SITFMOD(value uint32) {
	volatile.StoreUint32(&o.SITF0CR.Reg, volatile.LoadUint32(&o.SITF0CR.Reg)&^(0x30)|value<<4)
}
func (o *ADF_Type) GetSITF0CR_SITFMOD() uint32 {
	return (volatile.LoadUint32(&o.SITF0CR.Reg) & 0x30) >> 4
}
func (o *ADF_Type) SetSITF0CR_SCKSRC(value uint32) {
	volatile.StoreUint32(&o.SITF0CR.Reg, volatile.LoadUint32(&o.SITF0CR.Reg)&^(0x6)|value<<1)
}
func (o *ADF_Type) GetSITF0CR_SCKSRC() uint32 {
	return (volatile.LoadUint32(&o.SITF0CR.Reg) & 0x6) >> 1
}
func (o *ADF_Type) SetSITF0CR_SITFEN(value uint32) {
	volatile.StoreUint32(&o.SITF0CR.Reg, volatile.LoadUint32(&o.SITF0CR.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetSITF0CR_SITFEN() uint32 {
	return volatile.LoadUint32(&o.SITF0CR.Reg) & 0x1
}

// ADF.BSMX0CR: ADF bitstream matrix control register 0
func (o *ADF_Type) SetBSMX0CR_BSMXACTIVE(value uint32) {
	volatile.StoreUint32(&o.BSMX0CR.Reg, volatile.LoadUint32(&o.BSMX0CR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADF_Type) GetBSMX0CR_BSMXACTIVE() uint32 {
	return (volatile.LoadUint32(&o.BSMX0CR.Reg) & 0x80000000) >> 31
}
func (o *ADF_Type) SetBSMX0CR_BSSEL(value uint32) {
	volatile.StoreUint32(&o.BSMX0CR.Reg, volatile.LoadUint32(&o.BSMX0CR.Reg)&^(0x1f)|value)
}
func (o *ADF_Type) GetBSMX0CR_BSSEL() uint32 {
	return volatile.LoadUint32(&o.BSMX0CR.Reg) & 0x1f
}

// ADF.DFLT0CR: ADF digital filter control register 0
func (o *ADF_Type) SetDFLT0CR_DFLTACTIVE(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADF_Type) GetDFLT0CR_DFLTACTIVE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CR.Reg) & 0x80000000) >> 31
}
func (o *ADF_Type) SetDFLT0CR_DFLTRUN(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0x40000000)|value<<30)
}
func (o *ADF_Type) GetDFLT0CR_DFLTRUN() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CR.Reg) & 0x40000000) >> 30
}
func (o *ADF_Type) SetDFLT0CR_NBDIS(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0xff00000)|value<<20)
}
func (o *ADF_Type) GetDFLT0CR_NBDIS() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CR.Reg) & 0xff00000) >> 20
}
func (o *ADF_Type) SetDFLT0CR_TRGSRC(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0xf000)|value<<12)
}
func (o *ADF_Type) GetDFLT0CR_TRGSRC() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CR.Reg) & 0xf000) >> 12
}
func (o *ADF_Type) SetDFLT0CR_ACQMOD(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0x70)|value<<4)
}
func (o *ADF_Type) GetDFLT0CR_ACQMOD() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CR.Reg) & 0x70) >> 4
}
func (o *ADF_Type) SetDFLT0CR_FTH(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0x4)|value<<2)
}
func (o *ADF_Type) GetDFLT0CR_FTH() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CR.Reg) & 0x4) >> 2
}
func (o *ADF_Type) SetDFLT0CR_DMAEN(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0x2)|value<<1)
}
func (o *ADF_Type) GetDFLT0CR_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CR.Reg) & 0x2) >> 1
}
func (o *ADF_Type) SetDFLT0CR_DFLTEN(value uint32) {
	volatile.StoreUint32(&o.DFLT0CR.Reg, volatile.LoadUint32(&o.DFLT0CR.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetDFLT0CR_DFLTEN() uint32 {
	return volatile.LoadUint32(&o.DFLT0CR.Reg) & 0x1
}

// ADF.DFLT0CICR: ADF digital filer configuration register 0
func (o *ADF_Type) SetDFLT0CICR_SCALE(value uint32) {
	volatile.StoreUint32(&o.DFLT0CICR.Reg, volatile.LoadUint32(&o.DFLT0CICR.Reg)&^(0x3f00000)|value<<20)
}
func (o *ADF_Type) GetDFLT0CICR_SCALE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CICR.Reg) & 0x3f00000) >> 20
}
func (o *ADF_Type) SetDFLT0CICR_MCICD(value uint32) {
	volatile.StoreUint32(&o.DFLT0CICR.Reg, volatile.LoadUint32(&o.DFLT0CICR.Reg)&^(0x1ff00)|value<<8)
}
func (o *ADF_Type) GetDFLT0CICR_MCICD() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CICR.Reg) & 0x1ff00) >> 8
}
func (o *ADF_Type) SetDFLT0CICR_CICMOD(value uint32) {
	volatile.StoreUint32(&o.DFLT0CICR.Reg, volatile.LoadUint32(&o.DFLT0CICR.Reg)&^(0x70)|value<<4)
}
func (o *ADF_Type) GetDFLT0CICR_CICMOD() uint32 {
	return (volatile.LoadUint32(&o.DFLT0CICR.Reg) & 0x70) >> 4
}
func (o *ADF_Type) SetDFLT0CICR_DATSRC(value uint32) {
	volatile.StoreUint32(&o.DFLT0CICR.Reg, volatile.LoadUint32(&o.DFLT0CICR.Reg)&^(0x3)|value)
}
func (o *ADF_Type) GetDFLT0CICR_DATSRC() uint32 {
	return volatile.LoadUint32(&o.DFLT0CICR.Reg) & 0x3
}

// ADF.DFLT0RSFR: ADF reshape filter configuration register 0
func (o *ADF_Type) SetDFLT0RSFR_HPFC(value uint32) {
	volatile.StoreUint32(&o.DFLT0RSFR.Reg, volatile.LoadUint32(&o.DFLT0RSFR.Reg)&^(0x300)|value<<8)
}
func (o *ADF_Type) GetDFLT0RSFR_HPFC() uint32 {
	return (volatile.LoadUint32(&o.DFLT0RSFR.Reg) & 0x300) >> 8
}
func (o *ADF_Type) SetDFLT0RSFR_HPFBYP(value uint32) {
	volatile.StoreUint32(&o.DFLT0RSFR.Reg, volatile.LoadUint32(&o.DFLT0RSFR.Reg)&^(0x80)|value<<7)
}
func (o *ADF_Type) GetDFLT0RSFR_HPFBYP() uint32 {
	return (volatile.LoadUint32(&o.DFLT0RSFR.Reg) & 0x80) >> 7
}
func (o *ADF_Type) SetDFLT0RSFR_RSFLTD(value uint32) {
	volatile.StoreUint32(&o.DFLT0RSFR.Reg, volatile.LoadUint32(&o.DFLT0RSFR.Reg)&^(0x10)|value<<4)
}
func (o *ADF_Type) GetDFLT0RSFR_RSFLTD() uint32 {
	return (volatile.LoadUint32(&o.DFLT0RSFR.Reg) & 0x10) >> 4
}
func (o *ADF_Type) SetDFLT0RSFR_RSFLTBYP(value uint32) {
	volatile.StoreUint32(&o.DFLT0RSFR.Reg, volatile.LoadUint32(&o.DFLT0RSFR.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetDFLT0RSFR_RSFLTBYP() uint32 {
	return volatile.LoadUint32(&o.DFLT0RSFR.Reg) & 0x1
}

// ADF.DLY0CR: ADF delay control register 0
func (o *ADF_Type) SetDLY0CR_SKPBF(value uint32) {
	volatile.StoreUint32(&o.DLY0CR.Reg, volatile.LoadUint32(&o.DLY0CR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADF_Type) GetDLY0CR_SKPBF() uint32 {
	return (volatile.LoadUint32(&o.DLY0CR.Reg) & 0x80000000) >> 31
}
func (o *ADF_Type) SetDLY0CR_SKPDLY(value uint32) {
	volatile.StoreUint32(&o.DLY0CR.Reg, volatile.LoadUint32(&o.DLY0CR.Reg)&^(0x7f)|value)
}
func (o *ADF_Type) GetDLY0CR_SKPDLY() uint32 {
	return volatile.LoadUint32(&o.DLY0CR.Reg) & 0x7f
}

// ADF.DFLT0IER: ADF DFLT0 interrupt enable register
func (o *ADF_Type) SetDFLT0IER_SDLVLIE(value uint32) {
	volatile.StoreUint32(&o.DFLT0IER.Reg, volatile.LoadUint32(&o.DFLT0IER.Reg)&^(0x2000)|value<<13)
}
func (o *ADF_Type) GetDFLT0IER_SDLVLIE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0IER.Reg) & 0x2000) >> 13
}
func (o *ADF_Type) SetDFLT0IER_SDDETIE(value uint32) {
	volatile.StoreUint32(&o.DFLT0IER.Reg, volatile.LoadUint32(&o.DFLT0IER.Reg)&^(0x1000)|value<<12)
}
func (o *ADF_Type) GetDFLT0IER_SDDETIE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0IER.Reg) & 0x1000) >> 12
}
func (o *ADF_Type) SetDFLT0IER_RFOVRIE(value uint32) {
	volatile.StoreUint32(&o.DFLT0IER.Reg, volatile.LoadUint32(&o.DFLT0IER.Reg)&^(0x800)|value<<11)
}
func (o *ADF_Type) GetDFLT0IER_RFOVRIE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0IER.Reg) & 0x800) >> 11
}
func (o *ADF_Type) SetDFLT0IER_CKABIE(value uint32) {
	volatile.StoreUint32(&o.DFLT0IER.Reg, volatile.LoadUint32(&o.DFLT0IER.Reg)&^(0x400)|value<<10)
}
func (o *ADF_Type) GetDFLT0IER_CKABIE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0IER.Reg) & 0x400) >> 10
}
func (o *ADF_Type) SetDFLT0IER_SATIE(value uint32) {
	volatile.StoreUint32(&o.DFLT0IER.Reg, volatile.LoadUint32(&o.DFLT0IER.Reg)&^(0x200)|value<<9)
}
func (o *ADF_Type) GetDFLT0IER_SATIE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0IER.Reg) & 0x200) >> 9
}
func (o *ADF_Type) SetDFLT0IER_DOVRIE(value uint32) {
	volatile.StoreUint32(&o.DFLT0IER.Reg, volatile.LoadUint32(&o.DFLT0IER.Reg)&^(0x2)|value<<1)
}
func (o *ADF_Type) GetDFLT0IER_DOVRIE() uint32 {
	return (volatile.LoadUint32(&o.DFLT0IER.Reg) & 0x2) >> 1
}
func (o *ADF_Type) SetDFLT0IER_FTHIE(value uint32) {
	volatile.StoreUint32(&o.DFLT0IER.Reg, volatile.LoadUint32(&o.DFLT0IER.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetDFLT0IER_FTHIE() uint32 {
	return volatile.LoadUint32(&o.DFLT0IER.Reg) & 0x1
}

// ADF.DFLT0ISR: ADF DFLT0 interrupt status register 0
func (o *ADF_Type) SetDFLT0ISR_SDLVLF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x2000)|value<<13)
}
func (o *ADF_Type) GetDFLT0ISR_SDLVLF() uint32 {
	return (volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x2000) >> 13
}
func (o *ADF_Type) SetDFLT0ISR_SDDETF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x1000)|value<<12)
}
func (o *ADF_Type) GetDFLT0ISR_SDDETF() uint32 {
	return (volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x1000) >> 12
}
func (o *ADF_Type) SetDFLT0ISR_RFOVRF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x800)|value<<11)
}
func (o *ADF_Type) GetDFLT0ISR_RFOVRF() uint32 {
	return (volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x800) >> 11
}
func (o *ADF_Type) SetDFLT0ISR_CKABF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x400)|value<<10)
}
func (o *ADF_Type) GetDFLT0ISR_CKABF() uint32 {
	return (volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x400) >> 10
}
func (o *ADF_Type) SetDFLT0ISR_SATF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x200)|value<<9)
}
func (o *ADF_Type) GetDFLT0ISR_SATF() uint32 {
	return (volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x200) >> 9
}
func (o *ADF_Type) SetDFLT0ISR_RXNEF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x8)|value<<3)
}
func (o *ADF_Type) GetDFLT0ISR_RXNEF() uint32 {
	return (volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x8) >> 3
}
func (o *ADF_Type) SetDFLT0ISR_DOVRF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x2)|value<<1)
}
func (o *ADF_Type) GetDFLT0ISR_DOVRF() uint32 {
	return (volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x2) >> 1
}
func (o *ADF_Type) SetDFLT0ISR_FTHF(value uint32) {
	volatile.StoreUint32(&o.DFLT0ISR.Reg, volatile.LoadUint32(&o.DFLT0ISR.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetDFLT0ISR_FTHF() uint32 {
	return volatile.LoadUint32(&o.DFLT0ISR.Reg) & 0x1
}

// ADF.SADCR: ADF SAD control register
func (o *ADF_Type) SetSADCR_SADACTIVE(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADF_Type) GetSADCR_SADACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SADCR.Reg) & 0x80000000) >> 31
}
func (o *ADF_Type) SetSADCR_SADMOD(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x3000)|value<<12)
}
func (o *ADF_Type) GetSADCR_SADMOD() uint32 {
	return (volatile.LoadUint32(&o.SADCR.Reg) & 0x3000) >> 12
}
func (o *ADF_Type) SetSADCR_FRSIZE(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x700)|value<<8)
}
func (o *ADF_Type) GetSADCR_FRSIZE() uint32 {
	return (volatile.LoadUint32(&o.SADCR.Reg) & 0x700) >> 8
}
func (o *ADF_Type) SetSADCR_HYSTEN(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x80)|value<<7)
}
func (o *ADF_Type) GetSADCR_HYSTEN() uint32 {
	return (volatile.LoadUint32(&o.SADCR.Reg) & 0x80) >> 7
}
func (o *ADF_Type) SetSADCR_SADST(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x30)|value<<4)
}
func (o *ADF_Type) GetSADCR_SADST() uint32 {
	return (volatile.LoadUint32(&o.SADCR.Reg) & 0x30) >> 4
}
func (o *ADF_Type) SetSADCR_DETCFG(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x8)|value<<3)
}
func (o *ADF_Type) GetSADCR_DETCFG() uint32 {
	return (volatile.LoadUint32(&o.SADCR.Reg) & 0x8) >> 3
}
func (o *ADF_Type) SetSADCR_DATCAP(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x6)|value<<1)
}
func (o *ADF_Type) GetSADCR_DATCAP() uint32 {
	return (volatile.LoadUint32(&o.SADCR.Reg) & 0x6) >> 1
}
func (o *ADF_Type) SetSADCR_SADEN(value uint32) {
	volatile.StoreUint32(&o.SADCR.Reg, volatile.LoadUint32(&o.SADCR.Reg)&^(0x1)|value)
}
func (o *ADF_Type) GetSADCR_SADEN() uint32 {
	return volatile.LoadUint32(&o.SADCR.Reg) & 0x1
}

// ADF.SADCFGR: ADF SAD configuration register
func (o *ADF_Type) SetSADCFGR_ANMIN(value uint32) {
	volatile.StoreUint32(&o.SADCFGR.Reg, volatile.LoadUint32(&o.SADCFGR.Reg)&^(0x1fff0000)|value<<16)
}
func (o *ADF_Type) GetSADCFGR_ANMIN() uint32 {
	return (volatile.LoadUint32(&o.SADCFGR.Reg) & 0x1fff0000) >> 16
}
func (o *ADF_Type) SetSADCFGR_HGOVR(value uint32) {
	volatile.StoreUint32(&o.SADCFGR.Reg, volatile.LoadUint32(&o.SADCFGR.Reg)&^(0x7000)|value<<12)
}
func (o *ADF_Type) GetSADCFGR_HGOVR() uint32 {
	return (volatile.LoadUint32(&o.SADCFGR.Reg) & 0x7000) >> 12
}
func (o *ADF_Type) SetSADCFGR_LFRNB(value uint32) {
	volatile.StoreUint32(&o.SADCFGR.Reg, volatile.LoadUint32(&o.SADCFGR.Reg)&^(0x700)|value<<8)
}
func (o *ADF_Type) GetSADCFGR_LFRNB() uint32 {
	return (volatile.LoadUint32(&o.SADCFGR.Reg) & 0x700) >> 8
}
func (o *ADF_Type) SetSADCFGR_ANSLP(value uint32) {
	volatile.StoreUint32(&o.SADCFGR.Reg, volatile.LoadUint32(&o.SADCFGR.Reg)&^(0x70)|value<<4)
}
func (o *ADF_Type) GetSADCFGR_ANSLP() uint32 {
	return (volatile.LoadUint32(&o.SADCFGR.Reg) & 0x70) >> 4
}
func (o *ADF_Type) SetSADCFGR_SNTHR(value uint32) {
	volatile.StoreUint32(&o.SADCFGR.Reg, volatile.LoadUint32(&o.SADCFGR.Reg)&^(0xf)|value)
}
func (o *ADF_Type) GetSADCFGR_SNTHR() uint32 {
	return volatile.LoadUint32(&o.SADCFGR.Reg) & 0xf
}

// ADF.SADSDLVR: ADF SAD sound level register
func (o *ADF_Type) SetSADSDLVR_SDLVL(value uint32) {
	volatile.StoreUint32(&o.SADSDLVR.Reg, volatile.LoadUint32(&o.SADSDLVR.Reg)&^(0x7fff)|value)
}
func (o *ADF_Type) GetSADSDLVR_SDLVL() uint32 {
	return volatile.LoadUint32(&o.SADSDLVR.Reg) & 0x7fff
}

// ADF.SADANLVR: ADF SAD ambient noise level register
func (o *ADF_Type) SetSADANLVR_ANLVL(value uint32) {
	volatile.StoreUint32(&o.SADANLVR.Reg, volatile.LoadUint32(&o.SADANLVR.Reg)&^(0x7fff)|value)
}
func (o *ADF_Type) GetSADANLVR_ANLVL() uint32 {
	return volatile.LoadUint32(&o.SADANLVR.Reg) & 0x7fff
}

// ADF.DFLT0DR: ADF digital filter data register 0
func (o *ADF_Type) SetDFLT0DR_DR(value uint32) {
	volatile.StoreUint32(&o.DFLT0DR.Reg, volatile.LoadUint32(&o.DFLT0DR.Reg)&^(0xffffff00)|value<<8)
}
func (o *ADF_Type) GetDFLT0DR_DR() uint32 {
	return (volatile.LoadUint32(&o.DFLT0DR.Reg) & 0xffffff00) >> 8
}

// Advanced encryption standard hardware accelerator
type AES_Type struct {
	CR     volatile.Register32 // 0x0
	SR     volatile.Register32 // 0x4
	DINR   volatile.Register32 // 0x8
	DOUTR  volatile.Register32 // 0xC
	KEYR0  volatile.Register32 // 0x10
	KEYR1  volatile.Register32 // 0x14
	KEYR2  volatile.Register32 // 0x18
	KEYR3  volatile.Register32 // 0x1C
	IVR0   volatile.Register32 // 0x20
	IVR1   volatile.Register32 // 0x24
	IVR2   volatile.Register32 // 0x28
	IVR3   volatile.Register32 // 0x2C
	KEYR4  volatile.Register32 // 0x30
	KEYR5  volatile.Register32 // 0x34
	KEYR6  volatile.Register32 // 0x38
	KEYR7  volatile.Register32 // 0x3C
	SUSP0R volatile.Register32 // 0x40
	SUSP1R volatile.Register32 // 0x44
	SUSP2R volatile.Register32 // 0x48
	SUSP3R volatile.Register32 // 0x4C
	SUSP4R volatile.Register32 // 0x50
	SUSP5R volatile.Register32 // 0x54
	SUSP6R volatile.Register32 // 0x58
	SUSP7R volatile.Register32 // 0x5C
	_      [672]byte
	IER    volatile.Register32 // 0x300
	ISR    volatile.Register32 // 0x304
	ICR    volatile.Register32 // 0x308
}

// AES.CR: control register
func (o *AES_Type) SetCR_IPRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *AES_Type) GetCR_IPRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}
func (o *AES_Type) SetCR_KMOD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3000000)|value<<24)
}
func (o *AES_Type) GetCR_KMOD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3000000) >> 24
}
func (o *AES_Type) SetCR_NPBLB(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf00000)|value<<20)
}
func (o *AES_Type) GetCR_NPBLB() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf00000) >> 20
}
func (o *AES_Type) SetCR_KEYSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *AES_Type) GetCR_KEYSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *AES_Type) SetCR_CHMOD_2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *AES_Type) GetCR_CHMOD_2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *AES_Type) SetCR_GCMPH(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x6000)|value<<13)
}
func (o *AES_Type) GetCR_GCMPH() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x6000) >> 13
}
func (o *AES_Type) SetCR_DMAOUTEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *AES_Type) GetCR_DMAOUTEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *AES_Type) SetCR_DMAINEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *AES_Type) GetCR_DMAINEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *AES_Type) SetCR_CHMOD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x60)|value<<5)
}
func (o *AES_Type) GetCR_CHMOD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x60) >> 5
}
func (o *AES_Type) SetCR_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x18)|value<<3)
}
func (o *AES_Type) GetCR_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x18) >> 3
}
func (o *AES_Type) SetCR_DATATYPE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x6)|value<<1)
}
func (o *AES_Type) GetCR_DATATYPE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x6) >> 1
}
func (o *AES_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// AES.SR: status register
func (o *AES_Type) SetSR_KEYVALID(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *AES_Type) GetSR_KEYVALID() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *AES_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *AES_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *AES_Type) SetSR_WRERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *AES_Type) GetSR_WRERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *AES_Type) SetSR_RDERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *AES_Type) GetSR_RDERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *AES_Type) SetSR_CCF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetSR_CCF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// AES.DINR: data input register
func (o *AES_Type) SetDINR(value uint32) {
	volatile.StoreUint32(&o.DINR.Reg, value)
}
func (o *AES_Type) GetDINR() uint32 {
	return volatile.LoadUint32(&o.DINR.Reg)
}

// AES.DOUTR: data output register
func (o *AES_Type) SetDOUTR(value uint32) {
	volatile.StoreUint32(&o.DOUTR.Reg, value)
}
func (o *AES_Type) GetDOUTR() uint32 {
	return volatile.LoadUint32(&o.DOUTR.Reg)
}

// AES.KEYR0: key register 0
func (o *AES_Type) SetKEYR0(value uint32) {
	volatile.StoreUint32(&o.KEYR0.Reg, value)
}
func (o *AES_Type) GetKEYR0() uint32 {
	return volatile.LoadUint32(&o.KEYR0.Reg)
}

// AES.KEYR1: key register 1
func (o *AES_Type) SetKEYR1(value uint32) {
	volatile.StoreUint32(&o.KEYR1.Reg, value)
}
func (o *AES_Type) GetKEYR1() uint32 {
	return volatile.LoadUint32(&o.KEYR1.Reg)
}

// AES.KEYR2: key register 2
func (o *AES_Type) SetKEYR2(value uint32) {
	volatile.StoreUint32(&o.KEYR2.Reg, value)
}
func (o *AES_Type) GetKEYR2() uint32 {
	return volatile.LoadUint32(&o.KEYR2.Reg)
}

// AES.KEYR3: key register 3
func (o *AES_Type) SetKEYR3(value uint32) {
	volatile.StoreUint32(&o.KEYR3.Reg, value)
}
func (o *AES_Type) GetKEYR3() uint32 {
	return volatile.LoadUint32(&o.KEYR3.Reg)
}

// AES.IVR0: initialization vector register 0
func (o *AES_Type) SetIVR0(value uint32) {
	volatile.StoreUint32(&o.IVR0.Reg, value)
}
func (o *AES_Type) GetIVR0() uint32 {
	return volatile.LoadUint32(&o.IVR0.Reg)
}

// AES.IVR1: initialization vector register 1
func (o *AES_Type) SetIVR1(value uint32) {
	volatile.StoreUint32(&o.IVR1.Reg, value)
}
func (o *AES_Type) GetIVR1() uint32 {
	return volatile.LoadUint32(&o.IVR1.Reg)
}

// AES.IVR2: initialization vector register 2
func (o *AES_Type) SetIVR2(value uint32) {
	volatile.StoreUint32(&o.IVR2.Reg, value)
}
func (o *AES_Type) GetIVR2() uint32 {
	return volatile.LoadUint32(&o.IVR2.Reg)
}

// AES.IVR3: initialization vector register 3
func (o *AES_Type) SetIVR3(value uint32) {
	volatile.StoreUint32(&o.IVR3.Reg, value)
}
func (o *AES_Type) GetIVR3() uint32 {
	return volatile.LoadUint32(&o.IVR3.Reg)
}

// AES.KEYR4: key register 4
func (o *AES_Type) SetKEYR4(value uint32) {
	volatile.StoreUint32(&o.KEYR4.Reg, value)
}
func (o *AES_Type) GetKEYR4() uint32 {
	return volatile.LoadUint32(&o.KEYR4.Reg)
}

// AES.KEYR5: key register 5
func (o *AES_Type) SetKEYR5(value uint32) {
	volatile.StoreUint32(&o.KEYR5.Reg, value)
}
func (o *AES_Type) GetKEYR5() uint32 {
	return volatile.LoadUint32(&o.KEYR5.Reg)
}

// AES.KEYR6: key register 6
func (o *AES_Type) SetKEYR6(value uint32) {
	volatile.StoreUint32(&o.KEYR6.Reg, value)
}
func (o *AES_Type) GetKEYR6() uint32 {
	return volatile.LoadUint32(&o.KEYR6.Reg)
}

// AES.KEYR7: key register 7
func (o *AES_Type) SetKEYR7(value uint32) {
	volatile.StoreUint32(&o.KEYR7.Reg, value)
}
func (o *AES_Type) GetKEYR7() uint32 {
	return volatile.LoadUint32(&o.KEYR7.Reg)
}

// AES.SUSP0R: suspend registers
func (o *AES_Type) SetSUSP0R(value uint32) {
	volatile.StoreUint32(&o.SUSP0R.Reg, value)
}
func (o *AES_Type) GetSUSP0R() uint32 {
	return volatile.LoadUint32(&o.SUSP0R.Reg)
}

// AES.SUSP1R: suspend registers
func (o *AES_Type) SetSUSP1R(value uint32) {
	volatile.StoreUint32(&o.SUSP1R.Reg, value)
}
func (o *AES_Type) GetSUSP1R() uint32 {
	return volatile.LoadUint32(&o.SUSP1R.Reg)
}

// AES.SUSP2R: suspend registers
func (o *AES_Type) SetSUSP2R(value uint32) {
	volatile.StoreUint32(&o.SUSP2R.Reg, value)
}
func (o *AES_Type) GetSUSP2R() uint32 {
	return volatile.LoadUint32(&o.SUSP2R.Reg)
}

// AES.SUSP3R: suspend registers
func (o *AES_Type) SetSUSP3R(value uint32) {
	volatile.StoreUint32(&o.SUSP3R.Reg, value)
}
func (o *AES_Type) GetSUSP3R() uint32 {
	return volatile.LoadUint32(&o.SUSP3R.Reg)
}

// AES.SUSP4R: suspend registers
func (o *AES_Type) SetSUSP4R(value uint32) {
	volatile.StoreUint32(&o.SUSP4R.Reg, value)
}
func (o *AES_Type) GetSUSP4R() uint32 {
	return volatile.LoadUint32(&o.SUSP4R.Reg)
}

// AES.SUSP5R: suspend registers
func (o *AES_Type) SetSUSP5R(value uint32) {
	volatile.StoreUint32(&o.SUSP5R.Reg, value)
}
func (o *AES_Type) GetSUSP5R() uint32 {
	return volatile.LoadUint32(&o.SUSP5R.Reg)
}

// AES.SUSP6R: suspend registers
func (o *AES_Type) SetSUSP6R(value uint32) {
	volatile.StoreUint32(&o.SUSP6R.Reg, value)
}
func (o *AES_Type) GetSUSP6R() uint32 {
	return volatile.LoadUint32(&o.SUSP6R.Reg)
}

// AES.SUSP7R: suspend registers
func (o *AES_Type) SetSUSP7R(value uint32) {
	volatile.StoreUint32(&o.SUSP7R.Reg, value)
}
func (o *AES_Type) GetSUSP7R() uint32 {
	return volatile.LoadUint32(&o.SUSP7R.Reg)
}

// AES.IER: interrupt enable register
func (o *AES_Type) SetIER_CCFIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetIER_CCFIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *AES_Type) SetIER_KEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *AES_Type) GetIER_KEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *AES_Type) SetIER_RWEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *AES_Type) GetIER_RWEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}

// AES.ISR: interrupt status register
func (o *AES_Type) SetISR_RWEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *AES_Type) GetISR_RWEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *AES_Type) SetISR_KEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *AES_Type) GetISR_KEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *AES_Type) SetISR_CCF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetISR_CCF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// AES.ICR: interrupt clear register
func (o *AES_Type) SetICR_CCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *AES_Type) GetICR_CCF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *AES_Type) SetICR_KEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *AES_Type) GetICR_KEIF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *AES_Type) SetICR_RWEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *AES_Type) GetICR_RWEIF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}

// Comparator
type COMP_Type struct {
	COMP1_CSR volatile.Register32 // 0x0
	COMP2_CSR volatile.Register32 // 0x4
}

// COMP.COMP1_CSR: Comparator 1 control and status register
func (o *COMP_Type) SetCOMP1_CSR_COMP1_EN(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x1)|value)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_EN() uint32 {
	return volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x1
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_INMSEL(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0xf0)|value<<4)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_INMSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0xf0) >> 4
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_INPSEL(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x300)|value<<8)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_INPSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x300) >> 8
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_WINMODE(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x800)|value<<11)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_WINMODE() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x800) >> 11
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_WINOUT(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x4000)|value<<14)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_WINOUT() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x4000) >> 14
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_POLARITY(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x8000)|value<<15)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_POLARITY() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x8000) >> 15
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_HYST(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x30000)|value<<16)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_HYST() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x30000) >> 16
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_PWRMODE(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0xc0000)|value<<18)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_PWRMODE() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0xc0000) >> 18
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_BLANKSEL(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x1f00000)|value<<20)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_BLANKSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x1f00000) >> 20
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_VALUE(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_VALUE() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x40000000) >> 30
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_LOCK(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_LOCK() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x80000000) >> 31
}

// COMP.COMP2_CSR: Comparator 2 control and status register
func (o *COMP_Type) SetCOMP2_CSR_COM2_EN(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x1)|value)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_EN() uint32 {
	return volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x1
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_INMSEL(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0xf0)|value<<4)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_INMSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0xf0) >> 4
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_INPSEL(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x300)|value<<8)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_INPSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x300) >> 8
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_WINMODE(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x800)|value<<11)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_WINMODE() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x800) >> 11
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_WINOUT(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x4000)|value<<14)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_WINOUT() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x4000) >> 14
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_POLARITY(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x8000)|value<<15)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_POLARITY() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x8000) >> 15
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_HYST(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x30000)|value<<16)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_HYST() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x30000) >> 16
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_PWRMODE(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0xc0000)|value<<18)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_PWRMODE() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0xc0000) >> 18
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_BLANKSEL(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x1f00000)|value<<20)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_BLANKSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x1f00000) >> 20
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_VALUE(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_VALUE() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x40000000) >> 30
}
func (o *COMP_Type) SetCOMP2_CSR_COM2_LOCK(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *COMP_Type) GetCOMP2_CSR_COM2_LOCK() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x80000000) >> 31
}

// CORDIC Co-processor
type CORDIC_Type struct {
	CSR   volatile.Register32 // 0x0
	WDATA volatile.Register32 // 0x4
	RDATA volatile.Register32 // 0x8
}

// CORDIC.CSR: CORDIC Control Status register
func (o *CORDIC_Type) SetCSR_FUNC(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0xf)|value)
}
func (o *CORDIC_Type) GetCSR_FUNC() uint32 {
	return volatile.LoadUint32(&o.CSR.Reg) & 0xf
}
func (o *CORDIC_Type) SetCSR_PRECISION(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0xf0)|value<<4)
}
func (o *CORDIC_Type) GetCSR_PRECISION() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0xf0) >> 4
}
func (o *CORDIC_Type) SetCSR_SCALE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x700)|value<<8)
}
func (o *CORDIC_Type) GetCSR_SCALE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x700) >> 8
}
func (o *CORDIC_Type) SetCSR_IEN(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10000)|value<<16)
}
func (o *CORDIC_Type) GetCSR_IEN() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10000) >> 16
}
func (o *CORDIC_Type) SetCSR_DMAREN(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20000)|value<<17)
}
func (o *CORDIC_Type) GetCSR_DMAREN() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20000) >> 17
}
func (o *CORDIC_Type) SetCSR_DMAWEN(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40000)|value<<18)
}
func (o *CORDIC_Type) GetCSR_DMAWEN() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40000) >> 18
}
func (o *CORDIC_Type) SetCSR_NRES(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80000)|value<<19)
}
func (o *CORDIC_Type) GetCSR_NRES() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80000) >> 19
}
func (o *CORDIC_Type) SetCSR_NARGS(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x100000)|value<<20)
}
func (o *CORDIC_Type) GetCSR_NARGS() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x100000) >> 20
}
func (o *CORDIC_Type) SetCSR_RESSIZE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x200000)|value<<21)
}
func (o *CORDIC_Type) GetCSR_RESSIZE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x200000) >> 21
}
func (o *CORDIC_Type) SetCSR_ARGSIZE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x400000)|value<<22)
}
func (o *CORDIC_Type) GetCSR_ARGSIZE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x400000) >> 22
}
func (o *CORDIC_Type) SetCSR_RRDY(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *CORDIC_Type) GetCSR_RRDY() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80000000) >> 31
}

// CORDIC.WDATA: FMAC Write Data register
func (o *CORDIC_Type) SetWDATA(value uint32) {
	volatile.StoreUint32(&o.WDATA.Reg, value)
}
func (o *CORDIC_Type) GetWDATA() uint32 {
	return volatile.LoadUint32(&o.WDATA.Reg)
}

// CORDIC.RDATA: FMAC Read Data register
func (o *CORDIC_Type) SetRDATA(value uint32) {
	volatile.StoreUint32(&o.RDATA.Reg, value)
}
func (o *CORDIC_Type) GetRDATA() uint32 {
	return volatile.LoadUint32(&o.RDATA.Reg)
}

// Cyclic redundancy check calculation unit
type CRC_Type struct {
	DR   volatile.Register32 // 0x0
	IDR  volatile.Register32 // 0x4
	CR   volatile.Register32 // 0x8
	_    [4]byte
	INIT volatile.Register32 // 0x10
	POL  volatile.Register32 // 0x14
}

// CRC.DR: Data register
func (o *CRC_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *CRC_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// CRC.IDR: Independent data register
func (o *CRC_Type) SetIDR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, value)
}
func (o *CRC_Type) GetIDR() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg)
}

// CRC.CR: Control register
func (o *CRC_Type) SetCR_REV_OUT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *CRC_Type) GetCR_REV_OUT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *CRC_Type) SetCR_REV_IN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x60)|value<<5)
}
func (o *CRC_Type) GetCR_REV_IN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x60) >> 5
}
func (o *CRC_Type) SetCR_POLYSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x18)|value<<3)
}
func (o *CRC_Type) GetCR_POLYSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x18) >> 3
}
func (o *CRC_Type) SetCR_RESET(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *CRC_Type) GetCR_RESET() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// CRC.INIT: Initial CRC value
func (o *CRC_Type) SetINIT(value uint32) {
	volatile.StoreUint32(&o.INIT.Reg, value)
}
func (o *CRC_Type) GetINIT() uint32 {
	return volatile.LoadUint32(&o.INIT.Reg)
}

// CRC.POL: polynomial
func (o *CRC_Type) SetPOL(value uint32) {
	volatile.StoreUint32(&o.POL.Reg, value)
}
func (o *CRC_Type) GetPOL() uint32 {
	return volatile.LoadUint32(&o.POL.Reg)
}

// Clock recovery system
type CRS_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
	ISR  volatile.Register32 // 0x8
	ICR  volatile.Register32 // 0xC
}

// CRS.CR: control register
func (o *CRS_Type) SetCR_TRIM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7f00)|value<<8)
}
func (o *CRS_Type) GetCR_TRIM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x7f00) >> 8
}
func (o *CRS_Type) SetCR_SWSYNC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *CRS_Type) GetCR_SWSYNC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *CRS_Type) SetCR_AUTOTRIMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *CRS_Type) GetCR_AUTOTRIMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *CRS_Type) SetCR_CEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *CRS_Type) GetCR_CEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *CRS_Type) SetCR_SYNCOKIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *CRS_Type) GetCR_SYNCOKIE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *CRS_Type) SetCR_ESYNCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *CRS_Type) GetCR_ESYNCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *CRS_Type) SetCR_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *CRS_Type) GetCR_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *CRS_Type) SetCR_SYNCWARNIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *CRS_Type) GetCR_SYNCWARNIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}

// CRS.CFGR: configuration register
func (o *CRS_Type) SetCFGR_SYNCPOL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x80000000)|value<<31)
}
func (o *CRS_Type) GetCFGR_SYNCPOL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x80000000) >> 31
}
func (o *CRS_Type) SetCFGR_SYNCSRC(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x30000000)|value<<28)
}
func (o *CRS_Type) GetCFGR_SYNCSRC() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x30000000) >> 28
}
func (o *CRS_Type) SetCFGR_SYNCDIV(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x7000000)|value<<24)
}
func (o *CRS_Type) GetCFGR_SYNCDIV() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x7000000) >> 24
}
func (o *CRS_Type) SetCFGR_FELIM(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xff0000)|value<<16)
}
func (o *CRS_Type) GetCFGR_FELIM() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xff0000) >> 16
}
func (o *CRS_Type) SetCFGR_RELOAD(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xffff)|value)
}
func (o *CRS_Type) GetCFGR_RELOAD() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0xffff
}

// CRS.ISR: interrupt and status register
func (o *CRS_Type) SetISR_FECAP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CRS_Type) GetISR_FECAP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xffff0000) >> 16
}
func (o *CRS_Type) SetISR_FEDIR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *CRS_Type) GetISR_FEDIR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *CRS_Type) SetISR_SYNCOKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *CRS_Type) GetISR_SYNCOKF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *CRS_Type) SetISR_TRIMOVF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *CRS_Type) GetISR_TRIMOVF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *CRS_Type) SetISR_SYNCMISS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *CRS_Type) GetISR_SYNCMISS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *CRS_Type) SetISR_SYNCERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *CRS_Type) GetISR_SYNCERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *CRS_Type) SetISR_ESYNCF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *CRS_Type) GetISR_ESYNCF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *CRS_Type) SetISR_ERRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *CRS_Type) GetISR_ERRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *CRS_Type) SetISR_SYNCWARNF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *CRS_Type) GetISR_SYNCWARNF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}

// CRS.ICR: interrupt flag clear register
func (o *CRS_Type) SetICR_SYNCOKC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *CRS_Type) GetICR_SYNCOKC() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *CRS_Type) SetICR_ESYNCC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *CRS_Type) GetICR_ESYNCC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *CRS_Type) SetICR_ERRC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *CRS_Type) GetICR_ERRC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *CRS_Type) SetICR_SYNCWARNC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *CRS_Type) GetICR_SYNCWARNC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}

// Digital-to-analog converter
type DAC_Type struct {
	CR      volatile.Register32 // 0x0
	SWTRGR  volatile.Register32 // 0x4
	DHR12R1 volatile.Register32 // 0x8
	DHR12L1 volatile.Register32 // 0xC
	DHR8R1  volatile.Register32 // 0x10
	DHR12R2 volatile.Register32 // 0x14
	DHR12L2 volatile.Register32 // 0x18
	DHR8R2  volatile.Register32 // 0x1C
	DHR12RD volatile.Register32 // 0x20
	DHR12LD volatile.Register32 // 0x24
	DHR8RD  volatile.Register32 // 0x28
	DOR1    volatile.Register32 // 0x2C
	DOR2    volatile.Register32 // 0x30
	SR      volatile.Register32 // 0x34
	CCR     volatile.Register32 // 0x38
	MCR     volatile.Register32 // 0x3C
	SHSR1   volatile.Register32 // 0x40
	SHSR2   volatile.Register32 // 0x44
	SHHR    volatile.Register32 // 0x48
	SHRR    volatile.Register32 // 0x4C
	_       [4]byte
	AUTOCR  volatile.Register32 // 0x54
}

// DAC.CR: DAC control register
func (o *DAC_Type) SetCR_EN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *DAC_Type) GetCR_EN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *DAC_Type) SetCR_EN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetCR_EN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 32
}
func (o *DAC_Type) SetCR_TEN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *DAC_Type) GetCR_TEN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *DAC_Type) SetCR_TEN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<33)
}
func (o *DAC_Type) GetCR_TEN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 33
}
func (o *DAC_Type) SetCR_TSEL1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3c)|value<<2)
}
func (o *DAC_Type) GetCR_TSEL1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3c) >> 2
}
func (o *DAC_Type) SetCR_WAVE1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00000)|value<<22)
}
func (o *DAC_Type) GetCR_WAVE1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00000) >> 22
}
func (o *DAC_Type) SetCR_WAVE2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<38)
}
func (o *DAC_Type) GetCR_WAVE2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 38
}
func (o *DAC_Type) SetCR_MAMP1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf000000)|value<<24)
}
func (o *DAC_Type) GetCR_MAMP1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf000000) >> 24
}
func (o *DAC_Type) SetCR_MAMP2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<40)
}
func (o *DAC_Type) GetCR_MAMP2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 40
}
func (o *DAC_Type) SetCR_DMAEN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *DAC_Type) GetCR_DMAEN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *DAC_Type) SetCR_DMAEN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<44)
}
func (o *DAC_Type) GetCR_DMAEN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 44
}
func (o *DAC_Type) SetCR_DMAUDRIE1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *DAC_Type) GetCR_DMAUDRIE1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *DAC_Type) SetCR_DMAUDRIE2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<45)
}
func (o *DAC_Type) GetCR_DMAUDRIE2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 45
}
func (o *DAC_Type) SetCR_CEN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *DAC_Type) GetCR_CEN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *DAC_Type) SetCR_CEN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<46)
}
func (o *DAC_Type) GetCR_CEN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 46
}
func (o *DAC_Type) SetCR_TSEL2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3c0000)|value<<18)
}
func (o *DAC_Type) GetCR_TSEL2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3c0000) >> 18
}

// DAC.SWTRGR: DAC software trigger register
func (o *DAC_Type) SetSWTRGR_SWTRIG1(value uint32) {
	volatile.StoreUint32(&o.SWTRGR.Reg, volatile.LoadUint32(&o.SWTRGR.Reg)&^(0x2)|value<<1)
}
func (o *DAC_Type) GetSWTRGR_SWTRIG1() uint32 {
	return (volatile.LoadUint32(&o.SWTRGR.Reg) & 0x2) >> 1
}
func (o *DAC_Type) SetSWTRGR_SWTRIG2(value uint32) {
	volatile.StoreUint32(&o.SWTRGR.Reg, volatile.LoadUint32(&o.SWTRGR.Reg)&^(0x4)|value<<2)
}
func (o *DAC_Type) GetSWTRGR_SWTRIG2() uint32 {
	return (volatile.LoadUint32(&o.SWTRGR.Reg) & 0x4) >> 2
}

// DAC.DHR12R1: channel%s 12-bit right-aligned data holding register
func (o *DAC_Type) SetDHR12R1_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12R1.Reg, volatile.LoadUint32(&o.DHR12R1.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDHR12R1_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR12R1.Reg) & 0xfff
}
func (o *DAC_Type) SetDHR12R1_DACC1DHRB(value uint32) {
	volatile.StoreUint32(&o.DHR12R1.Reg, volatile.LoadUint32(&o.DHR12R1.Reg)&^(0xfff0000)|value<<16)
}
func (o *DAC_Type) GetDHR12R1_DACC1DHRB() uint32 {
	return (volatile.LoadUint32(&o.DHR12R1.Reg) & 0xfff0000) >> 16
}

// DAC.DHR12L1: channel%s 12-bit left aligned data holding register
func (o *DAC_Type) SetDHR12L1_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12L1.Reg, volatile.LoadUint32(&o.DHR12L1.Reg)&^(0xfff0)|value<<4)
}
func (o *DAC_Type) GetDHR12L1_DACCDHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12L1.Reg) & 0xfff0) >> 4
}
func (o *DAC_Type) SetDHR12L1_DACC1DHRB(value uint32) {
	volatile.StoreUint32(&o.DHR12L1.Reg, volatile.LoadUint32(&o.DHR12L1.Reg)&^(0xfff00000)|value<<20)
}
func (o *DAC_Type) GetDHR12L1_DACC1DHRB() uint32 {
	return (volatile.LoadUint32(&o.DHR12L1.Reg) & 0xfff00000) >> 20
}

// DAC.DHR8R1: channel%s 8-bit right aligned data holding register
func (o *DAC_Type) SetDHR8R1_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR8R1.Reg, volatile.LoadUint32(&o.DHR8R1.Reg)&^(0xff)|value)
}
func (o *DAC_Type) GetDHR8R1_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR8R1.Reg) & 0xff
}
func (o *DAC_Type) SetDHR8R1_DACC1DHRB(value uint32) {
	volatile.StoreUint32(&o.DHR8R1.Reg, volatile.LoadUint32(&o.DHR8R1.Reg)&^(0xff00)|value<<8)
}
func (o *DAC_Type) GetDHR8R1_DACC1DHRB() uint32 {
	return (volatile.LoadUint32(&o.DHR8R1.Reg) & 0xff00) >> 8
}

// DAC.DHR12R2: channel%s 12-bit right-aligned data holding register
func (o *DAC_Type) SetDHR12R2_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12R2.Reg, volatile.LoadUint32(&o.DHR12R2.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDHR12R2_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR12R2.Reg) & 0xfff
}
func (o *DAC_Type) SetDHR12R2_DACC1DHRB(value uint32) {
	volatile.StoreUint32(&o.DHR12R2.Reg, volatile.LoadUint32(&o.DHR12R2.Reg)&^(0xfff0000)|value<<16)
}
func (o *DAC_Type) GetDHR12R2_DACC1DHRB() uint32 {
	return (volatile.LoadUint32(&o.DHR12R2.Reg) & 0xfff0000) >> 16
}

// DAC.DHR12L2: channel%s 12-bit left aligned data holding register
func (o *DAC_Type) SetDHR12L2_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12L2.Reg, volatile.LoadUint32(&o.DHR12L2.Reg)&^(0xfff0)|value<<4)
}
func (o *DAC_Type) GetDHR12L2_DACCDHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12L2.Reg) & 0xfff0) >> 4
}
func (o *DAC_Type) SetDHR12L2_DACC1DHRB(value uint32) {
	volatile.StoreUint32(&o.DHR12L2.Reg, volatile.LoadUint32(&o.DHR12L2.Reg)&^(0xfff00000)|value<<20)
}
func (o *DAC_Type) GetDHR12L2_DACC1DHRB() uint32 {
	return (volatile.LoadUint32(&o.DHR12L2.Reg) & 0xfff00000) >> 20
}

// DAC.DHR8R2: channel%s 8-bit right aligned data holding register
func (o *DAC_Type) SetDHR8R2_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR8R2.Reg, volatile.LoadUint32(&o.DHR8R2.Reg)&^(0xff)|value)
}
func (o *DAC_Type) GetDHR8R2_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR8R2.Reg) & 0xff
}
func (o *DAC_Type) SetDHR8R2_DACC1DHRB(value uint32) {
	volatile.StoreUint32(&o.DHR8R2.Reg, volatile.LoadUint32(&o.DHR8R2.Reg)&^(0xff00)|value<<8)
}
func (o *DAC_Type) GetDHR8R2_DACC1DHRB() uint32 {
	return (volatile.LoadUint32(&o.DHR8R2.Reg) & 0xff00) >> 8
}

// DAC.DHR12RD: Dual DAC 12-bit right-aligned data holding register
func (o *DAC_Type) SetDHR12RD_DACC1DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12RD.Reg, volatile.LoadUint32(&o.DHR12RD.Reg)&^(0xfff0000)|value<<16)
}
func (o *DAC_Type) GetDHR12RD_DACC1DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12RD.Reg) & 0xfff0000) >> 16
}
func (o *DAC_Type) SetDHR12RD_DACC2DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12RD.Reg, volatile.LoadUint32(&o.DHR12RD.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetDHR12RD_DACC2DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12RD.Reg) & 0x0) >> 32
}

// DAC.DHR12LD: DUAL DAC 12-bit left aligned data holding register
func (o *DAC_Type) SetDHR12LD_DACC1DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12LD.Reg, volatile.LoadUint32(&o.DHR12LD.Reg)&^(0xfff00000)|value<<20)
}
func (o *DAC_Type) GetDHR12LD_DACC1DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12LD.Reg) & 0xfff00000) >> 20
}
func (o *DAC_Type) SetDHR12LD_DACC2DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12LD.Reg, volatile.LoadUint32(&o.DHR12LD.Reg)&^(0x0)|value<<36)
}
func (o *DAC_Type) GetDHR12LD_DACC2DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12LD.Reg) & 0x0) >> 36
}

// DAC.DHR8RD: DUAL DAC 8-bit right aligned data holding register
func (o *DAC_Type) SetDHR8RD_DACC1DHR(value uint32) {
	volatile.StoreUint32(&o.DHR8RD.Reg, volatile.LoadUint32(&o.DHR8RD.Reg)&^(0xff00)|value<<8)
}
func (o *DAC_Type) GetDHR8RD_DACC1DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR8RD.Reg) & 0xff00) >> 8
}
func (o *DAC_Type) SetDHR8RD_DACC2DHR(value uint32) {
	volatile.StoreUint32(&o.DHR8RD.Reg, volatile.LoadUint32(&o.DHR8RD.Reg)&^(0xff0000)|value<<16)
}
func (o *DAC_Type) GetDHR8RD_DACC2DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR8RD.Reg) & 0xff0000) >> 16
}

// DAC.DOR1: channel%s data output register
func (o *DAC_Type) SetDOR1_DACCDOR(value uint32) {
	volatile.StoreUint32(&o.DOR1.Reg, volatile.LoadUint32(&o.DOR1.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDOR1_DACCDOR() uint32 {
	return volatile.LoadUint32(&o.DOR1.Reg) & 0xfff
}
func (o *DAC_Type) SetDOR1_DACC1DORB(value uint32) {
	volatile.StoreUint32(&o.DOR1.Reg, volatile.LoadUint32(&o.DOR1.Reg)&^(0xfff0000)|value<<16)
}
func (o *DAC_Type) GetDOR1_DACC1DORB() uint32 {
	return (volatile.LoadUint32(&o.DOR1.Reg) & 0xfff0000) >> 16
}

// DAC.DOR2: channel%s data output register
func (o *DAC_Type) SetDOR2_DACCDOR(value uint32) {
	volatile.StoreUint32(&o.DOR2.Reg, volatile.LoadUint32(&o.DOR2.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDOR2_DACCDOR() uint32 {
	return volatile.LoadUint32(&o.DOR2.Reg) & 0xfff
}
func (o *DAC_Type) SetDOR2_DACC1DORB(value uint32) {
	volatile.StoreUint32(&o.DOR2.Reg, volatile.LoadUint32(&o.DOR2.Reg)&^(0xfff0000)|value<<16)
}
func (o *DAC_Type) GetDOR2_DACC1DORB() uint32 {
	return (volatile.LoadUint32(&o.DOR2.Reg) & 0xfff0000) >> 16
}

// DAC.SR: DAC status register
func (o *DAC_Type) SetSR_DAC1RDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000000)|value<<27)
}
func (o *DAC_Type) GetSR_DAC1RDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000000) >> 27
}
func (o *DAC_Type) SetSR_DAC2RDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<43)
}
func (o *DAC_Type) GetSR_DAC2RDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 43
}
func (o *DAC_Type) SetSR_DORSTAT1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000000)|value<<28)
}
func (o *DAC_Type) GetSR_DORSTAT1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000000) >> 28
}
func (o *DAC_Type) SetSR_DORSTAT2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<44)
}
func (o *DAC_Type) GetSR_DORSTAT2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 44
}
func (o *DAC_Type) SetSR_DMAUDR1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000000)|value<<29)
}
func (o *DAC_Type) GetSR_DMAUDR1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000000) >> 29
}
func (o *DAC_Type) SetSR_DMAUDR2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<45)
}
func (o *DAC_Type) GetSR_DMAUDR2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 45
}
func (o *DAC_Type) SetSR_CAL_FLAG1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000000)|value<<30)
}
func (o *DAC_Type) GetSR_CAL_FLAG1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000000) >> 30
}
func (o *DAC_Type) SetSR_CAL_FLAG2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<46)
}
func (o *DAC_Type) GetSR_CAL_FLAG2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 46
}
func (o *DAC_Type) SetSR_BWST1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000000)|value<<31)
}
func (o *DAC_Type) GetSR_BWST1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000000) >> 31
}
func (o *DAC_Type) SetSR_BWST2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<47)
}
func (o *DAC_Type) GetSR_BWST2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 47
}

// DAC.CCR: DAC calibration control register
func (o *DAC_Type) SetCCR_OTRIM1(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x1f0000)|value<<16)
}
func (o *DAC_Type) GetCCR_OTRIM1() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x1f0000) >> 16
}
func (o *DAC_Type) SetCCR_OTRIM2(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetCCR_OTRIM2() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x0) >> 32
}

// DAC.MCR: DAC mode control register
func (o *DAC_Type) SetMCR_MODE1(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x70000)|value<<16)
}
func (o *DAC_Type) GetMCR_MODE1() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x70000) >> 16
}
func (o *DAC_Type) SetMCR_MODE2(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetMCR_MODE2() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x0) >> 32
}
func (o *DAC_Type) SetMCR_DMADOUBLE1(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x1000000)|value<<24)
}
func (o *DAC_Type) GetMCR_DMADOUBLE1() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x1000000) >> 24
}
func (o *DAC_Type) SetMCR_DMADOUBLE2(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x0)|value<<40)
}
func (o *DAC_Type) GetMCR_DMADOUBLE2() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x0) >> 40
}
func (o *DAC_Type) SetMCR_SINFORMAT1(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x2000000)|value<<25)
}
func (o *DAC_Type) GetMCR_SINFORMAT1() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x2000000) >> 25
}
func (o *DAC_Type) SetMCR_SINFORMAT2(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x0)|value<<41)
}
func (o *DAC_Type) GetMCR_SINFORMAT2() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x0) >> 41
}
func (o *DAC_Type) SetMCR_HFSEL(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0xc000)|value<<14)
}
func (o *DAC_Type) GetMCR_HFSEL() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0xc000) >> 14
}

// DAC.SHSR1: DAC channel%s sample and hold sample time register
func (o *DAC_Type) SetSHSR1_TSAMPLE(value uint32) {
	volatile.StoreUint32(&o.SHSR1.Reg, volatile.LoadUint32(&o.SHSR1.Reg)&^(0x3ff)|value)
}
func (o *DAC_Type) GetSHSR1_TSAMPLE() uint32 {
	return volatile.LoadUint32(&o.SHSR1.Reg) & 0x3ff
}

// DAC.SHSR2: DAC channel%s sample and hold sample time register
func (o *DAC_Type) SetSHSR2_TSAMPLE(value uint32) {
	volatile.StoreUint32(&o.SHSR2.Reg, volatile.LoadUint32(&o.SHSR2.Reg)&^(0x3ff)|value)
}
func (o *DAC_Type) GetSHSR2_TSAMPLE() uint32 {
	return volatile.LoadUint32(&o.SHSR2.Reg) & 0x3ff
}

// DAC.SHHR: DAC Sample and Hold hold time register
func (o *DAC_Type) SetSHHR_THOLD1(value uint32) {
	volatile.StoreUint32(&o.SHHR.Reg, volatile.LoadUint32(&o.SHHR.Reg)&^(0x3ff0000)|value<<16)
}
func (o *DAC_Type) GetSHHR_THOLD1() uint32 {
	return (volatile.LoadUint32(&o.SHHR.Reg) & 0x3ff0000) >> 16
}
func (o *DAC_Type) SetSHHR_THOLD2(value uint32) {
	volatile.StoreUint32(&o.SHHR.Reg, volatile.LoadUint32(&o.SHHR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetSHHR_THOLD2() uint32 {
	return (volatile.LoadUint32(&o.SHHR.Reg) & 0x0) >> 32
}

// DAC.SHRR: DAC Sample and Hold refresh time register
func (o *DAC_Type) SetSHRR_TREFRESH1(value uint32) {
	volatile.StoreUint32(&o.SHRR.Reg, volatile.LoadUint32(&o.SHRR.Reg)&^(0xff0000)|value<<16)
}
func (o *DAC_Type) GetSHRR_TREFRESH1() uint32 {
	return (volatile.LoadUint32(&o.SHRR.Reg) & 0xff0000) >> 16
}
func (o *DAC_Type) SetSHRR_TREFRESH2(value uint32) {
	volatile.StoreUint32(&o.SHRR.Reg, volatile.LoadUint32(&o.SHRR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetSHRR_TREFRESH2() uint32 {
	return (volatile.LoadUint32(&o.SHRR.Reg) & 0x0) >> 32
}

// DAC.AUTOCR: Autonomous mode control register
func (o *DAC_Type) SetAUTOCR_AUTOMODE(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x400000)|value<<22)
}
func (o *DAC_Type) GetAUTOCR_AUTOMODE() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x400000) >> 22
}

// MCU debug component
type DBGMCU_Type struct {
	IDCODE               volatile.Register32 // 0x0
	CR                   volatile.Register32 // 0x4
	APB1LFZR             volatile.Register32 // 0x8
	APB1HFZR             volatile.Register32 // 0xC
	APB2FZR              volatile.Register32 // 0x10
	APB3FZR              volatile.Register32 // 0x14
	_                    [8]byte
	AHB1FZR              volatile.Register32 // 0x20
	_                    [4]byte
	AHB3FZR              volatile.Register32 // 0x28
	_                    [208]byte
	SR                   volatile.Register32 // 0xFC
	DBGMCU_DBG_AUTH_HOST volatile.Register32 // 0x100
	DBG_AUTH_DEVICE      volatile.Register32 // 0x104
	_                    [3784]byte
	PIDR4                volatile.Register32 // 0xFD0
	_                    [12]byte
	PIDR0                volatile.Register32 // 0xFE0
	PIDR1                volatile.Register32 // 0xFE4
	PIDR2                volatile.Register32 // 0xFE8
	PIDR3                volatile.Register32 // 0xFEC
	CIDR0                volatile.Register32 // 0xFF0
	CIDR1                volatile.Register32 // 0xFF4
	CIDR2                volatile.Register32 // 0xFF8
	CIDR3                volatile.Register32 // 0xFFC
}

// DBGMCU.IDCODE: DBGMCU_IDCODE
func (o *DBGMCU_Type) SetIDCODE_DEV_ID(value uint32) {
	volatile.StoreUint32(&o.IDCODE.Reg, volatile.LoadUint32(&o.IDCODE.Reg)&^(0xfff)|value)
}
func (o *DBGMCU_Type) GetIDCODE_DEV_ID() uint32 {
	return volatile.LoadUint32(&o.IDCODE.Reg) & 0xfff
}
func (o *DBGMCU_Type) SetIDCODE_REV_ID(value uint32) {
	volatile.StoreUint32(&o.IDCODE.Reg, volatile.LoadUint32(&o.IDCODE.Reg)&^(0xffff0000)|value<<16)
}
func (o *DBGMCU_Type) GetIDCODE_REV_ID() uint32 {
	return (volatile.LoadUint32(&o.IDCODE.Reg) & 0xffff0000) >> 16
}

// DBGMCU.CR: Debug MCU configuration register
func (o *DBGMCU_Type) SetCR_DBG_STOP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetCR_DBG_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetCR_DBG_STANDBY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DBGMCU_Type) GetCR_DBG_STANDBY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *DBGMCU_Type) SetCR_TRACE_IOEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *DBGMCU_Type) GetCR_TRACE_IOEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *DBGMCU_Type) SetCR_TRACE_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *DBGMCU_Type) GetCR_TRACE_EN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *DBGMCU_Type) SetCR_TRACE_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc0)|value<<6)
}
func (o *DBGMCU_Type) GetCR_TRACE_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc0) >> 6
}

// DBGMCU.APB1LFZR: Debug MCU APB1L peripheral freeze register
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM2_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x1)|value)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM2_STOP() uint32 {
	return volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x1
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM3_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM3_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM4_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x4)|value<<2)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM4_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x4) >> 2
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM5_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x8)|value<<3)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM5_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x8) >> 3
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM6_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x10)|value<<4)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM6_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x10) >> 4
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM7_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x20)|value<<5)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM7_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x20) >> 5
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_WWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x800)|value<<11)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_WWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x800) >> 11
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_IWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x1000)|value<<12)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_IWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x1000) >> 12
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_I2C1_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x200000)|value<<21)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_I2C1_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x200000) >> 21
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_I2C2_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x400000)|value<<22)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_I2C2_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x400000) >> 22
}

// DBGMCU.APB1HFZR: Debug MCU APB1H peripheral freeze register
func (o *DBGMCU_Type) SetAPB1HFZR_DBG_I2C4_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1HFZR.Reg, volatile.LoadUint32(&o.APB1HFZR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetAPB1HFZR_DBG_I2C4_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1HFZR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetAPB1HFZR_DBG_LPTIM2_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1HFZR.Reg, volatile.LoadUint32(&o.APB1HFZR.Reg)&^(0x20)|value<<5)
}
func (o *DBGMCU_Type) GetAPB1HFZR_DBG_LPTIM2_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1HFZR.Reg) & 0x20) >> 5
}

// DBGMCU.APB2FZR: Debug MCU APB2 peripheral freeze register
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM1_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x800)|value<<11)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM1_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x800) >> 11
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM8_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x2000)|value<<13)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM8_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x2000) >> 13
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM15_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x10000)|value<<16)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM15_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x10000) >> 16
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM16_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x20000)|value<<17)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM16_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x20000) >> 17
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM17_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x40000)|value<<18)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM17_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x40000) >> 18
}

// DBGMCU.APB3FZR: Debug MCU APB3 peripheral freeze register
func (o *DBGMCU_Type) SetAPB3FZR_DBG_I2C3_STOP(value uint32) {
	volatile.StoreUint32(&o.APB3FZR.Reg, volatile.LoadUint32(&o.APB3FZR.Reg)&^(0x400)|value<<10)
}
func (o *DBGMCU_Type) GetAPB3FZR_DBG_I2C3_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB3FZR.Reg) & 0x400) >> 10
}
func (o *DBGMCU_Type) SetAPB3FZR_DBG_LPTIM1_STOP(value uint32) {
	volatile.StoreUint32(&o.APB3FZR.Reg, volatile.LoadUint32(&o.APB3FZR.Reg)&^(0x20000)|value<<17)
}
func (o *DBGMCU_Type) GetAPB3FZR_DBG_LPTIM1_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB3FZR.Reg) & 0x20000) >> 17
}
func (o *DBGMCU_Type) SetAPB3FZR_DBG_LPTIM3_STOP(value uint32) {
	volatile.StoreUint32(&o.APB3FZR.Reg, volatile.LoadUint32(&o.APB3FZR.Reg)&^(0x40000)|value<<18)
}
func (o *DBGMCU_Type) GetAPB3FZR_DBG_LPTIM3_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB3FZR.Reg) & 0x40000) >> 18
}
func (o *DBGMCU_Type) SetAPB3FZR_DBG_LPTIM4_STOP(value uint32) {
	volatile.StoreUint32(&o.APB3FZR.Reg, volatile.LoadUint32(&o.APB3FZR.Reg)&^(0x80000)|value<<19)
}
func (o *DBGMCU_Type) GetAPB3FZR_DBG_LPTIM4_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB3FZR.Reg) & 0x80000) >> 19
}
func (o *DBGMCU_Type) SetAPB3FZR_DBG_RTC_STOP(value uint32) {
	volatile.StoreUint32(&o.APB3FZR.Reg, volatile.LoadUint32(&o.APB3FZR.Reg)&^(0x40000000)|value<<30)
}
func (o *DBGMCU_Type) GetAPB3FZR_DBG_RTC_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB3FZR.Reg) & 0x40000000) >> 30
}

// DBGMCU.AHB1FZR: Debug MCU AHB1 peripheral freeze register
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA0_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x1)|value)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA0_STOP() uint32 {
	return volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x1
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA1_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA1_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA2_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x4)|value<<2)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA2_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x4) >> 2
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA3_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x8)|value<<3)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA3_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x8) >> 3
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA4_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x10)|value<<4)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA4_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x10) >> 4
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA5_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x20)|value<<5)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA5_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x20) >> 5
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA6_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x40)|value<<6)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA6_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x40) >> 6
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA7_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x80)|value<<7)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA7_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x80) >> 7
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA8_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x100)|value<<8)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA8_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x100) >> 8
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA9_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x200)|value<<9)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA9_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x200) >> 9
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA10_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x400)|value<<10)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA10_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x400) >> 10
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA11_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x800)|value<<11)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA11_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x800) >> 11
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA12_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x1000)|value<<12)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA12_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x1000) >> 12
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA13_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x2000)|value<<13)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA13_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x2000) >> 13
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA14_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x4000)|value<<14)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA14_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x4000) >> 14
}
func (o *DBGMCU_Type) SetAHB1FZR_DBG_GPDMA15_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB1FZR.Reg, volatile.LoadUint32(&o.AHB1FZR.Reg)&^(0x8000)|value<<15)
}
func (o *DBGMCU_Type) GetAHB1FZR_DBG_GPDMA15_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB1FZR.Reg) & 0x8000) >> 15
}

// DBGMCU.AHB3FZR: Debug MCU AHB3 peripheral freeze register
func (o *DBGMCU_Type) SetAHB3FZR_DBG_LPDMA0_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB3FZR.Reg, volatile.LoadUint32(&o.AHB3FZR.Reg)&^(0x1)|value)
}
func (o *DBGMCU_Type) GetAHB3FZR_DBG_LPDMA0_STOP() uint32 {
	return volatile.LoadUint32(&o.AHB3FZR.Reg) & 0x1
}
func (o *DBGMCU_Type) SetAHB3FZR_DBG_LPDMA1_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB3FZR.Reg, volatile.LoadUint32(&o.AHB3FZR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetAHB3FZR_DBG_LPDMA1_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB3FZR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetAHB3FZR_DBG_LPDMA2_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB3FZR.Reg, volatile.LoadUint32(&o.AHB3FZR.Reg)&^(0x4)|value<<2)
}
func (o *DBGMCU_Type) GetAHB3FZR_DBG_LPDMA2_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB3FZR.Reg) & 0x4) >> 2
}
func (o *DBGMCU_Type) SetAHB3FZR_DBG_LPDMA3_STOP(value uint32) {
	volatile.StoreUint32(&o.AHB3FZR.Reg, volatile.LoadUint32(&o.AHB3FZR.Reg)&^(0x8)|value<<3)
}
func (o *DBGMCU_Type) GetAHB3FZR_DBG_LPDMA3_STOP() uint32 {
	return (volatile.LoadUint32(&o.AHB3FZR.Reg) & 0x8) >> 3
}

// DBGMCU.SR: DBGMCU status register
func (o *DBGMCU_Type) SetSR_AP_PRESENT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xff)|value)
}
func (o *DBGMCU_Type) GetSR_AP_PRESENT() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0xff
}
func (o *DBGMCU_Type) SetSR_AP_LOCKED(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xff00)|value<<8)
}
func (o *DBGMCU_Type) GetSR_AP_LOCKED() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0xff00) >> 8
}

// DBGMCU.DBGMCU_DBG_AUTH_HOST: DBGMCU debug host authentication register
func (o *DBGMCU_Type) SetDBGMCU_DBG_AUTH_HOST(value uint32) {
	volatile.StoreUint32(&o.DBGMCU_DBG_AUTH_HOST.Reg, value)
}
func (o *DBGMCU_Type) GetDBGMCU_DBG_AUTH_HOST() uint32 {
	return volatile.LoadUint32(&o.DBGMCU_DBG_AUTH_HOST.Reg)
}

// DBGMCU.DBG_AUTH_DEVICE: DBGMCU debug device authentication register
func (o *DBGMCU_Type) SetDBG_AUTH_DEVICE_AUTH_ID(value uint32) {
	volatile.StoreUint32(&o.DBG_AUTH_DEVICE.Reg, volatile.LoadUint32(&o.DBG_AUTH_DEVICE.Reg)&^(0xffff)|value)
}
func (o *DBGMCU_Type) GetDBG_AUTH_DEVICE_AUTH_ID() uint32 {
	return volatile.LoadUint32(&o.DBG_AUTH_DEVICE.Reg) & 0xffff
}

// DBGMCU.PIDR4: Debug MCU CoreSight peripheral identity register 4
func (o *DBGMCU_Type) SetPIDR4_JEP106CON(value uint32) {
	volatile.StoreUint32(&o.PIDR4.Reg, volatile.LoadUint32(&o.PIDR4.Reg)&^(0xf)|value)
}
func (o *DBGMCU_Type) GetPIDR4_JEP106CON() uint32 {
	return volatile.LoadUint32(&o.PIDR4.Reg) & 0xf
}
func (o *DBGMCU_Type) SetPIDR4_KCOUNT_4(value uint32) {
	volatile.StoreUint32(&o.PIDR4.Reg, volatile.LoadUint32(&o.PIDR4.Reg)&^(0xf0)|value<<4)
}
func (o *DBGMCU_Type) GetPIDR4_KCOUNT_4() uint32 {
	return (volatile.LoadUint32(&o.PIDR4.Reg) & 0xf0) >> 4
}

// DBGMCU.PIDR0: Debug MCU CoreSight peripheral identity register 0
func (o *DBGMCU_Type) SetPIDR0_PARTNUM(value uint32) {
	volatile.StoreUint32(&o.PIDR0.Reg, volatile.LoadUint32(&o.PIDR0.Reg)&^(0xff)|value)
}
func (o *DBGMCU_Type) GetPIDR0_PARTNUM() uint32 {
	return volatile.LoadUint32(&o.PIDR0.Reg) & 0xff
}

// DBGMCU.PIDR1: Debug MCU CoreSight peripheral identity register 1
func (o *DBGMCU_Type) SetPIDR1_PARTNUM(value uint32) {
	volatile.StoreUint32(&o.PIDR1.Reg, volatile.LoadUint32(&o.PIDR1.Reg)&^(0xf)|value)
}
func (o *DBGMCU_Type) GetPIDR1_PARTNUM() uint32 {
	return volatile.LoadUint32(&o.PIDR1.Reg) & 0xf
}
func (o *DBGMCU_Type) SetPIDR1_JEP106ID(value uint32) {
	volatile.StoreUint32(&o.PIDR1.Reg, volatile.LoadUint32(&o.PIDR1.Reg)&^(0xf0)|value<<4)
}
func (o *DBGMCU_Type) GetPIDR1_JEP106ID() uint32 {
	return (volatile.LoadUint32(&o.PIDR1.Reg) & 0xf0) >> 4
}

// DBGMCU.PIDR2: Debug MCU CoreSight peripheral identity register 2
func (o *DBGMCU_Type) SetPIDR2_JEP106ID(value uint32) {
	volatile.StoreUint32(&o.PIDR2.Reg, volatile.LoadUint32(&o.PIDR2.Reg)&^(0x7)|value)
}
func (o *DBGMCU_Type) GetPIDR2_JEP106ID() uint32 {
	return volatile.LoadUint32(&o.PIDR2.Reg) & 0x7
}
func (o *DBGMCU_Type) SetPIDR2_JEDEC(value uint32) {
	volatile.StoreUint32(&o.PIDR2.Reg, volatile.LoadUint32(&o.PIDR2.Reg)&^(0x8)|value<<3)
}
func (o *DBGMCU_Type) GetPIDR2_JEDEC() uint32 {
	return (volatile.LoadUint32(&o.PIDR2.Reg) & 0x8) >> 3
}
func (o *DBGMCU_Type) SetPIDR2_REVISION(value uint32) {
	volatile.StoreUint32(&o.PIDR2.Reg, volatile.LoadUint32(&o.PIDR2.Reg)&^(0xf0)|value<<4)
}
func (o *DBGMCU_Type) GetPIDR2_REVISION() uint32 {
	return (volatile.LoadUint32(&o.PIDR2.Reg) & 0xf0) >> 4
}

// DBGMCU.PIDR3: Debug MCU CoreSight peripheral identity register 3
func (o *DBGMCU_Type) SetPIDR3_CMOD(value uint32) {
	volatile.StoreUint32(&o.PIDR3.Reg, volatile.LoadUint32(&o.PIDR3.Reg)&^(0xf)|value)
}
func (o *DBGMCU_Type) GetPIDR3_CMOD() uint32 {
	return volatile.LoadUint32(&o.PIDR3.Reg) & 0xf
}
func (o *DBGMCU_Type) SetPIDR3_REVAND(value uint32) {
	volatile.StoreUint32(&o.PIDR3.Reg, volatile.LoadUint32(&o.PIDR3.Reg)&^(0xf0)|value<<4)
}
func (o *DBGMCU_Type) GetPIDR3_REVAND() uint32 {
	return (volatile.LoadUint32(&o.PIDR3.Reg) & 0xf0) >> 4
}

// DBGMCU.CIDR0: Debug MCU CoreSight component identity register 0
func (o *DBGMCU_Type) SetCIDR0_PREAMBLE(value uint32) {
	volatile.StoreUint32(&o.CIDR0.Reg, volatile.LoadUint32(&o.CIDR0.Reg)&^(0xff)|value)
}
func (o *DBGMCU_Type) GetCIDR0_PREAMBLE() uint32 {
	return volatile.LoadUint32(&o.CIDR0.Reg) & 0xff
}

// DBGMCU.CIDR1: Debug MCU CoreSight component identity register 1
func (o *DBGMCU_Type) SetCIDR1_PREAMBLE(value uint32) {
	volatile.StoreUint32(&o.CIDR1.Reg, volatile.LoadUint32(&o.CIDR1.Reg)&^(0xf)|value)
}
func (o *DBGMCU_Type) GetCIDR1_PREAMBLE() uint32 {
	return volatile.LoadUint32(&o.CIDR1.Reg) & 0xf
}
func (o *DBGMCU_Type) SetCIDR1_CLASS(value uint32) {
	volatile.StoreUint32(&o.CIDR1.Reg, volatile.LoadUint32(&o.CIDR1.Reg)&^(0xf0)|value<<4)
}
func (o *DBGMCU_Type) GetCIDR1_CLASS() uint32 {
	return (volatile.LoadUint32(&o.CIDR1.Reg) & 0xf0) >> 4
}

// DBGMCU.CIDR2: Debug MCU CoreSight component identity register 2
func (o *DBGMCU_Type) SetCIDR2_PREAMBLE(value uint32) {
	volatile.StoreUint32(&o.CIDR2.Reg, volatile.LoadUint32(&o.CIDR2.Reg)&^(0xff)|value)
}
func (o *DBGMCU_Type) GetCIDR2_PREAMBLE() uint32 {
	return volatile.LoadUint32(&o.CIDR2.Reg) & 0xff
}

// DBGMCU.CIDR3: Debug MCU CoreSight component identity register 3
func (o *DBGMCU_Type) SetCIDR3_PREAMBLE(value uint32) {
	volatile.StoreUint32(&o.CIDR3.Reg, volatile.LoadUint32(&o.CIDR3.Reg)&^(0xff)|value)
}
func (o *DBGMCU_Type) GetCIDR3_PREAMBLE() uint32 {
	return volatile.LoadUint32(&o.CIDR3.Reg) & 0xff
}

// DCACHE1
type DCACHE_Type struct {
	CR         volatile.Register32 // 0x0
	SR         volatile.Register32 // 0x4
	IER        volatile.Register32 // 0x8
	FCR        volatile.Register32 // 0xC
	RHMONR     volatile.Register32 // 0x10
	RMMONR     volatile.Register32 // 0x14
	_          [8]byte
	WHMONR     volatile.Register32 // 0x20
	WMMONR     volatile.Register32 // 0x24
	CMDRSADDRR volatile.Register32 // 0x28
	CMDREADDRR volatile.Register32 // 0x2C
}

// DCACHE.CR: DCACHE control register
func (o *DCACHE_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DCACHE_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *DCACHE_Type) SetCR_CACHEINV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DCACHE_Type) GetCR_CACHEINV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DCACHE_Type) SetCR_CACHECMD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x700)|value<<8)
}
func (o *DCACHE_Type) GetCR_CACHECMD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x700) >> 8
}
func (o *DCACHE_Type) SetCR_STARTCMD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *DCACHE_Type) GetCR_STARTCMD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *DCACHE_Type) SetCR_RHITMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *DCACHE_Type) GetCR_RHITMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *DCACHE_Type) SetCR_RMISSMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *DCACHE_Type) GetCR_RMISSMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *DCACHE_Type) SetCR_RHITMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *DCACHE_Type) GetCR_RHITMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *DCACHE_Type) SetCR_RMISSMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *DCACHE_Type) GetCR_RMISSMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *DCACHE_Type) SetCR_WHITMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *DCACHE_Type) GetCR_WHITMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *DCACHE_Type) SetCR_WMISSMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200000)|value<<21)
}
func (o *DCACHE_Type) GetCR_WMISSMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200000) >> 21
}
func (o *DCACHE_Type) SetCR_WHITMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400000)|value<<22)
}
func (o *DCACHE_Type) GetCR_WHITMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400000) >> 22
}
func (o *DCACHE_Type) SetCR_WMISSMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800000)|value<<23)
}
func (o *DCACHE_Type) GetCR_WMISSMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800000) >> 23
}
func (o *DCACHE_Type) SetCR_HBURST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *DCACHE_Type) GetCR_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// DCACHE.SR: DCACHE status register
func (o *DCACHE_Type) SetSR_BUSYF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *DCACHE_Type) GetSR_BUSYF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *DCACHE_Type) SetSR_BSYENDF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *DCACHE_Type) GetSR_BSYENDF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *DCACHE_Type) SetSR_ERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *DCACHE_Type) GetSR_ERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *DCACHE_Type) SetSR_BUSYCMDF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *DCACHE_Type) GetSR_BUSYCMDF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *DCACHE_Type) SetSR_CMDENDF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *DCACHE_Type) GetSR_CMDENDF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}

// DCACHE.IER: DCACHE interrupt enable register
func (o *DCACHE_Type) SetIER_BSYENDIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *DCACHE_Type) GetIER_BSYENDIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *DCACHE_Type) SetIER_ERRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *DCACHE_Type) GetIER_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *DCACHE_Type) SetIER_CMDENDIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *DCACHE_Type) GetIER_CMDENDIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}

// DCACHE.FCR: DCACHE flag clear register
func (o *DCACHE_Type) SetFCR_CBSYENDF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x2)|value<<1)
}
func (o *DCACHE_Type) GetFCR_CBSYENDF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x2) >> 1
}
func (o *DCACHE_Type) SetFCR_CERRF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x4)|value<<2)
}
func (o *DCACHE_Type) GetFCR_CERRF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x4) >> 2
}
func (o *DCACHE_Type) SetFCR_CCMDENDF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x10)|value<<4)
}
func (o *DCACHE_Type) GetFCR_CCMDENDF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x10) >> 4
}

// DCACHE.RHMONR: DCACHE read-hit monitor register
func (o *DCACHE_Type) SetRHMONR(value uint32) {
	volatile.StoreUint32(&o.RHMONR.Reg, value)
}
func (o *DCACHE_Type) GetRHMONR() uint32 {
	return volatile.LoadUint32(&o.RHMONR.Reg)
}

// DCACHE.RMMONR: DCACHE read-miss monitor register
func (o *DCACHE_Type) SetRMMONR_MRISSMON(value uint32) {
	volatile.StoreUint32(&o.RMMONR.Reg, volatile.LoadUint32(&o.RMMONR.Reg)&^(0xffff)|value)
}
func (o *DCACHE_Type) GetRMMONR_MRISSMON() uint32 {
	return volatile.LoadUint32(&o.RMMONR.Reg) & 0xffff
}

// DCACHE.WHMONR: write-hit monitor register
func (o *DCACHE_Type) SetWHMONR(value uint32) {
	volatile.StoreUint32(&o.WHMONR.Reg, value)
}
func (o *DCACHE_Type) GetWHMONR() uint32 {
	return volatile.LoadUint32(&o.WHMONR.Reg)
}

// DCACHE.WMMONR: write-miss monitor register
func (o *DCACHE_Type) SetWMMONR_WMISSMON(value uint32) {
	volatile.StoreUint32(&o.WMMONR.Reg, volatile.LoadUint32(&o.WMMONR.Reg)&^(0xffff)|value)
}
func (o *DCACHE_Type) GetWMMONR_WMISSMON() uint32 {
	return volatile.LoadUint32(&o.WMMONR.Reg) & 0xffff
}

// DCACHE.CMDRSADDRR: command range start address register
func (o *DCACHE_Type) SetCMDRSADDRR_CMDSTARTADDR(value uint32) {
	volatile.StoreUint32(&o.CMDRSADDRR.Reg, volatile.LoadUint32(&o.CMDRSADDRR.Reg)&^(0xfffffff0)|value<<4)
}
func (o *DCACHE_Type) GetCMDRSADDRR_CMDSTARTADDR() uint32 {
	return (volatile.LoadUint32(&o.CMDRSADDRR.Reg) & 0xfffffff0) >> 4
}

// DCACHE.CMDREADDRR: command range start address register
func (o *DCACHE_Type) SetCMDREADDRR_CMDENDADDR(value uint32) {
	volatile.StoreUint32(&o.CMDREADDRR.Reg, volatile.LoadUint32(&o.CMDREADDRR.Reg)&^(0xfffffff0)|value<<4)
}
func (o *DCACHE_Type) GetCMDREADDRR_CMDENDADDR() uint32 {
	return (volatile.LoadUint32(&o.CMDREADDRR.Reg) & 0xfffffff0) >> 4
}

// Digital camera interface
type DCMI_Type struct {
	CR     volatile.Register32 // 0x0
	SR     volatile.Register32 // 0x4
	RIS    volatile.Register32 // 0x8
	IER    volatile.Register32 // 0xC
	MIS    volatile.Register32 // 0x10
	ICR    volatile.Register32 // 0x14
	ESCR   volatile.Register32 // 0x18
	ESUR   volatile.Register32 // 0x1C
	CWSTRT volatile.Register32 // 0x20
	CWSIZE volatile.Register32 // 0x24
	DR     volatile.Register32 // 0x28
}

// DCMI.CR: control register
func (o *DCMI_Type) SetCR_OELS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *DCMI_Type) GetCR_OELS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *DCMI_Type) SetCR_LSM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *DCMI_Type) GetCR_LSM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *DCMI_Type) SetCR_OEBS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *DCMI_Type) GetCR_OEBS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *DCMI_Type) SetCR_BSM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x30000)|value<<16)
}
func (o *DCMI_Type) GetCR_BSM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x30000) >> 16
}
func (o *DCMI_Type) SetCR_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *DCMI_Type) GetCR_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *DCMI_Type) SetCR_EDM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00)|value<<10)
}
func (o *DCMI_Type) GetCR_EDM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00) >> 10
}
func (o *DCMI_Type) SetCR_FCRC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x300)|value<<8)
}
func (o *DCMI_Type) GetCR_FCRC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x300) >> 8
}
func (o *DCMI_Type) SetCR_VSPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *DCMI_Type) GetCR_VSPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *DCMI_Type) SetCR_HSPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *DCMI_Type) GetCR_HSPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *DCMI_Type) SetCR_PCKPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *DCMI_Type) GetCR_PCKPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *DCMI_Type) SetCR_ESS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *DCMI_Type) GetCR_ESS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *DCMI_Type) SetCR_JPEG(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *DCMI_Type) GetCR_JPEG() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *DCMI_Type) SetCR_CROP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DCMI_Type) GetCR_CROP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *DCMI_Type) SetCR_CM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DCMI_Type) GetCR_CM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DCMI_Type) SetCR_CAPTURE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DCMI_Type) GetCR_CAPTURE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// DCMI.SR: status register
func (o *DCMI_Type) SetSR_FNE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *DCMI_Type) GetSR_FNE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *DCMI_Type) SetSR_VSYNC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *DCMI_Type) GetSR_VSYNC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *DCMI_Type) SetSR_HSYNC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *DCMI_Type) GetSR_HSYNC() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// DCMI.RIS: raw interrupt status register
func (o *DCMI_Type) SetRIS_LINE_RIS(value uint32) {
	volatile.StoreUint32(&o.RIS.Reg, volatile.LoadUint32(&o.RIS.Reg)&^(0x10)|value<<4)
}
func (o *DCMI_Type) GetRIS_LINE_RIS() uint32 {
	return (volatile.LoadUint32(&o.RIS.Reg) & 0x10) >> 4
}
func (o *DCMI_Type) SetRIS_VSYNC_RIS(value uint32) {
	volatile.StoreUint32(&o.RIS.Reg, volatile.LoadUint32(&o.RIS.Reg)&^(0x8)|value<<3)
}
func (o *DCMI_Type) GetRIS_VSYNC_RIS() uint32 {
	return (volatile.LoadUint32(&o.RIS.Reg) & 0x8) >> 3
}
func (o *DCMI_Type) SetRIS_ERR_RIS(value uint32) {
	volatile.StoreUint32(&o.RIS.Reg, volatile.LoadUint32(&o.RIS.Reg)&^(0x4)|value<<2)
}
func (o *DCMI_Type) GetRIS_ERR_RIS() uint32 {
	return (volatile.LoadUint32(&o.RIS.Reg) & 0x4) >> 2
}
func (o *DCMI_Type) SetRIS_OVR_RIS(value uint32) {
	volatile.StoreUint32(&o.RIS.Reg, volatile.LoadUint32(&o.RIS.Reg)&^(0x2)|value<<1)
}
func (o *DCMI_Type) GetRIS_OVR_RIS() uint32 {
	return (volatile.LoadUint32(&o.RIS.Reg) & 0x2) >> 1
}
func (o *DCMI_Type) SetRIS_FRAME_RIS(value uint32) {
	volatile.StoreUint32(&o.RIS.Reg, volatile.LoadUint32(&o.RIS.Reg)&^(0x1)|value)
}
func (o *DCMI_Type) GetRIS_FRAME_RIS() uint32 {
	return volatile.LoadUint32(&o.RIS.Reg) & 0x1
}

// DCMI.IER: interrupt enable register
func (o *DCMI_Type) SetIER_LINE_IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *DCMI_Type) GetIER_LINE_IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *DCMI_Type) SetIER_VSYNC_IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *DCMI_Type) GetIER_VSYNC_IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *DCMI_Type) SetIER_ERR_IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *DCMI_Type) GetIER_ERR_IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *DCMI_Type) SetIER_OVR_IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *DCMI_Type) GetIER_OVR_IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *DCMI_Type) SetIER_FRAME_IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *DCMI_Type) GetIER_FRAME_IE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}

// DCMI.MIS: masked interrupt status register
func (o *DCMI_Type) SetMIS_LINE_MIS(value uint32) {
	volatile.StoreUint32(&o.MIS.Reg, volatile.LoadUint32(&o.MIS.Reg)&^(0x10)|value<<4)
}
func (o *DCMI_Type) GetMIS_LINE_MIS() uint32 {
	return (volatile.LoadUint32(&o.MIS.Reg) & 0x10) >> 4
}
func (o *DCMI_Type) SetMIS_VSYNC_MIS(value uint32) {
	volatile.StoreUint32(&o.MIS.Reg, volatile.LoadUint32(&o.MIS.Reg)&^(0x8)|value<<3)
}
func (o *DCMI_Type) GetMIS_VSYNC_MIS() uint32 {
	return (volatile.LoadUint32(&o.MIS.Reg) & 0x8) >> 3
}
func (o *DCMI_Type) SetMIS_ERR_MIS(value uint32) {
	volatile.StoreUint32(&o.MIS.Reg, volatile.LoadUint32(&o.MIS.Reg)&^(0x4)|value<<2)
}
func (o *DCMI_Type) GetMIS_ERR_MIS() uint32 {
	return (volatile.LoadUint32(&o.MIS.Reg) & 0x4) >> 2
}
func (o *DCMI_Type) SetMIS_OVR_MIS(value uint32) {
	volatile.StoreUint32(&o.MIS.Reg, volatile.LoadUint32(&o.MIS.Reg)&^(0x2)|value<<1)
}
func (o *DCMI_Type) GetMIS_OVR_MIS() uint32 {
	return (volatile.LoadUint32(&o.MIS.Reg) & 0x2) >> 1
}
func (o *DCMI_Type) SetMIS_FRAME_MIS(value uint32) {
	volatile.StoreUint32(&o.MIS.Reg, volatile.LoadUint32(&o.MIS.Reg)&^(0x1)|value)
}
func (o *DCMI_Type) GetMIS_FRAME_MIS() uint32 {
	return volatile.LoadUint32(&o.MIS.Reg) & 0x1
}

// DCMI.ICR: interrupt clear register
func (o *DCMI_Type) SetICR_LINE_ISC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *DCMI_Type) GetICR_LINE_ISC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *DCMI_Type) SetICR_VSYNC_ISC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *DCMI_Type) GetICR_VSYNC_ISC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *DCMI_Type) SetICR_ERR_ISC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *DCMI_Type) GetICR_ERR_ISC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *DCMI_Type) SetICR_OVR_ISC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *DCMI_Type) GetICR_OVR_ISC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *DCMI_Type) SetICR_FRAME_ISC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *DCMI_Type) GetICR_FRAME_ISC() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}

// DCMI.ESCR: background offset register
func (o *DCMI_Type) SetESCR_FEC(value uint32) {
	volatile.StoreUint32(&o.ESCR.Reg, volatile.LoadUint32(&o.ESCR.Reg)&^(0xff000000)|value<<24)
}
func (o *DCMI_Type) GetESCR_FEC() uint32 {
	return (volatile.LoadUint32(&o.ESCR.Reg) & 0xff000000) >> 24
}
func (o *DCMI_Type) SetESCR_LEC(value uint32) {
	volatile.StoreUint32(&o.ESCR.Reg, volatile.LoadUint32(&o.ESCR.Reg)&^(0xff0000)|value<<16)
}
func (o *DCMI_Type) GetESCR_LEC() uint32 {
	return (volatile.LoadUint32(&o.ESCR.Reg) & 0xff0000) >> 16
}
func (o *DCMI_Type) SetESCR_LSC(value uint32) {
	volatile.StoreUint32(&o.ESCR.Reg, volatile.LoadUint32(&o.ESCR.Reg)&^(0xff00)|value<<8)
}
func (o *DCMI_Type) GetESCR_LSC() uint32 {
	return (volatile.LoadUint32(&o.ESCR.Reg) & 0xff00) >> 8
}
func (o *DCMI_Type) SetESCR_FSC(value uint32) {
	volatile.StoreUint32(&o.ESCR.Reg, volatile.LoadUint32(&o.ESCR.Reg)&^(0xff)|value)
}
func (o *DCMI_Type) GetESCR_FSC() uint32 {
	return volatile.LoadUint32(&o.ESCR.Reg) & 0xff
}

// DCMI.ESUR: embedded synchronization unmask register
func (o *DCMI_Type) SetESUR_FEU(value uint32) {
	volatile.StoreUint32(&o.ESUR.Reg, volatile.LoadUint32(&o.ESUR.Reg)&^(0xff000000)|value<<24)
}
func (o *DCMI_Type) GetESUR_FEU() uint32 {
	return (volatile.LoadUint32(&o.ESUR.Reg) & 0xff000000) >> 24
}
func (o *DCMI_Type) SetESUR_LEU(value uint32) {
	volatile.StoreUint32(&o.ESUR.Reg, volatile.LoadUint32(&o.ESUR.Reg)&^(0xff0000)|value<<16)
}
func (o *DCMI_Type) GetESUR_LEU() uint32 {
	return (volatile.LoadUint32(&o.ESUR.Reg) & 0xff0000) >> 16
}
func (o *DCMI_Type) SetESUR_LSU(value uint32) {
	volatile.StoreUint32(&o.ESUR.Reg, volatile.LoadUint32(&o.ESUR.Reg)&^(0xff00)|value<<8)
}
func (o *DCMI_Type) GetESUR_LSU() uint32 {
	return (volatile.LoadUint32(&o.ESUR.Reg) & 0xff00) >> 8
}
func (o *DCMI_Type) SetESUR_FSU(value uint32) {
	volatile.StoreUint32(&o.ESUR.Reg, volatile.LoadUint32(&o.ESUR.Reg)&^(0xff)|value)
}
func (o *DCMI_Type) GetESUR_FSU() uint32 {
	return volatile.LoadUint32(&o.ESUR.Reg) & 0xff
}

// DCMI.CWSTRT: crop window start
func (o *DCMI_Type) SetCWSTRT_VST(value uint32) {
	volatile.StoreUint32(&o.CWSTRT.Reg, volatile.LoadUint32(&o.CWSTRT.Reg)&^(0x1fff0000)|value<<16)
}
func (o *DCMI_Type) GetCWSTRT_VST() uint32 {
	return (volatile.LoadUint32(&o.CWSTRT.Reg) & 0x1fff0000) >> 16
}
func (o *DCMI_Type) SetCWSTRT_HOFFCNT(value uint32) {
	volatile.StoreUint32(&o.CWSTRT.Reg, volatile.LoadUint32(&o.CWSTRT.Reg)&^(0x3fff)|value)
}
func (o *DCMI_Type) GetCWSTRT_HOFFCNT() uint32 {
	return volatile.LoadUint32(&o.CWSTRT.Reg) & 0x3fff
}

// DCMI.CWSIZE: crop window size
func (o *DCMI_Type) SetCWSIZE_VLINE(value uint32) {
	volatile.StoreUint32(&o.CWSIZE.Reg, volatile.LoadUint32(&o.CWSIZE.Reg)&^(0x3fff0000)|value<<16)
}
func (o *DCMI_Type) GetCWSIZE_VLINE() uint32 {
	return (volatile.LoadUint32(&o.CWSIZE.Reg) & 0x3fff0000) >> 16
}
func (o *DCMI_Type) SetCWSIZE_CAPCNT(value uint32) {
	volatile.StoreUint32(&o.CWSIZE.Reg, volatile.LoadUint32(&o.CWSIZE.Reg)&^(0x3fff)|value)
}
func (o *DCMI_Type) GetCWSIZE_CAPCNT() uint32 {
	return volatile.LoadUint32(&o.CWSIZE.Reg) & 0x3fff
}

// DCMI.DR: data register
func (o *DCMI_Type) SetDR_BYTE0(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xff00)|value<<8)
}
func (o *DCMI_Type) GetDR_BYTE0() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xff00) >> 8
}
func (o *DCMI_Type) SetDR_BYTE1(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xff0000)|value<<16)
}
func (o *DCMI_Type) GetDR_BYTE1() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xff0000) >> 16
}
func (o *DCMI_Type) SetDR_BYTE2(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xff000000)|value<<24)
}
func (o *DCMI_Type) GetDR_BYTE2() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xff000000) >> 24
}
func (o *DCMI_Type) SetDR_BYTE3(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x0)|value<<32)
}
func (o *DCMI_Type) GetDR_BYTE3() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x0) >> 32
}

// The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
type DLYB_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
}

// DLYB.CR: control register
func (o *DLYB_Type) SetCR_DEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DLYB_Type) GetCR_DEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *DLYB_Type) SetCR_SEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DLYB_Type) GetCR_SEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}

// DLYB.CFGR: configuration register
func (o *DLYB_Type) SetCFGR_SEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xf)|value)
}
func (o *DLYB_Type) GetCFGR_SEL() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0xf
}
func (o *DLYB_Type) SetCFGR_UNIT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x7f00)|value<<8)
}
func (o *DLYB_Type) GetCFGR_UNIT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x7f00) >> 8
}
func (o *DLYB_Type) SetCFGR_LNG(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xfff0000)|value<<16)
}
func (o *DLYB_Type) GetCFGR_LNG() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xfff0000) >> 16
}
func (o *DLYB_Type) SetCFGR_LNGF(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x80000000)|value<<31)
}
func (o *DLYB_Type) GetCFGR_LNGF() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x80000000) >> 31
}

// DMA2D controller
type DMA2D_Type struct {
	CR           volatile.Register32 // 0x0
	ISR          volatile.Register32 // 0x4
	IFCR         volatile.Register32 // 0x8
	FGMAR        volatile.Register32 // 0xC
	FGOR         volatile.Register32 // 0x10
	BGMAR        volatile.Register32 // 0x14
	BGOR         volatile.Register32 // 0x18
	FGPFCCR      volatile.Register32 // 0x1C
	FGCOLR       volatile.Register32 // 0x20
	BGPFCCR      volatile.Register32 // 0x24
	BGCOLR       volatile.Register32 // 0x28
	FGCMAR       volatile.Register32 // 0x2C
	BGCMAR       volatile.Register32 // 0x30
	OPFCCR       volatile.Register32 // 0x34
	OCOLR_RGB888 volatile.Register32 // 0x38
	OMAR         volatile.Register32 // 0x3C
	OOR          volatile.Register32 // 0x40
	NLR          volatile.Register32 // 0x44
	LWR          volatile.Register32 // 0x48
	AMTCR        volatile.Register32 // 0x4C
	_            [944]byte
	FGCLUT       volatile.Register32 // 0x400
	_            [1020]byte
	BGCLUT       volatile.Register32 // 0x800
}

// DMA2D.CR: control register
func (o *DMA2D_Type) SetCR_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x70000)|value<<16)
}
func (o *DMA2D_Type) GetCR_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x70000) >> 16
}
func (o *DMA2D_Type) SetCR_CEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *DMA2D_Type) GetCR_CEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *DMA2D_Type) SetCR_CTCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *DMA2D_Type) GetCR_CTCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *DMA2D_Type) SetCR_CAEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *DMA2D_Type) GetCR_CAEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *DMA2D_Type) SetCR_TWIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *DMA2D_Type) GetCR_TWIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *DMA2D_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *DMA2D_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *DMA2D_Type) SetCR_TEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *DMA2D_Type) GetCR_TEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *DMA2D_Type) SetCR_LOM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *DMA2D_Type) GetCR_LOM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *DMA2D_Type) SetCR_ABORT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DMA2D_Type) GetCR_ABORT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *DMA2D_Type) SetCR_SUSP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DMA2D_Type) GetCR_SUSP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DMA2D_Type) SetCR_START(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DMA2D_Type) GetCR_START() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// DMA2D.ISR: Interrupt Status Register
func (o *DMA2D_Type) SetISR_CEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *DMA2D_Type) GetISR_CEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *DMA2D_Type) SetISR_CTCIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *DMA2D_Type) GetISR_CTCIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *DMA2D_Type) SetISR_CAEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *DMA2D_Type) GetISR_CAEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *DMA2D_Type) SetISR_TWIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *DMA2D_Type) GetISR_TWIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *DMA2D_Type) SetISR_TCIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *DMA2D_Type) GetISR_TCIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *DMA2D_Type) SetISR_TEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *DMA2D_Type) GetISR_TEIF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// DMA2D.IFCR: interrupt flag clear register
func (o *DMA2D_Type) SetIFCR_CCEIF(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20)|value<<5)
}
func (o *DMA2D_Type) GetIFCR_CCEIF() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20) >> 5
}
func (o *DMA2D_Type) SetIFCR_CCTCIF(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10)|value<<4)
}
func (o *DMA2D_Type) GetIFCR_CCTCIF() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10) >> 4
}
func (o *DMA2D_Type) SetIFCR_CAECIF(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8)|value<<3)
}
func (o *DMA2D_Type) GetIFCR_CAECIF() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8) >> 3
}
func (o *DMA2D_Type) SetIFCR_CTWIF(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x4)|value<<2)
}
func (o *DMA2D_Type) GetIFCR_CTWIF() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x4) >> 2
}
func (o *DMA2D_Type) SetIFCR_CTCIF(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x2)|value<<1)
}
func (o *DMA2D_Type) GetIFCR_CTCIF() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x2) >> 1
}
func (o *DMA2D_Type) SetIFCR_CTEIF(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x1)|value)
}
func (o *DMA2D_Type) GetIFCR_CTEIF() uint32 {
	return volatile.LoadUint32(&o.IFCR.Reg) & 0x1
}

// DMA2D.FGMAR: foreground memory address register
func (o *DMA2D_Type) SetFGMAR(value uint32) {
	volatile.StoreUint32(&o.FGMAR.Reg, value)
}
func (o *DMA2D_Type) GetFGMAR() uint32 {
	return volatile.LoadUint32(&o.FGMAR.Reg)
}

// DMA2D.FGOR: foreground offset register
func (o *DMA2D_Type) SetFGOR_LO(value uint32) {
	volatile.StoreUint32(&o.FGOR.Reg, volatile.LoadUint32(&o.FGOR.Reg)&^(0xffff)|value)
}
func (o *DMA2D_Type) GetFGOR_LO() uint32 {
	return volatile.LoadUint32(&o.FGOR.Reg) & 0xffff
}

// DMA2D.BGMAR: background memory address register
func (o *DMA2D_Type) SetBGMAR(value uint32) {
	volatile.StoreUint32(&o.BGMAR.Reg, value)
}
func (o *DMA2D_Type) GetBGMAR() uint32 {
	return volatile.LoadUint32(&o.BGMAR.Reg)
}

// DMA2D.BGOR: background offset register
func (o *DMA2D_Type) SetBGOR_LO(value uint32) {
	volatile.StoreUint32(&o.BGOR.Reg, volatile.LoadUint32(&o.BGOR.Reg)&^(0xffff)|value)
}
func (o *DMA2D_Type) GetBGOR_LO() uint32 {
	return volatile.LoadUint32(&o.BGOR.Reg) & 0xffff
}

// DMA2D.FGPFCCR: foreground PFC control register
func (o *DMA2D_Type) SetFGPFCCR_ALPHA(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0xff000000)|value<<24)
}
func (o *DMA2D_Type) GetFGPFCCR_ALPHA() uint32 {
	return (volatile.LoadUint32(&o.FGPFCCR.Reg) & 0xff000000) >> 24
}
func (o *DMA2D_Type) SetFGPFCCR_RBS(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA2D_Type) GetFGPFCCR_RBS() uint32 {
	return (volatile.LoadUint32(&o.FGPFCCR.Reg) & 0x200000) >> 21
}
func (o *DMA2D_Type) SetFGPFCCR_AI(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA2D_Type) GetFGPFCCR_AI() uint32 {
	return (volatile.LoadUint32(&o.FGPFCCR.Reg) & 0x100000) >> 20
}
func (o *DMA2D_Type) SetFGPFCCR_AM(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0x30000)|value<<16)
}
func (o *DMA2D_Type) GetFGPFCCR_AM() uint32 {
	return (volatile.LoadUint32(&o.FGPFCCR.Reg) & 0x30000) >> 16
}
func (o *DMA2D_Type) SetFGPFCCR_CS(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetFGPFCCR_CS() uint32 {
	return (volatile.LoadUint32(&o.FGPFCCR.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetFGPFCCR_START(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0x20)|value<<5)
}
func (o *DMA2D_Type) GetFGPFCCR_START() uint32 {
	return (volatile.LoadUint32(&o.FGPFCCR.Reg) & 0x20) >> 5
}
func (o *DMA2D_Type) SetFGPFCCR_CCM(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0x10)|value<<4)
}
func (o *DMA2D_Type) GetFGPFCCR_CCM() uint32 {
	return (volatile.LoadUint32(&o.FGPFCCR.Reg) & 0x10) >> 4
}
func (o *DMA2D_Type) SetFGPFCCR_CM(value uint32) {
	volatile.StoreUint32(&o.FGPFCCR.Reg, volatile.LoadUint32(&o.FGPFCCR.Reg)&^(0xf)|value)
}
func (o *DMA2D_Type) GetFGPFCCR_CM() uint32 {
	return volatile.LoadUint32(&o.FGPFCCR.Reg) & 0xf
}

// DMA2D.FGCOLR: foreground color register
func (o *DMA2D_Type) SetFGCOLR_RED(value uint32) {
	volatile.StoreUint32(&o.FGCOLR.Reg, volatile.LoadUint32(&o.FGCOLR.Reg)&^(0xff0000)|value<<16)
}
func (o *DMA2D_Type) GetFGCOLR_RED() uint32 {
	return (volatile.LoadUint32(&o.FGCOLR.Reg) & 0xff0000) >> 16
}
func (o *DMA2D_Type) SetFGCOLR_GREEN(value uint32) {
	volatile.StoreUint32(&o.FGCOLR.Reg, volatile.LoadUint32(&o.FGCOLR.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetFGCOLR_GREEN() uint32 {
	return (volatile.LoadUint32(&o.FGCOLR.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetFGCOLR_BLUE(value uint32) {
	volatile.StoreUint32(&o.FGCOLR.Reg, volatile.LoadUint32(&o.FGCOLR.Reg)&^(0xff)|value)
}
func (o *DMA2D_Type) GetFGCOLR_BLUE() uint32 {
	return volatile.LoadUint32(&o.FGCOLR.Reg) & 0xff
}

// DMA2D.BGPFCCR: background PFC control register
func (o *DMA2D_Type) SetBGPFCCR_ALPHA(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0xff000000)|value<<24)
}
func (o *DMA2D_Type) GetBGPFCCR_ALPHA() uint32 {
	return (volatile.LoadUint32(&o.BGPFCCR.Reg) & 0xff000000) >> 24
}
func (o *DMA2D_Type) SetBGPFCCR_RBS(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA2D_Type) GetBGPFCCR_RBS() uint32 {
	return (volatile.LoadUint32(&o.BGPFCCR.Reg) & 0x200000) >> 21
}
func (o *DMA2D_Type) SetBGPFCCR_AI(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA2D_Type) GetBGPFCCR_AI() uint32 {
	return (volatile.LoadUint32(&o.BGPFCCR.Reg) & 0x100000) >> 20
}
func (o *DMA2D_Type) SetBGPFCCR_AM(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0x30000)|value<<16)
}
func (o *DMA2D_Type) GetBGPFCCR_AM() uint32 {
	return (volatile.LoadUint32(&o.BGPFCCR.Reg) & 0x30000) >> 16
}
func (o *DMA2D_Type) SetBGPFCCR_CS(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetBGPFCCR_CS() uint32 {
	return (volatile.LoadUint32(&o.BGPFCCR.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetBGPFCCR_START(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0x20)|value<<5)
}
func (o *DMA2D_Type) GetBGPFCCR_START() uint32 {
	return (volatile.LoadUint32(&o.BGPFCCR.Reg) & 0x20) >> 5
}
func (o *DMA2D_Type) SetBGPFCCR_CCM(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0x10)|value<<4)
}
func (o *DMA2D_Type) GetBGPFCCR_CCM() uint32 {
	return (volatile.LoadUint32(&o.BGPFCCR.Reg) & 0x10) >> 4
}
func (o *DMA2D_Type) SetBGPFCCR_CM(value uint32) {
	volatile.StoreUint32(&o.BGPFCCR.Reg, volatile.LoadUint32(&o.BGPFCCR.Reg)&^(0xf)|value)
}
func (o *DMA2D_Type) GetBGPFCCR_CM() uint32 {
	return volatile.LoadUint32(&o.BGPFCCR.Reg) & 0xf
}

// DMA2D.BGCOLR: background color register
func (o *DMA2D_Type) SetBGCOLR_RED(value uint32) {
	volatile.StoreUint32(&o.BGCOLR.Reg, volatile.LoadUint32(&o.BGCOLR.Reg)&^(0xff0000)|value<<16)
}
func (o *DMA2D_Type) GetBGCOLR_RED() uint32 {
	return (volatile.LoadUint32(&o.BGCOLR.Reg) & 0xff0000) >> 16
}
func (o *DMA2D_Type) SetBGCOLR_GREEN(value uint32) {
	volatile.StoreUint32(&o.BGCOLR.Reg, volatile.LoadUint32(&o.BGCOLR.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetBGCOLR_GREEN() uint32 {
	return (volatile.LoadUint32(&o.BGCOLR.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetBGCOLR_BLUE(value uint32) {
	volatile.StoreUint32(&o.BGCOLR.Reg, volatile.LoadUint32(&o.BGCOLR.Reg)&^(0xff)|value)
}
func (o *DMA2D_Type) GetBGCOLR_BLUE() uint32 {
	return volatile.LoadUint32(&o.BGCOLR.Reg) & 0xff
}

// DMA2D.FGCMAR: foreground CLUT memory address register
func (o *DMA2D_Type) SetFGCMAR(value uint32) {
	volatile.StoreUint32(&o.FGCMAR.Reg, value)
}
func (o *DMA2D_Type) GetFGCMAR() uint32 {
	return volatile.LoadUint32(&o.FGCMAR.Reg)
}

// DMA2D.BGCMAR: background CLUT memory address register
func (o *DMA2D_Type) SetBGCMAR(value uint32) {
	volatile.StoreUint32(&o.BGCMAR.Reg, value)
}
func (o *DMA2D_Type) GetBGCMAR() uint32 {
	return volatile.LoadUint32(&o.BGCMAR.Reg)
}

// DMA2D.OPFCCR: output PFC control register
func (o *DMA2D_Type) SetOPFCCR_RBS(value uint32) {
	volatile.StoreUint32(&o.OPFCCR.Reg, volatile.LoadUint32(&o.OPFCCR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA2D_Type) GetOPFCCR_RBS() uint32 {
	return (volatile.LoadUint32(&o.OPFCCR.Reg) & 0x200000) >> 21
}
func (o *DMA2D_Type) SetOPFCCR_AI(value uint32) {
	volatile.StoreUint32(&o.OPFCCR.Reg, volatile.LoadUint32(&o.OPFCCR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA2D_Type) GetOPFCCR_AI() uint32 {
	return (volatile.LoadUint32(&o.OPFCCR.Reg) & 0x100000) >> 20
}
func (o *DMA2D_Type) SetOPFCCR_SB(value uint32) {
	volatile.StoreUint32(&o.OPFCCR.Reg, volatile.LoadUint32(&o.OPFCCR.Reg)&^(0x200)|value<<9)
}
func (o *DMA2D_Type) GetOPFCCR_SB() uint32 {
	return (volatile.LoadUint32(&o.OPFCCR.Reg) & 0x200) >> 9
}
func (o *DMA2D_Type) SetOPFCCR_CM(value uint32) {
	volatile.StoreUint32(&o.OPFCCR.Reg, volatile.LoadUint32(&o.OPFCCR.Reg)&^(0x7)|value)
}
func (o *DMA2D_Type) GetOPFCCR_CM() uint32 {
	return volatile.LoadUint32(&o.OPFCCR.Reg) & 0x7
}

// DMA2D.OCOLR_RGB888: output color register
func (o *DMA2D_Type) SetOCOLR_RGB888_APLHA(value uint32) {
	volatile.StoreUint32(&o.OCOLR_RGB888.Reg, volatile.LoadUint32(&o.OCOLR_RGB888.Reg)&^(0xff000000)|value<<24)
}
func (o *DMA2D_Type) GetOCOLR_RGB888_APLHA() uint32 {
	return (volatile.LoadUint32(&o.OCOLR_RGB888.Reg) & 0xff000000) >> 24
}
func (o *DMA2D_Type) SetOCOLR_RGB888_RED(value uint32) {
	volatile.StoreUint32(&o.OCOLR_RGB888.Reg, volatile.LoadUint32(&o.OCOLR_RGB888.Reg)&^(0xff0000)|value<<16)
}
func (o *DMA2D_Type) GetOCOLR_RGB888_RED() uint32 {
	return (volatile.LoadUint32(&o.OCOLR_RGB888.Reg) & 0xff0000) >> 16
}
func (o *DMA2D_Type) SetOCOLR_RGB888_GREEN(value uint32) {
	volatile.StoreUint32(&o.OCOLR_RGB888.Reg, volatile.LoadUint32(&o.OCOLR_RGB888.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetOCOLR_RGB888_GREEN() uint32 {
	return (volatile.LoadUint32(&o.OCOLR_RGB888.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetOCOLR_RGB888_BLUE(value uint32) {
	volatile.StoreUint32(&o.OCOLR_RGB888.Reg, volatile.LoadUint32(&o.OCOLR_RGB888.Reg)&^(0xff)|value)
}
func (o *DMA2D_Type) GetOCOLR_RGB888_BLUE() uint32 {
	return volatile.LoadUint32(&o.OCOLR_RGB888.Reg) & 0xff
}

// DMA2D.OMAR: output memory address register
func (o *DMA2D_Type) SetOMAR(value uint32) {
	volatile.StoreUint32(&o.OMAR.Reg, value)
}
func (o *DMA2D_Type) GetOMAR() uint32 {
	return volatile.LoadUint32(&o.OMAR.Reg)
}

// DMA2D.OOR: output offset register
func (o *DMA2D_Type) SetOOR_LO(value uint32) {
	volatile.StoreUint32(&o.OOR.Reg, volatile.LoadUint32(&o.OOR.Reg)&^(0xffff)|value)
}
func (o *DMA2D_Type) GetOOR_LO() uint32 {
	return volatile.LoadUint32(&o.OOR.Reg) & 0xffff
}

// DMA2D.NLR: number of line register
func (o *DMA2D_Type) SetNLR_PL(value uint32) {
	volatile.StoreUint32(&o.NLR.Reg, volatile.LoadUint32(&o.NLR.Reg)&^(0x3fff0000)|value<<16)
}
func (o *DMA2D_Type) GetNLR_PL() uint32 {
	return (volatile.LoadUint32(&o.NLR.Reg) & 0x3fff0000) >> 16
}
func (o *DMA2D_Type) SetNLR_NL(value uint32) {
	volatile.StoreUint32(&o.NLR.Reg, volatile.LoadUint32(&o.NLR.Reg)&^(0xffff)|value)
}
func (o *DMA2D_Type) GetNLR_NL() uint32 {
	return volatile.LoadUint32(&o.NLR.Reg) & 0xffff
}

// DMA2D.LWR: line watermark register
func (o *DMA2D_Type) SetLWR_LW(value uint32) {
	volatile.StoreUint32(&o.LWR.Reg, volatile.LoadUint32(&o.LWR.Reg)&^(0xffff)|value)
}
func (o *DMA2D_Type) GetLWR_LW() uint32 {
	return volatile.LoadUint32(&o.LWR.Reg) & 0xffff
}

// DMA2D.AMTCR: AHB master timer configuration register
func (o *DMA2D_Type) SetAMTCR_DT(value uint32) {
	volatile.StoreUint32(&o.AMTCR.Reg, volatile.LoadUint32(&o.AMTCR.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetAMTCR_DT() uint32 {
	return (volatile.LoadUint32(&o.AMTCR.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetAMTCR_EN(value uint32) {
	volatile.StoreUint32(&o.AMTCR.Reg, volatile.LoadUint32(&o.AMTCR.Reg)&^(0x1)|value)
}
func (o *DMA2D_Type) GetAMTCR_EN() uint32 {
	return volatile.LoadUint32(&o.AMTCR.Reg) & 0x1
}

// DMA2D.FGCLUT: FGCLUT
func (o *DMA2D_Type) SetFGCLUT_APLHA(value uint32) {
	volatile.StoreUint32(&o.FGCLUT.Reg, volatile.LoadUint32(&o.FGCLUT.Reg)&^(0xff000000)|value<<24)
}
func (o *DMA2D_Type) GetFGCLUT_APLHA() uint32 {
	return (volatile.LoadUint32(&o.FGCLUT.Reg) & 0xff000000) >> 24
}
func (o *DMA2D_Type) SetFGCLUT_RED(value uint32) {
	volatile.StoreUint32(&o.FGCLUT.Reg, volatile.LoadUint32(&o.FGCLUT.Reg)&^(0xff0000)|value<<16)
}
func (o *DMA2D_Type) GetFGCLUT_RED() uint32 {
	return (volatile.LoadUint32(&o.FGCLUT.Reg) & 0xff0000) >> 16
}
func (o *DMA2D_Type) SetFGCLUT_GREEN(value uint32) {
	volatile.StoreUint32(&o.FGCLUT.Reg, volatile.LoadUint32(&o.FGCLUT.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetFGCLUT_GREEN() uint32 {
	return (volatile.LoadUint32(&o.FGCLUT.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetFGCLUT_BLUE(value uint32) {
	volatile.StoreUint32(&o.FGCLUT.Reg, volatile.LoadUint32(&o.FGCLUT.Reg)&^(0xff)|value)
}
func (o *DMA2D_Type) GetFGCLUT_BLUE() uint32 {
	return volatile.LoadUint32(&o.FGCLUT.Reg) & 0xff
}

// DMA2D.BGCLUT: BGCLUT
func (o *DMA2D_Type) SetBGCLUT_APLHA(value uint32) {
	volatile.StoreUint32(&o.BGCLUT.Reg, volatile.LoadUint32(&o.BGCLUT.Reg)&^(0xff000000)|value<<24)
}
func (o *DMA2D_Type) GetBGCLUT_APLHA() uint32 {
	return (volatile.LoadUint32(&o.BGCLUT.Reg) & 0xff000000) >> 24
}
func (o *DMA2D_Type) SetBGCLUT_RED(value uint32) {
	volatile.StoreUint32(&o.BGCLUT.Reg, volatile.LoadUint32(&o.BGCLUT.Reg)&^(0xff0000)|value<<16)
}
func (o *DMA2D_Type) GetBGCLUT_RED() uint32 {
	return (volatile.LoadUint32(&o.BGCLUT.Reg) & 0xff0000) >> 16
}
func (o *DMA2D_Type) SetBGCLUT_GREEN(value uint32) {
	volatile.StoreUint32(&o.BGCLUT.Reg, volatile.LoadUint32(&o.BGCLUT.Reg)&^(0xff00)|value<<8)
}
func (o *DMA2D_Type) GetBGCLUT_GREEN() uint32 {
	return (volatile.LoadUint32(&o.BGCLUT.Reg) & 0xff00) >> 8
}
func (o *DMA2D_Type) SetBGCLUT_BLUE(value uint32) {
	volatile.StoreUint32(&o.BGCLUT.Reg, volatile.LoadUint32(&o.BGCLUT.Reg)&^(0xff)|value)
}
func (o *DMA2D_Type) GetBGCLUT_BLUE() uint32 {
	return volatile.LoadUint32(&o.BGCLUT.Reg) & 0xff
}

// External interrupt/event controller
type EXTI_Type struct {
	RTSR1     volatile.Register32 // 0x0
	FTSR1     volatile.Register32 // 0x4
	SWIER1    volatile.Register32 // 0x8
	RPR1      volatile.Register32 // 0xC
	FPR1      volatile.Register32 // 0x10
	SECCFGR1  volatile.Register32 // 0x14
	PRIVCFGR1 volatile.Register32 // 0x18
	_         [68]byte
	EXTICR1   volatile.Register32 // 0x60
	EXTICR2   volatile.Register32 // 0x64
	EXTICR3   volatile.Register32 // 0x68
	EXTICR4   volatile.Register32 // 0x6C
	LOCKR     volatile.Register32 // 0x70
	_         [12]byte
	IMR1      volatile.Register32 // 0x80
	EMR1      volatile.Register32 // 0x84
}

// EXTI.RTSR1: EXTI rising trigger selection register
func (o *EXTI_Type) SetRTSR1_RT0(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetRTSR1_RT0() uint32 {
	return volatile.LoadUint32(&o.RTSR1.Reg) & 0x1
}
func (o *EXTI_Type) SetRTSR1_RT1(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetRTSR1_RT1() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetRTSR1_RT2(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetRTSR1_RT2() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetRTSR1_RT3(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRTSR1_RT3() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRTSR1_RT4(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRTSR1_RT4() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRTSR1_RT5(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRTSR1_RT5() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRTSR1_RT6(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRTSR1_RT6() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetRTSR1_RT7(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetRTSR1_RT7() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetRTSR1_RT8(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetRTSR1_RT8() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetRTSR1_RT9(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetRTSR1_RT9() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetRTSR1_RT10(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetRTSR1_RT10() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetRTSR1_RT11(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetRTSR1_RT11() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetRTSR1_RT12(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetRTSR1_RT12() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetRTSR1_RT13(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetRTSR1_RT13() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetRTSR1_RT14(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetRTSR1_RT14() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetRTSR1_RT15(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetRTSR1_RT15() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetRTSR1_RT16(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetRTSR1_RT16() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetRTSR1_RT17(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetRTSR1_RT17() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetRTSR1_RT18(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetRTSR1_RT18() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetRTSR1_RT19(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetRTSR1_RT19() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetRTSR1_RT20(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetRTSR1_RT20() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetRTSR1_RT21(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetRTSR1_RT21() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetRTSR1_RT22(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetRTSR1_RT22() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetRTSR1_RT23(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetRTSR1_RT23() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetRTSR1_RT24(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetRTSR1_RT24() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetRTSR1_RT25(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetRTSR1_RT25() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x2000000) >> 25
}

// EXTI.FTSR1: EXTI falling trigger selection register
func (o *EXTI_Type) SetFTSR1_FT0(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetFTSR1_FT0() uint32 {
	return volatile.LoadUint32(&o.FTSR1.Reg) & 0x1
}
func (o *EXTI_Type) SetFTSR1_FT1(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetFTSR1_FT1() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetFTSR1_FT2(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetFTSR1_FT2() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetFTSR1_FT3(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFTSR1_FT3() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFTSR1_FT4(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFTSR1_FT4() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFTSR1_FT5(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFTSR1_FT5() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFTSR1_FT6(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFTSR1_FT6() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetFTSR1_FT7(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetFTSR1_FT7() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetFTSR1_FT8(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetFTSR1_FT8() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetFTSR1_FT9(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetFTSR1_FT9() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetFTSR1_FT10(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetFTSR1_FT10() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetFTSR1_FT11(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetFTSR1_FT11() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetFTSR1_FT12(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetFTSR1_FT12() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetFTSR1_FT13(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetFTSR1_FT13() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetFTSR1_FT14(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetFTSR1_FT14() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetFTSR1_FT15(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetFTSR1_FT15() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetFTSR1_FT16(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetFTSR1_FT16() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetFTSR1_FT17(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetFTSR1_FT17() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetFTSR1_FT18(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetFTSR1_FT18() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetFTSR1_FT19(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetFTSR1_FT19() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetFTSR1_FT20(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetFTSR1_FT20() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetFTSR1_FT21(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetFTSR1_FT21() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetFTSR1_FT22(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetFTSR1_FT22() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetFTSR1_FT23(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetFTSR1_FT23() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetFTSR1_FT24(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetFTSR1_FT24() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetFTSR1_FT25(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetFTSR1_FT25() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x2000000) >> 25
}

// EXTI.SWIER1: EXTI software interrupt event register
func (o *EXTI_Type) SetSWIER1_SWI0(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetSWIER1_SWI0() uint32 {
	return volatile.LoadUint32(&o.SWIER1.Reg) & 0x1
}
func (o *EXTI_Type) SetSWIER1_SWI1(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetSWIER1_SWI1() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetSWIER1_SWI2(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetSWIER1_SWI2() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetSWIER1_SWI3(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetSWIER1_SWI3() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetSWIER1_SWI4(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetSWIER1_SWI4() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetSWIER1_SWI5(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetSWIER1_SWI5() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetSWIER1_SWI6(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetSWIER1_SWI6() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetSWIER1_SWI7(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetSWIER1_SWI7() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetSWIER1_SWI8(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetSWIER1_SWI8() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetSWIER1_SWI9(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetSWIER1_SWI9() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetSWIER1_SWI10(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetSWIER1_SWI10() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetSWIER1_SWI11(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetSWIER1_SWI11() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetSWIER1_SWI12(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetSWIER1_SWI12() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetSWIER1_SWI13(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetSWIER1_SWI13() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetSWIER1_SWI14(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetSWIER1_SWI14() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetSWIER1_SWI15(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetSWIER1_SWI15() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetSWIER1_SWI16(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetSWIER1_SWI16() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetSWIER1_SWI17(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetSWIER1_SWI17() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetSWIER1_SWI18(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetSWIER1_SWI18() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetSWIER1_SWI19(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetSWIER1_SWI19() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetSWIER1_SWI20(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetSWIER1_SWI20() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetSWIER1_SWI21(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetSWIER1_SWI21() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetSWIER1_SWI22(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetSWIER1_SWI22() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetSWIER1_SWI23(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetSWIER1_SWI23() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetSWIER1_SWI24(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetSWIER1_SWI24() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetSWIER1_SWI25(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetSWIER1_SWI25() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x2000000) >> 25
}

// EXTI.RPR1: EXTI rising edge pending register
func (o *EXTI_Type) SetRPR1_RPIF0(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetRPR1_RPIF0() uint32 {
	return volatile.LoadUint32(&o.RPR1.Reg) & 0x1
}
func (o *EXTI_Type) SetRPR1_RPIF1(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetRPR1_RPIF1() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetRPR1_RPIF2(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetRPR1_RPIF2() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetRPR1_RPIF3(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRPR1_RPIF3() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRPR1_RPIF4(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRPR1_RPIF4() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRPR1_RPIF5(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRPR1_RPIF5() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRPR1_RPIF6(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRPR1_RPIF6() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetRPR1_RPIF7(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetRPR1_RPIF7() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetRPR1_RPIF8(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetRPR1_RPIF8() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetRPR1_RPIF9(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetRPR1_RPIF9() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetRPR1_RPIF10(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetRPR1_RPIF10() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetRPR1_RPIF11(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetRPR1_RPIF11() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetRPR1_RPIF12(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetRPR1_RPIF12() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetRPR1_RPIF13(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetRPR1_RPIF13() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetRPR1_RPIF14(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetRPR1_RPIF14() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetRPR1_RPIF15(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetRPR1_RPIF15() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetRPR1_RPIF16(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetRPR1_RPIF16() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetRPR1_RPIF17(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetRPR1_RPIF17() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetRPR1_RPIF18(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetRPR1_RPIF18() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetRPR1_RPIF19(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetRPR1_RPIF19() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetRPR1_RPIF20(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetRPR1_RPIF20() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetRPR1_RPIF21(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetRPR1_RPIF21() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetRPR1_RPIF22(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetRPR1_RPIF22() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetRPR1_RPIF23(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetRPR1_RPIF23() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetRPR1_RPIF24(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetRPR1_RPIF24() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetRPR1_RPIF25(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetRPR1_RPIF25() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x2000000) >> 25
}

// EXTI.FPR1: EXTI falling edge pending register
func (o *EXTI_Type) SetFPR1_FPIF0(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetFPR1_FPIF0() uint32 {
	return volatile.LoadUint32(&o.FPR1.Reg) & 0x1
}
func (o *EXTI_Type) SetFPR1_FPIF1(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetFPR1_FPIF1() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetFPR1_FPIF2(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetFPR1_FPIF2() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetFPR1_FPIF3(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFPR1_FPIF3() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFPR1_FPIF4(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFPR1_FPIF4() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFPR1_FPIF5(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFPR1_FPIF5() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFPR1_FPIF6(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFPR1_FPIF6() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetFPR1_FPIF7(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetFPR1_FPIF7() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetFPR1_FPIF8(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetFPR1_FPIF8() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetFPR1_FPIF9(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetFPR1_FPIF9() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetFPR1_FPIF10(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetFPR1_FPIF10() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetFPR1_FPIF11(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetFPR1_FPIF11() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetFPR1_FPIF12(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetFPR1_FPIF12() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetFPR1_FPIF13(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetFPR1_FPIF13() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetFPR1_FPIF14(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetFPR1_FPIF14() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetFPR1_FPIF15(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetFPR1_FPIF15() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetFPR1_FPIF16(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetFPR1_FPIF16() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetFPR1_FPIF17(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetFPR1_FPIF17() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetFPR1_FPIF18(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetFPR1_FPIF18() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetFPR1_FPIF19(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetFPR1_FPIF19() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetFPR1_FPIF20(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetFPR1_FPIF20() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetFPR1_FPIF21(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetFPR1_FPIF21() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetFPR1_FPIF22(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetFPR1_FPIF22() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetFPR1_FPIF23(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetFPR1_FPIF23() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetFPR1_FPIF24(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetFPR1_FPIF24() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetFPR1_FPIF25(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetFPR1_FPIF25() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x2000000) >> 25
}

// EXTI.SECCFGR1: EXTI security configuration register
func (o *EXTI_Type) SetSECCFGR1_SEC0(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetSECCFGR1_SEC0() uint32 {
	return volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x1
}
func (o *EXTI_Type) SetSECCFGR1_SEC1(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetSECCFGR1_SEC1() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetSECCFGR1_SEC2(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetSECCFGR1_SEC2() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetSECCFGR1_SEC3(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetSECCFGR1_SEC3() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetSECCFGR1_SEC4(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetSECCFGR1_SEC4() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetSECCFGR1_SEC5(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetSECCFGR1_SEC5() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetSECCFGR1_SEC6(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetSECCFGR1_SEC6() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetSECCFGR1_SEC7(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetSECCFGR1_SEC7() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetSECCFGR1_SEC8(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetSECCFGR1_SEC8() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetSECCFGR1_SEC9(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetSECCFGR1_SEC9() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetSECCFGR1_SEC10(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetSECCFGR1_SEC10() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetSECCFGR1_SEC11(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetSECCFGR1_SEC11() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetSECCFGR1_SEC12(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetSECCFGR1_SEC12() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetSECCFGR1_SEC13(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetSECCFGR1_SEC13() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetSECCFGR1_SEC14(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetSECCFGR1_SEC14() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetSECCFGR1_SEC15(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetSECCFGR1_SEC15() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetSECCFGR1_SEC16(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetSECCFGR1_SEC16() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetSECCFGR1_SEC17(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetSECCFGR1_SEC17() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetSECCFGR1_SEC18(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetSECCFGR1_SEC18() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetSECCFGR1_SEC19(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetSECCFGR1_SEC19() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetSECCFGR1_SEC20(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetSECCFGR1_SEC20() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetSECCFGR1_SEC21(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetSECCFGR1_SEC21() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetSECCFGR1_SEC22(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetSECCFGR1_SEC22() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetSECCFGR1_SEC23(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetSECCFGR1_SEC23() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetSECCFGR1_SEC24(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetSECCFGR1_SEC24() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetSECCFGR1_SEC25(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetSECCFGR1_SEC25() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x2000000) >> 25
}

// EXTI.PRIVCFGR1: EXTI privilege configuration register
func (o *EXTI_Type) SetPRIVCFGR1_PRIV0(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV0() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x1
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV1(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV1() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV2(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV2() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV3(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV3() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV4(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV4() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV5(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV5() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV6(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV6() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV7(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV7() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV8(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV8() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV9(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV9() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV10(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV10() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV11(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV11() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV12(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV12() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV13(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV13() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV14(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV14() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV15(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV15() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV16(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV16() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV17(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV17() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV18(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV18() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV19(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV19() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV20(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV20() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV21(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV21() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV22(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV22() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV23(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV23() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV24(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV24() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV25(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV25() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x2000000) >> 25
}

// EXTI.EXTICR1: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR1_EXTI0(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR1_EXTI0() uint32 {
	return volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR1_EXTI1(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR1_EXTI1() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR1_EXTI2(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR1_EXTI2() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR1_EXTI3(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR1_EXTI3() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR2: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR2_EXTI4(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR2_EXTI4() uint32 {
	return volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR2_EXTI5(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR2_EXTI5() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR2_EXTI6(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR2_EXTI6() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR2_EXTI7(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR2_EXTI7() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR3: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR3_EXTI8(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR3_EXTI8() uint32 {
	return volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR3_EXTI9(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR3_EXTI9() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR3_EXTI10(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR3_EXTI10() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR3_EXTI11(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR3_EXTI11() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR4: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR4_EXTI12(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR4_EXTI12() uint32 {
	return volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR4_EXTI13(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR4_EXTI13() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR4_EXTI14(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR4_EXTI14() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR4_EXTI15(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR4_EXTI15() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff000000) >> 24
}

// EXTI.LOCKR: EXTI lock register
func (o *EXTI_Type) SetLOCKR_LOCK(value uint32) {
	volatile.StoreUint32(&o.LOCKR.Reg, volatile.LoadUint32(&o.LOCKR.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetLOCKR_LOCK() uint32 {
	return volatile.LoadUint32(&o.LOCKR.Reg) & 0x1
}

// EXTI.IMR1: EXTI CPU wake-up with interrupt mask register
func (o *EXTI_Type) SetIMR1_IM0(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetIMR1_IM0() uint32 {
	return volatile.LoadUint32(&o.IMR1.Reg) & 0x1
}
func (o *EXTI_Type) SetIMR1_IM1(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetIMR1_IM1() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetIMR1_IM2(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetIMR1_IM2() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetIMR1_IM3(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetIMR1_IM3() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetIMR1_IM4(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetIMR1_IM4() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetIMR1_IM5(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetIMR1_IM5() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetIMR1_IM6(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetIMR1_IM6() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetIMR1_IM7(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetIMR1_IM7() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetIMR1_IM8(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetIMR1_IM8() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetIMR1_IM9(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetIMR1_IM9() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetIMR1_IM10(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetIMR1_IM10() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetIMR1_IM11(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetIMR1_IM11() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetIMR1_IM12(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetIMR1_IM12() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetIMR1_IM13(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetIMR1_IM13() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetIMR1_IM14(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetIMR1_IM14() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetIMR1_IM15(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetIMR1_IM15() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetIMR1_IM16(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetIMR1_IM16() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetIMR1_IM17(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetIMR1_IM17() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetIMR1_IM18(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetIMR1_IM18() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetIMR1_IM19(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetIMR1_IM19() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetIMR1_IM20(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetIMR1_IM20() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetIMR1_IM21(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetIMR1_IM21() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetIMR1_IM22(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetIMR1_IM22() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetIMR1_IM23(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetIMR1_IM23() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetIMR1_IM24(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetIMR1_IM24() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetIMR1_IM25(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetIMR1_IM25() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2000000) >> 25
}

// EXTI.EMR1: EXTI CPU wake-up with event mask register
func (o *EXTI_Type) SetEMR1_EM0(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetEMR1_EM0() uint32 {
	return volatile.LoadUint32(&o.EMR1.Reg) & 0x1
}
func (o *EXTI_Type) SetEMR1_EM1(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetEMR1_EM1() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetEMR1_EM2(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetEMR1_EM2() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetEMR1_EM3(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetEMR1_EM3() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetEMR1_EM4(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetEMR1_EM4() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetEMR1_EM5(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetEMR1_EM5() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetEMR1_EM6(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetEMR1_EM6() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetEMR1_EM7(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetEMR1_EM7() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetEMR1_EM8(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetEMR1_EM8() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetEMR1_EM9(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetEMR1_EM9() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetEMR1_EM10(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetEMR1_EM10() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetEMR1_EM11(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetEMR1_EM11() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetEMR1_EM12(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetEMR1_EM12() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetEMR1_EM13(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetEMR1_EM13() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetEMR1_EM14(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetEMR1_EM14() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetEMR1_EM15(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetEMR1_EM15() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetEMR1_EM16(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetEMR1_EM16() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetEMR1_EM17(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetEMR1_EM17() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetEMR1_EM18(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetEMR1_EM18() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetEMR1_EM19(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetEMR1_EM19() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetEMR1_EM20(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetEMR1_EM20() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetEMR1_EM21(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetEMR1_EM21() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetEMR1_EM22(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetEMR1_EM22() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetEMR1_EM23(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetEMR1_EM23() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetEMR1_EM24(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetEMR1_EM24() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetEMR1_EM25(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetEMR1_EM25() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2000000) >> 25
}

// FDCAN1_RAM
type FDCAN_Type struct {
	CREL   volatile.Register32 // 0x0
	ENDN   volatile.Register32 // 0x4
	_      [4]byte
	DBTP   volatile.Register32 // 0xC
	TEST   volatile.Register32 // 0x10
	RWD    volatile.Register32 // 0x14
	CCCR   volatile.Register32 // 0x18
	NBTP   volatile.Register32 // 0x1C
	TSCC   volatile.Register32 // 0x20
	TSCV   volatile.Register32 // 0x24
	TOCC   volatile.Register32 // 0x28
	TOCV   volatile.Register32 // 0x2C
	_      [16]byte
	ECR    volatile.Register32 // 0x40
	PSR    volatile.Register32 // 0x44
	TDCR   volatile.Register32 // 0x48
	_      [4]byte
	IR     volatile.Register32 // 0x50
	IE     volatile.Register32 // 0x54
	ILS    volatile.Register32 // 0x58
	ILE    volatile.Register32 // 0x5C
	_      [32]byte
	RXGFC  volatile.Register32 // 0x80
	XIDAM  volatile.Register32 // 0x84
	HPMS   volatile.Register32 // 0x88
	_      [4]byte
	RXF0S  volatile.Register32 // 0x90
	RXF0A  volatile.Register32 // 0x94
	RXF1S  volatile.Register32 // 0x98
	RXF1A  volatile.Register32 // 0x9C
	_      [32]byte
	TXBC   volatile.Register32 // 0xC0
	TXFQS  volatile.Register32 // 0xC4
	TXBRP  volatile.Register32 // 0xC8
	TXBAR  volatile.Register32 // 0xCC
	TXBCR  volatile.Register32 // 0xD0
	TXBTO  volatile.Register32 // 0xD4
	TXBCF  volatile.Register32 // 0xD8
	TXBTIE volatile.Register32 // 0xDC
	TXBCIE volatile.Register32 // 0xE0
	TXEFS  volatile.Register32 // 0xE4
	TXEFA  volatile.Register32 // 0xE8
	_      [20]byte
	CKDIV  volatile.Register32 // 0x100
}

// FDCAN.CREL: FDCAN Core Release Register
func (o *FDCAN_Type) SetCREL_REL(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf0000000)|value<<28)
}
func (o *FDCAN_Type) GetCREL_REL() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf0000000) >> 28
}
func (o *FDCAN_Type) SetCREL_STEP(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf000000)|value<<24)
}
func (o *FDCAN_Type) GetCREL_STEP() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf000000) >> 24
}
func (o *FDCAN_Type) SetCREL_SUBSTEP(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf00000)|value<<20)
}
func (o *FDCAN_Type) GetCREL_SUBSTEP() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf00000) >> 20
}
func (o *FDCAN_Type) SetCREL_YEAR(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf0000)|value<<16)
}
func (o *FDCAN_Type) GetCREL_YEAR() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf0000) >> 16
}
func (o *FDCAN_Type) SetCREL_MON(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xff00)|value<<8)
}
func (o *FDCAN_Type) GetCREL_MON() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xff00) >> 8
}
func (o *FDCAN_Type) SetCREL_DAY(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xff)|value)
}
func (o *FDCAN_Type) GetCREL_DAY() uint32 {
	return volatile.LoadUint32(&o.CREL.Reg) & 0xff
}

// FDCAN.ENDN: FDCAN endian register
func (o *FDCAN_Type) SetENDN(value uint32) {
	volatile.StoreUint32(&o.ENDN.Reg, value)
}
func (o *FDCAN_Type) GetENDN() uint32 {
	return volatile.LoadUint32(&o.ENDN.Reg)
}

// FDCAN.DBTP: FDCAN Data Bit Timing and Prescaler Register
func (o *FDCAN_Type) SetDBTP_DSJW(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetDBTP_DSJW() uint32 {
	return volatile.LoadUint32(&o.DBTP.Reg) & 0xf
}
func (o *FDCAN_Type) SetDBTP_DTSEG2(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0xf0)|value<<4)
}
func (o *FDCAN_Type) GetDBTP_DTSEG2() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0xf0) >> 4
}
func (o *FDCAN_Type) SetDBTP_DTSEG1(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0x1f00)|value<<8)
}
func (o *FDCAN_Type) GetDBTP_DTSEG1() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0x1f00) >> 8
}
func (o *FDCAN_Type) SetDBTP_DBRP(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0x1f0000)|value<<16)
}
func (o *FDCAN_Type) GetDBTP_DBRP() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0x1f0000) >> 16
}
func (o *FDCAN_Type) SetDBTP_TDC(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0x800000)|value<<23)
}
func (o *FDCAN_Type) GetDBTP_TDC() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0x800000) >> 23
}

// FDCAN.TEST: FDCAN Test Register
func (o *FDCAN_Type) SetTEST_LBCK(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetTEST_LBCK() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetTEST_TX(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x60)|value<<5)
}
func (o *FDCAN_Type) GetTEST_TX() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x60) >> 5
}
func (o *FDCAN_Type) SetTEST_RX(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetTEST_RX() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x80) >> 7
}

// FDCAN.RWD: FDCAN RAM Watchdog Register
func (o *FDCAN_Type) SetRWD_WDV(value uint32) {
	volatile.StoreUint32(&o.RWD.Reg, volatile.LoadUint32(&o.RWD.Reg)&^(0xff00)|value<<8)
}
func (o *FDCAN_Type) GetRWD_WDV() uint32 {
	return (volatile.LoadUint32(&o.RWD.Reg) & 0xff00) >> 8
}
func (o *FDCAN_Type) SetRWD_WDC(value uint32) {
	volatile.StoreUint32(&o.RWD.Reg, volatile.LoadUint32(&o.RWD.Reg)&^(0xff)|value)
}
func (o *FDCAN_Type) GetRWD_WDC() uint32 {
	return volatile.LoadUint32(&o.RWD.Reg) & 0xff
}

// FDCAN.CCCR: FDCAN CC Control Register
func (o *FDCAN_Type) SetCCCR_INIT(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetCCCR_INIT() uint32 {
	return volatile.LoadUint32(&o.CCCR.Reg) & 0x1
}
func (o *FDCAN_Type) SetCCCR_CCE(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetCCCR_CCE() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetCCCR_ASM(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetCCCR_ASM() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetCCCR_CSA(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetCCCR_CSA() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetCCCR_CSR(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetCCCR_CSR() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetCCCR_MON(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetCCCR_MON() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetCCCR_DAR(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetCCCR_DAR() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetCCCR_TEST(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetCCCR_TEST() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetCCCR_FDOE(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetCCCR_FDOE() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetCCCR_BRSE(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetCCCR_BRSE() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetCCCR_PXHD(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetCCCR_PXHD() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetCCCR_EFBI(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetCCCR_EFBI() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetCCCR_TXP(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetCCCR_TXP() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetCCCR_NISO(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetCCCR_NISO() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x8000) >> 15
}

// FDCAN.NBTP: FDCAN Nominal Bit Timing and Prescaler Register
func (o *FDCAN_Type) SetNBTP_NSJW(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0xfe000000)|value<<25)
}
func (o *FDCAN_Type) GetNBTP_NSJW() uint32 {
	return (volatile.LoadUint32(&o.NBTP.Reg) & 0xfe000000) >> 25
}
func (o *FDCAN_Type) SetNBTP_NBRP(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0x1ff0000)|value<<16)
}
func (o *FDCAN_Type) GetNBTP_NBRP() uint32 {
	return (volatile.LoadUint32(&o.NBTP.Reg) & 0x1ff0000) >> 16
}
func (o *FDCAN_Type) SetNBTP_NTSEG1(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0xff00)|value<<8)
}
func (o *FDCAN_Type) GetNBTP_NTSEG1() uint32 {
	return (volatile.LoadUint32(&o.NBTP.Reg) & 0xff00) >> 8
}
func (o *FDCAN_Type) SetNBTP_NTSEG2(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0x7f)|value)
}
func (o *FDCAN_Type) GetNBTP_NTSEG2() uint32 {
	return volatile.LoadUint32(&o.NBTP.Reg) & 0x7f
}

// FDCAN.TSCC: FDCAN Timestamp Counter Configuration Register
func (o *FDCAN_Type) SetTSCC_TCP(value uint32) {
	volatile.StoreUint32(&o.TSCC.Reg, volatile.LoadUint32(&o.TSCC.Reg)&^(0xf0000)|value<<16)
}
func (o *FDCAN_Type) GetTSCC_TCP() uint32 {
	return (volatile.LoadUint32(&o.TSCC.Reg) & 0xf0000) >> 16
}
func (o *FDCAN_Type) SetTSCC_TSS(value uint32) {
	volatile.StoreUint32(&o.TSCC.Reg, volatile.LoadUint32(&o.TSCC.Reg)&^(0x3)|value)
}
func (o *FDCAN_Type) GetTSCC_TSS() uint32 {
	return volatile.LoadUint32(&o.TSCC.Reg) & 0x3
}

// FDCAN.TSCV: FDCAN Timestamp Counter Value Register
func (o *FDCAN_Type) SetTSCV_TSC(value uint32) {
	volatile.StoreUint32(&o.TSCV.Reg, volatile.LoadUint32(&o.TSCV.Reg)&^(0xffff)|value)
}
func (o *FDCAN_Type) GetTSCV_TSC() uint32 {
	return volatile.LoadUint32(&o.TSCV.Reg) & 0xffff
}

// FDCAN.TOCC: FDCAN Timeout Counter Configuration Register
func (o *FDCAN_Type) SetTOCC_ETOC(value uint32) {
	volatile.StoreUint32(&o.TOCC.Reg, volatile.LoadUint32(&o.TOCC.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetTOCC_ETOC() uint32 {
	return volatile.LoadUint32(&o.TOCC.Reg) & 0x1
}
func (o *FDCAN_Type) SetTOCC_TOS(value uint32) {
	volatile.StoreUint32(&o.TOCC.Reg, volatile.LoadUint32(&o.TOCC.Reg)&^(0x6)|value<<1)
}
func (o *FDCAN_Type) GetTOCC_TOS() uint32 {
	return (volatile.LoadUint32(&o.TOCC.Reg) & 0x6) >> 1
}
func (o *FDCAN_Type) SetTOCC_TOP(value uint32) {
	volatile.StoreUint32(&o.TOCC.Reg, volatile.LoadUint32(&o.TOCC.Reg)&^(0xffff0000)|value<<16)
}
func (o *FDCAN_Type) GetTOCC_TOP() uint32 {
	return (volatile.LoadUint32(&o.TOCC.Reg) & 0xffff0000) >> 16
}

// FDCAN.TOCV: FDCAN Timeout Counter Value Register
func (o *FDCAN_Type) SetTOCV_TOC(value uint32) {
	volatile.StoreUint32(&o.TOCV.Reg, volatile.LoadUint32(&o.TOCV.Reg)&^(0xffff)|value)
}
func (o *FDCAN_Type) GetTOCV_TOC() uint32 {
	return volatile.LoadUint32(&o.TOCV.Reg) & 0xffff
}

// FDCAN.ECR: FDCAN Error Counter Register
func (o *FDCAN_Type) SetECR_CEL(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xff0000)|value<<16)
}
func (o *FDCAN_Type) GetECR_CEL() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0xff0000) >> 16
}
func (o *FDCAN_Type) SetECR_RP(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetECR_RP() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0x8000) >> 15
}
func (o *FDCAN_Type) SetECR_REC(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x7f00)|value<<8)
}
func (o *FDCAN_Type) GetECR_REC() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0x7f00) >> 8
}
func (o *FDCAN_Type) SetECR_TEC(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xff)|value)
}
func (o *FDCAN_Type) GetECR_TEC() uint32 {
	return volatile.LoadUint32(&o.ECR.Reg) & 0xff
}

// FDCAN.PSR: FDCAN Protocol Status Register
func (o *FDCAN_Type) SetPSR_LEC(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetPSR_LEC() uint32 {
	return volatile.LoadUint32(&o.PSR.Reg) & 0x7
}
func (o *FDCAN_Type) SetPSR_ACT(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x18)|value<<3)
}
func (o *FDCAN_Type) GetPSR_ACT() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x18) >> 3
}
func (o *FDCAN_Type) SetPSR_EP(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetPSR_EP() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetPSR_EW(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetPSR_EW() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetPSR_BO(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetPSR_BO() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetPSR_DLEC(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x700)|value<<8)
}
func (o *FDCAN_Type) GetPSR_DLEC() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x700) >> 8
}
func (o *FDCAN_Type) SetPSR_RESI(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x800)|value<<11)
}
func (o *FDCAN_Type) GetPSR_RESI() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x800) >> 11
}
func (o *FDCAN_Type) SetPSR_RBRS(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetPSR_RBRS() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetPSR_REDL(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetPSR_REDL() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetPSR_PXE(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetPSR_PXE() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetPSR_TDCV(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x7f0000)|value<<16)
}
func (o *FDCAN_Type) GetPSR_TDCV() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x7f0000) >> 16
}

// FDCAN.TDCR: FDCAN Transmitter Delay Compensation Register
func (o *FDCAN_Type) SetTDCR_TDCF(value uint32) {
	volatile.StoreUint32(&o.TDCR.Reg, volatile.LoadUint32(&o.TDCR.Reg)&^(0x7f)|value)
}
func (o *FDCAN_Type) GetTDCR_TDCF() uint32 {
	return volatile.LoadUint32(&o.TDCR.Reg) & 0x7f
}
func (o *FDCAN_Type) SetTDCR_TDCO(value uint32) {
	volatile.StoreUint32(&o.TDCR.Reg, volatile.LoadUint32(&o.TDCR.Reg)&^(0x7f00)|value<<8)
}
func (o *FDCAN_Type) GetTDCR_TDCO() uint32 {
	return (volatile.LoadUint32(&o.TDCR.Reg) & 0x7f00) >> 8
}

// FDCAN.IR: FDCAN Interrupt Register
func (o *FDCAN_Type) SetIR_RF0N(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetIR_RF0N() uint32 {
	return volatile.LoadUint32(&o.IR.Reg) & 0x1
}
func (o *FDCAN_Type) SetIR_RF0F(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetIR_RF0F() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetIR_RF0L(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetIR_RF0L() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetIR_RF1N(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetIR_RF1N() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetIR_RF1F(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetIR_RF1F() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetIR_RF1L(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetIR_RF1L() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetIR_HPM(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetIR_HPM() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetIR_TC(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetIR_TC() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetIR_TCF(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetIR_TCF() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetIR_TFE(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetIR_TFE() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetIR_TEFN(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x400)|value<<10)
}
func (o *FDCAN_Type) GetIR_TEFN() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x400) >> 10
}
func (o *FDCAN_Type) SetIR_TEFF(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x800)|value<<11)
}
func (o *FDCAN_Type) GetIR_TEFF() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x800) >> 11
}
func (o *FDCAN_Type) SetIR_TEFL(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetIR_TEFL() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetIR_TSW(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetIR_TSW() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetIR_MRAF(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetIR_MRAF() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetIR_TOO(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetIR_TOO() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x8000) >> 15
}
func (o *FDCAN_Type) SetIR_ELO(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x10000)|value<<16)
}
func (o *FDCAN_Type) GetIR_ELO() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x10000) >> 16
}
func (o *FDCAN_Type) SetIR_EP(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x20000)|value<<17)
}
func (o *FDCAN_Type) GetIR_EP() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x20000) >> 17
}
func (o *FDCAN_Type) SetIR_EW(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x40000)|value<<18)
}
func (o *FDCAN_Type) GetIR_EW() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x40000) >> 18
}
func (o *FDCAN_Type) SetIR_BO(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x80000)|value<<19)
}
func (o *FDCAN_Type) GetIR_BO() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x80000) >> 19
}
func (o *FDCAN_Type) SetIR_WDI(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x100000)|value<<20)
}
func (o *FDCAN_Type) GetIR_WDI() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x100000) >> 20
}
func (o *FDCAN_Type) SetIR_PEA(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x200000)|value<<21)
}
func (o *FDCAN_Type) GetIR_PEA() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x200000) >> 21
}
func (o *FDCAN_Type) SetIR_PED(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x400000)|value<<22)
}
func (o *FDCAN_Type) GetIR_PED() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x400000) >> 22
}
func (o *FDCAN_Type) SetIR_ARA(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x800000)|value<<23)
}
func (o *FDCAN_Type) GetIR_ARA() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x800000) >> 23
}

// FDCAN.IE: FDCAN Interrupt Enable Register
func (o *FDCAN_Type) SetIE_RF0NE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetIE_RF0NE() uint32 {
	return volatile.LoadUint32(&o.IE.Reg) & 0x1
}
func (o *FDCAN_Type) SetIE_RF0FE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetIE_RF0FE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetIE_RF0LE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetIE_RF0LE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetIE_RF1NE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetIE_RF1NE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetIE_RF1FE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetIE_RF1FE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetIE_RF1LE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetIE_RF1LE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetIE_HPME(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetIE_HPME() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetIE_TCE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetIE_TCE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetIE_TCFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetIE_TCFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetIE_TEFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetIE_TEFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetIE_TEFNE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x400)|value<<10)
}
func (o *FDCAN_Type) GetIE_TEFNE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x400) >> 10
}
func (o *FDCAN_Type) SetIE_TEFFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x800)|value<<11)
}
func (o *FDCAN_Type) GetIE_TEFFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x800) >> 11
}
func (o *FDCAN_Type) SetIE_TEFLE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetIE_TEFLE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetIE_TSWE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetIE_TSWE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetIE_MRAFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetIE_MRAFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetIE_TOOE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetIE_TOOE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x8000) >> 15
}
func (o *FDCAN_Type) SetIE_ELOE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x10000)|value<<16)
}
func (o *FDCAN_Type) GetIE_ELOE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x10000) >> 16
}
func (o *FDCAN_Type) SetIE_EPE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x20000)|value<<17)
}
func (o *FDCAN_Type) GetIE_EPE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x20000) >> 17
}
func (o *FDCAN_Type) SetIE_EWE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x40000)|value<<18)
}
func (o *FDCAN_Type) GetIE_EWE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x40000) >> 18
}
func (o *FDCAN_Type) SetIE_BOE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x80000)|value<<19)
}
func (o *FDCAN_Type) GetIE_BOE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x80000) >> 19
}
func (o *FDCAN_Type) SetIE_WDIE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x100000)|value<<20)
}
func (o *FDCAN_Type) GetIE_WDIE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x100000) >> 20
}
func (o *FDCAN_Type) SetIE_PEAE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x200000)|value<<21)
}
func (o *FDCAN_Type) GetIE_PEAE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x200000) >> 21
}
func (o *FDCAN_Type) SetIE_PEDE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x400000)|value<<22)
}
func (o *FDCAN_Type) GetIE_PEDE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x400000) >> 22
}
func (o *FDCAN_Type) SetIE_ARAE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x800000)|value<<23)
}
func (o *FDCAN_Type) GetIE_ARAE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x800000) >> 23
}

// FDCAN.ILS: FDCAN Interrupt Line Select Register
func (o *FDCAN_Type) SetILS_RxFIFO0(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetILS_RxFIFO0() uint32 {
	return volatile.LoadUint32(&o.ILS.Reg) & 0x1
}
func (o *FDCAN_Type) SetILS_RxFIFO1(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetILS_RxFIFO1() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetILS_SMSG(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetILS_SMSG() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetILS_TFERR(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetILS_TFERR() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetILS_MISC(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetILS_MISC() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetILS_BERR(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetILS_BERR() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetILS_PERR(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetILS_PERR() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x40) >> 6
}

// FDCAN.ILE: FDCAN Interrupt Line Enable Register
func (o *FDCAN_Type) SetILE_EINT0(value uint32) {
	volatile.StoreUint32(&o.ILE.Reg, volatile.LoadUint32(&o.ILE.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetILE_EINT0() uint32 {
	return volatile.LoadUint32(&o.ILE.Reg) & 0x1
}
func (o *FDCAN_Type) SetILE_EINT1(value uint32) {
	volatile.StoreUint32(&o.ILE.Reg, volatile.LoadUint32(&o.ILE.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetILE_EINT1() uint32 {
	return (volatile.LoadUint32(&o.ILE.Reg) & 0x2) >> 1
}

// FDCAN.RXGFC: FDCAN Global Filter Configuration Register
func (o *FDCAN_Type) SetRXGFC_RRFE(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetRXGFC_RRFE() uint32 {
	return volatile.LoadUint32(&o.RXGFC.Reg) & 0x1
}
func (o *FDCAN_Type) SetRXGFC_RRFS(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetRXGFC_RRFS() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetRXGFC_ANFE(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0xc)|value<<2)
}
func (o *FDCAN_Type) GetRXGFC_ANFE() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0xc) >> 2
}
func (o *FDCAN_Type) SetRXGFC_ANFS(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x30)|value<<4)
}
func (o *FDCAN_Type) GetRXGFC_ANFS() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x30) >> 4
}
func (o *FDCAN_Type) SetRXGFC_F1OM(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetRXGFC_F1OM() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetRXGFC_F0OM(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetRXGFC_F0OM() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetRXGFC_LSS(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x1f0000)|value<<16)
}
func (o *FDCAN_Type) GetRXGFC_LSS() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x1f0000) >> 16
}
func (o *FDCAN_Type) SetRXGFC_LSE(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0xf000000)|value<<24)
}
func (o *FDCAN_Type) GetRXGFC_LSE() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0xf000000) >> 24
}

// FDCAN.XIDAM: FDCAN Extended ID and Mask Register
func (o *FDCAN_Type) SetXIDAM_EIDM(value uint32) {
	volatile.StoreUint32(&o.XIDAM.Reg, volatile.LoadUint32(&o.XIDAM.Reg)&^(0x1fffffff)|value)
}
func (o *FDCAN_Type) GetXIDAM_EIDM() uint32 {
	return volatile.LoadUint32(&o.XIDAM.Reg) & 0x1fffffff
}

// FDCAN.HPMS: FDCAN High Priority Message Status Register
func (o *FDCAN_Type) SetHPMS_BIDX(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetHPMS_BIDX() uint32 {
	return volatile.LoadUint32(&o.HPMS.Reg) & 0x7
}
func (o *FDCAN_Type) SetHPMS_MSI(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0xc0)|value<<6)
}
func (o *FDCAN_Type) GetHPMS_MSI() uint32 {
	return (volatile.LoadUint32(&o.HPMS.Reg) & 0xc0) >> 6
}
func (o *FDCAN_Type) SetHPMS_FIDX(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0x1f00)|value<<8)
}
func (o *FDCAN_Type) GetHPMS_FIDX() uint32 {
	return (volatile.LoadUint32(&o.HPMS.Reg) & 0x1f00) >> 8
}
func (o *FDCAN_Type) SetHPMS_FLST(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetHPMS_FLST() uint32 {
	return (volatile.LoadUint32(&o.HPMS.Reg) & 0x8000) >> 15
}

// FDCAN.RXF0S: FDCAN Rx FIFO 0 Status Register
func (o *FDCAN_Type) SetRXF0S_F0FL(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetRXF0S_F0FL() uint32 {
	return volatile.LoadUint32(&o.RXF0S.Reg) & 0xf
}
func (o *FDCAN_Type) SetRXF0S_F0GI(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetRXF0S_F0GI() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetRXF0S_F0PI(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetRXF0S_F0PI() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x30000) >> 16
}
func (o *FDCAN_Type) SetRXF0S_F0F(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetRXF0S_F0F() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x1000000) >> 24
}
func (o *FDCAN_Type) SetRXF0S_RF0L(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x2000000)|value<<25)
}
func (o *FDCAN_Type) GetRXF0S_RF0L() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x2000000) >> 25
}

// FDCAN.RXF0A: CAN Rx FIFO 0 Acknowledge Register
func (o *FDCAN_Type) SetRXF0A_F0AI(value uint32) {
	volatile.StoreUint32(&o.RXF0A.Reg, volatile.LoadUint32(&o.RXF0A.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetRXF0A_F0AI() uint32 {
	return volatile.LoadUint32(&o.RXF0A.Reg) & 0x7
}

// FDCAN.RXF1S: FDCAN Rx FIFO 1 Status Register
func (o *FDCAN_Type) SetRXF1S_F1FL(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetRXF1S_F1FL() uint32 {
	return volatile.LoadUint32(&o.RXF1S.Reg) & 0xf
}
func (o *FDCAN_Type) SetRXF1S_F1GI(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetRXF1S_F1GI() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetRXF1S_F1PI(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetRXF1S_F1PI() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x30000) >> 16
}
func (o *FDCAN_Type) SetRXF1S_F1F(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetRXF1S_F1F() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x1000000) >> 24
}
func (o *FDCAN_Type) SetRXF1S_RF1L(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x2000000)|value<<25)
}
func (o *FDCAN_Type) GetRXF1S_RF1L() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x2000000) >> 25
}

// FDCAN.RXF1A: FDCAN Rx FIFO 1 Acknowledge Register
func (o *FDCAN_Type) SetRXF1A_F1AI(value uint32) {
	volatile.StoreUint32(&o.RXF1A.Reg, volatile.LoadUint32(&o.RXF1A.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetRXF1A_F1AI() uint32 {
	return volatile.LoadUint32(&o.RXF1A.Reg) & 0x7
}

// FDCAN.TXBC: FDCAN Tx buffer configuration register
func (o *FDCAN_Type) SetTXBC_TFQM(value uint32) {
	volatile.StoreUint32(&o.TXBC.Reg, volatile.LoadUint32(&o.TXBC.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetTXBC_TFQM() uint32 {
	return (volatile.LoadUint32(&o.TXBC.Reg) & 0x1000000) >> 24
}

// FDCAN.TXFQS: FDCAN Tx FIFO/Queue Status Register
func (o *FDCAN_Type) SetTXFQS_TFFL(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXFQS_TFFL() uint32 {
	return volatile.LoadUint32(&o.TXFQS.Reg) & 0x7
}
func (o *FDCAN_Type) SetTXFQS_TFGI(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetTXFQS_TFGI() uint32 {
	return (volatile.LoadUint32(&o.TXFQS.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetTXFQS_TFQPI(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetTXFQS_TFQPI() uint32 {
	return (volatile.LoadUint32(&o.TXFQS.Reg) & 0x30000) >> 16
}
func (o *FDCAN_Type) SetTXFQS_TFQF(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x200000)|value<<21)
}
func (o *FDCAN_Type) GetTXFQS_TFQF() uint32 {
	return (volatile.LoadUint32(&o.TXFQS.Reg) & 0x200000) >> 21
}

// FDCAN.TXBRP: FDCAN Tx Buffer Request Pending Register
func (o *FDCAN_Type) SetTXBRP_TRP(value uint32) {
	volatile.StoreUint32(&o.TXBRP.Reg, volatile.LoadUint32(&o.TXBRP.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBRP_TRP() uint32 {
	return volatile.LoadUint32(&o.TXBRP.Reg) & 0x7
}

// FDCAN.TXBAR: FDCAN Tx Buffer Add Request Register
func (o *FDCAN_Type) SetTXBAR_AR(value uint32) {
	volatile.StoreUint32(&o.TXBAR.Reg, volatile.LoadUint32(&o.TXBAR.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBAR_AR() uint32 {
	return volatile.LoadUint32(&o.TXBAR.Reg) & 0x7
}

// FDCAN.TXBCR: FDCAN Tx Buffer Cancellation Request Register
func (o *FDCAN_Type) SetTXBCR_CR(value uint32) {
	volatile.StoreUint32(&o.TXBCR.Reg, volatile.LoadUint32(&o.TXBCR.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBCR_CR() uint32 {
	return volatile.LoadUint32(&o.TXBCR.Reg) & 0x7
}

// FDCAN.TXBTO: FDCAN Tx Buffer Transmission Occurred Register
func (o *FDCAN_Type) SetTXBTO_TO(value uint32) {
	volatile.StoreUint32(&o.TXBTO.Reg, volatile.LoadUint32(&o.TXBTO.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBTO_TO() uint32 {
	return volatile.LoadUint32(&o.TXBTO.Reg) & 0x7
}

// FDCAN.TXBCF: FDCAN Tx Buffer Cancellation Finished Register
func (o *FDCAN_Type) SetTXBCF_CF(value uint32) {
	volatile.StoreUint32(&o.TXBCF.Reg, volatile.LoadUint32(&o.TXBCF.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBCF_CF() uint32 {
	return volatile.LoadUint32(&o.TXBCF.Reg) & 0x7
}

// FDCAN.TXBTIE: FDCAN Tx Buffer Transmission Interrupt Enable Register
func (o *FDCAN_Type) SetTXBTIE_TIE(value uint32) {
	volatile.StoreUint32(&o.TXBTIE.Reg, volatile.LoadUint32(&o.TXBTIE.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBTIE_TIE() uint32 {
	return volatile.LoadUint32(&o.TXBTIE.Reg) & 0x7
}

// FDCAN.TXBCIE: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
func (o *FDCAN_Type) SetTXBCIE_CFIE(value uint32) {
	volatile.StoreUint32(&o.TXBCIE.Reg, volatile.LoadUint32(&o.TXBCIE.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBCIE_CFIE() uint32 {
	return volatile.LoadUint32(&o.TXBCIE.Reg) & 0x7
}

// FDCAN.TXEFS: FDCAN Tx Event FIFO Status Register
func (o *FDCAN_Type) SetTXEFS_EFFL(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXEFS_EFFL() uint32 {
	return volatile.LoadUint32(&o.TXEFS.Reg) & 0x7
}
func (o *FDCAN_Type) SetTXEFS_EFGI(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetTXEFS_EFGI() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetTXEFS_EFPI(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetTXEFS_EFPI() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x30000) >> 16
}
func (o *FDCAN_Type) SetTXEFS_EFF(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetTXEFS_EFF() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x1000000) >> 24
}
func (o *FDCAN_Type) SetTXEFS_TEFL(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x2000000)|value<<25)
}
func (o *FDCAN_Type) GetTXEFS_TEFL() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x2000000) >> 25
}

// FDCAN.TXEFA: FDCAN Tx Event FIFO Acknowledge Register
func (o *FDCAN_Type) SetTXEFA_EFAI(value uint32) {
	volatile.StoreUint32(&o.TXEFA.Reg, volatile.LoadUint32(&o.TXEFA.Reg)&^(0x3)|value)
}
func (o *FDCAN_Type) GetTXEFA_EFAI() uint32 {
	return volatile.LoadUint32(&o.TXEFA.Reg) & 0x3
}

// FDCAN.CKDIV: FDCAN CFG clock divider register
func (o *FDCAN_Type) SetCKDIV_PDIV(value uint32) {
	volatile.StoreUint32(&o.CKDIV.Reg, volatile.LoadUint32(&o.CKDIV.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetCKDIV_PDIV() uint32 {
	return volatile.LoadUint32(&o.CKDIV.Reg) & 0xf
}

// Flash
type Flash_Type struct {
	ACR          volatile.Register32 // 0x0
	_            [4]byte
	NSKEYR       volatile.Register32 // 0x8
	SECKEYR      volatile.Register32 // 0xC
	OPTKEYR      volatile.Register32 // 0x10
	_            [4]byte
	PDKEY1R      volatile.Register32 // 0x18
	PDKEY2R      volatile.Register32 // 0x1C
	NSSR         volatile.Register32 // 0x20
	SECSR        volatile.Register32 // 0x24
	NSCR         volatile.Register32 // 0x28
	SECCR        volatile.Register32 // 0x2C
	ECCR         volatile.Register32 // 0x30
	OPSR         volatile.Register32 // 0x34
	_            [8]byte
	OPTR         volatile.Register32 // 0x40
	NSBOOTADD0R  volatile.Register32 // 0x44
	NSBOOTADD1R  volatile.Register32 // 0x48
	SECBOOTADD0R volatile.Register32 // 0x4C
	SECWM1R1     volatile.Register32 // 0x50
	SECWM1R2     volatile.Register32 // 0x54
	WRP1AR       volatile.Register32 // 0x58
	WRP1BR       volatile.Register32 // 0x5C
	SECWM2R1     volatile.Register32 // 0x60
	SECWM2R2     volatile.Register32 // 0x64
	WRP2AR       volatile.Register32 // 0x68
	WRP2BR       volatile.Register32 // 0x6C
	OEM1KEYR1    volatile.Register32 // 0x70
	OEM1KEYR2    volatile.Register32 // 0x74
	OEM2KEYR1    volatile.Register32 // 0x78
	OEM2KEYR2    volatile.Register32 // 0x7C
	SEC1BBR1     volatile.Register32 // 0x80
	SEC1BBR2     volatile.Register32 // 0x84
	SEC1BBR3     volatile.Register32 // 0x88
	SEC1BBR4     volatile.Register32 // 0x8C
	SEC1BBR5     volatile.Register32 // 0x90
	SEC1BBR6     volatile.Register32 // 0x94
	SEC1BBR7     volatile.Register32 // 0x98
	SEC1BBR8     volatile.Register32 // 0x9C
	SEC2BBR1     volatile.Register32 // 0xA0
	SEC2BBR2     volatile.Register32 // 0xA4
	SEC2BBR3     volatile.Register32 // 0xA8
	SEC2BBR4     volatile.Register32 // 0xAC
	SEC2BBR5     volatile.Register32 // 0xB0
	SEC2BBR6     volatile.Register32 // 0xB4
	SEC2BBR7     volatile.Register32 // 0xB8
	SEC2BBR8     volatile.Register32 // 0xBC
	SECHDPCR     volatile.Register32 // 0xC0
	PRIVCFGR     volatile.Register32 // 0xC4
	_            [8]byte
	PRIV1BBR1    volatile.Register32 // 0xD0
	PRIV1BBR2    volatile.Register32 // 0xD4
	PRIV1BBR3    volatile.Register32 // 0xD8
	PRIV1BBR4    volatile.Register32 // 0xDC
	PRIV1BBR5    volatile.Register32 // 0xE0
	PRIV1BBR6    volatile.Register32 // 0xE4
	PRIV1BBR7    volatile.Register32 // 0xE8
	PRIV1BBR8    volatile.Register32 // 0xEC
	PRIV2BBR1    volatile.Register32 // 0xF0
	PRIV2BBR2    volatile.Register32 // 0xF4
	PRIV2BBR3    volatile.Register32 // 0xF8
	PRIV2BBR4    volatile.Register32 // 0xFC
	PRIV2BBR5    volatile.Register32 // 0x100
	PRIV2BBR6    volatile.Register32 // 0x104
	PRIV2BBR7    volatile.Register32 // 0x108
	PRIV2BBR8    volatile.Register32 // 0x10C
}

// Flash.ACR: FLASH access control register
func (o *Flash_Type) SetACR_LATENCY(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0xf)|value)
}
func (o *Flash_Type) GetACR_LATENCY() uint32 {
	return volatile.LoadUint32(&o.ACR.Reg) & 0xf
}
func (o *Flash_Type) SetACR_PRFTEN(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetACR_PRFTEN() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetACR_LPM(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetACR_LPM() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetACR_PDREQ1(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetACR_PDREQ1() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetACR_PDREQ2(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetACR_PDREQ2() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetACR_SLEEP_PD(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetACR_SLEEP_PD() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x4000) >> 14
}

// Flash.NSKEYR: FLASH non-secure key register
func (o *Flash_Type) SetNSKEYR(value uint32) {
	volatile.StoreUint32(&o.NSKEYR.Reg, value)
}
func (o *Flash_Type) GetNSKEYR() uint32 {
	return volatile.LoadUint32(&o.NSKEYR.Reg)
}

// Flash.SECKEYR: FLASH secure key register
func (o *Flash_Type) SetSECKEYR(value uint32) {
	volatile.StoreUint32(&o.SECKEYR.Reg, value)
}
func (o *Flash_Type) GetSECKEYR() uint32 {
	return volatile.LoadUint32(&o.SECKEYR.Reg)
}

// Flash.OPTKEYR: FLASH option key register
func (o *Flash_Type) SetOPTKEYR(value uint32) {
	volatile.StoreUint32(&o.OPTKEYR.Reg, value)
}
func (o *Flash_Type) GetOPTKEYR() uint32 {
	return volatile.LoadUint32(&o.OPTKEYR.Reg)
}

// Flash.PDKEY1R: FLASH bank 1 power-down key register
func (o *Flash_Type) SetPDKEY1R(value uint32) {
	volatile.StoreUint32(&o.PDKEY1R.Reg, value)
}
func (o *Flash_Type) GetPDKEY1R() uint32 {
	return volatile.LoadUint32(&o.PDKEY1R.Reg)
}

// Flash.PDKEY2R: FLASH bank 2 power-down key register
func (o *Flash_Type) SetPDKEY2R(value uint32) {
	volatile.StoreUint32(&o.PDKEY2R.Reg, value)
}
func (o *Flash_Type) GetPDKEY2R() uint32 {
	return volatile.LoadUint32(&o.PDKEY2R.Reg)
}

// Flash.NSSR: FLASH non-secure status register
func (o *Flash_Type) SetNSSR_EOP(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetNSSR_EOP() uint32 {
	return volatile.LoadUint32(&o.NSSR.Reg) & 0x1
}
func (o *Flash_Type) SetNSSR_OPERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetNSSR_OPERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetNSSR_PROGERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetNSSR_PROGERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetNSSR_WRPERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetNSSR_WRPERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetNSSR_PGAERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetNSSR_PGAERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetNSSR_SIZERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetNSSR_SIZERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetNSSR_PGSERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetNSSR_PGSERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetNSSR_OPTWERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetNSSR_OPTWERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetNSSR_BSY(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetNSSR_BSY() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetNSSR_WDW(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetNSSR_WDW() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetNSSR_OEM1LOCK(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetNSSR_OEM1LOCK() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetNSSR_OEM2LOCK(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetNSSR_OEM2LOCK() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetNSSR_PD1(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetNSSR_PD1() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetNSSR_PD2(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetNSSR_PD2() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x200000) >> 21
}

// Flash.SECSR: FLASH secure status register
func (o *Flash_Type) SetSECSR_EOP(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECSR_EOP() uint32 {
	return volatile.LoadUint32(&o.SECSR.Reg) & 0x1
}
func (o *Flash_Type) SetSECSR_OPERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSECSR_OPERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSECSR_PROGERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSECSR_PROGERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSECSR_WRPERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSECSR_WRPERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSECSR_PGAERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSECSR_PGAERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSECSR_SIZERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSECSR_SIZERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSECSR_PGSERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSECSR_PGSERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSECSR_RDERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSECSR_RDERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSECSR_BSY(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSECSR_BSY() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSECSR_WDW(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSECSR_WDW() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x20000) >> 17
}

// Flash.NSCR: FLASH non-secure control register
func (o *Flash_Type) SetNSCR_PG(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetNSCR_PG() uint32 {
	return volatile.LoadUint32(&o.NSCR.Reg) & 0x1
}
func (o *Flash_Type) SetNSCR_PER(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetNSCR_PER() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetNSCR_MER1(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetNSCR_MER1() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetNSCR_PNB(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x7f8)|value<<3)
}
func (o *Flash_Type) GetNSCR_PNB() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x7f8) >> 3
}
func (o *Flash_Type) SetNSCR_BKER(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetNSCR_BKER() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetNSCR_BWR(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetNSCR_BWR() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetNSCR_MER2(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetNSCR_MER2() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetNSCR_STRT(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetNSCR_STRT() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetNSCR_OPTSTRT(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetNSCR_OPTSTRT() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetNSCR_EOPIE(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetNSCR_EOPIE() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetNSCR_ERRIE(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetNSCR_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetNSCR_OBL_LAUNCH(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetNSCR_OBL_LAUNCH() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetNSCR_OPTLOCK(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetNSCR_OPTLOCK() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetNSCR_LOCK(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetNSCR_LOCK() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x80000000) >> 31
}

// Flash.SECCR: FLASH secure control register
func (o *Flash_Type) SetSECCR_PG(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECCR_PG() uint32 {
	return volatile.LoadUint32(&o.SECCR.Reg) & 0x1
}
func (o *Flash_Type) SetSECCR_PER(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSECCR_PER() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSECCR_MER1(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSECCR_MER1() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSECCR_PNB(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x7f8)|value<<3)
}
func (o *Flash_Type) GetSECCR_PNB() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x7f8) >> 3
}
func (o *Flash_Type) SetSECCR_BKER(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSECCR_BKER() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSECCR_BWR(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSECCR_BWR() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSECCR_MER2(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSECCR_MER2() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSECCR_STRT(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSECCR_STRT() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSECCR_EOPIE(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSECCR_EOPIE() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSECCR_ERRIE(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSECCR_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSECCR_RDERRIE(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSECCR_RDERRIE() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSECCR_INV(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSECCR_INV() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSECCR_LOCK(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSECCR_LOCK() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x80000000) >> 31
}

// Flash.ECCR: FLASH ECC register
func (o *Flash_Type) SetECCR_ADDR_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x1fffff)|value)
}
func (o *Flash_Type) GetECCR_ADDR_ECC() uint32 {
	return volatile.LoadUint32(&o.ECCR.Reg) & 0x1fffff
}
func (o *Flash_Type) SetECCR_BK_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetECCR_BK_ECC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetECCR_SYSF_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetECCR_SYSF_ECC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetECCR_ECCIE(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetECCR_ECCIE() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetECCR_ECCC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetECCR_ECCC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetECCR_ECCD(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetECCR_ECCD() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x80000000) >> 31
}

// Flash.OPSR: FLASH operation status register
func (o *Flash_Type) SetOPSR_ADDR_OP(value uint32) {
	volatile.StoreUint32(&o.OPSR.Reg, volatile.LoadUint32(&o.OPSR.Reg)&^(0x1fffff)|value)
}
func (o *Flash_Type) GetOPSR_ADDR_OP() uint32 {
	return volatile.LoadUint32(&o.OPSR.Reg) & 0x1fffff
}
func (o *Flash_Type) SetOPSR_BK_OP(value uint32) {
	volatile.StoreUint32(&o.OPSR.Reg, volatile.LoadUint32(&o.OPSR.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetOPSR_BK_OP() uint32 {
	return (volatile.LoadUint32(&o.OPSR.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetOPSR_SYSF_OP(value uint32) {
	volatile.StoreUint32(&o.OPSR.Reg, volatile.LoadUint32(&o.OPSR.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetOPSR_SYSF_OP() uint32 {
	return (volatile.LoadUint32(&o.OPSR.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetOPSR_CODE_OP(value uint32) {
	volatile.StoreUint32(&o.OPSR.Reg, volatile.LoadUint32(&o.OPSR.Reg)&^(0xe0000000)|value<<29)
}
func (o *Flash_Type) GetOPSR_CODE_OP() uint32 {
	return (volatile.LoadUint32(&o.OPSR.Reg) & 0xe0000000) >> 29
}

// Flash.OPTR: FLASH option register
func (o *Flash_Type) SetOPTR_RDP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetOPTR_RDP() uint32 {
	return volatile.LoadUint32(&o.OPTR.Reg) & 0xff
}
func (o *Flash_Type) SetOPTR_BOR_LEV(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x700)|value<<8)
}
func (o *Flash_Type) GetOPTR_BOR_LEV() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x700) >> 8
}
func (o *Flash_Type) SetOPTR_NRST_STOP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetOPTR_NRST_STOP() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetOPTR_NRST_STDBY(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetOPTR_NRST_STDBY() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetOPTR_NRST_SHDW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetOPTR_NRST_SHDW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetOPTR_SRAM1345_RST(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetOPTR_SRAM1345_RST() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetOPTR_IWDG_SW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetOPTR_IWDG_SW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetOPTR_IWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetOPTR_IWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetOPTR_IWDG_STDBY(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetOPTR_IWDG_STDBY() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetOPTR_WWDG_SW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetOPTR_WWDG_SW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetOPTR_SWAP_BANK(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetOPTR_SWAP_BANK() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetOPTR_DUALBANK(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetOPTR_DUALBANK() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetOPTR_BKPRAM_ECC(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetOPTR_BKPRAM_ECC() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetOPTR_SRAM3_ECC(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetOPTR_SRAM3_ECC() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetOPTR_SRAM2_ECC(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetOPTR_SRAM2_ECC() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetOPTR_SRAM2_RST(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetOPTR_SRAM2_RST() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetOPTR_NSWBOOT0(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetOPTR_NSWBOOT0() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetOPTR_NBOOT0(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetOPTR_NBOOT0() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetOPTR_PA15_PUPEN(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetOPTR_PA15_PUPEN() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetOPTR_IO_VDD_HSLV(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetOPTR_IO_VDD_HSLV() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetOPTR_IO_VDDIO2_HSLV(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetOPTR_IO_VDDIO2_HSLV() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetOPTR_TZEN(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetOPTR_TZEN() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x80000000) >> 31
}

// Flash.NSBOOTADD0R: FLASH non-secure boot address 0 register
func (o *Flash_Type) SetNSBOOTADD0R_NSBOOTADD0(value uint32) {
	volatile.StoreUint32(&o.NSBOOTADD0R.Reg, volatile.LoadUint32(&o.NSBOOTADD0R.Reg)&^(0xffffff80)|value<<7)
}
func (o *Flash_Type) GetNSBOOTADD0R_NSBOOTADD0() uint32 {
	return (volatile.LoadUint32(&o.NSBOOTADD0R.Reg) & 0xffffff80) >> 7
}

// Flash.NSBOOTADD1R: FLASH non-secure boot address 1 register
func (o *Flash_Type) SetNSBOOTADD1R_NSBOOTADD1(value uint32) {
	volatile.StoreUint32(&o.NSBOOTADD1R.Reg, volatile.LoadUint32(&o.NSBOOTADD1R.Reg)&^(0xffffff80)|value<<7)
}
func (o *Flash_Type) GetNSBOOTADD1R_NSBOOTADD1() uint32 {
	return (volatile.LoadUint32(&o.NSBOOTADD1R.Reg) & 0xffffff80) >> 7
}

// Flash.SECBOOTADD0R: FLASH secure boot address 0 register
func (o *Flash_Type) SetSECBOOTADD0R_BOOT_LOCK(value uint32) {
	volatile.StoreUint32(&o.SECBOOTADD0R.Reg, volatile.LoadUint32(&o.SECBOOTADD0R.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECBOOTADD0R_BOOT_LOCK() uint32 {
	return volatile.LoadUint32(&o.SECBOOTADD0R.Reg) & 0x1
}
func (o *Flash_Type) SetSECBOOTADD0R_SECBOOTADD0(value uint32) {
	volatile.StoreUint32(&o.SECBOOTADD0R.Reg, volatile.LoadUint32(&o.SECBOOTADD0R.Reg)&^(0xffffff80)|value<<7)
}
func (o *Flash_Type) GetSECBOOTADD0R_SECBOOTADD0() uint32 {
	return (volatile.LoadUint32(&o.SECBOOTADD0R.Reg) & 0xffffff80) >> 7
}

// Flash.SECWM1R1: FLASH secure watermark1 register 1
func (o *Flash_Type) SetSECWM1R1_SECWM1_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM1R1.Reg, volatile.LoadUint32(&o.SECWM1R1.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetSECWM1R1_SECWM1_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM1R1.Reg) & 0xff
}
func (o *Flash_Type) SetSECWM1R1_SECWM1_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM1R1.Reg, volatile.LoadUint32(&o.SECWM1R1.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetSECWM1R1_SECWM1_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R1.Reg) & 0xff0000) >> 16
}

// Flash.SECWM1R2: FLASH secure watermark1 register 2
func (o *Flash_Type) SetSECWM1R2_PCROP1_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetSECWM1R2_PCROP1_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM1R2.Reg) & 0xff
}
func (o *Flash_Type) SetSECWM1R2_PCROP1EN(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSECWM1R2_PCROP1EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSECWM1R2_HDP1_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetSECWM1R2_HDP1_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R2.Reg) & 0xff0000) >> 16
}
func (o *Flash_Type) SetSECWM1R2_HDP1EN(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSECWM1R2_HDP1EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R2.Reg) & 0x80000000) >> 31
}

// Flash.WRP1AR: FLASH WRP1 area A address register
func (o *Flash_Type) SetWRP1AR_WRP1A_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP1AR.Reg, volatile.LoadUint32(&o.WRP1AR.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetWRP1AR_WRP1A_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP1AR.Reg) & 0xff
}
func (o *Flash_Type) SetWRP1AR_WRP1A_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP1AR.Reg, volatile.LoadUint32(&o.WRP1AR.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetWRP1AR_WRP1A_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP1AR.Reg) & 0xff0000) >> 16
}
func (o *Flash_Type) SetWRP1AR_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.WRP1AR.Reg, volatile.LoadUint32(&o.WRP1AR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetWRP1AR_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.WRP1AR.Reg) & 0x80000000) >> 31
}

// Flash.WRP1BR: FLASH WRP1 area B address register
func (o *Flash_Type) SetWRP1BR_WRP1B_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP1BR.Reg, volatile.LoadUint32(&o.WRP1BR.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetWRP1BR_WRP1B_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP1BR.Reg) & 0xff
}
func (o *Flash_Type) SetWRP1BR_WRP1B_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP1BR.Reg, volatile.LoadUint32(&o.WRP1BR.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetWRP1BR_WRP1B_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP1BR.Reg) & 0xff0000) >> 16
}
func (o *Flash_Type) SetWRP1BR_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.WRP1BR.Reg, volatile.LoadUint32(&o.WRP1BR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetWRP1BR_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.WRP1BR.Reg) & 0x80000000) >> 31
}

// Flash.SECWM2R1: FLASH secure watermark2 register 1
func (o *Flash_Type) SetSECWM2R1_SECWM2_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM2R1.Reg, volatile.LoadUint32(&o.SECWM2R1.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetSECWM2R1_SECWM2_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM2R1.Reg) & 0xff
}
func (o *Flash_Type) SetSECWM2R1_SECWM2_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM2R1.Reg, volatile.LoadUint32(&o.SECWM2R1.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetSECWM2R1_SECWM2_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R1.Reg) & 0xff0000) >> 16
}

// Flash.SECWM2R2: FLASH secure watermark2 register 2
func (o *Flash_Type) SetSECWM2R2_PCROP2_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetSECWM2R2_PCROP2_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM2R2.Reg) & 0xff
}
func (o *Flash_Type) SetSECWM2R2_PCROP2EN(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSECWM2R2_PCROP2EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSECWM2R2_HDP2_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetSECWM2R2_HDP2_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R2.Reg) & 0xff0000) >> 16
}
func (o *Flash_Type) SetSECWM2R2_HDP2EN(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSECWM2R2_HDP2EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R2.Reg) & 0x80000000) >> 31
}

// Flash.WRP2AR: FLASH WPR2 area A address register
func (o *Flash_Type) SetWRP2AR_WRP2A_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP2AR.Reg, volatile.LoadUint32(&o.WRP2AR.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetWRP2AR_WRP2A_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP2AR.Reg) & 0xff
}
func (o *Flash_Type) SetWRP2AR_WRP2A_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP2AR.Reg, volatile.LoadUint32(&o.WRP2AR.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetWRP2AR_WRP2A_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP2AR.Reg) & 0xff0000) >> 16
}
func (o *Flash_Type) SetWRP2AR_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.WRP2AR.Reg, volatile.LoadUint32(&o.WRP2AR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetWRP2AR_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.WRP2AR.Reg) & 0x80000000) >> 31
}

// Flash.WRP2BR: FLASH WPR2 area B address register
func (o *Flash_Type) SetWRP2BR_WRP2B_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP2BR.Reg, volatile.LoadUint32(&o.WRP2BR.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetWRP2BR_WRP2B_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP2BR.Reg) & 0xff
}
func (o *Flash_Type) SetWRP2BR_WRP2B_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP2BR.Reg, volatile.LoadUint32(&o.WRP2BR.Reg)&^(0xff0000)|value<<16)
}
func (o *Flash_Type) GetWRP2BR_WRP2B_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP2BR.Reg) & 0xff0000) >> 16
}
func (o *Flash_Type) SetWRP2BR_UNLOCK(value uint32) {
	volatile.StoreUint32(&o.WRP2BR.Reg, volatile.LoadUint32(&o.WRP2BR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetWRP2BR_UNLOCK() uint32 {
	return (volatile.LoadUint32(&o.WRP2BR.Reg) & 0x80000000) >> 31
}

// Flash.OEM1KEYR1: FLASH OEM1 key register 1
func (o *Flash_Type) SetOEM1KEYR1(value uint32) {
	volatile.StoreUint32(&o.OEM1KEYR1.Reg, value)
}
func (o *Flash_Type) GetOEM1KEYR1() uint32 {
	return volatile.LoadUint32(&o.OEM1KEYR1.Reg)
}

// Flash.OEM1KEYR2: FLASH OEM1 key register 2
func (o *Flash_Type) SetOEM1KEYR2(value uint32) {
	volatile.StoreUint32(&o.OEM1KEYR2.Reg, value)
}
func (o *Flash_Type) GetOEM1KEYR2() uint32 {
	return volatile.LoadUint32(&o.OEM1KEYR2.Reg)
}

// Flash.OEM2KEYR1: FLASH OEM2 key register 1
func (o *Flash_Type) SetOEM2KEYR1(value uint32) {
	volatile.StoreUint32(&o.OEM2KEYR1.Reg, value)
}
func (o *Flash_Type) GetOEM2KEYR1() uint32 {
	return volatile.LoadUint32(&o.OEM2KEYR1.Reg)
}

// Flash.OEM2KEYR2: FLASH OEM2 key register 2
func (o *Flash_Type) SetOEM2KEYR2(value uint32) {
	volatile.StoreUint32(&o.OEM2KEYR2.Reg, value)
}
func (o *Flash_Type) GetOEM2KEYR2() uint32 {
	return volatile.LoadUint32(&o.OEM2KEYR2.Reg)
}

// Flash.SEC1BBR1: FLASH secure block based bank 1 register 1
func (o *Flash_Type) SetSEC1BBR1_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR1_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR1.Reg, volatile.LoadUint32(&o.SEC1BBR1.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR1_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR1.Reg) & 0x80000000) >> 31
}

// Flash.SEC1BBR2: FLASH secure block based bank 1 register 2
func (o *Flash_Type) SetSEC1BBR2_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR2_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR2.Reg, volatile.LoadUint32(&o.SEC1BBR2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR2_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR2.Reg) & 0x80000000) >> 31
}

// Flash.SEC1BBR3: FLASH secure block based bank 1 register 3
func (o *Flash_Type) SetSEC1BBR3_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR3_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR3.Reg, volatile.LoadUint32(&o.SEC1BBR3.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR3_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR3.Reg) & 0x80000000) >> 31
}

// Flash.SEC1BBR4: FLASH secure block based bank 1 register 4
func (o *Flash_Type) SetSEC1BBR4_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR4_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR4.Reg, volatile.LoadUint32(&o.SEC1BBR4.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR4_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR4.Reg) & 0x80000000) >> 31
}

// Flash.SEC1BBR5: FLASH secure block based bank 1 register 5
func (o *Flash_Type) SetSEC1BBR5_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR5_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR5.Reg, volatile.LoadUint32(&o.SEC1BBR5.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR5_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR5.Reg) & 0x80000000) >> 31
}

// Flash.SEC1BBR6: FLASH secure block based bank 1 register 6
func (o *Flash_Type) SetSEC1BBR6_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR6_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR6.Reg, volatile.LoadUint32(&o.SEC1BBR6.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR6_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR6.Reg) & 0x80000000) >> 31
}

// Flash.SEC1BBR7: FLASH secure block based bank 1 register 7
func (o *Flash_Type) SetSEC1BBR7_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR7_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR7.Reg, volatile.LoadUint32(&o.SEC1BBR7.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR7_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR7.Reg) & 0x80000000) >> 31
}

// Flash.SEC1BBR8: FLASH secure block based bank 1 register 8
func (o *Flash_Type) SetSEC1BBR8_SEC1BB0(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB0() uint32 {
	return volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x1
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB1(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB2(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB3(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB4(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB5(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB6(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB7(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB8(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB9(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB10(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB11(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB12(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB13(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB14(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB15(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB16(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB17(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB18(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB19(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB20(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB21(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB22(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB23(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB24(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB25(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB26(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB27(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB28(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB29(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB30(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC1BBR8_SEC1BB31(value uint32) {
	volatile.StoreUint32(&o.SEC1BBR8.Reg, volatile.LoadUint32(&o.SEC1BBR8.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC1BBR8_SEC1BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC1BBR8.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR1: FLASH secure block based bank 2 register 1
func (o *Flash_Type) SetSEC2BBR1_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR1_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR1.Reg, volatile.LoadUint32(&o.SEC2BBR1.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR1_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR1.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR2: FLASH secure block based bank 2 register 2
func (o *Flash_Type) SetSEC2BBR2_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR2_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR2.Reg, volatile.LoadUint32(&o.SEC2BBR2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR2_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR2.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR3: FLASH secure block based bank 2 register 3
func (o *Flash_Type) SetSEC2BBR3_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR3_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR3.Reg, volatile.LoadUint32(&o.SEC2BBR3.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR3_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR3.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR4: FLASH secure block based bank 2 register 4
func (o *Flash_Type) SetSEC2BBR4_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR4_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR4.Reg, volatile.LoadUint32(&o.SEC2BBR4.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR4_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR4.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR5: FLASH secure block based bank 2 register 5
func (o *Flash_Type) SetSEC2BBR5_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR5_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR5.Reg, volatile.LoadUint32(&o.SEC2BBR5.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR5_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR5.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR6: FLASH secure block based bank 2 register 6
func (o *Flash_Type) SetSEC2BBR6_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR6_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR6.Reg, volatile.LoadUint32(&o.SEC2BBR6.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR6_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR6.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR7: FLASH secure block based bank 2 register 7
func (o *Flash_Type) SetSEC2BBR7_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR7_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR7.Reg, volatile.LoadUint32(&o.SEC2BBR7.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR7_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR7.Reg) & 0x80000000) >> 31
}

// Flash.SEC2BBR8: FLASH secure block based bank 2 register 8
func (o *Flash_Type) SetSEC2BBR8_SEC2BB0(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB0() uint32 {
	return volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x1
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB1(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB1() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB2(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB2() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB3(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB3() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB4(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB4() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB5(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB5() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB6(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB6() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB7(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB7() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB8(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB8() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB9(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB9() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB10(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB10() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB11(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB11() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB12(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB12() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB13(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB13() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB14(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB14() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB15(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB15() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB16(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB16() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB17(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB17() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB18(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB18() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB19(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB19() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB20(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB20() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB21(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB21() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB22(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB22() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB23(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB23() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB24(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB24() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB25(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB25() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB26(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB26() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB27(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB27() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB28(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB28() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB29(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB29() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB30(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB30() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetSEC2BBR8_SEC2BB31(value uint32) {
	volatile.StoreUint32(&o.SEC2BBR8.Reg, volatile.LoadUint32(&o.SEC2BBR8.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSEC2BBR8_SEC2BB31() uint32 {
	return (volatile.LoadUint32(&o.SEC2BBR8.Reg) & 0x80000000) >> 31
}

// Flash.SECHDPCR: FLASH secure HDP control register
func (o *Flash_Type) SetSECHDPCR_HDP1_ACCDIS(value uint32) {
	volatile.StoreUint32(&o.SECHDPCR.Reg, volatile.LoadUint32(&o.SECHDPCR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECHDPCR_HDP1_ACCDIS() uint32 {
	return volatile.LoadUint32(&o.SECHDPCR.Reg) & 0x1
}
func (o *Flash_Type) SetSECHDPCR_HDP2_ACCDIS(value uint32) {
	volatile.StoreUint32(&o.SECHDPCR.Reg, volatile.LoadUint32(&o.SECHDPCR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSECHDPCR_HDP2_ACCDIS() uint32 {
	return (volatile.LoadUint32(&o.SECHDPCR.Reg) & 0x2) >> 1
}

// Flash.PRIVCFGR: FLASH privilege configuration register
func (o *Flash_Type) SetPRIVCFGR_SPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIVCFGR_SPRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x1
}
func (o *Flash_Type) SetPRIVCFGR_NSPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIVCFGR_NSPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x2) >> 1
}

// Flash.PRIV1BBR1: FLASH privilege block based bank 1 register 1
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR1_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR1.Reg, volatile.LoadUint32(&o.PRIV1BBR1.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR1_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR1.Reg) & 0x80000000) >> 31
}

// Flash.PRIV1BBR2: FLASH privilege block based bank 1 register 2
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR2_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR2.Reg, volatile.LoadUint32(&o.PRIV1BBR2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR2_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR2.Reg) & 0x80000000) >> 31
}

// Flash.PRIV1BBR3: FLASH privilege block based bank 1 register 3
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR3_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR3.Reg, volatile.LoadUint32(&o.PRIV1BBR3.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR3_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR3.Reg) & 0x80000000) >> 31
}

// Flash.PRIV1BBR4: FLASH privilege block based bank 1 register 4
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR4_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR4.Reg, volatile.LoadUint32(&o.PRIV1BBR4.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR4_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR4.Reg) & 0x80000000) >> 31
}

// Flash.PRIV1BBR5: FLASH privilege block based bank 1 register 5
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR5_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR5.Reg, volatile.LoadUint32(&o.PRIV1BBR5.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR5_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR5.Reg) & 0x80000000) >> 31
}

// Flash.PRIV1BBR6: FLASH privilege block based bank 1 register 6
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR6_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR6.Reg, volatile.LoadUint32(&o.PRIV1BBR6.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR6_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR6.Reg) & 0x80000000) >> 31
}

// Flash.PRIV1BBR7: FLASH privilege block based bank 1 register 7
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR7_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR7.Reg, volatile.LoadUint32(&o.PRIV1BBR7.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR7_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR7.Reg) & 0x80000000) >> 31
}

// Flash.PRIV1BBR8: FLASH privilege block based bank 1 register 8
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV1BBR8_PRIV1BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV1BBR8.Reg, volatile.LoadUint32(&o.PRIV1BBR8.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV1BBR8_PRIV1BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV1BBR8.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR1: FLASH privilege block based bank 2 register 1
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR1_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR1.Reg, volatile.LoadUint32(&o.PRIV2BBR1.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR1_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR1.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR2: FLASH privilege block based bank 2 register 2
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR2_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR2.Reg, volatile.LoadUint32(&o.PRIV2BBR2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR2_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR2.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR3: FLASH privilege block based bank 2 register 3
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR3_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR3.Reg, volatile.LoadUint32(&o.PRIV2BBR3.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR3_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR3.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR4: FLASH privilege block based bank 2 register 4
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR4_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR4.Reg, volatile.LoadUint32(&o.PRIV2BBR4.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR4_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR4.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR5: FLASH privilege block based bank 2 register 5
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR5_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR5.Reg, volatile.LoadUint32(&o.PRIV2BBR5.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR5_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR5.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR6: FLASH privilege block based bank 2 register 6
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR6_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR6.Reg, volatile.LoadUint32(&o.PRIV2BBR6.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR6_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR6.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR7: FLASH privilege block based bank 2 register 7
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR7_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR7.Reg, volatile.LoadUint32(&o.PRIV2BBR7.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR7_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR7.Reg) & 0x80000000) >> 31
}

// Flash.PRIV2BBR8: FLASH privilege block based bank 2 register 8
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB0(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB0() uint32 {
	return volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x1
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB1(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB1() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB2(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB2() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB3(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB3() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB4(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB4() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB5(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB5() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB6(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB6() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB7(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB7() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB8(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x100)|value<<8)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB8() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x100) >> 8
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB9(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x200)|value<<9)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB9() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x200) >> 9
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB10(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x400)|value<<10)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB10() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x400) >> 10
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB11(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB11() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB12(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB12() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB13(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB13() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB14(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB14() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB15(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB15() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB16(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB16() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB17(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB17() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB18(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB18() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB19(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB19() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB20(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB20() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB21(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB21() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB22(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB22() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB23(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x800000)|value<<23)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB23() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x800000) >> 23
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB24(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB24() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB25(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB25() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB26(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB26() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB27(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB27() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB28(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB28() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB29(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB29() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB30(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB30() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetPRIV2BBR8_PRIV2BB31(value uint32) {
	volatile.StoreUint32(&o.PRIV2BBR8.Reg, volatile.LoadUint32(&o.PRIV2BBR8.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetPRIV2BBR8_PRIV2BB31() uint32 {
	return (volatile.LoadUint32(&o.PRIV2BBR8.Reg) & 0x80000000) >> 31
}

// Filter Math Accelerator
type FMAC_Type struct {
	X1BUFCFG volatile.Register32 // 0x0
	X2BUFCFG volatile.Register32 // 0x4
	YBUFCFG  volatile.Register32 // 0x8
	PARAM    volatile.Register32 // 0xC
	CR       volatile.Register32 // 0x10
	SR       volatile.Register32 // 0x14
	WDATA    volatile.Register32 // 0x18
	RDATA    volatile.Register32 // 0x1C
}

// FMAC.X1BUFCFG: FMAC X1 Buffer Configuration register
func (o *FMAC_Type) SetX1BUFCFG_X1_BASE(value uint32) {
	volatile.StoreUint32(&o.X1BUFCFG.Reg, volatile.LoadUint32(&o.X1BUFCFG.Reg)&^(0xff)|value)
}
func (o *FMAC_Type) GetX1BUFCFG_X1_BASE() uint32 {
	return volatile.LoadUint32(&o.X1BUFCFG.Reg) & 0xff
}
func (o *FMAC_Type) SetX1BUFCFG_X1_BUF_SIZE(value uint32) {
	volatile.StoreUint32(&o.X1BUFCFG.Reg, volatile.LoadUint32(&o.X1BUFCFG.Reg)&^(0xff00)|value<<8)
}
func (o *FMAC_Type) GetX1BUFCFG_X1_BUF_SIZE() uint32 {
	return (volatile.LoadUint32(&o.X1BUFCFG.Reg) & 0xff00) >> 8
}
func (o *FMAC_Type) SetX1BUFCFG_FULL_WM(value uint32) {
	volatile.StoreUint32(&o.X1BUFCFG.Reg, volatile.LoadUint32(&o.X1BUFCFG.Reg)&^(0x3000000)|value<<24)
}
func (o *FMAC_Type) GetX1BUFCFG_FULL_WM() uint32 {
	return (volatile.LoadUint32(&o.X1BUFCFG.Reg) & 0x3000000) >> 24
}

// FMAC.X2BUFCFG: FMAC X2 Buffer Configuration register
func (o *FMAC_Type) SetX2BUFCFG_X2_BASE(value uint32) {
	volatile.StoreUint32(&o.X2BUFCFG.Reg, volatile.LoadUint32(&o.X2BUFCFG.Reg)&^(0xff)|value)
}
func (o *FMAC_Type) GetX2BUFCFG_X2_BASE() uint32 {
	return volatile.LoadUint32(&o.X2BUFCFG.Reg) & 0xff
}
func (o *FMAC_Type) SetX2BUFCFG_X2_BUF_SIZE(value uint32) {
	volatile.StoreUint32(&o.X2BUFCFG.Reg, volatile.LoadUint32(&o.X2BUFCFG.Reg)&^(0xff00)|value<<8)
}
func (o *FMAC_Type) GetX2BUFCFG_X2_BUF_SIZE() uint32 {
	return (volatile.LoadUint32(&o.X2BUFCFG.Reg) & 0xff00) >> 8
}

// FMAC.YBUFCFG: FMAC Y Buffer Configuration register
func (o *FMAC_Type) SetYBUFCFG_Y_BASE(value uint32) {
	volatile.StoreUint32(&o.YBUFCFG.Reg, volatile.LoadUint32(&o.YBUFCFG.Reg)&^(0xff)|value)
}
func (o *FMAC_Type) GetYBUFCFG_Y_BASE() uint32 {
	return volatile.LoadUint32(&o.YBUFCFG.Reg) & 0xff
}
func (o *FMAC_Type) SetYBUFCFG_Y_BUF_SIZE(value uint32) {
	volatile.StoreUint32(&o.YBUFCFG.Reg, volatile.LoadUint32(&o.YBUFCFG.Reg)&^(0xff00)|value<<8)
}
func (o *FMAC_Type) GetYBUFCFG_Y_BUF_SIZE() uint32 {
	return (volatile.LoadUint32(&o.YBUFCFG.Reg) & 0xff00) >> 8
}
func (o *FMAC_Type) SetYBUFCFG_EMPTY_WM(value uint32) {
	volatile.StoreUint32(&o.YBUFCFG.Reg, volatile.LoadUint32(&o.YBUFCFG.Reg)&^(0x3000000)|value<<24)
}
func (o *FMAC_Type) GetYBUFCFG_EMPTY_WM() uint32 {
	return (volatile.LoadUint32(&o.YBUFCFG.Reg) & 0x3000000) >> 24
}

// FMAC.PARAM: FMAC Parameter register
func (o *FMAC_Type) SetPARAM_START(value uint32) {
	volatile.StoreUint32(&o.PARAM.Reg, volatile.LoadUint32(&o.PARAM.Reg)&^(0x80000000)|value<<31)
}
func (o *FMAC_Type) GetPARAM_START() uint32 {
	return (volatile.LoadUint32(&o.PARAM.Reg) & 0x80000000) >> 31
}
func (o *FMAC_Type) SetPARAM_FUNC(value uint32) {
	volatile.StoreUint32(&o.PARAM.Reg, volatile.LoadUint32(&o.PARAM.Reg)&^(0x7f000000)|value<<24)
}
func (o *FMAC_Type) GetPARAM_FUNC() uint32 {
	return (volatile.LoadUint32(&o.PARAM.Reg) & 0x7f000000) >> 24
}
func (o *FMAC_Type) SetPARAM_R(value uint32) {
	volatile.StoreUint32(&o.PARAM.Reg, volatile.LoadUint32(&o.PARAM.Reg)&^(0xff0000)|value<<16)
}
func (o *FMAC_Type) GetPARAM_R() uint32 {
	return (volatile.LoadUint32(&o.PARAM.Reg) & 0xff0000) >> 16
}
func (o *FMAC_Type) SetPARAM_Q(value uint32) {
	volatile.StoreUint32(&o.PARAM.Reg, volatile.LoadUint32(&o.PARAM.Reg)&^(0xff00)|value<<8)
}
func (o *FMAC_Type) GetPARAM_Q() uint32 {
	return (volatile.LoadUint32(&o.PARAM.Reg) & 0xff00) >> 8
}
func (o *FMAC_Type) SetPARAM_P(value uint32) {
	volatile.StoreUint32(&o.PARAM.Reg, volatile.LoadUint32(&o.PARAM.Reg)&^(0xff)|value)
}
func (o *FMAC_Type) GetPARAM_P() uint32 {
	return volatile.LoadUint32(&o.PARAM.Reg) & 0xff
}

// FMAC.CR: FMAC Control register
func (o *FMAC_Type) SetCR_RESET(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *FMAC_Type) GetCR_RESET() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *FMAC_Type) SetCR_CLIPEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *FMAC_Type) GetCR_CLIPEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *FMAC_Type) SetCR_DMAWEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *FMAC_Type) GetCR_DMAWEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *FMAC_Type) SetCR_DMAREN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *FMAC_Type) GetCR_DMAREN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *FMAC_Type) SetCR_SATIEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *FMAC_Type) GetCR_SATIEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *FMAC_Type) SetCR_UNFLIEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *FMAC_Type) GetCR_UNFLIEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *FMAC_Type) SetCR_OVFLIEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *FMAC_Type) GetCR_OVFLIEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *FMAC_Type) SetCR_WIEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *FMAC_Type) GetCR_WIEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *FMAC_Type) SetCR_RIEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *FMAC_Type) GetCR_RIEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// FMAC.SR: FMAC Status register
func (o *FMAC_Type) SetSR_YEMPTY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *FMAC_Type) GetSR_YEMPTY() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *FMAC_Type) SetSR_X1FULL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *FMAC_Type) GetSR_X1FULL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *FMAC_Type) SetSR_OVFL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *FMAC_Type) GetSR_OVFL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *FMAC_Type) SetSR_UNFL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *FMAC_Type) GetSR_UNFL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *FMAC_Type) SetSR_SAT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *FMAC_Type) GetSR_SAT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}

// FMAC.WDATA: FMAC Write Data register
func (o *FMAC_Type) SetWDATA(value uint32) {
	volatile.StoreUint32(&o.WDATA.Reg, volatile.LoadUint32(&o.WDATA.Reg)&^(0xffff)|value)
}
func (o *FMAC_Type) GetWDATA() uint32 {
	return volatile.LoadUint32(&o.WDATA.Reg) & 0xffff
}

// FMAC.RDATA: FMAC Read Data register
func (o *FMAC_Type) SetRDATA(value uint32) {
	volatile.StoreUint32(&o.RDATA.Reg, volatile.LoadUint32(&o.RDATA.Reg)&^(0xffff)|value)
}
func (o *FMAC_Type) GetRDATA() uint32 {
	return volatile.LoadUint32(&o.RDATA.Reg) & 0xffff
}

// FMC
type FMC_Type struct {
	BCR1    volatile.Register32 // 0x0
	BTR1    volatile.Register32 // 0x4
	BCR2    volatile.Register32 // 0x8
	BTR2    volatile.Register32 // 0xC
	BCR3    volatile.Register32 // 0x10
	BTR3    volatile.Register32 // 0x14
	BCR4    volatile.Register32 // 0x18
	BTR4    volatile.Register32 // 0x1C
	PCSCNTR volatile.Register32 // 0x20
	_       [92]byte
	PCR     volatile.Register32 // 0x80
	SR      volatile.Register32 // 0x84
	PMEM    volatile.Register32 // 0x88
	PATT    volatile.Register32 // 0x8C
	_       [4]byte
	ECCR    volatile.Register32 // 0x94
	_       [108]byte
	BWTR1   volatile.Register32 // 0x104
	_       [4]byte
	BWTR2   volatile.Register32 // 0x10C
	_       [4]byte
	BWTR3   volatile.Register32 // 0x114
	_       [4]byte
	BWTR4   volatile.Register32 // 0x11C
}

// FMC.BCR1: SRAM/NOR-Flash chip-select control register for bank 1
func (o *FMC_Type) SetBCR1_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR1_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR1.Reg) & 0x1
}
func (o *FMC_Type) SetBCR1_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR1_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR1_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR1_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR1_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR1_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR1_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR1_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR1_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR1_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR1_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR1_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR1_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR1_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR1_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR1_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR1_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR1_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR1_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR1_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR1_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR1_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR1_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR1_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR1_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR1_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR1_CCLKEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x100000)|value<<20)
}
func (o *FMC_Type) GetBCR1_CCLKEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x100000) >> 20
}
func (o *FMC_Type) SetBCR1_WFDIS(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x200000)|value<<21)
}
func (o *FMC_Type) GetBCR1_WFDIS() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x200000) >> 21
}
func (o *FMC_Type) SetBCR1_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR1_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0xc00000) >> 22
}
func (o *FMC_Type) SetBCR1_FMCEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x80000000)|value<<31)
}
func (o *FMC_Type) GetBCR1_FMCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x80000000) >> 31
}

// FMC.BTR1: SRAM/NOR-Flash chip-select timing register for bank %s
func (o *FMC_Type) SetBTR1_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR1_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR1.Reg) & 0xf
}
func (o *FMC_Type) SetBTR1_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR1_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR1_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR1_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR1_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR1_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR1_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR1_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR1_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR1_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR1_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR1_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR1_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR1_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xc0000000) >> 30
}

// FMC.BCR2: SRAM/NOR-Flash chip-select control register for bank %s
func (o *FMC_Type) SetBCR2_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR2_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR2.Reg) & 0x1
}
func (o *FMC_Type) SetBCR2_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR2_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR2_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR2_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR2_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR2_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR2_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR2_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR2_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR2_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR2_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR2_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR2_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR2_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR2_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR2_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR2_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR2_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR2_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR2_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR2_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR2_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR2_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR2_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR2_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR2_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR2_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR2_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0xc00000) >> 22
}

// FMC.BTR2: SRAM/NOR-Flash chip-select timing register for bank %s
func (o *FMC_Type) SetBTR2_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR2_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR2.Reg) & 0xf
}
func (o *FMC_Type) SetBTR2_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR2_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR2_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR2_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR2_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR2_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR2_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR2_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR2_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR2_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR2_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR2_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR2_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR2_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xc0000000) >> 30
}

// FMC.BCR3: SRAM/NOR-Flash chip-select control register for bank %s
func (o *FMC_Type) SetBCR3_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR3_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR3.Reg) & 0x1
}
func (o *FMC_Type) SetBCR3_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR3_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR3_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR3_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR3_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR3_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR3_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR3_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR3_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR3_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR3_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR3_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR3_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR3_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR3_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR3_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR3_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR3_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR3_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR3_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR3_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR3_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR3_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR3_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR3_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR3_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR3_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR3_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0xc00000) >> 22
}

// FMC.BTR3: SRAM/NOR-Flash chip-select timing register for bank %s
func (o *FMC_Type) SetBTR3_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR3_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR3.Reg) & 0xf
}
func (o *FMC_Type) SetBTR3_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR3_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR3_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR3_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR3_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR3_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR3_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR3_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR3_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR3_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR3_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR3_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR3_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR3_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xc0000000) >> 30
}

// FMC.BCR4: SRAM/NOR-Flash chip-select control register for bank %s
func (o *FMC_Type) SetBCR4_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR4_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR4.Reg) & 0x1
}
func (o *FMC_Type) SetBCR4_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR4_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR4_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR4_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR4_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR4_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR4_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR4_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR4_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR4_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR4_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR4_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR4_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR4_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR4_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR4_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR4_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR4_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR4_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR4_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR4_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR4_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR4_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR4_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR4_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR4_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR4_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR4_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0xc00000) >> 22
}

// FMC.BTR4: SRAM/NOR-Flash chip-select timing register for bank %s
func (o *FMC_Type) SetBTR4_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR4_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR4.Reg) & 0xf
}
func (o *FMC_Type) SetBTR4_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR4_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR4_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR4_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR4_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR4_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR4_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR4_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR4_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR4_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR4_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR4_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR4_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR4_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xc0000000) >> 30
}

// FMC.PCSCNTR: PSRAM chip select counter register
func (o *FMC_Type) SetPCSCNTR_CSCOUNT(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0xffff)|value)
}
func (o *FMC_Type) GetPCSCNTR_CSCOUNT() uint32 {
	return volatile.LoadUint32(&o.PCSCNTR.Reg) & 0xffff
}
func (o *FMC_Type) SetPCSCNTR_CNTB1EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x20000)|value<<17)
}
func (o *FMC_Type) GetPCSCNTR_CNTB1EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x20000) >> 17
}
func (o *FMC_Type) SetPCSCNTR_CNTB2EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x40000)|value<<18)
}
func (o *FMC_Type) GetPCSCNTR_CNTB2EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x40000) >> 18
}
func (o *FMC_Type) SetPCSCNTR_CNTB3EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetPCSCNTR_CNTB3EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetPCSCNTR_CNTB4EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x100000)|value<<20)
}
func (o *FMC_Type) GetPCSCNTR_CNTB4EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x100000) >> 20
}

// FMC.PCR: NAND Flash control registers
func (o *FMC_Type) SetPCR_PWAITEN(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetPCR_PWAITEN() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetPCR_PBKEN(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x4)|value<<2)
}
func (o *FMC_Type) GetPCR_PBKEN() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x4) >> 2
}
func (o *FMC_Type) SetPCR_PTYP(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x8)|value<<3)
}
func (o *FMC_Type) GetPCR_PTYP() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x8) >> 3
}
func (o *FMC_Type) SetPCR_PWID(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetPCR_PWID() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetPCR_ECCEN(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetPCR_ECCEN() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetPCR_TCLR(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x1e00)|value<<9)
}
func (o *FMC_Type) GetPCR_TCLR() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x1e00) >> 9
}
func (o *FMC_Type) SetPCR_TAR(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x1e000)|value<<13)
}
func (o *FMC_Type) GetPCR_TAR() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x1e000) >> 13
}
func (o *FMC_Type) SetPCR_ECCPS(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0xe0000)|value<<17)
}
func (o *FMC_Type) GetPCR_ECCPS() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0xe0000) >> 17
}

// FMC.SR: status and interrupt register
func (o *FMC_Type) SetSR_IRS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetSR_IRS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *FMC_Type) SetSR_ILS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetSR_ILS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetSR_IFS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *FMC_Type) GetSR_IFS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *FMC_Type) SetSR_IREN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *FMC_Type) GetSR_IREN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *FMC_Type) SetSR_ILEN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *FMC_Type) GetSR_ILEN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *FMC_Type) SetSR_IFEN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *FMC_Type) GetSR_IFEN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *FMC_Type) SetSR_FEMPT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetSR_FEMPT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}

// FMC.PMEM: Common memory space timing register
func (o *FMC_Type) SetPMEM_MEMSET(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff)|value)
}
func (o *FMC_Type) GetPMEM_MEMSET() uint32 {
	return volatile.LoadUint32(&o.PMEM.Reg) & 0xff
}
func (o *FMC_Type) SetPMEM_MEMWAIT(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetPMEM_MEMWAIT() uint32 {
	return (volatile.LoadUint32(&o.PMEM.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetPMEM_MEMHOLD(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff0000)|value<<16)
}
func (o *FMC_Type) GetPMEM_MEMHOLD() uint32 {
	return (volatile.LoadUint32(&o.PMEM.Reg) & 0xff0000) >> 16
}
func (o *FMC_Type) SetPMEM_MEMHIZ(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff000000)|value<<24)
}
func (o *FMC_Type) GetPMEM_MEMHIZ() uint32 {
	return (volatile.LoadUint32(&o.PMEM.Reg) & 0xff000000) >> 24
}

// FMC.PATT: The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
func (o *FMC_Type) SetPATT_ATTSET(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff)|value)
}
func (o *FMC_Type) GetPATT_ATTSET() uint32 {
	return volatile.LoadUint32(&o.PATT.Reg) & 0xff
}
func (o *FMC_Type) SetPATT_ATTWAIT(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetPATT_ATTWAIT() uint32 {
	return (volatile.LoadUint32(&o.PATT.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetPATT_ATTHOLD(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff0000)|value<<16)
}
func (o *FMC_Type) GetPATT_ATTHOLD() uint32 {
	return (volatile.LoadUint32(&o.PATT.Reg) & 0xff0000) >> 16
}
func (o *FMC_Type) SetPATT_ATTHIZ(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff000000)|value<<24)
}
func (o *FMC_Type) GetPATT_ATTHIZ() uint32 {
	return (volatile.LoadUint32(&o.PATT.Reg) & 0xff000000) >> 24
}

// FMC.ECCR: This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
func (o *FMC_Type) SetECCR(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, value)
}
func (o *FMC_Type) GetECCR() uint32 {
	return volatile.LoadUint32(&o.ECCR.Reg)
}

// FMC.BWTR1: SRAM/NOR-Flash write timing registers %s
func (o *FMC_Type) SetBWTR1_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR1_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR1.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR1_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR1_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR1_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR1_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR1_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR1_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR1_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR1_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBWTR1_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBWTR1_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0xc0000000) >> 30
}

// FMC.BWTR2: SRAM/NOR-Flash write timing registers %s
func (o *FMC_Type) SetBWTR2_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR2_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR2.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR2_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR2_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR2_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR2_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR2_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR2_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR2_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR2_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBWTR2_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBWTR2_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0xc0000000) >> 30
}

// FMC.BWTR3: SRAM/NOR-Flash write timing registers %s
func (o *FMC_Type) SetBWTR3_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR3_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR3.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR3_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR3_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR3_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR3_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR3_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR3_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR3_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR3_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBWTR3_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBWTR3_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0xc0000000) >> 30
}

// FMC.BWTR4: SRAM/NOR-Flash write timing registers %s
func (o *FMC_Type) SetBWTR4_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR4_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR4.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR4_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR4_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR4_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR4_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR4_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR4_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR4_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR4_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBWTR4_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBWTR4_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0xc0000000) >> 30
}

// GPDMA1
type GPDMA_Type struct {
	SECCFGR  volatile.Register32 // 0x0
	PRIVCFGR volatile.Register32 // 0x4
	_        [4]byte
	MISR     volatile.Register32 // 0xC
	SMISR    volatile.Register32 // 0x10
	_        [60]byte
	CH       [12]GPDMA_CH_Type  // 0x50
	CH2D     [4]GPDMA_CH2D_Type // 0x650
}

// GPDMA.SECCFGR: GPDMA secure configuration register
func (o *GPDMA_Type) SetSECCFGR_SEC0(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *GPDMA_Type) GetSECCFGR_SEC0() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *GPDMA_Type) SetSECCFGR_SEC1(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *GPDMA_Type) GetSECCFGR_SEC1() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *GPDMA_Type) SetSECCFGR_SEC2(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *GPDMA_Type) GetSECCFGR_SEC2() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *GPDMA_Type) SetSECCFGR_SEC3(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *GPDMA_Type) GetSECCFGR_SEC3() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}
func (o *GPDMA_Type) SetSECCFGR_SEC4(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x20)|value<<5)
}
func (o *GPDMA_Type) GetSECCFGR_SEC4() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x20) >> 5
}
func (o *GPDMA_Type) SetSECCFGR_SEC5(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x40)|value<<6)
}
func (o *GPDMA_Type) GetSECCFGR_SEC5() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x40) >> 6
}
func (o *GPDMA_Type) SetSECCFGR_SEC6(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x80)|value<<7)
}
func (o *GPDMA_Type) GetSECCFGR_SEC6() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x80) >> 7
}
func (o *GPDMA_Type) SetSECCFGR_SEC7(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x100)|value<<8)
}
func (o *GPDMA_Type) GetSECCFGR_SEC7() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x100) >> 8
}
func (o *GPDMA_Type) SetSECCFGR_SEC8(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_Type) GetSECCFGR_SEC8() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x200) >> 9
}
func (o *GPDMA_Type) SetSECCFGR_SEC9(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_Type) GetSECCFGR_SEC9() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x400) >> 10
}
func (o *GPDMA_Type) SetSECCFGR_SEC10(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_Type) GetSECCFGR_SEC10() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x800) >> 11
}
func (o *GPDMA_Type) SetSECCFGR_SEC11(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *GPDMA_Type) GetSECCFGR_SEC11() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1000) >> 12
}
func (o *GPDMA_Type) SetSECCFGR_SEC12(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_Type) GetSECCFGR_SEC12() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2000) >> 13
}
func (o *GPDMA_Type) SetSECCFGR_SEC13(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4000)|value<<14)
}
func (o *GPDMA_Type) GetSECCFGR_SEC13() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4000) >> 14
}
func (o *GPDMA_Type) SetSECCFGR_SEC14(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8000)|value<<15)
}
func (o *GPDMA_Type) GetSECCFGR_SEC14() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8000) >> 15
}
func (o *GPDMA_Type) SetSECCFGR_SEC15(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10000)|value<<16)
}
func (o *GPDMA_Type) GetSECCFGR_SEC15() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10000) >> 16
}

// GPDMA.PRIVCFGR: GPDMA privileged configuration register
func (o *GPDMA_Type) SetPRIVCFGR_PRIV0(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x2)|value<<1)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV0() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x2) >> 1
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV1(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x4)|value<<2)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV1() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x4) >> 2
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV2(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x8)|value<<3)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV2() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x8) >> 3
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV3(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x10)|value<<4)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV3() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x10) >> 4
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV4(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x20)|value<<5)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV4() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x20) >> 5
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV5(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x40)|value<<6)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV5() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x40) >> 6
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV6(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x80)|value<<7)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV6() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x80) >> 7
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV7(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x100)|value<<8)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV7() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x100) >> 8
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV8(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV8() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x200) >> 9
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV9(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV9() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x400) >> 10
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV10(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV10() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x800) >> 11
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV11(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV11() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x1000) >> 12
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV12(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV12() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x2000) >> 13
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV13(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x4000)|value<<14)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV13() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x4000) >> 14
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV14(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x8000)|value<<15)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV14() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x8000) >> 15
}
func (o *GPDMA_Type) SetPRIVCFGR_PRIV15(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x10000)|value<<16)
}
func (o *GPDMA_Type) GetPRIVCFGR_PRIV15() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x10000) >> 16
}

// GPDMA.MISR: non-secure masked interrupt status register
func (o *GPDMA_Type) SetMISR_MIS0(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *GPDMA_Type) GetMISR_MIS0() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *GPDMA_Type) SetMISR_MIS1(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *GPDMA_Type) GetMISR_MIS1() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *GPDMA_Type) SetMISR_MIS2(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8)|value<<3)
}
func (o *GPDMA_Type) GetMISR_MIS2() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8) >> 3
}
func (o *GPDMA_Type) SetMISR_MIS3(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10)|value<<4)
}
func (o *GPDMA_Type) GetMISR_MIS3() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10) >> 4
}
func (o *GPDMA_Type) SetMISR_MIS4(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20)|value<<5)
}
func (o *GPDMA_Type) GetMISR_MIS4() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20) >> 5
}
func (o *GPDMA_Type) SetMISR_MIS5(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x40)|value<<6)
}
func (o *GPDMA_Type) GetMISR_MIS5() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x40) >> 6
}
func (o *GPDMA_Type) SetMISR_MIS6(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x80)|value<<7)
}
func (o *GPDMA_Type) GetMISR_MIS6() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x80) >> 7
}
func (o *GPDMA_Type) SetMISR_MIS7(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x100)|value<<8)
}
func (o *GPDMA_Type) GetMISR_MIS7() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x100) >> 8
}
func (o *GPDMA_Type) SetMISR_MIS8(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_Type) GetMISR_MIS8() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x200) >> 9
}
func (o *GPDMA_Type) SetMISR_MIS9(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_Type) GetMISR_MIS9() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x400) >> 10
}
func (o *GPDMA_Type) SetMISR_MIS10(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_Type) GetMISR_MIS10() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x800) >> 11
}
func (o *GPDMA_Type) SetMISR_MIS11(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x1000)|value<<12)
}
func (o *GPDMA_Type) GetMISR_MIS11() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x1000) >> 12
}
func (o *GPDMA_Type) SetMISR_MIS12(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_Type) GetMISR_MIS12() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2000) >> 13
}
func (o *GPDMA_Type) SetMISR_MIS13(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4000)|value<<14)
}
func (o *GPDMA_Type) GetMISR_MIS13() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4000) >> 14
}
func (o *GPDMA_Type) SetMISR_MIS14(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8000)|value<<15)
}
func (o *GPDMA_Type) GetMISR_MIS14() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8000) >> 15
}
func (o *GPDMA_Type) SetMISR_MIS15(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10000)|value<<16)
}
func (o *GPDMA_Type) GetMISR_MIS15() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10000) >> 16
}

// GPDMA.SMISR: secure masked interrupt status register
func (o *GPDMA_Type) SetSMISR_MIS0(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x2)|value<<1)
}
func (o *GPDMA_Type) GetSMISR_MIS0() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x2) >> 1
}
func (o *GPDMA_Type) SetSMISR_MIS1(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4)|value<<2)
}
func (o *GPDMA_Type) GetSMISR_MIS1() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4) >> 2
}
func (o *GPDMA_Type) SetSMISR_MIS2(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8)|value<<3)
}
func (o *GPDMA_Type) GetSMISR_MIS2() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8) >> 3
}
func (o *GPDMA_Type) SetSMISR_MIS3(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10)|value<<4)
}
func (o *GPDMA_Type) GetSMISR_MIS3() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10) >> 4
}
func (o *GPDMA_Type) SetSMISR_MIS4(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x20)|value<<5)
}
func (o *GPDMA_Type) GetSMISR_MIS4() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x20) >> 5
}
func (o *GPDMA_Type) SetSMISR_MIS5(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x40)|value<<6)
}
func (o *GPDMA_Type) GetSMISR_MIS5() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x40) >> 6
}
func (o *GPDMA_Type) SetSMISR_MIS6(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x80)|value<<7)
}
func (o *GPDMA_Type) GetSMISR_MIS6() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x80) >> 7
}
func (o *GPDMA_Type) SetSMISR_MIS7(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x100)|value<<8)
}
func (o *GPDMA_Type) GetSMISR_MIS7() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x100) >> 8
}
func (o *GPDMA_Type) SetSMISR_MIS8(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_Type) GetSMISR_MIS8() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x200) >> 9
}
func (o *GPDMA_Type) SetSMISR_MIS9(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_Type) GetSMISR_MIS9() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x400) >> 10
}
func (o *GPDMA_Type) SetSMISR_MIS10(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_Type) GetSMISR_MIS10() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x800) >> 11
}
func (o *GPDMA_Type) SetSMISR_MIS11(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x1000)|value<<12)
}
func (o *GPDMA_Type) GetSMISR_MIS11() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x1000) >> 12
}
func (o *GPDMA_Type) SetSMISR_MIS12(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_Type) GetSMISR_MIS12() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x2000) >> 13
}
func (o *GPDMA_Type) SetSMISR_MIS13(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4000)|value<<14)
}
func (o *GPDMA_Type) GetSMISR_MIS13() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4000) >> 14
}
func (o *GPDMA_Type) SetSMISR_MIS14(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8000)|value<<15)
}
func (o *GPDMA_Type) GetSMISR_MIS14() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8000) >> 15
}
func (o *GPDMA_Type) SetSMISR_MIS15(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10000)|value<<16)
}
func (o *GPDMA_Type) GetSMISR_MIS15() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10000) >> 16
}

// Channel cluster
type GPDMA_CH_Type struct {
	LBAR volatile.Register32 // 0x50
	_    [8]byte
	FCR  volatile.Register32 // 0x5C
	SR   volatile.Register32 // 0x60
	CR   volatile.Register32 // 0x64
	_    [40]byte
	TR1  volatile.Register32 // 0x90
	TR2  volatile.Register32 // 0x94
	BR1  volatile.Register32 // 0x98
	SAR  volatile.Register32 // 0x9C
	DAR  volatile.Register32 // 0xA0
	_    [40]byte
	LLR  volatile.Register32 // 0xCC
}

// GPDMA_CH.LBAR: channel x linked-list base address register
func (o *GPDMA_CH_Type) SetLBAR_LBA(value uint32) {
	volatile.StoreUint32(&o.LBAR.Reg, volatile.LoadUint32(&o.LBAR.Reg)&^(0xffff0000)|value<<16)
}
func (o *GPDMA_CH_Type) GetLBAR_LBA() uint32 {
	return (volatile.LoadUint32(&o.LBAR.Reg) & 0xffff0000) >> 16
}

// GPDMA_CH.FCR: GPDMA channel x flag clear register
func (o *GPDMA_CH_Type) SetFCR_TCF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x100)|value<<8)
}
func (o *GPDMA_CH_Type) GetFCR_TCF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x100) >> 8
}
func (o *GPDMA_CH_Type) SetFCR_HTF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_CH_Type) GetFCR_HTF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x200) >> 9
}
func (o *GPDMA_CH_Type) SetFCR_DTEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_CH_Type) GetFCR_DTEF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x400) >> 10
}
func (o *GPDMA_CH_Type) SetFCR_ULEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_CH_Type) GetFCR_ULEF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x800) >> 11
}
func (o *GPDMA_CH_Type) SetFCR_USEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x1000)|value<<12)
}
func (o *GPDMA_CH_Type) GetFCR_USEF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x1000) >> 12
}
func (o *GPDMA_CH_Type) SetFCR_SUSPF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_CH_Type) GetFCR_SUSPF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x2000) >> 13
}
func (o *GPDMA_CH_Type) SetFCR_TOF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x4000)|value<<14)
}
func (o *GPDMA_CH_Type) GetFCR_TOF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x4000) >> 14
}

// GPDMA_CH.SR: channel x status register
func (o *GPDMA_CH_Type) SetSR_IDLEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *GPDMA_CH_Type) GetSR_IDLEF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *GPDMA_CH_Type) SetSR_TCF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *GPDMA_CH_Type) GetSR_TCF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *GPDMA_CH_Type) SetSR_HTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_CH_Type) GetSR_HTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *GPDMA_CH_Type) SetSR_DTEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_CH_Type) GetSR_DTEF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *GPDMA_CH_Type) SetSR_ULEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_CH_Type) GetSR_ULEF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *GPDMA_CH_Type) SetSR_USEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *GPDMA_CH_Type) GetSR_USEF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *GPDMA_CH_Type) SetSR_SUSPF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_CH_Type) GetSR_SUSPF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *GPDMA_CH_Type) SetSR_FIFOL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xff0000)|value<<16)
}
func (o *GPDMA_CH_Type) GetSR_FIFOL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0xff0000) >> 16
}

// GPDMA_CH.CR: channel x control register
func (o *GPDMA_CH_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *GPDMA_CH_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *GPDMA_CH_Type) SetCR_RESET(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *GPDMA_CH_Type) GetCR_RESET() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *GPDMA_CH_Type) SetCR_SUSP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *GPDMA_CH_Type) GetCR_SUSP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *GPDMA_CH_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *GPDMA_CH_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *GPDMA_CH_Type) SetCR_HTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_CH_Type) GetCR_HTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *GPDMA_CH_Type) SetCR_DTEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_CH_Type) GetCR_DTEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *GPDMA_CH_Type) SetCR_ULEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_CH_Type) GetCR_ULEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *GPDMA_CH_Type) SetCR_USEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *GPDMA_CH_Type) GetCR_USEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *GPDMA_CH_Type) SetCR_SUSPIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_CH_Type) GetCR_SUSPIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *GPDMA_CH_Type) SetCR_LSM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *GPDMA_CH_Type) GetCR_LSM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *GPDMA_CH_Type) SetCR_LAP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *GPDMA_CH_Type) GetCR_LAP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *GPDMA_CH_Type) SetCR_PRIO(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPDMA_CH_Type) GetCR_PRIO() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00000) >> 22
}

// GPDMA_CH.TR1: GPDMA channel x transfer register 1
func (o *GPDMA_CH_Type) SetTR1_SDW_LOG2(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x3)|value)
}
func (o *GPDMA_CH_Type) GetTR1_SDW_LOG2() uint32 {
	return volatile.LoadUint32(&o.TR1.Reg) & 0x3
}
func (o *GPDMA_CH_Type) SetTR1_SINC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x8)|value<<3)
}
func (o *GPDMA_CH_Type) GetTR1_SINC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x8) >> 3
}
func (o *GPDMA_CH_Type) SetTR1_SBL_1(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x3f0)|value<<4)
}
func (o *GPDMA_CH_Type) GetTR1_SBL_1() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x3f0) >> 4
}
func (o *GPDMA_CH_Type) SetTR1_PAM(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x1800)|value<<11)
}
func (o *GPDMA_CH_Type) GetTR1_PAM() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x1800) >> 11
}
func (o *GPDMA_CH_Type) SetTR1_SBX(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x2000)|value<<13)
}
func (o *GPDMA_CH_Type) GetTR1_SBX() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x2000) >> 13
}
func (o *GPDMA_CH_Type) SetTR1_SAP(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x4000)|value<<14)
}
func (o *GPDMA_CH_Type) GetTR1_SAP() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x4000) >> 14
}
func (o *GPDMA_CH_Type) SetTR1_SSEC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x8000)|value<<15)
}
func (o *GPDMA_CH_Type) GetTR1_SSEC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x8000) >> 15
}
func (o *GPDMA_CH_Type) SetTR1_DDW_LOG2(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x30000)|value<<16)
}
func (o *GPDMA_CH_Type) GetTR1_DDW_LOG2() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x30000) >> 16
}
func (o *GPDMA_CH_Type) SetTR1_DINC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x80000)|value<<19)
}
func (o *GPDMA_CH_Type) GetTR1_DINC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x80000) >> 19
}
func (o *GPDMA_CH_Type) SetTR1_DBL_1(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x3f00000)|value<<20)
}
func (o *GPDMA_CH_Type) GetTR1_DBL_1() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x3f00000) >> 20
}
func (o *GPDMA_CH_Type) SetTR1_DBX(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x4000000)|value<<26)
}
func (o *GPDMA_CH_Type) GetTR1_DBX() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x4000000) >> 26
}
func (o *GPDMA_CH_Type) SetTR1_DHX(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x8000000)|value<<27)
}
func (o *GPDMA_CH_Type) GetTR1_DHX() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x8000000) >> 27
}
func (o *GPDMA_CH_Type) SetTR1_DAP(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x40000000)|value<<30)
}
func (o *GPDMA_CH_Type) GetTR1_DAP() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x40000000) >> 30
}
func (o *GPDMA_CH_Type) SetTR1_DSEC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x80000000)|value<<31)
}
func (o *GPDMA_CH_Type) GetTR1_DSEC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x80000000) >> 31
}

// GPDMA_CH.TR2: GPDMA channel x transfer register 2
func (o *GPDMA_CH_Type) SetTR2_REQSEL(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x7f)|value)
}
func (o *GPDMA_CH_Type) GetTR2_REQSEL() uint32 {
	return volatile.LoadUint32(&o.TR2.Reg) & 0x7f
}
func (o *GPDMA_CH_Type) SetTR2_SWREQ(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x200)|value<<9)
}
func (o *GPDMA_CH_Type) GetTR2_SWREQ() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x200) >> 9
}
func (o *GPDMA_CH_Type) SetTR2_DREQ(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x400)|value<<10)
}
func (o *GPDMA_CH_Type) GetTR2_DREQ() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x400) >> 10
}
func (o *GPDMA_CH_Type) SetTR2_BREQ(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x800)|value<<11)
}
func (o *GPDMA_CH_Type) GetTR2_BREQ() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x800) >> 11
}
func (o *GPDMA_CH_Type) SetTR2_TRIGM(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0xc000)|value<<14)
}
func (o *GPDMA_CH_Type) GetTR2_TRIGM() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0xc000) >> 14
}
func (o *GPDMA_CH_Type) SetTR2_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x3f0000)|value<<16)
}
func (o *GPDMA_CH_Type) GetTR2_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x3f0000) >> 16
}
func (o *GPDMA_CH_Type) SetTR2_TRIGPOL(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x3000000)|value<<24)
}
func (o *GPDMA_CH_Type) GetTR2_TRIGPOL() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x3000000) >> 24
}
func (o *GPDMA_CH_Type) SetTR2_TCEM(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPDMA_CH_Type) GetTR2_TCEM() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0xc0000000) >> 30
}

// GPDMA_CH.BR1: GPDMA channel x block register 1
func (o *GPDMA_CH_Type) SetBR1_BNDT(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0xffff)|value)
}
func (o *GPDMA_CH_Type) GetBR1_BNDT() uint32 {
	return volatile.LoadUint32(&o.BR1.Reg) & 0xffff
}

// GPDMA_CH.SAR: GPDMA channel x source address register
func (o *GPDMA_CH_Type) SetSAR(value uint32) {
	volatile.StoreUint32(&o.SAR.Reg, value)
}
func (o *GPDMA_CH_Type) GetSAR() uint32 {
	return volatile.LoadUint32(&o.SAR.Reg)
}

// GPDMA_CH.DAR: GPDMA channel x destination address register
func (o *GPDMA_CH_Type) SetDAR(value uint32) {
	volatile.StoreUint32(&o.DAR.Reg, value)
}
func (o *GPDMA_CH_Type) GetDAR() uint32 {
	return volatile.LoadUint32(&o.DAR.Reg)
}

// GPDMA_CH.LLR: GPDMA channel x linked-list address register
func (o *GPDMA_CH_Type) SetLLR_LA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0xfffc)|value<<2)
}
func (o *GPDMA_CH_Type) GetLLR_LA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0xfffc) >> 2
}
func (o *GPDMA_CH_Type) SetLLR_ULL(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x10000)|value<<16)
}
func (o *GPDMA_CH_Type) GetLLR_ULL() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x10000) >> 16
}
func (o *GPDMA_CH_Type) SetLLR_UDA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x8000000)|value<<27)
}
func (o *GPDMA_CH_Type) GetLLR_UDA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x8000000) >> 27
}
func (o *GPDMA_CH_Type) SetLLR_USA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x10000000)|value<<28)
}
func (o *GPDMA_CH_Type) GetLLR_USA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x10000000) >> 28
}
func (o *GPDMA_CH_Type) SetLLR_UB1(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x20000000)|value<<29)
}
func (o *GPDMA_CH_Type) GetLLR_UB1() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x20000000) >> 29
}
func (o *GPDMA_CH_Type) SetLLR_UT2(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x40000000)|value<<30)
}
func (o *GPDMA_CH_Type) GetLLR_UT2() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x40000000) >> 30
}
func (o *GPDMA_CH_Type) SetLLR_UT1(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPDMA_CH_Type) GetLLR_UT1() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x80000000) >> 31
}

// Extended channel cluster
type GPDMA_CH2D_Type struct {
	LBAR volatile.Register32 // 0x650
	_    [8]byte
	FCR  volatile.Register32 // 0x65C
	SR   volatile.Register32 // 0x660
	CR   volatile.Register32 // 0x664
	_    [40]byte
	TR1  volatile.Register32 // 0x690
	TR2  volatile.Register32 // 0x694
	BR1  volatile.Register32 // 0x698
	SAR  volatile.Register32 // 0x69C
	DAR  volatile.Register32 // 0x6A0
	TR3  volatile.Register32 // 0x6A4
	BR2  volatile.Register32 // 0x6A8
	_    [32]byte
	LLR  volatile.Register32 // 0x6CC
}

// GPDMA_CH2D.BR1: GPDMA channel x block register 1
func (o *GPDMA_CH2D_Type) SetBR1_BNDT(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0xffff)|value)
}
func (o *GPDMA_CH2D_Type) GetBR1_BNDT() uint32 {
	return volatile.LoadUint32(&o.BR1.Reg) & 0xffff
}
func (o *GPDMA_CH2D_Type) SetBR1_BRC(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0x7ff0000)|value<<16)
}
func (o *GPDMA_CH2D_Type) GetBR1_BRC() uint32 {
	return (volatile.LoadUint32(&o.BR1.Reg) & 0x7ff0000) >> 16
}
func (o *GPDMA_CH2D_Type) SetBR1_SDEC(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0x10000000)|value<<28)
}
func (o *GPDMA_CH2D_Type) GetBR1_SDEC() uint32 {
	return (volatile.LoadUint32(&o.BR1.Reg) & 0x10000000) >> 28
}
func (o *GPDMA_CH2D_Type) SetBR1_DDEC(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0x20000000)|value<<29)
}
func (o *GPDMA_CH2D_Type) GetBR1_DDEC() uint32 {
	return (volatile.LoadUint32(&o.BR1.Reg) & 0x20000000) >> 29
}
func (o *GPDMA_CH2D_Type) SetBR1_BRSDEC(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0x40000000)|value<<30)
}
func (o *GPDMA_CH2D_Type) GetBR1_BRSDEC() uint32 {
	return (volatile.LoadUint32(&o.BR1.Reg) & 0x40000000) >> 30
}
func (o *GPDMA_CH2D_Type) SetBR1_BRDDEC(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0x80000000)|value<<31)
}
func (o *GPDMA_CH2D_Type) GetBR1_BRDDEC() uint32 {
	return (volatile.LoadUint32(&o.BR1.Reg) & 0x80000000) >> 31
}

// GPDMA_CH2D.TR3: GPDMA channel x transfer register 3
func (o *GPDMA_CH2D_Type) SetTR3_SAO(value uint32) {
	volatile.StoreUint32(&o.TR3.Reg, volatile.LoadUint32(&o.TR3.Reg)&^(0x1fff)|value)
}
func (o *GPDMA_CH2D_Type) GetTR3_SAO() uint32 {
	return volatile.LoadUint32(&o.TR3.Reg) & 0x1fff
}
func (o *GPDMA_CH2D_Type) SetTR3_DAO(value uint32) {
	volatile.StoreUint32(&o.TR3.Reg, volatile.LoadUint32(&o.TR3.Reg)&^(0x1fff0000)|value<<16)
}
func (o *GPDMA_CH2D_Type) GetTR3_DAO() uint32 {
	return (volatile.LoadUint32(&o.TR3.Reg) & 0x1fff0000) >> 16
}

// GPDMA_CH2D.BR2: GPDMA channel x block register 2
func (o *GPDMA_CH2D_Type) SetBR2_BRSAO(value uint32) {
	volatile.StoreUint32(&o.BR2.Reg, volatile.LoadUint32(&o.BR2.Reg)&^(0xffff)|value)
}
func (o *GPDMA_CH2D_Type) GetBR2_BRSAO() uint32 {
	return volatile.LoadUint32(&o.BR2.Reg) & 0xffff
}
func (o *GPDMA_CH2D_Type) SetBR2_BRDAO(value uint32) {
	volatile.StoreUint32(&o.BR2.Reg, volatile.LoadUint32(&o.BR2.Reg)&^(0xffff0000)|value<<16)
}
func (o *GPDMA_CH2D_Type) GetBR2_BRDAO() uint32 {
	return (volatile.LoadUint32(&o.BR2.Reg) & 0xffff0000) >> 16
}

// GPDMA_CH2D.LLR: GPDMA channel x linked-list address register
func (o *GPDMA_CH2D_Type) SetLLR_LA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0xfffc)|value<<2)
}
func (o *GPDMA_CH2D_Type) GetLLR_LA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0xfffc) >> 2
}
func (o *GPDMA_CH2D_Type) SetLLR_ULL(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x10000)|value<<16)
}
func (o *GPDMA_CH2D_Type) GetLLR_ULL() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x10000) >> 16
}
func (o *GPDMA_CH2D_Type) SetLLR_UB2(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x2000000)|value<<25)
}
func (o *GPDMA_CH2D_Type) GetLLR_UB2() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x2000000) >> 25
}
func (o *GPDMA_CH2D_Type) SetLLR_UT3(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x4000000)|value<<26)
}
func (o *GPDMA_CH2D_Type) GetLLR_UT3() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x4000000) >> 26
}
func (o *GPDMA_CH2D_Type) SetLLR_UDA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x8000000)|value<<27)
}
func (o *GPDMA_CH2D_Type) GetLLR_UDA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x8000000) >> 27
}
func (o *GPDMA_CH2D_Type) SetLLR_USA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x10000000)|value<<28)
}
func (o *GPDMA_CH2D_Type) GetLLR_USA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x10000000) >> 28
}
func (o *GPDMA_CH2D_Type) SetLLR_UB1(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x20000000)|value<<29)
}
func (o *GPDMA_CH2D_Type) GetLLR_UB1() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x20000000) >> 29
}
func (o *GPDMA_CH2D_Type) SetLLR_UT2(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x40000000)|value<<30)
}
func (o *GPDMA_CH2D_Type) GetLLR_UT2() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x40000000) >> 30
}
func (o *GPDMA_CH2D_Type) SetLLR_UT1(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPDMA_CH2D_Type) GetLLR_UT1() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x80000000) >> 31
}

// General-purpose I/Os
type GPIO_Type struct {
	MODER   volatile.Register32 // 0x0
	OTYPER  volatile.Register32 // 0x4
	OSPEEDR volatile.Register32 // 0x8
	PUPDR   volatile.Register32 // 0xC
	IDR     volatile.Register32 // 0x10
	ODR     volatile.Register32 // 0x14
	BSRR    volatile.Register32 // 0x18
	LCKR    volatile.Register32 // 0x1C
	AFRL    volatile.Register32 // 0x20
	AFRH    volatile.Register32 // 0x24
	BRR     volatile.Register32 // 0x28
	HSLVR   volatile.Register32 // 0x2C
	SECCFGR volatile.Register32 // 0x30
}

// GPIO.MODER: GPIO port mode register
func (o *GPIO_Type) SetMODER_MODE0(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetMODER_MODE0() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetMODER_MODE1(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetMODER_MODE1() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetMODER_MODE2(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetMODER_MODE2() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetMODER_MODE3(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetMODER_MODE3() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetMODER_MODE4(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetMODER_MODE4() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetMODER_MODE5(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetMODER_MODE5() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetMODER_MODE6(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetMODER_MODE6() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetMODER_MODE7(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetMODER_MODE7() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetMODER_MODE8(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetMODER_MODE8() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetMODER_MODE9(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetMODER_MODE9() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetMODER_MODE10(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetMODER_MODE10() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetMODER_MODE11(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetMODER_MODE11() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetMODER_MODE12(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetMODER_MODE12() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetMODER_MODE13(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetMODER_MODE13() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetMODER_MODE14(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetMODER_MODE14() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetMODER_MODE15(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetMODER_MODE15() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x0) >> 32
}

// GPIO.OTYPER: GPIO port output type register
func (o *GPIO_Type) SetOTYPER_OT0(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetOTYPER_OT0() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetOTYPER_OT1(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetOTYPER_OT1() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetOTYPER_OT2(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetOTYPER_OT2() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetOTYPER_OT3(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetOTYPER_OT3() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetOTYPER_OT4(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetOTYPER_OT4() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetOTYPER_OT5(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetOTYPER_OT5() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetOTYPER_OT6(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetOTYPER_OT6() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetOTYPER_OT7(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetOTYPER_OT7() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetOTYPER_OT8(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetOTYPER_OT8() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetOTYPER_OT9(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetOTYPER_OT9() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetOTYPER_OT10(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetOTYPER_OT10() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetOTYPER_OT11(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetOTYPER_OT11() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetOTYPER_OT12(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetOTYPER_OT12() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetOTYPER_OT13(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetOTYPER_OT13() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetOTYPER_OT14(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetOTYPER_OT14() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetOTYPER_OT15(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetOTYPER_OT15() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x10000) >> 16
}

// GPIO.OSPEEDR: GPIO port output speed register
func (o *GPIO_Type) SetOSPEEDR_OSPEED0(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED0() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED1(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED1() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED2(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED2() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED3(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED3() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED4(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED4() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED5(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED5() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED6(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED6() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED7(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED7() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED8(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED8() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED9(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED9() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED10(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED10() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED11(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED11() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED12(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED12() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED13(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED13() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED14(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED14() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetOSPEEDR_OSPEED15(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEED15() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x0) >> 32
}

// GPIO.PUPDR: GPIO port pull-up/pull-down register
func (o *GPIO_Type) SetPUPDR_PUPD0(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetPUPDR_PUPD0() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetPUPDR_PUPD1(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetPUPDR_PUPD1() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetPUPDR_PUPD2(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetPUPDR_PUPD2() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetPUPDR_PUPD3(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetPUPDR_PUPD3() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetPUPDR_PUPD4(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetPUPDR_PUPD4() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetPUPDR_PUPD5(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetPUPDR_PUPD5() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetPUPDR_PUPD6(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetPUPDR_PUPD6() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetPUPDR_PUPD7(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetPUPDR_PUPD7() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetPUPDR_PUPD8(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetPUPDR_PUPD8() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetPUPDR_PUPD9(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetPUPDR_PUPD9() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetPUPDR_PUPD10(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetPUPDR_PUPD10() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetPUPDR_PUPD11(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetPUPDR_PUPD11() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetPUPDR_PUPD12(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetPUPDR_PUPD12() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetPUPDR_PUPD13(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetPUPDR_PUPD13() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetPUPDR_PUPD14(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetPUPDR_PUPD14() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetPUPDR_PUPD15(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetPUPDR_PUPD15() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x0) >> 32
}

// GPIO.IDR: GPIO port input data register
func (o *GPIO_Type) SetIDR_ID0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetIDR_ID0() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetIDR_ID1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetIDR_ID1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetIDR_ID2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetIDR_ID2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetIDR_ID3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetIDR_ID3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetIDR_ID4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetIDR_ID4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetIDR_ID5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetIDR_ID5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetIDR_ID6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetIDR_ID6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetIDR_ID7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetIDR_ID7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetIDR_ID8(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetIDR_ID8() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetIDR_ID9(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetIDR_ID9() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetIDR_ID10(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetIDR_ID10() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetIDR_ID11(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetIDR_ID11() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetIDR_ID12(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetIDR_ID12() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetIDR_ID13(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetIDR_ID13() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetIDR_ID14(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetIDR_ID14() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetIDR_ID15(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetIDR_ID15() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}

// GPIO.ODR: GPIO port output data register
func (o *GPIO_Type) SetODR_OD0(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetODR_OD0() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetODR_OD1(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetODR_OD1() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetODR_OD2(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetODR_OD2() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetODR_OD3(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetODR_OD3() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetODR_OD4(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetODR_OD4() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetODR_OD5(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetODR_OD5() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetODR_OD6(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetODR_OD6() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetODR_OD7(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetODR_OD7() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetODR_OD8(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetODR_OD8() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetODR_OD9(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetODR_OD9() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetODR_OD10(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetODR_OD10() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetODR_OD11(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetODR_OD11() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetODR_OD12(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetODR_OD12() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetODR_OD13(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetODR_OD13() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetODR_OD14(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetODR_OD14() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetODR_OD15(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetODR_OD15() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10000) >> 16
}

// GPIO.BSRR: GPIO port bit set/reset register
func (o *GPIO_Type) SetBSRR_BS0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBSRR_BS0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBSRR_BS1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBSRR_BS1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBSRR_BS2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBSRR_BS2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBSRR_BS3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBSRR_BS3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBSRR_BS4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBSRR_BS4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBSRR_BS5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBSRR_BS5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBSRR_BS6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBSRR_BS6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBSRR_BS7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBSRR_BS7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBSRR_BS8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBSRR_BS8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBSRR_BS9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBSRR_BS9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBSRR_BS10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBSRR_BS10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBSRR_BS11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBSRR_BS11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetBSRR_BS12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetBSRR_BS12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetBSRR_BS13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetBSRR_BS13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetBSRR_BS14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetBSRR_BS14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetBSRR_BS15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetBSRR_BS15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000) >> 16
}
func (o *GPIO_Type) SetBSRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000)|value<<17)
}
func (o *GPIO_Type) GetBSRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000) >> 17
}
func (o *GPIO_Type) SetBSRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000)|value<<18)
}
func (o *GPIO_Type) GetBSRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000) >> 18
}
func (o *GPIO_Type) SetBSRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000)|value<<19)
}
func (o *GPIO_Type) GetBSRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000) >> 19
}
func (o *GPIO_Type) SetBSRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100000)|value<<20)
}
func (o *GPIO_Type) GetBSRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100000) >> 20
}
func (o *GPIO_Type) SetBSRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200000)|value<<21)
}
func (o *GPIO_Type) GetBSRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200000) >> 21
}
func (o *GPIO_Type) SetBSRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400000)|value<<22)
}
func (o *GPIO_Type) GetBSRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400000) >> 22
}
func (o *GPIO_Type) SetBSRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800000)|value<<23)
}
func (o *GPIO_Type) GetBSRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800000) >> 23
}
func (o *GPIO_Type) SetBSRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIO_Type) GetBSRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000000) >> 24
}
func (o *GPIO_Type) SetBSRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000000)|value<<25)
}
func (o *GPIO_Type) GetBSRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000000) >> 25
}
func (o *GPIO_Type) SetBSRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000000)|value<<26)
}
func (o *GPIO_Type) GetBSRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000000) >> 26
}
func (o *GPIO_Type) SetBSRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000000)|value<<27)
}
func (o *GPIO_Type) GetBSRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000000) >> 27
}
func (o *GPIO_Type) SetBSRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000000)|value<<28)
}
func (o *GPIO_Type) GetBSRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000000) >> 28
}
func (o *GPIO_Type) SetBSRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000000)|value<<29)
}
func (o *GPIO_Type) GetBSRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000000) >> 29
}
func (o *GPIO_Type) SetBSRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000000)|value<<30)
}
func (o *GPIO_Type) GetBSRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000000) >> 30
}
func (o *GPIO_Type) SetBSRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPIO_Type) GetBSRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000000) >> 31
}
func (o *GPIO_Type) SetBSRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetBSRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x0) >> 32
}

// GPIO.LCKR: GPIO port configuration lock register
func (o *GPIO_Type) SetLCKR_LCK0(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetLCKR_LCK0() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetLCKR_LCK1(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetLCKR_LCK1() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetLCKR_LCK2(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetLCKR_LCK2() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetLCKR_LCK3(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetLCKR_LCK3() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetLCKR_LCK4(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetLCKR_LCK4() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetLCKR_LCK5(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetLCKR_LCK5() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetLCKR_LCK6(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetLCKR_LCK6() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetLCKR_LCK7(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetLCKR_LCK7() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetLCKR_LCK8(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetLCKR_LCK8() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetLCKR_LCK9(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetLCKR_LCK9() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetLCKR_LCK10(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetLCKR_LCK10() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetLCKR_LCK11(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetLCKR_LCK11() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetLCKR_LCK12(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetLCKR_LCK12() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetLCKR_LCK13(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetLCKR_LCK13() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetLCKR_LCK14(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetLCKR_LCK14() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetLCKR_LCK15(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetLCKR_LCK15() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10000) >> 16
}
func (o *GPIO_Type) SetLCKR_LCKK(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetLCKR_LCKK() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10000) >> 16
}

// GPIO.AFRL: GPIO alternate function low register
func (o *GPIO_Type) SetAFRL_AFSEL0(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRL_AFSEL0() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRL_AFSEL1(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRL_AFSEL1() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRL_AFSEL2(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRL_AFSEL2() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRL_AFSEL3(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRL_AFSEL3() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0000) >> 16
}
func (o *GPIO_Type) SetAFRL_AFSEL4(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf00000)|value<<20)
}
func (o *GPIO_Type) GetAFRL_AFSEL4() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf00000) >> 20
}
func (o *GPIO_Type) SetAFRL_AFSEL5(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf000000)|value<<24)
}
func (o *GPIO_Type) GetAFRL_AFSEL5() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf000000) >> 24
}
func (o *GPIO_Type) SetAFRL_AFSEL6(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0000000)|value<<28)
}
func (o *GPIO_Type) GetAFRL_AFSEL6() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0000000) >> 28
}
func (o *GPIO_Type) SetAFRL_AFSEL7(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetAFRL_AFSEL7() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0x0) >> 32
}

// GPIO.AFRH: GPIO alternate function high register
func (o *GPIO_Type) SetAFRH_AFSEL8(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRH_AFSEL8() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRH_AFSEL9(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRH_AFSEL9() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRH_AFSEL10(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRH_AFSEL10() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRH_AFSEL11(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRH_AFSEL11() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0000) >> 16
}
func (o *GPIO_Type) SetAFRH_AFSEL12(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf00000)|value<<20)
}
func (o *GPIO_Type) GetAFRH_AFSEL12() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf00000) >> 20
}
func (o *GPIO_Type) SetAFRH_AFSEL13(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf000000)|value<<24)
}
func (o *GPIO_Type) GetAFRH_AFSEL13() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf000000) >> 24
}
func (o *GPIO_Type) SetAFRH_AFSEL14(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0000000)|value<<28)
}
func (o *GPIO_Type) GetAFRH_AFSEL14() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0000000) >> 28
}
func (o *GPIO_Type) SetAFRH_AFSEL15(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetAFRH_AFSEL15() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0x0) >> 32
}

// GPIO.BRR: GPIO port bit reset register
func (o *GPIO_Type) SetBRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetBRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetBRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetBRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetBRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetBRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetBRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetBRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetBRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10000) >> 16
}

// GPIO.HSLVR: GPIO high-speed low-voltage register
func (o *GPIO_Type) SetHSLVR_HSLV0(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetHSLVR_HSLV0() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetHSLVR_HSLV1(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetHSLVR_HSLV1() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetHSLVR_HSLV2(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetHSLVR_HSLV2() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetHSLVR_HSLV3(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetHSLVR_HSLV3() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetHSLVR_HSLV4(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetHSLVR_HSLV4() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetHSLVR_HSLV5(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetHSLVR_HSLV5() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetHSLVR_HSLV6(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetHSLVR_HSLV6() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetHSLVR_HSLV7(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetHSLVR_HSLV7() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetHSLVR_HSLV8(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetHSLVR_HSLV8() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetHSLVR_HSLV9(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetHSLVR_HSLV9() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetHSLVR_HSLV10(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetHSLVR_HSLV10() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetHSLVR_HSLV11(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetHSLVR_HSLV11() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetHSLVR_HSLV12(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetHSLVR_HSLV12() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetHSLVR_HSLV13(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetHSLVR_HSLV13() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetHSLVR_HSLV14(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetHSLVR_HSLV14() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetHSLVR_HSLV15(value uint32) {
	volatile.StoreUint32(&o.HSLVR.Reg, volatile.LoadUint32(&o.HSLVR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetHSLVR_HSLV15() uint32 {
	return (volatile.LoadUint32(&o.HSLVR.Reg) & 0x10000) >> 16
}

// GPIO.SECCFGR: GPIO secure configuration register
func (o *GPIO_Type) SetSECCFGR_SEC0(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetSECCFGR_SEC0() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetSECCFGR_SEC1(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetSECCFGR_SEC1() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetSECCFGR_SEC2(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetSECCFGR_SEC2() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetSECCFGR_SEC3(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetSECCFGR_SEC3() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetSECCFGR_SEC4(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetSECCFGR_SEC4() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetSECCFGR_SEC5(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetSECCFGR_SEC5() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetSECCFGR_SEC6(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetSECCFGR_SEC6() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetSECCFGR_SEC7(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetSECCFGR_SEC7() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetSECCFGR_SEC8(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetSECCFGR_SEC8() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetSECCFGR_SEC9(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetSECCFGR_SEC9() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetSECCFGR_SEC10(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetSECCFGR_SEC10() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetSECCFGR_SEC11(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetSECCFGR_SEC11() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetSECCFGR_SEC12(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetSECCFGR_SEC12() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetSECCFGR_SEC13(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetSECCFGR_SEC13() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetSECCFGR_SEC14(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetSECCFGR_SEC14() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetSECCFGR_SEC15(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetSECCFGR_SEC15() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10000) >> 16
}

// GTZC1_TZIC
type GTZC_Type struct {
	IER1 volatile.Register32 // 0x0
	IER2 volatile.Register32 // 0x4
	IER3 volatile.Register32 // 0x8
	IER4 volatile.Register32 // 0xC
	SR1  volatile.Register32 // 0x10
	SR2  volatile.Register32 // 0x14
	SR3  volatile.Register32 // 0x18
	SR4  volatile.Register32 // 0x1C
	FCR1 volatile.Register32 // 0x20
	FCR2 volatile.Register32 // 0x24
	FCR3 volatile.Register32 // 0x28
	FCR4 volatile.Register32 // 0x2C
}

// GTZC.IER1: TZIC interrupt enable register 1
func (o *GTZC_Type) SetIER1_TIM2IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetIER1_TIM2IE() uint32 {
	return volatile.LoadUint32(&o.IER1.Reg) & 0x1
}
func (o *GTZC_Type) SetIER1_TIM3IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetIER1_TIM3IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetIER1_TIM4IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetIER1_TIM4IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetIER1_TIM5IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetIER1_TIM5IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetIER1_TIM6IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetIER1_TIM6IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetIER1_TIM7IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetIER1_TIM7IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetIER1_WWDGIE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetIER1_WWDGIE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetIER1_IWDGIE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetIER1_IWDGIE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetIER1_SPI2IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetIER1_SPI2IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetIER1_USART2IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetIER1_USART2IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetIER1_USART3IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetIER1_USART3IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetIER1_USART4IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetIER1_USART4IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetIER1_UART5IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetIER1_UART5IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetIER1_I2C1IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetIER1_I2C1IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetIER1_I2C2IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetIER1_I2C2IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetIER1_CRSIE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetIER1_CRSIE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetIER1_I2C4IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetIER1_I2C4IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetIER1_LPTIM2IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetIER1_LPTIM2IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetIER1_FDCAN1IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetIER1_FDCAN1IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetIER1_UCPD1IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetIER1_UCPD1IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetIER1_USART6IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetIER1_USART6IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetIER1_I2C5IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetIER1_I2C5IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetIER1_I2C6IE(value uint32) {
	volatile.StoreUint32(&o.IER1.Reg, volatile.LoadUint32(&o.IER1.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetIER1_I2C6IE() uint32 {
	return (volatile.LoadUint32(&o.IER1.Reg) & 0x800000) >> 23
}

// GTZC.IER2: TZIC interrupt enable register 2
func (o *GTZC_Type) SetIER2_TIM1IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetIER2_TIM1IE() uint32 {
	return volatile.LoadUint32(&o.IER2.Reg) & 0x1
}
func (o *GTZC_Type) SetIER2_SPI1IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetIER2_SPI1IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetIER2_TIM8IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetIER2_TIM8IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetIER2_USART1IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetIER2_USART1IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetIER2_TIM15IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetIER2_TIM15IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetIER2_TIM16IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetIER2_TIM16IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetIER2_TIM17IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetIER2_TIM17IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetIER2_SAI1IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetIER2_SAI1IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetIER2_SAI2IE(value uint32) {
	volatile.StoreUint32(&o.IER2.Reg, volatile.LoadUint32(&o.IER2.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetIER2_SAI2IE() uint32 {
	return (volatile.LoadUint32(&o.IER2.Reg) & 0x100) >> 8
}

// GTZC.IER3: TZIC interrupt enable register 3
func (o *GTZC_Type) SetIER3_MDF1IE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetIER3_MDF1IE() uint32 {
	return volatile.LoadUint32(&o.IER3.Reg) & 0x1
}
func (o *GTZC_Type) SetIER3_CORDICIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetIER3_CORDICIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetIER3_FMACIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetIER3_FMACIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetIER3_CRCIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetIER3_CRCIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetIER3_TSCIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetIER3_TSCIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetIER3_DMA2DIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetIER3_DMA2DIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetIER3_ICACHE_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetIER3_ICACHE_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetIER3_DCACHE1_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetIER3_DCACHE1_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetIER3_ADC1I2E(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetIER3_ADC1I2E() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetIER3_DCMIIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetIER3_DCMIIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetIER3_OTGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetIER3_OTGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetIER3_AESIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetIER3_AESIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetIER3_HASHIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetIER3_HASHIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetIER3_RNGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetIER3_RNGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetIER3_PKAIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetIER3_PKAIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetIER3_SAESIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetIER3_SAESIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetIER3_OCTOSPIMIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetIER3_OCTOSPIMIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetIER3_SDMMC1IE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetIER3_SDMMC1IE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetIER3_SDMMC2IE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetIER3_SDMMC2IE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetIER3_FSMC_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetIER3_FSMC_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetIER3_OCTOSPI1_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetIER3_OCTOSPI1_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetIER3_OCTOSPI2_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetIER3_OCTOSPI2_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetIER3_RAMCFGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetIER3_RAMCFGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetIER3_HSPI1_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER3.Reg, volatile.LoadUint32(&o.IER3.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetIER3_HSPI1_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER3.Reg) & 0x4000000) >> 26
}

// GTZC.IER4: TZIC interrupt enable register 4
func (o *GTZC_Type) SetIER4_GPDMA1IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetIER4_GPDMA1IE() uint32 {
	return volatile.LoadUint32(&o.IER4.Reg) & 0x1
}
func (o *GTZC_Type) SetIER4_FLASH_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetIER4_FLASH_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetIER4_FLASHIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetIER4_FLASHIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetIER4_OTFDEC1IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetIER4_OTFDEC1IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetIER4_OTFDEC2IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetIER4_OTFDEC2IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetIER4_TZSC1IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetIER4_TZSC1IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetIER4_TZIC1IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetIER4_TZIC1IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetIER4_OCTOSPI1_MEMIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetIER4_OCTOSPI1_MEMIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetIER4_FSMC_MEMIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetIER4_FSMC_MEMIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetIER4_BKPSRAMIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetIER4_BKPSRAMIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetIER4_OCTOSPI2_MEMIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetIER4_OCTOSPI2_MEMIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetIER4_HSPI1_MEMIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetIER4_HSPI1_MEMIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetIER4_SRAM1IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetIER4_SRAM1IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetIER4_MPCBB1_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetIER4_MPCBB1_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetIER4_SRAM2IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetIER4_SRAM2IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetIER4_MPCBB2_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetIER4_MPCBB2_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetIER4_SRAM3IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetIER4_SRAM3IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetIER4_MPCBB3_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetIER4_MPCBB3_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetIER4_SRAM5IE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetIER4_SRAM5IE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetIER4_MPCBB5_REGIE(value uint32) {
	volatile.StoreUint32(&o.IER4.Reg, volatile.LoadUint32(&o.IER4.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetIER4_MPCBB5_REGIE() uint32 {
	return (volatile.LoadUint32(&o.IER4.Reg) & 0x80000000) >> 31
}

// GTZC.SR1: TZIC status register 1
func (o *GTZC_Type) SetSR1_TIM2F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetSR1_TIM2F() uint32 {
	return volatile.LoadUint32(&o.SR1.Reg) & 0x1
}
func (o *GTZC_Type) SetSR1_TIM3F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetSR1_TIM3F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetSR1_TIM4F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetSR1_TIM4F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetSR1_TIM5F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetSR1_TIM5F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetSR1_TIM6F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetSR1_TIM6F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetSR1_TIM7F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetSR1_TIM7F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetSR1_WWDGF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetSR1_WWDGF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetSR1_IWDGF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetSR1_IWDGF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetSR1_SPI2F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetSR1_SPI2F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetSR1_USART2F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetSR1_USART2F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetSR1_USART3F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetSR1_USART3F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetSR1_UART4F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetSR1_UART4F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetSR1_UART5F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetSR1_UART5F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetSR1_I2C1F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetSR1_I2C1F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetSR1_I2C2F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetSR1_I2C2F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetSR1_CRSF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetSR1_CRSF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetSR1_I2C4F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetSR1_I2C4F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetSR1_LPTIM2F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetSR1_LPTIM2F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetSR1_FDCAN1F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetSR1_FDCAN1F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetSR1_UCPD1F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetSR1_UCPD1F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetSR1_USART6F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetSR1_USART6F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetSR1_I2C5F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetSR1_I2C5F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetSR1_I2C6F(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetSR1_I2C6F() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x800000) >> 23
}

// GTZC.SR2: TZIC status register 2
func (o *GTZC_Type) SetSR2_TIM1F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetSR2_TIM1F() uint32 {
	return volatile.LoadUint32(&o.SR2.Reg) & 0x1
}
func (o *GTZC_Type) SetSR2_SPI1F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetSR2_SPI1F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetSR2_TIM8F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetSR2_TIM8F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetSR2_USART1F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetSR2_USART1F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetSR2_TIM15F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetSR2_TIM15F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetSR2_TIM16F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetSR2_TIM16F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetSR2_TIM17F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetSR2_TIM17F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetSR2_SAI1F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetSR2_SAI1F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetSR2_SAI2F(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetSR2_SAI2F() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x100) >> 8
}

// GTZC.SR3: TZIC status register 3
func (o *GTZC_Type) SetSR3_MDF1F(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetSR3_MDF1F() uint32 {
	return volatile.LoadUint32(&o.SR3.Reg) & 0x1
}
func (o *GTZC_Type) SetSR3_CORDICF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetSR3_CORDICF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetSR3_FMACF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetSR3_FMACF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetSR3_CRCF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetSR3_CRCF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetSR3_TSCF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetSR3_TSCF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetSR3_DMA2DF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetSR3_DMA2DF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetSR3_ICACHE_REGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetSR3_ICACHE_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetSR3_DCACHE1_REGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetSR3_DCACHE1_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetSR3_ADC12F(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetSR3_ADC12F() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetSR3_DCMIF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetSR3_DCMIF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetSR3_OTGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetSR3_OTGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetSR3_AESF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetSR3_AESF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetSR3_HASHF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetSR3_HASHF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetSR3_RNGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetSR3_RNGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetSR3_PKAF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetSR3_PKAF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetSR3_SAESF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetSR3_SAESF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetSR3_OCTOSPIMF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetSR3_OCTOSPIMF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetSR3_SDMMC1F(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetSR3_SDMMC1F() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetSR3_SDMMC2F(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetSR3_SDMMC2F() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetSR3_FSMC_REGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetSR3_FSMC_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetSR3_OCTOSPI1_REGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetSR3_OCTOSPI1_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetSR3_OCTOSPI2_REGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetSR3_OCTOSPI2_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetSR3_RAMCFGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetSR3_RAMCFGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetSR3_HSPI1_REGF(value uint32) {
	volatile.StoreUint32(&o.SR3.Reg, volatile.LoadUint32(&o.SR3.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetSR3_HSPI1_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR3.Reg) & 0x4000000) >> 26
}

// GTZC.SR4: TZIC status register 4
func (o *GTZC_Type) SetSR4_GPDMA1F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetSR4_GPDMA1F() uint32 {
	return volatile.LoadUint32(&o.SR4.Reg) & 0x1
}
func (o *GTZC_Type) SetSR4_FLASH_REGF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetSR4_FLASH_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetSR4_FLASHF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetSR4_FLASHF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetSR4_OTFDEC1F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetSR4_OTFDEC1F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetSR4_OTFDEC2F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetSR4_OTFDEC2F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetSR4_TZSC1F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetSR4_TZSC1F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetSR4_TZIC1F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetSR4_TZIC1F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetSR4_OCTOSPI1_MEMF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetSR4_OCTOSPI1_MEMF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetSR4_FSMC_MEMF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetSR4_FSMC_MEMF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetSR4_BKPSRAMF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetSR4_BKPSRAMF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetSR4_OCTOSPI2_MEMF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetSR4_OCTOSPI2_MEMF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetSR4_HSPI1_MEMF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetSR4_HSPI1_MEMF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetSR4_SRAM1F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetSR4_SRAM1F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetSR4_MPCBB1_REGF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetSR4_MPCBB1_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetSR4_SRAM2F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetSR4_SRAM2F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetSR4_MPCBB2_REGF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetSR4_MPCBB2_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetSR4_SRAM3F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetSR4_SRAM3F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetSR4_MPCBB3_REGF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetSR4_MPCBB3_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetSR4_SRAM5F(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetSR4_SRAM5F() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetSR4_MPCBB5_REGF(value uint32) {
	volatile.StoreUint32(&o.SR4.Reg, volatile.LoadUint32(&o.SR4.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetSR4_MPCBB5_REGF() uint32 {
	return (volatile.LoadUint32(&o.SR4.Reg) & 0x80000000) >> 31
}

// GTZC.FCR1: TZIC flag clear register 1
func (o *GTZC_Type) SetFCR1_CTIM2F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetFCR1_CTIM2F() uint32 {
	return volatile.LoadUint32(&o.FCR1.Reg) & 0x1
}
func (o *GTZC_Type) SetFCR1_CTIM3F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetFCR1_CTIM3F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetFCR1_CTIM4F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetFCR1_CTIM4F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetFCR1_CTIM5F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetFCR1_CTIM5F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetFCR1_CTIM6F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetFCR1_CTIM6F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetFCR1_CTIM7F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetFCR1_CTIM7F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetFCR1_CWWDGF(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetFCR1_CWWDGF() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetFCR1_CIWDGF(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetFCR1_CIWDGF() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetFCR1_CSPI2F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetFCR1_CSPI2F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetFCR1_CUSART2F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetFCR1_CUSART2F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetFCR1_CUSART3F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetFCR1_CUSART3F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetFCR1_CUART4F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetFCR1_CUART4F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetFCR1_CUART5F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetFCR1_CUART5F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetFCR1_CI2C1F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetFCR1_CI2C1F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetFCR1_CI2C2F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetFCR1_CI2C2F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetFCR1_CCRSF(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetFCR1_CCRSF() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetFCR1_CI2C4F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetFCR1_CI2C4F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetFCR1_CLPTIM2F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetFCR1_CLPTIM2F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetFCR1_CFDCAN1F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetFCR1_CFDCAN1F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetFCR1_CUCPD1F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetFCR1_CUCPD1F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetFCR1_CUSART6F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetFCR1_CUSART6F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetFCR1_CI2C5F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetFCR1_CI2C5F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetFCR1_CI2C6F(value uint32) {
	volatile.StoreUint32(&o.FCR1.Reg, volatile.LoadUint32(&o.FCR1.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetFCR1_CI2C6F() uint32 {
	return (volatile.LoadUint32(&o.FCR1.Reg) & 0x800000) >> 23
}

// GTZC.FCR2: TZIC flag clear register 2
func (o *GTZC_Type) SetFCR2_CTIM1F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetFCR2_CTIM1F() uint32 {
	return volatile.LoadUint32(&o.FCR2.Reg) & 0x1
}
func (o *GTZC_Type) SetFCR2_CSPI1F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetFCR2_CSPI1F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetFCR2_CTIM8F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetFCR2_CTIM8F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetFCR2_CUSART1F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetFCR2_CUSART1F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetFCR2_CTIM15F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetFCR2_CTIM15F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetFCR2_CTIM16F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetFCR2_CTIM16F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetFCR2_CTIM17F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetFCR2_CTIM17F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetFCR2_CSAI1F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetFCR2_CSAI1F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetFCR2_CSAI2F(value uint32) {
	volatile.StoreUint32(&o.FCR2.Reg, volatile.LoadUint32(&o.FCR2.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetFCR2_CSAI2F() uint32 {
	return (volatile.LoadUint32(&o.FCR2.Reg) & 0x100) >> 8
}

// GTZC.FCR3: TZIC flag clear register 3
func (o *GTZC_Type) SetFCR3_CMDF1F(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetFCR3_CMDF1F() uint32 {
	return volatile.LoadUint32(&o.FCR3.Reg) & 0x1
}
func (o *GTZC_Type) SetFCR3_CCORDICF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetFCR3_CCORDICF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetFCR3_CFMACF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetFCR3_CFMACF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetFCR3_CCRCF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetFCR3_CCRCF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetFCR3_CTSCF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetFCR3_CTSCF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetFCR3_CDMA2DF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetFCR3_CDMA2DF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetFCR3_CICACHE_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetFCR3_CICACHE_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetFCR3_CDCACHE1_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetFCR3_CDCACHE1_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetFCR3_CADC12F(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetFCR3_CADC12F() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetFCR3_CDCMIF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetFCR3_CDCMIF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetFCR3_COTGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetFCR3_COTGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetFCR3_CAESF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetFCR3_CAESF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetFCR3_CHASHF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetFCR3_CHASHF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetFCR3_CRNGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetFCR3_CRNGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetFCR3_CPKAF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetFCR3_CPKAF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetFCR3_CSAESF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetFCR3_CSAESF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetFCR3_COCTOSPIMF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetFCR3_COCTOSPIMF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetFCR3_CSDMMC1F(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetFCR3_CSDMMC1F() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetFCR3_CSDMMC2F(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetFCR3_CSDMMC2F() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetFCR3_CFSMC_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetFCR3_CFSMC_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetFCR3_COCTOSPI1_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetFCR3_COCTOSPI1_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetFCR3_COCTOSPI2_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetFCR3_COCTOSPI2_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetFCR3_CRAMCFGF(value uint32) {
	volatile.StoreUint32(&o.FCR3.Reg, volatile.LoadUint32(&o.FCR3.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetFCR3_CRAMCFGF() uint32 {
	return (volatile.LoadUint32(&o.FCR3.Reg) & 0x400000) >> 22
}

// GTZC.FCR4: TZIC flag clear register 4
func (o *GTZC_Type) SetFCR4_CGPDMA1F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetFCR4_CGPDMA1F() uint32 {
	return volatile.LoadUint32(&o.FCR4.Reg) & 0x1
}
func (o *GTZC_Type) SetFCR4_CFLASH_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetFCR4_CFLASH_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetFCR4_CFLASHF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetFCR4_CFLASHF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetFCR4_COTFDEC1F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetFCR4_COTFDEC1F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetFCR4_COTFDEC2F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetFCR4_COTFDEC2F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetFCR4_CTZSC1F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetFCR4_CTZSC1F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetFCR4_CTZIC1F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetFCR4_CTZIC1F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetFCR4_COCTOSPI1_MEMF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetFCR4_COCTOSPI1_MEMF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetFCR4_CFSMC_MEMF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetFCR4_CFSMC_MEMF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetFCR4_CBKPSRAMF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetFCR4_CBKPSRAMF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetFCR4_COCTOSPI2_MEMF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetFCR4_COCTOSPI2_MEMF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetFCR4_CHSPI1_MEMF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetFCR4_CHSPI1_MEMF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetFCR4_CSRAM1F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetFCR4_CSRAM1F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetFCR4_CMPCBB1_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetFCR4_CMPCBB1_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetFCR4_CSRAM2F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetFCR4_CSRAM2F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetFCR4_CMPCBB2_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetFCR4_CMPCBB2_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetFCR4_CSRAM3F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetFCR4_CSRAM3F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetFCR4_CMPCBB3_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetFCR4_CMPCBB3_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetFCR4_CSRAM5F(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetFCR4_CSRAM5F() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetFCR4_CMPCBB5_REGF(value uint32) {
	volatile.StoreUint32(&o.FCR4.Reg, volatile.LoadUint32(&o.FCR4.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetFCR4_CMPCBB5_REGF() uint32 {
	return (volatile.LoadUint32(&o.FCR4.Reg) & 0x80000000) >> 31
}

// Hash processor
type HASH_Type struct {
	CR    volatile.Register32 // 0x0
	DIN   volatile.Register32 // 0x4
	STR   volatile.Register32 // 0x8
	HRA0  volatile.Register32 // 0xC
	HRA1  volatile.Register32 // 0x10
	HRA2  volatile.Register32 // 0x14
	HRA3  volatile.Register32 // 0x18
	HRA4  volatile.Register32 // 0x1C
	IMR   volatile.Register32 // 0x20
	SR    volatile.Register32 // 0x24
	_     [208]byte
	CSR0  volatile.Register32 // 0xF8
	CSR1  volatile.Register32 // 0xFC
	CSR2  volatile.Register32 // 0x100
	CSR3  volatile.Register32 // 0x104
	CSR4  volatile.Register32 // 0x108
	CSR5  volatile.Register32 // 0x10C
	CSR6  volatile.Register32 // 0x110
	CSR7  volatile.Register32 // 0x114
	CSR8  volatile.Register32 // 0x118
	CSR9  volatile.Register32 // 0x11C
	CSR10 volatile.Register32 // 0x120
	CSR11 volatile.Register32 // 0x124
	CSR12 volatile.Register32 // 0x128
	CSR13 volatile.Register32 // 0x12C
	CSR14 volatile.Register32 // 0x130
	CSR15 volatile.Register32 // 0x134
	CSR16 volatile.Register32 // 0x138
	CSR17 volatile.Register32 // 0x13C
	CSR18 volatile.Register32 // 0x140
	CSR19 volatile.Register32 // 0x144
	CSR20 volatile.Register32 // 0x148
	CSR21 volatile.Register32 // 0x14C
	CSR22 volatile.Register32 // 0x150
	CSR23 volatile.Register32 // 0x154
	CSR24 volatile.Register32 // 0x158
	CSR25 volatile.Register32 // 0x15C
	CSR26 volatile.Register32 // 0x160
	CSR27 volatile.Register32 // 0x164
	CSR28 volatile.Register32 // 0x168
	CSR29 volatile.Register32 // 0x16C
	CSR30 volatile.Register32 // 0x170
	CSR31 volatile.Register32 // 0x174
	CSR32 volatile.Register32 // 0x178
	CSR33 volatile.Register32 // 0x17C
	CSR34 volatile.Register32 // 0x180
	CSR35 volatile.Register32 // 0x184
	CSR36 volatile.Register32 // 0x188
	CSR37 volatile.Register32 // 0x18C
	CSR38 volatile.Register32 // 0x190
	CSR39 volatile.Register32 // 0x194
	CSR40 volatile.Register32 // 0x198
	CSR41 volatile.Register32 // 0x19C
	CSR42 volatile.Register32 // 0x1A0
	CSR43 volatile.Register32 // 0x1A4
	CSR44 volatile.Register32 // 0x1A8
	CSR45 volatile.Register32 // 0x1AC
	CSR46 volatile.Register32 // 0x1B0
	CSR47 volatile.Register32 // 0x1B4
	CSR48 volatile.Register32 // 0x1B8
	CSR49 volatile.Register32 // 0x1BC
	CSR50 volatile.Register32 // 0x1C0
	CSR51 volatile.Register32 // 0x1C4
	CSR52 volatile.Register32 // 0x1C8
	CSR53 volatile.Register32 // 0x1CC
	_     [320]byte
	HR0   volatile.Register32 // 0x310
	HR1   volatile.Register32 // 0x314
	HR2   volatile.Register32 // 0x318
	HR3   volatile.Register32 // 0x31C
	HR4   volatile.Register32 // 0x320
	HR5   volatile.Register32 // 0x324
	HR6   volatile.Register32 // 0x328
	HR7   volatile.Register32 // 0x32C
}

// HASH.CR: control register
func (o *HASH_Type) SetCR_INIT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *HASH_Type) GetCR_INIT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *HASH_Type) SetCR_DMAE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *HASH_Type) GetCR_DMAE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *HASH_Type) SetCR_DATATYPE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x30)|value<<4)
}
func (o *HASH_Type) GetCR_DATATYPE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x30) >> 4
}
func (o *HASH_Type) SetCR_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *HASH_Type) GetCR_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *HASH_Type) SetCR_ALGO(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x60000)|value<<17)
}
func (o *HASH_Type) GetCR_ALGO() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x60000) >> 17
}
func (o *HASH_Type) SetCR_NBW(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf00)|value<<8)
}
func (o *HASH_Type) GetCR_NBW() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf00) >> 8
}
func (o *HASH_Type) SetCR_DINNE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *HASH_Type) GetCR_DINNE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *HASH_Type) SetCR_MDMAT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *HASH_Type) GetCR_MDMAT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *HASH_Type) SetCR_LKEY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *HASH_Type) GetCR_LKEY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}

// HASH.DIN: data input register
func (o *HASH_Type) SetDIN(value uint32) {
	volatile.StoreUint32(&o.DIN.Reg, value)
}
func (o *HASH_Type) GetDIN() uint32 {
	return volatile.LoadUint32(&o.DIN.Reg)
}

// HASH.STR: start register
func (o *HASH_Type) SetSTR_DCAL(value uint32) {
	volatile.StoreUint32(&o.STR.Reg, volatile.LoadUint32(&o.STR.Reg)&^(0x100)|value<<8)
}
func (o *HASH_Type) GetSTR_DCAL() uint32 {
	return (volatile.LoadUint32(&o.STR.Reg) & 0x100) >> 8
}
func (o *HASH_Type) SetSTR_NBLW(value uint32) {
	volatile.StoreUint32(&o.STR.Reg, volatile.LoadUint32(&o.STR.Reg)&^(0x1f)|value)
}
func (o *HASH_Type) GetSTR_NBLW() uint32 {
	return volatile.LoadUint32(&o.STR.Reg) & 0x1f
}

// HASH.HRA0: HASH aliased digest register 0
func (o *HASH_Type) SetHRA0(value uint32) {
	volatile.StoreUint32(&o.HRA0.Reg, value)
}
func (o *HASH_Type) GetHRA0() uint32 {
	return volatile.LoadUint32(&o.HRA0.Reg)
}

// HASH.HRA1: HASH aliased digest register 1
func (o *HASH_Type) SetHRA1(value uint32) {
	volatile.StoreUint32(&o.HRA1.Reg, value)
}
func (o *HASH_Type) GetHRA1() uint32 {
	return volatile.LoadUint32(&o.HRA1.Reg)
}

// HASH.HRA2: HASH aliased digest register 2
func (o *HASH_Type) SetHRA2(value uint32) {
	volatile.StoreUint32(&o.HRA2.Reg, value)
}
func (o *HASH_Type) GetHRA2() uint32 {
	return volatile.LoadUint32(&o.HRA2.Reg)
}

// HASH.HRA3: HASH aliased digest register 3
func (o *HASH_Type) SetHRA3(value uint32) {
	volatile.StoreUint32(&o.HRA3.Reg, value)
}
func (o *HASH_Type) GetHRA3() uint32 {
	return volatile.LoadUint32(&o.HRA3.Reg)
}

// HASH.HRA4: HASH aliased digest register 4
func (o *HASH_Type) SetHRA4(value uint32) {
	volatile.StoreUint32(&o.HRA4.Reg, value)
}
func (o *HASH_Type) GetHRA4() uint32 {
	return volatile.LoadUint32(&o.HRA4.Reg)
}

// HASH.IMR: interrupt enable register
func (o *HASH_Type) SetIMR_DCIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *HASH_Type) GetIMR_DCIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *HASH_Type) SetIMR_DINIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *HASH_Type) GetIMR_DINIE() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}

// HASH.SR: status register
func (o *HASH_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *HASH_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *HASH_Type) SetSR_DMAS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *HASH_Type) GetSR_DMAS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *HASH_Type) SetSR_DCIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *HASH_Type) GetSR_DCIS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *HASH_Type) SetSR_DINIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *HASH_Type) GetSR_DINIS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *HASH_Type) SetSR_NBWE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1f0000)|value<<16)
}
func (o *HASH_Type) GetSR_NBWE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1f0000) >> 16
}
func (o *HASH_Type) SetSR_DINNE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000)|value<<15)
}
func (o *HASH_Type) GetSR_DINNE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000) >> 15
}
func (o *HASH_Type) SetSR_NBWP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3e00)|value<<9)
}
func (o *HASH_Type) GetSR_NBWP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x3e00) >> 9
}

// HASH.CSR0: context swap registers
func (o *HASH_Type) SetCSR0(value uint32) {
	volatile.StoreUint32(&o.CSR0.Reg, value)
}
func (o *HASH_Type) GetCSR0() uint32 {
	return volatile.LoadUint32(&o.CSR0.Reg)
}

// HASH.CSR1: context swap registers
func (o *HASH_Type) SetCSR1(value uint32) {
	volatile.StoreUint32(&o.CSR1.Reg, value)
}
func (o *HASH_Type) GetCSR1() uint32 {
	return volatile.LoadUint32(&o.CSR1.Reg)
}

// HASH.CSR2: context swap registers
func (o *HASH_Type) SetCSR2(value uint32) {
	volatile.StoreUint32(&o.CSR2.Reg, value)
}
func (o *HASH_Type) GetCSR2() uint32 {
	return volatile.LoadUint32(&o.CSR2.Reg)
}

// HASH.CSR3: context swap registers
func (o *HASH_Type) SetCSR3(value uint32) {
	volatile.StoreUint32(&o.CSR3.Reg, value)
}
func (o *HASH_Type) GetCSR3() uint32 {
	return volatile.LoadUint32(&o.CSR3.Reg)
}

// HASH.CSR4: context swap registers
func (o *HASH_Type) SetCSR4(value uint32) {
	volatile.StoreUint32(&o.CSR4.Reg, value)
}
func (o *HASH_Type) GetCSR4() uint32 {
	return volatile.LoadUint32(&o.CSR4.Reg)
}

// HASH.CSR5: context swap registers
func (o *HASH_Type) SetCSR5(value uint32) {
	volatile.StoreUint32(&o.CSR5.Reg, value)
}
func (o *HASH_Type) GetCSR5() uint32 {
	return volatile.LoadUint32(&o.CSR5.Reg)
}

// HASH.CSR6: context swap registers
func (o *HASH_Type) SetCSR6(value uint32) {
	volatile.StoreUint32(&o.CSR6.Reg, value)
}
func (o *HASH_Type) GetCSR6() uint32 {
	return volatile.LoadUint32(&o.CSR6.Reg)
}

// HASH.CSR7: context swap registers
func (o *HASH_Type) SetCSR7(value uint32) {
	volatile.StoreUint32(&o.CSR7.Reg, value)
}
func (o *HASH_Type) GetCSR7() uint32 {
	return volatile.LoadUint32(&o.CSR7.Reg)
}

// HASH.CSR8: context swap registers
func (o *HASH_Type) SetCSR8(value uint32) {
	volatile.StoreUint32(&o.CSR8.Reg, value)
}
func (o *HASH_Type) GetCSR8() uint32 {
	return volatile.LoadUint32(&o.CSR8.Reg)
}

// HASH.CSR9: context swap registers
func (o *HASH_Type) SetCSR9(value uint32) {
	volatile.StoreUint32(&o.CSR9.Reg, value)
}
func (o *HASH_Type) GetCSR9() uint32 {
	return volatile.LoadUint32(&o.CSR9.Reg)
}

// HASH.CSR10: context swap registers
func (o *HASH_Type) SetCSR10(value uint32) {
	volatile.StoreUint32(&o.CSR10.Reg, value)
}
func (o *HASH_Type) GetCSR10() uint32 {
	return volatile.LoadUint32(&o.CSR10.Reg)
}

// HASH.CSR11: context swap registers
func (o *HASH_Type) SetCSR11(value uint32) {
	volatile.StoreUint32(&o.CSR11.Reg, value)
}
func (o *HASH_Type) GetCSR11() uint32 {
	return volatile.LoadUint32(&o.CSR11.Reg)
}

// HASH.CSR12: context swap registers
func (o *HASH_Type) SetCSR12(value uint32) {
	volatile.StoreUint32(&o.CSR12.Reg, value)
}
func (o *HASH_Type) GetCSR12() uint32 {
	return volatile.LoadUint32(&o.CSR12.Reg)
}

// HASH.CSR13: context swap registers
func (o *HASH_Type) SetCSR13(value uint32) {
	volatile.StoreUint32(&o.CSR13.Reg, value)
}
func (o *HASH_Type) GetCSR13() uint32 {
	return volatile.LoadUint32(&o.CSR13.Reg)
}

// HASH.CSR14: context swap registers
func (o *HASH_Type) SetCSR14(value uint32) {
	volatile.StoreUint32(&o.CSR14.Reg, value)
}
func (o *HASH_Type) GetCSR14() uint32 {
	return volatile.LoadUint32(&o.CSR14.Reg)
}

// HASH.CSR15: context swap registers
func (o *HASH_Type) SetCSR15(value uint32) {
	volatile.StoreUint32(&o.CSR15.Reg, value)
}
func (o *HASH_Type) GetCSR15() uint32 {
	return volatile.LoadUint32(&o.CSR15.Reg)
}

// HASH.CSR16: context swap registers
func (o *HASH_Type) SetCSR16(value uint32) {
	volatile.StoreUint32(&o.CSR16.Reg, value)
}
func (o *HASH_Type) GetCSR16() uint32 {
	return volatile.LoadUint32(&o.CSR16.Reg)
}

// HASH.CSR17: context swap registers
func (o *HASH_Type) SetCSR17(value uint32) {
	volatile.StoreUint32(&o.CSR17.Reg, value)
}
func (o *HASH_Type) GetCSR17() uint32 {
	return volatile.LoadUint32(&o.CSR17.Reg)
}

// HASH.CSR18: context swap registers
func (o *HASH_Type) SetCSR18(value uint32) {
	volatile.StoreUint32(&o.CSR18.Reg, value)
}
func (o *HASH_Type) GetCSR18() uint32 {
	return volatile.LoadUint32(&o.CSR18.Reg)
}

// HASH.CSR19: context swap registers
func (o *HASH_Type) SetCSR19(value uint32) {
	volatile.StoreUint32(&o.CSR19.Reg, value)
}
func (o *HASH_Type) GetCSR19() uint32 {
	return volatile.LoadUint32(&o.CSR19.Reg)
}

// HASH.CSR20: context swap registers
func (o *HASH_Type) SetCSR20(value uint32) {
	volatile.StoreUint32(&o.CSR20.Reg, value)
}
func (o *HASH_Type) GetCSR20() uint32 {
	return volatile.LoadUint32(&o.CSR20.Reg)
}

// HASH.CSR21: context swap registers
func (o *HASH_Type) SetCSR21(value uint32) {
	volatile.StoreUint32(&o.CSR21.Reg, value)
}
func (o *HASH_Type) GetCSR21() uint32 {
	return volatile.LoadUint32(&o.CSR21.Reg)
}

// HASH.CSR22: context swap registers
func (o *HASH_Type) SetCSR22(value uint32) {
	volatile.StoreUint32(&o.CSR22.Reg, value)
}
func (o *HASH_Type) GetCSR22() uint32 {
	return volatile.LoadUint32(&o.CSR22.Reg)
}

// HASH.CSR23: context swap registers
func (o *HASH_Type) SetCSR23(value uint32) {
	volatile.StoreUint32(&o.CSR23.Reg, value)
}
func (o *HASH_Type) GetCSR23() uint32 {
	return volatile.LoadUint32(&o.CSR23.Reg)
}

// HASH.CSR24: context swap registers
func (o *HASH_Type) SetCSR24(value uint32) {
	volatile.StoreUint32(&o.CSR24.Reg, value)
}
func (o *HASH_Type) GetCSR24() uint32 {
	return volatile.LoadUint32(&o.CSR24.Reg)
}

// HASH.CSR25: context swap registers
func (o *HASH_Type) SetCSR25(value uint32) {
	volatile.StoreUint32(&o.CSR25.Reg, value)
}
func (o *HASH_Type) GetCSR25() uint32 {
	return volatile.LoadUint32(&o.CSR25.Reg)
}

// HASH.CSR26: context swap registers
func (o *HASH_Type) SetCSR26(value uint32) {
	volatile.StoreUint32(&o.CSR26.Reg, value)
}
func (o *HASH_Type) GetCSR26() uint32 {
	return volatile.LoadUint32(&o.CSR26.Reg)
}

// HASH.CSR27: context swap registers
func (o *HASH_Type) SetCSR27(value uint32) {
	volatile.StoreUint32(&o.CSR27.Reg, value)
}
func (o *HASH_Type) GetCSR27() uint32 {
	return volatile.LoadUint32(&o.CSR27.Reg)
}

// HASH.CSR28: context swap registers
func (o *HASH_Type) SetCSR28(value uint32) {
	volatile.StoreUint32(&o.CSR28.Reg, value)
}
func (o *HASH_Type) GetCSR28() uint32 {
	return volatile.LoadUint32(&o.CSR28.Reg)
}

// HASH.CSR29: context swap registers
func (o *HASH_Type) SetCSR29(value uint32) {
	volatile.StoreUint32(&o.CSR29.Reg, value)
}
func (o *HASH_Type) GetCSR29() uint32 {
	return volatile.LoadUint32(&o.CSR29.Reg)
}

// HASH.CSR30: context swap registers
func (o *HASH_Type) SetCSR30(value uint32) {
	volatile.StoreUint32(&o.CSR30.Reg, value)
}
func (o *HASH_Type) GetCSR30() uint32 {
	return volatile.LoadUint32(&o.CSR30.Reg)
}

// HASH.CSR31: context swap registers
func (o *HASH_Type) SetCSR31(value uint32) {
	volatile.StoreUint32(&o.CSR31.Reg, value)
}
func (o *HASH_Type) GetCSR31() uint32 {
	return volatile.LoadUint32(&o.CSR31.Reg)
}

// HASH.CSR32: context swap registers
func (o *HASH_Type) SetCSR32(value uint32) {
	volatile.StoreUint32(&o.CSR32.Reg, value)
}
func (o *HASH_Type) GetCSR32() uint32 {
	return volatile.LoadUint32(&o.CSR32.Reg)
}

// HASH.CSR33: context swap registers
func (o *HASH_Type) SetCSR33(value uint32) {
	volatile.StoreUint32(&o.CSR33.Reg, value)
}
func (o *HASH_Type) GetCSR33() uint32 {
	return volatile.LoadUint32(&o.CSR33.Reg)
}

// HASH.CSR34: context swap registers
func (o *HASH_Type) SetCSR34(value uint32) {
	volatile.StoreUint32(&o.CSR34.Reg, value)
}
func (o *HASH_Type) GetCSR34() uint32 {
	return volatile.LoadUint32(&o.CSR34.Reg)
}

// HASH.CSR35: context swap registers
func (o *HASH_Type) SetCSR35(value uint32) {
	volatile.StoreUint32(&o.CSR35.Reg, value)
}
func (o *HASH_Type) GetCSR35() uint32 {
	return volatile.LoadUint32(&o.CSR35.Reg)
}

// HASH.CSR36: context swap registers
func (o *HASH_Type) SetCSR36(value uint32) {
	volatile.StoreUint32(&o.CSR36.Reg, value)
}
func (o *HASH_Type) GetCSR36() uint32 {
	return volatile.LoadUint32(&o.CSR36.Reg)
}

// HASH.CSR37: context swap registers
func (o *HASH_Type) SetCSR37(value uint32) {
	volatile.StoreUint32(&o.CSR37.Reg, value)
}
func (o *HASH_Type) GetCSR37() uint32 {
	return volatile.LoadUint32(&o.CSR37.Reg)
}

// HASH.CSR38: context swap registers
func (o *HASH_Type) SetCSR38(value uint32) {
	volatile.StoreUint32(&o.CSR38.Reg, value)
}
func (o *HASH_Type) GetCSR38() uint32 {
	return volatile.LoadUint32(&o.CSR38.Reg)
}

// HASH.CSR39: context swap registers
func (o *HASH_Type) SetCSR39(value uint32) {
	volatile.StoreUint32(&o.CSR39.Reg, value)
}
func (o *HASH_Type) GetCSR39() uint32 {
	return volatile.LoadUint32(&o.CSR39.Reg)
}

// HASH.CSR40: context swap registers
func (o *HASH_Type) SetCSR40(value uint32) {
	volatile.StoreUint32(&o.CSR40.Reg, value)
}
func (o *HASH_Type) GetCSR40() uint32 {
	return volatile.LoadUint32(&o.CSR40.Reg)
}

// HASH.CSR41: context swap registers
func (o *HASH_Type) SetCSR41(value uint32) {
	volatile.StoreUint32(&o.CSR41.Reg, value)
}
func (o *HASH_Type) GetCSR41() uint32 {
	return volatile.LoadUint32(&o.CSR41.Reg)
}

// HASH.CSR42: context swap registers
func (o *HASH_Type) SetCSR42(value uint32) {
	volatile.StoreUint32(&o.CSR42.Reg, value)
}
func (o *HASH_Type) GetCSR42() uint32 {
	return volatile.LoadUint32(&o.CSR42.Reg)
}

// HASH.CSR43: context swap registers
func (o *HASH_Type) SetCSR43(value uint32) {
	volatile.StoreUint32(&o.CSR43.Reg, value)
}
func (o *HASH_Type) GetCSR43() uint32 {
	return volatile.LoadUint32(&o.CSR43.Reg)
}

// HASH.CSR44: context swap registers
func (o *HASH_Type) SetCSR44(value uint32) {
	volatile.StoreUint32(&o.CSR44.Reg, value)
}
func (o *HASH_Type) GetCSR44() uint32 {
	return volatile.LoadUint32(&o.CSR44.Reg)
}

// HASH.CSR45: context swap registers
func (o *HASH_Type) SetCSR45(value uint32) {
	volatile.StoreUint32(&o.CSR45.Reg, value)
}
func (o *HASH_Type) GetCSR45() uint32 {
	return volatile.LoadUint32(&o.CSR45.Reg)
}

// HASH.CSR46: context swap registers
func (o *HASH_Type) SetCSR46(value uint32) {
	volatile.StoreUint32(&o.CSR46.Reg, value)
}
func (o *HASH_Type) GetCSR46() uint32 {
	return volatile.LoadUint32(&o.CSR46.Reg)
}

// HASH.CSR47: context swap registers
func (o *HASH_Type) SetCSR47(value uint32) {
	volatile.StoreUint32(&o.CSR47.Reg, value)
}
func (o *HASH_Type) GetCSR47() uint32 {
	return volatile.LoadUint32(&o.CSR47.Reg)
}

// HASH.CSR48: context swap registers
func (o *HASH_Type) SetCSR48(value uint32) {
	volatile.StoreUint32(&o.CSR48.Reg, value)
}
func (o *HASH_Type) GetCSR48() uint32 {
	return volatile.LoadUint32(&o.CSR48.Reg)
}

// HASH.CSR49: context swap registers
func (o *HASH_Type) SetCSR49(value uint32) {
	volatile.StoreUint32(&o.CSR49.Reg, value)
}
func (o *HASH_Type) GetCSR49() uint32 {
	return volatile.LoadUint32(&o.CSR49.Reg)
}

// HASH.CSR50: context swap registers
func (o *HASH_Type) SetCSR50(value uint32) {
	volatile.StoreUint32(&o.CSR50.Reg, value)
}
func (o *HASH_Type) GetCSR50() uint32 {
	return volatile.LoadUint32(&o.CSR50.Reg)
}

// HASH.CSR51: context swap registers
func (o *HASH_Type) SetCSR51(value uint32) {
	volatile.StoreUint32(&o.CSR51.Reg, value)
}
func (o *HASH_Type) GetCSR51() uint32 {
	return volatile.LoadUint32(&o.CSR51.Reg)
}

// HASH.CSR52: context swap registers
func (o *HASH_Type) SetCSR52(value uint32) {
	volatile.StoreUint32(&o.CSR52.Reg, value)
}
func (o *HASH_Type) GetCSR52() uint32 {
	return volatile.LoadUint32(&o.CSR52.Reg)
}

// HASH.CSR53: context swap registers
func (o *HASH_Type) SetCSR53(value uint32) {
	volatile.StoreUint32(&o.CSR53.Reg, value)
}
func (o *HASH_Type) GetCSR53() uint32 {
	return volatile.LoadUint32(&o.CSR53.Reg)
}

// HASH.HR0: digest register 0
func (o *HASH_Type) SetHR0(value uint32) {
	volatile.StoreUint32(&o.HR0.Reg, value)
}
func (o *HASH_Type) GetHR0() uint32 {
	return volatile.LoadUint32(&o.HR0.Reg)
}

// HASH.HR1: digest register 1
func (o *HASH_Type) SetHR1(value uint32) {
	volatile.StoreUint32(&o.HR1.Reg, value)
}
func (o *HASH_Type) GetHR1() uint32 {
	return volatile.LoadUint32(&o.HR1.Reg)
}

// HASH.HR2: digest register 4
func (o *HASH_Type) SetHR2(value uint32) {
	volatile.StoreUint32(&o.HR2.Reg, value)
}
func (o *HASH_Type) GetHR2() uint32 {
	return volatile.LoadUint32(&o.HR2.Reg)
}

// HASH.HR3: digest register 3
func (o *HASH_Type) SetHR3(value uint32) {
	volatile.StoreUint32(&o.HR3.Reg, value)
}
func (o *HASH_Type) GetHR3() uint32 {
	return volatile.LoadUint32(&o.HR3.Reg)
}

// HASH.HR4: digest register 4
func (o *HASH_Type) SetHR4(value uint32) {
	volatile.StoreUint32(&o.HR4.Reg, value)
}
func (o *HASH_Type) GetHR4() uint32 {
	return volatile.LoadUint32(&o.HR4.Reg)
}

// HASH.HR5: supplementary digest register 5
func (o *HASH_Type) SetHR5(value uint32) {
	volatile.StoreUint32(&o.HR5.Reg, value)
}
func (o *HASH_Type) GetHR5() uint32 {
	return volatile.LoadUint32(&o.HR5.Reg)
}

// HASH.HR6: supplementary digest register 6
func (o *HASH_Type) SetHR6(value uint32) {
	volatile.StoreUint32(&o.HR6.Reg, value)
}
func (o *HASH_Type) GetHR6() uint32 {
	return volatile.LoadUint32(&o.HR6.Reg)
}

// HASH.HR7: supplementary digest register 7
func (o *HASH_Type) SetHR7(value uint32) {
	volatile.StoreUint32(&o.HR7.Reg, value)
}
func (o *HASH_Type) GetHR7() uint32 {
	return volatile.LoadUint32(&o.HR7.Reg)
}

// Inter-integrated circuit
type I2C_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	OAR1     volatile.Register32 // 0x8
	OAR2     volatile.Register32 // 0xC
	TIMINGR  volatile.Register32 // 0x10
	TIMEOUTR volatile.Register32 // 0x14
	ISR      volatile.Register32 // 0x18
	ICR      volatile.Register32 // 0x1C
	PECR     volatile.Register32 // 0x20
	RXDR     volatile.Register32 // 0x24
	TXDR     volatile.Register32 // 0x28
	AUTOCR   volatile.Register32 // 0x2C
}

// I2C.CR1: Control register 1
func (o *I2C_Type) SetCR1_PE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetCR1_PE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *I2C_Type) SetCR1_TXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetCR1_TXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetCR1_RXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetCR1_RXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetCR1_ADDRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetCR1_ADDRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetCR1_NACKIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetCR1_NACKIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetCR1_STOPIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetCR1_STOPIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetCR1_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetCR1_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetCR1_DNF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xf00)|value<<8)
}
func (o *I2C_Type) GetCR1_DNF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xf00) >> 8
}
func (o *I2C_Type) SetCR1_ANFOFF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR1_ANFOFF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR1_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR1_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR1_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR1_RXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR1_SBC(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetCR1_SBC() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetCR1_NOSTRETCH(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetCR1_NOSTRETCH() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetCR1_WUPEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetCR1_WUPEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *I2C_Type) SetCR1_GCEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000)|value<<19)
}
func (o *I2C_Type) GetCR1_GCEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000) >> 19
}
func (o *I2C_Type) SetCR1_SMBHEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100000)|value<<20)
}
func (o *I2C_Type) GetCR1_SMBHEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100000) >> 20
}
func (o *I2C_Type) SetCR1_SMBDEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200000)|value<<21)
}
func (o *I2C_Type) GetCR1_SMBDEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200000) >> 21
}
func (o *I2C_Type) SetCR1_ALERTEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400000)|value<<22)
}
func (o *I2C_Type) GetCR1_ALERTEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400000) >> 22
}
func (o *I2C_Type) SetCR1_PECEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800000)|value<<23)
}
func (o *I2C_Type) GetCR1_PECEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800000) >> 23
}
func (o *I2C_Type) SetCR1_FMP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000000)|value<<24)
}
func (o *I2C_Type) GetCR1_FMP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000000) >> 24
}
func (o *I2C_Type) SetCR1_ADDRACLR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *I2C_Type) GetCR1_ADDRACLR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *I2C_Type) SetCR1_STOPFACLR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetCR1_STOPFACLR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000000) >> 31
}

// I2C.CR2: Control register 2
func (o *I2C_Type) SetCR2_PECBYTE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000000)|value<<26)
}
func (o *I2C_Type) GetCR2_PECBYTE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000000) >> 26
}
func (o *I2C_Type) SetCR2_AUTOEND(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *I2C_Type) GetCR2_AUTOEND() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *I2C_Type) SetCR2_RELOAD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000000)|value<<24)
}
func (o *I2C_Type) GetCR2_RELOAD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000000) >> 24
}
func (o *I2C_Type) SetCR2_NBYTES(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff0000)|value<<16)
}
func (o *I2C_Type) GetCR2_NBYTES() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff0000) >> 16
}
func (o *I2C_Type) SetCR2_NACK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR2_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR2_START(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetCR2_START() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetCR2_HEAD10R(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR2_HEAD10R() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR2_ADD10(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetCR2_ADD10() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetCR2_RD_WRN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetCR2_RD_WRN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetCR2_SADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetCR2_SADD() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x3ff
}

// I2C.OAR1: Own address register 1
func (o *I2C_Type) SetOAR1_OA1(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetOAR1_OA1() uint32 {
	return volatile.LoadUint32(&o.OAR1.Reg) & 0x3ff
}
func (o *I2C_Type) SetOAR1_OA1MODE(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetOAR1_OA1MODE() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetOAR1_OA1EN(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR1_OA1EN() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x8000) >> 15
}

// I2C.OAR2: Own address register 2
func (o *I2C_Type) SetOAR2_OA2(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0xfe)|value<<1)
}
func (o *I2C_Type) GetOAR2_OA2() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0xfe) >> 1
}
func (o *I2C_Type) SetOAR2_OA2MSK(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x700)|value<<8)
}
func (o *I2C_Type) GetOAR2_OA2MSK() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x700) >> 8
}
func (o *I2C_Type) SetOAR2_OA2EN(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR2_OA2EN() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x8000) >> 15
}

// I2C.TIMINGR: Timing register
func (o *I2C_Type) SetTIMINGR_SCLL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTIMINGR_SCLL() uint32 {
	return volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff
}
func (o *I2C_Type) SetTIMINGR_SCLH(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff00)|value<<8)
}
func (o *I2C_Type) GetTIMINGR_SCLH() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff00) >> 8
}
func (o *I2C_Type) SetTIMINGR_SDADEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000)|value<<16)
}
func (o *I2C_Type) GetTIMINGR_SDADEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000) >> 16
}
func (o *I2C_Type) SetTIMINGR_SCLDEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf00000)|value<<20)
}
func (o *I2C_Type) GetTIMINGR_SCLDEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf00000) >> 20
}
func (o *I2C_Type) SetTIMINGR_PRESC(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000000)|value<<28)
}
func (o *I2C_Type) GetTIMINGR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000000) >> 28
}

// I2C.TIMEOUTR: Status register 1
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTA(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff)|value)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTA() uint32 {
	return volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff
}
func (o *I2C_Type) SetTIMEOUTR_TIDLE(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetTIMEOUTR_TIDLE() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetTIMEOUTR_TIMOUTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetTIMEOUTR_TIMOUTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTB(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff0000)|value<<16)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTB() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff0000) >> 16
}
func (o *I2C_Type) SetTIMEOUTR_TEXTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetTIMEOUTR_TEXTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x80000000) >> 31
}

// I2C.ISR: Interrupt and Status register
func (o *I2C_Type) SetISR_ADDCODE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xfe0000)|value<<17)
}
func (o *I2C_Type) GetISR_ADDCODE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xfe0000) >> 17
}
func (o *I2C_Type) SetISR_DIR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetISR_DIR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetISR_ALERT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetISR_ALERT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetISR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetISR_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetISR_PECERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetISR_PECERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetISR_OVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetISR_OVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetISR_ARLO(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetISR_ARLO() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetISR_BERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetISR_BERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetISR_TCR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetISR_TCR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetISR_STOPF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetISR_STOPF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetISR_NACKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetISR_NACKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetISR_ADDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetISR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetISR_RXNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetISR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetISR_TXIS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetISR_TXIS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetISR_TXE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetISR_TXE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// I2C.ICR: Interrupt clear register
func (o *I2C_Type) SetICR_ALERTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetICR_ALERTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetICR_TIMOUTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetICR_TIMOUTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetICR_PECCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetICR_PECCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetICR_OVRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetICR_OVRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetICR_ARLOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetICR_ARLOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetICR_BERRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetICR_BERRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetICR_STOPCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetICR_STOPCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetICR_NACKCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetICR_NACKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetICR_ADDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetICR_ADDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}

// I2C.PECR: PEC register
func (o *I2C_Type) SetPECR_PEC(value uint32) {
	volatile.StoreUint32(&o.PECR.Reg, volatile.LoadUint32(&o.PECR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetPECR_PEC() uint32 {
	return volatile.LoadUint32(&o.PECR.Reg) & 0xff
}

// I2C.RXDR: Receive data register
func (o *I2C_Type) SetRXDR_RXDATA(value uint32) {
	volatile.StoreUint32(&o.RXDR.Reg, volatile.LoadUint32(&o.RXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetRXDR_RXDATA() uint32 {
	return volatile.LoadUint32(&o.RXDR.Reg) & 0xff
}

// I2C.TXDR: Transmit data register
func (o *I2C_Type) SetTXDR_TXDATA(value uint32) {
	volatile.StoreUint32(&o.TXDR.Reg, volatile.LoadUint32(&o.TXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTXDR_TXDATA() uint32 {
	return volatile.LoadUint32(&o.TXDR.Reg) & 0xff
}

// I2C.AUTOCR: I2C Autonomous mode control register
func (o *I2C_Type) SetAUTOCR_TCDMAEN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetAUTOCR_TCDMAEN() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetAUTOCR_TCRDMAEN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetAUTOCR_TCRDMAEN() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetAUTOCR_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0xf0000)|value<<16)
}
func (o *I2C_Type) GetAUTOCR_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0xf0000) >> 16
}
func (o *I2C_Type) SetAUTOCR_TRIGPOL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x100000)|value<<20)
}
func (o *I2C_Type) GetAUTOCR_TRIGPOL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x100000) >> 20
}
func (o *I2C_Type) SetAUTOCR_TRIGEN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x200000)|value<<21)
}
func (o *I2C_Type) GetAUTOCR_TRIGEN() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x200000) >> 21
}

// ICache
type ICache_Type struct {
	CR    volatile.Register32 // 0x0
	SR    volatile.Register32 // 0x4
	IER   volatile.Register32 // 0x8
	FCR   volatile.Register32 // 0xC
	HMONR volatile.Register32 // 0x10
	MMONR volatile.Register32 // 0x14
	_     [8]byte
	CRR0  volatile.Register32 // 0x20
	CRR1  volatile.Register32 // 0x24
	CRR2  volatile.Register32 // 0x28
	CRR3  volatile.Register32 // 0x2C
}

// ICache.CR: ICACHE control register
func (o *ICache_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *ICache_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *ICache_Type) SetCR_CACHEINV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetCR_CACHEINV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetCR_WAYSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetCR_WAYSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *ICache_Type) SetCR_HITMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *ICache_Type) GetCR_HITMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *ICache_Type) SetCR_MISSMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *ICache_Type) GetCR_MISSMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *ICache_Type) SetCR_HITMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *ICache_Type) GetCR_HITMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *ICache_Type) SetCR_MISSMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *ICache_Type) GetCR_MISSMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}

// ICache.SR: ICACHE status register
func (o *ICache_Type) SetSR_BUSYF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *ICache_Type) GetSR_BUSYF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *ICache_Type) SetSR_BSYENDF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetSR_BSYENDF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetSR_ERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetSR_ERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}

// ICache.IER: ICACHE interrupt enable register
func (o *ICache_Type) SetIER_BSYENDIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetIER_BSYENDIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetIER_ERRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetIER_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}

// ICache.FCR: ICACHE flag clear register
func (o *ICache_Type) SetFCR_CBSYENDF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetFCR_CBSYENDF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetFCR_CERRF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetFCR_CERRF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x4) >> 2
}

// ICache.HMONR: ICACHE hit monitor register
func (o *ICache_Type) SetHMONR(value uint32) {
	volatile.StoreUint32(&o.HMONR.Reg, value)
}
func (o *ICache_Type) GetHMONR() uint32 {
	return volatile.LoadUint32(&o.HMONR.Reg)
}

// ICache.MMONR: ICACHE miss monitor register
func (o *ICache_Type) SetMMONR_MISSMON(value uint32) {
	volatile.StoreUint32(&o.MMONR.Reg, volatile.LoadUint32(&o.MMONR.Reg)&^(0xffff)|value)
}
func (o *ICache_Type) GetMMONR_MISSMON() uint32 {
	return volatile.LoadUint32(&o.MMONR.Reg) & 0xffff
}

// ICache.CRR0: ICACHE region configuration register
func (o *ICache_Type) SetCRR0_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR0_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR0.Reg) & 0xff
}
func (o *ICache_Type) SetCRR0_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR0_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR0_REN(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR0_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR0_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR0_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR0_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR0_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR0_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR0_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x80000000) >> 31
}

// ICache.CRR1: ICACHE region configuration register
func (o *ICache_Type) SetCRR1_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR1_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR1.Reg) & 0xff
}
func (o *ICache_Type) SetCRR1_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR1_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR1_REN(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR1_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR1_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR1_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR1_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR1_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR1_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR1_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x80000000) >> 31
}

// ICache.CRR2: ICACHE region configuration register
func (o *ICache_Type) SetCRR2_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR2_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR2.Reg) & 0xff
}
func (o *ICache_Type) SetCRR2_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR2_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR2_REN(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR2_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR2_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR2_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR2_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR2_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR2_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR2_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x80000000) >> 31
}

// ICache.CRR3: ICACHE region configuration register
func (o *ICache_Type) SetCRR3_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR3_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR3.Reg) & 0xff
}
func (o *ICache_Type) SetCRR3_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR3_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR3_REN(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR3_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR3_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR3_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR3_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR3_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR3_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR3_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x80000000) >> 31
}

// Independent watchdog
type IWDG_Type struct {
	KR   volatile.Register32 // 0x0
	PR   volatile.Register32 // 0x4
	RLR  volatile.Register32 // 0x8
	SR   volatile.Register32 // 0xC
	WINR volatile.Register32 // 0x10
	EWCR volatile.Register32 // 0x14
}

// IWDG.KR: Key register
func (o *IWDG_Type) SetKR_KEY(value uint32) {
	volatile.StoreUint32(&o.KR.Reg, volatile.LoadUint32(&o.KR.Reg)&^(0xffff)|value)
}
func (o *IWDG_Type) GetKR_KEY() uint32 {
	return volatile.LoadUint32(&o.KR.Reg) & 0xffff
}

// IWDG.PR: Prescaler register
func (o *IWDG_Type) SetPR(value uint32) {
	volatile.StoreUint32(&o.PR.Reg, volatile.LoadUint32(&o.PR.Reg)&^(0xf)|value)
}
func (o *IWDG_Type) GetPR() uint32 {
	return volatile.LoadUint32(&o.PR.Reg) & 0xf
}

// IWDG.RLR: Reload register
func (o *IWDG_Type) SetRLR_RL(value uint32) {
	volatile.StoreUint32(&o.RLR.Reg, volatile.LoadUint32(&o.RLR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetRLR_RL() uint32 {
	return volatile.LoadUint32(&o.RLR.Reg) & 0xfff
}

// IWDG.SR: Status register
func (o *IWDG_Type) SetSR_EWIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000)|value<<14)
}
func (o *IWDG_Type) GetSR_EWIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000) >> 14
}
func (o *IWDG_Type) SetSR_EWU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *IWDG_Type) GetSR_EWU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *IWDG_Type) SetSR_WVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *IWDG_Type) GetSR_WVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *IWDG_Type) SetSR_RVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *IWDG_Type) GetSR_RVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *IWDG_Type) SetSR_PVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *IWDG_Type) GetSR_PVU() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// IWDG.WINR: Window register
func (o *IWDG_Type) SetWINR_WIN(value uint32) {
	volatile.StoreUint32(&o.WINR.Reg, volatile.LoadUint32(&o.WINR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetWINR_WIN() uint32 {
	return volatile.LoadUint32(&o.WINR.Reg) & 0xfff
}

// IWDG.EWCR: IWDG early wakeup interrupt register
func (o *IWDG_Type) SetEWCR_EWIT(value uint32) {
	volatile.StoreUint32(&o.EWCR.Reg, volatile.LoadUint32(&o.EWCR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetEWCR_EWIT() uint32 {
	return volatile.LoadUint32(&o.EWCR.Reg) & 0xfff
}
func (o *IWDG_Type) SetEWCR_EWIC(value uint32) {
	volatile.StoreUint32(&o.EWCR.Reg, volatile.LoadUint32(&o.EWCR.Reg)&^(0x4000)|value<<14)
}
func (o *IWDG_Type) GetEWCR_EWIC() uint32 {
	return (volatile.LoadUint32(&o.EWCR.Reg) & 0x4000) >> 14
}
func (o *IWDG_Type) SetEWCR_EWIE(value uint32) {
	volatile.StoreUint32(&o.EWCR.Reg, volatile.LoadUint32(&o.EWCR.Reg)&^(0x8000)|value<<15)
}
func (o *IWDG_Type) GetEWCR_EWIE() uint32 {
	return (volatile.LoadUint32(&o.EWCR.Reg) & 0x8000) >> 15
}

// LPDMA1
type LPDMA_Type struct {
	SECCFGR  volatile.Register32 // 0x0
	PRIVCFGR volatile.Register32 // 0x4
	_        [4]byte
	MISR     volatile.Register32 // 0xC
	SMISR    volatile.Register32 // 0x10
	_        [60]byte
	CH       [4]LPDMA_CH_Type // 0x50
}

// LPDMA.SECCFGR: LPDMA secure configuration register
func (o *LPDMA_Type) SetSECCFGR_SEC0(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *LPDMA_Type) GetSECCFGR_SEC0() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *LPDMA_Type) SetSECCFGR_SEC1(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *LPDMA_Type) GetSECCFGR_SEC1() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *LPDMA_Type) SetSECCFGR_SEC2(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *LPDMA_Type) GetSECCFGR_SEC2() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *LPDMA_Type) SetSECCFGR_SEC3(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *LPDMA_Type) GetSECCFGR_SEC3() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}

// LPDMA.PRIVCFGR: LPDMA privileged configuration register
func (o *LPDMA_Type) SetPRIVCFGR_PRIV0(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x2)|value<<1)
}
func (o *LPDMA_Type) GetPRIVCFGR_PRIV0() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x2) >> 1
}
func (o *LPDMA_Type) SetPRIVCFGR_PRIV1(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x4)|value<<2)
}
func (o *LPDMA_Type) GetPRIVCFGR_PRIV1() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x4) >> 2
}
func (o *LPDMA_Type) SetPRIVCFGR_PRIV2(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x8)|value<<3)
}
func (o *LPDMA_Type) GetPRIVCFGR_PRIV2() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x8) >> 3
}
func (o *LPDMA_Type) SetPRIVCFGR_PRIV3(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x10)|value<<4)
}
func (o *LPDMA_Type) GetPRIVCFGR_PRIV3() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x10) >> 4
}

// LPDMA.MISR: LPDMA non-secure masked interrupt status register
func (o *LPDMA_Type) SetMISR_MIS0(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *LPDMA_Type) GetMISR_MIS0() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *LPDMA_Type) SetMISR_MIS1(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *LPDMA_Type) GetMISR_MIS1() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *LPDMA_Type) SetMISR_MIS2(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8)|value<<3)
}
func (o *LPDMA_Type) GetMISR_MIS2() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8) >> 3
}
func (o *LPDMA_Type) SetMISR_MIS3(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10)|value<<4)
}
func (o *LPDMA_Type) GetMISR_MIS3() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10) >> 4
}

// LPDMA.SMISR: LPDMA secure masked interrupt status register
func (o *LPDMA_Type) SetSMISR_MIS0(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x2)|value<<1)
}
func (o *LPDMA_Type) GetSMISR_MIS0() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x2) >> 1
}
func (o *LPDMA_Type) SetSMISR_MIS1(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4)|value<<2)
}
func (o *LPDMA_Type) GetSMISR_MIS1() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4) >> 2
}
func (o *LPDMA_Type) SetSMISR_MIS2(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8)|value<<3)
}
func (o *LPDMA_Type) GetSMISR_MIS2() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8) >> 3
}
func (o *LPDMA_Type) SetSMISR_MIS3(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10)|value<<4)
}
func (o *LPDMA_Type) GetSMISR_MIS3() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10) >> 4
}

// Cluster CH%s, containing C?LBAR, C?FCR, C?SR, C?CR, C?TR1, C?TR2, C?BR1, C?SAR, C?DAR, C?LLR
type LPDMA_CH_Type struct {
	LBAR volatile.Register32 // 0x50
	_    [8]byte
	FCR  volatile.Register32 // 0x5C
	SR   volatile.Register32 // 0x60
	CR   volatile.Register32 // 0x64
	_    [40]byte
	TR1  volatile.Register32 // 0x90
	TR2  volatile.Register32 // 0x94
	BR1  volatile.Register32 // 0x98
	SAR  volatile.Register32 // 0x9C
	DAR  volatile.Register32 // 0xA0
	_    [40]byte
	LLR  volatile.Register32 // 0xCC
}

// LPDMA_CH.LBAR: channel x linked-list base address register
func (o *LPDMA_CH_Type) SetLBAR_LBA(value uint32) {
	volatile.StoreUint32(&o.LBAR.Reg, volatile.LoadUint32(&o.LBAR.Reg)&^(0xffff0000)|value<<16)
}
func (o *LPDMA_CH_Type) GetLBAR_LBA() uint32 {
	return (volatile.LoadUint32(&o.LBAR.Reg) & 0xffff0000) >> 16
}

// LPDMA_CH.FCR: LPDMA channel x flag clear register
func (o *LPDMA_CH_Type) SetFCR_TCF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x100)|value<<8)
}
func (o *LPDMA_CH_Type) GetFCR_TCF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x100) >> 8
}
func (o *LPDMA_CH_Type) SetFCR_HTF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x200)|value<<9)
}
func (o *LPDMA_CH_Type) GetFCR_HTF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x200) >> 9
}
func (o *LPDMA_CH_Type) SetFCR_DTEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x400)|value<<10)
}
func (o *LPDMA_CH_Type) GetFCR_DTEF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x400) >> 10
}
func (o *LPDMA_CH_Type) SetFCR_ULEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x800)|value<<11)
}
func (o *LPDMA_CH_Type) GetFCR_ULEF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x800) >> 11
}
func (o *LPDMA_CH_Type) SetFCR_USEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x1000)|value<<12)
}
func (o *LPDMA_CH_Type) GetFCR_USEF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x1000) >> 12
}
func (o *LPDMA_CH_Type) SetFCR_SUSPF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x2000)|value<<13)
}
func (o *LPDMA_CH_Type) GetFCR_SUSPF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x2000) >> 13
}

// LPDMA_CH.SR: channel x status register
func (o *LPDMA_CH_Type) SetSR_IDLEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *LPDMA_CH_Type) GetSR_IDLEF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *LPDMA_CH_Type) SetSR_TCF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *LPDMA_CH_Type) GetSR_TCF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *LPDMA_CH_Type) SetSR_HTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *LPDMA_CH_Type) GetSR_HTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *LPDMA_CH_Type) SetSR_DTEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *LPDMA_CH_Type) GetSR_DTEF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *LPDMA_CH_Type) SetSR_ULEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *LPDMA_CH_Type) GetSR_ULEF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *LPDMA_CH_Type) SetSR_USEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *LPDMA_CH_Type) GetSR_USEF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *LPDMA_CH_Type) SetSR_SUSPF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *LPDMA_CH_Type) GetSR_SUSPF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}

// LPDMA_CH.CR: channel x control register
func (o *LPDMA_CH_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *LPDMA_CH_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *LPDMA_CH_Type) SetCR_RESET(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *LPDMA_CH_Type) GetCR_RESET() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *LPDMA_CH_Type) SetCR_SUSP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *LPDMA_CH_Type) GetCR_SUSP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *LPDMA_CH_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *LPDMA_CH_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *LPDMA_CH_Type) SetCR_HTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *LPDMA_CH_Type) GetCR_HTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *LPDMA_CH_Type) SetCR_DTEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *LPDMA_CH_Type) GetCR_DTEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *LPDMA_CH_Type) SetCR_ULEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *LPDMA_CH_Type) GetCR_ULEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *LPDMA_CH_Type) SetCR_USEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *LPDMA_CH_Type) GetCR_USEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *LPDMA_CH_Type) SetCR_SUSPIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *LPDMA_CH_Type) GetCR_SUSPIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *LPDMA_CH_Type) SetCR_LSM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *LPDMA_CH_Type) GetCR_LSM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *LPDMA_CH_Type) SetCR_PRIO(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00000)|value<<22)
}
func (o *LPDMA_CH_Type) GetCR_PRIO() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00000) >> 22
}

// LPDMA_CH.TR1: LPDMA channel x transfer register 1
func (o *LPDMA_CH_Type) SetTR1_SDW_LOG2(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x3)|value)
}
func (o *LPDMA_CH_Type) GetTR1_SDW_LOG2() uint32 {
	return volatile.LoadUint32(&o.TR1.Reg) & 0x3
}
func (o *LPDMA_CH_Type) SetTR1_SINC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x8)|value<<3)
}
func (o *LPDMA_CH_Type) GetTR1_SINC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x8) >> 3
}
func (o *LPDMA_CH_Type) SetTR1_PAM(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x1800)|value<<11)
}
func (o *LPDMA_CH_Type) GetTR1_PAM() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x1800) >> 11
}
func (o *LPDMA_CH_Type) SetTR1_SSEC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x8000)|value<<15)
}
func (o *LPDMA_CH_Type) GetTR1_SSEC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x8000) >> 15
}
func (o *LPDMA_CH_Type) SetTR1_DDW_LOG2(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x30000)|value<<16)
}
func (o *LPDMA_CH_Type) GetTR1_DDW_LOG2() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x30000) >> 16
}
func (o *LPDMA_CH_Type) SetTR1_DINC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x80000)|value<<19)
}
func (o *LPDMA_CH_Type) GetTR1_DINC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x80000) >> 19
}
func (o *LPDMA_CH_Type) SetTR1_DSEC(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0x80000000)|value<<31)
}
func (o *LPDMA_CH_Type) GetTR1_DSEC() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0x80000000) >> 31
}

// LPDMA_CH.TR2: LPDMA channel x transfer register 2
func (o *LPDMA_CH_Type) SetTR2_REQSEL(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x1f)|value)
}
func (o *LPDMA_CH_Type) GetTR2_REQSEL() uint32 {
	return volatile.LoadUint32(&o.TR2.Reg) & 0x1f
}
func (o *LPDMA_CH_Type) SetTR2_SWREQ(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x200)|value<<9)
}
func (o *LPDMA_CH_Type) GetTR2_SWREQ() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x200) >> 9
}
func (o *LPDMA_CH_Type) SetTR2_BREQ(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x800)|value<<11)
}
func (o *LPDMA_CH_Type) GetTR2_BREQ() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x800) >> 11
}
func (o *LPDMA_CH_Type) SetTR2_TRIGM(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0xc000)|value<<14)
}
func (o *LPDMA_CH_Type) GetTR2_TRIGM() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0xc000) >> 14
}
func (o *LPDMA_CH_Type) SetTR2_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x1f0000)|value<<16)
}
func (o *LPDMA_CH_Type) GetTR2_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x1f0000) >> 16
}
func (o *LPDMA_CH_Type) SetTR2_TRIGPOL(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0x3000000)|value<<24)
}
func (o *LPDMA_CH_Type) GetTR2_TRIGPOL() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0x3000000) >> 24
}
func (o *LPDMA_CH_Type) SetTR2_TCEM(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *LPDMA_CH_Type) GetTR2_TCEM() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0xc0000000) >> 30
}

// LPDMA_CH.BR1: LPDMA channel x block register 1
func (o *LPDMA_CH_Type) SetBR1_BNDT(value uint32) {
	volatile.StoreUint32(&o.BR1.Reg, volatile.LoadUint32(&o.BR1.Reg)&^(0xffff)|value)
}
func (o *LPDMA_CH_Type) GetBR1_BNDT() uint32 {
	return volatile.LoadUint32(&o.BR1.Reg) & 0xffff
}

// LPDMA_CH.SAR: LPDMA channel x source address register
func (o *LPDMA_CH_Type) SetSAR(value uint32) {
	volatile.StoreUint32(&o.SAR.Reg, value)
}
func (o *LPDMA_CH_Type) GetSAR() uint32 {
	return volatile.LoadUint32(&o.SAR.Reg)
}

// LPDMA_CH.DAR: LPDMA channel x destination address register
func (o *LPDMA_CH_Type) SetDAR(value uint32) {
	volatile.StoreUint32(&o.DAR.Reg, value)
}
func (o *LPDMA_CH_Type) GetDAR() uint32 {
	return volatile.LoadUint32(&o.DAR.Reg)
}

// LPDMA_CH.LLR: LPDMA channel x linked-list address register
func (o *LPDMA_CH_Type) SetLLR_LA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0xfffc)|value<<2)
}
func (o *LPDMA_CH_Type) GetLLR_LA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0xfffc) >> 2
}
func (o *LPDMA_CH_Type) SetLLR_ULL(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x10000)|value<<16)
}
func (o *LPDMA_CH_Type) GetLLR_ULL() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x10000) >> 16
}
func (o *LPDMA_CH_Type) SetLLR_UDA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x8000000)|value<<27)
}
func (o *LPDMA_CH_Type) GetLLR_UDA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x8000000) >> 27
}
func (o *LPDMA_CH_Type) SetLLR_USA(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x10000000)|value<<28)
}
func (o *LPDMA_CH_Type) GetLLR_USA() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x10000000) >> 28
}
func (o *LPDMA_CH_Type) SetLLR_UB1(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x20000000)|value<<29)
}
func (o *LPDMA_CH_Type) GetLLR_UB1() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x20000000) >> 29
}
func (o *LPDMA_CH_Type) SetLLR_UT2(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x40000000)|value<<30)
}
func (o *LPDMA_CH_Type) GetLLR_UT2() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x40000000) >> 30
}
func (o *LPDMA_CH_Type) SetLLR_UT1(value uint32) {
	volatile.StoreUint32(&o.LLR.Reg, volatile.LoadUint32(&o.LLR.Reg)&^(0x80000000)|value<<31)
}
func (o *LPDMA_CH_Type) GetLLR_UT1() uint32 {
	return (volatile.LoadUint32(&o.LLR.Reg) & 0x80000000) >> 31
}

// LPGPIO1
type LPGPIO_Type struct {
	MODER volatile.Register32 // 0x0
	_     [12]byte
	IDR   volatile.Register32 // 0x10
	ODR   volatile.Register32 // 0x14
	BSRR  volatile.Register32 // 0x18
	_     [12]byte
	BRR   volatile.Register32 // 0x28
}

// LPGPIO.MODER: LPGPIO port mode register
func (o *LPGPIO_Type) SetMODER_MODE0(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x2)|value<<1)
}
func (o *LPGPIO_Type) GetMODER_MODE0() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x2) >> 1
}
func (o *LPGPIO_Type) SetMODER_MODE1(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x4)|value<<2)
}
func (o *LPGPIO_Type) GetMODER_MODE1() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x4) >> 2
}
func (o *LPGPIO_Type) SetMODER_MODE2(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x8)|value<<3)
}
func (o *LPGPIO_Type) GetMODER_MODE2() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x8) >> 3
}
func (o *LPGPIO_Type) SetMODER_MODE3(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x10)|value<<4)
}
func (o *LPGPIO_Type) GetMODER_MODE3() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x10) >> 4
}
func (o *LPGPIO_Type) SetMODER_MODE4(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x20)|value<<5)
}
func (o *LPGPIO_Type) GetMODER_MODE4() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x20) >> 5
}
func (o *LPGPIO_Type) SetMODER_MODE5(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x40)|value<<6)
}
func (o *LPGPIO_Type) GetMODER_MODE5() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x40) >> 6
}
func (o *LPGPIO_Type) SetMODER_MODE6(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x80)|value<<7)
}
func (o *LPGPIO_Type) GetMODER_MODE6() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x80) >> 7
}
func (o *LPGPIO_Type) SetMODER_MODE7(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x100)|value<<8)
}
func (o *LPGPIO_Type) GetMODER_MODE7() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x100) >> 8
}
func (o *LPGPIO_Type) SetMODER_MODE8(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x200)|value<<9)
}
func (o *LPGPIO_Type) GetMODER_MODE8() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x200) >> 9
}
func (o *LPGPIO_Type) SetMODER_MODE9(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x400)|value<<10)
}
func (o *LPGPIO_Type) GetMODER_MODE9() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x400) >> 10
}
func (o *LPGPIO_Type) SetMODER_MODE10(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x800)|value<<11)
}
func (o *LPGPIO_Type) GetMODER_MODE10() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x800) >> 11
}
func (o *LPGPIO_Type) SetMODER_MODE11(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x1000)|value<<12)
}
func (o *LPGPIO_Type) GetMODER_MODE11() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x1000) >> 12
}
func (o *LPGPIO_Type) SetMODER_MODE12(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x2000)|value<<13)
}
func (o *LPGPIO_Type) GetMODER_MODE12() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x2000) >> 13
}
func (o *LPGPIO_Type) SetMODER_MODE13(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x4000)|value<<14)
}
func (o *LPGPIO_Type) GetMODER_MODE13() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x4000) >> 14
}
func (o *LPGPIO_Type) SetMODER_MODE14(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x8000)|value<<15)
}
func (o *LPGPIO_Type) GetMODER_MODE14() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x8000) >> 15
}
func (o *LPGPIO_Type) SetMODER_MODE15(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x10000)|value<<16)
}
func (o *LPGPIO_Type) GetMODER_MODE15() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x10000) >> 16
}

// LPGPIO.IDR: LPGPIO port input data register
func (o *LPGPIO_Type) SetIDR_ID0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *LPGPIO_Type) GetIDR_ID0() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *LPGPIO_Type) SetIDR_ID1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *LPGPIO_Type) GetIDR_ID1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *LPGPIO_Type) SetIDR_ID2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *LPGPIO_Type) GetIDR_ID2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *LPGPIO_Type) SetIDR_ID3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *LPGPIO_Type) GetIDR_ID3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *LPGPIO_Type) SetIDR_ID4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *LPGPIO_Type) GetIDR_ID4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *LPGPIO_Type) SetIDR_ID5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *LPGPIO_Type) GetIDR_ID5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *LPGPIO_Type) SetIDR_ID6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *LPGPIO_Type) GetIDR_ID6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *LPGPIO_Type) SetIDR_ID7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *LPGPIO_Type) GetIDR_ID7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *LPGPIO_Type) SetIDR_ID8(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *LPGPIO_Type) GetIDR_ID8() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *LPGPIO_Type) SetIDR_ID9(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *LPGPIO_Type) GetIDR_ID9() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *LPGPIO_Type) SetIDR_ID10(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *LPGPIO_Type) GetIDR_ID10() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *LPGPIO_Type) SetIDR_ID11(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *LPGPIO_Type) GetIDR_ID11() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *LPGPIO_Type) SetIDR_ID12(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *LPGPIO_Type) GetIDR_ID12() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *LPGPIO_Type) SetIDR_ID13(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000)|value<<14)
}
func (o *LPGPIO_Type) GetIDR_ID13() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000) >> 14
}
func (o *LPGPIO_Type) SetIDR_ID14(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000)|value<<15)
}
func (o *LPGPIO_Type) GetIDR_ID14() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000) >> 15
}
func (o *LPGPIO_Type) SetIDR_ID15(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *LPGPIO_Type) GetIDR_ID15() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}

// LPGPIO.ODR: LPGPIO port output data register
func (o *LPGPIO_Type) SetODR_OD0(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2)|value<<1)
}
func (o *LPGPIO_Type) GetODR_OD0() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2) >> 1
}
func (o *LPGPIO_Type) SetODR_OD1(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4)|value<<2)
}
func (o *LPGPIO_Type) GetODR_OD1() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4) >> 2
}
func (o *LPGPIO_Type) SetODR_OD2(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8)|value<<3)
}
func (o *LPGPIO_Type) GetODR_OD2() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8) >> 3
}
func (o *LPGPIO_Type) SetODR_OD3(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10)|value<<4)
}
func (o *LPGPIO_Type) GetODR_OD3() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10) >> 4
}
func (o *LPGPIO_Type) SetODR_OD4(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20)|value<<5)
}
func (o *LPGPIO_Type) GetODR_OD4() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20) >> 5
}
func (o *LPGPIO_Type) SetODR_OD5(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40)|value<<6)
}
func (o *LPGPIO_Type) GetODR_OD5() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40) >> 6
}
func (o *LPGPIO_Type) SetODR_OD6(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80)|value<<7)
}
func (o *LPGPIO_Type) GetODR_OD6() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80) >> 7
}
func (o *LPGPIO_Type) SetODR_OD7(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x100)|value<<8)
}
func (o *LPGPIO_Type) GetODR_OD7() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x100) >> 8
}
func (o *LPGPIO_Type) SetODR_OD8(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x200)|value<<9)
}
func (o *LPGPIO_Type) GetODR_OD8() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x200) >> 9
}
func (o *LPGPIO_Type) SetODR_OD9(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x400)|value<<10)
}
func (o *LPGPIO_Type) GetODR_OD9() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x400) >> 10
}
func (o *LPGPIO_Type) SetODR_OD10(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x800)|value<<11)
}
func (o *LPGPIO_Type) GetODR_OD10() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x800) >> 11
}
func (o *LPGPIO_Type) SetODR_OD11(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1000)|value<<12)
}
func (o *LPGPIO_Type) GetODR_OD11() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x1000) >> 12
}
func (o *LPGPIO_Type) SetODR_OD12(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2000)|value<<13)
}
func (o *LPGPIO_Type) GetODR_OD12() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2000) >> 13
}
func (o *LPGPIO_Type) SetODR_OD13(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4000)|value<<14)
}
func (o *LPGPIO_Type) GetODR_OD13() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4000) >> 14
}
func (o *LPGPIO_Type) SetODR_OD14(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8000)|value<<15)
}
func (o *LPGPIO_Type) GetODR_OD14() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8000) >> 15
}
func (o *LPGPIO_Type) SetODR_OD15(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10000)|value<<16)
}
func (o *LPGPIO_Type) GetODR_OD15() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10000) >> 16
}

// LPGPIO.BSRR: LPGPIO port bit set/reset register
func (o *LPGPIO_Type) SetBSRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000)|value<<17)
}
func (o *LPGPIO_Type) GetBSRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000) >> 17
}
func (o *LPGPIO_Type) SetBSRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000)|value<<18)
}
func (o *LPGPIO_Type) GetBSRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000) >> 18
}
func (o *LPGPIO_Type) SetBSRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000)|value<<19)
}
func (o *LPGPIO_Type) GetBSRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000) >> 19
}
func (o *LPGPIO_Type) SetBSRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100000)|value<<20)
}
func (o *LPGPIO_Type) GetBSRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100000) >> 20
}
func (o *LPGPIO_Type) SetBSRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200000)|value<<21)
}
func (o *LPGPIO_Type) GetBSRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200000) >> 21
}
func (o *LPGPIO_Type) SetBSRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400000)|value<<22)
}
func (o *LPGPIO_Type) GetBSRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400000) >> 22
}
func (o *LPGPIO_Type) SetBSRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800000)|value<<23)
}
func (o *LPGPIO_Type) GetBSRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800000) >> 23
}
func (o *LPGPIO_Type) SetBSRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000000)|value<<24)
}
func (o *LPGPIO_Type) GetBSRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000000) >> 24
}
func (o *LPGPIO_Type) SetBSRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000000)|value<<25)
}
func (o *LPGPIO_Type) GetBSRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000000) >> 25
}
func (o *LPGPIO_Type) SetBSRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000000)|value<<26)
}
func (o *LPGPIO_Type) GetBSRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000000) >> 26
}
func (o *LPGPIO_Type) SetBSRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000000)|value<<27)
}
func (o *LPGPIO_Type) GetBSRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000000) >> 27
}
func (o *LPGPIO_Type) SetBSRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000000)|value<<28)
}
func (o *LPGPIO_Type) GetBSRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000000) >> 28
}
func (o *LPGPIO_Type) SetBSRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000000)|value<<29)
}
func (o *LPGPIO_Type) GetBSRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000000) >> 29
}
func (o *LPGPIO_Type) SetBSRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000000)|value<<30)
}
func (o *LPGPIO_Type) GetBSRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000000) >> 30
}
func (o *LPGPIO_Type) SetBSRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000000)|value<<31)
}
func (o *LPGPIO_Type) GetBSRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000000) >> 31
}
func (o *LPGPIO_Type) SetBSRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x0)|value<<32)
}
func (o *LPGPIO_Type) GetBSRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x0) >> 32
}
func (o *LPGPIO_Type) SetBSRR_BS0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2)|value<<1)
}
func (o *LPGPIO_Type) GetBSRR_BS0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2) >> 1
}
func (o *LPGPIO_Type) SetBSRR_BS1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4)|value<<2)
}
func (o *LPGPIO_Type) GetBSRR_BS1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4) >> 2
}
func (o *LPGPIO_Type) SetBSRR_BS2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8)|value<<3)
}
func (o *LPGPIO_Type) GetBSRR_BS2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8) >> 3
}
func (o *LPGPIO_Type) SetBSRR_BS3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10)|value<<4)
}
func (o *LPGPIO_Type) GetBSRR_BS3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10) >> 4
}
func (o *LPGPIO_Type) SetBSRR_BS4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20)|value<<5)
}
func (o *LPGPIO_Type) GetBSRR_BS4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20) >> 5
}
func (o *LPGPIO_Type) SetBSRR_BS5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40)|value<<6)
}
func (o *LPGPIO_Type) GetBSRR_BS5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40) >> 6
}
func (o *LPGPIO_Type) SetBSRR_BS6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80)|value<<7)
}
func (o *LPGPIO_Type) GetBSRR_BS6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80) >> 7
}
func (o *LPGPIO_Type) SetBSRR_BS7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100)|value<<8)
}
func (o *LPGPIO_Type) GetBSRR_BS7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100) >> 8
}
func (o *LPGPIO_Type) SetBSRR_BS8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200)|value<<9)
}
func (o *LPGPIO_Type) GetBSRR_BS8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200) >> 9
}
func (o *LPGPIO_Type) SetBSRR_BS9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400)|value<<10)
}
func (o *LPGPIO_Type) GetBSRR_BS9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400) >> 10
}
func (o *LPGPIO_Type) SetBSRR_BS10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800)|value<<11)
}
func (o *LPGPIO_Type) GetBSRR_BS10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800) >> 11
}
func (o *LPGPIO_Type) SetBSRR_BS11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000)|value<<12)
}
func (o *LPGPIO_Type) GetBSRR_BS11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000) >> 12
}
func (o *LPGPIO_Type) SetBSRR_BS12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000)|value<<13)
}
func (o *LPGPIO_Type) GetBSRR_BS12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000) >> 13
}
func (o *LPGPIO_Type) SetBSRR_BS13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000)|value<<14)
}
func (o *LPGPIO_Type) GetBSRR_BS13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000) >> 14
}
func (o *LPGPIO_Type) SetBSRR_BS14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000)|value<<15)
}
func (o *LPGPIO_Type) GetBSRR_BS14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000) >> 15
}
func (o *LPGPIO_Type) SetBSRR_BS15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000)|value<<16)
}
func (o *LPGPIO_Type) GetBSRR_BS15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000) >> 16
}

// LPGPIO.BRR: LPGPIO port bit reset register
func (o *LPGPIO_Type) SetBRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2)|value<<1)
}
func (o *LPGPIO_Type) GetBRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2) >> 1
}
func (o *LPGPIO_Type) SetBRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4)|value<<2)
}
func (o *LPGPIO_Type) GetBRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4) >> 2
}
func (o *LPGPIO_Type) SetBRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8)|value<<3)
}
func (o *LPGPIO_Type) GetBRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8) >> 3
}
func (o *LPGPIO_Type) SetBRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10)|value<<4)
}
func (o *LPGPIO_Type) GetBRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10) >> 4
}
func (o *LPGPIO_Type) SetBRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x20)|value<<5)
}
func (o *LPGPIO_Type) GetBRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x20) >> 5
}
func (o *LPGPIO_Type) SetBRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x40)|value<<6)
}
func (o *LPGPIO_Type) GetBRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x40) >> 6
}
func (o *LPGPIO_Type) SetBRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x80)|value<<7)
}
func (o *LPGPIO_Type) GetBRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x80) >> 7
}
func (o *LPGPIO_Type) SetBRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x100)|value<<8)
}
func (o *LPGPIO_Type) GetBRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x100) >> 8
}
func (o *LPGPIO_Type) SetBRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x200)|value<<9)
}
func (o *LPGPIO_Type) GetBRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x200) >> 9
}
func (o *LPGPIO_Type) SetBRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x400)|value<<10)
}
func (o *LPGPIO_Type) GetBRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x400) >> 10
}
func (o *LPGPIO_Type) SetBRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x800)|value<<11)
}
func (o *LPGPIO_Type) GetBRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x800) >> 11
}
func (o *LPGPIO_Type) SetBRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x1000)|value<<12)
}
func (o *LPGPIO_Type) GetBRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x1000) >> 12
}
func (o *LPGPIO_Type) SetBRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2000)|value<<13)
}
func (o *LPGPIO_Type) GetBRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2000) >> 13
}
func (o *LPGPIO_Type) SetBRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4000)|value<<14)
}
func (o *LPGPIO_Type) GetBRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4000) >> 14
}
func (o *LPGPIO_Type) SetBRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8000)|value<<15)
}
func (o *LPGPIO_Type) GetBRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8000) >> 15
}
func (o *LPGPIO_Type) SetBRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10000)|value<<16)
}
func (o *LPGPIO_Type) GetBRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10000) >> 16
}

// Low power timer
type LPTIM_Type struct {
	ISR_output  volatile.Register32 // 0x0
	ICR_output  volatile.Register32 // 0x4
	DIER_output volatile.Register32 // 0x8
	CFGR        volatile.Register32 // 0xC
	CR          volatile.Register32 // 0x10
	CCR1        volatile.Register32 // 0x14
	ARR         volatile.Register32 // 0x18
	CNT         volatile.Register32 // 0x1C
	_           [4]byte
	CFGR2       volatile.Register32 // 0x24
	RCR         volatile.Register32 // 0x28
	CCMR1       volatile.Register32 // 0x2C
	_           [4]byte
	CCR2        volatile.Register32 // 0x34
}

// LPTIM.ISR_output: Interrupt and Status Register (output mode)
func (o *LPTIM_Type) SetISR_output_DIEROK(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x1000000)|value<<24)
}
func (o *LPTIM_Type) GetISR_output_DIEROK() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x1000000) >> 24
}
func (o *LPTIM_Type) SetISR_output_CMP2OK(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x80000)|value<<19)
}
func (o *LPTIM_Type) GetISR_output_CMP2OK() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x80000) >> 19
}
func (o *LPTIM_Type) SetISR_output_CC2IF(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x200)|value<<9)
}
func (o *LPTIM_Type) GetISR_output_CC2IF() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x200) >> 9
}
func (o *LPTIM_Type) SetISR_output_REPOK(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x100)|value<<8)
}
func (o *LPTIM_Type) GetISR_output_REPOK() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x100) >> 8
}
func (o *LPTIM_Type) SetISR_output_UE(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x80)|value<<7)
}
func (o *LPTIM_Type) GetISR_output_UE() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x80) >> 7
}
func (o *LPTIM_Type) SetISR_output_DOWN(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x40)|value<<6)
}
func (o *LPTIM_Type) GetISR_output_DOWN() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x40) >> 6
}
func (o *LPTIM_Type) SetISR_output_UP(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x20)|value<<5)
}
func (o *LPTIM_Type) GetISR_output_UP() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x20) >> 5
}
func (o *LPTIM_Type) SetISR_output_ARROK(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetISR_output_ARROK() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetISR_output_CMP1OK(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetISR_output_CMP1OK() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x8) >> 3
}
func (o *LPTIM_Type) SetISR_output_EXTTRIG(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetISR_output_EXTTRIG() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetISR_output_ARRM(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetISR_output_ARRM() uint32 {
	return (volatile.LoadUint32(&o.ISR_output.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetISR_output_CC1IF(value uint32) {
	volatile.StoreUint32(&o.ISR_output.Reg, volatile.LoadUint32(&o.ISR_output.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetISR_output_CC1IF() uint32 {
	return volatile.LoadUint32(&o.ISR_output.Reg) & 0x1
}

// LPTIM.ICR_output: Interrupt Clear Register (output mode)
func (o *LPTIM_Type) SetICR_output_DIEROKCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x1000000)|value<<24)
}
func (o *LPTIM_Type) GetICR_output_DIEROKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x1000000) >> 24
}
func (o *LPTIM_Type) SetICR_output_CMP2OKCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x80000)|value<<19)
}
func (o *LPTIM_Type) GetICR_output_CMP2OKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x80000) >> 19
}
func (o *LPTIM_Type) SetICR_output_CC2CF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x200)|value<<9)
}
func (o *LPTIM_Type) GetICR_output_CC2CF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x200) >> 9
}
func (o *LPTIM_Type) SetICR_output_REPOKCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x100)|value<<8)
}
func (o *LPTIM_Type) GetICR_output_REPOKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x100) >> 8
}
func (o *LPTIM_Type) SetICR_output_UECF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x80)|value<<7)
}
func (o *LPTIM_Type) GetICR_output_UECF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x80) >> 7
}
func (o *LPTIM_Type) SetICR_output_DOWNCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x40)|value<<6)
}
func (o *LPTIM_Type) GetICR_output_DOWNCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x40) >> 6
}
func (o *LPTIM_Type) SetICR_output_UPCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x20)|value<<5)
}
func (o *LPTIM_Type) GetICR_output_UPCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x20) >> 5
}
func (o *LPTIM_Type) SetICR_output_ARROKCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetICR_output_ARROKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetICR_output_CMP1OKCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetICR_output_CMP1OKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x8) >> 3
}
func (o *LPTIM_Type) SetICR_output_EXTTRIGCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetICR_output_EXTTRIGCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetICR_output_ARRMCF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetICR_output_ARRMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR_output.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetICR_output_CC1IF(value uint32) {
	volatile.StoreUint32(&o.ICR_output.Reg, volatile.LoadUint32(&o.ICR_output.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetICR_output_CC1IF() uint32 {
	return volatile.LoadUint32(&o.ICR_output.Reg) & 0x1
}

// LPTIM.DIER_output: LPTIM interrupt Enable Register (output mode)
func (o *LPTIM_Type) SetDIER_output_UEDE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x800000)|value<<23)
}
func (o *LPTIM_Type) GetDIER_output_UEDE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x800000) >> 23
}
func (o *LPTIM_Type) SetDIER_output_CMP2OKIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x80000)|value<<19)
}
func (o *LPTIM_Type) GetDIER_output_CMP2OKIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x80000) >> 19
}
func (o *LPTIM_Type) SetDIER_output_CC2IE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x200)|value<<9)
}
func (o *LPTIM_Type) GetDIER_output_CC2IE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x200) >> 9
}
func (o *LPTIM_Type) SetDIER_output_REPOKIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x100)|value<<8)
}
func (o *LPTIM_Type) GetDIER_output_REPOKIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x100) >> 8
}
func (o *LPTIM_Type) SetDIER_output_UEIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x80)|value<<7)
}
func (o *LPTIM_Type) GetDIER_output_UEIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x80) >> 7
}
func (o *LPTIM_Type) SetDIER_output_DOWNIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x40)|value<<6)
}
func (o *LPTIM_Type) GetDIER_output_DOWNIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x40) >> 6
}
func (o *LPTIM_Type) SetDIER_output_UPIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x20)|value<<5)
}
func (o *LPTIM_Type) GetDIER_output_UPIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x20) >> 5
}
func (o *LPTIM_Type) SetDIER_output_ARROKIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetDIER_output_ARROKIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetDIER_output_CMP1OKIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetDIER_output_CMP1OKIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x8) >> 3
}
func (o *LPTIM_Type) SetDIER_output_EXTTRIGIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetDIER_output_EXTTRIGIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetDIER_output_ARRMIE(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetDIER_output_ARRMIE() uint32 {
	return (volatile.LoadUint32(&o.DIER_output.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetDIER_output_CC1IF(value uint32) {
	volatile.StoreUint32(&o.DIER_output.Reg, volatile.LoadUint32(&o.DIER_output.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetDIER_output_CC1IF() uint32 {
	return volatile.LoadUint32(&o.DIER_output.Reg) & 0x1
}

// LPTIM.CFGR: Configuration Register
func (o *LPTIM_Type) SetCFGR_ENC(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1000000)|value<<24)
}
func (o *LPTIM_Type) GetCFGR_ENC() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x1000000) >> 24
}
func (o *LPTIM_Type) SetCFGR_COUNTMODE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x800000)|value<<23)
}
func (o *LPTIM_Type) GetCFGR_COUNTMODE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x800000) >> 23
}
func (o *LPTIM_Type) SetCFGR_PRELOAD(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x400000)|value<<22)
}
func (o *LPTIM_Type) GetCFGR_PRELOAD() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x400000) >> 22
}
func (o *LPTIM_Type) SetCFGR_WAVPOL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x200000)|value<<21)
}
func (o *LPTIM_Type) GetCFGR_WAVPOL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x200000) >> 21
}
func (o *LPTIM_Type) SetCFGR_WAVE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x100000)|value<<20)
}
func (o *LPTIM_Type) GetCFGR_WAVE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x100000) >> 20
}
func (o *LPTIM_Type) SetCFGR_TIMOUT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x80000)|value<<19)
}
func (o *LPTIM_Type) GetCFGR_TIMOUT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x80000) >> 19
}
func (o *LPTIM_Type) SetCFGR_TRIGEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x60000)|value<<17)
}
func (o *LPTIM_Type) GetCFGR_TRIGEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x60000) >> 17
}
func (o *LPTIM_Type) SetCFGR_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xe000)|value<<13)
}
func (o *LPTIM_Type) GetCFGR_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xe000) >> 13
}
func (o *LPTIM_Type) SetCFGR_PRESC(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xe00)|value<<9)
}
func (o *LPTIM_Type) GetCFGR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xe00) >> 9
}
func (o *LPTIM_Type) SetCFGR_TRGFLT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xc0)|value<<6)
}
func (o *LPTIM_Type) GetCFGR_TRGFLT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xc0) >> 6
}
func (o *LPTIM_Type) SetCFGR_CKFLT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x18)|value<<3)
}
func (o *LPTIM_Type) GetCFGR_CKFLT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x18) >> 3
}
func (o *LPTIM_Type) SetCFGR_CKPOL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x6)|value<<1)
}
func (o *LPTIM_Type) GetCFGR_CKPOL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x6) >> 1
}
func (o *LPTIM_Type) SetCFGR_CKSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetCFGR_CKSEL() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0x1
}

// LPTIM.CR: Control Register
func (o *LPTIM_Type) SetCR_RSTARE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetCR_RSTARE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetCR_COUNTRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetCR_COUNTRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *LPTIM_Type) SetCR_CNTSTRT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetCR_CNTSTRT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetCR_SNGSTRT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetCR_SNGSTRT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetCR_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetCR_ENABLE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// LPTIM.CCR1: Compare Register
func (o *LPTIM_Type) SetCCR1(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0xffff)|value)
}
func (o *LPTIM_Type) GetCCR1() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0xffff
}

// LPTIM.ARR: Autoreload Register
func (o *LPTIM_Type) SetARR(value uint32) {
	volatile.StoreUint32(&o.ARR.Reg, volatile.LoadUint32(&o.ARR.Reg)&^(0xffff)|value)
}
func (o *LPTIM_Type) GetARR() uint32 {
	return volatile.LoadUint32(&o.ARR.Reg) & 0xffff
}

// LPTIM.CNT: Counter Register
func (o *LPTIM_Type) SetCNT(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0xffff)|value)
}
func (o *LPTIM_Type) GetCNT() uint32 {
	return volatile.LoadUint32(&o.CNT.Reg) & 0xffff
}

// LPTIM.CFGR2: LPTIM configuration register 2
func (o *LPTIM_Type) SetCFGR2_IC2SEL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x300000)|value<<20)
}
func (o *LPTIM_Type) GetCFGR2_IC2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x300000) >> 20
}
func (o *LPTIM_Type) SetCFGR2_IC1SEL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x30000)|value<<16)
}
func (o *LPTIM_Type) GetCFGR2_IC1SEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x30000) >> 16
}
func (o *LPTIM_Type) SetCFGR2_IN2SEL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x30)|value<<4)
}
func (o *LPTIM_Type) GetCFGR2_IN2SEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x30) >> 4
}
func (o *LPTIM_Type) SetCFGR2_IN1SEL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x3)|value)
}
func (o *LPTIM_Type) GetCFGR2_IN1SEL() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x3
}

// LPTIM.RCR: LPTIM repetition register
func (o *LPTIM_Type) SetRCR_REP(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xff)|value)
}
func (o *LPTIM_Type) GetRCR_REP() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xff
}

// LPTIM.CCMR1: LPTIM capture/compare mode register 1
func (o *LPTIM_Type) SetCCMR1_CC1SEL(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetCCMR1_CC1SEL() uint32 {
	return volatile.LoadUint32(&o.CCMR1.Reg) & 0x1
}
func (o *LPTIM_Type) SetCCMR1_CC1E(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetCCMR1_CC1E() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetCCMR1_CC1P(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0xc)|value<<2)
}
func (o *LPTIM_Type) GetCCMR1_CC1P() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0xc) >> 2
}
func (o *LPTIM_Type) SetCCMR1_IC1PSC(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x300)|value<<8)
}
func (o *LPTIM_Type) GetCCMR1_IC1PSC() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0x300) >> 8
}
func (o *LPTIM_Type) SetCCMR1_IC1F(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x3000)|value<<12)
}
func (o *LPTIM_Type) GetCCMR1_IC1F() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0x3000) >> 12
}
func (o *LPTIM_Type) SetCCMR1_CC2SEL(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x10000)|value<<16)
}
func (o *LPTIM_Type) GetCCMR1_CC2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0x10000) >> 16
}
func (o *LPTIM_Type) SetCCMR1_CC2E(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x20000)|value<<17)
}
func (o *LPTIM_Type) GetCCMR1_CC2E() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0x20000) >> 17
}
func (o *LPTIM_Type) SetCCMR1_CC2P(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0xc0000)|value<<18)
}
func (o *LPTIM_Type) GetCCMR1_CC2P() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0xc0000) >> 18
}
func (o *LPTIM_Type) SetCCMR1_IC2PSC(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x3000000)|value<<24)
}
func (o *LPTIM_Type) GetCCMR1_IC2PSC() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0x3000000) >> 24
}
func (o *LPTIM_Type) SetCCMR1_IC2F(value uint32) {
	volatile.StoreUint32(&o.CCMR1.Reg, volatile.LoadUint32(&o.CCMR1.Reg)&^(0x30000000)|value<<28)
}
func (o *LPTIM_Type) GetCCMR1_IC2F() uint32 {
	return (volatile.LoadUint32(&o.CCMR1.Reg) & 0x30000000) >> 28
}

// LPTIM.CCR2: LPTIM Compare Register 2
func (o *LPTIM_Type) SetCCR2(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0xffff)|value)
}
func (o *LPTIM_Type) GetCCR2() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0xffff
}

// Universal synchronous asynchronous receiver transmitter
type LPUART_Type struct {
	CR1    volatile.Register32 // 0x0
	CR2    volatile.Register32 // 0x4
	CR3    volatile.Register32 // 0x8
	BRR    volatile.Register32 // 0xC
	_      [8]byte
	RQR    volatile.Register32 // 0x18
	ISR    volatile.Register32 // 0x1C
	ICR    volatile.Register32 // 0x20
	RDR    volatile.Register32 // 0x24
	TDR    volatile.Register32 // 0x28
	PRESC  volatile.Register32 // 0x2C
	AUTOCR volatile.Register32 // 0x30
}

// LPUART.CR1: Control register 1
func (o *LPUART_Type) SetCR1_RXFFIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000000)|value<<31)
}
func (o *LPUART_Type) GetCR1_RXFFIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000000) >> 31
}
func (o *LPUART_Type) SetCR1_TXFEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *LPUART_Type) GetCR1_TXFEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *LPUART_Type) SetCR1_FIFOEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000000)|value<<29)
}
func (o *LPUART_Type) GetCR1_FIFOEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000000) >> 29
}
func (o *LPUART_Type) SetCR1_M1(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000000)|value<<28)
}
func (o *LPUART_Type) GetCR1_M1() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000000) >> 28
}
func (o *LPUART_Type) SetCR1_DEAT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x3e00000)|value<<21)
}
func (o *LPUART_Type) GetCR1_DEAT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x3e00000) >> 21
}
func (o *LPUART_Type) SetCR1_DEDT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *LPUART_Type) GetCR1_DEDT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1f0000) >> 16
}
func (o *LPUART_Type) SetCR1_CMIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *LPUART_Type) GetCR1_CMIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *LPUART_Type) SetCR1_MME(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *LPUART_Type) GetCR1_MME() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *LPUART_Type) SetCR1_M0(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *LPUART_Type) GetCR1_M0() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *LPUART_Type) SetCR1_WAKE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *LPUART_Type) GetCR1_WAKE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *LPUART_Type) SetCR1_PCE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *LPUART_Type) GetCR1_PCE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *LPUART_Type) SetCR1_PS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetCR1_PS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetCR1_PEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *LPUART_Type) GetCR1_PEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *LPUART_Type) SetCR1_TXEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *LPUART_Type) GetCR1_TXEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *LPUART_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetCR1_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *LPUART_Type) GetCR1_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *LPUART_Type) SetCR1_IDLEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetCR1_IDLEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetCR1_TE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetCR1_TE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetCR1_RE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetCR1_RE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetCR1_UESM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetCR1_UESM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *LPUART_Type) SetCR1_UE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetCR1_UE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}

// LPUART.CR2: Control register 2
func (o *LPUART_Type) SetCR2_ADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff000000)|value<<24)
}
func (o *LPUART_Type) GetCR2_ADD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff000000) >> 24
}
func (o *LPUART_Type) SetCR2_MSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000)|value<<19)
}
func (o *LPUART_Type) GetCR2_MSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000) >> 19
}
func (o *LPUART_Type) SetCR2_DATAINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *LPUART_Type) GetCR2_DATAINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *LPUART_Type) SetCR2_TXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *LPUART_Type) GetCR2_TXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *LPUART_Type) SetCR2_RXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *LPUART_Type) GetCR2_RXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *LPUART_Type) SetCR2_SWAP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *LPUART_Type) GetCR2_SWAP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *LPUART_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3000)|value<<12)
}
func (o *LPUART_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x3000) >> 12
}
func (o *LPUART_Type) SetCR2_ADDM7(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetCR2_ADDM7() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}

// LPUART.CR3: Control register 3
func (o *LPUART_Type) SetCR3_TXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000000)|value<<29)
}
func (o *LPUART_Type) GetCR3_TXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000000) >> 29
}
func (o *LPUART_Type) SetCR3_RXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10000000)|value<<28)
}
func (o *LPUART_Type) GetCR3_RXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10000000) >> 28
}
func (o *LPUART_Type) SetCR3_RXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe000000)|value<<25)
}
func (o *LPUART_Type) GetCR3_RXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe000000) >> 25
}
func (o *LPUART_Type) SetCR3_TXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800000)|value<<23)
}
func (o *LPUART_Type) GetCR3_TXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800000) >> 23
}
func (o *LPUART_Type) SetCR3_DEP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *LPUART_Type) GetCR3_DEP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}
func (o *LPUART_Type) SetCR3_DEM(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *LPUART_Type) GetCR3_DEM() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *LPUART_Type) SetCR3_DDRE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *LPUART_Type) GetCR3_DDRE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *LPUART_Type) SetCR3_OVRDIS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *LPUART_Type) GetCR3_OVRDIS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}
func (o *LPUART_Type) SetCR3_CTSIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *LPUART_Type) GetCR3_CTSIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *LPUART_Type) SetCR3_CTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetCR3_CTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetCR3_RTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *LPUART_Type) GetCR3_RTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *LPUART_Type) SetCR3_DMAT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *LPUART_Type) GetCR3_DMAT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *LPUART_Type) SetCR3_DMAR(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetCR3_DMAR() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetCR3_HDSEL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetCR3_HDSEL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetCR3_EIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetCR3_EIE() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}

// LPUART.BRR: Baud rate register
func (o *LPUART_Type) SetBRR(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0xfffff)|value)
}
func (o *LPUART_Type) GetBRR() uint32 {
	return volatile.LoadUint32(&o.BRR.Reg) & 0xfffff
}

// LPUART.RQR: Request register
func (o *LPUART_Type) SetRQR_TXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetRQR_TXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetRQR_RXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetRQR_RXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetRQR_MMRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetRQR_MMRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetRQR_SBKRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetRQR_SBKRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x2) >> 1
}

// LPUART.ISR: Interrupt and status register
func (o *LPUART_Type) SetISR_TXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *LPUART_Type) GetISR_TXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *LPUART_Type) SetISR_RXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *LPUART_Type) GetISR_RXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *LPUART_Type) SetISR_RXFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *LPUART_Type) GetISR_RXFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *LPUART_Type) SetISR_TXFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *LPUART_Type) GetISR_TXFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *LPUART_Type) SetISR_REACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *LPUART_Type) GetISR_REACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *LPUART_Type) SetISR_TEACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *LPUART_Type) GetISR_TEACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *LPUART_Type) SetISR_RWU(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *LPUART_Type) GetISR_RWU() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *LPUART_Type) SetISR_SBKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *LPUART_Type) GetISR_SBKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *LPUART_Type) SetISR_CMF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *LPUART_Type) GetISR_CMF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *LPUART_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *LPUART_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *LPUART_Type) SetISR_CTS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *LPUART_Type) GetISR_CTS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *LPUART_Type) SetISR_CTSIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetISR_CTSIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetISR_TXFNF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *LPUART_Type) GetISR_TXFNF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *LPUART_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetISR_RXFNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *LPUART_Type) GetISR_RXFNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *LPUART_Type) SetISR_IDLE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetISR_IDLE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetISR_ORE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetISR_ORE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetISR_NE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetISR_NE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetISR_FE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetISR_FE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *LPUART_Type) SetISR_PE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetISR_PE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// LPUART.ICR: Interrupt flag clear register
func (o *LPUART_Type) SetICR_CMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20000)|value<<17)
}
func (o *LPUART_Type) GetICR_CMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20000) >> 17
}
func (o *LPUART_Type) SetICR_CTSCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *LPUART_Type) GetICR_CTSCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *LPUART_Type) SetICR_TCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *LPUART_Type) GetICR_TCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *LPUART_Type) SetICR_IDLECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *LPUART_Type) GetICR_IDLECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *LPUART_Type) SetICR_ORECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *LPUART_Type) GetICR_ORECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *LPUART_Type) SetICR_NECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *LPUART_Type) GetICR_NECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *LPUART_Type) SetICR_FECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *LPUART_Type) GetICR_FECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *LPUART_Type) SetICR_PECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *LPUART_Type) GetICR_PECF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}

// LPUART.RDR: Receive data register
func (o *LPUART_Type) SetRDR(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0x1ff)|value)
}
func (o *LPUART_Type) GetRDR() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg) & 0x1ff
}

// LPUART.TDR: Transmit data register
func (o *LPUART_Type) SetTDR(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0x1ff)|value)
}
func (o *LPUART_Type) GetTDR() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg) & 0x1ff
}

// LPUART.PRESC: prescaler register
func (o *LPUART_Type) SetPRESC_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.PRESC.Reg, volatile.LoadUint32(&o.PRESC.Reg)&^(0xf)|value)
}
func (o *LPUART_Type) GetPRESC_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.PRESC.Reg) & 0xf
}

// LPUART.AUTOCR: Autonomous mode control register
func (o *LPUART_Type) SetAUTOCR_TDN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0xffff)|value)
}
func (o *LPUART_Type) GetAUTOCR_TDN() uint32 {
	return volatile.LoadUint32(&o.AUTOCR.Reg) & 0xffff
}
func (o *LPUART_Type) SetAUTOCR_TRIGPOL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x10000)|value<<16)
}
func (o *LPUART_Type) GetAUTOCR_TRIGPOL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x10000) >> 16
}
func (o *LPUART_Type) SetAUTOCR_TRIGEN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x20000)|value<<17)
}
func (o *LPUART_Type) GetAUTOCR_TRIGEN() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x20000) >> 17
}
func (o *LPUART_Type) SetAUTOCR_IDLEDIS(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x40000)|value<<18)
}
func (o *LPUART_Type) GetAUTOCR_IDLEDIS() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x40000) >> 18
}
func (o *LPUART_Type) SetAUTOCR_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x780000)|value<<19)
}
func (o *LPUART_Type) GetAUTOCR_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x780000) >> 19
}

// Multi-function digital filter
type MDF_Type struct {
	GCR   volatile.Register32 // 0x0
	CKGCR volatile.Register32 // 0x4
	_     [120]byte
	FLT   [6]MDF_FLT_Type // 0x80
}

// MDF.GCR: MDF global control register
func (o *MDF_Type) SetGCR_TRGO(value uint32) {
	volatile.StoreUint32(&o.GCR.Reg, volatile.LoadUint32(&o.GCR.Reg)&^(0x1)|value)
}
func (o *MDF_Type) GetGCR_TRGO() uint32 {
	return volatile.LoadUint32(&o.GCR.Reg) & 0x1
}
func (o *MDF_Type) SetGCR_ILVNB(value uint32) {
	volatile.StoreUint32(&o.GCR.Reg, volatile.LoadUint32(&o.GCR.Reg)&^(0xf0)|value<<4)
}
func (o *MDF_Type) GetGCR_ILVNB() uint32 {
	return (volatile.LoadUint32(&o.GCR.Reg) & 0xf0) >> 4
}

// MDF.CKGCR: MDF clock generator control register
func (o *MDF_Type) SetCKGCR_CKGDEN(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x1)|value)
}
func (o *MDF_Type) GetCKGCR_CKGDEN() uint32 {
	return volatile.LoadUint32(&o.CKGCR.Reg) & 0x1
}
func (o *MDF_Type) SetCKGCR_CCK0EN(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x2)|value<<1)
}
func (o *MDF_Type) GetCKGCR_CCK0EN() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x2) >> 1
}
func (o *MDF_Type) SetCKGCR_CCK1EN(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x4)|value<<2)
}
func (o *MDF_Type) GetCKGCR_CCK1EN() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x4) >> 2
}
func (o *MDF_Type) SetCKGCR_CKGMOD(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x10)|value<<4)
}
func (o *MDF_Type) GetCKGCR_CKGMOD() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x10) >> 4
}
func (o *MDF_Type) SetCKGCR_CCK0DIR(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x20)|value<<5)
}
func (o *MDF_Type) GetCKGCR_CCK0DIR() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x20) >> 5
}
func (o *MDF_Type) SetCKGCR_CCK1DIR(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x40)|value<<6)
}
func (o *MDF_Type) GetCKGCR_CCK1DIR() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x40) >> 6
}
func (o *MDF_Type) SetCKGCR_TRGSENS(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x100)|value<<8)
}
func (o *MDF_Type) GetCKGCR_TRGSENS() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x100) >> 8
}
func (o *MDF_Type) SetCKGCR_TRGSRC(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0xf000)|value<<12)
}
func (o *MDF_Type) GetCKGCR_TRGSRC() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0xf000) >> 12
}
func (o *MDF_Type) SetCKGCR_CCKDIV(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0xf0000)|value<<16)
}
func (o *MDF_Type) GetCKGCR_CCKDIV() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0xf0000) >> 16
}
func (o *MDF_Type) SetCKGCR_PROCDIV(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x7f000000)|value<<24)
}
func (o *MDF_Type) GetCKGCR_PROCDIV() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x7f000000) >> 24
}
func (o *MDF_Type) SetCKGCR_CKGACTIVE(value uint32) {
	volatile.StoreUint32(&o.CKGCR.Reg, volatile.LoadUint32(&o.CKGCR.Reg)&^(0x80000000)|value<<31)
}
func (o *MDF_Type) GetCKGCR_CKGACTIVE() uint32 {
	return (volatile.LoadUint32(&o.CKGCR.Reg) & 0x80000000) >> 31
}

// Cluster FLT%s, containing SITF?CR, BSMX?CR, DFLT?CR, DFLT?CICR, DFLT?RSFR, DFLT?INTR, OLD?CR, OLD?THLR, OLD?THHR, DLY?CR, SCD?CR, DFLT?IER, DFLT?ISR, OEC?CR, SNPS?DR, DFLT?DR
type MDF_FLT_Type struct {
	SITFCR   volatile.Register32 // 0x80
	BSMXCR   volatile.Register32 // 0x84
	DFLTCR   volatile.Register32 // 0x88
	DFLTCICR volatile.Register32 // 0x8C
	DFLTRSFR volatile.Register32 // 0x90
	DFLTINTR volatile.Register32 // 0x94
	OLDCR    volatile.Register32 // 0x98
	OLDTHLR  volatile.Register32 // 0x9C
	OLDTHHR  volatile.Register32 // 0xA0
	DLYCR    volatile.Register32 // 0xA4
	SCDCR    volatile.Register32 // 0xA8
	DFLTIER  volatile.Register32 // 0xAC
	DFLTISR  volatile.Register32 // 0xB0
	OECCR    volatile.Register32 // 0xB4
	_        [52]byte
	SNPSDR   volatile.Register32 // 0xEC
	DFLTDR   volatile.Register32 // 0xF0
	_        [12]byte
}

// MDF_FLT.SITFCR: This register is used to control the serial interfaces (SITFx).
func (o *MDF_FLT_Type) SetSITFCR_SITFEN(value uint32) {
	volatile.StoreUint32(&o.SITFCR.Reg, volatile.LoadUint32(&o.SITFCR.Reg)&^(0x1)|value)
}
func (o *MDF_FLT_Type) GetSITFCR_SITFEN() uint32 {
	return volatile.LoadUint32(&o.SITFCR.Reg) & 0x1
}
func (o *MDF_FLT_Type) SetSITFCR_SCKSRC(value uint32) {
	volatile.StoreUint32(&o.SITFCR.Reg, volatile.LoadUint32(&o.SITFCR.Reg)&^(0x6)|value<<1)
}
func (o *MDF_FLT_Type) GetSITFCR_SCKSRC() uint32 {
	return (volatile.LoadUint32(&o.SITFCR.Reg) & 0x6) >> 1
}
func (o *MDF_FLT_Type) SetSITFCR_SITFMOD(value uint32) {
	volatile.StoreUint32(&o.SITFCR.Reg, volatile.LoadUint32(&o.SITFCR.Reg)&^(0x30)|value<<4)
}
func (o *MDF_FLT_Type) GetSITFCR_SITFMOD() uint32 {
	return (volatile.LoadUint32(&o.SITFCR.Reg) & 0x30) >> 4
}
func (o *MDF_FLT_Type) SetSITFCR_STH(value uint32) {
	volatile.StoreUint32(&o.SITFCR.Reg, volatile.LoadUint32(&o.SITFCR.Reg)&^(0x1f00)|value<<8)
}
func (o *MDF_FLT_Type) GetSITFCR_STH() uint32 {
	return (volatile.LoadUint32(&o.SITFCR.Reg) & 0x1f00) >> 8
}
func (o *MDF_FLT_Type) SetSITFCR_SITFACTIVE(value uint32) {
	volatile.StoreUint32(&o.SITFCR.Reg, volatile.LoadUint32(&o.SITFCR.Reg)&^(0x80000000)|value<<31)
}
func (o *MDF_FLT_Type) GetSITFCR_SITFACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SITFCR.Reg) & 0x80000000) >> 31
}

// MDF_FLT.BSMXCR: This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.
func (o *MDF_FLT_Type) SetBSMXCR_BSSEL(value uint32) {
	volatile.StoreUint32(&o.BSMXCR.Reg, volatile.LoadUint32(&o.BSMXCR.Reg)&^(0x1f)|value)
}
func (o *MDF_FLT_Type) GetBSMXCR_BSSEL() uint32 {
	return volatile.LoadUint32(&o.BSMXCR.Reg) & 0x1f
}
func (o *MDF_FLT_Type) SetBSMXCR_BSMXACTIVE(value uint32) {
	volatile.StoreUint32(&o.BSMXCR.Reg, volatile.LoadUint32(&o.BSMXCR.Reg)&^(0x80000000)|value<<31)
}
func (o *MDF_FLT_Type) GetBSMXCR_BSMXACTIVE() uint32 {
	return (volatile.LoadUint32(&o.BSMXCR.Reg) & 0x80000000) >> 31
}

// MDF_FLT.DFLTCR: This register is used to control the digital filter x.
func (o *MDF_FLT_Type) SetDFLTCR_DFLTEN(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x1)|value)
}
func (o *MDF_FLT_Type) GetDFLTCR_DFLTEN() uint32 {
	return volatile.LoadUint32(&o.DFLTCR.Reg) & 0x1
}
func (o *MDF_FLT_Type) SetDFLTCR_DMAEN(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x2)|value<<1)
}
func (o *MDF_FLT_Type) GetDFLTCR_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0x2) >> 1
}
func (o *MDF_FLT_Type) SetDFLTCR_FTH(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x4)|value<<2)
}
func (o *MDF_FLT_Type) GetDFLTCR_FTH() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0x4) >> 2
}
func (o *MDF_FLT_Type) SetDFLTCR_ACQMOD(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x70)|value<<4)
}
func (o *MDF_FLT_Type) GetDFLTCR_ACQMOD() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0x70) >> 4
}
func (o *MDF_FLT_Type) SetDFLTCR_TRGSENS(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x100)|value<<8)
}
func (o *MDF_FLT_Type) GetDFLTCR_TRGSENS() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0x100) >> 8
}
func (o *MDF_FLT_Type) SetDFLTCR_TRGSRC(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0xf000)|value<<12)
}
func (o *MDF_FLT_Type) GetDFLTCR_TRGSRC() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0xf000) >> 12
}
func (o *MDF_FLT_Type) SetDFLTCR_SNPSFMT(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x10000)|value<<16)
}
func (o *MDF_FLT_Type) GetDFLTCR_SNPSFMT() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0x10000) >> 16
}
func (o *MDF_FLT_Type) SetDFLTCR_NBDIS(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0xff00000)|value<<20)
}
func (o *MDF_FLT_Type) GetDFLTCR_NBDIS() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0xff00000) >> 20
}
func (o *MDF_FLT_Type) SetDFLTCR_DFLTRUN(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x40000000)|value<<30)
}
func (o *MDF_FLT_Type) GetDFLTCR_DFLTRUN() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0x40000000) >> 30
}
func (o *MDF_FLT_Type) SetDFLTCR_DFLTACTIVE(value uint32) {
	volatile.StoreUint32(&o.DFLTCR.Reg, volatile.LoadUint32(&o.DFLTCR.Reg)&^(0x80000000)|value<<31)
}
func (o *MDF_FLT_Type) GetDFLTCR_DFLTACTIVE() uint32 {
	return (volatile.LoadUint32(&o.DFLTCR.Reg) & 0x80000000) >> 31
}

// MDF_FLT.DFLTCICR: This register is used to control the main CIC filter.
func (o *MDF_FLT_Type) SetDFLTCICR_DATSRC(value uint32) {
	volatile.StoreUint32(&o.DFLTCICR.Reg, volatile.LoadUint32(&o.DFLTCICR.Reg)&^(0x3)|value)
}
func (o *MDF_FLT_Type) GetDFLTCICR_DATSRC() uint32 {
	return volatile.LoadUint32(&o.DFLTCICR.Reg) & 0x3
}
func (o *MDF_FLT_Type) SetDFLTCICR_CICMOD(value uint32) {
	volatile.StoreUint32(&o.DFLTCICR.Reg, volatile.LoadUint32(&o.DFLTCICR.Reg)&^(0x70)|value<<4)
}
func (o *MDF_FLT_Type) GetDFLTCICR_CICMOD() uint32 {
	return (volatile.LoadUint32(&o.DFLTCICR.Reg) & 0x70) >> 4
}
func (o *MDF_FLT_Type) SetDFLTCICR_MCICD(value uint32) {
	volatile.StoreUint32(&o.DFLTCICR.Reg, volatile.LoadUint32(&o.DFLTCICR.Reg)&^(0x1ff00)|value<<8)
}
func (o *MDF_FLT_Type) GetDFLTCICR_MCICD() uint32 {
	return (volatile.LoadUint32(&o.DFLTCICR.Reg) & 0x1ff00) >> 8
}
func (o *MDF_FLT_Type) SetDFLTCICR_SCALE(value uint32) {
	volatile.StoreUint32(&o.DFLTCICR.Reg, volatile.LoadUint32(&o.DFLTCICR.Reg)&^(0x3f00000)|value<<20)
}
func (o *MDF_FLT_Type) GetDFLTCICR_SCALE() uint32 {
	return (volatile.LoadUint32(&o.DFLTCICR.Reg) & 0x3f00000) >> 20
}

// MDF_FLT.DFLTRSFR: This register is used to control the reshape and HPF filters.
func (o *MDF_FLT_Type) SetDFLTRSFR_RSFLTBYP(value uint32) {
	volatile.StoreUint32(&o.DFLTRSFR.Reg, volatile.LoadUint32(&o.DFLTRSFR.Reg)&^(0x1)|value)
}
func (o *MDF_FLT_Type) GetDFLTRSFR_RSFLTBYP() uint32 {
	return volatile.LoadUint32(&o.DFLTRSFR.Reg) & 0x1
}
func (o *MDF_FLT_Type) SetDFLTRSFR_RSFLTD(value uint32) {
	volatile.StoreUint32(&o.DFLTRSFR.Reg, volatile.LoadUint32(&o.DFLTRSFR.Reg)&^(0x10)|value<<4)
}
func (o *MDF_FLT_Type) GetDFLTRSFR_RSFLTD() uint32 {
	return (volatile.LoadUint32(&o.DFLTRSFR.Reg) & 0x10) >> 4
}
func (o *MDF_FLT_Type) SetDFLTRSFR_HPFBYP(value uint32) {
	volatile.StoreUint32(&o.DFLTRSFR.Reg, volatile.LoadUint32(&o.DFLTRSFR.Reg)&^(0x80)|value<<7)
}
func (o *MDF_FLT_Type) GetDFLTRSFR_HPFBYP() uint32 {
	return (volatile.LoadUint32(&o.DFLTRSFR.Reg) & 0x80) >> 7
}
func (o *MDF_FLT_Type) SetDFLTRSFR_HPFC(value uint32) {
	volatile.StoreUint32(&o.DFLTRSFR.Reg, volatile.LoadUint32(&o.DFLTRSFR.Reg)&^(0x300)|value<<8)
}
func (o *MDF_FLT_Type) GetDFLTRSFR_HPFC() uint32 {
	return (volatile.LoadUint32(&o.DFLTRSFR.Reg) & 0x300) >> 8
}

// MDF_FLT.DFLTINTR: This register is used to the integrator (INT) settings.
func (o *MDF_FLT_Type) SetDFLTINTR_INTDIV(value uint32) {
	volatile.StoreUint32(&o.DFLTINTR.Reg, volatile.LoadUint32(&o.DFLTINTR.Reg)&^(0x3)|value)
}
func (o *MDF_FLT_Type) GetDFLTINTR_INTDIV() uint32 {
	return volatile.LoadUint32(&o.DFLTINTR.Reg) & 0x3
}
func (o *MDF_FLT_Type) SetDFLTINTR_INTVAL(value uint32) {
	volatile.StoreUint32(&o.DFLTINTR.Reg, volatile.LoadUint32(&o.DFLTINTR.Reg)&^(0x7f0)|value<<4)
}
func (o *MDF_FLT_Type) GetDFLTINTR_INTVAL() uint32 {
	return (volatile.LoadUint32(&o.DFLTINTR.Reg) & 0x7f0) >> 4
}

// MDF_FLT.OLDCR: This register is used to configure the Out-of Limit Detector function.
func (o *MDF_FLT_Type) SetOLDCR_OLDEN(value uint32) {
	volatile.StoreUint32(&o.OLDCR.Reg, volatile.LoadUint32(&o.OLDCR.Reg)&^(0x1)|value)
}
func (o *MDF_FLT_Type) GetOLDCR_OLDEN() uint32 {
	return volatile.LoadUint32(&o.OLDCR.Reg) & 0x1
}
func (o *MDF_FLT_Type) SetOLDCR_THINB(value uint32) {
	volatile.StoreUint32(&o.OLDCR.Reg, volatile.LoadUint32(&o.OLDCR.Reg)&^(0x2)|value<<1)
}
func (o *MDF_FLT_Type) GetOLDCR_THINB() uint32 {
	return (volatile.LoadUint32(&o.OLDCR.Reg) & 0x2) >> 1
}
func (o *MDF_FLT_Type) SetOLDCR_BKOLD(value uint32) {
	volatile.StoreUint32(&o.OLDCR.Reg, volatile.LoadUint32(&o.OLDCR.Reg)&^(0xf0)|value<<4)
}
func (o *MDF_FLT_Type) GetOLDCR_BKOLD() uint32 {
	return (volatile.LoadUint32(&o.OLDCR.Reg) & 0xf0) >> 4
}
func (o *MDF_FLT_Type) SetOLDCR_ACICN(value uint32) {
	volatile.StoreUint32(&o.OLDCR.Reg, volatile.LoadUint32(&o.OLDCR.Reg)&^(0x3000)|value<<12)
}
func (o *MDF_FLT_Type) GetOLDCR_ACICN() uint32 {
	return (volatile.LoadUint32(&o.OLDCR.Reg) & 0x3000) >> 12
}
func (o *MDF_FLT_Type) SetOLDCR_ACICD(value uint32) {
	volatile.StoreUint32(&o.OLDCR.Reg, volatile.LoadUint32(&o.OLDCR.Reg)&^(0x3e0000)|value<<17)
}
func (o *MDF_FLT_Type) GetOLDCR_ACICD() uint32 {
	return (volatile.LoadUint32(&o.OLDCR.Reg) & 0x3e0000) >> 17
}
func (o *MDF_FLT_Type) SetOLDCR_OLDACTIVE(value uint32) {
	volatile.StoreUint32(&o.OLDCR.Reg, volatile.LoadUint32(&o.OLDCR.Reg)&^(0x80000000)|value<<31)
}
func (o *MDF_FLT_Type) GetOLDCR_OLDACTIVE() uint32 {
	return (volatile.LoadUint32(&o.OLDCR.Reg) & 0x80000000) >> 31
}

// MDF_FLT.OLDTHLR: This register is used for the adjustment of the Out-off Limit low threshold.
func (o *MDF_FLT_Type) SetOLDTHLR_OLDTHL(value uint32) {
	volatile.StoreUint32(&o.OLDTHLR.Reg, volatile.LoadUint32(&o.OLDTHLR.Reg)&^(0x3ffffff)|value)
}
func (o *MDF_FLT_Type) GetOLDTHLR_OLDTHL() uint32 {
	return volatile.LoadUint32(&o.OLDTHLR.Reg) & 0x3ffffff
}

// MDF_FLT.OLDTHHR: This register is used for the adjustment of the Out-off Limit high threshold.
func (o *MDF_FLT_Type) SetOLDTHHR_OLDTHH(value uint32) {
	volatile.StoreUint32(&o.OLDTHHR.Reg, volatile.LoadUint32(&o.OLDTHHR.Reg)&^(0x3ffffff)|value)
}
func (o *MDF_FLT_Type) GetOLDTHHR_OLDTHH() uint32 {
	return volatile.LoadUint32(&o.OLDTHHR.Reg) & 0x3ffffff
}

// MDF_FLT.DLYCR: This register is used for the adjustment stream delays.
func (o *MDF_FLT_Type) SetDLYCR_SKPDLY(value uint32) {
	volatile.StoreUint32(&o.DLYCR.Reg, volatile.LoadUint32(&o.DLYCR.Reg)&^(0x7f)|value)
}
func (o *MDF_FLT_Type) GetDLYCR_SKPDLY() uint32 {
	return volatile.LoadUint32(&o.DLYCR.Reg) & 0x7f
}
func (o *MDF_FLT_Type) SetDLYCR_SKPBF(value uint32) {
	volatile.StoreUint32(&o.DLYCR.Reg, volatile.LoadUint32(&o.DLYCR.Reg)&^(0x80000000)|value<<31)
}
func (o *MDF_FLT_Type) GetDLYCR_SKPBF() uint32 {
	return (volatile.LoadUint32(&o.DLYCR.Reg) & 0x80000000) >> 31
}

// MDF_FLT.SCDCR: This register is used for the adjustment stream delays.
func (o *MDF_FLT_Type) SetSCDCR_SCDEN(value uint32) {
	volatile.StoreUint32(&o.SCDCR.Reg, volatile.LoadUint32(&o.SCDCR.Reg)&^(0x1)|value)
}
func (o *MDF_FLT_Type) GetSCDCR_SCDEN() uint32 {
	return volatile.LoadUint32(&o.SCDCR.Reg) & 0x1
}
func (o *MDF_FLT_Type) SetSCDCR_BKSCD(value uint32) {
	volatile.StoreUint32(&o.SCDCR.Reg, volatile.LoadUint32(&o.SCDCR.Reg)&^(0xf0)|value<<4)
}
func (o *MDF_FLT_Type) GetSCDCR_BKSCD() uint32 {
	return (volatile.LoadUint32(&o.SCDCR.Reg) & 0xf0) >> 4
}
func (o *MDF_FLT_Type) SetSCDCR_SCDT(value uint32) {
	volatile.StoreUint32(&o.SCDCR.Reg, volatile.LoadUint32(&o.SCDCR.Reg)&^(0xff000)|value<<12)
}
func (o *MDF_FLT_Type) GetSCDCR_SCDT() uint32 {
	return (volatile.LoadUint32(&o.SCDCR.Reg) & 0xff000) >> 12
}
func (o *MDF_FLT_Type) SetSCDCR_SCDACTIVE(value uint32) {
	volatile.StoreUint32(&o.SCDCR.Reg, volatile.LoadUint32(&o.SCDCR.Reg)&^(0x80000000)|value<<31)
}
func (o *MDF_FLT_Type) GetSCDCR_SCDACTIVE() uint32 {
	return (volatile.LoadUint32(&o.SCDCR.Reg) & 0x80000000) >> 31
}

// MDF_FLT.DFLTIER: This register is used for allowing or not the events to generate an interrupt.
func (o *MDF_FLT_Type) SetDFLTIER_FTHIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x1)|value)
}
func (o *MDF_FLT_Type) GetDFLTIER_FTHIE() uint32 {
	return volatile.LoadUint32(&o.DFLTIER.Reg) & 0x1
}
func (o *MDF_FLT_Type) SetDFLTIER_DOVRIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x2)|value<<1)
}
func (o *MDF_FLT_Type) GetDFLTIER_DOVRIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x2) >> 1
}
func (o *MDF_FLT_Type) SetDFLTIER_SSDRIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x4)|value<<2)
}
func (o *MDF_FLT_Type) GetDFLTIER_SSDRIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x4) >> 2
}
func (o *MDF_FLT_Type) SetDFLTIER_OLDIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x10)|value<<4)
}
func (o *MDF_FLT_Type) GetDFLTIER_OLDIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x10) >> 4
}
func (o *MDF_FLT_Type) SetDFLTIER_SSOVRIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x80)|value<<7)
}
func (o *MDF_FLT_Type) GetDFLTIER_SSOVRIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x80) >> 7
}
func (o *MDF_FLT_Type) SetDFLTIER_SCDIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x100)|value<<8)
}
func (o *MDF_FLT_Type) GetDFLTIER_SCDIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x100) >> 8
}
func (o *MDF_FLT_Type) SetDFLTIER_SATIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x200)|value<<9)
}
func (o *MDF_FLT_Type) GetDFLTIER_SATIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x200) >> 9
}
func (o *MDF_FLT_Type) SetDFLTIER_CKABIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x400)|value<<10)
}
func (o *MDF_FLT_Type) GetDFLTIER_CKABIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x400) >> 10
}
func (o *MDF_FLT_Type) SetDFLTIER_RFOVRIE(value uint32) {
	volatile.StoreUint32(&o.DFLTIER.Reg, volatile.LoadUint32(&o.DFLTIER.Reg)&^(0x800)|value<<11)
}
func (o *MDF_FLT_Type) GetDFLTIER_RFOVRIE() uint32 {
	return (volatile.LoadUint32(&o.DFLTIER.Reg) & 0x800) >> 11
}

// MDF_FLT.DFLTISR: MDF DFLT0 interrupt status register 0
func (o *MDF_FLT_Type) SetDFLTISR_FTHF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x1)|value)
}
func (o *MDF_FLT_Type) GetDFLTISR_FTHF() uint32 {
	return volatile.LoadUint32(&o.DFLTISR.Reg) & 0x1
}
func (o *MDF_FLT_Type) SetDFLTISR_DOVRF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x2)|value<<1)
}
func (o *MDF_FLT_Type) GetDFLTISR_DOVRF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x2) >> 1
}
func (o *MDF_FLT_Type) SetDFLTISR_SSDRF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x4)|value<<2)
}
func (o *MDF_FLT_Type) GetDFLTISR_SSDRF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x4) >> 2
}
func (o *MDF_FLT_Type) SetDFLTISR_RXNEF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x8)|value<<3)
}
func (o *MDF_FLT_Type) GetDFLTISR_RXNEF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x8) >> 3
}
func (o *MDF_FLT_Type) SetDFLTISR_OLDF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x10)|value<<4)
}
func (o *MDF_FLT_Type) GetDFLTISR_OLDF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x10) >> 4
}
func (o *MDF_FLT_Type) SetDFLTISR_THLF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x20)|value<<5)
}
func (o *MDF_FLT_Type) GetDFLTISR_THLF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x20) >> 5
}
func (o *MDF_FLT_Type) SetDFLTISR_THHF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x40)|value<<6)
}
func (o *MDF_FLT_Type) GetDFLTISR_THHF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x40) >> 6
}
func (o *MDF_FLT_Type) SetDFLTISR_SSOVRF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x80)|value<<7)
}
func (o *MDF_FLT_Type) GetDFLTISR_SSOVRF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x80) >> 7
}
func (o *MDF_FLT_Type) SetDFLTISR_SCDF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x100)|value<<8)
}
func (o *MDF_FLT_Type) GetDFLTISR_SCDF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x100) >> 8
}
func (o *MDF_FLT_Type) SetDFLTISR_SATF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x200)|value<<9)
}
func (o *MDF_FLT_Type) GetDFLTISR_SATF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x200) >> 9
}
func (o *MDF_FLT_Type) SetDFLTISR_CKABF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x400)|value<<10)
}
func (o *MDF_FLT_Type) GetDFLTISR_CKABF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x400) >> 10
}
func (o *MDF_FLT_Type) SetDFLTISR_RFOVRF(value uint32) {
	volatile.StoreUint32(&o.DFLTISR.Reg, volatile.LoadUint32(&o.DFLTISR.Reg)&^(0x800)|value<<11)
}
func (o *MDF_FLT_Type) GetDFLTISR_RFOVRF() uint32 {
	return (volatile.LoadUint32(&o.DFLTISR.Reg) & 0x800) >> 11
}

// MDF_FLT.OECCR: This register contains the offset compensation value.
func (o *MDF_FLT_Type) SetOECCR_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OECCR.Reg, volatile.LoadUint32(&o.OECCR.Reg)&^(0x3ffffff)|value)
}
func (o *MDF_FLT_Type) GetOECCR_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OECCR.Reg) & 0x3ffffff
}

// MDF_FLT.SNPSDR: This register is used to read the data processed by each digital filter in snapshot mode.
func (o *MDF_FLT_Type) SetSNPSDR_MCICDC(value uint32) {
	volatile.StoreUint32(&o.SNPSDR.Reg, volatile.LoadUint32(&o.SNPSDR.Reg)&^(0x1ff)|value)
}
func (o *MDF_FLT_Type) GetSNPSDR_MCICDC() uint32 {
	return volatile.LoadUint32(&o.SNPSDR.Reg) & 0x1ff
}
func (o *MDF_FLT_Type) SetSNPSDR_EXTSDR(value uint32) {
	volatile.StoreUint32(&o.SNPSDR.Reg, volatile.LoadUint32(&o.SNPSDR.Reg)&^(0xfe00)|value<<9)
}
func (o *MDF_FLT_Type) GetSNPSDR_EXTSDR() uint32 {
	return (volatile.LoadUint32(&o.SNPSDR.Reg) & 0xfe00) >> 9
}
func (o *MDF_FLT_Type) SetSNPSDR_SDR(value uint32) {
	volatile.StoreUint32(&o.SNPSDR.Reg, volatile.LoadUint32(&o.SNPSDR.Reg)&^(0xffff0000)|value<<16)
}
func (o *MDF_FLT_Type) GetSNPSDR_SDR() uint32 {
	return (volatile.LoadUint32(&o.SNPSDR.Reg) & 0xffff0000) >> 16
}

// MDF_FLT.DFLTDR: This register is used to read the data processed by each digital filter.
func (o *MDF_FLT_Type) SetDFLTDR_DR(value uint32) {
	volatile.StoreUint32(&o.DFLTDR.Reg, volatile.LoadUint32(&o.DFLTDR.Reg)&^(0xffffff00)|value<<8)
}
func (o *MDF_FLT_Type) GetDFLTDR_DR() uint32 {
	return (volatile.LoadUint32(&o.DFLTDR.Reg) & 0xffffff00) >> 8
}

// OctoSPI
type OctoSPI_Type struct {
	CR    volatile.Register32 // 0x0
	_     [4]byte
	DCR1  volatile.Register32 // 0x8
	DCR2  volatile.Register32 // 0xC
	DCR3  volatile.Register32 // 0x10
	DCR4  volatile.Register32 // 0x14
	_     [8]byte
	SR    volatile.Register32 // 0x20
	FCR   volatile.Register32 // 0x24
	_     [24]byte
	DLR   volatile.Register32 // 0x40
	_     [4]byte
	AR    volatile.Register32 // 0x48
	_     [4]byte
	DR    volatile.Register32 // 0x50
	_     [44]byte
	PSMKR volatile.Register32 // 0x80
	_     [4]byte
	PSMAR volatile.Register32 // 0x88
	_     [4]byte
	PIR   volatile.Register32 // 0x90
	_     [108]byte
	CCR   volatile.Register32 // 0x100
	_     [4]byte
	TCR   volatile.Register32 // 0x108
	_     [4]byte
	IR    volatile.Register32 // 0x110
	_     [12]byte
	ABR   volatile.Register32 // 0x120
	_     [12]byte
	LPTR  volatile.Register32 // 0x130
	_     [12]byte
	WPCCR volatile.Register32 // 0x140
	_     [4]byte
	WPTCR volatile.Register32 // 0x148
	_     [4]byte
	WPIR  volatile.Register32 // 0x150
	_     [12]byte
	WPABR volatile.Register32 // 0x160
	_     [28]byte
	WCCR  volatile.Register32 // 0x180
	_     [4]byte
	WTCR  volatile.Register32 // 0x188
	_     [4]byte
	WIR   volatile.Register32 // 0x190
	_     [12]byte
	WABR  volatile.Register32 // 0x1A0
	_     [92]byte
	HLCR  volatile.Register32 // 0x200
}

// OctoSPI.CR: control register
func (o *OctoSPI_Type) SetCR_FMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x30000000)|value<<28)
}
func (o *OctoSPI_Type) GetCR_FMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x30000000) >> 28
}
func (o *OctoSPI_Type) SetCR_PMM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800000)|value<<23)
}
func (o *OctoSPI_Type) GetCR_PMM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800000) >> 23
}
func (o *OctoSPI_Type) SetCR_APMS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400000)|value<<22)
}
func (o *OctoSPI_Type) GetCR_APMS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400000) >> 22
}
func (o *OctoSPI_Type) SetCR_TEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *OctoSPI_Type) GetCR_TEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *OctoSPI_Type) SetCR_TOIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *OctoSPI_Type) GetCR_TOIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *OctoSPI_Type) SetCR_SMIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetCR_SMIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetCR_FTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *OctoSPI_Type) GetCR_FTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *OctoSPI_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *OctoSPI_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *OctoSPI_Type) SetCR_FTHRES(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1f00)|value<<8)
}
func (o *OctoSPI_Type) GetCR_FTHRES() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1f00) >> 8
}
func (o *OctoSPI_Type) SetCR_MSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *OctoSPI_Type) GetCR_MSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *OctoSPI_Type) SetCR_DMM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *OctoSPI_Type) GetCR_DMM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *OctoSPI_Type) SetCR_TCEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetCR_TCEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetCR_DMAEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *OctoSPI_Type) GetCR_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *OctoSPI_Type) SetCR_ABORT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetCR_ABORT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// OctoSPI.DCR1: device configuration register 1
func (o *OctoSPI_Type) SetDCR1_CKMODE(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetDCR1_CKMODE() uint32 {
	return volatile.LoadUint32(&o.DCR1.Reg) & 0x1
}
func (o *OctoSPI_Type) SetDCR1_FRCK(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetDCR1_FRCK() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetDCR1_DLYBYP(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetDCR1_DLYBYP() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetDCR1_CSHT(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x3f00)|value<<8)
}
func (o *OctoSPI_Type) GetDCR1_CSHT() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x3f00) >> 8
}
func (o *OctoSPI_Type) SetDCR1_DEVSIZE(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *OctoSPI_Type) GetDCR1_DEVSIZE() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x1f0000) >> 16
}
func (o *OctoSPI_Type) SetDCR1_MTYP(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetDCR1_MTYP() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x7000000) >> 24
}

// OctoSPI.DCR2: device configuration register 2
func (o *OctoSPI_Type) SetDCR2_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.DCR2.Reg, volatile.LoadUint32(&o.DCR2.Reg)&^(0xff)|value)
}
func (o *OctoSPI_Type) GetDCR2_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.DCR2.Reg) & 0xff
}
func (o *OctoSPI_Type) SetDCR2_WRAPSIZE(value uint32) {
	volatile.StoreUint32(&o.DCR2.Reg, volatile.LoadUint32(&o.DCR2.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetDCR2_WRAPSIZE() uint32 {
	return (volatile.LoadUint32(&o.DCR2.Reg) & 0x70000) >> 16
}

// OctoSPI.DCR3: device configuration register 3
func (o *OctoSPI_Type) SetDCR3_MAXTRAN(value uint32) {
	volatile.StoreUint32(&o.DCR3.Reg, volatile.LoadUint32(&o.DCR3.Reg)&^(0xff)|value)
}
func (o *OctoSPI_Type) GetDCR3_MAXTRAN() uint32 {
	return volatile.LoadUint32(&o.DCR3.Reg) & 0xff
}
func (o *OctoSPI_Type) SetDCR3_CSBOUND(value uint32) {
	volatile.StoreUint32(&o.DCR3.Reg, volatile.LoadUint32(&o.DCR3.Reg)&^(0x1f0000)|value<<16)
}
func (o *OctoSPI_Type) GetDCR3_CSBOUND() uint32 {
	return (volatile.LoadUint32(&o.DCR3.Reg) & 0x1f0000) >> 16
}

// OctoSPI.DCR4: DCR4
func (o *OctoSPI_Type) SetDCR4(value uint32) {
	volatile.StoreUint32(&o.DCR4.Reg, value)
}
func (o *OctoSPI_Type) GetDCR4() uint32 {
	return volatile.LoadUint32(&o.DCR4.Reg)
}

// OctoSPI.SR: status register
func (o *OctoSPI_Type) SetSR_TEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetSR_TEF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *OctoSPI_Type) SetSR_TCF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetSR_TCF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetSR_FTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *OctoSPI_Type) GetSR_FTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *OctoSPI_Type) SetSR_SMF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetSR_SMF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetSR_TOF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *OctoSPI_Type) GetSR_TOF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *OctoSPI_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *OctoSPI_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *OctoSPI_Type) SetSR_FLEVEL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8)
}
func (o *OctoSPI_Type) GetSR_FLEVEL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8
}

// OctoSPI.FCR: flag clear register
func (o *OctoSPI_Type) SetFCR_CTEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetFCR_CTEF() uint32 {
	return volatile.LoadUint32(&o.FCR.Reg) & 0x1
}
func (o *OctoSPI_Type) SetFCR_CTCF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetFCR_CTCF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetFCR_CSMF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetFCR_CSMF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetFCR_CTOF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x10)|value<<4)
}
func (o *OctoSPI_Type) GetFCR_CTOF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x10) >> 4
}

// OctoSPI.DLR: data length register
func (o *OctoSPI_Type) SetDLR(value uint32) {
	volatile.StoreUint32(&o.DLR.Reg, value)
}
func (o *OctoSPI_Type) GetDLR() uint32 {
	return volatile.LoadUint32(&o.DLR.Reg)
}

// OctoSPI.AR: address register
func (o *OctoSPI_Type) SetAR(value uint32) {
	volatile.StoreUint32(&o.AR.Reg, value)
}
func (o *OctoSPI_Type) GetAR() uint32 {
	return volatile.LoadUint32(&o.AR.Reg)
}

// OctoSPI.DR: data register
func (o *OctoSPI_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *OctoSPI_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// OctoSPI.PSMKR: polling status mask register
func (o *OctoSPI_Type) SetPSMKR(value uint32) {
	volatile.StoreUint32(&o.PSMKR.Reg, value)
}
func (o *OctoSPI_Type) GetPSMKR() uint32 {
	return volatile.LoadUint32(&o.PSMKR.Reg)
}

// OctoSPI.PSMAR: polling status match register
func (o *OctoSPI_Type) SetPSMAR(value uint32) {
	volatile.StoreUint32(&o.PSMAR.Reg, value)
}
func (o *OctoSPI_Type) GetPSMAR() uint32 {
	return volatile.LoadUint32(&o.PSMAR.Reg)
}

// OctoSPI.PIR: polling interval register
func (o *OctoSPI_Type) SetPIR_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.PIR.Reg, volatile.LoadUint32(&o.PIR.Reg)&^(0xffff)|value)
}
func (o *OctoSPI_Type) GetPIR_INTERVAL() uint32 {
	return volatile.LoadUint32(&o.PIR.Reg) & 0xffff
}

// OctoSPI.CCR: communication configuration register
func (o *OctoSPI_Type) SetCCR_IMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x7)|value)
}
func (o *OctoSPI_Type) GetCCR_IMODE() uint32 {
	return volatile.LoadUint32(&o.CCR.Reg) & 0x7
}
func (o *OctoSPI_Type) SetCCR_IDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetCCR_IDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetCCR_ISIZE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x30)|value<<4)
}
func (o *OctoSPI_Type) GetCCR_ISIZE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x30) >> 4
}
func (o *OctoSPI_Type) SetCCR_ADMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x700)|value<<8)
}
func (o *OctoSPI_Type) GetCCR_ADMODE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x700) >> 8
}
func (o *OctoSPI_Type) SetCCR_ADDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x800)|value<<11)
}
func (o *OctoSPI_Type) GetCCR_ADDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x800) >> 11
}
func (o *OctoSPI_Type) SetCCR_ADSIZE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x3000)|value<<12)
}
func (o *OctoSPI_Type) GetCCR_ADSIZE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x3000) >> 12
}
func (o *OctoSPI_Type) SetCCR_ABMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetCCR_ABMODE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x70000) >> 16
}
func (o *OctoSPI_Type) SetCCR_ABDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetCCR_ABDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetCCR_ABSIZE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x300000)|value<<20)
}
func (o *OctoSPI_Type) GetCCR_ABSIZE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x300000) >> 20
}
func (o *OctoSPI_Type) SetCCR_DMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetCCR_DMODE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x7000000) >> 24
}
func (o *OctoSPI_Type) SetCCR_DDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x8000000)|value<<27)
}
func (o *OctoSPI_Type) GetCCR_DDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x8000000) >> 27
}
func (o *OctoSPI_Type) SetCCR_DQSE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x20000000)|value<<29)
}
func (o *OctoSPI_Type) GetCCR_DQSE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x20000000) >> 29
}
func (o *OctoSPI_Type) SetCCR_SIOO(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x80000000)|value<<31)
}
func (o *OctoSPI_Type) GetCCR_SIOO() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x80000000) >> 31
}

// OctoSPI.TCR: timing configuration register
func (o *OctoSPI_Type) SetTCR_DCYC(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x1f)|value)
}
func (o *OctoSPI_Type) GetTCR_DCYC() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0x1f
}
func (o *OctoSPI_Type) SetTCR_DHQC(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x10000000)|value<<28)
}
func (o *OctoSPI_Type) GetTCR_DHQC() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x10000000) >> 28
}
func (o *OctoSPI_Type) SetTCR_SSHIFT(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x40000000)|value<<30)
}
func (o *OctoSPI_Type) GetTCR_SSHIFT() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x40000000) >> 30
}

// OctoSPI.IR: instruction register
func (o *OctoSPI_Type) SetIR(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, value)
}
func (o *OctoSPI_Type) GetIR() uint32 {
	return volatile.LoadUint32(&o.IR.Reg)
}

// OctoSPI.ABR: alternate bytes register
func (o *OctoSPI_Type) SetABR(value uint32) {
	volatile.StoreUint32(&o.ABR.Reg, value)
}
func (o *OctoSPI_Type) GetABR() uint32 {
	return volatile.LoadUint32(&o.ABR.Reg)
}

// OctoSPI.LPTR: low-power timeout register
func (o *OctoSPI_Type) SetLPTR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.LPTR.Reg, volatile.LoadUint32(&o.LPTR.Reg)&^(0xffff)|value)
}
func (o *OctoSPI_Type) GetLPTR_TIMEOUT() uint32 {
	return volatile.LoadUint32(&o.LPTR.Reg) & 0xffff
}

// OctoSPI.WPCCR: wrap communication configuration register
func (o *OctoSPI_Type) SetWPCCR_IMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x7)|value)
}
func (o *OctoSPI_Type) GetWPCCR_IMODE() uint32 {
	return volatile.LoadUint32(&o.WPCCR.Reg) & 0x7
}
func (o *OctoSPI_Type) SetWPCCR_IDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetWPCCR_IDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetWPCCR_ISIZE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x30)|value<<4)
}
func (o *OctoSPI_Type) GetWPCCR_ISIZE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x30) >> 4
}
func (o *OctoSPI_Type) SetWPCCR_ADMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x700)|value<<8)
}
func (o *OctoSPI_Type) GetWPCCR_ADMODE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x700) >> 8
}
func (o *OctoSPI_Type) SetWPCCR_ADDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x800)|value<<11)
}
func (o *OctoSPI_Type) GetWPCCR_ADDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x800) >> 11
}
func (o *OctoSPI_Type) SetWPCCR_ADSIZE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x3000)|value<<12)
}
func (o *OctoSPI_Type) GetWPCCR_ADSIZE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x3000) >> 12
}
func (o *OctoSPI_Type) SetWPCCR_ABMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetWPCCR_ABMODE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x70000) >> 16
}
func (o *OctoSPI_Type) SetWPCCR_ABDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetWPCCR_ABDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetWPCCR_ABSIZE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x300000)|value<<20)
}
func (o *OctoSPI_Type) GetWPCCR_ABSIZE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x300000) >> 20
}
func (o *OctoSPI_Type) SetWPCCR_DMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetWPCCR_DMODE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x7000000) >> 24
}
func (o *OctoSPI_Type) SetWPCCR_DDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x8000000)|value<<27)
}
func (o *OctoSPI_Type) GetWPCCR_DDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x8000000) >> 27
}
func (o *OctoSPI_Type) SetWPCCR_DQSE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x20000000)|value<<29)
}
func (o *OctoSPI_Type) GetWPCCR_DQSE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x20000000) >> 29
}

// OctoSPI.WPTCR: wrap timing configuration register
func (o *OctoSPI_Type) SetWPTCR_DCYC(value uint32) {
	volatile.StoreUint32(&o.WPTCR.Reg, volatile.LoadUint32(&o.WPTCR.Reg)&^(0x1f)|value)
}
func (o *OctoSPI_Type) GetWPTCR_DCYC() uint32 {
	return volatile.LoadUint32(&o.WPTCR.Reg) & 0x1f
}
func (o *OctoSPI_Type) SetWPTCR_DHQC(value uint32) {
	volatile.StoreUint32(&o.WPTCR.Reg, volatile.LoadUint32(&o.WPTCR.Reg)&^(0x10000000)|value<<28)
}
func (o *OctoSPI_Type) GetWPTCR_DHQC() uint32 {
	return (volatile.LoadUint32(&o.WPTCR.Reg) & 0x10000000) >> 28
}
func (o *OctoSPI_Type) SetWPTCR_SSHIFT(value uint32) {
	volatile.StoreUint32(&o.WPTCR.Reg, volatile.LoadUint32(&o.WPTCR.Reg)&^(0x40000000)|value<<30)
}
func (o *OctoSPI_Type) GetWPTCR_SSHIFT() uint32 {
	return (volatile.LoadUint32(&o.WPTCR.Reg) & 0x40000000) >> 30
}

// OctoSPI.WPIR: wrap instruction register
func (o *OctoSPI_Type) SetWPIR(value uint32) {
	volatile.StoreUint32(&o.WPIR.Reg, value)
}
func (o *OctoSPI_Type) GetWPIR() uint32 {
	return volatile.LoadUint32(&o.WPIR.Reg)
}

// OctoSPI.WPABR: wrap alternate bytes register
func (o *OctoSPI_Type) SetWPABR(value uint32) {
	volatile.StoreUint32(&o.WPABR.Reg, value)
}
func (o *OctoSPI_Type) GetWPABR() uint32 {
	return volatile.LoadUint32(&o.WPABR.Reg)
}

// OctoSPI.WCCR: write communication configuration register
func (o *OctoSPI_Type) SetWCCR_IMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x7)|value)
}
func (o *OctoSPI_Type) GetWCCR_IMODE() uint32 {
	return volatile.LoadUint32(&o.WCCR.Reg) & 0x7
}
func (o *OctoSPI_Type) SetWCCR_IDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetWCCR_IDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetWCCR_ISIZE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x30)|value<<4)
}
func (o *OctoSPI_Type) GetWCCR_ISIZE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x30) >> 4
}
func (o *OctoSPI_Type) SetWCCR_ADMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x700)|value<<8)
}
func (o *OctoSPI_Type) GetWCCR_ADMODE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x700) >> 8
}
func (o *OctoSPI_Type) SetWCCR_ADDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x800)|value<<11)
}
func (o *OctoSPI_Type) GetWCCR_ADDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x800) >> 11
}
func (o *OctoSPI_Type) SetWCCR_ADSIZE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x3000)|value<<12)
}
func (o *OctoSPI_Type) GetWCCR_ADSIZE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x3000) >> 12
}
func (o *OctoSPI_Type) SetWCCR_ABMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetWCCR_ABMODE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x70000) >> 16
}
func (o *OctoSPI_Type) SetWCCR_ABDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetWCCR_ABDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetWCCR_ABSIZE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x300000)|value<<20)
}
func (o *OctoSPI_Type) GetWCCR_ABSIZE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x300000) >> 20
}
func (o *OctoSPI_Type) SetWCCR_DMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetWCCR_DMODE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x7000000) >> 24
}
func (o *OctoSPI_Type) SetWCCR_DDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x8000000)|value<<27)
}
func (o *OctoSPI_Type) GetWCCR_DDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x8000000) >> 27
}
func (o *OctoSPI_Type) SetWCCR_DQSE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x20000000)|value<<29)
}
func (o *OctoSPI_Type) GetWCCR_DQSE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x20000000) >> 29
}

// OctoSPI.WTCR: write timing configuration register
func (o *OctoSPI_Type) SetWTCR_DCYC(value uint32) {
	volatile.StoreUint32(&o.WTCR.Reg, volatile.LoadUint32(&o.WTCR.Reg)&^(0x1f)|value)
}
func (o *OctoSPI_Type) GetWTCR_DCYC() uint32 {
	return volatile.LoadUint32(&o.WTCR.Reg) & 0x1f
}

// OctoSPI.WIR: write instruction register
func (o *OctoSPI_Type) SetWIR(value uint32) {
	volatile.StoreUint32(&o.WIR.Reg, value)
}
func (o *OctoSPI_Type) GetWIR() uint32 {
	return volatile.LoadUint32(&o.WIR.Reg)
}

// OctoSPI.WABR: write alternate bytes register
func (o *OctoSPI_Type) SetWABR(value uint32) {
	volatile.StoreUint32(&o.WABR.Reg, value)
}
func (o *OctoSPI_Type) GetWABR() uint32 {
	return volatile.LoadUint32(&o.WABR.Reg)
}

// OctoSPI.HLCR: HyperBus latency configuration register
func (o *OctoSPI_Type) SetHLCR_LM(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetHLCR_LM() uint32 {
	return volatile.LoadUint32(&o.HLCR.Reg) & 0x1
}
func (o *OctoSPI_Type) SetHLCR_WZL(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetHLCR_WZL() uint32 {
	return (volatile.LoadUint32(&o.HLCR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetHLCR_TACC(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0xff00)|value<<8)
}
func (o *OctoSPI_Type) GetHLCR_TACC() uint32 {
	return (volatile.LoadUint32(&o.HLCR.Reg) & 0xff00) >> 8
}
func (o *OctoSPI_Type) SetHLCR_TRWR(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0xff0000)|value<<16)
}
func (o *OctoSPI_Type) GetHLCR_TRWR() uint32 {
	return (volatile.LoadUint32(&o.HLCR.Reg) & 0xff0000) >> 16
}

// Operational amplifiers
type OPAMP_Type struct {
	OPAMP1_CSR   volatile.Register32 // 0x0
	OPAMP1_OTR   volatile.Register32 // 0x4
	OPAMP1_LPOTR volatile.Register32 // 0x8
	_            [4]byte
	OPAMP2_CRS   volatile.Register32 // 0x10
	OPAMP2_OTR   volatile.Register32 // 0x14
	OPAMP2_LPOTR volatile.Register32 // 0x18
}

// OPAMP.OPAMP1_CSR: OPAMP1 control/status register
func (o *OPAMP_Type) SetOPAMP1_CSR_OPAEN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x1)|value)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPAEN() uint32 {
	return volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x1
}
func (o *OPAMP_Type) SetOPAMP1_CSR_OPALPM(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x2)|value<<1)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPALPM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x2) >> 1
}
func (o *OPAMP_Type) SetOPAMP1_CSR_OPAMODE(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0xc)|value<<2)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPAMODE() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0xc) >> 2
}
func (o *OPAMP_Type) SetOPAMP1_CSR_PGA_GAIN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x30)|value<<4)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_PGA_GAIN() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x30) >> 4
}
func (o *OPAMP_Type) SetOPAMP1_CSR_VM_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x300)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_VM_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x300) >> 8
}
func (o *OPAMP_Type) SetOPAMP1_CSR_VP_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x400)|value<<10)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_VP_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x400) >> 10
}
func (o *OPAMP_Type) SetOPAMP1_CSR_CALON(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x1000)|value<<12)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_CALON() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x1000) >> 12
}
func (o *OPAMP_Type) SetOPAMP1_CSR_CALSEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x2000)|value<<13)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_CALSEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x2000) >> 13
}
func (o *OPAMP_Type) SetOPAMP1_CSR_USERTRIM(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x4000)|value<<14)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_USERTRIM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x4000) >> 14
}
func (o *OPAMP_Type) SetOPAMP1_CSR_CALOUT(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x8000)|value<<15)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_CALOUT() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x8000) >> 15
}
func (o *OPAMP_Type) SetOPAMP1_CSR_OPAHSM(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPAHSM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x40000000) >> 30
}
func (o *OPAMP_Type) SetOPAMP1_CSR_OPA_RANGE(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPA_RANGE() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x80000000) >> 31
}

// OPAMP.OPAMP1_OTR: OPAMP1 offset trimming register in normal mode
func (o *OPAMP_Type) SetOPAMP1_OTR_TRIMOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_OTR.Reg, volatile.LoadUint32(&o.OPAMP1_OTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP1_OTR_TRIMOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP1_OTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP1_OTR_TRIMOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_OTR.Reg, volatile.LoadUint32(&o.OPAMP1_OTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP1_OTR_TRIMOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_OTR.Reg) & 0x1f00) >> 8
}

// OPAMP.OPAMP1_LPOTR: OPAMP1 offset trimming register in low-power mode
func (o *OPAMP_Type) SetOPAMP1_LPOTR_TRIMLPOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP1_LPOTR_TRIMLPOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP1_LPOTR_TRIMLPOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP1_LPOTR_TRIMLPOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg) & 0x1f00) >> 8
}

// OPAMP.OPAMP2_CRS: OPAMP2 control/status register
func (o *OPAMP_Type) SetOPAMP2_CRS_OPAEN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x1)|value)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_OPAEN() uint32 {
	return volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x1
}
func (o *OPAMP_Type) SetOPAMP2_CRS_OPALPM(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x2)|value<<1)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_OPALPM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x2) >> 1
}
func (o *OPAMP_Type) SetOPAMP2_CRS_OPAMODE(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0xc)|value<<2)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_OPAMODE() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0xc) >> 2
}
func (o *OPAMP_Type) SetOPAMP2_CRS_PGA_GAIN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x30)|value<<4)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_PGA_GAIN() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x30) >> 4
}
func (o *OPAMP_Type) SetOPAMP2_CRS_VM_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x300)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_VM_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x300) >> 8
}
func (o *OPAMP_Type) SetOPAMP2_CRS_VP_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x400)|value<<10)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_VP_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x400) >> 10
}
func (o *OPAMP_Type) SetOPAMP2_CRS_CALON(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x1000)|value<<12)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_CALON() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x1000) >> 12
}
func (o *OPAMP_Type) SetOPAMP2_CRS_CALSEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x2000)|value<<13)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_CALSEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x2000) >> 13
}
func (o *OPAMP_Type) SetOPAMP2_CRS_USERTRIM(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x4000)|value<<14)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_USERTRIM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x4000) >> 14
}
func (o *OPAMP_Type) SetOPAMP2_CRS_CALOUT(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x8000)|value<<15)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_CALOUT() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x8000) >> 15
}
func (o *OPAMP_Type) SetOPAMP2_CRS_OPAHSM(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x40000000)|value<<30)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_OPAHSM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x40000000) >> 30
}

// OPAMP.OPAMP2_OTR: OPAMP2 offset trimming register in normal mode
func (o *OPAMP_Type) SetOPAMP2_OTR_TRIMOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_OTR.Reg, volatile.LoadUint32(&o.OPAMP2_OTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP2_OTR_TRIMOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP2_OTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP2_OTR_TRIMOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_OTR.Reg, volatile.LoadUint32(&o.OPAMP2_OTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP2_OTR_TRIMOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_OTR.Reg) & 0x1f00) >> 8
}

// OPAMP.OPAMP2_LPOTR: OPAMP2 offset trimming register in low-power mode
func (o *OPAMP_Type) SetOPAMP2_LPOTR_TRIMLPOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP2_LPOTR_TRIMLPOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP2_LPOTR_TRIMLPOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP2_LPOTR_TRIMLPOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg) & 0x1f00) >> 8
}

// On-The-Fly Decryption engine
type OTFDEC_Type struct {
	CR          volatile.Register32 // 0x0
	_           [12]byte
	PRIVCFGR    volatile.Register32 // 0x10
	_           [12]byte
	R1CFGR      volatile.Register32 // 0x20
	R1STARTADDR volatile.Register32 // 0x24
	R1ENDADDR   volatile.Register32 // 0x28
	R1NONCER0   volatile.Register32 // 0x2C
	R1NONCER1   volatile.Register32 // 0x30
	R1KEYR0     volatile.Register32 // 0x34
	R1KEYR1     volatile.Register32 // 0x38
	R1KEYR2     volatile.Register32 // 0x3C
	R1KEYR3     volatile.Register32 // 0x40
	_           [12]byte
	R2CFGR      volatile.Register32 // 0x50
	R2STARTADDR volatile.Register32 // 0x54
	R2ENDADDR   volatile.Register32 // 0x58
	R2NONCER0   volatile.Register32 // 0x5C
	R2NONCER1   volatile.Register32 // 0x60
	R2KEYR0     volatile.Register32 // 0x64
	R2KEYR1     volatile.Register32 // 0x68
	R2KEYR2     volatile.Register32 // 0x6C
	R2KEYR3     volatile.Register32 // 0x70
	_           [12]byte
	R3CFGR      volatile.Register32 // 0x80
	R3STARTADDR volatile.Register32 // 0x84
	R3ENDADDR   volatile.Register32 // 0x88
	R3NONCER0   volatile.Register32 // 0x8C
	R3NONCER1   volatile.Register32 // 0x90
	R3KEYR0     volatile.Register32 // 0x94
	R3KEYR1     volatile.Register32 // 0x98
	R3KEYR2     volatile.Register32 // 0x9C
	R3KEYR3     volatile.Register32 // 0xA0
	_           [12]byte
	R4CFGR      volatile.Register32 // 0xB0
	R4STARTADDR volatile.Register32 // 0xB4
	R4ENDADDR   volatile.Register32 // 0xB8
	R4NONCER0   volatile.Register32 // 0xBC
	R4NONCER1   volatile.Register32 // 0xC0
	R4KEYR0     volatile.Register32 // 0xC4
	R4KEYR1     volatile.Register32 // 0xC8
	R4KEYR2     volatile.Register32 // 0xCC
	R4KEYR3     volatile.Register32 // 0xD0
	_           [556]byte
	ISR         volatile.Register32 // 0x300
	ICR         volatile.Register32 // 0x304
	IER         volatile.Register32 // 0x308
}

// OTFDEC.CR: OTFDEC control register
func (o *OTFDEC_Type) SetCR_ENC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetCR_ENC() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// OTFDEC.PRIVCFGR: OTFDEC privileged access control configuration register
func (o *OTFDEC_Type) SetPRIVCFGR_PRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetPRIVCFGR_PRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x1
}

// OTFDEC.R1CFGR: OTFDEC region x configuration register
func (o *OTFDEC_Type) SetR1CFGR_REG_EN(value uint32) {
	volatile.StoreUint32(&o.R1CFGR.Reg, volatile.LoadUint32(&o.R1CFGR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetR1CFGR_REG_EN() uint32 {
	return volatile.LoadUint32(&o.R1CFGR.Reg) & 0x1
}
func (o *OTFDEC_Type) SetR1CFGR_CONFIGLOCK(value uint32) {
	volatile.StoreUint32(&o.R1CFGR.Reg, volatile.LoadUint32(&o.R1CFGR.Reg)&^(0x2)|value<<1)
}
func (o *OTFDEC_Type) GetR1CFGR_CONFIGLOCK() uint32 {
	return (volatile.LoadUint32(&o.R1CFGR.Reg) & 0x2) >> 1
}
func (o *OTFDEC_Type) SetR1CFGR_KEYLOCK(value uint32) {
	volatile.StoreUint32(&o.R1CFGR.Reg, volatile.LoadUint32(&o.R1CFGR.Reg)&^(0x4)|value<<2)
}
func (o *OTFDEC_Type) GetR1CFGR_KEYLOCK() uint32 {
	return (volatile.LoadUint32(&o.R1CFGR.Reg) & 0x4) >> 2
}
func (o *OTFDEC_Type) SetR1CFGR_MODE(value uint32) {
	volatile.StoreUint32(&o.R1CFGR.Reg, volatile.LoadUint32(&o.R1CFGR.Reg)&^(0x30)|value<<4)
}
func (o *OTFDEC_Type) GetR1CFGR_MODE() uint32 {
	return (volatile.LoadUint32(&o.R1CFGR.Reg) & 0x30) >> 4
}
func (o *OTFDEC_Type) SetR1CFGR_KEYCRC(value uint32) {
	volatile.StoreUint32(&o.R1CFGR.Reg, volatile.LoadUint32(&o.R1CFGR.Reg)&^(0xff00)|value<<8)
}
func (o *OTFDEC_Type) GetR1CFGR_KEYCRC() uint32 {
	return (volatile.LoadUint32(&o.R1CFGR.Reg) & 0xff00) >> 8
}
func (o *OTFDEC_Type) SetR1CFGR_REG1_VERSION(value uint32) {
	volatile.StoreUint32(&o.R1CFGR.Reg, volatile.LoadUint32(&o.R1CFGR.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTFDEC_Type) GetR1CFGR_REG1_VERSION() uint32 {
	return (volatile.LoadUint32(&o.R1CFGR.Reg) & 0xffff0000) >> 16
}

// OTFDEC.R1STARTADDR: OTFDEC region x start address register
func (o *OTFDEC_Type) SetR1STARTADDR(value uint32) {
	volatile.StoreUint32(&o.R1STARTADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR1STARTADDR() uint32 {
	return volatile.LoadUint32(&o.R1STARTADDR.Reg)
}

// OTFDEC.R1ENDADDR: OTFDEC region x end address register
func (o *OTFDEC_Type) SetR1ENDADDR(value uint32) {
	volatile.StoreUint32(&o.R1ENDADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR1ENDADDR() uint32 {
	return volatile.LoadUint32(&o.R1ENDADDR.Reg)
}

// OTFDEC.R1NONCER0: OTFDEC region x nonce register 0
func (o *OTFDEC_Type) SetR1NONCER0(value uint32) {
	volatile.StoreUint32(&o.R1NONCER0.Reg, value)
}
func (o *OTFDEC_Type) GetR1NONCER0() uint32 {
	return volatile.LoadUint32(&o.R1NONCER0.Reg)
}

// OTFDEC.R1NONCER1: OTFDEC region x nonce register 1
func (o *OTFDEC_Type) SetR1NONCER1(value uint32) {
	volatile.StoreUint32(&o.R1NONCER1.Reg, value)
}
func (o *OTFDEC_Type) GetR1NONCER1() uint32 {
	return volatile.LoadUint32(&o.R1NONCER1.Reg)
}

// OTFDEC.R1KEYR0: OTFDEC region x key register 0
func (o *OTFDEC_Type) SetR1KEYR0(value uint32) {
	volatile.StoreUint32(&o.R1KEYR0.Reg, value)
}
func (o *OTFDEC_Type) GetR1KEYR0() uint32 {
	return volatile.LoadUint32(&o.R1KEYR0.Reg)
}

// OTFDEC.R1KEYR1: OTFDEC region x key register 1
func (o *OTFDEC_Type) SetR1KEYR1(value uint32) {
	volatile.StoreUint32(&o.R1KEYR1.Reg, value)
}
func (o *OTFDEC_Type) GetR1KEYR1() uint32 {
	return volatile.LoadUint32(&o.R1KEYR1.Reg)
}

// OTFDEC.R1KEYR2: OTFDEC region x key register 2
func (o *OTFDEC_Type) SetR1KEYR2(value uint32) {
	volatile.StoreUint32(&o.R1KEYR2.Reg, value)
}
func (o *OTFDEC_Type) GetR1KEYR2() uint32 {
	return volatile.LoadUint32(&o.R1KEYR2.Reg)
}

// OTFDEC.R1KEYR3: OTFDEC region x key register 3
func (o *OTFDEC_Type) SetR1KEYR3(value uint32) {
	volatile.StoreUint32(&o.R1KEYR3.Reg, value)
}
func (o *OTFDEC_Type) GetR1KEYR3() uint32 {
	return volatile.LoadUint32(&o.R1KEYR3.Reg)
}

// OTFDEC.R2CFGR: OTFDEC region x configuration register
func (o *OTFDEC_Type) SetR2CFGR_REG_EN(value uint32) {
	volatile.StoreUint32(&o.R2CFGR.Reg, volatile.LoadUint32(&o.R2CFGR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetR2CFGR_REG_EN() uint32 {
	return volatile.LoadUint32(&o.R2CFGR.Reg) & 0x1
}
func (o *OTFDEC_Type) SetR2CFGR_CONFIGLOCK(value uint32) {
	volatile.StoreUint32(&o.R2CFGR.Reg, volatile.LoadUint32(&o.R2CFGR.Reg)&^(0x2)|value<<1)
}
func (o *OTFDEC_Type) GetR2CFGR_CONFIGLOCK() uint32 {
	return (volatile.LoadUint32(&o.R2CFGR.Reg) & 0x2) >> 1
}
func (o *OTFDEC_Type) SetR2CFGR_KEYLOCK(value uint32) {
	volatile.StoreUint32(&o.R2CFGR.Reg, volatile.LoadUint32(&o.R2CFGR.Reg)&^(0x4)|value<<2)
}
func (o *OTFDEC_Type) GetR2CFGR_KEYLOCK() uint32 {
	return (volatile.LoadUint32(&o.R2CFGR.Reg) & 0x4) >> 2
}
func (o *OTFDEC_Type) SetR2CFGR_MODE(value uint32) {
	volatile.StoreUint32(&o.R2CFGR.Reg, volatile.LoadUint32(&o.R2CFGR.Reg)&^(0x30)|value<<4)
}
func (o *OTFDEC_Type) GetR2CFGR_MODE() uint32 {
	return (volatile.LoadUint32(&o.R2CFGR.Reg) & 0x30) >> 4
}
func (o *OTFDEC_Type) SetR2CFGR_KEYCRC(value uint32) {
	volatile.StoreUint32(&o.R2CFGR.Reg, volatile.LoadUint32(&o.R2CFGR.Reg)&^(0xff00)|value<<8)
}
func (o *OTFDEC_Type) GetR2CFGR_KEYCRC() uint32 {
	return (volatile.LoadUint32(&o.R2CFGR.Reg) & 0xff00) >> 8
}
func (o *OTFDEC_Type) SetR2CFGR_REG2_VERSION(value uint32) {
	volatile.StoreUint32(&o.R2CFGR.Reg, volatile.LoadUint32(&o.R2CFGR.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTFDEC_Type) GetR2CFGR_REG2_VERSION() uint32 {
	return (volatile.LoadUint32(&o.R2CFGR.Reg) & 0xffff0000) >> 16
}

// OTFDEC.R2STARTADDR: OTFDEC region x start address register
func (o *OTFDEC_Type) SetR2STARTADDR(value uint32) {
	volatile.StoreUint32(&o.R2STARTADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR2STARTADDR() uint32 {
	return volatile.LoadUint32(&o.R2STARTADDR.Reg)
}

// OTFDEC.R2ENDADDR: OTFDEC region x end address register
func (o *OTFDEC_Type) SetR2ENDADDR(value uint32) {
	volatile.StoreUint32(&o.R2ENDADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR2ENDADDR() uint32 {
	return volatile.LoadUint32(&o.R2ENDADDR.Reg)
}

// OTFDEC.R2NONCER0: OTFDEC region x nonce register 0
func (o *OTFDEC_Type) SetR2NONCER0(value uint32) {
	volatile.StoreUint32(&o.R2NONCER0.Reg, value)
}
func (o *OTFDEC_Type) GetR2NONCER0() uint32 {
	return volatile.LoadUint32(&o.R2NONCER0.Reg)
}

// OTFDEC.R2NONCER1: OTFDEC region x nonce register 1
func (o *OTFDEC_Type) SetR2NONCER1(value uint32) {
	volatile.StoreUint32(&o.R2NONCER1.Reg, value)
}
func (o *OTFDEC_Type) GetR2NONCER1() uint32 {
	return volatile.LoadUint32(&o.R2NONCER1.Reg)
}

// OTFDEC.R2KEYR0: OTFDEC region x key register 0
func (o *OTFDEC_Type) SetR2KEYR0(value uint32) {
	volatile.StoreUint32(&o.R2KEYR0.Reg, value)
}
func (o *OTFDEC_Type) GetR2KEYR0() uint32 {
	return volatile.LoadUint32(&o.R2KEYR0.Reg)
}

// OTFDEC.R2KEYR1: OTFDEC region x key register 1
func (o *OTFDEC_Type) SetR2KEYR1(value uint32) {
	volatile.StoreUint32(&o.R2KEYR1.Reg, value)
}
func (o *OTFDEC_Type) GetR2KEYR1() uint32 {
	return volatile.LoadUint32(&o.R2KEYR1.Reg)
}

// OTFDEC.R2KEYR2: OTFDEC region x key register 2
func (o *OTFDEC_Type) SetR2KEYR2(value uint32) {
	volatile.StoreUint32(&o.R2KEYR2.Reg, value)
}
func (o *OTFDEC_Type) GetR2KEYR2() uint32 {
	return volatile.LoadUint32(&o.R2KEYR2.Reg)
}

// OTFDEC.R2KEYR3: OTFDEC region x key register 3
func (o *OTFDEC_Type) SetR2KEYR3(value uint32) {
	volatile.StoreUint32(&o.R2KEYR3.Reg, value)
}
func (o *OTFDEC_Type) GetR2KEYR3() uint32 {
	return volatile.LoadUint32(&o.R2KEYR3.Reg)
}

// OTFDEC.R3CFGR: OTFDEC region x configuration register
func (o *OTFDEC_Type) SetR3CFGR_REG_EN(value uint32) {
	volatile.StoreUint32(&o.R3CFGR.Reg, volatile.LoadUint32(&o.R3CFGR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetR3CFGR_REG_EN() uint32 {
	return volatile.LoadUint32(&o.R3CFGR.Reg) & 0x1
}
func (o *OTFDEC_Type) SetR3CFGR_CONFIGLOCK(value uint32) {
	volatile.StoreUint32(&o.R3CFGR.Reg, volatile.LoadUint32(&o.R3CFGR.Reg)&^(0x2)|value<<1)
}
func (o *OTFDEC_Type) GetR3CFGR_CONFIGLOCK() uint32 {
	return (volatile.LoadUint32(&o.R3CFGR.Reg) & 0x2) >> 1
}
func (o *OTFDEC_Type) SetR3CFGR_KEYLOCK(value uint32) {
	volatile.StoreUint32(&o.R3CFGR.Reg, volatile.LoadUint32(&o.R3CFGR.Reg)&^(0x4)|value<<2)
}
func (o *OTFDEC_Type) GetR3CFGR_KEYLOCK() uint32 {
	return (volatile.LoadUint32(&o.R3CFGR.Reg) & 0x4) >> 2
}
func (o *OTFDEC_Type) SetR3CFGR_MODE(value uint32) {
	volatile.StoreUint32(&o.R3CFGR.Reg, volatile.LoadUint32(&o.R3CFGR.Reg)&^(0x30)|value<<4)
}
func (o *OTFDEC_Type) GetR3CFGR_MODE() uint32 {
	return (volatile.LoadUint32(&o.R3CFGR.Reg) & 0x30) >> 4
}
func (o *OTFDEC_Type) SetR3CFGR_KEYCRC(value uint32) {
	volatile.StoreUint32(&o.R3CFGR.Reg, volatile.LoadUint32(&o.R3CFGR.Reg)&^(0xff00)|value<<8)
}
func (o *OTFDEC_Type) GetR3CFGR_KEYCRC() uint32 {
	return (volatile.LoadUint32(&o.R3CFGR.Reg) & 0xff00) >> 8
}
func (o *OTFDEC_Type) SetR3CFGR_REG3_VERSION(value uint32) {
	volatile.StoreUint32(&o.R3CFGR.Reg, volatile.LoadUint32(&o.R3CFGR.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTFDEC_Type) GetR3CFGR_REG3_VERSION() uint32 {
	return (volatile.LoadUint32(&o.R3CFGR.Reg) & 0xffff0000) >> 16
}

// OTFDEC.R3STARTADDR: OTFDEC region x start address register
func (o *OTFDEC_Type) SetR3STARTADDR(value uint32) {
	volatile.StoreUint32(&o.R3STARTADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR3STARTADDR() uint32 {
	return volatile.LoadUint32(&o.R3STARTADDR.Reg)
}

// OTFDEC.R3ENDADDR: OTFDEC region x end address register
func (o *OTFDEC_Type) SetR3ENDADDR(value uint32) {
	volatile.StoreUint32(&o.R3ENDADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR3ENDADDR() uint32 {
	return volatile.LoadUint32(&o.R3ENDADDR.Reg)
}

// OTFDEC.R3NONCER0: OTFDEC region x nonce register 0
func (o *OTFDEC_Type) SetR3NONCER0(value uint32) {
	volatile.StoreUint32(&o.R3NONCER0.Reg, value)
}
func (o *OTFDEC_Type) GetR3NONCER0() uint32 {
	return volatile.LoadUint32(&o.R3NONCER0.Reg)
}

// OTFDEC.R3NONCER1: OTFDEC region x nonce register 1
func (o *OTFDEC_Type) SetR3NONCER1(value uint32) {
	volatile.StoreUint32(&o.R3NONCER1.Reg, value)
}
func (o *OTFDEC_Type) GetR3NONCER1() uint32 {
	return volatile.LoadUint32(&o.R3NONCER1.Reg)
}

// OTFDEC.R3KEYR0: OTFDEC region x key register 0
func (o *OTFDEC_Type) SetR3KEYR0(value uint32) {
	volatile.StoreUint32(&o.R3KEYR0.Reg, value)
}
func (o *OTFDEC_Type) GetR3KEYR0() uint32 {
	return volatile.LoadUint32(&o.R3KEYR0.Reg)
}

// OTFDEC.R3KEYR1: OTFDEC region x key register 1
func (o *OTFDEC_Type) SetR3KEYR1(value uint32) {
	volatile.StoreUint32(&o.R3KEYR1.Reg, value)
}
func (o *OTFDEC_Type) GetR3KEYR1() uint32 {
	return volatile.LoadUint32(&o.R3KEYR1.Reg)
}

// OTFDEC.R3KEYR2: OTFDEC region x key register 2
func (o *OTFDEC_Type) SetR3KEYR2(value uint32) {
	volatile.StoreUint32(&o.R3KEYR2.Reg, value)
}
func (o *OTFDEC_Type) GetR3KEYR2() uint32 {
	return volatile.LoadUint32(&o.R3KEYR2.Reg)
}

// OTFDEC.R3KEYR3: OTFDEC region x key register 3
func (o *OTFDEC_Type) SetR3KEYR3(value uint32) {
	volatile.StoreUint32(&o.R3KEYR3.Reg, value)
}
func (o *OTFDEC_Type) GetR3KEYR3() uint32 {
	return volatile.LoadUint32(&o.R3KEYR3.Reg)
}

// OTFDEC.R4CFGR: OTFDEC region x configuration register
func (o *OTFDEC_Type) SetR4CFGR_REG_EN(value uint32) {
	volatile.StoreUint32(&o.R4CFGR.Reg, volatile.LoadUint32(&o.R4CFGR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetR4CFGR_REG_EN() uint32 {
	return volatile.LoadUint32(&o.R4CFGR.Reg) & 0x1
}
func (o *OTFDEC_Type) SetR4CFGR_CONFIGLOCK(value uint32) {
	volatile.StoreUint32(&o.R4CFGR.Reg, volatile.LoadUint32(&o.R4CFGR.Reg)&^(0x2)|value<<1)
}
func (o *OTFDEC_Type) GetR4CFGR_CONFIGLOCK() uint32 {
	return (volatile.LoadUint32(&o.R4CFGR.Reg) & 0x2) >> 1
}
func (o *OTFDEC_Type) SetR4CFGR_KEYLOCK(value uint32) {
	volatile.StoreUint32(&o.R4CFGR.Reg, volatile.LoadUint32(&o.R4CFGR.Reg)&^(0x4)|value<<2)
}
func (o *OTFDEC_Type) GetR4CFGR_KEYLOCK() uint32 {
	return (volatile.LoadUint32(&o.R4CFGR.Reg) & 0x4) >> 2
}
func (o *OTFDEC_Type) SetR4CFGR_MODE(value uint32) {
	volatile.StoreUint32(&o.R4CFGR.Reg, volatile.LoadUint32(&o.R4CFGR.Reg)&^(0x30)|value<<4)
}
func (o *OTFDEC_Type) GetR4CFGR_MODE() uint32 {
	return (volatile.LoadUint32(&o.R4CFGR.Reg) & 0x30) >> 4
}
func (o *OTFDEC_Type) SetR4CFGR_KEYCRC(value uint32) {
	volatile.StoreUint32(&o.R4CFGR.Reg, volatile.LoadUint32(&o.R4CFGR.Reg)&^(0xff00)|value<<8)
}
func (o *OTFDEC_Type) GetR4CFGR_KEYCRC() uint32 {
	return (volatile.LoadUint32(&o.R4CFGR.Reg) & 0xff00) >> 8
}
func (o *OTFDEC_Type) SetR4CFGR_REG4_VERSION(value uint32) {
	volatile.StoreUint32(&o.R4CFGR.Reg, volatile.LoadUint32(&o.R4CFGR.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTFDEC_Type) GetR4CFGR_REG4_VERSION() uint32 {
	return (volatile.LoadUint32(&o.R4CFGR.Reg) & 0xffff0000) >> 16
}

// OTFDEC.R4STARTADDR: OTFDEC region x start address register
func (o *OTFDEC_Type) SetR4STARTADDR(value uint32) {
	volatile.StoreUint32(&o.R4STARTADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR4STARTADDR() uint32 {
	return volatile.LoadUint32(&o.R4STARTADDR.Reg)
}

// OTFDEC.R4ENDADDR: OTFDEC region x end address register
func (o *OTFDEC_Type) SetR4ENDADDR(value uint32) {
	volatile.StoreUint32(&o.R4ENDADDR.Reg, value)
}
func (o *OTFDEC_Type) GetR4ENDADDR() uint32 {
	return volatile.LoadUint32(&o.R4ENDADDR.Reg)
}

// OTFDEC.R4NONCER0: OTFDEC region x nonce register 0
func (o *OTFDEC_Type) SetR4NONCER0(value uint32) {
	volatile.StoreUint32(&o.R4NONCER0.Reg, value)
}
func (o *OTFDEC_Type) GetR4NONCER0() uint32 {
	return volatile.LoadUint32(&o.R4NONCER0.Reg)
}

// OTFDEC.R4NONCER1: OTFDEC region x nonce register 1
func (o *OTFDEC_Type) SetR4NONCER1(value uint32) {
	volatile.StoreUint32(&o.R4NONCER1.Reg, value)
}
func (o *OTFDEC_Type) GetR4NONCER1() uint32 {
	return volatile.LoadUint32(&o.R4NONCER1.Reg)
}

// OTFDEC.R4KEYR0: OTFDEC region x key register 0
func (o *OTFDEC_Type) SetR4KEYR0(value uint32) {
	volatile.StoreUint32(&o.R4KEYR0.Reg, value)
}
func (o *OTFDEC_Type) GetR4KEYR0() uint32 {
	return volatile.LoadUint32(&o.R4KEYR0.Reg)
}

// OTFDEC.R4KEYR1: OTFDEC region x key register 1
func (o *OTFDEC_Type) SetR4KEYR1(value uint32) {
	volatile.StoreUint32(&o.R4KEYR1.Reg, value)
}
func (o *OTFDEC_Type) GetR4KEYR1() uint32 {
	return volatile.LoadUint32(&o.R4KEYR1.Reg)
}

// OTFDEC.R4KEYR2: OTFDEC region x key register 2
func (o *OTFDEC_Type) SetR4KEYR2(value uint32) {
	volatile.StoreUint32(&o.R4KEYR2.Reg, value)
}
func (o *OTFDEC_Type) GetR4KEYR2() uint32 {
	return volatile.LoadUint32(&o.R4KEYR2.Reg)
}

// OTFDEC.R4KEYR3: OTFDEC region x key register 3
func (o *OTFDEC_Type) SetR4KEYR3(value uint32) {
	volatile.StoreUint32(&o.R4KEYR3.Reg, value)
}
func (o *OTFDEC_Type) GetR4KEYR3() uint32 {
	return volatile.LoadUint32(&o.R4KEYR3.Reg)
}

// OTFDEC.ISR: OTFDEC interrupt status register
func (o *OTFDEC_Type) SetISR_SEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetISR_SEIF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *OTFDEC_Type) SetISR_XONEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *OTFDEC_Type) GetISR_XONEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *OTFDEC_Type) SetISR_KEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *OTFDEC_Type) GetISR_KEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}

// OTFDEC.ICR: OTFDEC interrupt clear register
func (o *OTFDEC_Type) SetICR_SEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetICR_SEIF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *OTFDEC_Type) SetICR_XONEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *OTFDEC_Type) GetICR_XONEIF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *OTFDEC_Type) SetICR_KEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *OTFDEC_Type) GetICR_KEIF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}

// OTFDEC.IER: OTFDEC interrupt enable register
func (o *OTFDEC_Type) SetIER_SEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *OTFDEC_Type) GetIER_SEIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *OTFDEC_Type) SetIER_XONEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *OTFDEC_Type) GetIER_XONEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *OTFDEC_Type) SetIER_KEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *OTFDEC_Type) GetIER_KEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}

// OTG_HS
type OTG_HS_Type struct {
	GOTGCTL         volatile.Register32 // 0x0
	GOTGINT         volatile.Register32 // 0x4
	GAHBCFG         volatile.Register32 // 0x8
	GUSBCFG         volatile.Register32 // 0xC
	GRSTCTL         volatile.Register32 // 0x10
	GINTSTS         volatile.Register32 // 0x14
	GINTMSK         volatile.Register32 // 0x18
	GRXSTSR_DEVICE  volatile.Register32 // 0x1C
	GRXSTSP_DEVICE  volatile.Register32 // 0x20
	GRXFSIZ         volatile.Register32 // 0x24
	HNPTXFSIZ       volatile.Register32 // 0x28
	HNPTXSTS        volatile.Register32 // 0x2C
	_               [8]byte
	GCCFG           volatile.Register32 // 0x38
	CID             volatile.Register32 // 0x3C
	_               [20]byte
	GLPMCFG         volatile.Register32 // 0x54
	_               [168]byte
	HPTXFSIZ        volatile.Register32 // 0x100
	DIEPTXF1        volatile.Register32 // 0x104
	DIEPTXF2        volatile.Register32 // 0x108
	DIEPTXF3        volatile.Register32 // 0x10C
	DIEPTXF4        volatile.Register32 // 0x110
	DIEPTXF5        volatile.Register32 // 0x114
	DIEPTXF6        volatile.Register32 // 0x118
	DIEPTXF7        volatile.Register32 // 0x11C
	DIEPTXF8        volatile.Register32 // 0x120
	_               [732]byte
	HCFG            volatile.Register32 // 0x400
	HFIR            volatile.Register32 // 0x404
	HFNUM           volatile.Register32 // 0x408
	_               [4]byte
	HPTXSTS         volatile.Register32 // 0x410
	HAINT           volatile.Register32 // 0x414
	HAINTMSK        volatile.Register32 // 0x418
	_               [36]byte
	HPRT            volatile.Register32 // 0x440
	_               [188]byte
	HCCHAR0         volatile.Register32 // 0x500
	HCSPLT0         volatile.Register32 // 0x504
	HCINT0          volatile.Register32 // 0x508
	HCINTMSK0       volatile.Register32 // 0x50C
	HCTSIZ0         volatile.Register32 // 0x510
	HCDMA0          volatile.Register32 // 0x514
	_               [8]byte
	HCCHAR1         volatile.Register32 // 0x520
	HCSPLT1         volatile.Register32 // 0x524
	HCINT1_DEVICE   volatile.Register32 // 0x528
	HCINTMSK1       volatile.Register32 // 0x52C
	HCTSIZ1         volatile.Register32 // 0x530
	HCDMA1          volatile.Register32 // 0x534
	_               [8]byte
	HCCHAR2         volatile.Register32 // 0x540
	HCSPLT2         volatile.Register32 // 0x544
	HCINT2          volatile.Register32 // 0x548
	HCINTMSK2       volatile.Register32 // 0x54C
	HCTSIZ2         volatile.Register32 // 0x550
	HCDMA2          volatile.Register32 // 0x554
	_               [8]byte
	HCCHAR3         volatile.Register32 // 0x560
	HCSPLT3         volatile.Register32 // 0x564
	HCINT3          volatile.Register32 // 0x568
	HCINTMSK3       volatile.Register32 // 0x56C
	HCTSIZ3         volatile.Register32 // 0x570
	HCDMA3          volatile.Register32 // 0x574
	_               [8]byte
	HCCHAR4         volatile.Register32 // 0x580
	HCSPLT4         volatile.Register32 // 0x584
	HCINT4          volatile.Register32 // 0x588
	HCINTMSK4       volatile.Register32 // 0x58C
	HCTSIZ4         volatile.Register32 // 0x590
	HCDMA4          volatile.Register32 // 0x594
	_               [8]byte
	HCCHAR5         volatile.Register32 // 0x5A0
	HCSPLT5         volatile.Register32 // 0x5A4
	HCINT5          volatile.Register32 // 0x5A8
	HCINTMSK5       volatile.Register32 // 0x5AC
	HCTSIZ5         volatile.Register32 // 0x5B0
	HCDMA5          volatile.Register32 // 0x5B4
	_               [8]byte
	HCCHAR6         volatile.Register32 // 0x5C0
	HCSPLT6         volatile.Register32 // 0x5C4
	HCINT6          volatile.Register32 // 0x5C8
	HCINTMSK6       volatile.Register32 // 0x5CC
	HCTSIZ6         volatile.Register32 // 0x5D0
	HCDMA6          volatile.Register32 // 0x5D4
	_               [8]byte
	HCCHAR7         volatile.Register32 // 0x5E0
	HCSPLT7         volatile.Register32 // 0x5E4
	HCINT7          volatile.Register32 // 0x5E8
	HCINTMSK7       volatile.Register32 // 0x5EC
	HCTSIZ7         volatile.Register32 // 0x5F0
	HCDMA7          volatile.Register32 // 0x5F4
	_               [8]byte
	HCCHAR8         volatile.Register32 // 0x600
	HCSPLT8         volatile.Register32 // 0x604
	HCINT8          volatile.Register32 // 0x608
	HCINTMSK8       volatile.Register32 // 0x60C
	HCTSIZ8         volatile.Register32 // 0x610
	HCDMA8          volatile.Register32 // 0x614
	_               [8]byte
	HCCHAR9         volatile.Register32 // 0x620
	HCSPLT9         volatile.Register32 // 0x624
	HCINT9          volatile.Register32 // 0x628
	HCINTMSK9       volatile.Register32 // 0x62C
	HCTSIZ9         volatile.Register32 // 0x630
	HCDMA9          volatile.Register32 // 0x634
	_               [8]byte
	HCCHAR10        volatile.Register32 // 0x640
	HCSPLT10        volatile.Register32 // 0x644
	HCINT10         volatile.Register32 // 0x648
	HCINTMSK10      volatile.Register32 // 0x64C
	HCTSIZ10        volatile.Register32 // 0x650
	HCDMA10         volatile.Register32 // 0x654
	_               [8]byte
	HCCHAR11        volatile.Register32 // 0x660
	HCSPLT11        volatile.Register32 // 0x664
	HCINT11         volatile.Register32 // 0x668
	HCINTMSK11      volatile.Register32 // 0x66C
	HCTSIZ11        volatile.Register32 // 0x670
	HCDMA11         volatile.Register32 // 0x674
	_               [8]byte
	HCCHAR12        volatile.Register32 // 0x680
	HCSPLT12        volatile.Register32 // 0x684
	HCINT12         volatile.Register32 // 0x688
	HCINTMSK12      volatile.Register32 // 0x68C
	HCTSIZ12        volatile.Register32 // 0x690
	HCDMA12         volatile.Register32 // 0x694
	_               [8]byte
	HCCHAR13        volatile.Register32 // 0x6A0
	HCSPLT13        volatile.Register32 // 0x6A4
	HCINT13         volatile.Register32 // 0x6A8
	HCINTMSK13      volatile.Register32 // 0x6AC
	HCTSIZ13        volatile.Register32 // 0x6B0
	HCDMA13         volatile.Register32 // 0x6B4
	_               [8]byte
	HCCHAR14        volatile.Register32 // 0x6C0
	HCSPLT14        volatile.Register32 // 0x6C4
	HCINT14         volatile.Register32 // 0x6C8
	HCINTMSK14      volatile.Register32 // 0x6CC
	HCTSIZ14        volatile.Register32 // 0x6D0
	HCDMA14         volatile.Register32 // 0x6D4
	_               [8]byte
	HCCHAR15        volatile.Register32 // 0x6E0
	HCSPLT15        volatile.Register32 // 0x6E4
	HCINT15         volatile.Register32 // 0x6E8
	HCINTMSK15      volatile.Register32 // 0x6EC
	HCTSIZ15        volatile.Register32 // 0x6F0
	HCDMA15         volatile.Register32 // 0x6F4
	_               [264]byte
	DCFG            volatile.Register32 // 0x800
	DCTL            volatile.Register32 // 0x804
	DSTS            volatile.Register32 // 0x808
	_               [4]byte
	DIEPMSK         volatile.Register32 // 0x810
	DOEPMSK         volatile.Register32 // 0x814
	DAINT           volatile.Register32 // 0x818
	DAINTMSK        volatile.Register32 // 0x81C
	_               [8]byte
	DVBUSDIS        volatile.Register32 // 0x828
	DVBUSPULSE      volatile.Register32 // 0x82C
	DTHRCTL         volatile.Register32 // 0x830
	DIEPEMPMSK      volatile.Register32 // 0x834
	_               [76]byte
	HS_DOEPEACHMSK1 volatile.Register32 // 0x884
	_               [120]byte
	DIEPCTL0        volatile.Register32 // 0x900
	_               [4]byte
	DIEPINT0        volatile.Register32 // 0x908
	_               [4]byte
	DIEPTSIZ0       volatile.Register32 // 0x910
	_               [4]byte
	DTXFSTS0        volatile.Register32 // 0x918
	_               [4]byte
	DIEPCTL1        volatile.Register32 // 0x920
	_               [4]byte
	DIEPINT1        volatile.Register32 // 0x928
	_               [4]byte
	DIEPTSIZ1       volatile.Register32 // 0x930
	DIEPDMA1        volatile.Register32 // 0x934
	DTXFSTS1        volatile.Register32 // 0x938
	_               [4]byte
	DIEPCTL2        volatile.Register32 // 0x940
	_               [4]byte
	DIEPINT2        volatile.Register32 // 0x948
	_               [4]byte
	DIEPTSIZ2       volatile.Register32 // 0x950
	DIEPDMA2        volatile.Register32 // 0x954
	DTXFSTS2        volatile.Register32 // 0x958
	_               [4]byte
	DIEPCTL3        volatile.Register32 // 0x960
	_               [4]byte
	DIEPINT3        volatile.Register32 // 0x968
	_               [4]byte
	DIEPTSIZ3       volatile.Register32 // 0x970
	DIEPDMA3        volatile.Register32 // 0x974
	DTXFSTS3        volatile.Register32 // 0x978
	_               [4]byte
	DIEPCTL4        volatile.Register32 // 0x980
	_               [4]byte
	DIEPINT4        volatile.Register32 // 0x988
	_               [4]byte
	DIEPTSIZ4       volatile.Register32 // 0x990
	DIEPDMA4        volatile.Register32 // 0x994
	DTXFSTS4        volatile.Register32 // 0x998
	_               [4]byte
	DIEPCTL5        volatile.Register32 // 0x9A0
	_               [4]byte
	DIEPINT5        volatile.Register32 // 0x9A8
	_               [4]byte
	DIEPTSIZ5       volatile.Register32 // 0x9B0
	DIEPDMA5        volatile.Register32 // 0x9B4
	DTXFSTS5        volatile.Register32 // 0x9B8
	_               [12]byte
	DIEPINT6        volatile.Register32 // 0x9C8
	_               [4]byte
	DIEPTSIZ6       volatile.Register32 // 0x9D0
	DIEPDMA6        volatile.Register32 // 0x9D4
	_               [16]byte
	DIEPINT7        volatile.Register32 // 0x9E8
	_               [4]byte
	DIEPTSIZ7       volatile.Register32 // 0x9F0
	DIEPDMA7        volatile.Register32 // 0x9F4
	_               [16]byte
	DIEPINT8        volatile.Register32 // 0xA08
	_               [4]byte
	DIEPTSIZ8       volatile.Register32 // 0xA10
	DIEPDMA8        volatile.Register32 // 0xA14
	_               [232]byte
	DOEPCTL0        volatile.Register32 // 0xB00
	_               [4]byte
	DOEPINT0        volatile.Register32 // 0xB08
	_               [4]byte
	DOEPTSIZ0       volatile.Register32 // 0xB10
	DOEPDMA0        volatile.Register32 // 0xB14
	_               [8]byte
	DOEPCTL1        volatile.Register32 // 0xB20
	_               [4]byte
	DOEPINT1        volatile.Register32 // 0xB28
	_               [4]byte
	DOEPTSIZ1       volatile.Register32 // 0xB30
	DOEPDMA1        volatile.Register32 // 0xB34
	_               [8]byte
	DOEPCTL2        volatile.Register32 // 0xB40
	_               [4]byte
	DOEPINT2        volatile.Register32 // 0xB48
	_               [4]byte
	DOEPTSIZ2       volatile.Register32 // 0xB50
	DOEPDMA2        volatile.Register32 // 0xB54
	_               [8]byte
	DOEPCTL3        volatile.Register32 // 0xB60
	_               [4]byte
	DOEPINT3        volatile.Register32 // 0xB68
	_               [4]byte
	DOEPTSIZ3       volatile.Register32 // 0xB70
	DOEPDMA3        volatile.Register32 // 0xB74
	_               [8]byte
	DOEPCTL4        volatile.Register32 // 0xB80
	_               [4]byte
	DOEPINT4        volatile.Register32 // 0xB88
	_               [4]byte
	DOEPTSIZ4       volatile.Register32 // 0xB90
	DOEPDMA4        volatile.Register32 // 0xB94
	_               [8]byte
	DOEPCTL5        volatile.Register32 // 0xBA0
	_               [4]byte
	DOEPINT5        volatile.Register32 // 0xBA8
	_               [4]byte
	DOEPTSIZ5       volatile.Register32 // 0xBB0
	DOEPDMA5        volatile.Register32 // 0xBB4
	_               [8]byte
	DOEPCTL6        volatile.Register32 // 0xBC0
	_               [4]byte
	DOEPINT6        volatile.Register32 // 0xBC8
	_               [4]byte
	DOEPTSIZ6       volatile.Register32 // 0xBD0
	DOEPDMA6        volatile.Register32 // 0xBD4
	_               [8]byte
	DOEPCTL7        volatile.Register32 // 0xBE0
	_               [4]byte
	DOEPINT7        volatile.Register32 // 0xBE8
	_               [4]byte
	DOEPTSIZ7       volatile.Register32 // 0xBF0
	DOEPDMA7        volatile.Register32 // 0xBF4
	_               [8]byte
	DOEPCTL8        volatile.Register32 // 0xC00
	_               [4]byte
	DOEPINT8        volatile.Register32 // 0xC08
	_               [4]byte
	DOEPTSIZ8       volatile.Register32 // 0xC10
	DOEPDMA8        volatile.Register32 // 0xC14
	_               [488]byte
	PCGCCTL         volatile.Register32 // 0xE00
}

// OTG_HS.GOTGCTL: The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
func (o *OTG_HS_Type) SetGOTGCTL_SRQSCS(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetGOTGCTL_SRQSCS() uint32 {
	return volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x1
}
func (o *OTG_HS_Type) SetGOTGCTL_SRQ(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetGOTGCTL_SRQ() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetGOTGCTL_VBVALOEN(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetGOTGCTL_VBVALOEN() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetGOTGCTL_VBVALOVAL(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetGOTGCTL_VBVALOVAL() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetGOTGCTL_AVALOEN(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetGOTGCTL_AVALOEN() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetGOTGCTL_AVALOVAL(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetGOTGCTL_AVALOVAL() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetGOTGCTL_BVALOEN(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetGOTGCTL_BVALOEN() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetGOTGCTL_BVALOVAL(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetGOTGCTL_BVALOVAL() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetGOTGCTL_HNGSCS(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetGOTGCTL_HNGSCS() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetGOTGCTL_HNPRQ(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetGOTGCTL_HNPRQ() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetGOTGCTL_HSHNPEN(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetGOTGCTL_HSHNPEN() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x400) >> 10
}
func (o *OTG_HS_Type) SetGOTGCTL_DHNPEN(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetGOTGCTL_DHNPEN() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetGOTGCTL_EHEN(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetGOTGCTL_EHEN() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetGOTGCTL_CIDSTS(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetGOTGCTL_CIDSTS() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetGOTGCTL_DBCT(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetGOTGCTL_DBCT() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetGOTGCTL_ASVLD(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x40000)|value<<18)
}
func (o *OTG_HS_Type) GetGOTGCTL_ASVLD() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x40000) >> 18
}
func (o *OTG_HS_Type) SetGOTGCTL_BSVLD(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x80000)|value<<19)
}
func (o *OTG_HS_Type) GetGOTGCTL_BSVLD() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x80000) >> 19
}
func (o *OTG_HS_Type) SetGOTGCTL_OTGVER(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetGOTGCTL_OTGVER() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetGOTGCTL_CURMOD(value uint32) {
	volatile.StoreUint32(&o.GOTGCTL.Reg, volatile.LoadUint32(&o.GOTGCTL.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetGOTGCTL_CURMOD() uint32 {
	return (volatile.LoadUint32(&o.GOTGCTL.Reg) & 0x200000) >> 21
}

// OTG_HS.GOTGINT: The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
func (o *OTG_HS_Type) SetGOTGINT_SEDET(value uint32) {
	volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetGOTGINT_SEDET() uint32 {
	return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetGOTGINT_SRSSCHG(value uint32) {
	volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetGOTGINT_SRSSCHG() uint32 {
	return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetGOTGINT_HNSSCHG(value uint32) {
	volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetGOTGINT_HNSSCHG() uint32 {
	return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetGOTGINT_HNGDET(value uint32) {
	volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetGOTGINT_HNGDET() uint32 {
	return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetGOTGINT_ADTOCHG(value uint32) {
	volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x40000)|value<<18)
}
func (o *OTG_HS_Type) GetGOTGINT_ADTOCHG() uint32 {
	return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x40000) >> 18
}
func (o *OTG_HS_Type) SetGOTGINT_DBCDNE(value uint32) {
	volatile.StoreUint32(&o.GOTGINT.Reg, volatile.LoadUint32(&o.GOTGINT.Reg)&^(0x80000)|value<<19)
}
func (o *OTG_HS_Type) GetGOTGINT_DBCDNE() uint32 {
	return (volatile.LoadUint32(&o.GOTGINT.Reg) & 0x80000) >> 19
}

// OTG_HS.GAHBCFG: This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
func (o *OTG_HS_Type) SetGAHBCFG_GINTMSK(value uint32) {
	volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetGAHBCFG_GINTMSK() uint32 {
	return volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x1
}
func (o *OTG_HS_Type) SetGAHBCFG_TXFELVL(value uint32) {
	volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetGAHBCFG_TXFELVL() uint32 {
	return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetGAHBCFG_PTXFELVL(value uint32) {
	volatile.StoreUint32(&o.GAHBCFG.Reg, volatile.LoadUint32(&o.GAHBCFG.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetGAHBCFG_PTXFELVL() uint32 {
	return (volatile.LoadUint32(&o.GAHBCFG.Reg) & 0x100) >> 8
}

// OTG_HS.GUSBCFG: This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
func (o *OTG_HS_Type) SetGUSBCFG_TOCAL(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x7)|value)
}
func (o *OTG_HS_Type) GetGUSBCFG_TOCAL() uint32 {
	return volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x7
}
func (o *OTG_HS_Type) SetGUSBCFG_PHYSEL(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetGUSBCFG_PHYSEL() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetGUSBCFG_SRPCAP(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetGUSBCFG_SRPCAP() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetGUSBCFG_HNPCAP(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetGUSBCFG_HNPCAP() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetGUSBCFG_TRDT(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x3c00)|value<<10)
}
func (o *OTG_HS_Type) GetGUSBCFG_TRDT() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x3c00) >> 10
}
func (o *OTG_HS_Type) SetGUSBCFG_PHYLPC(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetGUSBCFG_PHYLPC() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetGUSBCFG_TSDPS(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x400000)|value<<22)
}
func (o *OTG_HS_Type) GetGUSBCFG_TSDPS() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x400000) >> 22
}
func (o *OTG_HS_Type) SetGUSBCFG_FHMOD(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetGUSBCFG_FHMOD() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetGUSBCFG_FDMOD(value uint32) {
	volatile.StoreUint32(&o.GUSBCFG.Reg, volatile.LoadUint32(&o.GUSBCFG.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetGUSBCFG_FDMOD() uint32 {
	return (volatile.LoadUint32(&o.GUSBCFG.Reg) & 0x40000000) >> 30
}

// OTG_HS.GRSTCTL: The application uses this register to reset various hardware features inside the core.
func (o *OTG_HS_Type) SetGRSTCTL_CSRST(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetGRSTCTL_CSRST() uint32 {
	return volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x1
}
func (o *OTG_HS_Type) SetGRSTCTL_PSRST(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetGRSTCTL_PSRST() uint32 {
	return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetGRSTCTL_FSRST(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetGRSTCTL_FSRST() uint32 {
	return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetGRSTCTL_RXFFLSH(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetGRSTCTL_RXFFLSH() uint32 {
	return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetGRSTCTL_TXFFLSH(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetGRSTCTL_TXFFLSH() uint32 {
	return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetGRSTCTL_TXFNUM(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x7c0)|value<<6)
}
func (o *OTG_HS_Type) GetGRSTCTL_TXFNUM() uint32 {
	return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x7c0) >> 6
}
func (o *OTG_HS_Type) SetGRSTCTL_DMAREQ(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetGRSTCTL_DMAREQ() uint32 {
	return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetGRSTCTL_AHBIDL(value uint32) {
	volatile.StoreUint32(&o.GRSTCTL.Reg, volatile.LoadUint32(&o.GRSTCTL.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetGRSTCTL_AHBIDL() uint32 {
	return (volatile.LoadUint32(&o.GRSTCTL.Reg) & 0x80000000) >> 31
}

// OTG_HS.GINTSTS: This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
func (o *OTG_HS_Type) SetGINTSTS_CMOD(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetGINTSTS_CMOD() uint32 {
	return volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1
}
func (o *OTG_HS_Type) SetGINTSTS_MMIS(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetGINTSTS_MMIS() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetGINTSTS_OTGINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetGINTSTS_OTGINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetGINTSTS_SOF(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetGINTSTS_SOF() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetGINTSTS_RXFLVL(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetGINTSTS_RXFLVL() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetGINTSTS_NPTXFE(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetGINTSTS_NPTXFE() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetGINTSTS_GINAKEFF(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetGINTSTS_GINAKEFF() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetGINTSTS_GONAKEFF(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetGINTSTS_GONAKEFF() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetGINTSTS_ESUSP(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetGINTSTS_ESUSP() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x400) >> 10
}
func (o *OTG_HS_Type) SetGINTSTS_USBSUSP(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetGINTSTS_USBSUSP() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetGINTSTS_USBRST(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetGINTSTS_USBRST() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetGINTSTS_ENUMDNE(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetGINTSTS_ENUMDNE() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetGINTSTS_ISOODRP(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetGINTSTS_ISOODRP() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetGINTSTS_EOPF(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetGINTSTS_EOPF() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetGINTSTS_IEPINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40000)|value<<18)
}
func (o *OTG_HS_Type) GetGINTSTS_IEPINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40000) >> 18
}
func (o *OTG_HS_Type) SetGINTSTS_OEPINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80000)|value<<19)
}
func (o *OTG_HS_Type) GetGINTSTS_OEPINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80000) >> 19
}
func (o *OTG_HS_Type) SetGINTSTS_IISOIXFR(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetGINTSTS_IISOIXFR() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetGINTSTS_IPXFR(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetGINTSTS_IPXFR() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetGINTSTS_DATAFSUSP(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x400000)|value<<22)
}
func (o *OTG_HS_Type) GetGINTSTS_DATAFSUSP() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x400000) >> 22
}
func (o *OTG_HS_Type) SetGINTSTS_RSTDET(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x800000)|value<<23)
}
func (o *OTG_HS_Type) GetGINTSTS_RSTDET() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x800000) >> 23
}
func (o *OTG_HS_Type) SetGINTSTS_HPRTINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x1000000)|value<<24)
}
func (o *OTG_HS_Type) GetGINTSTS_HPRTINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x1000000) >> 24
}
func (o *OTG_HS_Type) SetGINTSTS_HCINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x2000000)|value<<25)
}
func (o *OTG_HS_Type) GetGINTSTS_HCINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x2000000) >> 25
}
func (o *OTG_HS_Type) SetGINTSTS_PTXFE(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetGINTSTS_PTXFE() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetGINTSTS_LPMINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetGINTSTS_LPMINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetGINTSTS_CIDSCHG(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetGINTSTS_CIDSCHG() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetGINTSTS_DISCINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetGINTSTS_DISCINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetGINTSTS_SRQINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetGINTSTS_SRQINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetGINTSTS_WKUPINT(value uint32) {
	volatile.StoreUint32(&o.GINTSTS.Reg, volatile.LoadUint32(&o.GINTSTS.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetGINTSTS_WKUPINT() uint32 {
	return (volatile.LoadUint32(&o.GINTSTS.Reg) & 0x80000000) >> 31
}

// OTG_HS.GINTMSK: This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set.
func (o *OTG_HS_Type) SetGINTMSK_MMISM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetGINTMSK_MMISM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetGINTMSK_OTGINT(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetGINTMSK_OTGINT() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetGINTMSK_SOFM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetGINTMSK_SOFM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetGINTMSK_RXFLVLM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetGINTMSK_RXFLVLM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetGINTMSK_NPTXFEM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetGINTMSK_NPTXFEM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetGINTMSK_GINAKEFFM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetGINTMSK_GINAKEFFM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetGINTMSK_GONAKEFFM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetGINTMSK_GONAKEFFM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetGINTMSK_ESUSPM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetGINTMSK_ESUSPM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x400) >> 10
}
func (o *OTG_HS_Type) SetGINTMSK_USBSUSPM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetGINTMSK_USBSUSPM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetGINTMSK_USBRST(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetGINTMSK_USBRST() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetGINTMSK_ENUMDNEM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetGINTMSK_ENUMDNEM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetGINTMSK_ISOODRPM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetGINTMSK_ISOODRPM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetGINTMSK_EOPFM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetGINTMSK_EOPFM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetGINTMSK_IEPINT(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40000)|value<<18)
}
func (o *OTG_HS_Type) GetGINTMSK_IEPINT() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40000) >> 18
}
func (o *OTG_HS_Type) SetGINTMSK_OEPINT(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80000)|value<<19)
}
func (o *OTG_HS_Type) GetGINTMSK_OEPINT() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80000) >> 19
}
func (o *OTG_HS_Type) SetGINTMSK_IISOIXFRM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetGINTMSK_IISOIXFRM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetGINTMSK_IPXFRM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetGINTMSK_IPXFRM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetGINTMSK_FSUSPM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x400000)|value<<22)
}
func (o *OTG_HS_Type) GetGINTMSK_FSUSPM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x400000) >> 22
}
func (o *OTG_HS_Type) SetGINTMSK_RSTDETM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x800000)|value<<23)
}
func (o *OTG_HS_Type) GetGINTMSK_RSTDETM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x800000) >> 23
}
func (o *OTG_HS_Type) SetGINTMSK_PRTIM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x1000000)|value<<24)
}
func (o *OTG_HS_Type) GetGINTMSK_PRTIM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x1000000) >> 24
}
func (o *OTG_HS_Type) SetGINTMSK_HCIM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x2000000)|value<<25)
}
func (o *OTG_HS_Type) GetGINTMSK_HCIM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x2000000) >> 25
}
func (o *OTG_HS_Type) SetGINTMSK_PTXFEM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetGINTMSK_PTXFEM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetGINTMSK_LPMINTM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetGINTMSK_LPMINTM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetGINTMSK_CIDSCHGM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetGINTMSK_CIDSCHGM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetGINTMSK_DISCINT(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetGINTMSK_DISCINT() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetGINTMSK_SRQIM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetGINTMSK_SRQIM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetGINTMSK_WUIM(value uint32) {
	volatile.StoreUint32(&o.GINTMSK.Reg, volatile.LoadUint32(&o.GINTMSK.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetGINTMSK_WUIM() uint32 {
	return (volatile.LoadUint32(&o.GINTMSK.Reg) & 0x80000000) >> 31
}

// OTG_HS.GRXSTSR_DEVICE: This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
func (o *OTG_HS_Type) SetGRXSTSR_DEVICE_EPNUM(value uint32) {
	volatile.StoreUint32(&o.GRXSTSR_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg)&^(0xf)|value)
}
func (o *OTG_HS_Type) GetGRXSTSR_DEVICE_EPNUM() uint32 {
	return volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg) & 0xf
}
func (o *OTG_HS_Type) SetGRXSTSR_DEVICE_BCNT(value uint32) {
	volatile.StoreUint32(&o.GRXSTSR_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg)&^(0x7ff0)|value<<4)
}
func (o *OTG_HS_Type) GetGRXSTSR_DEVICE_BCNT() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg) & 0x7ff0) >> 4
}
func (o *OTG_HS_Type) SetGRXSTSR_DEVICE_DPID(value uint32) {
	volatile.StoreUint32(&o.GRXSTSR_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg)&^(0x18000)|value<<15)
}
func (o *OTG_HS_Type) GetGRXSTSR_DEVICE_DPID() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg) & 0x18000) >> 15
}
func (o *OTG_HS_Type) SetGRXSTSR_DEVICE_PKTSTS(value uint32) {
	volatile.StoreUint32(&o.GRXSTSR_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg)&^(0x1e0000)|value<<17)
}
func (o *OTG_HS_Type) GetGRXSTSR_DEVICE_PKTSTS() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg) & 0x1e0000) >> 17
}
func (o *OTG_HS_Type) SetGRXSTSR_DEVICE_FRMNUM(value uint32) {
	volatile.StoreUint32(&o.GRXSTSR_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg)&^(0x1e00000)|value<<21)
}
func (o *OTG_HS_Type) GetGRXSTSR_DEVICE_FRMNUM() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg) & 0x1e00000) >> 21
}
func (o *OTG_HS_Type) SetGRXSTSR_DEVICE_STSPHST(value uint32) {
	volatile.StoreUint32(&o.GRXSTSR_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetGRXSTSR_DEVICE_STSPHST() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSR_DEVICE.Reg) & 0x8000000) >> 27
}

// OTG_HS.GRXSTSP_DEVICE: This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in GINTSTS) is asserted.
func (o *OTG_HS_Type) SetGRXSTSP_DEVICE_EPNUM(value uint32) {
	volatile.StoreUint32(&o.GRXSTSP_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg)&^(0xf)|value)
}
func (o *OTG_HS_Type) GetGRXSTSP_DEVICE_EPNUM() uint32 {
	return volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg) & 0xf
}
func (o *OTG_HS_Type) SetGRXSTSP_DEVICE_BCNT(value uint32) {
	volatile.StoreUint32(&o.GRXSTSP_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg)&^(0x7ff0)|value<<4)
}
func (o *OTG_HS_Type) GetGRXSTSP_DEVICE_BCNT() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg) & 0x7ff0) >> 4
}
func (o *OTG_HS_Type) SetGRXSTSP_DEVICE_DPID(value uint32) {
	volatile.StoreUint32(&o.GRXSTSP_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg)&^(0x18000)|value<<15)
}
func (o *OTG_HS_Type) GetGRXSTSP_DEVICE_DPID() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg) & 0x18000) >> 15
}
func (o *OTG_HS_Type) SetGRXSTSP_DEVICE_PKTSTS(value uint32) {
	volatile.StoreUint32(&o.GRXSTSP_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg)&^(0x1e0000)|value<<17)
}
func (o *OTG_HS_Type) GetGRXSTSP_DEVICE_PKTSTS() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg) & 0x1e0000) >> 17
}
func (o *OTG_HS_Type) SetGRXSTSP_DEVICE_FRMNUM(value uint32) {
	volatile.StoreUint32(&o.GRXSTSP_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg)&^(0x1e00000)|value<<21)
}
func (o *OTG_HS_Type) GetGRXSTSP_DEVICE_FRMNUM() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg) & 0x1e00000) >> 21
}
func (o *OTG_HS_Type) SetGRXSTSP_DEVICE_STSPHST(value uint32) {
	volatile.StoreUint32(&o.GRXSTSP_DEVICE.Reg, volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetGRXSTSP_DEVICE_STSPHST() uint32 {
	return (volatile.LoadUint32(&o.GRXSTSP_DEVICE.Reg) & 0x8000000) >> 27
}

// OTG_HS.GRXFSIZ: The application can program the RAM size that must be allocated to the Rx FIFO.
func (o *OTG_HS_Type) SetGRXFSIZ_RXFD(value uint32) {
	volatile.StoreUint32(&o.GRXFSIZ.Reg, volatile.LoadUint32(&o.GRXFSIZ.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetGRXFSIZ_RXFD() uint32 {
	return volatile.LoadUint32(&o.GRXFSIZ.Reg) & 0xffff
}

// OTG_HS.HNPTXFSIZ: Host mode
func (o *OTG_HS_Type) SetHNPTXFSIZ_NPTXFSA(value uint32) {
	volatile.StoreUint32(&o.HNPTXFSIZ.Reg, volatile.LoadUint32(&o.HNPTXFSIZ.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHNPTXFSIZ_NPTXFSA() uint32 {
	return volatile.LoadUint32(&o.HNPTXFSIZ.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetHNPTXFSIZ_NPTXFD(value uint32) {
	volatile.StoreUint32(&o.HNPTXFSIZ.Reg, volatile.LoadUint32(&o.HNPTXFSIZ.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetHNPTXFSIZ_NPTXFD() uint32 {
	return (volatile.LoadUint32(&o.HNPTXFSIZ.Reg) & 0xffff0000) >> 16
}

// OTG_HS.HNPTXSTS: In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
func (o *OTG_HS_Type) SetHNPTXSTS_NPTXFSAV(value uint32) {
	volatile.StoreUint32(&o.HNPTXSTS.Reg, volatile.LoadUint32(&o.HNPTXSTS.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHNPTXSTS_NPTXFSAV() uint32 {
	return volatile.LoadUint32(&o.HNPTXSTS.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetHNPTXSTS_NPTQXSAV(value uint32) {
	volatile.StoreUint32(&o.HNPTXSTS.Reg, volatile.LoadUint32(&o.HNPTXSTS.Reg)&^(0xff0000)|value<<16)
}
func (o *OTG_HS_Type) GetHNPTXSTS_NPTQXSAV() uint32 {
	return (volatile.LoadUint32(&o.HNPTXSTS.Reg) & 0xff0000) >> 16
}
func (o *OTG_HS_Type) SetHNPTXSTS_NPTXQTOP(value uint32) {
	volatile.StoreUint32(&o.HNPTXSTS.Reg, volatile.LoadUint32(&o.HNPTXSTS.Reg)&^(0x7f000000)|value<<24)
}
func (o *OTG_HS_Type) GetHNPTXSTS_NPTXQTOP() uint32 {
	return (volatile.LoadUint32(&o.HNPTXSTS.Reg) & 0x7f000000) >> 24
}

// OTG_HS.GCCFG: OTG general core configuration register
func (o *OTG_HS_Type) SetGCCFG_DCDET(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetGCCFG_DCDET() uint32 {
	return volatile.LoadUint32(&o.GCCFG.Reg) & 0x1
}
func (o *OTG_HS_Type) SetGCCFG_PDET(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetGCCFG_PDET() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetGCCFG_SDET(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetGCCFG_SDET() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetGCCFG_PS2DET(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetGCCFG_PS2DET() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetGCCFG_PWRDWN(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetGCCFG_PWRDWN() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetGCCFG_BCDEN(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetGCCFG_BCDEN() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetGCCFG_DCDEN(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x40000)|value<<18)
}
func (o *OTG_HS_Type) GetGCCFG_DCDEN() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x40000) >> 18
}
func (o *OTG_HS_Type) SetGCCFG_PDEN(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x80000)|value<<19)
}
func (o *OTG_HS_Type) GetGCCFG_PDEN() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x80000) >> 19
}
func (o *OTG_HS_Type) SetGCCFG_SDEN(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetGCCFG_SDEN() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetGCCFG_VBDEN(value uint32) {
	volatile.StoreUint32(&o.GCCFG.Reg, volatile.LoadUint32(&o.GCCFG.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetGCCFG_VBDEN() uint32 {
	return (volatile.LoadUint32(&o.GCCFG.Reg) & 0x200000) >> 21
}

// OTG_HS.CID: This is a register containing the Product ID as reset value.
func (o *OTG_HS_Type) SetCID(value uint32) {
	volatile.StoreUint32(&o.CID.Reg, value)
}
func (o *OTG_HS_Type) GetCID() uint32 {
	return volatile.LoadUint32(&o.CID.Reg)
}

// OTG_HS.GLPMCFG: OTG core LPM configuration register
func (o *OTG_HS_Type) SetGLPMCFG_LPMEN(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetGLPMCFG_LPMEN() uint32 {
	return volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x1
}
func (o *OTG_HS_Type) SetGLPMCFG_LPMACK(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetGLPMCFG_LPMACK() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetGLPMCFG_BESL(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x3c)|value<<2)
}
func (o *OTG_HS_Type) GetGLPMCFG_BESL() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x3c) >> 2
}
func (o *OTG_HS_Type) SetGLPMCFG_REMWAKE(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetGLPMCFG_REMWAKE() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetGLPMCFG_L1SSEN(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetGLPMCFG_L1SSEN() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetGLPMCFG_BESLTHRS(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0xf00)|value<<8)
}
func (o *OTG_HS_Type) GetGLPMCFG_BESLTHRS() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0xf00) >> 8
}
func (o *OTG_HS_Type) SetGLPMCFG_L1DSEN(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetGLPMCFG_L1DSEN() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetGLPMCFG_LPMRSP(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x6000)|value<<13)
}
func (o *OTG_HS_Type) GetGLPMCFG_LPMRSP() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x6000) >> 13
}
func (o *OTG_HS_Type) SetGLPMCFG_SLPSTS(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetGLPMCFG_SLPSTS() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetGLPMCFG_L1RSMOK(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetGLPMCFG_L1RSMOK() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetGLPMCFG_LPMCHIDX(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x1e0000)|value<<17)
}
func (o *OTG_HS_Type) GetGLPMCFG_LPMCHIDX() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x1e0000) >> 17
}
func (o *OTG_HS_Type) SetGLPMCFG_LPMRCNT(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0xe00000)|value<<21)
}
func (o *OTG_HS_Type) GetGLPMCFG_LPMRCNT() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0xe00000) >> 21
}
func (o *OTG_HS_Type) SetGLPMCFG_SNDLPM(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x1000000)|value<<24)
}
func (o *OTG_HS_Type) GetGLPMCFG_SNDLPM() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x1000000) >> 24
}
func (o *OTG_HS_Type) SetGLPMCFG_LPMRCNTSTS(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0xe000000)|value<<25)
}
func (o *OTG_HS_Type) GetGLPMCFG_LPMRCNTSTS() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0xe000000) >> 25
}
func (o *OTG_HS_Type) SetGLPMCFG_ENBESL(value uint32) {
	volatile.StoreUint32(&o.GLPMCFG.Reg, volatile.LoadUint32(&o.GLPMCFG.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetGLPMCFG_ENBESL() uint32 {
	return (volatile.LoadUint32(&o.GLPMCFG.Reg) & 0x10000000) >> 28
}

// OTG_HS.HPTXFSIZ: OTG host periodic transmit FIFO size register
func (o *OTG_HS_Type) SetHPTXFSIZ_PTXSA(value uint32) {
	volatile.StoreUint32(&o.HPTXFSIZ.Reg, volatile.LoadUint32(&o.HPTXFSIZ.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHPTXFSIZ_PTXSA() uint32 {
	return volatile.LoadUint32(&o.HPTXFSIZ.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetHPTXFSIZ_PTXFSIZ(value uint32) {
	volatile.StoreUint32(&o.HPTXFSIZ.Reg, volatile.LoadUint32(&o.HPTXFSIZ.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetHPTXFSIZ_PTXFSIZ() uint32 {
	return (volatile.LoadUint32(&o.HPTXFSIZ.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF1: OTG device IN endpoint transmit FIFO 1 size register
func (o *OTG_HS_Type) SetDIEPTXF1_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF1.Reg, volatile.LoadUint32(&o.DIEPTXF1.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF1_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF1.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF1_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF1.Reg, volatile.LoadUint32(&o.DIEPTXF1.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF1_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF1.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF2: OTG device IN endpoint transmit FIFO 2 size register
func (o *OTG_HS_Type) SetDIEPTXF2_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF2.Reg, volatile.LoadUint32(&o.DIEPTXF2.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF2_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF2.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF2_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF2.Reg, volatile.LoadUint32(&o.DIEPTXF2.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF2_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF2.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF3: OTG device IN endpoint transmit FIFO 3 size register
func (o *OTG_HS_Type) SetDIEPTXF3_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF3.Reg, volatile.LoadUint32(&o.DIEPTXF3.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF3_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF3.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF3_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF3.Reg, volatile.LoadUint32(&o.DIEPTXF3.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF3_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF3.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF4: OTG device IN endpoint transmit FIFO 4 size register
func (o *OTG_HS_Type) SetDIEPTXF4_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF4.Reg, volatile.LoadUint32(&o.DIEPTXF4.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF4_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF4.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF4_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF4.Reg, volatile.LoadUint32(&o.DIEPTXF4.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF4_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF4.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF5: OTG device IN endpoint transmit FIFO 5 size register
func (o *OTG_HS_Type) SetDIEPTXF5_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF5.Reg, volatile.LoadUint32(&o.DIEPTXF5.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF5_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF5.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF5_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF5.Reg, volatile.LoadUint32(&o.DIEPTXF5.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF5_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF5.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF6: OTG device IN endpoint transmit FIFO 6 size register
func (o *OTG_HS_Type) SetDIEPTXF6_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF6.Reg, volatile.LoadUint32(&o.DIEPTXF6.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF6_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF6.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF6_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF6.Reg, volatile.LoadUint32(&o.DIEPTXF6.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF6_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF6.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF7: OTG device IN endpoint transmit FIFO 7 size register
func (o *OTG_HS_Type) SetDIEPTXF7_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF7.Reg, volatile.LoadUint32(&o.DIEPTXF7.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF7_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF7.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF7_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF7.Reg, volatile.LoadUint32(&o.DIEPTXF7.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF7_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF7.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DIEPTXF8: OTG device IN endpoint transmit FIFO 8 size register
func (o *OTG_HS_Type) SetDIEPTXF8_INEPTXSA(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF8.Reg, volatile.LoadUint32(&o.DIEPTXF8.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTXF8_INEPTXSA() uint32 {
	return volatile.LoadUint32(&o.DIEPTXF8.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDIEPTXF8_INEPTXFD(value uint32) {
	volatile.StoreUint32(&o.DIEPTXF8.Reg, volatile.LoadUint32(&o.DIEPTXF8.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPTXF8_INEPTXFD() uint32 {
	return (volatile.LoadUint32(&o.DIEPTXF8.Reg) & 0xffff0000) >> 16
}

// OTG_HS.HCFG: This register configures the core after power-on. Do not make changes to this register after initializing the host.
func (o *OTG_HS_Type) SetHCFG_FSLSPCS(value uint32) {
	volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x3)|value)
}
func (o *OTG_HS_Type) GetHCFG_FSLSPCS() uint32 {
	return volatile.LoadUint32(&o.HCFG.Reg) & 0x3
}
func (o *OTG_HS_Type) SetHCFG_FSLSS(value uint32) {
	volatile.StoreUint32(&o.HCFG.Reg, volatile.LoadUint32(&o.HCFG.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetHCFG_FSLSS() uint32 {
	return (volatile.LoadUint32(&o.HCFG.Reg) & 0x4) >> 2
}

// OTG_HS.HFIR: This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
func (o *OTG_HS_Type) SetHFIR_FRIVL(value uint32) {
	volatile.StoreUint32(&o.HFIR.Reg, volatile.LoadUint32(&o.HFIR.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHFIR_FRIVL() uint32 {
	return volatile.LoadUint32(&o.HFIR.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetHFIR_RLDCTRL(value uint32) {
	volatile.StoreUint32(&o.HFIR.Reg, volatile.LoadUint32(&o.HFIR.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHFIR_RLDCTRL() uint32 {
	return (volatile.LoadUint32(&o.HFIR.Reg) & 0x10000) >> 16
}

// OTG_HS.HFNUM: This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
func (o *OTG_HS_Type) SetHFNUM_FRNUM(value uint32) {
	volatile.StoreUint32(&o.HFNUM.Reg, volatile.LoadUint32(&o.HFNUM.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHFNUM_FRNUM() uint32 {
	return volatile.LoadUint32(&o.HFNUM.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetHFNUM_FTREM(value uint32) {
	volatile.StoreUint32(&o.HFNUM.Reg, volatile.LoadUint32(&o.HFNUM.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetHFNUM_FTREM() uint32 {
	return (volatile.LoadUint32(&o.HFNUM.Reg) & 0xffff0000) >> 16
}

// OTG_HS.HPTXSTS: This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
func (o *OTG_HS_Type) SetHPTXSTS_PTXFSAVL(value uint32) {
	volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHPTXSTS_PTXFSAVL() uint32 {
	return volatile.LoadUint32(&o.HPTXSTS.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetHPTXSTS_PTXQSAV(value uint32) {
	volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0xff0000)|value<<16)
}
func (o *OTG_HS_Type) GetHPTXSTS_PTXQSAV() uint32 {
	return (volatile.LoadUint32(&o.HPTXSTS.Reg) & 0xff0000) >> 16
}
func (o *OTG_HS_Type) SetHPTXSTS_PTXQTOP(value uint32) {
	volatile.StoreUint32(&o.HPTXSTS.Reg, volatile.LoadUint32(&o.HPTXSTS.Reg)&^(0xff000000)|value<<24)
}
func (o *OTG_HS_Type) GetHPTXSTS_PTXQTOP() uint32 {
	return (volatile.LoadUint32(&o.HPTXSTS.Reg) & 0xff000000) >> 24
}

// OTG_HS.HAINT: When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
func (o *OTG_HS_Type) SetHAINT(value uint32) {
	volatile.StoreUint32(&o.HAINT.Reg, volatile.LoadUint32(&o.HAINT.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHAINT() uint32 {
	return volatile.LoadUint32(&o.HAINT.Reg) & 0xffff
}

// OTG_HS.HAINTMSK: The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
func (o *OTG_HS_Type) SetHAINTMSK_HAINTM(value uint32) {
	volatile.StoreUint32(&o.HAINTMSK.Reg, volatile.LoadUint32(&o.HAINTMSK.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetHAINTMSK_HAINTM() uint32 {
	return volatile.LoadUint32(&o.HAINTMSK.Reg) & 0xffff
}

// OTG_HS.HPRT: This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
func (o *OTG_HS_Type) SetHPRT_PCSTS(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHPRT_PCSTS() uint32 {
	return volatile.LoadUint32(&o.HPRT.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHPRT_PCDET(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHPRT_PCDET() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHPRT_PENA(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetHPRT_PENA() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetHPRT_PENCHNG(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHPRT_PENCHNG() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHPRT_POCA(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHPRT_POCA() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHPRT_POCCHNG(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHPRT_POCCHNG() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHPRT_PRES(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetHPRT_PRES() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetHPRT_PSUSP(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHPRT_PSUSP() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHPRT_PRST(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHPRT_PRST() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHPRT_PLSTS(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0xc00)|value<<10)
}
func (o *OTG_HS_Type) GetHPRT_PLSTS() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0xc00) >> 10
}
func (o *OTG_HS_Type) SetHPRT_PPWR(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetHPRT_PPWR() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetHPRT_PTCTL(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x1e000)|value<<13)
}
func (o *OTG_HS_Type) GetHPRT_PTCTL() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x1e000) >> 13
}
func (o *OTG_HS_Type) SetHPRT_PSPD(value uint32) {
	volatile.StoreUint32(&o.HPRT.Reg, volatile.LoadUint32(&o.HPRT.Reg)&^(0x60000)|value<<17)
}
func (o *OTG_HS_Type) GetHPRT_PSPD() uint32 {
	return (volatile.LoadUint32(&o.HPRT.Reg) & 0x60000) >> 17
}

// OTG_HS.HCCHAR0: OTG host channel 0 characteristics register
func (o *OTG_HS_Type) SetHCCHAR0_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR0_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR0_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR0_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR0_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR0_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR0_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR0_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR0_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR0_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR0_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR0_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR0_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR0_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR0_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR0_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR0_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR0_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR0_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR0.Reg, volatile.LoadUint32(&o.HCCHAR0.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR0_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR0.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT0: OTG host channel 0 split control register
func (o *OTG_HS_Type) SetHCSPLT0_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT0.Reg, volatile.LoadUint32(&o.HCSPLT0.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT0_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT0.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT0_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT0.Reg, volatile.LoadUint32(&o.HCSPLT0.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT0_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT0.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT0_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT0.Reg, volatile.LoadUint32(&o.HCSPLT0.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT0_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT0.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT0_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT0.Reg, volatile.LoadUint32(&o.HCSPLT0.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT0_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT0.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT0_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT0.Reg, volatile.LoadUint32(&o.HCSPLT0.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT0_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT0.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT0: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT0_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT0_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT0.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT0_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT0_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT0_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT0_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT0_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT0_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT0_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT0_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT0_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT0_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT0_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT0_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT0_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT0_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT0_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT0.Reg, volatile.LoadUint32(&o.HCINT0.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT0_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT0.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK0: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK0_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK0_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK0_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK0_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK0_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK0_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK0_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK0_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK0_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK0_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK0_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK0_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK0_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK0_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK0_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK0_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK0_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK0.Reg, volatile.LoadUint32(&o.HCINTMSK0.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK0_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK0.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ0: OTG host channel 0 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ0_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ0_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ0_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ0_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ0_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ0_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ0_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ0.Reg, volatile.LoadUint32(&o.HCTSIZ0.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ0_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ0.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA0: OTG host channel 0 DMA address register
func (o *OTG_HS_Type) SetHCDMA0(value uint32) {
	volatile.StoreUint32(&o.HCDMA0.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA0() uint32 {
	return volatile.LoadUint32(&o.HCDMA0.Reg)
}

// OTG_HS.HCCHAR1: OTG host channel 1 characteristics register
func (o *OTG_HS_Type) SetHCCHAR1_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR1_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR1_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR1_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR1_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR1_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR1_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR1_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR1_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR1_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR1_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR1_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR1_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR1_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR1_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR1_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR1_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR1_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR1_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR1.Reg, volatile.LoadUint32(&o.HCCHAR1.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR1_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR1.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT1: OTG host channel 1 split control register
func (o *OTG_HS_Type) SetHCSPLT1_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT1.Reg, volatile.LoadUint32(&o.HCSPLT1.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT1_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT1.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT1_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT1.Reg, volatile.LoadUint32(&o.HCSPLT1.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT1_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT1.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT1_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT1.Reg, volatile.LoadUint32(&o.HCSPLT1.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT1_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT1.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT1_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT1.Reg, volatile.LoadUint32(&o.HCSPLT1.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT1_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT1.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT1_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT1.Reg, volatile.LoadUint32(&o.HCSPLT1.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT1_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT1.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT1_DEVICE: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT1_DEVICE_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT1_DEVICE_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT1_DEVICE.Reg, volatile.LoadUint32(&o.HCINT1_DEVICE.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT1_DEVICE_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT1_DEVICE.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK1: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK1_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK1_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK1_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK1_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK1_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK1_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK1_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK1_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK1_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK1_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK1_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK1_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK1_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK1_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK1_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK1_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK1_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK1.Reg, volatile.LoadUint32(&o.HCINTMSK1.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK1_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK1.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ1: OTG host channel 1 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ1_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ1_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ1_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ1_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ1_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ1_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ1_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ1.Reg, volatile.LoadUint32(&o.HCTSIZ1.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ1_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ1.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA1: OTG host channel 1 DMA address register
func (o *OTG_HS_Type) SetHCDMA1(value uint32) {
	volatile.StoreUint32(&o.HCDMA1.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA1() uint32 {
	return volatile.LoadUint32(&o.HCDMA1.Reg)
}

// OTG_HS.HCCHAR2: OTG host channel 2 characteristics register
func (o *OTG_HS_Type) SetHCCHAR2_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR2_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR2_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR2_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR2_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR2_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR2_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR2_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR2_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR2_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR2_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR2_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR2_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR2_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR2_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR2_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR2_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR2_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR2_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR2.Reg, volatile.LoadUint32(&o.HCCHAR2.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR2_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR2.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT2: OTG host channel 2 split control register
func (o *OTG_HS_Type) SetHCSPLT2_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT2.Reg, volatile.LoadUint32(&o.HCSPLT2.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT2_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT2.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT2_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT2.Reg, volatile.LoadUint32(&o.HCSPLT2.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT2_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT2.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT2_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT2.Reg, volatile.LoadUint32(&o.HCSPLT2.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT2_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT2.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT2_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT2.Reg, volatile.LoadUint32(&o.HCSPLT2.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT2_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT2.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT2_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT2.Reg, volatile.LoadUint32(&o.HCSPLT2.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT2_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT2.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT2: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT2_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT2_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT2.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT2_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT2_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT2_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT2_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT2_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT2_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT2_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT2_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT2_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT2_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT2_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT2_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT2_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT2_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT2_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT2.Reg, volatile.LoadUint32(&o.HCINT2.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT2_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT2.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK2: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK2_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK2_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK2_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK2_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK2_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK2_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK2_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK2_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK2_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK2_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK2_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK2_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK2_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK2_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK2_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK2_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK2_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK2.Reg, volatile.LoadUint32(&o.HCINTMSK2.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK2_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK2.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ2: OTG host channel 2 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ2_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ2_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ2_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ2_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ2_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ2_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ2_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ2.Reg, volatile.LoadUint32(&o.HCTSIZ2.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ2_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ2.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA2: OTG host channel 2 DMA address register
func (o *OTG_HS_Type) SetHCDMA2(value uint32) {
	volatile.StoreUint32(&o.HCDMA2.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA2() uint32 {
	return volatile.LoadUint32(&o.HCDMA2.Reg)
}

// OTG_HS.HCCHAR3: OTG host channel 3 characteristics register
func (o *OTG_HS_Type) SetHCCHAR3_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR3_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR3_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR3_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR3_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR3_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR3_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR3_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR3_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR3_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR3_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR3_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR3_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR3_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR3_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR3_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR3_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR3_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR3_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR3.Reg, volatile.LoadUint32(&o.HCCHAR3.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR3_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR3.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT3: OTG host channel 3 split control register
func (o *OTG_HS_Type) SetHCSPLT3_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT3.Reg, volatile.LoadUint32(&o.HCSPLT3.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT3_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT3.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT3_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT3.Reg, volatile.LoadUint32(&o.HCSPLT3.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT3_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT3.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT3_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT3.Reg, volatile.LoadUint32(&o.HCSPLT3.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT3_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT3.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT3_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT3.Reg, volatile.LoadUint32(&o.HCSPLT3.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT3_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT3.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT3_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT3.Reg, volatile.LoadUint32(&o.HCSPLT3.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT3_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT3.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT3: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT3_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT3_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT3.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT3_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT3_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT3_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT3_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT3_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT3_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT3_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT3_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT3_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT3_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT3_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT3_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT3_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT3_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT3_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT3.Reg, volatile.LoadUint32(&o.HCINT3.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT3_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT3.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK3: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK3_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK3_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK3_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK3_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK3_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK3_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK3_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK3_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK3_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK3_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK3_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK3_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK3_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK3_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK3_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK3_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK3_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK3.Reg, volatile.LoadUint32(&o.HCINTMSK3.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK3_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK3.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ3: OTG host channel 3 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ3_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ3_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ3_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ3_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ3_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ3_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ3_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ3.Reg, volatile.LoadUint32(&o.HCTSIZ3.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ3_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ3.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA3: OTG host channel 3 DMA address register
func (o *OTG_HS_Type) SetHCDMA3(value uint32) {
	volatile.StoreUint32(&o.HCDMA3.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA3() uint32 {
	return volatile.LoadUint32(&o.HCDMA3.Reg)
}

// OTG_HS.HCCHAR4: OTG host channel 4 characteristics register
func (o *OTG_HS_Type) SetHCCHAR4_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR4_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR4_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR4_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR4_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR4_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR4_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR4_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR4_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR4_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR4_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR4_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR4_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR4_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR4_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR4_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR4_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR4_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR4_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR4.Reg, volatile.LoadUint32(&o.HCCHAR4.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR4_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR4.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT4: OTG host channel 4 split control register
func (o *OTG_HS_Type) SetHCSPLT4_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT4.Reg, volatile.LoadUint32(&o.HCSPLT4.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT4_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT4.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT4_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT4.Reg, volatile.LoadUint32(&o.HCSPLT4.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT4_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT4.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT4_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT4.Reg, volatile.LoadUint32(&o.HCSPLT4.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT4_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT4.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT4_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT4.Reg, volatile.LoadUint32(&o.HCSPLT4.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT4_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT4.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT4_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT4.Reg, volatile.LoadUint32(&o.HCSPLT4.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT4_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT4.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT4: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT4_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT4_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT4.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT4_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT4_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT4_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT4_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT4_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT4_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT4_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT4_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT4_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT4_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT4_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT4_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT4_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT4_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT4_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT4.Reg, volatile.LoadUint32(&o.HCINT4.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT4_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT4.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK4: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK4_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK4_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK4_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK4_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK4_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK4_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK4_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK4_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK4_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK4_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK4_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK4_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK4_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK4_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK4_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK4_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK4_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK4.Reg, volatile.LoadUint32(&o.HCINTMSK4.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK4_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK4.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ4: OTG host channel 4 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ4_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ4_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ4_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ4_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ4_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ4_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ4_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ4.Reg, volatile.LoadUint32(&o.HCTSIZ4.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ4_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ4.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA4: OTG host channel 4 DMA address register
func (o *OTG_HS_Type) SetHCDMA4(value uint32) {
	volatile.StoreUint32(&o.HCDMA4.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA4() uint32 {
	return volatile.LoadUint32(&o.HCDMA4.Reg)
}

// OTG_HS.HCCHAR5: OTG host channel 5 characteristics register
func (o *OTG_HS_Type) SetHCCHAR5_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR5_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR5_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR5_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR5_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR5_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR5_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR5_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR5_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR5_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR5_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR5_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR5_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR5_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR5_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR5_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR5_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR5_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR5_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR5.Reg, volatile.LoadUint32(&o.HCCHAR5.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR5_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR5.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT5: OTG host channel 5 split control register
func (o *OTG_HS_Type) SetHCSPLT5_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT5.Reg, volatile.LoadUint32(&o.HCSPLT5.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT5_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT5.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT5_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT5.Reg, volatile.LoadUint32(&o.HCSPLT5.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT5_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT5.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT5_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT5.Reg, volatile.LoadUint32(&o.HCSPLT5.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT5_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT5.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT5_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT5.Reg, volatile.LoadUint32(&o.HCSPLT5.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT5_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT5.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT5_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT5.Reg, volatile.LoadUint32(&o.HCSPLT5.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT5_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT5.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT5: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT5_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT5_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT5.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT5_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT5_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT5_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT5_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT5_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT5_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT5_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT5_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT5_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT5_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT5_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT5_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT5_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT5_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT5_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT5.Reg, volatile.LoadUint32(&o.HCINT5.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT5_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT5.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK5: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK5_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK5_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK5_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK5_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK5_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK5_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK5_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK5_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK5_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK5_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK5_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK5_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK5_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK5_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK5_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK5_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK5_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK5.Reg, volatile.LoadUint32(&o.HCINTMSK5.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK5_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK5.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ5: OTG host channel 5 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ5_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ5_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ5_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ5_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ5_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ5_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ5_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ5.Reg, volatile.LoadUint32(&o.HCTSIZ5.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ5_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ5.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA5: OTG host channel 5 DMA address register
func (o *OTG_HS_Type) SetHCDMA5(value uint32) {
	volatile.StoreUint32(&o.HCDMA5.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA5() uint32 {
	return volatile.LoadUint32(&o.HCDMA5.Reg)
}

// OTG_HS.HCCHAR6: OTG host channel 6 characteristics register
func (o *OTG_HS_Type) SetHCCHAR6_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR6_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR6_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR6_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR6_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR6_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR6_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR6_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR6_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR6_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR6_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR6_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR6_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR6_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR6_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR6_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR6_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR6_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR6_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR6.Reg, volatile.LoadUint32(&o.HCCHAR6.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR6_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR6.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT6: OTG host channel 6 split control register
func (o *OTG_HS_Type) SetHCSPLT6_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT6.Reg, volatile.LoadUint32(&o.HCSPLT6.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT6_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT6.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT6_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT6.Reg, volatile.LoadUint32(&o.HCSPLT6.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT6_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT6.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT6_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT6.Reg, volatile.LoadUint32(&o.HCSPLT6.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT6_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT6.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT6_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT6.Reg, volatile.LoadUint32(&o.HCSPLT6.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT6_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT6.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT6_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT6.Reg, volatile.LoadUint32(&o.HCSPLT6.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT6_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT6.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT6: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT6_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT6_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT6.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT6_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT6_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT6_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT6_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT6_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT6_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT6_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT6_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT6_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT6_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT6_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT6_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT6_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT6_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT6_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT6.Reg, volatile.LoadUint32(&o.HCINT6.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT6_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT6.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK6: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK6_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK6_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK6_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK6_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK6_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK6_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK6_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK6_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK6_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK6_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK6_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK6_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK6_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK6_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK6_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK6_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK6_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK6.Reg, volatile.LoadUint32(&o.HCINTMSK6.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK6_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK6.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ6: OTG host channel 6 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ6_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ6_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ6_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ6_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ6_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ6_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ6_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ6.Reg, volatile.LoadUint32(&o.HCTSIZ6.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ6_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ6.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA6: OTG host channel 6 DMA address register
func (o *OTG_HS_Type) SetHCDMA6(value uint32) {
	volatile.StoreUint32(&o.HCDMA6.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA6() uint32 {
	return volatile.LoadUint32(&o.HCDMA6.Reg)
}

// OTG_HS.HCCHAR7: OTG host channel 7 characteristics register
func (o *OTG_HS_Type) SetHCCHAR7_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR7_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR7_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR7_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR7_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR7_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR7_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR7_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR7_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR7_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR7_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR7_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR7_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR7_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR7_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR7_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR7_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR7_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR7_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR7.Reg, volatile.LoadUint32(&o.HCCHAR7.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR7_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR7.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT7: OTG host channel 7 split control register
func (o *OTG_HS_Type) SetHCSPLT7_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT7.Reg, volatile.LoadUint32(&o.HCSPLT7.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT7_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT7.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT7_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT7.Reg, volatile.LoadUint32(&o.HCSPLT7.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT7_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT7.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT7_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT7.Reg, volatile.LoadUint32(&o.HCSPLT7.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT7_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT7.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT7_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT7.Reg, volatile.LoadUint32(&o.HCSPLT7.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT7_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT7.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT7_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT7.Reg, volatile.LoadUint32(&o.HCSPLT7.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT7_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT7.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT7: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT7_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT7_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT7.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT7_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT7_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT7_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT7_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT7_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT7_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT7_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT7_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT7_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT7_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT7_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT7_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT7_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT7_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT7_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT7.Reg, volatile.LoadUint32(&o.HCINT7.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT7_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT7.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK7: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK7_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK7_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK7_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK7_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK7_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK7_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK7_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK7_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK7_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK7_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK7_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK7_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK7_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK7_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK7_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK7_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK7_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK7.Reg, volatile.LoadUint32(&o.HCINTMSK7.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK7_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK7.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ7: OTG host channel 7 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ7_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ7_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ7_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ7_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ7_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ7_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ7_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ7.Reg, volatile.LoadUint32(&o.HCTSIZ7.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ7_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ7.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA7: OTG host channel 7 DMA address register
func (o *OTG_HS_Type) SetHCDMA7(value uint32) {
	volatile.StoreUint32(&o.HCDMA7.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA7() uint32 {
	return volatile.LoadUint32(&o.HCDMA7.Reg)
}

// OTG_HS.HCCHAR8: OTG host channel 8 characteristics register
func (o *OTG_HS_Type) SetHCCHAR8_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR8_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR8_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR8_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR8_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR8_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR8_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR8_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR8_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR8_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR8_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR8_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR8_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR8_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR8_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR8_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR8_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR8_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR8_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR8.Reg, volatile.LoadUint32(&o.HCCHAR8.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR8_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR8.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT8: OTG host channel 8 split control register
func (o *OTG_HS_Type) SetHCSPLT8_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT8.Reg, volatile.LoadUint32(&o.HCSPLT8.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT8_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT8.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT8_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT8.Reg, volatile.LoadUint32(&o.HCSPLT8.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT8_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT8.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT8_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT8.Reg, volatile.LoadUint32(&o.HCSPLT8.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT8_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT8.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT8_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT8.Reg, volatile.LoadUint32(&o.HCSPLT8.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT8_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT8.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT8_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT8.Reg, volatile.LoadUint32(&o.HCSPLT8.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT8_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT8.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT8: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT8_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT8_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT8.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT8_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT8_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT8_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT8_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT8_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT8_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT8_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT8_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT8_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT8_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT8_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT8_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT8_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT8_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT8_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT8.Reg, volatile.LoadUint32(&o.HCINT8.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT8_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT8.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK8: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK8_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK8_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK8_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK8_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK8_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK8_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK8_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK8_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK8_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK8_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK8_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK8_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK8_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK8_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK8_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK8_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK8_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK8.Reg, volatile.LoadUint32(&o.HCINTMSK8.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK8_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK8.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ8: OTG host channel 8 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ8_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ8.Reg, volatile.LoadUint32(&o.HCTSIZ8.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ8_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ8.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ8_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ8.Reg, volatile.LoadUint32(&o.HCTSIZ8.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ8_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ8.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ8_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ8.Reg, volatile.LoadUint32(&o.HCTSIZ8.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ8_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ8.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ8_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ8.Reg, volatile.LoadUint32(&o.HCTSIZ8.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ8_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ8.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA8: OTG host channel 8 DMA address register
func (o *OTG_HS_Type) SetHCDMA8(value uint32) {
	volatile.StoreUint32(&o.HCDMA8.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA8() uint32 {
	return volatile.LoadUint32(&o.HCDMA8.Reg)
}

// OTG_HS.HCCHAR9: OTG host channel 9 characteristics register
func (o *OTG_HS_Type) SetHCCHAR9_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR9_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR9_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR9_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR9_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR9_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR9_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR9_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR9_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR9_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR9_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR9_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR9_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR9_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR9_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR9_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR9_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR9_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR9_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR9.Reg, volatile.LoadUint32(&o.HCCHAR9.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR9_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR9.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT9: OTG host channel 9 split control register
func (o *OTG_HS_Type) SetHCSPLT9_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT9.Reg, volatile.LoadUint32(&o.HCSPLT9.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT9_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT9.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT9_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT9.Reg, volatile.LoadUint32(&o.HCSPLT9.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT9_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT9.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT9_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT9.Reg, volatile.LoadUint32(&o.HCSPLT9.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT9_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT9.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT9_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT9.Reg, volatile.LoadUint32(&o.HCSPLT9.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT9_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT9.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT9_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT9.Reg, volatile.LoadUint32(&o.HCSPLT9.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT9_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT9.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT9: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT9_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT9_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT9.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT9_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT9_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT9_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT9_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT9_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT9_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT9_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT9_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT9_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT9_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT9_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT9_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT9_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT9_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT9_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT9.Reg, volatile.LoadUint32(&o.HCINT9.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT9_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT9.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK9: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK9_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK9_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK9_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK9_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK9_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK9_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK9_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK9_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK9_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK9_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK9_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK9_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK9_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK9_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK9_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK9_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK9_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK9.Reg, volatile.LoadUint32(&o.HCINTMSK9.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK9_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK9.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ9: OTG host channel 9 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ9_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ9.Reg, volatile.LoadUint32(&o.HCTSIZ9.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ9_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ9.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ9_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ9.Reg, volatile.LoadUint32(&o.HCTSIZ9.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ9_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ9.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ9_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ9.Reg, volatile.LoadUint32(&o.HCTSIZ9.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ9_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ9.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ9_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ9.Reg, volatile.LoadUint32(&o.HCTSIZ9.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ9_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ9.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA9: OTG host channel 9 DMA address register
func (o *OTG_HS_Type) SetHCDMA9(value uint32) {
	volatile.StoreUint32(&o.HCDMA9.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA9() uint32 {
	return volatile.LoadUint32(&o.HCDMA9.Reg)
}

// OTG_HS.HCCHAR10: OTG host channel 10 characteristics register
func (o *OTG_HS_Type) SetHCCHAR10_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR10_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR10_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR10_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR10_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR10_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR10_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR10_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR10_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR10_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR10_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR10_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR10_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR10_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR10_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR10_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR10_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR10_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR10_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR10.Reg, volatile.LoadUint32(&o.HCCHAR10.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR10_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR10.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT10: OTG host channel 10 split control register
func (o *OTG_HS_Type) SetHCSPLT10_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT10.Reg, volatile.LoadUint32(&o.HCSPLT10.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT10_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT10.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT10_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT10.Reg, volatile.LoadUint32(&o.HCSPLT10.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT10_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT10.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT10_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT10.Reg, volatile.LoadUint32(&o.HCSPLT10.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT10_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT10.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT10_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT10.Reg, volatile.LoadUint32(&o.HCSPLT10.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT10_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT10.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT10_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT10.Reg, volatile.LoadUint32(&o.HCSPLT10.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT10_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT10.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT10: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT10_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT10_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT10.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT10_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT10_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT10_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT10_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT10_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT10_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT10_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT10_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT10_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT10_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT10_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT10_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT10_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT10_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT10_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT10.Reg, volatile.LoadUint32(&o.HCINT10.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT10_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT10.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK10: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK10_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK10_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK10_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK10_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK10_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK10_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK10_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK10_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK10_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK10_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK10_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK10_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK10_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK10_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK10_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK10_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK10_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK10.Reg, volatile.LoadUint32(&o.HCINTMSK10.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK10_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK10.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ10: OTG host channel 10 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ10_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ10.Reg, volatile.LoadUint32(&o.HCTSIZ10.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ10_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ10.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ10_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ10.Reg, volatile.LoadUint32(&o.HCTSIZ10.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ10_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ10.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ10_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ10.Reg, volatile.LoadUint32(&o.HCTSIZ10.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ10_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ10.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ10_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ10.Reg, volatile.LoadUint32(&o.HCTSIZ10.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ10_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ10.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA10: OTG host channel 10 DMA address register
func (o *OTG_HS_Type) SetHCDMA10(value uint32) {
	volatile.StoreUint32(&o.HCDMA10.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA10() uint32 {
	return volatile.LoadUint32(&o.HCDMA10.Reg)
}

// OTG_HS.HCCHAR11: OTG host channel 11 characteristics register
func (o *OTG_HS_Type) SetHCCHAR11_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR11_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR11_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR11_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR11_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR11_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR11_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR11_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR11_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR11_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR11_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR11_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR11_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR11_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR11_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR11_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR11_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR11_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR11_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR11.Reg, volatile.LoadUint32(&o.HCCHAR11.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR11_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR11.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT11: OTG host channel 11 split control register
func (o *OTG_HS_Type) SetHCSPLT11_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT11.Reg, volatile.LoadUint32(&o.HCSPLT11.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT11_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT11.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT11_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT11.Reg, volatile.LoadUint32(&o.HCSPLT11.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT11_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT11.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT11_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT11.Reg, volatile.LoadUint32(&o.HCSPLT11.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT11_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT11.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT11_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT11.Reg, volatile.LoadUint32(&o.HCSPLT11.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT11_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT11.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT11_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT11.Reg, volatile.LoadUint32(&o.HCSPLT11.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT11_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT11.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT11: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT11_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT11_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT11.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT11_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT11_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT11_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT11_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT11_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT11_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT11_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT11_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT11_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT11_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT11_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT11_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT11_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT11_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT11_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT11.Reg, volatile.LoadUint32(&o.HCINT11.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT11_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT11.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK11: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK11_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK11_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK11_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK11_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK11_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK11_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK11_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK11_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK11_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK11_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK11_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK11_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK11_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK11_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK11_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK11_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK11_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK11.Reg, volatile.LoadUint32(&o.HCINTMSK11.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK11_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK11.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ11: OTG host channel 11 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ11_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ11.Reg, volatile.LoadUint32(&o.HCTSIZ11.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ11_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ11.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ11_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ11.Reg, volatile.LoadUint32(&o.HCTSIZ11.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ11_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ11.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ11_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ11.Reg, volatile.LoadUint32(&o.HCTSIZ11.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ11_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ11.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ11_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ11.Reg, volatile.LoadUint32(&o.HCTSIZ11.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ11_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ11.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA11: OTG host channel 11 DMA address register
func (o *OTG_HS_Type) SetHCDMA11(value uint32) {
	volatile.StoreUint32(&o.HCDMA11.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA11() uint32 {
	return volatile.LoadUint32(&o.HCDMA11.Reg)
}

// OTG_HS.HCCHAR12: OTG host channel 12 characteristics register
func (o *OTG_HS_Type) SetHCCHAR12_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR12_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR12_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR12_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR12_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR12_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR12_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR12_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR12_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR12_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR12_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR12_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR12_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR12_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR12_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR12_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR12_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR12_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR12_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR12.Reg, volatile.LoadUint32(&o.HCCHAR12.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR12_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR12.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT12: OTG host channel 0 split control register
func (o *OTG_HS_Type) SetHCSPLT12_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT12.Reg, volatile.LoadUint32(&o.HCSPLT12.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT12_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT12.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT12_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT12.Reg, volatile.LoadUint32(&o.HCSPLT12.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT12_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT12.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT12_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT12.Reg, volatile.LoadUint32(&o.HCSPLT12.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT12_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT12.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT12_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT12.Reg, volatile.LoadUint32(&o.HCSPLT12.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT12_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT12.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT12_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT12.Reg, volatile.LoadUint32(&o.HCSPLT12.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT12_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT12.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT12: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT12_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT12_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT12.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT12_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT12_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT12_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT12_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT12_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT12_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT12_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT12_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT12_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT12_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT12_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT12_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT12_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT12_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT12_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT12.Reg, volatile.LoadUint32(&o.HCINT12.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT12_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT12.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK12: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK12_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK12_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK12_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK12_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK12_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK12_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK12_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK12_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK12_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK12_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK12_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK12_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK12_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK12_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK12_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK12_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK12_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK12.Reg, volatile.LoadUint32(&o.HCINTMSK12.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK12_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK12.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ12: OTG host channel 12 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ12_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ12.Reg, volatile.LoadUint32(&o.HCTSIZ12.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ12_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ12.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ12_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ12.Reg, volatile.LoadUint32(&o.HCTSIZ12.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ12_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ12.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ12_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ12.Reg, volatile.LoadUint32(&o.HCTSIZ12.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ12_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ12.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ12_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ12.Reg, volatile.LoadUint32(&o.HCTSIZ12.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ12_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ12.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA12: OTG host channel 12 DMA address register
func (o *OTG_HS_Type) SetHCDMA12(value uint32) {
	volatile.StoreUint32(&o.HCDMA12.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA12() uint32 {
	return volatile.LoadUint32(&o.HCDMA12.Reg)
}

// OTG_HS.HCCHAR13: OTG host channel 13 characteristics register
func (o *OTG_HS_Type) SetHCCHAR13_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR13_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR13_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR13_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR13_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR13_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR13_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR13_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR13_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR13_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR13_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR13_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR13_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR13_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR13_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR13_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR13_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR13_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR13_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR13.Reg, volatile.LoadUint32(&o.HCCHAR13.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR13_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR13.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT13: OTG host channel 13 split control register
func (o *OTG_HS_Type) SetHCSPLT13_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT13.Reg, volatile.LoadUint32(&o.HCSPLT13.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT13_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT13.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT13_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT13.Reg, volatile.LoadUint32(&o.HCSPLT13.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT13_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT13.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT13_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT13.Reg, volatile.LoadUint32(&o.HCSPLT13.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT13_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT13.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT13_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT13.Reg, volatile.LoadUint32(&o.HCSPLT13.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT13_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT13.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT13_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT13.Reg, volatile.LoadUint32(&o.HCSPLT13.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT13_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT13.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT13: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT13_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT13_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT13.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT13_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT13_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT13_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT13_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT13_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT13_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT13_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT13_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT13_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT13_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT13_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT13_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT13_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT13_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT13_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT13.Reg, volatile.LoadUint32(&o.HCINT13.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT13_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT13.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK13: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK13_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK13_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK13_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK13_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK13_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK13_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK13_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK13_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK13_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK13_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK13_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK13_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK13_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK13_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK13_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK13_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK13_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK13.Reg, volatile.LoadUint32(&o.HCINTMSK13.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK13_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK13.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ13: OTG host channel 13 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ13_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ13.Reg, volatile.LoadUint32(&o.HCTSIZ13.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ13_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ13.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ13_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ13.Reg, volatile.LoadUint32(&o.HCTSIZ13.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ13_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ13.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ13_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ13.Reg, volatile.LoadUint32(&o.HCTSIZ13.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ13_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ13.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ13_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ13.Reg, volatile.LoadUint32(&o.HCTSIZ13.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ13_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ13.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA13: OTG host channel 13 DMA address register
func (o *OTG_HS_Type) SetHCDMA13(value uint32) {
	volatile.StoreUint32(&o.HCDMA13.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA13() uint32 {
	return volatile.LoadUint32(&o.HCDMA13.Reg)
}

// OTG_HS.HCCHAR14: OTG host channel 14 characteristics register
func (o *OTG_HS_Type) SetHCCHAR14_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR14_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR14_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR14_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR14_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR14_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR14_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR14_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR14_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR14_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR14_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR14_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR14_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR14_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR14_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR14_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR14_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR14_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR14_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR14.Reg, volatile.LoadUint32(&o.HCCHAR14.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR14_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR14.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT14: OTG host channel 14 split control register
func (o *OTG_HS_Type) SetHCSPLT14_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT14.Reg, volatile.LoadUint32(&o.HCSPLT14.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT14_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT14.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT14_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT14.Reg, volatile.LoadUint32(&o.HCSPLT14.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT14_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT14.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT14_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT14.Reg, volatile.LoadUint32(&o.HCSPLT14.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT14_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT14.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT14_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT14.Reg, volatile.LoadUint32(&o.HCSPLT14.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT14_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT14.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT14_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT14.Reg, volatile.LoadUint32(&o.HCSPLT14.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT14_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT14.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT14: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT14_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT14_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT14.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT14_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT14_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT14_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT14_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT14_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT14_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT14_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT14_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT14_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT14_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT14_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT14_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT14_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT14_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT14_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT14.Reg, volatile.LoadUint32(&o.HCINT14.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT14_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT14.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK14: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK14_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK14_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK14_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK14_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK14_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK14_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK14_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK14_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK14_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK14_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK14_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK14_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK14_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK14_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK14_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK14_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK14_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK14.Reg, volatile.LoadUint32(&o.HCINTMSK14.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK14_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK14.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ14: OTG host channel 14 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ14_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ14.Reg, volatile.LoadUint32(&o.HCTSIZ14.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ14_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ14.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ14_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ14.Reg, volatile.LoadUint32(&o.HCTSIZ14.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ14_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ14.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ14_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ14.Reg, volatile.LoadUint32(&o.HCTSIZ14.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ14_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ14.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ14_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ14.Reg, volatile.LoadUint32(&o.HCTSIZ14.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ14_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ14.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA14: OTG host channel 14 DMA address register
func (o *OTG_HS_Type) SetHCDMA14(value uint32) {
	volatile.StoreUint32(&o.HCDMA14.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA14() uint32 {
	return volatile.LoadUint32(&o.HCDMA14.Reg)
}

// OTG_HS.HCCHAR15: OTG host channel 15 characteristics register
func (o *OTG_HS_Type) SetHCCHAR15_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetHCCHAR15_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetHCCHAR15_EPNUM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x7800)|value<<11)
}
func (o *OTG_HS_Type) GetHCCHAR15_EPNUM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x7800) >> 11
}
func (o *OTG_HS_Type) SetHCCHAR15_EPDIR(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetHCCHAR15_EPDIR() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetHCCHAR15_LSDEV(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetHCCHAR15_LSDEV() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetHCCHAR15_EPTYP(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetHCCHAR15_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetHCCHAR15_MCNT(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x300000)|value<<20)
}
func (o *OTG_HS_Type) GetHCCHAR15_MCNT() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x300000) >> 20
}
func (o *OTG_HS_Type) SetHCCHAR15_DAD(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x1fc00000)|value<<22)
}
func (o *OTG_HS_Type) GetHCCHAR15_DAD() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x1fc00000) >> 22
}
func (o *OTG_HS_Type) SetHCCHAR15_ODDFRM(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCCHAR15_ODDFRM() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetHCCHAR15_CHDIS(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetHCCHAR15_CHDIS() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetHCCHAR15_CHENA(value uint32) {
	volatile.StoreUint32(&o.HCCHAR15.Reg, volatile.LoadUint32(&o.HCCHAR15.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCCHAR15_CHENA() uint32 {
	return (volatile.LoadUint32(&o.HCCHAR15.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCSPLT15: OTG host channel 15 split control register
func (o *OTG_HS_Type) SetHCSPLT15_PRTADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT15.Reg, volatile.LoadUint32(&o.HCSPLT15.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetHCSPLT15_PRTADDR() uint32 {
	return volatile.LoadUint32(&o.HCSPLT15.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetHCSPLT15_HUBADDR(value uint32) {
	volatile.StoreUint32(&o.HCSPLT15.Reg, volatile.LoadUint32(&o.HCSPLT15.Reg)&^(0x3f80)|value<<7)
}
func (o *OTG_HS_Type) GetHCSPLT15_HUBADDR() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT15.Reg) & 0x3f80) >> 7
}
func (o *OTG_HS_Type) SetHCSPLT15_XACTPOS(value uint32) {
	volatile.StoreUint32(&o.HCSPLT15.Reg, volatile.LoadUint32(&o.HCSPLT15.Reg)&^(0xc000)|value<<14)
}
func (o *OTG_HS_Type) GetHCSPLT15_XACTPOS() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT15.Reg) & 0xc000) >> 14
}
func (o *OTG_HS_Type) SetHCSPLT15_COMPLSPLT(value uint32) {
	volatile.StoreUint32(&o.HCSPLT15.Reg, volatile.LoadUint32(&o.HCSPLT15.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetHCSPLT15_COMPLSPLT() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT15.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetHCSPLT15_SPLITEN(value uint32) {
	volatile.StoreUint32(&o.HCSPLT15.Reg, volatile.LoadUint32(&o.HCSPLT15.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCSPLT15_SPLITEN() uint32 {
	return (volatile.LoadUint32(&o.HCSPLT15.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCINT15: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetHCINT15_XFRC(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINT15_XFRC() uint32 {
	return volatile.LoadUint32(&o.HCINT15.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINT15_CHH(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINT15_CHH() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINT15_STALL(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINT15_STALL() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINT15_NAK(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINT15_NAK() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINT15_ACK(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINT15_ACK() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINT15_TXERR(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINT15_TXERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINT15_BBERR(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINT15_BBERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINT15_FRMOR(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINT15_FRMOR() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINT15_DTERR(value uint32) {
	volatile.StoreUint32(&o.HCINT15.Reg, volatile.LoadUint32(&o.HCINT15.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINT15_DTERR() uint32 {
	return (volatile.LoadUint32(&o.HCINT15.Reg) & 0x400) >> 10
}

// OTG_HS.HCINTMSK15: This register reflects the mask for each channel status described in the previous section.
func (o *OTG_HS_Type) SetHCINTMSK15_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHCINTMSK15_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHCINTMSK15_CHHM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHCINTMSK15_CHHM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHCINTMSK15_STALLM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHCINTMSK15_STALLM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHCINTMSK15_NAKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHCINTMSK15_NAKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHCINTMSK15_ACKM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetHCINTMSK15_ACKM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetHCINTMSK15_TXERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetHCINTMSK15_TXERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetHCINTMSK15_BBERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHCINTMSK15_BBERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHCINTMSK15_FRMORM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHCINTMSK15_FRMORM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHCINTMSK15_DTERRM(value uint32) {
	volatile.StoreUint32(&o.HCINTMSK15.Reg, volatile.LoadUint32(&o.HCINTMSK15.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetHCINTMSK15_DTERRM() uint32 {
	return (volatile.LoadUint32(&o.HCINTMSK15.Reg) & 0x400) >> 10
}

// OTG_HS.HCTSIZ15: OTG host channel 15 transfer size register
func (o *OTG_HS_Type) SetHCTSIZ15_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ15.Reg, volatile.LoadUint32(&o.HCTSIZ15.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetHCTSIZ15_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.HCTSIZ15.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetHCTSIZ15_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ15.Reg, volatile.LoadUint32(&o.HCTSIZ15.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetHCTSIZ15_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ15.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetHCTSIZ15_DPID(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ15.Reg, volatile.LoadUint32(&o.HCTSIZ15.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetHCTSIZ15_DPID() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ15.Reg) & 0x60000000) >> 29
}
func (o *OTG_HS_Type) SetHCTSIZ15_DOPNG(value uint32) {
	volatile.StoreUint32(&o.HCTSIZ15.Reg, volatile.LoadUint32(&o.HCTSIZ15.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetHCTSIZ15_DOPNG() uint32 {
	return (volatile.LoadUint32(&o.HCTSIZ15.Reg) & 0x80000000) >> 31
}

// OTG_HS.HCDMA15: OTG host channel 15 DMA address register
func (o *OTG_HS_Type) SetHCDMA15(value uint32) {
	volatile.StoreUint32(&o.HCDMA15.Reg, value)
}
func (o *OTG_HS_Type) GetHCDMA15() uint32 {
	return volatile.LoadUint32(&o.HCDMA15.Reg)
}

// OTG_HS.DCFG: This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
func (o *OTG_HS_Type) SetDCFG_DSPD(value uint32) {
	volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x3)|value)
}
func (o *OTG_HS_Type) GetDCFG_DSPD() uint32 {
	return volatile.LoadUint32(&o.DCFG.Reg) & 0x3
}
func (o *OTG_HS_Type) SetDCFG_NZLSOHSK(value uint32) {
	volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDCFG_NZLSOHSK() uint32 {
	return (volatile.LoadUint32(&o.DCFG.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDCFG_DAD(value uint32) {
	volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x7f0)|value<<4)
}
func (o *OTG_HS_Type) GetDCFG_DAD() uint32 {
	return (volatile.LoadUint32(&o.DCFG.Reg) & 0x7f0) >> 4
}
func (o *OTG_HS_Type) SetDCFG_PFIVL(value uint32) {
	volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x1800)|value<<11)
}
func (o *OTG_HS_Type) GetDCFG_PFIVL() uint32 {
	return (volatile.LoadUint32(&o.DCFG.Reg) & 0x1800) >> 11
}
func (o *OTG_HS_Type) SetDCFG_ERRATIM(value uint32) {
	volatile.StoreUint32(&o.DCFG.Reg, volatile.LoadUint32(&o.DCFG.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDCFG_ERRATIM() uint32 {
	return (volatile.LoadUint32(&o.DCFG.Reg) & 0x8000) >> 15
}

// OTG_HS.DCTL: OTG device control register
func (o *OTG_HS_Type) SetDCTL_RWUSIG(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDCTL_RWUSIG() uint32 {
	return volatile.LoadUint32(&o.DCTL.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDCTL_SDIS(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDCTL_SDIS() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDCTL_GINSTS(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDCTL_GINSTS() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDCTL_GONSTS(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDCTL_GONSTS() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDCTL_TCTL(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x70)|value<<4)
}
func (o *OTG_HS_Type) GetDCTL_TCTL() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x70) >> 4
}
func (o *OTG_HS_Type) SetDCTL_SGINAK(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDCTL_SGINAK() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDCTL_CGINAK(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDCTL_CGINAK() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDCTL_SGONAK(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDCTL_SGONAK() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDCTL_CGONAK(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x400)|value<<10)
}
func (o *OTG_HS_Type) GetDCTL_CGONAK() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x400) >> 10
}
func (o *OTG_HS_Type) SetDCTL_POPRGDNE(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDCTL_POPRGDNE() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDCTL_DSBESLRJCT(value uint32) {
	volatile.StoreUint32(&o.DCTL.Reg, volatile.LoadUint32(&o.DCTL.Reg)&^(0x40000)|value<<18)
}
func (o *OTG_HS_Type) GetDCTL_DSBESLRJCT() uint32 {
	return (volatile.LoadUint32(&o.DCTL.Reg) & 0x40000) >> 18
}

// OTG_HS.DSTS: This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register.
func (o *OTG_HS_Type) SetDSTS_SUSPSTS(value uint32) {
	volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDSTS_SUSPSTS() uint32 {
	return volatile.LoadUint32(&o.DSTS.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDSTS_ENUMSPD(value uint32) {
	volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x6)|value<<1)
}
func (o *OTG_HS_Type) GetDSTS_ENUMSPD() uint32 {
	return (volatile.LoadUint32(&o.DSTS.Reg) & 0x6) >> 1
}
func (o *OTG_HS_Type) SetDSTS_EERR(value uint32) {
	volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDSTS_EERR() uint32 {
	return (volatile.LoadUint32(&o.DSTS.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDSTS_FNSOF(value uint32) {
	volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0x3fff00)|value<<8)
}
func (o *OTG_HS_Type) GetDSTS_FNSOF() uint32 {
	return (volatile.LoadUint32(&o.DSTS.Reg) & 0x3fff00) >> 8
}
func (o *OTG_HS_Type) SetDSTS_DEVLNSTS(value uint32) {
	volatile.StoreUint32(&o.DSTS.Reg, volatile.LoadUint32(&o.DSTS.Reg)&^(0xc00000)|value<<22)
}
func (o *OTG_HS_Type) GetDSTS_DEVLNSTS() uint32 {
	return (volatile.LoadUint32(&o.DSTS.Reg) & 0xc00000) >> 22
}

// OTG_HS.DIEPMSK: This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
func (o *OTG_HS_Type) SetDIEPMSK_XFRCM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPMSK_XFRCM() uint32 {
	return volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPMSK_EPDM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPMSK_EPDM() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPMSK_AHBERRM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDIEPMSK_AHBERRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDIEPMSK_TOM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPMSK_TOM() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPMSK_ITTXFEMSK(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPMSK_ITTXFEMSK() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPMSK_INEPNMM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPMSK_INEPNMM() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPMSK_INEPNEM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPMSK_INEPNEM() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPMSK_TXFURM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDIEPMSK_TXFURM() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDIEPMSK_NAKM(value uint32) {
	volatile.StoreUint32(&o.DIEPMSK.Reg, volatile.LoadUint32(&o.DIEPMSK.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPMSK_NAKM() uint32 {
	return (volatile.LoadUint32(&o.DIEPMSK.Reg) & 0x2000) >> 13
}

// OTG_HS.DOEPMSK: This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
func (o *OTG_HS_Type) SetDOEPMSK_XFRCM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPMSK_XFRCM() uint32 {
	return volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPMSK_EPDM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPMSK_EPDM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPMSK_AHBERRM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPMSK_AHBERRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPMSK_STUPM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPMSK_STUPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPMSK_OTEPDM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPMSK_OTEPDM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPMSK_STSPHSRXM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPMSK_STSPHSRXM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPMSK_B2BSTUPM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPMSK_B2BSTUPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPMSK_OUTPKTERRM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPMSK_OUTPKTERRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPMSK_BERRM(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPMSK_BERRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPMSK_NAKMSK(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPMSK_NAKMSK() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPMSK_NYETMSK(value uint32) {
	volatile.StoreUint32(&o.DOEPMSK.Reg, volatile.LoadUint32(&o.DOEPMSK.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPMSK_NYETMSK() uint32 {
	return (volatile.LoadUint32(&o.DOEPMSK.Reg) & 0x4000) >> 14
}

// OTG_HS.DAINT: When a significant event occurs on an endpoint, a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (DIEPINTx/DOEPINTx).
func (o *OTG_HS_Type) SetDAINT_IEPINT(value uint32) {
	volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDAINT_IEPINT() uint32 {
	return volatile.LoadUint32(&o.DAINT.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDAINT_OEPINT(value uint32) {
	volatile.StoreUint32(&o.DAINT.Reg, volatile.LoadUint32(&o.DAINT.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDAINT_OEPINT() uint32 {
	return (volatile.LoadUint32(&o.DAINT.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DAINTMSK: The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the DAINT register bit corresponding to that interrupt is still set.
func (o *OTG_HS_Type) SetDAINTMSK_IEPM(value uint32) {
	volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDAINTMSK_IEPM() uint32 {
	return volatile.LoadUint32(&o.DAINTMSK.Reg) & 0xffff
}
func (o *OTG_HS_Type) SetDAINTMSK_OEPM(value uint32) {
	volatile.StoreUint32(&o.DAINTMSK.Reg, volatile.LoadUint32(&o.DAINTMSK.Reg)&^(0xffff0000)|value<<16)
}
func (o *OTG_HS_Type) GetDAINTMSK_OEPM() uint32 {
	return (volatile.LoadUint32(&o.DAINTMSK.Reg) & 0xffff0000) >> 16
}

// OTG_HS.DVBUSDIS: This register specifies the VBUS discharge time after VBUS pulsing during SRP.
func (o *OTG_HS_Type) SetDVBUSDIS_VBUSDT(value uint32) {
	volatile.StoreUint32(&o.DVBUSDIS.Reg, volatile.LoadUint32(&o.DVBUSDIS.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDVBUSDIS_VBUSDT() uint32 {
	return volatile.LoadUint32(&o.DVBUSDIS.Reg) & 0xffff
}

// OTG_HS.DVBUSPULSE: This register specifies the VBUS pulsing time during SRP.
func (o *OTG_HS_Type) SetDVBUSPULSE_DVBUSP(value uint32) {
	volatile.StoreUint32(&o.DVBUSPULSE.Reg, volatile.LoadUint32(&o.DVBUSPULSE.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDVBUSPULSE_DVBUSP() uint32 {
	return volatile.LoadUint32(&o.DVBUSPULSE.Reg) & 0xffff
}

// OTG_HS.DTHRCTL: OTG device threshold control register
func (o *OTG_HS_Type) SetDTHRCTL_NONISOTHREN(value uint32) {
	volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDTHRCTL_NONISOTHREN() uint32 {
	return volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDTHRCTL_ISOTHREN(value uint32) {
	volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDTHRCTL_ISOTHREN() uint32 {
	return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDTHRCTL_TXTHRLEN(value uint32) {
	volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x7fc)|value<<2)
}
func (o *OTG_HS_Type) GetDTHRCTL_TXTHRLEN() uint32 {
	return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x7fc) >> 2
}
func (o *OTG_HS_Type) SetDTHRCTL_RXTHREN(value uint32) {
	volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDTHRCTL_RXTHREN() uint32 {
	return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDTHRCTL_RXTHRLEN(value uint32) {
	volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x3fe0000)|value<<17)
}
func (o *OTG_HS_Type) GetDTHRCTL_RXTHRLEN() uint32 {
	return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x3fe0000) >> 17
}
func (o *OTG_HS_Type) SetDTHRCTL_ARPEN(value uint32) {
	volatile.StoreUint32(&o.DTHRCTL.Reg, volatile.LoadUint32(&o.DTHRCTL.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDTHRCTL_ARPEN() uint32 {
	return (volatile.LoadUint32(&o.DTHRCTL.Reg) & 0x8000000) >> 27
}

// OTG_HS.DIEPEMPMSK: This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).
func (o *OTG_HS_Type) SetDIEPEMPMSK_INEPTXFEM(value uint32) {
	volatile.StoreUint32(&o.DIEPEMPMSK.Reg, volatile.LoadUint32(&o.DIEPEMPMSK.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDIEPEMPMSK_INEPTXFEM() uint32 {
	return volatile.LoadUint32(&o.DIEPEMPMSK.Reg) & 0xffff
}

// OTG_HS.HS_DOEPEACHMSK1: OTG device each OUT endpoint-1 interrupt mask register
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_XFRCM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_XFRCM() uint32 {
	return volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x1
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_EPDM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_EPDM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_AHBERRM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_AHBERRM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_STUPM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_STUPM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_OTEPDM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_OTEPDM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_B2BSTUPM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_B2BSTUPM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_OUTPKTERRM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_OUTPKTERRM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_BNAM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_BNAM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_BERRM(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_BERRM() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_NAKMSK(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_NAKMSK() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetHS_DOEPEACHMSK1_NYETMSK(value uint32) {
	volatile.StoreUint32(&o.HS_DOEPEACHMSK1.Reg, volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetHS_DOEPEACHMSK1_NYETMSK() uint32 {
	return (volatile.LoadUint32(&o.HS_DOEPEACHMSK1.Reg) & 0x4000) >> 14
}

// OTG_HS.DIEPCTL0: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDIEPCTL0_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x3)|value)
}
func (o *OTG_HS_Type) GetDIEPCTL0_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x3
}
func (o *OTG_HS_Type) SetDIEPCTL0_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDIEPCTL0_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDIEPCTL0_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDIEPCTL0_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDIEPCTL0_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDIEPCTL0_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDIEPCTL0_STALL(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDIEPCTL0_STALL() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDIEPCTL0_TXFNUM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x3c00000)|value<<22)
}
func (o *OTG_HS_Type) GetDIEPCTL0_TXFNUM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x3c00000) >> 22
}
func (o *OTG_HS_Type) SetDIEPCTL0_CNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDIEPCTL0_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDIEPCTL0_SNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDIEPCTL0_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDIEPCTL0_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDIEPCTL0_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDIEPCTL0_EPENA(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL0.Reg, volatile.LoadUint32(&o.DIEPCTL0.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDIEPCTL0_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL0.Reg) & 0x80000000) >> 31
}

// OTG_HS.DIEPINT0: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT0_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT0_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT0_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT0_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT0_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT0_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT0_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT0_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT0_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT0_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT0_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT0_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT0_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT0_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT0_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT0_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT0_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT0.Reg, volatile.LoadUint32(&o.DIEPINT0.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT0_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT0.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ0: The application must modify this register before enabling endpoint 0.
func (o *OTG_HS_Type) SetDIEPTSIZ0_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ0.Reg, volatile.LoadUint32(&o.DIEPTSIZ0.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ0_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ0.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetDIEPTSIZ0_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ0.Reg, volatile.LoadUint32(&o.DIEPTSIZ0.Reg)&^(0x180000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ0_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ0.Reg) & 0x180000) >> 19
}

// OTG_HS.DTXFSTS0: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
func (o *OTG_HS_Type) SetDTXFSTS0_INEPTFSAV(value uint32) {
	volatile.StoreUint32(&o.DTXFSTS0.Reg, volatile.LoadUint32(&o.DTXFSTS0.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDTXFSTS0_INEPTFSAV() uint32 {
	return volatile.LoadUint32(&o.DTXFSTS0.Reg) & 0xffff
}

// OTG_HS.DIEPCTL1: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDIEPCTL1_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDIEPCTL1_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDIEPCTL1_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDIEPCTL1_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDIEPCTL1_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPCTL1_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDIEPCTL1_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDIEPCTL1_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDIEPCTL1_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDIEPCTL1_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDIEPCTL1_STALL(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDIEPCTL1_STALL() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDIEPCTL1_TXFNUM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x3c00000)|value<<22)
}
func (o *OTG_HS_Type) GetDIEPCTL1_TXFNUM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x3c00000) >> 22
}
func (o *OTG_HS_Type) SetDIEPCTL1_CNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDIEPCTL1_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDIEPCTL1_SNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDIEPCTL1_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDIEPCTL1_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDIEPCTL1_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDIEPCTL1_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPCTL1_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDIEPCTL1_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDIEPCTL1_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDIEPCTL1_EPENA(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL1.Reg, volatile.LoadUint32(&o.DIEPCTL1.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDIEPCTL1_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL1.Reg) & 0x80000000) >> 31
}

// OTG_HS.DIEPINT1: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT1_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT1_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT1_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT1_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT1_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT1_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT1_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT1_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT1_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT1_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT1_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT1_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT1_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT1_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT1_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT1_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT1_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT1.Reg, volatile.LoadUint32(&o.DIEPINT1.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT1_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT1.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ1: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ1_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ1.Reg, volatile.LoadUint32(&o.DIEPTSIZ1.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ1_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ1.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ1_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ1.Reg, volatile.LoadUint32(&o.DIEPTSIZ1.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ1_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ1.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ1_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ1.Reg, volatile.LoadUint32(&o.DIEPTSIZ1.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ1_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ1.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA1: OTG device IN endpoint 1 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA1(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA1.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA1() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA1.Reg)
}

// OTG_HS.DTXFSTS1: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
func (o *OTG_HS_Type) SetDTXFSTS1_INEPTFSAV(value uint32) {
	volatile.StoreUint32(&o.DTXFSTS1.Reg, volatile.LoadUint32(&o.DTXFSTS1.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDTXFSTS1_INEPTFSAV() uint32 {
	return volatile.LoadUint32(&o.DTXFSTS1.Reg) & 0xffff
}

// OTG_HS.DIEPCTL2: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDIEPCTL2_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDIEPCTL2_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDIEPCTL2_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDIEPCTL2_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDIEPCTL2_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPCTL2_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDIEPCTL2_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDIEPCTL2_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDIEPCTL2_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDIEPCTL2_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDIEPCTL2_STALL(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDIEPCTL2_STALL() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDIEPCTL2_TXFNUM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x3c00000)|value<<22)
}
func (o *OTG_HS_Type) GetDIEPCTL2_TXFNUM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x3c00000) >> 22
}
func (o *OTG_HS_Type) SetDIEPCTL2_CNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDIEPCTL2_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDIEPCTL2_SNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDIEPCTL2_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDIEPCTL2_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDIEPCTL2_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDIEPCTL2_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPCTL2_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDIEPCTL2_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDIEPCTL2_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDIEPCTL2_EPENA(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL2.Reg, volatile.LoadUint32(&o.DIEPCTL2.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDIEPCTL2_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL2.Reg) & 0x80000000) >> 31
}

// OTG_HS.DIEPINT2: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT2_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT2_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT2_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT2_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT2_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT2_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT2_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT2_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT2_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT2_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT2_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT2_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT2_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT2_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT2_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT2_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT2_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT2.Reg, volatile.LoadUint32(&o.DIEPINT2.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT2_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT2.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ2: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ2_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ2.Reg, volatile.LoadUint32(&o.DIEPTSIZ2.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ2_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ2.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ2_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ2.Reg, volatile.LoadUint32(&o.DIEPTSIZ2.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ2_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ2.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ2_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ2.Reg, volatile.LoadUint32(&o.DIEPTSIZ2.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ2_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ2.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA2: OTG device IN endpoint 2 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA2(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA2.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA2() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA2.Reg)
}

// OTG_HS.DTXFSTS2: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
func (o *OTG_HS_Type) SetDTXFSTS2_INEPTFSAV(value uint32) {
	volatile.StoreUint32(&o.DTXFSTS2.Reg, volatile.LoadUint32(&o.DTXFSTS2.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDTXFSTS2_INEPTFSAV() uint32 {
	return volatile.LoadUint32(&o.DTXFSTS2.Reg) & 0xffff
}

// OTG_HS.DIEPCTL3: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDIEPCTL3_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDIEPCTL3_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDIEPCTL3_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDIEPCTL3_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDIEPCTL3_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPCTL3_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDIEPCTL3_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDIEPCTL3_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDIEPCTL3_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDIEPCTL3_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDIEPCTL3_STALL(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDIEPCTL3_STALL() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDIEPCTL3_TXFNUM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x3c00000)|value<<22)
}
func (o *OTG_HS_Type) GetDIEPCTL3_TXFNUM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x3c00000) >> 22
}
func (o *OTG_HS_Type) SetDIEPCTL3_CNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDIEPCTL3_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDIEPCTL3_SNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDIEPCTL3_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDIEPCTL3_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDIEPCTL3_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDIEPCTL3_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPCTL3_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDIEPCTL3_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDIEPCTL3_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDIEPCTL3_EPENA(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL3.Reg, volatile.LoadUint32(&o.DIEPCTL3.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDIEPCTL3_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL3.Reg) & 0x80000000) >> 31
}

// OTG_HS.DIEPINT3: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT3_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT3_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT3_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT3_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT3_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT3_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT3_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT3_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT3_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT3_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT3_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT3_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT3_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT3_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT3_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT3_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT3_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT3.Reg, volatile.LoadUint32(&o.DIEPINT3.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT3_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT3.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ3: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ3_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ3.Reg, volatile.LoadUint32(&o.DIEPTSIZ3.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ3_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ3.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ3_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ3.Reg, volatile.LoadUint32(&o.DIEPTSIZ3.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ3_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ3.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ3_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ3.Reg, volatile.LoadUint32(&o.DIEPTSIZ3.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ3_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ3.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA3: OTG device IN endpoint 3 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA3(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA3.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA3() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA3.Reg)
}

// OTG_HS.DTXFSTS3: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
func (o *OTG_HS_Type) SetDTXFSTS3_INEPTFSAV(value uint32) {
	volatile.StoreUint32(&o.DTXFSTS3.Reg, volatile.LoadUint32(&o.DTXFSTS3.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDTXFSTS3_INEPTFSAV() uint32 {
	return volatile.LoadUint32(&o.DTXFSTS3.Reg) & 0xffff
}

// OTG_HS.DIEPCTL4: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDIEPCTL4_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDIEPCTL4_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDIEPCTL4_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDIEPCTL4_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDIEPCTL4_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPCTL4_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDIEPCTL4_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDIEPCTL4_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDIEPCTL4_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDIEPCTL4_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDIEPCTL4_STALL(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDIEPCTL4_STALL() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDIEPCTL4_TXFNUM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x3c00000)|value<<22)
}
func (o *OTG_HS_Type) GetDIEPCTL4_TXFNUM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x3c00000) >> 22
}
func (o *OTG_HS_Type) SetDIEPCTL4_CNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDIEPCTL4_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDIEPCTL4_SNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDIEPCTL4_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDIEPCTL4_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDIEPCTL4_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDIEPCTL4_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPCTL4_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDIEPCTL4_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDIEPCTL4_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDIEPCTL4_EPENA(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL4.Reg, volatile.LoadUint32(&o.DIEPCTL4.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDIEPCTL4_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL4.Reg) & 0x80000000) >> 31
}

// OTG_HS.DIEPINT4: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT4_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT4_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT4_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT4_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT4_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT4_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT4_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT4_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT4_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT4_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT4_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT4_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT4_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT4_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT4_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT4_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT4_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT4.Reg, volatile.LoadUint32(&o.DIEPINT4.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT4_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT4.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ4: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ4_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ4.Reg, volatile.LoadUint32(&o.DIEPTSIZ4.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ4_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ4.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ4_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ4.Reg, volatile.LoadUint32(&o.DIEPTSIZ4.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ4_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ4.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ4_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ4.Reg, volatile.LoadUint32(&o.DIEPTSIZ4.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ4_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ4.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA4: OTG device IN endpoint 4 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA4(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA4.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA4() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA4.Reg)
}

// OTG_HS.DTXFSTS4: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
func (o *OTG_HS_Type) SetDTXFSTS4_INEPTFSAV(value uint32) {
	volatile.StoreUint32(&o.DTXFSTS4.Reg, volatile.LoadUint32(&o.DTXFSTS4.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDTXFSTS4_INEPTFSAV() uint32 {
	return volatile.LoadUint32(&o.DTXFSTS4.Reg) & 0xffff
}

// OTG_HS.DIEPCTL5: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDIEPCTL5_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDIEPCTL5_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDIEPCTL5_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDIEPCTL5_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDIEPCTL5_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDIEPCTL5_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDIEPCTL5_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDIEPCTL5_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDIEPCTL5_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDIEPCTL5_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDIEPCTL5_STALL(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDIEPCTL5_STALL() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDIEPCTL5_TXFNUM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x3c00000)|value<<22)
}
func (o *OTG_HS_Type) GetDIEPCTL5_TXFNUM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x3c00000) >> 22
}
func (o *OTG_HS_Type) SetDIEPCTL5_CNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDIEPCTL5_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDIEPCTL5_SNAK(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDIEPCTL5_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDIEPCTL5_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDIEPCTL5_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDIEPCTL5_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPCTL5_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDIEPCTL5_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDIEPCTL5_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDIEPCTL5_EPENA(value uint32) {
	volatile.StoreUint32(&o.DIEPCTL5.Reg, volatile.LoadUint32(&o.DIEPCTL5.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDIEPCTL5_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DIEPCTL5.Reg) & 0x80000000) >> 31
}

// OTG_HS.DIEPINT5: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT5_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT5_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT5_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT5_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT5_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT5_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT5_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT5_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT5_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT5_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT5_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT5_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT5_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT5_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT5_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT5_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT5_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT5.Reg, volatile.LoadUint32(&o.DIEPINT5.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT5_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT5.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ5: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ5_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ5.Reg, volatile.LoadUint32(&o.DIEPTSIZ5.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ5_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ5.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ5_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ5.Reg, volatile.LoadUint32(&o.DIEPTSIZ5.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ5_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ5.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ5_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ5.Reg, volatile.LoadUint32(&o.DIEPTSIZ5.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ5_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ5.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA5: OTG device IN endpoint 5 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA5(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA5.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA5() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA5.Reg)
}

// OTG_HS.DTXFSTS5: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
func (o *OTG_HS_Type) SetDTXFSTS5_INEPTFSAV(value uint32) {
	volatile.StoreUint32(&o.DTXFSTS5.Reg, volatile.LoadUint32(&o.DTXFSTS5.Reg)&^(0xffff)|value)
}
func (o *OTG_HS_Type) GetDTXFSTS5_INEPTFSAV() uint32 {
	return volatile.LoadUint32(&o.DTXFSTS5.Reg) & 0xffff
}

// OTG_HS.DIEPINT6: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT6_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT6_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT6_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT6_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT6_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDIEPINT6_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDIEPINT6_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT6_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT6_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT6_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT6_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT6_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT6_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT6_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT6_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT6_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT6_TXFIFOUDRN(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDIEPINT6_TXFIFOUDRN() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDIEPINT6_BNA(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDIEPINT6_BNA() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDIEPINT6_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT6_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT6_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT6.Reg, volatile.LoadUint32(&o.DIEPINT6.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT6_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT6.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ6: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ6_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ6.Reg, volatile.LoadUint32(&o.DIEPTSIZ6.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ6_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ6.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ6_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ6.Reg, volatile.LoadUint32(&o.DIEPTSIZ6.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ6_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ6.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ6_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ6.Reg, volatile.LoadUint32(&o.DIEPTSIZ6.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ6_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ6.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA6: OTG device IN endpoint 6 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA6(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA6.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA6() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA6.Reg)
}

// OTG_HS.DIEPINT7: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT7_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT7_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT7_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT7_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT7_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDIEPINT7_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDIEPINT7_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT7_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT7_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT7_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT7_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT7_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT7_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT7_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT7_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT7_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT7_TXFIFOUDRN(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDIEPINT7_TXFIFOUDRN() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDIEPINT7_BNA(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDIEPINT7_BNA() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDIEPINT7_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT7_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT7_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT7.Reg, volatile.LoadUint32(&o.DIEPINT7.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT7_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT7.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ7: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ7_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ7.Reg, volatile.LoadUint32(&o.DIEPTSIZ7.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ7_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ7.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ7_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ7.Reg, volatile.LoadUint32(&o.DIEPTSIZ7.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ7_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ7.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ7_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ7.Reg, volatile.LoadUint32(&o.DIEPTSIZ7.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ7_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ7.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA7: OTG device IN endpoint 7 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA7(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA7.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA7() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA7.Reg)
}

// OTG_HS.DIEPINT8: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDIEPINT8_XFRC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDIEPINT8_XFRC() uint32 {
	return volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDIEPINT8_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDIEPINT8_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDIEPINT8_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDIEPINT8_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDIEPINT8_TOC(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDIEPINT8_TOC() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDIEPINT8_ITTXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDIEPINT8_ITTXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDIEPINT8_INEPNM(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDIEPINT8_INEPNM() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDIEPINT8_INEPNE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDIEPINT8_INEPNE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDIEPINT8_TXFE(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetDIEPINT8_TXFE() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x80) >> 7
}
func (o *OTG_HS_Type) SetDIEPINT8_TXFIFOUDRN(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDIEPINT8_TXFIFOUDRN() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDIEPINT8_BNA(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDIEPINT8_BNA() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDIEPINT8_PKTDRPSTS(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x800)|value<<11)
}
func (o *OTG_HS_Type) GetDIEPINT8_PKTDRPSTS() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x800) >> 11
}
func (o *OTG_HS_Type) SetDIEPINT8_NAK(value uint32) {
	volatile.StoreUint32(&o.DIEPINT8.Reg, volatile.LoadUint32(&o.DIEPINT8.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDIEPINT8_NAK() uint32 {
	return (volatile.LoadUint32(&o.DIEPINT8.Reg) & 0x2000) >> 13
}

// OTG_HS.DIEPTSIZ8: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDIEPTSIZ8_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ8.Reg, volatile.LoadUint32(&o.DIEPTSIZ8.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDIEPTSIZ8_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DIEPTSIZ8.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDIEPTSIZ8_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ8.Reg, volatile.LoadUint32(&o.DIEPTSIZ8.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDIEPTSIZ8_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ8.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDIEPTSIZ8_MCNT(value uint32) {
	volatile.StoreUint32(&o.DIEPTSIZ8.Reg, volatile.LoadUint32(&o.DIEPTSIZ8.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDIEPTSIZ8_MCNT() uint32 {
	return (volatile.LoadUint32(&o.DIEPTSIZ8.Reg) & 0x60000000) >> 29
}

// OTG_HS.DIEPDMA8: OTG device IN endpoint 8 DMA address register
func (o *OTG_HS_Type) SetDIEPDMA8(value uint32) {
	volatile.StoreUint32(&o.DIEPDMA8.Reg, value)
}
func (o *OTG_HS_Type) GetDIEPDMA8() uint32 {
	return volatile.LoadUint32(&o.DIEPDMA8.Reg)
}

// OTG_HS.DOEPCTL0: This section describes the DOEPCTL0 register.
func (o *OTG_HS_Type) SetDOEPCTL0_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x3)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL0_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x3
}
func (o *OTG_HS_Type) SetDOEPCTL0_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL0_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL0_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL0_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL0_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL0_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL0_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL0_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL0_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL0_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL0_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL0_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL0_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL0_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL0_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL0_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL0_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL0.Reg, volatile.LoadUint32(&o.DOEPCTL0.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL0_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL0.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT0: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT0_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT0_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT0_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT0_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT0_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT0_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT0_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT0_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT0_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT0_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT0_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT0_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT0_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT0_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT0_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT0_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT0_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT0_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT0_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT0_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT0_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT0_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT0_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT0_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT0_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT0.Reg, volatile.LoadUint32(&o.DOEPINT0.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT0_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT0.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ0: The application must modify this register before enabling endpoint 0.
func (o *OTG_HS_Type) SetDOEPTSIZ0_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x7f)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ0_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x7f
}
func (o *OTG_HS_Type) SetDOEPTSIZ0_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ0_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ0_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ0.Reg, volatile.LoadUint32(&o.DOEPTSIZ0.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ0_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ0.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA0: OTG device OUT endpoint 0 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA0(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA0.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA0() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA0.Reg)
}

// OTG_HS.DOEPCTL1: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL1_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL1_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL1_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL1_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL1_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL1_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL1_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL1_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL1_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL1_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL1_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL1_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL1_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL1_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL1_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL1_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL1_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL1_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL1_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL1_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL1_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL1_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL1_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL1_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL1_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL1.Reg, volatile.LoadUint32(&o.DOEPCTL1.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL1_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL1.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT1: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT1_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT1_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT1_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT1_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT1_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT1_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT1_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT1_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT1_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT1_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT1_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT1_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT1_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT1_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT1_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT1_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT1_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT1_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT1_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT1_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT1_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT1_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT1_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT1_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT1_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT1.Reg, volatile.LoadUint32(&o.DOEPINT1.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT1_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT1.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ1: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ1_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ1_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ1_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ1_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ1_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ1.Reg, volatile.LoadUint32(&o.DOEPTSIZ1.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ1_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ1.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA1: OTG device OUT endpoint 1 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA1(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA1.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA1() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA1.Reg)
}

// OTG_HS.DOEPCTL2: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL2_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL2_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL2_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL2_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL2_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL2_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL2_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL2_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL2_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL2_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL2_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL2_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL2_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL2_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL2_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL2_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL2_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL2_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL2_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL2_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL2_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL2_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL2_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL2_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL2_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL2.Reg, volatile.LoadUint32(&o.DOEPCTL2.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL2_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL2.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT2: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT2_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT2_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT2_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT2_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT2_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT2_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT2_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT2_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT2_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT2_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT2_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT2_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT2_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT2_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT2_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT2_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT2_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT2_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT2_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT2_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT2_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT2_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT2_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT2_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT2_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT2.Reg, volatile.LoadUint32(&o.DOEPINT2.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT2_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT2.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ2: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ2_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ2_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ2_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ2_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ2_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ2.Reg, volatile.LoadUint32(&o.DOEPTSIZ2.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ2_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ2.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA2: OTG device OUT endpoint 2 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA2(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA2.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA2() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA2.Reg)
}

// OTG_HS.DOEPCTL3: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL3_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL3_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL3_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL3_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL3_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL3_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL3_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL3_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL3_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL3_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL3_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL3_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL3_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL3_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL3_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL3_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL3_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL3_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL3_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL3_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL3_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL3_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL3_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL3_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL3_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL3.Reg, volatile.LoadUint32(&o.DOEPCTL3.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL3_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL3.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT3: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT3_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT3_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT3_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT3_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT3_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT3_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT3_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT3_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT3_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT3_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT3_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT3_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT3_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT3_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT3_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT3_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT3_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT3_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT3_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT3_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT3_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT3_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT3_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT3_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT3_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT3.Reg, volatile.LoadUint32(&o.DOEPINT3.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT3_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT3.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ3: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ3_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ3_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ3_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ3_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ3_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ3.Reg, volatile.LoadUint32(&o.DOEPTSIZ3.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ3_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ3.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA3: OTG device OUT endpoint 3 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA3(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA3.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA3() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA3.Reg)
}

// OTG_HS.DOEPCTL4: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL4_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL4_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL4_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL4_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL4_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL4_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL4_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL4_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL4_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL4_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL4_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL4_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL4_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL4_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL4_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL4_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL4_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL4_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL4_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL4_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL4_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL4_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL4_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL4_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL4_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL4.Reg, volatile.LoadUint32(&o.DOEPCTL4.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL4_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL4.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT4: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT4_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT4_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT4_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT4_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT4_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT4_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT4_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT4_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT4_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT4_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT4_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT4_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT4_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT4_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT4_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT4_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT4_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT4_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT4_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT4_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT4_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT4_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT4_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT4_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT4_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT4.Reg, volatile.LoadUint32(&o.DOEPINT4.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT4_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT4.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ4: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ4_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ4_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ4_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ4_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ4_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ4.Reg, volatile.LoadUint32(&o.DOEPTSIZ4.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ4_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ4.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA4: OTG device OUT endpoint 4 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA4(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA4.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA4() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA4.Reg)
}

// OTG_HS.DOEPCTL5: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL5_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL5_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL5_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL5_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL5_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL5_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL5_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL5_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL5_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL5_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL5_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL5_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL5_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL5_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL5_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL5_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL5_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL5_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL5_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL5_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL5_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL5_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL5_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL5_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL5_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL5.Reg, volatile.LoadUint32(&o.DOEPCTL5.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL5_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL5.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT5: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT5_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT5_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT5_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT5_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT5_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT5_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT5_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT5_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT5_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT5_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT5_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT5_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT5_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT5_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT5_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT5_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT5_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT5_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT5_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT5_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT5_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT5_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT5_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT5_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT5_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT5.Reg, volatile.LoadUint32(&o.DOEPINT5.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT5_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT5.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ5: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ5_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ5_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ5_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ5_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ5_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ5.Reg, volatile.LoadUint32(&o.DOEPTSIZ5.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ5_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ5.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA5: OTG device OUT endpoint 5 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA5(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA5.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA5() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA5.Reg)
}

// OTG_HS.DOEPCTL6: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL6_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL6_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL6_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL6_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL6_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL6_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL6_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL6_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL6_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL6_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL6_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL6_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL6_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL6_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL6_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL6_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL6_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL6_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL6_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL6_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL6_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL6_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL6_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL6_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL6_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL6.Reg, volatile.LoadUint32(&o.DOEPCTL6.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL6_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL6.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT6: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT6_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT6_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT6_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT6_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT6_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT6_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT6_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT6_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT6_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT6_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT6_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT6_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT6_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT6_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT6_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT6_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT6_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT6_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT6_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT6_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT6_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT6_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT6_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT6_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT6_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT6.Reg, volatile.LoadUint32(&o.DOEPINT6.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT6_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT6.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ6: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ6_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ6_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ6_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ6_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ6_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ6.Reg, volatile.LoadUint32(&o.DOEPTSIZ6.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ6_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ6.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA6: OTG device OUT endpoint 6 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA6(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA6.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA6() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA6.Reg)
}

// OTG_HS.DOEPCTL7: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL7_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL7_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL7_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL7_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL7_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL7_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL7_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL7_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL7_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL7_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL7_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL7_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL7_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL7_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL7_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL7_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL7_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL7_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL7_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL7_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL7_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL7_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL7_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL7_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL7_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL7.Reg, volatile.LoadUint32(&o.DOEPCTL7.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL7_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL7.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT7: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT7_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT7_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT7_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT7_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT7_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT7_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT7_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT7_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT7_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT7_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT7_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT7_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT7_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT7_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT7_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT7_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT7_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT7_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT7_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT7_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT7_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT7_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT7_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT7_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT7_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT7.Reg, volatile.LoadUint32(&o.DOEPINT7.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT7_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT7.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ7: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ7_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ7.Reg, volatile.LoadUint32(&o.DOEPTSIZ7.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ7_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ7.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ7_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ7.Reg, volatile.LoadUint32(&o.DOEPTSIZ7.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ7_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ7.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ7_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ7.Reg, volatile.LoadUint32(&o.DOEPTSIZ7.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ7_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ7.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA7: OTG device OUT endpoint 7 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA7(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA7.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA7() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA7.Reg)
}

// OTG_HS.DOEPCTL8: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
func (o *OTG_HS_Type) SetDOEPCTL8_MPSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x7ff)|value)
}
func (o *OTG_HS_Type) GetDOEPCTL8_MPSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x7ff
}
func (o *OTG_HS_Type) SetDOEPCTL8_USBAEP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPCTL8_USBAEP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x8000) >> 15
}
func (o *OTG_HS_Type) SetDOEPCTL8_EONUM_DPIP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x10000)|value<<16)
}
func (o *OTG_HS_Type) GetDOEPCTL8_EONUM_DPIP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x10000) >> 16
}
func (o *OTG_HS_Type) SetDOEPCTL8_NAKSTS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x20000)|value<<17)
}
func (o *OTG_HS_Type) GetDOEPCTL8_NAKSTS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x20000) >> 17
}
func (o *OTG_HS_Type) SetDOEPCTL8_EPTYP(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0xc0000)|value<<18)
}
func (o *OTG_HS_Type) GetDOEPCTL8_EPTYP() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0xc0000) >> 18
}
func (o *OTG_HS_Type) SetDOEPCTL8_SNPM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x100000)|value<<20)
}
func (o *OTG_HS_Type) GetDOEPCTL8_SNPM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x100000) >> 20
}
func (o *OTG_HS_Type) SetDOEPCTL8_STALL(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x200000)|value<<21)
}
func (o *OTG_HS_Type) GetDOEPCTL8_STALL() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x200000) >> 21
}
func (o *OTG_HS_Type) SetDOEPCTL8_CNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x4000000)|value<<26)
}
func (o *OTG_HS_Type) GetDOEPCTL8_CNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x4000000) >> 26
}
func (o *OTG_HS_Type) SetDOEPCTL8_SNAK(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x8000000)|value<<27)
}
func (o *OTG_HS_Type) GetDOEPCTL8_SNAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x8000000) >> 27
}
func (o *OTG_HS_Type) SetDOEPCTL8_SD0PID_SEVNFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x10000000)|value<<28)
}
func (o *OTG_HS_Type) GetDOEPCTL8_SD0PID_SEVNFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x10000000) >> 28
}
func (o *OTG_HS_Type) SetDOEPCTL8_SD1PID_SODDFRM(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x20000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPCTL8_SD1PID_SODDFRM() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x20000000) >> 29
}
func (o *OTG_HS_Type) SetDOEPCTL8_EPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x40000000)|value<<30)
}
func (o *OTG_HS_Type) GetDOEPCTL8_EPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x40000000) >> 30
}
func (o *OTG_HS_Type) SetDOEPCTL8_EPENA(value uint32) {
	volatile.StoreUint32(&o.DOEPCTL8.Reg, volatile.LoadUint32(&o.DOEPCTL8.Reg)&^(0x80000000)|value<<31)
}
func (o *OTG_HS_Type) GetDOEPCTL8_EPENA() uint32 {
	return (volatile.LoadUint32(&o.DOEPCTL8.Reg) & 0x80000000) >> 31
}

// OTG_HS.DOEPINT8: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
func (o *OTG_HS_Type) SetDOEPINT8_XFRC(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetDOEPINT8_XFRC() uint32 {
	return volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x1
}
func (o *OTG_HS_Type) SetDOEPINT8_EPDISD(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetDOEPINT8_EPDISD() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetDOEPINT8_AHBERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x4)|value<<2)
}
func (o *OTG_HS_Type) GetDOEPINT8_AHBERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x4) >> 2
}
func (o *OTG_HS_Type) SetDOEPINT8_STUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x8)|value<<3)
}
func (o *OTG_HS_Type) GetDOEPINT8_STUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x8) >> 3
}
func (o *OTG_HS_Type) SetDOEPINT8_OTEPDIS(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetDOEPINT8_OTEPDIS() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetDOEPINT8_STSPHSRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetDOEPINT8_STSPHSRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetDOEPINT8_B2BSTUP(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetDOEPINT8_B2BSTUP() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetDOEPINT8_OUTPKTERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x100)|value<<8)
}
func (o *OTG_HS_Type) GetDOEPINT8_OUTPKTERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x100) >> 8
}
func (o *OTG_HS_Type) SetDOEPINT8_BNA(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x200)|value<<9)
}
func (o *OTG_HS_Type) GetDOEPINT8_BNA() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x200) >> 9
}
func (o *OTG_HS_Type) SetDOEPINT8_BERR(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x1000)|value<<12)
}
func (o *OTG_HS_Type) GetDOEPINT8_BERR() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x1000) >> 12
}
func (o *OTG_HS_Type) SetDOEPINT8_NAK(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x2000)|value<<13)
}
func (o *OTG_HS_Type) GetDOEPINT8_NAK() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x2000) >> 13
}
func (o *OTG_HS_Type) SetDOEPINT8_NYET(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x4000)|value<<14)
}
func (o *OTG_HS_Type) GetDOEPINT8_NYET() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x4000) >> 14
}
func (o *OTG_HS_Type) SetDOEPINT8_STPKTRX(value uint32) {
	volatile.StoreUint32(&o.DOEPINT8.Reg, volatile.LoadUint32(&o.DOEPINT8.Reg)&^(0x8000)|value<<15)
}
func (o *OTG_HS_Type) GetDOEPINT8_STPKTRX() uint32 {
	return (volatile.LoadUint32(&o.DOEPINT8.Reg) & 0x8000) >> 15
}

// OTG_HS.DOEPTSIZ8: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
func (o *OTG_HS_Type) SetDOEPTSIZ8_XFRSIZ(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ8.Reg, volatile.LoadUint32(&o.DOEPTSIZ8.Reg)&^(0x7ffff)|value)
}
func (o *OTG_HS_Type) GetDOEPTSIZ8_XFRSIZ() uint32 {
	return volatile.LoadUint32(&o.DOEPTSIZ8.Reg) & 0x7ffff
}
func (o *OTG_HS_Type) SetDOEPTSIZ8_PKTCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ8.Reg, volatile.LoadUint32(&o.DOEPTSIZ8.Reg)&^(0x1ff80000)|value<<19)
}
func (o *OTG_HS_Type) GetDOEPTSIZ8_PKTCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ8.Reg) & 0x1ff80000) >> 19
}
func (o *OTG_HS_Type) SetDOEPTSIZ8_RXDPID_STUPCNT(value uint32) {
	volatile.StoreUint32(&o.DOEPTSIZ8.Reg, volatile.LoadUint32(&o.DOEPTSIZ8.Reg)&^(0x60000000)|value<<29)
}
func (o *OTG_HS_Type) GetDOEPTSIZ8_RXDPID_STUPCNT() uint32 {
	return (volatile.LoadUint32(&o.DOEPTSIZ8.Reg) & 0x60000000) >> 29
}

// OTG_HS.DOEPDMA8: OTG device OUT endpoint 8 DMA address register
func (o *OTG_HS_Type) SetDOEPDMA8(value uint32) {
	volatile.StoreUint32(&o.DOEPDMA8.Reg, value)
}
func (o *OTG_HS_Type) GetDOEPDMA8() uint32 {
	return volatile.LoadUint32(&o.DOEPDMA8.Reg)
}

// OTG_HS.PCGCCTL: This register is available in host and device modes.
func (o *OTG_HS_Type) SetPCGCCTL_STPPCLK(value uint32) {
	volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x1)|value)
}
func (o *OTG_HS_Type) GetPCGCCTL_STPPCLK() uint32 {
	return volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x1
}
func (o *OTG_HS_Type) SetPCGCCTL_GATEHCLK(value uint32) {
	volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x2)|value<<1)
}
func (o *OTG_HS_Type) GetPCGCCTL_GATEHCLK() uint32 {
	return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x2) >> 1
}
func (o *OTG_HS_Type) SetPCGCCTL_PHYSUSP(value uint32) {
	volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x10)|value<<4)
}
func (o *OTG_HS_Type) GetPCGCCTL_PHYSUSP() uint32 {
	return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x10) >> 4
}
func (o *OTG_HS_Type) SetPCGCCTL_ENL1GTG(value uint32) {
	volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x20)|value<<5)
}
func (o *OTG_HS_Type) GetPCGCCTL_ENL1GTG() uint32 {
	return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x20) >> 5
}
func (o *OTG_HS_Type) SetPCGCCTL_PHYSLEEP(value uint32) {
	volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x40)|value<<6)
}
func (o *OTG_HS_Type) GetPCGCCTL_PHYSLEEP() uint32 {
	return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x40) >> 6
}
func (o *OTG_HS_Type) SetPCGCCTL_SUSP(value uint32) {
	volatile.StoreUint32(&o.PCGCCTL.Reg, volatile.LoadUint32(&o.PCGCCTL.Reg)&^(0x80)|value<<7)
}
func (o *OTG_HS_Type) GetPCGCCTL_SUSP() uint32 {
	return (volatile.LoadUint32(&o.PCGCCTL.Reg) & 0x80) >> 7
}

// Private key accelerator
type PKA_Type struct {
	CR    volatile.Register32 // 0x0
	SR    volatile.Register32 // 0x4
	CLRFR volatile.Register32 // 0x8
}

// PKA.CR: Control register
func (o *PKA_Type) SetCR_OPERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200000)|value<<21)
}
func (o *PKA_Type) GetCR_OPERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200000) >> 21
}
func (o *PKA_Type) SetCR_ADDRERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *PKA_Type) GetCR_ADDRERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *PKA_Type) SetCR_RAMERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *PKA_Type) GetCR_RAMERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *PKA_Type) SetCR_PROCENDIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *PKA_Type) GetCR_PROCENDIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *PKA_Type) SetCR_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3f00)|value<<8)
}
func (o *PKA_Type) GetCR_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3f00) >> 8
}
func (o *PKA_Type) SetCR_START(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *PKA_Type) GetCR_START() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *PKA_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *PKA_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// PKA.SR: PKA status register
func (o *PKA_Type) SetSR_INITOK(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *PKA_Type) GetSR_INITOK() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *PKA_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *PKA_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *PKA_Type) SetSR_PROCENDF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *PKA_Type) GetSR_PROCENDF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *PKA_Type) SetSR_RAMERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000)|value<<19)
}
func (o *PKA_Type) GetSR_RAMERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000) >> 19
}
func (o *PKA_Type) SetSR_ADDRERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *PKA_Type) GetSR_ADDRERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *PKA_Type) SetSR_OPERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200000)|value<<21)
}
func (o *PKA_Type) GetSR_OPERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200000) >> 21
}

// PKA.CLRFR: PKA clear flag register
func (o *PKA_Type) SetCLRFR_PROCENDFC(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x20000)|value<<17)
}
func (o *PKA_Type) GetCLRFR_PROCENDFC() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x20000) >> 17
}
func (o *PKA_Type) SetCLRFR_RAMERRFC(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x80000)|value<<19)
}
func (o *PKA_Type) GetCLRFR_RAMERRFC() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x80000) >> 19
}
func (o *PKA_Type) SetCLRFR_ADDRERRFC(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x100000)|value<<20)
}
func (o *PKA_Type) GetCLRFR_ADDRERRFC() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x100000) >> 20
}
func (o *PKA_Type) SetCLRFR_OPERRFC(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x200000)|value<<21)
}
func (o *PKA_Type) GetCLRFR_OPERRFC() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x200000) >> 21
}

// PSSI
type PSSI_Type struct {
	CR  volatile.Register32 // 0x0
	SR  volatile.Register32 // 0x4
	RIS volatile.Register32 // 0x8
	IER volatile.Register32 // 0xC
	MIS volatile.Register32 // 0x10
	ICR volatile.Register32 // 0x14
	_   [16]byte
	DR  volatile.Register32 // 0x28
}

// PSSI.CR: PSSI control register
func (o *PSSI_Type) SetCR_CKPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *PSSI_Type) GetCR_CKPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *PSSI_Type) SetCR_DEPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *PSSI_Type) GetCR_DEPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *PSSI_Type) SetCR_RDYPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *PSSI_Type) GetCR_RDYPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *PSSI_Type) SetCR_EDM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00)|value<<10)
}
func (o *PSSI_Type) GetCR_EDM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00) >> 10
}
func (o *PSSI_Type) SetCR_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *PSSI_Type) GetCR_ENABLE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *PSSI_Type) SetCR_DERDYCFG(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1c0000)|value<<18)
}
func (o *PSSI_Type) GetCR_DERDYCFG() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1c0000) >> 18
}
func (o *PSSI_Type) SetCR_DMAEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *PSSI_Type) GetCR_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *PSSI_Type) SetCR_OUTEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *PSSI_Type) GetCR_OUTEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// PSSI.SR: PSSI status register
func (o *PSSI_Type) SetSR_RTT4B(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *PSSI_Type) GetSR_RTT4B() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *PSSI_Type) SetSR_RTT1B(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *PSSI_Type) GetSR_RTT1B() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}

// PSSI.RIS: PSSI raw interrupt status register
func (o *PSSI_Type) SetRIS_OVR_RIS(value uint32) {
	volatile.StoreUint32(&o.RIS.Reg, volatile.LoadUint32(&o.RIS.Reg)&^(0x2)|value<<1)
}
func (o *PSSI_Type) GetRIS_OVR_RIS() uint32 {
	return (volatile.LoadUint32(&o.RIS.Reg) & 0x2) >> 1
}

// PSSI.IER: PSSI interrupt enable register
func (o *PSSI_Type) SetIER_OVR_IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *PSSI_Type) GetIER_OVR_IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}

// PSSI.MIS: PSSI masked interrupt status register
func (o *PSSI_Type) SetMIS_OVR_MIS(value uint32) {
	volatile.StoreUint32(&o.MIS.Reg, volatile.LoadUint32(&o.MIS.Reg)&^(0x2)|value<<1)
}
func (o *PSSI_Type) GetMIS_OVR_MIS() uint32 {
	return (volatile.LoadUint32(&o.MIS.Reg) & 0x2) >> 1
}

// PSSI.ICR: PSSI interrupt clear register
func (o *PSSI_Type) SetICR_OVR_ISC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *PSSI_Type) GetICR_OVR_ISC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}

// PSSI.DR: PSSI data register
func (o *PSSI_Type) SetDR_BYTE0(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xff)|value)
}
func (o *PSSI_Type) GetDR_BYTE0() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xff
}
func (o *PSSI_Type) SetDR_BYTE1(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xff00)|value<<8)
}
func (o *PSSI_Type) GetDR_BYTE1() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xff00) >> 8
}
func (o *PSSI_Type) SetDR_BYTE2(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xff0000)|value<<16)
}
func (o *PSSI_Type) GetDR_BYTE2() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xff0000) >> 16
}
func (o *PSSI_Type) SetDR_BYTE3(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xff000000)|value<<24)
}
func (o *PSSI_Type) GetDR_BYTE3() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xff000000) >> 24
}

// Power control
type PWR_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	CR3      volatile.Register32 // 0x8
	VOSR     volatile.Register32 // 0xC
	SVMCR    volatile.Register32 // 0x10
	WUCR1    volatile.Register32 // 0x14
	WUCR2    volatile.Register32 // 0x18
	WUCR3    volatile.Register32 // 0x1C
	BDCR1    volatile.Register32 // 0x20
	BDCR2    volatile.Register32 // 0x24
	DBPR     volatile.Register32 // 0x28
	UCPDR    volatile.Register32 // 0x2C
	SECCFGR  volatile.Register32 // 0x30
	PRIVCFGR volatile.Register32 // 0x34
	SR       volatile.Register32 // 0x38
	SVMSR    volatile.Register32 // 0x3C
	BDSR     volatile.Register32 // 0x40
	WUSR     volatile.Register32 // 0x44
	WUSCR    volatile.Register32 // 0x48
	APCR     volatile.Register32 // 0x4C
	PUCRA    volatile.Register32 // 0x50
	PDCRA    volatile.Register32 // 0x54
	PUCRB    volatile.Register32 // 0x58
	PDCRB    volatile.Register32 // 0x5C
	PUCRC    volatile.Register32 // 0x60
	PDCRC    volatile.Register32 // 0x64
	PUCRD    volatile.Register32 // 0x68
	PDCRD    volatile.Register32 // 0x6C
	PUCRE    volatile.Register32 // 0x70
	PDCRE    volatile.Register32 // 0x74
	PUCRF    volatile.Register32 // 0x78
	PDCRF    volatile.Register32 // 0x7C
	PUCRG    volatile.Register32 // 0x80
	PDCRG    volatile.Register32 // 0x84
	PUCRH    volatile.Register32 // 0x88
	PDCRH    volatile.Register32 // 0x8C
	PUCRI    volatile.Register32 // 0x90
	PDCRI    volatile.Register32 // 0x94
	PUCRJ    volatile.Register32 // 0x98
	PDCRJ    volatile.Register32 // 0x9C
	_        [8]byte
	CR4      volatile.Register32 // 0xA8
	CR5      volatile.Register32 // 0xAC
}

// PWR.CR1: PWR control register 1
func (o *PWR_Type) SetCR1_LPMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x7)|value)
}
func (o *PWR_Type) GetCR1_LPMS() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x7
}
func (o *PWR_Type) SetCR1_RRSB1(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetCR1_RRSB1() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetCR1_RRSB2(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetCR1_RRSB2() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetCR1_ULPMEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetCR1_ULPMEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetCR1_SRAM1PD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetCR1_SRAM1PD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetCR1_SRAM2PD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetCR1_SRAM2PD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetCR1_SRAM3PD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetCR1_SRAM3PD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetCR1_SRAM4PD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetCR1_SRAM4PD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetCR1_SRAM5PD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetCR1_SRAM5PD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetCR1_FORCE_USBPWR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetCR1_FORCE_USBPWR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}

// PWR.CR2: PWR control register 2
func (o *PWR_Type) SetCR2_SRAM1PDS1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetCR2_SRAM1PDS1() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *PWR_Type) SetCR2_SRAM1PDS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetCR2_SRAM1PDS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetCR2_SRAM1PDS3(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetCR2_SRAM1PDS3() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetCR2_SRAM2PDS1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR2_SRAM2PDS1() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR2_SRAM2PDS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetCR2_SRAM2PDS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetCR2_SRAM4PDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetCR2_SRAM4PDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetCR2_ICRAMPDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetCR2_ICRAMPDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetCR2_DC1RAMPDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetCR2_DC1RAMPDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetCR2_DMA2DRAMPDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetCR2_DMA2DRAMPDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetCR2_PRAMPDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetCR2_PRAMPDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetCR2_PKARAMPDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetCR2_PKARAMPDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetCR2_SRAM4FWU(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetCR2_SRAM4FWU() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetCR2_FLASHFWU(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetCR2_FLASHFWU() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetCR2_SRAM3PDS1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *PWR_Type) GetCR2_SRAM3PDS1() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *PWR_Type) SetCR2_SRAM3PDS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *PWR_Type) GetCR2_SRAM3PDS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *PWR_Type) SetCR2_SRAM3PDS3(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *PWR_Type) GetCR2_SRAM3PDS3() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *PWR_Type) SetCR2_SRAM3PDS4(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000)|value<<19)
}
func (o *PWR_Type) GetCR2_SRAM3PDS4() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000) >> 19
}
func (o *PWR_Type) SetCR2_SRAM3PDS5(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *PWR_Type) GetCR2_SRAM3PDS5() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *PWR_Type) SetCR2_SRAM3PDS6(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200000)|value<<21)
}
func (o *PWR_Type) GetCR2_SRAM3PDS6() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200000) >> 21
}
func (o *PWR_Type) SetCR2_SRAM3PDS7(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400000)|value<<22)
}
func (o *PWR_Type) GetCR2_SRAM3PDS7() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400000) >> 22
}
func (o *PWR_Type) SetCR2_SRAM3PDS8(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800000)|value<<23)
}
func (o *PWR_Type) GetCR2_SRAM3PDS8() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800000) >> 23
}
func (o *PWR_Type) SetCR2_SRDRUN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000000)|value<<31)
}
func (o *PWR_Type) GetCR2_SRDRUN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000000) >> 31
}

// PWR.CR3: PWR control register 3
func (o *PWR_Type) SetCR3_REGSEL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetCR3_REGSEL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetCR3_FSTEN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetCR3_FSTEN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}

// PWR.VOSR: PWR voltage scaling register
func (o *PWR_Type) SetVOSR_USBBOOSTRDY(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetVOSR_USBBOOSTRDY() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetVOSR_BOOSTRDY(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetVOSR_BOOSTRDY() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetVOSR_VOSRDY(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetVOSR_VOSRDY() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetVOSR_VOS(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x30000)|value<<16)
}
func (o *PWR_Type) GetVOSR_VOS() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x30000) >> 16
}
func (o *PWR_Type) SetVOSR_BOOSTEN(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x40000)|value<<18)
}
func (o *PWR_Type) GetVOSR_BOOSTEN() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x40000) >> 18
}
func (o *PWR_Type) SetVOSR_USBPWREN(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x80000)|value<<19)
}
func (o *PWR_Type) GetVOSR_USBPWREN() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x80000) >> 19
}
func (o *PWR_Type) SetVOSR_USBBOOSTEN(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x100000)|value<<20)
}
func (o *PWR_Type) GetVOSR_USBBOOSTEN() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x100000) >> 20
}
func (o *PWR_Type) SetVOSR_VDD11USBDIS(value uint32) {
	volatile.StoreUint32(&o.VOSR.Reg, volatile.LoadUint32(&o.VOSR.Reg)&^(0x200000)|value<<21)
}
func (o *PWR_Type) GetVOSR_VDD11USBDIS() uint32 {
	return (volatile.LoadUint32(&o.VOSR.Reg) & 0x200000) >> 21
}

// PWR.SVMCR: PWR supply voltage monitoring control register
func (o *PWR_Type) SetSVMCR_PVDE(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSVMCR_PVDE() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSVMCR_PVDLS(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0xe0)|value<<5)
}
func (o *PWR_Type) GetSVMCR_PVDLS() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0xe0) >> 5
}
func (o *PWR_Type) SetSVMCR_UVMEN(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x1000000)|value<<24)
}
func (o *PWR_Type) GetSVMCR_UVMEN() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x1000000) >> 24
}
func (o *PWR_Type) SetSVMCR_IO2VMEN(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x2000000)|value<<25)
}
func (o *PWR_Type) GetSVMCR_IO2VMEN() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x2000000) >> 25
}
func (o *PWR_Type) SetSVMCR_AVM1EN(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x4000000)|value<<26)
}
func (o *PWR_Type) GetSVMCR_AVM1EN() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x4000000) >> 26
}
func (o *PWR_Type) SetSVMCR_AVM2EN(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x8000000)|value<<27)
}
func (o *PWR_Type) GetSVMCR_AVM2EN() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x8000000) >> 27
}
func (o *PWR_Type) SetSVMCR_USV(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x10000000)|value<<28)
}
func (o *PWR_Type) GetSVMCR_USV() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x10000000) >> 28
}
func (o *PWR_Type) SetSVMCR_IO2SV(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x20000000)|value<<29)
}
func (o *PWR_Type) GetSVMCR_IO2SV() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x20000000) >> 29
}
func (o *PWR_Type) SetSVMCR_ASV(value uint32) {
	volatile.StoreUint32(&o.SVMCR.Reg, volatile.LoadUint32(&o.SVMCR.Reg)&^(0x40000000)|value<<30)
}
func (o *PWR_Type) GetSVMCR_ASV() uint32 {
	return (volatile.LoadUint32(&o.SVMCR.Reg) & 0x40000000) >> 30
}

// PWR.WUCR1: PWR wakeup control register 1
func (o *PWR_Type) SetWUCR1_WUPEN1(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetWUCR1_WUPEN1() uint32 {
	return volatile.LoadUint32(&o.WUCR1.Reg) & 0x1
}
func (o *PWR_Type) SetWUCR1_WUPEN2(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetWUCR1_WUPEN2() uint32 {
	return (volatile.LoadUint32(&o.WUCR1.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetWUCR1_WUPEN3(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetWUCR1_WUPEN3() uint32 {
	return (volatile.LoadUint32(&o.WUCR1.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetWUCR1_WUPEN4(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetWUCR1_WUPEN4() uint32 {
	return (volatile.LoadUint32(&o.WUCR1.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetWUCR1_WUPEN5(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetWUCR1_WUPEN5() uint32 {
	return (volatile.LoadUint32(&o.WUCR1.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetWUCR1_WUPEN6(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetWUCR1_WUPEN6() uint32 {
	return (volatile.LoadUint32(&o.WUCR1.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetWUCR1_WUPEN7(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetWUCR1_WUPEN7() uint32 {
	return (volatile.LoadUint32(&o.WUCR1.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetWUCR1_WUPEN8(value uint32) {
	volatile.StoreUint32(&o.WUCR1.Reg, volatile.LoadUint32(&o.WUCR1.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetWUCR1_WUPEN8() uint32 {
	return (volatile.LoadUint32(&o.WUCR1.Reg) & 0x80) >> 7
}

// PWR.WUCR2: PWR wakeup control register 2
func (o *PWR_Type) SetWUCR2_WUPP1(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetWUCR2_WUPP1() uint32 {
	return volatile.LoadUint32(&o.WUCR2.Reg) & 0x1
}
func (o *PWR_Type) SetWUCR2_WUPP2(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetWUCR2_WUPP2() uint32 {
	return (volatile.LoadUint32(&o.WUCR2.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetWUCR2_WUPP3(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetWUCR2_WUPP3() uint32 {
	return (volatile.LoadUint32(&o.WUCR2.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetWUCR2_WUPP4(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetWUCR2_WUPP4() uint32 {
	return (volatile.LoadUint32(&o.WUCR2.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetWUCR2_WUPP5(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetWUCR2_WUPP5() uint32 {
	return (volatile.LoadUint32(&o.WUCR2.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetWUCR2_WUPP6(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetWUCR2_WUPP6() uint32 {
	return (volatile.LoadUint32(&o.WUCR2.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetWUCR2_WUPP7(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetWUCR2_WUPP7() uint32 {
	return (volatile.LoadUint32(&o.WUCR2.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetWUCR2_WUPP8(value uint32) {
	volatile.StoreUint32(&o.WUCR2.Reg, volatile.LoadUint32(&o.WUCR2.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetWUCR2_WUPP8() uint32 {
	return (volatile.LoadUint32(&o.WUCR2.Reg) & 0x80) >> 7
}

// PWR.WUCR3: PWR wakeup control register 3
func (o *PWR_Type) SetWUCR3_WUSEL1(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0x3)|value)
}
func (o *PWR_Type) GetWUCR3_WUSEL1() uint32 {
	return volatile.LoadUint32(&o.WUCR3.Reg) & 0x3
}
func (o *PWR_Type) SetWUCR3_WUSEL2(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0xc)|value<<2)
}
func (o *PWR_Type) GetWUCR3_WUSEL2() uint32 {
	return (volatile.LoadUint32(&o.WUCR3.Reg) & 0xc) >> 2
}
func (o *PWR_Type) SetWUCR3_WUSEL3(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0x30)|value<<4)
}
func (o *PWR_Type) GetWUCR3_WUSEL3() uint32 {
	return (volatile.LoadUint32(&o.WUCR3.Reg) & 0x30) >> 4
}
func (o *PWR_Type) SetWUCR3_WUSEL4(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0xc0)|value<<6)
}
func (o *PWR_Type) GetWUCR3_WUSEL4() uint32 {
	return (volatile.LoadUint32(&o.WUCR3.Reg) & 0xc0) >> 6
}
func (o *PWR_Type) SetWUCR3_WUSEL5(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0x300)|value<<8)
}
func (o *PWR_Type) GetWUCR3_WUSEL5() uint32 {
	return (volatile.LoadUint32(&o.WUCR3.Reg) & 0x300) >> 8
}
func (o *PWR_Type) SetWUCR3_WUSEL6(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0xc00)|value<<10)
}
func (o *PWR_Type) GetWUCR3_WUSEL6() uint32 {
	return (volatile.LoadUint32(&o.WUCR3.Reg) & 0xc00) >> 10
}
func (o *PWR_Type) SetWUCR3_WUSEL7(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0x3000)|value<<12)
}
func (o *PWR_Type) GetWUCR3_WUSEL7() uint32 {
	return (volatile.LoadUint32(&o.WUCR3.Reg) & 0x3000) >> 12
}
func (o *PWR_Type) SetWUCR3_WUSEL8(value uint32) {
	volatile.StoreUint32(&o.WUCR3.Reg, volatile.LoadUint32(&o.WUCR3.Reg)&^(0xc000)|value<<14)
}
func (o *PWR_Type) GetWUCR3_WUSEL8() uint32 {
	return (volatile.LoadUint32(&o.WUCR3.Reg) & 0xc000) >> 14
}

// PWR.BDCR1: PWR Backup domain control register 1
func (o *PWR_Type) SetBDCR1_BREN(value uint32) {
	volatile.StoreUint32(&o.BDCR1.Reg, volatile.LoadUint32(&o.BDCR1.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetBDCR1_BREN() uint32 {
	return volatile.LoadUint32(&o.BDCR1.Reg) & 0x1
}
func (o *PWR_Type) SetBDCR1_MONEN(value uint32) {
	volatile.StoreUint32(&o.BDCR1.Reg, volatile.LoadUint32(&o.BDCR1.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetBDCR1_MONEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR1.Reg) & 0x10) >> 4
}

// PWR.BDCR2: PWR Backup domain control register 2
func (o *PWR_Type) SetBDCR2_VBE(value uint32) {
	volatile.StoreUint32(&o.BDCR2.Reg, volatile.LoadUint32(&o.BDCR2.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetBDCR2_VBE() uint32 {
	return volatile.LoadUint32(&o.BDCR2.Reg) & 0x1
}
func (o *PWR_Type) SetBDCR2_VBRS(value uint32) {
	volatile.StoreUint32(&o.BDCR2.Reg, volatile.LoadUint32(&o.BDCR2.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetBDCR2_VBRS() uint32 {
	return (volatile.LoadUint32(&o.BDCR2.Reg) & 0x2) >> 1
}

// PWR.DBPR: PWR disable Backup domain register
func (o *PWR_Type) SetDBPR_DBP(value uint32) {
	volatile.StoreUint32(&o.DBPR.Reg, volatile.LoadUint32(&o.DBPR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetDBPR_DBP() uint32 {
	return volatile.LoadUint32(&o.DBPR.Reg) & 0x1
}

// PWR.UCPDR: PWR USB Type-C™ and Power Delivery register
func (o *PWR_Type) SetUCPDR_UCPD_DBDIS(value uint32) {
	volatile.StoreUint32(&o.UCPDR.Reg, volatile.LoadUint32(&o.UCPDR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetUCPDR_UCPD_DBDIS() uint32 {
	return volatile.LoadUint32(&o.UCPDR.Reg) & 0x1
}
func (o *PWR_Type) SetUCPDR_UCPD_STBY(value uint32) {
	volatile.StoreUint32(&o.UCPDR.Reg, volatile.LoadUint32(&o.UCPDR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetUCPDR_UCPD_STBY() uint32 {
	return (volatile.LoadUint32(&o.UCPDR.Reg) & 0x2) >> 1
}

// PWR.SECCFGR: PWR security configuration register
func (o *PWR_Type) SetSECCFGR_WUP1SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetSECCFGR_WUP1SEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}
func (o *PWR_Type) SetSECCFGR_WUP2SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSECCFGR_WUP2SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSECCFGR_WUP3SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetSECCFGR_WUP3SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetSECCFGR_WUP4SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetSECCFGR_WUP4SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetSECCFGR_WUP5SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSECCFGR_WUP5SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSECCFGR_WUP6SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetSECCFGR_WUP6SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetSECCFGR_WUP7SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetSECCFGR_WUP7SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetSECCFGR_WUP8SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetSECCFGR_WUP8SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetSECCFGR_LPMSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetSECCFGR_LPMSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetSECCFGR_VDMSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetSECCFGR_VDMSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetSECCFGR_VBSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetSECCFGR_VBSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetSECCFGR_APCSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetSECCFGR_APCSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8000) >> 15
}

// PWR.PRIVCFGR: PWR privilege control register
func (o *PWR_Type) SetPRIVCFGR_SPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPRIVCFGR_SPRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x1
}
func (o *PWR_Type) SetPRIVCFGR_NSPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPRIVCFGR_NSPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x2) >> 1
}

// PWR.SR: PWR status register
func (o *PWR_Type) SetSR_CSSF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetSR_CSSF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *PWR_Type) SetSR_STOPF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSR_STOPF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSR_SBF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetSR_SBF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}

// PWR.SVMSR: PWR supply voltage monitoring status register
func (o *PWR_Type) SetSVMSR_REGS(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSVMSR_REGS() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSVMSR_PVDO(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSVMSR_PVDO() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSVMSR_ACTVOSRDY(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetSVMSR_ACTVOSRDY() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetSVMSR_ACTVOS(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x30000)|value<<16)
}
func (o *PWR_Type) GetSVMSR_ACTVOS() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x30000) >> 16
}
func (o *PWR_Type) SetSVMSR_VDDUSBRDY(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x1000000)|value<<24)
}
func (o *PWR_Type) GetSVMSR_VDDUSBRDY() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x1000000) >> 24
}
func (o *PWR_Type) SetSVMSR_VDDIO2RDY(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x2000000)|value<<25)
}
func (o *PWR_Type) GetSVMSR_VDDIO2RDY() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x2000000) >> 25
}
func (o *PWR_Type) SetSVMSR_VDDA1RDY(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x4000000)|value<<26)
}
func (o *PWR_Type) GetSVMSR_VDDA1RDY() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x4000000) >> 26
}
func (o *PWR_Type) SetSVMSR_VDDA2RDY(value uint32) {
	volatile.StoreUint32(&o.SVMSR.Reg, volatile.LoadUint32(&o.SVMSR.Reg)&^(0x8000000)|value<<27)
}
func (o *PWR_Type) GetSVMSR_VDDA2RDY() uint32 {
	return (volatile.LoadUint32(&o.SVMSR.Reg) & 0x8000000) >> 27
}

// PWR.BDSR: PWR Backup domain status register
func (o *PWR_Type) SetBDSR_VBATH(value uint32) {
	volatile.StoreUint32(&o.BDSR.Reg, volatile.LoadUint32(&o.BDSR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetBDSR_VBATH() uint32 {
	return (volatile.LoadUint32(&o.BDSR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetBDSR_TEMPL(value uint32) {
	volatile.StoreUint32(&o.BDSR.Reg, volatile.LoadUint32(&o.BDSR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetBDSR_TEMPL() uint32 {
	return (volatile.LoadUint32(&o.BDSR.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetBDSR_TEMPH(value uint32) {
	volatile.StoreUint32(&o.BDSR.Reg, volatile.LoadUint32(&o.BDSR.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetBDSR_TEMPH() uint32 {
	return (volatile.LoadUint32(&o.BDSR.Reg) & 0x8) >> 3
}

// PWR.WUSR: PWR wakeup status register
func (o *PWR_Type) SetWUSR_WUF1(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetWUSR_WUF1() uint32 {
	return volatile.LoadUint32(&o.WUSR.Reg) & 0x1
}
func (o *PWR_Type) SetWUSR_WUF2(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetWUSR_WUF2() uint32 {
	return (volatile.LoadUint32(&o.WUSR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetWUSR_WUF3(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetWUSR_WUF3() uint32 {
	return (volatile.LoadUint32(&o.WUSR.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetWUSR_WUF4(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetWUSR_WUF4() uint32 {
	return (volatile.LoadUint32(&o.WUSR.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetWUSR_WUF5(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetWUSR_WUF5() uint32 {
	return (volatile.LoadUint32(&o.WUSR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetWUSR_WUF6(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetWUSR_WUF6() uint32 {
	return (volatile.LoadUint32(&o.WUSR.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetWUSR_WUF7(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetWUSR_WUF7() uint32 {
	return (volatile.LoadUint32(&o.WUSR.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetWUSR_WUF8(value uint32) {
	volatile.StoreUint32(&o.WUSR.Reg, volatile.LoadUint32(&o.WUSR.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetWUSR_WUF8() uint32 {
	return (volatile.LoadUint32(&o.WUSR.Reg) & 0x80) >> 7
}

// PWR.WUSCR: PWR wakeup status clear register
func (o *PWR_Type) SetWUSCR_CWUF1(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetWUSCR_CWUF1() uint32 {
	return volatile.LoadUint32(&o.WUSCR.Reg) & 0x1
}
func (o *PWR_Type) SetWUSCR_CWUF2(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetWUSCR_CWUF2() uint32 {
	return (volatile.LoadUint32(&o.WUSCR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetWUSCR_CWUF3(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetWUSCR_CWUF3() uint32 {
	return (volatile.LoadUint32(&o.WUSCR.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetWUSCR_CWUF4(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetWUSCR_CWUF4() uint32 {
	return (volatile.LoadUint32(&o.WUSCR.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetWUSCR_CWUF5(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetWUSCR_CWUF5() uint32 {
	return (volatile.LoadUint32(&o.WUSCR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetWUSCR_CWUF6(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetWUSCR_CWUF6() uint32 {
	return (volatile.LoadUint32(&o.WUSCR.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetWUSCR_CWUF7(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetWUSCR_CWUF7() uint32 {
	return (volatile.LoadUint32(&o.WUSCR.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetWUSCR_CWUF8(value uint32) {
	volatile.StoreUint32(&o.WUSCR.Reg, volatile.LoadUint32(&o.WUSCR.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetWUSCR_CWUF8() uint32 {
	return (volatile.LoadUint32(&o.WUSCR.Reg) & 0x80) >> 7
}

// PWR.APCR: PWR apply pull configuration register
func (o *PWR_Type) SetAPCR_APC(value uint32) {
	volatile.StoreUint32(&o.APCR.Reg, volatile.LoadUint32(&o.APCR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetAPCR_APC() uint32 {
	return volatile.LoadUint32(&o.APCR.Reg) & 0x1
}

// PWR.PUCRA: PWR port A pull-up control register
func (o *PWR_Type) SetPUCRA_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRA_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRA.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRA_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRA_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRA_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRA_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRA_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRA_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRA_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRA_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRA_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRA_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRA_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRA_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRA_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRA_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRA_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRA_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRA_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRA_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRA_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRA_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRA_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRA_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRA_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRA_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRA_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRA_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRA_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRA_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x8000) >> 15
}

// PWR.PDCRA: PWR port A pull-down control register
func (o *PWR_Type) SetPDCRA_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRA_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRA.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRA_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRA_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRA_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRA_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRA_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRA_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRA_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRA_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRA_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRA_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRA_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRA_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRA_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRA_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRA_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRA_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRA_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRA_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRA_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRA_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRA_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRA_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRA_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRA_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRA_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRA_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x4000) >> 14
}

// PWR.PUCRB: PWR port B pull-up control register
func (o *PWR_Type) SetPUCRB_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRB_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRB.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRB_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRB_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRB_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRB_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRB_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRB_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRB_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRB_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRB_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRB_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRB_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRB_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRB_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRB_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRB_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRB_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRB_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRB_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRB_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRB_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRB_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRB_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRB_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRB_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRB_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRB_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRB_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRB_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRB_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRB_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x8000) >> 15
}

// PWR.PDCRB: PWR port B pull-down control register
func (o *PWR_Type) SetPDCRB_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRB_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRB.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRB_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRB_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRB_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRB_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRB_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRB_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRB_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRB_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRB_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRB_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRB_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRB_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRB_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRB_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRB_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRB_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRB_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRB_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRB_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRB_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRB_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRB_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRB_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRB_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRB_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRB_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRB_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRB_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x8000) >> 15
}

// PWR.PUCRC: Power port C pull up control register
func (o *PWR_Type) SetPUCRC_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRC_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRC.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRC_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRC_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRC_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRC_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRC_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRC_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRC_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRC_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRC_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRC_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRC_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRC_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRC_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRC_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRC_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRC_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRC_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRC_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRC_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRC_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRC_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRC_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRC_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRC_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRC_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRC_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRC_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRC_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRC_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRC_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x8000) >> 15
}

// PWR.PDCRC: PWR port C pull-down control register
func (o *PWR_Type) SetPDCRC_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRC_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRC.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRC_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRC_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRC_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRC_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRC_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRC_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRC_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRC_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRC_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRC_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRC_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRC_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRC_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRC_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRC_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRC_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRC_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRC_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRC_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRC_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRC_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRC_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRC_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRC_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRC_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRC_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRC_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRC_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRC_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRC_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x8000) >> 15
}

// PWR.PUCRD: PWR port D pull-up control register
func (o *PWR_Type) SetPUCRD_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRD_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRD.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRD_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRD_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRD_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRD_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRD_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRD_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRD_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRD_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRD_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRD_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRD_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRD_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRD_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRD_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRD_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRD_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRD_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRD_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRD_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRD_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRD_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRD_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRD_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRD_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRD_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRD_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRD_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRD_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRD_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRD_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x8000) >> 15
}

// PWR.PDCRD: PWR port D pull-down control register
func (o *PWR_Type) SetPDCRD_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRD_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRD.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRD_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRD_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRD_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRD_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRD_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRD_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRD_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRD_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRD_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRD_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRD_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRD_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRD_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRD_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRD_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRD_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRD_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRD_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRD_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRD_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRD_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRD_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRD_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRD_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRD_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRD_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRD_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRD_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRD_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRD_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x8000) >> 15
}

// PWR.PUCRE: PWR port E pull-up control register
func (o *PWR_Type) SetPUCRE_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRE_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRE.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRE_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRE_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRE_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRE_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRE_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRE_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRE_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRE_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRE_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRE_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRE_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRE_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRE_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRE_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRE_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRE_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRE_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRE_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRE_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRE_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRE_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRE_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRE_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRE_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRE_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRE_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRE_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRE_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRE_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRE_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x8000) >> 15
}

// PWR.PDCRE: PWR port E pull-down control register
func (o *PWR_Type) SetPDCRE_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRE_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRE.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRE_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRE_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRE_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRE_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRE_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRE_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRE_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRE_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRE_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRE_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRE_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRE_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRE_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRE_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRE_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRE_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRE_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRE_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRE_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRE_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRE_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRE_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRE_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRE_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRE_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRE_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRE_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRE_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRE_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRE_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x8000) >> 15
}

// PWR.PUCRF: PWR port F pull-up control register
func (o *PWR_Type) SetPUCRF_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRF_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRF.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRF_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRF_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRF_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRF_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRF_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRF_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRF_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRF_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRF_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRF_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRF_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRF_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRF_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRF_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRF_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRF_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRF_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRF_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRF_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRF_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRF_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRF_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRF_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRF_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRF_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRF_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRF_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRF_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRF_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRF_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x8000) >> 15
}

// PWR.PDCRF: PWR port F pull-down control register
func (o *PWR_Type) SetPDCRF_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRF_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRF.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRF_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRF_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRF_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRF_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRF_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRF_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRF_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRF_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRF_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRF_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRF_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRF_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRF_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRF_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRF_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRF_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRF_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRF_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRF_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRF_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRF_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRF_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRF_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRF_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRF_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRF_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRF_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRF_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRF_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRF_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x8000) >> 15
}

// PWR.PUCRG: PWR port G pull-up control register
func (o *PWR_Type) SetPUCRG_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRG_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRG.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRG_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRG_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRG_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRG_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRG_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRG_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRG_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRG_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRG_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRG_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRG_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRG_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRG_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRG_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRG_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRG_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRG_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRG_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRG_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRG_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRG_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRG_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRG_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRG_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRG_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRG_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRG_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRG_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRG_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRG_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x8000) >> 15
}

// PWR.PDCRG: PWR port G pull-down control register
func (o *PWR_Type) SetPDCRG_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRG_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRG.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRG_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRG_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRG_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRG_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRG_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRG_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRG_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRG_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRG_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRG_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRG_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRG_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRG_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRG_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRG_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRG_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRG_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRG_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRG_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRG_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRG_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRG_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRG_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRG_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRG_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRG_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRG_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRG_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRG_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRG_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x8000) >> 15
}

// PWR.PUCRH: PWR port H pull-up control register
func (o *PWR_Type) SetPUCRH_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRH_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRH.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRH_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRH_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRH_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRH_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRH_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRH_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRH_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRH_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRH_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRH_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRH_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRH_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRH_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRH_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRH_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRH_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRH_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRH_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRH_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRH_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRH_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRH_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRH_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRH_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRH_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRH_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRH_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRH_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRH_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRH_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x8000) >> 15
}

// PWR.PDCRH: PWR port H pull-down control register
func (o *PWR_Type) SetPDCRH_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRH_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRH.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRH_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRH_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRH_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRH_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRH_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRH_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRH_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRH_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRH_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRH_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRH_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRH_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRH_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRH_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRH_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRH_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRH_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRH_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRH_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRH_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRH_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRH_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRH_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRH_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRH_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRH_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRH_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRH_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRH_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRH_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x8000) >> 15
}

// PWR.PUCRI: PWR port I pull-up control register
func (o *PWR_Type) SetPUCRI_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRI_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRI.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRI_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRI_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRI_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRI_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRI_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRI_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRI_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRI_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRI_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRI_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRI_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRI_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRI_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRI_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRI_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRI_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRI_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRI_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRI_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRI_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRI_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRI_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRI_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRI_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRI_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRI_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRI_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRI_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRI_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRI.Reg, volatile.LoadUint32(&o.PUCRI.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRI_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRI.Reg) & 0x8000) >> 15
}

// PWR.PDCRI: PWR port I pull-down control register
func (o *PWR_Type) SetPDCRI_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRI_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRI.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRI_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRI_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRI_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRI_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRI_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRI_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRI_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRI_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRI_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRI_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRI_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRI_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRI_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRI_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRI_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRI_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRI_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRI_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRI_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRI_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRI_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRI_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRI_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRI_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRI_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRI_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRI_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRI_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRI_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRI.Reg, volatile.LoadUint32(&o.PDCRI.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRI_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRI.Reg) & 0x8000) >> 15
}

// PWR.PUCRJ: PWR port J pull-up control register
func (o *PWR_Type) SetPUCRJ_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRJ_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRJ.Reg) & 0x1
}
func (o *PWR_Type) SetPUCRJ_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRJ_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRJ_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRJ_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRJ_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRJ_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRJ_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRJ_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRJ_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRJ_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRJ_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRJ_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRJ_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRJ_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRJ_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRJ_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRJ_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRJ_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRJ_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRJ_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRJ_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRJ.Reg, volatile.LoadUint32(&o.PUCRJ.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRJ_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRJ.Reg) & 0x800) >> 11
}

// PWR.PDCRJ: PWR port J pull-down control register
func (o *PWR_Type) SetPDCRJ_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRJ_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRJ.Reg) & 0x1
}
func (o *PWR_Type) SetPDCRJ_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRJ_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRJ_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRJ_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRJ_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRJ_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRJ_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRJ_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRJ_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRJ_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRJ_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRJ_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRJ_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRJ_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRJ_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRJ_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRJ_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRJ_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRJ_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRJ_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRJ_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRJ.Reg, volatile.LoadUint32(&o.PDCRJ.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRJ_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRJ.Reg) & 0x800) >> 11
}

// PWR.CR4: PWR control register 4
func (o *PWR_Type) SetCR4_SRAM1PDS4(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetCR4_SRAM1PDS4() uint32 {
	return volatile.LoadUint32(&o.CR4.Reg) & 0x1
}
func (o *PWR_Type) SetCR4_SRAM1PDS5(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetCR4_SRAM1PDS5() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetCR4_SRAM1PDS6(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetCR4_SRAM1PDS6() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetCR4_SRAM1PDS7(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetCR4_SRAM1PDS7() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetCR4_SRAM1PDS8(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR4_SRAM1PDS8() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR4_SRAM1PDS9(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetCR4_SRAM1PDS9() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetCR4_SRAM1PDS10(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetCR4_SRAM1PDS10() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetCR4_SRAM1PDS11(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetCR4_SRAM1PDS11() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetCR4_SRAM1PDS12(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetCR4_SRAM1PDS12() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetCR4_SRAM3PDS9(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetCR4_SRAM3PDS9() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetCR4_SRAM3PDS10(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetCR4_SRAM3PDS10() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetCR4_SRAM3PDS11(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetCR4_SRAM3PDS11() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetCR4_SRAM3PDS12(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetCR4_SRAM3PDS12() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetCR4_SRAM3PDS13(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetCR4_SRAM3PDS13() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetCR4_SRAM5PDS1(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x10000)|value<<16)
}
func (o *PWR_Type) GetCR4_SRAM5PDS1() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x10000) >> 16
}
func (o *PWR_Type) SetCR4_SRAM5PDS2(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x20000)|value<<17)
}
func (o *PWR_Type) GetCR4_SRAM5PDS2() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x20000) >> 17
}
func (o *PWR_Type) SetCR4_SRAM5PDS3(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x40000)|value<<18)
}
func (o *PWR_Type) GetCR4_SRAM5PDS3() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x40000) >> 18
}
func (o *PWR_Type) SetCR4_SRAM5PDS4(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x80000)|value<<19)
}
func (o *PWR_Type) GetCR4_SRAM5PDS4() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x80000) >> 19
}
func (o *PWR_Type) SetCR4_SRAM5PDS5(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x100000)|value<<20)
}
func (o *PWR_Type) GetCR4_SRAM5PDS5() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x100000) >> 20
}
func (o *PWR_Type) SetCR4_SRAM5PDS6(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x200000)|value<<21)
}
func (o *PWR_Type) GetCR4_SRAM5PDS6() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x200000) >> 21
}
func (o *PWR_Type) SetCR4_SRAM5PDS7(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x400000)|value<<22)
}
func (o *PWR_Type) GetCR4_SRAM5PDS7() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x400000) >> 22
}
func (o *PWR_Type) SetCR4_SRAM5PDS8(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x800000)|value<<23)
}
func (o *PWR_Type) GetCR4_SRAM5PDS8() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x800000) >> 23
}
func (o *PWR_Type) SetCR4_SRAM5PDS9(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x1000000)|value<<24)
}
func (o *PWR_Type) GetCR4_SRAM5PDS9() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x1000000) >> 24
}
func (o *PWR_Type) SetCR4_SRAM5PDS10(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x2000000)|value<<25)
}
func (o *PWR_Type) GetCR4_SRAM5PDS10() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x2000000) >> 25
}
func (o *PWR_Type) SetCR4_SRAM5PDS11(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x4000000)|value<<26)
}
func (o *PWR_Type) GetCR4_SRAM5PDS11() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x4000000) >> 26
}
func (o *PWR_Type) SetCR4_SRAM5PDS12(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x8000000)|value<<27)
}
func (o *PWR_Type) GetCR4_SRAM5PDS12() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x8000000) >> 27
}
func (o *PWR_Type) SetCR4_SRAM5PDS13(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x10000000)|value<<28)
}
func (o *PWR_Type) GetCR4_SRAM5PDS13() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x10000000) >> 28
}

// RAMCFG
type RAMCFG_Type struct {
	M1CR       volatile.Register32 // 0x0
	_          [4]byte
	M1ISR      volatile.Register32 // 0x8
	_          [28]byte
	RAM1ERKEYR volatile.Register32 // 0x28
	_          [20]byte
	M2CR       volatile.Register32 // 0x40
	M2IER      volatile.Register32 // 0x44
	M2ISR      volatile.Register32 // 0x48
	M2SEAR     volatile.Register32 // 0x4C
	M2DEAR     volatile.Register32 // 0x50
	M2ICR      volatile.Register32 // 0x54
	M2WPR1     volatile.Register32 // 0x58
	M2WPR2     volatile.Register32 // 0x5C
	_          [4]byte
	M2ECCKEYR  volatile.Register32 // 0x64
	M2ERKEYR   volatile.Register32 // 0x68
	_          [20]byte
	M3CR       volatile.Register32 // 0x80
	M3IER      volatile.Register32 // 0x84
	M3ISR      volatile.Register32 // 0x88
	M3SEAR     volatile.Register32 // 0x8C
	M3DEAR     volatile.Register32 // 0x90
	M3ICR      volatile.Register32 // 0x94
	_          [12]byte
	M3ECCKEYR  volatile.Register32 // 0xA4
	M3ERKEYR   volatile.Register32 // 0xA8
	_          [20]byte
	M4CR       volatile.Register32 // 0xC0
	_          [4]byte
	M4ISR      volatile.Register32 // 0xC8
	_          [28]byte
	M4ERKEYR   volatile.Register32 // 0xE8
	_          [20]byte
	M5CR       volatile.Register32 // 0x100
	M5IER      volatile.Register32 // 0x104
	M5ISR      volatile.Register32 // 0x108
	M5SEAR     volatile.Register32 // 0x10C
	M5DEAR     volatile.Register32 // 0x110
	M5ICR      volatile.Register32 // 0x114
	_          [12]byte
	M5ECCKEYR  volatile.Register32 // 0x124
	M5ERKEYR   volatile.Register32 // 0x128
	_          [20]byte
	M6CR       volatile.Register32 // 0x140
	_          [4]byte
	M6ISR      volatile.Register32 // 0x148
	_          [28]byte
	M6ERKEYR   volatile.Register32 // 0x168
}

// RAMCFG.M1CR: RAMCFG SRAM x control register
func (o *RAMCFG_Type) SetM1CR_ECCE(value uint32) {
	volatile.StoreUint32(&o.M1CR.Reg, volatile.LoadUint32(&o.M1CR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM1CR_ECCE() uint32 {
	return volatile.LoadUint32(&o.M1CR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM1CR_ALE(value uint32) {
	volatile.StoreUint32(&o.M1CR.Reg, volatile.LoadUint32(&o.M1CR.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM1CR_ALE() uint32 {
	return (volatile.LoadUint32(&o.M1CR.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM1CR_SRAMER(value uint32) {
	volatile.StoreUint32(&o.M1CR.Reg, volatile.LoadUint32(&o.M1CR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM1CR_SRAMER() uint32 {
	return (volatile.LoadUint32(&o.M1CR.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM1CR_WSC(value uint32) {
	volatile.StoreUint32(&o.M1CR.Reg, volatile.LoadUint32(&o.M1CR.Reg)&^(0x70000)|value<<16)
}
func (o *RAMCFG_Type) GetM1CR_WSC() uint32 {
	return (volatile.LoadUint32(&o.M1CR.Reg) & 0x70000) >> 16
}

// RAMCFG.M1ISR: RAMCFG RAMx interrupt status register
func (o *RAMCFG_Type) SetM1ISR_SEDC(value uint32) {
	volatile.StoreUint32(&o.M1ISR.Reg, volatile.LoadUint32(&o.M1ISR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM1ISR_SEDC() uint32 {
	return volatile.LoadUint32(&o.M1ISR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM1ISR_DED(value uint32) {
	volatile.StoreUint32(&o.M1ISR.Reg, volatile.LoadUint32(&o.M1ISR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM1ISR_DED() uint32 {
	return (volatile.LoadUint32(&o.M1ISR.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM1ISR_SRAMBUSY(value uint32) {
	volatile.StoreUint32(&o.M1ISR.Reg, volatile.LoadUint32(&o.M1ISR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM1ISR_SRAMBUSY() uint32 {
	return (volatile.LoadUint32(&o.M1ISR.Reg) & 0x100) >> 8
}

// RAMCFG.RAM1ERKEYR: RAMCFG SRAM x erase key register
func (o *RAMCFG_Type) SetRAM1ERKEYR_ERASEKEY(value uint32) {
	volatile.StoreUint32(&o.RAM1ERKEYR.Reg, volatile.LoadUint32(&o.RAM1ERKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetRAM1ERKEYR_ERASEKEY() uint32 {
	return volatile.LoadUint32(&o.RAM1ERKEYR.Reg) & 0xff
}

// RAMCFG.M2CR: RAMCFG SRAM x control register
func (o *RAMCFG_Type) SetM2CR_ECCE(value uint32) {
	volatile.StoreUint32(&o.M2CR.Reg, volatile.LoadUint32(&o.M2CR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM2CR_ECCE() uint32 {
	return volatile.LoadUint32(&o.M2CR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM2CR_ALE(value uint32) {
	volatile.StoreUint32(&o.M2CR.Reg, volatile.LoadUint32(&o.M2CR.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM2CR_ALE() uint32 {
	return (volatile.LoadUint32(&o.M2CR.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM2CR_SRAMER(value uint32) {
	volatile.StoreUint32(&o.M2CR.Reg, volatile.LoadUint32(&o.M2CR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM2CR_SRAMER() uint32 {
	return (volatile.LoadUint32(&o.M2CR.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM2CR_WSC(value uint32) {
	volatile.StoreUint32(&o.M2CR.Reg, volatile.LoadUint32(&o.M2CR.Reg)&^(0x70000)|value<<16)
}
func (o *RAMCFG_Type) GetM2CR_WSC() uint32 {
	return (volatile.LoadUint32(&o.M2CR.Reg) & 0x70000) >> 16
}

// RAMCFG.M2IER: RAMCFG SRAM x interrupt enable register
func (o *RAMCFG_Type) SetM2IER_SEIE(value uint32) {
	volatile.StoreUint32(&o.M2IER.Reg, volatile.LoadUint32(&o.M2IER.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM2IER_SEIE() uint32 {
	return volatile.LoadUint32(&o.M2IER.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM2IER_DEIE(value uint32) {
	volatile.StoreUint32(&o.M2IER.Reg, volatile.LoadUint32(&o.M2IER.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM2IER_DEIE() uint32 {
	return (volatile.LoadUint32(&o.M2IER.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM2IER_ECCNMI(value uint32) {
	volatile.StoreUint32(&o.M2IER.Reg, volatile.LoadUint32(&o.M2IER.Reg)&^(0x8)|value<<3)
}
func (o *RAMCFG_Type) GetM2IER_ECCNMI() uint32 {
	return (volatile.LoadUint32(&o.M2IER.Reg) & 0x8) >> 3
}

// RAMCFG.M2ISR: RAMCFG RAMx interrupt status register
func (o *RAMCFG_Type) SetM2ISR_SEDC(value uint32) {
	volatile.StoreUint32(&o.M2ISR.Reg, volatile.LoadUint32(&o.M2ISR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM2ISR_SEDC() uint32 {
	return volatile.LoadUint32(&o.M2ISR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM2ISR_DED(value uint32) {
	volatile.StoreUint32(&o.M2ISR.Reg, volatile.LoadUint32(&o.M2ISR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM2ISR_DED() uint32 {
	return (volatile.LoadUint32(&o.M2ISR.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM2ISR_SRAMBUSY(value uint32) {
	volatile.StoreUint32(&o.M2ISR.Reg, volatile.LoadUint32(&o.M2ISR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM2ISR_SRAMBUSY() uint32 {
	return (volatile.LoadUint32(&o.M2ISR.Reg) & 0x100) >> 8
}

// RAMCFG.M2SEAR: RAMCFG RAM x ECC single error address register
func (o *RAMCFG_Type) SetM2SEAR(value uint32) {
	volatile.StoreUint32(&o.M2SEAR.Reg, value)
}
func (o *RAMCFG_Type) GetM2SEAR() uint32 {
	return volatile.LoadUint32(&o.M2SEAR.Reg)
}

// RAMCFG.M2DEAR: RAMCFG RAM x ECC double error address register
func (o *RAMCFG_Type) SetM2DEAR(value uint32) {
	volatile.StoreUint32(&o.M2DEAR.Reg, value)
}
func (o *RAMCFG_Type) GetM2DEAR() uint32 {
	return volatile.LoadUint32(&o.M2DEAR.Reg)
}

// RAMCFG.M2ICR: RAMCFG RAM x interrupt clear register x
func (o *RAMCFG_Type) SetM2ICR_CSEDC(value uint32) {
	volatile.StoreUint32(&o.M2ICR.Reg, volatile.LoadUint32(&o.M2ICR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM2ICR_CSEDC() uint32 {
	return volatile.LoadUint32(&o.M2ICR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM2ICR_CDED(value uint32) {
	volatile.StoreUint32(&o.M2ICR.Reg, volatile.LoadUint32(&o.M2ICR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM2ICR_CDED() uint32 {
	return (volatile.LoadUint32(&o.M2ICR.Reg) & 0x2) >> 1
}

// RAMCFG.M2WPR1: RAMCFG SRAM2 write protection register 1
func (o *RAMCFG_Type) SetM2WPR1_P0WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM2WPR1_P0WP() uint32 {
	return volatile.LoadUint32(&o.M2WPR1.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM2WPR1_P1WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM2WPR1_P1WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM2WPR1_P2WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x4)|value<<2)
}
func (o *RAMCFG_Type) GetM2WPR1_P2WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x4) >> 2
}
func (o *RAMCFG_Type) SetM2WPR1_P3WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x8)|value<<3)
}
func (o *RAMCFG_Type) GetM2WPR1_P3WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x8) >> 3
}
func (o *RAMCFG_Type) SetM2WPR1_P4WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM2WPR1_P4WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM2WPR1_P5WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x20)|value<<5)
}
func (o *RAMCFG_Type) GetM2WPR1_P5WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x20) >> 5
}
func (o *RAMCFG_Type) SetM2WPR1_P6WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x40)|value<<6)
}
func (o *RAMCFG_Type) GetM2WPR1_P6WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x40) >> 6
}
func (o *RAMCFG_Type) SetM2WPR1_P7WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x80)|value<<7)
}
func (o *RAMCFG_Type) GetM2WPR1_P7WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x80) >> 7
}
func (o *RAMCFG_Type) SetM2WPR1_P8WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM2WPR1_P8WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM2WPR1_P9WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x200)|value<<9)
}
func (o *RAMCFG_Type) GetM2WPR1_P9WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x200) >> 9
}
func (o *RAMCFG_Type) SetM2WPR1_P10WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x400)|value<<10)
}
func (o *RAMCFG_Type) GetM2WPR1_P10WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x400) >> 10
}
func (o *RAMCFG_Type) SetM2WPR1_P11WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x800)|value<<11)
}
func (o *RAMCFG_Type) GetM2WPR1_P11WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x800) >> 11
}
func (o *RAMCFG_Type) SetM2WPR1_P12WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x1000)|value<<12)
}
func (o *RAMCFG_Type) GetM2WPR1_P12WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x1000) >> 12
}
func (o *RAMCFG_Type) SetM2WPR1_P13WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x2000)|value<<13)
}
func (o *RAMCFG_Type) GetM2WPR1_P13WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x2000) >> 13
}
func (o *RAMCFG_Type) SetM2WPR1_P14WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x4000)|value<<14)
}
func (o *RAMCFG_Type) GetM2WPR1_P14WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x4000) >> 14
}
func (o *RAMCFG_Type) SetM2WPR1_P15WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x8000)|value<<15)
}
func (o *RAMCFG_Type) GetM2WPR1_P15WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x8000) >> 15
}
func (o *RAMCFG_Type) SetM2WPR1_P16WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x10000)|value<<16)
}
func (o *RAMCFG_Type) GetM2WPR1_P16WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x10000) >> 16
}
func (o *RAMCFG_Type) SetM2WPR1_P17WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x20000)|value<<17)
}
func (o *RAMCFG_Type) GetM2WPR1_P17WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x20000) >> 17
}
func (o *RAMCFG_Type) SetM2WPR1_P18WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x40000)|value<<18)
}
func (o *RAMCFG_Type) GetM2WPR1_P18WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x40000) >> 18
}
func (o *RAMCFG_Type) SetM2WPR1_P19WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x80000)|value<<19)
}
func (o *RAMCFG_Type) GetM2WPR1_P19WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x80000) >> 19
}
func (o *RAMCFG_Type) SetM2WPR1_P20WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x100000)|value<<20)
}
func (o *RAMCFG_Type) GetM2WPR1_P20WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x100000) >> 20
}
func (o *RAMCFG_Type) SetM2WPR1_P21WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x200000)|value<<21)
}
func (o *RAMCFG_Type) GetM2WPR1_P21WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x200000) >> 21
}
func (o *RAMCFG_Type) SetM2WPR1_P22WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x400000)|value<<22)
}
func (o *RAMCFG_Type) GetM2WPR1_P22WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x400000) >> 22
}
func (o *RAMCFG_Type) SetM2WPR1_P23WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x800000)|value<<23)
}
func (o *RAMCFG_Type) GetM2WPR1_P23WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x800000) >> 23
}
func (o *RAMCFG_Type) SetM2WPR1_P24WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RAMCFG_Type) GetM2WPR1_P24WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x1000000) >> 24
}
func (o *RAMCFG_Type) SetM2WPR1_P25WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x2000000)|value<<25)
}
func (o *RAMCFG_Type) GetM2WPR1_P25WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x2000000) >> 25
}
func (o *RAMCFG_Type) SetM2WPR1_P26WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x4000000)|value<<26)
}
func (o *RAMCFG_Type) GetM2WPR1_P26WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x4000000) >> 26
}
func (o *RAMCFG_Type) SetM2WPR1_P27WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x8000000)|value<<27)
}
func (o *RAMCFG_Type) GetM2WPR1_P27WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x8000000) >> 27
}
func (o *RAMCFG_Type) SetM2WPR1_P28WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RAMCFG_Type) GetM2WPR1_P28WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x10000000) >> 28
}
func (o *RAMCFG_Type) SetM2WPR1_P29WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x20000000)|value<<29)
}
func (o *RAMCFG_Type) GetM2WPR1_P29WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x20000000) >> 29
}
func (o *RAMCFG_Type) SetM2WPR1_P30WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x40000000)|value<<30)
}
func (o *RAMCFG_Type) GetM2WPR1_P30WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x40000000) >> 30
}
func (o *RAMCFG_Type) SetM2WPR1_P31WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR1.Reg, volatile.LoadUint32(&o.M2WPR1.Reg)&^(0x80000000)|value<<31)
}
func (o *RAMCFG_Type) GetM2WPR1_P31WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR1.Reg) & 0x80000000) >> 31
}

// RAMCFG.M2WPR2: RAMCFG SRAM2 write protection register 2
func (o *RAMCFG_Type) SetM2WPR2_P32WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM2WPR2_P32WP() uint32 {
	return volatile.LoadUint32(&o.M2WPR2.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM2WPR2_P33WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM2WPR2_P33WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM2WPR2_P34WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x4)|value<<2)
}
func (o *RAMCFG_Type) GetM2WPR2_P34WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x4) >> 2
}
func (o *RAMCFG_Type) SetM2WPR2_P35WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x8)|value<<3)
}
func (o *RAMCFG_Type) GetM2WPR2_P35WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x8) >> 3
}
func (o *RAMCFG_Type) SetM2WPR2_P36WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM2WPR2_P36WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM2WPR2_P37WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x20)|value<<5)
}
func (o *RAMCFG_Type) GetM2WPR2_P37WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x20) >> 5
}
func (o *RAMCFG_Type) SetM2WPR2_P38WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x40)|value<<6)
}
func (o *RAMCFG_Type) GetM2WPR2_P38WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x40) >> 6
}
func (o *RAMCFG_Type) SetM2WPR2_P39WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x80)|value<<7)
}
func (o *RAMCFG_Type) GetM2WPR2_P39WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x80) >> 7
}
func (o *RAMCFG_Type) SetM2WPR2_P40WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM2WPR2_P40WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM2WPR2_P41WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x200)|value<<9)
}
func (o *RAMCFG_Type) GetM2WPR2_P41WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x200) >> 9
}
func (o *RAMCFG_Type) SetM2WPR2_P42WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x400)|value<<10)
}
func (o *RAMCFG_Type) GetM2WPR2_P42WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x400) >> 10
}
func (o *RAMCFG_Type) SetM2WPR2_P43WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x800)|value<<11)
}
func (o *RAMCFG_Type) GetM2WPR2_P43WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x800) >> 11
}
func (o *RAMCFG_Type) SetM2WPR2_P44WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x1000)|value<<12)
}
func (o *RAMCFG_Type) GetM2WPR2_P44WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x1000) >> 12
}
func (o *RAMCFG_Type) SetM2WPR2_P45WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x2000)|value<<13)
}
func (o *RAMCFG_Type) GetM2WPR2_P45WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x2000) >> 13
}
func (o *RAMCFG_Type) SetM2WPR2_P46WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x4000)|value<<14)
}
func (o *RAMCFG_Type) GetM2WPR2_P46WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x4000) >> 14
}
func (o *RAMCFG_Type) SetM2WPR2_P47WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x8000)|value<<15)
}
func (o *RAMCFG_Type) GetM2WPR2_P47WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x8000) >> 15
}
func (o *RAMCFG_Type) SetM2WPR2_P48WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x10000)|value<<16)
}
func (o *RAMCFG_Type) GetM2WPR2_P48WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x10000) >> 16
}
func (o *RAMCFG_Type) SetM2WPR2_P49WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x20000)|value<<17)
}
func (o *RAMCFG_Type) GetM2WPR2_P49WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x20000) >> 17
}
func (o *RAMCFG_Type) SetM2WPR2_P50WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x40000)|value<<18)
}
func (o *RAMCFG_Type) GetM2WPR2_P50WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x40000) >> 18
}
func (o *RAMCFG_Type) SetM2WPR2_P51WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x80000)|value<<19)
}
func (o *RAMCFG_Type) GetM2WPR2_P51WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x80000) >> 19
}
func (o *RAMCFG_Type) SetM2WPR2_P52WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x100000)|value<<20)
}
func (o *RAMCFG_Type) GetM2WPR2_P52WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x100000) >> 20
}
func (o *RAMCFG_Type) SetM2WPR2_P53WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x200000)|value<<21)
}
func (o *RAMCFG_Type) GetM2WPR2_P53WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x200000) >> 21
}
func (o *RAMCFG_Type) SetM2WPR2_P54WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x400000)|value<<22)
}
func (o *RAMCFG_Type) GetM2WPR2_P54WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x400000) >> 22
}
func (o *RAMCFG_Type) SetM2WPR2_P55WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x800000)|value<<23)
}
func (o *RAMCFG_Type) GetM2WPR2_P55WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x800000) >> 23
}
func (o *RAMCFG_Type) SetM2WPR2_P56WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x1000000)|value<<24)
}
func (o *RAMCFG_Type) GetM2WPR2_P56WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x1000000) >> 24
}
func (o *RAMCFG_Type) SetM2WPR2_P57WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x2000000)|value<<25)
}
func (o *RAMCFG_Type) GetM2WPR2_P57WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x2000000) >> 25
}
func (o *RAMCFG_Type) SetM2WPR2_P58WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x4000000)|value<<26)
}
func (o *RAMCFG_Type) GetM2WPR2_P58WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x4000000) >> 26
}
func (o *RAMCFG_Type) SetM2WPR2_P59WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x8000000)|value<<27)
}
func (o *RAMCFG_Type) GetM2WPR2_P59WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x8000000) >> 27
}
func (o *RAMCFG_Type) SetM2WPR2_P60WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x10000000)|value<<28)
}
func (o *RAMCFG_Type) GetM2WPR2_P60WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x10000000) >> 28
}
func (o *RAMCFG_Type) SetM2WPR2_P61WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x20000000)|value<<29)
}
func (o *RAMCFG_Type) GetM2WPR2_P61WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x20000000) >> 29
}
func (o *RAMCFG_Type) SetM2WPR2_P62WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x40000000)|value<<30)
}
func (o *RAMCFG_Type) GetM2WPR2_P62WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x40000000) >> 30
}
func (o *RAMCFG_Type) SetM2WPR2_P63WP(value uint32) {
	volatile.StoreUint32(&o.M2WPR2.Reg, volatile.LoadUint32(&o.M2WPR2.Reg)&^(0x80000000)|value<<31)
}
func (o *RAMCFG_Type) GetM2WPR2_P63WP() uint32 {
	return (volatile.LoadUint32(&o.M2WPR2.Reg) & 0x80000000) >> 31
}

// RAMCFG.M2ECCKEYR: RAMCFG SRAM x ECC key register
func (o *RAMCFG_Type) SetM2ECCKEYR_ECCKEY(value uint32) {
	volatile.StoreUint32(&o.M2ECCKEYR.Reg, volatile.LoadUint32(&o.M2ECCKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM2ECCKEYR_ECCKEY() uint32 {
	return volatile.LoadUint32(&o.M2ECCKEYR.Reg) & 0xff
}

// RAMCFG.M2ERKEYR: RAMCFG SRAM x erase key register
func (o *RAMCFG_Type) SetM2ERKEYR_ERASEKEY(value uint32) {
	volatile.StoreUint32(&o.M2ERKEYR.Reg, volatile.LoadUint32(&o.M2ERKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM2ERKEYR_ERASEKEY() uint32 {
	return volatile.LoadUint32(&o.M2ERKEYR.Reg) & 0xff
}

// RAMCFG.M3CR: RAMCFG SRAM x control register
func (o *RAMCFG_Type) SetM3CR_ECCE(value uint32) {
	volatile.StoreUint32(&o.M3CR.Reg, volatile.LoadUint32(&o.M3CR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM3CR_ECCE() uint32 {
	return volatile.LoadUint32(&o.M3CR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM3CR_ALE(value uint32) {
	volatile.StoreUint32(&o.M3CR.Reg, volatile.LoadUint32(&o.M3CR.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM3CR_ALE() uint32 {
	return (volatile.LoadUint32(&o.M3CR.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM3CR_SRAMER(value uint32) {
	volatile.StoreUint32(&o.M3CR.Reg, volatile.LoadUint32(&o.M3CR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM3CR_SRAMER() uint32 {
	return (volatile.LoadUint32(&o.M3CR.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM3CR_WSC(value uint32) {
	volatile.StoreUint32(&o.M3CR.Reg, volatile.LoadUint32(&o.M3CR.Reg)&^(0x70000)|value<<16)
}
func (o *RAMCFG_Type) GetM3CR_WSC() uint32 {
	return (volatile.LoadUint32(&o.M3CR.Reg) & 0x70000) >> 16
}

// RAMCFG.M3IER: RAMCFG SRAM x interrupt enable register
func (o *RAMCFG_Type) SetM3IER_SEIE(value uint32) {
	volatile.StoreUint32(&o.M3IER.Reg, volatile.LoadUint32(&o.M3IER.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM3IER_SEIE() uint32 {
	return volatile.LoadUint32(&o.M3IER.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM3IER_DEIE(value uint32) {
	volatile.StoreUint32(&o.M3IER.Reg, volatile.LoadUint32(&o.M3IER.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM3IER_DEIE() uint32 {
	return (volatile.LoadUint32(&o.M3IER.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM3IER_ECCNMI(value uint32) {
	volatile.StoreUint32(&o.M3IER.Reg, volatile.LoadUint32(&o.M3IER.Reg)&^(0x8)|value<<3)
}
func (o *RAMCFG_Type) GetM3IER_ECCNMI() uint32 {
	return (volatile.LoadUint32(&o.M3IER.Reg) & 0x8) >> 3
}

// RAMCFG.M3ISR: RAMCFG RAMx interrupt status register
func (o *RAMCFG_Type) SetM3ISR_SEDC(value uint32) {
	volatile.StoreUint32(&o.M3ISR.Reg, volatile.LoadUint32(&o.M3ISR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM3ISR_SEDC() uint32 {
	return volatile.LoadUint32(&o.M3ISR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM3ISR_DED(value uint32) {
	volatile.StoreUint32(&o.M3ISR.Reg, volatile.LoadUint32(&o.M3ISR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM3ISR_DED() uint32 {
	return (volatile.LoadUint32(&o.M3ISR.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM3ISR_SRAMBUSY(value uint32) {
	volatile.StoreUint32(&o.M3ISR.Reg, volatile.LoadUint32(&o.M3ISR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM3ISR_SRAMBUSY() uint32 {
	return (volatile.LoadUint32(&o.M3ISR.Reg) & 0x100) >> 8
}

// RAMCFG.M3SEAR: RAMCFG RAM x ECC single error address register
func (o *RAMCFG_Type) SetM3SEAR(value uint32) {
	volatile.StoreUint32(&o.M3SEAR.Reg, value)
}
func (o *RAMCFG_Type) GetM3SEAR() uint32 {
	return volatile.LoadUint32(&o.M3SEAR.Reg)
}

// RAMCFG.M3DEAR: RAMCFG RAM x ECC double error address register
func (o *RAMCFG_Type) SetM3DEAR(value uint32) {
	volatile.StoreUint32(&o.M3DEAR.Reg, value)
}
func (o *RAMCFG_Type) GetM3DEAR() uint32 {
	return volatile.LoadUint32(&o.M3DEAR.Reg)
}

// RAMCFG.M3ICR: RAMCFG RAM x interrupt clear register x
func (o *RAMCFG_Type) SetM3ICR_CSEDC(value uint32) {
	volatile.StoreUint32(&o.M3ICR.Reg, volatile.LoadUint32(&o.M3ICR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM3ICR_CSEDC() uint32 {
	return volatile.LoadUint32(&o.M3ICR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM3ICR_CDED(value uint32) {
	volatile.StoreUint32(&o.M3ICR.Reg, volatile.LoadUint32(&o.M3ICR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM3ICR_CDED() uint32 {
	return (volatile.LoadUint32(&o.M3ICR.Reg) & 0x2) >> 1
}

// RAMCFG.M3ECCKEYR: RAMCFG SRAM x ECC key register
func (o *RAMCFG_Type) SetM3ECCKEYR_ECCKEY(value uint32) {
	volatile.StoreUint32(&o.M3ECCKEYR.Reg, volatile.LoadUint32(&o.M3ECCKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM3ECCKEYR_ECCKEY() uint32 {
	return volatile.LoadUint32(&o.M3ECCKEYR.Reg) & 0xff
}

// RAMCFG.M3ERKEYR: RAMCFG SRAM x erase key register
func (o *RAMCFG_Type) SetM3ERKEYR_ERASEKEY(value uint32) {
	volatile.StoreUint32(&o.M3ERKEYR.Reg, volatile.LoadUint32(&o.M3ERKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM3ERKEYR_ERASEKEY() uint32 {
	return volatile.LoadUint32(&o.M3ERKEYR.Reg) & 0xff
}

// RAMCFG.M4CR: RAMCFG SRAM x control register
func (o *RAMCFG_Type) SetM4CR_ECCE(value uint32) {
	volatile.StoreUint32(&o.M4CR.Reg, volatile.LoadUint32(&o.M4CR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM4CR_ECCE() uint32 {
	return volatile.LoadUint32(&o.M4CR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM4CR_ALE(value uint32) {
	volatile.StoreUint32(&o.M4CR.Reg, volatile.LoadUint32(&o.M4CR.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM4CR_ALE() uint32 {
	return (volatile.LoadUint32(&o.M4CR.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM4CR_SRAMER(value uint32) {
	volatile.StoreUint32(&o.M4CR.Reg, volatile.LoadUint32(&o.M4CR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM4CR_SRAMER() uint32 {
	return (volatile.LoadUint32(&o.M4CR.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM4CR_WSC(value uint32) {
	volatile.StoreUint32(&o.M4CR.Reg, volatile.LoadUint32(&o.M4CR.Reg)&^(0x70000)|value<<16)
}
func (o *RAMCFG_Type) GetM4CR_WSC() uint32 {
	return (volatile.LoadUint32(&o.M4CR.Reg) & 0x70000) >> 16
}

// RAMCFG.M4ISR: RAMCFG RAMx interrupt status register
func (o *RAMCFG_Type) SetM4ISR_SEDC(value uint32) {
	volatile.StoreUint32(&o.M4ISR.Reg, volatile.LoadUint32(&o.M4ISR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM4ISR_SEDC() uint32 {
	return volatile.LoadUint32(&o.M4ISR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM4ISR_DED(value uint32) {
	volatile.StoreUint32(&o.M4ISR.Reg, volatile.LoadUint32(&o.M4ISR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM4ISR_DED() uint32 {
	return (volatile.LoadUint32(&o.M4ISR.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM4ISR_SRAMBUSY(value uint32) {
	volatile.StoreUint32(&o.M4ISR.Reg, volatile.LoadUint32(&o.M4ISR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM4ISR_SRAMBUSY() uint32 {
	return (volatile.LoadUint32(&o.M4ISR.Reg) & 0x100) >> 8
}

// RAMCFG.M4ERKEYR: RAMCFG SRAM x erase key register
func (o *RAMCFG_Type) SetM4ERKEYR_ERASEKEY(value uint32) {
	volatile.StoreUint32(&o.M4ERKEYR.Reg, volatile.LoadUint32(&o.M4ERKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM4ERKEYR_ERASEKEY() uint32 {
	return volatile.LoadUint32(&o.M4ERKEYR.Reg) & 0xff
}

// RAMCFG.M5CR: RAMCFG SRAM x control register
func (o *RAMCFG_Type) SetM5CR_ECCE(value uint32) {
	volatile.StoreUint32(&o.M5CR.Reg, volatile.LoadUint32(&o.M5CR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM5CR_ECCE() uint32 {
	return volatile.LoadUint32(&o.M5CR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM5CR_ALE(value uint32) {
	volatile.StoreUint32(&o.M5CR.Reg, volatile.LoadUint32(&o.M5CR.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM5CR_ALE() uint32 {
	return (volatile.LoadUint32(&o.M5CR.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM5CR_SRAMER(value uint32) {
	volatile.StoreUint32(&o.M5CR.Reg, volatile.LoadUint32(&o.M5CR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM5CR_SRAMER() uint32 {
	return (volatile.LoadUint32(&o.M5CR.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM5CR_WSC(value uint32) {
	volatile.StoreUint32(&o.M5CR.Reg, volatile.LoadUint32(&o.M5CR.Reg)&^(0x70000)|value<<16)
}
func (o *RAMCFG_Type) GetM5CR_WSC() uint32 {
	return (volatile.LoadUint32(&o.M5CR.Reg) & 0x70000) >> 16
}

// RAMCFG.M5IER: RAMCFG SRAM x interrupt enable register
func (o *RAMCFG_Type) SetM5IER_SEIE(value uint32) {
	volatile.StoreUint32(&o.M5IER.Reg, volatile.LoadUint32(&o.M5IER.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM5IER_SEIE() uint32 {
	return volatile.LoadUint32(&o.M5IER.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM5IER_DEIE(value uint32) {
	volatile.StoreUint32(&o.M5IER.Reg, volatile.LoadUint32(&o.M5IER.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM5IER_DEIE() uint32 {
	return (volatile.LoadUint32(&o.M5IER.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM5IER_ECCNMI(value uint32) {
	volatile.StoreUint32(&o.M5IER.Reg, volatile.LoadUint32(&o.M5IER.Reg)&^(0x8)|value<<3)
}
func (o *RAMCFG_Type) GetM5IER_ECCNMI() uint32 {
	return (volatile.LoadUint32(&o.M5IER.Reg) & 0x8) >> 3
}

// RAMCFG.M5ISR: RAMCFG RAMx interrupt status register
func (o *RAMCFG_Type) SetM5ISR_SEDC(value uint32) {
	volatile.StoreUint32(&o.M5ISR.Reg, volatile.LoadUint32(&o.M5ISR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM5ISR_SEDC() uint32 {
	return volatile.LoadUint32(&o.M5ISR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM5ISR_DED(value uint32) {
	volatile.StoreUint32(&o.M5ISR.Reg, volatile.LoadUint32(&o.M5ISR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM5ISR_DED() uint32 {
	return (volatile.LoadUint32(&o.M5ISR.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM5ISR_SRAMBUSY(value uint32) {
	volatile.StoreUint32(&o.M5ISR.Reg, volatile.LoadUint32(&o.M5ISR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM5ISR_SRAMBUSY() uint32 {
	return (volatile.LoadUint32(&o.M5ISR.Reg) & 0x100) >> 8
}

// RAMCFG.M5SEAR: RAMCFG RAM x ECC single error address register
func (o *RAMCFG_Type) SetM5SEAR(value uint32) {
	volatile.StoreUint32(&o.M5SEAR.Reg, value)
}
func (o *RAMCFG_Type) GetM5SEAR() uint32 {
	return volatile.LoadUint32(&o.M5SEAR.Reg)
}

// RAMCFG.M5DEAR: RAMCFG RAM x ECC double error address register
func (o *RAMCFG_Type) SetM5DEAR(value uint32) {
	volatile.StoreUint32(&o.M5DEAR.Reg, value)
}
func (o *RAMCFG_Type) GetM5DEAR() uint32 {
	return volatile.LoadUint32(&o.M5DEAR.Reg)
}

// RAMCFG.M5ICR: RAMCFG RAM x interrupt clear register x
func (o *RAMCFG_Type) SetM5ICR_CSEDC(value uint32) {
	volatile.StoreUint32(&o.M5ICR.Reg, volatile.LoadUint32(&o.M5ICR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM5ICR_CSEDC() uint32 {
	return volatile.LoadUint32(&o.M5ICR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM5ICR_CDED(value uint32) {
	volatile.StoreUint32(&o.M5ICR.Reg, volatile.LoadUint32(&o.M5ICR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM5ICR_CDED() uint32 {
	return (volatile.LoadUint32(&o.M5ICR.Reg) & 0x2) >> 1
}

// RAMCFG.M5ECCKEYR: RAMCFG RAM x interrupt clear register x
func (o *RAMCFG_Type) SetM5ECCKEYR_ECCKEY(value uint32) {
	volatile.StoreUint32(&o.M5ECCKEYR.Reg, volatile.LoadUint32(&o.M5ECCKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM5ECCKEYR_ECCKEY() uint32 {
	return volatile.LoadUint32(&o.M5ECCKEYR.Reg) & 0xff
}

// RAMCFG.M5ERKEYR
func (o *RAMCFG_Type) SetM5ERKEYR_ERASEKEY(value uint32) {
	volatile.StoreUint32(&o.M5ERKEYR.Reg, volatile.LoadUint32(&o.M5ERKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM5ERKEYR_ERASEKEY() uint32 {
	return volatile.LoadUint32(&o.M5ERKEYR.Reg) & 0xff
}

// RAMCFG.M6CR: memory x control register
func (o *RAMCFG_Type) SetM6CR_ECCE(value uint32) {
	volatile.StoreUint32(&o.M6CR.Reg, volatile.LoadUint32(&o.M6CR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM6CR_ECCE() uint32 {
	return volatile.LoadUint32(&o.M6CR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM6CR_ALE(value uint32) {
	volatile.StoreUint32(&o.M6CR.Reg, volatile.LoadUint32(&o.M6CR.Reg)&^(0x10)|value<<4)
}
func (o *RAMCFG_Type) GetM6CR_ALE() uint32 {
	return (volatile.LoadUint32(&o.M6CR.Reg) & 0x10) >> 4
}
func (o *RAMCFG_Type) SetM6CR_SRAMER(value uint32) {
	volatile.StoreUint32(&o.M6CR.Reg, volatile.LoadUint32(&o.M6CR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM6CR_SRAMER() uint32 {
	return (volatile.LoadUint32(&o.M6CR.Reg) & 0x100) >> 8
}
func (o *RAMCFG_Type) SetM6CR_WSC(value uint32) {
	volatile.StoreUint32(&o.M6CR.Reg, volatile.LoadUint32(&o.M6CR.Reg)&^(0x70000)|value<<16)
}
func (o *RAMCFG_Type) GetM6CR_WSC() uint32 {
	return (volatile.LoadUint32(&o.M6CR.Reg) & 0x70000) >> 16
}

// RAMCFG.M6ISR
func (o *RAMCFG_Type) SetM6ISR_SEDC(value uint32) {
	volatile.StoreUint32(&o.M6ISR.Reg, volatile.LoadUint32(&o.M6ISR.Reg)&^(0x1)|value)
}
func (o *RAMCFG_Type) GetM6ISR_SEDC() uint32 {
	return volatile.LoadUint32(&o.M6ISR.Reg) & 0x1
}
func (o *RAMCFG_Type) SetM6ISR_DED(value uint32) {
	volatile.StoreUint32(&o.M6ISR.Reg, volatile.LoadUint32(&o.M6ISR.Reg)&^(0x2)|value<<1)
}
func (o *RAMCFG_Type) GetM6ISR_DED() uint32 {
	return (volatile.LoadUint32(&o.M6ISR.Reg) & 0x2) >> 1
}
func (o *RAMCFG_Type) SetM6ISR_SRAMBUSY(value uint32) {
	volatile.StoreUint32(&o.M6ISR.Reg, volatile.LoadUint32(&o.M6ISR.Reg)&^(0x100)|value<<8)
}
func (o *RAMCFG_Type) GetM6ISR_SRAMBUSY() uint32 {
	return (volatile.LoadUint32(&o.M6ISR.Reg) & 0x100) >> 8
}

// RAMCFG.M6ERKEYR
func (o *RAMCFG_Type) SetM6ERKEYR_ERASEKEY(value uint32) {
	volatile.StoreUint32(&o.M6ERKEYR.Reg, volatile.LoadUint32(&o.M6ERKEYR.Reg)&^(0xff)|value)
}
func (o *RAMCFG_Type) GetM6ERKEYR_ERASEKEY() uint32 {
	return volatile.LoadUint32(&o.M6ERKEYR.Reg) & 0xff
}

// Reset and clock control
type RCC_Type struct {
	CR         volatile.Register32 // 0x0
	_          [4]byte
	ICSCR1     volatile.Register32 // 0x8
	ICSCR2     volatile.Register32 // 0xC
	ICSCR3     volatile.Register32 // 0x10
	CRRCR      volatile.Register32 // 0x14
	_          [4]byte
	CFGR1      volatile.Register32 // 0x1C
	CFGR2      volatile.Register32 // 0x20
	CFGR3      volatile.Register32 // 0x24
	PLL1CFGR   volatile.Register32 // 0x28
	PLL2CFGR   volatile.Register32 // 0x2C
	PLL3CFGR   volatile.Register32 // 0x30
	PLL1DIVR   volatile.Register32 // 0x34
	PLL1FRACR  volatile.Register32 // 0x38
	PLL2DIVR   volatile.Register32 // 0x3C
	PLL2FRACR  volatile.Register32 // 0x40
	PLL3DIVR   volatile.Register32 // 0x44
	PLL3FRACR  volatile.Register32 // 0x48
	_          [4]byte
	CIER       volatile.Register32 // 0x50
	CIFR       volatile.Register32 // 0x54
	CICR       volatile.Register32 // 0x58
	_          [4]byte
	AHB1RSTR   volatile.Register32 // 0x60
	AHB2RSTR1  volatile.Register32 // 0x64
	AHB2RSTR2  volatile.Register32 // 0x68
	AHB3RSTR   volatile.Register32 // 0x6C
	_          [4]byte
	APB1RSTR1  volatile.Register32 // 0x74
	APB1RSTR2  volatile.Register32 // 0x78
	APB2RSTR   volatile.Register32 // 0x7C
	APB3RSTR   volatile.Register32 // 0x80
	_          [4]byte
	AHB1ENR    volatile.Register32 // 0x88
	AHB2ENR1   volatile.Register32 // 0x8C
	AHB2ENR2   volatile.Register32 // 0x90
	AHB3ENR    volatile.Register32 // 0x94
	_          [4]byte
	APB1ENR1   volatile.Register32 // 0x9C
	APB1ENR2   volatile.Register32 // 0xA0
	APB2ENR    volatile.Register32 // 0xA4
	APB3ENR    volatile.Register32 // 0xA8
	_          [4]byte
	AHB1SMENR  volatile.Register32 // 0xB0
	AHB2SMENR1 volatile.Register32 // 0xB4
	AHB2SMENR2 volatile.Register32 // 0xB8
	AHB3SMENR  volatile.Register32 // 0xBC
	_          [4]byte
	APB1SMENR1 volatile.Register32 // 0xC4
	APB1SMENR2 volatile.Register32 // 0xC8
	APB2SMENR  volatile.Register32 // 0xCC
	APB3SMENR  volatile.Register32 // 0xD0
	_          [4]byte
	SRDAMR     volatile.Register32 // 0xD8
	_          [4]byte
	CCIPR1     volatile.Register32 // 0xE0
	CCIPR2     volatile.Register32 // 0xE4
	CCIPR3     volatile.Register32 // 0xE8
	_          [4]byte
	BDCR       volatile.Register32 // 0xF0
	CSR        volatile.Register32 // 0xF4
	_          [24]byte
	SECCFGR    volatile.Register32 // 0x110
	PRIVCFGR   volatile.Register32 // 0x114
}

// RCC.CR: RCC clock control register
func (o *RCC_Type) SetCR_MSISON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCR_MSISON() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *RCC_Type) SetCR_MSIKERON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCR_MSIKERON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCR_MSISRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCR_MSISRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCR_MSIPLLEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCR_MSIPLLEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCR_MSIKON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCR_MSIKON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCR_MSIKRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCR_MSIKRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCR_MSIPLLSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCR_MSIPLLSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCR_MSIPLLFAST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCR_MSIPLLFAST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCR_HSION(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCR_HSION() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCR_HSIKERON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCR_HSIKERON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetCR_HSIRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCR_HSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetCR_HSI48ON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetCR_HSI48ON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetCR_HSI48RDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetCR_HSI48RDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetCR_SHSION(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetCR_SHSION() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetCR_SHSIRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetCR_SHSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetCR_HSEON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetCR_HSEON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetCR_HSERDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetCR_HSERDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetCR_HSEBYP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetCR_HSEBYP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetCR_CSSON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetCR_CSSON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetCR_HSEEXT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetCR_HSEEXT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetCR_PLL1ON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetCR_PLL1ON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetCR_PLL1RDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetCR_PLL1RDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetCR_PLL2ON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetCR_PLL2ON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetCR_PLL2RDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetCR_PLL2RDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetCR_PLL3ON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetCR_PLL3ON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetCR_PLL3RDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetCR_PLL3RDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}

// RCC.ICSCR1: RCC internal clock sources calibration register 1
func (o *RCC_Type) SetICSCR1_MSICAL3(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0x1f)|value)
}
func (o *RCC_Type) GetICSCR1_MSICAL3() uint32 {
	return volatile.LoadUint32(&o.ICSCR1.Reg) & 0x1f
}
func (o *RCC_Type) SetICSCR1_MSICAL2(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0x3e0)|value<<5)
}
func (o *RCC_Type) GetICSCR1_MSICAL2() uint32 {
	return (volatile.LoadUint32(&o.ICSCR1.Reg) & 0x3e0) >> 5
}
func (o *RCC_Type) SetICSCR1_MSICAL1(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0x7c00)|value<<10)
}
func (o *RCC_Type) GetICSCR1_MSICAL1() uint32 {
	return (volatile.LoadUint32(&o.ICSCR1.Reg) & 0x7c00) >> 10
}
func (o *RCC_Type) SetICSCR1_MSICAL0(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0xf8000)|value<<15)
}
func (o *RCC_Type) GetICSCR1_MSICAL0() uint32 {
	return (volatile.LoadUint32(&o.ICSCR1.Reg) & 0xf8000) >> 15
}
func (o *RCC_Type) SetICSCR1_MSIBIAS(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetICSCR1_MSIBIAS() uint32 {
	return (volatile.LoadUint32(&o.ICSCR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetICSCR1_MSIRGSEL(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetICSCR1_MSIRGSEL() uint32 {
	return (volatile.LoadUint32(&o.ICSCR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetICSCR1_MSIKRANGE(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0xf000000)|value<<24)
}
func (o *RCC_Type) GetICSCR1_MSIKRANGE() uint32 {
	return (volatile.LoadUint32(&o.ICSCR1.Reg) & 0xf000000) >> 24
}
func (o *RCC_Type) SetICSCR1_MSISRANGE(value uint32) {
	volatile.StoreUint32(&o.ICSCR1.Reg, volatile.LoadUint32(&o.ICSCR1.Reg)&^(0xf0000000)|value<<28)
}
func (o *RCC_Type) GetICSCR1_MSISRANGE() uint32 {
	return (volatile.LoadUint32(&o.ICSCR1.Reg) & 0xf0000000) >> 28
}

// RCC.ICSCR2: RCC internal clock sources calibration register 2
func (o *RCC_Type) SetICSCR2_MSITRIM3(value uint32) {
	volatile.StoreUint32(&o.ICSCR2.Reg, volatile.LoadUint32(&o.ICSCR2.Reg)&^(0x1f)|value)
}
func (o *RCC_Type) GetICSCR2_MSITRIM3() uint32 {
	return volatile.LoadUint32(&o.ICSCR2.Reg) & 0x1f
}
func (o *RCC_Type) SetICSCR2_MSITRIM2(value uint32) {
	volatile.StoreUint32(&o.ICSCR2.Reg, volatile.LoadUint32(&o.ICSCR2.Reg)&^(0x3e0)|value<<5)
}
func (o *RCC_Type) GetICSCR2_MSITRIM2() uint32 {
	return (volatile.LoadUint32(&o.ICSCR2.Reg) & 0x3e0) >> 5
}
func (o *RCC_Type) SetICSCR2_MSITRIM1(value uint32) {
	volatile.StoreUint32(&o.ICSCR2.Reg, volatile.LoadUint32(&o.ICSCR2.Reg)&^(0x7c00)|value<<10)
}
func (o *RCC_Type) GetICSCR2_MSITRIM1() uint32 {
	return (volatile.LoadUint32(&o.ICSCR2.Reg) & 0x7c00) >> 10
}
func (o *RCC_Type) SetICSCR2_MSITRIM0(value uint32) {
	volatile.StoreUint32(&o.ICSCR2.Reg, volatile.LoadUint32(&o.ICSCR2.Reg)&^(0xf8000)|value<<15)
}
func (o *RCC_Type) GetICSCR2_MSITRIM0() uint32 {
	return (volatile.LoadUint32(&o.ICSCR2.Reg) & 0xf8000) >> 15
}

// RCC.ICSCR3: RCC internal clock sources calibration register 3
func (o *RCC_Type) SetICSCR3_HSICAL(value uint32) {
	volatile.StoreUint32(&o.ICSCR3.Reg, volatile.LoadUint32(&o.ICSCR3.Reg)&^(0xfff)|value)
}
func (o *RCC_Type) GetICSCR3_HSICAL() uint32 {
	return volatile.LoadUint32(&o.ICSCR3.Reg) & 0xfff
}
func (o *RCC_Type) SetICSCR3_HSITRIM(value uint32) {
	volatile.StoreUint32(&o.ICSCR3.Reg, volatile.LoadUint32(&o.ICSCR3.Reg)&^(0x1f0000)|value<<16)
}
func (o *RCC_Type) GetICSCR3_HSITRIM() uint32 {
	return (volatile.LoadUint32(&o.ICSCR3.Reg) & 0x1f0000) >> 16
}

// RCC.CRRCR: RCC clock recovery RC register
func (o *RCC_Type) SetCRRCR_HSI48CAL(value uint32) {
	volatile.StoreUint32(&o.CRRCR.Reg, volatile.LoadUint32(&o.CRRCR.Reg)&^(0x1ff)|value)
}
func (o *RCC_Type) GetCRRCR_HSI48CAL() uint32 {
	return volatile.LoadUint32(&o.CRRCR.Reg) & 0x1ff
}

// RCC.CFGR1: RCC clock configuration register 1
func (o *RCC_Type) SetCFGR1_SW(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetCFGR1_SW() uint32 {
	return volatile.LoadUint32(&o.CFGR1.Reg) & 0x3
}
func (o *RCC_Type) SetCFGR1_SWS(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetCFGR1_SWS() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetCFGR1_STOPWUCK(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCFGR1_STOPWUCK() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCFGR1_STOPKERWUCK(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCFGR1_STOPKERWUCK() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCFGR1_MCOSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xf000000)|value<<24)
}
func (o *RCC_Type) GetCFGR1_MCOSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xf000000) >> 24
}
func (o *RCC_Type) SetCFGR1_MCOPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x70000000)|value<<28)
}
func (o *RCC_Type) GetCFGR1_MCOPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x70000000) >> 28
}

// RCC.CFGR2: RCC clock configuration register 2
func (o *RCC_Type) SetCFGR2_HPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0xf)|value)
}
func (o *RCC_Type) GetCFGR2_HPRE() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0xf
}
func (o *RCC_Type) SetCFGR2_PPRE1(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x70)|value<<4)
}
func (o *RCC_Type) GetCFGR2_PPRE1() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x70) >> 4
}
func (o *RCC_Type) SetCFGR2_PPRE2(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x700)|value<<8)
}
func (o *RCC_Type) GetCFGR2_PPRE2() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x700) >> 8
}
func (o *RCC_Type) SetCFGR2_DPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x7000)|value<<12)
}
func (o *RCC_Type) GetCFGR2_DPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x7000) >> 12
}
func (o *RCC_Type) SetCFGR2_AHB1DIS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetCFGR2_AHB1DIS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetCFGR2_AHB2DIS1(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetCFGR2_AHB2DIS1() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetCFGR2_AHB2DIS2(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetCFGR2_AHB2DIS2() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetCFGR2_APB1DIS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetCFGR2_APB1DIS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetCFGR2_APB2DIS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetCFGR2_APB2DIS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x100000) >> 20
}

// RCC.CFGR3: RCC clock configuration register 3
func (o *RCC_Type) SetCFGR3_PPRE3(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x70)|value<<4)
}
func (o *RCC_Type) GetCFGR3_PPRE3() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x70) >> 4
}
func (o *RCC_Type) SetCFGR3_AHB3DIS(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetCFGR3_AHB3DIS() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetCFGR3_APB3DIS(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetCFGR3_APB3DIS() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x20000) >> 17
}

// RCC.PLL1CFGR: RCC PLL1 configuration register
func (o *RCC_Type) SetPLL1CFGR_PLL1SRC(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1SRC() uint32 {
	return volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0x3
}
func (o *RCC_Type) SetPLL1CFGR_PLL1RGE(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1RGE() uint32 {
	return (volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetPLL1CFGR_PLL1FRACEN(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1FRACEN() uint32 {
	return (volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetPLL1CFGR_PLL1M(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0xf00)|value<<8)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1M() uint32 {
	return (volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0xf00) >> 8
}
func (o *RCC_Type) SetPLL1CFGR_PLL1MBOOST(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0xf000)|value<<12)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1MBOOST() uint32 {
	return (volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0xf000) >> 12
}
func (o *RCC_Type) SetPLL1CFGR_PLL1PEN(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1PEN() uint32 {
	return (volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetPLL1CFGR_PLL1QEN(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1QEN() uint32 {
	return (volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetPLL1CFGR_PLL1REN(value uint32) {
	volatile.StoreUint32(&o.PLL1CFGR.Reg, volatile.LoadUint32(&o.PLL1CFGR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetPLL1CFGR_PLL1REN() uint32 {
	return (volatile.LoadUint32(&o.PLL1CFGR.Reg) & 0x40000) >> 18
}

// RCC.PLL2CFGR: RCC PLL2 configuration register
func (o *RCC_Type) SetPLL2CFGR_PLL2SRC(value uint32) {
	volatile.StoreUint32(&o.PLL2CFGR.Reg, volatile.LoadUint32(&o.PLL2CFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetPLL2CFGR_PLL2SRC() uint32 {
	return volatile.LoadUint32(&o.PLL2CFGR.Reg) & 0x3
}
func (o *RCC_Type) SetPLL2CFGR_PLL2RGE(value uint32) {
	volatile.StoreUint32(&o.PLL2CFGR.Reg, volatile.LoadUint32(&o.PLL2CFGR.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetPLL2CFGR_PLL2RGE() uint32 {
	return (volatile.LoadUint32(&o.PLL2CFGR.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetPLL2CFGR_PLL2FRACEN(value uint32) {
	volatile.StoreUint32(&o.PLL2CFGR.Reg, volatile.LoadUint32(&o.PLL2CFGR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetPLL2CFGR_PLL2FRACEN() uint32 {
	return (volatile.LoadUint32(&o.PLL2CFGR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetPLL2CFGR_PLL2M(value uint32) {
	volatile.StoreUint32(&o.PLL2CFGR.Reg, volatile.LoadUint32(&o.PLL2CFGR.Reg)&^(0xf00)|value<<8)
}
func (o *RCC_Type) GetPLL2CFGR_PLL2M() uint32 {
	return (volatile.LoadUint32(&o.PLL2CFGR.Reg) & 0xf00) >> 8
}
func (o *RCC_Type) SetPLL2CFGR_PLL2PEN(value uint32) {
	volatile.StoreUint32(&o.PLL2CFGR.Reg, volatile.LoadUint32(&o.PLL2CFGR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetPLL2CFGR_PLL2PEN() uint32 {
	return (volatile.LoadUint32(&o.PLL2CFGR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetPLL2CFGR_PLL2QEN(value uint32) {
	volatile.StoreUint32(&o.PLL2CFGR.Reg, volatile.LoadUint32(&o.PLL2CFGR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetPLL2CFGR_PLL2QEN() uint32 {
	return (volatile.LoadUint32(&o.PLL2CFGR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetPLL2CFGR_PLL2REN(value uint32) {
	volatile.StoreUint32(&o.PLL2CFGR.Reg, volatile.LoadUint32(&o.PLL2CFGR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetPLL2CFGR_PLL2REN() uint32 {
	return (volatile.LoadUint32(&o.PLL2CFGR.Reg) & 0x40000) >> 18
}

// RCC.PLL3CFGR: RCC PLL3 configuration register
func (o *RCC_Type) SetPLL3CFGR_PLL3SRC(value uint32) {
	volatile.StoreUint32(&o.PLL3CFGR.Reg, volatile.LoadUint32(&o.PLL3CFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetPLL3CFGR_PLL3SRC() uint32 {
	return volatile.LoadUint32(&o.PLL3CFGR.Reg) & 0x3
}
func (o *RCC_Type) SetPLL3CFGR_PLL3RGE(value uint32) {
	volatile.StoreUint32(&o.PLL3CFGR.Reg, volatile.LoadUint32(&o.PLL3CFGR.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetPLL3CFGR_PLL3RGE() uint32 {
	return (volatile.LoadUint32(&o.PLL3CFGR.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetPLL3CFGR_PLL3FRACEN(value uint32) {
	volatile.StoreUint32(&o.PLL3CFGR.Reg, volatile.LoadUint32(&o.PLL3CFGR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetPLL3CFGR_PLL3FRACEN() uint32 {
	return (volatile.LoadUint32(&o.PLL3CFGR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetPLL3CFGR_PLL3M(value uint32) {
	volatile.StoreUint32(&o.PLL3CFGR.Reg, volatile.LoadUint32(&o.PLL3CFGR.Reg)&^(0xf00)|value<<8)
}
func (o *RCC_Type) GetPLL3CFGR_PLL3M() uint32 {
	return (volatile.LoadUint32(&o.PLL3CFGR.Reg) & 0xf00) >> 8
}
func (o *RCC_Type) SetPLL3CFGR_PLL3PEN(value uint32) {
	volatile.StoreUint32(&o.PLL3CFGR.Reg, volatile.LoadUint32(&o.PLL3CFGR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetPLL3CFGR_PLL3PEN() uint32 {
	return (volatile.LoadUint32(&o.PLL3CFGR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetPLL3CFGR_PLL3QEN(value uint32) {
	volatile.StoreUint32(&o.PLL3CFGR.Reg, volatile.LoadUint32(&o.PLL3CFGR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetPLL3CFGR_PLL3QEN() uint32 {
	return (volatile.LoadUint32(&o.PLL3CFGR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetPLL3CFGR_PLL3REN(value uint32) {
	volatile.StoreUint32(&o.PLL3CFGR.Reg, volatile.LoadUint32(&o.PLL3CFGR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetPLL3CFGR_PLL3REN() uint32 {
	return (volatile.LoadUint32(&o.PLL3CFGR.Reg) & 0x40000) >> 18
}

// RCC.PLL1DIVR: RCC PLL1 dividers register
func (o *RCC_Type) SetPLL1DIVR_PLL1N(value uint32) {
	volatile.StoreUint32(&o.PLL1DIVR.Reg, volatile.LoadUint32(&o.PLL1DIVR.Reg)&^(0x1ff)|value)
}
func (o *RCC_Type) GetPLL1DIVR_PLL1N() uint32 {
	return volatile.LoadUint32(&o.PLL1DIVR.Reg) & 0x1ff
}
func (o *RCC_Type) SetPLL1DIVR_PLL1P(value uint32) {
	volatile.StoreUint32(&o.PLL1DIVR.Reg, volatile.LoadUint32(&o.PLL1DIVR.Reg)&^(0xfe00)|value<<9)
}
func (o *RCC_Type) GetPLL1DIVR_PLL1P() uint32 {
	return (volatile.LoadUint32(&o.PLL1DIVR.Reg) & 0xfe00) >> 9
}
func (o *RCC_Type) SetPLL1DIVR_PLL1Q(value uint32) {
	volatile.StoreUint32(&o.PLL1DIVR.Reg, volatile.LoadUint32(&o.PLL1DIVR.Reg)&^(0x7f0000)|value<<16)
}
func (o *RCC_Type) GetPLL1DIVR_PLL1Q() uint32 {
	return (volatile.LoadUint32(&o.PLL1DIVR.Reg) & 0x7f0000) >> 16
}
func (o *RCC_Type) SetPLL1DIVR_PLL1R(value uint32) {
	volatile.StoreUint32(&o.PLL1DIVR.Reg, volatile.LoadUint32(&o.PLL1DIVR.Reg)&^(0x7f000000)|value<<24)
}
func (o *RCC_Type) GetPLL1DIVR_PLL1R() uint32 {
	return (volatile.LoadUint32(&o.PLL1DIVR.Reg) & 0x7f000000) >> 24
}

// RCC.PLL1FRACR: RCC PLL1 fractional divider register
func (o *RCC_Type) SetPLL1FRACR_PLL1FRACN(value uint32) {
	volatile.StoreUint32(&o.PLL1FRACR.Reg, volatile.LoadUint32(&o.PLL1FRACR.Reg)&^(0xfff8)|value<<3)
}
func (o *RCC_Type) GetPLL1FRACR_PLL1FRACN() uint32 {
	return (volatile.LoadUint32(&o.PLL1FRACR.Reg) & 0xfff8) >> 3
}

// RCC.PLL2DIVR: RCC PLL2 dividers configuration register
func (o *RCC_Type) SetPLL2DIVR_PLL2N(value uint32) {
	volatile.StoreUint32(&o.PLL2DIVR.Reg, volatile.LoadUint32(&o.PLL2DIVR.Reg)&^(0x1ff)|value)
}
func (o *RCC_Type) GetPLL2DIVR_PLL2N() uint32 {
	return volatile.LoadUint32(&o.PLL2DIVR.Reg) & 0x1ff
}
func (o *RCC_Type) SetPLL2DIVR_PLL2P(value uint32) {
	volatile.StoreUint32(&o.PLL2DIVR.Reg, volatile.LoadUint32(&o.PLL2DIVR.Reg)&^(0xfe00)|value<<9)
}
func (o *RCC_Type) GetPLL2DIVR_PLL2P() uint32 {
	return (volatile.LoadUint32(&o.PLL2DIVR.Reg) & 0xfe00) >> 9
}
func (o *RCC_Type) SetPLL2DIVR_PLL2Q(value uint32) {
	volatile.StoreUint32(&o.PLL2DIVR.Reg, volatile.LoadUint32(&o.PLL2DIVR.Reg)&^(0x7f0000)|value<<16)
}
func (o *RCC_Type) GetPLL2DIVR_PLL2Q() uint32 {
	return (volatile.LoadUint32(&o.PLL2DIVR.Reg) & 0x7f0000) >> 16
}
func (o *RCC_Type) SetPLL2DIVR_PLL2R(value uint32) {
	volatile.StoreUint32(&o.PLL2DIVR.Reg, volatile.LoadUint32(&o.PLL2DIVR.Reg)&^(0x7f000000)|value<<24)
}
func (o *RCC_Type) GetPLL2DIVR_PLL2R() uint32 {
	return (volatile.LoadUint32(&o.PLL2DIVR.Reg) & 0x7f000000) >> 24
}

// RCC.PLL2FRACR: RCC PLL2 fractional divider register
func (o *RCC_Type) SetPLL2FRACR_PLL2FRACN(value uint32) {
	volatile.StoreUint32(&o.PLL2FRACR.Reg, volatile.LoadUint32(&o.PLL2FRACR.Reg)&^(0xfff8)|value<<3)
}
func (o *RCC_Type) GetPLL2FRACR_PLL2FRACN() uint32 {
	return (volatile.LoadUint32(&o.PLL2FRACR.Reg) & 0xfff8) >> 3
}

// RCC.PLL3DIVR: RCC PLL3 dividers configuration register
func (o *RCC_Type) SetPLL3DIVR_PLL3N(value uint32) {
	volatile.StoreUint32(&o.PLL3DIVR.Reg, volatile.LoadUint32(&o.PLL3DIVR.Reg)&^(0x1ff)|value)
}
func (o *RCC_Type) GetPLL3DIVR_PLL3N() uint32 {
	return volatile.LoadUint32(&o.PLL3DIVR.Reg) & 0x1ff
}
func (o *RCC_Type) SetPLL3DIVR_PLL3P(value uint32) {
	volatile.StoreUint32(&o.PLL3DIVR.Reg, volatile.LoadUint32(&o.PLL3DIVR.Reg)&^(0xfe00)|value<<9)
}
func (o *RCC_Type) GetPLL3DIVR_PLL3P() uint32 {
	return (volatile.LoadUint32(&o.PLL3DIVR.Reg) & 0xfe00) >> 9
}
func (o *RCC_Type) SetPLL3DIVR_PLL3Q(value uint32) {
	volatile.StoreUint32(&o.PLL3DIVR.Reg, volatile.LoadUint32(&o.PLL3DIVR.Reg)&^(0x7f0000)|value<<16)
}
func (o *RCC_Type) GetPLL3DIVR_PLL3Q() uint32 {
	return (volatile.LoadUint32(&o.PLL3DIVR.Reg) & 0x7f0000) >> 16
}
func (o *RCC_Type) SetPLL3DIVR_PLL3R(value uint32) {
	volatile.StoreUint32(&o.PLL3DIVR.Reg, volatile.LoadUint32(&o.PLL3DIVR.Reg)&^(0x7f000000)|value<<24)
}
func (o *RCC_Type) GetPLL3DIVR_PLL3R() uint32 {
	return (volatile.LoadUint32(&o.PLL3DIVR.Reg) & 0x7f000000) >> 24
}

// RCC.PLL3FRACR: RCC PLL3 fractional divider register
func (o *RCC_Type) SetPLL3FRACR_PLL3FRACN(value uint32) {
	volatile.StoreUint32(&o.PLL3FRACR.Reg, volatile.LoadUint32(&o.PLL3FRACR.Reg)&^(0xfff8)|value<<3)
}
func (o *RCC_Type) GetPLL3FRACR_PLL3FRACN() uint32 {
	return (volatile.LoadUint32(&o.PLL3FRACR.Reg) & 0xfff8) >> 3
}

// RCC.CIER: RCC clock interrupt enable register
func (o *RCC_Type) SetCIER_LSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIER_LSIRDYIE() uint32 {
	return volatile.LoadUint32(&o.CIER.Reg) & 0x1
}
func (o *RCC_Type) SetCIER_LSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIER_LSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIER_MSISRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCIER_MSISRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCIER_HSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIER_HSIRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIER_HSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIER_HSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIER_HSI48RDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIER_HSI48RDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCIER_PLL1RDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCIER_PLL1RDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCIER_PLL2RDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCIER_PLL2RDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCIER_PLL3RDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCIER_PLL3RDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCIER_MSIKRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetCIER_MSIKRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetCIER_SHSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetCIER_SHSIRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x1000) >> 12
}

// RCC.CIFR: RCC clock interrupt flag register
func (o *RCC_Type) SetCIFR_LSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIFR_LSIRDYF() uint32 {
	return volatile.LoadUint32(&o.CIFR.Reg) & 0x1
}
func (o *RCC_Type) SetCIFR_LSERDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIFR_LSERDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIFR_MSISRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCIFR_MSISRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCIFR_HSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIFR_HSIRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIFR_HSERDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIFR_HSERDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIFR_HSI48RDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIFR_HSI48RDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCIFR_PLL1RDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCIFR_PLL1RDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCIFR_PLL2RDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCIFR_PLL2RDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCIFR_PLL3RDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCIFR_PLL3RDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCIFR_CSSF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCIFR_CSSF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetCIFR_MSIKRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetCIFR_MSIKRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetCIFR_SHSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetCIFR_SHSIRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x1000) >> 12
}

// RCC.CICR: RCC clock interrupt clear register
func (o *RCC_Type) SetCICR_LSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCICR_LSIRDYC() uint32 {
	return volatile.LoadUint32(&o.CICR.Reg) & 0x1
}
func (o *RCC_Type) SetCICR_LSERDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCICR_LSERDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCICR_MSISRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCICR_MSISRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCICR_HSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCICR_HSIRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCICR_HSERDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCICR_HSERDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCICR_HSI48RDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCICR_HSI48RDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCICR_PLL1RDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCICR_PLL1RDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCICR_PLL2RDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCICR_PLL2RDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCICR_PLL3RDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCICR_PLL3RDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCICR_CSSC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCICR_CSSC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetCICR_MSIKRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetCICR_MSIKRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetCICR_SHSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetCICR_SHSIRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x1000) >> 12
}

// RCC.AHB1RSTR: RCC AHB1 peripheral reset register
func (o *RCC_Type) SetAHB1RSTR_GPDMA1RST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB1RSTR_GPDMA1RST() uint32 {
	return volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB1RSTR_CORDICRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB1RSTR_CORDICRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB1RSTR_FMACRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB1RSTR_FMACRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB1RSTR_MDF1RST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB1RSTR_MDF1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB1RSTR_CRCRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB1RSTR_CRCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB1RSTR_JPEGRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAHB1RSTR_JPEGRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAHB1RSTR_TSCRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB1RSTR_TSCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB1RSTR_RAMCFGRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB1RSTR_RAMCFGRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB1RSTR_DMA2DRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB1RSTR_DMA2DRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB1RSTR_GFXMMURST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB1RSTR_GFXMMURST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB1RSTR_GPU2DRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAHB1RSTR_GPU2DRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x100000) >> 20
}

// RCC.AHB2RSTR1: RCC AHB2 peripheral reset register 1
func (o *RCC_Type) SetAHB2RSTR1_GPIOARST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOARST() uint32 {
	return volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOBRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOBRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOCRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB2RSTR1_GPIODRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIODRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOERST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOERST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOFRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOFRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOGRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOGRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOHRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOHRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOIRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOIRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB2RSTR1_GPIOJRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB2RSTR1_GPIOJRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB2RSTR1_ADC12RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAHB2RSTR1_ADC12RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAHB2RSTR1_DCMI_PSSIRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB2RSTR1_DCMI_PSSIRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB2RSTR1_OTGRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAHB2RSTR1_OTGRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAHB2RSTR1_AESRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB2RSTR1_AESRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB2RSTR1_HASHRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB2RSTR1_HASHRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB2RSTR1_RNGRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB2RSTR1_RNGRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB2RSTR1_PKARST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB2RSTR1_PKARST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB2RSTR1_SAESRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAHB2RSTR1_SAESRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAHB2RSTR1_OCTOSPIMRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB2RSTR1_OCTOSPIMRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB2RSTR1_OTFDEC1RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAHB2RSTR1_OTFDEC1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAHB2RSTR1_OTFDEC2RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAHB2RSTR1_OTFDEC2RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAHB2RSTR1_SDMMC1RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAHB2RSTR1_SDMMC1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetAHB2RSTR1_SDMMC2RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR1.Reg, volatile.LoadUint32(&o.AHB2RSTR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAHB2RSTR1_SDMMC2RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR1.Reg) & 0x10000000) >> 28
}

// RCC.AHB2RSTR2: RCC AHB2 peripheral reset register 2
func (o *RCC_Type) SetAHB2RSTR2_FSMCRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR2.Reg, volatile.LoadUint32(&o.AHB2RSTR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2RSTR2_FSMCRST() uint32 {
	return volatile.LoadUint32(&o.AHB2RSTR2.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2RSTR2_OCTOSPI1RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR2.Reg, volatile.LoadUint32(&o.AHB2RSTR2.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2RSTR2_OCTOSPI1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR2.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2RSTR2_OCTOSPI2RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR2.Reg, volatile.LoadUint32(&o.AHB2RSTR2.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB2RSTR2_OCTOSPI2RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR2.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB2RSTR2_HSPI1RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR2.Reg, volatile.LoadUint32(&o.AHB2RSTR2.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB2RSTR2_HSPI1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR2.Reg) & 0x1000) >> 12
}

// RCC.AHB3RSTR: RCC AHB3 peripheral reset register
func (o *RCC_Type) SetAHB3RSTR_LPGPIO1RST(value uint32) {
	volatile.StoreUint32(&o.AHB3RSTR.Reg, volatile.LoadUint32(&o.AHB3RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB3RSTR_LPGPIO1RST() uint32 {
	return volatile.LoadUint32(&o.AHB3RSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB3RSTR_ADC4RST(value uint32) {
	volatile.StoreUint32(&o.AHB3RSTR.Reg, volatile.LoadUint32(&o.AHB3RSTR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB3RSTR_ADC4RST() uint32 {
	return (volatile.LoadUint32(&o.AHB3RSTR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB3RSTR_DAC1RST(value uint32) {
	volatile.StoreUint32(&o.AHB3RSTR.Reg, volatile.LoadUint32(&o.AHB3RSTR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB3RSTR_DAC1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB3RSTR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB3RSTR_LPDMA1RST(value uint32) {
	volatile.StoreUint32(&o.AHB3RSTR.Reg, volatile.LoadUint32(&o.AHB3RSTR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB3RSTR_LPDMA1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB3RSTR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB3RSTR_ADF1RST(value uint32) {
	volatile.StoreUint32(&o.AHB3RSTR.Reg, volatile.LoadUint32(&o.AHB3RSTR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAHB3RSTR_ADF1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB3RSTR.Reg) & 0x400) >> 10
}

// RCC.APB1RSTR1: RCC APB1 peripheral reset register 1
func (o *RCC_Type) SetAPB1RSTR1_TIM2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM2RST() uint32 {
	return volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1RSTR1_TIM3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1RSTR1_TIM4RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM4RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB1RSTR1_TIM5RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM5RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAPB1RSTR1_TIM6RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM6RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1RSTR1_TIM7RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM7RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1RSTR1_SPI2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1RSTR1_SPI2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1RSTR1_USART2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB1RSTR1_USART2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB1RSTR1_USART3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB1RSTR1_USART3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB1RSTR1_UART4RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAPB1RSTR1_UART4RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAPB1RSTR1_UART5RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB1RSTR1_UART5RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB1RSTR1_I2C1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1RSTR1_I2C1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1RSTR1_I2C2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB1RSTR1_I2C2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB1RSTR1_CRSRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB1RSTR1_CRSRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB1RSTR1_USART6RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetAPB1RSTR1_USART6RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x2000000) >> 25
}

// RCC.APB1RSTR2: RCC APB1 peripheral reset register 2
func (o *RCC_Type) SetAPB1RSTR2_I2C4RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1RSTR2_I2C4RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1RSTR2_LPTIM2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1RSTR2_LPTIM2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1RSTR2_I2C5RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB1RSTR2_I2C5RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB1RSTR2_I2C6RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAPB1RSTR2_I2C6RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAPB1RSTR2_FDCAN1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAPB1RSTR2_FDCAN1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAPB1RSTR2_UCPD1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1RSTR2_UCPD1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x800000) >> 23
}

// RCC.APB2RSTR: RCC APB2 peripheral reset register
func (o *RCC_Type) SetAPB2RSTR_TIM1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB2RSTR_TIM1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB2RSTR_SPI1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB2RSTR_SPI1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB2RSTR_TIM8RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB2RSTR_TIM8RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB2RSTR_USART1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB2RSTR_USART1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB2RSTR_TIM15RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPB2RSTR_TIM15RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPB2RSTR_TIM16RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB2RSTR_TIM16RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB2RSTR_TIM17RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB2RSTR_TIM17RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB2RSTR_SAI1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB2RSTR_SAI1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB2RSTR_SAI2RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB2RSTR_SAI2RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB2RSTR_USBRST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB2RSTR_USBRST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB2RSTR_GFXTIMRST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetAPB2RSTR_GFXTIMRST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetAPB2RSTR_LTDCRST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetAPB2RSTR_LTDCRST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetAPB2RSTR_DSIRST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAPB2RSTR_DSIRST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x8000000) >> 27
}

// RCC.APB3RSTR: RCC APB3 peripheral reset register
func (o *RCC_Type) SetAPB3RSTR_SYSCFGRST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB3RSTR_SYSCFGRST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB3RSTR_SPI3RST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB3RSTR_SPI3RST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB3RSTR_LPUART1RST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB3RSTR_LPUART1RST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB3RSTR_I2C3RST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAPB3RSTR_I2C3RST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAPB3RSTR_LPTIM1RST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB3RSTR_LPTIM1RST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB3RSTR_LPTIM3RST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB3RSTR_LPTIM3RST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB3RSTR_LPTIM4RST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB3RSTR_LPTIM4RST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB3RSTR_OPAMPRST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB3RSTR_OPAMPRST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB3RSTR_COMPRST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPB3RSTR_COMPRST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPB3RSTR_VREFRST(value uint32) {
	volatile.StoreUint32(&o.APB3RSTR.Reg, volatile.LoadUint32(&o.APB3RSTR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB3RSTR_VREFRST() uint32 {
	return (volatile.LoadUint32(&o.APB3RSTR.Reg) & 0x100000) >> 20
}

// RCC.AHB1ENR: RCC AHB1 peripheral clock enable register
func (o *RCC_Type) SetAHB1ENR_GPDMA1EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB1ENR_GPDMA1EN() uint32 {
	return volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB1ENR_CORDICEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB1ENR_CORDICEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB1ENR_FMACEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB1ENR_FMACEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB1ENR_MDF1EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB1ENR_MDF1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB1ENR_FLASHEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB1ENR_FLASHEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB1ENR_CRCEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB1ENR_CRCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB1ENR_JPEGEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAHB1ENR_JPEGEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAHB1ENR_TSCEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB1ENR_TSCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB1ENR_RAMCFGEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB1ENR_RAMCFGEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB1ENR_DMA2DEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB1ENR_DMA2DEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB1ENR_GFXMMUEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB1ENR_GFXMMUEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB1ENR_GPU2DEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAHB1ENR_GPU2DEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAHB1ENR_DCACHE2EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB1ENR_DCACHE2EN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB1ENR_GTZC1EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAHB1ENR_GTZC1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAHB1ENR_BKPSRAMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAHB1ENR_BKPSRAMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAHB1ENR_DCACHE1EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAHB1ENR_DCACHE1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAHB1ENR_SRAM1EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB1ENR_SRAM1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x80000000) >> 31
}

// RCC.AHB2ENR1: RCC AHB2 peripheral clock enable register 1
func (o *RCC_Type) SetAHB2ENR1_GPIOAEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOAEN() uint32 {
	return volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2ENR1_GPIOBEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOBEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB2ENR1_GPIOCEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB2ENR1_GPIODEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB2ENR1_GPIODEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB2ENR1_GPIOEEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOEEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2ENR1_GPIOFEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOFEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB2ENR1_GPIOGEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOGEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB2ENR1_GPIOHEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOHEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAHB2ENR1_GPIOIEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOIEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB2ENR1_GPIOJEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB2ENR1_GPIOJEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB2ENR1_ADC12EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAHB2ENR1_ADC12EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAHB2ENR1_DCMI_PSSIEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB2ENR1_DCMI_PSSIEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB2ENR1_OTGEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAHB2ENR1_OTGEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAHB2ENR1_OTGHSPHYEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAHB2ENR1_OTGHSPHYEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAHB2ENR1_AESEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB2ENR1_AESEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB2ENR1_HASHEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB2ENR1_HASHEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB2ENR1_RNGEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB2ENR1_RNGEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB2ENR1_PKAEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB2ENR1_PKAEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB2ENR1_SAESEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAHB2ENR1_SAESEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAHB2ENR1_OCTOSPIMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB2ENR1_OCTOSPIMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB2ENR1_OTFDEC1EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAHB2ENR1_OTFDEC1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAHB2ENR1_OTFDEC2EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAHB2ENR1_OTFDEC2EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAHB2ENR1_SDMMC1EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAHB2ENR1_SDMMC1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetAHB2ENR1_SDMMC2EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAHB2ENR1_SDMMC2EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAHB2ENR1_SRAM2EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAHB2ENR1_SRAM2EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAHB2ENR1_SRAM3EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR1.Reg, volatile.LoadUint32(&o.AHB2ENR1.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB2ENR1_SRAM3EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR1.Reg) & 0x80000000) >> 31
}

// RCC.AHB2ENR2: RCC AHB2 peripheral clock enable register 2
func (o *RCC_Type) SetAHB2ENR2_FSMCEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR2.Reg, volatile.LoadUint32(&o.AHB2ENR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2ENR2_FSMCEN() uint32 {
	return volatile.LoadUint32(&o.AHB2ENR2.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2ENR2_OCTOSPI1EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR2.Reg, volatile.LoadUint32(&o.AHB2ENR2.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2ENR2_OCTOSPI1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR2.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2ENR2_OCTOSPI2EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR2.Reg, volatile.LoadUint32(&o.AHB2ENR2.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB2ENR2_OCTOSPI2EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR2.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB2ENR2_HSPI1EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR2.Reg, volatile.LoadUint32(&o.AHB2ENR2.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB2ENR2_HSPI1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR2.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB2ENR2_SRAM6EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR2.Reg, volatile.LoadUint32(&o.AHB2ENR2.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAHB2ENR2_SRAM6EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR2.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAHB2ENR2_SRAM5EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR2.Reg, volatile.LoadUint32(&o.AHB2ENR2.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB2ENR2_SRAM5EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR2.Reg) & 0x80000000) >> 31
}

// RCC.AHB3ENR: RCC AHB3 peripheral clock enable register
func (o *RCC_Type) SetAHB3ENR_LPGPIO1EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB3ENR_LPGPIO1EN() uint32 {
	return volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB3ENR_PWREN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB3ENR_PWREN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB3ENR_ADC4EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB3ENR_ADC4EN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB3ENR_DAC1EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB3ENR_DAC1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB3ENR_LPDMA1EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB3ENR_LPDMA1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB3ENR_ADF1EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAHB3ENR_ADF1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAHB3ENR_GTZC2EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB3ENR_GTZC2EN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB3ENR_SRAM4EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB3ENR_SRAM4EN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x80000000) >> 31
}

// RCC.APB1ENR1: RCC APB1 peripheral clock enable register 1
func (o *RCC_Type) SetAPB1ENR1_TIM2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1ENR1_TIM2EN() uint32 {
	return volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1ENR1_TIM3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1ENR1_TIM3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1ENR1_TIM4EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB1ENR1_TIM4EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB1ENR1_TIM5EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAPB1ENR1_TIM5EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAPB1ENR1_TIM6EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1ENR1_TIM6EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1ENR1_TIM7EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1ENR1_TIM7EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1ENR1_WWDGEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB1ENR1_WWDGEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB1ENR1_SPI2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1ENR1_SPI2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1ENR1_USART2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB1ENR1_USART2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB1ENR1_USART3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB1ENR1_USART3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB1ENR1_UART4EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAPB1ENR1_UART4EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAPB1ENR1_UART5EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB1ENR1_UART5EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB1ENR1_I2C1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1ENR1_I2C1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1ENR1_I2C2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB1ENR1_I2C2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB1ENR1_CRSEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB1ENR1_CRSEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB1ENR1_USART6EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetAPB1ENR1_USART6EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x2000000) >> 25
}

// RCC.APB1ENR2: RCC APB1 peripheral clock enable register 2
func (o *RCC_Type) SetAPB1ENR2_I2C4EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1ENR2_I2C4EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1ENR2_LPTIM2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1ENR2_LPTIM2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1ENR2_I2C5EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB1ENR2_I2C5EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB1ENR2_I2C6EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAPB1ENR2_I2C6EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAPB1ENR2_FDCAN1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAPB1ENR2_FDCAN1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAPB1ENR2_UCPD1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1ENR2_UCPD1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x800000) >> 23
}

// RCC.APB2ENR: RCC APB2 peripheral clock enable register
func (o *RCC_Type) SetAPB2ENR_TIM1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB2ENR_TIM1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB2ENR_SPI1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB2ENR_SPI1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB2ENR_TIM8EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB2ENR_TIM8EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB2ENR_USART1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB2ENR_USART1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB2ENR_TIM15EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPB2ENR_TIM15EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPB2ENR_TIM16EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB2ENR_TIM16EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB2ENR_TIM17EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB2ENR_TIM17EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB2ENR_SAI1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB2ENR_SAI1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB2ENR_SAI2EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB2ENR_SAI2EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB2ENR_USBEN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB2ENR_USBEN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB2ENR_GFXTIMEN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetAPB2ENR_GFXTIMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetAPB2ENR_LTDCEN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetAPB2ENR_LTDCEN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetAPB2ENR_DSIEN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAPB2ENR_DSIEN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x8000000) >> 27
}

// RCC.APB3ENR: RCC APB3 peripheral clock enable register
func (o *RCC_Type) SetAPB3ENR_SYSCFGEN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB3ENR_SYSCFGEN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB3ENR_SPI3EN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB3ENR_SPI3EN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB3ENR_LPUART1EN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB3ENR_LPUART1EN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB3ENR_I2C3EN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAPB3ENR_I2C3EN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAPB3ENR_LPTIM1EN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB3ENR_LPTIM1EN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB3ENR_LPTIM3EN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB3ENR_LPTIM3EN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB3ENR_LPTIM4EN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB3ENR_LPTIM4EN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB3ENR_OPAMPEN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB3ENR_OPAMPEN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB3ENR_COMPEN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPB3ENR_COMPEN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPB3ENR_VREFEN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB3ENR_VREFEN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB3ENR_RTCAPBEN(value uint32) {
	volatile.StoreUint32(&o.APB3ENR.Reg, volatile.LoadUint32(&o.APB3ENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB3ENR_RTCAPBEN() uint32 {
	return (volatile.LoadUint32(&o.APB3ENR.Reg) & 0x200000) >> 21
}

// RCC.AHB1SMENR: RCC AHB1 peripheral clock enable in Sleep and Stop modes register
func (o *RCC_Type) SetAHB1SMENR_GPDMA1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB1SMENR_GPDMA1SMEN() uint32 {
	return volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB1SMENR_CORDICSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB1SMENR_CORDICSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB1SMENR_FMACSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB1SMENR_FMACSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB1SMENR_MDF1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB1SMENR_MDF1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB1SMENR_FLASHSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB1SMENR_FLASHSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB1SMENR_CRCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB1SMENR_CRCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB1SMENR_JPEGSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAHB1SMENR_JPEGSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAHB1SMENR_TSCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB1SMENR_TSCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB1SMENR_RAMCFGSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB1SMENR_RAMCFGSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB1SMENR_DMA2DSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB1SMENR_DMA2DSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB1SMENR_GFXMMUSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB1SMENR_GFXMMUSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB1SMENR_GPU2DSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAHB1SMENR_GPU2DSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAHB1SMENR_DCACHE2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB1SMENR_DCACHE2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB1SMENR_GTZC1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAHB1SMENR_GTZC1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAHB1SMENR_BKPSRAMSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAHB1SMENR_BKPSRAMSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAHB1SMENR_ICACHESMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetAHB1SMENR_ICACHESMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetAHB1SMENR_DCACHE1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAHB1SMENR_DCACHE1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAHB1SMENR_SRAM1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB1SMENR_SRAM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x80000000) >> 31
}

// RCC.AHB2SMENR1: RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1
func (o *RCC_Type) SetAHB2SMENR1_GPIOASMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOASMEN() uint32 {
	return volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOBSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOBSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB2SMENR1_GPIODSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIODSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOESMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOESMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOFSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOFSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOGSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOGSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOHSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOHSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOISMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOISMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB2SMENR1_GPIOJSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB2SMENR1_GPIOJSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB2SMENR1_ADC12SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAHB2SMENR1_ADC12SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAHB2SMENR1_DCMI_PSSISMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB2SMENR1_DCMI_PSSISMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB2SMENR1_OTGSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAHB2SMENR1_OTGSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAHB2SMENR1_OTGHSPHYSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAHB2SMENR1_OTGHSPHYSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAHB2SMENR1_AESSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB2SMENR1_AESSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB2SMENR1_HASHSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB2SMENR1_HASHSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB2SMENR1_RNGSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB2SMENR1_RNGSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB2SMENR1_PKASMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB2SMENR1_PKASMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB2SMENR1_SAESSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAHB2SMENR1_SAESSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAHB2SMENR1_OCTOSPIMSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB2SMENR1_OCTOSPIMSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB2SMENR1_OTFDEC1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAHB2SMENR1_OTFDEC1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAHB2SMENR1_OTFDEC2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAHB2SMENR1_OTFDEC2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAHB2SMENR1_SDMMC1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAHB2SMENR1_SDMMC1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetAHB2SMENR1_SDMMC2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAHB2SMENR1_SDMMC2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAHB2SMENR1_SRAM2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAHB2SMENR1_SRAM2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAHB2SMENR1_SRAM3SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR1.Reg, volatile.LoadUint32(&o.AHB2SMENR1.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB2SMENR1_SRAM3SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR1.Reg) & 0x80000000) >> 31
}

// RCC.AHB2SMENR2: RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2
func (o *RCC_Type) SetAHB2SMENR2_FSMCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR2.Reg, volatile.LoadUint32(&o.AHB2SMENR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2SMENR2_FSMCSMEN() uint32 {
	return volatile.LoadUint32(&o.AHB2SMENR2.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2SMENR2_OCTOSPI1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR2.Reg, volatile.LoadUint32(&o.AHB2SMENR2.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2SMENR2_OCTOSPI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR2.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2SMENR2_OCTOSPI2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR2.Reg, volatile.LoadUint32(&o.AHB2SMENR2.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB2SMENR2_OCTOSPI2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR2.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB2SMENR2_HSPI1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR2.Reg, volatile.LoadUint32(&o.AHB2SMENR2.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB2SMENR2_HSPI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR2.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB2SMENR2_SRAM6SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR2.Reg, volatile.LoadUint32(&o.AHB2SMENR2.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAHB2SMENR2_SRAM6SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR2.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAHB2SMENR2_SRAM5SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR2.Reg, volatile.LoadUint32(&o.AHB2SMENR2.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB2SMENR2_SRAM5SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR2.Reg) & 0x80000000) >> 31
}

// RCC.AHB3SMENR: RCC AHB3 peripheral clock enable in Sleep and Stop modes register
func (o *RCC_Type) SetAHB3SMENR_LPGPIO1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB3SMENR_LPGPIO1SMEN() uint32 {
	return volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB3SMENR_PWRSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB3SMENR_PWRSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB3SMENR_ADC4SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB3SMENR_ADC4SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB3SMENR_DAC1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB3SMENR_DAC1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB3SMENR_LPDMA1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB3SMENR_LPDMA1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB3SMENR_ADF1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAHB3SMENR_ADF1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAHB3SMENR_GTZC2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB3SMENR_GTZC2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB3SMENR_SRAM4SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAHB3SMENR_SRAM4SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x80000000) >> 31
}

// RCC.APB1SMENR1: RCC APB1 peripheral clock enable in Sleep and Stop modes register 1
func (o *RCC_Type) SetAPB1SMENR1_TIM2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM2SMEN() uint32 {
	return volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1SMENR1_TIM3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1SMENR1_TIM4SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM4SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB1SMENR1_TIM5SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM5SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAPB1SMENR1_TIM6SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM6SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1SMENR1_TIM7SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM7SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1SMENR1_WWDGSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB1SMENR1_WWDGSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB1SMENR1_SPI2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1SMENR1_SPI2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1SMENR1_USART2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB1SMENR1_USART2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB1SMENR1_USART3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB1SMENR1_USART3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB1SMENR1_UART4SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAPB1SMENR1_UART4SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAPB1SMENR1_UART5SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB1SMENR1_UART5SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB1SMENR1_I2C1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1SMENR1_I2C1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1SMENR1_I2C2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB1SMENR1_I2C2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB1SMENR1_CRSSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB1SMENR1_CRSSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB1SMENR1_USART6SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetAPB1SMENR1_USART6SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x2000000) >> 25
}

// RCC.APB1SMENR2: RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2
func (o *RCC_Type) SetAPB1SMENR2_I2C4SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1SMENR2_I2C4SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1SMENR2_LPTIM2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1SMENR2_LPTIM2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1SMENR2_I2C5SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB1SMENR2_I2C5SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB1SMENR2_I2C6SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAPB1SMENR2_I2C6SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAPB1SMENR2_FDCAN1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAPB1SMENR2_FDCAN1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAPB1SMENR2_UCPD1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1SMENR2_UCPD1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x800000) >> 23
}

// RCC.APB2SMENR: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
func (o *RCC_Type) SetAPB2SMENR_TIM1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB2SMENR_TIM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB2SMENR_SPI1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB2SMENR_SPI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB2SMENR_TIM8SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB2SMENR_TIM8SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB2SMENR_USART1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB2SMENR_USART1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB2SMENR_TIM15SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPB2SMENR_TIM15SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPB2SMENR_TIM16SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB2SMENR_TIM16SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB2SMENR_TIM17SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB2SMENR_TIM17SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB2SMENR_SAI1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB2SMENR_SAI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB2SMENR_SAI2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB2SMENR_SAI2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB2SMENR_USBSMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB2SMENR_USBSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB2SMENR_GFXTIMSMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetAPB2SMENR_GFXTIMSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetAPB2SMENR_LTDCSMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetAPB2SMENR_LTDCSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetAPB2SMENR_DSISMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetAPB2SMENR_DSISMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x8000000) >> 27
}

// RCC.APB3SMENR: RCC APB3 peripheral clock enable in Sleep and Stop modes register
func (o *RCC_Type) SetAPB3SMENR_SYSCFGSMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB3SMENR_SYSCFGSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB3SMENR_SPI3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB3SMENR_SPI3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB3SMENR_LPUART1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB3SMENR_LPUART1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB3SMENR_I2C3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAPB3SMENR_I2C3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAPB3SMENR_LPTIM1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB3SMENR_LPTIM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB3SMENR_LPTIM3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB3SMENR_LPTIM3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB3SMENR_LPTIM4SMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB3SMENR_LPTIM4SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB3SMENR_OPAMPSMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB3SMENR_OPAMPSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB3SMENR_COMPSMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPB3SMENR_COMPSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPB3SMENR_VREFSMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB3SMENR_VREFSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB3SMENR_RTCAPBSMEN(value uint32) {
	volatile.StoreUint32(&o.APB3SMENR.Reg, volatile.LoadUint32(&o.APB3SMENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB3SMENR_RTCAPBSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB3SMENR.Reg) & 0x200000) >> 21
}

// RCC.SRDAMR: RCC SmartRun domain peripheral autonomous mode register
func (o *RCC_Type) SetSRDAMR_SPI3AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetSRDAMR_SPI3AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetSRDAMR_LPUART1AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetSRDAMR_LPUART1AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetSRDAMR_I2C3AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetSRDAMR_I2C3AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetSRDAMR_LPTIM1AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetSRDAMR_LPTIM1AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetSRDAMR_LPTIM3AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetSRDAMR_LPTIM3AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetSRDAMR_LPTIM4AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetSRDAMR_LPTIM4AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetSRDAMR_OPAMPAMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetSRDAMR_OPAMPAMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetSRDAMR_COMPAMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetSRDAMR_COMPAMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetSRDAMR_VREFAMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetSRDAMR_VREFAMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetSRDAMR_RTCAPBAMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetSRDAMR_RTCAPBAMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetSRDAMR_ADC4AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetSRDAMR_ADC4AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetSRDAMR_LPGPIO1AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetSRDAMR_LPGPIO1AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetSRDAMR_DAC1AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetSRDAMR_DAC1AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetSRDAMR_LPDMA1AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetSRDAMR_LPDMA1AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetSRDAMR_ADF1AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetSRDAMR_ADF1AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetSRDAMR_SRAM4AMEN(value uint32) {
	volatile.StoreUint32(&o.SRDAMR.Reg, volatile.LoadUint32(&o.SRDAMR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetSRDAMR_SRAM4AMEN() uint32 {
	return (volatile.LoadUint32(&o.SRDAMR.Reg) & 0x80000000) >> 31
}

// RCC.CCIPR1: RCC peripherals independent clock configuration register 1
func (o *RCC_Type) SetCCIPR1_USART1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetCCIPR1_USART1SEL() uint32 {
	return volatile.LoadUint32(&o.CCIPR1.Reg) & 0x3
}
func (o *RCC_Type) SetCCIPR1_USART2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetCCIPR1_USART2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetCCIPR1_USART3SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x30)|value<<4)
}
func (o *RCC_Type) GetCCIPR1_USART3SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x30) >> 4
}
func (o *RCC_Type) SetCCIPR1_UART4SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc0)|value<<6)
}
func (o *RCC_Type) GetCCIPR1_UART4SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc0) >> 6
}
func (o *RCC_Type) SetCCIPR1_UART5SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x300)|value<<8)
}
func (o *RCC_Type) GetCCIPR1_UART5SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x300) >> 8
}
func (o *RCC_Type) SetCCIPR1_I2C1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc00)|value<<10)
}
func (o *RCC_Type) GetCCIPR1_I2C1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc00) >> 10
}
func (o *RCC_Type) SetCCIPR1_I2C2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x3000)|value<<12)
}
func (o *RCC_Type) GetCCIPR1_I2C2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x3000) >> 12
}
func (o *RCC_Type) SetCCIPR1_I2C4SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc000)|value<<14)
}
func (o *RCC_Type) GetCCIPR1_I2C4SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc000) >> 14
}
func (o *RCC_Type) SetCCIPR1_SPI2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x30000)|value<<16)
}
func (o *RCC_Type) GetCCIPR1_SPI2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x30000) >> 16
}
func (o *RCC_Type) SetCCIPR1_LPTIM2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc0000)|value<<18)
}
func (o *RCC_Type) GetCCIPR1_LPTIM2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc0000) >> 18
}
func (o *RCC_Type) SetCCIPR1_SPI1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x300000)|value<<20)
}
func (o *RCC_Type) GetCCIPR1_SPI1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x300000) >> 20
}
func (o *RCC_Type) SetCCIPR1_SYSTICKSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc00000)|value<<22)
}
func (o *RCC_Type) GetCCIPR1_SYSTICKSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc00000) >> 22
}
func (o *RCC_Type) SetCCIPR1_FDCAN1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x3000000)|value<<24)
}
func (o *RCC_Type) GetCCIPR1_FDCAN1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x3000000) >> 24
}
func (o *RCC_Type) SetCCIPR1_ICLKSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc000000)|value<<26)
}
func (o *RCC_Type) GetCCIPR1_ICLKSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc000000) >> 26
}
func (o *RCC_Type) SetCCIPR1_TIMICSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xe0000000)|value<<29)
}
func (o *RCC_Type) GetCCIPR1_TIMICSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xe0000000) >> 29
}

// RCC.CCIPR2: RCC peripherals independent clock configuration register 2
func (o *RCC_Type) SetCCIPR2_MDF1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x7)|value)
}
func (o *RCC_Type) GetCCIPR2_MDF1SEL() uint32 {
	return volatile.LoadUint32(&o.CCIPR2.Reg) & 0x7
}
func (o *RCC_Type) SetCCIPR2_SAI1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0xe0)|value<<5)
}
func (o *RCC_Type) GetCCIPR2_SAI1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0xe0) >> 5
}
func (o *RCC_Type) SetCCIPR2_SAI2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x700)|value<<8)
}
func (o *RCC_Type) GetCCIPR2_SAI2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x700) >> 8
}
func (o *RCC_Type) SetCCIPR2_SAESSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetCCIPR2_SAESSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetCCIPR2_RNGSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x3000)|value<<12)
}
func (o *RCC_Type) GetCCIPR2_RNGSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x3000) >> 12
}
func (o *RCC_Type) SetCCIPR2_SDMMCSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetCCIPR2_SDMMCSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetCCIPR2_DSISEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetCCIPR2_DSISEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetCCIPR2_USART6SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x30000)|value<<16)
}
func (o *RCC_Type) GetCCIPR2_USART6SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x30000) >> 16
}
func (o *RCC_Type) SetCCIPR2_LTDCSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetCCIPR2_LTDCSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetCCIPR2_OCTOSPISEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x300000)|value<<20)
}
func (o *RCC_Type) GetCCIPR2_OCTOSPISEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x300000) >> 20
}
func (o *RCC_Type) SetCCIPR2_HSPI1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0xc00000)|value<<22)
}
func (o *RCC_Type) GetCCIPR2_HSPI1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0xc00000) >> 22
}
func (o *RCC_Type) SetCCIPR2_I2C5SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x3000000)|value<<24)
}
func (o *RCC_Type) GetCCIPR2_I2C5SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x3000000) >> 24
}
func (o *RCC_Type) SetCCIPR2_I2C6SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0xc000000)|value<<26)
}
func (o *RCC_Type) GetCCIPR2_I2C6SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0xc000000) >> 26
}
func (o *RCC_Type) SetCCIPR2_OTGHSSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *RCC_Type) GetCCIPR2_OTGHSSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0xc0000000) >> 30
}

// RCC.CCIPR3: RCC peripherals independent clock configuration register 3
func (o *RCC_Type) SetCCIPR3_LPUART1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0x7)|value)
}
func (o *RCC_Type) GetCCIPR3_LPUART1SEL() uint32 {
	return volatile.LoadUint32(&o.CCIPR3.Reg) & 0x7
}
func (o *RCC_Type) SetCCIPR3_SPI3SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0x18)|value<<3)
}
func (o *RCC_Type) GetCCIPR3_SPI3SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR3.Reg) & 0x18) >> 3
}
func (o *RCC_Type) SetCCIPR3_I2C3SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0xc0)|value<<6)
}
func (o *RCC_Type) GetCCIPR3_I2C3SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR3.Reg) & 0xc0) >> 6
}
func (o *RCC_Type) SetCCIPR3_LPTIM34SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0x300)|value<<8)
}
func (o *RCC_Type) GetCCIPR3_LPTIM34SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR3.Reg) & 0x300) >> 8
}
func (o *RCC_Type) SetCCIPR3_LPTIM1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0xc00)|value<<10)
}
func (o *RCC_Type) GetCCIPR3_LPTIM1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR3.Reg) & 0xc00) >> 10
}
func (o *RCC_Type) SetCCIPR3_ADCDACSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0x7000)|value<<12)
}
func (o *RCC_Type) GetCCIPR3_ADCDACSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR3.Reg) & 0x7000) >> 12
}
func (o *RCC_Type) SetCCIPR3_DAC1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetCCIPR3_DAC1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR3.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetCCIPR3_ADF1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR3.Reg, volatile.LoadUint32(&o.CCIPR3.Reg)&^(0x70000)|value<<16)
}
func (o *RCC_Type) GetCCIPR3_ADF1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR3.Reg) & 0x70000) >> 16
}

// RCC.BDCR: RCC backup domain control register
func (o *RCC_Type) SetBDCR_LSEON(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetBDCR_LSEON() uint32 {
	return volatile.LoadUint32(&o.BDCR.Reg) & 0x1
}
func (o *RCC_Type) SetBDCR_LSERDY(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetBDCR_LSERDY() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetBDCR_LSEBYP(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetBDCR_LSEBYP() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetBDCR_LSEDRV(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x18)|value<<3)
}
func (o *RCC_Type) GetBDCR_LSEDRV() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x18) >> 3
}
func (o *RCC_Type) SetBDCR_LSECSSON(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetBDCR_LSECSSON() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetBDCR_LSECSSD(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetBDCR_LSECSSD() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetBDCR_LSESYSEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetBDCR_LSESYSEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetBDCR_RTCSEL(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x300)|value<<8)
}
func (o *RCC_Type) GetBDCR_RTCSEL() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x300) >> 8
}
func (o *RCC_Type) SetBDCR_LSESYSRDY(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetBDCR_LSESYSRDY() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetBDCR_LSEGFON(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetBDCR_LSEGFON() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetBDCR_RTCEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetBDCR_RTCEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetBDCR_BDRST(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetBDCR_BDRST() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetBDCR_LSCOEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetBDCR_LSCOEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetBDCR_LSCOSEL(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetBDCR_LSCOSEL() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetBDCR_LSION(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetBDCR_LSION() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetBDCR_LSIRDY(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetBDCR_LSIRDY() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetBDCR_LSIPREDIV(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetBDCR_LSIPREDIV() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x10000000) >> 28
}

// RCC.CSR: RCC control/status register
func (o *RCC_Type) SetCSR_MSIKSRANGE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0xf00)|value<<8)
}
func (o *RCC_Type) GetCSR_MSIKSRANGE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0xf00) >> 8
}
func (o *RCC_Type) SetCSR_MSISSRANGE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0xf000)|value<<12)
}
func (o *RCC_Type) GetCSR_MSISSRANGE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0xf000) >> 12
}
func (o *RCC_Type) SetCSR_RMVF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetCSR_RMVF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetCSR_OBLRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetCSR_OBLRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetCSR_PINRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetCSR_PINRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetCSR_BORRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetCSR_BORRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetCSR_SFTRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetCSR_SFTRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetCSR_IWDGRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetCSR_IWDGRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetCSR_WWDGRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetCSR_WWDGRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetCSR_LPWRRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetCSR_LPWRRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80000000) >> 31
}

// RCC.SECCFGR: RCC secure configuration register
func (o *RCC_Type) SetSECCFGR_HSISEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetSECCFGR_HSISEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}
func (o *RCC_Type) SetSECCFGR_HSESEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetSECCFGR_HSESEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetSECCFGR_MSISEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetSECCFGR_MSISEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetSECCFGR_LSISEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetSECCFGR_LSISEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetSECCFGR_LSESEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetSECCFGR_LSESEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetSECCFGR_SYSCLKSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetSECCFGR_SYSCLKSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetSECCFGR_PRESCSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetSECCFGR_PRESCSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetSECCFGR_PLL1SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetSECCFGR_PLL1SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetSECCFGR_PLL2SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetSECCFGR_PLL2SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetSECCFGR_PLL3SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetSECCFGR_PLL3SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetSECCFGR_ICLKSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetSECCFGR_ICLKSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetSECCFGR_HSI48SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetSECCFGR_HSI48SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetSECCFGR_RMVFSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetSECCFGR_RMVFSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1000) >> 12
}

// RCC.PRIVCFGR: RCC privilege configuration register
func (o *RCC_Type) SetPRIVCFGR_SPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetPRIVCFGR_SPRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x1
}
func (o *RCC_Type) SetPRIVCFGR_NSPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetPRIVCFGR_NSPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x2) >> 1
}

// Random number generator
type RNG_Type struct {
	CR   volatile.Register32 // 0x0
	SR   volatile.Register32 // 0x4
	DR   volatile.Register32 // 0x8
	_    [4]byte
	HTCR volatile.Register32 // 0x10
}

// RNG.CR: control register
func (o *RNG_Type) SetCR_CONFIGLOCK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *RNG_Type) GetCR_CONFIGLOCK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}
func (o *RNG_Type) SetCR_CONDRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *RNG_Type) GetCR_CONDRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *RNG_Type) SetCR_RNG_CONFIG1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3f00000)|value<<20)
}
func (o *RNG_Type) GetCR_RNG_CONFIG1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3f00000) >> 20
}
func (o *RNG_Type) SetCR_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf0000)|value<<16)
}
func (o *RNG_Type) GetCR_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf0000) >> 16
}
func (o *RNG_Type) SetCR_RNG_CONFIG2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xe000)|value<<13)
}
func (o *RNG_Type) GetCR_RNG_CONFIG2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xe000) >> 13
}
func (o *RNG_Type) SetCR_NISTC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *RNG_Type) GetCR_NISTC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *RNG_Type) SetCR_RNG_CONFIG3(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf00)|value<<8)
}
func (o *RNG_Type) GetCR_RNG_CONFIG3() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf00) >> 8
}
func (o *RNG_Type) SetCR_ARDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *RNG_Type) GetCR_ARDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *RNG_Type) SetCR_CED(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RNG_Type) GetCR_CED() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RNG_Type) SetCR_IE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RNG_Type) GetCR_IE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RNG_Type) SetCR_RNGEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *RNG_Type) GetCR_RNGEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}

// RNG.SR: status register
func (o *RNG_Type) SetSR_CEIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *RNG_Type) GetSR_CEIS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *RNG_Type) SetSR_SEIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *RNG_Type) GetSR_SEIS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *RNG_Type) SetSR_SECS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RNG_Type) GetSR_SECS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RNG_Type) SetSR_CECS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *RNG_Type) GetSR_CECS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *RNG_Type) SetSR_DRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *RNG_Type) GetSR_DRDY() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// RNG.DR: data register
func (o *RNG_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *RNG_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// RNG.HTCR: health test control register
func (o *RNG_Type) SetHTCR(value uint32) {
	volatile.StoreUint32(&o.HTCR.Reg, value)
}
func (o *RNG_Type) GetHTCR() uint32 {
	return volatile.LoadUint32(&o.HTCR.Reg)
}

// Real-time clock
type RTC_Type struct {
	TR       volatile.Register32 // 0x0
	DR       volatile.Register32 // 0x4
	SSR      volatile.Register32 // 0x8
	ICSR     volatile.Register32 // 0xC
	PRER     volatile.Register32 // 0x10
	WUTR     volatile.Register32 // 0x14
	CR       volatile.Register32 // 0x18
	PRIVCR   volatile.Register32 // 0x1C
	SECCFGR  volatile.Register32 // 0x20
	WPR      volatile.Register32 // 0x24
	CALR     volatile.Register32 // 0x28
	SHIFTR   volatile.Register32 // 0x2C
	TSTR     volatile.Register32 // 0x30
	TSDR     volatile.Register32 // 0x34
	TSSSR    volatile.Register32 // 0x38
	_        [4]byte
	ALRMAR   volatile.Register32 // 0x40
	ALRMASSR volatile.Register32 // 0x44
	ALRMBR   volatile.Register32 // 0x48
	ALRMBSSR volatile.Register32 // 0x4C
	SR       volatile.Register32 // 0x50
	MISR     volatile.Register32 // 0x54
	SMISR    volatile.Register32 // 0x58
	SCR      volatile.Register32 // 0x5C
	_        [16]byte
	ALRABINR volatile.Register32 // 0x70
	ALRBBINR volatile.Register32 // 0x74
}

// RTC.TR: time register
func (o *RTC_Type) SetTR_PM(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetTR_PM() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetTR_HT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetTR_HT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetTR_HU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetTR_HU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetTR_MNT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetTR_MNT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetTR_MNU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetTR_MNU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetTR_ST(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetTR_ST() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetTR_SU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetTR_SU() uint32 {
	return volatile.LoadUint32(&o.TR.Reg) & 0xf
}

// RTC.DR: date register
func (o *RTC_Type) SetDR_YT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00000)|value<<20)
}
func (o *RTC_Type) GetDR_YT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00000) >> 20
}
func (o *RTC_Type) SetDR_YU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetDR_YU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetDR_WDU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xe000)|value<<13)
}
func (o *RTC_Type) GetDR_WDU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xe000) >> 13
}
func (o *RTC_Type) SetDR_MT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_Type) GetDR_MT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x1000) >> 12
}
func (o *RTC_Type) SetDR_MU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetDR_MU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetDR_DT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x30)|value<<4)
}
func (o *RTC_Type) GetDR_DT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x30) >> 4
}
func (o *RTC_Type) SetDR_DU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetDR_DU() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xf
}

// RTC.SSR: RTC sub second register
func (o *RTC_Type) SetSSR(value uint32) {
	volatile.StoreUint32(&o.SSR.Reg, value)
}
func (o *RTC_Type) GetSSR() uint32 {
	return volatile.LoadUint32(&o.SSR.Reg)
}

// RTC.ICSR: RTC initialization control and status register
func (o *RTC_Type) SetICSR_WUTWF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetICSR_WUTWF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetICSR_SHPF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetICSR_SHPF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetICSR_INITS(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetICSR_INITS() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetICSR_RSF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetICSR_RSF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetICSR_INITF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetICSR_INITF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetICSR_INIT(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetICSR_INIT() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetICSR_BIN(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x300)|value<<8)
}
func (o *RTC_Type) GetICSR_BIN() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x300) >> 8
}
func (o *RTC_Type) SetICSR_BCDU(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x1c00)|value<<10)
}
func (o *RTC_Type) GetICSR_BCDU() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x1c00) >> 10
}
func (o *RTC_Type) SetICSR_RECALPF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetICSR_RECALPF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x10000) >> 16
}

// RTC.PRER: prescaler register
func (o *RTC_Type) SetPRER_PREDIV_A(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7f0000)|value<<16)
}
func (o *RTC_Type) GetPRER_PREDIV_A() uint32 {
	return (volatile.LoadUint32(&o.PRER.Reg) & 0x7f0000) >> 16
}
func (o *RTC_Type) SetPRER_PREDIV_S(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetPRER_PREDIV_S() uint32 {
	return volatile.LoadUint32(&o.PRER.Reg) & 0x7fff
}

// RTC.WUTR: wakeup timer register
func (o *RTC_Type) SetWUTR_WUT(value uint32) {
	volatile.StoreUint32(&o.WUTR.Reg, volatile.LoadUint32(&o.WUTR.Reg)&^(0xffff)|value)
}
func (o *RTC_Type) GetWUTR_WUT() uint32 {
	return volatile.LoadUint32(&o.WUTR.Reg) & 0xffff
}
func (o *RTC_Type) SetWUTR_WUTOCLR(value uint32) {
	volatile.StoreUint32(&o.WUTR.Reg, volatile.LoadUint32(&o.WUTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *RTC_Type) GetWUTR_WUTOCLR() uint32 {
	return (volatile.LoadUint32(&o.WUTR.Reg) & 0xffff0000) >> 16
}

// RTC.CR: RTC control register
func (o *RTC_Type) SetCR_WUCKSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7)|value)
}
func (o *RTC_Type) GetCR_WUCKSEL() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x7
}
func (o *RTC_Type) SetCR_TSEDGE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetCR_TSEDGE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetCR_REFCKON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetCR_REFCKON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetCR_BYPSHAD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetCR_BYPSHAD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetCR_FMT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetCR_FMT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetCR_SSRUIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetCR_SSRUIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetCR_ALRAE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *RTC_Type) GetCR_ALRAE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *RTC_Type) SetCR_ALRBE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetCR_ALRBE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetCR_WUTE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetCR_WUTE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetCR_TSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *RTC_Type) GetCR_TSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *RTC_Type) SetCR_ALRAIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetCR_ALRAIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetCR_ALRBIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCR_ALRBIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCR_WUTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCR_WUTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCR_TSIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetCR_TSIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetCR_ADD1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetCR_ADD1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RTC_Type) SetCR_SUB1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RTC_Type) GetCR_SUB1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *RTC_Type) SetCR_BKP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *RTC_Type) GetCR_BKP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *RTC_Type) SetCR_COSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *RTC_Type) GetCR_COSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *RTC_Type) SetCR_POL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *RTC_Type) GetCR_POL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *RTC_Type) SetCR_OSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x600000)|value<<21)
}
func (o *RTC_Type) GetCR_OSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x600000) >> 21
}
func (o *RTC_Type) SetCR_COE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetCR_COE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetCR_ITSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *RTC_Type) GetCR_ITSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}
func (o *RTC_Type) SetCR_TAMPTS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000000)|value<<25)
}
func (o *RTC_Type) GetCR_TAMPTS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000000) >> 25
}
func (o *RTC_Type) SetCR_TAMPOE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000000)|value<<26)
}
func (o *RTC_Type) GetCR_TAMPOE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000000) >> 26
}
func (o *RTC_Type) SetCR_ALRAFCLR(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000000)|value<<27)
}
func (o *RTC_Type) GetCR_ALRAFCLR() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000000) >> 27
}
func (o *RTC_Type) SetCR_ALRBFCLR(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *RTC_Type) GetCR_ALRBFCLR() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *RTC_Type) SetCR_TAMPALRM_PU(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *RTC_Type) GetCR_TAMPALRM_PU() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *RTC_Type) SetCR_TAMPALRM_TYPE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetCR_TAMPALRM_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetCR_OUT2EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetCR_OUT2EN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// RTC.PRIVCR: RTC privilege mode control register
func (o *RTC_Type) SetPRIVCR_PRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetPRIVCR_PRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetPRIVCR_INITPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetPRIVCR_INITPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetPRIVCR_CALPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetPRIVCR_CALPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetPRIVCR_TSPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetPRIVCR_TSPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetPRIVCR_WUTPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetPRIVCR_WUTPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetPRIVCR_ALRBPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetPRIVCR_ALRBPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetPRIVCR_ALRAPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetPRIVCR_ALRAPRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCR.Reg) & 0x1
}

// RTC.SECCFGR: RTC secure mode control register
func (o *RTC_Type) SetSECCFGR_SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetSECCFGR_SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetSECCFGR_INITSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetSECCFGR_INITSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetSECCFGR_CALSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetSECCFGR_CALSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetSECCFGR_TSSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSECCFGR_TSSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSECCFGR_WUTSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSECCFGR_WUTSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSECCFGR_ALRBSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSECCFGR_ALRBSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSECCFGR_ALRASEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetSECCFGR_ALRASEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}

// RTC.WPR: write protection register
func (o *RTC_Type) SetWPR_KEY(value uint32) {
	volatile.StoreUint32(&o.WPR.Reg, volatile.LoadUint32(&o.WPR.Reg)&^(0xff)|value)
}
func (o *RTC_Type) GetWPR_KEY() uint32 {
	return volatile.LoadUint32(&o.WPR.Reg) & 0xff
}

// RTC.CALR: calibration register
func (o *RTC_Type) SetCALR_CALP(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetCALR_CALP() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetCALR_CALW8(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCALR_CALW8() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCALR_CALW16(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetCALR_CALW16() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetCALR_LPCAL(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_Type) GetCALR_LPCAL() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x1000) >> 12
}
func (o *RTC_Type) SetCALR_CALM(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x1ff)|value)
}
func (o *RTC_Type) GetCALR_CALM() uint32 {
	return volatile.LoadUint32(&o.CALR.Reg) & 0x1ff
}

// RTC.SHIFTR: shift control register
func (o *RTC_Type) SetSHIFTR_ADD1S(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetSHIFTR_ADD1S() uint32 {
	return (volatile.LoadUint32(&o.SHIFTR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetSHIFTR_SUBFS(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetSHIFTR_SUBFS() uint32 {
	return volatile.LoadUint32(&o.SHIFTR.Reg) & 0x7fff
}

// RTC.ALRMAR: Alarm %s register
func (o *RTC_Type) SetALRMAR_MSK1(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetALRMAR_MSK1() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetALRMAR_MSK4(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMAR_MSK4() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetALRMAR_WDSEL(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetALRMAR_WDSEL() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetALRMAR_DT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x30000000)|value<<28)
}
func (o *RTC_Type) GetALRMAR_DT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x30000000) >> 28
}
func (o *RTC_Type) SetALRMAR_DU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMAR_DU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMAR_MSK3(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetALRMAR_MSK3() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetALRMAR_PM(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetALRMAR_PM() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetALRMAR_HT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetALRMAR_HT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetALRMAR_HU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetALRMAR_HU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetALRMAR_MSK2(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetALRMAR_MSK2() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetALRMAR_MNT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetALRMAR_MNT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetALRMAR_MNU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetALRMAR_MNU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetALRMAR_ST(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetALRMAR_ST() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetALRMAR_SU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetALRMAR_SU() uint32 {
	return volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf
}

// RTC.ALRMASSR: Alarm %s sub-second register
func (o *RTC_Type) SetALRMASSR_SSCLR(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMASSR_SSCLR() uint32 {
	return (volatile.LoadUint32(&o.ALRMASSR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetALRMASSR_MASKSS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0x3f000000)|value<<24)
}
func (o *RTC_Type) GetALRMASSR_MASKSS() uint32 {
	return (volatile.LoadUint32(&o.ALRMASSR.Reg) & 0x3f000000) >> 24
}
func (o *RTC_Type) SetALRMASSR_SS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetALRMASSR_SS() uint32 {
	return volatile.LoadUint32(&o.ALRMASSR.Reg) & 0x7fff
}

// RTC.ALRMBR: Alarm %s register
func (o *RTC_Type) SetALRMBR_MSK1(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetALRMBR_MSK1() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetALRMBR_MSK4(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMBR_MSK4() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetALRMBR_WDSEL(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetALRMBR_WDSEL() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetALRMBR_DT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x30000000)|value<<28)
}
func (o *RTC_Type) GetALRMBR_DT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x30000000) >> 28
}
func (o *RTC_Type) SetALRMBR_DU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMBR_DU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMBR_MSK3(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetALRMBR_MSK3() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetALRMBR_PM(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetALRMBR_PM() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetALRMBR_HT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetALRMBR_HT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetALRMBR_HU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetALRMBR_HU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetALRMBR_MSK2(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetALRMBR_MSK2() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetALRMBR_MNT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetALRMBR_MNT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetALRMBR_MNU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetALRMBR_MNU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetALRMBR_ST(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetALRMBR_ST() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetALRMBR_SU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetALRMBR_SU() uint32 {
	return volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf
}

// RTC.ALRMBSSR: Alarm %s sub-second register
func (o *RTC_Type) SetALRMBSSR_SSCLR(value uint32) {
	volatile.StoreUint32(&o.ALRMBSSR.Reg, volatile.LoadUint32(&o.ALRMBSSR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMBSSR_SSCLR() uint32 {
	return (volatile.LoadUint32(&o.ALRMBSSR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetALRMBSSR_MASKSS(value uint32) {
	volatile.StoreUint32(&o.ALRMBSSR.Reg, volatile.LoadUint32(&o.ALRMBSSR.Reg)&^(0x3f000000)|value<<24)
}
func (o *RTC_Type) GetALRMBSSR_MASKSS() uint32 {
	return (volatile.LoadUint32(&o.ALRMBSSR.Reg) & 0x3f000000) >> 24
}
func (o *RTC_Type) SetALRMBSSR_SS(value uint32) {
	volatile.StoreUint32(&o.ALRMBSSR.Reg, volatile.LoadUint32(&o.ALRMBSSR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetALRMBSSR_SS() uint32 {
	return volatile.LoadUint32(&o.ALRMBSSR.Reg) & 0x7fff
}

// RTC.SR: RTC status register
func (o *RTC_Type) SetSR_ALRAF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSR_ALRAF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSR_ALRBF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSR_ALRBF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSR_WUTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSR_WUTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSR_TSF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSR_TSF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSR_TSOVF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSR_TSOVF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSR_ITSF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSR_ITSF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetSR_SSRUF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetSR_SSRUF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}

// RTC.MISR: RTC non-secure masked interrupt status register
func (o *RTC_Type) SetMISR_ALRAMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetMISR_ALRAMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetMISR_ALRBMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetMISR_ALRBMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetMISR_WUTMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetMISR_WUTMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetMISR_TSMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetMISR_TSMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetMISR_TSOVMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetMISR_TSOVMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetMISR_ITSMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetMISR_ITSMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetMISR_SSRUMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetMISR_SSRUMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x40) >> 6
}

// RTC.SMISR: RTC secure masked interrupt status register
func (o *RTC_Type) SetSMISR_ALRAMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetSMISR_ALRAMF() uint32 {
	return volatile.LoadUint32(&o.SMISR.Reg) & 0x1
}
func (o *RTC_Type) SetSMISR_ALRBMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSMISR_ALRBMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSMISR_WUTMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSMISR_WUTMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSMISR_TSMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSMISR_TSMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSMISR_TSOVMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSMISR_TSOVMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSMISR_ITSMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSMISR_ITSMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetSMISR_SSRUMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetSMISR_SSRUMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x40) >> 6
}

// RTC.SCR: RTC status clear register
func (o *RTC_Type) SetSCR_CALRAF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetSCR_CALRAF() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}
func (o *RTC_Type) SetSCR_CALRBF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSCR_CALRBF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSCR_CWUTF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSCR_CWUTF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSCR_CTSF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSCR_CTSF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSCR_CTSOVF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSCR_CTSOVF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSCR_CITSF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSCR_CITSF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetSCR_CSSRUF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetSCR_CSSRUF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x40) >> 6
}

// RTC.ALRABINR: Alarm %s binary mode register
func (o *RTC_Type) SetALRABINR(value uint32) {
	volatile.StoreUint32(&o.ALRABINR.Reg, value)
}
func (o *RTC_Type) GetALRABINR() uint32 {
	return volatile.LoadUint32(&o.ALRABINR.Reg)
}

// RTC.ALRBBINR: Alarm %s binary mode register
func (o *RTC_Type) SetALRBBINR(value uint32) {
	volatile.StoreUint32(&o.ALRBBINR.Reg, value)
}
func (o *RTC_Type) GetALRBBINR() uint32 {
	return volatile.LoadUint32(&o.ALRBBINR.Reg)
}

// Secure AES coprocessor
type SAES_Type struct {
	CR      volatile.Register32 // 0x0
	SR      volatile.Register32 // 0x4
	DINR    volatile.Register32 // 0x8
	DOUTR   volatile.Register32 // 0xC
	KEYR0   volatile.Register32 // 0x10
	KEYR1   volatile.Register32 // 0x14
	KEYR2   volatile.Register32 // 0x18
	KEYR3   volatile.Register32 // 0x1C
	IVR0    volatile.Register32 // 0x20
	IVR1    volatile.Register32 // 0x24
	IVR2    volatile.Register32 // 0x28
	IVR3    volatile.Register32 // 0x2C
	KEYR4   volatile.Register32 // 0x30
	KEYR5   volatile.Register32 // 0x34
	KEYR6   volatile.Register32 // 0x38
	KEYR7   volatile.Register32 // 0x3C
	_       [192]byte
	DPACFGR volatile.Register32 // 0x100
	_       [508]byte
	IER     volatile.Register32 // 0x300
	ISR     volatile.Register32 // 0x304
	ICR     volatile.Register32 // 0x308
}

// SAES.CR: control register
func (o *SAES_Type) SetCR_IPRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *SAES_Type) GetCR_IPRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}
func (o *SAES_Type) SetCR_KEYSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x70000000)|value<<28)
}
func (o *SAES_Type) GetCR_KEYSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x70000000) >> 28
}
func (o *SAES_Type) SetCR_KSHAREID(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc000000)|value<<26)
}
func (o *SAES_Type) GetCR_KSHAREID() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc000000) >> 26
}
func (o *SAES_Type) SetCR_KMOD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3000000)|value<<24)
}
func (o *SAES_Type) GetCR_KMOD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3000000) >> 24
}
func (o *SAES_Type) SetCR_KEYPROT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *SAES_Type) GetCR_KEYPROT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *SAES_Type) SetCR_KEYSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *SAES_Type) GetCR_KEYSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *SAES_Type) SetCR_DMAOUTEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *SAES_Type) GetCR_DMAOUTEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *SAES_Type) SetCR_DMAINEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *SAES_Type) GetCR_DMAINEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *SAES_Type) SetCR_CHMOD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x60)|value<<5)
}
func (o *SAES_Type) GetCR_CHMOD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x60) >> 5
}
func (o *SAES_Type) SetCR_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x18)|value<<3)
}
func (o *SAES_Type) GetCR_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x18) >> 3
}
func (o *SAES_Type) SetCR_DATATYPE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x6)|value<<1)
}
func (o *SAES_Type) GetCR_DATATYPE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x6) >> 1
}
func (o *SAES_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *SAES_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// SAES.SR: status register
func (o *SAES_Type) SetSR_KEYVALID(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *SAES_Type) GetSR_KEYVALID() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *SAES_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *SAES_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *SAES_Type) SetSR_WRERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *SAES_Type) GetSR_WRERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *SAES_Type) SetSR_RDERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SAES_Type) GetSR_RDERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *SAES_Type) SetSR_CCF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *SAES_Type) GetSR_CCF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// SAES.DINR: data input register
func (o *SAES_Type) SetDINR(value uint32) {
	volatile.StoreUint32(&o.DINR.Reg, value)
}
func (o *SAES_Type) GetDINR() uint32 {
	return volatile.LoadUint32(&o.DINR.Reg)
}

// SAES.DOUTR: data output register
func (o *SAES_Type) SetDOUTR(value uint32) {
	volatile.StoreUint32(&o.DOUTR.Reg, value)
}
func (o *SAES_Type) GetDOUTR() uint32 {
	return volatile.LoadUint32(&o.DOUTR.Reg)
}

// SAES.KEYR0: key register 0
func (o *SAES_Type) SetKEYR0(value uint32) {
	volatile.StoreUint32(&o.KEYR0.Reg, value)
}
func (o *SAES_Type) GetKEYR0() uint32 {
	return volatile.LoadUint32(&o.KEYR0.Reg)
}

// SAES.KEYR1: key register 1
func (o *SAES_Type) SetKEYR1(value uint32) {
	volatile.StoreUint32(&o.KEYR1.Reg, value)
}
func (o *SAES_Type) GetKEYR1() uint32 {
	return volatile.LoadUint32(&o.KEYR1.Reg)
}

// SAES.KEYR2: key register 2
func (o *SAES_Type) SetKEYR2(value uint32) {
	volatile.StoreUint32(&o.KEYR2.Reg, value)
}
func (o *SAES_Type) GetKEYR2() uint32 {
	return volatile.LoadUint32(&o.KEYR2.Reg)
}

// SAES.KEYR3: key register 3
func (o *SAES_Type) SetKEYR3(value uint32) {
	volatile.StoreUint32(&o.KEYR3.Reg, value)
}
func (o *SAES_Type) GetKEYR3() uint32 {
	return volatile.LoadUint32(&o.KEYR3.Reg)
}

// SAES.IVR0: initialization vector register 0
func (o *SAES_Type) SetIVR0(value uint32) {
	volatile.StoreUint32(&o.IVR0.Reg, value)
}
func (o *SAES_Type) GetIVR0() uint32 {
	return volatile.LoadUint32(&o.IVR0.Reg)
}

// SAES.IVR1: initialization vector register 1
func (o *SAES_Type) SetIVR1(value uint32) {
	volatile.StoreUint32(&o.IVR1.Reg, value)
}
func (o *SAES_Type) GetIVR1() uint32 {
	return volatile.LoadUint32(&o.IVR1.Reg)
}

// SAES.IVR2: initialization vector register 2
func (o *SAES_Type) SetIVR2(value uint32) {
	volatile.StoreUint32(&o.IVR2.Reg, value)
}
func (o *SAES_Type) GetIVR2() uint32 {
	return volatile.LoadUint32(&o.IVR2.Reg)
}

// SAES.IVR3: initialization vector register 3
func (o *SAES_Type) SetIVR3(value uint32) {
	volatile.StoreUint32(&o.IVR3.Reg, value)
}
func (o *SAES_Type) GetIVR3() uint32 {
	return volatile.LoadUint32(&o.IVR3.Reg)
}

// SAES.KEYR4: key register 4
func (o *SAES_Type) SetKEYR4(value uint32) {
	volatile.StoreUint32(&o.KEYR4.Reg, value)
}
func (o *SAES_Type) GetKEYR4() uint32 {
	return volatile.LoadUint32(&o.KEYR4.Reg)
}

// SAES.KEYR5: key register 5
func (o *SAES_Type) SetKEYR5(value uint32) {
	volatile.StoreUint32(&o.KEYR5.Reg, value)
}
func (o *SAES_Type) GetKEYR5() uint32 {
	return volatile.LoadUint32(&o.KEYR5.Reg)
}

// SAES.KEYR6: key register 6
func (o *SAES_Type) SetKEYR6(value uint32) {
	volatile.StoreUint32(&o.KEYR6.Reg, value)
}
func (o *SAES_Type) GetKEYR6() uint32 {
	return volatile.LoadUint32(&o.KEYR6.Reg)
}

// SAES.KEYR7: key register 7
func (o *SAES_Type) SetKEYR7(value uint32) {
	volatile.StoreUint32(&o.KEYR7.Reg, value)
}
func (o *SAES_Type) GetKEYR7() uint32 {
	return volatile.LoadUint32(&o.KEYR7.Reg)
}

// SAES.DPACFGR: configuration register
func (o *SAES_Type) SetDPACFGR_CONFIGLOCK(value uint32) {
	volatile.StoreUint32(&o.DPACFGR.Reg, volatile.LoadUint32(&o.DPACFGR.Reg)&^(0x80000000)|value<<31)
}
func (o *SAES_Type) GetDPACFGR_CONFIGLOCK() uint32 {
	return (volatile.LoadUint32(&o.DPACFGR.Reg) & 0x80000000) >> 31
}
func (o *SAES_Type) SetDPACFGR_TRIMCFG(value uint32) {
	volatile.StoreUint32(&o.DPACFGR.Reg, volatile.LoadUint32(&o.DPACFGR.Reg)&^(0x18)|value<<3)
}
func (o *SAES_Type) GetDPACFGR_TRIMCFG() uint32 {
	return (volatile.LoadUint32(&o.DPACFGR.Reg) & 0x18) >> 3
}
func (o *SAES_Type) SetDPACFGR_RESEED(value uint32) {
	volatile.StoreUint32(&o.DPACFGR.Reg, volatile.LoadUint32(&o.DPACFGR.Reg)&^(0x4)|value<<2)
}
func (o *SAES_Type) GetDPACFGR_RESEED() uint32 {
	return (volatile.LoadUint32(&o.DPACFGR.Reg) & 0x4) >> 2
}
func (o *SAES_Type) SetDPACFGR_REDCFG(value uint32) {
	volatile.StoreUint32(&o.DPACFGR.Reg, volatile.LoadUint32(&o.DPACFGR.Reg)&^(0x2)|value<<1)
}
func (o *SAES_Type) GetDPACFGR_REDCFG() uint32 {
	return (volatile.LoadUint32(&o.DPACFGR.Reg) & 0x2) >> 1
}

// SAES.IER: interrupt enable register
func (o *SAES_Type) SetIER_RNGEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *SAES_Type) GetIER_RNGEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *SAES_Type) SetIER_KEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *SAES_Type) GetIER_KEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *SAES_Type) SetIER_RWEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *SAES_Type) GetIER_RWEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *SAES_Type) SetIER_CCFIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *SAES_Type) GetIER_CCFIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}

// SAES.ISR: interrupt status register
func (o *SAES_Type) SetISR_RNGEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *SAES_Type) GetISR_RNGEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *SAES_Type) SetISR_KEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *SAES_Type) GetISR_KEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *SAES_Type) SetISR_RWEIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *SAES_Type) GetISR_RWEIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *SAES_Type) SetISR_CCF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *SAES_Type) GetISR_CCF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// SAES.ICR: interrupt clear register
func (o *SAES_Type) SetICR_RNGEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *SAES_Type) GetICR_RNGEIF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *SAES_Type) SetICR_KEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *SAES_Type) GetICR_KEIF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *SAES_Type) SetICR_RWEIF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *SAES_Type) GetICR_RWEIF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *SAES_Type) SetICR_CCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *SAES_Type) GetICR_CCF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}

// Serial audio interface
type SAI_Type struct {
	GCR    volatile.Register32 // 0x0
	ACR1   volatile.Register32 // 0x4
	ACR2   volatile.Register32 // 0x8
	AFRCR  volatile.Register32 // 0xC
	ASLOTR volatile.Register32 // 0x10
	AIM    volatile.Register32 // 0x14
	ASR    volatile.Register32 // 0x18
	ACLRFR volatile.Register32 // 0x1C
	ADR    volatile.Register32 // 0x20
	BCR1   volatile.Register32 // 0x24
	BCR2   volatile.Register32 // 0x28
	BFRCR  volatile.Register32 // 0x2C
	BSLOTR volatile.Register32 // 0x30
	BIM    volatile.Register32 // 0x34
	BSR    volatile.Register32 // 0x38
	BCLRFR volatile.Register32 // 0x3C
	BDR    volatile.Register32 // 0x40
	PDMCR  volatile.Register32 // 0x44
	PDMDLY volatile.Register32 // 0x48
}

// SAI.GCR: Global configuration register
func (o *SAI_Type) SetGCR_SYNCIN(value uint32) {
	volatile.StoreUint32(&o.GCR.Reg, volatile.LoadUint32(&o.GCR.Reg)&^(0x3)|value)
}
func (o *SAI_Type) GetGCR_SYNCIN() uint32 {
	return volatile.LoadUint32(&o.GCR.Reg) & 0x3
}
func (o *SAI_Type) SetGCR_SYNCOUT(value uint32) {
	volatile.StoreUint32(&o.GCR.Reg, volatile.LoadUint32(&o.GCR.Reg)&^(0x30)|value<<4)
}
func (o *SAI_Type) GetGCR_SYNCOUT() uint32 {
	return (volatile.LoadUint32(&o.GCR.Reg) & 0x30) >> 4
}

// SAI.ACR1: A Configuration register 1
func (o *SAI_Type) SetACR1_MCKEN(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x8000000)|value<<27)
}
func (o *SAI_Type) GetACR1_MCKEN() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x8000000) >> 27
}
func (o *SAI_Type) SetACR1_OSR(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x4000000)|value<<26)
}
func (o *SAI_Type) GetACR1_OSR() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x4000000) >> 26
}
func (o *SAI_Type) SetACR1_MCKDIV(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x3f00000)|value<<20)
}
func (o *SAI_Type) GetACR1_MCKDIV() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x3f00000) >> 20
}
func (o *SAI_Type) SetACR1_NODIV(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x80000)|value<<19)
}
func (o *SAI_Type) GetACR1_NODIV() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x80000) >> 19
}
func (o *SAI_Type) SetACR1_DMAEN(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x20000)|value<<17)
}
func (o *SAI_Type) GetACR1_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x20000) >> 17
}
func (o *SAI_Type) SetACR1_SAIAEN(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x10000)|value<<16)
}
func (o *SAI_Type) GetACR1_SAIAEN() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x10000) >> 16
}
func (o *SAI_Type) SetACR1_OUTDRIV(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x2000)|value<<13)
}
func (o *SAI_Type) GetACR1_OUTDRIV() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x2000) >> 13
}
func (o *SAI_Type) SetACR1_MONO(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x1000)|value<<12)
}
func (o *SAI_Type) GetACR1_MONO() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x1000) >> 12
}
func (o *SAI_Type) SetACR1_SYNCEN(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0xc00)|value<<10)
}
func (o *SAI_Type) GetACR1_SYNCEN() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0xc00) >> 10
}
func (o *SAI_Type) SetACR1_CKSTR(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x200)|value<<9)
}
func (o *SAI_Type) GetACR1_CKSTR() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x200) >> 9
}
func (o *SAI_Type) SetACR1_LSBFIRST(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x100)|value<<8)
}
func (o *SAI_Type) GetACR1_LSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0x100) >> 8
}
func (o *SAI_Type) SetACR1_DS(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0xe0)|value<<5)
}
func (o *SAI_Type) GetACR1_DS() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0xe0) >> 5
}
func (o *SAI_Type) SetACR1_PRTCFG(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0xc)|value<<2)
}
func (o *SAI_Type) GetACR1_PRTCFG() uint32 {
	return (volatile.LoadUint32(&o.ACR1.Reg) & 0xc) >> 2
}
func (o *SAI_Type) SetACR1_MODE(value uint32) {
	volatile.StoreUint32(&o.ACR1.Reg, volatile.LoadUint32(&o.ACR1.Reg)&^(0x3)|value)
}
func (o *SAI_Type) GetACR1_MODE() uint32 {
	return volatile.LoadUint32(&o.ACR1.Reg) & 0x3
}

// SAI.ACR2: A Configuration register 2
func (o *SAI_Type) SetACR2_COMP(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0xc000)|value<<14)
}
func (o *SAI_Type) GetACR2_COMP() uint32 {
	return (volatile.LoadUint32(&o.ACR2.Reg) & 0xc000) >> 14
}
func (o *SAI_Type) SetACR2_CPL(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0x2000)|value<<13)
}
func (o *SAI_Type) GetACR2_CPL() uint32 {
	return (volatile.LoadUint32(&o.ACR2.Reg) & 0x2000) >> 13
}
func (o *SAI_Type) SetACR2_MUTECN(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0x1f80)|value<<7)
}
func (o *SAI_Type) GetACR2_MUTECN() uint32 {
	return (volatile.LoadUint32(&o.ACR2.Reg) & 0x1f80) >> 7
}
func (o *SAI_Type) SetACR2_MUTEVAL(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetACR2_MUTEVAL() uint32 {
	return (volatile.LoadUint32(&o.ACR2.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetACR2_MUTE(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetACR2_MUTE() uint32 {
	return (volatile.LoadUint32(&o.ACR2.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetACR2_TRIS(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetACR2_TRIS() uint32 {
	return (volatile.LoadUint32(&o.ACR2.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetACR2_FFLUSH(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0x8)|value<<3)
}
func (o *SAI_Type) GetACR2_FFLUSH() uint32 {
	return (volatile.LoadUint32(&o.ACR2.Reg) & 0x8) >> 3
}
func (o *SAI_Type) SetACR2_FTH(value uint32) {
	volatile.StoreUint32(&o.ACR2.Reg, volatile.LoadUint32(&o.ACR2.Reg)&^(0x7)|value)
}
func (o *SAI_Type) GetACR2_FTH() uint32 {
	return volatile.LoadUint32(&o.ACR2.Reg) & 0x7
}

// SAI.AFRCR: A frame configuration register
func (o *SAI_Type) SetAFRCR_FSOFF(value uint32) {
	volatile.StoreUint32(&o.AFRCR.Reg, volatile.LoadUint32(&o.AFRCR.Reg)&^(0x40000)|value<<18)
}
func (o *SAI_Type) GetAFRCR_FSOFF() uint32 {
	return (volatile.LoadUint32(&o.AFRCR.Reg) & 0x40000) >> 18
}
func (o *SAI_Type) SetAFRCR_FSPOL(value uint32) {
	volatile.StoreUint32(&o.AFRCR.Reg, volatile.LoadUint32(&o.AFRCR.Reg)&^(0x20000)|value<<17)
}
func (o *SAI_Type) GetAFRCR_FSPOL() uint32 {
	return (volatile.LoadUint32(&o.AFRCR.Reg) & 0x20000) >> 17
}
func (o *SAI_Type) SetAFRCR_FSDEF(value uint32) {
	volatile.StoreUint32(&o.AFRCR.Reg, volatile.LoadUint32(&o.AFRCR.Reg)&^(0x10000)|value<<16)
}
func (o *SAI_Type) GetAFRCR_FSDEF() uint32 {
	return (volatile.LoadUint32(&o.AFRCR.Reg) & 0x10000) >> 16
}
func (o *SAI_Type) SetAFRCR_FSALL(value uint32) {
	volatile.StoreUint32(&o.AFRCR.Reg, volatile.LoadUint32(&o.AFRCR.Reg)&^(0x7f00)|value<<8)
}
func (o *SAI_Type) GetAFRCR_FSALL() uint32 {
	return (volatile.LoadUint32(&o.AFRCR.Reg) & 0x7f00) >> 8
}
func (o *SAI_Type) SetAFRCR_FRL(value uint32) {
	volatile.StoreUint32(&o.AFRCR.Reg, volatile.LoadUint32(&o.AFRCR.Reg)&^(0xff)|value)
}
func (o *SAI_Type) GetAFRCR_FRL() uint32 {
	return volatile.LoadUint32(&o.AFRCR.Reg) & 0xff
}

// SAI.ASLOTR: A Slot register
func (o *SAI_Type) SetASLOTR_SLOTEN(value uint32) {
	volatile.StoreUint32(&o.ASLOTR.Reg, volatile.LoadUint32(&o.ASLOTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *SAI_Type) GetASLOTR_SLOTEN() uint32 {
	return (volatile.LoadUint32(&o.ASLOTR.Reg) & 0xffff0000) >> 16
}
func (o *SAI_Type) SetASLOTR_NBSLOT(value uint32) {
	volatile.StoreUint32(&o.ASLOTR.Reg, volatile.LoadUint32(&o.ASLOTR.Reg)&^(0xf00)|value<<8)
}
func (o *SAI_Type) GetASLOTR_NBSLOT() uint32 {
	return (volatile.LoadUint32(&o.ASLOTR.Reg) & 0xf00) >> 8
}
func (o *SAI_Type) SetASLOTR_SLOTSZ(value uint32) {
	volatile.StoreUint32(&o.ASLOTR.Reg, volatile.LoadUint32(&o.ASLOTR.Reg)&^(0xc0)|value<<6)
}
func (o *SAI_Type) GetASLOTR_SLOTSZ() uint32 {
	return (volatile.LoadUint32(&o.ASLOTR.Reg) & 0xc0) >> 6
}
func (o *SAI_Type) SetASLOTR_FBOFF(value uint32) {
	volatile.StoreUint32(&o.ASLOTR.Reg, volatile.LoadUint32(&o.ASLOTR.Reg)&^(0x1f)|value)
}
func (o *SAI_Type) GetASLOTR_FBOFF() uint32 {
	return volatile.LoadUint32(&o.ASLOTR.Reg) & 0x1f
}

// SAI.AIM: A Interrupt mask register
func (o *SAI_Type) SetAIM_LFSDETIE(value uint32) {
	volatile.StoreUint32(&o.AIM.Reg, volatile.LoadUint32(&o.AIM.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetAIM_LFSDETIE() uint32 {
	return (volatile.LoadUint32(&o.AIM.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetAIM_AFSDETIE(value uint32) {
	volatile.StoreUint32(&o.AIM.Reg, volatile.LoadUint32(&o.AIM.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetAIM_AFSDETIE() uint32 {
	return (volatile.LoadUint32(&o.AIM.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetAIM_CNRDYIE(value uint32) {
	volatile.StoreUint32(&o.AIM.Reg, volatile.LoadUint32(&o.AIM.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetAIM_CNRDYIE() uint32 {
	return (volatile.LoadUint32(&o.AIM.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetAIM_FREQIE(value uint32) {
	volatile.StoreUint32(&o.AIM.Reg, volatile.LoadUint32(&o.AIM.Reg)&^(0x8)|value<<3)
}
func (o *SAI_Type) GetAIM_FREQIE() uint32 {
	return (volatile.LoadUint32(&o.AIM.Reg) & 0x8) >> 3
}
func (o *SAI_Type) SetAIM_WCKCFGIE(value uint32) {
	volatile.StoreUint32(&o.AIM.Reg, volatile.LoadUint32(&o.AIM.Reg)&^(0x4)|value<<2)
}
func (o *SAI_Type) GetAIM_WCKCFGIE() uint32 {
	return (volatile.LoadUint32(&o.AIM.Reg) & 0x4) >> 2
}
func (o *SAI_Type) SetAIM_MUTEDETIE(value uint32) {
	volatile.StoreUint32(&o.AIM.Reg, volatile.LoadUint32(&o.AIM.Reg)&^(0x2)|value<<1)
}
func (o *SAI_Type) GetAIM_MUTEDETIE() uint32 {
	return (volatile.LoadUint32(&o.AIM.Reg) & 0x2) >> 1
}
func (o *SAI_Type) SetAIM_OVRUDRIE(value uint32) {
	volatile.StoreUint32(&o.AIM.Reg, volatile.LoadUint32(&o.AIM.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetAIM_OVRUDRIE() uint32 {
	return volatile.LoadUint32(&o.AIM.Reg) & 0x1
}

// SAI.ASR: A Status register
func (o *SAI_Type) SetASR_FLVL(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x70000)|value<<16)
}
func (o *SAI_Type) GetASR_FLVL() uint32 {
	return (volatile.LoadUint32(&o.ASR.Reg) & 0x70000) >> 16
}
func (o *SAI_Type) SetASR_LFSDET(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetASR_LFSDET() uint32 {
	return (volatile.LoadUint32(&o.ASR.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetASR_AFSDET(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetASR_AFSDET() uint32 {
	return (volatile.LoadUint32(&o.ASR.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetASR_CNRDY(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetASR_CNRDY() uint32 {
	return (volatile.LoadUint32(&o.ASR.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetASR_FREQ(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x8)|value<<3)
}
func (o *SAI_Type) GetASR_FREQ() uint32 {
	return (volatile.LoadUint32(&o.ASR.Reg) & 0x8) >> 3
}
func (o *SAI_Type) SetASR_WCKCFG(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x4)|value<<2)
}
func (o *SAI_Type) GetASR_WCKCFG() uint32 {
	return (volatile.LoadUint32(&o.ASR.Reg) & 0x4) >> 2
}
func (o *SAI_Type) SetASR_MUTEDET(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x2)|value<<1)
}
func (o *SAI_Type) GetASR_MUTEDET() uint32 {
	return (volatile.LoadUint32(&o.ASR.Reg) & 0x2) >> 1
}
func (o *SAI_Type) SetASR_OVRUDR(value uint32) {
	volatile.StoreUint32(&o.ASR.Reg, volatile.LoadUint32(&o.ASR.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetASR_OVRUDR() uint32 {
	return volatile.LoadUint32(&o.ASR.Reg) & 0x1
}

// SAI.ACLRFR: A Clear flag register
func (o *SAI_Type) SetACLRFR_CLFSDET(value uint32) {
	volatile.StoreUint32(&o.ACLRFR.Reg, volatile.LoadUint32(&o.ACLRFR.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetACLRFR_CLFSDET() uint32 {
	return (volatile.LoadUint32(&o.ACLRFR.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetACLRFR_CAFSDET(value uint32) {
	volatile.StoreUint32(&o.ACLRFR.Reg, volatile.LoadUint32(&o.ACLRFR.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetACLRFR_CAFSDET() uint32 {
	return (volatile.LoadUint32(&o.ACLRFR.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetACLRFR_CCNRDY(value uint32) {
	volatile.StoreUint32(&o.ACLRFR.Reg, volatile.LoadUint32(&o.ACLRFR.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetACLRFR_CCNRDY() uint32 {
	return (volatile.LoadUint32(&o.ACLRFR.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetACLRFR_CWCKCFG(value uint32) {
	volatile.StoreUint32(&o.ACLRFR.Reg, volatile.LoadUint32(&o.ACLRFR.Reg)&^(0x4)|value<<2)
}
func (o *SAI_Type) GetACLRFR_CWCKCFG() uint32 {
	return (volatile.LoadUint32(&o.ACLRFR.Reg) & 0x4) >> 2
}
func (o *SAI_Type) SetACLRFR_CMUTEDET(value uint32) {
	volatile.StoreUint32(&o.ACLRFR.Reg, volatile.LoadUint32(&o.ACLRFR.Reg)&^(0x2)|value<<1)
}
func (o *SAI_Type) GetACLRFR_CMUTEDET() uint32 {
	return (volatile.LoadUint32(&o.ACLRFR.Reg) & 0x2) >> 1
}
func (o *SAI_Type) SetACLRFR_COVRUDR(value uint32) {
	volatile.StoreUint32(&o.ACLRFR.Reg, volatile.LoadUint32(&o.ACLRFR.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetACLRFR_COVRUDR() uint32 {
	return volatile.LoadUint32(&o.ACLRFR.Reg) & 0x1
}

// SAI.ADR: A Data register
func (o *SAI_Type) SetADR(value uint32) {
	volatile.StoreUint32(&o.ADR.Reg, value)
}
func (o *SAI_Type) GetADR() uint32 {
	return volatile.LoadUint32(&o.ADR.Reg)
}

// SAI.BCR1: B Configuration register 1
func (o *SAI_Type) SetBCR1_MCKEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x8000000)|value<<27)
}
func (o *SAI_Type) GetBCR1_MCKEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x8000000) >> 27
}
func (o *SAI_Type) SetBCR1_OSR(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x4000000)|value<<26)
}
func (o *SAI_Type) GetBCR1_OSR() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x4000000) >> 26
}
func (o *SAI_Type) SetBCR1_MCKDIV(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x3f00000)|value<<20)
}
func (o *SAI_Type) GetBCR1_MCKDIV() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x3f00000) >> 20
}
func (o *SAI_Type) SetBCR1_NODIV(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x80000)|value<<19)
}
func (o *SAI_Type) GetBCR1_NODIV() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x80000) >> 19
}
func (o *SAI_Type) SetBCR1_DMAEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x20000)|value<<17)
}
func (o *SAI_Type) GetBCR1_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x20000) >> 17
}
func (o *SAI_Type) SetBCR1_SAIAEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x10000)|value<<16)
}
func (o *SAI_Type) GetBCR1_SAIAEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x10000) >> 16
}
func (o *SAI_Type) SetBCR1_OUTDRIV(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x2000)|value<<13)
}
func (o *SAI_Type) GetBCR1_OUTDRIV() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x2000) >> 13
}
func (o *SAI_Type) SetBCR1_MONO(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x1000)|value<<12)
}
func (o *SAI_Type) GetBCR1_MONO() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x1000) >> 12
}
func (o *SAI_Type) SetBCR1_SYNCEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0xc00)|value<<10)
}
func (o *SAI_Type) GetBCR1_SYNCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0xc00) >> 10
}
func (o *SAI_Type) SetBCR1_CKSTR(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x200)|value<<9)
}
func (o *SAI_Type) GetBCR1_CKSTR() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x200) >> 9
}
func (o *SAI_Type) SetBCR1_LSBFIRST(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x100)|value<<8)
}
func (o *SAI_Type) GetBCR1_LSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x100) >> 8
}
func (o *SAI_Type) SetBCR1_DS(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0xe0)|value<<5)
}
func (o *SAI_Type) GetBCR1_DS() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0xe0) >> 5
}
func (o *SAI_Type) SetBCR1_PRTCFG(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0xc)|value<<2)
}
func (o *SAI_Type) GetBCR1_PRTCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0xc) >> 2
}
func (o *SAI_Type) SetBCR1_MODE(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x3)|value)
}
func (o *SAI_Type) GetBCR1_MODE() uint32 {
	return volatile.LoadUint32(&o.BCR1.Reg) & 0x3
}

// SAI.BCR2: B Configuration register 2
func (o *SAI_Type) SetBCR2_COMP(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0xc000)|value<<14)
}
func (o *SAI_Type) GetBCR2_COMP() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0xc000) >> 14
}
func (o *SAI_Type) SetBCR2_CPL(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x2000)|value<<13)
}
func (o *SAI_Type) GetBCR2_CPL() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x2000) >> 13
}
func (o *SAI_Type) SetBCR2_MUTECN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x1f80)|value<<7)
}
func (o *SAI_Type) GetBCR2_MUTECN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x1f80) >> 7
}
func (o *SAI_Type) SetBCR2_MUTEVAL(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetBCR2_MUTEVAL() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetBCR2_MUTE(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetBCR2_MUTE() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetBCR2_TRIS(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetBCR2_TRIS() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetBCR2_FFLUSH(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x8)|value<<3)
}
func (o *SAI_Type) GetBCR2_FFLUSH() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x8) >> 3
}
func (o *SAI_Type) SetBCR2_FTH(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x7)|value)
}
func (o *SAI_Type) GetBCR2_FTH() uint32 {
	return volatile.LoadUint32(&o.BCR2.Reg) & 0x7
}

// SAI.BFRCR: B frame configuration register
func (o *SAI_Type) SetBFRCR_FSOFF(value uint32) {
	volatile.StoreUint32(&o.BFRCR.Reg, volatile.LoadUint32(&o.BFRCR.Reg)&^(0x40000)|value<<18)
}
func (o *SAI_Type) GetBFRCR_FSOFF() uint32 {
	return (volatile.LoadUint32(&o.BFRCR.Reg) & 0x40000) >> 18
}
func (o *SAI_Type) SetBFRCR_FSPOL(value uint32) {
	volatile.StoreUint32(&o.BFRCR.Reg, volatile.LoadUint32(&o.BFRCR.Reg)&^(0x20000)|value<<17)
}
func (o *SAI_Type) GetBFRCR_FSPOL() uint32 {
	return (volatile.LoadUint32(&o.BFRCR.Reg) & 0x20000) >> 17
}
func (o *SAI_Type) SetBFRCR_FSDEF(value uint32) {
	volatile.StoreUint32(&o.BFRCR.Reg, volatile.LoadUint32(&o.BFRCR.Reg)&^(0x10000)|value<<16)
}
func (o *SAI_Type) GetBFRCR_FSDEF() uint32 {
	return (volatile.LoadUint32(&o.BFRCR.Reg) & 0x10000) >> 16
}
func (o *SAI_Type) SetBFRCR_FSALL(value uint32) {
	volatile.StoreUint32(&o.BFRCR.Reg, volatile.LoadUint32(&o.BFRCR.Reg)&^(0x7f00)|value<<8)
}
func (o *SAI_Type) GetBFRCR_FSALL() uint32 {
	return (volatile.LoadUint32(&o.BFRCR.Reg) & 0x7f00) >> 8
}
func (o *SAI_Type) SetBFRCR_FRL(value uint32) {
	volatile.StoreUint32(&o.BFRCR.Reg, volatile.LoadUint32(&o.BFRCR.Reg)&^(0xff)|value)
}
func (o *SAI_Type) GetBFRCR_FRL() uint32 {
	return volatile.LoadUint32(&o.BFRCR.Reg) & 0xff
}

// SAI.BSLOTR: B Slot register
func (o *SAI_Type) SetBSLOTR_SLOTEN(value uint32) {
	volatile.StoreUint32(&o.BSLOTR.Reg, volatile.LoadUint32(&o.BSLOTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *SAI_Type) GetBSLOTR_SLOTEN() uint32 {
	return (volatile.LoadUint32(&o.BSLOTR.Reg) & 0xffff0000) >> 16
}
func (o *SAI_Type) SetBSLOTR_NBSLOT(value uint32) {
	volatile.StoreUint32(&o.BSLOTR.Reg, volatile.LoadUint32(&o.BSLOTR.Reg)&^(0xf00)|value<<8)
}
func (o *SAI_Type) GetBSLOTR_NBSLOT() uint32 {
	return (volatile.LoadUint32(&o.BSLOTR.Reg) & 0xf00) >> 8
}
func (o *SAI_Type) SetBSLOTR_SLOTSZ(value uint32) {
	volatile.StoreUint32(&o.BSLOTR.Reg, volatile.LoadUint32(&o.BSLOTR.Reg)&^(0xc0)|value<<6)
}
func (o *SAI_Type) GetBSLOTR_SLOTSZ() uint32 {
	return (volatile.LoadUint32(&o.BSLOTR.Reg) & 0xc0) >> 6
}
func (o *SAI_Type) SetBSLOTR_FBOFF(value uint32) {
	volatile.StoreUint32(&o.BSLOTR.Reg, volatile.LoadUint32(&o.BSLOTR.Reg)&^(0x1f)|value)
}
func (o *SAI_Type) GetBSLOTR_FBOFF() uint32 {
	return volatile.LoadUint32(&o.BSLOTR.Reg) & 0x1f
}

// SAI.BIM: B Interrupt mask register
func (o *SAI_Type) SetBIM_LFSDETIE(value uint32) {
	volatile.StoreUint32(&o.BIM.Reg, volatile.LoadUint32(&o.BIM.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetBIM_LFSDETIE() uint32 {
	return (volatile.LoadUint32(&o.BIM.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetBIM_AFSDETIE(value uint32) {
	volatile.StoreUint32(&o.BIM.Reg, volatile.LoadUint32(&o.BIM.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetBIM_AFSDETIE() uint32 {
	return (volatile.LoadUint32(&o.BIM.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetBIM_CNRDYIE(value uint32) {
	volatile.StoreUint32(&o.BIM.Reg, volatile.LoadUint32(&o.BIM.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetBIM_CNRDYIE() uint32 {
	return (volatile.LoadUint32(&o.BIM.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetBIM_FREQIE(value uint32) {
	volatile.StoreUint32(&o.BIM.Reg, volatile.LoadUint32(&o.BIM.Reg)&^(0x8)|value<<3)
}
func (o *SAI_Type) GetBIM_FREQIE() uint32 {
	return (volatile.LoadUint32(&o.BIM.Reg) & 0x8) >> 3
}
func (o *SAI_Type) SetBIM_WCKCFGIE(value uint32) {
	volatile.StoreUint32(&o.BIM.Reg, volatile.LoadUint32(&o.BIM.Reg)&^(0x4)|value<<2)
}
func (o *SAI_Type) GetBIM_WCKCFGIE() uint32 {
	return (volatile.LoadUint32(&o.BIM.Reg) & 0x4) >> 2
}
func (o *SAI_Type) SetBIM_MUTEDETIE(value uint32) {
	volatile.StoreUint32(&o.BIM.Reg, volatile.LoadUint32(&o.BIM.Reg)&^(0x2)|value<<1)
}
func (o *SAI_Type) GetBIM_MUTEDETIE() uint32 {
	return (volatile.LoadUint32(&o.BIM.Reg) & 0x2) >> 1
}
func (o *SAI_Type) SetBIM_OVRUDRIE(value uint32) {
	volatile.StoreUint32(&o.BIM.Reg, volatile.LoadUint32(&o.BIM.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetBIM_OVRUDRIE() uint32 {
	return volatile.LoadUint32(&o.BIM.Reg) & 0x1
}

// SAI.BSR: B Status register
func (o *SAI_Type) SetBSR_FLVL(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x70000)|value<<16)
}
func (o *SAI_Type) GetBSR_FLVL() uint32 {
	return (volatile.LoadUint32(&o.BSR.Reg) & 0x70000) >> 16
}
func (o *SAI_Type) SetBSR_LFSDET(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetBSR_LFSDET() uint32 {
	return (volatile.LoadUint32(&o.BSR.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetBSR_AFSDET(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetBSR_AFSDET() uint32 {
	return (volatile.LoadUint32(&o.BSR.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetBSR_CNRDY(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetBSR_CNRDY() uint32 {
	return (volatile.LoadUint32(&o.BSR.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetBSR_FREQ(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x8)|value<<3)
}
func (o *SAI_Type) GetBSR_FREQ() uint32 {
	return (volatile.LoadUint32(&o.BSR.Reg) & 0x8) >> 3
}
func (o *SAI_Type) SetBSR_WCKCFG(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x4)|value<<2)
}
func (o *SAI_Type) GetBSR_WCKCFG() uint32 {
	return (volatile.LoadUint32(&o.BSR.Reg) & 0x4) >> 2
}
func (o *SAI_Type) SetBSR_MUTEDET(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x2)|value<<1)
}
func (o *SAI_Type) GetBSR_MUTEDET() uint32 {
	return (volatile.LoadUint32(&o.BSR.Reg) & 0x2) >> 1
}
func (o *SAI_Type) SetBSR_OVRUDR(value uint32) {
	volatile.StoreUint32(&o.BSR.Reg, volatile.LoadUint32(&o.BSR.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetBSR_OVRUDR() uint32 {
	return volatile.LoadUint32(&o.BSR.Reg) & 0x1
}

// SAI.BCLRFR: B Clear flag register
func (o *SAI_Type) SetBCLRFR_CLFSDET(value uint32) {
	volatile.StoreUint32(&o.BCLRFR.Reg, volatile.LoadUint32(&o.BCLRFR.Reg)&^(0x40)|value<<6)
}
func (o *SAI_Type) GetBCLRFR_CLFSDET() uint32 {
	return (volatile.LoadUint32(&o.BCLRFR.Reg) & 0x40) >> 6
}
func (o *SAI_Type) SetBCLRFR_CAFSDET(value uint32) {
	volatile.StoreUint32(&o.BCLRFR.Reg, volatile.LoadUint32(&o.BCLRFR.Reg)&^(0x20)|value<<5)
}
func (o *SAI_Type) GetBCLRFR_CAFSDET() uint32 {
	return (volatile.LoadUint32(&o.BCLRFR.Reg) & 0x20) >> 5
}
func (o *SAI_Type) SetBCLRFR_CCNRDY(value uint32) {
	volatile.StoreUint32(&o.BCLRFR.Reg, volatile.LoadUint32(&o.BCLRFR.Reg)&^(0x10)|value<<4)
}
func (o *SAI_Type) GetBCLRFR_CCNRDY() uint32 {
	return (volatile.LoadUint32(&o.BCLRFR.Reg) & 0x10) >> 4
}
func (o *SAI_Type) SetBCLRFR_CWCKCFG(value uint32) {
	volatile.StoreUint32(&o.BCLRFR.Reg, volatile.LoadUint32(&o.BCLRFR.Reg)&^(0x4)|value<<2)
}
func (o *SAI_Type) GetBCLRFR_CWCKCFG() uint32 {
	return (volatile.LoadUint32(&o.BCLRFR.Reg) & 0x4) >> 2
}
func (o *SAI_Type) SetBCLRFR_CMUTEDET(value uint32) {
	volatile.StoreUint32(&o.BCLRFR.Reg, volatile.LoadUint32(&o.BCLRFR.Reg)&^(0x2)|value<<1)
}
func (o *SAI_Type) GetBCLRFR_CMUTEDET() uint32 {
	return (volatile.LoadUint32(&o.BCLRFR.Reg) & 0x2) >> 1
}
func (o *SAI_Type) SetBCLRFR_COVRUDR(value uint32) {
	volatile.StoreUint32(&o.BCLRFR.Reg, volatile.LoadUint32(&o.BCLRFR.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetBCLRFR_COVRUDR() uint32 {
	return volatile.LoadUint32(&o.BCLRFR.Reg) & 0x1
}

// SAI.BDR: B Data register
func (o *SAI_Type) SetBDR(value uint32) {
	volatile.StoreUint32(&o.BDR.Reg, value)
}
func (o *SAI_Type) GetBDR() uint32 {
	return volatile.LoadUint32(&o.BDR.Reg)
}

// SAI.PDMCR: PDM control register
func (o *SAI_Type) SetPDMCR_PDMEN(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetPDMCR_PDMEN() uint32 {
	return volatile.LoadUint32(&o.PDMCR.Reg) & 0x1
}
func (o *SAI_Type) SetPDMCR_MICNBR(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x30)|value<<4)
}
func (o *SAI_Type) GetPDMCR_MICNBR() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x30) >> 4
}
func (o *SAI_Type) SetPDMCR_CKEN1(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x100)|value<<8)
}
func (o *SAI_Type) GetPDMCR_CKEN1() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x100) >> 8
}
func (o *SAI_Type) SetPDMCR_CKEN2(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x200)|value<<9)
}
func (o *SAI_Type) GetPDMCR_CKEN2() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x200) >> 9
}
func (o *SAI_Type) SetPDMCR_CKEN3(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x400)|value<<10)
}
func (o *SAI_Type) GetPDMCR_CKEN3() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x400) >> 10
}
func (o *SAI_Type) SetPDMCR_CKEN4(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x800)|value<<11)
}
func (o *SAI_Type) GetPDMCR_CKEN4() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x800) >> 11
}

// SAI.PDMDLY: PDM delay register
func (o *SAI_Type) SetPDMDLY_DLYM1L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x7)|value)
}
func (o *SAI_Type) GetPDMDLY_DLYM1L() uint32 {
	return volatile.LoadUint32(&o.PDMDLY.Reg) & 0x7
}
func (o *SAI_Type) SetPDMDLY_DLYM1R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x70)|value<<4)
}
func (o *SAI_Type) GetPDMDLY_DLYM1R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x70) >> 4
}
func (o *SAI_Type) SetPDMDLY_DLYM2L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x700)|value<<8)
}
func (o *SAI_Type) GetPDMDLY_DLYM2L() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x700) >> 8
}
func (o *SAI_Type) SetPDMDLY_DLYM2R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x7000)|value<<12)
}
func (o *SAI_Type) GetPDMDLY_DLYM2R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x7000) >> 12
}
func (o *SAI_Type) SetPDMDLY_DLYM3L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x70000)|value<<16)
}
func (o *SAI_Type) GetPDMDLY_DLYM3L() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x70000) >> 16
}
func (o *SAI_Type) SetPDMDLY_DLYM3R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x700000)|value<<20)
}
func (o *SAI_Type) GetPDMDLY_DLYM3R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x700000) >> 20
}
func (o *SAI_Type) SetPDMDLY_DLYM4L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x7000000)|value<<24)
}
func (o *SAI_Type) GetPDMDLY_DLYM4L() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x7000000) >> 24
}
func (o *SAI_Type) SetPDMDLY_DLYM4R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x70000000)|value<<28)
}
func (o *SAI_Type) GetPDMDLY_DLYM4R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x70000000) >> 28
}

// Secure digital input/output MultiMediaCard interface
type SDMMC_Type struct {
	POWER      volatile.Register32 // 0x0
	CLKCR      volatile.Register32 // 0x4
	ARGR       volatile.Register32 // 0x8
	CMDR       volatile.Register32 // 0xC
	RESPCMDR   volatile.Register32 // 0x10
	RESP1      volatile.Register32 // 0x14
	RESP2      volatile.Register32 // 0x18
	RESP3      volatile.Register32 // 0x1C
	RESP4      volatile.Register32 // 0x20
	DTIMER     volatile.Register32 // 0x24
	DLENR      volatile.Register32 // 0x28
	DCTRL      volatile.Register32 // 0x2C
	DCNTR      volatile.Register32 // 0x30
	STAR       volatile.Register32 // 0x34
	ICR        volatile.Register32 // 0x38
	MASKR      volatile.Register32 // 0x3C
	ACKTIMER   volatile.Register32 // 0x40
	_          [12]byte
	IDMACTRLR  volatile.Register32 // 0x50
	IDMABSIZER volatile.Register32 // 0x54
	IDMABASER  volatile.Register32 // 0x58
	_          [8]byte
	IDMALAR    volatile.Register32 // 0x64
	IDMABAR    volatile.Register32 // 0x68
	_          [20]byte
	FIFOR0     volatile.Register32 // 0x80
	FIFOR1     volatile.Register32 // 0x84
	FIFOR2     volatile.Register32 // 0x88
	FIFOR3     volatile.Register32 // 0x8C
	FIFOR4     volatile.Register32 // 0x90
	FIFOR5     volatile.Register32 // 0x94
	FIFOR6     volatile.Register32 // 0x98
	FIFOR7     volatile.Register32 // 0x9C
	FIFOR8     volatile.Register32 // 0xA0
	FIFOR9     volatile.Register32 // 0xA4
	FIFOR10    volatile.Register32 // 0xA8
	FIFOR11    volatile.Register32 // 0xAC
	FIFOR12    volatile.Register32 // 0xB0
	FIFOR13    volatile.Register32 // 0xB4
	FIFOR14    volatile.Register32 // 0xB8
	FIFOR15    volatile.Register32 // 0xBC
}

// SDMMC.POWER: power control register
func (o *SDMMC_Type) SetPOWER_PWRCTRL(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x3)|value)
}
func (o *SDMMC_Type) GetPOWER_PWRCTRL() uint32 {
	return volatile.LoadUint32(&o.POWER.Reg) & 0x3
}
func (o *SDMMC_Type) SetPOWER_VSWITCH(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetPOWER_VSWITCH() uint32 {
	return (volatile.LoadUint32(&o.POWER.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetPOWER_VSWITCHEN(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetPOWER_VSWITCHEN() uint32 {
	return (volatile.LoadUint32(&o.POWER.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetPOWER_DIRPOL(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetPOWER_DIRPOL() uint32 {
	return (volatile.LoadUint32(&o.POWER.Reg) & 0x10) >> 4
}

// SDMMC.CLKCR: clock control register
func (o *SDMMC_Type) SetCLKCR_SELCLKRX(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x300000)|value<<20)
}
func (o *SDMMC_Type) GetCLKCR_SELCLKRX() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x300000) >> 20
}
func (o *SDMMC_Type) SetCLKCR_BUSSPEED(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x80000)|value<<19)
}
func (o *SDMMC_Type) GetCLKCR_BUSSPEED() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x80000) >> 19
}
func (o *SDMMC_Type) SetCLKCR_DDR(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x40000)|value<<18)
}
func (o *SDMMC_Type) GetCLKCR_DDR() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x40000) >> 18
}
func (o *SDMMC_Type) SetCLKCR_HWFC_EN(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x20000)|value<<17)
}
func (o *SDMMC_Type) GetCLKCR_HWFC_EN() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x20000) >> 17
}
func (o *SDMMC_Type) SetCLKCR_NEGEDGE(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x10000)|value<<16)
}
func (o *SDMMC_Type) GetCLKCR_NEGEDGE() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x10000) >> 16
}
func (o *SDMMC_Type) SetCLKCR_WIDBUS(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0xc000)|value<<14)
}
func (o *SDMMC_Type) GetCLKCR_WIDBUS() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0xc000) >> 14
}
func (o *SDMMC_Type) SetCLKCR_PWRSAV(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetCLKCR_PWRSAV() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetCLKCR_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x3ff)|value)
}
func (o *SDMMC_Type) GetCLKCR_CLKDIV() uint32 {
	return volatile.LoadUint32(&o.CLKCR.Reg) & 0x3ff
}

// SDMMC.ARGR: argument register
func (o *SDMMC_Type) SetARGR(value uint32) {
	volatile.StoreUint32(&o.ARGR.Reg, value)
}
func (o *SDMMC_Type) GetARGR() uint32 {
	return volatile.LoadUint32(&o.ARGR.Reg)
}

// SDMMC.CMDR: command register
func (o *SDMMC_Type) SetCMDR_CMDSUSPEND(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x10000)|value<<16)
}
func (o *SDMMC_Type) GetCMDR_CMDSUSPEND() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x10000) >> 16
}
func (o *SDMMC_Type) SetCMDR_BOOTEN(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x8000)|value<<15)
}
func (o *SDMMC_Type) GetCMDR_BOOTEN() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x8000) >> 15
}
func (o *SDMMC_Type) SetCMDR_BOOTMODE(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x4000)|value<<14)
}
func (o *SDMMC_Type) GetCMDR_BOOTMODE() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x4000) >> 14
}
func (o *SDMMC_Type) SetCMDR_DTHOLD(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x2000)|value<<13)
}
func (o *SDMMC_Type) GetCMDR_DTHOLD() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x2000) >> 13
}
func (o *SDMMC_Type) SetCMDR_CPSMEN(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetCMDR_CPSMEN() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetCMDR_WAITPEND(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetCMDR_WAITPEND() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetCMDR_WAITINT(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetCMDR_WAITINT() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetCMDR_WAITRESP(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x300)|value<<8)
}
func (o *SDMMC_Type) GetCMDR_WAITRESP() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x300) >> 8
}
func (o *SDMMC_Type) SetCMDR_CMDSTOP(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetCMDR_CMDSTOP() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetCMDR_CMDTRANS(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetCMDR_CMDTRANS() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetCMDR_CMDINDEX(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x3f)|value)
}
func (o *SDMMC_Type) GetCMDR_CMDINDEX() uint32 {
	return volatile.LoadUint32(&o.CMDR.Reg) & 0x3f
}

// SDMMC.RESPCMDR: command response register
func (o *SDMMC_Type) SetRESPCMDR_RESPCMD(value uint32) {
	volatile.StoreUint32(&o.RESPCMDR.Reg, volatile.LoadUint32(&o.RESPCMDR.Reg)&^(0x3f)|value)
}
func (o *SDMMC_Type) GetRESPCMDR_RESPCMD() uint32 {
	return volatile.LoadUint32(&o.RESPCMDR.Reg) & 0x3f
}

// SDMMC.RESP1: SDIO response %s register
func (o *SDMMC_Type) SetRESP1(value uint32) {
	volatile.StoreUint32(&o.RESP1.Reg, value)
}
func (o *SDMMC_Type) GetRESP1() uint32 {
	return volatile.LoadUint32(&o.RESP1.Reg)
}

// SDMMC.RESP2: SDIO response %s register
func (o *SDMMC_Type) SetRESP2(value uint32) {
	volatile.StoreUint32(&o.RESP2.Reg, value)
}
func (o *SDMMC_Type) GetRESP2() uint32 {
	return volatile.LoadUint32(&o.RESP2.Reg)
}

// SDMMC.RESP3: SDIO response %s register
func (o *SDMMC_Type) SetRESP3(value uint32) {
	volatile.StoreUint32(&o.RESP3.Reg, value)
}
func (o *SDMMC_Type) GetRESP3() uint32 {
	return volatile.LoadUint32(&o.RESP3.Reg)
}

// SDMMC.RESP4: SDIO response %s register
func (o *SDMMC_Type) SetRESP4(value uint32) {
	volatile.StoreUint32(&o.RESP4.Reg, value)
}
func (o *SDMMC_Type) GetRESP4() uint32 {
	return volatile.LoadUint32(&o.RESP4.Reg)
}

// SDMMC.DTIMER: data timer register
func (o *SDMMC_Type) SetDTIMER(value uint32) {
	volatile.StoreUint32(&o.DTIMER.Reg, value)
}
func (o *SDMMC_Type) GetDTIMER() uint32 {
	return volatile.LoadUint32(&o.DTIMER.Reg)
}

// SDMMC.DLENR: data length register
func (o *SDMMC_Type) SetDLENR_DATALENGTH(value uint32) {
	volatile.StoreUint32(&o.DLENR.Reg, volatile.LoadUint32(&o.DLENR.Reg)&^(0x1ffffff)|value)
}
func (o *SDMMC_Type) GetDLENR_DATALENGTH() uint32 {
	return volatile.LoadUint32(&o.DLENR.Reg) & 0x1ffffff
}

// SDMMC.DCTRL: data control register
func (o *SDMMC_Type) SetDCTRL_FIFORST(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x2000)|value<<13)
}
func (o *SDMMC_Type) GetDCTRL_FIFORST() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x2000) >> 13
}
func (o *SDMMC_Type) SetDCTRL_BOOTACKEN(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetDCTRL_BOOTACKEN() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetDCTRL_SDIOEN(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetDCTRL_SDIOEN() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetDCTRL_RWMOD(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetDCTRL_RWMOD() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetDCTRL_RWSTOP(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetDCTRL_RWSTOP() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetDCTRL_RWSTART(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetDCTRL_RWSTART() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetDCTRL_DBLOCKSIZE(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0xf0)|value<<4)
}
func (o *SDMMC_Type) GetDCTRL_DBLOCKSIZE() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0xf0) >> 4
}
func (o *SDMMC_Type) SetDCTRL_DTMODE(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0xc)|value<<2)
}
func (o *SDMMC_Type) GetDCTRL_DTMODE() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0xc) >> 2
}
func (o *SDMMC_Type) SetDCTRL_DTDIR(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetDCTRL_DTDIR() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetDCTRL_DTEN(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetDCTRL_DTEN() uint32 {
	return volatile.LoadUint32(&o.DCTRL.Reg) & 0x1
}

// SDMMC.DCNTR: data counter register
func (o *SDMMC_Type) SetDCNTR_DATACOUNT(value uint32) {
	volatile.StoreUint32(&o.DCNTR.Reg, volatile.LoadUint32(&o.DCNTR.Reg)&^(0x1ffffff)|value)
}
func (o *SDMMC_Type) GetDCNTR_DATACOUNT() uint32 {
	return volatile.LoadUint32(&o.DCNTR.Reg) & 0x1ffffff
}

// SDMMC.STAR: status register
func (o *SDMMC_Type) SetSTAR_IDMABTC(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x10000000)|value<<28)
}
func (o *SDMMC_Type) GetSTAR_IDMABTC() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x10000000) >> 28
}
func (o *SDMMC_Type) SetSTAR_IDMATE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x8000000)|value<<27)
}
func (o *SDMMC_Type) GetSTAR_IDMATE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x8000000) >> 27
}
func (o *SDMMC_Type) SetSTAR_CKSTOP(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x4000000)|value<<26)
}
func (o *SDMMC_Type) GetSTAR_CKSTOP() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x4000000) >> 26
}
func (o *SDMMC_Type) SetSTAR_VSWEND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x2000000)|value<<25)
}
func (o *SDMMC_Type) GetSTAR_VSWEND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x2000000) >> 25
}
func (o *SDMMC_Type) SetSTAR_ACKTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x1000000)|value<<24)
}
func (o *SDMMC_Type) GetSTAR_ACKTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x1000000) >> 24
}
func (o *SDMMC_Type) SetSTAR_ACKFAIL(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x800000)|value<<23)
}
func (o *SDMMC_Type) GetSTAR_ACKFAIL() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x800000) >> 23
}
func (o *SDMMC_Type) SetSTAR_SDIOIT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x400000)|value<<22)
}
func (o *SDMMC_Type) GetSTAR_SDIOIT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x400000) >> 22
}
func (o *SDMMC_Type) SetSTAR_BUSYD0END(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x200000)|value<<21)
}
func (o *SDMMC_Type) GetSTAR_BUSYD0END() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x200000) >> 21
}
func (o *SDMMC_Type) SetSTAR_BUSYD0(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x100000)|value<<20)
}
func (o *SDMMC_Type) GetSTAR_BUSYD0() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x100000) >> 20
}
func (o *SDMMC_Type) SetSTAR_RXFIFOE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x80000)|value<<19)
}
func (o *SDMMC_Type) GetSTAR_RXFIFOE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x80000) >> 19
}
func (o *SDMMC_Type) SetSTAR_TXFIFOE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x40000)|value<<18)
}
func (o *SDMMC_Type) GetSTAR_TXFIFOE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x40000) >> 18
}
func (o *SDMMC_Type) SetSTAR_RXFIFOF(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x20000)|value<<17)
}
func (o *SDMMC_Type) GetSTAR_RXFIFOF() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x20000) >> 17
}
func (o *SDMMC_Type) SetSTAR_TXFIFOF(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x10000)|value<<16)
}
func (o *SDMMC_Type) GetSTAR_TXFIFOF() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x10000) >> 16
}
func (o *SDMMC_Type) SetSTAR_RXFIFOHF(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x8000)|value<<15)
}
func (o *SDMMC_Type) GetSTAR_RXFIFOHF() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x8000) >> 15
}
func (o *SDMMC_Type) SetSTAR_TXFIFOHE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x4000)|value<<14)
}
func (o *SDMMC_Type) GetSTAR_TXFIFOHE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x4000) >> 14
}
func (o *SDMMC_Type) SetSTAR_CPSMACT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x2000)|value<<13)
}
func (o *SDMMC_Type) GetSTAR_CPSMACT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x2000) >> 13
}
func (o *SDMMC_Type) SetSTAR_DPSMACT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetSTAR_DPSMACT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetSTAR_DABORT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetSTAR_DABORT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetSTAR_DBCKEND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetSTAR_DBCKEND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetSTAR_DHOLD(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetSTAR_DHOLD() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetSTAR_DATAEND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetSTAR_DATAEND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetSTAR_CMDSENT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetSTAR_CMDSENT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetSTAR_CMDREND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetSTAR_CMDREND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetSTAR_RXOVERR(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x20)|value<<5)
}
func (o *SDMMC_Type) GetSTAR_RXOVERR() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x20) >> 5
}
func (o *SDMMC_Type) SetSTAR_TXUNDERR(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetSTAR_TXUNDERR() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x10) >> 4
}
func (o *SDMMC_Type) SetSTAR_DTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetSTAR_DTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetSTAR_CTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetSTAR_CTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetSTAR_DCRCFAIL(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetSTAR_DCRCFAIL() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetSTAR_CCRCFAIL(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetSTAR_CCRCFAIL() uint32 {
	return volatile.LoadUint32(&o.STAR.Reg) & 0x1
}

// SDMMC.ICR: interrupt clear register
func (o *SDMMC_Type) SetICR_IDMABTCC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10000000)|value<<28)
}
func (o *SDMMC_Type) GetICR_IDMABTCC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10000000) >> 28
}
func (o *SDMMC_Type) SetICR_IDMATEC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8000000)|value<<27)
}
func (o *SDMMC_Type) GetICR_IDMATEC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8000000) >> 27
}
func (o *SDMMC_Type) SetICR_CKSTOPC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4000000)|value<<26)
}
func (o *SDMMC_Type) GetICR_CKSTOPC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4000000) >> 26
}
func (o *SDMMC_Type) SetICR_VSWENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000000)|value<<25)
}
func (o *SDMMC_Type) GetICR_VSWENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000000) >> 25
}
func (o *SDMMC_Type) SetICR_ACKTIMEOUTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000000)|value<<24)
}
func (o *SDMMC_Type) GetICR_ACKTIMEOUTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000000) >> 24
}
func (o *SDMMC_Type) SetICR_ACKFAILC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800000)|value<<23)
}
func (o *SDMMC_Type) GetICR_ACKFAILC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800000) >> 23
}
func (o *SDMMC_Type) SetICR_SDIOITC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400000)|value<<22)
}
func (o *SDMMC_Type) GetICR_SDIOITC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400000) >> 22
}
func (o *SDMMC_Type) SetICR_BUSYD0ENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200000)|value<<21)
}
func (o *SDMMC_Type) GetICR_BUSYD0ENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200000) >> 21
}
func (o *SDMMC_Type) SetICR_DABORTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetICR_DABORTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetICR_DBCKENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetICR_DBCKENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetICR_DHOLDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetICR_DHOLDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetICR_DATAENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetICR_DATAENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetICR_CMDSENTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetICR_CMDSENTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetICR_CMDRENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetICR_CMDRENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetICR_RXOVERRC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *SDMMC_Type) GetICR_RXOVERRC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *SDMMC_Type) SetICR_TXUNDERRC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetICR_TXUNDERRC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *SDMMC_Type) SetICR_DTIMEOUTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetICR_DTIMEOUTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetICR_CTIMEOUTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetICR_CTIMEOUTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetICR_DCRCFAILC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetICR_DCRCFAILC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetICR_CCRCFAILC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetICR_CCRCFAILC() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}

// SDMMC.MASKR: mask register
func (o *SDMMC_Type) SetMASKR_IDMABTCIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x10000000)|value<<28)
}
func (o *SDMMC_Type) GetMASKR_IDMABTCIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x10000000) >> 28
}
func (o *SDMMC_Type) SetMASKR_CKSTOPIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x4000000)|value<<26)
}
func (o *SDMMC_Type) GetMASKR_CKSTOPIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x4000000) >> 26
}
func (o *SDMMC_Type) SetMASKR_VSWENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x2000000)|value<<25)
}
func (o *SDMMC_Type) GetMASKR_VSWENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x2000000) >> 25
}
func (o *SDMMC_Type) SetMASKR_ACKTIMEOUTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x1000000)|value<<24)
}
func (o *SDMMC_Type) GetMASKR_ACKTIMEOUTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x1000000) >> 24
}
func (o *SDMMC_Type) SetMASKR_ACKFAILIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x800000)|value<<23)
}
func (o *SDMMC_Type) GetMASKR_ACKFAILIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x800000) >> 23
}
func (o *SDMMC_Type) SetMASKR_SDIOITIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x400000)|value<<22)
}
func (o *SDMMC_Type) GetMASKR_SDIOITIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x400000) >> 22
}
func (o *SDMMC_Type) SetMASKR_BUSYD0ENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x200000)|value<<21)
}
func (o *SDMMC_Type) GetMASKR_BUSYD0ENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x200000) >> 21
}
func (o *SDMMC_Type) SetMASKR_TXFIFOEIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x40000)|value<<18)
}
func (o *SDMMC_Type) GetMASKR_TXFIFOEIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x40000) >> 18
}
func (o *SDMMC_Type) SetMASKR_RXFIFOFIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x20000)|value<<17)
}
func (o *SDMMC_Type) GetMASKR_RXFIFOFIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x20000) >> 17
}
func (o *SDMMC_Type) SetMASKR_RXFIFOHFIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x8000)|value<<15)
}
func (o *SDMMC_Type) GetMASKR_RXFIFOHFIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x8000) >> 15
}
func (o *SDMMC_Type) SetMASKR_TXFIFOHEIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x4000)|value<<14)
}
func (o *SDMMC_Type) GetMASKR_TXFIFOHEIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x4000) >> 14
}
func (o *SDMMC_Type) SetMASKR_DABORTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetMASKR_DABORTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetMASKR_DBCKENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetMASKR_DBCKENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetMASKR_DHOLDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetMASKR_DHOLDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetMASKR_DATAENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetMASKR_DATAENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetMASKR_CMDSENTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetMASKR_CMDSENTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetMASKR_CMDRENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetMASKR_CMDRENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetMASKR_RXOVERRIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x20)|value<<5)
}
func (o *SDMMC_Type) GetMASKR_RXOVERRIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x20) >> 5
}
func (o *SDMMC_Type) SetMASKR_TXUNDERRIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetMASKR_TXUNDERRIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x10) >> 4
}
func (o *SDMMC_Type) SetMASKR_DTIMEOUTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetMASKR_DTIMEOUTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetMASKR_CTIMEOUTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetMASKR_CTIMEOUTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetMASKR_DCRCFAILIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetMASKR_DCRCFAILIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetMASKR_CCRCFAILIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetMASKR_CCRCFAILIE() uint32 {
	return volatile.LoadUint32(&o.MASKR.Reg) & 0x1
}

// SDMMC.ACKTIMER: acknowledgment timer register
func (o *SDMMC_Type) SetACKTIMER_ACKTIME(value uint32) {
	volatile.StoreUint32(&o.ACKTIMER.Reg, volatile.LoadUint32(&o.ACKTIMER.Reg)&^(0x1ffffff)|value)
}
func (o *SDMMC_Type) GetACKTIMER_ACKTIME() uint32 {
	return volatile.LoadUint32(&o.ACKTIMER.Reg) & 0x1ffffff
}

// SDMMC.IDMACTRLR: DMA control register
func (o *SDMMC_Type) SetIDMACTRLR_IDMAEN(value uint32) {
	volatile.StoreUint32(&o.IDMACTRLR.Reg, volatile.LoadUint32(&o.IDMACTRLR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetIDMACTRLR_IDMAEN() uint32 {
	return volatile.LoadUint32(&o.IDMACTRLR.Reg) & 0x1
}
func (o *SDMMC_Type) SetIDMACTRLR_IDMABMODE(value uint32) {
	volatile.StoreUint32(&o.IDMACTRLR.Reg, volatile.LoadUint32(&o.IDMACTRLR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetIDMACTRLR_IDMABMODE() uint32 {
	return (volatile.LoadUint32(&o.IDMACTRLR.Reg) & 0x2) >> 1
}

// SDMMC.IDMABSIZER: buffer size register
func (o *SDMMC_Type) SetIDMABSIZER_IDMABNDT(value uint32) {
	volatile.StoreUint32(&o.IDMABSIZER.Reg, volatile.LoadUint32(&o.IDMABSIZER.Reg)&^(0x1ffe0)|value<<5)
}
func (o *SDMMC_Type) GetIDMABSIZER_IDMABNDT() uint32 {
	return (volatile.LoadUint32(&o.IDMABSIZER.Reg) & 0x1ffe0) >> 5
}

// SDMMC.IDMABASER: buffer base address register
func (o *SDMMC_Type) SetIDMABASER(value uint32) {
	volatile.StoreUint32(&o.IDMABASER.Reg, value)
}
func (o *SDMMC_Type) GetIDMABASER() uint32 {
	return volatile.LoadUint32(&o.IDMABASER.Reg)
}

// SDMMC.IDMALAR: linked list address register
func (o *SDMMC_Type) SetIDMALAR_ULA(value uint32) {
	volatile.StoreUint32(&o.IDMALAR.Reg, volatile.LoadUint32(&o.IDMALAR.Reg)&^(0x80000000)|value<<31)
}
func (o *SDMMC_Type) GetIDMALAR_ULA() uint32 {
	return (volatile.LoadUint32(&o.IDMALAR.Reg) & 0x80000000) >> 31
}
func (o *SDMMC_Type) SetIDMALAR_ULS(value uint32) {
	volatile.StoreUint32(&o.IDMALAR.Reg, volatile.LoadUint32(&o.IDMALAR.Reg)&^(0x40000000)|value<<30)
}
func (o *SDMMC_Type) GetIDMALAR_ULS() uint32 {
	return (volatile.LoadUint32(&o.IDMALAR.Reg) & 0x40000000) >> 30
}
func (o *SDMMC_Type) SetIDMALAR_ABR(value uint32) {
	volatile.StoreUint32(&o.IDMALAR.Reg, volatile.LoadUint32(&o.IDMALAR.Reg)&^(0x20000000)|value<<29)
}
func (o *SDMMC_Type) GetIDMALAR_ABR() uint32 {
	return (volatile.LoadUint32(&o.IDMALAR.Reg) & 0x20000000) >> 29
}
func (o *SDMMC_Type) SetIDMALAR_IDMALA(value uint32) {
	volatile.StoreUint32(&o.IDMALAR.Reg, volatile.LoadUint32(&o.IDMALAR.Reg)&^(0xfffc)|value<<2)
}
func (o *SDMMC_Type) GetIDMALAR_IDMALA() uint32 {
	return (volatile.LoadUint32(&o.IDMALAR.Reg) & 0xfffc) >> 2
}

// SDMMC.IDMABAR: linked list memory base register
func (o *SDMMC_Type) SetIDMABAR_IDMABA(value uint32) {
	volatile.StoreUint32(&o.IDMABAR.Reg, volatile.LoadUint32(&o.IDMABAR.Reg)&^(0xfffffffc)|value<<2)
}
func (o *SDMMC_Type) GetIDMABAR_IDMABA() uint32 {
	return (volatile.LoadUint32(&o.IDMABAR.Reg) & 0xfffffffc) >> 2
}

// SDMMC.FIFOR0: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR0(value uint32) {
	volatile.StoreUint32(&o.FIFOR0.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR0() uint32 {
	return volatile.LoadUint32(&o.FIFOR0.Reg)
}

// SDMMC.FIFOR1: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR1(value uint32) {
	volatile.StoreUint32(&o.FIFOR1.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR1() uint32 {
	return volatile.LoadUint32(&o.FIFOR1.Reg)
}

// SDMMC.FIFOR2: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR2(value uint32) {
	volatile.StoreUint32(&o.FIFOR2.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR2() uint32 {
	return volatile.LoadUint32(&o.FIFOR2.Reg)
}

// SDMMC.FIFOR3: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR3(value uint32) {
	volatile.StoreUint32(&o.FIFOR3.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR3() uint32 {
	return volatile.LoadUint32(&o.FIFOR3.Reg)
}

// SDMMC.FIFOR4: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR4(value uint32) {
	volatile.StoreUint32(&o.FIFOR4.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR4() uint32 {
	return volatile.LoadUint32(&o.FIFOR4.Reg)
}

// SDMMC.FIFOR5: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR5(value uint32) {
	volatile.StoreUint32(&o.FIFOR5.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR5() uint32 {
	return volatile.LoadUint32(&o.FIFOR5.Reg)
}

// SDMMC.FIFOR6: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR6(value uint32) {
	volatile.StoreUint32(&o.FIFOR6.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR6() uint32 {
	return volatile.LoadUint32(&o.FIFOR6.Reg)
}

// SDMMC.FIFOR7: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR7(value uint32) {
	volatile.StoreUint32(&o.FIFOR7.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR7() uint32 {
	return volatile.LoadUint32(&o.FIFOR7.Reg)
}

// SDMMC.FIFOR8: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR8(value uint32) {
	volatile.StoreUint32(&o.FIFOR8.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR8() uint32 {
	return volatile.LoadUint32(&o.FIFOR8.Reg)
}

// SDMMC.FIFOR9: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR9(value uint32) {
	volatile.StoreUint32(&o.FIFOR9.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR9() uint32 {
	return volatile.LoadUint32(&o.FIFOR9.Reg)
}

// SDMMC.FIFOR10: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR10(value uint32) {
	volatile.StoreUint32(&o.FIFOR10.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR10() uint32 {
	return volatile.LoadUint32(&o.FIFOR10.Reg)
}

// SDMMC.FIFOR11: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR11(value uint32) {
	volatile.StoreUint32(&o.FIFOR11.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR11() uint32 {
	return volatile.LoadUint32(&o.FIFOR11.Reg)
}

// SDMMC.FIFOR12: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR12(value uint32) {
	volatile.StoreUint32(&o.FIFOR12.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR12() uint32 {
	return volatile.LoadUint32(&o.FIFOR12.Reg)
}

// SDMMC.FIFOR13: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR13(value uint32) {
	volatile.StoreUint32(&o.FIFOR13.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR13() uint32 {
	return volatile.LoadUint32(&o.FIFOR13.Reg)
}

// SDMMC.FIFOR14: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR14(value uint32) {
	volatile.StoreUint32(&o.FIFOR14.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR14() uint32 {
	return volatile.LoadUint32(&o.FIFOR14.Reg)
}

// SDMMC.FIFOR15: data FIFO register %s
func (o *SDMMC_Type) SetFIFOR15(value uint32) {
	volatile.StoreUint32(&o.FIFOR15.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR15() uint32 {
	return volatile.LoadUint32(&o.FIFOR15.Reg)
}

// Serial peripheral interface
type SPI_Type struct {
	CR1     volatile.Register32 // 0x0
	CR2     volatile.Register32 // 0x4
	CFG1    volatile.Register32 // 0x8
	CFG2    volatile.Register32 // 0xC
	IER     volatile.Register32 // 0x10
	SR      volatile.Register32 // 0x14
	IFCR    volatile.Register32 // 0x18
	AUTOCR  volatile.Register32 // 0x1C
	TXDR    volatile.Register32 // 0x20
	_       [12]byte
	RXDR    volatile.Register32 // 0x30
	_       [12]byte
	CRCPOLY volatile.Register32 // 0x40
	TXCRC   volatile.Register32 // 0x44
	RXCRC   volatile.Register32 // 0x48
	UDRDR   volatile.Register32 // 0x4C
}

// SPI.CR1: control register 1
func (o *SPI_Type) SetCR1_IOLOCK(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *SPI_Type) GetCR1_IOLOCK() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *SPI_Type) SetCR1_TCRCINI(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *SPI_Type) GetCR1_TCRCINI() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *SPI_Type) SetCR1_RCRCINI(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCR1_RCRCINI() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *SPI_Type) SetCR1_CRC33_17(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCR1_CRC33_17() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCR1_SSI(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetCR1_SSI() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetCR1_HDDIR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetCR1_HDDIR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetCR1_CSUSP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetCR1_CSUSP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *SPI_Type) SetCR1_CSTART(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetCR1_CSTART() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetCR1_MASRX(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetCR1_MASRX() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetCR1_SPE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR1_SPE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}

// SPI.CR2: control register 2
func (o *SPI_Type) SetCR2_TSIZE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xffff)|value)
}
func (o *SPI_Type) GetCR2_TSIZE() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0xffff
}

// SPI.CFG1: configuration register 1
func (o *SPI_Type) SetCFG1_BPASS(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI_Type) GetCFG1_BPASS() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x80000000) >> 31
}
func (o *SPI_Type) SetCFG1_MBR(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x70000000)|value<<28)
}
func (o *SPI_Type) GetCFG1_MBR() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x70000000) >> 28
}
func (o *SPI_Type) SetCFG1_CRCEN(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x400000)|value<<22)
}
func (o *SPI_Type) GetCFG1_CRCEN() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x400000) >> 22
}
func (o *SPI_Type) SetCFG1_CRCSIZE(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x1f0000)|value<<16)
}
func (o *SPI_Type) GetCFG1_CRCSIZE() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x1f0000) >> 16
}
func (o *SPI_Type) SetCFG1_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x8000)|value<<15)
}
func (o *SPI_Type) GetCFG1_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x8000) >> 15
}
func (o *SPI_Type) SetCFG1_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCFG1_RXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x4000) >> 14
}
func (o *SPI_Type) SetCFG1_UDRCFG(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetCFG1_UDRCFG() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetCFG1_FTHLV(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x1e0)|value<<5)
}
func (o *SPI_Type) GetCFG1_FTHLV() uint32 {
	return (volatile.LoadUint32(&o.CFG1.Reg) & 0x1e0) >> 5
}
func (o *SPI_Type) SetCFG1_DSIZE(value uint32) {
	volatile.StoreUint32(&o.CFG1.Reg, volatile.LoadUint32(&o.CFG1.Reg)&^(0x1f)|value)
}
func (o *SPI_Type) GetCFG1_DSIZE() uint32 {
	return volatile.LoadUint32(&o.CFG1.Reg) & 0x1f
}

// SPI.CFG2: configuration register 2
func (o *SPI_Type) SetCFG2_AFCNTR(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x80000000)|value<<31)
}
func (o *SPI_Type) GetCFG2_AFCNTR() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x80000000) >> 31
}
func (o *SPI_Type) SetCFG2_SSOM(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x40000000)|value<<30)
}
func (o *SPI_Type) GetCFG2_SSOM() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x40000000) >> 30
}
func (o *SPI_Type) SetCFG2_SSOE(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x20000000)|value<<29)
}
func (o *SPI_Type) GetCFG2_SSOE() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x20000000) >> 29
}
func (o *SPI_Type) SetCFG2_SSIOP(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x10000000)|value<<28)
}
func (o *SPI_Type) GetCFG2_SSIOP() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x10000000) >> 28
}
func (o *SPI_Type) SetCFG2_SSM(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x4000000)|value<<26)
}
func (o *SPI_Type) GetCFG2_SSM() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x4000000) >> 26
}
func (o *SPI_Type) SetCFG2_CPOL(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x2000000)|value<<25)
}
func (o *SPI_Type) GetCFG2_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x2000000) >> 25
}
func (o *SPI_Type) SetCFG2_CPHA(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x1000000)|value<<24)
}
func (o *SPI_Type) GetCFG2_CPHA() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x1000000) >> 24
}
func (o *SPI_Type) SetCFG2_LSBFRST(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x800000)|value<<23)
}
func (o *SPI_Type) GetCFG2_LSBFRST() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x800000) >> 23
}
func (o *SPI_Type) SetCFG2_MASTER(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x400000)|value<<22)
}
func (o *SPI_Type) GetCFG2_MASTER() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x400000) >> 22
}
func (o *SPI_Type) SetCFG2_SP(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x380000)|value<<19)
}
func (o *SPI_Type) GetCFG2_SP() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x380000) >> 19
}
func (o *SPI_Type) SetCFG2_COMM(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x60000)|value<<17)
}
func (o *SPI_Type) GetCFG2_COMM() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x60000) >> 17
}
func (o *SPI_Type) SetCFG2_IOSWP(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x8000)|value<<15)
}
func (o *SPI_Type) GetCFG2_IOSWP() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x8000) >> 15
}
func (o *SPI_Type) SetCFG2_RDIOP(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCFG2_RDIOP() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x4000) >> 14
}
func (o *SPI_Type) SetCFG2_RDIOM(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCFG2_RDIOM() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCFG2_MIDI(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0xf0)|value<<4)
}
func (o *SPI_Type) GetCFG2_MIDI() uint32 {
	return (volatile.LoadUint32(&o.CFG2.Reg) & 0xf0) >> 4
}
func (o *SPI_Type) SetCFG2_MSSI(value uint32) {
	volatile.StoreUint32(&o.CFG2.Reg, volatile.LoadUint32(&o.CFG2.Reg)&^(0xf)|value)
}
func (o *SPI_Type) GetCFG2_MSSI() uint32 {
	return volatile.LoadUint32(&o.CFG2.Reg) & 0xf
}

// SPI.IER: Interrupt Enable Register
func (o *SPI_Type) SetIER_RXPIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetIER_RXPIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *SPI_Type) SetIER_MODFIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetIER_MODFIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetIER_TIFREIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetIER_TIFREIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetIER_CRCEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetIER_CRCEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetIER_OVRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetIER_OVRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetIER_UDRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetIER_UDRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetIER_TXTFIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetIER_TXTFIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetIER_EOTIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetIER_EOTIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetIER_DXPIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetIER_DXPIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetIER_TXPIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetIER_TXPIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}

// SPI.SR: Status Register
func (o *SPI_Type) SetSR_CTSIZE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xffff0000)|value<<16)
}
func (o *SPI_Type) GetSR_CTSIZE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0xffff0000) >> 16
}
func (o *SPI_Type) SetSR_RXWNE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000)|value<<15)
}
func (o *SPI_Type) GetSR_RXWNE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000) >> 15
}
func (o *SPI_Type) SetSR_RXPLVL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x6000)|value<<13)
}
func (o *SPI_Type) GetSR_RXPLVL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x6000) >> 13
}
func (o *SPI_Type) SetSR_TXC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetSR_TXC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetSR_SUSP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetSR_SUSP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetSR_MODF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetSR_MODF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetSR_TIFRE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetSR_TIFRE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetSR_CRCE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetSR_CRCE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetSR_OVR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetSR_OVR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetSR_UDR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetSR_UDR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetSR_TXTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetSR_TXTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetSR_EOT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetSR_EOT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetSR_DXP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetSR_DXP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetSR_TXP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetSR_TXP() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetSR_RXP(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetSR_RXP() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// SPI.IFCR: Interrupt/Status Flags Clear Register
func (o *SPI_Type) SetIFCR_EOTC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetIFCR_EOTC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetIFCR_SUSPC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetIFCR_SUSPC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetIFCR_MODFC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetIFCR_MODFC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetIFCR_TIFREC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetIFCR_TIFREC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetIFCR_CRCEC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetIFCR_CRCEC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetIFCR_OVRC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetIFCR_OVRC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetIFCR_UDRC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetIFCR_UDRC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetIFCR_TXTFC(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetIFCR_TXTFC() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10) >> 4
}

// SPI.AUTOCR: SPI autonomous mode control register
func (o *SPI_Type) SetAUTOCR_TRIGEN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x200000)|value<<21)
}
func (o *SPI_Type) GetAUTOCR_TRIGEN() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x200000) >> 21
}
func (o *SPI_Type) SetAUTOCR_TRIGPOL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x100000)|value<<20)
}
func (o *SPI_Type) GetAUTOCR_TRIGPOL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x100000) >> 20
}
func (o *SPI_Type) SetAUTOCR_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0xf0000)|value<<16)
}
func (o *SPI_Type) GetAUTOCR_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0xf0000) >> 16
}

// SPI.TXDR: Transmit Data Register
func (o *SPI_Type) SetTXDR(value uint32) {
	volatile.StoreUint32(&o.TXDR.Reg, value)
}
func (o *SPI_Type) GetTXDR() uint32 {
	return volatile.LoadUint32(&o.TXDR.Reg)
}

// SPI.RXDR: Receive Data Register
func (o *SPI_Type) SetRXDR(value uint32) {
	volatile.StoreUint32(&o.RXDR.Reg, value)
}
func (o *SPI_Type) GetRXDR() uint32 {
	return volatile.LoadUint32(&o.RXDR.Reg)
}

// SPI.CRCPOLY: Polynomial Register
func (o *SPI_Type) SetCRCPOLY(value uint32) {
	volatile.StoreUint32(&o.CRCPOLY.Reg, value)
}
func (o *SPI_Type) GetCRCPOLY() uint32 {
	return volatile.LoadUint32(&o.CRCPOLY.Reg)
}

// SPI.TXCRC: Transmitter CRC Register
func (o *SPI_Type) SetTXCRC(value uint32) {
	volatile.StoreUint32(&o.TXCRC.Reg, value)
}
func (o *SPI_Type) GetTXCRC() uint32 {
	return volatile.LoadUint32(&o.TXCRC.Reg)
}

// SPI.RXCRC: Receiver CRC Register
func (o *SPI_Type) SetRXCRC(value uint32) {
	volatile.StoreUint32(&o.RXCRC.Reg, value)
}
func (o *SPI_Type) GetRXCRC() uint32 {
	return volatile.LoadUint32(&o.RXCRC.Reg)
}

// SPI.UDRDR: Underrun Data Register
func (o *SPI_Type) SetUDRDR(value uint32) {
	volatile.StoreUint32(&o.UDRDR.Reg, value)
}
func (o *SPI_Type) GetUDRDR() uint32 {
	return volatile.LoadUint32(&o.UDRDR.Reg)
}

// System configuration controller
type SYSCFG_Type struct {
	SECCFGR    volatile.Register32 // 0x0
	CFGR1      volatile.Register32 // 0x4
	FPUIMR     volatile.Register32 // 0x8
	CNSLCKR    volatile.Register32 // 0xC
	CSLOCKR    volatile.Register32 // 0x10
	CFGR2      volatile.Register32 // 0x14
	MESR       volatile.Register32 // 0x18
	CCCSR      volatile.Register32 // 0x1C
	CCVR       volatile.Register32 // 0x20
	CCCR       volatile.Register32 // 0x24
	_          [4]byte
	RSSCMDR    volatile.Register32 // 0x2C
	_          [68]byte
	OTGHSPHYCR volatile.Register32 // 0x74
}

// SYSCFG.SECCFGR: SYSCFG secure configuration register
func (o *SYSCFG_Type) SetSECCFGR_SYSCFGSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetSECCFGR_SYSCFGSEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetSECCFGR_CLASSBSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetSECCFGR_CLASSBSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetSECCFGR_FPUSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetSECCFGR_FPUSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}

// SYSCFG.CFGR1: configuration register 1
func (o *SYSCFG_Type) SetCFGR1_ENDCAP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3000000)|value<<24)
}
func (o *SYSCFG_Type) GetCFGR1_ENDCAP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x3000000) >> 24
}
func (o *SYSCFG_Type) SetCFGR1_PB9_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x80000)|value<<19)
}
func (o *SYSCFG_Type) GetCFGR1_PB9_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x80000) >> 19
}
func (o *SYSCFG_Type) SetCFGR1_PB8_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x40000)|value<<18)
}
func (o *SYSCFG_Type) GetCFGR1_PB8_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x40000) >> 18
}
func (o *SYSCFG_Type) SetCFGR1_PB7_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20000)|value<<17)
}
func (o *SYSCFG_Type) GetCFGR1_PB7_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20000) >> 17
}
func (o *SYSCFG_Type) SetCFGR1_PB6_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *SYSCFG_Type) GetCFGR1_PB6_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10000) >> 16
}
func (o *SYSCFG_Type) SetCFGR1_ANASWVDD(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200)|value<<9)
}
func (o *SYSCFG_Type) GetCFGR1_ANASWVDD() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200) >> 9
}
func (o *SYSCFG_Type) SetCFGR1_BOOSTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetCFGR1_BOOSTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100) >> 8
}

// SYSCFG.FPUIMR: FPU interrupt mask register
func (o *SYSCFG_Type) SetFPUIMR_FPU_IE(value uint32) {
	volatile.StoreUint32(&o.FPUIMR.Reg, volatile.LoadUint32(&o.FPUIMR.Reg)&^(0x3f)|value)
}
func (o *SYSCFG_Type) GetFPUIMR_FPU_IE() uint32 {
	return volatile.LoadUint32(&o.FPUIMR.Reg) & 0x3f
}

// SYSCFG.CNSLCKR: SYSCFG CPU non-secure lock register
func (o *SYSCFG_Type) SetCNSLCKR_LOCKNSVTOR(value uint32) {
	volatile.StoreUint32(&o.CNSLCKR.Reg, volatile.LoadUint32(&o.CNSLCKR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCNSLCKR_LOCKNSVTOR() uint32 {
	return volatile.LoadUint32(&o.CNSLCKR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetCNSLCKR_LOCKNSMPU(value uint32) {
	volatile.StoreUint32(&o.CNSLCKR.Reg, volatile.LoadUint32(&o.CNSLCKR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCNSLCKR_LOCKNSMPU() uint32 {
	return (volatile.LoadUint32(&o.CNSLCKR.Reg) & 0x2) >> 1
}

// SYSCFG.CSLOCKR: SYSCFG CPU secure lock register
func (o *SYSCFG_Type) SetCSLOCKR_LOCKSVTAIRCR(value uint32) {
	volatile.StoreUint32(&o.CSLOCKR.Reg, volatile.LoadUint32(&o.CSLOCKR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCSLOCKR_LOCKSVTAIRCR() uint32 {
	return volatile.LoadUint32(&o.CSLOCKR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetCSLOCKR_LOCKSMPU(value uint32) {
	volatile.StoreUint32(&o.CSLOCKR.Reg, volatile.LoadUint32(&o.CSLOCKR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCSLOCKR_LOCKSMPU() uint32 {
	return (volatile.LoadUint32(&o.CSLOCKR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetCSLOCKR_LOCKSAU(value uint32) {
	volatile.StoreUint32(&o.CSLOCKR.Reg, volatile.LoadUint32(&o.CSLOCKR.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetCSLOCKR_LOCKSAU() uint32 {
	return (volatile.LoadUint32(&o.CSLOCKR.Reg) & 0x4) >> 2
}

// SYSCFG.CFGR2: configuration register 2
func (o *SYSCFG_Type) SetCFGR2_ECCL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetCFGR2_ECCL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetCFGR2_PVDL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetCFGR2_PVDL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetCFGR2_SPL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCFGR2_SPL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetCFGR2_CLL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCFGR2_CLL() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}

// SYSCFG.MESR: memory erase status register
func (o *SYSCFG_Type) SetMESR_IPMEE(value uint32) {
	volatile.StoreUint32(&o.MESR.Reg, volatile.LoadUint32(&o.MESR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSCFG_Type) GetMESR_IPMEE() uint32 {
	return (volatile.LoadUint32(&o.MESR.Reg) & 0x10000) >> 16
}
func (o *SYSCFG_Type) SetMESR_MCLR(value uint32) {
	volatile.StoreUint32(&o.MESR.Reg, volatile.LoadUint32(&o.MESR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetMESR_MCLR() uint32 {
	return volatile.LoadUint32(&o.MESR.Reg) & 0x1
}

// SYSCFG.CCCSR: compensation cell control/status register
func (o *SYSCFG_Type) SetCCCSR_EN1(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCCCSR_EN1() uint32 {
	return volatile.LoadUint32(&o.CCCSR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetCCCSR_CS1(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCCCSR_CS1() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetCCCSR_EN2(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetCCCSR_EN2() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetCCCSR_CS2(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetCCCSR_CS2() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetCCCSR_EN3(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x10)|value<<4)
}
func (o *SYSCFG_Type) GetCCCSR_EN3() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x10) >> 4
}
func (o *SYSCFG_Type) SetCCCSR_CS3(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x20)|value<<5)
}
func (o *SYSCFG_Type) GetCCCSR_CS3() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x20) >> 5
}
func (o *SYSCFG_Type) SetCCCSR_RDY1(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetCCCSR_RDY1() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x100) >> 8
}
func (o *SYSCFG_Type) SetCCCSR_RDY2(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x200)|value<<9)
}
func (o *SYSCFG_Type) GetCCCSR_RDY2() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x200) >> 9
}
func (o *SYSCFG_Type) SetCCCSR_RDY3(value uint32) {
	volatile.StoreUint32(&o.CCCSR.Reg, volatile.LoadUint32(&o.CCCSR.Reg)&^(0x400)|value<<10)
}
func (o *SYSCFG_Type) GetCCCSR_RDY3() uint32 {
	return (volatile.LoadUint32(&o.CCCSR.Reg) & 0x400) >> 10
}

// SYSCFG.CCVR: compensation cell value register
func (o *SYSCFG_Type) SetCCVR_NCV1(value uint32) {
	volatile.StoreUint32(&o.CCVR.Reg, volatile.LoadUint32(&o.CCVR.Reg)&^(0xf)|value)
}
func (o *SYSCFG_Type) GetCCVR_NCV1() uint32 {
	return volatile.LoadUint32(&o.CCVR.Reg) & 0xf
}
func (o *SYSCFG_Type) SetCCVR_PCV1(value uint32) {
	volatile.StoreUint32(&o.CCVR.Reg, volatile.LoadUint32(&o.CCVR.Reg)&^(0xf0)|value<<4)
}
func (o *SYSCFG_Type) GetCCVR_PCV1() uint32 {
	return (volatile.LoadUint32(&o.CCVR.Reg) & 0xf0) >> 4
}
func (o *SYSCFG_Type) SetCCVR_NCV2(value uint32) {
	volatile.StoreUint32(&o.CCVR.Reg, volatile.LoadUint32(&o.CCVR.Reg)&^(0xf00)|value<<8)
}
func (o *SYSCFG_Type) GetCCVR_NCV2() uint32 {
	return (volatile.LoadUint32(&o.CCVR.Reg) & 0xf00) >> 8
}
func (o *SYSCFG_Type) SetCCVR_PCV2(value uint32) {
	volatile.StoreUint32(&o.CCVR.Reg, volatile.LoadUint32(&o.CCVR.Reg)&^(0xf000)|value<<12)
}
func (o *SYSCFG_Type) GetCCVR_PCV2() uint32 {
	return (volatile.LoadUint32(&o.CCVR.Reg) & 0xf000) >> 12
}
func (o *SYSCFG_Type) SetCCVR_NCV3(value uint32) {
	volatile.StoreUint32(&o.CCVR.Reg, volatile.LoadUint32(&o.CCVR.Reg)&^(0xf0000)|value<<16)
}
func (o *SYSCFG_Type) GetCCVR_NCV3() uint32 {
	return (volatile.LoadUint32(&o.CCVR.Reg) & 0xf0000) >> 16
}
func (o *SYSCFG_Type) SetCCVR_PCV3(value uint32) {
	volatile.StoreUint32(&o.CCVR.Reg, volatile.LoadUint32(&o.CCVR.Reg)&^(0xf00000)|value<<20)
}
func (o *SYSCFG_Type) GetCCVR_PCV3() uint32 {
	return (volatile.LoadUint32(&o.CCVR.Reg) & 0xf00000) >> 20
}

// SYSCFG.CCCR: compensation cell code register
func (o *SYSCFG_Type) SetCCCR_NCC1(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0xf)|value)
}
func (o *SYSCFG_Type) GetCCCR_NCC1() uint32 {
	return volatile.LoadUint32(&o.CCCR.Reg) & 0xf
}
func (o *SYSCFG_Type) SetCCCR_PCC1(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0xf0)|value<<4)
}
func (o *SYSCFG_Type) GetCCCR_PCC1() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0xf0) >> 4
}
func (o *SYSCFG_Type) SetCCCR_NCC2(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0xf00)|value<<8)
}
func (o *SYSCFG_Type) GetCCCR_NCC2() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0xf00) >> 8
}
func (o *SYSCFG_Type) SetCCCR_PCC2(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0xf000)|value<<12)
}
func (o *SYSCFG_Type) GetCCCR_PCC2() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0xf000) >> 12
}
func (o *SYSCFG_Type) SetCCCR_NCC3(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0xf0000)|value<<16)
}
func (o *SYSCFG_Type) GetCCCR_NCC3() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0xf0000) >> 16
}
func (o *SYSCFG_Type) SetCCCR_PCC3(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0xf00000)|value<<20)
}
func (o *SYSCFG_Type) GetCCCR_PCC3() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0xf00000) >> 20
}

// SYSCFG.RSSCMDR: RSS command register
func (o *SYSCFG_Type) SetRSSCMDR_RSSCMD(value uint32) {
	volatile.StoreUint32(&o.RSSCMDR.Reg, volatile.LoadUint32(&o.RSSCMDR.Reg)&^(0xffff)|value)
}
func (o *SYSCFG_Type) GetRSSCMDR_RSSCMD() uint32 {
	return volatile.LoadUint32(&o.RSSCMDR.Reg) & 0xffff
}

// SYSCFG.OTGHSPHYCR: SYSCFG USB OTG_HS PHY register
func (o *SYSCFG_Type) SetOTGHSPHYCR_EN(value uint32) {
	volatile.StoreUint32(&o.OTGHSPHYCR.Reg, volatile.LoadUint32(&o.OTGHSPHYCR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetOTGHSPHYCR_EN() uint32 {
	return volatile.LoadUint32(&o.OTGHSPHYCR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetOTGHSPHYCR_PDCTRL(value uint32) {
	volatile.StoreUint32(&o.OTGHSPHYCR.Reg, volatile.LoadUint32(&o.OTGHSPHYCR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetOTGHSPHYCR_PDCTRL() uint32 {
	return (volatile.LoadUint32(&o.OTGHSPHYCR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetOTGHSPHYCR_CLKSEL(value uint32) {
	volatile.StoreUint32(&o.OTGHSPHYCR.Reg, volatile.LoadUint32(&o.OTGHSPHYCR.Reg)&^(0x3c)|value<<2)
}
func (o *SYSCFG_Type) GetOTGHSPHYCR_CLKSEL() uint32 {
	return (volatile.LoadUint32(&o.OTGHSPHYCR.Reg) & 0x3c) >> 2
}

// Tamper and backup registers
type TAMP_Type struct {
	CR1     volatile.Register32 // 0x0
	CR2     volatile.Register32 // 0x4
	CR3     volatile.Register32 // 0x8
	FLTCR   volatile.Register32 // 0xC
	ATCR1   volatile.Register32 // 0x10
	ATSEEDR volatile.Register32 // 0x14
	ATOR    volatile.Register32 // 0x18
	ATCR2   volatile.Register32 // 0x1C
	SECCFGR volatile.Register32 // 0x20
	PRIVCR  volatile.Register32 // 0x24
	_       [4]byte
	IER     volatile.Register32 // 0x2C
	SR      volatile.Register32 // 0x30
	MISR    volatile.Register32 // 0x34
	SMISR   volatile.Register32 // 0x38
	SCR     volatile.Register32 // 0x3C
	COUNT1R volatile.Register32 // 0x40
	_       [16]byte
	ERCFGR  volatile.Register32 // 0x54
	_       [168]byte
	BKP0R   volatile.Register32 // 0x100
	BKP1R   volatile.Register32 // 0x104
	BKP2R   volatile.Register32 // 0x108
	BKP3R   volatile.Register32 // 0x10C
	BKP4R   volatile.Register32 // 0x110
	BKP5R   volatile.Register32 // 0x114
	BKP6R   volatile.Register32 // 0x118
	BKP7R   volatile.Register32 // 0x11C
	BKP8R   volatile.Register32 // 0x120
	BKP9R   volatile.Register32 // 0x124
	BKP10R  volatile.Register32 // 0x128
	BKP11R  volatile.Register32 // 0x12C
	BKP12R  volatile.Register32 // 0x130
	BKP13R  volatile.Register32 // 0x134
	BKP14R  volatile.Register32 // 0x138
	BKP15R  volatile.Register32 // 0x13C
	BKP16R  volatile.Register32 // 0x140
	BKP17R  volatile.Register32 // 0x144
	BKP18R  volatile.Register32 // 0x148
	BKP19R  volatile.Register32 // 0x14C
	BKP20R  volatile.Register32 // 0x150
	BKP21R  volatile.Register32 // 0x154
	BKP22R  volatile.Register32 // 0x158
	BKP23R  volatile.Register32 // 0x15C
	BKP24R  volatile.Register32 // 0x160
	BKP25R  volatile.Register32 // 0x164
	BKP26R  volatile.Register32 // 0x168
	BKP27R  volatile.Register32 // 0x16C
	BKP28R  volatile.Register32 // 0x170
	BKP29R  volatile.Register32 // 0x174
	BKP30R  volatile.Register32 // 0x178
	BKP31R  volatile.Register32 // 0x17C
}

// TAMP.CR1: control register 1
func (o *TAMP_Type) SetCR1_ITAMP13E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetCR1_ITAMP13E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000000) >> 28
}
func (o *TAMP_Type) SetCR1_ITAMP12E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetCR1_ITAMP12E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetCR1_ITAMP11E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetCR1_ITAMP11E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetCR1_ITAMP9E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetCR1_ITAMP9E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetCR1_ITAMP8E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetCR1_ITAMP8E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetCR1_ITAMP7E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400000)|value<<22)
}
func (o *TAMP_Type) GetCR1_ITAMP7E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400000) >> 22
}
func (o *TAMP_Type) SetCR1_ITAMP6E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetCR1_ITAMP6E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200000) >> 21
}
func (o *TAMP_Type) SetCR1_ITAMP5E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetCR1_ITAMP5E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetCR1_ITAMP3E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetCR1_ITAMP3E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetCR1_ITAMP2E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetCR1_ITAMP2E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetCR1_ITAMP1E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetCR1_ITAMP1E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetCR1_TAMP8E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetCR1_TAMP8E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetCR1_TAMP7E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetCR1_TAMP7E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetCR1_TAMP6E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetCR1_TAMP6E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetCR1_TAMP5E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetCR1_TAMP5E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetCR1_TAMP4E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetCR1_TAMP4E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetCR1_TAMP3E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR1_TAMP3E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR1_TAMP2E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR1_TAMP2E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR1_TAMP1E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR1_TAMP1E() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}

// TAMP.CR2: control register 2
func (o *TAMP_Type) SetCR2_TAMP1NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR2_TAMP1NOER() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *TAMP_Type) SetCR2_TAMP2NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR2_TAMP2NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR2_TAMP3NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR2_TAMP3NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR2_TAMP4NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetCR2_TAMP4NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetCR2_TAMP5NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetCR2_TAMP5NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetCR2_TAMP6NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetCR2_TAMP6NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetCR2_TAMP7NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetCR2_TAMP7NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetCR2_TAMP8NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetCR2_TAMP8NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetCR2_TAMP1MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetCR2_TAMP1MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetCR2_TAMP2MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetCR2_TAMP2MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetCR2_TAMP3MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetCR2_TAMP3MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetCR2_BKBLOCK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400000)|value<<22)
}
func (o *TAMP_Type) GetCR2_BKBLOCK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400000) >> 22
}
func (o *TAMP_Type) SetCR2_BKERASE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetCR2_BKERASE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetCR2_TAMP1TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetCR2_TAMP1TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetCR2_TAMP2TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *TAMP_Type) GetCR2_TAMP2TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *TAMP_Type) SetCR2_TAMP3TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetCR2_TAMP3TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetCR2_TAMP4TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetCR2_TAMP4TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetCR2_TAMP5TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetCR2_TAMP5TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000000) >> 28
}
func (o *TAMP_Type) SetCR2_TAMP6TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000000)|value<<29)
}
func (o *TAMP_Type) GetCR2_TAMP6TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000000) >> 29
}
func (o *TAMP_Type) SetCR2_TAMP7TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000000)|value<<30)
}
func (o *TAMP_Type) GetCR2_TAMP7TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000000) >> 30
}
func (o *TAMP_Type) SetCR2_TAMP8TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetCR2_TAMP8TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000000) >> 31
}

// TAMP.CR3: control register 3
func (o *TAMP_Type) SetCR3_ITAMP1NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR3_ITAMP1NOER() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *TAMP_Type) SetCR3_ITAMP2NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR3_ITAMP2NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR3_ITAMP3NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR3_ITAMP3NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR3_TAMP5NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetCR3_TAMP5NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetCR3_TAMP6NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetCR3_TAMP6NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetCR3_TAMP7NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetCR3_TAMP7NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetCR3_TAMP8NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetCR3_TAMP8NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetCR3_ITAMP9NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *TAMP_Type) GetCR3_ITAMP9NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *TAMP_Type) SetCR3_ITAMP11NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *TAMP_Type) GetCR3_ITAMP11NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *TAMP_Type) SetCR3_ITAMP12NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800)|value<<11)
}
func (o *TAMP_Type) GetCR3_ITAMP12NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800) >> 11
}
func (o *TAMP_Type) SetCR3_ITAMP13NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *TAMP_Type) GetCR3_ITAMP13NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}

// TAMP.FLTCR: TAMP filter control register
func (o *TAMP_Type) SetFLTCR_TAMPFREQ(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x7)|value)
}
func (o *TAMP_Type) GetFLTCR_TAMPFREQ() uint32 {
	return volatile.LoadUint32(&o.FLTCR.Reg) & 0x7
}
func (o *TAMP_Type) SetFLTCR_TAMPFLT(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x18)|value<<3)
}
func (o *TAMP_Type) GetFLTCR_TAMPFLT() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x18) >> 3
}
func (o *TAMP_Type) SetFLTCR_TAMPPRCH(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x60)|value<<5)
}
func (o *TAMP_Type) GetFLTCR_TAMPPRCH() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x60) >> 5
}
func (o *TAMP_Type) SetFLTCR_TAMPPUDIS(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetFLTCR_TAMPPUDIS() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x80) >> 7
}

// TAMP.ATCR1: TAMP active tamper control register
func (o *TAMP_Type) SetATCR1_TAMP1AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetATCR1_TAMP1AM() uint32 {
	return volatile.LoadUint32(&o.ATCR1.Reg) & 0x1
}
func (o *TAMP_Type) SetATCR1_TAMP2AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetATCR1_TAMP2AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetATCR1_TAMP3AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetATCR1_TAMP3AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetATCR1_TAMP4AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetATCR1_TAMP4AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetATCR1_TAMP5AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetATCR1_TAMP5AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetATCR1_TAMP6AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetATCR1_TAMP6AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetATCR1_TAMP7AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetATCR1_TAMP7AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetATCR1_TAMP8AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetATCR1_TAMP8AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetATCR1_ATOSEL1(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x300)|value<<8)
}
func (o *TAMP_Type) GetATCR1_ATOSEL1() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x300) >> 8
}
func (o *TAMP_Type) SetATCR1_ATOSEL2(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0xc00)|value<<10)
}
func (o *TAMP_Type) GetATCR1_ATOSEL2() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0xc00) >> 10
}
func (o *TAMP_Type) SetATCR1_ATOSEL3(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x3000)|value<<12)
}
func (o *TAMP_Type) GetATCR1_ATOSEL3() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x3000) >> 12
}
func (o *TAMP_Type) SetATCR1_ATOSEL4(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0xc000)|value<<14)
}
func (o *TAMP_Type) GetATCR1_ATOSEL4() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0xc000) >> 14
}
func (o *TAMP_Type) SetATCR1_ATCKSEL(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x70000)|value<<16)
}
func (o *TAMP_Type) GetATCR1_ATCKSEL() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x70000) >> 16
}
func (o *TAMP_Type) SetATCR1_ATPER(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x7000000)|value<<24)
}
func (o *TAMP_Type) GetATCR1_ATPER() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x7000000) >> 24
}
func (o *TAMP_Type) SetATCR1_ATOSHARE(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x40000000)|value<<30)
}
func (o *TAMP_Type) GetATCR1_ATOSHARE() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x40000000) >> 30
}
func (o *TAMP_Type) SetATCR1_FLTEN(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetATCR1_FLTEN() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x80000000) >> 31
}

// TAMP.ATSEEDR: TAMP active tamper seed register
func (o *TAMP_Type) SetATSEEDR(value uint32) {
	volatile.StoreUint32(&o.ATSEEDR.Reg, value)
}
func (o *TAMP_Type) GetATSEEDR() uint32 {
	return volatile.LoadUint32(&o.ATSEEDR.Reg)
}

// TAMP.ATOR: TAMP active tamper output register
func (o *TAMP_Type) SetATOR_PRNG(value uint32) {
	volatile.StoreUint32(&o.ATOR.Reg, volatile.LoadUint32(&o.ATOR.Reg)&^(0xff)|value)
}
func (o *TAMP_Type) GetATOR_PRNG() uint32 {
	return volatile.LoadUint32(&o.ATOR.Reg) & 0xff
}
func (o *TAMP_Type) SetATOR_SEEDF(value uint32) {
	volatile.StoreUint32(&o.ATOR.Reg, volatile.LoadUint32(&o.ATOR.Reg)&^(0x4000)|value<<14)
}
func (o *TAMP_Type) GetATOR_SEEDF() uint32 {
	return (volatile.LoadUint32(&o.ATOR.Reg) & 0x4000) >> 14
}
func (o *TAMP_Type) SetATOR_INITS(value uint32) {
	volatile.StoreUint32(&o.ATOR.Reg, volatile.LoadUint32(&o.ATOR.Reg)&^(0x8000)|value<<15)
}
func (o *TAMP_Type) GetATOR_INITS() uint32 {
	return (volatile.LoadUint32(&o.ATOR.Reg) & 0x8000) >> 15
}

// TAMP.ATCR2: TAMP active tamper control register 2
func (o *TAMP_Type) SetATCR2_ATOSEL1(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x700)|value<<8)
}
func (o *TAMP_Type) GetATCR2_ATOSEL1() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x700) >> 8
}
func (o *TAMP_Type) SetATCR2_ATOSEL2(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x3800)|value<<11)
}
func (o *TAMP_Type) GetATCR2_ATOSEL2() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x3800) >> 11
}
func (o *TAMP_Type) SetATCR2_ATOSEL3(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x1c000)|value<<14)
}
func (o *TAMP_Type) GetATCR2_ATOSEL3() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x1c000) >> 14
}
func (o *TAMP_Type) SetATCR2_ATOSEL4(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x60000)|value<<17)
}
func (o *TAMP_Type) GetATCR2_ATOSEL4() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x60000) >> 17
}
func (o *TAMP_Type) SetATCR2_ATOSEL5(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x700000)|value<<20)
}
func (o *TAMP_Type) GetATCR2_ATOSEL5() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x700000) >> 20
}
func (o *TAMP_Type) SetATCR2_ATOSEL6(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x3800000)|value<<23)
}
func (o *TAMP_Type) GetATCR2_ATOSEL6() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x3800000) >> 23
}
func (o *TAMP_Type) SetATCR2_ATOSEL7(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x1c000000)|value<<26)
}
func (o *TAMP_Type) GetATCR2_ATOSEL7() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x1c000000) >> 26
}
func (o *TAMP_Type) SetATCR2_ATOSEL8(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0xe0000000)|value<<29)
}
func (o *TAMP_Type) GetATCR2_ATOSEL8() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0xe0000000) >> 29
}

// TAMP.SECCFGR: TAMP secure mode register
func (o *TAMP_Type) SetSECCFGR_BKPRWSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0xff)|value)
}
func (o *TAMP_Type) GetSECCFGR_BKPRWSEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0xff
}
func (o *TAMP_Type) SetSECCFGR_CNT1SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8000)|value<<15)
}
func (o *TAMP_Type) GetSECCFGR_CNT1SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8000) >> 15
}
func (o *TAMP_Type) SetSECCFGR_BKPWSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0xff0000)|value<<16)
}
func (o *TAMP_Type) GetSECCFGR_BKPWSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0xff0000) >> 16
}
func (o *TAMP_Type) SetSECCFGR_BHKLOCK(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x40000000)|value<<30)
}
func (o *TAMP_Type) GetSECCFGR_BHKLOCK() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x40000000) >> 30
}
func (o *TAMP_Type) SetSECCFGR_TAMPSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetSECCFGR_TAMPSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x80000000) >> 31
}

// TAMP.PRIVCR: TAMP privilege mode control register
func (o *TAMP_Type) SetPRIVCR_CNT1PRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x8000)|value<<15)
}
func (o *TAMP_Type) GetPRIVCR_CNT1PRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x8000) >> 15
}
func (o *TAMP_Type) SetPRIVCR_BKPRWPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TAMP_Type) GetPRIVCR_BKPRWPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x20000000) >> 29
}
func (o *TAMP_Type) SetPRIVCR_BKPWPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TAMP_Type) GetPRIVCR_BKPWPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x40000000) >> 30
}
func (o *TAMP_Type) SetPRIVCR_TAMPPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetPRIVCR_TAMPPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x80000000) >> 31
}

// TAMP.IER: TAMP interrupt enable register
func (o *TAMP_Type) SetIER_TAMP1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetIER_TAMP1IE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *TAMP_Type) SetIER_TAMP2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetIER_TAMP2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetIER_TAMP3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetIER_TAMP3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetIER_TAMP4IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetIER_TAMP4IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetIER_TAMP5IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetIER_TAMP5IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetIER_TAMP6IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetIER_TAMP6IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetIER_TAMP7IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetIER_TAMP7IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetIER_TAMP8IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetIER_TAMP8IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetIER_ITAMP1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetIER_ITAMP1IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetIER_ITAMP2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetIER_ITAMP2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetIER_ITAMP3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetIER_ITAMP3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetIER_ITAMP5IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetIER_ITAMP5IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetIER_ITAMP6IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetIER_ITAMP6IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200000) >> 21
}
func (o *TAMP_Type) SetIER_ITAMP7IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400000)|value<<22)
}
func (o *TAMP_Type) GetIER_ITAMP7IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400000) >> 22
}
func (o *TAMP_Type) SetIER_ITAMP8IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetIER_ITAMP8IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetIER_ITAMP9IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetIER_ITAMP9IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetIER_ITAMP11IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetIER_ITAMP11IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetIER_ITAMP12IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetIER_ITAMP12IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetIER_ITAMP13IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetIER_ITAMP13IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000000) >> 28
}

// TAMP.SR: TAMP status register
func (o *TAMP_Type) SetSR_TAMP1F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSR_TAMP1F() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *TAMP_Type) SetSR_TAMP2F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSR_TAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSR_TAMP3F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSR_TAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSR_TAMP4F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetSR_TAMP4F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetSR_TAMP5F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetSR_TAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetSR_TAMP6F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetSR_TAMP6F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetSR_TAMP7F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetSR_TAMP7F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetSR_TAMP8F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetSR_TAMP8F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetSR_CITAMP1F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetSR_CITAMP1F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetSR_CITAMP2F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetSR_CITAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetSR_ITAMP3F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSR_ITAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSR_ITAMP5F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSR_ITAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSR_ITAMP6F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetSR_ITAMP6F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200000) >> 21
}
func (o *TAMP_Type) SetSR_ITAMP7F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400000)|value<<22)
}
func (o *TAMP_Type) GetSR_ITAMP7F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400000) >> 22
}
func (o *TAMP_Type) SetSR_ITAMP8F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetSR_ITAMP8F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetSR_ITAMP9F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetSR_ITAMP9F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetSR_CITAMP11F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetSR_CITAMP11F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetSR_ITAMP12F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetSR_ITAMP12F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetSR_ITAMP13IE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetSR_ITAMP13IE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000000) >> 28
}

// TAMP.MISR: TAMP masked interrupt status register
func (o *TAMP_Type) SetMISR_TAMP1MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetMISR_TAMP1MF() uint32 {
	return volatile.LoadUint32(&o.MISR.Reg) & 0x1
}
func (o *TAMP_Type) SetMISR_TAMP2MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetMISR_TAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetMISR_TAMP3MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetMISR_TAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetMISR_TAMP4MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetMISR_TAMP4MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetMISR_TAMP5MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetMISR_TAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetMISR_TAMP6MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetMISR_TAMP6MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetMISR_TAMP7MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetMISR_TAMP7MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetMISR_TAMP8MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetMISR_TAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetMISR_ITAMP1MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetMISR_ITAMP1MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetMISR_ITAMP2MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetMISR_ITAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetMISR_ITAMP3MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetMISR_ITAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetMISR_ITAMP5MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetMISR_ITAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetMISR_ITAMP6MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetMISR_ITAMP6MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x200000) >> 21
}
func (o *TAMP_Type) SetMISR_ITAMP7MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x400000)|value<<22)
}
func (o *TAMP_Type) GetMISR_ITAMP7MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x400000) >> 22
}
func (o *TAMP_Type) SetMISR_ITAMP8MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetMISR_ITAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetMISR_ITAMP9MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetMISR_ITAMP9MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetMISR_ITAMP11MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetMISR_ITAMP11MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetMISR_ITAMP12MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetMISR_ITAMP12MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetMISR_ITAMP13MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetMISR_ITAMP13MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10000000) >> 28
}

// TAMP.SMISR: TAMP secure masked interrupt status register
func (o *TAMP_Type) SetSMISR_TAMP1MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSMISR_TAMP1MF() uint32 {
	return volatile.LoadUint32(&o.SMISR.Reg) & 0x1
}
func (o *TAMP_Type) SetSMISR_TAMP2MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSMISR_TAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSMISR_TAMP3MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSMISR_TAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSMISR_TAMP4MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetSMISR_TAMP4MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetSMISR_TAMP5MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetSMISR_TAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetSMISR_TAMP6MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetSMISR_TAMP6MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetSMISR_TAMP7MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetSMISR_TAMP7MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetSMISR_TAMP8MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetSMISR_TAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetSMISR_ITAMP1MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetSMISR_ITAMP1MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetSMISR_ITAMP2MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetSMISR_ITAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetSMISR_ITAMP3MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSMISR_ITAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSMISR_ITAMP5MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSMISR_ITAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSMISR_ITAMP6MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetSMISR_ITAMP6MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x200000) >> 21
}
func (o *TAMP_Type) SetSMISR_ITAMP7MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x400000)|value<<22)
}
func (o *TAMP_Type) GetSMISR_ITAMP7MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x400000) >> 22
}
func (o *TAMP_Type) SetSMISR_ITAMP8MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetSMISR_ITAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetSMISR_ITAMP9MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetSMISR_ITAMP9MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetSMISR_ITAMP11MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetSMISR_ITAMP11MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetSMISR_ITAMP12MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetSMISR_ITAMP12MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetSMISR_ITAMP13MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetSMISR_ITAMP13MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10000000) >> 28
}

// TAMP.SCR: TAMP status clear register
func (o *TAMP_Type) SetSCR_CTAMP1F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSCR_CTAMP1F() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}
func (o *TAMP_Type) SetSCR_CTAMP2F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSCR_CTAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSCR_CTAMP3F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSCR_CTAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSCR_CTAMP4F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetSCR_CTAMP4F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetSCR_CTAMP5F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetSCR_CTAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetSCR_CTAMP6F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetSCR_CTAMP6F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetSCR_CITAMP7F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetSCR_CITAMP7F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetSCR_CITAMP8F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetSCR_CITAMP8F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetSCR_CITAMP1F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetSCR_CITAMP1F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetSCR_CITAMP2F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetSCR_CITAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetSCR_CITAMP3F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSCR_CITAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSCR_CITAMP5F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSCR_CITAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSCR_CITAMP6F_bit21(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x200000)|value<<21)
}
func (o *TAMP_Type) GetSCR_CITAMP6F_bit21() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x200000) >> 21
}
func (o *TAMP_Type) SetSCR_CITAMP7F_bit22(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x400000)|value<<22)
}
func (o *TAMP_Type) GetSCR_CITAMP7F_bit22() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x400000) >> 22
}
func (o *TAMP_Type) SetSCR_CITAMP8F_bit23(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetSCR_CITAMP8F_bit23() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetSCR_CITAMP9F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetSCR_CITAMP9F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetSCR_CITAMP11F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetSCR_CITAMP11F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetSCR_CITAMP12F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetSCR_CITAMP12F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetSCR_CITAMP13F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetSCR_CITAMP13F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10000000) >> 28
}

// TAMP.COUNT1R: TAMP monotonic counter 1register
func (o *TAMP_Type) SetCOUNT1R(value uint32) {
	volatile.StoreUint32(&o.COUNT1R.Reg, value)
}
func (o *TAMP_Type) GetCOUNT1R() uint32 {
	return volatile.LoadUint32(&o.COUNT1R.Reg)
}

// TAMP.ERCFGR: TAMP erase configuration register
func (o *TAMP_Type) SetERCFGR_ERCFG0(value uint32) {
	volatile.StoreUint32(&o.ERCFGR.Reg, volatile.LoadUint32(&o.ERCFGR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetERCFGR_ERCFG0() uint32 {
	return volatile.LoadUint32(&o.ERCFGR.Reg) & 0x1
}

// TAMP.BKP0R: TAMP backup register
func (o *TAMP_Type) SetBKP0R(value uint32) {
	volatile.StoreUint32(&o.BKP0R.Reg, value)
}
func (o *TAMP_Type) GetBKP0R() uint32 {
	return volatile.LoadUint32(&o.BKP0R.Reg)
}

// TAMP.BKP1R: TAMP backup register
func (o *TAMP_Type) SetBKP1R(value uint32) {
	volatile.StoreUint32(&o.BKP1R.Reg, value)
}
func (o *TAMP_Type) GetBKP1R() uint32 {
	return volatile.LoadUint32(&o.BKP1R.Reg)
}

// TAMP.BKP2R: TAMP backup register
func (o *TAMP_Type) SetBKP2R(value uint32) {
	volatile.StoreUint32(&o.BKP2R.Reg, value)
}
func (o *TAMP_Type) GetBKP2R() uint32 {
	return volatile.LoadUint32(&o.BKP2R.Reg)
}

// TAMP.BKP3R: TAMP backup register
func (o *TAMP_Type) SetBKP3R(value uint32) {
	volatile.StoreUint32(&o.BKP3R.Reg, value)
}
func (o *TAMP_Type) GetBKP3R() uint32 {
	return volatile.LoadUint32(&o.BKP3R.Reg)
}

// TAMP.BKP4R: TAMP backup register
func (o *TAMP_Type) SetBKP4R(value uint32) {
	volatile.StoreUint32(&o.BKP4R.Reg, value)
}
func (o *TAMP_Type) GetBKP4R() uint32 {
	return volatile.LoadUint32(&o.BKP4R.Reg)
}

// TAMP.BKP5R: TAMP backup register
func (o *TAMP_Type) SetBKP5R(value uint32) {
	volatile.StoreUint32(&o.BKP5R.Reg, value)
}
func (o *TAMP_Type) GetBKP5R() uint32 {
	return volatile.LoadUint32(&o.BKP5R.Reg)
}

// TAMP.BKP6R: TAMP backup register
func (o *TAMP_Type) SetBKP6R(value uint32) {
	volatile.StoreUint32(&o.BKP6R.Reg, value)
}
func (o *TAMP_Type) GetBKP6R() uint32 {
	return volatile.LoadUint32(&o.BKP6R.Reg)
}

// TAMP.BKP7R: TAMP backup register
func (o *TAMP_Type) SetBKP7R(value uint32) {
	volatile.StoreUint32(&o.BKP7R.Reg, value)
}
func (o *TAMP_Type) GetBKP7R() uint32 {
	return volatile.LoadUint32(&o.BKP7R.Reg)
}

// TAMP.BKP8R: TAMP backup register
func (o *TAMP_Type) SetBKP8R(value uint32) {
	volatile.StoreUint32(&o.BKP8R.Reg, value)
}
func (o *TAMP_Type) GetBKP8R() uint32 {
	return volatile.LoadUint32(&o.BKP8R.Reg)
}

// TAMP.BKP9R: TAMP backup register
func (o *TAMP_Type) SetBKP9R(value uint32) {
	volatile.StoreUint32(&o.BKP9R.Reg, value)
}
func (o *TAMP_Type) GetBKP9R() uint32 {
	return volatile.LoadUint32(&o.BKP9R.Reg)
}

// TAMP.BKP10R: TAMP backup register
func (o *TAMP_Type) SetBKP10R(value uint32) {
	volatile.StoreUint32(&o.BKP10R.Reg, value)
}
func (o *TAMP_Type) GetBKP10R() uint32 {
	return volatile.LoadUint32(&o.BKP10R.Reg)
}

// TAMP.BKP11R: TAMP backup register
func (o *TAMP_Type) SetBKP11R(value uint32) {
	volatile.StoreUint32(&o.BKP11R.Reg, value)
}
func (o *TAMP_Type) GetBKP11R() uint32 {
	return volatile.LoadUint32(&o.BKP11R.Reg)
}

// TAMP.BKP12R: TAMP backup register
func (o *TAMP_Type) SetBKP12R(value uint32) {
	volatile.StoreUint32(&o.BKP12R.Reg, value)
}
func (o *TAMP_Type) GetBKP12R() uint32 {
	return volatile.LoadUint32(&o.BKP12R.Reg)
}

// TAMP.BKP13R: TAMP backup register
func (o *TAMP_Type) SetBKP13R(value uint32) {
	volatile.StoreUint32(&o.BKP13R.Reg, value)
}
func (o *TAMP_Type) GetBKP13R() uint32 {
	return volatile.LoadUint32(&o.BKP13R.Reg)
}

// TAMP.BKP14R: TAMP backup register
func (o *TAMP_Type) SetBKP14R(value uint32) {
	volatile.StoreUint32(&o.BKP14R.Reg, value)
}
func (o *TAMP_Type) GetBKP14R() uint32 {
	return volatile.LoadUint32(&o.BKP14R.Reg)
}

// TAMP.BKP15R: TAMP backup register
func (o *TAMP_Type) SetBKP15R(value uint32) {
	volatile.StoreUint32(&o.BKP15R.Reg, value)
}
func (o *TAMP_Type) GetBKP15R() uint32 {
	return volatile.LoadUint32(&o.BKP15R.Reg)
}

// TAMP.BKP16R: TAMP backup register
func (o *TAMP_Type) SetBKP16R(value uint32) {
	volatile.StoreUint32(&o.BKP16R.Reg, value)
}
func (o *TAMP_Type) GetBKP16R() uint32 {
	return volatile.LoadUint32(&o.BKP16R.Reg)
}

// TAMP.BKP17R: TAMP backup register
func (o *TAMP_Type) SetBKP17R(value uint32) {
	volatile.StoreUint32(&o.BKP17R.Reg, value)
}
func (o *TAMP_Type) GetBKP17R() uint32 {
	return volatile.LoadUint32(&o.BKP17R.Reg)
}

// TAMP.BKP18R: TAMP backup register
func (o *TAMP_Type) SetBKP18R(value uint32) {
	volatile.StoreUint32(&o.BKP18R.Reg, value)
}
func (o *TAMP_Type) GetBKP18R() uint32 {
	return volatile.LoadUint32(&o.BKP18R.Reg)
}

// TAMP.BKP19R: TAMP backup register
func (o *TAMP_Type) SetBKP19R(value uint32) {
	volatile.StoreUint32(&o.BKP19R.Reg, value)
}
func (o *TAMP_Type) GetBKP19R() uint32 {
	return volatile.LoadUint32(&o.BKP19R.Reg)
}

// TAMP.BKP20R: TAMP backup register
func (o *TAMP_Type) SetBKP20R(value uint32) {
	volatile.StoreUint32(&o.BKP20R.Reg, value)
}
func (o *TAMP_Type) GetBKP20R() uint32 {
	return volatile.LoadUint32(&o.BKP20R.Reg)
}

// TAMP.BKP21R: TAMP backup register
func (o *TAMP_Type) SetBKP21R(value uint32) {
	volatile.StoreUint32(&o.BKP21R.Reg, value)
}
func (o *TAMP_Type) GetBKP21R() uint32 {
	return volatile.LoadUint32(&o.BKP21R.Reg)
}

// TAMP.BKP22R: TAMP backup register
func (o *TAMP_Type) SetBKP22R(value uint32) {
	volatile.StoreUint32(&o.BKP22R.Reg, value)
}
func (o *TAMP_Type) GetBKP22R() uint32 {
	return volatile.LoadUint32(&o.BKP22R.Reg)
}

// TAMP.BKP23R: TAMP backup register
func (o *TAMP_Type) SetBKP23R(value uint32) {
	volatile.StoreUint32(&o.BKP23R.Reg, value)
}
func (o *TAMP_Type) GetBKP23R() uint32 {
	return volatile.LoadUint32(&o.BKP23R.Reg)
}

// TAMP.BKP24R: TAMP backup register
func (o *TAMP_Type) SetBKP24R(value uint32) {
	volatile.StoreUint32(&o.BKP24R.Reg, value)
}
func (o *TAMP_Type) GetBKP24R() uint32 {
	return volatile.LoadUint32(&o.BKP24R.Reg)
}

// TAMP.BKP25R: TAMP backup register
func (o *TAMP_Type) SetBKP25R(value uint32) {
	volatile.StoreUint32(&o.BKP25R.Reg, value)
}
func (o *TAMP_Type) GetBKP25R() uint32 {
	return volatile.LoadUint32(&o.BKP25R.Reg)
}

// TAMP.BKP26R: TAMP backup register
func (o *TAMP_Type) SetBKP26R(value uint32) {
	volatile.StoreUint32(&o.BKP26R.Reg, value)
}
func (o *TAMP_Type) GetBKP26R() uint32 {
	return volatile.LoadUint32(&o.BKP26R.Reg)
}

// TAMP.BKP27R: TAMP backup register
func (o *TAMP_Type) SetBKP27R(value uint32) {
	volatile.StoreUint32(&o.BKP27R.Reg, value)
}
func (o *TAMP_Type) GetBKP27R() uint32 {
	return volatile.LoadUint32(&o.BKP27R.Reg)
}

// TAMP.BKP28R: TAMP backup register
func (o *TAMP_Type) SetBKP28R(value uint32) {
	volatile.StoreUint32(&o.BKP28R.Reg, value)
}
func (o *TAMP_Type) GetBKP28R() uint32 {
	return volatile.LoadUint32(&o.BKP28R.Reg)
}

// TAMP.BKP29R: TAMP backup register
func (o *TAMP_Type) SetBKP29R(value uint32) {
	volatile.StoreUint32(&o.BKP29R.Reg, value)
}
func (o *TAMP_Type) GetBKP29R() uint32 {
	return volatile.LoadUint32(&o.BKP29R.Reg)
}

// TAMP.BKP30R: TAMP backup register
func (o *TAMP_Type) SetBKP30R(value uint32) {
	volatile.StoreUint32(&o.BKP30R.Reg, value)
}
func (o *TAMP_Type) GetBKP30R() uint32 {
	return volatile.LoadUint32(&o.BKP30R.Reg)
}

// TAMP.BKP31R: TAMP backup register
func (o *TAMP_Type) SetBKP31R(value uint32) {
	volatile.StoreUint32(&o.BKP31R.Reg, value)
}
func (o *TAMP_Type) GetBKP31R() uint32 {
	return volatile.LoadUint32(&o.BKP31R.Reg)
}

// Advanced-timers
type TIM_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	SMCR         volatile.Register32 // 0x8
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	CCMR2_Output volatile.Register32 // 0x1C
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	CCR2         volatile.Register32 // 0x38
	CCR3         volatile.Register32 // 0x3C
	CCR4         volatile.Register32 // 0x40
	BDTR         volatile.Register32 // 0x44
	CCR5         volatile.Register32 // 0x48
	CCR6         volatile.Register32 // 0x4C
	CCMR3_Output volatile.Register32 // 0x50
	DTR2         volatile.Register32 // 0x54
	ECR          volatile.Register32 // 0x58
	TISEL        volatile.Register32 // 0x5C
	AF1          volatile.Register32 // 0x60
	AF2          volatile.Register32 // 0x64
	_            [884]byte
	DCR          volatile.Register32 // 0x3DC
	DMAR         volatile.Register32 // 0x3E0
}

// TIM.CR1: control register 1
func (o *TIM_Type) SetCR1_DITHEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCR1_DITHEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCR1_UIFREMAP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCR1_UIFREMAP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCR1_CKD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCR1_CKD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCR1_ARPE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR1_ARPE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCR1_CMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x60)|value<<5)
}
func (o *TIM_Type) GetCR1_CMS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x60) >> 5
}
func (o *TIM_Type) SetCR1_DIR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCR1_DIR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCR1_OPM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR1_OPM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR1_URS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetCR1_URS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetCR1_UDIS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetCR1_UDIS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetCR1_CEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetCR1_CEN() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}

// TIM.CR2: control register 2
func (o *TIM_Type) SetCR2_MMS_3(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetCR2_MMS_3() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetCR2_MMS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xf00000)|value<<20)
}
func (o *TIM_Type) GetCR2_MMS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xf00000) >> 20
}
func (o *TIM_Type) SetCR2_OIS1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCR2_OIS1() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCR2_OIS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCR2_OIS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCR2_OIS3(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetCR2_OIS3() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetCR2_OIS4(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetCR2_OIS4() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetCR2_OIS5(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCR2_OIS5() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCR2_OIS6(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetCR2_OIS6() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetCR2_OIS1N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCR2_OIS1N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCR2_OIS2N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetCR2_OIS2N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetCR2_OIS3N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCR2_OIS3N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCR2_OIS4N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetCR2_OIS4N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *TIM_Type) SetCR2_TI1S(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR2_TI1S() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCR2_MMS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetCR2_MMS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetCR2_CCDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR2_CCDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR2_CCUS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetCR2_CCUS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetCR2_CCPC(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetCR2_CCPC() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}

// TIM.SMCR: slave mode control register
func (o *TIM_Type) SetSMCR_SMSPS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetSMCR_SMSPS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetSMCR_SMSPE(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetSMCR_SMSPE() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetSMCR_TS2(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x300000)|value<<20)
}
func (o *TIM_Type) GetSMCR_TS2() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x300000) >> 20
}
func (o *TIM_Type) SetSMCR_SMS_3(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetSMCR_SMS_3() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetSMCR_ETP(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetSMCR_ETP() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetSMCR_ECE(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetSMCR_ECE() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetSMCR_ETPS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x3000)|value<<12)
}
func (o *TIM_Type) GetSMCR_ETPS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x3000) >> 12
}
func (o *TIM_Type) SetSMCR_ETF(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0xf00)|value<<8)
}
func (o *TIM_Type) GetSMCR_ETF() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0xf00) >> 8
}
func (o *TIM_Type) SetSMCR_MSM(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetSMCR_MSM() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetSMCR_TS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetSMCR_TS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetSMCR_OCCS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetSMCR_OCCS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetSMCR_SMS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x7)|value)
}
func (o *TIM_Type) GetSMCR_SMS() uint32 {
	return volatile.LoadUint32(&o.SMCR.Reg) & 0x7
}

// TIM.DIER: DMA/Interrupt enable register
func (o *TIM_Type) SetDIER_TERRIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetDIER_TERRIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetDIER_IERRIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x400000)|value<<22)
}
func (o *TIM_Type) GetDIER_IERRIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x400000) >> 22
}
func (o *TIM_Type) SetDIER_DIRIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x200000)|value<<21)
}
func (o *TIM_Type) GetDIER_DIRIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x200000) >> 21
}
func (o *TIM_Type) SetDIER_IDXIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetDIER_IDXIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetDIER_TDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetDIER_TDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetDIER_COMDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetDIER_COMDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetDIER_CC1DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetDIER_CC1DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetDIER_CC2DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetDIER_CC2DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetDIER_CC3DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetDIER_CC3DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetDIER_CC4DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetDIER_CC4DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetDIER_UDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetDIER_UDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetDIER_BIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetDIER_BIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetDIER_TIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetDIER_TIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetDIER_COMIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetDIER_COMIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetDIER_CC1IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetDIER_CC1IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetDIER_CC2IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetDIER_CC2IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetDIER_CC3IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetDIER_CC3IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetDIER_CC4IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetDIER_CC4IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetDIER_UIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetDIER_UIE() uint32 {
	return volatile.LoadUint32(&o.DIER.Reg) & 0x1
}

// TIM.SR: status register
func (o *TIM_Type) SetSR_TERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetSR_TERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetSR_IERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400000)|value<<22)
}
func (o *TIM_Type) GetSR_IERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400000) >> 22
}
func (o *TIM_Type) SetSR_DIRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200000)|value<<21)
}
func (o *TIM_Type) GetSR_DIRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200000) >> 21
}
func (o *TIM_Type) SetSR_IDXF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetSR_IDXF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetSR_CC1IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetSR_CC1IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetSR_CC2IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetSR_CC2IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetSR_CC3IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetSR_CC3IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetSR_CC4IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetSR_CC4IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetSR_CC6IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetSR_CC6IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *TIM_Type) SetSR_CC5IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetSR_CC5IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetSR_SBIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetSR_SBIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetSR_CC1OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetSR_CC1OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetSR_CC2OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetSR_CC2OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetSR_CC3OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetSR_CC3OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetSR_CC4OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetSR_CC4OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetSR_B2IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetSR_B2IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetSR_BIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetSR_BIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetSR_TIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetSR_TIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetSR_COMIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetSR_COMIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetSR_UIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetSR_UIF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// TIM.EGR: event generation register
func (o *TIM_Type) SetEGR_B2G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetEGR_B2G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetEGR_BG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetEGR_BG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetEGR_TG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetEGR_TG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetEGR_COMG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetEGR_COMG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetEGR_CC1G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetEGR_CC1G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetEGR_CC2G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetEGR_CC2G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetEGR_CC3G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetEGR_CC3G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetEGR_CC4G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetEGR_CC4G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetEGR_UG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetEGR_UG() uint32 {
	return volatile.LoadUint32(&o.EGR.Reg) & 0x1
}

// TIM.CCMR1_Output: capture/compare mode register 1 (output mode)
func (o *TIM_Type) SetCCMR1_Output_OC1M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR1_Output_OC2M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x0) >> 32
}
func (o *TIM_Type) SetCCMR1_Output_OC1CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR1_Output_OC1CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR1_Output_OC2CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR1_Output_OC2CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR1_Output_OC1M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR1_Output_OC2M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR1_Output_OC1PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR1_Output_OC1PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR1_Output_OC2PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR1_Output_OC2PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR1_Output_OC1FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR1_Output_OC1FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR1_Output_OC2FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR1_Output_OC2FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR1_Output_CC1S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR1_Output_CC1S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR1_Output_CC2S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR1_Output_CC2S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x30000) >> 16
}

// TIM.CCMR2_Output: capture/compare mode register 2 (output mode)
func (o *TIM_Type) SetCCMR2_Output_OC3M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR2_Output_OC4M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x0) >> 32
}
func (o *TIM_Type) SetCCMR2_Output_OC3CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR2_Output_OC3CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR2_Output_OC4CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR2_Output_OC4CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR2_Output_OC3M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR2_Output_OC4M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR2_Output_OC3PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR2_Output_OC3PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR2_Output_OC4PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR2_Output_OC4PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR2_Output_OC3FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR2_Output_OC3FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR2_Output_OC4FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR2_Output_OC4FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR2_Output_CC3S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR2_Output_CC3S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR2_Output_CC4S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR2_Output_CC4S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x30000) >> 16
}

// TIM.CCER: capture/compare enable register
func (o *TIM_Type) SetCCER_CC1P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetCCER_CC1P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetCCER_CC2P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetCCER_CC2P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetCCER_CC3P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetCCER_CC3P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetCCER_CC4P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetCCER_CC4P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20000) >> 17
}
func (o *TIM_Type) SetCCER_CC5P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x200000)|value<<21)
}
func (o *TIM_Type) GetCCER_CC5P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x200000) >> 21
}
func (o *TIM_Type) SetCCER_CC6P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetCCER_CC6P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetCCER_CC1E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCCER_CC1E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCCER_CC2E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetCCER_CC2E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetCCER_CC3E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCCER_CC3E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCCER_CC4E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetCCER_CC4E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetCCER_CC5E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetCCER_CC5E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetCCER_CC6E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCER_CC6E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCER_CC1NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCCER_CC1NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCCER_CC2NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCER_CC2NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCER_CC3NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCER_CC3NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCER_CC4NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCER_CC4NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCER_CC1NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetCCER_CC1NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetCCER_CC2NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCER_CC2NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCER_CC3NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetCCER_CC3NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x4000) >> 14
}

// TIM.CNT: counter
func (o *TIM_Type) SetCNT_UIFCPY(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0x80000000)|value<<31)
}
func (o *TIM_Type) GetCNT_UIFCPY() uint32 {
	return (volatile.LoadUint32(&o.CNT.Reg) & 0x80000000) >> 31
}
func (o *TIM_Type) SetCNT(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCNT() uint32 {
	return volatile.LoadUint32(&o.CNT.Reg) & 0xffff
}

// TIM.PSC: prescaler
func (o *TIM_Type) SetPSC(value uint32) {
	volatile.StoreUint32(&o.PSC.Reg, volatile.LoadUint32(&o.PSC.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetPSC() uint32 {
	return volatile.LoadUint32(&o.PSC.Reg) & 0xffff
}

// TIM.ARR: auto-reload register
func (o *TIM_Type) SetARR(value uint32) {
	volatile.StoreUint32(&o.ARR.Reg, volatile.LoadUint32(&o.ARR.Reg)&^(0xfffff)|value)
}
func (o *TIM_Type) GetARR() uint32 {
	return volatile.LoadUint32(&o.ARR.Reg) & 0xfffff
}

// TIM.RCR: repetition counter register
func (o *TIM_Type) SetRCR_REP(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetRCR_REP() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xffff
}

// TIM.CCR1: capture/compare register
func (o *TIM_Type) SetCCR1_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0xfffff)|value)
}
func (o *TIM_Type) GetCCR1_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0xfffff
}

// TIM.CCR2: capture/compare register
func (o *TIM_Type) SetCCR2_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0xfffff)|value)
}
func (o *TIM_Type) GetCCR2_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0xfffff
}

// TIM.CCR3: capture/compare register
func (o *TIM_Type) SetCCR3_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0xfffff)|value)
}
func (o *TIM_Type) GetCCR3_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR3.Reg) & 0xfffff
}

// TIM.CCR4: capture/compare register
func (o *TIM_Type) SetCCR4_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0xfffff)|value)
}
func (o *TIM_Type) GetCCR4_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR4.Reg) & 0xfffff
}

// TIM.BDTR: break and dead-time register
func (o *TIM_Type) SetBDTR_BK2BID(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x20000000)|value<<29)
}
func (o *TIM_Type) GetBDTR_BK2BID() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x20000000) >> 29
}
func (o *TIM_Type) SetBDTR_BKBID(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x10000000)|value<<28)
}
func (o *TIM_Type) GetBDTR_BKBID() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x10000000) >> 28
}
func (o *TIM_Type) SetBDTR_BK2DSRAM(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x8000000)|value<<27)
}
func (o *TIM_Type) GetBDTR_BK2DSRAM() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x8000000) >> 27
}
func (o *TIM_Type) SetBDTR_BKDSRM(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x4000000)|value<<26)
}
func (o *TIM_Type) GetBDTR_BKDSRM() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x4000000) >> 26
}
func (o *TIM_Type) SetBDTR_BKP(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetBDTR_BKP() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetBDTR_BK2P(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetBDTR_BK2P() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetBDTR_BKE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetBDTR_BKE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetBDTR_BK2E(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetBDTR_BK2E() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetBDTR_BK2F(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xf00000)|value<<20)
}
func (o *TIM_Type) GetBDTR_BK2F() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0xf00000) >> 20
}
func (o *TIM_Type) SetBDTR_BKF(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xf0000)|value<<16)
}
func (o *TIM_Type) GetBDTR_BKF() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0xf0000) >> 16
}
func (o *TIM_Type) SetBDTR_MOE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetBDTR_MOE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetBDTR_AOE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetBDTR_AOE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetBDTR_OSSR(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetBDTR_OSSR() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetBDTR_OSSI(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetBDTR_OSSI() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetBDTR_LOCK(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetBDTR_LOCK() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetBDTR_DTG(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xff)|value)
}
func (o *TIM_Type) GetBDTR_DTG() uint32 {
	return volatile.LoadUint32(&o.BDTR.Reg) & 0xff
}

// TIM.CCR5: capture/compare register
func (o *TIM_Type) SetCCR5_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0xfffff)|value)
}
func (o *TIM_Type) GetCCR5_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR5.Reg) & 0xfffff
}
func (o *TIM_Type) SetCCR5_GC5C1(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x20000000)|value<<29)
}
func (o *TIM_Type) GetCCR5_GC5C1() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x20000000) >> 29
}
func (o *TIM_Type) SetCCR5_GC5C2(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x40000000)|value<<30)
}
func (o *TIM_Type) GetCCR5_GC5C2() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x40000000) >> 30
}
func (o *TIM_Type) SetCCR5_GC5C3(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x80000000)|value<<31)
}
func (o *TIM_Type) GetCCR5_GC5C3() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x80000000) >> 31
}

// TIM.CCR6: capture/compare register
func (o *TIM_Type) SetCCR6_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0xfffff)|value)
}
func (o *TIM_Type) GetCCR6_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR6.Reg) & 0xfffff
}

// TIM.CCMR3_Output: capture/compare mode register 3
func (o *TIM_Type) SetCCMR3_Output_OC5FE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR3_Output_OC5FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR3_Output_OC6FE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR3_Output_OC6FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR3_Output_OC5PE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR3_Output_OC5PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR3_Output_OC6PE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR3_Output_OC6PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR3_Output_OC5M(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR3_Output_OC5M() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR3_Output_OC6M(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR3_Output_OC6M() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR3_Output_OC5CE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR3_Output_OC5CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR3_Output_OC6CE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR3_Output_OC6CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR3_Output_OC5M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR3_Output_OC5M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR3_Output_OC6M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR3_Output_OC6M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x0) >> 32
}

// TIM.DTR2: deadtime register 2
func (o *TIM_Type) SetDTR2_DTPE(value uint32) {
	volatile.StoreUint32(&o.DTR2.Reg, volatile.LoadUint32(&o.DTR2.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetDTR2_DTPE() uint32 {
	return (volatile.LoadUint32(&o.DTR2.Reg) & 0x20000) >> 17
}
func (o *TIM_Type) SetDTR2_DTAE(value uint32) {
	volatile.StoreUint32(&o.DTR2.Reg, volatile.LoadUint32(&o.DTR2.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetDTR2_DTAE() uint32 {
	return (volatile.LoadUint32(&o.DTR2.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetDTR2_DTGF(value uint32) {
	volatile.StoreUint32(&o.DTR2.Reg, volatile.LoadUint32(&o.DTR2.Reg)&^(0xff)|value)
}
func (o *TIM_Type) GetDTR2_DTGF() uint32 {
	return volatile.LoadUint32(&o.DTR2.Reg) & 0xff
}

// TIM.ECR: encoder control register
func (o *TIM_Type) SetECR_PWPRSC(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x7000000)|value<<24)
}
func (o *TIM_Type) GetECR_PWPRSC() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0x7000000) >> 24
}
func (o *TIM_Type) SetECR_PW(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xff0000)|value<<16)
}
func (o *TIM_Type) GetECR_PW() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0xff0000) >> 16
}
func (o *TIM_Type) SetECR_IPOS(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xc0)|value<<6)
}
func (o *TIM_Type) GetECR_IPOS() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0xc0) >> 6
}
func (o *TIM_Type) SetECR_FIDX(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetECR_FIDX() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetECR_IDIR(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x6)|value<<1)
}
func (o *TIM_Type) GetECR_IDIR() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0x6) >> 1
}
func (o *TIM_Type) SetECR_IE(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetECR_IE() uint32 {
	return volatile.LoadUint32(&o.ECR.Reg) & 0x1
}

// TIM.TISEL: timer input selection register
func (o *TIM_Type) SetTISEL_TI4SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf000000)|value<<24)
}
func (o *TIM_Type) GetTISEL_TI4SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf000000) >> 24
}
func (o *TIM_Type) SetTISEL_TI3SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf0000)|value<<16)
}
func (o *TIM_Type) GetTISEL_TI3SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf0000) >> 16
}
func (o *TIM_Type) SetTISEL_TI2SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf00)|value<<8)
}
func (o *TIM_Type) GetTISEL_TI2SEL() uint32 {
	return (volatile.LoadUint32(&o.TISEL.Reg) & 0xf00) >> 8
}
func (o *TIM_Type) SetTISEL_TI1SEL(value uint32) {
	volatile.StoreUint32(&o.TISEL.Reg, volatile.LoadUint32(&o.TISEL.Reg)&^(0xf)|value)
}
func (o *TIM_Type) GetTISEL_TI1SEL() uint32 {
	return volatile.LoadUint32(&o.TISEL.Reg) & 0xf
}

// TIM.AF1: alternate function option register 1
func (o *TIM_Type) SetAF1_ETRSEL(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x3c000)|value<<14)
}
func (o *TIM_Type) GetAF1_ETRSEL() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x3c000) >> 14
}
func (o *TIM_Type) SetAF1_BKCMP4P(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetAF1_BKCMP4P() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetAF1_BKCMP3P(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetAF1_BKCMP3P() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetAF1_BKCMP2P(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetAF1_BKCMP2P() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetAF1_BKCMP1P(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetAF1_BKCMP1P() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetAF1_BKINP(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetAF1_BKINP() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetAF1_BKCMP8E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetAF1_BKCMP8E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetAF1_BKCMP7E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetAF1_BKCMP7E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetAF1_BKCMP6E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetAF1_BKCMP6E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetAF1_BKCMP5E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetAF1_BKCMP5E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetAF1_BKCMP4E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetAF1_BKCMP4E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetAF1_BKCMP3E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetAF1_BKCMP3E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetAF1_BKCMP2E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetAF1_BKCMP2E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetAF1_BKCMP1E(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetAF1_BKCMP1E() uint32 {
	return (volatile.LoadUint32(&o.AF1.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetAF1_BKINE(value uint32) {
	volatile.StoreUint32(&o.AF1.Reg, volatile.LoadUint32(&o.AF1.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetAF1_BKINE() uint32 {
	return volatile.LoadUint32(&o.AF1.Reg) & 0x1
}

// TIM.AF2: alternate function register 2
func (o *TIM_Type) SetAF2_OCRSEL(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x70000)|value<<16)
}
func (o *TIM_Type) GetAF2_OCRSEL() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x70000) >> 16
}
func (o *TIM_Type) SetAF2_BK2CMP4P(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetAF2_BK2CMP4P() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetAF2_BK2CMP3P(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetAF2_BK2CMP3P() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetAF2_BK2CMP2P(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetAF2_BK2CMP2P() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetAF2_BK2CMP1P(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetAF2_BK2CMP1P() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetAF2_BK2INP(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetAF2_BK2INP() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetAF2_BK2CMP8E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetAF2_BK2CMP8E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetAF2_BK2CMP7E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetAF2_BK2CMP7E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetAF2_BK2CMP6E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetAF2_BK2CMP6E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetAF2_BK2CMP5E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetAF2_BK2CMP5E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetAF2_BK2CMP4E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetAF2_BK2CMP4E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetAF2_BK2CMP3E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetAF2_BK2CMP3E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetAF2_BK2CMP2E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetAF2_BK2CMP2E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetAF2_BK2CMP1E(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetAF2_BK2CMP1E() uint32 {
	return (volatile.LoadUint32(&o.AF2.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetAF2_BK2INE(value uint32) {
	volatile.StoreUint32(&o.AF2.Reg, volatile.LoadUint32(&o.AF2.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetAF2_BK2INE() uint32 {
	return volatile.LoadUint32(&o.AF2.Reg) & 0x1
}

// TIM.DCR: DMA control register
func (o *TIM_Type) SetDCR_DBSS(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0xf0000)|value<<16)
}
func (o *TIM_Type) GetDCR_DBSS() uint32 {
	return (volatile.LoadUint32(&o.DCR.Reg) & 0xf0000) >> 16
}
func (o *TIM_Type) SetDCR_DBL(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f00)|value<<8)
}
func (o *TIM_Type) GetDCR_DBL() uint32 {
	return (volatile.LoadUint32(&o.DCR.Reg) & 0x1f00) >> 8
}
func (o *TIM_Type) SetDCR_DBA(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f)|value)
}
func (o *TIM_Type) GetDCR_DBA() uint32 {
	return volatile.LoadUint32(&o.DCR.Reg) & 0x1f
}

// TIM.DMAR: DMA address for full transfer
func (o *TIM_Type) SetDMAR(value uint32) {
	volatile.StoreUint32(&o.DMAR.Reg, value)
}
func (o *TIM_Type) GetDMAR() uint32 {
	return volatile.LoadUint32(&o.DMAR.Reg)
}

// Touch sensing controller
type TSC_Type struct {
	CR     volatile.Register32 // 0x0
	IER    volatile.Register32 // 0x4
	ICR    volatile.Register32 // 0x8
	ISR    volatile.Register32 // 0xC
	IOHCR  volatile.Register32 // 0x10
	_      [4]byte
	IOASCR volatile.Register32 // 0x18
	_      [4]byte
	IOSCR  volatile.Register32 // 0x20
	_      [4]byte
	IOCCR  volatile.Register32 // 0x28
	_      [4]byte
	IOGCSR volatile.Register32 // 0x30
	IOG1CR volatile.Register32 // 0x34
	IOG2CR volatile.Register32 // 0x38
	IOG3CR volatile.Register32 // 0x3C
	IOG4CR volatile.Register32 // 0x40
	IOG5CR volatile.Register32 // 0x44
	IOG6CR volatile.Register32 // 0x48
	IOG7CR volatile.Register32 // 0x4C
	IOG8CR volatile.Register32 // 0x50
}

// TSC.CR: control register
func (o *TSC_Type) SetCR_CTPH(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf0000000)|value<<28)
}
func (o *TSC_Type) GetCR_CTPH() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf0000000) >> 28
}
func (o *TSC_Type) SetCR_CTPL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf000000)|value<<24)
}
func (o *TSC_Type) GetCR_CTPL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf000000) >> 24
}
func (o *TSC_Type) SetCR_SSD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xfe0000)|value<<17)
}
func (o *TSC_Type) GetCR_SSD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xfe0000) >> 17
}
func (o *TSC_Type) SetCR_SSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetCR_SSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetCR_SSPSC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetCR_SSPSC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetCR_PGPSC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7000)|value<<12)
}
func (o *TSC_Type) GetCR_PGPSC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x7000) >> 12
}
func (o *TSC_Type) SetCR_MCV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xe0)|value<<5)
}
func (o *TSC_Type) GetCR_MCV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xe0) >> 5
}
func (o *TSC_Type) SetCR_IODEF(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetCR_IODEF() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetCR_SYNCPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *TSC_Type) GetCR_SYNCPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *TSC_Type) SetCR_AM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *TSC_Type) GetCR_AM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *TSC_Type) SetCR_START(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetCR_START() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetCR_TSCE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetCR_TSCE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// TSC.IER: interrupt enable register
func (o *TSC_Type) SetIER_MCEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetIER_MCEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetIER_EOAIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetIER_EOAIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}

// TSC.ICR: interrupt clear register
func (o *TSC_Type) SetICR_MCEIC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetICR_MCEIC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetICR_EOAIC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetICR_EOAIC() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}

// TSC.ISR: interrupt status register
func (o *TSC_Type) SetISR_MCEF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetISR_MCEF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetISR_EOAF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetISR_EOAF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// TSC.IOHCR: I/O hysteresis control register
func (o *TSC_Type) SetIOHCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOHCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOHCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOHCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOHCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOHCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOHCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOHCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOHCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOHCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOHCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOHCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOHCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOHCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOHCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOHCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOHCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOHCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOHCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOHCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOHCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOHCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOHCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOHCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOHCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOHCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOHCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOHCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOHCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOHCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOHCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOHCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOHCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOHCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOHCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOHCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOHCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOHCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOHCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOHCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOHCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOHCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOHCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOHCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOHCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOHCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOHCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOHCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOHCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOHCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOHCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOHCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOHCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOHCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOHCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOHCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOHCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOHCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOHCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOHCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOHCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOHCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOHCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOHCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 33
}

// TSC.IOASCR: I/O analog switch control register
func (o *TSC_Type) SetIOASCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOASCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOASCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOASCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOASCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOASCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOASCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOASCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOASCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOASCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOASCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOASCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOASCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOASCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOASCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOASCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOASCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOASCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOASCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOASCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOASCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOASCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOASCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOASCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOASCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOASCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOASCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOASCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOASCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOASCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOASCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOASCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOASCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOASCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOASCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOASCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOASCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOASCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOASCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOASCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOASCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOASCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOASCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOASCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOASCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOASCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOASCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOASCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOASCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOASCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOASCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOASCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOASCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOASCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOASCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOASCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOASCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOASCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOASCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOASCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOASCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOASCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOASCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOASCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 33
}

// TSC.IOSCR: I/O sampling control register
func (o *TSC_Type) SetIOSCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOSCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOSCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOSCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOSCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOSCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOSCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOSCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOSCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOSCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOSCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOSCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOSCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOSCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOSCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOSCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOSCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOSCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOSCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOSCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOSCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOSCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOSCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOSCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOSCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOSCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOSCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOSCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOSCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOSCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOSCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOSCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOSCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOSCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOSCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOSCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOSCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOSCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOSCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOSCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOSCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOSCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOSCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOSCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOSCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOSCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOSCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOSCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOSCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOSCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOSCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOSCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOSCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOSCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOSCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOSCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOSCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOSCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOSCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOSCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOSCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOSCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOSCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOSCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 33
}

// TSC.IOCCR: I/O channel control register
func (o *TSC_Type) SetIOCCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOCCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOCCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOCCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOCCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOCCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOCCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOCCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOCCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOCCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOCCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOCCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOCCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOCCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOCCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOCCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOCCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOCCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOCCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOCCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOCCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOCCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOCCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOCCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOCCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOCCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOCCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOCCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOCCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOCCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOCCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOCCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOCCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOCCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOCCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOCCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOCCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOCCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOCCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOCCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOCCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOCCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOCCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOCCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOCCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOCCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOCCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOCCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOCCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOCCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOCCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOCCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOCCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOCCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOCCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOCCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOCCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOCCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOCCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOCCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOCCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOCCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOCCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOCCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 33
}

// TSC.IOGCSR: I/O group control status register
func (o *TSC_Type) SetIOGCSR_G1S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOGCSR_G1S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOGCSR_G2S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOGCSR_G2S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOGCSR_G3S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOGCSR_G3S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOGCSR_G4S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOGCSR_G4S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOGCSR_G5S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOGCSR_G5S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOGCSR_G6S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOGCSR_G6S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOGCSR_G7S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOGCSR_G7S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOGCSR_G8S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOGCSR_G8S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOGCSR_G1E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetIOGCSR_G1E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetIOGCSR_G2E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x4)|value<<2)
}
func (o *TSC_Type) GetIOGCSR_G2E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x4) >> 2
}
func (o *TSC_Type) SetIOGCSR_G3E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x8)|value<<3)
}
func (o *TSC_Type) GetIOGCSR_G3E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x8) >> 3
}
func (o *TSC_Type) SetIOGCSR_G4E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOGCSR_G4E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOGCSR_G5E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOGCSR_G5E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOGCSR_G6E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOGCSR_G6E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOGCSR_G7E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOGCSR_G7E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOGCSR_G8E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOGCSR_G8E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x100) >> 8
}

// TSC.IOG1CR: I/O group x counter register
func (o *TSC_Type) SetIOG1CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG1CR.Reg, volatile.LoadUint32(&o.IOG1CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG1CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG1CR.Reg) & 0x3fff
}

// TSC.IOG2CR: I/O group x counter register
func (o *TSC_Type) SetIOG2CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG2CR.Reg, volatile.LoadUint32(&o.IOG2CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG2CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG2CR.Reg) & 0x3fff
}

// TSC.IOG3CR: I/O group x counter register
func (o *TSC_Type) SetIOG3CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG3CR.Reg, volatile.LoadUint32(&o.IOG3CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG3CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG3CR.Reg) & 0x3fff
}

// TSC.IOG4CR: I/O group x counter register
func (o *TSC_Type) SetIOG4CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG4CR.Reg, volatile.LoadUint32(&o.IOG4CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG4CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG4CR.Reg) & 0x3fff
}

// TSC.IOG5CR: I/O group x counter register
func (o *TSC_Type) SetIOG5CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG5CR.Reg, volatile.LoadUint32(&o.IOG5CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG5CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG5CR.Reg) & 0x3fff
}

// TSC.IOG6CR: I/O group x counter register
func (o *TSC_Type) SetIOG6CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG6CR.Reg, volatile.LoadUint32(&o.IOG6CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG6CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG6CR.Reg) & 0x3fff
}

// TSC.IOG7CR: I/O group x counter register
func (o *TSC_Type) SetIOG7CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG7CR.Reg, volatile.LoadUint32(&o.IOG7CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG7CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG7CR.Reg) & 0x3fff
}

// TSC.IOG8CR: I/O group x counter register
func (o *TSC_Type) SetIOG8CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG8CR.Reg, volatile.LoadUint32(&o.IOG8CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG8CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG8CR.Reg) & 0x3fff
}

// USB Power Delivery interface
type UCPD_Type struct {
	CFGR1       volatile.Register32 // 0x0
	CFGR2       volatile.Register32 // 0x4
	CFGR3       volatile.Register32 // 0x8
	CR          volatile.Register32 // 0xC
	IMR         volatile.Register32 // 0x10
	SR          volatile.Register32 // 0x14
	ICR         volatile.Register32 // 0x18
	TX_ORDSETR  volatile.Register32 // 0x1C
	TX_PAYSZR   volatile.Register32 // 0x20
	TXDR        volatile.Register32 // 0x24
	RX_ORDSETR  volatile.Register32 // 0x28
	RX_PAYSZR   volatile.Register32 // 0x2C
	RXDR        volatile.Register32 // 0x30
	RX_ORDEXTR1 volatile.Register32 // 0x34
	RX_ORDEXTR2 volatile.Register32 // 0x38
}

// UCPD.CFGR1: UCPD configuration register 1
func (o *UCPD_Type) SetCFGR1_HBITCLKDIV(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3f)|value)
}
func (o *UCPD_Type) GetCFGR1_HBITCLKDIV() uint32 {
	return volatile.LoadUint32(&o.CFGR1.Reg) & 0x3f
}
func (o *UCPD_Type) SetCFGR1_IFRGAP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x7c0)|value<<6)
}
func (o *UCPD_Type) GetCFGR1_IFRGAP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x7c0) >> 6
}
func (o *UCPD_Type) SetCFGR1_TRANSWIN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xf800)|value<<11)
}
func (o *UCPD_Type) GetCFGR1_TRANSWIN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xf800) >> 11
}
func (o *UCPD_Type) SetCFGR1_PSC_USBPDCLK(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xe0000)|value<<17)
}
func (o *UCPD_Type) GetCFGR1_PSC_USBPDCLK() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xe0000) >> 17
}
func (o *UCPD_Type) SetCFGR1_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20000000)|value<<29)
}
func (o *UCPD_Type) GetCFGR1_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20000000) >> 29
}
func (o *UCPD_Type) SetCFGR1_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x40000000)|value<<30)
}
func (o *UCPD_Type) GetCFGR1_RXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x40000000) >> 30
}
func (o *UCPD_Type) SetCFGR1_UCPDEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x80000000)|value<<31)
}
func (o *UCPD_Type) GetCFGR1_UCPDEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x80000000) >> 31
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN0(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN0() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100000) >> 20
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN1(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN1() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200000) >> 21
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN2(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN2() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x400000) >> 22
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN3(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN3() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x800000) >> 23
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN4(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN4() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x1000000) >> 24
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN5(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x2000000)|value<<25)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN5() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x2000000) >> 25
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN6(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x4000000)|value<<26)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN6() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x4000000) >> 26
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN7(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x8000000)|value<<27)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN7() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x8000000) >> 27
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN8(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10000000)|value<<28)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN8() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10000000) >> 28
}

// UCPD.CFGR2: UCPD configuration register 2
func (o *UCPD_Type) SetCFGR2_RXFILTDIS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *UCPD_Type) GetCFGR2_RXFILTDIS() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}
func (o *UCPD_Type) SetCFGR2_RXFILT2N3(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetCFGR2_RXFILT2N3() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetCFGR2_FORCECLK(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetCFGR2_FORCECLK() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetCFGR2_WUPEN(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetCFGR2_WUPEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x8) >> 3
}

// UCPD.CFGR3: UCPD configuration register 3
func (o *UCPD_Type) SetCFGR3_TRIM1_NG_CCRPD(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0xf)|value)
}
func (o *UCPD_Type) GetCFGR3_TRIM1_NG_CCRPD() uint32 {
	return volatile.LoadUint32(&o.CFGR3.Reg) & 0xf
}
func (o *UCPD_Type) SetCFGR3_TRIM1_NG_CC3A0(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x1e00)|value<<9)
}
func (o *UCPD_Type) GetCFGR3_TRIM1_NG_CC3A0() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x1e00) >> 9
}
func (o *UCPD_Type) SetCFGR3_TRIM2_NG_CCRPD(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0xf0000)|value<<16)
}
func (o *UCPD_Type) GetCFGR3_TRIM2_NG_CCRPD() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0xf0000) >> 16
}
func (o *UCPD_Type) SetCFGR3_TRIM2_NG_CC3A0(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x1e000000)|value<<25)
}
func (o *UCPD_Type) GetCFGR3_TRIM2_NG_CC3A0() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x1e000000) >> 25
}

// UCPD.CR: UCPD control register
func (o *UCPD_Type) SetCR_TXMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3)|value)
}
func (o *UCPD_Type) GetCR_TXMODE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x3
}
func (o *UCPD_Type) SetCR_TXSEND(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetCR_TXSEND() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetCR_TXHRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetCR_TXHRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetCR_RXMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetCR_RXMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetCR_PHYRXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetCR_PHYRXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetCR_PHYCCSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetCR_PHYCCSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetCR_ANASUBMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x180)|value<<7)
}
func (o *UCPD_Type) GetCR_ANASUBMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x180) >> 7
}
func (o *UCPD_Type) SetCR_ANAMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetCR_ANAMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetCR_CCENABLE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00)|value<<10)
}
func (o *UCPD_Type) GetCR_CCENABLE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00) >> 10
}
func (o *UCPD_Type) SetCR_FRSRXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *UCPD_Type) GetCR_FRSRXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *UCPD_Type) SetCR_FRSTX(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *UCPD_Type) GetCR_FRSTX() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *UCPD_Type) SetCR_RDCH(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *UCPD_Type) GetCR_RDCH() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *UCPD_Type) SetCR_CC1TCDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetCR_CC1TCDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *UCPD_Type) SetCR_CC2TCDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200000)|value<<21)
}
func (o *UCPD_Type) GetCR_CC2TCDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200000) >> 21
}

// UCPD.IMR: UCPD Interrupt Mask Register
func (o *UCPD_Type) SetIMR_TXISIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *UCPD_Type) GetIMR_TXISIE() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *UCPD_Type) SetIMR_TXMSGDISCIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetIMR_TXMSGDISCIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetIMR_TXMSGSENTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetIMR_TXMSGSENTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetIMR_TXMSGABTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetIMR_TXMSGABTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetIMR_HRSTDISCIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetIMR_HRSTDISCIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetIMR_HRSTSENTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetIMR_HRSTSENTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetIMR_TXUNDIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetIMR_TXUNDIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetIMR_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *UCPD_Type) GetIMR_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *UCPD_Type) SetIMR_RXORDDETIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetIMR_RXORDDETIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetIMR_RXHRSTDETIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *UCPD_Type) GetIMR_RXHRSTDETIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *UCPD_Type) SetIMR_RXOVRIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *UCPD_Type) GetIMR_RXOVRIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *UCPD_Type) SetIMR_RXMSGENDIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *UCPD_Type) GetIMR_RXMSGENDIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *UCPD_Type) SetIMR_TYPECEVT1IE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000)|value<<14)
}
func (o *UCPD_Type) GetIMR_TYPECEVT1IE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000) >> 14
}
func (o *UCPD_Type) SetIMR_TYPECEVT2IE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000)|value<<15)
}
func (o *UCPD_Type) GetIMR_TYPECEVT2IE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000) >> 15
}
func (o *UCPD_Type) SetIMR_FRSEVTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetIMR_FRSEVTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100000) >> 20
}

// UCPD.SR: UCPD Status Register
func (o *UCPD_Type) SetSR_TXIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *UCPD_Type) GetSR_TXIS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *UCPD_Type) SetSR_TXMSGDISC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetSR_TXMSGDISC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetSR_TXMSGSENT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetSR_TXMSGSENT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetSR_TXMSGABT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetSR_TXMSGABT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetSR_HRSTDISC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetSR_HRSTDISC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetSR_HRSTSENT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetSR_HRSTSENT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetSR_TXUND(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetSR_TXUND() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetSR_RXNE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *UCPD_Type) GetSR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *UCPD_Type) SetSR_RXORDDET(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetSR_RXORDDET() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetSR_RXHRSTDET(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *UCPD_Type) GetSR_RXHRSTDET() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *UCPD_Type) SetSR_RXOVR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *UCPD_Type) GetSR_RXOVR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *UCPD_Type) SetSR_RXMSGEND(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *UCPD_Type) GetSR_RXMSGEND() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *UCPD_Type) SetSR_RXERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *UCPD_Type) GetSR_RXERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *UCPD_Type) SetSR_TYPECEVT1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000)|value<<14)
}
func (o *UCPD_Type) GetSR_TYPECEVT1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000) >> 14
}
func (o *UCPD_Type) SetSR_TYPECEVT2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000)|value<<15)
}
func (o *UCPD_Type) GetSR_TYPECEVT2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000) >> 15
}
func (o *UCPD_Type) SetSR_TYPEC_VSTATE_CC1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x30000)|value<<16)
}
func (o *UCPD_Type) GetSR_TYPEC_VSTATE_CC1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x30000) >> 16
}
func (o *UCPD_Type) SetSR_TYPEC_VSTATE_CC2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc0000)|value<<18)
}
func (o *UCPD_Type) GetSR_TYPEC_VSTATE_CC2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0xc0000) >> 18
}
func (o *UCPD_Type) SetSR_FRSEVT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetSR_FRSEVT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}

// UCPD.ICR: UCPD Interrupt Clear Register
func (o *UCPD_Type) SetICR_TXMSGDISCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetICR_TXMSGDISCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetICR_TXMSGSENTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetICR_TXMSGSENTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetICR_TXMSGABTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetICR_TXMSGABTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetICR_HRSTDISCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetICR_HRSTDISCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetICR_HRSTSENTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetICR_HRSTSENTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetICR_TXUNDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetICR_TXUNDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetICR_RXORDDETCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetICR_RXORDDETCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetICR_RXHRSTDETCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *UCPD_Type) GetICR_RXHRSTDETCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *UCPD_Type) SetICR_RXOVRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *UCPD_Type) GetICR_RXOVRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *UCPD_Type) SetICR_RXMSGENDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *UCPD_Type) GetICR_RXMSGENDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *UCPD_Type) SetICR_TYPECEVT1CF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4000)|value<<14)
}
func (o *UCPD_Type) GetICR_TYPECEVT1CF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4000) >> 14
}
func (o *UCPD_Type) SetICR_TYPECEVT2CF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8000)|value<<15)
}
func (o *UCPD_Type) GetICR_TYPECEVT2CF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8000) >> 15
}
func (o *UCPD_Type) SetICR_FRSEVTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetICR_FRSEVTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100000) >> 20
}

// UCPD.TX_ORDSETR: UCPD Tx Ordered Set Type Register
func (o *UCPD_Type) SetTX_ORDSETR_TXORDSET(value uint32) {
	volatile.StoreUint32(&o.TX_ORDSETR.Reg, volatile.LoadUint32(&o.TX_ORDSETR.Reg)&^(0xfffff)|value)
}
func (o *UCPD_Type) GetTX_ORDSETR_TXORDSET() uint32 {
	return volatile.LoadUint32(&o.TX_ORDSETR.Reg) & 0xfffff
}

// UCPD.TX_PAYSZR: UCPD Tx payload size Register
func (o *UCPD_Type) SetTX_PAYSZR_TXPAYSZ(value uint32) {
	volatile.StoreUint32(&o.TX_PAYSZR.Reg, volatile.LoadUint32(&o.TX_PAYSZR.Reg)&^(0x3ff)|value)
}
func (o *UCPD_Type) GetTX_PAYSZR_TXPAYSZ() uint32 {
	return volatile.LoadUint32(&o.TX_PAYSZR.Reg) & 0x3ff
}

// UCPD.TXDR: UCPD Tx Data Register
func (o *UCPD_Type) SetTXDR_TXDATA(value uint32) {
	volatile.StoreUint32(&o.TXDR.Reg, volatile.LoadUint32(&o.TXDR.Reg)&^(0xff)|value)
}
func (o *UCPD_Type) GetTXDR_TXDATA() uint32 {
	return volatile.LoadUint32(&o.TXDR.Reg) & 0xff
}

// UCPD.RX_ORDSETR: UCPD Rx Ordered Set Register
func (o *UCPD_Type) SetRX_ORDSETR_RXORDSET(value uint32) {
	volatile.StoreUint32(&o.RX_ORDSETR.Reg, volatile.LoadUint32(&o.RX_ORDSETR.Reg)&^(0x7)|value)
}
func (o *UCPD_Type) GetRX_ORDSETR_RXORDSET() uint32 {
	return volatile.LoadUint32(&o.RX_ORDSETR.Reg) & 0x7
}
func (o *UCPD_Type) SetRX_ORDSETR_RXSOP3OF4(value uint32) {
	volatile.StoreUint32(&o.RX_ORDSETR.Reg, volatile.LoadUint32(&o.RX_ORDSETR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetRX_ORDSETR_RXSOP3OF4() uint32 {
	return (volatile.LoadUint32(&o.RX_ORDSETR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetRX_ORDSETR_RXSOPKINVALID(value uint32) {
	volatile.StoreUint32(&o.RX_ORDSETR.Reg, volatile.LoadUint32(&o.RX_ORDSETR.Reg)&^(0x70)|value<<4)
}
func (o *UCPD_Type) GetRX_ORDSETR_RXSOPKINVALID() uint32 {
	return (volatile.LoadUint32(&o.RX_ORDSETR.Reg) & 0x70) >> 4
}

// UCPD.RX_PAYSZR: UCPD Rx payload size Register
func (o *UCPD_Type) SetRX_PAYSZR_RXPAYSZ(value uint32) {
	volatile.StoreUint32(&o.RX_PAYSZR.Reg, volatile.LoadUint32(&o.RX_PAYSZR.Reg)&^(0x3ff)|value)
}
func (o *UCPD_Type) GetRX_PAYSZR_RXPAYSZ() uint32 {
	return volatile.LoadUint32(&o.RX_PAYSZR.Reg) & 0x3ff
}

// UCPD.RXDR: UCPD Receive Data Register
func (o *UCPD_Type) SetRXDR_RXDATA(value uint32) {
	volatile.StoreUint32(&o.RXDR.Reg, volatile.LoadUint32(&o.RXDR.Reg)&^(0xff)|value)
}
func (o *UCPD_Type) GetRXDR_RXDATA() uint32 {
	return volatile.LoadUint32(&o.RXDR.Reg) & 0xff
}

// UCPD.RX_ORDEXTR1: UCPD Rx Ordered Set Extension Register 1
func (o *UCPD_Type) SetRX_ORDEXTR1_RXSOPX1(value uint32) {
	volatile.StoreUint32(&o.RX_ORDEXTR1.Reg, volatile.LoadUint32(&o.RX_ORDEXTR1.Reg)&^(0xfffff)|value)
}
func (o *UCPD_Type) GetRX_ORDEXTR1_RXSOPX1() uint32 {
	return volatile.LoadUint32(&o.RX_ORDEXTR1.Reg) & 0xfffff
}

// UCPD.RX_ORDEXTR2: UCPD Rx Ordered Set Extension Register 2
func (o *UCPD_Type) SetRX_ORDEXTR2_RXSOPX2(value uint32) {
	volatile.StoreUint32(&o.RX_ORDEXTR2.Reg, volatile.LoadUint32(&o.RX_ORDEXTR2.Reg)&^(0xfffff)|value)
}
func (o *UCPD_Type) GetRX_ORDEXTR2_RXSOPX2() uint32 {
	return volatile.LoadUint32(&o.RX_ORDEXTR2.Reg) & 0xfffff
}

// Universal synchronous asynchronous receiver transmitter
type USART_Type struct {
	CR1    volatile.Register32 // 0x0
	CR2    volatile.Register32 // 0x4
	CR3    volatile.Register32 // 0x8
	BRR    volatile.Register32 // 0xC
	GTPR   volatile.Register32 // 0x10
	RTOR   volatile.Register32 // 0x14
	RQR    volatile.Register32 // 0x18
	ISR    volatile.Register32 // 0x1C
	ICR    volatile.Register32 // 0x20
	RDR    volatile.Register32 // 0x24
	TDR    volatile.Register32 // 0x28
	PRESC  volatile.Register32 // 0x2C
	AUTOCR volatile.Register32 // 0x30
}

// USART.CR1: Control register 1
func (o *USART_Type) SetCR1_M1(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR1_M1() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR1_EOBIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetCR1_EOBIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000000) >> 27
}
func (o *USART_Type) SetCR1_RTOIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetCR1_RTOIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetCR1_DEAT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x3e00000)|value<<21)
}
func (o *USART_Type) GetCR1_DEAT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x3e00000) >> 21
}
func (o *USART_Type) SetCR1_DEDT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *USART_Type) GetCR1_DEDT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1f0000) >> 16
}
func (o *USART_Type) SetCR1_OVER8(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR1_OVER8() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR1_CMIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR1_CMIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR1_MME(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR1_MME() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR1_M0(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR1_M0() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR1_WAKE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR1_WAKE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR1_PCE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR1_PCE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR1_PS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR1_PS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR1_PEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR1_PEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR1_TXEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR1_TXEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR1_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR1_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR1_IDLEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR1_IDLEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR1_TE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR1_TE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR1_RE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR1_RE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR1_UESM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCR1_UESM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCR1_UE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR1_UE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *USART_Type) SetCR1_FIFOEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000000)|value<<29)
}
func (o *USART_Type) GetCR1_FIFOEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000000) >> 29
}
func (o *USART_Type) SetCR1_TXFEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *USART_Type) GetCR1_TXFEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *USART_Type) SetCR1_RXFFIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000000)|value<<31)
}
func (o *USART_Type) GetCR1_RXFFIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000000) >> 31
}

// USART.CR2: Control register 2
func (o *USART_Type) SetCR2_ADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetCR2_ADD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff000000) >> 24
}
func (o *USART_Type) SetCR2_RTOEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR2_RTOEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR2_ABRMOD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x600000)|value<<21)
}
func (o *USART_Type) GetCR2_ABRMOD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x600000) >> 21
}
func (o *USART_Type) SetCR2_ABREN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetCR2_ABREN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetCR2_MSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetCR2_MSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetCR2_DATAINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetCR2_DATAINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetCR2_TXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetCR2_TXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetCR2_RXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetCR2_RXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetCR2_SWAP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR2_SWAP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR2_LINEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR2_LINEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3000)|value<<12)
}
func (o *USART_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x3000) >> 12
}
func (o *USART_Type) SetCR2_CLKEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR2_CLKEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR2_CPOL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR2_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR2_CPHA(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR2_CPHA() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR2_LBCL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR2_LBCL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR2_LBDIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR2_LBDIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR2_LBDL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR2_LBDL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR2_ADDM7(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR2_ADDM7() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR2_SLVEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR2_SLVEN() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *USART_Type) SetCR2_DIS_NSS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR2_DIS_NSS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}

// USART.CR3: Control register 3
func (o *USART_Type) SetCR3_SCARCNT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000)|value<<17)
}
func (o *USART_Type) GetCR3_SCARCNT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000) >> 17
}
func (o *USART_Type) SetCR3_DEP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR3_DEP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR3_DEM(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR3_DEM() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR3_DDRE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR3_DDRE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR3_OVRDIS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR3_OVRDIS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR3_ONEBIT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR3_ONEBIT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR3_CTSIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR3_CTSIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR3_CTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR3_CTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR3_RTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR3_RTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR3_DMAT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR3_DMAT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR3_DMAR(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR3_DMAR() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR3_SCEN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR3_SCEN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR3_NACK(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR3_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR3_HDSEL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR3_HDSEL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR3_IRLP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR3_IRLP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR3_IREN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCR3_IREN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCR3_EIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR3_EIE() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *USART_Type) SetCR3_TXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR3_TXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR3_TCBGTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetCR3_TCBGTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetCR3_RXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe000000)|value<<25)
}
func (o *USART_Type) GetCR3_RXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe000000) >> 25
}
func (o *USART_Type) SetCR3_RXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR3_RXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR3_TXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000000)|value<<29)
}
func (o *USART_Type) GetCR3_TXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000000) >> 29
}

// USART.BRR: Baud rate register
func (o *USART_Type) SetBRR(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetBRR() uint32 {
	return volatile.LoadUint32(&o.BRR.Reg) & 0xffff
}

// USART.GTPR: Guard time and prescaler register
func (o *USART_Type) SetGTPR_GT(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff00)|value<<8)
}
func (o *USART_Type) GetGTPR_GT() uint32 {
	return (volatile.LoadUint32(&o.GTPR.Reg) & 0xff00) >> 8
}
func (o *USART_Type) SetGTPR_PSC(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetGTPR_PSC() uint32 {
	return volatile.LoadUint32(&o.GTPR.Reg) & 0xff
}

// USART.RTOR: Receiver timeout register
func (o *USART_Type) SetRTOR_BLEN(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetRTOR_BLEN() uint32 {
	return (volatile.LoadUint32(&o.RTOR.Reg) & 0xff000000) >> 24
}
func (o *USART_Type) SetRTOR_RTO(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xffffff)|value)
}
func (o *USART_Type) GetRTOR_RTO() uint32 {
	return volatile.LoadUint32(&o.RTOR.Reg) & 0xffffff
}

// USART.RQR: Request register
func (o *USART_Type) SetRQR_TXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetRQR_TXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetRQR_RXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetRQR_RXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetRQR_MMRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetRQR_MMRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetRQR_SBKRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetRQR_SBKRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetRQR_ABRRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetRQR_ABRRQ() uint32 {
	return volatile.LoadUint32(&o.RQR.Reg) & 0x1
}

// USART.ISR: Interrupt & status register
func (o *USART_Type) SetISR_REACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *USART_Type) GetISR_REACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *USART_Type) SetISR_TEACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *USART_Type) GetISR_TEACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *USART_Type) SetISR_RWU(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetISR_RWU() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetISR_SBKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetISR_SBKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetISR_CMF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetISR_CMF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetISR_ABRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetISR_ABRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetISR_ABRE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetISR_ABRE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetISR_EOBF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetISR_EOBF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetISR_RTOF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetISR_RTOF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetISR_CTS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetISR_CTS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetISR_CTSIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetISR_CTSIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetISR_LBDF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetISR_LBDF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetISR_TXFNF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetISR_TXFNF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetISR_RXFNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetISR_RXFNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetISR_IDLE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetISR_IDLE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetISR_ORE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetISR_ORE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetISR_NE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetISR_NE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetISR_FE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetISR_FE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetISR_PE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetISR_PE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *USART_Type) SetISR_TXFE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetISR_TXFE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetISR_RXFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetISR_RXFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetISR_TCBGT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *USART_Type) GetISR_TCBGT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *USART_Type) SetISR_RXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetISR_RXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetISR_TXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetISR_TXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *USART_Type) SetISR_UDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetISR_UDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}

// USART.ICR: Interrupt flag clear register
func (o *USART_Type) SetICR_CMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetICR_CMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetICR_EOBCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetICR_EOBCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetICR_RTOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetICR_RTOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetICR_CTSCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetICR_CTSCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetICR_LBDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetICR_LBDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetICR_TCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetICR_TCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetICR_IDLECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetICR_IDLECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetICR_ORECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetICR_ORECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetICR_NECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetICR_NECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetICR_FECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetICR_FECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetICR_PECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetICR_PECF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *USART_Type) SetICR_TXFECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetICR_TXFECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetICR_TCBGTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetICR_TCBGTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetICR_UDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetICR_UDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}

// USART.RDR: Receive data register
func (o *USART_Type) SetRDR(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetRDR() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg) & 0x1ff
}

// USART.TDR: Transmit data register
func (o *USART_Type) SetTDR(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetTDR() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg) & 0x1ff
}

// USART.PRESC: PRESC
func (o *USART_Type) SetPRESC_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.PRESC.Reg, volatile.LoadUint32(&o.PRESC.Reg)&^(0xf)|value)
}
func (o *USART_Type) GetPRESC_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.PRESC.Reg) & 0xf
}

// USART.AUTOCR: AUTOCR
func (o *USART_Type) SetAUTOCR_TECLREN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x80000000)|value<<31)
}
func (o *USART_Type) GetAUTOCR_TECLREN() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x80000000) >> 31
}
func (o *USART_Type) SetAUTOCR_IDLEDIS(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetAUTOCR_IDLEDIS() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetAUTOCR_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x780000)|value<<19)
}
func (o *USART_Type) GetAUTOCR_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x780000) >> 19
}
func (o *USART_Type) SetAUTOCR_TRIGEN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetAUTOCR_TRIGEN() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetAUTOCR_TRIGPOL(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetAUTOCR_TRIGPOL() uint32 {
	return (volatile.LoadUint32(&o.AUTOCR.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetAUTOCR_TDN(value uint32) {
	volatile.StoreUint32(&o.AUTOCR.Reg, volatile.LoadUint32(&o.AUTOCR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetAUTOCR_TDN() uint32 {
	return volatile.LoadUint32(&o.AUTOCR.Reg) & 0xffff
}

// Voltage reference buffer
type VREF_Type struct {
	CSR volatile.Register32 // 0x0
	CCR volatile.Register32 // 0x4
}

// VREF.CSR: VREFBUF control and status register
func (o *VREF_Type) SetCSR_ENVR(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1)|value)
}
func (o *VREF_Type) GetCSR_ENVR() uint32 {
	return volatile.LoadUint32(&o.CSR.Reg) & 0x1
}
func (o *VREF_Type) SetCSR_HIZ(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *VREF_Type) GetCSR_HIZ() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *VREF_Type) SetCSR_VRR(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8)|value<<3)
}
func (o *VREF_Type) GetCSR_VRR() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8) >> 3
}
func (o *VREF_Type) SetCSR_VRS(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x70)|value<<4)
}
func (o *VREF_Type) GetCSR_VRS() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x70) >> 4
}

// VREF.CCR: VREFBUF calibration control register
func (o *VREF_Type) SetCCR_TRIM(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x3f)|value)
}
func (o *VREF_Type) GetCCR_TRIM() uint32 {
	return volatile.LoadUint32(&o.CCR.Reg) & 0x3f
}

// System window watchdog
type WWDG_Type struct {
	CR  volatile.Register32 // 0x0
	CFR volatile.Register32 // 0x4
	SR  volatile.Register32 // 0x8
}

// WWDG.CR: Control register
func (o *WWDG_Type) SetCR_WDGA(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *WWDG_Type) GetCR_WDGA() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *WWDG_Type) SetCR_T(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7f)|value)
}
func (o *WWDG_Type) GetCR_T() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x7f
}

// WWDG.CFR: Configuration register
func (o *WWDG_Type) SetCFR_WDGTB(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x3800)|value<<11)
}
func (o *WWDG_Type) GetCFR_WDGTB() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x3800) >> 11
}
func (o *WWDG_Type) SetCFR_EWI(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x200)|value<<9)
}
func (o *WWDG_Type) GetCFR_EWI() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x200) >> 9
}
func (o *WWDG_Type) SetCFR_W(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x7f)|value)
}
func (o *WWDG_Type) GetCFR_W() uint32 {
	return volatile.LoadUint32(&o.CFR.Reg) & 0x7f
}

// WWDG.SR: Status register
func (o *WWDG_Type) SetSR_EWIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *WWDG_Type) GetSR_EWIF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// Debug Control Block
type DCB_Type struct {
	DSCSR volatile.Register32 // 0x0
}

// DCB.DSCSR: Debug Security Control and Status Register
func (o *DCB_Type) SetDSCSR_CDS(value uint32) {
	volatile.StoreUint32(&o.DSCSR.Reg, volatile.LoadUint32(&o.DSCSR.Reg)&^(0x10000)|value<<16)
}
func (o *DCB_Type) GetDSCSR_CDS() uint32 {
	return (volatile.LoadUint32(&o.DSCSR.Reg) & 0x10000) >> 16
}

// Constants for ADC1: ADC1
const (
	// ISR: ADC interrupt and status register
	// Position of LDORDY field.
	ADC_ISR_LDORDY_Pos = 0xc
	// Bit mask of LDORDY field.
	ADC_ISR_LDORDY_Msk = 0x1000
	// Bit LDORDY.
	ADC_ISR_LDORDY = 0x1000
	// ADC voltage regulator disabled
	ADC_ISR_LDORDY_Disabled = 0x0
	// ADC voltage regulator enabled
	ADC_ISR_LDORDY_Enabled = 0x1
	// Position of AWD1 field.
	ADC_ISR_AWD1_Pos = 0x8
	// Bit mask of AWD1 field.
	ADC_ISR_AWD1_Msk = 0x100
	// Bit AWD1.
	ADC_ISR_AWD1 = 0x100
	// No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_AWD1_NoEvent = 0x0
	// Analog watchdog x event occurred
	ADC_ISR_AWD1_Event = 0x1
	// Clear the analog watchdog x event flag
	ADC_ISR_AWD1_Clear = 0x1
	// Position of AWD2 field.
	ADC_ISR_AWD2_Pos = 0x9
	// Bit mask of AWD2 field.
	ADC_ISR_AWD2_Msk = 0x200
	// Bit AWD2.
	ADC_ISR_AWD2 = 0x200
	// No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_AWD2_NoEvent = 0x0
	// Analog watchdog x event occurred
	ADC_ISR_AWD2_Event = 0x1
	// Clear the analog watchdog x event flag
	ADC_ISR_AWD2_Clear = 0x1
	// Position of AWD3 field.
	ADC_ISR_AWD3_Pos = 0xa
	// Bit mask of AWD3 field.
	ADC_ISR_AWD3_Msk = 0x400
	// Bit AWD3.
	ADC_ISR_AWD3 = 0x400
	// No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_AWD3_NoEvent = 0x0
	// Analog watchdog x event occurred
	ADC_ISR_AWD3_Event = 0x1
	// Clear the analog watchdog x event flag
	ADC_ISR_AWD3_Clear = 0x1
	// Position of JEOS field.
	ADC_ISR_JEOS_Pos = 0x6
	// Bit mask of JEOS field.
	ADC_ISR_JEOS_Msk = 0x40
	// Bit JEOS.
	ADC_ISR_JEOS = 0x40
	// Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_JEOS_NotComplete = 0x0
	// Injected conversions sequence complete
	ADC_ISR_JEOS_Complete = 0x1
	// Clear the injected conversion sequence flag
	ADC_ISR_JEOS_Clear = 0x1
	// Position of JEOC field.
	ADC_ISR_JEOC_Pos = 0x5
	// Bit mask of JEOC field.
	ADC_ISR_JEOC_Msk = 0x20
	// Bit JEOC.
	ADC_ISR_JEOC = 0x20
	// Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_JEOC_NotComplete = 0x0
	// Injected channel conversion complete
	ADC_ISR_JEOC_Complete = 0x1
	// Clear the injected channel conversion flag
	ADC_ISR_JEOC_Clear = 0x1
	// Position of OVR field.
	ADC_ISR_OVR_Pos = 0x4
	// Bit mask of OVR field.
	ADC_ISR_OVR_Msk = 0x10
	// Bit OVR.
	ADC_ISR_OVR = 0x10
	// No overrun occurred (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_OVR_NoOverrun = 0x0
	// Overrun has occurred
	ADC_ISR_OVR_Overrun = 0x1
	// Clear the overrun flag
	ADC_ISR_OVR_Clear = 0x1
	// Position of EOS field.
	ADC_ISR_EOS_Pos = 0x3
	// Bit mask of EOS field.
	ADC_ISR_EOS_Msk = 0x8
	// Bit EOS.
	ADC_ISR_EOS = 0x8
	// Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_EOS_NotComplete = 0x0
	// Regular conversions sequence complete
	ADC_ISR_EOS_Complete = 0x1
	// Clear the regular conversion sequence flag
	ADC_ISR_EOS_Clear = 0x1
	// Position of EOC field.
	ADC_ISR_EOC_Pos = 0x2
	// Bit mask of EOC field.
	ADC_ISR_EOC_Msk = 0x4
	// Bit EOC.
	ADC_ISR_EOC = 0x4
	// Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_EOC_NotComplete = 0x0
	// Regular channel conversion complete
	ADC_ISR_EOC_Complete = 0x1
	// Clear the regular channel conversion flag
	ADC_ISR_EOC_Clear = 0x1
	// Position of EOSMP field.
	ADC_ISR_EOSMP_Pos = 0x1
	// Bit mask of EOSMP field.
	ADC_ISR_EOSMP_Msk = 0x2
	// Bit EOSMP.
	ADC_ISR_EOSMP = 0x2
	// Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_EOSMP_NotAtEnd = 0x0
	// End of sampling phase reached
	ADC_ISR_EOSMP_AtEnd = 0x1
	// Clear the sampling phase flag
	ADC_ISR_EOSMP_Clear = 0x1
	// Position of ADRDY field.
	ADC_ISR_ADRDY_Pos = 0x0
	// Bit mask of ADRDY field.
	ADC_ISR_ADRDY_Msk = 0x1
	// Bit ADRDY.
	ADC_ISR_ADRDY = 0x1
	// ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
	ADC_ISR_ADRDY_NotReady = 0x0
	// ADC is ready to start conversion
	ADC_ISR_ADRDY_Ready = 0x1
	// Clear the ADC ready flag
	ADC_ISR_ADRDY_Clear = 0x1

	// IER: ADC interrupt enable register
	// Position of AWD1IE field.
	ADC_IER_AWD1IE_Pos = 0x8
	// Bit mask of AWD1IE field.
	ADC_IER_AWD1IE_Msk = 0x100
	// Bit AWD1IE.
	ADC_IER_AWD1IE = 0x100
	// Analog watchdog x interrupt disabled
	ADC_IER_AWD1IE_Disabled = 0x0
	// Analog watchdog x interrupt enabled
	ADC_IER_AWD1IE_Enabled = 0x1
	// Position of AWD2IE field.
	ADC_IER_AWD2IE_Pos = 0x9
	// Bit mask of AWD2IE field.
	ADC_IER_AWD2IE_Msk = 0x200
	// Bit AWD2IE.
	ADC_IER_AWD2IE = 0x200
	// Analog watchdog x interrupt disabled
	ADC_IER_AWD2IE_Disabled = 0x0
	// Analog watchdog x interrupt enabled
	ADC_IER_AWD2IE_Enabled = 0x1
	// Position of AWD3IE field.
	ADC_IER_AWD3IE_Pos = 0xa
	// Bit mask of AWD3IE field.
	ADC_IER_AWD3IE_Msk = 0x400
	// Bit AWD3IE.
	ADC_IER_AWD3IE = 0x400
	// Analog watchdog x interrupt disabled
	ADC_IER_AWD3IE_Disabled = 0x0
	// Analog watchdog x interrupt enabled
	ADC_IER_AWD3IE_Enabled = 0x1
	// Position of JEOSIE field.
	ADC_IER_JEOSIE_Pos = 0x6
	// Bit mask of JEOSIE field.
	ADC_IER_JEOSIE_Msk = 0x40
	// Bit JEOSIE.
	ADC_IER_JEOSIE = 0x40
	// JEOS interrupt disabled
	ADC_IER_JEOSIE_Disabled = 0x0
	// JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
	ADC_IER_JEOSIE_Enabled = 0x1
	// Position of JEOCIE field.
	ADC_IER_JEOCIE_Pos = 0x5
	// Bit mask of JEOCIE field.
	ADC_IER_JEOCIE_Msk = 0x20
	// Bit JEOCIE.
	ADC_IER_JEOCIE = 0x20
	// JEOC interrupt disable
	ADC_IER_JEOCIE_Disabled = 0x0
	// JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
	ADC_IER_JEOCIE_Enabled = 0x1
	// Position of OVRIE field.
	ADC_IER_OVRIE_Pos = 0x4
	// Bit mask of OVRIE field.
	ADC_IER_OVRIE_Msk = 0x10
	// Bit OVRIE.
	ADC_IER_OVRIE = 0x10
	// Overrun interrupt disabled
	ADC_IER_OVRIE_Disabled = 0x0
	// Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
	ADC_IER_OVRIE_Enabled = 0x1
	// Position of EOSIE field.
	ADC_IER_EOSIE_Pos = 0x3
	// Bit mask of EOSIE field.
	ADC_IER_EOSIE_Msk = 0x8
	// Bit EOSIE.
	ADC_IER_EOSIE = 0x8
	// EOS interrupt disabled
	ADC_IER_EOSIE_Disabled = 0x0
	// EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
	ADC_IER_EOSIE_Enabled = 0x1
	// Position of EOCIE field.
	ADC_IER_EOCIE_Pos = 0x2
	// Bit mask of EOCIE field.
	ADC_IER_EOCIE_Msk = 0x4
	// Bit EOCIE.
	ADC_IER_EOCIE = 0x4
	// EOC interrupt disabled
	ADC_IER_EOCIE_Disabled = 0x0
	// EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
	ADC_IER_EOCIE_Enabled = 0x1
	// Position of EOSMPIE field.
	ADC_IER_EOSMPIE_Pos = 0x1
	// Bit mask of EOSMPIE field.
	ADC_IER_EOSMPIE_Msk = 0x2
	// Bit EOSMPIE.
	ADC_IER_EOSMPIE = 0x2
	// EOSMP interrupt disabled
	ADC_IER_EOSMPIE_Disabled = 0x0
	// EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
	ADC_IER_EOSMPIE_Enabled = 0x1
	// Position of ADRDYIE field.
	ADC_IER_ADRDYIE_Pos = 0x0
	// Bit mask of ADRDYIE field.
	ADC_IER_ADRDYIE_Msk = 0x1
	// Bit ADRDYIE.
	ADC_IER_ADRDYIE = 0x1
	// ADRDY interrupt disabled
	ADC_IER_ADRDYIE_Disabled = 0x0
	// ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
	ADC_IER_ADRDYIE_Enabled = 0x1

	// CR: ADC control register
	// Position of ADCAL field.
	ADC_CR_ADCAL_Pos = 0x1f
	// Bit mask of ADCAL field.
	ADC_CR_ADCAL_Msk = 0x80000000
	// Bit ADCAL.
	ADC_CR_ADCAL = 0x80000000
	// Calibration complete
	ADC_CR_ADCAL_NotCalibrating = 0x0
	// Calibration in progress
	ADC_CR_ADCAL_Calibrating = 0x1
	// Calibrate the ADC
	ADC_CR_ADCAL_StartCalibration = 0x1
	// Position of DEEPPWD field.
	ADC_CR_DEEPPWD_Pos = 0x1d
	// Bit mask of DEEPPWD field.
	ADC_CR_DEEPPWD_Msk = 0x20000000
	// Bit DEEPPWD.
	ADC_CR_DEEPPWD = 0x20000000
	// ADC not in deep-power down
	ADC_CR_DEEPPWD_Disabled = 0x0
	// ADC in deep-power down
	ADC_CR_DEEPPWD_Enabled = 0x1
	// Position of ADVREGEN field.
	ADC_CR_ADVREGEN_Pos = 0x1c
	// Bit mask of ADVREGEN field.
	ADC_CR_ADVREGEN_Msk = 0x10000000
	// Bit ADVREGEN.
	ADC_CR_ADVREGEN = 0x10000000
	// ADC voltage regulator disabled
	ADC_CR_ADVREGEN_Disabled = 0x0
	// ADC voltage regulator enabled
	ADC_CR_ADVREGEN_Enabled = 0x1
	// Position of CALINDEX field.
	ADC_CR_CALINDEX_Pos = 0x18
	// Bit mask of CALINDEX field.
	ADC_CR_CALINDEX_Msk = 0xf000000
	// Offset calibration factor
	ADC_CR_CALINDEX_OffsetCalFactor = 0x0
	// Calibration factor 1
	ADC_CR_CALINDEX_CalFactor1 = 0x1
	// Calibration factor 2
	ADC_CR_CALINDEX_CalFactor2 = 0x2
	// Calibration factor 3
	ADC_CR_CALINDEX_CalFactor3 = 0x3
	// Calibration factor 4
	ADC_CR_CALINDEX_CalFactor4 = 0x4
	// Calibration factor 5
	ADC_CR_CALINDEX_CalFactor5 = 0x5
	// Calibration factor 6
	ADC_CR_CALINDEX_CalFactor6 = 0x6
	// Calibration factor 7 and (write access only) internal offset
	ADC_CR_CALINDEX_CalFactor7 = 0x7
	// Internal offset (read access only)
	ADC_CR_CALINDEX_InternalOffset = 0x8
	// Calibration mode selection
	ADC_CR_CALINDEX_CalibrationMode = 0x9
	// Position of ADCALLIN field.
	ADC_CR_ADCALLIN_Pos = 0x10
	// Bit mask of ADCALLIN field.
	ADC_CR_ADCALLIN_Msk = 0x10000
	// Bit ADCALLIN.
	ADC_CR_ADCALLIN = 0x10000
	// Writing ADCAL launches a calibration without the linearity calibration
	ADC_CR_ADCALLIN_Disabled = 0x0
	// Writing ADCAL launches a calibration with he linearity calibration
	ADC_CR_ADCALLIN_Enabled = 0x1
	// Position of JADSTP field.
	ADC_CR_JADSTP_Pos = 0x5
	// Bit mask of JADSTP field.
	ADC_CR_JADSTP_Msk = 0x20
	// Bit JADSTP.
	ADC_CR_JADSTP = 0x20
	// No ADC stop injected conversion command ongoing
	ADC_CR_JADSTP_NotStopped = 0x0
	// ADSTP command is in progress
	ADC_CR_JADSTP_Stopped = 0x1
	// Stop injected conversions ongoing
	ADC_CR_JADSTP_Stop = 0x1
	// Position of ADSTP field.
	ADC_CR_ADSTP_Pos = 0x4
	// Bit mask of ADSTP field.
	ADC_CR_ADSTP_Msk = 0x10
	// Bit ADSTP.
	ADC_CR_ADSTP = 0x10
	// No ADC stop regular conversion command ongoing
	ADC_CR_ADSTP_NotStopping = 0x0
	// ADSTP command is in progress
	ADC_CR_ADSTP_Stopping = 0x1
	// Stop regular conversions ongoing
	ADC_CR_ADSTP_StopConversion = 0x1
	// Position of JADSTART field.
	ADC_CR_JADSTART_Pos = 0x3
	// Bit mask of JADSTART field.
	ADC_CR_JADSTART_Msk = 0x8
	// Bit JADSTART.
	ADC_CR_JADSTART = 0x8
	// No ADC injected conversion is ongoing
	ADC_CR_JADSTART_NotActive = 0x0
	// ADC is operating and eventually converting an injected channel
	ADC_CR_JADSTART_Active = 0x1
	// Start injected conversions
	ADC_CR_JADSTART_Start = 0x1
	// Position of ADSTART field.
	ADC_CR_ADSTART_Pos = 0x2
	// Bit mask of ADSTART field.
	ADC_CR_ADSTART_Msk = 0x4
	// Bit ADSTART.
	ADC_CR_ADSTART = 0x4
	// No ADC regular conversion is ongoing
	ADC_CR_ADSTART_NotActive = 0x0
	// ADC is operating and eventually converting a regular channel
	ADC_CR_ADSTART_Active = 0x1
	// Start regular conversions
	ADC_CR_ADSTART_Start = 0x1
	// Position of ADDIS field.
	ADC_CR_ADDIS_Pos = 0x1
	// Bit mask of ADDIS field.
	ADC_CR_ADDIS_Msk = 0x2
	// Bit ADDIS.
	ADC_CR_ADDIS = 0x2
	// No ADDIS command ongoing
	ADC_CR_ADDIS_NotOngoing = 0x0
	// An ADDIS command is in progress
	ADC_CR_ADDIS_InProgress = 0x1
	// Disable the ADC
	ADC_CR_ADDIS_Disable = 0x1
	// Position of ADEN field.
	ADC_CR_ADEN_Pos = 0x0
	// Bit mask of ADEN field.
	ADC_CR_ADEN_Msk = 0x1
	// Bit ADEN.
	ADC_CR_ADEN = 0x1
	// ADC is disabled
	ADC_CR_ADEN_Disabled = 0x0
	// ADC is enabled
	ADC_CR_ADEN_Enabled = 0x1

	// CFGR1: ADC configuration register
	// Position of AWD1CH field.
	ADC_CFGR1_AWD1CH_Pos = 0x1a
	// Bit mask of AWD1CH field.
	ADC_CFGR1_AWD1CH_Msk = 0x7c000000
	// Position of JAUTO field.
	ADC_CFGR1_JAUTO_Pos = 0x19
	// Bit mask of JAUTO field.
	ADC_CFGR1_JAUTO_Msk = 0x2000000
	// Bit JAUTO.
	ADC_CFGR1_JAUTO = 0x2000000
	// Automatic injected group conversion disabled
	ADC_CFGR1_JAUTO_Disabled = 0x0
	// Automatic injected group conversion enabled
	ADC_CFGR1_JAUTO_Enabled = 0x1
	// Position of JAWD1EN field.
	ADC_CFGR1_JAWD1EN_Pos = 0x18
	// Bit mask of JAWD1EN field.
	ADC_CFGR1_JAWD1EN_Msk = 0x1000000
	// Bit JAWD1EN.
	ADC_CFGR1_JAWD1EN = 0x1000000
	// Analog watchdog 1 disabled on injected channels
	ADC_CFGR1_JAWD1EN_Disabled = 0x0
	// Analog watchdog 1 enabled on injected channels
	ADC_CFGR1_JAWD1EN_Enabled = 0x1
	// Position of AWD1EN field.
	ADC_CFGR1_AWD1EN_Pos = 0x17
	// Bit mask of AWD1EN field.
	ADC_CFGR1_AWD1EN_Msk = 0x800000
	// Bit AWD1EN.
	ADC_CFGR1_AWD1EN = 0x800000
	// Analog watchdog 1 disabled on regular channels
	ADC_CFGR1_AWD1EN_Disabled = 0x0
	// Analog watchdog 1 enabled on regular channels
	ADC_CFGR1_AWD1EN_Enabled = 0x1
	// Position of AWD1SGL field.
	ADC_CFGR1_AWD1SGL_Pos = 0x16
	// Bit mask of AWD1SGL field.
	ADC_CFGR1_AWD1SGL_Msk = 0x400000
	// Bit AWD1SGL.
	ADC_CFGR1_AWD1SGL = 0x400000
	// Analog watchdog 1 enabled on all channels
	ADC_CFGR1_AWD1SGL_AllChannels = 0x0
	// Analog watchdog 1 enabled on a single channel
	ADC_CFGR1_AWD1SGL_SingleChannel = 0x1
	// Position of JDISCEN field.
	ADC_CFGR1_JDISCEN_Pos = 0x14
	// Bit mask of JDISCEN field.
	ADC_CFGR1_JDISCEN_Msk = 0x100000
	// Bit JDISCEN.
	ADC_CFGR1_JDISCEN = 0x100000
	// Discontinuous mode on injected channels disabled
	ADC_CFGR1_JDISCEN_Disabled = 0x0
	// Discontinuous mode on injected channels enabled
	ADC_CFGR1_JDISCEN_Enabled = 0x1
	// Position of DISCNUM field.
	ADC_CFGR1_DISCNUM_Pos = 0x11
	// Bit mask of DISCNUM field.
	ADC_CFGR1_DISCNUM_Msk = 0xe0000
	// 1 channel
	ADC_CFGR1_DISCNUM_N1 = 0x0
	// 2 channels
	ADC_CFGR1_DISCNUM_N2 = 0x1
	// 3 channels
	ADC_CFGR1_DISCNUM_N3 = 0x2
	// 4 channels
	ADC_CFGR1_DISCNUM_N4 = 0x3
	// 5 channels
	ADC_CFGR1_DISCNUM_N5 = 0x4
	// 6 channels
	ADC_CFGR1_DISCNUM_N6 = 0x5
	// 7 channels
	ADC_CFGR1_DISCNUM_N7 = 0x6
	// 8 channels
	ADC_CFGR1_DISCNUM_N8 = 0x7
	// Position of DISCEN field.
	ADC_CFGR1_DISCEN_Pos = 0x10
	// Bit mask of DISCEN field.
	ADC_CFGR1_DISCEN_Msk = 0x10000
	// Bit DISCEN.
	ADC_CFGR1_DISCEN = 0x10000
	// Discontinuous mode for regular channels disabled
	ADC_CFGR1_DISCEN_Disabled = 0x0
	// Discontinuous mode for regular channels enabled
	ADC_CFGR1_DISCEN_Enabled = 0x1
	// Position of AUTDLY field.
	ADC_CFGR1_AUTDLY_Pos = 0xe
	// Bit mask of AUTDLY field.
	ADC_CFGR1_AUTDLY_Msk = 0x4000
	// Bit AUTDLY.
	ADC_CFGR1_AUTDLY = 0x4000
	// Auto-delayed conversion mode off
	ADC_CFGR1_AUTDLY_Disabled = 0x0
	// Auto-delayed conversion mode on
	ADC_CFGR1_AUTDLY_Enabled = 0x1
	// Position of CONT field.
	ADC_CFGR1_CONT_Pos = 0xd
	// Bit mask of CONT field.
	ADC_CFGR1_CONT_Msk = 0x2000
	// Bit CONT.
	ADC_CFGR1_CONT = 0x2000
	// Single conversion mode
	ADC_CFGR1_CONT_Single = 0x0
	// Continuous conversion mode
	ADC_CFGR1_CONT_Continuous = 0x1
	// Position of OVRMOD field.
	ADC_CFGR1_OVRMOD_Pos = 0xc
	// Bit mask of OVRMOD field.
	ADC_CFGR1_OVRMOD_Msk = 0x1000
	// Bit OVRMOD.
	ADC_CFGR1_OVRMOD = 0x1000
	// ADC_DR register is preserved with the old data when an overrun is detected
	ADC_CFGR1_OVRMOD_Preserve = 0x0
	// ADC_DR register is overwritten with the last conversion result when an overrun is detected
	ADC_CFGR1_OVRMOD_Overwrite = 0x1
	// Position of EXTEN field.
	ADC_CFGR1_EXTEN_Pos = 0xa
	// Bit mask of EXTEN field.
	ADC_CFGR1_EXTEN_Msk = 0xc00
	// Hardware trigger detection disabled (conversions can be launched by software)
	ADC_CFGR1_EXTEN_Disabled = 0x0
	// Hardware trigger detection on the rising edge
	ADC_CFGR1_EXTEN_RisingEdge = 0x1
	// Hardware trigger detection on the falling edge
	ADC_CFGR1_EXTEN_FallingEdge = 0x2
	// Hardware trigger detection on both the rising and falling edges
	ADC_CFGR1_EXTEN_BothEdges = 0x3
	// Position of EXTSEL field.
	ADC_CFGR1_EXTSEL_Pos = 0x5
	// Bit mask of EXTSEL field.
	ADC_CFGR1_EXTSEL_Msk = 0x3e0
	// tim1_oc1
	ADC_CFGR1_EXTSEL_TIM1_OC1 = 0x0
	// tim1_oc2
	ADC_CFGR1_EXTSEL_TIM1_OC2 = 0x1
	// tim1_oc3
	ADC_CFGR1_EXTSEL_TIM1_OC3 = 0x2
	// tim2_oc2
	ADC_CFGR1_EXTSEL_TIM2_OC2 = 0x3
	// tim3_trgo
	ADC_CFGR1_EXTSEL_TIM3_TRGO = 0x4
	// tim4_oc4
	ADC_CFGR1_EXTSEL_TIM4_OC4 = 0x5
	// exti11
	ADC_CFGR1_EXTSEL_EXTI11 = 0x6
	// tim8_trgo
	ADC_CFGR1_EXTSEL_TIM8_TRGO = 0x7
	// tim8_trgo2
	ADC_CFGR1_EXTSEL_TIM8_TRGO2 = 0x8
	// tim1_trgo
	ADC_CFGR1_EXTSEL_TIM1_TRGO = 0x9
	// tim1_trgo2
	ADC_CFGR1_EXTSEL_TIM1_TRGO2 = 0xa
	// tim2_trgo
	ADC_CFGR1_EXTSEL_TIM2_TRGO = 0xb
	// tim4_trgo
	ADC_CFGR1_EXTSEL_TIM4_TRGO = 0xc
	// tim6_trgo
	ADC_CFGR1_EXTSEL_TIM6_TRGO = 0xd
	// tim15_trgo
	ADC_CFGR1_EXTSEL_TIM15_TRGO = 0xe
	// tim3_oc4
	ADC_CFGR1_EXTSEL_TIM3_OC4 = 0xf
	// exti15
	ADC_CFGR1_EXTSEL_EXTI15 = 0x10
	// lptim1_ch1
	ADC_CFGR1_EXTSEL_LPTIM1_CH1 = 0x12
	// lptim2_ch1
	ADC_CFGR1_EXTSEL_LPTIM2_CH1 = 0x13
	// lptim3_ch1
	ADC_CFGR1_EXTSEL_LPTIM3_CH1 = 0x14
	// lptim4_out
	ADC_CFGR1_EXTSEL_LPTIM4_OUT = 0x15
	// Position of RES field.
	ADC_CFGR1_RES_Pos = 0x2
	// Bit mask of RES field.
	ADC_CFGR1_RES_Msk = 0xc
	// 14 bits
	ADC_CFGR1_RES_FourteenBit = 0x0
	// 12 bits
	ADC_CFGR1_RES_TwelveBit = 0x1
	// 10 bits
	ADC_CFGR1_RES_TenBit = 0x2
	// 8 bits
	ADC_CFGR1_RES_EightBit = 0x3
	// Position of DMNGT field.
	ADC_CFGR1_DMNGT_Pos = 0x0
	// Bit mask of DMNGT field.
	ADC_CFGR1_DMNGT_Msk = 0x3
	// Store output data in DR only
	ADC_CFGR1_DMNGT_DR = 0x0
	// DMA One Shot Mode selected
	ADC_CFGR1_DMNGT_DMA_OneShot = 0x1
	// DFSDM mode selected
	ADC_CFGR1_DMNGT_DFSDM = 0x2
	// DMA Circular Mode selected
	ADC_CFGR1_DMNGT_DMA_Circular = 0x3

	// CFGR2: ADC configuration register 2
	// Position of LSHIFT field.
	ADC_CFGR2_LSHIFT_Pos = 0x1c
	// Bit mask of LSHIFT field.
	ADC_CFGR2_LSHIFT_Msk = 0xf0000000
	// Position of LFTRIG field.
	ADC_CFGR2_LFTRIG_Pos = 0x1b
	// Bit mask of LFTRIG field.
	ADC_CFGR2_LFTRIG_Msk = 0x8000000
	// Bit LFTRIG.
	ADC_CFGR2_LFTRIG = 0x8000000
	// Low-frequency trigger mode disabled
	ADC_CFGR2_LFTRIG_Disabled = 0x0
	// Low-frequency trigger mode enabled
	ADC_CFGR2_LFTRIG_Enabled = 0x1
	// Position of OSR field.
	ADC_CFGR2_OSR_Pos = 0x10
	// Bit mask of OSR field.
	ADC_CFGR2_OSR_Msk = 0x3ff0000
	// Position of SMPTRIG field.
	ADC_CFGR2_SMPTRIG_Pos = 0xf
	// Bit mask of SMPTRIG field.
	ADC_CFGR2_SMPTRIG_Msk = 0x8000
	// Bit SMPTRIG.
	ADC_CFGR2_SMPTRIG = 0x8000
	// Sampling time control trigger mode disabled
	ADC_CFGR2_SMPTRIG_Disabled = 0x0
	// Sampling time control trigger mode enabled
	ADC_CFGR2_SMPTRIG_Enabled = 0x1
	// Position of SWTRIG field.
	ADC_CFGR2_SWTRIG_Pos = 0xe
	// Bit mask of SWTRIG field.
	ADC_CFGR2_SWTRIG_Msk = 0x4000
	// Bit SWTRIG.
	ADC_CFGR2_SWTRIG = 0x4000
	// Software trigger starts the conversion for sampling time control trigger mode
	ADC_CFGR2_SWTRIG_Disabled = 0x0
	// Software trigger starts the sampling for sampling time control trigger mode
	ADC_CFGR2_SWTRIG_Enabled = 0x1
	// Position of BULB field.
	ADC_CFGR2_BULB_Pos = 0xd
	// Bit mask of BULB field.
	ADC_CFGR2_BULB_Msk = 0x2000
	// Bit BULB.
	ADC_CFGR2_BULB = 0x2000
	// Bulb sampling mode disabled
	ADC_CFGR2_BULB_Disabled = 0x0
	// Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion.
	ADC_CFGR2_BULB_Enabled = 0x1
	// Position of ROVSM field.
	ADC_CFGR2_ROVSM_Pos = 0xa
	// Bit mask of ROVSM field.
	ADC_CFGR2_ROVSM_Msk = 0x400
	// Bit ROVSM.
	ADC_CFGR2_ROVSM = 0x400
	// When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
	ADC_CFGR2_ROVSM_Continued = 0x0
	// When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
	ADC_CFGR2_ROVSM_Resumed = 0x1
	// Position of TROVS field.
	ADC_CFGR2_TROVS_Pos = 0x9
	// Bit mask of TROVS field.
	ADC_CFGR2_TROVS_Msk = 0x200
	// Bit TROVS.
	ADC_CFGR2_TROVS = 0x200
	// All oversampled conversions for a channel are done consecutively following a trigger
	ADC_CFGR2_TROVS_Automatic = 0x0
	// Each oversampled conversion for a channel needs a new trigger
	ADC_CFGR2_TROVS_Triggered = 0x1
	// Position of OVSS field.
	ADC_CFGR2_OVSS_Pos = 0x5
	// Bit mask of OVSS field.
	ADC_CFGR2_OVSS_Msk = 0x1e0
	// Position of JOVSE field.
	ADC_CFGR2_JOVSE_Pos = 0x1
	// Bit mask of JOVSE field.
	ADC_CFGR2_JOVSE_Msk = 0x2
	// Bit JOVSE.
	ADC_CFGR2_JOVSE = 0x2
	// Injected oversampling disabled
	ADC_CFGR2_JOVSE_Disabled = 0x0
	// Injected oversampling enabled
	ADC_CFGR2_JOVSE_Enabled = 0x1
	// Position of ROVSE field.
	ADC_CFGR2_ROVSE_Pos = 0x0
	// Bit mask of ROVSE field.
	ADC_CFGR2_ROVSE_Msk = 0x1
	// Bit ROVSE.
	ADC_CFGR2_ROVSE = 0x1
	// Regular oversampling disabled
	ADC_CFGR2_ROVSE_Disabled = 0x0
	// Regular oversampling enabled
	ADC_CFGR2_ROVSE_Enabled = 0x1

	// SMPR1: ADC sample time register 1
	// Position of SMP0 field.
	ADC_SMPR1_SMP0_Pos = 0x3
	// Bit mask of SMP0 field.
	ADC_SMPR1_SMP0_Msk = 0x38
	// 5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles814 = 0x7
	// Position of SMP1 field.
	ADC_SMPR1_SMP1_Pos = 0x6
	// Bit mask of SMP1 field.
	ADC_SMPR1_SMP1_Msk = 0x1c0
	// 5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles814 = 0x7
	// Position of SMP2 field.
	ADC_SMPR1_SMP2_Pos = 0x9
	// Bit mask of SMP2 field.
	ADC_SMPR1_SMP2_Msk = 0xe00
	// 5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles814 = 0x7
	// Position of SMP3 field.
	ADC_SMPR1_SMP3_Pos = 0xc
	// Bit mask of SMP3 field.
	ADC_SMPR1_SMP3_Msk = 0x7000
	// 5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles814 = 0x7
	// Position of SMP4 field.
	ADC_SMPR1_SMP4_Pos = 0xf
	// Bit mask of SMP4 field.
	ADC_SMPR1_SMP4_Msk = 0x38000
	// 5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles814 = 0x7
	// Position of SMP5 field.
	ADC_SMPR1_SMP5_Pos = 0x12
	// Bit mask of SMP5 field.
	ADC_SMPR1_SMP5_Msk = 0x1c0000
	// 5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles814 = 0x7
	// Position of SMP6 field.
	ADC_SMPR1_SMP6_Pos = 0x15
	// Bit mask of SMP6 field.
	ADC_SMPR1_SMP6_Msk = 0xe00000
	// 5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles814 = 0x7
	// Position of SMP7 field.
	ADC_SMPR1_SMP7_Pos = 0x18
	// Bit mask of SMP7 field.
	ADC_SMPR1_SMP7_Msk = 0x7000000
	// 5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles814 = 0x7
	// Position of SMP8 field.
	ADC_SMPR1_SMP8_Pos = 0x1b
	// Bit mask of SMP8 field.
	ADC_SMPR1_SMP8_Msk = 0x38000000
	// 5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles814 = 0x7
	// Position of SMP9 field.
	ADC_SMPR1_SMP9_Pos = 0x1e
	// Bit mask of SMP9 field.
	ADC_SMPR1_SMP9_Msk = 0x1c0000000
	// 5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles814 = 0x7

	// SMPR2: ADC sample time register 2
	// Position of SMP10 field.
	ADC_SMPR2_SMP10_Pos = 0x3
	// Bit mask of SMP10 field.
	ADC_SMPR2_SMP10_Msk = 0x38
	// 5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles814 = 0x7
	// Position of SMP11 field.
	ADC_SMPR2_SMP11_Pos = 0x6
	// Bit mask of SMP11 field.
	ADC_SMPR2_SMP11_Msk = 0x1c0
	// 5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles814 = 0x7
	// Position of SMP12 field.
	ADC_SMPR2_SMP12_Pos = 0x9
	// Bit mask of SMP12 field.
	ADC_SMPR2_SMP12_Msk = 0xe00
	// 5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles814 = 0x7
	// Position of SMP13 field.
	ADC_SMPR2_SMP13_Pos = 0xc
	// Bit mask of SMP13 field.
	ADC_SMPR2_SMP13_Msk = 0x7000
	// 5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles814 = 0x7
	// Position of SMP14 field.
	ADC_SMPR2_SMP14_Pos = 0xf
	// Bit mask of SMP14 field.
	ADC_SMPR2_SMP14_Msk = 0x38000
	// 5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles814 = 0x7
	// Position of SMP15 field.
	ADC_SMPR2_SMP15_Pos = 0x12
	// Bit mask of SMP15 field.
	ADC_SMPR2_SMP15_Msk = 0x1c0000
	// 5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles814 = 0x7
	// Position of SMP16 field.
	ADC_SMPR2_SMP16_Pos = 0x15
	// Bit mask of SMP16 field.
	ADC_SMPR2_SMP16_Msk = 0xe00000
	// 5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles814 = 0x7
	// Position of SMP17 field.
	ADC_SMPR2_SMP17_Pos = 0x18
	// Bit mask of SMP17 field.
	ADC_SMPR2_SMP17_Msk = 0x7000000
	// 5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles814 = 0x7
	// Position of SMP18 field.
	ADC_SMPR2_SMP18_Pos = 0x1b
	// Bit mask of SMP18 field.
	ADC_SMPR2_SMP18_Msk = 0x38000000
	// 5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles814 = 0x7
	// Position of SMP19 field.
	ADC_SMPR2_SMP19_Pos = 0x1e
	// Bit mask of SMP19 field.
	ADC_SMPR2_SMP19_Msk = 0x1c0000000
	// 5 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles5 = 0x0
	// 6 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles6 = 0x1
	// 12 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles12 = 0x2
	// 20 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles20 = 0x3
	// 36 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles36 = 0x4
	// 68 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles68 = 0x5
	// 391 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles391 = 0x6
	// 814 ADC clock cycles
	ADC_SMPR2_SMP19_Cycles814 = 0x7

	// PCSEL: ADC channel preselection register
	// Position of PCSEL0 field.
	ADC_PCSEL_PCSEL0_Pos = 0x0
	// Bit mask of PCSEL0 field.
	ADC_PCSEL_PCSEL0_Msk = 0x1
	// Bit PCSEL0.
	ADC_PCSEL_PCSEL0 = 0x1
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL0_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL0_Preselected = 0x1
	// Position of PCSEL19 field.
	ADC_PCSEL_PCSEL19_Pos = 0x13
	// Bit mask of PCSEL19 field.
	ADC_PCSEL_PCSEL19_Msk = 0x80000
	// Bit PCSEL19.
	ADC_PCSEL_PCSEL19 = 0x80000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL19_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL19_Preselected = 0x1
	// Position of PCSEL18 field.
	ADC_PCSEL_PCSEL18_Pos = 0x12
	// Bit mask of PCSEL18 field.
	ADC_PCSEL_PCSEL18_Msk = 0x40000
	// Bit PCSEL18.
	ADC_PCSEL_PCSEL18 = 0x40000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL18_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL18_Preselected = 0x1
	// Position of PCSEL17 field.
	ADC_PCSEL_PCSEL17_Pos = 0x11
	// Bit mask of PCSEL17 field.
	ADC_PCSEL_PCSEL17_Msk = 0x20000
	// Bit PCSEL17.
	ADC_PCSEL_PCSEL17 = 0x20000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL17_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL17_Preselected = 0x1
	// Position of PCSEL16 field.
	ADC_PCSEL_PCSEL16_Pos = 0x10
	// Bit mask of PCSEL16 field.
	ADC_PCSEL_PCSEL16_Msk = 0x10000
	// Bit PCSEL16.
	ADC_PCSEL_PCSEL16 = 0x10000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL16_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL16_Preselected = 0x1
	// Position of PCSEL15 field.
	ADC_PCSEL_PCSEL15_Pos = 0xf
	// Bit mask of PCSEL15 field.
	ADC_PCSEL_PCSEL15_Msk = 0x8000
	// Bit PCSEL15.
	ADC_PCSEL_PCSEL15 = 0x8000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL15_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL15_Preselected = 0x1
	// Position of PCSEL14 field.
	ADC_PCSEL_PCSEL14_Pos = 0xe
	// Bit mask of PCSEL14 field.
	ADC_PCSEL_PCSEL14_Msk = 0x4000
	// Bit PCSEL14.
	ADC_PCSEL_PCSEL14 = 0x4000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL14_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL14_Preselected = 0x1
	// Position of PCSEL13 field.
	ADC_PCSEL_PCSEL13_Pos = 0xd
	// Bit mask of PCSEL13 field.
	ADC_PCSEL_PCSEL13_Msk = 0x2000
	// Bit PCSEL13.
	ADC_PCSEL_PCSEL13 = 0x2000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL13_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL13_Preselected = 0x1
	// Position of PCSEL12 field.
	ADC_PCSEL_PCSEL12_Pos = 0xc
	// Bit mask of PCSEL12 field.
	ADC_PCSEL_PCSEL12_Msk = 0x1000
	// Bit PCSEL12.
	ADC_PCSEL_PCSEL12 = 0x1000
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL12_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL12_Preselected = 0x1
	// Position of PCSEL11 field.
	ADC_PCSEL_PCSEL11_Pos = 0xb
	// Bit mask of PCSEL11 field.
	ADC_PCSEL_PCSEL11_Msk = 0x800
	// Bit PCSEL11.
	ADC_PCSEL_PCSEL11 = 0x800
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL11_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL11_Preselected = 0x1
	// Position of PCSEL10 field.
	ADC_PCSEL_PCSEL10_Pos = 0xa
	// Bit mask of PCSEL10 field.
	ADC_PCSEL_PCSEL10_Msk = 0x400
	// Bit PCSEL10.
	ADC_PCSEL_PCSEL10 = 0x400
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL10_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL10_Preselected = 0x1
	// Position of PCSEL9 field.
	ADC_PCSEL_PCSEL9_Pos = 0x9
	// Bit mask of PCSEL9 field.
	ADC_PCSEL_PCSEL9_Msk = 0x200
	// Bit PCSEL9.
	ADC_PCSEL_PCSEL9 = 0x200
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL9_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL9_Preselected = 0x1
	// Position of PCSEL8 field.
	ADC_PCSEL_PCSEL8_Pos = 0x8
	// Bit mask of PCSEL8 field.
	ADC_PCSEL_PCSEL8_Msk = 0x100
	// Bit PCSEL8.
	ADC_PCSEL_PCSEL8 = 0x100
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL8_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL8_Preselected = 0x1
	// Position of PCSEL7 field.
	ADC_PCSEL_PCSEL7_Pos = 0x7
	// Bit mask of PCSEL7 field.
	ADC_PCSEL_PCSEL7_Msk = 0x80
	// Bit PCSEL7.
	ADC_PCSEL_PCSEL7 = 0x80
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL7_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL7_Preselected = 0x1
	// Position of PCSEL6 field.
	ADC_PCSEL_PCSEL6_Pos = 0x6
	// Bit mask of PCSEL6 field.
	ADC_PCSEL_PCSEL6_Msk = 0x40
	// Bit PCSEL6.
	ADC_PCSEL_PCSEL6 = 0x40
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL6_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL6_Preselected = 0x1
	// Position of PCSEL5 field.
	ADC_PCSEL_PCSEL5_Pos = 0x5
	// Bit mask of PCSEL5 field.
	ADC_PCSEL_PCSEL5_Msk = 0x20
	// Bit PCSEL5.
	ADC_PCSEL_PCSEL5 = 0x20
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL5_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL5_Preselected = 0x1
	// Position of PCSEL4 field.
	ADC_PCSEL_PCSEL4_Pos = 0x4
	// Bit mask of PCSEL4 field.
	ADC_PCSEL_PCSEL4_Msk = 0x10
	// Bit PCSEL4.
	ADC_PCSEL_PCSEL4 = 0x10
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL4_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL4_Preselected = 0x1
	// Position of PCSEL3 field.
	ADC_PCSEL_PCSEL3_Pos = 0x3
	// Bit mask of PCSEL3 field.
	ADC_PCSEL_PCSEL3_Msk = 0x8
	// Bit PCSEL3.
	ADC_PCSEL_PCSEL3 = 0x8
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL3_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL3_Preselected = 0x1
	// Position of PCSEL2 field.
	ADC_PCSEL_PCSEL2_Pos = 0x2
	// Bit mask of PCSEL2 field.
	ADC_PCSEL_PCSEL2_Msk = 0x4
	// Bit PCSEL2.
	ADC_PCSEL_PCSEL2 = 0x4
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL2_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL2_Preselected = 0x1
	// Position of PCSEL1 field.
	ADC_PCSEL_PCSEL1_Pos = 0x1
	// Bit mask of PCSEL1 field.
	ADC_PCSEL_PCSEL1_Msk = 0x2
	// Bit PCSEL1.
	ADC_PCSEL_PCSEL1 = 0x2
	// Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result.
	ADC_PCSEL_PCSEL1_NotPreselected = 0x0
	// Input channel x is preselected for conversion
	ADC_PCSEL_PCSEL1_Preselected = 0x1

	// SQR1: ADC regular sequence register 1
	// Position of SQ1 field.
	ADC_SQR1_SQ1_Pos = 0xc
	// Bit mask of SQ1 field.
	ADC_SQR1_SQ1_Msk = 0x1f000
	// Position of SQ2 field.
	ADC_SQR1_SQ2_Pos = 0x12
	// Bit mask of SQ2 field.
	ADC_SQR1_SQ2_Msk = 0x7c0000
	// Position of SQ3 field.
	ADC_SQR1_SQ3_Pos = 0x18
	// Bit mask of SQ3 field.
	ADC_SQR1_SQ3_Msk = 0x1f000000
	// Position of SQ4 field.
	ADC_SQR1_SQ4_Pos = 0x1e
	// Bit mask of SQ4 field.
	ADC_SQR1_SQ4_Msk = 0x7c0000000
	// Position of L field.
	ADC_SQR1_L_Pos = 0x0
	// Bit mask of L field.
	ADC_SQR1_L_Msk = 0xf

	// SQR2: ADC regular sequence register 2
	// Position of SQ5 field.
	ADC_SQR2_SQ5_Pos = 0x6
	// Bit mask of SQ5 field.
	ADC_SQR2_SQ5_Msk = 0x7c0
	// Position of SQ6 field.
	ADC_SQR2_SQ6_Pos = 0xc
	// Bit mask of SQ6 field.
	ADC_SQR2_SQ6_Msk = 0x1f000
	// Position of SQ7 field.
	ADC_SQR2_SQ7_Pos = 0x12
	// Bit mask of SQ7 field.
	ADC_SQR2_SQ7_Msk = 0x7c0000
	// Position of SQ8 field.
	ADC_SQR2_SQ8_Pos = 0x18
	// Bit mask of SQ8 field.
	ADC_SQR2_SQ8_Msk = 0x1f000000
	// Position of SQ9 field.
	ADC_SQR2_SQ9_Pos = 0x1e
	// Bit mask of SQ9 field.
	ADC_SQR2_SQ9_Msk = 0x7c0000000

	// SQR3: ADC regular sequence register 3
	// Position of SQ10 field.
	ADC_SQR3_SQ10_Pos = 0x6
	// Bit mask of SQ10 field.
	ADC_SQR3_SQ10_Msk = 0x7c0
	// Position of SQ11 field.
	ADC_SQR3_SQ11_Pos = 0xc
	// Bit mask of SQ11 field.
	ADC_SQR3_SQ11_Msk = 0x1f000
	// Position of SQ12 field.
	ADC_SQR3_SQ12_Pos = 0x12
	// Bit mask of SQ12 field.
	ADC_SQR3_SQ12_Msk = 0x7c0000
	// Position of SQ13 field.
	ADC_SQR3_SQ13_Pos = 0x18
	// Bit mask of SQ13 field.
	ADC_SQR3_SQ13_Msk = 0x1f000000
	// Position of SQ14 field.
	ADC_SQR3_SQ14_Pos = 0x1e
	// Bit mask of SQ14 field.
	ADC_SQR3_SQ14_Msk = 0x7c0000000

	// SQR4: ADC regular sequence register 4
	// Position of SQ15 field.
	ADC_SQR4_SQ15_Pos = 0x6
	// Bit mask of SQ15 field.
	ADC_SQR4_SQ15_Msk = 0x7c0
	// Position of SQ16 field.
	ADC_SQR4_SQ16_Pos = 0xc
	// Bit mask of SQ16 field.
	ADC_SQR4_SQ16_Msk = 0x1f000

	// DR: ADC regular Data Register
	// Position of RDATA field.
	ADC_DR_RDATA_Pos = 0x0
	// Bit mask of RDATA field.
	ADC_DR_RDATA_Msk = 0xffffffff

	// JSQR: ADC injected sequence register
	// Position of JSQ1 field.
	ADC_JSQR_JSQ1_Pos = 0xf
	// Bit mask of JSQ1 field.
	ADC_JSQR_JSQ1_Msk = 0xf8000
	// Position of JSQ2 field.
	ADC_JSQR_JSQ2_Pos = 0x15
	// Bit mask of JSQ2 field.
	ADC_JSQR_JSQ2_Msk = 0x3e00000
	// Position of JSQ3 field.
	ADC_JSQR_JSQ3_Pos = 0x1b
	// Bit mask of JSQ3 field.
	ADC_JSQR_JSQ3_Msk = 0xf8000000
	// Position of JSQ4 field.
	ADC_JSQR_JSQ4_Pos = 0x21
	// Bit mask of JSQ4 field.
	ADC_JSQR_JSQ4_Msk = 0x3e00000000
	// Position of JEXTEN field.
	ADC_JSQR_JEXTEN_Pos = 0x7
	// Bit mask of JEXTEN field.
	ADC_JSQR_JEXTEN_Msk = 0x180
	// Hardware trigger detection disabled (conversions can be launched by software)
	ADC_JSQR_JEXTEN_Disabled = 0x0
	// Hardware trigger detection on the rising edge
	ADC_JSQR_JEXTEN_RisingEdge = 0x1
	// Hardware trigger detection on the falling edge
	ADC_JSQR_JEXTEN_FallingEdge = 0x2
	// Hardware trigger detection on both the rising and falling edges
	ADC_JSQR_JEXTEN_BothEdges = 0x3
	// Position of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Pos = 0x2
	// Bit mask of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Msk = 0x7c
	// tim1_trgo
	ADC_JSQR_JEXTSEL_TIM1_TRGO = 0x0
	// tim1_oc4
	ADC_JSQR_JEXTSEL_TIM1_OC4 = 0x1
	// tim2_trgo
	ADC_JSQR_JEXTSEL_TIM2_TRGO = 0x2
	// tim2_oc1
	ADC_JSQR_JEXTSEL_TIM2_OC1 = 0x3
	// tim3_oc4
	ADC_JSQR_JEXTSEL_TIM3_OC4 = 0x4
	// tim4_trgo
	ADC_JSQR_JEXTSEL_TIM4_TRGO = 0x5
	// exti15
	ADC_JSQR_JEXTSEL_EXTI15 = 0x6
	// tim8_oc4
	ADC_JSQR_JEXTSEL_TIM8_OC4 = 0x7
	// tim1_trgo2
	ADC_JSQR_JEXTSEL_TIM1_TRGO2 = 0x8
	// tim8_trgo
	ADC_JSQR_JEXTSEL_TIM8_TRGO = 0x9
	// tim8_trgo2
	ADC_JSQR_JEXTSEL_TIM8_TRGO2 = 0xa
	// tim3_oc3
	ADC_JSQR_JEXTSEL_TIM3_OC3 = 0xb
	// tim3_trgo
	ADC_JSQR_JEXTSEL_TIM3_TRGO = 0xc
	// tim3_oc1
	ADC_JSQR_JEXTSEL_TIM3_OC1 = 0xd
	// tim6_trgo
	ADC_JSQR_JEXTSEL_TIM6_TRGO = 0xe
	// tim15_trgo
	ADC_JSQR_JEXTSEL_TIM15_TRGO = 0xf
	// lptim1_ch2
	ADC_JSQR_JEXTSEL_LPTIM1_CH2 = 0x10
	// lptim2_ch2
	ADC_JSQR_JEXTSEL_LPTIM2_CH2 = 0x11
	// lptim3_ch1
	ADC_JSQR_JEXTSEL_LPTIM3_CH1 = 0x12
	// lptim4_out1
	ADC_JSQR_JEXTSEL_LPTIM4_OUT1 = 0x13
	// Position of JL field.
	ADC_JSQR_JL_Pos = 0x0
	// Bit mask of JL field.
	ADC_JSQR_JL_Msk = 0x3

	// OFR1: ADC offset register
	// Position of OFFSET_CH field.
	ADC_OFR_OFFSET_CH_Pos = 0x1b
	// Bit mask of OFFSET_CH field.
	ADC_OFR_OFFSET_CH_Msk = 0xf8000000
	// Position of SSAT field.
	ADC_OFR_SSAT_Pos = 0x1a
	// Bit mask of SSAT field.
	ADC_OFR_SSAT_Msk = 0x4000000
	// Bit SSAT.
	ADC_OFR_SSAT = 0x4000000
	// Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format)
	ADC_OFR_SSAT_Disabled = 0x0
	// Offset is subtracted and result is saturated to maintain converted data size
	ADC_OFR_SSAT_Enabled = 0x1
	// Position of USAT field.
	ADC_OFR_USAT_Pos = 0x19
	// Bit mask of USAT field.
	ADC_OFR_USAT_Msk = 0x2000000
	// Bit USAT.
	ADC_OFR_USAT = 0x2000000
	// Offset is subtracted maintaining data integrity and keeping converted data size
	ADC_OFR_USAT_Disabled = 0x0
	// Offset is subtracted and result is saturated to maintain converted data size
	ADC_OFR_USAT_Enabled = 0x1
	// Position of POSOFF field.
	ADC_OFR_POSOFF_Pos = 0x18
	// Bit mask of POSOFF field.
	ADC_OFR_POSOFF_Msk = 0x1000000
	// Bit POSOFF.
	ADC_OFR_POSOFF = 0x1000000
	// Negative offset
	ADC_OFR_POSOFF_Negative = 0x0
	// Positive offset
	ADC_OFR_POSOFF_Positive = 0x1
	// Position of OFFSET field.
	ADC_OFR_OFFSET_Pos = 0x0
	// Bit mask of OFFSET field.
	ADC_OFR_OFFSET_Msk = 0xffffff

	// GCOMP: ADC gain compensation register
	// Position of GCOMP field.
	ADC_GCOMP_GCOMP_Pos = 0x1f
	// Bit mask of GCOMP field.
	ADC_GCOMP_GCOMP_Msk = 0x80000000
	// Bit GCOMP.
	ADC_GCOMP_GCOMP = 0x80000000
	// Regular ADC operating mode
	ADC_GCOMP_GCOMP_Disabled = 0x0
	// Gain compensation enabled and applied to all channels
	ADC_GCOMP_GCOMP_Enabled = 0x1
	// Position of GCOMPCOEFF field.
	ADC_GCOMP_GCOMPCOEFF_Pos = 0x0
	// Bit mask of GCOMPCOEFF field.
	ADC_GCOMP_GCOMPCOEFF_Msk = 0x3fff

	// JDR1: ADC injected data register
	// Position of JDATA field.
	ADC_JDR_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC_JDR_JDATA_Msk = 0xffffffff

	// AWD2CR: ADC analog watchdog 2 configuration register
	// Position of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Pos = 0x1
	// Bit mask of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Msk = 0x2
	// Bit AWD2CH0.
	ADC_AWD2CR_AWD2CH0 = 0x2
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH0_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH0_Enabled = 0x1
	// Position of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Pos = 0x2
	// Bit mask of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Msk = 0x4
	// Bit AWD2CH1.
	ADC_AWD2CR_AWD2CH1 = 0x4
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH1_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH1_Enabled = 0x1
	// Position of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Pos = 0x3
	// Bit mask of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Msk = 0x8
	// Bit AWD2CH2.
	ADC_AWD2CR_AWD2CH2 = 0x8
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH2_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH2_Enabled = 0x1
	// Position of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Pos = 0x4
	// Bit mask of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Msk = 0x10
	// Bit AWD2CH3.
	ADC_AWD2CR_AWD2CH3 = 0x10
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH3_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH3_Enabled = 0x1
	// Position of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Pos = 0x5
	// Bit mask of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Msk = 0x20
	// Bit AWD2CH4.
	ADC_AWD2CR_AWD2CH4 = 0x20
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH4_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH4_Enabled = 0x1
	// Position of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Pos = 0x6
	// Bit mask of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Msk = 0x40
	// Bit AWD2CH5.
	ADC_AWD2CR_AWD2CH5 = 0x40
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH5_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH5_Enabled = 0x1
	// Position of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Pos = 0x7
	// Bit mask of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Msk = 0x80
	// Bit AWD2CH6.
	ADC_AWD2CR_AWD2CH6 = 0x80
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH6_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH6_Enabled = 0x1
	// Position of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Pos = 0x8
	// Bit mask of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Msk = 0x100
	// Bit AWD2CH7.
	ADC_AWD2CR_AWD2CH7 = 0x100
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH7_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH7_Enabled = 0x1
	// Position of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Pos = 0x9
	// Bit mask of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Msk = 0x200
	// Bit AWD2CH8.
	ADC_AWD2CR_AWD2CH8 = 0x200
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH8_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH8_Enabled = 0x1
	// Position of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Pos = 0xa
	// Bit mask of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Msk = 0x400
	// Bit AWD2CH9.
	ADC_AWD2CR_AWD2CH9 = 0x400
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH9_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH9_Enabled = 0x1
	// Position of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Pos = 0xb
	// Bit mask of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Msk = 0x800
	// Bit AWD2CH10.
	ADC_AWD2CR_AWD2CH10 = 0x800
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH10_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH10_Enabled = 0x1
	// Position of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Pos = 0xc
	// Bit mask of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Msk = 0x1000
	// Bit AWD2CH11.
	ADC_AWD2CR_AWD2CH11 = 0x1000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH11_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH11_Enabled = 0x1
	// Position of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Pos = 0xd
	// Bit mask of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Msk = 0x2000
	// Bit AWD2CH12.
	ADC_AWD2CR_AWD2CH12 = 0x2000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH12_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH12_Enabled = 0x1
	// Position of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Pos = 0xe
	// Bit mask of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Msk = 0x4000
	// Bit AWD2CH13.
	ADC_AWD2CR_AWD2CH13 = 0x4000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH13_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH13_Enabled = 0x1
	// Position of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Pos = 0xf
	// Bit mask of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Msk = 0x8000
	// Bit AWD2CH14.
	ADC_AWD2CR_AWD2CH14 = 0x8000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH14_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH14_Enabled = 0x1
	// Position of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Pos = 0x10
	// Bit mask of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Msk = 0x10000
	// Bit AWD2CH15.
	ADC_AWD2CR_AWD2CH15 = 0x10000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH15_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH15_Enabled = 0x1
	// Position of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Pos = 0x11
	// Bit mask of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Msk = 0x20000
	// Bit AWD2CH16.
	ADC_AWD2CR_AWD2CH16 = 0x20000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH16_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH16_Enabled = 0x1
	// Position of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Pos = 0x12
	// Bit mask of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Msk = 0x40000
	// Bit AWD2CH17.
	ADC_AWD2CR_AWD2CH17 = 0x40000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH17_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH17_Enabled = 0x1
	// Position of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Pos = 0x13
	// Bit mask of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Msk = 0x80000
	// Bit AWD2CH18.
	ADC_AWD2CR_AWD2CH18 = 0x80000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH18_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH18_Enabled = 0x1
	// Position of AWD2CH19 field.
	ADC_AWD2CR_AWD2CH19_Pos = 0x14
	// Bit mask of AWD2CH19 field.
	ADC_AWD2CR_AWD2CH19_Msk = 0x100000
	// Bit AWD2CH19.
	ADC_AWD2CR_AWD2CH19 = 0x100000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD2CR_AWD2CH19_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD2CR_AWD2CH19_Enabled = 0x1

	// AWD3CR: ADC analog watchdog 3 configuration register
	// Position of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Pos = 0x1
	// Bit mask of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Msk = 0x2
	// Bit AWD3CH0.
	ADC_AWD3CR_AWD3CH0 = 0x2
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH0_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH0_Enabled = 0x1
	// Position of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Pos = 0x2
	// Bit mask of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Msk = 0x4
	// Bit AWD3CH1.
	ADC_AWD3CR_AWD3CH1 = 0x4
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH1_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH1_Enabled = 0x1
	// Position of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Pos = 0x3
	// Bit mask of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Msk = 0x8
	// Bit AWD3CH2.
	ADC_AWD3CR_AWD3CH2 = 0x8
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH2_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH2_Enabled = 0x1
	// Position of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Pos = 0x4
	// Bit mask of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Msk = 0x10
	// Bit AWD3CH3.
	ADC_AWD3CR_AWD3CH3 = 0x10
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH3_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH3_Enabled = 0x1
	// Position of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Pos = 0x5
	// Bit mask of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Msk = 0x20
	// Bit AWD3CH4.
	ADC_AWD3CR_AWD3CH4 = 0x20
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH4_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH4_Enabled = 0x1
	// Position of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Pos = 0x6
	// Bit mask of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Msk = 0x40
	// Bit AWD3CH5.
	ADC_AWD3CR_AWD3CH5 = 0x40
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH5_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH5_Enabled = 0x1
	// Position of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Pos = 0x7
	// Bit mask of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Msk = 0x80
	// Bit AWD3CH6.
	ADC_AWD3CR_AWD3CH6 = 0x80
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH6_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH6_Enabled = 0x1
	// Position of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Pos = 0x8
	// Bit mask of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Msk = 0x100
	// Bit AWD3CH7.
	ADC_AWD3CR_AWD3CH7 = 0x100
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH7_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH7_Enabled = 0x1
	// Position of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Pos = 0x9
	// Bit mask of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Msk = 0x200
	// Bit AWD3CH8.
	ADC_AWD3CR_AWD3CH8 = 0x200
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH8_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH8_Enabled = 0x1
	// Position of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Pos = 0xa
	// Bit mask of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Msk = 0x400
	// Bit AWD3CH9.
	ADC_AWD3CR_AWD3CH9 = 0x400
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH9_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH9_Enabled = 0x1
	// Position of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Pos = 0xb
	// Bit mask of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Msk = 0x800
	// Bit AWD3CH10.
	ADC_AWD3CR_AWD3CH10 = 0x800
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH10_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH10_Enabled = 0x1
	// Position of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Pos = 0xc
	// Bit mask of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Msk = 0x1000
	// Bit AWD3CH11.
	ADC_AWD3CR_AWD3CH11 = 0x1000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH11_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH11_Enabled = 0x1
	// Position of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Pos = 0xd
	// Bit mask of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Msk = 0x2000
	// Bit AWD3CH12.
	ADC_AWD3CR_AWD3CH12 = 0x2000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH12_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH12_Enabled = 0x1
	// Position of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Pos = 0xe
	// Bit mask of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Msk = 0x4000
	// Bit AWD3CH13.
	ADC_AWD3CR_AWD3CH13 = 0x4000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH13_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH13_Enabled = 0x1
	// Position of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Pos = 0xf
	// Bit mask of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Msk = 0x8000
	// Bit AWD3CH14.
	ADC_AWD3CR_AWD3CH14 = 0x8000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH14_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH14_Enabled = 0x1
	// Position of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Pos = 0x10
	// Bit mask of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Msk = 0x10000
	// Bit AWD3CH15.
	ADC_AWD3CR_AWD3CH15 = 0x10000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH15_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH15_Enabled = 0x1
	// Position of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Pos = 0x11
	// Bit mask of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Msk = 0x20000
	// Bit AWD3CH16.
	ADC_AWD3CR_AWD3CH16 = 0x20000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH16_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH16_Enabled = 0x1
	// Position of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Pos = 0x12
	// Bit mask of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Msk = 0x40000
	// Bit AWD3CH17.
	ADC_AWD3CR_AWD3CH17 = 0x40000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH17_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH17_Enabled = 0x1
	// Position of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Pos = 0x13
	// Bit mask of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Msk = 0x80000
	// Bit AWD3CH18.
	ADC_AWD3CR_AWD3CH18 = 0x80000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH18_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH18_Enabled = 0x1
	// Position of AWD3CH19 field.
	ADC_AWD3CR_AWD3CH19_Pos = 0x14
	// Bit mask of AWD3CH19 field.
	ADC_AWD3CR_AWD3CH19_Msk = 0x100000
	// Bit AWD3CH19.
	ADC_AWD3CR_AWD3CH19 = 0x100000
	// ADC analog input channel x is not monitored by AWDy
	ADC_AWD3CR_AWD3CH19_Disabled = 0x0
	// ADC analog input channel x is monitored by AWDy
	ADC_AWD3CR_AWD3CH19_Enabled = 0x1

	// LTR1: ADC watchdog threshold register 1
	// Position of LTR1 field.
	ADC_LTR1_LTR1_Pos = 0x0
	// Bit mask of LTR1 field.
	ADC_LTR1_LTR1_Msk = 0x1ffffff

	// HTR1: ADC watchdog threshold register 1
	// Position of AWDFILT1 field.
	ADC_HTR1_AWDFILT1_Pos = 0x1d
	// Bit mask of AWDFILT1 field.
	ADC_HTR1_AWDFILT1_Msk = 0xe0000000
	// No filtering
	ADC_HTR1_AWDFILT1_NoFiltering = 0x0
	// Two consecutive detections generates an AWDx flag or an interrupt
	ADC_HTR1_AWDFILT1_Detections2 = 0x1
	// Three consecutive detections generates an AWDx flag or an interrupt
	ADC_HTR1_AWDFILT1_Detections3 = 0x2
	// Four consecutive detections generates an AWDx flag or an interrupt
	ADC_HTR1_AWDFILT1_Detections4 = 0x3
	// Five consecutive detections generates an AWDx flag or an interrupt
	ADC_HTR1_AWDFILT1_Detections5 = 0x4
	// Six consecutive detections generates an AWDx flag or an interrupt
	ADC_HTR1_AWDFILT1_Detections6 = 0x5
	// Seven consecutive detections generates an AWDx flag or an interrupt
	ADC_HTR1_AWDFILT1_Detections7 = 0x6
	// Eight consecutive detections generates an AWDx flag or an interrupt
	ADC_HTR1_AWDFILT1_Detections8 = 0x7
	// Position of HTR1 field.
	ADC_HTR1_HTR1_Pos = 0x0
	// Bit mask of HTR1 field.
	ADC_HTR1_HTR1_Msk = 0x1ffffff

	// LTR2: ADC watchdog lower threshold register 2
	// Position of LTR2 field.
	ADC_LTR2_LTR2_Pos = 0x0
	// Bit mask of LTR2 field.
	ADC_LTR2_LTR2_Msk = 0x1ffffff

	// HTR2: ADC watchdog higher threshold register 2
	// Position of HTR2 field.
	ADC_HTR2_HTR2_Pos = 0x0
	// Bit mask of HTR2 field.
	ADC_HTR2_HTR2_Msk = 0x1ffffff

	// LTR3: ADC watchdog lower threshold register 3
	// Position of LTR3 field.
	ADC_LTR3_LTR3_Pos = 0x0
	// Bit mask of LTR3 field.
	ADC_LTR3_LTR3_Msk = 0x1ffffff

	// HTR3: ADC watchdog higher threshold register 3
	// Position of HTR3 field.
	ADC_HTR3_HTR3_Pos = 0x0
	// Bit mask of HTR3 field.
	ADC_HTR3_HTR3_Msk = 0x1ffffff

	// DIFSEL: ADC differential mode selection register
	// Position of DIFSEL0 field.
	ADC_DIFSEL_DIFSEL0_Pos = 0x1
	// Bit mask of DIFSEL0 field.
	ADC_DIFSEL_DIFSEL0_Msk = 0x2
	// Bit DIFSEL0.
	ADC_DIFSEL_DIFSEL0 = 0x2
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL0_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL0_Differential = 0x1
	// Position of DIFSEL1 field.
	ADC_DIFSEL_DIFSEL1_Pos = 0x2
	// Bit mask of DIFSEL1 field.
	ADC_DIFSEL_DIFSEL1_Msk = 0x4
	// Bit DIFSEL1.
	ADC_DIFSEL_DIFSEL1 = 0x4
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL1_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL1_Differential = 0x1
	// Position of DIFSEL2 field.
	ADC_DIFSEL_DIFSEL2_Pos = 0x3
	// Bit mask of DIFSEL2 field.
	ADC_DIFSEL_DIFSEL2_Msk = 0x8
	// Bit DIFSEL2.
	ADC_DIFSEL_DIFSEL2 = 0x8
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL2_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL2_Differential = 0x1
	// Position of DIFSEL3 field.
	ADC_DIFSEL_DIFSEL3_Pos = 0x4
	// Bit mask of DIFSEL3 field.
	ADC_DIFSEL_DIFSEL3_Msk = 0x10
	// Bit DIFSEL3.
	ADC_DIFSEL_DIFSEL3 = 0x10
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL3_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL3_Differential = 0x1
	// Position of DIFSEL4 field.
	ADC_DIFSEL_DIFSEL4_Pos = 0x5
	// Bit mask of DIFSEL4 field.
	ADC_DIFSEL_DIFSEL4_Msk = 0x20
	// Bit DIFSEL4.
	ADC_DIFSEL_DIFSEL4 = 0x20
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL4_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL4_Differential = 0x1
	// Position of DIFSEL5 field.
	ADC_DIFSEL_DIFSEL5_Pos = 0x6
	// Bit mask of DIFSEL5 field.
	ADC_DIFSEL_DIFSEL5_Msk = 0x40
	// Bit DIFSEL5.
	ADC_DIFSEL_DIFSEL5 = 0x40
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL5_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL5_Differential = 0x1
	// Position of DIFSEL6 field.
	ADC_DIFSEL_DIFSEL6_Pos = 0x7
	// Bit mask of DIFSEL6 field.
	ADC_DIFSEL_DIFSEL6_Msk = 0x80
	// Bit DIFSEL6.
	ADC_DIFSEL_DIFSEL6 = 0x80
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL6_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL6_Differential = 0x1
	// Position of DIFSEL7 field.
	ADC_DIFSEL_DIFSEL7_Pos = 0x8
	// Bit mask of DIFSEL7 field.
	ADC_DIFSEL_DIFSEL7_Msk = 0x100
	// Bit DIFSEL7.
	ADC_DIFSEL_DIFSEL7 = 0x100
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL7_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL7_Differential = 0x1
	// Position of DIFSEL8 field.
	ADC_DIFSEL_DIFSEL8_Pos = 0x9
	// Bit mask of DIFSEL8 field.
	ADC_DIFSEL_DIFSEL8_Msk = 0x200
	// Bit DIFSEL8.
	ADC_DIFSEL_DIFSEL8 = 0x200
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL8_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL8_Differential = 0x1
	// Position of DIFSEL9 field.
	ADC_DIFSEL_DIFSEL9_Pos = 0xa
	// Bit mask of DIFSEL9 field.
	ADC_DIFSEL_DIFSEL9_Msk = 0x400
	// Bit DIFSEL9.
	ADC_DIFSEL_DIFSEL9 = 0x400
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL9_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL9_Differential = 0x1
	// Position of DIFSEL10 field.
	ADC_DIFSEL_DIFSEL10_Pos = 0xb
	// Bit mask of DIFSEL10 field.
	ADC_DIFSEL_DIFSEL10_Msk = 0x800
	// Bit DIFSEL10.
	ADC_DIFSEL_DIFSEL10 = 0x800
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL10_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL10_Differential = 0x1
	// Position of DIFSEL11 field.
	ADC_DIFSEL_DIFSEL11_Pos = 0xc
	// Bit mask of DIFSEL11 field.
	ADC_DIFSEL_DIFSEL11_Msk = 0x1000
	// Bit DIFSEL11.
	ADC_DIFSEL_DIFSEL11 = 0x1000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL11_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL11_Differential = 0x1
	// Position of DIFSEL12 field.
	ADC_DIFSEL_DIFSEL12_Pos = 0xd
	// Bit mask of DIFSEL12 field.
	ADC_DIFSEL_DIFSEL12_Msk = 0x2000
	// Bit DIFSEL12.
	ADC_DIFSEL_DIFSEL12 = 0x2000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL12_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL12_Differential = 0x1
	// Position of DIFSEL13 field.
	ADC_DIFSEL_DIFSEL13_Pos = 0xe
	// Bit mask of DIFSEL13 field.
	ADC_DIFSEL_DIFSEL13_Msk = 0x4000
	// Bit DIFSEL13.
	ADC_DIFSEL_DIFSEL13 = 0x4000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL13_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL13_Differential = 0x1
	// Position of DIFSEL14 field.
	ADC_DIFSEL_DIFSEL14_Pos = 0xf
	// Bit mask of DIFSEL14 field.
	ADC_DIFSEL_DIFSEL14_Msk = 0x8000
	// Bit DIFSEL14.
	ADC_DIFSEL_DIFSEL14 = 0x8000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL14_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL14_Differential = 0x1
	// Position of DIFSEL15 field.
	ADC_DIFSEL_DIFSEL15_Pos = 0x10
	// Bit mask of DIFSEL15 field.
	ADC_DIFSEL_DIFSEL15_Msk = 0x10000
	// Bit DIFSEL15.
	ADC_DIFSEL_DIFSEL15 = 0x10000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL15_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL15_Differential = 0x1
	// Position of DIFSEL16 field.
	ADC_DIFSEL_DIFSEL16_Pos = 0x11
	// Bit mask of DIFSEL16 field.
	ADC_DIFSEL_DIFSEL16_Msk = 0x20000
	// Bit DIFSEL16.
	ADC_DIFSEL_DIFSEL16 = 0x20000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL16_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL16_Differential = 0x1
	// Position of DIFSEL17 field.
	ADC_DIFSEL_DIFSEL17_Pos = 0x12
	// Bit mask of DIFSEL17 field.
	ADC_DIFSEL_DIFSEL17_Msk = 0x40000
	// Bit DIFSEL17.
	ADC_DIFSEL_DIFSEL17 = 0x40000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL17_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL17_Differential = 0x1
	// Position of DIFSEL18 field.
	ADC_DIFSEL_DIFSEL18_Pos = 0x13
	// Bit mask of DIFSEL18 field.
	ADC_DIFSEL_DIFSEL18_Msk = 0x80000
	// Bit DIFSEL18.
	ADC_DIFSEL_DIFSEL18 = 0x80000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL18_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL18_Differential = 0x1
	// Position of DIFSEL19 field.
	ADC_DIFSEL_DIFSEL19_Pos = 0x14
	// Bit mask of DIFSEL19 field.
	ADC_DIFSEL_DIFSEL19_Msk = 0x100000
	// Bit DIFSEL19.
	ADC_DIFSEL_DIFSEL19 = 0x100000
	// ADC analog input channel x is configured in single-ended mode
	ADC_DIFSEL_DIFSEL19_SingleEnded = 0x0
	// ADC analog input channel x is configured in differential mode
	ADC_DIFSEL_DIFSEL19_Differential = 0x1

	// CALFACT: ADC user control register
	// Position of CAPTURE_COEF field.
	ADC_CALFACT_CAPTURE_COEF_Pos = 0x19
	// Bit mask of CAPTURE_COEF field.
	ADC_CALFACT_CAPTURE_COEF_Msk = 0x2000000
	// Bit CAPTURE_COEF.
	ADC_CALFACT_CAPTURE_COEF = 0x2000000
	// Calibration factor not captured
	ADC_CALFACT_CAPTURE_COEF_Disabled = 0x0
	// Calibration factor available in CALFACT[31:0] bits, the calibration factor index being defined by CALINDEX[3:0] bits
	ADC_CALFACT_CAPTURE_COEF_Enabled = 0x1
	// Position of LATCH_COEF field.
	ADC_CALFACT_LATCH_COEF_Pos = 0x18
	// Bit mask of LATCH_COEF field.
	ADC_CALFACT_LATCH_COEF_Msk = 0x1000000
	// Bit LATCH_COEF.
	ADC_CALFACT_LATCH_COEF = 0x1000000
	// No effect
	ADC_CALFACT_LATCH_COEF_NoEffect = 0x0
	// Calibration factor latched in the analog block on LATCH_COEF bit transition from 0 to 1. Prior to latching the calibration factor, CALFACT[31:0] bits must be programmed with the content of CALINDEX[3:0] bits.
	ADC_CALFACT_LATCH_COEF_Latch = 0x1
	// Position of VALIDITY field.
	ADC_CALFACT_VALIDITY_Pos = 0x10
	// Bit mask of VALIDITY field.
	ADC_CALFACT_VALIDITY_Msk = 0x10000
	// Bit VALIDITY.
	ADC_CALFACT_VALIDITY = 0x10000
	// Operation still in progress
	ADC_CALFACT_VALIDITY_InProgress = 0x0
	// Operation complete
	ADC_CALFACT_VALIDITY_Complete = 0x1
	// Position of I_APB_DATA field.
	ADC_CALFACT_I_APB_DATA_Pos = 0x8
	// Bit mask of I_APB_DATA field.
	ADC_CALFACT_I_APB_DATA_Msk = 0xff00
	// Position of I_APB_ADDR field.
	ADC_CALFACT_I_APB_ADDR_Pos = 0x0
	// Bit mask of I_APB_ADDR field.
	ADC_CALFACT_I_APB_ADDR_Msk = 0xff

	// CALFACT2: ADC calibration factor register
	// Position of CALFACT field.
	ADC_CALFACT2_CALFACT_Pos = 0x0
	// Bit mask of CALFACT field.
	ADC_CALFACT2_CALFACT_Msk = 0xffffffff
)

// Constants for ADF1: ADF1
const (
	// GCR: ADF Global Control Register
	// Position of TRGO field.
	ADF_GCR_TRGO_Pos = 0x0
	// Bit mask of TRGO field.
	ADF_GCR_TRGO_Msk = 0x1
	// Bit TRGO.
	ADF_GCR_TRGO = 0x1

	// CKGCR: ADF clock generator control register
	// Position of CKGACTIVE field.
	ADF_CKGCR_CKGACTIVE_Pos = 0x1f
	// Bit mask of CKGACTIVE field.
	ADF_CKGCR_CKGACTIVE_Msk = 0x80000000
	// Bit CKGACTIVE.
	ADF_CKGCR_CKGACTIVE = 0x80000000
	// Position of PROCDIV field.
	ADF_CKGCR_PROCDIV_Pos = 0x18
	// Bit mask of PROCDIV field.
	ADF_CKGCR_PROCDIV_Msk = 0x7f000000
	// Position of CCKDIV field.
	ADF_CKGCR_CCKDIV_Pos = 0x10
	// Bit mask of CCKDIV field.
	ADF_CKGCR_CCKDIV_Msk = 0xf0000
	// Position of TRGSRC field.
	ADF_CKGCR_TRGSRC_Pos = 0xc
	// Bit mask of TRGSRC field.
	ADF_CKGCR_TRGSRC_Msk = 0xf000
	// Position of TRGSENS field.
	ADF_CKGCR_TRGSENS_Pos = 0x8
	// Bit mask of TRGSENS field.
	ADF_CKGCR_TRGSENS_Msk = 0x100
	// Bit TRGSENS.
	ADF_CKGCR_TRGSENS = 0x100
	// Position of CCK1DIR field.
	ADF_CKGCR_CCK1DIR_Pos = 0x6
	// Bit mask of CCK1DIR field.
	ADF_CKGCR_CCK1DIR_Msk = 0x40
	// Bit CCK1DIR.
	ADF_CKGCR_CCK1DIR = 0x40
	// Position of CCK0DIR field.
	ADF_CKGCR_CCK0DIR_Pos = 0x5
	// Bit mask of CCK0DIR field.
	ADF_CKGCR_CCK0DIR_Msk = 0x20
	// Bit CCK0DIR.
	ADF_CKGCR_CCK0DIR = 0x20
	// Position of CKGMOD field.
	ADF_CKGCR_CKGMOD_Pos = 0x4
	// Bit mask of CKGMOD field.
	ADF_CKGCR_CKGMOD_Msk = 0x10
	// Bit CKGMOD.
	ADF_CKGCR_CKGMOD = 0x10
	// Position of CCK1EN field.
	ADF_CKGCR_CCK1EN_Pos = 0x2
	// Bit mask of CCK1EN field.
	ADF_CKGCR_CCK1EN_Msk = 0x4
	// Bit CCK1EN.
	ADF_CKGCR_CCK1EN = 0x4
	// Position of CCK0EN field.
	ADF_CKGCR_CCK0EN_Pos = 0x1
	// Bit mask of CCK0EN field.
	ADF_CKGCR_CCK0EN_Msk = 0x2
	// Bit CCK0EN.
	ADF_CKGCR_CCK0EN = 0x2
	// Position of CKGDEN field.
	ADF_CKGCR_CKGDEN_Pos = 0x0
	// Bit mask of CKGDEN field.
	ADF_CKGCR_CKGDEN_Msk = 0x1
	// Bit CKGDEN.
	ADF_CKGCR_CKGDEN = 0x1

	// SITF0CR: ADF serial interface control register 0
	// Position of SITFACTIVE field.
	ADF_SITF0CR_SITFACTIVE_Pos = 0x1f
	// Bit mask of SITFACTIVE field.
	ADF_SITF0CR_SITFACTIVE_Msk = 0x80000000
	// Bit SITFACTIVE.
	ADF_SITF0CR_SITFACTIVE = 0x80000000
	// Position of STH field.
	ADF_SITF0CR_STH_Pos = 0x8
	// Bit mask of STH field.
	ADF_SITF0CR_STH_Msk = 0x1f00
	// Position of SITFMOD field.
	ADF_SITF0CR_SITFMOD_Pos = 0x4
	// Bit mask of SITFMOD field.
	ADF_SITF0CR_SITFMOD_Msk = 0x30
	// Position of SCKSRC field.
	ADF_SITF0CR_SCKSRC_Pos = 0x1
	// Bit mask of SCKSRC field.
	ADF_SITF0CR_SCKSRC_Msk = 0x6
	// Position of SITFEN field.
	ADF_SITF0CR_SITFEN_Pos = 0x0
	// Bit mask of SITFEN field.
	ADF_SITF0CR_SITFEN_Msk = 0x1
	// Bit SITFEN.
	ADF_SITF0CR_SITFEN = 0x1

	// BSMX0CR: ADF bitstream matrix control register 0
	// Position of BSMXACTIVE field.
	ADF_BSMX0CR_BSMXACTIVE_Pos = 0x1f
	// Bit mask of BSMXACTIVE field.
	ADF_BSMX0CR_BSMXACTIVE_Msk = 0x80000000
	// Bit BSMXACTIVE.
	ADF_BSMX0CR_BSMXACTIVE = 0x80000000
	// Position of BSSEL field.
	ADF_BSMX0CR_BSSEL_Pos = 0x0
	// Bit mask of BSSEL field.
	ADF_BSMX0CR_BSSEL_Msk = 0x1f

	// DFLT0CR: ADF digital filter control register 0
	// Position of DFLTACTIVE field.
	ADF_DFLT0CR_DFLTACTIVE_Pos = 0x1f
	// Bit mask of DFLTACTIVE field.
	ADF_DFLT0CR_DFLTACTIVE_Msk = 0x80000000
	// Bit DFLTACTIVE.
	ADF_DFLT0CR_DFLTACTIVE = 0x80000000
	// Position of DFLTRUN field.
	ADF_DFLT0CR_DFLTRUN_Pos = 0x1e
	// Bit mask of DFLTRUN field.
	ADF_DFLT0CR_DFLTRUN_Msk = 0x40000000
	// Bit DFLTRUN.
	ADF_DFLT0CR_DFLTRUN = 0x40000000
	// Position of NBDIS field.
	ADF_DFLT0CR_NBDIS_Pos = 0x14
	// Bit mask of NBDIS field.
	ADF_DFLT0CR_NBDIS_Msk = 0xff00000
	// Position of TRGSRC field.
	ADF_DFLT0CR_TRGSRC_Pos = 0xc
	// Bit mask of TRGSRC field.
	ADF_DFLT0CR_TRGSRC_Msk = 0xf000
	// Position of ACQMOD field.
	ADF_DFLT0CR_ACQMOD_Pos = 0x4
	// Bit mask of ACQMOD field.
	ADF_DFLT0CR_ACQMOD_Msk = 0x70
	// Position of FTH field.
	ADF_DFLT0CR_FTH_Pos = 0x2
	// Bit mask of FTH field.
	ADF_DFLT0CR_FTH_Msk = 0x4
	// Bit FTH.
	ADF_DFLT0CR_FTH = 0x4
	// Position of DMAEN field.
	ADF_DFLT0CR_DMAEN_Pos = 0x1
	// Bit mask of DMAEN field.
	ADF_DFLT0CR_DMAEN_Msk = 0x2
	// Bit DMAEN.
	ADF_DFLT0CR_DMAEN = 0x2
	// Position of DFLTEN field.
	ADF_DFLT0CR_DFLTEN_Pos = 0x0
	// Bit mask of DFLTEN field.
	ADF_DFLT0CR_DFLTEN_Msk = 0x1
	// Bit DFLTEN.
	ADF_DFLT0CR_DFLTEN = 0x1

	// DFLT0CICR: ADF digital filer configuration register 0
	// Position of SCALE field.
	ADF_DFLT0CICR_SCALE_Pos = 0x14
	// Bit mask of SCALE field.
	ADF_DFLT0CICR_SCALE_Msk = 0x3f00000
	// Position of MCICD field.
	ADF_DFLT0CICR_MCICD_Pos = 0x8
	// Bit mask of MCICD field.
	ADF_DFLT0CICR_MCICD_Msk = 0x1ff00
	// Position of CICMOD field.
	ADF_DFLT0CICR_CICMOD_Pos = 0x4
	// Bit mask of CICMOD field.
	ADF_DFLT0CICR_CICMOD_Msk = 0x70
	// Position of DATSRC field.
	ADF_DFLT0CICR_DATSRC_Pos = 0x0
	// Bit mask of DATSRC field.
	ADF_DFLT0CICR_DATSRC_Msk = 0x3

	// DFLT0RSFR: ADF reshape filter configuration register 0
	// Position of HPFC field.
	ADF_DFLT0RSFR_HPFC_Pos = 0x8
	// Bit mask of HPFC field.
	ADF_DFLT0RSFR_HPFC_Msk = 0x300
	// Position of HPFBYP field.
	ADF_DFLT0RSFR_HPFBYP_Pos = 0x7
	// Bit mask of HPFBYP field.
	ADF_DFLT0RSFR_HPFBYP_Msk = 0x80
	// Bit HPFBYP.
	ADF_DFLT0RSFR_HPFBYP = 0x80
	// Position of RSFLTD field.
	ADF_DFLT0RSFR_RSFLTD_Pos = 0x4
	// Bit mask of RSFLTD field.
	ADF_DFLT0RSFR_RSFLTD_Msk = 0x10
	// Bit RSFLTD.
	ADF_DFLT0RSFR_RSFLTD = 0x10
	// Position of RSFLTBYP field.
	ADF_DFLT0RSFR_RSFLTBYP_Pos = 0x0
	// Bit mask of RSFLTBYP field.
	ADF_DFLT0RSFR_RSFLTBYP_Msk = 0x1
	// Bit RSFLTBYP.
	ADF_DFLT0RSFR_RSFLTBYP = 0x1

	// DLY0CR: ADF delay control register 0
	// Position of SKPBF field.
	ADF_DLY0CR_SKPBF_Pos = 0x1f
	// Bit mask of SKPBF field.
	ADF_DLY0CR_SKPBF_Msk = 0x80000000
	// Bit SKPBF.
	ADF_DLY0CR_SKPBF = 0x80000000
	// Position of SKPDLY field.
	ADF_DLY0CR_SKPDLY_Pos = 0x0
	// Bit mask of SKPDLY field.
	ADF_DLY0CR_SKPDLY_Msk = 0x7f

	// DFLT0IER: ADF DFLT0 interrupt enable register
	// Position of SDLVLIE field.
	ADF_DFLT0IER_SDLVLIE_Pos = 0xd
	// Bit mask of SDLVLIE field.
	ADF_DFLT0IER_SDLVLIE_Msk = 0x2000
	// Bit SDLVLIE.
	ADF_DFLT0IER_SDLVLIE = 0x2000
	// Position of SDDETIE field.
	ADF_DFLT0IER_SDDETIE_Pos = 0xc
	// Bit mask of SDDETIE field.
	ADF_DFLT0IER_SDDETIE_Msk = 0x1000
	// Bit SDDETIE.
	ADF_DFLT0IER_SDDETIE = 0x1000
	// Position of RFOVRIE field.
	ADF_DFLT0IER_RFOVRIE_Pos = 0xb
	// Bit mask of RFOVRIE field.
	ADF_DFLT0IER_RFOVRIE_Msk = 0x800
	// Bit RFOVRIE.
	ADF_DFLT0IER_RFOVRIE = 0x800
	// Position of CKABIE field.
	ADF_DFLT0IER_CKABIE_Pos = 0xa
	// Bit mask of CKABIE field.
	ADF_DFLT0IER_CKABIE_Msk = 0x400
	// Bit CKABIE.
	ADF_DFLT0IER_CKABIE = 0x400
	// Position of SATIE field.
	ADF_DFLT0IER_SATIE_Pos = 0x9
	// Bit mask of SATIE field.
	ADF_DFLT0IER_SATIE_Msk = 0x200
	// Bit SATIE.
	ADF_DFLT0IER_SATIE = 0x200
	// Position of DOVRIE field.
	ADF_DFLT0IER_DOVRIE_Pos = 0x1
	// Bit mask of DOVRIE field.
	ADF_DFLT0IER_DOVRIE_Msk = 0x2
	// Bit DOVRIE.
	ADF_DFLT0IER_DOVRIE = 0x2
	// Position of FTHIE field.
	ADF_DFLT0IER_FTHIE_Pos = 0x0
	// Bit mask of FTHIE field.
	ADF_DFLT0IER_FTHIE_Msk = 0x1
	// Bit FTHIE.
	ADF_DFLT0IER_FTHIE = 0x1

	// DFLT0ISR: ADF DFLT0 interrupt status register 0
	// Position of SDLVLF field.
	ADF_DFLT0ISR_SDLVLF_Pos = 0xd
	// Bit mask of SDLVLF field.
	ADF_DFLT0ISR_SDLVLF_Msk = 0x2000
	// Bit SDLVLF.
	ADF_DFLT0ISR_SDLVLF = 0x2000
	// Position of SDDETF field.
	ADF_DFLT0ISR_SDDETF_Pos = 0xc
	// Bit mask of SDDETF field.
	ADF_DFLT0ISR_SDDETF_Msk = 0x1000
	// Bit SDDETF.
	ADF_DFLT0ISR_SDDETF = 0x1000
	// Position of RFOVRF field.
	ADF_DFLT0ISR_RFOVRF_Pos = 0xb
	// Bit mask of RFOVRF field.
	ADF_DFLT0ISR_RFOVRF_Msk = 0x800
	// Bit RFOVRF.
	ADF_DFLT0ISR_RFOVRF = 0x800
	// Position of CKABF field.
	ADF_DFLT0ISR_CKABF_Pos = 0xa
	// Bit mask of CKABF field.
	ADF_DFLT0ISR_CKABF_Msk = 0x400
	// Bit CKABF.
	ADF_DFLT0ISR_CKABF = 0x400
	// Position of SATF field.
	ADF_DFLT0ISR_SATF_Pos = 0x9
	// Bit mask of SATF field.
	ADF_DFLT0ISR_SATF_Msk = 0x200
	// Bit SATF.
	ADF_DFLT0ISR_SATF = 0x200
	// Position of RXNEF field.
	ADF_DFLT0ISR_RXNEF_Pos = 0x3
	// Bit mask of RXNEF field.
	ADF_DFLT0ISR_RXNEF_Msk = 0x8
	// Bit RXNEF.
	ADF_DFLT0ISR_RXNEF = 0x8
	// Position of DOVRF field.
	ADF_DFLT0ISR_DOVRF_Pos = 0x1
	// Bit mask of DOVRF field.
	ADF_DFLT0ISR_DOVRF_Msk = 0x2
	// Bit DOVRF.
	ADF_DFLT0ISR_DOVRF = 0x2
	// Position of FTHF field.
	ADF_DFLT0ISR_FTHF_Pos = 0x0
	// Bit mask of FTHF field.
	ADF_DFLT0ISR_FTHF_Msk = 0x1
	// Bit FTHF.
	ADF_DFLT0ISR_FTHF = 0x1

	// SADCR: ADF SAD control register
	// Position of SADACTIVE field.
	ADF_SADCR_SADACTIVE_Pos = 0x1f
	// Bit mask of SADACTIVE field.
	ADF_SADCR_SADACTIVE_Msk = 0x80000000
	// Bit SADACTIVE.
	ADF_SADCR_SADACTIVE = 0x80000000
	// Position of SADMOD field.
	ADF_SADCR_SADMOD_Pos = 0xc
	// Bit mask of SADMOD field.
	ADF_SADCR_SADMOD_Msk = 0x3000
	// Position of FRSIZE field.
	ADF_SADCR_FRSIZE_Pos = 0x8
	// Bit mask of FRSIZE field.
	ADF_SADCR_FRSIZE_Msk = 0x700
	// Position of HYSTEN field.
	ADF_SADCR_HYSTEN_Pos = 0x7
	// Bit mask of HYSTEN field.
	ADF_SADCR_HYSTEN_Msk = 0x80
	// Bit HYSTEN.
	ADF_SADCR_HYSTEN = 0x80
	// Position of SADST field.
	ADF_SADCR_SADST_Pos = 0x4
	// Bit mask of SADST field.
	ADF_SADCR_SADST_Msk = 0x30
	// Position of DETCFG field.
	ADF_SADCR_DETCFG_Pos = 0x3
	// Bit mask of DETCFG field.
	ADF_SADCR_DETCFG_Msk = 0x8
	// Bit DETCFG.
	ADF_SADCR_DETCFG = 0x8
	// Position of DATCAP field.
	ADF_SADCR_DATCAP_Pos = 0x1
	// Bit mask of DATCAP field.
	ADF_SADCR_DATCAP_Msk = 0x6
	// Position of SADEN field.
	ADF_SADCR_SADEN_Pos = 0x0
	// Bit mask of SADEN field.
	ADF_SADCR_SADEN_Msk = 0x1
	// Bit SADEN.
	ADF_SADCR_SADEN = 0x1

	// SADCFGR: ADF SAD configuration register
	// Position of ANMIN field.
	ADF_SADCFGR_ANMIN_Pos = 0x10
	// Bit mask of ANMIN field.
	ADF_SADCFGR_ANMIN_Msk = 0x1fff0000
	// Position of HGOVR field.
	ADF_SADCFGR_HGOVR_Pos = 0xc
	// Bit mask of HGOVR field.
	ADF_SADCFGR_HGOVR_Msk = 0x7000
	// Position of LFRNB field.
	ADF_SADCFGR_LFRNB_Pos = 0x8
	// Bit mask of LFRNB field.
	ADF_SADCFGR_LFRNB_Msk = 0x700
	// Position of ANSLP field.
	ADF_SADCFGR_ANSLP_Pos = 0x4
	// Bit mask of ANSLP field.
	ADF_SADCFGR_ANSLP_Msk = 0x70
	// Position of SNTHR field.
	ADF_SADCFGR_SNTHR_Pos = 0x0
	// Bit mask of SNTHR field.
	ADF_SADCFGR_SNTHR_Msk = 0xf

	// SADSDLVR: ADF SAD sound level register
	// Position of SDLVL field.
	ADF_SADSDLVR_SDLVL_Pos = 0x0
	// Bit mask of SDLVL field.
	ADF_SADSDLVR_SDLVL_Msk = 0x7fff

	// SADANLVR: ADF SAD ambient noise level register
	// Position of ANLVL field.
	ADF_SADANLVR_ANLVL_Pos = 0x0
	// Bit mask of ANLVL field.
	ADF_SADANLVR_ANLVL_Msk = 0x7fff

	// DFLT0DR: ADF digital filter data register 0
	// Position of DR field.
	ADF_DFLT0DR_DR_Pos = 0x8
	// Bit mask of DR field.
	ADF_DFLT0DR_DR_Msk = 0xffffff00
)

// Constants for AES: Advanced encryption standard hardware accelerator
const (
	// CR: control register
	// Position of IPRST field.
	AES_CR_IPRST_Pos = 0x1f
	// Bit mask of IPRST field.
	AES_CR_IPRST_Msk = 0x80000000
	// Bit IPRST.
	AES_CR_IPRST = 0x80000000
	// Position of KMOD field.
	AES_CR_KMOD_Pos = 0x18
	// Bit mask of KMOD field.
	AES_CR_KMOD_Msk = 0x3000000
	// Normal key mode. Key registers are freely usable
	AES_CR_KMOD_NormalKey = 0x0
	// Shared key mode. If shared key mode is properly initialized in SAES peripheral, the AES peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in AES key registers when BUSY bit is cleared and KEYVALID is set in the AES_SR register. Key error flag KEIF is set otherwise in the AES_ISR register
	AES_CR_KMOD_SharedKey = 0x2
	// Position of NPBLB field.
	AES_CR_NPBLB_Pos = 0x14
	// Bit mask of NPBLB field.
	AES_CR_NPBLB_Msk = 0xf00000
	// Position of KEYSIZE field.
	AES_CR_KEYSIZE_Pos = 0x12
	// Bit mask of KEYSIZE field.
	AES_CR_KEYSIZE_Msk = 0x40000
	// Bit KEYSIZE.
	AES_CR_KEYSIZE = 0x40000
	// 128
	AES_CR_KEYSIZE_AES128 = 0x0
	// 256
	AES_CR_KEYSIZE_AES256 = 0x1
	// Position of CHMOD_2 field.
	AES_CR_CHMOD_2_Pos = 0x10
	// Bit mask of CHMOD_2 field.
	AES_CR_CHMOD_2_Msk = 0x10000
	// Bit CHMOD_2.
	AES_CR_CHMOD_2 = 0x10000
	// Mode as per CHMOD (ECB, CBC, CTR, GCM)
	AES_CR_CHMOD_2_CHMOD = 0x0
	// Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)
	AES_CR_CHMOD_2_CCM = 0x1
	// Position of GCMPH field.
	AES_CR_GCMPH_Pos = 0xd
	// Bit mask of GCMPH field.
	AES_CR_GCMPH_Msk = 0x6000
	// Init phase
	AES_CR_GCMPH_Init = 0x0
	// Header phase
	AES_CR_GCMPH_Header = 0x1
	// Payload phase
	AES_CR_GCMPH_Payload = 0x2
	// Final Phase
	AES_CR_GCMPH_Final = 0x3
	// Position of DMAOUTEN field.
	AES_CR_DMAOUTEN_Pos = 0xc
	// Bit mask of DMAOUTEN field.
	AES_CR_DMAOUTEN_Msk = 0x1000
	// Bit DMAOUTEN.
	AES_CR_DMAOUTEN = 0x1000
	// Disable DMA Output
	AES_CR_DMAOUTEN_Disabled = 0x0
	// Enabled DMA Output
	AES_CR_DMAOUTEN_Enabled = 0x1
	// Position of DMAINEN field.
	AES_CR_DMAINEN_Pos = 0xb
	// Bit mask of DMAINEN field.
	AES_CR_DMAINEN_Msk = 0x800
	// Bit DMAINEN.
	AES_CR_DMAINEN = 0x800
	// Disable DMA Input
	AES_CR_DMAINEN_Disabled = 0x0
	// Enable DMA Input
	AES_CR_DMAINEN_Enabled = 0x1
	// Position of CHMOD field.
	AES_CR_CHMOD_Pos = 0x5
	// Bit mask of CHMOD field.
	AES_CR_CHMOD_Msk = 0x60
	// Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1
	AES_CR_CHMOD_ECB = 0x0
	// Cipher-block chaining (CBC)
	AES_CR_CHMOD_CBC = 0x1
	// Counter mode (CTR)
	AES_CR_CHMOD_CTR = 0x2
	// Galois counter mode (GCM) and Galois message authentication code (GMAC)
	AES_CR_CHMOD_GCM = 0x3
	// Position of MODE field.
	AES_CR_MODE_Pos = 0x3
	// Bit mask of MODE field.
	AES_CR_MODE_Msk = 0x18
	// Mode 1: encryption
	AES_CR_MODE_Mode1 = 0x0
	// Mode 2: key derivation (or key preparation for ECB/CBC decryption)
	AES_CR_MODE_Mode2 = 0x1
	// Mode 3: decryption
	AES_CR_MODE_Mode3 = 0x2
	// Mode 4: key derivation then single decryption
	AES_CR_MODE_Mode4 = 0x3
	// Position of DATATYPE field.
	AES_CR_DATATYPE_Pos = 0x1
	// Bit mask of DATATYPE field.
	AES_CR_DATATYPE_Msk = 0x6
	// Word
	AES_CR_DATATYPE_None = 0x0
	// Half-word (16-bit)
	AES_CR_DATATYPE_HalfWord = 0x1
	// Byte (8-bit)
	AES_CR_DATATYPE_Byte = 0x2
	// Bit
	AES_CR_DATATYPE_Bit = 0x3
	// Position of EN field.
	AES_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	AES_CR_EN_Msk = 0x1
	// Bit EN.
	AES_CR_EN = 0x1
	// Disable AES
	AES_CR_EN_Disabled = 0x0
	// Enable AES
	AES_CR_EN_Enabled = 0x1

	// SR: status register
	// Position of KEYVALID field.
	AES_SR_KEYVALID_Pos = 0x7
	// Bit mask of KEYVALID field.
	AES_SR_KEYVALID_Msk = 0x80
	// Bit KEYVALID.
	AES_SR_KEYVALID = 0x80
	// Position of BUSY field.
	AES_SR_BUSY_Pos = 0x3
	// Bit mask of BUSY field.
	AES_SR_BUSY_Msk = 0x8
	// Bit BUSY.
	AES_SR_BUSY = 0x8
	// Idle
	AES_SR_BUSY_Idle = 0x0
	// Busy
	AES_SR_BUSY_Busy = 0x1
	// Position of WRERR field.
	AES_SR_WRERR_Pos = 0x2
	// Bit mask of WRERR field.
	AES_SR_WRERR_Msk = 0x4
	// Bit WRERR.
	AES_SR_WRERR = 0x4
	// Write error not detected
	AES_SR_WRERR_NoError = 0x0
	// Write error detected
	AES_SR_WRERR_Error = 0x1
	// Position of RDERR field.
	AES_SR_RDERR_Pos = 0x1
	// Bit mask of RDERR field.
	AES_SR_RDERR_Msk = 0x2
	// Bit RDERR.
	AES_SR_RDERR = 0x2
	// Read error not detected
	AES_SR_RDERR_NoError = 0x0
	// Read error detected
	AES_SR_RDERR_Error = 0x1
	// Position of CCF field.
	AES_SR_CCF_Pos = 0x0
	// Bit mask of CCF field.
	AES_SR_CCF_Msk = 0x1
	// Bit CCF.
	AES_SR_CCF = 0x1
	// Computation complete
	AES_SR_CCF_Complete = 0x0
	// Computation not complete
	AES_SR_CCF_NotComplete = 0x1

	// DINR: data input register
	// Position of DIN field.
	AES_DINR_DIN_Pos = 0x0
	// Bit mask of DIN field.
	AES_DINR_DIN_Msk = 0xffffffff

	// DOUTR: data output register
	// Position of DOUT field.
	AES_DOUTR_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	AES_DOUTR_DOUT_Msk = 0xffffffff

	// KEYR0: key register 0
	// Position of KEY field.
	AES_KEYR0_KEY_Pos = 0x0
	// Bit mask of KEY field.
	AES_KEYR0_KEY_Msk = 0xffffffff

	// KEYR1: key register 1
	// Position of KEY field.
	AES_KEYR1_KEY_Pos = 0x0
	// Bit mask of KEY field.
	AES_KEYR1_KEY_Msk = 0xffffffff

	// KEYR2: key register 2
	// Position of KEYR field.
	AES_KEYR2_KEYR_Pos = 0x0
	// Bit mask of KEYR field.
	AES_KEYR2_KEYR_Msk = 0xffffffff

	// KEYR3: key register 3
	// Position of AES_KEYR3 field.
	AES_KEYR3_AES_KEYR3_Pos = 0x0
	// Bit mask of AES_KEYR3 field.
	AES_KEYR3_AES_KEYR3_Msk = 0xffffffff

	// IVR0: initialization vector register 0
	// Position of IVI field.
	AES_IVR0_IVI_Pos = 0x0
	// Bit mask of IVI field.
	AES_IVR0_IVI_Msk = 0xffffffff

	// IVR1: initialization vector register 1
	// Position of IVI field.
	AES_IVR1_IVI_Pos = 0x0
	// Bit mask of IVI field.
	AES_IVR1_IVI_Msk = 0xffffffff

	// IVR2: initialization vector register 2
	// Position of IVI field.
	AES_IVR2_IVI_Pos = 0x0
	// Bit mask of IVI field.
	AES_IVR2_IVI_Msk = 0xffffffff

	// IVR3: initialization vector register 3
	// Position of IVI field.
	AES_IVR3_IVI_Pos = 0x0
	// Bit mask of IVI field.
	AES_IVR3_IVI_Msk = 0xffffffff

	// KEYR4: key register 4
	// Position of KEY field.
	AES_KEYR4_KEY_Pos = 0x0
	// Bit mask of KEY field.
	AES_KEYR4_KEY_Msk = 0xffffffff

	// KEYR5: key register 5
	// Position of KEY field.
	AES_KEYR5_KEY_Pos = 0x0
	// Bit mask of KEY field.
	AES_KEYR5_KEY_Msk = 0xffffffff

	// KEYR6: key register 6
	// Position of KEY field.
	AES_KEYR6_KEY_Pos = 0x0
	// Bit mask of KEY field.
	AES_KEYR6_KEY_Msk = 0xffffffff

	// KEYR7: key register 7
	// Position of KEY field.
	AES_KEYR7_KEY_Pos = 0x0
	// Bit mask of KEY field.
	AES_KEYR7_KEY_Msk = 0xffffffff

	// SUSP0R: suspend registers
	// Position of SUSP field.
	AES_SUSP0R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP0R_SUSP_Msk = 0xffffffff

	// SUSP1R: suspend registers
	// Position of SUSP field.
	AES_SUSP1R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP1R_SUSP_Msk = 0xffffffff

	// SUSP2R: suspend registers
	// Position of SUSP field.
	AES_SUSP2R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP2R_SUSP_Msk = 0xffffffff

	// SUSP3R: suspend registers
	// Position of SUSP field.
	AES_SUSP3R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP3R_SUSP_Msk = 0xffffffff

	// SUSP4R: suspend registers
	// Position of SUSP field.
	AES_SUSP4R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP4R_SUSP_Msk = 0xffffffff

	// SUSP5R: suspend registers
	// Position of SUSP field.
	AES_SUSP5R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP5R_SUSP_Msk = 0xffffffff

	// SUSP6R: suspend registers
	// Position of SUSP field.
	AES_SUSP6R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP6R_SUSP_Msk = 0xffffffff

	// SUSP7R: suspend registers
	// Position of SUSP field.
	AES_SUSP7R_SUSP_Pos = 0x0
	// Bit mask of SUSP field.
	AES_SUSP7R_SUSP_Msk = 0xffffffff

	// IER: interrupt enable register
	// Position of CCFIE field.
	AES_IER_CCFIE_Pos = 0x0
	// Bit mask of CCFIE field.
	AES_IER_CCFIE_Msk = 0x1
	// Bit CCFIE.
	AES_IER_CCFIE = 0x1
	// Interrupt is disabled (masked)
	AES_IER_CCFIE_Disabled = 0x0
	// Interrupt is enabled (not masked)
	AES_IER_CCFIE_Enabled = 0x1
	// Position of KEIE field.
	AES_IER_KEIE_Pos = 0x2
	// Bit mask of KEIE field.
	AES_IER_KEIE_Msk = 0x4
	// Bit KEIE.
	AES_IER_KEIE = 0x4
	// Interrupt is disabled (masked)
	AES_IER_KEIE_Disabled = 0x0
	// Interrupt is enabled (not masked)
	AES_IER_KEIE_Enabled = 0x1
	// Position of RWEIE field.
	AES_IER_RWEIE_Pos = 0x1
	// Bit mask of RWEIE field.
	AES_IER_RWEIE_Msk = 0x2
	// Bit RWEIE.
	AES_IER_RWEIE = 0x2
	// Interrupt is disabled (masked)
	AES_IER_RWEIE_Disabled = 0x0
	// Interrupt is enabled (not masked)
	AES_IER_RWEIE_Enabled = 0x1

	// ISR: interrupt status register
	// Position of RWEIF field.
	AES_ISR_RWEIF_Pos = 0x1
	// Bit mask of RWEIF field.
	AES_ISR_RWEIF_Msk = 0x2
	// Bit RWEIF.
	AES_ISR_RWEIF = 0x2
	// No error detected
	AES_ISR_RWEIF_NoError = 0x0
	// The error detected
	AES_ISR_RWEIF_Error = 0x1
	// Position of KEIF field.
	AES_ISR_KEIF_Pos = 0x2
	// Bit mask of KEIF field.
	AES_ISR_KEIF_Msk = 0x4
	// Bit KEIF.
	AES_ISR_KEIF = 0x4
	// No error detected
	AES_ISR_KEIF_NoError = 0x0
	// The error detected
	AES_ISR_KEIF_Error = 0x1
	// Position of CCF field.
	AES_ISR_CCF_Pos = 0x0
	// Bit mask of CCF field.
	AES_ISR_CCF_Msk = 0x1
	// Bit CCF.
	AES_ISR_CCF = 0x1
	// Computation not completed
	AES_ISR_CCF_NotCompleted = 0x0
	// Computation completed
	AES_ISR_CCF_Completed = 0x1

	// ICR: interrupt clear register
	// Position of CCF field.
	AES_ICR_CCF_Pos = 0x0
	// Bit mask of CCF field.
	AES_ICR_CCF_Msk = 0x1
	// Bit CCF.
	AES_ICR_CCF = 0x1
	// Setting this bit clears corresponding interrupt status bit
	AES_ICR_CCF_Clear = 0x1
	// Position of KEIF field.
	AES_ICR_KEIF_Pos = 0x2
	// Bit mask of KEIF field.
	AES_ICR_KEIF_Msk = 0x4
	// Bit KEIF.
	AES_ICR_KEIF = 0x4
	// Setting this bit clears corresponding interrupt status bit
	AES_ICR_KEIF_Clear = 0x1
	// Position of RWEIF field.
	AES_ICR_RWEIF_Pos = 0x1
	// Bit mask of RWEIF field.
	AES_ICR_RWEIF_Msk = 0x2
	// Bit RWEIF.
	AES_ICR_RWEIF = 0x2
	// Setting this bit clears corresponding interrupt status bit
	AES_ICR_RWEIF_Clear = 0x1
)

// Constants for COMP: Comparator
const (
	// COMP1_CSR: Comparator 1 control and status register
	// Position of COMP1_EN field.
	COMP_COMP1_CSR_COMP1_EN_Pos = 0x0
	// Bit mask of COMP1_EN field.
	COMP_COMP1_CSR_COMP1_EN_Msk = 0x1
	// Bit COMP1_EN.
	COMP_COMP1_CSR_COMP1_EN = 0x1
	// Position of COMP1_INMSEL field.
	COMP_COMP1_CSR_COMP1_INMSEL_Pos = 0x4
	// Bit mask of COMP1_INMSEL field.
	COMP_COMP1_CSR_COMP1_INMSEL_Msk = 0xf0
	// Position of COMP1_INPSEL field.
	COMP_COMP1_CSR_COMP1_INPSEL_Pos = 0x8
	// Bit mask of COMP1_INPSEL field.
	COMP_COMP1_CSR_COMP1_INPSEL_Msk = 0x300
	// Position of COMP1_WINMODE field.
	COMP_COMP1_CSR_COMP1_WINMODE_Pos = 0xb
	// Bit mask of COMP1_WINMODE field.
	COMP_COMP1_CSR_COMP1_WINMODE_Msk = 0x800
	// Bit COMP1_WINMODE.
	COMP_COMP1_CSR_COMP1_WINMODE = 0x800
	// Position of COMP1_WINOUT field.
	COMP_COMP1_CSR_COMP1_WINOUT_Pos = 0xe
	// Bit mask of COMP1_WINOUT field.
	COMP_COMP1_CSR_COMP1_WINOUT_Msk = 0x4000
	// Bit COMP1_WINOUT.
	COMP_COMP1_CSR_COMP1_WINOUT = 0x4000
	// Position of COMP1_POLARITY field.
	COMP_COMP1_CSR_COMP1_POLARITY_Pos = 0xf
	// Bit mask of COMP1_POLARITY field.
	COMP_COMP1_CSR_COMP1_POLARITY_Msk = 0x8000
	// Bit COMP1_POLARITY.
	COMP_COMP1_CSR_COMP1_POLARITY = 0x8000
	// Position of COMP1_HYST field.
	COMP_COMP1_CSR_COMP1_HYST_Pos = 0x10
	// Bit mask of COMP1_HYST field.
	COMP_COMP1_CSR_COMP1_HYST_Msk = 0x30000
	// Position of COMP1_PWRMODE field.
	COMP_COMP1_CSR_COMP1_PWRMODE_Pos = 0x12
	// Bit mask of COMP1_PWRMODE field.
	COMP_COMP1_CSR_COMP1_PWRMODE_Msk = 0xc0000
	// Position of COMP1_BLANKSEL field.
	COMP_COMP1_CSR_COMP1_BLANKSEL_Pos = 0x14
	// Bit mask of COMP1_BLANKSEL field.
	COMP_COMP1_CSR_COMP1_BLANKSEL_Msk = 0x1f00000
	// Position of COMP1_VALUE field.
	COMP_COMP1_CSR_COMP1_VALUE_Pos = 0x1e
	// Bit mask of COMP1_VALUE field.
	COMP_COMP1_CSR_COMP1_VALUE_Msk = 0x40000000
	// Bit COMP1_VALUE.
	COMP_COMP1_CSR_COMP1_VALUE = 0x40000000
	// Position of COMP1_LOCK field.
	COMP_COMP1_CSR_COMP1_LOCK_Pos = 0x1f
	// Bit mask of COMP1_LOCK field.
	COMP_COMP1_CSR_COMP1_LOCK_Msk = 0x80000000
	// Bit COMP1_LOCK.
	COMP_COMP1_CSR_COMP1_LOCK = 0x80000000

	// COMP2_CSR: Comparator 2 control and status register
	// Position of COM2_EN field.
	COMP_COMP2_CSR_COM2_EN_Pos = 0x0
	// Bit mask of COM2_EN field.
	COMP_COMP2_CSR_COM2_EN_Msk = 0x1
	// Bit COM2_EN.
	COMP_COMP2_CSR_COM2_EN = 0x1
	// Position of COM2_INMSEL field.
	COMP_COMP2_CSR_COM2_INMSEL_Pos = 0x4
	// Bit mask of COM2_INMSEL field.
	COMP_COMP2_CSR_COM2_INMSEL_Msk = 0xf0
	// Position of COM2_INPSEL field.
	COMP_COMP2_CSR_COM2_INPSEL_Pos = 0x8
	// Bit mask of COM2_INPSEL field.
	COMP_COMP2_CSR_COM2_INPSEL_Msk = 0x300
	// Position of COM2_WINMODE field.
	COMP_COMP2_CSR_COM2_WINMODE_Pos = 0xb
	// Bit mask of COM2_WINMODE field.
	COMP_COMP2_CSR_COM2_WINMODE_Msk = 0x800
	// Bit COM2_WINMODE.
	COMP_COMP2_CSR_COM2_WINMODE = 0x800
	// Position of COM2_WINOUT field.
	COMP_COMP2_CSR_COM2_WINOUT_Pos = 0xe
	// Bit mask of COM2_WINOUT field.
	COMP_COMP2_CSR_COM2_WINOUT_Msk = 0x4000
	// Bit COM2_WINOUT.
	COMP_COMP2_CSR_COM2_WINOUT = 0x4000
	// Position of COM2_POLARITY field.
	COMP_COMP2_CSR_COM2_POLARITY_Pos = 0xf
	// Bit mask of COM2_POLARITY field.
	COMP_COMP2_CSR_COM2_POLARITY_Msk = 0x8000
	// Bit COM2_POLARITY.
	COMP_COMP2_CSR_COM2_POLARITY = 0x8000
	// Position of COM2_HYST field.
	COMP_COMP2_CSR_COM2_HYST_Pos = 0x10
	// Bit mask of COM2_HYST field.
	COMP_COMP2_CSR_COM2_HYST_Msk = 0x30000
	// Position of COM2_PWRMODE field.
	COMP_COMP2_CSR_COM2_PWRMODE_Pos = 0x12
	// Bit mask of COM2_PWRMODE field.
	COMP_COMP2_CSR_COM2_PWRMODE_Msk = 0xc0000
	// Position of COM2_BLANKSEL field.
	COMP_COMP2_CSR_COM2_BLANKSEL_Pos = 0x14
	// Bit mask of COM2_BLANKSEL field.
	COMP_COMP2_CSR_COM2_BLANKSEL_Msk = 0x1f00000
	// Position of COM2_VALUE field.
	COMP_COMP2_CSR_COM2_VALUE_Pos = 0x1e
	// Bit mask of COM2_VALUE field.
	COMP_COMP2_CSR_COM2_VALUE_Msk = 0x40000000
	// Bit COM2_VALUE.
	COMP_COMP2_CSR_COM2_VALUE = 0x40000000
	// Position of COM2_LOCK field.
	COMP_COMP2_CSR_COM2_LOCK_Pos = 0x1f
	// Bit mask of COM2_LOCK field.
	COMP_COMP2_CSR_COM2_LOCK_Msk = 0x80000000
	// Bit COM2_LOCK.
	COMP_COMP2_CSR_COM2_LOCK = 0x80000000
)

// Constants for CORDIC: CORDIC Co-processor
const (
	// CSR: CORDIC Control Status register
	// Position of FUNC field.
	CORDIC_CSR_FUNC_Pos = 0x0
	// Bit mask of FUNC field.
	CORDIC_CSR_FUNC_Msk = 0xf
	// Position of PRECISION field.
	CORDIC_CSR_PRECISION_Pos = 0x4
	// Bit mask of PRECISION field.
	CORDIC_CSR_PRECISION_Msk = 0xf0
	// Position of SCALE field.
	CORDIC_CSR_SCALE_Pos = 0x8
	// Bit mask of SCALE field.
	CORDIC_CSR_SCALE_Msk = 0x700
	// Position of IEN field.
	CORDIC_CSR_IEN_Pos = 0x10
	// Bit mask of IEN field.
	CORDIC_CSR_IEN_Msk = 0x10000
	// Bit IEN.
	CORDIC_CSR_IEN = 0x10000
	// Position of DMAREN field.
	CORDIC_CSR_DMAREN_Pos = 0x11
	// Bit mask of DMAREN field.
	CORDIC_CSR_DMAREN_Msk = 0x20000
	// Bit DMAREN.
	CORDIC_CSR_DMAREN = 0x20000
	// Position of DMAWEN field.
	CORDIC_CSR_DMAWEN_Pos = 0x12
	// Bit mask of DMAWEN field.
	CORDIC_CSR_DMAWEN_Msk = 0x40000
	// Bit DMAWEN.
	CORDIC_CSR_DMAWEN = 0x40000
	// Position of NRES field.
	CORDIC_CSR_NRES_Pos = 0x13
	// Bit mask of NRES field.
	CORDIC_CSR_NRES_Msk = 0x80000
	// Bit NRES.
	CORDIC_CSR_NRES = 0x80000
	// Position of NARGS field.
	CORDIC_CSR_NARGS_Pos = 0x14
	// Bit mask of NARGS field.
	CORDIC_CSR_NARGS_Msk = 0x100000
	// Bit NARGS.
	CORDIC_CSR_NARGS = 0x100000
	// Position of RESSIZE field.
	CORDIC_CSR_RESSIZE_Pos = 0x15
	// Bit mask of RESSIZE field.
	CORDIC_CSR_RESSIZE_Msk = 0x200000
	// Bit RESSIZE.
	CORDIC_CSR_RESSIZE = 0x200000
	// Position of ARGSIZE field.
	CORDIC_CSR_ARGSIZE_Pos = 0x16
	// Bit mask of ARGSIZE field.
	CORDIC_CSR_ARGSIZE_Msk = 0x400000
	// Bit ARGSIZE.
	CORDIC_CSR_ARGSIZE = 0x400000
	// Position of RRDY field.
	CORDIC_CSR_RRDY_Pos = 0x1f
	// Bit mask of RRDY field.
	CORDIC_CSR_RRDY_Msk = 0x80000000
	// Bit RRDY.
	CORDIC_CSR_RRDY = 0x80000000

	// WDATA: FMAC Write Data register
	// Position of ARG field.
	CORDIC_WDATA_ARG_Pos = 0x0
	// Bit mask of ARG field.
	CORDIC_WDATA_ARG_Msk = 0xffffffff

	// RDATA: FMAC Read Data register
	// Position of RES field.
	CORDIC_RDATA_RES_Pos = 0x0
	// Bit mask of RES field.
	CORDIC_RDATA_RES_Msk = 0xffffffff
)

// Constants for CRC: Cyclic redundancy check calculation unit
const (
	// DR: Data register
	// Position of DR field.
	CRC_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	CRC_DR_DR_Msk = 0xffffffff

	// DR8: Data register - byte sized
	// Position of DR8 field.
	CRC_DR8_DR8_Pos = 0x0
	// Bit mask of DR8 field.
	CRC_DR8_DR8_Msk = 0xff

	// DR16: Data register - half-word sized
	// Position of DR16 field.
	CRC_DR16_DR16_Pos = 0x0
	// Bit mask of DR16 field.
	CRC_DR16_DR16_Msk = 0xffff

	// IDR: Independent data register
	// Position of IDR field.
	CRC_IDR_IDR_Pos = 0x0
	// Bit mask of IDR field.
	CRC_IDR_IDR_Msk = 0xffffffff

	// CR: Control register
	// Position of REV_OUT field.
	CRC_CR_REV_OUT_Pos = 0x7
	// Bit mask of REV_OUT field.
	CRC_CR_REV_OUT_Msk = 0x80
	// Bit REV_OUT.
	CRC_CR_REV_OUT = 0x80
	// Bit order not affected
	CRC_CR_REV_OUT_Normal = 0x0
	// Bit reversed output
	CRC_CR_REV_OUT_Reversed = 0x1
	// Position of REV_IN field.
	CRC_CR_REV_IN_Pos = 0x5
	// Bit mask of REV_IN field.
	CRC_CR_REV_IN_Msk = 0x60
	// Bit order not affected
	CRC_CR_REV_IN_Normal = 0x0
	// Bit reversal done by byte
	CRC_CR_REV_IN_Byte = 0x1
	// Bit reversal done by half-word
	CRC_CR_REV_IN_HalfWord = 0x2
	// Bit reversal done by word
	CRC_CR_REV_IN_Word = 0x3
	// Position of POLYSIZE field.
	CRC_CR_POLYSIZE_Pos = 0x3
	// Bit mask of POLYSIZE field.
	CRC_CR_POLYSIZE_Msk = 0x18
	// 32-bit polynomial
	CRC_CR_POLYSIZE_Polysize32 = 0x0
	// 16-bit polynomial
	CRC_CR_POLYSIZE_Polysize16 = 0x1
	// 8-bit polynomial
	CRC_CR_POLYSIZE_Polysize8 = 0x2
	// 7-bit polynomial
	CRC_CR_POLYSIZE_Polysize7 = 0x3
	// Position of RESET field.
	CRC_CR_RESET_Pos = 0x0
	// Bit mask of RESET field.
	CRC_CR_RESET_Msk = 0x1
	// Bit RESET.
	CRC_CR_RESET = 0x1
	// Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
	CRC_CR_RESET_Reset = 0x1

	// INIT: Initial CRC value
	// Position of INIT field.
	CRC_INIT_INIT_Pos = 0x0
	// Bit mask of INIT field.
	CRC_INIT_INIT_Msk = 0xffffffff

	// POL: polynomial
	// Position of POL field.
	CRC_POL_POL_Pos = 0x0
	// Bit mask of POL field.
	CRC_POL_POL_Msk = 0xffffffff
)

// Constants for CRS: Clock recovery system
const (
	// CR: control register
	// Position of TRIM field.
	CRS_CR_TRIM_Pos = 0x8
	// Bit mask of TRIM field.
	CRS_CR_TRIM_Msk = 0x7f00
	// Position of SWSYNC field.
	CRS_CR_SWSYNC_Pos = 0x7
	// Bit mask of SWSYNC field.
	CRS_CR_SWSYNC_Msk = 0x80
	// Bit SWSYNC.
	CRS_CR_SWSYNC = 0x80
	// A software sync is generated
	CRS_CR_SWSYNC_Sync = 0x1
	// Position of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Pos = 0x6
	// Bit mask of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Msk = 0x40
	// Bit AUTOTRIMEN.
	CRS_CR_AUTOTRIMEN = 0x40
	// Automatic trimming disabled
	CRS_CR_AUTOTRIMEN_Disabled = 0x0
	// Automatic trimming enabled
	CRS_CR_AUTOTRIMEN_Enabled = 0x1
	// Position of CEN field.
	CRS_CR_CEN_Pos = 0x5
	// Bit mask of CEN field.
	CRS_CR_CEN_Msk = 0x20
	// Bit CEN.
	CRS_CR_CEN = 0x20
	// Frequency error counter disabled
	CRS_CR_CEN_Disabled = 0x0
	// Frequency error counter enabled
	CRS_CR_CEN_Enabled = 0x1
	// Position of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Pos = 0x0
	// Bit mask of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Msk = 0x1
	// Bit SYNCOKIE.
	CRS_CR_SYNCOKIE = 0x1
	// Interrupt disabled
	CRS_CR_SYNCOKIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_SYNCOKIE_Enabled = 0x1
	// Position of ESYNCIE field.
	CRS_CR_ESYNCIE_Pos = 0x3
	// Bit mask of ESYNCIE field.
	CRS_CR_ESYNCIE_Msk = 0x8
	// Bit ESYNCIE.
	CRS_CR_ESYNCIE = 0x8
	// Interrupt disabled
	CRS_CR_ESYNCIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_ESYNCIE_Enabled = 0x1
	// Position of ERRIE field.
	CRS_CR_ERRIE_Pos = 0x2
	// Bit mask of ERRIE field.
	CRS_CR_ERRIE_Msk = 0x4
	// Bit ERRIE.
	CRS_CR_ERRIE = 0x4
	// Interrupt disabled
	CRS_CR_ERRIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_ERRIE_Enabled = 0x1
	// Position of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Pos = 0x1
	// Bit mask of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Msk = 0x2
	// Bit SYNCWARNIE.
	CRS_CR_SYNCWARNIE = 0x2
	// Interrupt disabled
	CRS_CR_SYNCWARNIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_SYNCWARNIE_Enabled = 0x1

	// CFGR: configuration register
	// Position of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Pos = 0x1f
	// Bit mask of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Msk = 0x80000000
	// Bit SYNCPOL.
	CRS_CFGR_SYNCPOL = 0x80000000
	// SYNC active on rising edge
	CRS_CFGR_SYNCPOL_RisingEdge = 0x0
	// SYNC active on falling edge
	CRS_CFGR_SYNCPOL_FallingEdge = 0x1
	// Position of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Pos = 0x1c
	// Bit mask of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Msk = 0x30000000
	// GPIO AF (crs_sync_in_1) selected as SYNC signal source
	CRS_CFGR_SYNCSRC_GPIO_AF = 0x0
	// LSE (crs_sync_in_2) selected as SYNC signal source
	CRS_CFGR_SYNCSRC_LSE = 0x1
	// USB SOF (crs_sync_in_3) selected as SYNC signal source
	CRS_CFGR_SYNCSRC_USB_SOF = 0x2
	// Position of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Pos = 0x18
	// Bit mask of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Msk = 0x7000000
	// SYNC not divided
	CRS_CFGR_SYNCDIV_Div1 = 0x0
	// SYNC divided by 2
	CRS_CFGR_SYNCDIV_Div2 = 0x1
	// SYNC divided by 4
	CRS_CFGR_SYNCDIV_Div4 = 0x2
	// SYNC divided by 8
	CRS_CFGR_SYNCDIV_Div8 = 0x3
	// SYNC divided by 16
	CRS_CFGR_SYNCDIV_Div16 = 0x4
	// SYNC divided by 32
	CRS_CFGR_SYNCDIV_Div32 = 0x5
	// SYNC divided by 64
	CRS_CFGR_SYNCDIV_Div64 = 0x6
	// SYNC divided by 128
	CRS_CFGR_SYNCDIV_Div128 = 0x7
	// Position of FELIM field.
	CRS_CFGR_FELIM_Pos = 0x10
	// Bit mask of FELIM field.
	CRS_CFGR_FELIM_Msk = 0xff0000
	// Position of RELOAD field.
	CRS_CFGR_RELOAD_Pos = 0x0
	// Bit mask of RELOAD field.
	CRS_CFGR_RELOAD_Msk = 0xffff

	// ISR: interrupt and status register
	// Position of FECAP field.
	CRS_ISR_FECAP_Pos = 0x10
	// Bit mask of FECAP field.
	CRS_ISR_FECAP_Msk = 0xffff0000
	// Position of FEDIR field.
	CRS_ISR_FEDIR_Pos = 0xf
	// Bit mask of FEDIR field.
	CRS_ISR_FEDIR_Msk = 0x8000
	// Bit FEDIR.
	CRS_ISR_FEDIR = 0x8000
	// Error in up-counting direction
	CRS_ISR_FEDIR_UpCounting = 0x0
	// Error in down-counting direction
	CRS_ISR_FEDIR_DownCounting = 0x1
	// Position of SYNCOKF field.
	CRS_ISR_SYNCOKF_Pos = 0x0
	// Bit mask of SYNCOKF field.
	CRS_ISR_SYNCOKF_Msk = 0x1
	// Bit SYNCOKF.
	CRS_ISR_SYNCOKF = 0x1
	// Signal not set
	CRS_ISR_SYNCOKF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCOKF_Signaled = 0x1
	// Position of TRIMOVF field.
	CRS_ISR_TRIMOVF_Pos = 0xa
	// Bit mask of TRIMOVF field.
	CRS_ISR_TRIMOVF_Msk = 0x400
	// Bit TRIMOVF.
	CRS_ISR_TRIMOVF = 0x400
	// Signal not set
	CRS_ISR_TRIMOVF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_TRIMOVF_Signaled = 0x1
	// Position of SYNCMISS field.
	CRS_ISR_SYNCMISS_Pos = 0x9
	// Bit mask of SYNCMISS field.
	CRS_ISR_SYNCMISS_Msk = 0x200
	// Bit SYNCMISS.
	CRS_ISR_SYNCMISS = 0x200
	// Signal not set
	CRS_ISR_SYNCMISS_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCMISS_Signaled = 0x1
	// Position of SYNCERR field.
	CRS_ISR_SYNCERR_Pos = 0x8
	// Bit mask of SYNCERR field.
	CRS_ISR_SYNCERR_Msk = 0x100
	// Bit SYNCERR.
	CRS_ISR_SYNCERR = 0x100
	// Signal not set
	CRS_ISR_SYNCERR_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCERR_Signaled = 0x1
	// Position of ESYNCF field.
	CRS_ISR_ESYNCF_Pos = 0x3
	// Bit mask of ESYNCF field.
	CRS_ISR_ESYNCF_Msk = 0x8
	// Bit ESYNCF.
	CRS_ISR_ESYNCF = 0x8
	// Signal not set
	CRS_ISR_ESYNCF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_ESYNCF_Signaled = 0x1
	// Position of ERRF field.
	CRS_ISR_ERRF_Pos = 0x2
	// Bit mask of ERRF field.
	CRS_ISR_ERRF_Msk = 0x4
	// Bit ERRF.
	CRS_ISR_ERRF = 0x4
	// Signal not set
	CRS_ISR_ERRF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_ERRF_Signaled = 0x1
	// Position of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Pos = 0x1
	// Bit mask of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Msk = 0x2
	// Bit SYNCWARNF.
	CRS_ISR_SYNCWARNF = 0x2
	// Signal not set
	CRS_ISR_SYNCWARNF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCWARNF_Signaled = 0x1

	// ICR: interrupt flag clear register
	// Position of SYNCOKC field.
	CRS_ICR_SYNCOKC_Pos = 0x0
	// Bit mask of SYNCOKC field.
	CRS_ICR_SYNCOKC_Msk = 0x1
	// Bit SYNCOKC.
	CRS_ICR_SYNCOKC = 0x1
	// Clear flag
	CRS_ICR_SYNCOKC_Clear = 0x1
	// Position of ESYNCC field.
	CRS_ICR_ESYNCC_Pos = 0x3
	// Bit mask of ESYNCC field.
	CRS_ICR_ESYNCC_Msk = 0x8
	// Bit ESYNCC.
	CRS_ICR_ESYNCC = 0x8
	// Clear flag
	CRS_ICR_ESYNCC_Clear = 0x1
	// Position of ERRC field.
	CRS_ICR_ERRC_Pos = 0x2
	// Bit mask of ERRC field.
	CRS_ICR_ERRC_Msk = 0x4
	// Bit ERRC.
	CRS_ICR_ERRC = 0x4
	// Clear flag
	CRS_ICR_ERRC_Clear = 0x1
	// Position of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Pos = 0x1
	// Bit mask of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Msk = 0x2
	// Bit SYNCWARNC.
	CRS_ICR_SYNCWARNC = 0x2
	// Clear flag
	CRS_ICR_SYNCWARNC_Clear = 0x1
)

// Constants for DAC1: Digital-to-analog converter
const (
	// CR: DAC control register
	// Position of EN1 field.
	DAC_CR_EN1_Pos = 0x10
	// Bit mask of EN1 field.
	DAC_CR_EN1_Msk = 0x10000
	// Bit EN1.
	DAC_CR_EN1 = 0x10000
	// DAC Channel X disabled
	DAC_CR_EN1_Disabled = 0x0
	// DAC Channel X enabled
	DAC_CR_EN1_Enabled = 0x1
	// Position of EN2 field.
	DAC_CR_EN2_Pos = 0x20
	// Bit mask of EN2 field.
	DAC_CR_EN2_Msk = 0x100000000
	// Bit EN2.
	DAC_CR_EN2 = 0x100000000
	// DAC Channel X disabled
	DAC_CR_EN2_Disabled = 0x0
	// DAC Channel X enabled
	DAC_CR_EN2_Enabled = 0x1
	// Position of TEN1 field.
	DAC_CR_TEN1_Pos = 0x11
	// Bit mask of TEN1 field.
	DAC_CR_TEN1_Msk = 0x20000
	// Bit TEN1.
	DAC_CR_TEN1 = 0x20000
	// DAC Channel X trigger disabled
	DAC_CR_TEN1_Disabled = 0x0
	// DAC Channel X trigger enabled
	DAC_CR_TEN1_Enabled = 0x1
	// Position of TEN2 field.
	DAC_CR_TEN2_Pos = 0x21
	// Bit mask of TEN2 field.
	DAC_CR_TEN2_Msk = 0x200000000
	// Bit TEN2.
	DAC_CR_TEN2 = 0x200000000
	// DAC Channel X trigger disabled
	DAC_CR_TEN2_Disabled = 0x0
	// DAC Channel X trigger enabled
	DAC_CR_TEN2_Enabled = 0x1
	// Position of TSEL1 field.
	DAC_CR_TSEL1_Pos = 0x2
	// Bit mask of TSEL1 field.
	DAC_CR_TSEL1_Msk = 0x3c
	// Software trigger
	DAC_CR_TSEL1_Swtrig = 0x0
	// Timer 1 TRGO event
	DAC_CR_TSEL1_Tim1Trgo = 0x1
	// Timer 2 TRGO event
	DAC_CR_TSEL1_Tim2Trgo = 0x2
	// Timer 4 TRGO event
	DAC_CR_TSEL1_Tim4Trgo = 0x3
	// Timer 5 TRGO event
	DAC_CR_TSEL1_Tim5Trgo = 0x4
	// Timer 6 TRGO event
	DAC_CR_TSEL1_Tim6Trgo = 0x5
	// Timer 7 TRGO event
	DAC_CR_TSEL1_Tim7Trgo = 0x6
	// Timer 8 TRGO event
	DAC_CR_TSEL1_Tim8Trgo = 0x7
	// Timer 15 TRGO event
	DAC_CR_TSEL1_Tim15Trgo = 0x8
	// LPTIM1 CH1 event
	DAC_CR_TSEL1_Lptim1Ch1 = 0xb
	// LPTIM3 CH1 event
	DAC_CR_TSEL1_Lptim3Ch1 = 0xc
	// EXTI line 9
	DAC_CR_TSEL1_Exti9 = 0xd
	// Position of WAVE1 field.
	DAC_CR_WAVE1_Pos = 0x16
	// Bit mask of WAVE1 field.
	DAC_CR_WAVE1_Msk = 0xc00000
	// Wave generation disabled
	DAC_CR_WAVE1_Disabled = 0x0
	// Noise wave generation enabled
	DAC_CR_WAVE1_Noise = 0x1
	// Triangle wave generation enabled
	DAC_CR_WAVE1_Triangle = 0x2
	// Position of WAVE2 field.
	DAC_CR_WAVE2_Pos = 0x26
	// Bit mask of WAVE2 field.
	DAC_CR_WAVE2_Msk = 0xc000000000
	// Wave generation disabled
	DAC_CR_WAVE2_Disabled = 0x0
	// Noise wave generation enabled
	DAC_CR_WAVE2_Noise = 0x1
	// Triangle wave generation enabled
	DAC_CR_WAVE2_Triangle = 0x2
	// Position of MAMP1 field.
	DAC_CR_MAMP1_Pos = 0x18
	// Bit mask of MAMP1 field.
	DAC_CR_MAMP1_Msk = 0xf000000
	// Unmask bit0 of LFSR/ triangle amplitude equal to 1
	DAC_CR_MAMP1_Amp1 = 0x0
	// Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
	DAC_CR_MAMP1_Amp3 = 0x1
	// Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
	DAC_CR_MAMP1_Amp7 = 0x2
	// Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
	DAC_CR_MAMP1_Amp15 = 0x3
	// Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
	DAC_CR_MAMP1_Amp31 = 0x4
	// Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
	DAC_CR_MAMP1_Amp63 = 0x5
	// Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
	DAC_CR_MAMP1_Amp127 = 0x6
	// Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
	DAC_CR_MAMP1_Amp255 = 0x7
	// Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
	DAC_CR_MAMP1_Amp511 = 0x8
	// Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
	DAC_CR_MAMP1_Amp1023 = 0x9
	// Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
	DAC_CR_MAMP1_Amp2047 = 0xa
	// Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
	DAC_CR_MAMP1_Amp4095 = 0xb
	// Position of MAMP2 field.
	DAC_CR_MAMP2_Pos = 0x28
	// Bit mask of MAMP2 field.
	DAC_CR_MAMP2_Msk = 0xf0000000000
	// Unmask bit0 of LFSR/ triangle amplitude equal to 1
	DAC_CR_MAMP2_Amp1 = 0x0
	// Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
	DAC_CR_MAMP2_Amp3 = 0x1
	// Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
	DAC_CR_MAMP2_Amp7 = 0x2
	// Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
	DAC_CR_MAMP2_Amp15 = 0x3
	// Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
	DAC_CR_MAMP2_Amp31 = 0x4
	// Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
	DAC_CR_MAMP2_Amp63 = 0x5
	// Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
	DAC_CR_MAMP2_Amp127 = 0x6
	// Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
	DAC_CR_MAMP2_Amp255 = 0x7
	// Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
	DAC_CR_MAMP2_Amp511 = 0x8
	// Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
	DAC_CR_MAMP2_Amp1023 = 0x9
	// Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
	DAC_CR_MAMP2_Amp2047 = 0xa
	// Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
	DAC_CR_MAMP2_Amp4095 = 0xb
	// Position of DMAEN1 field.
	DAC_CR_DMAEN1_Pos = 0x1c
	// Bit mask of DMAEN1 field.
	DAC_CR_DMAEN1_Msk = 0x10000000
	// Bit DMAEN1.
	DAC_CR_DMAEN1 = 0x10000000
	// DAC Channel X DMA mode disabled
	DAC_CR_DMAEN1_Disabled = 0x0
	// DAC Channel X DMA mode enabled
	DAC_CR_DMAEN1_Enabled = 0x1
	// Position of DMAEN2 field.
	DAC_CR_DMAEN2_Pos = 0x2c
	// Bit mask of DMAEN2 field.
	DAC_CR_DMAEN2_Msk = 0x100000000000
	// Bit DMAEN2.
	DAC_CR_DMAEN2 = 0x100000000000
	// DAC Channel X DMA mode disabled
	DAC_CR_DMAEN2_Disabled = 0x0
	// DAC Channel X DMA mode enabled
	DAC_CR_DMAEN2_Enabled = 0x1
	// Position of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1_Pos = 0x1d
	// Bit mask of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1_Msk = 0x20000000
	// Bit DMAUDRIE1.
	DAC_CR_DMAUDRIE1 = 0x20000000
	// DAC channel X DMA Underrun Interrupt disabled
	DAC_CR_DMAUDRIE1_Disabled = 0x0
	// DAC channel X DMA Underrun Interrupt enabled
	DAC_CR_DMAUDRIE1_Enabled = 0x1
	// Position of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2_Pos = 0x2d
	// Bit mask of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2_Msk = 0x200000000000
	// Bit DMAUDRIE2.
	DAC_CR_DMAUDRIE2 = 0x200000000000
	// DAC channel X DMA Underrun Interrupt disabled
	DAC_CR_DMAUDRIE2_Disabled = 0x0
	// DAC channel X DMA Underrun Interrupt enabled
	DAC_CR_DMAUDRIE2_Enabled = 0x1
	// Position of CEN1 field.
	DAC_CR_CEN1_Pos = 0x1e
	// Bit mask of CEN1 field.
	DAC_CR_CEN1_Msk = 0x40000000
	// Bit CEN1.
	DAC_CR_CEN1 = 0x40000000
	// DAC Channel X Normal operating mode
	DAC_CR_CEN1_Normal = 0x0
	// DAC Channel X calibration mode
	DAC_CR_CEN1_Calibration = 0x1
	// Position of CEN2 field.
	DAC_CR_CEN2_Pos = 0x2e
	// Bit mask of CEN2 field.
	DAC_CR_CEN2_Msk = 0x400000000000
	// Bit CEN2.
	DAC_CR_CEN2 = 0x400000000000
	// DAC Channel X Normal operating mode
	DAC_CR_CEN2_Normal = 0x0
	// DAC Channel X calibration mode
	DAC_CR_CEN2_Calibration = 0x1
	// Position of TSEL2 field.
	DAC_CR_TSEL2_Pos = 0x12
	// Bit mask of TSEL2 field.
	DAC_CR_TSEL2_Msk = 0x3c0000
	// Software trigger
	DAC_CR_TSEL2_Swtrig = 0x0
	// Timer 1 TRGO event
	DAC_CR_TSEL2_Tim1Trgo = 0x1
	// Timer 2 TRGO event
	DAC_CR_TSEL2_Tim2Trgo = 0x2
	// Timer 4 TRGO event
	DAC_CR_TSEL2_Tim4Trgo = 0x3
	// Timer 5 TRGO event
	DAC_CR_TSEL2_Tim5Trgo = 0x4
	// Timer 6 TRGO event
	DAC_CR_TSEL2_Tim6Trgo = 0x5
	// Timer 7 TRGO event
	DAC_CR_TSEL2_Tim7Trgo = 0x6
	// Timer 8 TRGO event
	DAC_CR_TSEL2_Tim8Trgo = 0x7
	// Timer 15 TRGO event
	DAC_CR_TSEL2_Tim15Trgo = 0x8
	// LPTIM1 CH1 event
	DAC_CR_TSEL2_Lptim1Ch1 = 0xb
	// LPTIM3 CH1 event
	DAC_CR_TSEL2_Lptim3Ch1 = 0xc
	// EXTI line 9
	DAC_CR_TSEL2_Exti9 = 0xd

	// SWTRGR: DAC software trigger register
	// Position of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1_Pos = 0x1
	// Bit mask of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1_Msk = 0x2
	// Bit SWTRIG1.
	DAC_SWTRGR_SWTRIG1 = 0x2
	// No trigger
	DAC_SWTRGR_SWTRIG1_NoTrigger = 0x0
	// Trigger
	DAC_SWTRGR_SWTRIG1_Trigger = 0x1
	// Position of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2_Pos = 0x2
	// Bit mask of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2_Msk = 0x4
	// Bit SWTRIG2.
	DAC_SWTRGR_SWTRIG2 = 0x4
	// No trigger
	DAC_SWTRGR_SWTRIG2_NoTrigger = 0x0
	// Trigger
	DAC_SWTRGR_SWTRIG2_Trigger = 0x1

	// DHR12R1: channel%s 12-bit right-aligned data holding register
	// Position of DACCDHR field.
	DAC_DHR12R_DACCDHR_Pos = 0x0
	// Bit mask of DACCDHR field.
	DAC_DHR12R_DACCDHR_Msk = 0xfff
	// Position of DACC1DHRB field.
	DAC_DHR12R_DACC1DHRB_Pos = 0x10
	// Bit mask of DACC1DHRB field.
	DAC_DHR12R_DACC1DHRB_Msk = 0xfff0000

	// DHR12L1: channel%s 12-bit left aligned data holding register
	// Position of DACCDHR field.
	DAC_DHR12L_DACCDHR_Pos = 0x4
	// Bit mask of DACCDHR field.
	DAC_DHR12L_DACCDHR_Msk = 0xfff0
	// Position of DACC1DHRB field.
	DAC_DHR12L_DACC1DHRB_Pos = 0x14
	// Bit mask of DACC1DHRB field.
	DAC_DHR12L_DACC1DHRB_Msk = 0xfff00000

	// DHR8R1: channel%s 8-bit right aligned data holding register
	// Position of DACCDHR field.
	DAC_DHR8R_DACCDHR_Pos = 0x0
	// Bit mask of DACCDHR field.
	DAC_DHR8R_DACCDHR_Msk = 0xff
	// Position of DACC1DHRB field.
	DAC_DHR8R_DACC1DHRB_Pos = 0x8
	// Bit mask of DACC1DHRB field.
	DAC_DHR8R_DACC1DHRB_Msk = 0xff00

	// DHR12RD: Dual DAC 12-bit right-aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12RD_DACC1DHR_Pos = 0x10
	// Bit mask of DACC1DHR field.
	DAC_DHR12RD_DACC1DHR_Msk = 0xfff0000
	// Position of DACC2DHR field.
	DAC_DHR12RD_DACC2DHR_Pos = 0x20
	// Bit mask of DACC2DHR field.
	DAC_DHR12RD_DACC2DHR_Msk = 0xfff00000000

	// DHR12LD: DUAL DAC 12-bit left aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12LD_DACC1DHR_Pos = 0x14
	// Bit mask of DACC1DHR field.
	DAC_DHR12LD_DACC1DHR_Msk = 0xfff00000
	// Position of DACC2DHR field.
	DAC_DHR12LD_DACC2DHR_Pos = 0x24
	// Bit mask of DACC2DHR field.
	DAC_DHR12LD_DACC2DHR_Msk = 0xfff000000000

	// DHR8RD: DUAL DAC 8-bit right aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR8RD_DACC1DHR_Pos = 0x8
	// Bit mask of DACC1DHR field.
	DAC_DHR8RD_DACC1DHR_Msk = 0xff00
	// Position of DACC2DHR field.
	DAC_DHR8RD_DACC2DHR_Pos = 0x10
	// Bit mask of DACC2DHR field.
	DAC_DHR8RD_DACC2DHR_Msk = 0xff0000

	// DOR1: channel%s data output register
	// Position of DACCDOR field.
	DAC_DOR_DACCDOR_Pos = 0x0
	// Bit mask of DACCDOR field.
	DAC_DOR_DACCDOR_Msk = 0xfff
	// Position of DACC1DORB field.
	DAC_DOR_DACC1DORB_Pos = 0x10
	// Bit mask of DACC1DORB field.
	DAC_DOR_DACC1DORB_Msk = 0xfff0000

	// SR: DAC status register
	// Position of DAC1RDY field.
	DAC_SR_DAC1RDY_Pos = 0x1b
	// Bit mask of DAC1RDY field.
	DAC_SR_DAC1RDY_Msk = 0x8000000
	// Bit DAC1RDY.
	DAC_SR_DAC1RDY = 0x8000000
	// DAC channelX is not yet ready to accept the trigger nor output data
	DAC_SR_DAC1RDY_NotReady = 0x0
	// DAC channelX is ready to accept the trigger or output data
	DAC_SR_DAC1RDY_Ready = 0x1
	// Position of DAC2RDY field.
	DAC_SR_DAC2RDY_Pos = 0x2b
	// Bit mask of DAC2RDY field.
	DAC_SR_DAC2RDY_Msk = 0x80000000000
	// Bit DAC2RDY.
	DAC_SR_DAC2RDY = 0x80000000000
	// DAC channelX is not yet ready to accept the trigger nor output data
	DAC_SR_DAC2RDY_NotReady = 0x0
	// DAC channelX is ready to accept the trigger or output data
	DAC_SR_DAC2RDY_Ready = 0x1
	// Position of DORSTAT1 field.
	DAC_SR_DORSTAT1_Pos = 0x1c
	// Bit mask of DORSTAT1 field.
	DAC_SR_DORSTAT1_Msk = 0x10000000
	// Bit DORSTAT1.
	DAC_SR_DORSTAT1 = 0x10000000
	// DOR[11:0] is used actual DAC output
	DAC_SR_DORSTAT1_Dor = 0x0
	// DORB[11:0] is used actual DAC output
	DAC_SR_DORSTAT1_Dorb = 0x1
	// Position of DORSTAT2 field.
	DAC_SR_DORSTAT2_Pos = 0x2c
	// Bit mask of DORSTAT2 field.
	DAC_SR_DORSTAT2_Msk = 0x100000000000
	// Bit DORSTAT2.
	DAC_SR_DORSTAT2 = 0x100000000000
	// DOR[11:0] is used actual DAC output
	DAC_SR_DORSTAT2_Dor = 0x0
	// DORB[11:0] is used actual DAC output
	DAC_SR_DORSTAT2_Dorb = 0x1
	// Position of DMAUDR1 field.
	DAC_SR_DMAUDR1_Pos = 0x1d
	// Bit mask of DMAUDR1 field.
	DAC_SR_DMAUDR1_Msk = 0x20000000
	// Bit DMAUDR1.
	DAC_SR_DMAUDR1 = 0x20000000
	// No DMA underrun error condition occurred for DAC channel x
	DAC_SR_DMAUDR1_NoUnderrun = 0x0
	// DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
	DAC_SR_DMAUDR1_Underrun = 0x1
	// Position of DMAUDR2 field.
	DAC_SR_DMAUDR2_Pos = 0x2d
	// Bit mask of DMAUDR2 field.
	DAC_SR_DMAUDR2_Msk = 0x200000000000
	// Bit DMAUDR2.
	DAC_SR_DMAUDR2 = 0x200000000000
	// No DMA underrun error condition occurred for DAC channel x
	DAC_SR_DMAUDR2_NoUnderrun = 0x0
	// DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
	DAC_SR_DMAUDR2_Underrun = 0x1
	// Position of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1_Pos = 0x1e
	// Bit mask of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1_Msk = 0x40000000
	// Bit CAL_FLAG1.
	DAC_SR_CAL_FLAG1 = 0x40000000
	// Calibration trimming value is lower than the offset correction value
	DAC_SR_CAL_FLAG1_Lower = 0x0
	// Calibration trimming value is equal or greater than the offset correction value
	DAC_SR_CAL_FLAG1_Equal_Higher = 0x1
	// Position of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2_Pos = 0x2e
	// Bit mask of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2_Msk = 0x400000000000
	// Bit CAL_FLAG2.
	DAC_SR_CAL_FLAG2 = 0x400000000000
	// Calibration trimming value is lower than the offset correction value
	DAC_SR_CAL_FLAG2_Lower = 0x0
	// Calibration trimming value is equal or greater than the offset correction value
	DAC_SR_CAL_FLAG2_Equal_Higher = 0x1
	// Position of BWST1 field.
	DAC_SR_BWST1_Pos = 0x1f
	// Bit mask of BWST1 field.
	DAC_SR_BWST1_Msk = 0x80000000
	// Bit BWST1.
	DAC_SR_BWST1 = 0x80000000
	// There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
	DAC_SR_BWST1_Idle = 0x0
	// There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
	DAC_SR_BWST1_Busy = 0x1
	// Position of BWST2 field.
	DAC_SR_BWST2_Pos = 0x2f
	// Bit mask of BWST2 field.
	DAC_SR_BWST2_Msk = 0x800000000000
	// Bit BWST2.
	DAC_SR_BWST2 = 0x800000000000
	// There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
	DAC_SR_BWST2_Idle = 0x0
	// There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
	DAC_SR_BWST2_Busy = 0x1

	// CCR: DAC calibration control register
	// Position of OTRIM1 field.
	DAC_CCR_OTRIM1_Pos = 0x10
	// Bit mask of OTRIM1 field.
	DAC_CCR_OTRIM1_Msk = 0x1f0000
	// Position of OTRIM2 field.
	DAC_CCR_OTRIM2_Pos = 0x20
	// Bit mask of OTRIM2 field.
	DAC_CCR_OTRIM2_Msk = 0x1f00000000

	// MCR: DAC mode control register
	// Position of MODE1 field.
	DAC_MCR_MODE1_Pos = 0x10
	// Bit mask of MODE1 field.
	DAC_MCR_MODE1_Msk = 0x70000
	// Normal mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE1_NormalPinBuffer = 0x0
	// Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE1_NormalPinChipBuffer = 0x1
	// Normal mode - DAC channelx is connected to external pin with Buffer disabled
	DAC_MCR_MODE1_NormalPinNoBuffer = 0x2
	// Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE1_NormalChipNoBuffer = 0x3
	// S&H mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE1_SHPinBuffer = 0x4
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE1_SHPinChipBuffer = 0x5
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
	DAC_MCR_MODE1_SHPinNoBuffer = 0x6
	// S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE1_SHChipNoBuffer = 0x7
	// Position of MODE2 field.
	DAC_MCR_MODE2_Pos = 0x20
	// Bit mask of MODE2 field.
	DAC_MCR_MODE2_Msk = 0x700000000
	// Normal mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE2_NormalPinBuffer = 0x0
	// Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE2_NormalPinChipBuffer = 0x1
	// Normal mode - DAC channelx is connected to external pin with Buffer disabled
	DAC_MCR_MODE2_NormalPinNoBuffer = 0x2
	// Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE2_NormalChipNoBuffer = 0x3
	// S&H mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE2_SHPinBuffer = 0x4
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE2_SHPinChipBuffer = 0x5
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
	DAC_MCR_MODE2_SHPinNoBuffer = 0x6
	// S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE2_SHChipNoBuffer = 0x7
	// Position of DMADOUBLE1 field.
	DAC_MCR_DMADOUBLE1_Pos = 0x18
	// Bit mask of DMADOUBLE1 field.
	DAC_MCR_DMADOUBLE1_Msk = 0x1000000
	// Bit DMADOUBLE1.
	DAC_MCR_DMADOUBLE1 = 0x1000000
	// DMA Normal mode selected
	DAC_MCR_DMADOUBLE1_Normal = 0x0
	// DMA Double data mode selected
	DAC_MCR_DMADOUBLE1_DoubleData = 0x1
	// Position of DMADOUBLE2 field.
	DAC_MCR_DMADOUBLE2_Pos = 0x28
	// Bit mask of DMADOUBLE2 field.
	DAC_MCR_DMADOUBLE2_Msk = 0x10000000000
	// Bit DMADOUBLE2.
	DAC_MCR_DMADOUBLE2 = 0x10000000000
	// DMA Normal mode selected
	DAC_MCR_DMADOUBLE2_Normal = 0x0
	// DMA Double data mode selected
	DAC_MCR_DMADOUBLE2_DoubleData = 0x1
	// Position of SINFORMAT1 field.
	DAC_MCR_SINFORMAT1_Pos = 0x19
	// Bit mask of SINFORMAT1 field.
	DAC_MCR_SINFORMAT1_Msk = 0x2000000
	// Bit SINFORMAT1.
	DAC_MCR_SINFORMAT1 = 0x2000000
	// Input data is in unsigned format
	DAC_MCR_SINFORMAT1_Unsigned = 0x0
	// Input data is in signed format (2's complement). The MSB bit represents the sign.
	DAC_MCR_SINFORMAT1_Signed = 0x1
	// Position of SINFORMAT2 field.
	DAC_MCR_SINFORMAT2_Pos = 0x29
	// Bit mask of SINFORMAT2 field.
	DAC_MCR_SINFORMAT2_Msk = 0x20000000000
	// Bit SINFORMAT2.
	DAC_MCR_SINFORMAT2 = 0x20000000000
	// Input data is in unsigned format
	DAC_MCR_SINFORMAT2_Unsigned = 0x0
	// Input data is in signed format (2's complement). The MSB bit represents the sign.
	DAC_MCR_SINFORMAT2_Signed = 0x1
	// Position of HFSEL field.
	DAC_MCR_HFSEL_Pos = 0xe
	// Bit mask of HFSEL field.
	DAC_MCR_HFSEL_Msk = 0xc000
	// High frequency interface mode disabled
	DAC_MCR_HFSEL_Disabled = 0x0
	// High frequency interface mode enabled for AHB clock frequency > 80 MHz
	DAC_MCR_HFSEL_More80Mhz = 0x1
	// High frequency interface mode enabled for AHB clock frequency >160 MHz
	DAC_MCR_HFSEL_More160Mhz = 0x2

	// SHSR1: DAC channel%s sample and hold sample time register
	// Position of TSAMPLE field.
	DAC_SHSR_TSAMPLE_Pos = 0x0
	// Bit mask of TSAMPLE field.
	DAC_SHSR_TSAMPLE_Msk = 0x3ff

	// SHHR: DAC Sample and Hold hold time register
	// Position of THOLD1 field.
	DAC_SHHR_THOLD1_Pos = 0x10
	// Bit mask of THOLD1 field.
	DAC_SHHR_THOLD1_Msk = 0x3ff0000
	// Position of THOLD2 field.
	DAC_SHHR_THOLD2_Pos = 0x20
	// Bit mask of THOLD2 field.
	DAC_SHHR_THOLD2_Msk = 0x3ff00000000

	// SHRR: DAC Sample and Hold refresh time register
	// Position of TREFRESH1 field.
	DAC_SHRR_TREFRESH1_Pos = 0x10
	// Bit mask of TREFRESH1 field.
	DAC_SHRR_TREFRESH1_Msk = 0xff0000
	// Position of TREFRESH2 field.
	DAC_SHRR_TREFRESH2_Pos = 0x20
	// Bit mask of TREFRESH2 field.
	DAC_SHRR_TREFRESH2_Msk = 0xff00000000

	// AUTOCR: Autonomous mode control register
	// Position of AUTOMODE field.
	DAC_AUTOCR_AUTOMODE_Pos = 0x16
	// Bit mask of AUTOMODE field.
	DAC_AUTOCR_AUTOMODE_Msk = 0x400000
	// Bit AUTOMODE.
	DAC_AUTOCR_AUTOMODE = 0x400000
	// DAC Autonomous mode disabled
	DAC_AUTOCR_AUTOMODE_Disabled = 0x0
	// DAC Autonomous mode enabled
	DAC_AUTOCR_AUTOMODE_Enabled = 0x1
)

// Constants for DBGMCU: MCU debug component
const (
	// IDCODE: DBGMCU_IDCODE
	// Position of DEV_ID field.
	DBGMCU_IDCODE_DEV_ID_Pos = 0x0
	// Bit mask of DEV_ID field.
	DBGMCU_IDCODE_DEV_ID_Msk = 0xfff
	// Position of REV_ID field.
	DBGMCU_IDCODE_REV_ID_Pos = 0x10
	// Bit mask of REV_ID field.
	DBGMCU_IDCODE_REV_ID_Msk = 0xffff0000

	// CR: Debug MCU configuration register
	// Position of DBG_STOP field.
	DBGMCU_CR_DBG_STOP_Pos = 0x1
	// Bit mask of DBG_STOP field.
	DBGMCU_CR_DBG_STOP_Msk = 0x2
	// Bit DBG_STOP.
	DBGMCU_CR_DBG_STOP = 0x2
	// Position of DBG_STANDBY field.
	DBGMCU_CR_DBG_STANDBY_Pos = 0x2
	// Bit mask of DBG_STANDBY field.
	DBGMCU_CR_DBG_STANDBY_Msk = 0x4
	// Bit DBG_STANDBY.
	DBGMCU_CR_DBG_STANDBY = 0x4
	// Position of TRACE_IOEN field.
	DBGMCU_CR_TRACE_IOEN_Pos = 0x4
	// Bit mask of TRACE_IOEN field.
	DBGMCU_CR_TRACE_IOEN_Msk = 0x10
	// Bit TRACE_IOEN.
	DBGMCU_CR_TRACE_IOEN = 0x10
	// Position of TRACE_EN field.
	DBGMCU_CR_TRACE_EN_Pos = 0x5
	// Bit mask of TRACE_EN field.
	DBGMCU_CR_TRACE_EN_Msk = 0x20
	// Bit TRACE_EN.
	DBGMCU_CR_TRACE_EN = 0x20
	// Position of TRACE_MODE field.
	DBGMCU_CR_TRACE_MODE_Pos = 0x6
	// Bit mask of TRACE_MODE field.
	DBGMCU_CR_TRACE_MODE_Msk = 0xc0

	// APB1LFZR: Debug MCU APB1L peripheral freeze register
	// Position of DBG_TIM2_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos = 0x0
	// Bit mask of DBG_TIM2_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk = 0x1
	// Bit DBG_TIM2_STOP.
	DBGMCU_APB1LFZR_DBG_TIM2_STOP = 0x1
	// Position of DBG_TIM3_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos = 0x1
	// Bit mask of DBG_TIM3_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk = 0x2
	// Bit DBG_TIM3_STOP.
	DBGMCU_APB1LFZR_DBG_TIM3_STOP = 0x2
	// Position of DBG_TIM4_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos = 0x2
	// Bit mask of DBG_TIM4_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk = 0x4
	// Bit DBG_TIM4_STOP.
	DBGMCU_APB1LFZR_DBG_TIM4_STOP = 0x4
	// Position of DBG_TIM5_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos = 0x3
	// Bit mask of DBG_TIM5_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk = 0x8
	// Bit DBG_TIM5_STOP.
	DBGMCU_APB1LFZR_DBG_TIM5_STOP = 0x8
	// Position of DBG_TIM6_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos = 0x4
	// Bit mask of DBG_TIM6_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk = 0x10
	// Bit DBG_TIM6_STOP.
	DBGMCU_APB1LFZR_DBG_TIM6_STOP = 0x10
	// Position of DBG_TIM7_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos = 0x5
	// Bit mask of DBG_TIM7_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk = 0x20
	// Bit DBG_TIM7_STOP.
	DBGMCU_APB1LFZR_DBG_TIM7_STOP = 0x20
	// Position of DBG_WWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos = 0xb
	// Bit mask of DBG_WWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk = 0x800
	// Bit DBG_WWDG_STOP.
	DBGMCU_APB1LFZR_DBG_WWDG_STOP = 0x800
	// Position of DBG_IWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos = 0xc
	// Bit mask of DBG_IWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk = 0x1000
	// Bit DBG_IWDG_STOP.
	DBGMCU_APB1LFZR_DBG_IWDG_STOP = 0x1000
	// Position of DBG_I2C1_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos = 0x15
	// Bit mask of DBG_I2C1_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk = 0x200000
	// Bit DBG_I2C1_STOP.
	DBGMCU_APB1LFZR_DBG_I2C1_STOP = 0x200000
	// Position of DBG_I2C2_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos = 0x16
	// Bit mask of DBG_I2C2_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk = 0x400000
	// Bit DBG_I2C2_STOP.
	DBGMCU_APB1LFZR_DBG_I2C2_STOP = 0x400000

	// APB1HFZR: Debug MCU APB1H peripheral freeze register
	// Position of DBG_I2C4_STOP field.
	DBGMCU_APB1HFZR_DBG_I2C4_STOP_Pos = 0x1
	// Bit mask of DBG_I2C4_STOP field.
	DBGMCU_APB1HFZR_DBG_I2C4_STOP_Msk = 0x2
	// Bit DBG_I2C4_STOP.
	DBGMCU_APB1HFZR_DBG_I2C4_STOP = 0x2
	// Position of DBG_LPTIM2_STOP field.
	DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos = 0x5
	// Bit mask of DBG_LPTIM2_STOP field.
	DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk = 0x20
	// Bit DBG_LPTIM2_STOP.
	DBGMCU_APB1HFZR_DBG_LPTIM2_STOP = 0x20

	// APB2FZR: Debug MCU APB2 peripheral freeze register
	// Position of DBG_TIM1_STOP field.
	DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos = 0xb
	// Bit mask of DBG_TIM1_STOP field.
	DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk = 0x800
	// Bit DBG_TIM1_STOP.
	DBGMCU_APB2FZR_DBG_TIM1_STOP = 0x800
	// Position of DBG_TIM8_STOP field.
	DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos = 0xd
	// Bit mask of DBG_TIM8_STOP field.
	DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk = 0x2000
	// Bit DBG_TIM8_STOP.
	DBGMCU_APB2FZR_DBG_TIM8_STOP = 0x2000
	// Position of DBG_TIM15_STOP field.
	DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos = 0x10
	// Bit mask of DBG_TIM15_STOP field.
	DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk = 0x10000
	// Bit DBG_TIM15_STOP.
	DBGMCU_APB2FZR_DBG_TIM15_STOP = 0x10000
	// Position of DBG_TIM16_STOP field.
	DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos = 0x11
	// Bit mask of DBG_TIM16_STOP field.
	DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk = 0x20000
	// Bit DBG_TIM16_STOP.
	DBGMCU_APB2FZR_DBG_TIM16_STOP = 0x20000
	// Position of DBG_TIM17_STOP field.
	DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos = 0x12
	// Bit mask of DBG_TIM17_STOP field.
	DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk = 0x40000
	// Bit DBG_TIM17_STOP.
	DBGMCU_APB2FZR_DBG_TIM17_STOP = 0x40000

	// APB3FZR: Debug MCU APB3 peripheral freeze register
	// Position of DBG_I2C3_STOP field.
	DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos = 0xa
	// Bit mask of DBG_I2C3_STOP field.
	DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk = 0x400
	// Bit DBG_I2C3_STOP.
	DBGMCU_APB3FZR_DBG_I2C3_STOP = 0x400
	// Position of DBG_LPTIM1_STOP field.
	DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos = 0x11
	// Bit mask of DBG_LPTIM1_STOP field.
	DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk = 0x20000
	// Bit DBG_LPTIM1_STOP.
	DBGMCU_APB3FZR_DBG_LPTIM1_STOP = 0x20000
	// Position of DBG_LPTIM3_STOP field.
	DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos = 0x12
	// Bit mask of DBG_LPTIM3_STOP field.
	DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk = 0x40000
	// Bit DBG_LPTIM3_STOP.
	DBGMCU_APB3FZR_DBG_LPTIM3_STOP = 0x40000
	// Position of DBG_LPTIM4_STOP field.
	DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos = 0x13
	// Bit mask of DBG_LPTIM4_STOP field.
	DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk = 0x80000
	// Bit DBG_LPTIM4_STOP.
	DBGMCU_APB3FZR_DBG_LPTIM4_STOP = 0x80000
	// Position of DBG_RTC_STOP field.
	DBGMCU_APB3FZR_DBG_RTC_STOP_Pos = 0x1e
	// Bit mask of DBG_RTC_STOP field.
	DBGMCU_APB3FZR_DBG_RTC_STOP_Msk = 0x40000000
	// Bit DBG_RTC_STOP.
	DBGMCU_APB3FZR_DBG_RTC_STOP = 0x40000000

	// AHB1FZR: Debug MCU AHB1 peripheral freeze register
	// Position of DBG_GPDMA0_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Pos = 0x0
	// Bit mask of DBG_GPDMA0_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Msk = 0x1
	// Bit DBG_GPDMA0_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA0_STOP = 0x1
	// Position of DBG_GPDMA1_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Pos = 0x1
	// Bit mask of DBG_GPDMA1_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Msk = 0x2
	// Bit DBG_GPDMA1_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA1_STOP = 0x2
	// Position of DBG_GPDMA2_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Pos = 0x2
	// Bit mask of DBG_GPDMA2_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Msk = 0x4
	// Bit DBG_GPDMA2_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA2_STOP = 0x4
	// Position of DBG_GPDMA3_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Pos = 0x3
	// Bit mask of DBG_GPDMA3_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Msk = 0x8
	// Bit DBG_GPDMA3_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA3_STOP = 0x8
	// Position of DBG_GPDMA4_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Pos = 0x4
	// Bit mask of DBG_GPDMA4_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Msk = 0x10
	// Bit DBG_GPDMA4_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA4_STOP = 0x10
	// Position of DBG_GPDMA5_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Pos = 0x5
	// Bit mask of DBG_GPDMA5_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Msk = 0x20
	// Bit DBG_GPDMA5_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA5_STOP = 0x20
	// Position of DBG_GPDMA6_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Pos = 0x6
	// Bit mask of DBG_GPDMA6_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Msk = 0x40
	// Bit DBG_GPDMA6_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA6_STOP = 0x40
	// Position of DBG_GPDMA7_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Pos = 0x7
	// Bit mask of DBG_GPDMA7_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Msk = 0x80
	// Bit DBG_GPDMA7_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA7_STOP = 0x80
	// Position of DBG_GPDMA8_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Pos = 0x8
	// Bit mask of DBG_GPDMA8_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Msk = 0x100
	// Bit DBG_GPDMA8_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA8_STOP = 0x100
	// Position of DBG_GPDMA9_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Pos = 0x9
	// Bit mask of DBG_GPDMA9_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Msk = 0x200
	// Bit DBG_GPDMA9_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA9_STOP = 0x200
	// Position of DBG_GPDMA10_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Pos = 0xa
	// Bit mask of DBG_GPDMA10_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Msk = 0x400
	// Bit DBG_GPDMA10_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA10_STOP = 0x400
	// Position of DBG_GPDMA11_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Pos = 0xb
	// Bit mask of DBG_GPDMA11_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Msk = 0x800
	// Bit DBG_GPDMA11_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA11_STOP = 0x800
	// Position of DBG_GPDMA12_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Pos = 0xc
	// Bit mask of DBG_GPDMA12_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Msk = 0x1000
	// Bit DBG_GPDMA12_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA12_STOP = 0x1000
	// Position of DBG_GPDMA13_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Pos = 0xd
	// Bit mask of DBG_GPDMA13_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Msk = 0x2000
	// Bit DBG_GPDMA13_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA13_STOP = 0x2000
	// Position of DBG_GPDMA14_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Pos = 0xe
	// Bit mask of DBG_GPDMA14_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Msk = 0x4000
	// Bit DBG_GPDMA14_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA14_STOP = 0x4000
	// Position of DBG_GPDMA15_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Pos = 0xf
	// Bit mask of DBG_GPDMA15_STOP field.
	DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Msk = 0x8000
	// Bit DBG_GPDMA15_STOP.
	DBGMCU_AHB1FZR_DBG_GPDMA15_STOP = 0x8000

	// AHB3FZR: Debug MCU AHB3 peripheral freeze register
	// Position of DBG_LPDMA0_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Pos = 0x0
	// Bit mask of DBG_LPDMA0_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Msk = 0x1
	// Bit DBG_LPDMA0_STOP.
	DBGMCU_AHB3FZR_DBG_LPDMA0_STOP = 0x1
	// Position of DBG_LPDMA1_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Pos = 0x1
	// Bit mask of DBG_LPDMA1_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Msk = 0x2
	// Bit DBG_LPDMA1_STOP.
	DBGMCU_AHB3FZR_DBG_LPDMA1_STOP = 0x2
	// Position of DBG_LPDMA2_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Pos = 0x2
	// Bit mask of DBG_LPDMA2_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Msk = 0x4
	// Bit DBG_LPDMA2_STOP.
	DBGMCU_AHB3FZR_DBG_LPDMA2_STOP = 0x4
	// Position of DBG_LPDMA3_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Pos = 0x3
	// Bit mask of DBG_LPDMA3_STOP field.
	DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Msk = 0x8
	// Bit DBG_LPDMA3_STOP.
	DBGMCU_AHB3FZR_DBG_LPDMA3_STOP = 0x8

	// SR: DBGMCU status register
	// Position of AP_PRESENT field.
	DBGMCU_SR_AP_PRESENT_Pos = 0x0
	// Bit mask of AP_PRESENT field.
	DBGMCU_SR_AP_PRESENT_Msk = 0xff
	// Position of AP_LOCKED field.
	DBGMCU_SR_AP_LOCKED_Pos = 0x8
	// Bit mask of AP_LOCKED field.
	DBGMCU_SR_AP_LOCKED_Msk = 0xff00

	// DBGMCU_DBG_AUTH_HOST: DBGMCU debug host authentication register
	// Position of AUTH_KEY field.
	DBGMCU_DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Pos = 0x0
	// Bit mask of AUTH_KEY field.
	DBGMCU_DBGMCU_DBG_AUTH_HOST_AUTH_KEY_Msk = 0xffffffff

	// DBG_AUTH_DEVICE: DBGMCU debug device authentication register
	// Position of AUTH_ID field.
	DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Pos = 0x0
	// Bit mask of AUTH_ID field.
	DBGMCU_DBG_AUTH_DEVICE_AUTH_ID_Msk = 0xffff

	// PIDR4: Debug MCU CoreSight peripheral identity register 4
	// Position of JEP106CON field.
	DBGMCU_PIDR4_JEP106CON_Pos = 0x0
	// Bit mask of JEP106CON field.
	DBGMCU_PIDR4_JEP106CON_Msk = 0xf
	// Position of KCOUNT_4 field.
	DBGMCU_PIDR4_KCOUNT_4_Pos = 0x4
	// Bit mask of KCOUNT_4 field.
	DBGMCU_PIDR4_KCOUNT_4_Msk = 0xf0

	// PIDR0: Debug MCU CoreSight peripheral identity register 0
	// Position of PARTNUM field.
	DBGMCU_PIDR0_PARTNUM_Pos = 0x0
	// Bit mask of PARTNUM field.
	DBGMCU_PIDR0_PARTNUM_Msk = 0xff

	// PIDR1: Debug MCU CoreSight peripheral identity register 1
	// Position of PARTNUM field.
	DBGMCU_PIDR1_PARTNUM_Pos = 0x0
	// Bit mask of PARTNUM field.
	DBGMCU_PIDR1_PARTNUM_Msk = 0xf
	// Position of JEP106ID field.
	DBGMCU_PIDR1_JEP106ID_Pos = 0x4
	// Bit mask of JEP106ID field.
	DBGMCU_PIDR1_JEP106ID_Msk = 0xf0

	// PIDR2: Debug MCU CoreSight peripheral identity register 2
	// Position of JEP106ID field.
	DBGMCU_PIDR2_JEP106ID_Pos = 0x0
	// Bit mask of JEP106ID field.
	DBGMCU_PIDR2_JEP106ID_Msk = 0x7
	// Position of JEDEC field.
	DBGMCU_PIDR2_JEDEC_Pos = 0x3
	// Bit mask of JEDEC field.
	DBGMCU_PIDR2_JEDEC_Msk = 0x8
	// Bit JEDEC.
	DBGMCU_PIDR2_JEDEC = 0x8
	// Position of REVISION field.
	DBGMCU_PIDR2_REVISION_Pos = 0x4
	// Bit mask of REVISION field.
	DBGMCU_PIDR2_REVISION_Msk = 0xf0

	// PIDR3: Debug MCU CoreSight peripheral identity register 3
	// Position of CMOD field.
	DBGMCU_PIDR3_CMOD_Pos = 0x0
	// Bit mask of CMOD field.
	DBGMCU_PIDR3_CMOD_Msk = 0xf
	// Position of REVAND field.
	DBGMCU_PIDR3_REVAND_Pos = 0x4
	// Bit mask of REVAND field.
	DBGMCU_PIDR3_REVAND_Msk = 0xf0

	// CIDR0: Debug MCU CoreSight component identity register 0
	// Position of PREAMBLE field.
	DBGMCU_CIDR0_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	DBGMCU_CIDR0_PREAMBLE_Msk = 0xff

	// CIDR1: Debug MCU CoreSight component identity register 1
	// Position of PREAMBLE field.
	DBGMCU_CIDR1_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	DBGMCU_CIDR1_PREAMBLE_Msk = 0xf
	// Position of CLASS field.
	DBGMCU_CIDR1_CLASS_Pos = 0x4
	// Bit mask of CLASS field.
	DBGMCU_CIDR1_CLASS_Msk = 0xf0

	// CIDR2: Debug MCU CoreSight component identity register 2
	// Position of PREAMBLE field.
	DBGMCU_CIDR2_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	DBGMCU_CIDR2_PREAMBLE_Msk = 0xff

	// CIDR3: Debug MCU CoreSight component identity register 3
	// Position of PREAMBLE field.
	DBGMCU_CIDR3_PREAMBLE_Pos = 0x0
	// Bit mask of PREAMBLE field.
	DBGMCU_CIDR3_PREAMBLE_Msk = 0xff
)

// Constants for DCACHE1: DCACHE1
const (
	// CR: DCACHE control register
	// Position of EN field.
	DCACHE_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DCACHE_CR_EN_Msk = 0x1
	// Bit EN.
	DCACHE_CR_EN = 0x1
	// Position of CACHEINV field.
	DCACHE_CR_CACHEINV_Pos = 0x1
	// Bit mask of CACHEINV field.
	DCACHE_CR_CACHEINV_Msk = 0x2
	// Bit CACHEINV.
	DCACHE_CR_CACHEINV = 0x2
	// Position of CACHECMD field.
	DCACHE_CR_CACHECMD_Pos = 0x8
	// Bit mask of CACHECMD field.
	DCACHE_CR_CACHECMD_Msk = 0x700
	// Position of STARTCMD field.
	DCACHE_CR_STARTCMD_Pos = 0xb
	// Bit mask of STARTCMD field.
	DCACHE_CR_STARTCMD_Msk = 0x800
	// Bit STARTCMD.
	DCACHE_CR_STARTCMD = 0x800
	// Position of RHITMEN field.
	DCACHE_CR_RHITMEN_Pos = 0x10
	// Bit mask of RHITMEN field.
	DCACHE_CR_RHITMEN_Msk = 0x10000
	// Bit RHITMEN.
	DCACHE_CR_RHITMEN = 0x10000
	// Position of RMISSMEN field.
	DCACHE_CR_RMISSMEN_Pos = 0x11
	// Bit mask of RMISSMEN field.
	DCACHE_CR_RMISSMEN_Msk = 0x20000
	// Bit RMISSMEN.
	DCACHE_CR_RMISSMEN = 0x20000
	// Position of RHITMRST field.
	DCACHE_CR_RHITMRST_Pos = 0x12
	// Bit mask of RHITMRST field.
	DCACHE_CR_RHITMRST_Msk = 0x40000
	// Bit RHITMRST.
	DCACHE_CR_RHITMRST = 0x40000
	// Position of RMISSMRST field.
	DCACHE_CR_RMISSMRST_Pos = 0x13
	// Bit mask of RMISSMRST field.
	DCACHE_CR_RMISSMRST_Msk = 0x80000
	// Bit RMISSMRST.
	DCACHE_CR_RMISSMRST = 0x80000
	// Position of WHITMEN field.
	DCACHE_CR_WHITMEN_Pos = 0x14
	// Bit mask of WHITMEN field.
	DCACHE_CR_WHITMEN_Msk = 0x100000
	// Bit WHITMEN.
	DCACHE_CR_WHITMEN = 0x100000
	// Position of WMISSMEN field.
	DCACHE_CR_WMISSMEN_Pos = 0x15
	// Bit mask of WMISSMEN field.
	DCACHE_CR_WMISSMEN_Msk = 0x200000
	// Bit WMISSMEN.
	DCACHE_CR_WMISSMEN = 0x200000
	// Position of WHITMRST field.
	DCACHE_CR_WHITMRST_Pos = 0x16
	// Bit mask of WHITMRST field.
	DCACHE_CR_WHITMRST_Msk = 0x400000
	// Bit WHITMRST.
	DCACHE_CR_WHITMRST = 0x400000
	// Position of WMISSMRST field.
	DCACHE_CR_WMISSMRST_Pos = 0x17
	// Bit mask of WMISSMRST field.
	DCACHE_CR_WMISSMRST_Msk = 0x800000
	// Bit WMISSMRST.
	DCACHE_CR_WMISSMRST = 0x800000
	// Position of HBURST field.
	DCACHE_CR_HBURST_Pos = 0x1f
	// Bit mask of HBURST field.
	DCACHE_CR_HBURST_Msk = 0x80000000
	// Bit HBURST.
	DCACHE_CR_HBURST = 0x80000000

	// SR: DCACHE status register
	// Position of BUSYF field.
	DCACHE_SR_BUSYF_Pos = 0x0
	// Bit mask of BUSYF field.
	DCACHE_SR_BUSYF_Msk = 0x1
	// Bit BUSYF.
	DCACHE_SR_BUSYF = 0x1
	// Position of BSYENDF field.
	DCACHE_SR_BSYENDF_Pos = 0x1
	// Bit mask of BSYENDF field.
	DCACHE_SR_BSYENDF_Msk = 0x2
	// Bit BSYENDF.
	DCACHE_SR_BSYENDF = 0x2
	// Position of ERRF field.
	DCACHE_SR_ERRF_Pos = 0x2
	// Bit mask of ERRF field.
	DCACHE_SR_ERRF_Msk = 0x4
	// Bit ERRF.
	DCACHE_SR_ERRF = 0x4
	// Position of BUSYCMDF field.
	DCACHE_SR_BUSYCMDF_Pos = 0x3
	// Bit mask of BUSYCMDF field.
	DCACHE_SR_BUSYCMDF_Msk = 0x8
	// Bit BUSYCMDF.
	DCACHE_SR_BUSYCMDF = 0x8
	// Position of CMDENDF field.
	DCACHE_SR_CMDENDF_Pos = 0x4
	// Bit mask of CMDENDF field.
	DCACHE_SR_CMDENDF_Msk = 0x10
	// Bit CMDENDF.
	DCACHE_SR_CMDENDF = 0x10

	// IER: DCACHE interrupt enable register
	// Position of BSYENDIE field.
	DCACHE_IER_BSYENDIE_Pos = 0x1
	// Bit mask of BSYENDIE field.
	DCACHE_IER_BSYENDIE_Msk = 0x2
	// Bit BSYENDIE.
	DCACHE_IER_BSYENDIE = 0x2
	// Position of ERRIE field.
	DCACHE_IER_ERRIE_Pos = 0x2
	// Bit mask of ERRIE field.
	DCACHE_IER_ERRIE_Msk = 0x4
	// Bit ERRIE.
	DCACHE_IER_ERRIE = 0x4
	// Position of CMDENDIE field.
	DCACHE_IER_CMDENDIE_Pos = 0x4
	// Bit mask of CMDENDIE field.
	DCACHE_IER_CMDENDIE_Msk = 0x10
	// Bit CMDENDIE.
	DCACHE_IER_CMDENDIE = 0x10

	// FCR: DCACHE flag clear register
	// Position of CBSYENDF field.
	DCACHE_FCR_CBSYENDF_Pos = 0x1
	// Bit mask of CBSYENDF field.
	DCACHE_FCR_CBSYENDF_Msk = 0x2
	// Bit CBSYENDF.
	DCACHE_FCR_CBSYENDF = 0x2
	// Position of CERRF field.
	DCACHE_FCR_CERRF_Pos = 0x2
	// Bit mask of CERRF field.
	DCACHE_FCR_CERRF_Msk = 0x4
	// Bit CERRF.
	DCACHE_FCR_CERRF = 0x4
	// Position of CCMDENDF field.
	DCACHE_FCR_CCMDENDF_Pos = 0x4
	// Bit mask of CCMDENDF field.
	DCACHE_FCR_CCMDENDF_Msk = 0x10
	// Bit CCMDENDF.
	DCACHE_FCR_CCMDENDF = 0x10

	// RHMONR: DCACHE read-hit monitor register
	// Position of RHITMON field.
	DCACHE_RHMONR_RHITMON_Pos = 0x0
	// Bit mask of RHITMON field.
	DCACHE_RHMONR_RHITMON_Msk = 0xffffffff

	// RMMONR: DCACHE read-miss monitor register
	// Position of MRISSMON field.
	DCACHE_RMMONR_MRISSMON_Pos = 0x0
	// Bit mask of MRISSMON field.
	DCACHE_RMMONR_MRISSMON_Msk = 0xffff

	// WHMONR: write-hit monitor register
	// Position of WHITMON field.
	DCACHE_WHMONR_WHITMON_Pos = 0x0
	// Bit mask of WHITMON field.
	DCACHE_WHMONR_WHITMON_Msk = 0xffffffff

	// WMMONR: write-miss monitor register
	// Position of WMISSMON field.
	DCACHE_WMMONR_WMISSMON_Pos = 0x0
	// Bit mask of WMISSMON field.
	DCACHE_WMMONR_WMISSMON_Msk = 0xffff

	// CMDRSADDRR: command range start address register
	// Position of CMDSTARTADDR field.
	DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos = 0x4
	// Bit mask of CMDSTARTADDR field.
	DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk = 0xfffffff0

	// CMDREADDRR: command range start address register
	// Position of CMDENDADDR field.
	DCACHE_CMDREADDRR_CMDENDADDR_Pos = 0x4
	// Bit mask of CMDENDADDR field.
	DCACHE_CMDREADDRR_CMDENDADDR_Msk = 0xfffffff0
)

// Constants for DCMI: Digital camera interface
const (
	// CR: control register
	// Position of OELS field.
	DCMI_CR_OELS_Pos = 0x14
	// Bit mask of OELS field.
	DCMI_CR_OELS_Msk = 0x100000
	// Bit OELS.
	DCMI_CR_OELS = 0x100000
	// Interface captures first line after the frame start, second one being dropped
	DCMI_CR_OELS_Odd = 0x0
	// Interface captures second line from the frame start, first one being dropped
	DCMI_CR_OELS_Even = 0x1
	// Position of LSM field.
	DCMI_CR_LSM_Pos = 0x13
	// Bit mask of LSM field.
	DCMI_CR_LSM_Msk = 0x80000
	// Bit LSM.
	DCMI_CR_LSM = 0x80000
	// Interface captures all received lines
	DCMI_CR_LSM_All = 0x0
	// Interface captures one line out of two
	DCMI_CR_LSM_Half = 0x1
	// Position of OEBS field.
	DCMI_CR_OEBS_Pos = 0x12
	// Bit mask of OEBS field.
	DCMI_CR_OEBS_Msk = 0x40000
	// Bit OEBS.
	DCMI_CR_OEBS = 0x40000
	// Interface captures first data (byte or double byte) from the frame/line start, second one being dropped
	DCMI_CR_OEBS_Odd = 0x0
	// Interface captures second data (byte or double byte) from the frame/line start, first one being dropped
	DCMI_CR_OEBS_Even = 0x1
	// Position of BSM field.
	DCMI_CR_BSM_Pos = 0x10
	// Bit mask of BSM field.
	DCMI_CR_BSM_Msk = 0x30000
	// Interface captures all received data
	DCMI_CR_BSM_All = 0x0
	// Interface captures every other byte from the received data
	DCMI_CR_BSM_EveryOther = 0x1
	// Interface captures one byte out of four
	DCMI_CR_BSM_Fourth = 0x2
	// Interface captures two bytes out of four
	DCMI_CR_BSM_TwoOfFour = 0x3
	// Position of ENABLE field.
	DCMI_CR_ENABLE_Pos = 0xe
	// Bit mask of ENABLE field.
	DCMI_CR_ENABLE_Msk = 0x4000
	// Bit ENABLE.
	DCMI_CR_ENABLE = 0x4000
	// DCMI disabled
	DCMI_CR_ENABLE_Disabled = 0x0
	// DCMI enabled
	DCMI_CR_ENABLE_Enabled = 0x1
	// Position of EDM field.
	DCMI_CR_EDM_Pos = 0xa
	// Bit mask of EDM field.
	DCMI_CR_EDM_Msk = 0xc00
	// Interface captures 8-bit data on every pixel clock
	DCMI_CR_EDM_BitWidth8 = 0x0
	// Interface captures 10-bit data on every pixel clock
	DCMI_CR_EDM_BitWidth10 = 0x1
	// Interface captures 12-bit data on every pixel clock
	DCMI_CR_EDM_BitWidth12 = 0x2
	// Interface captures 14-bit data on every pixel clock
	DCMI_CR_EDM_BitWidth14 = 0x3
	// Position of FCRC field.
	DCMI_CR_FCRC_Pos = 0x8
	// Bit mask of FCRC field.
	DCMI_CR_FCRC_Msk = 0x300
	// All frames are captured
	DCMI_CR_FCRC_All = 0x0
	// Every alternate frame captured (50% bandwidth reduction)
	DCMI_CR_FCRC_Alternate = 0x1
	// One frame out of four captured (75% bandwidth reduction)
	DCMI_CR_FCRC_OneOfFour = 0x2
	// Position of VSPOL field.
	DCMI_CR_VSPOL_Pos = 0x7
	// Bit mask of VSPOL field.
	DCMI_CR_VSPOL_Msk = 0x80
	// Bit VSPOL.
	DCMI_CR_VSPOL = 0x80
	// DCMI_VSYNC active low
	DCMI_CR_VSPOL_ActiveLow = 0x0
	// DCMI_VSYNC active high
	DCMI_CR_VSPOL_ActiveHigh = 0x1
	// Position of HSPOL field.
	DCMI_CR_HSPOL_Pos = 0x6
	// Bit mask of HSPOL field.
	DCMI_CR_HSPOL_Msk = 0x40
	// Bit HSPOL.
	DCMI_CR_HSPOL = 0x40
	// DCMI_HSYNC active low
	DCMI_CR_HSPOL_ActiveLow = 0x0
	// DCMI_HSYNC active high
	DCMI_CR_HSPOL_ActiveHigh = 0x1
	// Position of PCKPOL field.
	DCMI_CR_PCKPOL_Pos = 0x5
	// Bit mask of PCKPOL field.
	DCMI_CR_PCKPOL_Msk = 0x20
	// Bit PCKPOL.
	DCMI_CR_PCKPOL = 0x20
	// Falling edge active
	DCMI_CR_PCKPOL_FallingEdge = 0x0
	// Rising edge active
	DCMI_CR_PCKPOL_RisingEdge = 0x1
	// Position of ESS field.
	DCMI_CR_ESS_Pos = 0x4
	// Bit mask of ESS field.
	DCMI_CR_ESS_Msk = 0x10
	// Bit ESS.
	DCMI_CR_ESS = 0x10
	// Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals
	DCMI_CR_ESS_Hardware = 0x0
	// Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow
	DCMI_CR_ESS_Embedded = 0x1
	// Position of JPEG field.
	DCMI_CR_JPEG_Pos = 0x3
	// Bit mask of JPEG field.
	DCMI_CR_JPEG_Msk = 0x8
	// Bit JPEG.
	DCMI_CR_JPEG = 0x8
	// Uncompressed video format
	DCMI_CR_JPEG_Uncompressed = 0x0
	// This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode
	DCMI_CR_JPEG_JPEG = 0x1
	// Position of CROP field.
	DCMI_CR_CROP_Pos = 0x2
	// Bit mask of CROP field.
	DCMI_CR_CROP_Msk = 0x4
	// Bit CROP.
	DCMI_CR_CROP = 0x4
	// The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four
	DCMI_CR_CROP_Full = 0x0
	// Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured
	DCMI_CR_CROP_Cropped = 0x1
	// Position of CM field.
	DCMI_CR_CM_Pos = 0x1
	// Bit mask of CM field.
	DCMI_CR_CM_Msk = 0x2
	// Bit CM.
	DCMI_CR_CM = 0x2
	// Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA
	DCMI_CR_CM_Continuous = 0x0
	// Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset
	DCMI_CR_CM_Snapshot = 0x1
	// Position of CAPTURE field.
	DCMI_CR_CAPTURE_Pos = 0x0
	// Bit mask of CAPTURE field.
	DCMI_CR_CAPTURE_Msk = 0x1
	// Bit CAPTURE.
	DCMI_CR_CAPTURE = 0x1
	// Capture disabled
	DCMI_CR_CAPTURE_Disabled = 0x0
	// Capture enabled
	DCMI_CR_CAPTURE_Enabled = 0x1

	// SR: status register
	// Position of FNE field.
	DCMI_SR_FNE_Pos = 0x2
	// Bit mask of FNE field.
	DCMI_SR_FNE_Msk = 0x4
	// Bit FNE.
	DCMI_SR_FNE = 0x4
	// FIFO contains valid data
	DCMI_SR_FNE_NotEmpty = 0x0
	// FIFO empty
	DCMI_SR_FNE_Empty = 0x1
	// Position of VSYNC field.
	DCMI_SR_VSYNC_Pos = 0x1
	// Bit mask of VSYNC field.
	DCMI_SR_VSYNC_Msk = 0x2
	// Bit VSYNC.
	DCMI_SR_VSYNC = 0x2
	// Active frame
	DCMI_SR_VSYNC_ActiveFrame = 0x0
	// Synchronization between frames
	DCMI_SR_VSYNC_BetweenFrames = 0x1
	// Position of HSYNC field.
	DCMI_SR_HSYNC_Pos = 0x0
	// Bit mask of HSYNC field.
	DCMI_SR_HSYNC_Msk = 0x1
	// Bit HSYNC.
	DCMI_SR_HSYNC = 0x1
	// Active line
	DCMI_SR_HSYNC_ActiveLine = 0x0
	// Synchronization between lines
	DCMI_SR_HSYNC_BetweenLines = 0x1

	// RIS: raw interrupt status register
	// Position of LINE_RIS field.
	DCMI_RIS_LINE_RIS_Pos = 0x4
	// Bit mask of LINE_RIS field.
	DCMI_RIS_LINE_RIS_Msk = 0x10
	// Bit LINE_RIS.
	DCMI_RIS_LINE_RIS = 0x10
	// Interrupt cleared
	DCMI_RIS_LINE_RIS_Cleared = 0x0
	// Interrupt set
	DCMI_RIS_LINE_RIS_Set = 0x1
	// Position of VSYNC_RIS field.
	DCMI_RIS_VSYNC_RIS_Pos = 0x3
	// Bit mask of VSYNC_RIS field.
	DCMI_RIS_VSYNC_RIS_Msk = 0x8
	// Bit VSYNC_RIS.
	DCMI_RIS_VSYNC_RIS = 0x8
	// Interrupt cleared
	DCMI_RIS_VSYNC_RIS_Cleared = 0x0
	// Interrupt set
	DCMI_RIS_VSYNC_RIS_Set = 0x1
	// Position of ERR_RIS field.
	DCMI_RIS_ERR_RIS_Pos = 0x2
	// Bit mask of ERR_RIS field.
	DCMI_RIS_ERR_RIS_Msk = 0x4
	// Bit ERR_RIS.
	DCMI_RIS_ERR_RIS = 0x4
	// No synchronization error detected
	DCMI_RIS_ERR_RIS_NoError = 0x0
	// Embedded synchronization characters are not received in the correct order
	DCMI_RIS_ERR_RIS_SynchronizationError = 0x1
	// Position of OVR_RIS field.
	DCMI_RIS_OVR_RIS_Pos = 0x1
	// Bit mask of OVR_RIS field.
	DCMI_RIS_OVR_RIS_Msk = 0x2
	// Bit OVR_RIS.
	DCMI_RIS_OVR_RIS = 0x2
	// No data buffer overrun occurred
	DCMI_RIS_OVR_RIS_NoOverrun = 0x0
	// A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register
	DCMI_RIS_OVR_RIS_OverrunOccured = 0x1
	// Position of FRAME_RIS field.
	DCMI_RIS_FRAME_RIS_Pos = 0x0
	// Bit mask of FRAME_RIS field.
	DCMI_RIS_FRAME_RIS_Msk = 0x1
	// Bit FRAME_RIS.
	DCMI_RIS_FRAME_RIS = 0x1
	// No new capture
	DCMI_RIS_FRAME_RIS_NoNewCapture = 0x0
	// A frame has been captured
	DCMI_RIS_FRAME_RIS_FrameCaptured = 0x1

	// IER: interrupt enable register
	// Position of LINE_IE field.
	DCMI_IER_LINE_IE_Pos = 0x4
	// Bit mask of LINE_IE field.
	DCMI_IER_LINE_IE_Msk = 0x10
	// Bit LINE_IE.
	DCMI_IER_LINE_IE = 0x10
	// No interrupt generation when the line is received
	DCMI_IER_LINE_IE_Disabled = 0x0
	// An Interrupt is generated when a line has been completely received
	DCMI_IER_LINE_IE_Enabled = 0x1
	// Position of VSYNC_IE field.
	DCMI_IER_VSYNC_IE_Pos = 0x3
	// Bit mask of VSYNC_IE field.
	DCMI_IER_VSYNC_IE_Msk = 0x8
	// Bit VSYNC_IE.
	DCMI_IER_VSYNC_IE = 0x8
	// No interrupt generation
	DCMI_IER_VSYNC_IE_Disabled = 0x0
	// An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state
	DCMI_IER_VSYNC_IE_Enabled = 0x1
	// Position of ERR_IE field.
	DCMI_IER_ERR_IE_Pos = 0x2
	// Bit mask of ERR_IE field.
	DCMI_IER_ERR_IE_Msk = 0x4
	// Bit ERR_IE.
	DCMI_IER_ERR_IE = 0x4
	// No interrupt generation
	DCMI_IER_ERR_IE_Disabled = 0x0
	// An interrupt is generated if the embedded synchronization codes are not received in the correct order
	DCMI_IER_ERR_IE_Enabled = 0x1
	// Position of OVR_IE field.
	DCMI_IER_OVR_IE_Pos = 0x1
	// Bit mask of OVR_IE field.
	DCMI_IER_OVR_IE_Msk = 0x2
	// Bit OVR_IE.
	DCMI_IER_OVR_IE = 0x2
	// No interrupt generation
	DCMI_IER_OVR_IE_Disabled = 0x0
	// An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received
	DCMI_IER_OVR_IE_Enabled = 0x1
	// Position of FRAME_IE field.
	DCMI_IER_FRAME_IE_Pos = 0x0
	// Bit mask of FRAME_IE field.
	DCMI_IER_FRAME_IE_Msk = 0x1
	// Bit FRAME_IE.
	DCMI_IER_FRAME_IE = 0x1
	// No interrupt generation
	DCMI_IER_FRAME_IE_Disabled = 0x0
	// An interrupt is generated at the end of each received frame/crop window (in crop mode)
	DCMI_IER_FRAME_IE_Enabled = 0x1

	// MIS: masked interrupt status register
	// Position of LINE_MIS field.
	DCMI_MIS_LINE_MIS_Pos = 0x4
	// Bit mask of LINE_MIS field.
	DCMI_MIS_LINE_MIS_Msk = 0x10
	// Bit LINE_MIS.
	DCMI_MIS_LINE_MIS = 0x10
	// No interrupt generation when the line is received
	DCMI_MIS_LINE_MIS_Disabled = 0x0
	// An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER
	DCMI_MIS_LINE_MIS_Enabled = 0x1
	// Position of VSYNC_MIS field.
	DCMI_MIS_VSYNC_MIS_Pos = 0x3
	// Bit mask of VSYNC_MIS field.
	DCMI_MIS_VSYNC_MIS_Msk = 0x8
	// Bit VSYNC_MIS.
	DCMI_MIS_VSYNC_MIS = 0x8
	// No interrupt is generated on DCMI_VSYNC transitions
	DCMI_MIS_VSYNC_MIS_Disabled = 0x0
	// An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER
	DCMI_MIS_VSYNC_MIS_Enabled = 0x1
	// Position of ERR_MIS field.
	DCMI_MIS_ERR_MIS_Pos = 0x2
	// Bit mask of ERR_MIS field.
	DCMI_MIS_ERR_MIS_Msk = 0x4
	// Bit ERR_MIS.
	DCMI_MIS_ERR_MIS = 0x4
	// No interrupt is generated on a synchronization error
	DCMI_MIS_ERR_MIS_Disabled = 0x0
	// An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set
	DCMI_MIS_ERR_MIS_Enabled = 0x1
	// Position of OVR_MIS field.
	DCMI_MIS_OVR_MIS_Pos = 0x1
	// Bit mask of OVR_MIS field.
	DCMI_MIS_OVR_MIS_Msk = 0x2
	// Bit OVR_MIS.
	DCMI_MIS_OVR_MIS = 0x2
	// No interrupt is generated on overrun
	DCMI_MIS_OVR_MIS_Disabled = 0x0
	// An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER
	DCMI_MIS_OVR_MIS_Enabled = 0x1
	// Position of FRAME_MIS field.
	DCMI_MIS_FRAME_MIS_Pos = 0x0
	// Bit mask of FRAME_MIS field.
	DCMI_MIS_FRAME_MIS_Msk = 0x1
	// Bit FRAME_MIS.
	DCMI_MIS_FRAME_MIS = 0x1
	// No interrupt is generated after a complete capture
	DCMI_MIS_FRAME_MIS_Disabled = 0x0
	// An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER
	DCMI_MIS_FRAME_MIS_Enabled = 0x1

	// ICR: interrupt clear register
	// Position of LINE_ISC field.
	DCMI_ICR_LINE_ISC_Pos = 0x4
	// Bit mask of LINE_ISC field.
	DCMI_ICR_LINE_ISC_Msk = 0x10
	// Bit LINE_ISC.
	DCMI_ICR_LINE_ISC = 0x10
	// Setting this bit clears the LINE_RIS flag in the DCMI_RIS register
	DCMI_ICR_LINE_ISC_Clear = 0x1
	// Position of VSYNC_ISC field.
	DCMI_ICR_VSYNC_ISC_Pos = 0x3
	// Bit mask of VSYNC_ISC field.
	DCMI_ICR_VSYNC_ISC_Msk = 0x8
	// Bit VSYNC_ISC.
	DCMI_ICR_VSYNC_ISC = 0x8
	// Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register
	DCMI_ICR_VSYNC_ISC_Clear = 0x1
	// Position of ERR_ISC field.
	DCMI_ICR_ERR_ISC_Pos = 0x2
	// Bit mask of ERR_ISC field.
	DCMI_ICR_ERR_ISC_Msk = 0x4
	// Bit ERR_ISC.
	DCMI_ICR_ERR_ISC = 0x4
	// Setting this bit clears the ERR_RIS flag in the DCMI_RIS register
	DCMI_ICR_ERR_ISC_Clear = 0x1
	// Position of OVR_ISC field.
	DCMI_ICR_OVR_ISC_Pos = 0x1
	// Bit mask of OVR_ISC field.
	DCMI_ICR_OVR_ISC_Msk = 0x2
	// Bit OVR_ISC.
	DCMI_ICR_OVR_ISC = 0x2
	// Setting this bit clears the OVR_RIS flag in the DCMI_RIS register
	DCMI_ICR_OVR_ISC_Clear = 0x1
	// Position of FRAME_ISC field.
	DCMI_ICR_FRAME_ISC_Pos = 0x0
	// Bit mask of FRAME_ISC field.
	DCMI_ICR_FRAME_ISC_Msk = 0x1
	// Bit FRAME_ISC.
	DCMI_ICR_FRAME_ISC = 0x1
	// Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register
	DCMI_ICR_FRAME_ISC_Clear = 0x1

	// ESCR: background offset register
	// Position of FEC field.
	DCMI_ESCR_FEC_Pos = 0x18
	// Bit mask of FEC field.
	DCMI_ESCR_FEC_Msk = 0xff000000
	// Position of LEC field.
	DCMI_ESCR_LEC_Pos = 0x10
	// Bit mask of LEC field.
	DCMI_ESCR_LEC_Msk = 0xff0000
	// Position of LSC field.
	DCMI_ESCR_LSC_Pos = 0x8
	// Bit mask of LSC field.
	DCMI_ESCR_LSC_Msk = 0xff00
	// Position of FSC field.
	DCMI_ESCR_FSC_Pos = 0x0
	// Bit mask of FSC field.
	DCMI_ESCR_FSC_Msk = 0xff

	// ESUR: embedded synchronization unmask register
	// Position of FEU field.
	DCMI_ESUR_FEU_Pos = 0x18
	// Bit mask of FEU field.
	DCMI_ESUR_FEU_Msk = 0xff000000
	// Position of LEU field.
	DCMI_ESUR_LEU_Pos = 0x10
	// Bit mask of LEU field.
	DCMI_ESUR_LEU_Msk = 0xff0000
	// Position of LSU field.
	DCMI_ESUR_LSU_Pos = 0x8
	// Bit mask of LSU field.
	DCMI_ESUR_LSU_Msk = 0xff00
	// Position of FSU field.
	DCMI_ESUR_FSU_Pos = 0x0
	// Bit mask of FSU field.
	DCMI_ESUR_FSU_Msk = 0xff

	// CWSTRT: crop window start
	// Position of VST field.
	DCMI_CWSTRT_VST_Pos = 0x10
	// Bit mask of VST field.
	DCMI_CWSTRT_VST_Msk = 0x1fff0000
	// Position of HOFFCNT field.
	DCMI_CWSTRT_HOFFCNT_Pos = 0x0
	// Bit mask of HOFFCNT field.
	DCMI_CWSTRT_HOFFCNT_Msk = 0x3fff

	// CWSIZE: crop window size
	// Position of VLINE field.
	DCMI_CWSIZE_VLINE_Pos = 0x10
	// Bit mask of VLINE field.
	DCMI_CWSIZE_VLINE_Msk = 0x3fff0000
	// Position of CAPCNT field.
	DCMI_CWSIZE_CAPCNT_Pos = 0x0
	// Bit mask of CAPCNT field.
	DCMI_CWSIZE_CAPCNT_Msk = 0x3fff

	// DR: data register
	// Position of BYTE0 field.
	DCMI_DR_BYTE0_Pos = 0x8
	// Bit mask of BYTE0 field.
	DCMI_DR_BYTE0_Msk = 0xff00
	// Position of BYTE1 field.
	DCMI_DR_BYTE1_Pos = 0x10
	// Bit mask of BYTE1 field.
	DCMI_DR_BYTE1_Msk = 0xff0000
	// Position of BYTE2 field.
	DCMI_DR_BYTE2_Pos = 0x18
	// Bit mask of BYTE2 field.
	DCMI_DR_BYTE2_Msk = 0xff000000
	// Position of BYTE3 field.
	DCMI_DR_BYTE3_Pos = 0x20
	// Bit mask of BYTE3 field.
	DCMI_DR_BYTE3_Msk = 0xff00000000
)

// Constants for DLYBOS1: The delay block (DLYB) is used to generate an output clock that is dephased from the input clock
const (
	// CR: control register
	// Position of DEN field.
	DLYB_CR_DEN_Pos = 0x0
	// Bit mask of DEN field.
	DLYB_CR_DEN_Msk = 0x1
	// Bit DEN.
	DLYB_CR_DEN = 0x1
	// Position of SEN field.
	DLYB_CR_SEN_Pos = 0x1
	// Bit mask of SEN field.
	DLYB_CR_SEN_Msk = 0x2
	// Bit SEN.
	DLYB_CR_SEN = 0x2

	// CFGR: configuration register
	// Position of SEL field.
	DLYB_CFGR_SEL_Pos = 0x0
	// Bit mask of SEL field.
	DLYB_CFGR_SEL_Msk = 0xf
	// Position of UNIT field.
	DLYB_CFGR_UNIT_Pos = 0x8
	// Bit mask of UNIT field.
	DLYB_CFGR_UNIT_Msk = 0x7f00
	// Position of LNG field.
	DLYB_CFGR_LNG_Pos = 0x10
	// Bit mask of LNG field.
	DLYB_CFGR_LNG_Msk = 0xfff0000
	// Position of LNGF field.
	DLYB_CFGR_LNGF_Pos = 0x1f
	// Bit mask of LNGF field.
	DLYB_CFGR_LNGF_Msk = 0x80000000
	// Bit LNGF.
	DLYB_CFGR_LNGF = 0x80000000
)

// Constants for DMA2D: DMA2D controller
const (
	// CR: control register
	// Position of MODE field.
	DMA2D_CR_MODE_Pos = 0x10
	// Bit mask of MODE field.
	DMA2D_CR_MODE_Msk = 0x70000
	// Memory-to-memory (FG fetch only)
	DMA2D_CR_MODE_MemoryToMemory = 0x0
	// Memory-to-memory with PFC (FG fetch only with FG PFC active)
	DMA2D_CR_MODE_MemoryToMemoryPFC = 0x1
	// Memory-to-memory with blending (FG and BG fetch with PFC and blending)
	DMA2D_CR_MODE_MemoryToMemoryPFCBlending = 0x2
	// Register-to-memory
	DMA2D_CR_MODE_RegisterToMemory = 0x3
	// Position of CEIE field.
	DMA2D_CR_CEIE_Pos = 0xd
	// Bit mask of CEIE field.
	DMA2D_CR_CEIE_Msk = 0x2000
	// Bit CEIE.
	DMA2D_CR_CEIE = 0x2000
	// CE interrupt disabled
	DMA2D_CR_CEIE_Disabled = 0x0
	// CE interrupt enabled
	DMA2D_CR_CEIE_Enabled = 0x1
	// Position of CTCIE field.
	DMA2D_CR_CTCIE_Pos = 0xc
	// Bit mask of CTCIE field.
	DMA2D_CR_CTCIE_Msk = 0x1000
	// Bit CTCIE.
	DMA2D_CR_CTCIE = 0x1000
	// CTC interrupt disabled
	DMA2D_CR_CTCIE_Disabled = 0x0
	// CTC interrupt enabled
	DMA2D_CR_CTCIE_Enabled = 0x1
	// Position of CAEIE field.
	DMA2D_CR_CAEIE_Pos = 0xb
	// Bit mask of CAEIE field.
	DMA2D_CR_CAEIE_Msk = 0x800
	// Bit CAEIE.
	DMA2D_CR_CAEIE = 0x800
	// CAE interrupt disabled
	DMA2D_CR_CAEIE_Disabled = 0x0
	// CAE interrupt enabled
	DMA2D_CR_CAEIE_Enabled = 0x1
	// Position of TWIE field.
	DMA2D_CR_TWIE_Pos = 0xa
	// Bit mask of TWIE field.
	DMA2D_CR_TWIE_Msk = 0x400
	// Bit TWIE.
	DMA2D_CR_TWIE = 0x400
	// TW interrupt disabled
	DMA2D_CR_TWIE_Disabled = 0x0
	// TW interrupt enabled
	DMA2D_CR_TWIE_Enabled = 0x1
	// Position of TCIE field.
	DMA2D_CR_TCIE_Pos = 0x9
	// Bit mask of TCIE field.
	DMA2D_CR_TCIE_Msk = 0x200
	// Bit TCIE.
	DMA2D_CR_TCIE = 0x200
	// TC interrupt disabled
	DMA2D_CR_TCIE_Disabled = 0x0
	// TC interrupt enabled
	DMA2D_CR_TCIE_Enabled = 0x1
	// Position of TEIE field.
	DMA2D_CR_TEIE_Pos = 0x8
	// Bit mask of TEIE field.
	DMA2D_CR_TEIE_Msk = 0x100
	// Bit TEIE.
	DMA2D_CR_TEIE = 0x100
	// TE interrupt disabled
	DMA2D_CR_TEIE_Disabled = 0x0
	// TE interrupt enabled
	DMA2D_CR_TEIE_Enabled = 0x1
	// Position of LOM field.
	DMA2D_CR_LOM_Pos = 0x6
	// Bit mask of LOM field.
	DMA2D_CR_LOM_Msk = 0x40
	// Bit LOM.
	DMA2D_CR_LOM = 0x40
	// Position of ABORT field.
	DMA2D_CR_ABORT_Pos = 0x2
	// Bit mask of ABORT field.
	DMA2D_CR_ABORT_Msk = 0x4
	// Bit ABORT.
	DMA2D_CR_ABORT = 0x4
	// Transfer abort requested
	DMA2D_CR_ABORT_AbortRequest = 0x1
	// Position of SUSP field.
	DMA2D_CR_SUSP_Pos = 0x1
	// Bit mask of SUSP field.
	DMA2D_CR_SUSP_Msk = 0x2
	// Bit SUSP.
	DMA2D_CR_SUSP = 0x2
	// Transfer not suspended
	DMA2D_CR_SUSP_NotSuspended = 0x0
	// Transfer suspended
	DMA2D_CR_SUSP_Suspended = 0x1
	// Position of START field.
	DMA2D_CR_START_Pos = 0x0
	// Bit mask of START field.
	DMA2D_CR_START_Msk = 0x1
	// Bit START.
	DMA2D_CR_START = 0x1
	// Launch the DMA2D
	DMA2D_CR_START_Start = 0x1

	// ISR: Interrupt Status Register
	// Position of CEIF field.
	DMA2D_ISR_CEIF_Pos = 0x5
	// Bit mask of CEIF field.
	DMA2D_ISR_CEIF_Msk = 0x20
	// Bit CEIF.
	DMA2D_ISR_CEIF = 0x20
	// Position of CTCIF field.
	DMA2D_ISR_CTCIF_Pos = 0x4
	// Bit mask of CTCIF field.
	DMA2D_ISR_CTCIF_Msk = 0x10
	// Bit CTCIF.
	DMA2D_ISR_CTCIF = 0x10
	// Position of CAEIF field.
	DMA2D_ISR_CAEIF_Pos = 0x3
	// Bit mask of CAEIF field.
	DMA2D_ISR_CAEIF_Msk = 0x8
	// Bit CAEIF.
	DMA2D_ISR_CAEIF = 0x8
	// Position of TWIF field.
	DMA2D_ISR_TWIF_Pos = 0x2
	// Bit mask of TWIF field.
	DMA2D_ISR_TWIF_Msk = 0x4
	// Bit TWIF.
	DMA2D_ISR_TWIF = 0x4
	// Position of TCIF field.
	DMA2D_ISR_TCIF_Pos = 0x1
	// Bit mask of TCIF field.
	DMA2D_ISR_TCIF_Msk = 0x2
	// Bit TCIF.
	DMA2D_ISR_TCIF = 0x2
	// Position of TEIF field.
	DMA2D_ISR_TEIF_Pos = 0x0
	// Bit mask of TEIF field.
	DMA2D_ISR_TEIF_Msk = 0x1
	// Bit TEIF.
	DMA2D_ISR_TEIF = 0x1

	// IFCR: interrupt flag clear register
	// Position of CCEIF field.
	DMA2D_IFCR_CCEIF_Pos = 0x5
	// Bit mask of CCEIF field.
	DMA2D_IFCR_CCEIF_Msk = 0x20
	// Bit CCEIF.
	DMA2D_IFCR_CCEIF = 0x20
	// Clear the CEIF flag in the ISR register
	DMA2D_IFCR_CCEIF_Clear = 0x1
	// Position of CCTCIF field.
	DMA2D_IFCR_CCTCIF_Pos = 0x4
	// Bit mask of CCTCIF field.
	DMA2D_IFCR_CCTCIF_Msk = 0x10
	// Bit CCTCIF.
	DMA2D_IFCR_CCTCIF = 0x10
	// Clear the CTCIF flag in the ISR register
	DMA2D_IFCR_CCTCIF_Clear = 0x1
	// Position of CAECIF field.
	DMA2D_IFCR_CAECIF_Pos = 0x3
	// Bit mask of CAECIF field.
	DMA2D_IFCR_CAECIF_Msk = 0x8
	// Bit CAECIF.
	DMA2D_IFCR_CAECIF = 0x8
	// Clear the CAEIF flag in the ISR register
	DMA2D_IFCR_CAECIF_Clear = 0x1
	// Position of CTWIF field.
	DMA2D_IFCR_CTWIF_Pos = 0x2
	// Bit mask of CTWIF field.
	DMA2D_IFCR_CTWIF_Msk = 0x4
	// Bit CTWIF.
	DMA2D_IFCR_CTWIF = 0x4
	// Clear the TWIF flag in the ISR register
	DMA2D_IFCR_CTWIF_Clear = 0x1
	// Position of CTCIF field.
	DMA2D_IFCR_CTCIF_Pos = 0x1
	// Bit mask of CTCIF field.
	DMA2D_IFCR_CTCIF_Msk = 0x2
	// Bit CTCIF.
	DMA2D_IFCR_CTCIF = 0x2
	// Clear the TCIF flag in the ISR register
	DMA2D_IFCR_CTCIF_Clear = 0x1
	// Position of CTEIF field.
	DMA2D_IFCR_CTEIF_Pos = 0x0
	// Bit mask of CTEIF field.
	DMA2D_IFCR_CTEIF_Msk = 0x1
	// Bit CTEIF.
	DMA2D_IFCR_CTEIF = 0x1
	// Clear the TEIF flag in the ISR register
	DMA2D_IFCR_CTEIF_Clear = 0x1

	// FGMAR: foreground memory address register
	// Position of MA field.
	DMA2D_FGMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_FGMAR_MA_Msk = 0xffffffff

	// FGOR: foreground offset register
	// Position of LO field.
	DMA2D_FGOR_LO_Pos = 0x0
	// Bit mask of LO field.
	DMA2D_FGOR_LO_Msk = 0xffff

	// BGMAR: background memory address register
	// Position of MA field.
	DMA2D_BGMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_BGMAR_MA_Msk = 0xffffffff

	// BGOR: background offset register
	// Position of LO field.
	DMA2D_BGOR_LO_Pos = 0x0
	// Bit mask of LO field.
	DMA2D_BGOR_LO_Msk = 0xffff

	// FGPFCCR: foreground PFC control register
	// Position of ALPHA field.
	DMA2D_FGPFCCR_ALPHA_Pos = 0x18
	// Bit mask of ALPHA field.
	DMA2D_FGPFCCR_ALPHA_Msk = 0xff000000
	// Position of RBS field.
	DMA2D_FGPFCCR_RBS_Pos = 0x15
	// Bit mask of RBS field.
	DMA2D_FGPFCCR_RBS_Msk = 0x200000
	// Bit RBS.
	DMA2D_FGPFCCR_RBS = 0x200000
	// No Red Blue Swap (RGB or ARGB)
	DMA2D_FGPFCCR_RBS_Regular = 0x0
	// Red Blue Swap (BGR or ABGR)
	DMA2D_FGPFCCR_RBS_Swap = 0x1
	// Position of AI field.
	DMA2D_FGPFCCR_AI_Pos = 0x14
	// Bit mask of AI field.
	DMA2D_FGPFCCR_AI_Msk = 0x100000
	// Bit AI.
	DMA2D_FGPFCCR_AI = 0x100000
	// Regular alpha
	DMA2D_FGPFCCR_AI_RegularAlpha = 0x0
	// Inverted alpha
	DMA2D_FGPFCCR_AI_InvertedAlpha = 0x1
	// Position of AM field.
	DMA2D_FGPFCCR_AM_Pos = 0x10
	// Bit mask of AM field.
	DMA2D_FGPFCCR_AM_Msk = 0x30000
	// No modification of alpha channel
	DMA2D_FGPFCCR_AM_NoModify = 0x0
	// Replace with value in ALPHA[7:0]
	DMA2D_FGPFCCR_AM_Replace = 0x1
	// Multiply with value in ALPHA[7:0]
	DMA2D_FGPFCCR_AM_Multiply = 0x2
	// Position of CS field.
	DMA2D_FGPFCCR_CS_Pos = 0x8
	// Bit mask of CS field.
	DMA2D_FGPFCCR_CS_Msk = 0xff00
	// Position of START field.
	DMA2D_FGPFCCR_START_Pos = 0x5
	// Bit mask of START field.
	DMA2D_FGPFCCR_START_Msk = 0x20
	// Bit START.
	DMA2D_FGPFCCR_START = 0x20
	// Start the automatic loading of the CLUT
	DMA2D_FGPFCCR_START_Start = 0x1
	// Position of CCM field.
	DMA2D_FGPFCCR_CCM_Pos = 0x4
	// Bit mask of CCM field.
	DMA2D_FGPFCCR_CCM_Msk = 0x10
	// Bit CCM.
	DMA2D_FGPFCCR_CCM = 0x10
	// CLUT color format ARGB8888
	DMA2D_FGPFCCR_CCM_ARGB8888 = 0x0
	// CLUT color format RGB888
	DMA2D_FGPFCCR_CCM_RGB888 = 0x1
	// Position of CM field.
	DMA2D_FGPFCCR_CM_Pos = 0x0
	// Bit mask of CM field.
	DMA2D_FGPFCCR_CM_Msk = 0xf
	// Color mode ARGB8888
	DMA2D_FGPFCCR_CM_ARGB8888 = 0x0
	// Color mode RGB888
	DMA2D_FGPFCCR_CM_RGB888 = 0x1
	// Color mode RGB565
	DMA2D_FGPFCCR_CM_RGB565 = 0x2
	// Color mode ARGB1555
	DMA2D_FGPFCCR_CM_ARGB1555 = 0x3
	// Color mode ARGB4444
	DMA2D_FGPFCCR_CM_ARGB4444 = 0x4
	// Color mode L8
	DMA2D_FGPFCCR_CM_L8 = 0x5
	// Color mode AL44
	DMA2D_FGPFCCR_CM_AL44 = 0x6
	// Color mode AL88
	DMA2D_FGPFCCR_CM_AL88 = 0x7
	// Color mode L4
	DMA2D_FGPFCCR_CM_L4 = 0x8
	// Color mode A8
	DMA2D_FGPFCCR_CM_A8 = 0x9
	// Color mode A4
	DMA2D_FGPFCCR_CM_A4 = 0xa
	// Color mode YCbCr
	DMA2D_FGPFCCR_CM_YCbCr = 0xb

	// FGCOLR: foreground color register
	// Position of RED field.
	DMA2D_FGCOLR_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_FGCOLR_RED_Msk = 0xff0000
	// Position of GREEN field.
	DMA2D_FGCOLR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_FGCOLR_GREEN_Msk = 0xff00
	// Position of BLUE field.
	DMA2D_FGCOLR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_FGCOLR_BLUE_Msk = 0xff

	// BGPFCCR: background PFC control register
	// Position of ALPHA field.
	DMA2D_BGPFCCR_ALPHA_Pos = 0x18
	// Bit mask of ALPHA field.
	DMA2D_BGPFCCR_ALPHA_Msk = 0xff000000
	// Position of RBS field.
	DMA2D_BGPFCCR_RBS_Pos = 0x15
	// Bit mask of RBS field.
	DMA2D_BGPFCCR_RBS_Msk = 0x200000
	// Bit RBS.
	DMA2D_BGPFCCR_RBS = 0x200000
	// No Red Blue Swap (RGB or ARGB)
	DMA2D_BGPFCCR_RBS_Regular = 0x0
	// Red Blue Swap (BGR or ABGR)
	DMA2D_BGPFCCR_RBS_Swap = 0x1
	// Position of AI field.
	DMA2D_BGPFCCR_AI_Pos = 0x14
	// Bit mask of AI field.
	DMA2D_BGPFCCR_AI_Msk = 0x100000
	// Bit AI.
	DMA2D_BGPFCCR_AI = 0x100000
	// Regular alpha
	DMA2D_BGPFCCR_AI_RegularAlpha = 0x0
	// Inverted alpha
	DMA2D_BGPFCCR_AI_InvertedAlpha = 0x1
	// Position of AM field.
	DMA2D_BGPFCCR_AM_Pos = 0x10
	// Bit mask of AM field.
	DMA2D_BGPFCCR_AM_Msk = 0x30000
	// No modification of alpha channel
	DMA2D_BGPFCCR_AM_NoModify = 0x0
	// Replace with value in ALPHA[7:0]
	DMA2D_BGPFCCR_AM_Replace = 0x1
	// Multiply with value in ALPHA[7:0]
	DMA2D_BGPFCCR_AM_Multiply = 0x2
	// Position of CS field.
	DMA2D_BGPFCCR_CS_Pos = 0x8
	// Bit mask of CS field.
	DMA2D_BGPFCCR_CS_Msk = 0xff00
	// Position of START field.
	DMA2D_BGPFCCR_START_Pos = 0x5
	// Bit mask of START field.
	DMA2D_BGPFCCR_START_Msk = 0x20
	// Bit START.
	DMA2D_BGPFCCR_START = 0x20
	// Start the automatic loading of the CLUT
	DMA2D_BGPFCCR_START_Start = 0x1
	// Position of CCM field.
	DMA2D_BGPFCCR_CCM_Pos = 0x4
	// Bit mask of CCM field.
	DMA2D_BGPFCCR_CCM_Msk = 0x10
	// Bit CCM.
	DMA2D_BGPFCCR_CCM = 0x10
	// CLUT color format ARGB8888
	DMA2D_BGPFCCR_CCM_ARGB8888 = 0x0
	// CLUT color format RGB888
	DMA2D_BGPFCCR_CCM_RGB888 = 0x1
	// Position of CM field.
	DMA2D_BGPFCCR_CM_Pos = 0x0
	// Bit mask of CM field.
	DMA2D_BGPFCCR_CM_Msk = 0xf
	// Color mode ARGB8888
	DMA2D_BGPFCCR_CM_ARGB8888 = 0x0
	// Color mode RGB888
	DMA2D_BGPFCCR_CM_RGB888 = 0x1
	// Color mode RGB565
	DMA2D_BGPFCCR_CM_RGB565 = 0x2
	// Color mode ARGB1555
	DMA2D_BGPFCCR_CM_ARGB1555 = 0x3
	// Color mode ARGB4444
	DMA2D_BGPFCCR_CM_ARGB4444 = 0x4
	// Color mode L8
	DMA2D_BGPFCCR_CM_L8 = 0x5
	// Color mode AL44
	DMA2D_BGPFCCR_CM_AL44 = 0x6
	// Color mode AL88
	DMA2D_BGPFCCR_CM_AL88 = 0x7
	// Color mode L4
	DMA2D_BGPFCCR_CM_L4 = 0x8
	// Color mode A8
	DMA2D_BGPFCCR_CM_A8 = 0x9
	// Color mode A4
	DMA2D_BGPFCCR_CM_A4 = 0xa

	// BGCOLR: background color register
	// Position of RED field.
	DMA2D_BGCOLR_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_BGCOLR_RED_Msk = 0xff0000
	// Position of GREEN field.
	DMA2D_BGCOLR_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_BGCOLR_GREEN_Msk = 0xff00
	// Position of BLUE field.
	DMA2D_BGCOLR_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_BGCOLR_BLUE_Msk = 0xff

	// FGCMAR: foreground CLUT memory address register
	// Position of MA field.
	DMA2D_FGCMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_FGCMAR_MA_Msk = 0xffffffff

	// BGCMAR: background CLUT memory address register
	// Position of MA field.
	DMA2D_BGCMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_BGCMAR_MA_Msk = 0xffffffff

	// OPFCCR: output PFC control register
	// Position of RBS field.
	DMA2D_OPFCCR_RBS_Pos = 0x15
	// Bit mask of RBS field.
	DMA2D_OPFCCR_RBS_Msk = 0x200000
	// Bit RBS.
	DMA2D_OPFCCR_RBS = 0x200000
	// No Red Blue Swap (RGB or ARGB)
	DMA2D_OPFCCR_RBS_Regular = 0x0
	// Red Blue Swap (BGR or ABGR)
	DMA2D_OPFCCR_RBS_Swap = 0x1
	// Position of AI field.
	DMA2D_OPFCCR_AI_Pos = 0x14
	// Bit mask of AI field.
	DMA2D_OPFCCR_AI_Msk = 0x100000
	// Bit AI.
	DMA2D_OPFCCR_AI = 0x100000
	// Regular alpha
	DMA2D_OPFCCR_AI_RegularAlpha = 0x0
	// Inverted alpha
	DMA2D_OPFCCR_AI_InvertedAlpha = 0x1
	// Position of SB field.
	DMA2D_OPFCCR_SB_Pos = 0x9
	// Bit mask of SB field.
	DMA2D_OPFCCR_SB_Msk = 0x200
	// Bit SB.
	DMA2D_OPFCCR_SB = 0x200
	// Regular byte order
	DMA2D_OPFCCR_SB_Regular = 0x0
	// Bytes are swapped two by two
	DMA2D_OPFCCR_SB_SwapBytes = 0x1
	// Position of CM field.
	DMA2D_OPFCCR_CM_Pos = 0x0
	// Bit mask of CM field.
	DMA2D_OPFCCR_CM_Msk = 0x7
	// ARGB8888
	DMA2D_OPFCCR_CM_ARGB8888 = 0x0
	// RGB888
	DMA2D_OPFCCR_CM_RGB888 = 0x1
	// RGB565
	DMA2D_OPFCCR_CM_RGB565 = 0x2
	// ARGB1555
	DMA2D_OPFCCR_CM_ARGB1555 = 0x3
	// ARGB4444
	DMA2D_OPFCCR_CM_ARGB4444 = 0x4

	// OCOLR_RGB888: output color register
	// Position of APLHA field.
	DMA2D_OCOLR_RGB888_APLHA_Pos = 0x18
	// Bit mask of APLHA field.
	DMA2D_OCOLR_RGB888_APLHA_Msk = 0xff000000
	// Position of RED field.
	DMA2D_OCOLR_RGB888_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_OCOLR_RGB888_RED_Msk = 0xff0000
	// Position of GREEN field.
	DMA2D_OCOLR_RGB888_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_OCOLR_RGB888_GREEN_Msk = 0xff00
	// Position of BLUE field.
	DMA2D_OCOLR_RGB888_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_OCOLR_RGB888_BLUE_Msk = 0xff

	// OCOLR_RGB565: output color register
	// Position of RED field.
	DMA2D_OCOLR_RGB565_RED_Pos = 0xb
	// Bit mask of RED field.
	DMA2D_OCOLR_RGB565_RED_Msk = 0xf800
	// Position of GREEN field.
	DMA2D_OCOLR_RGB565_GREEN_Pos = 0x5
	// Bit mask of GREEN field.
	DMA2D_OCOLR_RGB565_GREEN_Msk = 0x7e0
	// Position of BLUE field.
	DMA2D_OCOLR_RGB565_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_OCOLR_RGB565_BLUE_Msk = 0x1f

	// OCOLR_ARGB1555: output color register
	// Position of A field.
	DMA2D_OCOLR_ARGB1555_A_Pos = 0xf
	// Bit mask of A field.
	DMA2D_OCOLR_ARGB1555_A_Msk = 0x8000
	// Bit A.
	DMA2D_OCOLR_ARGB1555_A = 0x8000
	// Position of RED field.
	DMA2D_OCOLR_ARGB1555_RED_Pos = 0xa
	// Bit mask of RED field.
	DMA2D_OCOLR_ARGB1555_RED_Msk = 0x7c00
	// Position of GREEN field.
	DMA2D_OCOLR_ARGB1555_GREEN_Pos = 0x5
	// Bit mask of GREEN field.
	DMA2D_OCOLR_ARGB1555_GREEN_Msk = 0x3e0
	// Position of BLUE field.
	DMA2D_OCOLR_ARGB1555_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_OCOLR_ARGB1555_BLUE_Msk = 0x1f

	// OCOLR_ARGB4444: output color register
	// Position of ALPHA field.
	DMA2D_OCOLR_ARGB4444_ALPHA_Pos = 0xc
	// Bit mask of ALPHA field.
	DMA2D_OCOLR_ARGB4444_ALPHA_Msk = 0xf000
	// Position of RED field.
	DMA2D_OCOLR_ARGB4444_RED_Pos = 0x8
	// Bit mask of RED field.
	DMA2D_OCOLR_ARGB4444_RED_Msk = 0xf00
	// Position of GREEN field.
	DMA2D_OCOLR_ARGB4444_GREEN_Pos = 0x4
	// Bit mask of GREEN field.
	DMA2D_OCOLR_ARGB4444_GREEN_Msk = 0xf0
	// Position of BLUE field.
	DMA2D_OCOLR_ARGB4444_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_OCOLR_ARGB4444_BLUE_Msk = 0xf

	// OMAR: output memory address register
	// Position of MA field.
	DMA2D_OMAR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA2D_OMAR_MA_Msk = 0xffffffff

	// OOR: output offset register
	// Position of LO field.
	DMA2D_OOR_LO_Pos = 0x0
	// Bit mask of LO field.
	DMA2D_OOR_LO_Msk = 0xffff

	// NLR: number of line register
	// Position of PL field.
	DMA2D_NLR_PL_Pos = 0x10
	// Bit mask of PL field.
	DMA2D_NLR_PL_Msk = 0x3fff0000
	// Position of NL field.
	DMA2D_NLR_NL_Pos = 0x0
	// Bit mask of NL field.
	DMA2D_NLR_NL_Msk = 0xffff

	// LWR: line watermark register
	// Position of LW field.
	DMA2D_LWR_LW_Pos = 0x0
	// Bit mask of LW field.
	DMA2D_LWR_LW_Msk = 0xffff

	// AMTCR: AHB master timer configuration register
	// Position of DT field.
	DMA2D_AMTCR_DT_Pos = 0x8
	// Bit mask of DT field.
	DMA2D_AMTCR_DT_Msk = 0xff00
	// Position of EN field.
	DMA2D_AMTCR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA2D_AMTCR_EN_Msk = 0x1
	// Bit EN.
	DMA2D_AMTCR_EN = 0x1
	// Disabled AHB/AXI dead-time functionality
	DMA2D_AMTCR_EN_Disabled = 0x0
	// Enabled AHB/AXI dead-time functionality
	DMA2D_AMTCR_EN_Enabled = 0x1

	// FGCLUT: FGCLUT
	// Position of APLHA field.
	DMA2D_FGCLUT_APLHA_Pos = 0x18
	// Bit mask of APLHA field.
	DMA2D_FGCLUT_APLHA_Msk = 0xff000000
	// Position of RED field.
	DMA2D_FGCLUT_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_FGCLUT_RED_Msk = 0xff0000
	// Position of GREEN field.
	DMA2D_FGCLUT_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_FGCLUT_GREEN_Msk = 0xff00
	// Position of BLUE field.
	DMA2D_FGCLUT_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_FGCLUT_BLUE_Msk = 0xff

	// BGCLUT: BGCLUT
	// Position of APLHA field.
	DMA2D_BGCLUT_APLHA_Pos = 0x18
	// Bit mask of APLHA field.
	DMA2D_BGCLUT_APLHA_Msk = 0xff000000
	// Position of RED field.
	DMA2D_BGCLUT_RED_Pos = 0x10
	// Bit mask of RED field.
	DMA2D_BGCLUT_RED_Msk = 0xff0000
	// Position of GREEN field.
	DMA2D_BGCLUT_GREEN_Pos = 0x8
	// Bit mask of GREEN field.
	DMA2D_BGCLUT_GREEN_Msk = 0xff00
	// Position of BLUE field.
	DMA2D_BGCLUT_BLUE_Pos = 0x0
	// Bit mask of BLUE field.
	DMA2D_BGCLUT_BLUE_Msk = 0xff
)

// Constants for EXTI: External interrupt/event controller
const (
	// RTSR1: EXTI rising trigger selection register
	// Position of RT0 field.
	EXTI_RTSR1_RT0_Pos = 0x0
	// Bit mask of RT0 field.
	EXTI_RTSR1_RT0_Msk = 0x1
	// Bit RT0.
	EXTI_RTSR1_RT0 = 0x1
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT0_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT0_Enabled = 0x1
	// Position of RT1 field.
	EXTI_RTSR1_RT1_Pos = 0x1
	// Bit mask of RT1 field.
	EXTI_RTSR1_RT1_Msk = 0x2
	// Bit RT1.
	EXTI_RTSR1_RT1 = 0x2
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT1_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT1_Enabled = 0x1
	// Position of RT2 field.
	EXTI_RTSR1_RT2_Pos = 0x2
	// Bit mask of RT2 field.
	EXTI_RTSR1_RT2_Msk = 0x4
	// Bit RT2.
	EXTI_RTSR1_RT2 = 0x4
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT2_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT2_Enabled = 0x1
	// Position of RT3 field.
	EXTI_RTSR1_RT3_Pos = 0x3
	// Bit mask of RT3 field.
	EXTI_RTSR1_RT3_Msk = 0x8
	// Bit RT3.
	EXTI_RTSR1_RT3 = 0x8
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT3_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT3_Enabled = 0x1
	// Position of RT4 field.
	EXTI_RTSR1_RT4_Pos = 0x4
	// Bit mask of RT4 field.
	EXTI_RTSR1_RT4_Msk = 0x10
	// Bit RT4.
	EXTI_RTSR1_RT4 = 0x10
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT4_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT4_Enabled = 0x1
	// Position of RT5 field.
	EXTI_RTSR1_RT5_Pos = 0x5
	// Bit mask of RT5 field.
	EXTI_RTSR1_RT5_Msk = 0x20
	// Bit RT5.
	EXTI_RTSR1_RT5 = 0x20
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT5_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT5_Enabled = 0x1
	// Position of RT6 field.
	EXTI_RTSR1_RT6_Pos = 0x6
	// Bit mask of RT6 field.
	EXTI_RTSR1_RT6_Msk = 0x40
	// Bit RT6.
	EXTI_RTSR1_RT6 = 0x40
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT6_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT6_Enabled = 0x1
	// Position of RT7 field.
	EXTI_RTSR1_RT7_Pos = 0x7
	// Bit mask of RT7 field.
	EXTI_RTSR1_RT7_Msk = 0x80
	// Bit RT7.
	EXTI_RTSR1_RT7 = 0x80
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT7_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT7_Enabled = 0x1
	// Position of RT8 field.
	EXTI_RTSR1_RT8_Pos = 0x8
	// Bit mask of RT8 field.
	EXTI_RTSR1_RT8_Msk = 0x100
	// Bit RT8.
	EXTI_RTSR1_RT8 = 0x100
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT8_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT8_Enabled = 0x1
	// Position of RT9 field.
	EXTI_RTSR1_RT9_Pos = 0x9
	// Bit mask of RT9 field.
	EXTI_RTSR1_RT9_Msk = 0x200
	// Bit RT9.
	EXTI_RTSR1_RT9 = 0x200
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT9_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT9_Enabled = 0x1
	// Position of RT10 field.
	EXTI_RTSR1_RT10_Pos = 0xa
	// Bit mask of RT10 field.
	EXTI_RTSR1_RT10_Msk = 0x400
	// Bit RT10.
	EXTI_RTSR1_RT10 = 0x400
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT10_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT10_Enabled = 0x1
	// Position of RT11 field.
	EXTI_RTSR1_RT11_Pos = 0xb
	// Bit mask of RT11 field.
	EXTI_RTSR1_RT11_Msk = 0x800
	// Bit RT11.
	EXTI_RTSR1_RT11 = 0x800
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT11_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT11_Enabled = 0x1
	// Position of RT12 field.
	EXTI_RTSR1_RT12_Pos = 0xc
	// Bit mask of RT12 field.
	EXTI_RTSR1_RT12_Msk = 0x1000
	// Bit RT12.
	EXTI_RTSR1_RT12 = 0x1000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT12_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT12_Enabled = 0x1
	// Position of RT13 field.
	EXTI_RTSR1_RT13_Pos = 0xd
	// Bit mask of RT13 field.
	EXTI_RTSR1_RT13_Msk = 0x2000
	// Bit RT13.
	EXTI_RTSR1_RT13 = 0x2000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT13_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT13_Enabled = 0x1
	// Position of RT14 field.
	EXTI_RTSR1_RT14_Pos = 0xe
	// Bit mask of RT14 field.
	EXTI_RTSR1_RT14_Msk = 0x4000
	// Bit RT14.
	EXTI_RTSR1_RT14 = 0x4000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT14_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT14_Enabled = 0x1
	// Position of RT15 field.
	EXTI_RTSR1_RT15_Pos = 0xf
	// Bit mask of RT15 field.
	EXTI_RTSR1_RT15_Msk = 0x8000
	// Bit RT15.
	EXTI_RTSR1_RT15 = 0x8000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT15_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT15_Enabled = 0x1
	// Position of RT16 field.
	EXTI_RTSR1_RT16_Pos = 0x10
	// Bit mask of RT16 field.
	EXTI_RTSR1_RT16_Msk = 0x10000
	// Bit RT16.
	EXTI_RTSR1_RT16 = 0x10000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT16_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT16_Enabled = 0x1
	// Position of RT17 field.
	EXTI_RTSR1_RT17_Pos = 0x11
	// Bit mask of RT17 field.
	EXTI_RTSR1_RT17_Msk = 0x20000
	// Bit RT17.
	EXTI_RTSR1_RT17 = 0x20000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT17_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT17_Enabled = 0x1
	// Position of RT18 field.
	EXTI_RTSR1_RT18_Pos = 0x12
	// Bit mask of RT18 field.
	EXTI_RTSR1_RT18_Msk = 0x40000
	// Bit RT18.
	EXTI_RTSR1_RT18 = 0x40000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT18_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT18_Enabled = 0x1
	// Position of RT19 field.
	EXTI_RTSR1_RT19_Pos = 0x13
	// Bit mask of RT19 field.
	EXTI_RTSR1_RT19_Msk = 0x80000
	// Bit RT19.
	EXTI_RTSR1_RT19 = 0x80000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT19_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT19_Enabled = 0x1
	// Position of RT20 field.
	EXTI_RTSR1_RT20_Pos = 0x14
	// Bit mask of RT20 field.
	EXTI_RTSR1_RT20_Msk = 0x100000
	// Bit RT20.
	EXTI_RTSR1_RT20 = 0x100000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT20_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT20_Enabled = 0x1
	// Position of RT21 field.
	EXTI_RTSR1_RT21_Pos = 0x15
	// Bit mask of RT21 field.
	EXTI_RTSR1_RT21_Msk = 0x200000
	// Bit RT21.
	EXTI_RTSR1_RT21 = 0x200000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT21_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT21_Enabled = 0x1
	// Position of RT22 field.
	EXTI_RTSR1_RT22_Pos = 0x16
	// Bit mask of RT22 field.
	EXTI_RTSR1_RT22_Msk = 0x400000
	// Bit RT22.
	EXTI_RTSR1_RT22 = 0x400000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT22_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT22_Enabled = 0x1
	// Position of RT23 field.
	EXTI_RTSR1_RT23_Pos = 0x17
	// Bit mask of RT23 field.
	EXTI_RTSR1_RT23_Msk = 0x800000
	// Bit RT23.
	EXTI_RTSR1_RT23 = 0x800000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT23_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT23_Enabled = 0x1
	// Position of RT24 field.
	EXTI_RTSR1_RT24_Pos = 0x18
	// Bit mask of RT24 field.
	EXTI_RTSR1_RT24_Msk = 0x1000000
	// Bit RT24.
	EXTI_RTSR1_RT24 = 0x1000000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT24_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT24_Enabled = 0x1
	// Position of RT25 field.
	EXTI_RTSR1_RT25_Pos = 0x19
	// Bit mask of RT25 field.
	EXTI_RTSR1_RT25_Msk = 0x2000000
	// Bit RT25.
	EXTI_RTSR1_RT25 = 0x2000000
	// Rising edge trigger is disabled
	EXTI_RTSR1_RT25_Disabled = 0x0
	// Rising edge trigger is enabled
	EXTI_RTSR1_RT25_Enabled = 0x1

	// FTSR1: EXTI falling trigger selection register
	// Position of FT0 field.
	EXTI_FTSR1_FT0_Pos = 0x0
	// Bit mask of FT0 field.
	EXTI_FTSR1_FT0_Msk = 0x1
	// Bit FT0.
	EXTI_FTSR1_FT0 = 0x1
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT0_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT0_Enabled = 0x1
	// Position of FT1 field.
	EXTI_FTSR1_FT1_Pos = 0x1
	// Bit mask of FT1 field.
	EXTI_FTSR1_FT1_Msk = 0x2
	// Bit FT1.
	EXTI_FTSR1_FT1 = 0x2
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT1_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT1_Enabled = 0x1
	// Position of FT2 field.
	EXTI_FTSR1_FT2_Pos = 0x2
	// Bit mask of FT2 field.
	EXTI_FTSR1_FT2_Msk = 0x4
	// Bit FT2.
	EXTI_FTSR1_FT2 = 0x4
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT2_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT2_Enabled = 0x1
	// Position of FT3 field.
	EXTI_FTSR1_FT3_Pos = 0x3
	// Bit mask of FT3 field.
	EXTI_FTSR1_FT3_Msk = 0x8
	// Bit FT3.
	EXTI_FTSR1_FT3 = 0x8
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT3_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT3_Enabled = 0x1
	// Position of FT4 field.
	EXTI_FTSR1_FT4_Pos = 0x4
	// Bit mask of FT4 field.
	EXTI_FTSR1_FT4_Msk = 0x10
	// Bit FT4.
	EXTI_FTSR1_FT4 = 0x10
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT4_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT4_Enabled = 0x1
	// Position of FT5 field.
	EXTI_FTSR1_FT5_Pos = 0x5
	// Bit mask of FT5 field.
	EXTI_FTSR1_FT5_Msk = 0x20
	// Bit FT5.
	EXTI_FTSR1_FT5 = 0x20
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT5_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT5_Enabled = 0x1
	// Position of FT6 field.
	EXTI_FTSR1_FT6_Pos = 0x6
	// Bit mask of FT6 field.
	EXTI_FTSR1_FT6_Msk = 0x40
	// Bit FT6.
	EXTI_FTSR1_FT6 = 0x40
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT6_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT6_Enabled = 0x1
	// Position of FT7 field.
	EXTI_FTSR1_FT7_Pos = 0x7
	// Bit mask of FT7 field.
	EXTI_FTSR1_FT7_Msk = 0x80
	// Bit FT7.
	EXTI_FTSR1_FT7 = 0x80
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT7_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT7_Enabled = 0x1
	// Position of FT8 field.
	EXTI_FTSR1_FT8_Pos = 0x8
	// Bit mask of FT8 field.
	EXTI_FTSR1_FT8_Msk = 0x100
	// Bit FT8.
	EXTI_FTSR1_FT8 = 0x100
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT8_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT8_Enabled = 0x1
	// Position of FT9 field.
	EXTI_FTSR1_FT9_Pos = 0x9
	// Bit mask of FT9 field.
	EXTI_FTSR1_FT9_Msk = 0x200
	// Bit FT9.
	EXTI_FTSR1_FT9 = 0x200
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT9_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT9_Enabled = 0x1
	// Position of FT10 field.
	EXTI_FTSR1_FT10_Pos = 0xa
	// Bit mask of FT10 field.
	EXTI_FTSR1_FT10_Msk = 0x400
	// Bit FT10.
	EXTI_FTSR1_FT10 = 0x400
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT10_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT10_Enabled = 0x1
	// Position of FT11 field.
	EXTI_FTSR1_FT11_Pos = 0xb
	// Bit mask of FT11 field.
	EXTI_FTSR1_FT11_Msk = 0x800
	// Bit FT11.
	EXTI_FTSR1_FT11 = 0x800
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT11_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT11_Enabled = 0x1
	// Position of FT12 field.
	EXTI_FTSR1_FT12_Pos = 0xc
	// Bit mask of FT12 field.
	EXTI_FTSR1_FT12_Msk = 0x1000
	// Bit FT12.
	EXTI_FTSR1_FT12 = 0x1000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT12_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT12_Enabled = 0x1
	// Position of FT13 field.
	EXTI_FTSR1_FT13_Pos = 0xd
	// Bit mask of FT13 field.
	EXTI_FTSR1_FT13_Msk = 0x2000
	// Bit FT13.
	EXTI_FTSR1_FT13 = 0x2000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT13_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT13_Enabled = 0x1
	// Position of FT14 field.
	EXTI_FTSR1_FT14_Pos = 0xe
	// Bit mask of FT14 field.
	EXTI_FTSR1_FT14_Msk = 0x4000
	// Bit FT14.
	EXTI_FTSR1_FT14 = 0x4000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT14_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT14_Enabled = 0x1
	// Position of FT15 field.
	EXTI_FTSR1_FT15_Pos = 0xf
	// Bit mask of FT15 field.
	EXTI_FTSR1_FT15_Msk = 0x8000
	// Bit FT15.
	EXTI_FTSR1_FT15 = 0x8000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT15_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT15_Enabled = 0x1
	// Position of FT16 field.
	EXTI_FTSR1_FT16_Pos = 0x10
	// Bit mask of FT16 field.
	EXTI_FTSR1_FT16_Msk = 0x10000
	// Bit FT16.
	EXTI_FTSR1_FT16 = 0x10000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT16_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT16_Enabled = 0x1
	// Position of FT17 field.
	EXTI_FTSR1_FT17_Pos = 0x11
	// Bit mask of FT17 field.
	EXTI_FTSR1_FT17_Msk = 0x20000
	// Bit FT17.
	EXTI_FTSR1_FT17 = 0x20000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT17_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT17_Enabled = 0x1
	// Position of FT18 field.
	EXTI_FTSR1_FT18_Pos = 0x12
	// Bit mask of FT18 field.
	EXTI_FTSR1_FT18_Msk = 0x40000
	// Bit FT18.
	EXTI_FTSR1_FT18 = 0x40000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT18_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT18_Enabled = 0x1
	// Position of FT19 field.
	EXTI_FTSR1_FT19_Pos = 0x13
	// Bit mask of FT19 field.
	EXTI_FTSR1_FT19_Msk = 0x80000
	// Bit FT19.
	EXTI_FTSR1_FT19 = 0x80000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT19_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT19_Enabled = 0x1
	// Position of FT20 field.
	EXTI_FTSR1_FT20_Pos = 0x14
	// Bit mask of FT20 field.
	EXTI_FTSR1_FT20_Msk = 0x100000
	// Bit FT20.
	EXTI_FTSR1_FT20 = 0x100000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT20_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT20_Enabled = 0x1
	// Position of FT21 field.
	EXTI_FTSR1_FT21_Pos = 0x15
	// Bit mask of FT21 field.
	EXTI_FTSR1_FT21_Msk = 0x200000
	// Bit FT21.
	EXTI_FTSR1_FT21 = 0x200000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT21_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT21_Enabled = 0x1
	// Position of FT22 field.
	EXTI_FTSR1_FT22_Pos = 0x16
	// Bit mask of FT22 field.
	EXTI_FTSR1_FT22_Msk = 0x400000
	// Bit FT22.
	EXTI_FTSR1_FT22 = 0x400000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT22_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT22_Enabled = 0x1
	// Position of FT23 field.
	EXTI_FTSR1_FT23_Pos = 0x17
	// Bit mask of FT23 field.
	EXTI_FTSR1_FT23_Msk = 0x800000
	// Bit FT23.
	EXTI_FTSR1_FT23 = 0x800000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT23_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT23_Enabled = 0x1
	// Position of FT24 field.
	EXTI_FTSR1_FT24_Pos = 0x18
	// Bit mask of FT24 field.
	EXTI_FTSR1_FT24_Msk = 0x1000000
	// Bit FT24.
	EXTI_FTSR1_FT24 = 0x1000000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT24_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT24_Enabled = 0x1
	// Position of FT25 field.
	EXTI_FTSR1_FT25_Pos = 0x19
	// Bit mask of FT25 field.
	EXTI_FTSR1_FT25_Msk = 0x2000000
	// Bit FT25.
	EXTI_FTSR1_FT25 = 0x2000000
	// Falling edge trigger is disabled
	EXTI_FTSR1_FT25_Disabled = 0x0
	// Falling edge trigger is enabled
	EXTI_FTSR1_FT25_Enabled = 0x1

	// SWIER1: EXTI software interrupt event register
	// Position of SWI0 field.
	EXTI_SWIER1_SWI0_Pos = 0x0
	// Bit mask of SWI0 field.
	EXTI_SWIER1_SWI0_Msk = 0x1
	// Bit SWI0.
	EXTI_SWIER1_SWI0 = 0x1
	// Generates an interrupt request
	EXTI_SWIER1_SWI0_Pend = 0x1
	// Position of SWI1 field.
	EXTI_SWIER1_SWI1_Pos = 0x1
	// Bit mask of SWI1 field.
	EXTI_SWIER1_SWI1_Msk = 0x2
	// Bit SWI1.
	EXTI_SWIER1_SWI1 = 0x2
	// Generates an interrupt request
	EXTI_SWIER1_SWI1_Pend = 0x1
	// Position of SWI2 field.
	EXTI_SWIER1_SWI2_Pos = 0x2
	// Bit mask of SWI2 field.
	EXTI_SWIER1_SWI2_Msk = 0x4
	// Bit SWI2.
	EXTI_SWIER1_SWI2 = 0x4
	// Generates an interrupt request
	EXTI_SWIER1_SWI2_Pend = 0x1
	// Position of SWI3 field.
	EXTI_SWIER1_SWI3_Pos = 0x3
	// Bit mask of SWI3 field.
	EXTI_SWIER1_SWI3_Msk = 0x8
	// Bit SWI3.
	EXTI_SWIER1_SWI3 = 0x8
	// Generates an interrupt request
	EXTI_SWIER1_SWI3_Pend = 0x1
	// Position of SWI4 field.
	EXTI_SWIER1_SWI4_Pos = 0x4
	// Bit mask of SWI4 field.
	EXTI_SWIER1_SWI4_Msk = 0x10
	// Bit SWI4.
	EXTI_SWIER1_SWI4 = 0x10
	// Generates an interrupt request
	EXTI_SWIER1_SWI4_Pend = 0x1
	// Position of SWI5 field.
	EXTI_SWIER1_SWI5_Pos = 0x5
	// Bit mask of SWI5 field.
	EXTI_SWIER1_SWI5_Msk = 0x20
	// Bit SWI5.
	EXTI_SWIER1_SWI5 = 0x20
	// Generates an interrupt request
	EXTI_SWIER1_SWI5_Pend = 0x1
	// Position of SWI6 field.
	EXTI_SWIER1_SWI6_Pos = 0x6
	// Bit mask of SWI6 field.
	EXTI_SWIER1_SWI6_Msk = 0x40
	// Bit SWI6.
	EXTI_SWIER1_SWI6 = 0x40
	// Generates an interrupt request
	EXTI_SWIER1_SWI6_Pend = 0x1
	// Position of SWI7 field.
	EXTI_SWIER1_SWI7_Pos = 0x7
	// Bit mask of SWI7 field.
	EXTI_SWIER1_SWI7_Msk = 0x80
	// Bit SWI7.
	EXTI_SWIER1_SWI7 = 0x80
	// Generates an interrupt request
	EXTI_SWIER1_SWI7_Pend = 0x1
	// Position of SWI8 field.
	EXTI_SWIER1_SWI8_Pos = 0x8
	// Bit mask of SWI8 field.
	EXTI_SWIER1_SWI8_Msk = 0x100
	// Bit SWI8.
	EXTI_SWIER1_SWI8 = 0x100
	// Generates an interrupt request
	EXTI_SWIER1_SWI8_Pend = 0x1
	// Position of SWI9 field.
	EXTI_SWIER1_SWI9_Pos = 0x9
	// Bit mask of SWI9 field.
	EXTI_SWIER1_SWI9_Msk = 0x200
	// Bit SWI9.
	EXTI_SWIER1_SWI9 = 0x200
	// Generates an interrupt request
	EXTI_SWIER1_SWI9_Pend = 0x1
	// Position of SWI10 field.
	EXTI_SWIER1_SWI10_Pos = 0xa
	// Bit mask of SWI10 field.
	EXTI_SWIER1_SWI10_Msk = 0x400
	// Bit SWI10.
	EXTI_SWIER1_SWI10 = 0x400
	// Generates an interrupt request
	EXTI_SWIER1_SWI10_Pend = 0x1
	// Position of SWI11 field.
	EXTI_SWIER1_SWI11_Pos = 0xb
	// Bit mask of SWI11 field.
	EXTI_SWIER1_SWI11_Msk = 0x800
	// Bit SWI11.
	EXTI_SWIER1_SWI11 = 0x800
	// Generates an interrupt request
	EXTI_SWIER1_SWI11_Pend = 0x1
	// Position of SWI12 field.
	EXTI_SWIER1_SWI12_Pos = 0xc
	// Bit mask of SWI12 field.
	EXTI_SWIER1_SWI12_Msk = 0x1000
	// Bit SWI12.
	EXTI_SWIER1_SWI12 = 0x1000
	// Generates an interrupt request
	EXTI_SWIER1_SWI12_Pend = 0x1
	// Position of SWI13 field.
	EXTI_SWIER1_SWI13_Pos = 0xd
	// Bit mask of SWI13 field.
	EXTI_SWIER1_SWI13_Msk = 0x2000
	// Bit SWI13.
	EXTI_SWIER1_SWI13 = 0x2000
	// Generates an interrupt request
	EXTI_SWIER1_SWI13_Pend = 0x1
	// Position of SWI14 field.
	EXTI_SWIER1_SWI14_Pos = 0xe
	// Bit mask of SWI14 field.
	EXTI_SWIER1_SWI14_Msk = 0x4000
	// Bit SWI14.
	EXTI_SWIER1_SWI14 = 0x4000
	// Generates an interrupt request
	EXTI_SWIER1_SWI14_Pend = 0x1
	// Position of SWI15 field.
	EXTI_SWIER1_SWI15_Pos = 0xf
	// Bit mask of SWI15 field.
	EXTI_SWIER1_SWI15_Msk = 0x8000
	// Bit SWI15.
	EXTI_SWIER1_SWI15 = 0x8000
	// Generates an interrupt request
	EXTI_SWIER1_SWI15_Pend = 0x1
	// Position of SWI16 field.
	EXTI_SWIER1_SWI16_Pos = 0x10
	// Bit mask of SWI16 field.
	EXTI_SWIER1_SWI16_Msk = 0x10000
	// Bit SWI16.
	EXTI_SWIER1_SWI16 = 0x10000
	// Generates an interrupt request
	EXTI_SWIER1_SWI16_Pend = 0x1
	// Position of SWI17 field.
	EXTI_SWIER1_SWI17_Pos = 0x11
	// Bit mask of SWI17 field.
	EXTI_SWIER1_SWI17_Msk = 0x20000
	// Bit SWI17.
	EXTI_SWIER1_SWI17 = 0x20000
	// Generates an interrupt request
	EXTI_SWIER1_SWI17_Pend = 0x1
	// Position of SWI18 field.
	EXTI_SWIER1_SWI18_Pos = 0x12
	// Bit mask of SWI18 field.
	EXTI_SWIER1_SWI18_Msk = 0x40000
	// Bit SWI18.
	EXTI_SWIER1_SWI18 = 0x40000
	// Generates an interrupt request
	EXTI_SWIER1_SWI18_Pend = 0x1
	// Position of SWI19 field.
	EXTI_SWIER1_SWI19_Pos = 0x13
	// Bit mask of SWI19 field.
	EXTI_SWIER1_SWI19_Msk = 0x80000
	// Bit SWI19.
	EXTI_SWIER1_SWI19 = 0x80000
	// Generates an interrupt request
	EXTI_SWIER1_SWI19_Pend = 0x1
	// Position of SWI20 field.
	EXTI_SWIER1_SWI20_Pos = 0x14
	// Bit mask of SWI20 field.
	EXTI_SWIER1_SWI20_Msk = 0x100000
	// Bit SWI20.
	EXTI_SWIER1_SWI20 = 0x100000
	// Generates an interrupt request
	EXTI_SWIER1_SWI20_Pend = 0x1
	// Position of SWI21 field.
	EXTI_SWIER1_SWI21_Pos = 0x15
	// Bit mask of SWI21 field.
	EXTI_SWIER1_SWI21_Msk = 0x200000
	// Bit SWI21.
	EXTI_SWIER1_SWI21 = 0x200000
	// Generates an interrupt request
	EXTI_SWIER1_SWI21_Pend = 0x1
	// Position of SWI22 field.
	EXTI_SWIER1_SWI22_Pos = 0x16
	// Bit mask of SWI22 field.
	EXTI_SWIER1_SWI22_Msk = 0x400000
	// Bit SWI22.
	EXTI_SWIER1_SWI22 = 0x400000
	// Generates an interrupt request
	EXTI_SWIER1_SWI22_Pend = 0x1
	// Position of SWI23 field.
	EXTI_SWIER1_SWI23_Pos = 0x17
	// Bit mask of SWI23 field.
	EXTI_SWIER1_SWI23_Msk = 0x800000
	// Bit SWI23.
	EXTI_SWIER1_SWI23 = 0x800000
	// Generates an interrupt request
	EXTI_SWIER1_SWI23_Pend = 0x1
	// Position of SWI24 field.
	EXTI_SWIER1_SWI24_Pos = 0x18
	// Bit mask of SWI24 field.
	EXTI_SWIER1_SWI24_Msk = 0x1000000
	// Bit SWI24.
	EXTI_SWIER1_SWI24 = 0x1000000
	// Generates an interrupt request
	EXTI_SWIER1_SWI24_Pend = 0x1
	// Position of SWI25 field.
	EXTI_SWIER1_SWI25_Pos = 0x19
	// Bit mask of SWI25 field.
	EXTI_SWIER1_SWI25_Msk = 0x2000000
	// Bit SWI25.
	EXTI_SWIER1_SWI25 = 0x2000000
	// Generates an interrupt request
	EXTI_SWIER1_SWI25_Pend = 0x1

	// RPR1: EXTI rising edge pending register
	// Position of RPIF0 field.
	EXTI_RPR1_RPIF0_Pos = 0x0
	// Bit mask of RPIF0 field.
	EXTI_RPR1_RPIF0_Msk = 0x1
	// Bit RPIF0.
	EXTI_RPR1_RPIF0 = 0x1
	// No trigger request occurred
	EXTI_RPR1_RPIF0_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF0_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF0_Clear = 0x1
	// Position of RPIF1 field.
	EXTI_RPR1_RPIF1_Pos = 0x1
	// Bit mask of RPIF1 field.
	EXTI_RPR1_RPIF1_Msk = 0x2
	// Bit RPIF1.
	EXTI_RPR1_RPIF1 = 0x2
	// No trigger request occurred
	EXTI_RPR1_RPIF1_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF1_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF1_Clear = 0x1
	// Position of RPIF2 field.
	EXTI_RPR1_RPIF2_Pos = 0x2
	// Bit mask of RPIF2 field.
	EXTI_RPR1_RPIF2_Msk = 0x4
	// Bit RPIF2.
	EXTI_RPR1_RPIF2 = 0x4
	// No trigger request occurred
	EXTI_RPR1_RPIF2_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF2_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF2_Clear = 0x1
	// Position of RPIF3 field.
	EXTI_RPR1_RPIF3_Pos = 0x3
	// Bit mask of RPIF3 field.
	EXTI_RPR1_RPIF3_Msk = 0x8
	// Bit RPIF3.
	EXTI_RPR1_RPIF3 = 0x8
	// No trigger request occurred
	EXTI_RPR1_RPIF3_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF3_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF3_Clear = 0x1
	// Position of RPIF4 field.
	EXTI_RPR1_RPIF4_Pos = 0x4
	// Bit mask of RPIF4 field.
	EXTI_RPR1_RPIF4_Msk = 0x10
	// Bit RPIF4.
	EXTI_RPR1_RPIF4 = 0x10
	// No trigger request occurred
	EXTI_RPR1_RPIF4_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF4_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF4_Clear = 0x1
	// Position of RPIF5 field.
	EXTI_RPR1_RPIF5_Pos = 0x5
	// Bit mask of RPIF5 field.
	EXTI_RPR1_RPIF5_Msk = 0x20
	// Bit RPIF5.
	EXTI_RPR1_RPIF5 = 0x20
	// No trigger request occurred
	EXTI_RPR1_RPIF5_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF5_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF5_Clear = 0x1
	// Position of RPIF6 field.
	EXTI_RPR1_RPIF6_Pos = 0x6
	// Bit mask of RPIF6 field.
	EXTI_RPR1_RPIF6_Msk = 0x40
	// Bit RPIF6.
	EXTI_RPR1_RPIF6 = 0x40
	// No trigger request occurred
	EXTI_RPR1_RPIF6_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF6_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF6_Clear = 0x1
	// Position of RPIF7 field.
	EXTI_RPR1_RPIF7_Pos = 0x7
	// Bit mask of RPIF7 field.
	EXTI_RPR1_RPIF7_Msk = 0x80
	// Bit RPIF7.
	EXTI_RPR1_RPIF7 = 0x80
	// No trigger request occurred
	EXTI_RPR1_RPIF7_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF7_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF7_Clear = 0x1
	// Position of RPIF8 field.
	EXTI_RPR1_RPIF8_Pos = 0x8
	// Bit mask of RPIF8 field.
	EXTI_RPR1_RPIF8_Msk = 0x100
	// Bit RPIF8.
	EXTI_RPR1_RPIF8 = 0x100
	// No trigger request occurred
	EXTI_RPR1_RPIF8_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF8_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF8_Clear = 0x1
	// Position of RPIF9 field.
	EXTI_RPR1_RPIF9_Pos = 0x9
	// Bit mask of RPIF9 field.
	EXTI_RPR1_RPIF9_Msk = 0x200
	// Bit RPIF9.
	EXTI_RPR1_RPIF9 = 0x200
	// No trigger request occurred
	EXTI_RPR1_RPIF9_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF9_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF9_Clear = 0x1
	// Position of RPIF10 field.
	EXTI_RPR1_RPIF10_Pos = 0xa
	// Bit mask of RPIF10 field.
	EXTI_RPR1_RPIF10_Msk = 0x400
	// Bit RPIF10.
	EXTI_RPR1_RPIF10 = 0x400
	// No trigger request occurred
	EXTI_RPR1_RPIF10_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF10_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF10_Clear = 0x1
	// Position of RPIF11 field.
	EXTI_RPR1_RPIF11_Pos = 0xb
	// Bit mask of RPIF11 field.
	EXTI_RPR1_RPIF11_Msk = 0x800
	// Bit RPIF11.
	EXTI_RPR1_RPIF11 = 0x800
	// No trigger request occurred
	EXTI_RPR1_RPIF11_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF11_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF11_Clear = 0x1
	// Position of RPIF12 field.
	EXTI_RPR1_RPIF12_Pos = 0xc
	// Bit mask of RPIF12 field.
	EXTI_RPR1_RPIF12_Msk = 0x1000
	// Bit RPIF12.
	EXTI_RPR1_RPIF12 = 0x1000
	// No trigger request occurred
	EXTI_RPR1_RPIF12_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF12_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF12_Clear = 0x1
	// Position of RPIF13 field.
	EXTI_RPR1_RPIF13_Pos = 0xd
	// Bit mask of RPIF13 field.
	EXTI_RPR1_RPIF13_Msk = 0x2000
	// Bit RPIF13.
	EXTI_RPR1_RPIF13 = 0x2000
	// No trigger request occurred
	EXTI_RPR1_RPIF13_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF13_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF13_Clear = 0x1
	// Position of RPIF14 field.
	EXTI_RPR1_RPIF14_Pos = 0xe
	// Bit mask of RPIF14 field.
	EXTI_RPR1_RPIF14_Msk = 0x4000
	// Bit RPIF14.
	EXTI_RPR1_RPIF14 = 0x4000
	// No trigger request occurred
	EXTI_RPR1_RPIF14_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF14_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF14_Clear = 0x1
	// Position of RPIF15 field.
	EXTI_RPR1_RPIF15_Pos = 0xf
	// Bit mask of RPIF15 field.
	EXTI_RPR1_RPIF15_Msk = 0x8000
	// Bit RPIF15.
	EXTI_RPR1_RPIF15 = 0x8000
	// No trigger request occurred
	EXTI_RPR1_RPIF15_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF15_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF15_Clear = 0x1
	// Position of RPIF16 field.
	EXTI_RPR1_RPIF16_Pos = 0x10
	// Bit mask of RPIF16 field.
	EXTI_RPR1_RPIF16_Msk = 0x10000
	// Bit RPIF16.
	EXTI_RPR1_RPIF16 = 0x10000
	// No trigger request occurred
	EXTI_RPR1_RPIF16_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF16_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF16_Clear = 0x1
	// Position of RPIF17 field.
	EXTI_RPR1_RPIF17_Pos = 0x11
	// Bit mask of RPIF17 field.
	EXTI_RPR1_RPIF17_Msk = 0x20000
	// Bit RPIF17.
	EXTI_RPR1_RPIF17 = 0x20000
	// No trigger request occurred
	EXTI_RPR1_RPIF17_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF17_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF17_Clear = 0x1
	// Position of RPIF18 field.
	EXTI_RPR1_RPIF18_Pos = 0x12
	// Bit mask of RPIF18 field.
	EXTI_RPR1_RPIF18_Msk = 0x40000
	// Bit RPIF18.
	EXTI_RPR1_RPIF18 = 0x40000
	// No trigger request occurred
	EXTI_RPR1_RPIF18_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF18_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF18_Clear = 0x1
	// Position of RPIF19 field.
	EXTI_RPR1_RPIF19_Pos = 0x13
	// Bit mask of RPIF19 field.
	EXTI_RPR1_RPIF19_Msk = 0x80000
	// Bit RPIF19.
	EXTI_RPR1_RPIF19 = 0x80000
	// No trigger request occurred
	EXTI_RPR1_RPIF19_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF19_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF19_Clear = 0x1
	// Position of RPIF20 field.
	EXTI_RPR1_RPIF20_Pos = 0x14
	// Bit mask of RPIF20 field.
	EXTI_RPR1_RPIF20_Msk = 0x100000
	// Bit RPIF20.
	EXTI_RPR1_RPIF20 = 0x100000
	// No trigger request occurred
	EXTI_RPR1_RPIF20_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF20_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF20_Clear = 0x1
	// Position of RPIF21 field.
	EXTI_RPR1_RPIF21_Pos = 0x15
	// Bit mask of RPIF21 field.
	EXTI_RPR1_RPIF21_Msk = 0x200000
	// Bit RPIF21.
	EXTI_RPR1_RPIF21 = 0x200000
	// No trigger request occurred
	EXTI_RPR1_RPIF21_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF21_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF21_Clear = 0x1
	// Position of RPIF22 field.
	EXTI_RPR1_RPIF22_Pos = 0x16
	// Bit mask of RPIF22 field.
	EXTI_RPR1_RPIF22_Msk = 0x400000
	// Bit RPIF22.
	EXTI_RPR1_RPIF22 = 0x400000
	// No trigger request occurred
	EXTI_RPR1_RPIF22_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF22_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF22_Clear = 0x1
	// Position of RPIF23 field.
	EXTI_RPR1_RPIF23_Pos = 0x17
	// Bit mask of RPIF23 field.
	EXTI_RPR1_RPIF23_Msk = 0x800000
	// Bit RPIF23.
	EXTI_RPR1_RPIF23 = 0x800000
	// No trigger request occurred
	EXTI_RPR1_RPIF23_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF23_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF23_Clear = 0x1
	// Position of RPIF24 field.
	EXTI_RPR1_RPIF24_Pos = 0x18
	// Bit mask of RPIF24 field.
	EXTI_RPR1_RPIF24_Msk = 0x1000000
	// Bit RPIF24.
	EXTI_RPR1_RPIF24 = 0x1000000
	// No trigger request occurred
	EXTI_RPR1_RPIF24_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF24_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF24_Clear = 0x1
	// Position of RPIF25 field.
	EXTI_RPR1_RPIF25_Pos = 0x19
	// Bit mask of RPIF25 field.
	EXTI_RPR1_RPIF25_Msk = 0x2000000
	// Bit RPIF25.
	EXTI_RPR1_RPIF25 = 0x2000000
	// No trigger request occurred
	EXTI_RPR1_RPIF25_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_RPR1_RPIF25_Pending = 0x1
	// Clears pending bit
	EXTI_RPR1_RPIF25_Clear = 0x1

	// FPR1: EXTI falling edge pending register
	// Position of FPIF0 field.
	EXTI_FPR1_FPIF0_Pos = 0x0
	// Bit mask of FPIF0 field.
	EXTI_FPR1_FPIF0_Msk = 0x1
	// Bit FPIF0.
	EXTI_FPR1_FPIF0 = 0x1
	// No trigger request occurred
	EXTI_FPR1_FPIF0_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF0_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF0_Clear = 0x1
	// Position of FPIF1 field.
	EXTI_FPR1_FPIF1_Pos = 0x1
	// Bit mask of FPIF1 field.
	EXTI_FPR1_FPIF1_Msk = 0x2
	// Bit FPIF1.
	EXTI_FPR1_FPIF1 = 0x2
	// No trigger request occurred
	EXTI_FPR1_FPIF1_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF1_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF1_Clear = 0x1
	// Position of FPIF2 field.
	EXTI_FPR1_FPIF2_Pos = 0x2
	// Bit mask of FPIF2 field.
	EXTI_FPR1_FPIF2_Msk = 0x4
	// Bit FPIF2.
	EXTI_FPR1_FPIF2 = 0x4
	// No trigger request occurred
	EXTI_FPR1_FPIF2_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF2_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF2_Clear = 0x1
	// Position of FPIF3 field.
	EXTI_FPR1_FPIF3_Pos = 0x3
	// Bit mask of FPIF3 field.
	EXTI_FPR1_FPIF3_Msk = 0x8
	// Bit FPIF3.
	EXTI_FPR1_FPIF3 = 0x8
	// No trigger request occurred
	EXTI_FPR1_FPIF3_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF3_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF3_Clear = 0x1
	// Position of FPIF4 field.
	EXTI_FPR1_FPIF4_Pos = 0x4
	// Bit mask of FPIF4 field.
	EXTI_FPR1_FPIF4_Msk = 0x10
	// Bit FPIF4.
	EXTI_FPR1_FPIF4 = 0x10
	// No trigger request occurred
	EXTI_FPR1_FPIF4_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF4_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF4_Clear = 0x1
	// Position of FPIF5 field.
	EXTI_FPR1_FPIF5_Pos = 0x5
	// Bit mask of FPIF5 field.
	EXTI_FPR1_FPIF5_Msk = 0x20
	// Bit FPIF5.
	EXTI_FPR1_FPIF5 = 0x20
	// No trigger request occurred
	EXTI_FPR1_FPIF5_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF5_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF5_Clear = 0x1
	// Position of FPIF6 field.
	EXTI_FPR1_FPIF6_Pos = 0x6
	// Bit mask of FPIF6 field.
	EXTI_FPR1_FPIF6_Msk = 0x40
	// Bit FPIF6.
	EXTI_FPR1_FPIF6 = 0x40
	// No trigger request occurred
	EXTI_FPR1_FPIF6_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF6_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF6_Clear = 0x1
	// Position of FPIF7 field.
	EXTI_FPR1_FPIF7_Pos = 0x7
	// Bit mask of FPIF7 field.
	EXTI_FPR1_FPIF7_Msk = 0x80
	// Bit FPIF7.
	EXTI_FPR1_FPIF7 = 0x80
	// No trigger request occurred
	EXTI_FPR1_FPIF7_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF7_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF7_Clear = 0x1
	// Position of FPIF8 field.
	EXTI_FPR1_FPIF8_Pos = 0x8
	// Bit mask of FPIF8 field.
	EXTI_FPR1_FPIF8_Msk = 0x100
	// Bit FPIF8.
	EXTI_FPR1_FPIF8 = 0x100
	// No trigger request occurred
	EXTI_FPR1_FPIF8_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF8_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF8_Clear = 0x1
	// Position of FPIF9 field.
	EXTI_FPR1_FPIF9_Pos = 0x9
	// Bit mask of FPIF9 field.
	EXTI_FPR1_FPIF9_Msk = 0x200
	// Bit FPIF9.
	EXTI_FPR1_FPIF9 = 0x200
	// No trigger request occurred
	EXTI_FPR1_FPIF9_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF9_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF9_Clear = 0x1
	// Position of FPIF10 field.
	EXTI_FPR1_FPIF10_Pos = 0xa
	// Bit mask of FPIF10 field.
	EXTI_FPR1_FPIF10_Msk = 0x400
	// Bit FPIF10.
	EXTI_FPR1_FPIF10 = 0x400
	// No trigger request occurred
	EXTI_FPR1_FPIF10_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF10_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF10_Clear = 0x1
	// Position of FPIF11 field.
	EXTI_FPR1_FPIF11_Pos = 0xb
	// Bit mask of FPIF11 field.
	EXTI_FPR1_FPIF11_Msk = 0x800
	// Bit FPIF11.
	EXTI_FPR1_FPIF11 = 0x800
	// No trigger request occurred
	EXTI_FPR1_FPIF11_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF11_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF11_Clear = 0x1
	// Position of FPIF12 field.
	EXTI_FPR1_FPIF12_Pos = 0xc
	// Bit mask of FPIF12 field.
	EXTI_FPR1_FPIF12_Msk = 0x1000
	// Bit FPIF12.
	EXTI_FPR1_FPIF12 = 0x1000
	// No trigger request occurred
	EXTI_FPR1_FPIF12_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF12_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF12_Clear = 0x1
	// Position of FPIF13 field.
	EXTI_FPR1_FPIF13_Pos = 0xd
	// Bit mask of FPIF13 field.
	EXTI_FPR1_FPIF13_Msk = 0x2000
	// Bit FPIF13.
	EXTI_FPR1_FPIF13 = 0x2000
	// No trigger request occurred
	EXTI_FPR1_FPIF13_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF13_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF13_Clear = 0x1
	// Position of FPIF14 field.
	EXTI_FPR1_FPIF14_Pos = 0xe
	// Bit mask of FPIF14 field.
	EXTI_FPR1_FPIF14_Msk = 0x4000
	// Bit FPIF14.
	EXTI_FPR1_FPIF14 = 0x4000
	// No trigger request occurred
	EXTI_FPR1_FPIF14_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF14_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF14_Clear = 0x1
	// Position of FPIF15 field.
	EXTI_FPR1_FPIF15_Pos = 0xf
	// Bit mask of FPIF15 field.
	EXTI_FPR1_FPIF15_Msk = 0x8000
	// Bit FPIF15.
	EXTI_FPR1_FPIF15 = 0x8000
	// No trigger request occurred
	EXTI_FPR1_FPIF15_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF15_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF15_Clear = 0x1
	// Position of FPIF16 field.
	EXTI_FPR1_FPIF16_Pos = 0x10
	// Bit mask of FPIF16 field.
	EXTI_FPR1_FPIF16_Msk = 0x10000
	// Bit FPIF16.
	EXTI_FPR1_FPIF16 = 0x10000
	// No trigger request occurred
	EXTI_FPR1_FPIF16_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF16_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF16_Clear = 0x1
	// Position of FPIF17 field.
	EXTI_FPR1_FPIF17_Pos = 0x11
	// Bit mask of FPIF17 field.
	EXTI_FPR1_FPIF17_Msk = 0x20000
	// Bit FPIF17.
	EXTI_FPR1_FPIF17 = 0x20000
	// No trigger request occurred
	EXTI_FPR1_FPIF17_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF17_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF17_Clear = 0x1
	// Position of FPIF18 field.
	EXTI_FPR1_FPIF18_Pos = 0x12
	// Bit mask of FPIF18 field.
	EXTI_FPR1_FPIF18_Msk = 0x40000
	// Bit FPIF18.
	EXTI_FPR1_FPIF18 = 0x40000
	// No trigger request occurred
	EXTI_FPR1_FPIF18_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF18_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF18_Clear = 0x1
	// Position of FPIF19 field.
	EXTI_FPR1_FPIF19_Pos = 0x13
	// Bit mask of FPIF19 field.
	EXTI_FPR1_FPIF19_Msk = 0x80000
	// Bit FPIF19.
	EXTI_FPR1_FPIF19 = 0x80000
	// No trigger request occurred
	EXTI_FPR1_FPIF19_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF19_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF19_Clear = 0x1
	// Position of FPIF20 field.
	EXTI_FPR1_FPIF20_Pos = 0x14
	// Bit mask of FPIF20 field.
	EXTI_FPR1_FPIF20_Msk = 0x100000
	// Bit FPIF20.
	EXTI_FPR1_FPIF20 = 0x100000
	// No trigger request occurred
	EXTI_FPR1_FPIF20_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF20_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF20_Clear = 0x1
	// Position of FPIF21 field.
	EXTI_FPR1_FPIF21_Pos = 0x15
	// Bit mask of FPIF21 field.
	EXTI_FPR1_FPIF21_Msk = 0x200000
	// Bit FPIF21.
	EXTI_FPR1_FPIF21 = 0x200000
	// No trigger request occurred
	EXTI_FPR1_FPIF21_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF21_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF21_Clear = 0x1
	// Position of FPIF22 field.
	EXTI_FPR1_FPIF22_Pos = 0x16
	// Bit mask of FPIF22 field.
	EXTI_FPR1_FPIF22_Msk = 0x400000
	// Bit FPIF22.
	EXTI_FPR1_FPIF22 = 0x400000
	// No trigger request occurred
	EXTI_FPR1_FPIF22_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF22_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF22_Clear = 0x1
	// Position of FPIF23 field.
	EXTI_FPR1_FPIF23_Pos = 0x17
	// Bit mask of FPIF23 field.
	EXTI_FPR1_FPIF23_Msk = 0x800000
	// Bit FPIF23.
	EXTI_FPR1_FPIF23 = 0x800000
	// No trigger request occurred
	EXTI_FPR1_FPIF23_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF23_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF23_Clear = 0x1
	// Position of FPIF24 field.
	EXTI_FPR1_FPIF24_Pos = 0x18
	// Bit mask of FPIF24 field.
	EXTI_FPR1_FPIF24_Msk = 0x1000000
	// Bit FPIF24.
	EXTI_FPR1_FPIF24 = 0x1000000
	// No trigger request occurred
	EXTI_FPR1_FPIF24_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF24_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF24_Clear = 0x1
	// Position of FPIF25 field.
	EXTI_FPR1_FPIF25_Pos = 0x19
	// Bit mask of FPIF25 field.
	EXTI_FPR1_FPIF25_Msk = 0x2000000
	// Bit FPIF25.
	EXTI_FPR1_FPIF25 = 0x2000000
	// No trigger request occurred
	EXTI_FPR1_FPIF25_NotPending = 0x0
	// Selected trigger request occurred
	EXTI_FPR1_FPIF25_Pending = 0x1
	// Clears pending bit
	EXTI_FPR1_FPIF25_Clear = 0x1

	// SECCFGR1: EXTI security configuration register
	// Position of SEC0 field.
	EXTI_SECCFGR1_SEC0_Pos = 0x0
	// Bit mask of SEC0 field.
	EXTI_SECCFGR1_SEC0_Msk = 0x1
	// Bit SEC0.
	EXTI_SECCFGR1_SEC0 = 0x1
	// Position of SEC1 field.
	EXTI_SECCFGR1_SEC1_Pos = 0x1
	// Bit mask of SEC1 field.
	EXTI_SECCFGR1_SEC1_Msk = 0x2
	// Bit SEC1.
	EXTI_SECCFGR1_SEC1 = 0x2
	// Position of SEC2 field.
	EXTI_SECCFGR1_SEC2_Pos = 0x2
	// Bit mask of SEC2 field.
	EXTI_SECCFGR1_SEC2_Msk = 0x4
	// Bit SEC2.
	EXTI_SECCFGR1_SEC2 = 0x4
	// Position of SEC3 field.
	EXTI_SECCFGR1_SEC3_Pos = 0x3
	// Bit mask of SEC3 field.
	EXTI_SECCFGR1_SEC3_Msk = 0x8
	// Bit SEC3.
	EXTI_SECCFGR1_SEC3 = 0x8
	// Position of SEC4 field.
	EXTI_SECCFGR1_SEC4_Pos = 0x4
	// Bit mask of SEC4 field.
	EXTI_SECCFGR1_SEC4_Msk = 0x10
	// Bit SEC4.
	EXTI_SECCFGR1_SEC4 = 0x10
	// Position of SEC5 field.
	EXTI_SECCFGR1_SEC5_Pos = 0x5
	// Bit mask of SEC5 field.
	EXTI_SECCFGR1_SEC5_Msk = 0x20
	// Bit SEC5.
	EXTI_SECCFGR1_SEC5 = 0x20
	// Position of SEC6 field.
	EXTI_SECCFGR1_SEC6_Pos = 0x6
	// Bit mask of SEC6 field.
	EXTI_SECCFGR1_SEC6_Msk = 0x40
	// Bit SEC6.
	EXTI_SECCFGR1_SEC6 = 0x40
	// Position of SEC7 field.
	EXTI_SECCFGR1_SEC7_Pos = 0x7
	// Bit mask of SEC7 field.
	EXTI_SECCFGR1_SEC7_Msk = 0x80
	// Bit SEC7.
	EXTI_SECCFGR1_SEC7 = 0x80
	// Position of SEC8 field.
	EXTI_SECCFGR1_SEC8_Pos = 0x8
	// Bit mask of SEC8 field.
	EXTI_SECCFGR1_SEC8_Msk = 0x100
	// Bit SEC8.
	EXTI_SECCFGR1_SEC8 = 0x100
	// Position of SEC9 field.
	EXTI_SECCFGR1_SEC9_Pos = 0x9
	// Bit mask of SEC9 field.
	EXTI_SECCFGR1_SEC9_Msk = 0x200
	// Bit SEC9.
	EXTI_SECCFGR1_SEC9 = 0x200
	// Position of SEC10 field.
	EXTI_SECCFGR1_SEC10_Pos = 0xa
	// Bit mask of SEC10 field.
	EXTI_SECCFGR1_SEC10_Msk = 0x400
	// Bit SEC10.
	EXTI_SECCFGR1_SEC10 = 0x400
	// Position of SEC11 field.
	EXTI_SECCFGR1_SEC11_Pos = 0xb
	// Bit mask of SEC11 field.
	EXTI_SECCFGR1_SEC11_Msk = 0x800
	// Bit SEC11.
	EXTI_SECCFGR1_SEC11 = 0x800
	// Position of SEC12 field.
	EXTI_SECCFGR1_SEC12_Pos = 0xc
	// Bit mask of SEC12 field.
	EXTI_SECCFGR1_SEC12_Msk = 0x1000
	// Bit SEC12.
	EXTI_SECCFGR1_SEC12 = 0x1000
	// Position of SEC13 field.
	EXTI_SECCFGR1_SEC13_Pos = 0xd
	// Bit mask of SEC13 field.
	EXTI_SECCFGR1_SEC13_Msk = 0x2000
	// Bit SEC13.
	EXTI_SECCFGR1_SEC13 = 0x2000
	// Position of SEC14 field.
	EXTI_SECCFGR1_SEC14_Pos = 0xe
	// Bit mask of SEC14 field.
	EXTI_SECCFGR1_SEC14_Msk = 0x4000
	// Bit SEC14.
	EXTI_SECCFGR1_SEC14 = 0x4000
	// Position of SEC15 field.
	EXTI_SECCFGR1_SEC15_Pos = 0xf
	// Bit mask of SEC15 field.
	EXTI_SECCFGR1_SEC15_Msk = 0x8000
	// Bit SEC15.
	EXTI_SECCFGR1_SEC15 = 0x8000
	// Position of SEC16 field.
	EXTI_SECCFGR1_SEC16_Pos = 0x10
	// Bit mask of SEC16 field.
	EXTI_SECCFGR1_SEC16_Msk = 0x10000
	// Bit SEC16.
	EXTI_SECCFGR1_SEC16 = 0x10000
	// Position of SEC17 field.
	EXTI_SECCFGR1_SEC17_Pos = 0x11
	// Bit mask of SEC17 field.
	EXTI_SECCFGR1_SEC17_Msk = 0x20000
	// Bit SEC17.
	EXTI_SECCFGR1_SEC17 = 0x20000
	// Position of SEC18 field.
	EXTI_SECCFGR1_SEC18_Pos = 0x12
	// Bit mask of SEC18 field.
	EXTI_SECCFGR1_SEC18_Msk = 0x40000
	// Bit SEC18.
	EXTI_SECCFGR1_SEC18 = 0x40000
	// Position of SEC19 field.
	EXTI_SECCFGR1_SEC19_Pos = 0x13
	// Bit mask of SEC19 field.
	EXTI_SECCFGR1_SEC19_Msk = 0x80000
	// Bit SEC19.
	EXTI_SECCFGR1_SEC19 = 0x80000
	// Position of SEC20 field.
	EXTI_SECCFGR1_SEC20_Pos = 0x14
	// Bit mask of SEC20 field.
	EXTI_SECCFGR1_SEC20_Msk = 0x100000
	// Bit SEC20.
	EXTI_SECCFGR1_SEC20 = 0x100000
	// Position of SEC21 field.
	EXTI_SECCFGR1_SEC21_Pos = 0x15
	// Bit mask of SEC21 field.
	EXTI_SECCFGR1_SEC21_Msk = 0x200000
	// Bit SEC21.
	EXTI_SECCFGR1_SEC21 = 0x200000
	// Position of SEC22 field.
	EXTI_SECCFGR1_SEC22_Pos = 0x16
	// Bit mask of SEC22 field.
	EXTI_SECCFGR1_SEC22_Msk = 0x400000
	// Bit SEC22.
	EXTI_SECCFGR1_SEC22 = 0x400000
	// Position of SEC23 field.
	EXTI_SECCFGR1_SEC23_Pos = 0x17
	// Bit mask of SEC23 field.
	EXTI_SECCFGR1_SEC23_Msk = 0x800000
	// Bit SEC23.
	EXTI_SECCFGR1_SEC23 = 0x800000
	// Position of SEC24 field.
	EXTI_SECCFGR1_SEC24_Pos = 0x18
	// Bit mask of SEC24 field.
	EXTI_SECCFGR1_SEC24_Msk = 0x1000000
	// Bit SEC24.
	EXTI_SECCFGR1_SEC24 = 0x1000000
	// Position of SEC25 field.
	EXTI_SECCFGR1_SEC25_Pos = 0x19
	// Bit mask of SEC25 field.
	EXTI_SECCFGR1_SEC25_Msk = 0x2000000
	// Bit SEC25.
	EXTI_SECCFGR1_SEC25 = 0x2000000

	// PRIVCFGR1: EXTI privilege configuration register
	// Position of PRIV0 field.
	EXTI_PRIVCFGR1_PRIV0_Pos = 0x0
	// Bit mask of PRIV0 field.
	EXTI_PRIVCFGR1_PRIV0_Msk = 0x1
	// Bit PRIV0.
	EXTI_PRIVCFGR1_PRIV0 = 0x1
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV0_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV0_Privileged = 0x1
	// Position of PRIV1 field.
	EXTI_PRIVCFGR1_PRIV1_Pos = 0x1
	// Bit mask of PRIV1 field.
	EXTI_PRIVCFGR1_PRIV1_Msk = 0x2
	// Bit PRIV1.
	EXTI_PRIVCFGR1_PRIV1 = 0x2
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV1_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV1_Privileged = 0x1
	// Position of PRIV2 field.
	EXTI_PRIVCFGR1_PRIV2_Pos = 0x2
	// Bit mask of PRIV2 field.
	EXTI_PRIVCFGR1_PRIV2_Msk = 0x4
	// Bit PRIV2.
	EXTI_PRIVCFGR1_PRIV2 = 0x4
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV2_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV2_Privileged = 0x1
	// Position of PRIV3 field.
	EXTI_PRIVCFGR1_PRIV3_Pos = 0x3
	// Bit mask of PRIV3 field.
	EXTI_PRIVCFGR1_PRIV3_Msk = 0x8
	// Bit PRIV3.
	EXTI_PRIVCFGR1_PRIV3 = 0x8
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV3_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV3_Privileged = 0x1
	// Position of PRIV4 field.
	EXTI_PRIVCFGR1_PRIV4_Pos = 0x4
	// Bit mask of PRIV4 field.
	EXTI_PRIVCFGR1_PRIV4_Msk = 0x10
	// Bit PRIV4.
	EXTI_PRIVCFGR1_PRIV4 = 0x10
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV4_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV4_Privileged = 0x1
	// Position of PRIV5 field.
	EXTI_PRIVCFGR1_PRIV5_Pos = 0x5
	// Bit mask of PRIV5 field.
	EXTI_PRIVCFGR1_PRIV5_Msk = 0x20
	// Bit PRIV5.
	EXTI_PRIVCFGR1_PRIV5 = 0x20
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV5_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV5_Privileged = 0x1
	// Position of PRIV6 field.
	EXTI_PRIVCFGR1_PRIV6_Pos = 0x6
	// Bit mask of PRIV6 field.
	EXTI_PRIVCFGR1_PRIV6_Msk = 0x40
	// Bit PRIV6.
	EXTI_PRIVCFGR1_PRIV6 = 0x40
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV6_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV6_Privileged = 0x1
	// Position of PRIV7 field.
	EXTI_PRIVCFGR1_PRIV7_Pos = 0x7
	// Bit mask of PRIV7 field.
	EXTI_PRIVCFGR1_PRIV7_Msk = 0x80
	// Bit PRIV7.
	EXTI_PRIVCFGR1_PRIV7 = 0x80
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV7_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV7_Privileged = 0x1
	// Position of PRIV8 field.
	EXTI_PRIVCFGR1_PRIV8_Pos = 0x8
	// Bit mask of PRIV8 field.
	EXTI_PRIVCFGR1_PRIV8_Msk = 0x100
	// Bit PRIV8.
	EXTI_PRIVCFGR1_PRIV8 = 0x100
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV8_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV8_Privileged = 0x1
	// Position of PRIV9 field.
	EXTI_PRIVCFGR1_PRIV9_Pos = 0x9
	// Bit mask of PRIV9 field.
	EXTI_PRIVCFGR1_PRIV9_Msk = 0x200
	// Bit PRIV9.
	EXTI_PRIVCFGR1_PRIV9 = 0x200
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV9_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV9_Privileged = 0x1
	// Position of PRIV10 field.
	EXTI_PRIVCFGR1_PRIV10_Pos = 0xa
	// Bit mask of PRIV10 field.
	EXTI_PRIVCFGR1_PRIV10_Msk = 0x400
	// Bit PRIV10.
	EXTI_PRIVCFGR1_PRIV10 = 0x400
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV10_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV10_Privileged = 0x1
	// Position of PRIV11 field.
	EXTI_PRIVCFGR1_PRIV11_Pos = 0xb
	// Bit mask of PRIV11 field.
	EXTI_PRIVCFGR1_PRIV11_Msk = 0x800
	// Bit PRIV11.
	EXTI_PRIVCFGR1_PRIV11 = 0x800
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV11_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV11_Privileged = 0x1
	// Position of PRIV12 field.
	EXTI_PRIVCFGR1_PRIV12_Pos = 0xc
	// Bit mask of PRIV12 field.
	EXTI_PRIVCFGR1_PRIV12_Msk = 0x1000
	// Bit PRIV12.
	EXTI_PRIVCFGR1_PRIV12 = 0x1000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV12_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV12_Privileged = 0x1
	// Position of PRIV13 field.
	EXTI_PRIVCFGR1_PRIV13_Pos = 0xd
	// Bit mask of PRIV13 field.
	EXTI_PRIVCFGR1_PRIV13_Msk = 0x2000
	// Bit PRIV13.
	EXTI_PRIVCFGR1_PRIV13 = 0x2000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV13_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV13_Privileged = 0x1
	// Position of PRIV14 field.
	EXTI_PRIVCFGR1_PRIV14_Pos = 0xe
	// Bit mask of PRIV14 field.
	EXTI_PRIVCFGR1_PRIV14_Msk = 0x4000
	// Bit PRIV14.
	EXTI_PRIVCFGR1_PRIV14 = 0x4000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV14_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV14_Privileged = 0x1
	// Position of PRIV15 field.
	EXTI_PRIVCFGR1_PRIV15_Pos = 0xf
	// Bit mask of PRIV15 field.
	EXTI_PRIVCFGR1_PRIV15_Msk = 0x8000
	// Bit PRIV15.
	EXTI_PRIVCFGR1_PRIV15 = 0x8000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV15_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV15_Privileged = 0x1
	// Position of PRIV16 field.
	EXTI_PRIVCFGR1_PRIV16_Pos = 0x10
	// Bit mask of PRIV16 field.
	EXTI_PRIVCFGR1_PRIV16_Msk = 0x10000
	// Bit PRIV16.
	EXTI_PRIVCFGR1_PRIV16 = 0x10000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV16_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV16_Privileged = 0x1
	// Position of PRIV17 field.
	EXTI_PRIVCFGR1_PRIV17_Pos = 0x11
	// Bit mask of PRIV17 field.
	EXTI_PRIVCFGR1_PRIV17_Msk = 0x20000
	// Bit PRIV17.
	EXTI_PRIVCFGR1_PRIV17 = 0x20000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV17_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV17_Privileged = 0x1
	// Position of PRIV18 field.
	EXTI_PRIVCFGR1_PRIV18_Pos = 0x12
	// Bit mask of PRIV18 field.
	EXTI_PRIVCFGR1_PRIV18_Msk = 0x40000
	// Bit PRIV18.
	EXTI_PRIVCFGR1_PRIV18 = 0x40000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV18_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV18_Privileged = 0x1
	// Position of PRIV19 field.
	EXTI_PRIVCFGR1_PRIV19_Pos = 0x13
	// Bit mask of PRIV19 field.
	EXTI_PRIVCFGR1_PRIV19_Msk = 0x80000
	// Bit PRIV19.
	EXTI_PRIVCFGR1_PRIV19 = 0x80000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV19_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV19_Privileged = 0x1
	// Position of PRIV20 field.
	EXTI_PRIVCFGR1_PRIV20_Pos = 0x14
	// Bit mask of PRIV20 field.
	EXTI_PRIVCFGR1_PRIV20_Msk = 0x100000
	// Bit PRIV20.
	EXTI_PRIVCFGR1_PRIV20 = 0x100000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV20_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV20_Privileged = 0x1
	// Position of PRIV21 field.
	EXTI_PRIVCFGR1_PRIV21_Pos = 0x15
	// Bit mask of PRIV21 field.
	EXTI_PRIVCFGR1_PRIV21_Msk = 0x200000
	// Bit PRIV21.
	EXTI_PRIVCFGR1_PRIV21 = 0x200000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV21_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV21_Privileged = 0x1
	// Position of PRIV22 field.
	EXTI_PRIVCFGR1_PRIV22_Pos = 0x16
	// Bit mask of PRIV22 field.
	EXTI_PRIVCFGR1_PRIV22_Msk = 0x400000
	// Bit PRIV22.
	EXTI_PRIVCFGR1_PRIV22 = 0x400000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV22_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV22_Privileged = 0x1
	// Position of PRIV23 field.
	EXTI_PRIVCFGR1_PRIV23_Pos = 0x17
	// Bit mask of PRIV23 field.
	EXTI_PRIVCFGR1_PRIV23_Msk = 0x800000
	// Bit PRIV23.
	EXTI_PRIVCFGR1_PRIV23 = 0x800000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV23_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV23_Privileged = 0x1
	// Position of PRIV24 field.
	EXTI_PRIVCFGR1_PRIV24_Pos = 0x18
	// Bit mask of PRIV24 field.
	EXTI_PRIVCFGR1_PRIV24_Msk = 0x1000000
	// Bit PRIV24.
	EXTI_PRIVCFGR1_PRIV24 = 0x1000000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV24_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV24_Privileged = 0x1
	// Position of PRIV25 field.
	EXTI_PRIVCFGR1_PRIV25_Pos = 0x19
	// Bit mask of PRIV25 field.
	EXTI_PRIVCFGR1_PRIV25_Msk = 0x2000000
	// Bit PRIV25.
	EXTI_PRIVCFGR1_PRIV25 = 0x2000000
	// Event privilege disabled
	EXTI_PRIVCFGR1_PRIV25_Unprivileged = 0x0
	// Event privilege enabled
	EXTI_PRIVCFGR1_PRIV25_Privileged = 0x1

	// EXTICR1: EXTI external interrupt selection register
	// Position of EXTI0 field.
	EXTI_EXTICR1_EXTI0_Pos = 0x0
	// Bit mask of EXTI0 field.
	EXTI_EXTICR1_EXTI0_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI0_PJ = 0x9
	// Position of EXTI1 field.
	EXTI_EXTICR1_EXTI1_Pos = 0x8
	// Bit mask of EXTI1 field.
	EXTI_EXTICR1_EXTI1_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI1_PJ = 0x9
	// Position of EXTI2 field.
	EXTI_EXTICR1_EXTI2_Pos = 0x10
	// Bit mask of EXTI2 field.
	EXTI_EXTICR1_EXTI2_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI2_PJ = 0x9
	// Position of EXTI3 field.
	EXTI_EXTICR1_EXTI3_Pos = 0x18
	// Bit mask of EXTI3 field.
	EXTI_EXTICR1_EXTI3_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR1_EXTI3_PJ = 0x9

	// EXTICR2: EXTI external interrupt selection register
	// Position of EXTI4 field.
	EXTI_EXTICR2_EXTI4_Pos = 0x0
	// Bit mask of EXTI4 field.
	EXTI_EXTICR2_EXTI4_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI4_PJ = 0x9
	// Position of EXTI5 field.
	EXTI_EXTICR2_EXTI5_Pos = 0x8
	// Bit mask of EXTI5 field.
	EXTI_EXTICR2_EXTI5_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI5_PJ = 0x9
	// Position of EXTI6 field.
	EXTI_EXTICR2_EXTI6_Pos = 0x10
	// Bit mask of EXTI6 field.
	EXTI_EXTICR2_EXTI6_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI6_PJ = 0x9
	// Position of EXTI7 field.
	EXTI_EXTICR2_EXTI7_Pos = 0x18
	// Bit mask of EXTI7 field.
	EXTI_EXTICR2_EXTI7_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR2_EXTI7_PJ = 0x9

	// EXTICR3: EXTI external interrupt selection register
	// Position of EXTI8 field.
	EXTI_EXTICR3_EXTI8_Pos = 0x0
	// Bit mask of EXTI8 field.
	EXTI_EXTICR3_EXTI8_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI8_PJ = 0x9
	// Position of EXTI9 field.
	EXTI_EXTICR3_EXTI9_Pos = 0x8
	// Bit mask of EXTI9 field.
	EXTI_EXTICR3_EXTI9_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI9_PJ = 0x9
	// Position of EXTI10 field.
	EXTI_EXTICR3_EXTI10_Pos = 0x10
	// Bit mask of EXTI10 field.
	EXTI_EXTICR3_EXTI10_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI10_PJ = 0x9
	// Position of EXTI11 field.
	EXTI_EXTICR3_EXTI11_Pos = 0x18
	// Bit mask of EXTI11 field.
	EXTI_EXTICR3_EXTI11_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR3_EXTI11_PJ = 0x9

	// EXTICR4: EXTI external interrupt selection register
	// Position of EXTI12 field.
	EXTI_EXTICR4_EXTI12_Pos = 0x0
	// Bit mask of EXTI12 field.
	EXTI_EXTICR4_EXTI12_Msk = 0xff
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI12_PJ = 0x9
	// Position of EXTI13 field.
	EXTI_EXTICR4_EXTI13_Pos = 0x8
	// Bit mask of EXTI13 field.
	EXTI_EXTICR4_EXTI13_Msk = 0xff00
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI13_PJ = 0x9
	// Position of EXTI14 field.
	EXTI_EXTICR4_EXTI14_Pos = 0x10
	// Bit mask of EXTI14 field.
	EXTI_EXTICR4_EXTI14_Msk = 0xff0000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI14_PJ = 0x9
	// Position of EXTI15 field.
	EXTI_EXTICR4_EXTI15_Pos = 0x18
	// Bit mask of EXTI15 field.
	EXTI_EXTICR4_EXTI15_Msk = 0xff000000
	// Select PAx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PA = 0x0
	// Select PBx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PB = 0x1
	// Select PCx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PC = 0x2
	// Select PDx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PD = 0x3
	// Select PEx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PE = 0x4
	// Select PFx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PF = 0x5
	// Select PGx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PG = 0x6
	// Select PHx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PH = 0x7
	// Select PIx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PI = 0x8
	// Select PJx as the source input for the EXTIx external interrupt
	EXTI_EXTICR4_EXTI15_PJ = 0x9

	// LOCKR: EXTI lock register
	// Position of LOCK field.
	EXTI_LOCKR_LOCK_Pos = 0x0
	// Bit mask of LOCK field.
	EXTI_LOCKR_LOCK_Msk = 0x1
	// Bit LOCK.
	EXTI_LOCKR_LOCK = 0x1

	// IMR1: EXTI CPU wake-up with interrupt mask register
	// Position of IM0 field.
	EXTI_IMR1_IM0_Pos = 0x0
	// Bit mask of IM0 field.
	EXTI_IMR1_IM0_Msk = 0x1
	// Bit IM0.
	EXTI_IMR1_IM0 = 0x1
	// Interrupt request line is masked
	EXTI_IMR1_IM0_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM0_Unmasked = 0x1
	// Position of IM1 field.
	EXTI_IMR1_IM1_Pos = 0x1
	// Bit mask of IM1 field.
	EXTI_IMR1_IM1_Msk = 0x2
	// Bit IM1.
	EXTI_IMR1_IM1 = 0x2
	// Interrupt request line is masked
	EXTI_IMR1_IM1_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM1_Unmasked = 0x1
	// Position of IM2 field.
	EXTI_IMR1_IM2_Pos = 0x2
	// Bit mask of IM2 field.
	EXTI_IMR1_IM2_Msk = 0x4
	// Bit IM2.
	EXTI_IMR1_IM2 = 0x4
	// Interrupt request line is masked
	EXTI_IMR1_IM2_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM2_Unmasked = 0x1
	// Position of IM3 field.
	EXTI_IMR1_IM3_Pos = 0x3
	// Bit mask of IM3 field.
	EXTI_IMR1_IM3_Msk = 0x8
	// Bit IM3.
	EXTI_IMR1_IM3 = 0x8
	// Interrupt request line is masked
	EXTI_IMR1_IM3_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM3_Unmasked = 0x1
	// Position of IM4 field.
	EXTI_IMR1_IM4_Pos = 0x4
	// Bit mask of IM4 field.
	EXTI_IMR1_IM4_Msk = 0x10
	// Bit IM4.
	EXTI_IMR1_IM4 = 0x10
	// Interrupt request line is masked
	EXTI_IMR1_IM4_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM4_Unmasked = 0x1
	// Position of IM5 field.
	EXTI_IMR1_IM5_Pos = 0x5
	// Bit mask of IM5 field.
	EXTI_IMR1_IM5_Msk = 0x20
	// Bit IM5.
	EXTI_IMR1_IM5 = 0x20
	// Interrupt request line is masked
	EXTI_IMR1_IM5_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM5_Unmasked = 0x1
	// Position of IM6 field.
	EXTI_IMR1_IM6_Pos = 0x6
	// Bit mask of IM6 field.
	EXTI_IMR1_IM6_Msk = 0x40
	// Bit IM6.
	EXTI_IMR1_IM6 = 0x40
	// Interrupt request line is masked
	EXTI_IMR1_IM6_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM6_Unmasked = 0x1
	// Position of IM7 field.
	EXTI_IMR1_IM7_Pos = 0x7
	// Bit mask of IM7 field.
	EXTI_IMR1_IM7_Msk = 0x80
	// Bit IM7.
	EXTI_IMR1_IM7 = 0x80
	// Interrupt request line is masked
	EXTI_IMR1_IM7_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM7_Unmasked = 0x1
	// Position of IM8 field.
	EXTI_IMR1_IM8_Pos = 0x8
	// Bit mask of IM8 field.
	EXTI_IMR1_IM8_Msk = 0x100
	// Bit IM8.
	EXTI_IMR1_IM8 = 0x100
	// Interrupt request line is masked
	EXTI_IMR1_IM8_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM8_Unmasked = 0x1
	// Position of IM9 field.
	EXTI_IMR1_IM9_Pos = 0x9
	// Bit mask of IM9 field.
	EXTI_IMR1_IM9_Msk = 0x200
	// Bit IM9.
	EXTI_IMR1_IM9 = 0x200
	// Interrupt request line is masked
	EXTI_IMR1_IM9_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM9_Unmasked = 0x1
	// Position of IM10 field.
	EXTI_IMR1_IM10_Pos = 0xa
	// Bit mask of IM10 field.
	EXTI_IMR1_IM10_Msk = 0x400
	// Bit IM10.
	EXTI_IMR1_IM10 = 0x400
	// Interrupt request line is masked
	EXTI_IMR1_IM10_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM10_Unmasked = 0x1
	// Position of IM11 field.
	EXTI_IMR1_IM11_Pos = 0xb
	// Bit mask of IM11 field.
	EXTI_IMR1_IM11_Msk = 0x800
	// Bit IM11.
	EXTI_IMR1_IM11 = 0x800
	// Interrupt request line is masked
	EXTI_IMR1_IM11_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM11_Unmasked = 0x1
	// Position of IM12 field.
	EXTI_IMR1_IM12_Pos = 0xc
	// Bit mask of IM12 field.
	EXTI_IMR1_IM12_Msk = 0x1000
	// Bit IM12.
	EXTI_IMR1_IM12 = 0x1000
	// Interrupt request line is masked
	EXTI_IMR1_IM12_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM12_Unmasked = 0x1
	// Position of IM13 field.
	EXTI_IMR1_IM13_Pos = 0xd
	// Bit mask of IM13 field.
	EXTI_IMR1_IM13_Msk = 0x2000
	// Bit IM13.
	EXTI_IMR1_IM13 = 0x2000
	// Interrupt request line is masked
	EXTI_IMR1_IM13_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM13_Unmasked = 0x1
	// Position of IM14 field.
	EXTI_IMR1_IM14_Pos = 0xe
	// Bit mask of IM14 field.
	EXTI_IMR1_IM14_Msk = 0x4000
	// Bit IM14.
	EXTI_IMR1_IM14 = 0x4000
	// Interrupt request line is masked
	EXTI_IMR1_IM14_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM14_Unmasked = 0x1
	// Position of IM15 field.
	EXTI_IMR1_IM15_Pos = 0xf
	// Bit mask of IM15 field.
	EXTI_IMR1_IM15_Msk = 0x8000
	// Bit IM15.
	EXTI_IMR1_IM15 = 0x8000
	// Interrupt request line is masked
	EXTI_IMR1_IM15_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM15_Unmasked = 0x1
	// Position of IM16 field.
	EXTI_IMR1_IM16_Pos = 0x10
	// Bit mask of IM16 field.
	EXTI_IMR1_IM16_Msk = 0x10000
	// Bit IM16.
	EXTI_IMR1_IM16 = 0x10000
	// Interrupt request line is masked
	EXTI_IMR1_IM16_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM16_Unmasked = 0x1
	// Position of IM17 field.
	EXTI_IMR1_IM17_Pos = 0x11
	// Bit mask of IM17 field.
	EXTI_IMR1_IM17_Msk = 0x20000
	// Bit IM17.
	EXTI_IMR1_IM17 = 0x20000
	// Interrupt request line is masked
	EXTI_IMR1_IM17_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM17_Unmasked = 0x1
	// Position of IM18 field.
	EXTI_IMR1_IM18_Pos = 0x12
	// Bit mask of IM18 field.
	EXTI_IMR1_IM18_Msk = 0x40000
	// Bit IM18.
	EXTI_IMR1_IM18 = 0x40000
	// Interrupt request line is masked
	EXTI_IMR1_IM18_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM18_Unmasked = 0x1
	// Position of IM19 field.
	EXTI_IMR1_IM19_Pos = 0x13
	// Bit mask of IM19 field.
	EXTI_IMR1_IM19_Msk = 0x80000
	// Bit IM19.
	EXTI_IMR1_IM19 = 0x80000
	// Interrupt request line is masked
	EXTI_IMR1_IM19_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM19_Unmasked = 0x1
	// Position of IM20 field.
	EXTI_IMR1_IM20_Pos = 0x14
	// Bit mask of IM20 field.
	EXTI_IMR1_IM20_Msk = 0x100000
	// Bit IM20.
	EXTI_IMR1_IM20 = 0x100000
	// Interrupt request line is masked
	EXTI_IMR1_IM20_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM20_Unmasked = 0x1
	// Position of IM21 field.
	EXTI_IMR1_IM21_Pos = 0x15
	// Bit mask of IM21 field.
	EXTI_IMR1_IM21_Msk = 0x200000
	// Bit IM21.
	EXTI_IMR1_IM21 = 0x200000
	// Interrupt request line is masked
	EXTI_IMR1_IM21_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM21_Unmasked = 0x1
	// Position of IM22 field.
	EXTI_IMR1_IM22_Pos = 0x16
	// Bit mask of IM22 field.
	EXTI_IMR1_IM22_Msk = 0x400000
	// Bit IM22.
	EXTI_IMR1_IM22 = 0x400000
	// Interrupt request line is masked
	EXTI_IMR1_IM22_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM22_Unmasked = 0x1
	// Position of IM23 field.
	EXTI_IMR1_IM23_Pos = 0x17
	// Bit mask of IM23 field.
	EXTI_IMR1_IM23_Msk = 0x800000
	// Bit IM23.
	EXTI_IMR1_IM23 = 0x800000
	// Interrupt request line is masked
	EXTI_IMR1_IM23_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM23_Unmasked = 0x1
	// Position of IM24 field.
	EXTI_IMR1_IM24_Pos = 0x18
	// Bit mask of IM24 field.
	EXTI_IMR1_IM24_Msk = 0x1000000
	// Bit IM24.
	EXTI_IMR1_IM24 = 0x1000000
	// Interrupt request line is masked
	EXTI_IMR1_IM24_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM24_Unmasked = 0x1
	// Position of IM25 field.
	EXTI_IMR1_IM25_Pos = 0x19
	// Bit mask of IM25 field.
	EXTI_IMR1_IM25_Msk = 0x2000000
	// Bit IM25.
	EXTI_IMR1_IM25 = 0x2000000
	// Interrupt request line is masked
	EXTI_IMR1_IM25_Masked = 0x0
	// Interrupt request line is unmasked
	EXTI_IMR1_IM25_Unmasked = 0x1

	// EMR1: EXTI CPU wake-up with event mask register
	// Position of EM0 field.
	EXTI_EMR1_EM0_Pos = 0x0
	// Bit mask of EM0 field.
	EXTI_EMR1_EM0_Msk = 0x1
	// Bit EM0.
	EXTI_EMR1_EM0 = 0x1
	// Event request line is masked
	EXTI_EMR1_EM0_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM0_Unmasked = 0x1
	// Position of EM1 field.
	EXTI_EMR1_EM1_Pos = 0x1
	// Bit mask of EM1 field.
	EXTI_EMR1_EM1_Msk = 0x2
	// Bit EM1.
	EXTI_EMR1_EM1 = 0x2
	// Event request line is masked
	EXTI_EMR1_EM1_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM1_Unmasked = 0x1
	// Position of EM2 field.
	EXTI_EMR1_EM2_Pos = 0x2
	// Bit mask of EM2 field.
	EXTI_EMR1_EM2_Msk = 0x4
	// Bit EM2.
	EXTI_EMR1_EM2 = 0x4
	// Event request line is masked
	EXTI_EMR1_EM2_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM2_Unmasked = 0x1
	// Position of EM3 field.
	EXTI_EMR1_EM3_Pos = 0x3
	// Bit mask of EM3 field.
	EXTI_EMR1_EM3_Msk = 0x8
	// Bit EM3.
	EXTI_EMR1_EM3 = 0x8
	// Event request line is masked
	EXTI_EMR1_EM3_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM3_Unmasked = 0x1
	// Position of EM4 field.
	EXTI_EMR1_EM4_Pos = 0x4
	// Bit mask of EM4 field.
	EXTI_EMR1_EM4_Msk = 0x10
	// Bit EM4.
	EXTI_EMR1_EM4 = 0x10
	// Event request line is masked
	EXTI_EMR1_EM4_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM4_Unmasked = 0x1
	// Position of EM5 field.
	EXTI_EMR1_EM5_Pos = 0x5
	// Bit mask of EM5 field.
	EXTI_EMR1_EM5_Msk = 0x20
	// Bit EM5.
	EXTI_EMR1_EM5 = 0x20
	// Event request line is masked
	EXTI_EMR1_EM5_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM5_Unmasked = 0x1
	// Position of EM6 field.
	EXTI_EMR1_EM6_Pos = 0x6
	// Bit mask of EM6 field.
	EXTI_EMR1_EM6_Msk = 0x40
	// Bit EM6.
	EXTI_EMR1_EM6 = 0x40
	// Event request line is masked
	EXTI_EMR1_EM6_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM6_Unmasked = 0x1
	// Position of EM7 field.
	EXTI_EMR1_EM7_Pos = 0x7
	// Bit mask of EM7 field.
	EXTI_EMR1_EM7_Msk = 0x80
	// Bit EM7.
	EXTI_EMR1_EM7 = 0x80
	// Event request line is masked
	EXTI_EMR1_EM7_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM7_Unmasked = 0x1
	// Position of EM8 field.
	EXTI_EMR1_EM8_Pos = 0x8
	// Bit mask of EM8 field.
	EXTI_EMR1_EM8_Msk = 0x100
	// Bit EM8.
	EXTI_EMR1_EM8 = 0x100
	// Event request line is masked
	EXTI_EMR1_EM8_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM8_Unmasked = 0x1
	// Position of EM9 field.
	EXTI_EMR1_EM9_Pos = 0x9
	// Bit mask of EM9 field.
	EXTI_EMR1_EM9_Msk = 0x200
	// Bit EM9.
	EXTI_EMR1_EM9 = 0x200
	// Event request line is masked
	EXTI_EMR1_EM9_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM9_Unmasked = 0x1
	// Position of EM10 field.
	EXTI_EMR1_EM10_Pos = 0xa
	// Bit mask of EM10 field.
	EXTI_EMR1_EM10_Msk = 0x400
	// Bit EM10.
	EXTI_EMR1_EM10 = 0x400
	// Event request line is masked
	EXTI_EMR1_EM10_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM10_Unmasked = 0x1
	// Position of EM11 field.
	EXTI_EMR1_EM11_Pos = 0xb
	// Bit mask of EM11 field.
	EXTI_EMR1_EM11_Msk = 0x800
	// Bit EM11.
	EXTI_EMR1_EM11 = 0x800
	// Event request line is masked
	EXTI_EMR1_EM11_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM11_Unmasked = 0x1
	// Position of EM12 field.
	EXTI_EMR1_EM12_Pos = 0xc
	// Bit mask of EM12 field.
	EXTI_EMR1_EM12_Msk = 0x1000
	// Bit EM12.
	EXTI_EMR1_EM12 = 0x1000
	// Event request line is masked
	EXTI_EMR1_EM12_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM12_Unmasked = 0x1
	// Position of EM13 field.
	EXTI_EMR1_EM13_Pos = 0xd
	// Bit mask of EM13 field.
	EXTI_EMR1_EM13_Msk = 0x2000
	// Bit EM13.
	EXTI_EMR1_EM13 = 0x2000
	// Event request line is masked
	EXTI_EMR1_EM13_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM13_Unmasked = 0x1
	// Position of EM14 field.
	EXTI_EMR1_EM14_Pos = 0xe
	// Bit mask of EM14 field.
	EXTI_EMR1_EM14_Msk = 0x4000
	// Bit EM14.
	EXTI_EMR1_EM14 = 0x4000
	// Event request line is masked
	EXTI_EMR1_EM14_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM14_Unmasked = 0x1
	// Position of EM15 field.
	EXTI_EMR1_EM15_Pos = 0xf
	// Bit mask of EM15 field.
	EXTI_EMR1_EM15_Msk = 0x8000
	// Bit EM15.
	EXTI_EMR1_EM15 = 0x8000
	// Event request line is masked
	EXTI_EMR1_EM15_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM15_Unmasked = 0x1
	// Position of EM16 field.
	EXTI_EMR1_EM16_Pos = 0x10
	// Bit mask of EM16 field.
	EXTI_EMR1_EM16_Msk = 0x10000
	// Bit EM16.
	EXTI_EMR1_EM16 = 0x10000
	// Event request line is masked
	EXTI_EMR1_EM16_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM16_Unmasked = 0x1
	// Position of EM17 field.
	EXTI_EMR1_EM17_Pos = 0x11
	// Bit mask of EM17 field.
	EXTI_EMR1_EM17_Msk = 0x20000
	// Bit EM17.
	EXTI_EMR1_EM17 = 0x20000
	// Event request line is masked
	EXTI_EMR1_EM17_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM17_Unmasked = 0x1
	// Position of EM18 field.
	EXTI_EMR1_EM18_Pos = 0x12
	// Bit mask of EM18 field.
	EXTI_EMR1_EM18_Msk = 0x40000
	// Bit EM18.
	EXTI_EMR1_EM18 = 0x40000
	// Event request line is masked
	EXTI_EMR1_EM18_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM18_Unmasked = 0x1
	// Position of EM19 field.
	EXTI_EMR1_EM19_Pos = 0x13
	// Bit mask of EM19 field.
	EXTI_EMR1_EM19_Msk = 0x80000
	// Bit EM19.
	EXTI_EMR1_EM19 = 0x80000
	// Event request line is masked
	EXTI_EMR1_EM19_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM19_Unmasked = 0x1
	// Position of EM20 field.
	EXTI_EMR1_EM20_Pos = 0x14
	// Bit mask of EM20 field.
	EXTI_EMR1_EM20_Msk = 0x100000
	// Bit EM20.
	EXTI_EMR1_EM20 = 0x100000
	// Event request line is masked
	EXTI_EMR1_EM20_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM20_Unmasked = 0x1
	// Position of EM21 field.
	EXTI_EMR1_EM21_Pos = 0x15
	// Bit mask of EM21 field.
	EXTI_EMR1_EM21_Msk = 0x200000
	// Bit EM21.
	EXTI_EMR1_EM21 = 0x200000
	// Event request line is masked
	EXTI_EMR1_EM21_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM21_Unmasked = 0x1
	// Position of EM22 field.
	EXTI_EMR1_EM22_Pos = 0x16
	// Bit mask of EM22 field.
	EXTI_EMR1_EM22_Msk = 0x400000
	// Bit EM22.
	EXTI_EMR1_EM22 = 0x400000
	// Event request line is masked
	EXTI_EMR1_EM22_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM22_Unmasked = 0x1
	// Position of EM23 field.
	EXTI_EMR1_EM23_Pos = 0x17
	// Bit mask of EM23 field.
	EXTI_EMR1_EM23_Msk = 0x800000
	// Bit EM23.
	EXTI_EMR1_EM23 = 0x800000
	// Event request line is masked
	EXTI_EMR1_EM23_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM23_Unmasked = 0x1
	// Position of EM24 field.
	EXTI_EMR1_EM24_Pos = 0x18
	// Bit mask of EM24 field.
	EXTI_EMR1_EM24_Msk = 0x1000000
	// Bit EM24.
	EXTI_EMR1_EM24 = 0x1000000
	// Event request line is masked
	EXTI_EMR1_EM24_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM24_Unmasked = 0x1
	// Position of EM25 field.
	EXTI_EMR1_EM25_Pos = 0x19
	// Bit mask of EM25 field.
	EXTI_EMR1_EM25_Msk = 0x2000000
	// Bit EM25.
	EXTI_EMR1_EM25 = 0x2000000
	// Event request line is masked
	EXTI_EMR1_EM25_Masked = 0x0
	// Event request line is unmasked
	EXTI_EMR1_EM25_Unmasked = 0x1
)

// Constants for FDCAN1_RAM: FDCAN1_RAM
const (
	// CREL: FDCAN Core Release Register
	// Position of REL field.
	FDCAN_CREL_REL_Pos = 0x1c
	// Bit mask of REL field.
	FDCAN_CREL_REL_Msk = 0xf0000000
	// Position of STEP field.
	FDCAN_CREL_STEP_Pos = 0x18
	// Bit mask of STEP field.
	FDCAN_CREL_STEP_Msk = 0xf000000
	// Position of SUBSTEP field.
	FDCAN_CREL_SUBSTEP_Pos = 0x14
	// Bit mask of SUBSTEP field.
	FDCAN_CREL_SUBSTEP_Msk = 0xf00000
	// Position of YEAR field.
	FDCAN_CREL_YEAR_Pos = 0x10
	// Bit mask of YEAR field.
	FDCAN_CREL_YEAR_Msk = 0xf0000
	// Position of MON field.
	FDCAN_CREL_MON_Pos = 0x8
	// Bit mask of MON field.
	FDCAN_CREL_MON_Msk = 0xff00
	// Position of DAY field.
	FDCAN_CREL_DAY_Pos = 0x0
	// Bit mask of DAY field.
	FDCAN_CREL_DAY_Msk = 0xff

	// ENDN: FDCAN endian register
	// Position of ETV field.
	FDCAN_ENDN_ETV_Pos = 0x0
	// Bit mask of ETV field.
	FDCAN_ENDN_ETV_Msk = 0xffffffff

	// DBTP: FDCAN Data Bit Timing and Prescaler Register
	// Position of DSJW field.
	FDCAN_DBTP_DSJW_Pos = 0x0
	// Bit mask of DSJW field.
	FDCAN_DBTP_DSJW_Msk = 0xf
	// Position of DTSEG2 field.
	FDCAN_DBTP_DTSEG2_Pos = 0x4
	// Bit mask of DTSEG2 field.
	FDCAN_DBTP_DTSEG2_Msk = 0xf0
	// Position of DTSEG1 field.
	FDCAN_DBTP_DTSEG1_Pos = 0x8
	// Bit mask of DTSEG1 field.
	FDCAN_DBTP_DTSEG1_Msk = 0x1f00
	// Position of DBRP field.
	FDCAN_DBTP_DBRP_Pos = 0x10
	// Bit mask of DBRP field.
	FDCAN_DBTP_DBRP_Msk = 0x1f0000
	// Position of TDC field.
	FDCAN_DBTP_TDC_Pos = 0x17
	// Bit mask of TDC field.
	FDCAN_DBTP_TDC_Msk = 0x800000
	// Bit TDC.
	FDCAN_DBTP_TDC = 0x800000

	// TEST: FDCAN Test Register
	// Position of LBCK field.
	FDCAN_TEST_LBCK_Pos = 0x4
	// Bit mask of LBCK field.
	FDCAN_TEST_LBCK_Msk = 0x10
	// Bit LBCK.
	FDCAN_TEST_LBCK = 0x10
	// Position of TX field.
	FDCAN_TEST_TX_Pos = 0x5
	// Bit mask of TX field.
	FDCAN_TEST_TX_Msk = 0x60
	// Position of RX field.
	FDCAN_TEST_RX_Pos = 0x7
	// Bit mask of RX field.
	FDCAN_TEST_RX_Msk = 0x80
	// Bit RX.
	FDCAN_TEST_RX = 0x80

	// RWD: FDCAN RAM Watchdog Register
	// Position of WDV field.
	FDCAN_RWD_WDV_Pos = 0x8
	// Bit mask of WDV field.
	FDCAN_RWD_WDV_Msk = 0xff00
	// Position of WDC field.
	FDCAN_RWD_WDC_Pos = 0x0
	// Bit mask of WDC field.
	FDCAN_RWD_WDC_Msk = 0xff

	// CCCR: FDCAN CC Control Register
	// Position of INIT field.
	FDCAN_CCCR_INIT_Pos = 0x0
	// Bit mask of INIT field.
	FDCAN_CCCR_INIT_Msk = 0x1
	// Bit INIT.
	FDCAN_CCCR_INIT = 0x1
	// Position of CCE field.
	FDCAN_CCCR_CCE_Pos = 0x1
	// Bit mask of CCE field.
	FDCAN_CCCR_CCE_Msk = 0x2
	// Bit CCE.
	FDCAN_CCCR_CCE = 0x2
	// Position of ASM field.
	FDCAN_CCCR_ASM_Pos = 0x2
	// Bit mask of ASM field.
	FDCAN_CCCR_ASM_Msk = 0x4
	// Bit ASM.
	FDCAN_CCCR_ASM = 0x4
	// Position of CSA field.
	FDCAN_CCCR_CSA_Pos = 0x3
	// Bit mask of CSA field.
	FDCAN_CCCR_CSA_Msk = 0x8
	// Bit CSA.
	FDCAN_CCCR_CSA = 0x8
	// Position of CSR field.
	FDCAN_CCCR_CSR_Pos = 0x4
	// Bit mask of CSR field.
	FDCAN_CCCR_CSR_Msk = 0x10
	// Bit CSR.
	FDCAN_CCCR_CSR = 0x10
	// Position of MON field.
	FDCAN_CCCR_MON_Pos = 0x5
	// Bit mask of MON field.
	FDCAN_CCCR_MON_Msk = 0x20
	// Bit MON.
	FDCAN_CCCR_MON = 0x20
	// Position of DAR field.
	FDCAN_CCCR_DAR_Pos = 0x6
	// Bit mask of DAR field.
	FDCAN_CCCR_DAR_Msk = 0x40
	// Bit DAR.
	FDCAN_CCCR_DAR = 0x40
	// Position of TEST field.
	FDCAN_CCCR_TEST_Pos = 0x7
	// Bit mask of TEST field.
	FDCAN_CCCR_TEST_Msk = 0x80
	// Bit TEST.
	FDCAN_CCCR_TEST = 0x80
	// Position of FDOE field.
	FDCAN_CCCR_FDOE_Pos = 0x8
	// Bit mask of FDOE field.
	FDCAN_CCCR_FDOE_Msk = 0x100
	// Bit FDOE.
	FDCAN_CCCR_FDOE = 0x100
	// Position of BRSE field.
	FDCAN_CCCR_BRSE_Pos = 0x9
	// Bit mask of BRSE field.
	FDCAN_CCCR_BRSE_Msk = 0x200
	// Bit BRSE.
	FDCAN_CCCR_BRSE = 0x200
	// Position of PXHD field.
	FDCAN_CCCR_PXHD_Pos = 0xc
	// Bit mask of PXHD field.
	FDCAN_CCCR_PXHD_Msk = 0x1000
	// Bit PXHD.
	FDCAN_CCCR_PXHD = 0x1000
	// Position of EFBI field.
	FDCAN_CCCR_EFBI_Pos = 0xd
	// Bit mask of EFBI field.
	FDCAN_CCCR_EFBI_Msk = 0x2000
	// Bit EFBI.
	FDCAN_CCCR_EFBI = 0x2000
	// Position of TXP field.
	FDCAN_CCCR_TXP_Pos = 0xe
	// Bit mask of TXP field.
	FDCAN_CCCR_TXP_Msk = 0x4000
	// Bit TXP.
	FDCAN_CCCR_TXP = 0x4000
	// Position of NISO field.
	FDCAN_CCCR_NISO_Pos = 0xf
	// Bit mask of NISO field.
	FDCAN_CCCR_NISO_Msk = 0x8000
	// Bit NISO.
	FDCAN_CCCR_NISO = 0x8000

	// NBTP: FDCAN Nominal Bit Timing and Prescaler Register
	// Position of NSJW field.
	FDCAN_NBTP_NSJW_Pos = 0x19
	// Bit mask of NSJW field.
	FDCAN_NBTP_NSJW_Msk = 0xfe000000
	// Position of NBRP field.
	FDCAN_NBTP_NBRP_Pos = 0x10
	// Bit mask of NBRP field.
	FDCAN_NBTP_NBRP_Msk = 0x1ff0000
	// Position of NTSEG1 field.
	FDCAN_NBTP_NTSEG1_Pos = 0x8
	// Bit mask of NTSEG1 field.
	FDCAN_NBTP_NTSEG1_Msk = 0xff00
	// Position of NTSEG2 field.
	FDCAN_NBTP_NTSEG2_Pos = 0x0
	// Bit mask of NTSEG2 field.
	FDCAN_NBTP_NTSEG2_Msk = 0x7f

	// TSCC: FDCAN Timestamp Counter Configuration Register
	// Position of TCP field.
	FDCAN_TSCC_TCP_Pos = 0x10
	// Bit mask of TCP field.
	FDCAN_TSCC_TCP_Msk = 0xf0000
	// Position of TSS field.
	FDCAN_TSCC_TSS_Pos = 0x0
	// Bit mask of TSS field.
	FDCAN_TSCC_TSS_Msk = 0x3

	// TSCV: FDCAN Timestamp Counter Value Register
	// Position of TSC field.
	FDCAN_TSCV_TSC_Pos = 0x0
	// Bit mask of TSC field.
	FDCAN_TSCV_TSC_Msk = 0xffff

	// TOCC: FDCAN Timeout Counter Configuration Register
	// Position of ETOC field.
	FDCAN_TOCC_ETOC_Pos = 0x0
	// Bit mask of ETOC field.
	FDCAN_TOCC_ETOC_Msk = 0x1
	// Bit ETOC.
	FDCAN_TOCC_ETOC = 0x1
	// Position of TOS field.
	FDCAN_TOCC_TOS_Pos = 0x1
	// Bit mask of TOS field.
	FDCAN_TOCC_TOS_Msk = 0x6
	// Position of TOP field.
	FDCAN_TOCC_TOP_Pos = 0x10
	// Bit mask of TOP field.
	FDCAN_TOCC_TOP_Msk = 0xffff0000

	// TOCV: FDCAN Timeout Counter Value Register
	// Position of TOC field.
	FDCAN_TOCV_TOC_Pos = 0x0
	// Bit mask of TOC field.
	FDCAN_TOCV_TOC_Msk = 0xffff

	// ECR: FDCAN Error Counter Register
	// Position of CEL field.
	FDCAN_ECR_CEL_Pos = 0x10
	// Bit mask of CEL field.
	FDCAN_ECR_CEL_Msk = 0xff0000
	// Position of RP field.
	FDCAN_ECR_RP_Pos = 0xf
	// Bit mask of RP field.
	FDCAN_ECR_RP_Msk = 0x8000
	// Bit RP.
	FDCAN_ECR_RP = 0x8000
	// Position of REC field.
	FDCAN_ECR_REC_Pos = 0x8
	// Bit mask of REC field.
	FDCAN_ECR_REC_Msk = 0x7f00
	// Position of TEC field.
	FDCAN_ECR_TEC_Pos = 0x0
	// Bit mask of TEC field.
	FDCAN_ECR_TEC_Msk = 0xff

	// PSR: FDCAN Protocol Status Register
	// Position of LEC field.
	FDCAN_PSR_LEC_Pos = 0x0
	// Bit mask of LEC field.
	FDCAN_PSR_LEC_Msk = 0x7
	// Position of ACT field.
	FDCAN_PSR_ACT_Pos = 0x3
	// Bit mask of ACT field.
	FDCAN_PSR_ACT_Msk = 0x18
	// Position of EP field.
	FDCAN_PSR_EP_Pos = 0x5
	// Bit mask of EP field.
	FDCAN_PSR_EP_Msk = 0x20
	// Bit EP.
	FDCAN_PSR_EP = 0x20
	// Position of EW field.
	FDCAN_PSR_EW_Pos = 0x6
	// Bit mask of EW field.
	FDCAN_PSR_EW_Msk = 0x40
	// Bit EW.
	FDCAN_PSR_EW = 0x40
	// Position of BO field.
	FDCAN_PSR_BO_Pos = 0x7
	// Bit mask of BO field.
	FDCAN_PSR_BO_Msk = 0x80
	// Bit BO.
	FDCAN_PSR_BO = 0x80
	// Position of DLEC field.
	FDCAN_PSR_DLEC_Pos = 0x8
	// Bit mask of DLEC field.
	FDCAN_PSR_DLEC_Msk = 0x700
	// Position of RESI field.
	FDCAN_PSR_RESI_Pos = 0xb
	// Bit mask of RESI field.
	FDCAN_PSR_RESI_Msk = 0x800
	// Bit RESI.
	FDCAN_PSR_RESI = 0x800
	// Position of RBRS field.
	FDCAN_PSR_RBRS_Pos = 0xc
	// Bit mask of RBRS field.
	FDCAN_PSR_RBRS_Msk = 0x1000
	// Bit RBRS.
	FDCAN_PSR_RBRS = 0x1000
	// Position of REDL field.
	FDCAN_PSR_REDL_Pos = 0xd
	// Bit mask of REDL field.
	FDCAN_PSR_REDL_Msk = 0x2000
	// Bit REDL.
	FDCAN_PSR_REDL = 0x2000
	// Position of PXE field.
	FDCAN_PSR_PXE_Pos = 0xe
	// Bit mask of PXE field.
	FDCAN_PSR_PXE_Msk = 0x4000
	// Bit PXE.
	FDCAN_PSR_PXE = 0x4000
	// Position of TDCV field.
	FDCAN_PSR_TDCV_Pos = 0x10
	// Bit mask of TDCV field.
	FDCAN_PSR_TDCV_Msk = 0x7f0000

	// TDCR: FDCAN Transmitter Delay Compensation Register
	// Position of TDCF field.
	FDCAN_TDCR_TDCF_Pos = 0x0
	// Bit mask of TDCF field.
	FDCAN_TDCR_TDCF_Msk = 0x7f
	// Position of TDCO field.
	FDCAN_TDCR_TDCO_Pos = 0x8
	// Bit mask of TDCO field.
	FDCAN_TDCR_TDCO_Msk = 0x7f00

	// IR: FDCAN Interrupt Register
	// Position of RF0N field.
	FDCAN_IR_RF0N_Pos = 0x0
	// Bit mask of RF0N field.
	FDCAN_IR_RF0N_Msk = 0x1
	// Bit RF0N.
	FDCAN_IR_RF0N = 0x1
	// Position of RF0F field.
	FDCAN_IR_RF0F_Pos = 0x1
	// Bit mask of RF0F field.
	FDCAN_IR_RF0F_Msk = 0x2
	// Bit RF0F.
	FDCAN_IR_RF0F = 0x2
	// Position of RF0L field.
	FDCAN_IR_RF0L_Pos = 0x2
	// Bit mask of RF0L field.
	FDCAN_IR_RF0L_Msk = 0x4
	// Bit RF0L.
	FDCAN_IR_RF0L = 0x4
	// Position of RF1N field.
	FDCAN_IR_RF1N_Pos = 0x3
	// Bit mask of RF1N field.
	FDCAN_IR_RF1N_Msk = 0x8
	// Bit RF1N.
	FDCAN_IR_RF1N = 0x8
	// Position of RF1F field.
	FDCAN_IR_RF1F_Pos = 0x4
	// Bit mask of RF1F field.
	FDCAN_IR_RF1F_Msk = 0x10
	// Bit RF1F.
	FDCAN_IR_RF1F = 0x10
	// Position of RF1L field.
	FDCAN_IR_RF1L_Pos = 0x5
	// Bit mask of RF1L field.
	FDCAN_IR_RF1L_Msk = 0x20
	// Bit RF1L.
	FDCAN_IR_RF1L = 0x20
	// Position of HPM field.
	FDCAN_IR_HPM_Pos = 0x6
	// Bit mask of HPM field.
	FDCAN_IR_HPM_Msk = 0x40
	// Bit HPM.
	FDCAN_IR_HPM = 0x40
	// Position of TC field.
	FDCAN_IR_TC_Pos = 0x7
	// Bit mask of TC field.
	FDCAN_IR_TC_Msk = 0x80
	// Bit TC.
	FDCAN_IR_TC = 0x80
	// Position of TCF field.
	FDCAN_IR_TCF_Pos = 0x8
	// Bit mask of TCF field.
	FDCAN_IR_TCF_Msk = 0x100
	// Bit TCF.
	FDCAN_IR_TCF = 0x100
	// Position of TFE field.
	FDCAN_IR_TFE_Pos = 0x9
	// Bit mask of TFE field.
	FDCAN_IR_TFE_Msk = 0x200
	// Bit TFE.
	FDCAN_IR_TFE = 0x200
	// Position of TEFN field.
	FDCAN_IR_TEFN_Pos = 0xa
	// Bit mask of TEFN field.
	FDCAN_IR_TEFN_Msk = 0x400
	// Bit TEFN.
	FDCAN_IR_TEFN = 0x400
	// Position of TEFF field.
	FDCAN_IR_TEFF_Pos = 0xb
	// Bit mask of TEFF field.
	FDCAN_IR_TEFF_Msk = 0x800
	// Bit TEFF.
	FDCAN_IR_TEFF = 0x800
	// Position of TEFL field.
	FDCAN_IR_TEFL_Pos = 0xc
	// Bit mask of TEFL field.
	FDCAN_IR_TEFL_Msk = 0x1000
	// Bit TEFL.
	FDCAN_IR_TEFL = 0x1000
	// Position of TSW field.
	FDCAN_IR_TSW_Pos = 0xd
	// Bit mask of TSW field.
	FDCAN_IR_TSW_Msk = 0x2000
	// Bit TSW.
	FDCAN_IR_TSW = 0x2000
	// Position of MRAF field.
	FDCAN_IR_MRAF_Pos = 0xe
	// Bit mask of MRAF field.
	FDCAN_IR_MRAF_Msk = 0x4000
	// Bit MRAF.
	FDCAN_IR_MRAF = 0x4000
	// Position of TOO field.
	FDCAN_IR_TOO_Pos = 0xf
	// Bit mask of TOO field.
	FDCAN_IR_TOO_Msk = 0x8000
	// Bit TOO.
	FDCAN_IR_TOO = 0x8000
	// Position of ELO field.
	FDCAN_IR_ELO_Pos = 0x10
	// Bit mask of ELO field.
	FDCAN_IR_ELO_Msk = 0x10000
	// Bit ELO.
	FDCAN_IR_ELO = 0x10000
	// Position of EP field.
	FDCAN_IR_EP_Pos = 0x11
	// Bit mask of EP field.
	FDCAN_IR_EP_Msk = 0x20000
	// Bit EP.
	FDCAN_IR_EP = 0x20000
	// Position of EW field.
	FDCAN_IR_EW_Pos = 0x12
	// Bit mask of EW field.
	FDCAN_IR_EW_Msk = 0x40000
	// Bit EW.
	FDCAN_IR_EW = 0x40000
	// Position of BO field.
	FDCAN_IR_BO_Pos = 0x13
	// Bit mask of BO field.
	FDCAN_IR_BO_Msk = 0x80000
	// Bit BO.
	FDCAN_IR_BO = 0x80000
	// Position of WDI field.
	FDCAN_IR_WDI_Pos = 0x14
	// Bit mask of WDI field.
	FDCAN_IR_WDI_Msk = 0x100000
	// Bit WDI.
	FDCAN_IR_WDI = 0x100000
	// Position of PEA field.
	FDCAN_IR_PEA_Pos = 0x15
	// Bit mask of PEA field.
	FDCAN_IR_PEA_Msk = 0x200000
	// Bit PEA.
	FDCAN_IR_PEA = 0x200000
	// Position of PED field.
	FDCAN_IR_PED_Pos = 0x16
	// Bit mask of PED field.
	FDCAN_IR_PED_Msk = 0x400000
	// Bit PED.
	FDCAN_IR_PED = 0x400000
	// Position of ARA field.
	FDCAN_IR_ARA_Pos = 0x17
	// Bit mask of ARA field.
	FDCAN_IR_ARA_Msk = 0x800000
	// Bit ARA.
	FDCAN_IR_ARA = 0x800000

	// IE: FDCAN Interrupt Enable Register
	// Position of RF0NE field.
	FDCAN_IE_RF0NE_Pos = 0x0
	// Bit mask of RF0NE field.
	FDCAN_IE_RF0NE_Msk = 0x1
	// Bit RF0NE.
	FDCAN_IE_RF0NE = 0x1
	// Position of RF0FE field.
	FDCAN_IE_RF0FE_Pos = 0x1
	// Bit mask of RF0FE field.
	FDCAN_IE_RF0FE_Msk = 0x2
	// Bit RF0FE.
	FDCAN_IE_RF0FE = 0x2
	// Position of RF0LE field.
	FDCAN_IE_RF0LE_Pos = 0x2
	// Bit mask of RF0LE field.
	FDCAN_IE_RF0LE_Msk = 0x4
	// Bit RF0LE.
	FDCAN_IE_RF0LE = 0x4
	// Position of RF1NE field.
	FDCAN_IE_RF1NE_Pos = 0x3
	// Bit mask of RF1NE field.
	FDCAN_IE_RF1NE_Msk = 0x8
	// Bit RF1NE.
	FDCAN_IE_RF1NE = 0x8
	// Position of RF1FE field.
	FDCAN_IE_RF1FE_Pos = 0x4
	// Bit mask of RF1FE field.
	FDCAN_IE_RF1FE_Msk = 0x10
	// Bit RF1FE.
	FDCAN_IE_RF1FE = 0x10
	// Position of RF1LE field.
	FDCAN_IE_RF1LE_Pos = 0x5
	// Bit mask of RF1LE field.
	FDCAN_IE_RF1LE_Msk = 0x20
	// Bit RF1LE.
	FDCAN_IE_RF1LE = 0x20
	// Position of HPME field.
	FDCAN_IE_HPME_Pos = 0x6
	// Bit mask of HPME field.
	FDCAN_IE_HPME_Msk = 0x40
	// Bit HPME.
	FDCAN_IE_HPME = 0x40
	// Position of TCE field.
	FDCAN_IE_TCE_Pos = 0x7
	// Bit mask of TCE field.
	FDCAN_IE_TCE_Msk = 0x80
	// Bit TCE.
	FDCAN_IE_TCE = 0x80
	// Position of TCFE field.
	FDCAN_IE_TCFE_Pos = 0x8
	// Bit mask of TCFE field.
	FDCAN_IE_TCFE_Msk = 0x100
	// Bit TCFE.
	FDCAN_IE_TCFE = 0x100
	// Position of TEFE field.
	FDCAN_IE_TEFE_Pos = 0x9
	// Bit mask of TEFE field.
	FDCAN_IE_TEFE_Msk = 0x200
	// Bit TEFE.
	FDCAN_IE_TEFE = 0x200
	// Position of TEFNE field.
	FDCAN_IE_TEFNE_Pos = 0xa
	// Bit mask of TEFNE field.
	FDCAN_IE_TEFNE_Msk = 0x400
	// Bit TEFNE.
	FDCAN_IE_TEFNE = 0x400
	// Position of TEFFE field.
	FDCAN_IE_TEFFE_Pos = 0xb
	// Bit mask of TEFFE field.
	FDCAN_IE_TEFFE_Msk = 0x800
	// Bit TEFFE.
	FDCAN_IE_TEFFE = 0x800
	// Position of TEFLE field.
	FDCAN_IE_TEFLE_Pos = 0xc
	// Bit mask of TEFLE field.
	FDCAN_IE_TEFLE_Msk = 0x1000
	// Bit TEFLE.
	FDCAN_IE_TEFLE = 0x1000
	// Position of TSWE field.
	FDCAN_IE_TSWE_Pos = 0xd
	// Bit mask of TSWE field.
	FDCAN_IE_TSWE_Msk = 0x2000
	// Bit TSWE.
	FDCAN_IE_TSWE = 0x2000
	// Position of MRAFE field.
	FDCAN_IE_MRAFE_Pos = 0xe
	// Bit mask of MRAFE field.
	FDCAN_IE_MRAFE_Msk = 0x4000
	// Bit MRAFE.
	FDCAN_IE_MRAFE = 0x4000
	// Position of TOOE field.
	FDCAN_IE_TOOE_Pos = 0xf
	// Bit mask of TOOE field.
	FDCAN_IE_TOOE_Msk = 0x8000
	// Bit TOOE.
	FDCAN_IE_TOOE = 0x8000
	// Position of ELOE field.
	FDCAN_IE_ELOE_Pos = 0x10
	// Bit mask of ELOE field.
	FDCAN_IE_ELOE_Msk = 0x10000
	// Bit ELOE.
	FDCAN_IE_ELOE = 0x10000
	// Position of EPE field.
	FDCAN_IE_EPE_Pos = 0x11
	// Bit mask of EPE field.
	FDCAN_IE_EPE_Msk = 0x20000
	// Bit EPE.
	FDCAN_IE_EPE = 0x20000
	// Position of EWE field.
	FDCAN_IE_EWE_Pos = 0x12
	// Bit mask of EWE field.
	FDCAN_IE_EWE_Msk = 0x40000
	// Bit EWE.
	FDCAN_IE_EWE = 0x40000
	// Position of BOE field.
	FDCAN_IE_BOE_Pos = 0x13
	// Bit mask of BOE field.
	FDCAN_IE_BOE_Msk = 0x80000
	// Bit BOE.
	FDCAN_IE_BOE = 0x80000
	// Position of WDIE field.
	FDCAN_IE_WDIE_Pos = 0x14
	// Bit mask of WDIE field.
	FDCAN_IE_WDIE_Msk = 0x100000
	// Bit WDIE.
	FDCAN_IE_WDIE = 0x100000
	// Position of PEAE field.
	FDCAN_IE_PEAE_Pos = 0x15
	// Bit mask of PEAE field.
	FDCAN_IE_PEAE_Msk = 0x200000
	// Bit PEAE.
	FDCAN_IE_PEAE = 0x200000
	// Position of PEDE field.
	FDCAN_IE_PEDE_Pos = 0x16
	// Bit mask of PEDE field.
	FDCAN_IE_PEDE_Msk = 0x400000
	// Bit PEDE.
	FDCAN_IE_PEDE = 0x400000
	// Position of ARAE field.
	FDCAN_IE_ARAE_Pos = 0x17
	// Bit mask of ARAE field.
	FDCAN_IE_ARAE_Msk = 0x800000
	// Bit ARAE.
	FDCAN_IE_ARAE = 0x800000

	// ILS: FDCAN Interrupt Line Select Register
	// Position of RxFIFO0 field.
	FDCAN_ILS_RxFIFO0_Pos = 0x0
	// Bit mask of RxFIFO0 field.
	FDCAN_ILS_RxFIFO0_Msk = 0x1
	// Bit RxFIFO0.
	FDCAN_ILS_RxFIFO0 = 0x1
	// Position of RxFIFO1 field.
	FDCAN_ILS_RxFIFO1_Pos = 0x1
	// Bit mask of RxFIFO1 field.
	FDCAN_ILS_RxFIFO1_Msk = 0x2
	// Bit RxFIFO1.
	FDCAN_ILS_RxFIFO1 = 0x2
	// Position of SMSG field.
	FDCAN_ILS_SMSG_Pos = 0x2
	// Bit mask of SMSG field.
	FDCAN_ILS_SMSG_Msk = 0x4
	// Bit SMSG.
	FDCAN_ILS_SMSG = 0x4
	// Position of TFERR field.
	FDCAN_ILS_TFERR_Pos = 0x3
	// Bit mask of TFERR field.
	FDCAN_ILS_TFERR_Msk = 0x8
	// Bit TFERR.
	FDCAN_ILS_TFERR = 0x8
	// Position of MISC field.
	FDCAN_ILS_MISC_Pos = 0x4
	// Bit mask of MISC field.
	FDCAN_ILS_MISC_Msk = 0x10
	// Bit MISC.
	FDCAN_ILS_MISC = 0x10
	// Position of BERR field.
	FDCAN_ILS_BERR_Pos = 0x5
	// Bit mask of BERR field.
	FDCAN_ILS_BERR_Msk = 0x20
	// Bit BERR.
	FDCAN_ILS_BERR = 0x20
	// Position of PERR field.
	FDCAN_ILS_PERR_Pos = 0x6
	// Bit mask of PERR field.
	FDCAN_ILS_PERR_Msk = 0x40
	// Bit PERR.
	FDCAN_ILS_PERR = 0x40

	// ILE: FDCAN Interrupt Line Enable Register
	// Position of EINT0 field.
	FDCAN_ILE_EINT0_Pos = 0x0
	// Bit mask of EINT0 field.
	FDCAN_ILE_EINT0_Msk = 0x1
	// Bit EINT0.
	FDCAN_ILE_EINT0 = 0x1
	// Position of EINT1 field.
	FDCAN_ILE_EINT1_Pos = 0x1
	// Bit mask of EINT1 field.
	FDCAN_ILE_EINT1_Msk = 0x2
	// Bit EINT1.
	FDCAN_ILE_EINT1 = 0x2

	// RXGFC: FDCAN Global Filter Configuration Register
	// Position of RRFE field.
	FDCAN_RXGFC_RRFE_Pos = 0x0
	// Bit mask of RRFE field.
	FDCAN_RXGFC_RRFE_Msk = 0x1
	// Bit RRFE.
	FDCAN_RXGFC_RRFE = 0x1
	// Position of RRFS field.
	FDCAN_RXGFC_RRFS_Pos = 0x1
	// Bit mask of RRFS field.
	FDCAN_RXGFC_RRFS_Msk = 0x2
	// Bit RRFS.
	FDCAN_RXGFC_RRFS = 0x2
	// Position of ANFE field.
	FDCAN_RXGFC_ANFE_Pos = 0x2
	// Bit mask of ANFE field.
	FDCAN_RXGFC_ANFE_Msk = 0xc
	// Position of ANFS field.
	FDCAN_RXGFC_ANFS_Pos = 0x4
	// Bit mask of ANFS field.
	FDCAN_RXGFC_ANFS_Msk = 0x30
	// Position of F1OM field.
	FDCAN_RXGFC_F1OM_Pos = 0x8
	// Bit mask of F1OM field.
	FDCAN_RXGFC_F1OM_Msk = 0x100
	// Bit F1OM.
	FDCAN_RXGFC_F1OM = 0x100
	// Position of F0OM field.
	FDCAN_RXGFC_F0OM_Pos = 0x9
	// Bit mask of F0OM field.
	FDCAN_RXGFC_F0OM_Msk = 0x200
	// Bit F0OM.
	FDCAN_RXGFC_F0OM = 0x200
	// Position of LSS field.
	FDCAN_RXGFC_LSS_Pos = 0x10
	// Bit mask of LSS field.
	FDCAN_RXGFC_LSS_Msk = 0x1f0000
	// Position of LSE field.
	FDCAN_RXGFC_LSE_Pos = 0x18
	// Bit mask of LSE field.
	FDCAN_RXGFC_LSE_Msk = 0xf000000

	// XIDAM: FDCAN Extended ID and Mask Register
	// Position of EIDM field.
	FDCAN_XIDAM_EIDM_Pos = 0x0
	// Bit mask of EIDM field.
	FDCAN_XIDAM_EIDM_Msk = 0x1fffffff

	// HPMS: FDCAN High Priority Message Status Register
	// Position of BIDX field.
	FDCAN_HPMS_BIDX_Pos = 0x0
	// Bit mask of BIDX field.
	FDCAN_HPMS_BIDX_Msk = 0x7
	// Position of MSI field.
	FDCAN_HPMS_MSI_Pos = 0x6
	// Bit mask of MSI field.
	FDCAN_HPMS_MSI_Msk = 0xc0
	// Position of FIDX field.
	FDCAN_HPMS_FIDX_Pos = 0x8
	// Bit mask of FIDX field.
	FDCAN_HPMS_FIDX_Msk = 0x1f00
	// Position of FLST field.
	FDCAN_HPMS_FLST_Pos = 0xf
	// Bit mask of FLST field.
	FDCAN_HPMS_FLST_Msk = 0x8000
	// Bit FLST.
	FDCAN_HPMS_FLST = 0x8000

	// RXF0S: FDCAN Rx FIFO 0 Status Register
	// Position of F0FL field.
	FDCAN_RXF0S_F0FL_Pos = 0x0
	// Bit mask of F0FL field.
	FDCAN_RXF0S_F0FL_Msk = 0xf
	// Position of F0GI field.
	FDCAN_RXF0S_F0GI_Pos = 0x8
	// Bit mask of F0GI field.
	FDCAN_RXF0S_F0GI_Msk = 0x300
	// Position of F0PI field.
	FDCAN_RXF0S_F0PI_Pos = 0x10
	// Bit mask of F0PI field.
	FDCAN_RXF0S_F0PI_Msk = 0x30000
	// Position of F0F field.
	FDCAN_RXF0S_F0F_Pos = 0x18
	// Bit mask of F0F field.
	FDCAN_RXF0S_F0F_Msk = 0x1000000
	// Bit F0F.
	FDCAN_RXF0S_F0F = 0x1000000
	// Position of RF0L field.
	FDCAN_RXF0S_RF0L_Pos = 0x19
	// Bit mask of RF0L field.
	FDCAN_RXF0S_RF0L_Msk = 0x2000000
	// Bit RF0L.
	FDCAN_RXF0S_RF0L = 0x2000000

	// RXF0A: CAN Rx FIFO 0 Acknowledge Register
	// Position of F0AI field.
	FDCAN_RXF0A_F0AI_Pos = 0x0
	// Bit mask of F0AI field.
	FDCAN_RXF0A_F0AI_Msk = 0x7

	// RXF1S: FDCAN Rx FIFO 1 Status Register
	// Position of F1FL field.
	FDCAN_RXF1S_F1FL_Pos = 0x0
	// Bit mask of F1FL field.
	FDCAN_RXF1S_F1FL_Msk = 0xf
	// Position of F1GI field.
	FDCAN_RXF1S_F1GI_Pos = 0x8
	// Bit mask of F1GI field.
	FDCAN_RXF1S_F1GI_Msk = 0x300
	// Position of F1PI field.
	FDCAN_RXF1S_F1PI_Pos = 0x10
	// Bit mask of F1PI field.
	FDCAN_RXF1S_F1PI_Msk = 0x30000
	// Position of F1F field.
	FDCAN_RXF1S_F1F_Pos = 0x18
	// Bit mask of F1F field.
	FDCAN_RXF1S_F1F_Msk = 0x1000000
	// Bit F1F.
	FDCAN_RXF1S_F1F = 0x1000000
	// Position of RF1L field.
	FDCAN_RXF1S_RF1L_Pos = 0x19
	// Bit mask of RF1L field.
	FDCAN_RXF1S_RF1L_Msk = 0x2000000
	// Bit RF1L.
	FDCAN_RXF1S_RF1L = 0x2000000

	// RXF1A: FDCAN Rx FIFO 1 Acknowledge Register
	// Position of F1AI field.
	FDCAN_RXF1A_F1AI_Pos = 0x0
	// Bit mask of F1AI field.
	FDCAN_RXF1A_F1AI_Msk = 0x7

	// TXBC: FDCAN Tx buffer configuration register
	// Position of TFQM field.
	FDCAN_TXBC_TFQM_Pos = 0x18
	// Bit mask of TFQM field.
	FDCAN_TXBC_TFQM_Msk = 0x1000000
	// Bit TFQM.
	FDCAN_TXBC_TFQM = 0x1000000

	// TXFQS: FDCAN Tx FIFO/Queue Status Register
	// Position of TFFL field.
	FDCAN_TXFQS_TFFL_Pos = 0x0
	// Bit mask of TFFL field.
	FDCAN_TXFQS_TFFL_Msk = 0x7
	// Position of TFGI field.
	FDCAN_TXFQS_TFGI_Pos = 0x8
	// Bit mask of TFGI field.
	FDCAN_TXFQS_TFGI_Msk = 0x300
	// Position of TFQPI field.
	FDCAN_TXFQS_TFQPI_Pos = 0x10
	// Bit mask of TFQPI field.
	FDCAN_TXFQS_TFQPI_Msk = 0x30000
	// Position of TFQF field.
	FDCAN_TXFQS_TFQF_Pos = 0x15
	// Bit mask of TFQF field.
	FDCAN_TXFQS_TFQF_Msk = 0x200000
	// Bit TFQF.
	FDCAN_TXFQS_TFQF = 0x200000

	// TXBRP: FDCAN Tx Buffer Request Pending Register
	// Position of TRP field.
	FDCAN_TXBRP_TRP_Pos = 0x0
	// Bit mask of TRP field.
	FDCAN_TXBRP_TRP_Msk = 0x7

	// TXBAR: FDCAN Tx Buffer Add Request Register
	// Position of AR field.
	FDCAN_TXBAR_AR_Pos = 0x0
	// Bit mask of AR field.
	FDCAN_TXBAR_AR_Msk = 0x7

	// TXBCR: FDCAN Tx Buffer Cancellation Request Register
	// Position of CR field.
	FDCAN_TXBCR_CR_Pos = 0x0
	// Bit mask of CR field.
	FDCAN_TXBCR_CR_Msk = 0x7

	// TXBTO: FDCAN Tx Buffer Transmission Occurred Register
	// Position of TO field.
	FDCAN_TXBTO_TO_Pos = 0x0
	// Bit mask of TO field.
	FDCAN_TXBTO_TO_Msk = 0x7

	// TXBCF: FDCAN Tx Buffer Cancellation Finished Register
	// Position of CF field.
	FDCAN_TXBCF_CF_Pos = 0x0
	// Bit mask of CF field.
	FDCAN_TXBCF_CF_Msk = 0x7

	// TXBTIE: FDCAN Tx Buffer Transmission Interrupt Enable Register
	// Position of TIE field.
	FDCAN_TXBTIE_TIE_Pos = 0x0
	// Bit mask of TIE field.
	FDCAN_TXBTIE_TIE_Msk = 0x7

	// TXBCIE: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
	// Position of CFIE field.
	FDCAN_TXBCIE_CFIE_Pos = 0x0
	// Bit mask of CFIE field.
	FDCAN_TXBCIE_CFIE_Msk = 0x7

	// TXEFS: FDCAN Tx Event FIFO Status Register
	// Position of EFFL field.
	FDCAN_TXEFS_EFFL_Pos = 0x0
	// Bit mask of EFFL field.
	FDCAN_TXEFS_EFFL_Msk = 0x7
	// Position of EFGI field.
	FDCAN_TXEFS_EFGI_Pos = 0x8
	// Bit mask of EFGI field.
	FDCAN_TXEFS_EFGI_Msk = 0x300
	// Position of EFPI field.
	FDCAN_TXEFS_EFPI_Pos = 0x10
	// Bit mask of EFPI field.
	FDCAN_TXEFS_EFPI_Msk = 0x30000
	// Position of EFF field.
	FDCAN_TXEFS_EFF_Pos = 0x18
	// Bit mask of EFF field.
	FDCAN_TXEFS_EFF_Msk = 0x1000000
	// Bit EFF.
	FDCAN_TXEFS_EFF = 0x1000000
	// Position of TEFL field.
	FDCAN_TXEFS_TEFL_Pos = 0x19
	// Bit mask of TEFL field.
	FDCAN_TXEFS_TEFL_Msk = 0x2000000
	// Bit TEFL.
	FDCAN_TXEFS_TEFL = 0x2000000

	// TXEFA: FDCAN Tx Event FIFO Acknowledge Register
	// Position of EFAI field.
	FDCAN_TXEFA_EFAI_Pos = 0x0
	// Bit mask of EFAI field.
	FDCAN_TXEFA_EFAI_Msk = 0x3

	// CKDIV: FDCAN CFG clock divider register
	// Position of PDIV field.
	FDCAN_CKDIV_PDIV_Pos = 0x0
	// Bit mask of PDIV field.
	FDCAN_CKDIV_PDIV_Msk = 0xf
)

// Constants for FLASH: Flash
const (
	// ACR: FLASH access control register
	// Position of LATENCY field.
	Flash_ACR_LATENCY_Pos = 0x0
	// Bit mask of LATENCY field.
	Flash_ACR_LATENCY_Msk = 0xf
	// Position of PRFTEN field.
	Flash_ACR_PRFTEN_Pos = 0x8
	// Bit mask of PRFTEN field.
	Flash_ACR_PRFTEN_Msk = 0x100
	// Bit PRFTEN.
	Flash_ACR_PRFTEN = 0x100
	// Position of LPM field.
	Flash_ACR_LPM_Pos = 0xb
	// Bit mask of LPM field.
	Flash_ACR_LPM_Msk = 0x800
	// Bit LPM.
	Flash_ACR_LPM = 0x800
	// Position of PDREQ1 field.
	Flash_ACR_PDREQ1_Pos = 0xc
	// Bit mask of PDREQ1 field.
	Flash_ACR_PDREQ1_Msk = 0x1000
	// Bit PDREQ1.
	Flash_ACR_PDREQ1 = 0x1000
	// Position of PDREQ2 field.
	Flash_ACR_PDREQ2_Pos = 0xd
	// Bit mask of PDREQ2 field.
	Flash_ACR_PDREQ2_Msk = 0x2000
	// Bit PDREQ2.
	Flash_ACR_PDREQ2 = 0x2000
	// Position of SLEEP_PD field.
	Flash_ACR_SLEEP_PD_Pos = 0xe
	// Bit mask of SLEEP_PD field.
	Flash_ACR_SLEEP_PD_Msk = 0x4000
	// Bit SLEEP_PD.
	Flash_ACR_SLEEP_PD = 0x4000

	// NSKEYR: FLASH non-secure key register
	// Position of NSKEY field.
	Flash_NSKEYR_NSKEY_Pos = 0x0
	// Bit mask of NSKEY field.
	Flash_NSKEYR_NSKEY_Msk = 0xffffffff

	// SECKEYR: FLASH secure key register
	// Position of SECKEY field.
	Flash_SECKEYR_SECKEY_Pos = 0x0
	// Bit mask of SECKEY field.
	Flash_SECKEYR_SECKEY_Msk = 0xffffffff

	// OPTKEYR: FLASH option key register
	// Position of OPTKEY field.
	Flash_OPTKEYR_OPTKEY_Pos = 0x0
	// Bit mask of OPTKEY field.
	Flash_OPTKEYR_OPTKEY_Msk = 0xffffffff

	// PDKEY1R: FLASH bank 1 power-down key register
	// Position of PDKEY1 field.
	Flash_PDKEY1R_PDKEY1_Pos = 0x0
	// Bit mask of PDKEY1 field.
	Flash_PDKEY1R_PDKEY1_Msk = 0xffffffff

	// PDKEY2R: FLASH bank 2 power-down key register
	// Position of PDKEY2 field.
	Flash_PDKEY2R_PDKEY2_Pos = 0x0
	// Bit mask of PDKEY2 field.
	Flash_PDKEY2R_PDKEY2_Msk = 0xffffffff

	// NSSR: FLASH non-secure status register
	// Position of EOP field.
	Flash_NSSR_EOP_Pos = 0x0
	// Bit mask of EOP field.
	Flash_NSSR_EOP_Msk = 0x1
	// Bit EOP.
	Flash_NSSR_EOP = 0x1
	// Position of OPERR field.
	Flash_NSSR_OPERR_Pos = 0x1
	// Bit mask of OPERR field.
	Flash_NSSR_OPERR_Msk = 0x2
	// Bit OPERR.
	Flash_NSSR_OPERR = 0x2
	// Position of PROGERR field.
	Flash_NSSR_PROGERR_Pos = 0x3
	// Bit mask of PROGERR field.
	Flash_NSSR_PROGERR_Msk = 0x8
	// Bit PROGERR.
	Flash_NSSR_PROGERR = 0x8
	// Position of WRPERR field.
	Flash_NSSR_WRPERR_Pos = 0x4
	// Bit mask of WRPERR field.
	Flash_NSSR_WRPERR_Msk = 0x10
	// Bit WRPERR.
	Flash_NSSR_WRPERR = 0x10
	// Position of PGAERR field.
	Flash_NSSR_PGAERR_Pos = 0x5
	// Bit mask of PGAERR field.
	Flash_NSSR_PGAERR_Msk = 0x20
	// Bit PGAERR.
	Flash_NSSR_PGAERR = 0x20
	// Position of SIZERR field.
	Flash_NSSR_SIZERR_Pos = 0x6
	// Bit mask of SIZERR field.
	Flash_NSSR_SIZERR_Msk = 0x40
	// Bit SIZERR.
	Flash_NSSR_SIZERR = 0x40
	// Position of PGSERR field.
	Flash_NSSR_PGSERR_Pos = 0x7
	// Bit mask of PGSERR field.
	Flash_NSSR_PGSERR_Msk = 0x80
	// Bit PGSERR.
	Flash_NSSR_PGSERR = 0x80
	// Position of OPTWERR field.
	Flash_NSSR_OPTWERR_Pos = 0xd
	// Bit mask of OPTWERR field.
	Flash_NSSR_OPTWERR_Msk = 0x2000
	// Bit OPTWERR.
	Flash_NSSR_OPTWERR = 0x2000
	// Position of BSY field.
	Flash_NSSR_BSY_Pos = 0x10
	// Bit mask of BSY field.
	Flash_NSSR_BSY_Msk = 0x10000
	// Bit BSY.
	Flash_NSSR_BSY = 0x10000
	// Position of WDW field.
	Flash_NSSR_WDW_Pos = 0x11
	// Bit mask of WDW field.
	Flash_NSSR_WDW_Msk = 0x20000
	// Bit WDW.
	Flash_NSSR_WDW = 0x20000
	// Position of OEM1LOCK field.
	Flash_NSSR_OEM1LOCK_Pos = 0x12
	// Bit mask of OEM1LOCK field.
	Flash_NSSR_OEM1LOCK_Msk = 0x40000
	// Bit OEM1LOCK.
	Flash_NSSR_OEM1LOCK = 0x40000
	// Position of OEM2LOCK field.
	Flash_NSSR_OEM2LOCK_Pos = 0x13
	// Bit mask of OEM2LOCK field.
	Flash_NSSR_OEM2LOCK_Msk = 0x80000
	// Bit OEM2LOCK.
	Flash_NSSR_OEM2LOCK = 0x80000
	// Position of PD1 field.
	Flash_NSSR_PD1_Pos = 0x14
	// Bit mask of PD1 field.
	Flash_NSSR_PD1_Msk = 0x100000
	// Bit PD1.
	Flash_NSSR_PD1 = 0x100000
	// Position of PD2 field.
	Flash_NSSR_PD2_Pos = 0x15
	// Bit mask of PD2 field.
	Flash_NSSR_PD2_Msk = 0x200000
	// Bit PD2.
	Flash_NSSR_PD2 = 0x200000

	// SECSR: FLASH secure status register
	// Position of EOP field.
	Flash_SECSR_EOP_Pos = 0x0
	// Bit mask of EOP field.
	Flash_SECSR_EOP_Msk = 0x1
	// Bit EOP.
	Flash_SECSR_EOP = 0x1
	// Position of OPERR field.
	Flash_SECSR_OPERR_Pos = 0x1
	// Bit mask of OPERR field.
	Flash_SECSR_OPERR_Msk = 0x2
	// Bit OPERR.
	Flash_SECSR_OPERR = 0x2
	// Position of PROGERR field.
	Flash_SECSR_PROGERR_Pos = 0x3
	// Bit mask of PROGERR field.
	Flash_SECSR_PROGERR_Msk = 0x8
	// Bit PROGERR.
	Flash_SECSR_PROGERR = 0x8
	// Position of WRPERR field.
	Flash_SECSR_WRPERR_Pos = 0x4
	// Bit mask of WRPERR field.
	Flash_SECSR_WRPERR_Msk = 0x10
	// Bit WRPERR.
	Flash_SECSR_WRPERR = 0x10
	// Position of PGAERR field.
	Flash_SECSR_PGAERR_Pos = 0x5
	// Bit mask of PGAERR field.
	Flash_SECSR_PGAERR_Msk = 0x20
	// Bit PGAERR.
	Flash_SECSR_PGAERR = 0x20
	// Position of SIZERR field.
	Flash_SECSR_SIZERR_Pos = 0x6
	// Bit mask of SIZERR field.
	Flash_SECSR_SIZERR_Msk = 0x40
	// Bit SIZERR.
	Flash_SECSR_SIZERR = 0x40
	// Position of PGSERR field.
	Flash_SECSR_PGSERR_Pos = 0x7
	// Bit mask of PGSERR field.
	Flash_SECSR_PGSERR_Msk = 0x80
	// Bit PGSERR.
	Flash_SECSR_PGSERR = 0x80
	// Position of RDERR field.
	Flash_SECSR_RDERR_Pos = 0xe
	// Bit mask of RDERR field.
	Flash_SECSR_RDERR_Msk = 0x4000
	// Bit RDERR.
	Flash_SECSR_RDERR = 0x4000
	// Position of BSY field.
	Flash_SECSR_BSY_Pos = 0x10
	// Bit mask of BSY field.
	Flash_SECSR_BSY_Msk = 0x10000
	// Bit BSY.
	Flash_SECSR_BSY = 0x10000
	// Position of WDW field.
	Flash_SECSR_WDW_Pos = 0x11
	// Bit mask of WDW field.
	Flash_SECSR_WDW_Msk = 0x20000
	// Bit WDW.
	Flash_SECSR_WDW = 0x20000

	// NSCR: FLASH non-secure control register
	// Position of PG field.
	Flash_NSCR_PG_Pos = 0x0
	// Bit mask of PG field.
	Flash_NSCR_PG_Msk = 0x1
	// Bit PG.
	Flash_NSCR_PG = 0x1
	// Position of PER field.
	Flash_NSCR_PER_Pos = 0x1
	// Bit mask of PER field.
	Flash_NSCR_PER_Msk = 0x2
	// Bit PER.
	Flash_NSCR_PER = 0x2
	// Position of MER1 field.
	Flash_NSCR_MER1_Pos = 0x2
	// Bit mask of MER1 field.
	Flash_NSCR_MER1_Msk = 0x4
	// Bit MER1.
	Flash_NSCR_MER1 = 0x4
	// Position of PNB field.
	Flash_NSCR_PNB_Pos = 0x3
	// Bit mask of PNB field.
	Flash_NSCR_PNB_Msk = 0x7f8
	// Position of BKER field.
	Flash_NSCR_BKER_Pos = 0xb
	// Bit mask of BKER field.
	Flash_NSCR_BKER_Msk = 0x800
	// Bit BKER.
	Flash_NSCR_BKER = 0x800
	// Position of BWR field.
	Flash_NSCR_BWR_Pos = 0xe
	// Bit mask of BWR field.
	Flash_NSCR_BWR_Msk = 0x4000
	// Bit BWR.
	Flash_NSCR_BWR = 0x4000
	// Position of MER2 field.
	Flash_NSCR_MER2_Pos = 0xf
	// Bit mask of MER2 field.
	Flash_NSCR_MER2_Msk = 0x8000
	// Bit MER2.
	Flash_NSCR_MER2 = 0x8000
	// Position of STRT field.
	Flash_NSCR_STRT_Pos = 0x10
	// Bit mask of STRT field.
	Flash_NSCR_STRT_Msk = 0x10000
	// Bit STRT.
	Flash_NSCR_STRT = 0x10000
	// Position of OPTSTRT field.
	Flash_NSCR_OPTSTRT_Pos = 0x11
	// Bit mask of OPTSTRT field.
	Flash_NSCR_OPTSTRT_Msk = 0x20000
	// Bit OPTSTRT.
	Flash_NSCR_OPTSTRT = 0x20000
	// Position of EOPIE field.
	Flash_NSCR_EOPIE_Pos = 0x18
	// Bit mask of EOPIE field.
	Flash_NSCR_EOPIE_Msk = 0x1000000
	// Bit EOPIE.
	Flash_NSCR_EOPIE = 0x1000000
	// Position of ERRIE field.
	Flash_NSCR_ERRIE_Pos = 0x19
	// Bit mask of ERRIE field.
	Flash_NSCR_ERRIE_Msk = 0x2000000
	// Bit ERRIE.
	Flash_NSCR_ERRIE = 0x2000000
	// Position of OBL_LAUNCH field.
	Flash_NSCR_OBL_LAUNCH_Pos = 0x1b
	// Bit mask of OBL_LAUNCH field.
	Flash_NSCR_OBL_LAUNCH_Msk = 0x8000000
	// Bit OBL_LAUNCH.
	Flash_NSCR_OBL_LAUNCH = 0x8000000
	// Position of OPTLOCK field.
	Flash_NSCR_OPTLOCK_Pos = 0x1e
	// Bit mask of OPTLOCK field.
	Flash_NSCR_OPTLOCK_Msk = 0x40000000
	// Bit OPTLOCK.
	Flash_NSCR_OPTLOCK = 0x40000000
	// Position of LOCK field.
	Flash_NSCR_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	Flash_NSCR_LOCK_Msk = 0x80000000
	// Bit LOCK.
	Flash_NSCR_LOCK = 0x80000000

	// SECCR: FLASH secure control register
	// Position of PG field.
	Flash_SECCR_PG_Pos = 0x0
	// Bit mask of PG field.
	Flash_SECCR_PG_Msk = 0x1
	// Bit PG.
	Flash_SECCR_PG = 0x1
	// Position of PER field.
	Flash_SECCR_PER_Pos = 0x1
	// Bit mask of PER field.
	Flash_SECCR_PER_Msk = 0x2
	// Bit PER.
	Flash_SECCR_PER = 0x2
	// Position of MER1 field.
	Flash_SECCR_MER1_Pos = 0x2
	// Bit mask of MER1 field.
	Flash_SECCR_MER1_Msk = 0x4
	// Bit MER1.
	Flash_SECCR_MER1 = 0x4
	// Position of PNB field.
	Flash_SECCR_PNB_Pos = 0x3
	// Bit mask of PNB field.
	Flash_SECCR_PNB_Msk = 0x7f8
	// Position of BKER field.
	Flash_SECCR_BKER_Pos = 0xb
	// Bit mask of BKER field.
	Flash_SECCR_BKER_Msk = 0x800
	// Bit BKER.
	Flash_SECCR_BKER = 0x800
	// Position of BWR field.
	Flash_SECCR_BWR_Pos = 0xe
	// Bit mask of BWR field.
	Flash_SECCR_BWR_Msk = 0x4000
	// Bit BWR.
	Flash_SECCR_BWR = 0x4000
	// Position of MER2 field.
	Flash_SECCR_MER2_Pos = 0xf
	// Bit mask of MER2 field.
	Flash_SECCR_MER2_Msk = 0x8000
	// Bit MER2.
	Flash_SECCR_MER2 = 0x8000
	// Position of STRT field.
	Flash_SECCR_STRT_Pos = 0x10
	// Bit mask of STRT field.
	Flash_SECCR_STRT_Msk = 0x10000
	// Bit STRT.
	Flash_SECCR_STRT = 0x10000
	// Position of EOPIE field.
	Flash_SECCR_EOPIE_Pos = 0x18
	// Bit mask of EOPIE field.
	Flash_SECCR_EOPIE_Msk = 0x1000000
	// Bit EOPIE.
	Flash_SECCR_EOPIE = 0x1000000
	// Position of ERRIE field.
	Flash_SECCR_ERRIE_Pos = 0x19
	// Bit mask of ERRIE field.
	Flash_SECCR_ERRIE_Msk = 0x2000000
	// Bit ERRIE.
	Flash_SECCR_ERRIE = 0x2000000
	// Position of RDERRIE field.
	Flash_SECCR_RDERRIE_Pos = 0x1a
	// Bit mask of RDERRIE field.
	Flash_SECCR_RDERRIE_Msk = 0x4000000
	// Bit RDERRIE.
	Flash_SECCR_RDERRIE = 0x4000000
	// Position of INV field.
	Flash_SECCR_INV_Pos = 0x1d
	// Bit mask of INV field.
	Flash_SECCR_INV_Msk = 0x20000000
	// Bit INV.
	Flash_SECCR_INV = 0x20000000
	// Position of LOCK field.
	Flash_SECCR_LOCK_Pos = 0x1f
	// Bit mask of LOCK field.
	Flash_SECCR_LOCK_Msk = 0x80000000
	// Bit LOCK.
	Flash_SECCR_LOCK = 0x80000000

	// ECCR: FLASH ECC register
	// Position of ADDR_ECC field.
	Flash_ECCR_ADDR_ECC_Pos = 0x0
	// Bit mask of ADDR_ECC field.
	Flash_ECCR_ADDR_ECC_Msk = 0x1fffff
	// Position of BK_ECC field.
	Flash_ECCR_BK_ECC_Pos = 0x15
	// Bit mask of BK_ECC field.
	Flash_ECCR_BK_ECC_Msk = 0x200000
	// Bit BK_ECC.
	Flash_ECCR_BK_ECC = 0x200000
	// Position of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC_Pos = 0x16
	// Bit mask of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC_Msk = 0x400000
	// Bit SYSF_ECC.
	Flash_ECCR_SYSF_ECC = 0x400000
	// Position of ECCIE field.
	Flash_ECCR_ECCIE_Pos = 0x18
	// Bit mask of ECCIE field.
	Flash_ECCR_ECCIE_Msk = 0x1000000
	// Bit ECCIE.
	Flash_ECCR_ECCIE = 0x1000000
	// Position of ECCC field.
	Flash_ECCR_ECCC_Pos = 0x1e
	// Bit mask of ECCC field.
	Flash_ECCR_ECCC_Msk = 0x40000000
	// Bit ECCC.
	Flash_ECCR_ECCC = 0x40000000
	// Position of ECCD field.
	Flash_ECCR_ECCD_Pos = 0x1f
	// Bit mask of ECCD field.
	Flash_ECCR_ECCD_Msk = 0x80000000
	// Bit ECCD.
	Flash_ECCR_ECCD = 0x80000000

	// OPSR: FLASH operation status register
	// Position of ADDR_OP field.
	Flash_OPSR_ADDR_OP_Pos = 0x0
	// Bit mask of ADDR_OP field.
	Flash_OPSR_ADDR_OP_Msk = 0x1fffff
	// Position of BK_OP field.
	Flash_OPSR_BK_OP_Pos = 0x15
	// Bit mask of BK_OP field.
	Flash_OPSR_BK_OP_Msk = 0x200000
	// Bit BK_OP.
	Flash_OPSR_BK_OP = 0x200000
	// Position of SYSF_OP field.
	Flash_OPSR_SYSF_OP_Pos = 0x16
	// Bit mask of SYSF_OP field.
	Flash_OPSR_SYSF_OP_Msk = 0x400000
	// Bit SYSF_OP.
	Flash_OPSR_SYSF_OP = 0x400000
	// Position of CODE_OP field.
	Flash_OPSR_CODE_OP_Pos = 0x1d
	// Bit mask of CODE_OP field.
	Flash_OPSR_CODE_OP_Msk = 0xe0000000

	// OPTR: FLASH option register
	// Position of RDP field.
	Flash_OPTR_RDP_Pos = 0x0
	// Bit mask of RDP field.
	Flash_OPTR_RDP_Msk = 0xff
	// Position of BOR_LEV field.
	Flash_OPTR_BOR_LEV_Pos = 0x8
	// Bit mask of BOR_LEV field.
	Flash_OPTR_BOR_LEV_Msk = 0x700
	// Position of NRST_STOP field.
	Flash_OPTR_NRST_STOP_Pos = 0xc
	// Bit mask of NRST_STOP field.
	Flash_OPTR_NRST_STOP_Msk = 0x1000
	// Bit NRST_STOP.
	Flash_OPTR_NRST_STOP = 0x1000
	// Position of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY_Pos = 0xd
	// Bit mask of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY_Msk = 0x2000
	// Bit NRST_STDBY.
	Flash_OPTR_NRST_STDBY = 0x2000
	// Position of NRST_SHDW field.
	Flash_OPTR_NRST_SHDW_Pos = 0xe
	// Bit mask of NRST_SHDW field.
	Flash_OPTR_NRST_SHDW_Msk = 0x4000
	// Bit NRST_SHDW.
	Flash_OPTR_NRST_SHDW = 0x4000
	// Position of SRAM1345_RST field.
	Flash_OPTR_SRAM1345_RST_Pos = 0xf
	// Bit mask of SRAM1345_RST field.
	Flash_OPTR_SRAM1345_RST_Msk = 0x8000
	// Bit SRAM1345_RST.
	Flash_OPTR_SRAM1345_RST = 0x8000
	// Position of IWDG_SW field.
	Flash_OPTR_IWDG_SW_Pos = 0x10
	// Bit mask of IWDG_SW field.
	Flash_OPTR_IWDG_SW_Msk = 0x10000
	// Bit IWDG_SW.
	Flash_OPTR_IWDG_SW = 0x10000
	// Position of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP_Pos = 0x11
	// Bit mask of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP_Msk = 0x20000
	// Bit IWDG_STOP.
	Flash_OPTR_IWDG_STOP = 0x20000
	// Position of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY_Pos = 0x12
	// Bit mask of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY_Msk = 0x40000
	// Bit IWDG_STDBY.
	Flash_OPTR_IWDG_STDBY = 0x40000
	// Position of WWDG_SW field.
	Flash_OPTR_WWDG_SW_Pos = 0x13
	// Bit mask of WWDG_SW field.
	Flash_OPTR_WWDG_SW_Msk = 0x80000
	// Bit WWDG_SW.
	Flash_OPTR_WWDG_SW = 0x80000
	// Position of SWAP_BANK field.
	Flash_OPTR_SWAP_BANK_Pos = 0x14
	// Bit mask of SWAP_BANK field.
	Flash_OPTR_SWAP_BANK_Msk = 0x100000
	// Bit SWAP_BANK.
	Flash_OPTR_SWAP_BANK = 0x100000
	// Position of DUALBANK field.
	Flash_OPTR_DUALBANK_Pos = 0x15
	// Bit mask of DUALBANK field.
	Flash_OPTR_DUALBANK_Msk = 0x200000
	// Bit DUALBANK.
	Flash_OPTR_DUALBANK = 0x200000
	// Position of BKPRAM_ECC field.
	Flash_OPTR_BKPRAM_ECC_Pos = 0x16
	// Bit mask of BKPRAM_ECC field.
	Flash_OPTR_BKPRAM_ECC_Msk = 0x400000
	// Bit BKPRAM_ECC.
	Flash_OPTR_BKPRAM_ECC = 0x400000
	// Position of SRAM3_ECC field.
	Flash_OPTR_SRAM3_ECC_Pos = 0x17
	// Bit mask of SRAM3_ECC field.
	Flash_OPTR_SRAM3_ECC_Msk = 0x800000
	// Bit SRAM3_ECC.
	Flash_OPTR_SRAM3_ECC = 0x800000
	// Position of SRAM2_ECC field.
	Flash_OPTR_SRAM2_ECC_Pos = 0x18
	// Bit mask of SRAM2_ECC field.
	Flash_OPTR_SRAM2_ECC_Msk = 0x1000000
	// Bit SRAM2_ECC.
	Flash_OPTR_SRAM2_ECC = 0x1000000
	// Position of SRAM2_RST field.
	Flash_OPTR_SRAM2_RST_Pos = 0x19
	// Bit mask of SRAM2_RST field.
	Flash_OPTR_SRAM2_RST_Msk = 0x2000000
	// Bit SRAM2_RST.
	Flash_OPTR_SRAM2_RST = 0x2000000
	// Position of NSWBOOT0 field.
	Flash_OPTR_NSWBOOT0_Pos = 0x1a
	// Bit mask of NSWBOOT0 field.
	Flash_OPTR_NSWBOOT0_Msk = 0x4000000
	// Bit NSWBOOT0.
	Flash_OPTR_NSWBOOT0 = 0x4000000
	// Position of NBOOT0 field.
	Flash_OPTR_NBOOT0_Pos = 0x1b
	// Bit mask of NBOOT0 field.
	Flash_OPTR_NBOOT0_Msk = 0x8000000
	// Bit NBOOT0.
	Flash_OPTR_NBOOT0 = 0x8000000
	// Position of PA15_PUPEN field.
	Flash_OPTR_PA15_PUPEN_Pos = 0x1c
	// Bit mask of PA15_PUPEN field.
	Flash_OPTR_PA15_PUPEN_Msk = 0x10000000
	// Bit PA15_PUPEN.
	Flash_OPTR_PA15_PUPEN = 0x10000000
	// Position of IO_VDD_HSLV field.
	Flash_OPTR_IO_VDD_HSLV_Pos = 0x1d
	// Bit mask of IO_VDD_HSLV field.
	Flash_OPTR_IO_VDD_HSLV_Msk = 0x20000000
	// Bit IO_VDD_HSLV.
	Flash_OPTR_IO_VDD_HSLV = 0x20000000
	// Position of IO_VDDIO2_HSLV field.
	Flash_OPTR_IO_VDDIO2_HSLV_Pos = 0x1e
	// Bit mask of IO_VDDIO2_HSLV field.
	Flash_OPTR_IO_VDDIO2_HSLV_Msk = 0x40000000
	// Bit IO_VDDIO2_HSLV.
	Flash_OPTR_IO_VDDIO2_HSLV = 0x40000000
	// Position of TZEN field.
	Flash_OPTR_TZEN_Pos = 0x1f
	// Bit mask of TZEN field.
	Flash_OPTR_TZEN_Msk = 0x80000000
	// Bit TZEN.
	Flash_OPTR_TZEN = 0x80000000

	// NSBOOTADD0R: FLASH non-secure boot address 0 register
	// Position of NSBOOTADD0 field.
	Flash_NSBOOTADD0R_NSBOOTADD0_Pos = 0x7
	// Bit mask of NSBOOTADD0 field.
	Flash_NSBOOTADD0R_NSBOOTADD0_Msk = 0xffffff80

	// NSBOOTADD1R: FLASH non-secure boot address 1 register
	// Position of NSBOOTADD1 field.
	Flash_NSBOOTADD1R_NSBOOTADD1_Pos = 0x7
	// Bit mask of NSBOOTADD1 field.
	Flash_NSBOOTADD1R_NSBOOTADD1_Msk = 0xffffff80

	// SECBOOTADD0R: FLASH secure boot address 0 register
	// Position of BOOT_LOCK field.
	Flash_SECBOOTADD0R_BOOT_LOCK_Pos = 0x0
	// Bit mask of BOOT_LOCK field.
	Flash_SECBOOTADD0R_BOOT_LOCK_Msk = 0x1
	// Bit BOOT_LOCK.
	Flash_SECBOOTADD0R_BOOT_LOCK = 0x1
	// Position of SECBOOTADD0 field.
	Flash_SECBOOTADD0R_SECBOOTADD0_Pos = 0x7
	// Bit mask of SECBOOTADD0 field.
	Flash_SECBOOTADD0R_SECBOOTADD0_Msk = 0xffffff80

	// SECWM1R1: FLASH secure watermark1 register 1
	// Position of SECWM1_PSTRT field.
	Flash_SECWM1R1_SECWM1_PSTRT_Pos = 0x0
	// Bit mask of SECWM1_PSTRT field.
	Flash_SECWM1R1_SECWM1_PSTRT_Msk = 0xff
	// Position of SECWM1_PEND field.
	Flash_SECWM1R1_SECWM1_PEND_Pos = 0x10
	// Bit mask of SECWM1_PEND field.
	Flash_SECWM1R1_SECWM1_PEND_Msk = 0xff0000

	// SECWM1R2: FLASH secure watermark1 register 2
	// Position of PCROP1_PSTRT field.
	Flash_SECWM1R2_PCROP1_PSTRT_Pos = 0x0
	// Bit mask of PCROP1_PSTRT field.
	Flash_SECWM1R2_PCROP1_PSTRT_Msk = 0xff
	// Position of PCROP1EN field.
	Flash_SECWM1R2_PCROP1EN_Pos = 0xf
	// Bit mask of PCROP1EN field.
	Flash_SECWM1R2_PCROP1EN_Msk = 0x8000
	// Bit PCROP1EN.
	Flash_SECWM1R2_PCROP1EN = 0x8000
	// Position of HDP1_PEND field.
	Flash_SECWM1R2_HDP1_PEND_Pos = 0x10
	// Bit mask of HDP1_PEND field.
	Flash_SECWM1R2_HDP1_PEND_Msk = 0xff0000
	// Position of HDP1EN field.
	Flash_SECWM1R2_HDP1EN_Pos = 0x1f
	// Bit mask of HDP1EN field.
	Flash_SECWM1R2_HDP1EN_Msk = 0x80000000
	// Bit HDP1EN.
	Flash_SECWM1R2_HDP1EN = 0x80000000

	// WRP1AR: FLASH WRP1 area A address register
	// Position of WRP1A_PSTRT field.
	Flash_WRP1AR_WRP1A_PSTRT_Pos = 0x0
	// Bit mask of WRP1A_PSTRT field.
	Flash_WRP1AR_WRP1A_PSTRT_Msk = 0xff
	// Position of WRP1A_PEND field.
	Flash_WRP1AR_WRP1A_PEND_Pos = 0x10
	// Bit mask of WRP1A_PEND field.
	Flash_WRP1AR_WRP1A_PEND_Msk = 0xff0000
	// Position of UNLOCK field.
	Flash_WRP1AR_UNLOCK_Pos = 0x1f
	// Bit mask of UNLOCK field.
	Flash_WRP1AR_UNLOCK_Msk = 0x80000000
	// Bit UNLOCK.
	Flash_WRP1AR_UNLOCK = 0x80000000

	// WRP1BR: FLASH WRP1 area B address register
	// Position of WRP1B_PSTRT field.
	Flash_WRP1BR_WRP1B_PSTRT_Pos = 0x0
	// Bit mask of WRP1B_PSTRT field.
	Flash_WRP1BR_WRP1B_PSTRT_Msk = 0xff
	// Position of WRP1B_PEND field.
	Flash_WRP1BR_WRP1B_PEND_Pos = 0x10
	// Bit mask of WRP1B_PEND field.
	Flash_WRP1BR_WRP1B_PEND_Msk = 0xff0000
	// Position of UNLOCK field.
	Flash_WRP1BR_UNLOCK_Pos = 0x1f
	// Bit mask of UNLOCK field.
	Flash_WRP1BR_UNLOCK_Msk = 0x80000000
	// Bit UNLOCK.
	Flash_WRP1BR_UNLOCK = 0x80000000

	// SECWM2R1: FLASH secure watermark2 register 1
	// Position of SECWM2_PSTRT field.
	Flash_SECWM2R1_SECWM2_PSTRT_Pos = 0x0
	// Bit mask of SECWM2_PSTRT field.
	Flash_SECWM2R1_SECWM2_PSTRT_Msk = 0xff
	// Position of SECWM2_PEND field.
	Flash_SECWM2R1_SECWM2_PEND_Pos = 0x10
	// Bit mask of SECWM2_PEND field.
	Flash_SECWM2R1_SECWM2_PEND_Msk = 0xff0000

	// SECWM2R2: FLASH secure watermark2 register 2
	// Position of PCROP2_PSTRT field.
	Flash_SECWM2R2_PCROP2_PSTRT_Pos = 0x0
	// Bit mask of PCROP2_PSTRT field.
	Flash_SECWM2R2_PCROP2_PSTRT_Msk = 0xff
	// Position of PCROP2EN field.
	Flash_SECWM2R2_PCROP2EN_Pos = 0xf
	// Bit mask of PCROP2EN field.
	Flash_SECWM2R2_PCROP2EN_Msk = 0x8000
	// Bit PCROP2EN.
	Flash_SECWM2R2_PCROP2EN = 0x8000
	// Position of HDP2_PEND field.
	Flash_SECWM2R2_HDP2_PEND_Pos = 0x10
	// Bit mask of HDP2_PEND field.
	Flash_SECWM2R2_HDP2_PEND_Msk = 0xff0000
	// Position of HDP2EN field.
	Flash_SECWM2R2_HDP2EN_Pos = 0x1f
	// Bit mask of HDP2EN field.
	Flash_SECWM2R2_HDP2EN_Msk = 0x80000000
	// Bit HDP2EN.
	Flash_SECWM2R2_HDP2EN = 0x80000000

	// WRP2AR: FLASH WPR2 area A address register
	// Position of WRP2A_PSTRT field.
	Flash_WRP2AR_WRP2A_PSTRT_Pos = 0x0
	// Bit mask of WRP2A_PSTRT field.
	Flash_WRP2AR_WRP2A_PSTRT_Msk = 0xff
	// Position of WRP2A_PEND field.
	Flash_WRP2AR_WRP2A_PEND_Pos = 0x10
	// Bit mask of WRP2A_PEND field.
	Flash_WRP2AR_WRP2A_PEND_Msk = 0xff0000
	// Position of UNLOCK field.
	Flash_WRP2AR_UNLOCK_Pos = 0x1f
	// Bit mask of UNLOCK field.
	Flash_WRP2AR_UNLOCK_Msk = 0x80000000
	// Bit UNLOCK.
	Flash_WRP2AR_UNLOCK = 0x80000000

	// WRP2BR: FLASH WPR2 area B address register
	// Position of WRP2B_PSTRT field.
	Flash_WRP2BR_WRP2B_PSTRT_Pos = 0x0
	// Bit mask of WRP2B_PSTRT field.
	Flash_WRP2BR_WRP2B_PSTRT_Msk = 0xff
	// Position of WRP2B_PEND field.
	Flash_WRP2BR_WRP2B_PEND_Pos = 0x10
	// Bit mask of WRP2B_PEND field.
	Flash_WRP2BR_WRP2B_PEND_Msk = 0xff0000
	// Position of UNLOCK field.
	Flash_WRP2BR_UNLOCK_Pos = 0x1f
	// Bit mask of UNLOCK field.
	Flash_WRP2BR_UNLOCK_Msk = 0x80000000
	// Bit UNLOCK.
	Flash_WRP2BR_UNLOCK = 0x80000000

	// OEM1KEYR1: FLASH OEM1 key register 1
	// Position of OEM1KEY field.
	Flash_OEM1KEYR1_OEM1KEY_Pos = 0x0
	// Bit mask of OEM1KEY field.
	Flash_OEM1KEYR1_OEM1KEY_Msk = 0xffffffff

	// OEM1KEYR2: FLASH OEM1 key register 2
	// Position of OEM1KEY field.
	Flash_OEM1KEYR2_OEM1KEY_Pos = 0x0
	// Bit mask of OEM1KEY field.
	Flash_OEM1KEYR2_OEM1KEY_Msk = 0xffffffff

	// OEM2KEYR1: FLASH OEM2 key register 1
	// Position of OEM2KEY field.
	Flash_OEM2KEYR1_OEM2KEY_Pos = 0x0
	// Bit mask of OEM2KEY field.
	Flash_OEM2KEYR1_OEM2KEY_Msk = 0xffffffff

	// OEM2KEYR2: FLASH OEM2 key register 2
	// Position of OEM2KEY field.
	Flash_OEM2KEYR2_OEM2KEY_Pos = 0x0
	// Bit mask of OEM2KEY field.
	Flash_OEM2KEYR2_OEM2KEY_Msk = 0xffffffff

	// SEC1BBR1: FLASH secure block based bank 1 register 1
	// Position of SEC1BB0 field.
	Flash_SEC1BBR1_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR1_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR1_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR1_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR1_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR1_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR1_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR1_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR1_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR1_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR1_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR1_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR1_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR1_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR1_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR1_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR1_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR1_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR1_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR1_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR1_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR1_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR1_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR1_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR1_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR1_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR1_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR1_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR1_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR1_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR1_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR1_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR1_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR1_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR1_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR1_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR1_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR1_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR1_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR1_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR1_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR1_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR1_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR1_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR1_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR1_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR1_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR1_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR1_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR1_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR1_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR1_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR1_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR1_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR1_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR1_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR1_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR1_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR1_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR1_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR1_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR1_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR1_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR1_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR1_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR1_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR1_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR1_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR1_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR1_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR1_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR1_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR1_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR1_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR1_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR1_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR1_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR1_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR1_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR1_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR1_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR1_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR1_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR1_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR1_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR1_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR1_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR1_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR1_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR1_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR1_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR1_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR1_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR1_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR1_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR1_SEC1BB31 = 0x80000000

	// SEC1BBR2: FLASH secure block based bank 1 register 2
	// Position of SEC1BB0 field.
	Flash_SEC1BBR2_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR2_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR2_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR2_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR2_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR2_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR2_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR2_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR2_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR2_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR2_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR2_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR2_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR2_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR2_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR2_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR2_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR2_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR2_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR2_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR2_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR2_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR2_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR2_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR2_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR2_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR2_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR2_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR2_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR2_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR2_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR2_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR2_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR2_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR2_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR2_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR2_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR2_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR2_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR2_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR2_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR2_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR2_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR2_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR2_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR2_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR2_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR2_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR2_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR2_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR2_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR2_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR2_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR2_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR2_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR2_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR2_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR2_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR2_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR2_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR2_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR2_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR2_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR2_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR2_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR2_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR2_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR2_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR2_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR2_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR2_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR2_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR2_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR2_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR2_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR2_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR2_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR2_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR2_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR2_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR2_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR2_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR2_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR2_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR2_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR2_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR2_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR2_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR2_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR2_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR2_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR2_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR2_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR2_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR2_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR2_SEC1BB31 = 0x80000000

	// SEC1BBR3: FLASH secure block based bank 1 register 3
	// Position of SEC1BB0 field.
	Flash_SEC1BBR3_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR3_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR3_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR3_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR3_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR3_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR3_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR3_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR3_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR3_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR3_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR3_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR3_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR3_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR3_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR3_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR3_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR3_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR3_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR3_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR3_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR3_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR3_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR3_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR3_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR3_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR3_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR3_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR3_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR3_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR3_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR3_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR3_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR3_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR3_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR3_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR3_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR3_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR3_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR3_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR3_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR3_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR3_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR3_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR3_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR3_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR3_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR3_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR3_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR3_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR3_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR3_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR3_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR3_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR3_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR3_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR3_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR3_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR3_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR3_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR3_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR3_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR3_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR3_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR3_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR3_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR3_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR3_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR3_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR3_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR3_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR3_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR3_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR3_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR3_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR3_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR3_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR3_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR3_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR3_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR3_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR3_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR3_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR3_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR3_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR3_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR3_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR3_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR3_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR3_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR3_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR3_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR3_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR3_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR3_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR3_SEC1BB31 = 0x80000000

	// SEC1BBR4: FLASH secure block based bank 1 register 4
	// Position of SEC1BB0 field.
	Flash_SEC1BBR4_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR4_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR4_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR4_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR4_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR4_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR4_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR4_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR4_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR4_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR4_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR4_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR4_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR4_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR4_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR4_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR4_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR4_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR4_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR4_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR4_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR4_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR4_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR4_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR4_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR4_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR4_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR4_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR4_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR4_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR4_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR4_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR4_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR4_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR4_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR4_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR4_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR4_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR4_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR4_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR4_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR4_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR4_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR4_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR4_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR4_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR4_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR4_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR4_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR4_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR4_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR4_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR4_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR4_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR4_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR4_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR4_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR4_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR4_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR4_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR4_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR4_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR4_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR4_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR4_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR4_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR4_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR4_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR4_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR4_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR4_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR4_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR4_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR4_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR4_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR4_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR4_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR4_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR4_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR4_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR4_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR4_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR4_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR4_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR4_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR4_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR4_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR4_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR4_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR4_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR4_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR4_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR4_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR4_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR4_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR4_SEC1BB31 = 0x80000000

	// SEC1BBR5: FLASH secure block based bank 1 register 5
	// Position of SEC1BB0 field.
	Flash_SEC1BBR5_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR5_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR5_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR5_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR5_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR5_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR5_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR5_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR5_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR5_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR5_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR5_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR5_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR5_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR5_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR5_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR5_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR5_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR5_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR5_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR5_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR5_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR5_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR5_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR5_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR5_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR5_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR5_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR5_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR5_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR5_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR5_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR5_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR5_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR5_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR5_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR5_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR5_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR5_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR5_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR5_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR5_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR5_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR5_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR5_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR5_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR5_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR5_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR5_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR5_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR5_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR5_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR5_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR5_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR5_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR5_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR5_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR5_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR5_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR5_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR5_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR5_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR5_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR5_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR5_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR5_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR5_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR5_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR5_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR5_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR5_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR5_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR5_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR5_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR5_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR5_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR5_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR5_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR5_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR5_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR5_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR5_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR5_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR5_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR5_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR5_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR5_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR5_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR5_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR5_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR5_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR5_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR5_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR5_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR5_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR5_SEC1BB31 = 0x80000000

	// SEC1BBR6: FLASH secure block based bank 1 register 6
	// Position of SEC1BB0 field.
	Flash_SEC1BBR6_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR6_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR6_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR6_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR6_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR6_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR6_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR6_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR6_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR6_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR6_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR6_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR6_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR6_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR6_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR6_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR6_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR6_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR6_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR6_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR6_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR6_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR6_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR6_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR6_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR6_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR6_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR6_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR6_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR6_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR6_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR6_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR6_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR6_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR6_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR6_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR6_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR6_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR6_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR6_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR6_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR6_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR6_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR6_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR6_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR6_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR6_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR6_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR6_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR6_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR6_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR6_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR6_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR6_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR6_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR6_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR6_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR6_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR6_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR6_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR6_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR6_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR6_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR6_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR6_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR6_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR6_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR6_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR6_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR6_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR6_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR6_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR6_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR6_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR6_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR6_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR6_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR6_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR6_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR6_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR6_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR6_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR6_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR6_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR6_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR6_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR6_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR6_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR6_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR6_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR6_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR6_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR6_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR6_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR6_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR6_SEC1BB31 = 0x80000000

	// SEC1BBR7: FLASH secure block based bank 1 register 7
	// Position of SEC1BB0 field.
	Flash_SEC1BBR7_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR7_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR7_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR7_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR7_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR7_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR7_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR7_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR7_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR7_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR7_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR7_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR7_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR7_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR7_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR7_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR7_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR7_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR7_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR7_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR7_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR7_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR7_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR7_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR7_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR7_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR7_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR7_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR7_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR7_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR7_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR7_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR7_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR7_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR7_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR7_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR7_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR7_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR7_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR7_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR7_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR7_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR7_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR7_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR7_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR7_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR7_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR7_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR7_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR7_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR7_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR7_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR7_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR7_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR7_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR7_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR7_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR7_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR7_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR7_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR7_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR7_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR7_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR7_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR7_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR7_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR7_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR7_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR7_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR7_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR7_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR7_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR7_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR7_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR7_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR7_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR7_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR7_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR7_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR7_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR7_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR7_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR7_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR7_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR7_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR7_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR7_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR7_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR7_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR7_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR7_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR7_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR7_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR7_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR7_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR7_SEC1BB31 = 0x80000000

	// SEC1BBR8: FLASH secure block based bank 1 register 8
	// Position of SEC1BB0 field.
	Flash_SEC1BBR8_SEC1BB0_Pos = 0x0
	// Bit mask of SEC1BB0 field.
	Flash_SEC1BBR8_SEC1BB0_Msk = 0x1
	// Bit SEC1BB0.
	Flash_SEC1BBR8_SEC1BB0 = 0x1
	// Position of SEC1BB1 field.
	Flash_SEC1BBR8_SEC1BB1_Pos = 0x1
	// Bit mask of SEC1BB1 field.
	Flash_SEC1BBR8_SEC1BB1_Msk = 0x2
	// Bit SEC1BB1.
	Flash_SEC1BBR8_SEC1BB1 = 0x2
	// Position of SEC1BB2 field.
	Flash_SEC1BBR8_SEC1BB2_Pos = 0x2
	// Bit mask of SEC1BB2 field.
	Flash_SEC1BBR8_SEC1BB2_Msk = 0x4
	// Bit SEC1BB2.
	Flash_SEC1BBR8_SEC1BB2 = 0x4
	// Position of SEC1BB3 field.
	Flash_SEC1BBR8_SEC1BB3_Pos = 0x3
	// Bit mask of SEC1BB3 field.
	Flash_SEC1BBR8_SEC1BB3_Msk = 0x8
	// Bit SEC1BB3.
	Flash_SEC1BBR8_SEC1BB3 = 0x8
	// Position of SEC1BB4 field.
	Flash_SEC1BBR8_SEC1BB4_Pos = 0x4
	// Bit mask of SEC1BB4 field.
	Flash_SEC1BBR8_SEC1BB4_Msk = 0x10
	// Bit SEC1BB4.
	Flash_SEC1BBR8_SEC1BB4 = 0x10
	// Position of SEC1BB5 field.
	Flash_SEC1BBR8_SEC1BB5_Pos = 0x5
	// Bit mask of SEC1BB5 field.
	Flash_SEC1BBR8_SEC1BB5_Msk = 0x20
	// Bit SEC1BB5.
	Flash_SEC1BBR8_SEC1BB5 = 0x20
	// Position of SEC1BB6 field.
	Flash_SEC1BBR8_SEC1BB6_Pos = 0x6
	// Bit mask of SEC1BB6 field.
	Flash_SEC1BBR8_SEC1BB6_Msk = 0x40
	// Bit SEC1BB6.
	Flash_SEC1BBR8_SEC1BB6 = 0x40
	// Position of SEC1BB7 field.
	Flash_SEC1BBR8_SEC1BB7_Pos = 0x7
	// Bit mask of SEC1BB7 field.
	Flash_SEC1BBR8_SEC1BB7_Msk = 0x80
	// Bit SEC1BB7.
	Flash_SEC1BBR8_SEC1BB7 = 0x80
	// Position of SEC1BB8 field.
	Flash_SEC1BBR8_SEC1BB8_Pos = 0x8
	// Bit mask of SEC1BB8 field.
	Flash_SEC1BBR8_SEC1BB8_Msk = 0x100
	// Bit SEC1BB8.
	Flash_SEC1BBR8_SEC1BB8 = 0x100
	// Position of SEC1BB9 field.
	Flash_SEC1BBR8_SEC1BB9_Pos = 0x9
	// Bit mask of SEC1BB9 field.
	Flash_SEC1BBR8_SEC1BB9_Msk = 0x200
	// Bit SEC1BB9.
	Flash_SEC1BBR8_SEC1BB9 = 0x200
	// Position of SEC1BB10 field.
	Flash_SEC1BBR8_SEC1BB10_Pos = 0xa
	// Bit mask of SEC1BB10 field.
	Flash_SEC1BBR8_SEC1BB10_Msk = 0x400
	// Bit SEC1BB10.
	Flash_SEC1BBR8_SEC1BB10 = 0x400
	// Position of SEC1BB11 field.
	Flash_SEC1BBR8_SEC1BB11_Pos = 0xb
	// Bit mask of SEC1BB11 field.
	Flash_SEC1BBR8_SEC1BB11_Msk = 0x800
	// Bit SEC1BB11.
	Flash_SEC1BBR8_SEC1BB11 = 0x800
	// Position of SEC1BB12 field.
	Flash_SEC1BBR8_SEC1BB12_Pos = 0xc
	// Bit mask of SEC1BB12 field.
	Flash_SEC1BBR8_SEC1BB12_Msk = 0x1000
	// Bit SEC1BB12.
	Flash_SEC1BBR8_SEC1BB12 = 0x1000
	// Position of SEC1BB13 field.
	Flash_SEC1BBR8_SEC1BB13_Pos = 0xd
	// Bit mask of SEC1BB13 field.
	Flash_SEC1BBR8_SEC1BB13_Msk = 0x2000
	// Bit SEC1BB13.
	Flash_SEC1BBR8_SEC1BB13 = 0x2000
	// Position of SEC1BB14 field.
	Flash_SEC1BBR8_SEC1BB14_Pos = 0xe
	// Bit mask of SEC1BB14 field.
	Flash_SEC1BBR8_SEC1BB14_Msk = 0x4000
	// Bit SEC1BB14.
	Flash_SEC1BBR8_SEC1BB14 = 0x4000
	// Position of SEC1BB15 field.
	Flash_SEC1BBR8_SEC1BB15_Pos = 0xf
	// Bit mask of SEC1BB15 field.
	Flash_SEC1BBR8_SEC1BB15_Msk = 0x8000
	// Bit SEC1BB15.
	Flash_SEC1BBR8_SEC1BB15 = 0x8000
	// Position of SEC1BB16 field.
	Flash_SEC1BBR8_SEC1BB16_Pos = 0x10
	// Bit mask of SEC1BB16 field.
	Flash_SEC1BBR8_SEC1BB16_Msk = 0x10000
	// Bit SEC1BB16.
	Flash_SEC1BBR8_SEC1BB16 = 0x10000
	// Position of SEC1BB17 field.
	Flash_SEC1BBR8_SEC1BB17_Pos = 0x11
	// Bit mask of SEC1BB17 field.
	Flash_SEC1BBR8_SEC1BB17_Msk = 0x20000
	// Bit SEC1BB17.
	Flash_SEC1BBR8_SEC1BB17 = 0x20000
	// Position of SEC1BB18 field.
	Flash_SEC1BBR8_SEC1BB18_Pos = 0x12
	// Bit mask of SEC1BB18 field.
	Flash_SEC1BBR8_SEC1BB18_Msk = 0x40000
	// Bit SEC1BB18.
	Flash_SEC1BBR8_SEC1BB18 = 0x40000
	// Position of SEC1BB19 field.
	Flash_SEC1BBR8_SEC1BB19_Pos = 0x13
	// Bit mask of SEC1BB19 field.
	Flash_SEC1BBR8_SEC1BB19_Msk = 0x80000
	// Bit SEC1BB19.
	Flash_SEC1BBR8_SEC1BB19 = 0x80000
	// Position of SEC1BB20 field.
	Flash_SEC1BBR8_SEC1BB20_Pos = 0x14
	// Bit mask of SEC1BB20 field.
	Flash_SEC1BBR8_SEC1BB20_Msk = 0x100000
	// Bit SEC1BB20.
	Flash_SEC1BBR8_SEC1BB20 = 0x100000
	// Position of SEC1BB21 field.
	Flash_SEC1BBR8_SEC1BB21_Pos = 0x15
	// Bit mask of SEC1BB21 field.
	Flash_SEC1BBR8_SEC1BB21_Msk = 0x200000
	// Bit SEC1BB21.
	Flash_SEC1BBR8_SEC1BB21 = 0x200000
	// Position of SEC1BB22 field.
	Flash_SEC1BBR8_SEC1BB22_Pos = 0x16
	// Bit mask of SEC1BB22 field.
	Flash_SEC1BBR8_SEC1BB22_Msk = 0x400000
	// Bit SEC1BB22.
	Flash_SEC1BBR8_SEC1BB22 = 0x400000
	// Position of SEC1BB23 field.
	Flash_SEC1BBR8_SEC1BB23_Pos = 0x17
	// Bit mask of SEC1BB23 field.
	Flash_SEC1BBR8_SEC1BB23_Msk = 0x800000
	// Bit SEC1BB23.
	Flash_SEC1BBR8_SEC1BB23 = 0x800000
	// Position of SEC1BB24 field.
	Flash_SEC1BBR8_SEC1BB24_Pos = 0x18
	// Bit mask of SEC1BB24 field.
	Flash_SEC1BBR8_SEC1BB24_Msk = 0x1000000
	// Bit SEC1BB24.
	Flash_SEC1BBR8_SEC1BB24 = 0x1000000
	// Position of SEC1BB25 field.
	Flash_SEC1BBR8_SEC1BB25_Pos = 0x19
	// Bit mask of SEC1BB25 field.
	Flash_SEC1BBR8_SEC1BB25_Msk = 0x2000000
	// Bit SEC1BB25.
	Flash_SEC1BBR8_SEC1BB25 = 0x2000000
	// Position of SEC1BB26 field.
	Flash_SEC1BBR8_SEC1BB26_Pos = 0x1a
	// Bit mask of SEC1BB26 field.
	Flash_SEC1BBR8_SEC1BB26_Msk = 0x4000000
	// Bit SEC1BB26.
	Flash_SEC1BBR8_SEC1BB26 = 0x4000000
	// Position of SEC1BB27 field.
	Flash_SEC1BBR8_SEC1BB27_Pos = 0x1b
	// Bit mask of SEC1BB27 field.
	Flash_SEC1BBR8_SEC1BB27_Msk = 0x8000000
	// Bit SEC1BB27.
	Flash_SEC1BBR8_SEC1BB27 = 0x8000000
	// Position of SEC1BB28 field.
	Flash_SEC1BBR8_SEC1BB28_Pos = 0x1c
	// Bit mask of SEC1BB28 field.
	Flash_SEC1BBR8_SEC1BB28_Msk = 0x10000000
	// Bit SEC1BB28.
	Flash_SEC1BBR8_SEC1BB28 = 0x10000000
	// Position of SEC1BB29 field.
	Flash_SEC1BBR8_SEC1BB29_Pos = 0x1d
	// Bit mask of SEC1BB29 field.
	Flash_SEC1BBR8_SEC1BB29_Msk = 0x20000000
	// Bit SEC1BB29.
	Flash_SEC1BBR8_SEC1BB29 = 0x20000000
	// Position of SEC1BB30 field.
	Flash_SEC1BBR8_SEC1BB30_Pos = 0x1e
	// Bit mask of SEC1BB30 field.
	Flash_SEC1BBR8_SEC1BB30_Msk = 0x40000000
	// Bit SEC1BB30.
	Flash_SEC1BBR8_SEC1BB30 = 0x40000000
	// Position of SEC1BB31 field.
	Flash_SEC1BBR8_SEC1BB31_Pos = 0x1f
	// Bit mask of SEC1BB31 field.
	Flash_SEC1BBR8_SEC1BB31_Msk = 0x80000000
	// Bit SEC1BB31.
	Flash_SEC1BBR8_SEC1BB31 = 0x80000000

	// SEC2BBR1: FLASH secure block based bank 2 register 1
	// Position of SEC2BB0 field.
	Flash_SEC2BBR1_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR1_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR1_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR1_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR1_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR1_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR1_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR1_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR1_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR1_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR1_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR1_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR1_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR1_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR1_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR1_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR1_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR1_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR1_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR1_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR1_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR1_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR1_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR1_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR1_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR1_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR1_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR1_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR1_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR1_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR1_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR1_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR1_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR1_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR1_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR1_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR1_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR1_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR1_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR1_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR1_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR1_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR1_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR1_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR1_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR1_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR1_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR1_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR1_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR1_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR1_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR1_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR1_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR1_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR1_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR1_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR1_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR1_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR1_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR1_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR1_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR1_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR1_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR1_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR1_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR1_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR1_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR1_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR1_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR1_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR1_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR1_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR1_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR1_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR1_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR1_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR1_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR1_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR1_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR1_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR1_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR1_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR1_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR1_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR1_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR1_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR1_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR1_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR1_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR1_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR1_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR1_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR1_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR1_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR1_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR1_SEC2BB31 = 0x80000000

	// SEC2BBR2: FLASH secure block based bank 2 register 2
	// Position of SEC2BB0 field.
	Flash_SEC2BBR2_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR2_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR2_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR2_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR2_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR2_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR2_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR2_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR2_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR2_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR2_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR2_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR2_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR2_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR2_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR2_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR2_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR2_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR2_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR2_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR2_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR2_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR2_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR2_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR2_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR2_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR2_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR2_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR2_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR2_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR2_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR2_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR2_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR2_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR2_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR2_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR2_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR2_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR2_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR2_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR2_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR2_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR2_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR2_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR2_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR2_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR2_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR2_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR2_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR2_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR2_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR2_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR2_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR2_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR2_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR2_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR2_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR2_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR2_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR2_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR2_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR2_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR2_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR2_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR2_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR2_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR2_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR2_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR2_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR2_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR2_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR2_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR2_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR2_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR2_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR2_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR2_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR2_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR2_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR2_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR2_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR2_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR2_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR2_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR2_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR2_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR2_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR2_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR2_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR2_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR2_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR2_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR2_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR2_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR2_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR2_SEC2BB31 = 0x80000000

	// SEC2BBR3: FLASH secure block based bank 2 register 3
	// Position of SEC2BB0 field.
	Flash_SEC2BBR3_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR3_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR3_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR3_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR3_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR3_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR3_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR3_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR3_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR3_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR3_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR3_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR3_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR3_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR3_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR3_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR3_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR3_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR3_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR3_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR3_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR3_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR3_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR3_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR3_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR3_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR3_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR3_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR3_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR3_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR3_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR3_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR3_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR3_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR3_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR3_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR3_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR3_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR3_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR3_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR3_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR3_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR3_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR3_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR3_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR3_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR3_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR3_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR3_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR3_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR3_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR3_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR3_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR3_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR3_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR3_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR3_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR3_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR3_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR3_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR3_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR3_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR3_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR3_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR3_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR3_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR3_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR3_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR3_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR3_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR3_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR3_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR3_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR3_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR3_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR3_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR3_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR3_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR3_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR3_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR3_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR3_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR3_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR3_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR3_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR3_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR3_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR3_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR3_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR3_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR3_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR3_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR3_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR3_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR3_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR3_SEC2BB31 = 0x80000000

	// SEC2BBR4: FLASH secure block based bank 2 register 4
	// Position of SEC2BB0 field.
	Flash_SEC2BBR4_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR4_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR4_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR4_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR4_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR4_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR4_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR4_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR4_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR4_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR4_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR4_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR4_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR4_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR4_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR4_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR4_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR4_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR4_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR4_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR4_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR4_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR4_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR4_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR4_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR4_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR4_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR4_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR4_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR4_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR4_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR4_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR4_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR4_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR4_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR4_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR4_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR4_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR4_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR4_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR4_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR4_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR4_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR4_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR4_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR4_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR4_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR4_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR4_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR4_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR4_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR4_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR4_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR4_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR4_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR4_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR4_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR4_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR4_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR4_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR4_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR4_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR4_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR4_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR4_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR4_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR4_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR4_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR4_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR4_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR4_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR4_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR4_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR4_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR4_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR4_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR4_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR4_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR4_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR4_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR4_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR4_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR4_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR4_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR4_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR4_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR4_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR4_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR4_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR4_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR4_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR4_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR4_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR4_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR4_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR4_SEC2BB31 = 0x80000000

	// SEC2BBR5: FLASH secure block based bank 2 register 5
	// Position of SEC2BB0 field.
	Flash_SEC2BBR5_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR5_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR5_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR5_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR5_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR5_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR5_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR5_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR5_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR5_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR5_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR5_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR5_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR5_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR5_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR5_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR5_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR5_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR5_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR5_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR5_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR5_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR5_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR5_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR5_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR5_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR5_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR5_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR5_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR5_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR5_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR5_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR5_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR5_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR5_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR5_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR5_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR5_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR5_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR5_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR5_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR5_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR5_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR5_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR5_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR5_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR5_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR5_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR5_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR5_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR5_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR5_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR5_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR5_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR5_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR5_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR5_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR5_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR5_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR5_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR5_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR5_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR5_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR5_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR5_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR5_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR5_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR5_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR5_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR5_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR5_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR5_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR5_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR5_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR5_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR5_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR5_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR5_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR5_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR5_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR5_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR5_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR5_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR5_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR5_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR5_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR5_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR5_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR5_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR5_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR5_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR5_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR5_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR5_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR5_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR5_SEC2BB31 = 0x80000000

	// SEC2BBR6: FLASH secure block based bank 2 register 6
	// Position of SEC2BB0 field.
	Flash_SEC2BBR6_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR6_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR6_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR6_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR6_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR6_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR6_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR6_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR6_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR6_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR6_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR6_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR6_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR6_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR6_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR6_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR6_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR6_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR6_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR6_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR6_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR6_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR6_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR6_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR6_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR6_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR6_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR6_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR6_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR6_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR6_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR6_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR6_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR6_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR6_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR6_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR6_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR6_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR6_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR6_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR6_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR6_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR6_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR6_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR6_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR6_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR6_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR6_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR6_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR6_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR6_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR6_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR6_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR6_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR6_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR6_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR6_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR6_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR6_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR6_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR6_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR6_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR6_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR6_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR6_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR6_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR6_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR6_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR6_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR6_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR6_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR6_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR6_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR6_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR6_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR6_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR6_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR6_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR6_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR6_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR6_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR6_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR6_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR6_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR6_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR6_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR6_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR6_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR6_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR6_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR6_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR6_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR6_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR6_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR6_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR6_SEC2BB31 = 0x80000000

	// SEC2BBR7: FLASH secure block based bank 2 register 7
	// Position of SEC2BB0 field.
	Flash_SEC2BBR7_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR7_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR7_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR7_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR7_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR7_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR7_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR7_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR7_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR7_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR7_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR7_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR7_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR7_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR7_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR7_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR7_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR7_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR7_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR7_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR7_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR7_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR7_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR7_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR7_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR7_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR7_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR7_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR7_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR7_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR7_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR7_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR7_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR7_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR7_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR7_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR7_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR7_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR7_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR7_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR7_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR7_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR7_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR7_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR7_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR7_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR7_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR7_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR7_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR7_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR7_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR7_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR7_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR7_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR7_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR7_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR7_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR7_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR7_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR7_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR7_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR7_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR7_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR7_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR7_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR7_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR7_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR7_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR7_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR7_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR7_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR7_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR7_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR7_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR7_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR7_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR7_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR7_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR7_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR7_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR7_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR7_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR7_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR7_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR7_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR7_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR7_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR7_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR7_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR7_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR7_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR7_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR7_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR7_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR7_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR7_SEC2BB31 = 0x80000000

	// SEC2BBR8: FLASH secure block based bank 2 register 8
	// Position of SEC2BB0 field.
	Flash_SEC2BBR8_SEC2BB0_Pos = 0x0
	// Bit mask of SEC2BB0 field.
	Flash_SEC2BBR8_SEC2BB0_Msk = 0x1
	// Bit SEC2BB0.
	Flash_SEC2BBR8_SEC2BB0 = 0x1
	// Position of SEC2BB1 field.
	Flash_SEC2BBR8_SEC2BB1_Pos = 0x1
	// Bit mask of SEC2BB1 field.
	Flash_SEC2BBR8_SEC2BB1_Msk = 0x2
	// Bit SEC2BB1.
	Flash_SEC2BBR8_SEC2BB1 = 0x2
	// Position of SEC2BB2 field.
	Flash_SEC2BBR8_SEC2BB2_Pos = 0x2
	// Bit mask of SEC2BB2 field.
	Flash_SEC2BBR8_SEC2BB2_Msk = 0x4
	// Bit SEC2BB2.
	Flash_SEC2BBR8_SEC2BB2 = 0x4
	// Position of SEC2BB3 field.
	Flash_SEC2BBR8_SEC2BB3_Pos = 0x3
	// Bit mask of SEC2BB3 field.
	Flash_SEC2BBR8_SEC2BB3_Msk = 0x8
	// Bit SEC2BB3.
	Flash_SEC2BBR8_SEC2BB3 = 0x8
	// Position of SEC2BB4 field.
	Flash_SEC2BBR8_SEC2BB4_Pos = 0x4
	// Bit mask of SEC2BB4 field.
	Flash_SEC2BBR8_SEC2BB4_Msk = 0x10
	// Bit SEC2BB4.
	Flash_SEC2BBR8_SEC2BB4 = 0x10
	// Position of SEC2BB5 field.
	Flash_SEC2BBR8_SEC2BB5_Pos = 0x5
	// Bit mask of SEC2BB5 field.
	Flash_SEC2BBR8_SEC2BB5_Msk = 0x20
	// Bit SEC2BB5.
	Flash_SEC2BBR8_SEC2BB5 = 0x20
	// Position of SEC2BB6 field.
	Flash_SEC2BBR8_SEC2BB6_Pos = 0x6
	// Bit mask of SEC2BB6 field.
	Flash_SEC2BBR8_SEC2BB6_Msk = 0x40
	// Bit SEC2BB6.
	Flash_SEC2BBR8_SEC2BB6 = 0x40
	// Position of SEC2BB7 field.
	Flash_SEC2BBR8_SEC2BB7_Pos = 0x7
	// Bit mask of SEC2BB7 field.
	Flash_SEC2BBR8_SEC2BB7_Msk = 0x80
	// Bit SEC2BB7.
	Flash_SEC2BBR8_SEC2BB7 = 0x80
	// Position of SEC2BB8 field.
	Flash_SEC2BBR8_SEC2BB8_Pos = 0x8
	// Bit mask of SEC2BB8 field.
	Flash_SEC2BBR8_SEC2BB8_Msk = 0x100
	// Bit SEC2BB8.
	Flash_SEC2BBR8_SEC2BB8 = 0x100
	// Position of SEC2BB9 field.
	Flash_SEC2BBR8_SEC2BB9_Pos = 0x9
	// Bit mask of SEC2BB9 field.
	Flash_SEC2BBR8_SEC2BB9_Msk = 0x200
	// Bit SEC2BB9.
	Flash_SEC2BBR8_SEC2BB9 = 0x200
	// Position of SEC2BB10 field.
	Flash_SEC2BBR8_SEC2BB10_Pos = 0xa
	// Bit mask of SEC2BB10 field.
	Flash_SEC2BBR8_SEC2BB10_Msk = 0x400
	// Bit SEC2BB10.
	Flash_SEC2BBR8_SEC2BB10 = 0x400
	// Position of SEC2BB11 field.
	Flash_SEC2BBR8_SEC2BB11_Pos = 0xb
	// Bit mask of SEC2BB11 field.
	Flash_SEC2BBR8_SEC2BB11_Msk = 0x800
	// Bit SEC2BB11.
	Flash_SEC2BBR8_SEC2BB11 = 0x800
	// Position of SEC2BB12 field.
	Flash_SEC2BBR8_SEC2BB12_Pos = 0xc
	// Bit mask of SEC2BB12 field.
	Flash_SEC2BBR8_SEC2BB12_Msk = 0x1000
	// Bit SEC2BB12.
	Flash_SEC2BBR8_SEC2BB12 = 0x1000
	// Position of SEC2BB13 field.
	Flash_SEC2BBR8_SEC2BB13_Pos = 0xd
	// Bit mask of SEC2BB13 field.
	Flash_SEC2BBR8_SEC2BB13_Msk = 0x2000
	// Bit SEC2BB13.
	Flash_SEC2BBR8_SEC2BB13 = 0x2000
	// Position of SEC2BB14 field.
	Flash_SEC2BBR8_SEC2BB14_Pos = 0xe
	// Bit mask of SEC2BB14 field.
	Flash_SEC2BBR8_SEC2BB14_Msk = 0x4000
	// Bit SEC2BB14.
	Flash_SEC2BBR8_SEC2BB14 = 0x4000
	// Position of SEC2BB15 field.
	Flash_SEC2BBR8_SEC2BB15_Pos = 0xf
	// Bit mask of SEC2BB15 field.
	Flash_SEC2BBR8_SEC2BB15_Msk = 0x8000
	// Bit SEC2BB15.
	Flash_SEC2BBR8_SEC2BB15 = 0x8000
	// Position of SEC2BB16 field.
	Flash_SEC2BBR8_SEC2BB16_Pos = 0x10
	// Bit mask of SEC2BB16 field.
	Flash_SEC2BBR8_SEC2BB16_Msk = 0x10000
	// Bit SEC2BB16.
	Flash_SEC2BBR8_SEC2BB16 = 0x10000
	// Position of SEC2BB17 field.
	Flash_SEC2BBR8_SEC2BB17_Pos = 0x11
	// Bit mask of SEC2BB17 field.
	Flash_SEC2BBR8_SEC2BB17_Msk = 0x20000
	// Bit SEC2BB17.
	Flash_SEC2BBR8_SEC2BB17 = 0x20000
	// Position of SEC2BB18 field.
	Flash_SEC2BBR8_SEC2BB18_Pos = 0x12
	// Bit mask of SEC2BB18 field.
	Flash_SEC2BBR8_SEC2BB18_Msk = 0x40000
	// Bit SEC2BB18.
	Flash_SEC2BBR8_SEC2BB18 = 0x40000
	// Position of SEC2BB19 field.
	Flash_SEC2BBR8_SEC2BB19_Pos = 0x13
	// Bit mask of SEC2BB19 field.
	Flash_SEC2BBR8_SEC2BB19_Msk = 0x80000
	// Bit SEC2BB19.
	Flash_SEC2BBR8_SEC2BB19 = 0x80000
	// Position of SEC2BB20 field.
	Flash_SEC2BBR8_SEC2BB20_Pos = 0x14
	// Bit mask of SEC2BB20 field.
	Flash_SEC2BBR8_SEC2BB20_Msk = 0x100000
	// Bit SEC2BB20.
	Flash_SEC2BBR8_SEC2BB20 = 0x100000
	// Position of SEC2BB21 field.
	Flash_SEC2BBR8_SEC2BB21_Pos = 0x15
	// Bit mask of SEC2BB21 field.
	Flash_SEC2BBR8_SEC2BB21_Msk = 0x200000
	// Bit SEC2BB21.
	Flash_SEC2BBR8_SEC2BB21 = 0x200000
	// Position of SEC2BB22 field.
	Flash_SEC2BBR8_SEC2BB22_Pos = 0x16
	// Bit mask of SEC2BB22 field.
	Flash_SEC2BBR8_SEC2BB22_Msk = 0x400000
	// Bit SEC2BB22.
	Flash_SEC2BBR8_SEC2BB22 = 0x400000
	// Position of SEC2BB23 field.
	Flash_SEC2BBR8_SEC2BB23_Pos = 0x17
	// Bit mask of SEC2BB23 field.
	Flash_SEC2BBR8_SEC2BB23_Msk = 0x800000
	// Bit SEC2BB23.
	Flash_SEC2BBR8_SEC2BB23 = 0x800000
	// Position of SEC2BB24 field.
	Flash_SEC2BBR8_SEC2BB24_Pos = 0x18
	// Bit mask of SEC2BB24 field.
	Flash_SEC2BBR8_SEC2BB24_Msk = 0x1000000
	// Bit SEC2BB24.
	Flash_SEC2BBR8_SEC2BB24 = 0x1000000
	// Position of SEC2BB25 field.
	Flash_SEC2BBR8_SEC2BB25_Pos = 0x19
	// Bit mask of SEC2BB25 field.
	Flash_SEC2BBR8_SEC2BB25_Msk = 0x2000000
	// Bit SEC2BB25.
	Flash_SEC2BBR8_SEC2BB25 = 0x2000000
	// Position of SEC2BB26 field.
	Flash_SEC2BBR8_SEC2BB26_Pos = 0x1a
	// Bit mask of SEC2BB26 field.
	Flash_SEC2BBR8_SEC2BB26_Msk = 0x4000000
	// Bit SEC2BB26.
	Flash_SEC2BBR8_SEC2BB26 = 0x4000000
	// Position of SEC2BB27 field.
	Flash_SEC2BBR8_SEC2BB27_Pos = 0x1b
	// Bit mask of SEC2BB27 field.
	Flash_SEC2BBR8_SEC2BB27_Msk = 0x8000000
	// Bit SEC2BB27.
	Flash_SEC2BBR8_SEC2BB27 = 0x8000000
	// Position of SEC2BB28 field.
	Flash_SEC2BBR8_SEC2BB28_Pos = 0x1c
	// Bit mask of SEC2BB28 field.
	Flash_SEC2BBR8_SEC2BB28_Msk = 0x10000000
	// Bit SEC2BB28.
	Flash_SEC2BBR8_SEC2BB28 = 0x10000000
	// Position of SEC2BB29 field.
	Flash_SEC2BBR8_SEC2BB29_Pos = 0x1d
	// Bit mask of SEC2BB29 field.
	Flash_SEC2BBR8_SEC2BB29_Msk = 0x20000000
	// Bit SEC2BB29.
	Flash_SEC2BBR8_SEC2BB29 = 0x20000000
	// Position of SEC2BB30 field.
	Flash_SEC2BBR8_SEC2BB30_Pos = 0x1e
	// Bit mask of SEC2BB30 field.
	Flash_SEC2BBR8_SEC2BB30_Msk = 0x40000000
	// Bit SEC2BB30.
	Flash_SEC2BBR8_SEC2BB30 = 0x40000000
	// Position of SEC2BB31 field.
	Flash_SEC2BBR8_SEC2BB31_Pos = 0x1f
	// Bit mask of SEC2BB31 field.
	Flash_SEC2BBR8_SEC2BB31_Msk = 0x80000000
	// Bit SEC2BB31.
	Flash_SEC2BBR8_SEC2BB31 = 0x80000000

	// SECHDPCR: FLASH secure HDP control register
	// Position of HDP1_ACCDIS field.
	Flash_SECHDPCR_HDP1_ACCDIS_Pos = 0x0
	// Bit mask of HDP1_ACCDIS field.
	Flash_SECHDPCR_HDP1_ACCDIS_Msk = 0x1
	// Bit HDP1_ACCDIS.
	Flash_SECHDPCR_HDP1_ACCDIS = 0x1
	// Position of HDP2_ACCDIS field.
	Flash_SECHDPCR_HDP2_ACCDIS_Pos = 0x1
	// Bit mask of HDP2_ACCDIS field.
	Flash_SECHDPCR_HDP2_ACCDIS_Msk = 0x2
	// Bit HDP2_ACCDIS.
	Flash_SECHDPCR_HDP2_ACCDIS = 0x2

	// PRIVCFGR: FLASH privilege configuration register
	// Position of SPRIV field.
	Flash_PRIVCFGR_SPRIV_Pos = 0x0
	// Bit mask of SPRIV field.
	Flash_PRIVCFGR_SPRIV_Msk = 0x1
	// Bit SPRIV.
	Flash_PRIVCFGR_SPRIV = 0x1
	// Position of NSPRIV field.
	Flash_PRIVCFGR_NSPRIV_Pos = 0x1
	// Bit mask of NSPRIV field.
	Flash_PRIVCFGR_NSPRIV_Msk = 0x2
	// Bit NSPRIV.
	Flash_PRIVCFGR_NSPRIV = 0x2

	// PRIV1BBR1: FLASH privilege block based bank 1 register 1
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR1_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR1_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR1_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR1_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR1_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR1_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR1_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR1_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR1_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR1_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR1_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR1_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR1_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR1_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR1_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR1_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR1_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR1_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR1_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR1_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR1_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR1_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR1_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR1_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR1_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR1_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR1_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR1_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR1_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR1_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR1_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR1_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR1_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR1_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR1_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR1_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR1_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR1_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR1_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR1_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR1_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR1_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR1_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR1_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR1_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR1_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR1_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR1_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR1_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR1_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR1_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR1_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR1_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR1_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR1_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR1_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR1_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR1_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR1_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR1_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR1_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR1_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR1_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR1_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR1_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR1_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR1_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR1_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR1_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR1_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR1_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR1_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR1_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR1_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR1_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR1_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR1_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR1_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR1_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR1_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR1_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR1_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR1_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR1_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR1_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR1_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR1_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR1_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR1_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR1_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR1_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR1_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR1_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR1_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR1_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR1_PRIV1BB31 = 0x80000000

	// PRIV1BBR2: FLASH privilege block based bank 1 register 2
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR2_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR2_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR2_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR2_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR2_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR2_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR2_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR2_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR2_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR2_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR2_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR2_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR2_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR2_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR2_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR2_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR2_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR2_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR2_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR2_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR2_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR2_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR2_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR2_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR2_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR2_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR2_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR2_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR2_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR2_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR2_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR2_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR2_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR2_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR2_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR2_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR2_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR2_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR2_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR2_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR2_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR2_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR2_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR2_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR2_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR2_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR2_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR2_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR2_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR2_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR2_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR2_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR2_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR2_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR2_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR2_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR2_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR2_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR2_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR2_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR2_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR2_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR2_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR2_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR2_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR2_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR2_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR2_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR2_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR2_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR2_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR2_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR2_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR2_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR2_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR2_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR2_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR2_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR2_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR2_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR2_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR2_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR2_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR2_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR2_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR2_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR2_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR2_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR2_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR2_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR2_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR2_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR2_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR2_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR2_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR2_PRIV1BB31 = 0x80000000

	// PRIV1BBR3: FLASH privilege block based bank 1 register 3
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR3_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR3_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR3_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR3_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR3_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR3_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR3_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR3_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR3_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR3_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR3_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR3_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR3_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR3_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR3_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR3_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR3_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR3_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR3_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR3_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR3_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR3_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR3_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR3_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR3_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR3_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR3_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR3_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR3_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR3_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR3_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR3_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR3_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR3_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR3_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR3_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR3_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR3_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR3_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR3_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR3_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR3_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR3_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR3_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR3_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR3_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR3_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR3_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR3_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR3_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR3_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR3_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR3_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR3_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR3_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR3_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR3_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR3_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR3_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR3_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR3_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR3_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR3_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR3_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR3_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR3_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR3_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR3_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR3_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR3_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR3_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR3_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR3_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR3_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR3_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR3_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR3_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR3_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR3_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR3_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR3_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR3_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR3_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR3_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR3_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR3_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR3_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR3_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR3_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR3_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR3_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR3_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR3_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR3_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR3_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR3_PRIV1BB31 = 0x80000000

	// PRIV1BBR4: FLASH privilege block based bank 1 register 4
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR4_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR4_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR4_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR4_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR4_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR4_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR4_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR4_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR4_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR4_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR4_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR4_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR4_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR4_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR4_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR4_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR4_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR4_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR4_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR4_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR4_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR4_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR4_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR4_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR4_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR4_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR4_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR4_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR4_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR4_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR4_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR4_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR4_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR4_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR4_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR4_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR4_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR4_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR4_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR4_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR4_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR4_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR4_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR4_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR4_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR4_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR4_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR4_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR4_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR4_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR4_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR4_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR4_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR4_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR4_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR4_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR4_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR4_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR4_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR4_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR4_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR4_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR4_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR4_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR4_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR4_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR4_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR4_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR4_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR4_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR4_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR4_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR4_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR4_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR4_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR4_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR4_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR4_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR4_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR4_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR4_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR4_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR4_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR4_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR4_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR4_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR4_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR4_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR4_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR4_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR4_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR4_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR4_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR4_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR4_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR4_PRIV1BB31 = 0x80000000

	// PRIV1BBR5: FLASH privilege block based bank 1 register 5
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR5_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR5_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR5_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR5_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR5_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR5_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR5_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR5_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR5_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR5_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR5_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR5_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR5_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR5_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR5_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR5_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR5_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR5_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR5_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR5_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR5_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR5_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR5_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR5_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR5_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR5_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR5_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR5_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR5_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR5_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR5_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR5_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR5_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR5_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR5_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR5_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR5_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR5_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR5_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR5_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR5_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR5_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR5_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR5_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR5_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR5_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR5_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR5_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR5_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR5_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR5_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR5_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR5_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR5_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR5_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR5_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR5_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR5_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR5_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR5_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR5_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR5_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR5_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR5_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR5_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR5_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR5_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR5_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR5_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR5_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR5_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR5_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR5_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR5_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR5_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR5_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR5_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR5_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR5_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR5_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR5_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR5_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR5_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR5_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR5_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR5_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR5_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR5_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR5_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR5_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR5_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR5_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR5_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR5_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR5_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR5_PRIV1BB31 = 0x80000000

	// PRIV1BBR6: FLASH privilege block based bank 1 register 6
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR6_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR6_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR6_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR6_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR6_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR6_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR6_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR6_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR6_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR6_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR6_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR6_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR6_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR6_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR6_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR6_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR6_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR6_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR6_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR6_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR6_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR6_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR6_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR6_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR6_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR6_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR6_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR6_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR6_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR6_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR6_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR6_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR6_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR6_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR6_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR6_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR6_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR6_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR6_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR6_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR6_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR6_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR6_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR6_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR6_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR6_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR6_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR6_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR6_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR6_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR6_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR6_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR6_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR6_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR6_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR6_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR6_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR6_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR6_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR6_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR6_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR6_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR6_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR6_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR6_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR6_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR6_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR6_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR6_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR6_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR6_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR6_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR6_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR6_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR6_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR6_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR6_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR6_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR6_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR6_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR6_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR6_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR6_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR6_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR6_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR6_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR6_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR6_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR6_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR6_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR6_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR6_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR6_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR6_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR6_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR6_PRIV1BB31 = 0x80000000

	// PRIV1BBR7: FLASH privilege block based bank 1 register 7
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR7_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR7_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR7_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR7_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR7_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR7_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR7_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR7_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR7_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR7_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR7_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR7_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR7_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR7_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR7_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR7_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR7_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR7_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR7_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR7_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR7_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR7_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR7_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR7_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR7_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR7_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR7_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR7_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR7_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR7_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR7_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR7_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR7_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR7_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR7_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR7_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR7_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR7_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR7_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR7_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR7_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR7_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR7_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR7_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR7_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR7_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR7_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR7_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR7_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR7_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR7_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR7_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR7_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR7_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR7_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR7_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR7_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR7_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR7_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR7_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR7_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR7_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR7_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR7_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR7_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR7_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR7_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR7_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR7_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR7_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR7_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR7_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR7_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR7_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR7_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR7_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR7_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR7_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR7_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR7_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR7_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR7_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR7_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR7_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR7_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR7_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR7_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR7_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR7_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR7_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR7_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR7_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR7_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR7_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR7_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR7_PRIV1BB31 = 0x80000000

	// PRIV1BBR8: FLASH privilege block based bank 1 register 8
	// Position of PRIV1BB0 field.
	Flash_PRIV1BBR8_PRIV1BB0_Pos = 0x0
	// Bit mask of PRIV1BB0 field.
	Flash_PRIV1BBR8_PRIV1BB0_Msk = 0x1
	// Bit PRIV1BB0.
	Flash_PRIV1BBR8_PRIV1BB0 = 0x1
	// Position of PRIV1BB1 field.
	Flash_PRIV1BBR8_PRIV1BB1_Pos = 0x1
	// Bit mask of PRIV1BB1 field.
	Flash_PRIV1BBR8_PRIV1BB1_Msk = 0x2
	// Bit PRIV1BB1.
	Flash_PRIV1BBR8_PRIV1BB1 = 0x2
	// Position of PRIV1BB2 field.
	Flash_PRIV1BBR8_PRIV1BB2_Pos = 0x2
	// Bit mask of PRIV1BB2 field.
	Flash_PRIV1BBR8_PRIV1BB2_Msk = 0x4
	// Bit PRIV1BB2.
	Flash_PRIV1BBR8_PRIV1BB2 = 0x4
	// Position of PRIV1BB3 field.
	Flash_PRIV1BBR8_PRIV1BB3_Pos = 0x3
	// Bit mask of PRIV1BB3 field.
	Flash_PRIV1BBR8_PRIV1BB3_Msk = 0x8
	// Bit PRIV1BB3.
	Flash_PRIV1BBR8_PRIV1BB3 = 0x8
	// Position of PRIV1BB4 field.
	Flash_PRIV1BBR8_PRIV1BB4_Pos = 0x4
	// Bit mask of PRIV1BB4 field.
	Flash_PRIV1BBR8_PRIV1BB4_Msk = 0x10
	// Bit PRIV1BB4.
	Flash_PRIV1BBR8_PRIV1BB4 = 0x10
	// Position of PRIV1BB5 field.
	Flash_PRIV1BBR8_PRIV1BB5_Pos = 0x5
	// Bit mask of PRIV1BB5 field.
	Flash_PRIV1BBR8_PRIV1BB5_Msk = 0x20
	// Bit PRIV1BB5.
	Flash_PRIV1BBR8_PRIV1BB5 = 0x20
	// Position of PRIV1BB6 field.
	Flash_PRIV1BBR8_PRIV1BB6_Pos = 0x6
	// Bit mask of PRIV1BB6 field.
	Flash_PRIV1BBR8_PRIV1BB6_Msk = 0x40
	// Bit PRIV1BB6.
	Flash_PRIV1BBR8_PRIV1BB6 = 0x40
	// Position of PRIV1BB7 field.
	Flash_PRIV1BBR8_PRIV1BB7_Pos = 0x7
	// Bit mask of PRIV1BB7 field.
	Flash_PRIV1BBR8_PRIV1BB7_Msk = 0x80
	// Bit PRIV1BB7.
	Flash_PRIV1BBR8_PRIV1BB7 = 0x80
	// Position of PRIV1BB8 field.
	Flash_PRIV1BBR8_PRIV1BB8_Pos = 0x8
	// Bit mask of PRIV1BB8 field.
	Flash_PRIV1BBR8_PRIV1BB8_Msk = 0x100
	// Bit PRIV1BB8.
	Flash_PRIV1BBR8_PRIV1BB8 = 0x100
	// Position of PRIV1BB9 field.
	Flash_PRIV1BBR8_PRIV1BB9_Pos = 0x9
	// Bit mask of PRIV1BB9 field.
	Flash_PRIV1BBR8_PRIV1BB9_Msk = 0x200
	// Bit PRIV1BB9.
	Flash_PRIV1BBR8_PRIV1BB9 = 0x200
	// Position of PRIV1BB10 field.
	Flash_PRIV1BBR8_PRIV1BB10_Pos = 0xa
	// Bit mask of PRIV1BB10 field.
	Flash_PRIV1BBR8_PRIV1BB10_Msk = 0x400
	// Bit PRIV1BB10.
	Flash_PRIV1BBR8_PRIV1BB10 = 0x400
	// Position of PRIV1BB11 field.
	Flash_PRIV1BBR8_PRIV1BB11_Pos = 0xb
	// Bit mask of PRIV1BB11 field.
	Flash_PRIV1BBR8_PRIV1BB11_Msk = 0x800
	// Bit PRIV1BB11.
	Flash_PRIV1BBR8_PRIV1BB11 = 0x800
	// Position of PRIV1BB12 field.
	Flash_PRIV1BBR8_PRIV1BB12_Pos = 0xc
	// Bit mask of PRIV1BB12 field.
	Flash_PRIV1BBR8_PRIV1BB12_Msk = 0x1000
	// Bit PRIV1BB12.
	Flash_PRIV1BBR8_PRIV1BB12 = 0x1000
	// Position of PRIV1BB13 field.
	Flash_PRIV1BBR8_PRIV1BB13_Pos = 0xd
	// Bit mask of PRIV1BB13 field.
	Flash_PRIV1BBR8_PRIV1BB13_Msk = 0x2000
	// Bit PRIV1BB13.
	Flash_PRIV1BBR8_PRIV1BB13 = 0x2000
	// Position of PRIV1BB14 field.
	Flash_PRIV1BBR8_PRIV1BB14_Pos = 0xe
	// Bit mask of PRIV1BB14 field.
	Flash_PRIV1BBR8_PRIV1BB14_Msk = 0x4000
	// Bit PRIV1BB14.
	Flash_PRIV1BBR8_PRIV1BB14 = 0x4000
	// Position of PRIV1BB15 field.
	Flash_PRIV1BBR8_PRIV1BB15_Pos = 0xf
	// Bit mask of PRIV1BB15 field.
	Flash_PRIV1BBR8_PRIV1BB15_Msk = 0x8000
	// Bit PRIV1BB15.
	Flash_PRIV1BBR8_PRIV1BB15 = 0x8000
	// Position of PRIV1BB16 field.
	Flash_PRIV1BBR8_PRIV1BB16_Pos = 0x10
	// Bit mask of PRIV1BB16 field.
	Flash_PRIV1BBR8_PRIV1BB16_Msk = 0x10000
	// Bit PRIV1BB16.
	Flash_PRIV1BBR8_PRIV1BB16 = 0x10000
	// Position of PRIV1BB17 field.
	Flash_PRIV1BBR8_PRIV1BB17_Pos = 0x11
	// Bit mask of PRIV1BB17 field.
	Flash_PRIV1BBR8_PRIV1BB17_Msk = 0x20000
	// Bit PRIV1BB17.
	Flash_PRIV1BBR8_PRIV1BB17 = 0x20000
	// Position of PRIV1BB18 field.
	Flash_PRIV1BBR8_PRIV1BB18_Pos = 0x12
	// Bit mask of PRIV1BB18 field.
	Flash_PRIV1BBR8_PRIV1BB18_Msk = 0x40000
	// Bit PRIV1BB18.
	Flash_PRIV1BBR8_PRIV1BB18 = 0x40000
	// Position of PRIV1BB19 field.
	Flash_PRIV1BBR8_PRIV1BB19_Pos = 0x13
	// Bit mask of PRIV1BB19 field.
	Flash_PRIV1BBR8_PRIV1BB19_Msk = 0x80000
	// Bit PRIV1BB19.
	Flash_PRIV1BBR8_PRIV1BB19 = 0x80000
	// Position of PRIV1BB20 field.
	Flash_PRIV1BBR8_PRIV1BB20_Pos = 0x14
	// Bit mask of PRIV1BB20 field.
	Flash_PRIV1BBR8_PRIV1BB20_Msk = 0x100000
	// Bit PRIV1BB20.
	Flash_PRIV1BBR8_PRIV1BB20 = 0x100000
	// Position of PRIV1BB21 field.
	Flash_PRIV1BBR8_PRIV1BB21_Pos = 0x15
	// Bit mask of PRIV1BB21 field.
	Flash_PRIV1BBR8_PRIV1BB21_Msk = 0x200000
	// Bit PRIV1BB21.
	Flash_PRIV1BBR8_PRIV1BB21 = 0x200000
	// Position of PRIV1BB22 field.
	Flash_PRIV1BBR8_PRIV1BB22_Pos = 0x16
	// Bit mask of PRIV1BB22 field.
	Flash_PRIV1BBR8_PRIV1BB22_Msk = 0x400000
	// Bit PRIV1BB22.
	Flash_PRIV1BBR8_PRIV1BB22 = 0x400000
	// Position of PRIV1BB23 field.
	Flash_PRIV1BBR8_PRIV1BB23_Pos = 0x17
	// Bit mask of PRIV1BB23 field.
	Flash_PRIV1BBR8_PRIV1BB23_Msk = 0x800000
	// Bit PRIV1BB23.
	Flash_PRIV1BBR8_PRIV1BB23 = 0x800000
	// Position of PRIV1BB24 field.
	Flash_PRIV1BBR8_PRIV1BB24_Pos = 0x18
	// Bit mask of PRIV1BB24 field.
	Flash_PRIV1BBR8_PRIV1BB24_Msk = 0x1000000
	// Bit PRIV1BB24.
	Flash_PRIV1BBR8_PRIV1BB24 = 0x1000000
	// Position of PRIV1BB25 field.
	Flash_PRIV1BBR8_PRIV1BB25_Pos = 0x19
	// Bit mask of PRIV1BB25 field.
	Flash_PRIV1BBR8_PRIV1BB25_Msk = 0x2000000
	// Bit PRIV1BB25.
	Flash_PRIV1BBR8_PRIV1BB25 = 0x2000000
	// Position of PRIV1BB26 field.
	Flash_PRIV1BBR8_PRIV1BB26_Pos = 0x1a
	// Bit mask of PRIV1BB26 field.
	Flash_PRIV1BBR8_PRIV1BB26_Msk = 0x4000000
	// Bit PRIV1BB26.
	Flash_PRIV1BBR8_PRIV1BB26 = 0x4000000
	// Position of PRIV1BB27 field.
	Flash_PRIV1BBR8_PRIV1BB27_Pos = 0x1b
	// Bit mask of PRIV1BB27 field.
	Flash_PRIV1BBR8_PRIV1BB27_Msk = 0x8000000
	// Bit PRIV1BB27.
	Flash_PRIV1BBR8_PRIV1BB27 = 0x8000000
	// Position of PRIV1BB28 field.
	Flash_PRIV1BBR8_PRIV1BB28_Pos = 0x1c
	// Bit mask of PRIV1BB28 field.
	Flash_PRIV1BBR8_PRIV1BB28_Msk = 0x10000000
	// Bit PRIV1BB28.
	Flash_PRIV1BBR8_PRIV1BB28 = 0x10000000
	// Position of PRIV1BB29 field.
	Flash_PRIV1BBR8_PRIV1BB29_Pos = 0x1d
	// Bit mask of PRIV1BB29 field.
	Flash_PRIV1BBR8_PRIV1BB29_Msk = 0x20000000
	// Bit PRIV1BB29.
	Flash_PRIV1BBR8_PRIV1BB29 = 0x20000000
	// Position of PRIV1BB30 field.
	Flash_PRIV1BBR8_PRIV1BB30_Pos = 0x1e
	// Bit mask of PRIV1BB30 field.
	Flash_PRIV1BBR8_PRIV1BB30_Msk = 0x40000000
	// Bit PRIV1BB30.
	Flash_PRIV1BBR8_PRIV1BB30 = 0x40000000
	// Position of PRIV1BB31 field.
	Flash_PRIV1BBR8_PRIV1BB31_Pos = 0x1f
	// Bit mask of PRIV1BB31 field.
	Flash_PRIV1BBR8_PRIV1BB31_Msk = 0x80000000
	// Bit PRIV1BB31.
	Flash_PRIV1BBR8_PRIV1BB31 = 0x80000000

	// PRIV2BBR1: FLASH privilege block based bank 2 register 1
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR1_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR1_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR1_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR1_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR1_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR1_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR1_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR1_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR1_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR1_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR1_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR1_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR1_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR1_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR1_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR1_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR1_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR1_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR1_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR1_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR1_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR1_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR1_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR1_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR1_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR1_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR1_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR1_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR1_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR1_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR1_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR1_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR1_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR1_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR1_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR1_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR1_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR1_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR1_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR1_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR1_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR1_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR1_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR1_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR1_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR1_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR1_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR1_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR1_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR1_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR1_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR1_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR1_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR1_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR1_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR1_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR1_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR1_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR1_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR1_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR1_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR1_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR1_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR1_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR1_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR1_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR1_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR1_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR1_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR1_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR1_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR1_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR1_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR1_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR1_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR1_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR1_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR1_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR1_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR1_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR1_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR1_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR1_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR1_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR1_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR1_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR1_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR1_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR1_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR1_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR1_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR1_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR1_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR1_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR1_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR1_PRIV2BB31 = 0x80000000

	// PRIV2BBR2: FLASH privilege block based bank 2 register 2
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR2_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR2_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR2_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR2_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR2_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR2_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR2_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR2_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR2_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR2_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR2_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR2_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR2_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR2_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR2_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR2_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR2_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR2_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR2_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR2_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR2_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR2_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR2_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR2_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR2_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR2_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR2_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR2_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR2_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR2_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR2_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR2_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR2_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR2_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR2_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR2_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR2_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR2_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR2_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR2_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR2_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR2_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR2_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR2_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR2_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR2_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR2_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR2_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR2_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR2_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR2_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR2_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR2_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR2_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR2_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR2_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR2_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR2_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR2_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR2_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR2_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR2_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR2_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR2_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR2_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR2_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR2_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR2_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR2_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR2_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR2_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR2_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR2_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR2_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR2_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR2_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR2_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR2_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR2_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR2_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR2_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR2_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR2_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR2_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR2_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR2_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR2_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR2_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR2_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR2_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR2_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR2_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR2_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR2_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR2_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR2_PRIV2BB31 = 0x80000000

	// PRIV2BBR3: FLASH privilege block based bank 2 register 3
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR3_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR3_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR3_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR3_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR3_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR3_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR3_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR3_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR3_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR3_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR3_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR3_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR3_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR3_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR3_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR3_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR3_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR3_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR3_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR3_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR3_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR3_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR3_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR3_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR3_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR3_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR3_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR3_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR3_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR3_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR3_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR3_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR3_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR3_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR3_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR3_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR3_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR3_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR3_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR3_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR3_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR3_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR3_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR3_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR3_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR3_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR3_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR3_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR3_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR3_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR3_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR3_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR3_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR3_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR3_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR3_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR3_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR3_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR3_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR3_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR3_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR3_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR3_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR3_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR3_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR3_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR3_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR3_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR3_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR3_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR3_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR3_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR3_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR3_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR3_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR3_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR3_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR3_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR3_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR3_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR3_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR3_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR3_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR3_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR3_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR3_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR3_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR3_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR3_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR3_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR3_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR3_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR3_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR3_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR3_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR3_PRIV2BB31 = 0x80000000

	// PRIV2BBR4: FLASH privilege block based bank 2 register 4
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR4_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR4_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR4_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR4_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR4_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR4_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR4_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR4_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR4_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR4_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR4_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR4_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR4_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR4_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR4_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR4_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR4_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR4_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR4_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR4_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR4_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR4_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR4_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR4_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR4_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR4_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR4_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR4_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR4_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR4_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR4_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR4_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR4_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR4_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR4_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR4_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR4_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR4_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR4_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR4_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR4_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR4_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR4_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR4_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR4_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR4_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR4_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR4_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR4_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR4_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR4_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR4_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR4_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR4_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR4_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR4_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR4_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR4_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR4_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR4_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR4_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR4_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR4_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR4_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR4_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR4_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR4_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR4_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR4_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR4_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR4_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR4_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR4_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR4_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR4_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR4_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR4_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR4_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR4_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR4_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR4_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR4_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR4_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR4_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR4_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR4_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR4_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR4_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR4_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR4_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR4_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR4_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR4_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR4_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR4_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR4_PRIV2BB31 = 0x80000000

	// PRIV2BBR5: FLASH privilege block based bank 2 register 5
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR5_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR5_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR5_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR5_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR5_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR5_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR5_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR5_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR5_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR5_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR5_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR5_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR5_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR5_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR5_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR5_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR5_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR5_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR5_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR5_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR5_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR5_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR5_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR5_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR5_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR5_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR5_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR5_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR5_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR5_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR5_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR5_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR5_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR5_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR5_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR5_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR5_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR5_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR5_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR5_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR5_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR5_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR5_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR5_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR5_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR5_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR5_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR5_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR5_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR5_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR5_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR5_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR5_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR5_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR5_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR5_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR5_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR5_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR5_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR5_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR5_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR5_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR5_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR5_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR5_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR5_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR5_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR5_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR5_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR5_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR5_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR5_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR5_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR5_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR5_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR5_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR5_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR5_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR5_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR5_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR5_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR5_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR5_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR5_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR5_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR5_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR5_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR5_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR5_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR5_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR5_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR5_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR5_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR5_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR5_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR5_PRIV2BB31 = 0x80000000

	// PRIV2BBR6: FLASH privilege block based bank 2 register 6
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR6_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR6_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR6_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR6_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR6_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR6_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR6_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR6_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR6_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR6_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR6_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR6_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR6_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR6_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR6_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR6_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR6_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR6_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR6_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR6_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR6_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR6_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR6_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR6_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR6_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR6_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR6_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR6_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR6_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR6_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR6_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR6_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR6_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR6_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR6_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR6_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR6_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR6_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR6_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR6_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR6_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR6_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR6_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR6_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR6_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR6_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR6_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR6_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR6_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR6_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR6_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR6_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR6_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR6_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR6_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR6_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR6_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR6_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR6_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR6_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR6_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR6_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR6_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR6_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR6_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR6_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR6_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR6_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR6_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR6_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR6_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR6_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR6_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR6_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR6_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR6_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR6_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR6_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR6_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR6_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR6_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR6_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR6_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR6_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR6_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR6_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR6_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR6_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR6_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR6_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR6_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR6_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR6_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR6_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR6_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR6_PRIV2BB31 = 0x80000000

	// PRIV2BBR7: FLASH privilege block based bank 2 register 7
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR7_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR7_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR7_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR7_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR7_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR7_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR7_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR7_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR7_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR7_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR7_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR7_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR7_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR7_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR7_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR7_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR7_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR7_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR7_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR7_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR7_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR7_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR7_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR7_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR7_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR7_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR7_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR7_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR7_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR7_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR7_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR7_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR7_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR7_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR7_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR7_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR7_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR7_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR7_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR7_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR7_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR7_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR7_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR7_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR7_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR7_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR7_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR7_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR7_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR7_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR7_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR7_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR7_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR7_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR7_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR7_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR7_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR7_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR7_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR7_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR7_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR7_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR7_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR7_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR7_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR7_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR7_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR7_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR7_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR7_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR7_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR7_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR7_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR7_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR7_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR7_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR7_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR7_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR7_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR7_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR7_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR7_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR7_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR7_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR7_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR7_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR7_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR7_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR7_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR7_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR7_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR7_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR7_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR7_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR7_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR7_PRIV2BB31 = 0x80000000

	// PRIV2BBR8: FLASH privilege block based bank 2 register 8
	// Position of PRIV2BB0 field.
	Flash_PRIV2BBR8_PRIV2BB0_Pos = 0x0
	// Bit mask of PRIV2BB0 field.
	Flash_PRIV2BBR8_PRIV2BB0_Msk = 0x1
	// Bit PRIV2BB0.
	Flash_PRIV2BBR8_PRIV2BB0 = 0x1
	// Position of PRIV2BB1 field.
	Flash_PRIV2BBR8_PRIV2BB1_Pos = 0x1
	// Bit mask of PRIV2BB1 field.
	Flash_PRIV2BBR8_PRIV2BB1_Msk = 0x2
	// Bit PRIV2BB1.
	Flash_PRIV2BBR8_PRIV2BB1 = 0x2
	// Position of PRIV2BB2 field.
	Flash_PRIV2BBR8_PRIV2BB2_Pos = 0x2
	// Bit mask of PRIV2BB2 field.
	Flash_PRIV2BBR8_PRIV2BB2_Msk = 0x4
	// Bit PRIV2BB2.
	Flash_PRIV2BBR8_PRIV2BB2 = 0x4
	// Position of PRIV2BB3 field.
	Flash_PRIV2BBR8_PRIV2BB3_Pos = 0x3
	// Bit mask of PRIV2BB3 field.
	Flash_PRIV2BBR8_PRIV2BB3_Msk = 0x8
	// Bit PRIV2BB3.
	Flash_PRIV2BBR8_PRIV2BB3 = 0x8
	// Position of PRIV2BB4 field.
	Flash_PRIV2BBR8_PRIV2BB4_Pos = 0x4
	// Bit mask of PRIV2BB4 field.
	Flash_PRIV2BBR8_PRIV2BB4_Msk = 0x10
	// Bit PRIV2BB4.
	Flash_PRIV2BBR8_PRIV2BB4 = 0x10
	// Position of PRIV2BB5 field.
	Flash_PRIV2BBR8_PRIV2BB5_Pos = 0x5
	// Bit mask of PRIV2BB5 field.
	Flash_PRIV2BBR8_PRIV2BB5_Msk = 0x20
	// Bit PRIV2BB5.
	Flash_PRIV2BBR8_PRIV2BB5 = 0x20
	// Position of PRIV2BB6 field.
	Flash_PRIV2BBR8_PRIV2BB6_Pos = 0x6
	// Bit mask of PRIV2BB6 field.
	Flash_PRIV2BBR8_PRIV2BB6_Msk = 0x40
	// Bit PRIV2BB6.
	Flash_PRIV2BBR8_PRIV2BB6 = 0x40
	// Position of PRIV2BB7 field.
	Flash_PRIV2BBR8_PRIV2BB7_Pos = 0x7
	// Bit mask of PRIV2BB7 field.
	Flash_PRIV2BBR8_PRIV2BB7_Msk = 0x80
	// Bit PRIV2BB7.
	Flash_PRIV2BBR8_PRIV2BB7 = 0x80
	// Position of PRIV2BB8 field.
	Flash_PRIV2BBR8_PRIV2BB8_Pos = 0x8
	// Bit mask of PRIV2BB8 field.
	Flash_PRIV2BBR8_PRIV2BB8_Msk = 0x100
	// Bit PRIV2BB8.
	Flash_PRIV2BBR8_PRIV2BB8 = 0x100
	// Position of PRIV2BB9 field.
	Flash_PRIV2BBR8_PRIV2BB9_Pos = 0x9
	// Bit mask of PRIV2BB9 field.
	Flash_PRIV2BBR8_PRIV2BB9_Msk = 0x200
	// Bit PRIV2BB9.
	Flash_PRIV2BBR8_PRIV2BB9 = 0x200
	// Position of PRIV2BB10 field.
	Flash_PRIV2BBR8_PRIV2BB10_Pos = 0xa
	// Bit mask of PRIV2BB10 field.
	Flash_PRIV2BBR8_PRIV2BB10_Msk = 0x400
	// Bit PRIV2BB10.
	Flash_PRIV2BBR8_PRIV2BB10 = 0x400
	// Position of PRIV2BB11 field.
	Flash_PRIV2BBR8_PRIV2BB11_Pos = 0xb
	// Bit mask of PRIV2BB11 field.
	Flash_PRIV2BBR8_PRIV2BB11_Msk = 0x800
	// Bit PRIV2BB11.
	Flash_PRIV2BBR8_PRIV2BB11 = 0x800
	// Position of PRIV2BB12 field.
	Flash_PRIV2BBR8_PRIV2BB12_Pos = 0xc
	// Bit mask of PRIV2BB12 field.
	Flash_PRIV2BBR8_PRIV2BB12_Msk = 0x1000
	// Bit PRIV2BB12.
	Flash_PRIV2BBR8_PRIV2BB12 = 0x1000
	// Position of PRIV2BB13 field.
	Flash_PRIV2BBR8_PRIV2BB13_Pos = 0xd
	// Bit mask of PRIV2BB13 field.
	Flash_PRIV2BBR8_PRIV2BB13_Msk = 0x2000
	// Bit PRIV2BB13.
	Flash_PRIV2BBR8_PRIV2BB13 = 0x2000
	// Position of PRIV2BB14 field.
	Flash_PRIV2BBR8_PRIV2BB14_Pos = 0xe
	// Bit mask of PRIV2BB14 field.
	Flash_PRIV2BBR8_PRIV2BB14_Msk = 0x4000
	// Bit PRIV2BB14.
	Flash_PRIV2BBR8_PRIV2BB14 = 0x4000
	// Position of PRIV2BB15 field.
	Flash_PRIV2BBR8_PRIV2BB15_Pos = 0xf
	// Bit mask of PRIV2BB15 field.
	Flash_PRIV2BBR8_PRIV2BB15_Msk = 0x8000
	// Bit PRIV2BB15.
	Flash_PRIV2BBR8_PRIV2BB15 = 0x8000
	// Position of PRIV2BB16 field.
	Flash_PRIV2BBR8_PRIV2BB16_Pos = 0x10
	// Bit mask of PRIV2BB16 field.
	Flash_PRIV2BBR8_PRIV2BB16_Msk = 0x10000
	// Bit PRIV2BB16.
	Flash_PRIV2BBR8_PRIV2BB16 = 0x10000
	// Position of PRIV2BB17 field.
	Flash_PRIV2BBR8_PRIV2BB17_Pos = 0x11
	// Bit mask of PRIV2BB17 field.
	Flash_PRIV2BBR8_PRIV2BB17_Msk = 0x20000
	// Bit PRIV2BB17.
	Flash_PRIV2BBR8_PRIV2BB17 = 0x20000
	// Position of PRIV2BB18 field.
	Flash_PRIV2BBR8_PRIV2BB18_Pos = 0x12
	// Bit mask of PRIV2BB18 field.
	Flash_PRIV2BBR8_PRIV2BB18_Msk = 0x40000
	// Bit PRIV2BB18.
	Flash_PRIV2BBR8_PRIV2BB18 = 0x40000
	// Position of PRIV2BB19 field.
	Flash_PRIV2BBR8_PRIV2BB19_Pos = 0x13
	// Bit mask of PRIV2BB19 field.
	Flash_PRIV2BBR8_PRIV2BB19_Msk = 0x80000
	// Bit PRIV2BB19.
	Flash_PRIV2BBR8_PRIV2BB19 = 0x80000
	// Position of PRIV2BB20 field.
	Flash_PRIV2BBR8_PRIV2BB20_Pos = 0x14
	// Bit mask of PRIV2BB20 field.
	Flash_PRIV2BBR8_PRIV2BB20_Msk = 0x100000
	// Bit PRIV2BB20.
	Flash_PRIV2BBR8_PRIV2BB20 = 0x100000
	// Position of PRIV2BB21 field.
	Flash_PRIV2BBR8_PRIV2BB21_Pos = 0x15
	// Bit mask of PRIV2BB21 field.
	Flash_PRIV2BBR8_PRIV2BB21_Msk = 0x200000
	// Bit PRIV2BB21.
	Flash_PRIV2BBR8_PRIV2BB21 = 0x200000
	// Position of PRIV2BB22 field.
	Flash_PRIV2BBR8_PRIV2BB22_Pos = 0x16
	// Bit mask of PRIV2BB22 field.
	Flash_PRIV2BBR8_PRIV2BB22_Msk = 0x400000
	// Bit PRIV2BB22.
	Flash_PRIV2BBR8_PRIV2BB22 = 0x400000
	// Position of PRIV2BB23 field.
	Flash_PRIV2BBR8_PRIV2BB23_Pos = 0x17
	// Bit mask of PRIV2BB23 field.
	Flash_PRIV2BBR8_PRIV2BB23_Msk = 0x800000
	// Bit PRIV2BB23.
	Flash_PRIV2BBR8_PRIV2BB23 = 0x800000
	// Position of PRIV2BB24 field.
	Flash_PRIV2BBR8_PRIV2BB24_Pos = 0x18
	// Bit mask of PRIV2BB24 field.
	Flash_PRIV2BBR8_PRIV2BB24_Msk = 0x1000000
	// Bit PRIV2BB24.
	Flash_PRIV2BBR8_PRIV2BB24 = 0x1000000
	// Position of PRIV2BB25 field.
	Flash_PRIV2BBR8_PRIV2BB25_Pos = 0x19
	// Bit mask of PRIV2BB25 field.
	Flash_PRIV2BBR8_PRIV2BB25_Msk = 0x2000000
	// Bit PRIV2BB25.
	Flash_PRIV2BBR8_PRIV2BB25 = 0x2000000
	// Position of PRIV2BB26 field.
	Flash_PRIV2BBR8_PRIV2BB26_Pos = 0x1a
	// Bit mask of PRIV2BB26 field.
	Flash_PRIV2BBR8_PRIV2BB26_Msk = 0x4000000
	// Bit PRIV2BB26.
	Flash_PRIV2BBR8_PRIV2BB26 = 0x4000000
	// Position of PRIV2BB27 field.
	Flash_PRIV2BBR8_PRIV2BB27_Pos = 0x1b
	// Bit mask of PRIV2BB27 field.
	Flash_PRIV2BBR8_PRIV2BB27_Msk = 0x8000000
	// Bit PRIV2BB27.
	Flash_PRIV2BBR8_PRIV2BB27 = 0x8000000
	// Position of PRIV2BB28 field.
	Flash_PRIV2BBR8_PRIV2BB28_Pos = 0x1c
	// Bit mask of PRIV2BB28 field.
	Flash_PRIV2BBR8_PRIV2BB28_Msk = 0x10000000
	// Bit PRIV2BB28.
	Flash_PRIV2BBR8_PRIV2BB28 = 0x10000000
	// Position of PRIV2BB29 field.
	Flash_PRIV2BBR8_PRIV2BB29_Pos = 0x1d
	// Bit mask of PRIV2BB29 field.
	Flash_PRIV2BBR8_PRIV2BB29_Msk = 0x20000000
	// Bit PRIV2BB29.
	Flash_PRIV2BBR8_PRIV2BB29 = 0x20000000
	// Position of PRIV2BB30 field.
	Flash_PRIV2BBR8_PRIV2BB30_Pos = 0x1e
	// Bit mask of PRIV2BB30 field.
	Flash_PRIV2BBR8_PRIV2BB30_Msk = 0x40000000
	// Bit PRIV2BB30.
	Flash_PRIV2BBR8_PRIV2BB30 = 0x40000000
	// Position of PRIV2BB31 field.
	Flash_PRIV2BBR8_PRIV2BB31_Pos = 0x1f
	// Bit mask of PRIV2BB31 field.
	Flash_PRIV2BBR8_PRIV2BB31_Msk = 0x80000000
	// Bit PRIV2BB31.
	Flash_PRIV2BBR8_PRIV2BB31 = 0x80000000
)

// Constants for FMAC: Filter Math Accelerator
const (
	// X1BUFCFG: FMAC X1 Buffer Configuration register
	// Position of X1_BASE field.
	FMAC_X1BUFCFG_X1_BASE_Pos = 0x0
	// Bit mask of X1_BASE field.
	FMAC_X1BUFCFG_X1_BASE_Msk = 0xff
	// Position of X1_BUF_SIZE field.
	FMAC_X1BUFCFG_X1_BUF_SIZE_Pos = 0x8
	// Bit mask of X1_BUF_SIZE field.
	FMAC_X1BUFCFG_X1_BUF_SIZE_Msk = 0xff00
	// Position of FULL_WM field.
	FMAC_X1BUFCFG_FULL_WM_Pos = 0x18
	// Bit mask of FULL_WM field.
	FMAC_X1BUFCFG_FULL_WM_Msk = 0x3000000

	// X2BUFCFG: FMAC X2 Buffer Configuration register
	// Position of X2_BASE field.
	FMAC_X2BUFCFG_X2_BASE_Pos = 0x0
	// Bit mask of X2_BASE field.
	FMAC_X2BUFCFG_X2_BASE_Msk = 0xff
	// Position of X2_BUF_SIZE field.
	FMAC_X2BUFCFG_X2_BUF_SIZE_Pos = 0x8
	// Bit mask of X2_BUF_SIZE field.
	FMAC_X2BUFCFG_X2_BUF_SIZE_Msk = 0xff00

	// YBUFCFG: FMAC Y Buffer Configuration register
	// Position of Y_BASE field.
	FMAC_YBUFCFG_Y_BASE_Pos = 0x0
	// Bit mask of Y_BASE field.
	FMAC_YBUFCFG_Y_BASE_Msk = 0xff
	// Position of Y_BUF_SIZE field.
	FMAC_YBUFCFG_Y_BUF_SIZE_Pos = 0x8
	// Bit mask of Y_BUF_SIZE field.
	FMAC_YBUFCFG_Y_BUF_SIZE_Msk = 0xff00
	// Position of EMPTY_WM field.
	FMAC_YBUFCFG_EMPTY_WM_Pos = 0x18
	// Bit mask of EMPTY_WM field.
	FMAC_YBUFCFG_EMPTY_WM_Msk = 0x3000000

	// PARAM: FMAC Parameter register
	// Position of START field.
	FMAC_PARAM_START_Pos = 0x1f
	// Bit mask of START field.
	FMAC_PARAM_START_Msk = 0x80000000
	// Bit START.
	FMAC_PARAM_START = 0x80000000
	// Position of FUNC field.
	FMAC_PARAM_FUNC_Pos = 0x18
	// Bit mask of FUNC field.
	FMAC_PARAM_FUNC_Msk = 0x7f000000
	// Position of R field.
	FMAC_PARAM_R_Pos = 0x10
	// Bit mask of R field.
	FMAC_PARAM_R_Msk = 0xff0000
	// Position of Q field.
	FMAC_PARAM_Q_Pos = 0x8
	// Bit mask of Q field.
	FMAC_PARAM_Q_Msk = 0xff00
	// Position of P field.
	FMAC_PARAM_P_Pos = 0x0
	// Bit mask of P field.
	FMAC_PARAM_P_Msk = 0xff

	// CR: FMAC Control register
	// Position of RESET field.
	FMAC_CR_RESET_Pos = 0x10
	// Bit mask of RESET field.
	FMAC_CR_RESET_Msk = 0x10000
	// Bit RESET.
	FMAC_CR_RESET = 0x10000
	// Position of CLIPEN field.
	FMAC_CR_CLIPEN_Pos = 0xf
	// Bit mask of CLIPEN field.
	FMAC_CR_CLIPEN_Msk = 0x8000
	// Bit CLIPEN.
	FMAC_CR_CLIPEN = 0x8000
	// Position of DMAWEN field.
	FMAC_CR_DMAWEN_Pos = 0x9
	// Bit mask of DMAWEN field.
	FMAC_CR_DMAWEN_Msk = 0x200
	// Bit DMAWEN.
	FMAC_CR_DMAWEN = 0x200
	// Position of DMAREN field.
	FMAC_CR_DMAREN_Pos = 0x8
	// Bit mask of DMAREN field.
	FMAC_CR_DMAREN_Msk = 0x100
	// Bit DMAREN.
	FMAC_CR_DMAREN = 0x100
	// Position of SATIEN field.
	FMAC_CR_SATIEN_Pos = 0x4
	// Bit mask of SATIEN field.
	FMAC_CR_SATIEN_Msk = 0x10
	// Bit SATIEN.
	FMAC_CR_SATIEN = 0x10
	// Position of UNFLIEN field.
	FMAC_CR_UNFLIEN_Pos = 0x3
	// Bit mask of UNFLIEN field.
	FMAC_CR_UNFLIEN_Msk = 0x8
	// Bit UNFLIEN.
	FMAC_CR_UNFLIEN = 0x8
	// Position of OVFLIEN field.
	FMAC_CR_OVFLIEN_Pos = 0x2
	// Bit mask of OVFLIEN field.
	FMAC_CR_OVFLIEN_Msk = 0x4
	// Bit OVFLIEN.
	FMAC_CR_OVFLIEN = 0x4
	// Position of WIEN field.
	FMAC_CR_WIEN_Pos = 0x1
	// Bit mask of WIEN field.
	FMAC_CR_WIEN_Msk = 0x2
	// Bit WIEN.
	FMAC_CR_WIEN = 0x2
	// Position of RIEN field.
	FMAC_CR_RIEN_Pos = 0x0
	// Bit mask of RIEN field.
	FMAC_CR_RIEN_Msk = 0x1
	// Bit RIEN.
	FMAC_CR_RIEN = 0x1

	// SR: FMAC Status register
	// Position of YEMPTY field.
	FMAC_SR_YEMPTY_Pos = 0x0
	// Bit mask of YEMPTY field.
	FMAC_SR_YEMPTY_Msk = 0x1
	// Bit YEMPTY.
	FMAC_SR_YEMPTY = 0x1
	// Position of X1FULL field.
	FMAC_SR_X1FULL_Pos = 0x1
	// Bit mask of X1FULL field.
	FMAC_SR_X1FULL_Msk = 0x2
	// Bit X1FULL.
	FMAC_SR_X1FULL = 0x2
	// Position of OVFL field.
	FMAC_SR_OVFL_Pos = 0x8
	// Bit mask of OVFL field.
	FMAC_SR_OVFL_Msk = 0x100
	// Bit OVFL.
	FMAC_SR_OVFL = 0x100
	// Position of UNFL field.
	FMAC_SR_UNFL_Pos = 0x9
	// Bit mask of UNFL field.
	FMAC_SR_UNFL_Msk = 0x200
	// Bit UNFL.
	FMAC_SR_UNFL = 0x200
	// Position of SAT field.
	FMAC_SR_SAT_Pos = 0xa
	// Bit mask of SAT field.
	FMAC_SR_SAT_Msk = 0x400
	// Bit SAT.
	FMAC_SR_SAT = 0x400

	// WDATA: FMAC Write Data register
	// Position of WDATA field.
	FMAC_WDATA_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	FMAC_WDATA_WDATA_Msk = 0xffff

	// RDATA: FMAC Read Data register
	// Position of RDATA field.
	FMAC_RDATA_RDATA_Pos = 0x0
	// Bit mask of RDATA field.
	FMAC_RDATA_RDATA_Msk = 0xffff
)

// Constants for FMC: FMC
const (
	// BCR1: SRAM/NOR-Flash chip-select control register for bank 1
	// Position of MBKEN field.
	FMC_BCR1_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR1_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR1_MBKEN = 0x1
	// Corresponding memory bank is disabled
	FMC_BCR1_MBKEN_Disabled = 0x0
	// Corresponding memory bank is enabled
	FMC_BCR1_MBKEN_Enabled = 0x1
	// Position of MUXEN field.
	FMC_BCR1_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR1_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR1_MUXEN = 0x2
	// Address/Data non-multiplexed
	FMC_BCR1_MUXEN_Disabled = 0x0
	// Address/Data multiplexed on databus
	FMC_BCR1_MUXEN_Enabled = 0x1
	// Position of MTYP field.
	FMC_BCR1_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR1_MTYP_Msk = 0xc
	// SRAM memory type
	FMC_BCR1_MTYP_SRAM = 0x0
	// PSRAM (CRAM) memory type
	FMC_BCR1_MTYP_PSRAM = 0x1
	// NOR Flash/OneNAND Flash
	FMC_BCR1_MTYP_Flash = 0x2
	// Position of MWID field.
	FMC_BCR1_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR1_MWID_Msk = 0x30
	// Memory data bus width 8 bits
	FMC_BCR1_MWID_Bits8 = 0x0
	// Memory data bus width 16 bits
	FMC_BCR1_MWID_Bits16 = 0x1
	// Memory data bus width 32 bits
	FMC_BCR1_MWID_Bits32 = 0x2
	// Position of FACCEN field.
	FMC_BCR1_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR1_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR1_FACCEN = 0x40
	// Corresponding NOR Flash memory access is disabled
	FMC_BCR1_FACCEN_Disabled = 0x0
	// Corresponding NOR Flash memory access is enabled
	FMC_BCR1_FACCEN_Enabled = 0x1
	// Position of BURSTEN field.
	FMC_BCR1_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR1_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR1_BURSTEN = 0x100
	// Burst mode disabled
	FMC_BCR1_BURSTEN_Disabled = 0x0
	// Burst mode enabled
	FMC_BCR1_BURSTEN_Enabled = 0x1
	// Position of WAITPOL field.
	FMC_BCR1_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR1_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR1_WAITPOL = 0x200
	// NWAIT active low
	FMC_BCR1_WAITPOL_ActiveLow = 0x0
	// NWAIT active high
	FMC_BCR1_WAITPOL_ActiveHigh = 0x1
	// Position of WAITCFG field.
	FMC_BCR1_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR1_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR1_WAITCFG = 0x800
	// NWAIT signal is active one data cycle before wait state
	FMC_BCR1_WAITCFG_BeforeWaitState = 0x0
	// NWAIT signal is active during wait state
	FMC_BCR1_WAITCFG_DuringWaitState = 0x1
	// Position of WREN field.
	FMC_BCR1_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR1_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR1_WREN = 0x1000
	// Write operations disabled for the bank by the FMC
	FMC_BCR1_WREN_Disabled = 0x0
	// Write operations enabled for the bank by the FMC
	FMC_BCR1_WREN_Enabled = 0x1
	// Position of WAITEN field.
	FMC_BCR1_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR1_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR1_WAITEN = 0x2000
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR1_WAITEN_Disabled = 0x0
	// NWAIT signal enabled
	FMC_BCR1_WAITEN_Enabled = 0x1
	// Position of EXTMOD field.
	FMC_BCR1_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR1_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR1_EXTMOD = 0x4000
	// Values inside the FMC_BWTR are not taken into account
	FMC_BCR1_EXTMOD_Disabled = 0x0
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR1_EXTMOD_Enabled = 0x1
	// Position of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR1_ASYNCWAIT = 0x8000
	// Wait signal not used in asynchronous mode
	FMC_BCR1_ASYNCWAIT_Disabled = 0x0
	// Wait signal used even in asynchronous mode
	FMC_BCR1_ASYNCWAIT_Enabled = 0x1
	// Position of CPSIZE field.
	FMC_BCR1_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR1_CPSIZE_Msk = 0x70000
	// No burst split when crossing page boundary
	FMC_BCR1_CPSIZE_NoBurstSplit = 0x0
	// 128 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes128 = 0x1
	// 256 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes256 = 0x2
	// 512 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes512 = 0x3
	// 1024 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes1024 = 0x4
	// Position of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR1_CBURSTRW = 0x80000
	// Write operations are always performed in asynchronous mode
	FMC_BCR1_CBURSTRW_Disabled = 0x0
	// Write operations are performed in synchronous mode
	FMC_BCR1_CBURSTRW_Enabled = 0x1
	// Position of CCLKEN field.
	FMC_BCR1_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_BCR1_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_BCR1_CCLKEN = 0x100000
	// Position of WFDIS field.
	FMC_BCR1_WFDIS_Pos = 0x15
	// Bit mask of WFDIS field.
	FMC_BCR1_WFDIS_Msk = 0x200000
	// Bit WFDIS.
	FMC_BCR1_WFDIS = 0x200000
	// Position of NBLSET field.
	FMC_BCR1_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_BCR1_NBLSET_Msk = 0xc00000
	// Position of FMCEN field.
	FMC_BCR1_FMCEN_Pos = 0x1f
	// Bit mask of FMCEN field.
	FMC_BCR1_FMCEN_Msk = 0x80000000
	// Bit FMCEN.
	FMC_BCR1_FMCEN = 0x80000000

	// BTR1: SRAM/NOR-Flash chip-select timing register for bank %s
	// Position of ADDSET field.
	FMC_BTR_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BTR_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BTR_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BTR_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BTR_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BTR_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BTR_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BTR_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_BTR_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_BTR_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_BTR_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_BTR_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_BTR_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BTR_ACCMOD_Msk = 0x30000000
	// Access mode A
	FMC_BTR_ACCMOD_A = 0x0
	// Access mode B
	FMC_BTR_ACCMOD_B = 0x1
	// Access mode C
	FMC_BTR_ACCMOD_C = 0x2
	// Access mode D
	FMC_BTR_ACCMOD_D = 0x3
	// Position of DATAHLD field.
	FMC_BTR_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_BTR_DATAHLD_Msk = 0xc0000000

	// BCR2: SRAM/NOR-Flash chip-select control register for bank %s
	// Position of MBKEN field.
	FMC_BCR_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR_MBKEN = 0x1
	// Corresponding memory bank is disabled
	FMC_BCR_MBKEN_Disabled = 0x0
	// Corresponding memory bank is enabled
	FMC_BCR_MBKEN_Enabled = 0x1
	// Position of MUXEN field.
	FMC_BCR_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR_MUXEN = 0x2
	// Address/Data non-multiplexed
	FMC_BCR_MUXEN_Disabled = 0x0
	// Address/Data multiplexed on databus
	FMC_BCR_MUXEN_Enabled = 0x1
	// Position of MTYP field.
	FMC_BCR_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR_MTYP_Msk = 0xc
	// SRAM memory type
	FMC_BCR_MTYP_SRAM = 0x0
	// PSRAM (CRAM) memory type
	FMC_BCR_MTYP_PSRAM = 0x1
	// NOR Flash/OneNAND Flash
	FMC_BCR_MTYP_Flash = 0x2
	// Position of MWID field.
	FMC_BCR_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR_MWID_Msk = 0x30
	// Memory data bus width 8 bits
	FMC_BCR_MWID_Bits8 = 0x0
	// Memory data bus width 16 bits
	FMC_BCR_MWID_Bits16 = 0x1
	// Memory data bus width 32 bits
	FMC_BCR_MWID_Bits32 = 0x2
	// Position of FACCEN field.
	FMC_BCR_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR_FACCEN = 0x40
	// Corresponding NOR Flash memory access is disabled
	FMC_BCR_FACCEN_Disabled = 0x0
	// Corresponding NOR Flash memory access is enabled
	FMC_BCR_FACCEN_Enabled = 0x1
	// Position of BURSTEN field.
	FMC_BCR_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR_BURSTEN = 0x100
	// Burst mode disabled
	FMC_BCR_BURSTEN_Disabled = 0x0
	// Burst mode enabled
	FMC_BCR_BURSTEN_Enabled = 0x1
	// Position of WAITPOL field.
	FMC_BCR_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR_WAITPOL = 0x200
	// NWAIT active low
	FMC_BCR_WAITPOL_ActiveLow = 0x0
	// NWAIT active high
	FMC_BCR_WAITPOL_ActiveHigh = 0x1
	// Position of WAITCFG field.
	FMC_BCR_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR_WAITCFG = 0x800
	// NWAIT signal is active one data cycle before wait state
	FMC_BCR_WAITCFG_BeforeWaitState = 0x0
	// NWAIT signal is active during wait state
	FMC_BCR_WAITCFG_DuringWaitState = 0x1
	// Position of WREN field.
	FMC_BCR_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR_WREN = 0x1000
	// Write operations disabled for the bank by the FMC
	FMC_BCR_WREN_Disabled = 0x0
	// Write operations enabled for the bank by the FMC
	FMC_BCR_WREN_Enabled = 0x1
	// Position of WAITEN field.
	FMC_BCR_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR_WAITEN = 0x2000
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR_WAITEN_Disabled = 0x0
	// NWAIT signal enabled
	FMC_BCR_WAITEN_Enabled = 0x1
	// Position of EXTMOD field.
	FMC_BCR_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR_EXTMOD = 0x4000
	// Values inside the FMC_BWTR are not taken into account
	FMC_BCR_EXTMOD_Disabled = 0x0
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR_EXTMOD_Enabled = 0x1
	// Position of ASYNCWAIT field.
	FMC_BCR_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR_ASYNCWAIT = 0x8000
	// Wait signal not used in asynchronous mode
	FMC_BCR_ASYNCWAIT_Disabled = 0x0
	// Wait signal used even in asynchronous mode
	FMC_BCR_ASYNCWAIT_Enabled = 0x1
	// Position of CPSIZE field.
	FMC_BCR_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR_CPSIZE_Msk = 0x70000
	// No burst split when crossing page boundary
	FMC_BCR_CPSIZE_NoBurstSplit = 0x0
	// 128 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes128 = 0x1
	// 256 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes256 = 0x2
	// 512 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes512 = 0x3
	// 1024 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes1024 = 0x4
	// Position of CBURSTRW field.
	FMC_BCR_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR_CBURSTRW = 0x80000
	// Write operations are always performed in asynchronous mode
	FMC_BCR_CBURSTRW_Disabled = 0x0
	// Write operations are performed in synchronous mode
	FMC_BCR_CBURSTRW_Enabled = 0x1
	// Position of NBLSET field.
	FMC_BCR_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_BCR_NBLSET_Msk = 0xc00000

	// PCSCNTR: PSRAM chip select counter register
	// Position of CSCOUNT field.
	FMC_PCSCNTR_CSCOUNT_Pos = 0x0
	// Bit mask of CSCOUNT field.
	FMC_PCSCNTR_CSCOUNT_Msk = 0xffff
	// Position of CNTB1EN field.
	FMC_PCSCNTR_CNTB1EN_Pos = 0x11
	// Bit mask of CNTB1EN field.
	FMC_PCSCNTR_CNTB1EN_Msk = 0x20000
	// Bit CNTB1EN.
	FMC_PCSCNTR_CNTB1EN = 0x20000
	// Position of CNTB2EN field.
	FMC_PCSCNTR_CNTB2EN_Pos = 0x12
	// Bit mask of CNTB2EN field.
	FMC_PCSCNTR_CNTB2EN_Msk = 0x40000
	// Bit CNTB2EN.
	FMC_PCSCNTR_CNTB2EN = 0x40000
	// Position of CNTB3EN field.
	FMC_PCSCNTR_CNTB3EN_Pos = 0x13
	// Bit mask of CNTB3EN field.
	FMC_PCSCNTR_CNTB3EN_Msk = 0x80000
	// Bit CNTB3EN.
	FMC_PCSCNTR_CNTB3EN = 0x80000
	// Position of CNTB4EN field.
	FMC_PCSCNTR_CNTB4EN_Pos = 0x14
	// Bit mask of CNTB4EN field.
	FMC_PCSCNTR_CNTB4EN_Msk = 0x100000
	// Bit CNTB4EN.
	FMC_PCSCNTR_CNTB4EN = 0x100000

	// PCR: NAND Flash control registers
	// Position of PWAITEN field.
	FMC_PCR_PWAITEN_Pos = 0x1
	// Bit mask of PWAITEN field.
	FMC_PCR_PWAITEN_Msk = 0x2
	// Bit PWAITEN.
	FMC_PCR_PWAITEN = 0x2
	// Wait feature disabled
	FMC_PCR_PWAITEN_Disabled = 0x0
	// Wait feature enabled
	FMC_PCR_PWAITEN_Enabled = 0x1
	// Position of PBKEN field.
	FMC_PCR_PBKEN_Pos = 0x2
	// Bit mask of PBKEN field.
	FMC_PCR_PBKEN_Msk = 0x4
	// Bit PBKEN.
	FMC_PCR_PBKEN = 0x4
	// Corresponding memory bank is disabled
	FMC_PCR_PBKEN_Disabled = 0x0
	// Corresponding memory bank is enabled
	FMC_PCR_PBKEN_Enabled = 0x1
	// Position of PTYP field.
	FMC_PCR_PTYP_Pos = 0x3
	// Bit mask of PTYP field.
	FMC_PCR_PTYP_Msk = 0x8
	// Bit PTYP.
	FMC_PCR_PTYP = 0x8
	// NAND Flash
	FMC_PCR_PTYP_NANDFlash = 0x1
	// Position of PWID field.
	FMC_PCR_PWID_Pos = 0x4
	// Bit mask of PWID field.
	FMC_PCR_PWID_Msk = 0x30
	// External memory device width 8 bits
	FMC_PCR_PWID_Bits8 = 0x0
	// External memory device width 16 bits
	FMC_PCR_PWID_Bits16 = 0x1
	// Position of ECCEN field.
	FMC_PCR_ECCEN_Pos = 0x6
	// Bit mask of ECCEN field.
	FMC_PCR_ECCEN_Msk = 0x40
	// Bit ECCEN.
	FMC_PCR_ECCEN = 0x40
	// ECC logic is disabled and reset
	FMC_PCR_ECCEN_Disabled = 0x0
	// ECC logic is enabled
	FMC_PCR_ECCEN_Enabled = 0x1
	// Position of TCLR field.
	FMC_PCR_TCLR_Pos = 0x9
	// Bit mask of TCLR field.
	FMC_PCR_TCLR_Msk = 0x1e00
	// Position of TAR field.
	FMC_PCR_TAR_Pos = 0xd
	// Bit mask of TAR field.
	FMC_PCR_TAR_Msk = 0x1e000
	// Position of ECCPS field.
	FMC_PCR_ECCPS_Pos = 0x11
	// Bit mask of ECCPS field.
	FMC_PCR_ECCPS_Msk = 0xe0000
	// ECC page size 256 bytes
	FMC_PCR_ECCPS_Bytes256 = 0x0
	// ECC page size 512 bytes
	FMC_PCR_ECCPS_Bytes512 = 0x1
	// ECC page size 1024 bytes
	FMC_PCR_ECCPS_Bytes1024 = 0x2
	// ECC page size 2048 bytes
	FMC_PCR_ECCPS_Bytes2048 = 0x3
	// ECC page size 4096 bytes
	FMC_PCR_ECCPS_Bytes4096 = 0x4
	// ECC page size 8192 bytes
	FMC_PCR_ECCPS_Bytes8192 = 0x5

	// SR: status and interrupt register
	// Position of IRS field.
	FMC_SR_IRS_Pos = 0x0
	// Bit mask of IRS field.
	FMC_SR_IRS_Msk = 0x1
	// Bit IRS.
	FMC_SR_IRS = 0x1
	// Interrupt rising edge did not occur
	FMC_SR_IRS_DidNotOccur = 0x0
	// Interrupt rising edge occurred
	FMC_SR_IRS_Occurred = 0x1
	// Position of ILS field.
	FMC_SR_ILS_Pos = 0x1
	// Bit mask of ILS field.
	FMC_SR_ILS_Msk = 0x2
	// Bit ILS.
	FMC_SR_ILS = 0x2
	// Interrupt high-level did not occur
	FMC_SR_ILS_DidNotOccur = 0x0
	// Interrupt high-level occurred
	FMC_SR_ILS_Occurred = 0x1
	// Position of IFS field.
	FMC_SR_IFS_Pos = 0x2
	// Bit mask of IFS field.
	FMC_SR_IFS_Msk = 0x4
	// Bit IFS.
	FMC_SR_IFS = 0x4
	// Interrupt falling edge did not occur
	FMC_SR_IFS_DidNotOccur = 0x0
	// Interrupt falling edge occurred
	FMC_SR_IFS_Occurred = 0x1
	// Position of IREN field.
	FMC_SR_IREN_Pos = 0x3
	// Bit mask of IREN field.
	FMC_SR_IREN_Msk = 0x8
	// Bit IREN.
	FMC_SR_IREN = 0x8
	// Interrupt rising edge detection request disabled
	FMC_SR_IREN_Disabled = 0x0
	// Interrupt rising edge detection request enabled
	FMC_SR_IREN_Enabled = 0x1
	// Position of ILEN field.
	FMC_SR_ILEN_Pos = 0x4
	// Bit mask of ILEN field.
	FMC_SR_ILEN_Msk = 0x10
	// Bit ILEN.
	FMC_SR_ILEN = 0x10
	// Interrupt high-level detection request disabled
	FMC_SR_ILEN_Disabled = 0x0
	// Interrupt high-level detection request enabled
	FMC_SR_ILEN_Enabled = 0x1
	// Position of IFEN field.
	FMC_SR_IFEN_Pos = 0x5
	// Bit mask of IFEN field.
	FMC_SR_IFEN_Msk = 0x20
	// Bit IFEN.
	FMC_SR_IFEN = 0x20
	// Interrupt falling edge detection request disabled
	FMC_SR_IFEN_Disabled = 0x0
	// Interrupt falling edge detection request enabled
	FMC_SR_IFEN_Enabled = 0x1
	// Position of FEMPT field.
	FMC_SR_FEMPT_Pos = 0x6
	// Bit mask of FEMPT field.
	FMC_SR_FEMPT_Msk = 0x40
	// Bit FEMPT.
	FMC_SR_FEMPT = 0x40
	// FIFO not empty
	FMC_SR_FEMPT_NotEmpty = 0x0
	// FIFO empty
	FMC_SR_FEMPT_Empty = 0x1

	// PMEM: Common memory space timing register
	// Position of MEMSET field.
	FMC_PMEM_MEMSET_Pos = 0x0
	// Bit mask of MEMSET field.
	FMC_PMEM_MEMSET_Msk = 0xff
	// Position of MEMWAIT field.
	FMC_PMEM_MEMWAIT_Pos = 0x8
	// Bit mask of MEMWAIT field.
	FMC_PMEM_MEMWAIT_Msk = 0xff00
	// Position of MEMHOLD field.
	FMC_PMEM_MEMHOLD_Pos = 0x10
	// Bit mask of MEMHOLD field.
	FMC_PMEM_MEMHOLD_Msk = 0xff0000
	// Position of MEMHIZ field.
	FMC_PMEM_MEMHIZ_Pos = 0x18
	// Bit mask of MEMHIZ field.
	FMC_PMEM_MEMHIZ_Msk = 0xff000000

	// PATT: The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
	// Position of ATTSET field.
	FMC_PATT_ATTSET_Pos = 0x0
	// Bit mask of ATTSET field.
	FMC_PATT_ATTSET_Msk = 0xff
	// Position of ATTWAIT field.
	FMC_PATT_ATTWAIT_Pos = 0x8
	// Bit mask of ATTWAIT field.
	FMC_PATT_ATTWAIT_Msk = 0xff00
	// Position of ATTHOLD field.
	FMC_PATT_ATTHOLD_Pos = 0x10
	// Bit mask of ATTHOLD field.
	FMC_PATT_ATTHOLD_Msk = 0xff0000
	// Position of ATTHIZ field.
	FMC_PATT_ATTHIZ_Pos = 0x18
	// Bit mask of ATTHIZ field.
	FMC_PATT_ATTHIZ_Msk = 0xff000000

	// ECCR: This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
	// Position of ECC field.
	FMC_ECCR_ECC_Pos = 0x0
	// Bit mask of ECC field.
	FMC_ECCR_ECC_Msk = 0xffffffff

	// BWTR1: SRAM/NOR-Flash write timing registers %s
	// Position of ADDSET field.
	FMC_BWTR_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BWTR_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BWTR_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BWTR_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BWTR_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BWTR_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BWTR_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BWTR_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_BWTR_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BWTR_ACCMOD_Msk = 0x30000000
	// Access mode A
	FMC_BWTR_ACCMOD_A = 0x0
	// Access mode B
	FMC_BWTR_ACCMOD_B = 0x1
	// Access mode C
	FMC_BWTR_ACCMOD_C = 0x2
	// Access mode D
	FMC_BWTR_ACCMOD_D = 0x3
	// Position of DATAHLD field.
	FMC_BWTR_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_BWTR_DATAHLD_Msk = 0xc0000000
)

// Constants for GPDMA1: GPDMA1
const (
	// SECCFGR: GPDMA secure configuration register
	// Position of SEC0 field.
	GPDMA_SECCFGR_SEC0_Pos = 0x1
	// Bit mask of SEC0 field.
	GPDMA_SECCFGR_SEC0_Msk = 0x2
	// Bit SEC0.
	GPDMA_SECCFGR_SEC0 = 0x2
	// Position of SEC1 field.
	GPDMA_SECCFGR_SEC1_Pos = 0x2
	// Bit mask of SEC1 field.
	GPDMA_SECCFGR_SEC1_Msk = 0x4
	// Bit SEC1.
	GPDMA_SECCFGR_SEC1 = 0x4
	// Position of SEC2 field.
	GPDMA_SECCFGR_SEC2_Pos = 0x3
	// Bit mask of SEC2 field.
	GPDMA_SECCFGR_SEC2_Msk = 0x8
	// Bit SEC2.
	GPDMA_SECCFGR_SEC2 = 0x8
	// Position of SEC3 field.
	GPDMA_SECCFGR_SEC3_Pos = 0x4
	// Bit mask of SEC3 field.
	GPDMA_SECCFGR_SEC3_Msk = 0x10
	// Bit SEC3.
	GPDMA_SECCFGR_SEC3 = 0x10
	// Position of SEC4 field.
	GPDMA_SECCFGR_SEC4_Pos = 0x5
	// Bit mask of SEC4 field.
	GPDMA_SECCFGR_SEC4_Msk = 0x20
	// Bit SEC4.
	GPDMA_SECCFGR_SEC4 = 0x20
	// Position of SEC5 field.
	GPDMA_SECCFGR_SEC5_Pos = 0x6
	// Bit mask of SEC5 field.
	GPDMA_SECCFGR_SEC5_Msk = 0x40
	// Bit SEC5.
	GPDMA_SECCFGR_SEC5 = 0x40
	// Position of SEC6 field.
	GPDMA_SECCFGR_SEC6_Pos = 0x7
	// Bit mask of SEC6 field.
	GPDMA_SECCFGR_SEC6_Msk = 0x80
	// Bit SEC6.
	GPDMA_SECCFGR_SEC6 = 0x80
	// Position of SEC7 field.
	GPDMA_SECCFGR_SEC7_Pos = 0x8
	// Bit mask of SEC7 field.
	GPDMA_SECCFGR_SEC7_Msk = 0x100
	// Bit SEC7.
	GPDMA_SECCFGR_SEC7 = 0x100
	// Position of SEC8 field.
	GPDMA_SECCFGR_SEC8_Pos = 0x9
	// Bit mask of SEC8 field.
	GPDMA_SECCFGR_SEC8_Msk = 0x200
	// Bit SEC8.
	GPDMA_SECCFGR_SEC8 = 0x200
	// Position of SEC9 field.
	GPDMA_SECCFGR_SEC9_Pos = 0xa
	// Bit mask of SEC9 field.
	GPDMA_SECCFGR_SEC9_Msk = 0x400
	// Bit SEC9.
	GPDMA_SECCFGR_SEC9 = 0x400
	// Position of SEC10 field.
	GPDMA_SECCFGR_SEC10_Pos = 0xb
	// Bit mask of SEC10 field.
	GPDMA_SECCFGR_SEC10_Msk = 0x800
	// Bit SEC10.
	GPDMA_SECCFGR_SEC10 = 0x800
	// Position of SEC11 field.
	GPDMA_SECCFGR_SEC11_Pos = 0xc
	// Bit mask of SEC11 field.
	GPDMA_SECCFGR_SEC11_Msk = 0x1000
	// Bit SEC11.
	GPDMA_SECCFGR_SEC11 = 0x1000
	// Position of SEC12 field.
	GPDMA_SECCFGR_SEC12_Pos = 0xd
	// Bit mask of SEC12 field.
	GPDMA_SECCFGR_SEC12_Msk = 0x2000
	// Bit SEC12.
	GPDMA_SECCFGR_SEC12 = 0x2000
	// Position of SEC13 field.
	GPDMA_SECCFGR_SEC13_Pos = 0xe
	// Bit mask of SEC13 field.
	GPDMA_SECCFGR_SEC13_Msk = 0x4000
	// Bit SEC13.
	GPDMA_SECCFGR_SEC13 = 0x4000
	// Position of SEC14 field.
	GPDMA_SECCFGR_SEC14_Pos = 0xf
	// Bit mask of SEC14 field.
	GPDMA_SECCFGR_SEC14_Msk = 0x8000
	// Bit SEC14.
	GPDMA_SECCFGR_SEC14 = 0x8000
	// Position of SEC15 field.
	GPDMA_SECCFGR_SEC15_Pos = 0x10
	// Bit mask of SEC15 field.
	GPDMA_SECCFGR_SEC15_Msk = 0x10000
	// Bit SEC15.
	GPDMA_SECCFGR_SEC15 = 0x10000

	// PRIVCFGR: GPDMA privileged configuration register
	// Position of PRIV0 field.
	GPDMA_PRIVCFGR_PRIV0_Pos = 0x1
	// Bit mask of PRIV0 field.
	GPDMA_PRIVCFGR_PRIV0_Msk = 0x2
	// Bit PRIV0.
	GPDMA_PRIVCFGR_PRIV0 = 0x2
	// Position of PRIV1 field.
	GPDMA_PRIVCFGR_PRIV1_Pos = 0x2
	// Bit mask of PRIV1 field.
	GPDMA_PRIVCFGR_PRIV1_Msk = 0x4
	// Bit PRIV1.
	GPDMA_PRIVCFGR_PRIV1 = 0x4
	// Position of PRIV2 field.
	GPDMA_PRIVCFGR_PRIV2_Pos = 0x3
	// Bit mask of PRIV2 field.
	GPDMA_PRIVCFGR_PRIV2_Msk = 0x8
	// Bit PRIV2.
	GPDMA_PRIVCFGR_PRIV2 = 0x8
	// Position of PRIV3 field.
	GPDMA_PRIVCFGR_PRIV3_Pos = 0x4
	// Bit mask of PRIV3 field.
	GPDMA_PRIVCFGR_PRIV3_Msk = 0x10
	// Bit PRIV3.
	GPDMA_PRIVCFGR_PRIV3 = 0x10
	// Position of PRIV4 field.
	GPDMA_PRIVCFGR_PRIV4_Pos = 0x5
	// Bit mask of PRIV4 field.
	GPDMA_PRIVCFGR_PRIV4_Msk = 0x20
	// Bit PRIV4.
	GPDMA_PRIVCFGR_PRIV4 = 0x20
	// Position of PRIV5 field.
	GPDMA_PRIVCFGR_PRIV5_Pos = 0x6
	// Bit mask of PRIV5 field.
	GPDMA_PRIVCFGR_PRIV5_Msk = 0x40
	// Bit PRIV5.
	GPDMA_PRIVCFGR_PRIV5 = 0x40
	// Position of PRIV6 field.
	GPDMA_PRIVCFGR_PRIV6_Pos = 0x7
	// Bit mask of PRIV6 field.
	GPDMA_PRIVCFGR_PRIV6_Msk = 0x80
	// Bit PRIV6.
	GPDMA_PRIVCFGR_PRIV6 = 0x80
	// Position of PRIV7 field.
	GPDMA_PRIVCFGR_PRIV7_Pos = 0x8
	// Bit mask of PRIV7 field.
	GPDMA_PRIVCFGR_PRIV7_Msk = 0x100
	// Bit PRIV7.
	GPDMA_PRIVCFGR_PRIV7 = 0x100
	// Position of PRIV8 field.
	GPDMA_PRIVCFGR_PRIV8_Pos = 0x9
	// Bit mask of PRIV8 field.
	GPDMA_PRIVCFGR_PRIV8_Msk = 0x200
	// Bit PRIV8.
	GPDMA_PRIVCFGR_PRIV8 = 0x200
	// Position of PRIV9 field.
	GPDMA_PRIVCFGR_PRIV9_Pos = 0xa
	// Bit mask of PRIV9 field.
	GPDMA_PRIVCFGR_PRIV9_Msk = 0x400
	// Bit PRIV9.
	GPDMA_PRIVCFGR_PRIV9 = 0x400
	// Position of PRIV10 field.
	GPDMA_PRIVCFGR_PRIV10_Pos = 0xb
	// Bit mask of PRIV10 field.
	GPDMA_PRIVCFGR_PRIV10_Msk = 0x800
	// Bit PRIV10.
	GPDMA_PRIVCFGR_PRIV10 = 0x800
	// Position of PRIV11 field.
	GPDMA_PRIVCFGR_PRIV11_Pos = 0xc
	// Bit mask of PRIV11 field.
	GPDMA_PRIVCFGR_PRIV11_Msk = 0x1000
	// Bit PRIV11.
	GPDMA_PRIVCFGR_PRIV11 = 0x1000
	// Position of PRIV12 field.
	GPDMA_PRIVCFGR_PRIV12_Pos = 0xd
	// Bit mask of PRIV12 field.
	GPDMA_PRIVCFGR_PRIV12_Msk = 0x2000
	// Bit PRIV12.
	GPDMA_PRIVCFGR_PRIV12 = 0x2000
	// Position of PRIV13 field.
	GPDMA_PRIVCFGR_PRIV13_Pos = 0xe
	// Bit mask of PRIV13 field.
	GPDMA_PRIVCFGR_PRIV13_Msk = 0x4000
	// Bit PRIV13.
	GPDMA_PRIVCFGR_PRIV13 = 0x4000
	// Position of PRIV14 field.
	GPDMA_PRIVCFGR_PRIV14_Pos = 0xf
	// Bit mask of PRIV14 field.
	GPDMA_PRIVCFGR_PRIV14_Msk = 0x8000
	// Bit PRIV14.
	GPDMA_PRIVCFGR_PRIV14 = 0x8000
	// Position of PRIV15 field.
	GPDMA_PRIVCFGR_PRIV15_Pos = 0x10
	// Bit mask of PRIV15 field.
	GPDMA_PRIVCFGR_PRIV15_Msk = 0x10000
	// Bit PRIV15.
	GPDMA_PRIVCFGR_PRIV15 = 0x10000

	// MISR: non-secure masked interrupt status register
	// Position of MIS0 field.
	GPDMA_MISR_MIS0_Pos = 0x1
	// Bit mask of MIS0 field.
	GPDMA_MISR_MIS0_Msk = 0x2
	// Bit MIS0.
	GPDMA_MISR_MIS0 = 0x2
	// Position of MIS1 field.
	GPDMA_MISR_MIS1_Pos = 0x2
	// Bit mask of MIS1 field.
	GPDMA_MISR_MIS1_Msk = 0x4
	// Bit MIS1.
	GPDMA_MISR_MIS1 = 0x4
	// Position of MIS2 field.
	GPDMA_MISR_MIS2_Pos = 0x3
	// Bit mask of MIS2 field.
	GPDMA_MISR_MIS2_Msk = 0x8
	// Bit MIS2.
	GPDMA_MISR_MIS2 = 0x8
	// Position of MIS3 field.
	GPDMA_MISR_MIS3_Pos = 0x4
	// Bit mask of MIS3 field.
	GPDMA_MISR_MIS3_Msk = 0x10
	// Bit MIS3.
	GPDMA_MISR_MIS3 = 0x10
	// Position of MIS4 field.
	GPDMA_MISR_MIS4_Pos = 0x5
	// Bit mask of MIS4 field.
	GPDMA_MISR_MIS4_Msk = 0x20
	// Bit MIS4.
	GPDMA_MISR_MIS4 = 0x20
	// Position of MIS5 field.
	GPDMA_MISR_MIS5_Pos = 0x6
	// Bit mask of MIS5 field.
	GPDMA_MISR_MIS5_Msk = 0x40
	// Bit MIS5.
	GPDMA_MISR_MIS5 = 0x40
	// Position of MIS6 field.
	GPDMA_MISR_MIS6_Pos = 0x7
	// Bit mask of MIS6 field.
	GPDMA_MISR_MIS6_Msk = 0x80
	// Bit MIS6.
	GPDMA_MISR_MIS6 = 0x80
	// Position of MIS7 field.
	GPDMA_MISR_MIS7_Pos = 0x8
	// Bit mask of MIS7 field.
	GPDMA_MISR_MIS7_Msk = 0x100
	// Bit MIS7.
	GPDMA_MISR_MIS7 = 0x100
	// Position of MIS8 field.
	GPDMA_MISR_MIS8_Pos = 0x9
	// Bit mask of MIS8 field.
	GPDMA_MISR_MIS8_Msk = 0x200
	// Bit MIS8.
	GPDMA_MISR_MIS8 = 0x200
	// Position of MIS9 field.
	GPDMA_MISR_MIS9_Pos = 0xa
	// Bit mask of MIS9 field.
	GPDMA_MISR_MIS9_Msk = 0x400
	// Bit MIS9.
	GPDMA_MISR_MIS9 = 0x400
	// Position of MIS10 field.
	GPDMA_MISR_MIS10_Pos = 0xb
	// Bit mask of MIS10 field.
	GPDMA_MISR_MIS10_Msk = 0x800
	// Bit MIS10.
	GPDMA_MISR_MIS10 = 0x800
	// Position of MIS11 field.
	GPDMA_MISR_MIS11_Pos = 0xc
	// Bit mask of MIS11 field.
	GPDMA_MISR_MIS11_Msk = 0x1000
	// Bit MIS11.
	GPDMA_MISR_MIS11 = 0x1000
	// Position of MIS12 field.
	GPDMA_MISR_MIS12_Pos = 0xd
	// Bit mask of MIS12 field.
	GPDMA_MISR_MIS12_Msk = 0x2000
	// Bit MIS12.
	GPDMA_MISR_MIS12 = 0x2000
	// Position of MIS13 field.
	GPDMA_MISR_MIS13_Pos = 0xe
	// Bit mask of MIS13 field.
	GPDMA_MISR_MIS13_Msk = 0x4000
	// Bit MIS13.
	GPDMA_MISR_MIS13 = 0x4000
	// Position of MIS14 field.
	GPDMA_MISR_MIS14_Pos = 0xf
	// Bit mask of MIS14 field.
	GPDMA_MISR_MIS14_Msk = 0x8000
	// Bit MIS14.
	GPDMA_MISR_MIS14 = 0x8000
	// Position of MIS15 field.
	GPDMA_MISR_MIS15_Pos = 0x10
	// Bit mask of MIS15 field.
	GPDMA_MISR_MIS15_Msk = 0x10000
	// Bit MIS15.
	GPDMA_MISR_MIS15 = 0x10000

	// SMISR: secure masked interrupt status register
	// Position of MIS0 field.
	GPDMA_SMISR_MIS0_Pos = 0x1
	// Bit mask of MIS0 field.
	GPDMA_SMISR_MIS0_Msk = 0x2
	// Bit MIS0.
	GPDMA_SMISR_MIS0 = 0x2
	// Position of MIS1 field.
	GPDMA_SMISR_MIS1_Pos = 0x2
	// Bit mask of MIS1 field.
	GPDMA_SMISR_MIS1_Msk = 0x4
	// Bit MIS1.
	GPDMA_SMISR_MIS1 = 0x4
	// Position of MIS2 field.
	GPDMA_SMISR_MIS2_Pos = 0x3
	// Bit mask of MIS2 field.
	GPDMA_SMISR_MIS2_Msk = 0x8
	// Bit MIS2.
	GPDMA_SMISR_MIS2 = 0x8
	// Position of MIS3 field.
	GPDMA_SMISR_MIS3_Pos = 0x4
	// Bit mask of MIS3 field.
	GPDMA_SMISR_MIS3_Msk = 0x10
	// Bit MIS3.
	GPDMA_SMISR_MIS3 = 0x10
	// Position of MIS4 field.
	GPDMA_SMISR_MIS4_Pos = 0x5
	// Bit mask of MIS4 field.
	GPDMA_SMISR_MIS4_Msk = 0x20
	// Bit MIS4.
	GPDMA_SMISR_MIS4 = 0x20
	// Position of MIS5 field.
	GPDMA_SMISR_MIS5_Pos = 0x6
	// Bit mask of MIS5 field.
	GPDMA_SMISR_MIS5_Msk = 0x40
	// Bit MIS5.
	GPDMA_SMISR_MIS5 = 0x40
	// Position of MIS6 field.
	GPDMA_SMISR_MIS6_Pos = 0x7
	// Bit mask of MIS6 field.
	GPDMA_SMISR_MIS6_Msk = 0x80
	// Bit MIS6.
	GPDMA_SMISR_MIS6 = 0x80
	// Position of MIS7 field.
	GPDMA_SMISR_MIS7_Pos = 0x8
	// Bit mask of MIS7 field.
	GPDMA_SMISR_MIS7_Msk = 0x100
	// Bit MIS7.
	GPDMA_SMISR_MIS7 = 0x100
	// Position of MIS8 field.
	GPDMA_SMISR_MIS8_Pos = 0x9
	// Bit mask of MIS8 field.
	GPDMA_SMISR_MIS8_Msk = 0x200
	// Bit MIS8.
	GPDMA_SMISR_MIS8 = 0x200
	// Position of MIS9 field.
	GPDMA_SMISR_MIS9_Pos = 0xa
	// Bit mask of MIS9 field.
	GPDMA_SMISR_MIS9_Msk = 0x400
	// Bit MIS9.
	GPDMA_SMISR_MIS9 = 0x400
	// Position of MIS10 field.
	GPDMA_SMISR_MIS10_Pos = 0xb
	// Bit mask of MIS10 field.
	GPDMA_SMISR_MIS10_Msk = 0x800
	// Bit MIS10.
	GPDMA_SMISR_MIS10 = 0x800
	// Position of MIS11 field.
	GPDMA_SMISR_MIS11_Pos = 0xc
	// Bit mask of MIS11 field.
	GPDMA_SMISR_MIS11_Msk = 0x1000
	// Bit MIS11.
	GPDMA_SMISR_MIS11 = 0x1000
	// Position of MIS12 field.
	GPDMA_SMISR_MIS12_Pos = 0xd
	// Bit mask of MIS12 field.
	GPDMA_SMISR_MIS12_Msk = 0x2000
	// Bit MIS12.
	GPDMA_SMISR_MIS12 = 0x2000
	// Position of MIS13 field.
	GPDMA_SMISR_MIS13_Pos = 0xe
	// Bit mask of MIS13 field.
	GPDMA_SMISR_MIS13_Msk = 0x4000
	// Bit MIS13.
	GPDMA_SMISR_MIS13 = 0x4000
	// Position of MIS14 field.
	GPDMA_SMISR_MIS14_Pos = 0xf
	// Bit mask of MIS14 field.
	GPDMA_SMISR_MIS14_Msk = 0x8000
	// Bit MIS14.
	GPDMA_SMISR_MIS14 = 0x8000
	// Position of MIS15 field.
	GPDMA_SMISR_MIS15_Pos = 0x10
	// Bit mask of MIS15 field.
	GPDMA_SMISR_MIS15_Msk = 0x10000
	// Bit MIS15.
	GPDMA_SMISR_MIS15 = 0x10000

	// CH.LBAR: channel x linked-list base address register
	// Position of LBA field.
	GPDMA_CH_LBAR_LBA_Pos = 0x10
	// Bit mask of LBA field.
	GPDMA_CH_LBAR_LBA_Msk = 0xffff0000

	// CH.FCR: GPDMA channel x flag clear register
	// Position of TCF field.
	GPDMA_CH_FCR_TCF_Pos = 0x8
	// Bit mask of TCF field.
	GPDMA_CH_FCR_TCF_Msk = 0x100
	// Bit TCF.
	GPDMA_CH_FCR_TCF = 0x100
	// Position of HTF field.
	GPDMA_CH_FCR_HTF_Pos = 0x9
	// Bit mask of HTF field.
	GPDMA_CH_FCR_HTF_Msk = 0x200
	// Bit HTF.
	GPDMA_CH_FCR_HTF = 0x200
	// Position of DTEF field.
	GPDMA_CH_FCR_DTEF_Pos = 0xa
	// Bit mask of DTEF field.
	GPDMA_CH_FCR_DTEF_Msk = 0x400
	// Bit DTEF.
	GPDMA_CH_FCR_DTEF = 0x400
	// Position of ULEF field.
	GPDMA_CH_FCR_ULEF_Pos = 0xb
	// Bit mask of ULEF field.
	GPDMA_CH_FCR_ULEF_Msk = 0x800
	// Bit ULEF.
	GPDMA_CH_FCR_ULEF = 0x800
	// Position of USEF field.
	GPDMA_CH_FCR_USEF_Pos = 0xc
	// Bit mask of USEF field.
	GPDMA_CH_FCR_USEF_Msk = 0x1000
	// Bit USEF.
	GPDMA_CH_FCR_USEF = 0x1000
	// Position of SUSPF field.
	GPDMA_CH_FCR_SUSPF_Pos = 0xd
	// Bit mask of SUSPF field.
	GPDMA_CH_FCR_SUSPF_Msk = 0x2000
	// Bit SUSPF.
	GPDMA_CH_FCR_SUSPF = 0x2000
	// Position of TOF field.
	GPDMA_CH_FCR_TOF_Pos = 0xe
	// Bit mask of TOF field.
	GPDMA_CH_FCR_TOF_Msk = 0x4000
	// Bit TOF.
	GPDMA_CH_FCR_TOF = 0x4000

	// CH.SR: channel x status register
	// Position of IDLEF field.
	GPDMA_CH_SR_IDLEF_Pos = 0x0
	// Bit mask of IDLEF field.
	GPDMA_CH_SR_IDLEF_Msk = 0x1
	// Bit IDLEF.
	GPDMA_CH_SR_IDLEF = 0x1
	// Position of TCF field.
	GPDMA_CH_SR_TCF_Pos = 0x8
	// Bit mask of TCF field.
	GPDMA_CH_SR_TCF_Msk = 0x100
	// Bit TCF.
	GPDMA_CH_SR_TCF = 0x100
	// Position of HTF field.
	GPDMA_CH_SR_HTF_Pos = 0x9
	// Bit mask of HTF field.
	GPDMA_CH_SR_HTF_Msk = 0x200
	// Bit HTF.
	GPDMA_CH_SR_HTF = 0x200
	// Position of DTEF field.
	GPDMA_CH_SR_DTEF_Pos = 0xa
	// Bit mask of DTEF field.
	GPDMA_CH_SR_DTEF_Msk = 0x400
	// Bit DTEF.
	GPDMA_CH_SR_DTEF = 0x400
	// Position of ULEF field.
	GPDMA_CH_SR_ULEF_Pos = 0xb
	// Bit mask of ULEF field.
	GPDMA_CH_SR_ULEF_Msk = 0x800
	// Bit ULEF.
	GPDMA_CH_SR_ULEF = 0x800
	// Position of USEF field.
	GPDMA_CH_SR_USEF_Pos = 0xc
	// Bit mask of USEF field.
	GPDMA_CH_SR_USEF_Msk = 0x1000
	// Bit USEF.
	GPDMA_CH_SR_USEF = 0x1000
	// Position of SUSPF field.
	GPDMA_CH_SR_SUSPF_Pos = 0xd
	// Bit mask of SUSPF field.
	GPDMA_CH_SR_SUSPF_Msk = 0x2000
	// Bit SUSPF.
	GPDMA_CH_SR_SUSPF = 0x2000
	// Position of FIFOL field.
	GPDMA_CH_SR_FIFOL_Pos = 0x10
	// Bit mask of FIFOL field.
	GPDMA_CH_SR_FIFOL_Msk = 0xff0000

	// CH.CR: channel x control register
	// Position of EN field.
	GPDMA_CH_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	GPDMA_CH_CR_EN_Msk = 0x1
	// Bit EN.
	GPDMA_CH_CR_EN = 0x1
	// Position of RESET field.
	GPDMA_CH_CR_RESET_Pos = 0x1
	// Bit mask of RESET field.
	GPDMA_CH_CR_RESET_Msk = 0x2
	// Bit RESET.
	GPDMA_CH_CR_RESET = 0x2
	// Position of SUSP field.
	GPDMA_CH_CR_SUSP_Pos = 0x2
	// Bit mask of SUSP field.
	GPDMA_CH_CR_SUSP_Msk = 0x4
	// Bit SUSP.
	GPDMA_CH_CR_SUSP = 0x4
	// Position of TCIE field.
	GPDMA_CH_CR_TCIE_Pos = 0x8
	// Bit mask of TCIE field.
	GPDMA_CH_CR_TCIE_Msk = 0x100
	// Bit TCIE.
	GPDMA_CH_CR_TCIE = 0x100
	// Position of HTIE field.
	GPDMA_CH_CR_HTIE_Pos = 0x9
	// Bit mask of HTIE field.
	GPDMA_CH_CR_HTIE_Msk = 0x200
	// Bit HTIE.
	GPDMA_CH_CR_HTIE = 0x200
	// Position of DTEIE field.
	GPDMA_CH_CR_DTEIE_Pos = 0xa
	// Bit mask of DTEIE field.
	GPDMA_CH_CR_DTEIE_Msk = 0x400
	// Bit DTEIE.
	GPDMA_CH_CR_DTEIE = 0x400
	// Position of ULEIE field.
	GPDMA_CH_CR_ULEIE_Pos = 0xb
	// Bit mask of ULEIE field.
	GPDMA_CH_CR_ULEIE_Msk = 0x800
	// Bit ULEIE.
	GPDMA_CH_CR_ULEIE = 0x800
	// Position of USEIE field.
	GPDMA_CH_CR_USEIE_Pos = 0xc
	// Bit mask of USEIE field.
	GPDMA_CH_CR_USEIE_Msk = 0x1000
	// Bit USEIE.
	GPDMA_CH_CR_USEIE = 0x1000
	// Position of SUSPIE field.
	GPDMA_CH_CR_SUSPIE_Pos = 0xd
	// Bit mask of SUSPIE field.
	GPDMA_CH_CR_SUSPIE_Msk = 0x2000
	// Bit SUSPIE.
	GPDMA_CH_CR_SUSPIE = 0x2000
	// Position of LSM field.
	GPDMA_CH_CR_LSM_Pos = 0x10
	// Bit mask of LSM field.
	GPDMA_CH_CR_LSM_Msk = 0x10000
	// Bit LSM.
	GPDMA_CH_CR_LSM = 0x10000
	// Position of LAP field.
	GPDMA_CH_CR_LAP_Pos = 0x11
	// Bit mask of LAP field.
	GPDMA_CH_CR_LAP_Msk = 0x20000
	// Bit LAP.
	GPDMA_CH_CR_LAP = 0x20000
	// Position of PRIO field.
	GPDMA_CH_CR_PRIO_Pos = 0x16
	// Bit mask of PRIO field.
	GPDMA_CH_CR_PRIO_Msk = 0xc00000

	// CH.TR1: GPDMA channel x transfer register 1
	// Position of SDW_LOG2 field.
	GPDMA_CH_TR1_SDW_LOG2_Pos = 0x0
	// Bit mask of SDW_LOG2 field.
	GPDMA_CH_TR1_SDW_LOG2_Msk = 0x3
	// Position of SINC field.
	GPDMA_CH_TR1_SINC_Pos = 0x3
	// Bit mask of SINC field.
	GPDMA_CH_TR1_SINC_Msk = 0x8
	// Bit SINC.
	GPDMA_CH_TR1_SINC = 0x8
	// Position of SBL_1 field.
	GPDMA_CH_TR1_SBL_1_Pos = 0x4
	// Bit mask of SBL_1 field.
	GPDMA_CH_TR1_SBL_1_Msk = 0x3f0
	// Position of PAM field.
	GPDMA_CH_TR1_PAM_Pos = 0xb
	// Bit mask of PAM field.
	GPDMA_CH_TR1_PAM_Msk = 0x1800
	// Position of SBX field.
	GPDMA_CH_TR1_SBX_Pos = 0xd
	// Bit mask of SBX field.
	GPDMA_CH_TR1_SBX_Msk = 0x2000
	// Bit SBX.
	GPDMA_CH_TR1_SBX = 0x2000
	// Position of SAP field.
	GPDMA_CH_TR1_SAP_Pos = 0xe
	// Bit mask of SAP field.
	GPDMA_CH_TR1_SAP_Msk = 0x4000
	// Bit SAP.
	GPDMA_CH_TR1_SAP = 0x4000
	// Position of SSEC field.
	GPDMA_CH_TR1_SSEC_Pos = 0xf
	// Bit mask of SSEC field.
	GPDMA_CH_TR1_SSEC_Msk = 0x8000
	// Bit SSEC.
	GPDMA_CH_TR1_SSEC = 0x8000
	// Position of DDW_LOG2 field.
	GPDMA_CH_TR1_DDW_LOG2_Pos = 0x10
	// Bit mask of DDW_LOG2 field.
	GPDMA_CH_TR1_DDW_LOG2_Msk = 0x30000
	// Position of DINC field.
	GPDMA_CH_TR1_DINC_Pos = 0x13
	// Bit mask of DINC field.
	GPDMA_CH_TR1_DINC_Msk = 0x80000
	// Bit DINC.
	GPDMA_CH_TR1_DINC = 0x80000
	// Position of DBL_1 field.
	GPDMA_CH_TR1_DBL_1_Pos = 0x14
	// Bit mask of DBL_1 field.
	GPDMA_CH_TR1_DBL_1_Msk = 0x3f00000
	// Position of DBX field.
	GPDMA_CH_TR1_DBX_Pos = 0x1a
	// Bit mask of DBX field.
	GPDMA_CH_TR1_DBX_Msk = 0x4000000
	// Bit DBX.
	GPDMA_CH_TR1_DBX = 0x4000000
	// Position of DHX field.
	GPDMA_CH_TR1_DHX_Pos = 0x1b
	// Bit mask of DHX field.
	GPDMA_CH_TR1_DHX_Msk = 0x8000000
	// Bit DHX.
	GPDMA_CH_TR1_DHX = 0x8000000
	// Position of DAP field.
	GPDMA_CH_TR1_DAP_Pos = 0x1e
	// Bit mask of DAP field.
	GPDMA_CH_TR1_DAP_Msk = 0x40000000
	// Bit DAP.
	GPDMA_CH_TR1_DAP = 0x40000000
	// Position of DSEC field.
	GPDMA_CH_TR1_DSEC_Pos = 0x1f
	// Bit mask of DSEC field.
	GPDMA_CH_TR1_DSEC_Msk = 0x80000000
	// Bit DSEC.
	GPDMA_CH_TR1_DSEC = 0x80000000

	// CH.TR2: GPDMA channel x transfer register 2
	// Position of REQSEL field.
	GPDMA_CH_TR2_REQSEL_Pos = 0x0
	// Bit mask of REQSEL field.
	GPDMA_CH_TR2_REQSEL_Msk = 0x7f
	// Position of SWREQ field.
	GPDMA_CH_TR2_SWREQ_Pos = 0x9
	// Bit mask of SWREQ field.
	GPDMA_CH_TR2_SWREQ_Msk = 0x200
	// Bit SWREQ.
	GPDMA_CH_TR2_SWREQ = 0x200
	// Position of DREQ field.
	GPDMA_CH_TR2_DREQ_Pos = 0xa
	// Bit mask of DREQ field.
	GPDMA_CH_TR2_DREQ_Msk = 0x400
	// Bit DREQ.
	GPDMA_CH_TR2_DREQ = 0x400
	// Position of BREQ field.
	GPDMA_CH_TR2_BREQ_Pos = 0xb
	// Bit mask of BREQ field.
	GPDMA_CH_TR2_BREQ_Msk = 0x800
	// Bit BREQ.
	GPDMA_CH_TR2_BREQ = 0x800
	// Position of TRIGM field.
	GPDMA_CH_TR2_TRIGM_Pos = 0xe
	// Bit mask of TRIGM field.
	GPDMA_CH_TR2_TRIGM_Msk = 0xc000
	// Position of TRIGSEL field.
	GPDMA_CH_TR2_TRIGSEL_Pos = 0x10
	// Bit mask of TRIGSEL field.
	GPDMA_CH_TR2_TRIGSEL_Msk = 0x3f0000
	// Position of TRIGPOL field.
	GPDMA_CH_TR2_TRIGPOL_Pos = 0x18
	// Bit mask of TRIGPOL field.
	GPDMA_CH_TR2_TRIGPOL_Msk = 0x3000000
	// Position of TCEM field.
	GPDMA_CH_TR2_TCEM_Pos = 0x1e
	// Bit mask of TCEM field.
	GPDMA_CH_TR2_TCEM_Msk = 0xc0000000

	// CH.BR1: GPDMA channel x block register 1
	// Position of BNDT field.
	GPDMA_CH_BR1_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	GPDMA_CH_BR1_BNDT_Msk = 0xffff

	// CH.SAR: GPDMA channel x source address register
	// Position of SA field.
	GPDMA_CH_SAR_SA_Pos = 0x0
	// Bit mask of SA field.
	GPDMA_CH_SAR_SA_Msk = 0xffffffff

	// CH.DAR: GPDMA channel x destination address register
	// Position of DA field.
	GPDMA_CH_DAR_DA_Pos = 0x0
	// Bit mask of DA field.
	GPDMA_CH_DAR_DA_Msk = 0xffffffff

	// CH.LLR: GPDMA channel x linked-list address register
	// Position of LA field.
	GPDMA_CH_LLR_LA_Pos = 0x2
	// Bit mask of LA field.
	GPDMA_CH_LLR_LA_Msk = 0xfffc
	// Position of ULL field.
	GPDMA_CH_LLR_ULL_Pos = 0x10
	// Bit mask of ULL field.
	GPDMA_CH_LLR_ULL_Msk = 0x10000
	// Bit ULL.
	GPDMA_CH_LLR_ULL = 0x10000
	// Position of UDA field.
	GPDMA_CH_LLR_UDA_Pos = 0x1b
	// Bit mask of UDA field.
	GPDMA_CH_LLR_UDA_Msk = 0x8000000
	// Bit UDA.
	GPDMA_CH_LLR_UDA = 0x8000000
	// Position of USA field.
	GPDMA_CH_LLR_USA_Pos = 0x1c
	// Bit mask of USA field.
	GPDMA_CH_LLR_USA_Msk = 0x10000000
	// Bit USA.
	GPDMA_CH_LLR_USA = 0x10000000
	// Position of UB1 field.
	GPDMA_CH_LLR_UB1_Pos = 0x1d
	// Bit mask of UB1 field.
	GPDMA_CH_LLR_UB1_Msk = 0x20000000
	// Bit UB1.
	GPDMA_CH_LLR_UB1 = 0x20000000
	// Position of UT2 field.
	GPDMA_CH_LLR_UT2_Pos = 0x1e
	// Bit mask of UT2 field.
	GPDMA_CH_LLR_UT2_Msk = 0x40000000
	// Bit UT2.
	GPDMA_CH_LLR_UT2 = 0x40000000
	// Position of UT1 field.
	GPDMA_CH_LLR_UT1_Pos = 0x1f
	// Bit mask of UT1 field.
	GPDMA_CH_LLR_UT1_Msk = 0x80000000
	// Bit UT1.
	GPDMA_CH_LLR_UT1 = 0x80000000

	// CH2D.LBAR: channel x linked-list base address register

	// CH2D.FCR: GPDMA channel x flag clear register

	// CH2D.SR: channel x status register

	// CH2D.CR: channel x control register

	// CH2D.TR1: GPDMA channel x transfer register 1

	// CH2D.TR2: GPDMA channel x transfer register 2

	// CH2D.BR1: GPDMA channel x block register 1
	// Position of BNDT field.
	GPDMA_CH2D_BR1_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	GPDMA_CH2D_BR1_BNDT_Msk = 0xffff
	// Position of BRC field.
	GPDMA_CH2D_BR1_BRC_Pos = 0x10
	// Bit mask of BRC field.
	GPDMA_CH2D_BR1_BRC_Msk = 0x7ff0000
	// Position of SDEC field.
	GPDMA_CH2D_BR1_SDEC_Pos = 0x1c
	// Bit mask of SDEC field.
	GPDMA_CH2D_BR1_SDEC_Msk = 0x10000000
	// Bit SDEC.
	GPDMA_CH2D_BR1_SDEC = 0x10000000
	// Position of DDEC field.
	GPDMA_CH2D_BR1_DDEC_Pos = 0x1d
	// Bit mask of DDEC field.
	GPDMA_CH2D_BR1_DDEC_Msk = 0x20000000
	// Bit DDEC.
	GPDMA_CH2D_BR1_DDEC = 0x20000000
	// Position of BRSDEC field.
	GPDMA_CH2D_BR1_BRSDEC_Pos = 0x1e
	// Bit mask of BRSDEC field.
	GPDMA_CH2D_BR1_BRSDEC_Msk = 0x40000000
	// Bit BRSDEC.
	GPDMA_CH2D_BR1_BRSDEC = 0x40000000
	// Position of BRDDEC field.
	GPDMA_CH2D_BR1_BRDDEC_Pos = 0x1f
	// Bit mask of BRDDEC field.
	GPDMA_CH2D_BR1_BRDDEC_Msk = 0x80000000
	// Bit BRDDEC.
	GPDMA_CH2D_BR1_BRDDEC = 0x80000000

	// CH2D.SAR: GPDMA channel x source address register

	// CH2D.DAR: GPDMA channel x destination address register

	// CH2D.TR3: GPDMA channel x transfer register 3
	// Position of SAO field.
	GPDMA_CH2D_TR3_SAO_Pos = 0x0
	// Bit mask of SAO field.
	GPDMA_CH2D_TR3_SAO_Msk = 0x1fff
	// Position of DAO field.
	GPDMA_CH2D_TR3_DAO_Pos = 0x10
	// Bit mask of DAO field.
	GPDMA_CH2D_TR3_DAO_Msk = 0x1fff0000

	// CH2D.BR2: GPDMA channel x block register 2
	// Position of BRSAO field.
	GPDMA_CH2D_BR2_BRSAO_Pos = 0x0
	// Bit mask of BRSAO field.
	GPDMA_CH2D_BR2_BRSAO_Msk = 0xffff
	// Position of BRDAO field.
	GPDMA_CH2D_BR2_BRDAO_Pos = 0x10
	// Bit mask of BRDAO field.
	GPDMA_CH2D_BR2_BRDAO_Msk = 0xffff0000

	// CH2D.LLR: GPDMA channel x linked-list address register
	// Position of LA field.
	GPDMA_CH2D_LLR_LA_Pos = 0x2
	// Bit mask of LA field.
	GPDMA_CH2D_LLR_LA_Msk = 0xfffc
	// Position of ULL field.
	GPDMA_CH2D_LLR_ULL_Pos = 0x10
	// Bit mask of ULL field.
	GPDMA_CH2D_LLR_ULL_Msk = 0x10000
	// Bit ULL.
	GPDMA_CH2D_LLR_ULL = 0x10000
	// Position of UB2 field.
	GPDMA_CH2D_LLR_UB2_Pos = 0x19
	// Bit mask of UB2 field.
	GPDMA_CH2D_LLR_UB2_Msk = 0x2000000
	// Bit UB2.
	GPDMA_CH2D_LLR_UB2 = 0x2000000
	// Position of UT3 field.
	GPDMA_CH2D_LLR_UT3_Pos = 0x1a
	// Bit mask of UT3 field.
	GPDMA_CH2D_LLR_UT3_Msk = 0x4000000
	// Bit UT3.
	GPDMA_CH2D_LLR_UT3 = 0x4000000
	// Position of UDA field.
	GPDMA_CH2D_LLR_UDA_Pos = 0x1b
	// Bit mask of UDA field.
	GPDMA_CH2D_LLR_UDA_Msk = 0x8000000
	// Bit UDA.
	GPDMA_CH2D_LLR_UDA = 0x8000000
	// Position of USA field.
	GPDMA_CH2D_LLR_USA_Pos = 0x1c
	// Bit mask of USA field.
	GPDMA_CH2D_LLR_USA_Msk = 0x10000000
	// Bit USA.
	GPDMA_CH2D_LLR_USA = 0x10000000
	// Position of UB1 field.
	GPDMA_CH2D_LLR_UB1_Pos = 0x1d
	// Bit mask of UB1 field.
	GPDMA_CH2D_LLR_UB1_Msk = 0x20000000
	// Bit UB1.
	GPDMA_CH2D_LLR_UB1 = 0x20000000
	// Position of UT2 field.
	GPDMA_CH2D_LLR_UT2_Pos = 0x1e
	// Bit mask of UT2 field.
	GPDMA_CH2D_LLR_UT2_Msk = 0x40000000
	// Bit UT2.
	GPDMA_CH2D_LLR_UT2 = 0x40000000
	// Position of UT1 field.
	GPDMA_CH2D_LLR_UT1_Pos = 0x1f
	// Bit mask of UT1 field.
	GPDMA_CH2D_LLR_UT1_Msk = 0x80000000
	// Bit UT1.
	GPDMA_CH2D_LLR_UT1 = 0x80000000
)

// Constants for GPIOA: General-purpose I/Os
const (
	// MODER: GPIO port mode register
	// Position of MODE0 field.
	GPIO_MODER_MODE0_Pos = 0x2
	// Bit mask of MODE0 field.
	GPIO_MODER_MODE0_Msk = 0xc
	// Input mode
	GPIO_MODER_MODE0_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE0_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE0_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE0_Analog = 0x3
	// Position of MODE1 field.
	GPIO_MODER_MODE1_Pos = 0x4
	// Bit mask of MODE1 field.
	GPIO_MODER_MODE1_Msk = 0x30
	// Input mode
	GPIO_MODER_MODE1_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE1_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE1_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE1_Analog = 0x3
	// Position of MODE2 field.
	GPIO_MODER_MODE2_Pos = 0x6
	// Bit mask of MODE2 field.
	GPIO_MODER_MODE2_Msk = 0xc0
	// Input mode
	GPIO_MODER_MODE2_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE2_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE2_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE2_Analog = 0x3
	// Position of MODE3 field.
	GPIO_MODER_MODE3_Pos = 0x8
	// Bit mask of MODE3 field.
	GPIO_MODER_MODE3_Msk = 0x300
	// Input mode
	GPIO_MODER_MODE3_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE3_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE3_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE3_Analog = 0x3
	// Position of MODE4 field.
	GPIO_MODER_MODE4_Pos = 0xa
	// Bit mask of MODE4 field.
	GPIO_MODER_MODE4_Msk = 0xc00
	// Input mode
	GPIO_MODER_MODE4_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE4_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE4_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE4_Analog = 0x3
	// Position of MODE5 field.
	GPIO_MODER_MODE5_Pos = 0xc
	// Bit mask of MODE5 field.
	GPIO_MODER_MODE5_Msk = 0x3000
	// Input mode
	GPIO_MODER_MODE5_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE5_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE5_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE5_Analog = 0x3
	// Position of MODE6 field.
	GPIO_MODER_MODE6_Pos = 0xe
	// Bit mask of MODE6 field.
	GPIO_MODER_MODE6_Msk = 0xc000
	// Input mode
	GPIO_MODER_MODE6_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE6_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE6_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE6_Analog = 0x3
	// Position of MODE7 field.
	GPIO_MODER_MODE7_Pos = 0x10
	// Bit mask of MODE7 field.
	GPIO_MODER_MODE7_Msk = 0x30000
	// Input mode
	GPIO_MODER_MODE7_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE7_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE7_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE7_Analog = 0x3
	// Position of MODE8 field.
	GPIO_MODER_MODE8_Pos = 0x12
	// Bit mask of MODE8 field.
	GPIO_MODER_MODE8_Msk = 0xc0000
	// Input mode
	GPIO_MODER_MODE8_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE8_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE8_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE8_Analog = 0x3
	// Position of MODE9 field.
	GPIO_MODER_MODE9_Pos = 0x14
	// Bit mask of MODE9 field.
	GPIO_MODER_MODE9_Msk = 0x300000
	// Input mode
	GPIO_MODER_MODE9_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE9_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE9_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE9_Analog = 0x3
	// Position of MODE10 field.
	GPIO_MODER_MODE10_Pos = 0x16
	// Bit mask of MODE10 field.
	GPIO_MODER_MODE10_Msk = 0xc00000
	// Input mode
	GPIO_MODER_MODE10_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE10_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE10_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE10_Analog = 0x3
	// Position of MODE11 field.
	GPIO_MODER_MODE11_Pos = 0x18
	// Bit mask of MODE11 field.
	GPIO_MODER_MODE11_Msk = 0x3000000
	// Input mode
	GPIO_MODER_MODE11_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE11_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE11_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE11_Analog = 0x3
	// Position of MODE12 field.
	GPIO_MODER_MODE12_Pos = 0x1a
	// Bit mask of MODE12 field.
	GPIO_MODER_MODE12_Msk = 0xc000000
	// Input mode
	GPIO_MODER_MODE12_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE12_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE12_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE12_Analog = 0x3
	// Position of MODE13 field.
	GPIO_MODER_MODE13_Pos = 0x1c
	// Bit mask of MODE13 field.
	GPIO_MODER_MODE13_Msk = 0x30000000
	// Input mode
	GPIO_MODER_MODE13_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE13_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE13_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE13_Analog = 0x3
	// Position of MODE14 field.
	GPIO_MODER_MODE14_Pos = 0x1e
	// Bit mask of MODE14 field.
	GPIO_MODER_MODE14_Msk = 0xc0000000
	// Input mode
	GPIO_MODER_MODE14_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE14_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE14_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE14_Analog = 0x3
	// Position of MODE15 field.
	GPIO_MODER_MODE15_Pos = 0x20
	// Bit mask of MODE15 field.
	GPIO_MODER_MODE15_Msk = 0x300000000
	// Input mode
	GPIO_MODER_MODE15_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODE15_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODE15_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODE15_Analog = 0x3

	// OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIO_OTYPER_OT0_Pos = 0x1
	// Bit mask of OT0 field.
	GPIO_OTYPER_OT0_Msk = 0x2
	// Bit OT0.
	GPIO_OTYPER_OT0 = 0x2
	// Output push-pull (reset state)
	GPIO_OTYPER_OT0_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT0_OpenDrain = 0x1
	// Position of OT1 field.
	GPIO_OTYPER_OT1_Pos = 0x2
	// Bit mask of OT1 field.
	GPIO_OTYPER_OT1_Msk = 0x4
	// Bit OT1.
	GPIO_OTYPER_OT1 = 0x4
	// Output push-pull (reset state)
	GPIO_OTYPER_OT1_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT1_OpenDrain = 0x1
	// Position of OT2 field.
	GPIO_OTYPER_OT2_Pos = 0x3
	// Bit mask of OT2 field.
	GPIO_OTYPER_OT2_Msk = 0x8
	// Bit OT2.
	GPIO_OTYPER_OT2 = 0x8
	// Output push-pull (reset state)
	GPIO_OTYPER_OT2_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT2_OpenDrain = 0x1
	// Position of OT3 field.
	GPIO_OTYPER_OT3_Pos = 0x4
	// Bit mask of OT3 field.
	GPIO_OTYPER_OT3_Msk = 0x10
	// Bit OT3.
	GPIO_OTYPER_OT3 = 0x10
	// Output push-pull (reset state)
	GPIO_OTYPER_OT3_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT3_OpenDrain = 0x1
	// Position of OT4 field.
	GPIO_OTYPER_OT4_Pos = 0x5
	// Bit mask of OT4 field.
	GPIO_OTYPER_OT4_Msk = 0x20
	// Bit OT4.
	GPIO_OTYPER_OT4 = 0x20
	// Output push-pull (reset state)
	GPIO_OTYPER_OT4_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT4_OpenDrain = 0x1
	// Position of OT5 field.
	GPIO_OTYPER_OT5_Pos = 0x6
	// Bit mask of OT5 field.
	GPIO_OTYPER_OT5_Msk = 0x40
	// Bit OT5.
	GPIO_OTYPER_OT5 = 0x40
	// Output push-pull (reset state)
	GPIO_OTYPER_OT5_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT5_OpenDrain = 0x1
	// Position of OT6 field.
	GPIO_OTYPER_OT6_Pos = 0x7
	// Bit mask of OT6 field.
	GPIO_OTYPER_OT6_Msk = 0x80
	// Bit OT6.
	GPIO_OTYPER_OT6 = 0x80
	// Output push-pull (reset state)
	GPIO_OTYPER_OT6_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT6_OpenDrain = 0x1
	// Position of OT7 field.
	GPIO_OTYPER_OT7_Pos = 0x8
	// Bit mask of OT7 field.
	GPIO_OTYPER_OT7_Msk = 0x100
	// Bit OT7.
	GPIO_OTYPER_OT7 = 0x100
	// Output push-pull (reset state)
	GPIO_OTYPER_OT7_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT7_OpenDrain = 0x1
	// Position of OT8 field.
	GPIO_OTYPER_OT8_Pos = 0x9
	// Bit mask of OT8 field.
	GPIO_OTYPER_OT8_Msk = 0x200
	// Bit OT8.
	GPIO_OTYPER_OT8 = 0x200
	// Output push-pull (reset state)
	GPIO_OTYPER_OT8_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT8_OpenDrain = 0x1
	// Position of OT9 field.
	GPIO_OTYPER_OT9_Pos = 0xa
	// Bit mask of OT9 field.
	GPIO_OTYPER_OT9_Msk = 0x400
	// Bit OT9.
	GPIO_OTYPER_OT9 = 0x400
	// Output push-pull (reset state)
	GPIO_OTYPER_OT9_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT9_OpenDrain = 0x1
	// Position of OT10 field.
	GPIO_OTYPER_OT10_Pos = 0xb
	// Bit mask of OT10 field.
	GPIO_OTYPER_OT10_Msk = 0x800
	// Bit OT10.
	GPIO_OTYPER_OT10 = 0x800
	// Output push-pull (reset state)
	GPIO_OTYPER_OT10_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT10_OpenDrain = 0x1
	// Position of OT11 field.
	GPIO_OTYPER_OT11_Pos = 0xc
	// Bit mask of OT11 field.
	GPIO_OTYPER_OT11_Msk = 0x1000
	// Bit OT11.
	GPIO_OTYPER_OT11 = 0x1000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT11_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT11_OpenDrain = 0x1
	// Position of OT12 field.
	GPIO_OTYPER_OT12_Pos = 0xd
	// Bit mask of OT12 field.
	GPIO_OTYPER_OT12_Msk = 0x2000
	// Bit OT12.
	GPIO_OTYPER_OT12 = 0x2000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT12_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT12_OpenDrain = 0x1
	// Position of OT13 field.
	GPIO_OTYPER_OT13_Pos = 0xe
	// Bit mask of OT13 field.
	GPIO_OTYPER_OT13_Msk = 0x4000
	// Bit OT13.
	GPIO_OTYPER_OT13 = 0x4000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT13_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT13_OpenDrain = 0x1
	// Position of OT14 field.
	GPIO_OTYPER_OT14_Pos = 0xf
	// Bit mask of OT14 field.
	GPIO_OTYPER_OT14_Msk = 0x8000
	// Bit OT14.
	GPIO_OTYPER_OT14 = 0x8000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT14_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT14_OpenDrain = 0x1
	// Position of OT15 field.
	GPIO_OTYPER_OT15_Pos = 0x10
	// Bit mask of OT15 field.
	GPIO_OTYPER_OT15_Msk = 0x10000
	// Bit OT15.
	GPIO_OTYPER_OT15 = 0x10000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT15_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT15_OpenDrain = 0x1

	// OSPEEDR: GPIO port output speed register
	// Position of OSPEED0 field.
	GPIO_OSPEEDR_OSPEED0_Pos = 0x2
	// Bit mask of OSPEED0 field.
	GPIO_OSPEEDR_OSPEED0_Msk = 0xc
	// Low speed
	GPIO_OSPEEDR_OSPEED0_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED0_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED0_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED0_VeryHighSpeed = 0x3
	// Position of OSPEED1 field.
	GPIO_OSPEEDR_OSPEED1_Pos = 0x4
	// Bit mask of OSPEED1 field.
	GPIO_OSPEEDR_OSPEED1_Msk = 0x30
	// Low speed
	GPIO_OSPEEDR_OSPEED1_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED1_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED1_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED1_VeryHighSpeed = 0x3
	// Position of OSPEED2 field.
	GPIO_OSPEEDR_OSPEED2_Pos = 0x6
	// Bit mask of OSPEED2 field.
	GPIO_OSPEEDR_OSPEED2_Msk = 0xc0
	// Low speed
	GPIO_OSPEEDR_OSPEED2_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED2_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED2_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED2_VeryHighSpeed = 0x3
	// Position of OSPEED3 field.
	GPIO_OSPEEDR_OSPEED3_Pos = 0x8
	// Bit mask of OSPEED3 field.
	GPIO_OSPEEDR_OSPEED3_Msk = 0x300
	// Low speed
	GPIO_OSPEEDR_OSPEED3_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED3_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED3_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED3_VeryHighSpeed = 0x3
	// Position of OSPEED4 field.
	GPIO_OSPEEDR_OSPEED4_Pos = 0xa
	// Bit mask of OSPEED4 field.
	GPIO_OSPEEDR_OSPEED4_Msk = 0xc00
	// Low speed
	GPIO_OSPEEDR_OSPEED4_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED4_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED4_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED4_VeryHighSpeed = 0x3
	// Position of OSPEED5 field.
	GPIO_OSPEEDR_OSPEED5_Pos = 0xc
	// Bit mask of OSPEED5 field.
	GPIO_OSPEEDR_OSPEED5_Msk = 0x3000
	// Low speed
	GPIO_OSPEEDR_OSPEED5_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED5_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED5_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED5_VeryHighSpeed = 0x3
	// Position of OSPEED6 field.
	GPIO_OSPEEDR_OSPEED6_Pos = 0xe
	// Bit mask of OSPEED6 field.
	GPIO_OSPEEDR_OSPEED6_Msk = 0xc000
	// Low speed
	GPIO_OSPEEDR_OSPEED6_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED6_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED6_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED6_VeryHighSpeed = 0x3
	// Position of OSPEED7 field.
	GPIO_OSPEEDR_OSPEED7_Pos = 0x10
	// Bit mask of OSPEED7 field.
	GPIO_OSPEEDR_OSPEED7_Msk = 0x30000
	// Low speed
	GPIO_OSPEEDR_OSPEED7_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED7_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED7_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED7_VeryHighSpeed = 0x3
	// Position of OSPEED8 field.
	GPIO_OSPEEDR_OSPEED8_Pos = 0x12
	// Bit mask of OSPEED8 field.
	GPIO_OSPEEDR_OSPEED8_Msk = 0xc0000
	// Low speed
	GPIO_OSPEEDR_OSPEED8_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED8_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED8_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED8_VeryHighSpeed = 0x3
	// Position of OSPEED9 field.
	GPIO_OSPEEDR_OSPEED9_Pos = 0x14
	// Bit mask of OSPEED9 field.
	GPIO_OSPEEDR_OSPEED9_Msk = 0x300000
	// Low speed
	GPIO_OSPEEDR_OSPEED9_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED9_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED9_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED9_VeryHighSpeed = 0x3
	// Position of OSPEED10 field.
	GPIO_OSPEEDR_OSPEED10_Pos = 0x16
	// Bit mask of OSPEED10 field.
	GPIO_OSPEEDR_OSPEED10_Msk = 0xc00000
	// Low speed
	GPIO_OSPEEDR_OSPEED10_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED10_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED10_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED10_VeryHighSpeed = 0x3
	// Position of OSPEED11 field.
	GPIO_OSPEEDR_OSPEED11_Pos = 0x18
	// Bit mask of OSPEED11 field.
	GPIO_OSPEEDR_OSPEED11_Msk = 0x3000000
	// Low speed
	GPIO_OSPEEDR_OSPEED11_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED11_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED11_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED11_VeryHighSpeed = 0x3
	// Position of OSPEED12 field.
	GPIO_OSPEEDR_OSPEED12_Pos = 0x1a
	// Bit mask of OSPEED12 field.
	GPIO_OSPEEDR_OSPEED12_Msk = 0xc000000
	// Low speed
	GPIO_OSPEEDR_OSPEED12_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED12_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED12_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED12_VeryHighSpeed = 0x3
	// Position of OSPEED13 field.
	GPIO_OSPEEDR_OSPEED13_Pos = 0x1c
	// Bit mask of OSPEED13 field.
	GPIO_OSPEEDR_OSPEED13_Msk = 0x30000000
	// Low speed
	GPIO_OSPEEDR_OSPEED13_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED13_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED13_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED13_VeryHighSpeed = 0x3
	// Position of OSPEED14 field.
	GPIO_OSPEEDR_OSPEED14_Pos = 0x1e
	// Bit mask of OSPEED14 field.
	GPIO_OSPEEDR_OSPEED14_Msk = 0xc0000000
	// Low speed
	GPIO_OSPEEDR_OSPEED14_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED14_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED14_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED14_VeryHighSpeed = 0x3
	// Position of OSPEED15 field.
	GPIO_OSPEEDR_OSPEED15_Pos = 0x20
	// Bit mask of OSPEED15 field.
	GPIO_OSPEEDR_OSPEED15_Msk = 0x300000000
	// Low speed
	GPIO_OSPEEDR_OSPEED15_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEED15_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEED15_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEED15_VeryHighSpeed = 0x3

	// PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPD0 field.
	GPIO_PUPDR_PUPD0_Pos = 0x2
	// Bit mask of PUPD0 field.
	GPIO_PUPDR_PUPD0_Msk = 0xc
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD0_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD0_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD0_PullDown = 0x2
	// Position of PUPD1 field.
	GPIO_PUPDR_PUPD1_Pos = 0x4
	// Bit mask of PUPD1 field.
	GPIO_PUPDR_PUPD1_Msk = 0x30
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD1_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD1_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD1_PullDown = 0x2
	// Position of PUPD2 field.
	GPIO_PUPDR_PUPD2_Pos = 0x6
	// Bit mask of PUPD2 field.
	GPIO_PUPDR_PUPD2_Msk = 0xc0
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD2_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD2_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD2_PullDown = 0x2
	// Position of PUPD3 field.
	GPIO_PUPDR_PUPD3_Pos = 0x8
	// Bit mask of PUPD3 field.
	GPIO_PUPDR_PUPD3_Msk = 0x300
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD3_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD3_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD3_PullDown = 0x2
	// Position of PUPD4 field.
	GPIO_PUPDR_PUPD4_Pos = 0xa
	// Bit mask of PUPD4 field.
	GPIO_PUPDR_PUPD4_Msk = 0xc00
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD4_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD4_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD4_PullDown = 0x2
	// Position of PUPD5 field.
	GPIO_PUPDR_PUPD5_Pos = 0xc
	// Bit mask of PUPD5 field.
	GPIO_PUPDR_PUPD5_Msk = 0x3000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD5_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD5_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD5_PullDown = 0x2
	// Position of PUPD6 field.
	GPIO_PUPDR_PUPD6_Pos = 0xe
	// Bit mask of PUPD6 field.
	GPIO_PUPDR_PUPD6_Msk = 0xc000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD6_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD6_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD6_PullDown = 0x2
	// Position of PUPD7 field.
	GPIO_PUPDR_PUPD7_Pos = 0x10
	// Bit mask of PUPD7 field.
	GPIO_PUPDR_PUPD7_Msk = 0x30000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD7_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD7_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD7_PullDown = 0x2
	// Position of PUPD8 field.
	GPIO_PUPDR_PUPD8_Pos = 0x12
	// Bit mask of PUPD8 field.
	GPIO_PUPDR_PUPD8_Msk = 0xc0000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD8_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD8_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD8_PullDown = 0x2
	// Position of PUPD9 field.
	GPIO_PUPDR_PUPD9_Pos = 0x14
	// Bit mask of PUPD9 field.
	GPIO_PUPDR_PUPD9_Msk = 0x300000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD9_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD9_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD9_PullDown = 0x2
	// Position of PUPD10 field.
	GPIO_PUPDR_PUPD10_Pos = 0x16
	// Bit mask of PUPD10 field.
	GPIO_PUPDR_PUPD10_Msk = 0xc00000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD10_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD10_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD10_PullDown = 0x2
	// Position of PUPD11 field.
	GPIO_PUPDR_PUPD11_Pos = 0x18
	// Bit mask of PUPD11 field.
	GPIO_PUPDR_PUPD11_Msk = 0x3000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD11_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD11_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD11_PullDown = 0x2
	// Position of PUPD12 field.
	GPIO_PUPDR_PUPD12_Pos = 0x1a
	// Bit mask of PUPD12 field.
	GPIO_PUPDR_PUPD12_Msk = 0xc000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD12_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD12_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD12_PullDown = 0x2
	// Position of PUPD13 field.
	GPIO_PUPDR_PUPD13_Pos = 0x1c
	// Bit mask of PUPD13 field.
	GPIO_PUPDR_PUPD13_Msk = 0x30000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD13_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD13_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD13_PullDown = 0x2
	// Position of PUPD14 field.
	GPIO_PUPDR_PUPD14_Pos = 0x1e
	// Bit mask of PUPD14 field.
	GPIO_PUPDR_PUPD14_Msk = 0xc0000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD14_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD14_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD14_PullDown = 0x2
	// Position of PUPD15 field.
	GPIO_PUPDR_PUPD15_Pos = 0x20
	// Bit mask of PUPD15 field.
	GPIO_PUPDR_PUPD15_Msk = 0x300000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPD15_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPD15_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPD15_PullDown = 0x2

	// IDR: GPIO port input data register
	// Position of ID0 field.
	GPIO_IDR_ID0_Pos = 0x1
	// Bit mask of ID0 field.
	GPIO_IDR_ID0_Msk = 0x2
	// Bit ID0.
	GPIO_IDR_ID0 = 0x2
	// Input is logic low
	GPIO_IDR_ID0_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID0_High = 0x1
	// Position of ID1 field.
	GPIO_IDR_ID1_Pos = 0x2
	// Bit mask of ID1 field.
	GPIO_IDR_ID1_Msk = 0x4
	// Bit ID1.
	GPIO_IDR_ID1 = 0x4
	// Input is logic low
	GPIO_IDR_ID1_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID1_High = 0x1
	// Position of ID2 field.
	GPIO_IDR_ID2_Pos = 0x3
	// Bit mask of ID2 field.
	GPIO_IDR_ID2_Msk = 0x8
	// Bit ID2.
	GPIO_IDR_ID2 = 0x8
	// Input is logic low
	GPIO_IDR_ID2_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID2_High = 0x1
	// Position of ID3 field.
	GPIO_IDR_ID3_Pos = 0x4
	// Bit mask of ID3 field.
	GPIO_IDR_ID3_Msk = 0x10
	// Bit ID3.
	GPIO_IDR_ID3 = 0x10
	// Input is logic low
	GPIO_IDR_ID3_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID3_High = 0x1
	// Position of ID4 field.
	GPIO_IDR_ID4_Pos = 0x5
	// Bit mask of ID4 field.
	GPIO_IDR_ID4_Msk = 0x20
	// Bit ID4.
	GPIO_IDR_ID4 = 0x20
	// Input is logic low
	GPIO_IDR_ID4_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID4_High = 0x1
	// Position of ID5 field.
	GPIO_IDR_ID5_Pos = 0x6
	// Bit mask of ID5 field.
	GPIO_IDR_ID5_Msk = 0x40
	// Bit ID5.
	GPIO_IDR_ID5 = 0x40
	// Input is logic low
	GPIO_IDR_ID5_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID5_High = 0x1
	// Position of ID6 field.
	GPIO_IDR_ID6_Pos = 0x7
	// Bit mask of ID6 field.
	GPIO_IDR_ID6_Msk = 0x80
	// Bit ID6.
	GPIO_IDR_ID6 = 0x80
	// Input is logic low
	GPIO_IDR_ID6_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID6_High = 0x1
	// Position of ID7 field.
	GPIO_IDR_ID7_Pos = 0x8
	// Bit mask of ID7 field.
	GPIO_IDR_ID7_Msk = 0x100
	// Bit ID7.
	GPIO_IDR_ID7 = 0x100
	// Input is logic low
	GPIO_IDR_ID7_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID7_High = 0x1
	// Position of ID8 field.
	GPIO_IDR_ID8_Pos = 0x9
	// Bit mask of ID8 field.
	GPIO_IDR_ID8_Msk = 0x200
	// Bit ID8.
	GPIO_IDR_ID8 = 0x200
	// Input is logic low
	GPIO_IDR_ID8_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID8_High = 0x1
	// Position of ID9 field.
	GPIO_IDR_ID9_Pos = 0xa
	// Bit mask of ID9 field.
	GPIO_IDR_ID9_Msk = 0x400
	// Bit ID9.
	GPIO_IDR_ID9 = 0x400
	// Input is logic low
	GPIO_IDR_ID9_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID9_High = 0x1
	// Position of ID10 field.
	GPIO_IDR_ID10_Pos = 0xb
	// Bit mask of ID10 field.
	GPIO_IDR_ID10_Msk = 0x800
	// Bit ID10.
	GPIO_IDR_ID10 = 0x800
	// Input is logic low
	GPIO_IDR_ID10_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID10_High = 0x1
	// Position of ID11 field.
	GPIO_IDR_ID11_Pos = 0xc
	// Bit mask of ID11 field.
	GPIO_IDR_ID11_Msk = 0x1000
	// Bit ID11.
	GPIO_IDR_ID11 = 0x1000
	// Input is logic low
	GPIO_IDR_ID11_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID11_High = 0x1
	// Position of ID12 field.
	GPIO_IDR_ID12_Pos = 0xd
	// Bit mask of ID12 field.
	GPIO_IDR_ID12_Msk = 0x2000
	// Bit ID12.
	GPIO_IDR_ID12 = 0x2000
	// Input is logic low
	GPIO_IDR_ID12_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID12_High = 0x1
	// Position of ID13 field.
	GPIO_IDR_ID13_Pos = 0xe
	// Bit mask of ID13 field.
	GPIO_IDR_ID13_Msk = 0x4000
	// Bit ID13.
	GPIO_IDR_ID13 = 0x4000
	// Input is logic low
	GPIO_IDR_ID13_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID13_High = 0x1
	// Position of ID14 field.
	GPIO_IDR_ID14_Pos = 0xf
	// Bit mask of ID14 field.
	GPIO_IDR_ID14_Msk = 0x8000
	// Bit ID14.
	GPIO_IDR_ID14 = 0x8000
	// Input is logic low
	GPIO_IDR_ID14_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID14_High = 0x1
	// Position of ID15 field.
	GPIO_IDR_ID15_Pos = 0x10
	// Bit mask of ID15 field.
	GPIO_IDR_ID15_Msk = 0x10000
	// Bit ID15.
	GPIO_IDR_ID15 = 0x10000
	// Input is logic low
	GPIO_IDR_ID15_Low = 0x0
	// Input is logic high
	GPIO_IDR_ID15_High = 0x1

	// ODR: GPIO port output data register
	// Position of OD0 field.
	GPIO_ODR_OD0_Pos = 0x1
	// Bit mask of OD0 field.
	GPIO_ODR_OD0_Msk = 0x2
	// Bit OD0.
	GPIO_ODR_OD0 = 0x2
	// Set output to logic low
	GPIO_ODR_OD0_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD0_High = 0x1
	// Position of OD1 field.
	GPIO_ODR_OD1_Pos = 0x2
	// Bit mask of OD1 field.
	GPIO_ODR_OD1_Msk = 0x4
	// Bit OD1.
	GPIO_ODR_OD1 = 0x4
	// Set output to logic low
	GPIO_ODR_OD1_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD1_High = 0x1
	// Position of OD2 field.
	GPIO_ODR_OD2_Pos = 0x3
	// Bit mask of OD2 field.
	GPIO_ODR_OD2_Msk = 0x8
	// Bit OD2.
	GPIO_ODR_OD2 = 0x8
	// Set output to logic low
	GPIO_ODR_OD2_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD2_High = 0x1
	// Position of OD3 field.
	GPIO_ODR_OD3_Pos = 0x4
	// Bit mask of OD3 field.
	GPIO_ODR_OD3_Msk = 0x10
	// Bit OD3.
	GPIO_ODR_OD3 = 0x10
	// Set output to logic low
	GPIO_ODR_OD3_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD3_High = 0x1
	// Position of OD4 field.
	GPIO_ODR_OD4_Pos = 0x5
	// Bit mask of OD4 field.
	GPIO_ODR_OD4_Msk = 0x20
	// Bit OD4.
	GPIO_ODR_OD4 = 0x20
	// Set output to logic low
	GPIO_ODR_OD4_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD4_High = 0x1
	// Position of OD5 field.
	GPIO_ODR_OD5_Pos = 0x6
	// Bit mask of OD5 field.
	GPIO_ODR_OD5_Msk = 0x40
	// Bit OD5.
	GPIO_ODR_OD5 = 0x40
	// Set output to logic low
	GPIO_ODR_OD5_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD5_High = 0x1
	// Position of OD6 field.
	GPIO_ODR_OD6_Pos = 0x7
	// Bit mask of OD6 field.
	GPIO_ODR_OD6_Msk = 0x80
	// Bit OD6.
	GPIO_ODR_OD6 = 0x80
	// Set output to logic low
	GPIO_ODR_OD6_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD6_High = 0x1
	// Position of OD7 field.
	GPIO_ODR_OD7_Pos = 0x8
	// Bit mask of OD7 field.
	GPIO_ODR_OD7_Msk = 0x100
	// Bit OD7.
	GPIO_ODR_OD7 = 0x100
	// Set output to logic low
	GPIO_ODR_OD7_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD7_High = 0x1
	// Position of OD8 field.
	GPIO_ODR_OD8_Pos = 0x9
	// Bit mask of OD8 field.
	GPIO_ODR_OD8_Msk = 0x200
	// Bit OD8.
	GPIO_ODR_OD8 = 0x200
	// Set output to logic low
	GPIO_ODR_OD8_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD8_High = 0x1
	// Position of OD9 field.
	GPIO_ODR_OD9_Pos = 0xa
	// Bit mask of OD9 field.
	GPIO_ODR_OD9_Msk = 0x400
	// Bit OD9.
	GPIO_ODR_OD9 = 0x400
	// Set output to logic low
	GPIO_ODR_OD9_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD9_High = 0x1
	// Position of OD10 field.
	GPIO_ODR_OD10_Pos = 0xb
	// Bit mask of OD10 field.
	GPIO_ODR_OD10_Msk = 0x800
	// Bit OD10.
	GPIO_ODR_OD10 = 0x800
	// Set output to logic low
	GPIO_ODR_OD10_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD10_High = 0x1
	// Position of OD11 field.
	GPIO_ODR_OD11_Pos = 0xc
	// Bit mask of OD11 field.
	GPIO_ODR_OD11_Msk = 0x1000
	// Bit OD11.
	GPIO_ODR_OD11 = 0x1000
	// Set output to logic low
	GPIO_ODR_OD11_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD11_High = 0x1
	// Position of OD12 field.
	GPIO_ODR_OD12_Pos = 0xd
	// Bit mask of OD12 field.
	GPIO_ODR_OD12_Msk = 0x2000
	// Bit OD12.
	GPIO_ODR_OD12 = 0x2000
	// Set output to logic low
	GPIO_ODR_OD12_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD12_High = 0x1
	// Position of OD13 field.
	GPIO_ODR_OD13_Pos = 0xe
	// Bit mask of OD13 field.
	GPIO_ODR_OD13_Msk = 0x4000
	// Bit OD13.
	GPIO_ODR_OD13 = 0x4000
	// Set output to logic low
	GPIO_ODR_OD13_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD13_High = 0x1
	// Position of OD14 field.
	GPIO_ODR_OD14_Pos = 0xf
	// Bit mask of OD14 field.
	GPIO_ODR_OD14_Msk = 0x8000
	// Bit OD14.
	GPIO_ODR_OD14 = 0x8000
	// Set output to logic low
	GPIO_ODR_OD14_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD14_High = 0x1
	// Position of OD15 field.
	GPIO_ODR_OD15_Pos = 0x10
	// Bit mask of OD15 field.
	GPIO_ODR_OD15_Msk = 0x10000
	// Bit OD15.
	GPIO_ODR_OD15 = 0x10000
	// Set output to logic low
	GPIO_ODR_OD15_Low = 0x0
	// Set output to logic high
	GPIO_ODR_OD15_High = 0x1

	// BSRR: GPIO port bit set/reset register
	// Position of BS0 field.
	GPIO_BSRR_BS0_Pos = 0x1
	// Bit mask of BS0 field.
	GPIO_BSRR_BS0_Msk = 0x2
	// Bit BS0.
	GPIO_BSRR_BS0 = 0x2
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS0_Set = 0x1
	// Position of BS1 field.
	GPIO_BSRR_BS1_Pos = 0x2
	// Bit mask of BS1 field.
	GPIO_BSRR_BS1_Msk = 0x4
	// Bit BS1.
	GPIO_BSRR_BS1 = 0x4
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS1_Set = 0x1
	// Position of BS2 field.
	GPIO_BSRR_BS2_Pos = 0x3
	// Bit mask of BS2 field.
	GPIO_BSRR_BS2_Msk = 0x8
	// Bit BS2.
	GPIO_BSRR_BS2 = 0x8
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS2_Set = 0x1
	// Position of BS3 field.
	GPIO_BSRR_BS3_Pos = 0x4
	// Bit mask of BS3 field.
	GPIO_BSRR_BS3_Msk = 0x10
	// Bit BS3.
	GPIO_BSRR_BS3 = 0x10
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS3_Set = 0x1
	// Position of BS4 field.
	GPIO_BSRR_BS4_Pos = 0x5
	// Bit mask of BS4 field.
	GPIO_BSRR_BS4_Msk = 0x20
	// Bit BS4.
	GPIO_BSRR_BS4 = 0x20
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS4_Set = 0x1
	// Position of BS5 field.
	GPIO_BSRR_BS5_Pos = 0x6
	// Bit mask of BS5 field.
	GPIO_BSRR_BS5_Msk = 0x40
	// Bit BS5.
	GPIO_BSRR_BS5 = 0x40
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS5_Set = 0x1
	// Position of BS6 field.
	GPIO_BSRR_BS6_Pos = 0x7
	// Bit mask of BS6 field.
	GPIO_BSRR_BS6_Msk = 0x80
	// Bit BS6.
	GPIO_BSRR_BS6 = 0x80
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS6_Set = 0x1
	// Position of BS7 field.
	GPIO_BSRR_BS7_Pos = 0x8
	// Bit mask of BS7 field.
	GPIO_BSRR_BS7_Msk = 0x100
	// Bit BS7.
	GPIO_BSRR_BS7 = 0x100
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS7_Set = 0x1
	// Position of BS8 field.
	GPIO_BSRR_BS8_Pos = 0x9
	// Bit mask of BS8 field.
	GPIO_BSRR_BS8_Msk = 0x200
	// Bit BS8.
	GPIO_BSRR_BS8 = 0x200
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS8_Set = 0x1
	// Position of BS9 field.
	GPIO_BSRR_BS9_Pos = 0xa
	// Bit mask of BS9 field.
	GPIO_BSRR_BS9_Msk = 0x400
	// Bit BS9.
	GPIO_BSRR_BS9 = 0x400
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS9_Set = 0x1
	// Position of BS10 field.
	GPIO_BSRR_BS10_Pos = 0xb
	// Bit mask of BS10 field.
	GPIO_BSRR_BS10_Msk = 0x800
	// Bit BS10.
	GPIO_BSRR_BS10 = 0x800
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS10_Set = 0x1
	// Position of BS11 field.
	GPIO_BSRR_BS11_Pos = 0xc
	// Bit mask of BS11 field.
	GPIO_BSRR_BS11_Msk = 0x1000
	// Bit BS11.
	GPIO_BSRR_BS11 = 0x1000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS11_Set = 0x1
	// Position of BS12 field.
	GPIO_BSRR_BS12_Pos = 0xd
	// Bit mask of BS12 field.
	GPIO_BSRR_BS12_Msk = 0x2000
	// Bit BS12.
	GPIO_BSRR_BS12 = 0x2000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS12_Set = 0x1
	// Position of BS13 field.
	GPIO_BSRR_BS13_Pos = 0xe
	// Bit mask of BS13 field.
	GPIO_BSRR_BS13_Msk = 0x4000
	// Bit BS13.
	GPIO_BSRR_BS13 = 0x4000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS13_Set = 0x1
	// Position of BS14 field.
	GPIO_BSRR_BS14_Pos = 0xf
	// Bit mask of BS14 field.
	GPIO_BSRR_BS14_Msk = 0x8000
	// Bit BS14.
	GPIO_BSRR_BS14 = 0x8000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS14_Set = 0x1
	// Position of BS15 field.
	GPIO_BSRR_BS15_Pos = 0x10
	// Bit mask of BS15 field.
	GPIO_BSRR_BS15_Msk = 0x10000
	// Bit BS15.
	GPIO_BSRR_BS15 = 0x10000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS15_Set = 0x1
	// Position of BR0 field.
	GPIO_BSRR_BR0_Pos = 0x11
	// Bit mask of BR0 field.
	GPIO_BSRR_BR0_Msk = 0x20000
	// Bit BR0.
	GPIO_BSRR_BR0 = 0x20000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BSRR_BR1_Pos = 0x12
	// Bit mask of BR1 field.
	GPIO_BSRR_BR1_Msk = 0x40000
	// Bit BR1.
	GPIO_BSRR_BR1 = 0x40000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BSRR_BR2_Pos = 0x13
	// Bit mask of BR2 field.
	GPIO_BSRR_BR2_Msk = 0x80000
	// Bit BR2.
	GPIO_BSRR_BR2 = 0x80000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BSRR_BR3_Pos = 0x14
	// Bit mask of BR3 field.
	GPIO_BSRR_BR3_Msk = 0x100000
	// Bit BR3.
	GPIO_BSRR_BR3 = 0x100000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BSRR_BR4_Pos = 0x15
	// Bit mask of BR4 field.
	GPIO_BSRR_BR4_Msk = 0x200000
	// Bit BR4.
	GPIO_BSRR_BR4 = 0x200000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BSRR_BR5_Pos = 0x16
	// Bit mask of BR5 field.
	GPIO_BSRR_BR5_Msk = 0x400000
	// Bit BR5.
	GPIO_BSRR_BR5 = 0x400000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BSRR_BR6_Pos = 0x17
	// Bit mask of BR6 field.
	GPIO_BSRR_BR6_Msk = 0x800000
	// Bit BR6.
	GPIO_BSRR_BR6 = 0x800000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BSRR_BR7_Pos = 0x18
	// Bit mask of BR7 field.
	GPIO_BSRR_BR7_Msk = 0x1000000
	// Bit BR7.
	GPIO_BSRR_BR7 = 0x1000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BSRR_BR8_Pos = 0x19
	// Bit mask of BR8 field.
	GPIO_BSRR_BR8_Msk = 0x2000000
	// Bit BR8.
	GPIO_BSRR_BR8 = 0x2000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BSRR_BR9_Pos = 0x1a
	// Bit mask of BR9 field.
	GPIO_BSRR_BR9_Msk = 0x4000000
	// Bit BR9.
	GPIO_BSRR_BR9 = 0x4000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BSRR_BR10_Pos = 0x1b
	// Bit mask of BR10 field.
	GPIO_BSRR_BR10_Msk = 0x8000000
	// Bit BR10.
	GPIO_BSRR_BR10 = 0x8000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BSRR_BR11_Pos = 0x1c
	// Bit mask of BR11 field.
	GPIO_BSRR_BR11_Msk = 0x10000000
	// Bit BR11.
	GPIO_BSRR_BR11 = 0x10000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR11_Reset = 0x1
	// Position of BR12 field.
	GPIO_BSRR_BR12_Pos = 0x1d
	// Bit mask of BR12 field.
	GPIO_BSRR_BR12_Msk = 0x20000000
	// Bit BR12.
	GPIO_BSRR_BR12 = 0x20000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR12_Reset = 0x1
	// Position of BR13 field.
	GPIO_BSRR_BR13_Pos = 0x1e
	// Bit mask of BR13 field.
	GPIO_BSRR_BR13_Msk = 0x40000000
	// Bit BR13.
	GPIO_BSRR_BR13 = 0x40000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR13_Reset = 0x1
	// Position of BR14 field.
	GPIO_BSRR_BR14_Pos = 0x1f
	// Bit mask of BR14 field.
	GPIO_BSRR_BR14_Msk = 0x80000000
	// Bit BR14.
	GPIO_BSRR_BR14 = 0x80000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR14_Reset = 0x1
	// Position of BR15 field.
	GPIO_BSRR_BR15_Pos = 0x20
	// Bit mask of BR15 field.
	GPIO_BSRR_BR15_Msk = 0x100000000
	// Bit BR15.
	GPIO_BSRR_BR15 = 0x100000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR15_Reset = 0x1

	// LCKR: GPIO port configuration lock register
	// Position of LCK0 field.
	GPIO_LCKR_LCK0_Pos = 0x1
	// Bit mask of LCK0 field.
	GPIO_LCKR_LCK0_Msk = 0x2
	// Bit LCK0.
	GPIO_LCKR_LCK0 = 0x2
	// Port configuration not locked
	GPIO_LCKR_LCK0_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK0_Locked = 0x1
	// Position of LCK1 field.
	GPIO_LCKR_LCK1_Pos = 0x2
	// Bit mask of LCK1 field.
	GPIO_LCKR_LCK1_Msk = 0x4
	// Bit LCK1.
	GPIO_LCKR_LCK1 = 0x4
	// Port configuration not locked
	GPIO_LCKR_LCK1_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK1_Locked = 0x1
	// Position of LCK2 field.
	GPIO_LCKR_LCK2_Pos = 0x3
	// Bit mask of LCK2 field.
	GPIO_LCKR_LCK2_Msk = 0x8
	// Bit LCK2.
	GPIO_LCKR_LCK2 = 0x8
	// Port configuration not locked
	GPIO_LCKR_LCK2_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK2_Locked = 0x1
	// Position of LCK3 field.
	GPIO_LCKR_LCK3_Pos = 0x4
	// Bit mask of LCK3 field.
	GPIO_LCKR_LCK3_Msk = 0x10
	// Bit LCK3.
	GPIO_LCKR_LCK3 = 0x10
	// Port configuration not locked
	GPIO_LCKR_LCK3_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK3_Locked = 0x1
	// Position of LCK4 field.
	GPIO_LCKR_LCK4_Pos = 0x5
	// Bit mask of LCK4 field.
	GPIO_LCKR_LCK4_Msk = 0x20
	// Bit LCK4.
	GPIO_LCKR_LCK4 = 0x20
	// Port configuration not locked
	GPIO_LCKR_LCK4_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK4_Locked = 0x1
	// Position of LCK5 field.
	GPIO_LCKR_LCK5_Pos = 0x6
	// Bit mask of LCK5 field.
	GPIO_LCKR_LCK5_Msk = 0x40
	// Bit LCK5.
	GPIO_LCKR_LCK5 = 0x40
	// Port configuration not locked
	GPIO_LCKR_LCK5_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK5_Locked = 0x1
	// Position of LCK6 field.
	GPIO_LCKR_LCK6_Pos = 0x7
	// Bit mask of LCK6 field.
	GPIO_LCKR_LCK6_Msk = 0x80
	// Bit LCK6.
	GPIO_LCKR_LCK6 = 0x80
	// Port configuration not locked
	GPIO_LCKR_LCK6_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK6_Locked = 0x1
	// Position of LCK7 field.
	GPIO_LCKR_LCK7_Pos = 0x8
	// Bit mask of LCK7 field.
	GPIO_LCKR_LCK7_Msk = 0x100
	// Bit LCK7.
	GPIO_LCKR_LCK7 = 0x100
	// Port configuration not locked
	GPIO_LCKR_LCK7_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK7_Locked = 0x1
	// Position of LCK8 field.
	GPIO_LCKR_LCK8_Pos = 0x9
	// Bit mask of LCK8 field.
	GPIO_LCKR_LCK8_Msk = 0x200
	// Bit LCK8.
	GPIO_LCKR_LCK8 = 0x200
	// Port configuration not locked
	GPIO_LCKR_LCK8_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK8_Locked = 0x1
	// Position of LCK9 field.
	GPIO_LCKR_LCK9_Pos = 0xa
	// Bit mask of LCK9 field.
	GPIO_LCKR_LCK9_Msk = 0x400
	// Bit LCK9.
	GPIO_LCKR_LCK9 = 0x400
	// Port configuration not locked
	GPIO_LCKR_LCK9_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK9_Locked = 0x1
	// Position of LCK10 field.
	GPIO_LCKR_LCK10_Pos = 0xb
	// Bit mask of LCK10 field.
	GPIO_LCKR_LCK10_Msk = 0x800
	// Bit LCK10.
	GPIO_LCKR_LCK10 = 0x800
	// Port configuration not locked
	GPIO_LCKR_LCK10_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK10_Locked = 0x1
	// Position of LCK11 field.
	GPIO_LCKR_LCK11_Pos = 0xc
	// Bit mask of LCK11 field.
	GPIO_LCKR_LCK11_Msk = 0x1000
	// Bit LCK11.
	GPIO_LCKR_LCK11 = 0x1000
	// Port configuration not locked
	GPIO_LCKR_LCK11_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK11_Locked = 0x1
	// Position of LCK12 field.
	GPIO_LCKR_LCK12_Pos = 0xd
	// Bit mask of LCK12 field.
	GPIO_LCKR_LCK12_Msk = 0x2000
	// Bit LCK12.
	GPIO_LCKR_LCK12 = 0x2000
	// Port configuration not locked
	GPIO_LCKR_LCK12_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK12_Locked = 0x1
	// Position of LCK13 field.
	GPIO_LCKR_LCK13_Pos = 0xe
	// Bit mask of LCK13 field.
	GPIO_LCKR_LCK13_Msk = 0x4000
	// Bit LCK13.
	GPIO_LCKR_LCK13 = 0x4000
	// Port configuration not locked
	GPIO_LCKR_LCK13_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK13_Locked = 0x1
	// Position of LCK14 field.
	GPIO_LCKR_LCK14_Pos = 0xf
	// Bit mask of LCK14 field.
	GPIO_LCKR_LCK14_Msk = 0x8000
	// Bit LCK14.
	GPIO_LCKR_LCK14 = 0x8000
	// Port configuration not locked
	GPIO_LCKR_LCK14_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK14_Locked = 0x1
	// Position of LCK15 field.
	GPIO_LCKR_LCK15_Pos = 0x10
	// Bit mask of LCK15 field.
	GPIO_LCKR_LCK15_Msk = 0x10000
	// Bit LCK15.
	GPIO_LCKR_LCK15 = 0x10000
	// Port configuration not locked
	GPIO_LCKR_LCK15_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK15_Locked = 0x1
	// Position of LCKK field.
	GPIO_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIO_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIO_LCKR_LCKK = 0x10000
	// Port configuration lock key not active
	GPIO_LCKR_LCKK_NotActive = 0x0
	// Port configuration lock key active
	GPIO_LCKR_LCKK_Active = 0x1

	// AFRL: GPIO alternate function low register
	// Position of AFSEL0 field.
	GPIO_AFRL_AFSEL0_Pos = 0x4
	// Bit mask of AFSEL0 field.
	GPIO_AFRL_AFSEL0_Msk = 0xf0
	// AF0
	GPIO_AFRL_AFSEL0_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL0_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL0_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL0_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL0_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL0_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL0_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL0_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL0_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL0_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL0_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL0_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL0_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL0_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL0_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL0_AF15 = 0xf
	// Position of AFSEL1 field.
	GPIO_AFRL_AFSEL1_Pos = 0x8
	// Bit mask of AFSEL1 field.
	GPIO_AFRL_AFSEL1_Msk = 0xf00
	// AF0
	GPIO_AFRL_AFSEL1_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL1_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL1_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL1_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL1_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL1_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL1_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL1_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL1_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL1_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL1_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL1_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL1_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL1_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL1_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL1_AF15 = 0xf
	// Position of AFSEL2 field.
	GPIO_AFRL_AFSEL2_Pos = 0xc
	// Bit mask of AFSEL2 field.
	GPIO_AFRL_AFSEL2_Msk = 0xf000
	// AF0
	GPIO_AFRL_AFSEL2_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL2_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL2_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL2_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL2_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL2_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL2_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL2_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL2_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL2_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL2_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL2_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL2_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL2_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL2_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL2_AF15 = 0xf
	// Position of AFSEL3 field.
	GPIO_AFRL_AFSEL3_Pos = 0x10
	// Bit mask of AFSEL3 field.
	GPIO_AFRL_AFSEL3_Msk = 0xf0000
	// AF0
	GPIO_AFRL_AFSEL3_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL3_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL3_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL3_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL3_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL3_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL3_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL3_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL3_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL3_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL3_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL3_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL3_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL3_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL3_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL3_AF15 = 0xf
	// Position of AFSEL4 field.
	GPIO_AFRL_AFSEL4_Pos = 0x14
	// Bit mask of AFSEL4 field.
	GPIO_AFRL_AFSEL4_Msk = 0xf00000
	// AF0
	GPIO_AFRL_AFSEL4_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL4_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL4_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL4_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL4_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL4_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL4_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL4_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL4_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL4_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL4_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL4_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL4_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL4_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL4_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL4_AF15 = 0xf
	// Position of AFSEL5 field.
	GPIO_AFRL_AFSEL5_Pos = 0x18
	// Bit mask of AFSEL5 field.
	GPIO_AFRL_AFSEL5_Msk = 0xf000000
	// AF0
	GPIO_AFRL_AFSEL5_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL5_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL5_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL5_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL5_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL5_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL5_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL5_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL5_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL5_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL5_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL5_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL5_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL5_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL5_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL5_AF15 = 0xf
	// Position of AFSEL6 field.
	GPIO_AFRL_AFSEL6_Pos = 0x1c
	// Bit mask of AFSEL6 field.
	GPIO_AFRL_AFSEL6_Msk = 0xf0000000
	// AF0
	GPIO_AFRL_AFSEL6_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL6_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL6_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL6_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL6_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL6_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL6_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL6_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL6_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL6_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL6_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL6_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL6_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL6_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL6_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL6_AF15 = 0xf
	// Position of AFSEL7 field.
	GPIO_AFRL_AFSEL7_Pos = 0x20
	// Bit mask of AFSEL7 field.
	GPIO_AFRL_AFSEL7_Msk = 0xf00000000
	// AF0
	GPIO_AFRL_AFSEL7_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFSEL7_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFSEL7_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFSEL7_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFSEL7_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFSEL7_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFSEL7_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFSEL7_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFSEL7_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFSEL7_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFSEL7_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFSEL7_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFSEL7_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFSEL7_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFSEL7_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFSEL7_AF15 = 0xf

	// AFRH: GPIO alternate function high register
	// Position of AFSEL8 field.
	GPIO_AFRH_AFSEL8_Pos = 0x4
	// Bit mask of AFSEL8 field.
	GPIO_AFRH_AFSEL8_Msk = 0xf0
	// AF0
	GPIO_AFRH_AFSEL8_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL8_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL8_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL8_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL8_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL8_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL8_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL8_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL8_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL8_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL8_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL8_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL8_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL8_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL8_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL8_AF15 = 0xf
	// Position of AFSEL9 field.
	GPIO_AFRH_AFSEL9_Pos = 0x8
	// Bit mask of AFSEL9 field.
	GPIO_AFRH_AFSEL9_Msk = 0xf00
	// AF0
	GPIO_AFRH_AFSEL9_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL9_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL9_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL9_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL9_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL9_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL9_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL9_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL9_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL9_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL9_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL9_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL9_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL9_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL9_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL9_AF15 = 0xf
	// Position of AFSEL10 field.
	GPIO_AFRH_AFSEL10_Pos = 0xc
	// Bit mask of AFSEL10 field.
	GPIO_AFRH_AFSEL10_Msk = 0xf000
	// AF0
	GPIO_AFRH_AFSEL10_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL10_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL10_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL10_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL10_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL10_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL10_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL10_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL10_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL10_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL10_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL10_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL10_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL10_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL10_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL10_AF15 = 0xf
	// Position of AFSEL11 field.
	GPIO_AFRH_AFSEL11_Pos = 0x10
	// Bit mask of AFSEL11 field.
	GPIO_AFRH_AFSEL11_Msk = 0xf0000
	// AF0
	GPIO_AFRH_AFSEL11_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL11_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL11_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL11_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL11_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL11_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL11_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL11_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL11_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL11_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL11_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL11_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL11_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL11_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL11_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL11_AF15 = 0xf
	// Position of AFSEL12 field.
	GPIO_AFRH_AFSEL12_Pos = 0x14
	// Bit mask of AFSEL12 field.
	GPIO_AFRH_AFSEL12_Msk = 0xf00000
	// AF0
	GPIO_AFRH_AFSEL12_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL12_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL12_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL12_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL12_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL12_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL12_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL12_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL12_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL12_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL12_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL12_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL12_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL12_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL12_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL12_AF15 = 0xf
	// Position of AFSEL13 field.
	GPIO_AFRH_AFSEL13_Pos = 0x18
	// Bit mask of AFSEL13 field.
	GPIO_AFRH_AFSEL13_Msk = 0xf000000
	// AF0
	GPIO_AFRH_AFSEL13_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL13_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL13_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL13_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL13_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL13_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL13_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL13_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL13_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL13_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL13_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL13_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL13_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL13_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL13_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL13_AF15 = 0xf
	// Position of AFSEL14 field.
	GPIO_AFRH_AFSEL14_Pos = 0x1c
	// Bit mask of AFSEL14 field.
	GPIO_AFRH_AFSEL14_Msk = 0xf0000000
	// AF0
	GPIO_AFRH_AFSEL14_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL14_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL14_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL14_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL14_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL14_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL14_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL14_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL14_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL14_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL14_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL14_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL14_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL14_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL14_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL14_AF15 = 0xf
	// Position of AFSEL15 field.
	GPIO_AFRH_AFSEL15_Pos = 0x20
	// Bit mask of AFSEL15 field.
	GPIO_AFRH_AFSEL15_Msk = 0xf00000000
	// AF0
	GPIO_AFRH_AFSEL15_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFSEL15_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFSEL15_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFSEL15_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFSEL15_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFSEL15_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFSEL15_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFSEL15_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFSEL15_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFSEL15_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFSEL15_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFSEL15_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFSEL15_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFSEL15_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFSEL15_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFSEL15_AF15 = 0xf

	// BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIO_BRR_BR0_Pos = 0x1
	// Bit mask of BR0 field.
	GPIO_BRR_BR0_Msk = 0x2
	// Bit BR0.
	GPIO_BRR_BR0 = 0x2
	// No action on the corresponding ODx bit
	GPIO_BRR_BR0_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BRR_BR1_Pos = 0x2
	// Bit mask of BR1 field.
	GPIO_BRR_BR1_Msk = 0x4
	// Bit BR1.
	GPIO_BRR_BR1 = 0x4
	// No action on the corresponding ODx bit
	GPIO_BRR_BR1_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BRR_BR2_Pos = 0x3
	// Bit mask of BR2 field.
	GPIO_BRR_BR2_Msk = 0x8
	// Bit BR2.
	GPIO_BRR_BR2 = 0x8
	// No action on the corresponding ODx bit
	GPIO_BRR_BR2_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BRR_BR3_Pos = 0x4
	// Bit mask of BR3 field.
	GPIO_BRR_BR3_Msk = 0x10
	// Bit BR3.
	GPIO_BRR_BR3 = 0x10
	// No action on the corresponding ODx bit
	GPIO_BRR_BR3_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BRR_BR4_Pos = 0x5
	// Bit mask of BR4 field.
	GPIO_BRR_BR4_Msk = 0x20
	// Bit BR4.
	GPIO_BRR_BR4 = 0x20
	// No action on the corresponding ODx bit
	GPIO_BRR_BR4_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BRR_BR5_Pos = 0x6
	// Bit mask of BR5 field.
	GPIO_BRR_BR5_Msk = 0x40
	// Bit BR5.
	GPIO_BRR_BR5 = 0x40
	// No action on the corresponding ODx bit
	GPIO_BRR_BR5_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BRR_BR6_Pos = 0x7
	// Bit mask of BR6 field.
	GPIO_BRR_BR6_Msk = 0x80
	// Bit BR6.
	GPIO_BRR_BR6 = 0x80
	// No action on the corresponding ODx bit
	GPIO_BRR_BR6_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BRR_BR7_Pos = 0x8
	// Bit mask of BR7 field.
	GPIO_BRR_BR7_Msk = 0x100
	// Bit BR7.
	GPIO_BRR_BR7 = 0x100
	// No action on the corresponding ODx bit
	GPIO_BRR_BR7_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BRR_BR8_Pos = 0x9
	// Bit mask of BR8 field.
	GPIO_BRR_BR8_Msk = 0x200
	// Bit BR8.
	GPIO_BRR_BR8 = 0x200
	// No action on the corresponding ODx bit
	GPIO_BRR_BR8_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BRR_BR9_Pos = 0xa
	// Bit mask of BR9 field.
	GPIO_BRR_BR9_Msk = 0x400
	// Bit BR9.
	GPIO_BRR_BR9 = 0x400
	// No action on the corresponding ODx bit
	GPIO_BRR_BR9_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BRR_BR10_Pos = 0xb
	// Bit mask of BR10 field.
	GPIO_BRR_BR10_Msk = 0x800
	// Bit BR10.
	GPIO_BRR_BR10 = 0x800
	// No action on the corresponding ODx bit
	GPIO_BRR_BR10_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BRR_BR11_Pos = 0xc
	// Bit mask of BR11 field.
	GPIO_BRR_BR11_Msk = 0x1000
	// Bit BR11.
	GPIO_BRR_BR11 = 0x1000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR11_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR11_Reset = 0x1
	// Position of BR12 field.
	GPIO_BRR_BR12_Pos = 0xd
	// Bit mask of BR12 field.
	GPIO_BRR_BR12_Msk = 0x2000
	// Bit BR12.
	GPIO_BRR_BR12 = 0x2000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR12_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR12_Reset = 0x1
	// Position of BR13 field.
	GPIO_BRR_BR13_Pos = 0xe
	// Bit mask of BR13 field.
	GPIO_BRR_BR13_Msk = 0x4000
	// Bit BR13.
	GPIO_BRR_BR13 = 0x4000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR13_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR13_Reset = 0x1
	// Position of BR14 field.
	GPIO_BRR_BR14_Pos = 0xf
	// Bit mask of BR14 field.
	GPIO_BRR_BR14_Msk = 0x8000
	// Bit BR14.
	GPIO_BRR_BR14 = 0x8000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR14_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR14_Reset = 0x1
	// Position of BR15 field.
	GPIO_BRR_BR15_Pos = 0x10
	// Bit mask of BR15 field.
	GPIO_BRR_BR15_Msk = 0x10000
	// Bit BR15.
	GPIO_BRR_BR15 = 0x10000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR15_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR15_Reset = 0x1

	// HSLVR: GPIO high-speed low-voltage register
	// Position of HSLV0 field.
	GPIO_HSLVR_HSLV0_Pos = 0x1
	// Bit mask of HSLV0 field.
	GPIO_HSLVR_HSLV0_Msk = 0x2
	// Bit HSLV0.
	GPIO_HSLVR_HSLV0 = 0x2
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV0_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV0_Enabled = 0x1
	// Position of HSLV1 field.
	GPIO_HSLVR_HSLV1_Pos = 0x2
	// Bit mask of HSLV1 field.
	GPIO_HSLVR_HSLV1_Msk = 0x4
	// Bit HSLV1.
	GPIO_HSLVR_HSLV1 = 0x4
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV1_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV1_Enabled = 0x1
	// Position of HSLV2 field.
	GPIO_HSLVR_HSLV2_Pos = 0x3
	// Bit mask of HSLV2 field.
	GPIO_HSLVR_HSLV2_Msk = 0x8
	// Bit HSLV2.
	GPIO_HSLVR_HSLV2 = 0x8
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV2_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV2_Enabled = 0x1
	// Position of HSLV3 field.
	GPIO_HSLVR_HSLV3_Pos = 0x4
	// Bit mask of HSLV3 field.
	GPIO_HSLVR_HSLV3_Msk = 0x10
	// Bit HSLV3.
	GPIO_HSLVR_HSLV3 = 0x10
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV3_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV3_Enabled = 0x1
	// Position of HSLV4 field.
	GPIO_HSLVR_HSLV4_Pos = 0x5
	// Bit mask of HSLV4 field.
	GPIO_HSLVR_HSLV4_Msk = 0x20
	// Bit HSLV4.
	GPIO_HSLVR_HSLV4 = 0x20
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV4_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV4_Enabled = 0x1
	// Position of HSLV5 field.
	GPIO_HSLVR_HSLV5_Pos = 0x6
	// Bit mask of HSLV5 field.
	GPIO_HSLVR_HSLV5_Msk = 0x40
	// Bit HSLV5.
	GPIO_HSLVR_HSLV5 = 0x40
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV5_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV5_Enabled = 0x1
	// Position of HSLV6 field.
	GPIO_HSLVR_HSLV6_Pos = 0x7
	// Bit mask of HSLV6 field.
	GPIO_HSLVR_HSLV6_Msk = 0x80
	// Bit HSLV6.
	GPIO_HSLVR_HSLV6 = 0x80
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV6_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV6_Enabled = 0x1
	// Position of HSLV7 field.
	GPIO_HSLVR_HSLV7_Pos = 0x8
	// Bit mask of HSLV7 field.
	GPIO_HSLVR_HSLV7_Msk = 0x100
	// Bit HSLV7.
	GPIO_HSLVR_HSLV7 = 0x100
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV7_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV7_Enabled = 0x1
	// Position of HSLV8 field.
	GPIO_HSLVR_HSLV8_Pos = 0x9
	// Bit mask of HSLV8 field.
	GPIO_HSLVR_HSLV8_Msk = 0x200
	// Bit HSLV8.
	GPIO_HSLVR_HSLV8 = 0x200
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV8_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV8_Enabled = 0x1
	// Position of HSLV9 field.
	GPIO_HSLVR_HSLV9_Pos = 0xa
	// Bit mask of HSLV9 field.
	GPIO_HSLVR_HSLV9_Msk = 0x400
	// Bit HSLV9.
	GPIO_HSLVR_HSLV9 = 0x400
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV9_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV9_Enabled = 0x1
	// Position of HSLV10 field.
	GPIO_HSLVR_HSLV10_Pos = 0xb
	// Bit mask of HSLV10 field.
	GPIO_HSLVR_HSLV10_Msk = 0x800
	// Bit HSLV10.
	GPIO_HSLVR_HSLV10 = 0x800
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV10_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV10_Enabled = 0x1
	// Position of HSLV11 field.
	GPIO_HSLVR_HSLV11_Pos = 0xc
	// Bit mask of HSLV11 field.
	GPIO_HSLVR_HSLV11_Msk = 0x1000
	// Bit HSLV11.
	GPIO_HSLVR_HSLV11 = 0x1000
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV11_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV11_Enabled = 0x1
	// Position of HSLV12 field.
	GPIO_HSLVR_HSLV12_Pos = 0xd
	// Bit mask of HSLV12 field.
	GPIO_HSLVR_HSLV12_Msk = 0x2000
	// Bit HSLV12.
	GPIO_HSLVR_HSLV12 = 0x2000
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV12_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV12_Enabled = 0x1
	// Position of HSLV13 field.
	GPIO_HSLVR_HSLV13_Pos = 0xe
	// Bit mask of HSLV13 field.
	GPIO_HSLVR_HSLV13_Msk = 0x4000
	// Bit HSLV13.
	GPIO_HSLVR_HSLV13 = 0x4000
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV13_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV13_Enabled = 0x1
	// Position of HSLV14 field.
	GPIO_HSLVR_HSLV14_Pos = 0xf
	// Bit mask of HSLV14 field.
	GPIO_HSLVR_HSLV14_Msk = 0x8000
	// Bit HSLV14.
	GPIO_HSLVR_HSLV14 = 0x8000
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV14_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV14_Enabled = 0x1
	// Position of HSLV15 field.
	GPIO_HSLVR_HSLV15_Pos = 0x10
	// Bit mask of HSLV15 field.
	GPIO_HSLVR_HSLV15_Msk = 0x10000
	// Bit HSLV15.
	GPIO_HSLVR_HSLV15 = 0x10000
	// I/O speed optimization disabled
	GPIO_HSLVR_HSLV15_Disabled = 0x0
	// I/O speed optimization enabled
	GPIO_HSLVR_HSLV15_Enabled = 0x1

	// SECCFGR: GPIO secure configuration register
	// Position of SEC0 field.
	GPIO_SECCFGR_SEC0_Pos = 0x1
	// Bit mask of SEC0 field.
	GPIO_SECCFGR_SEC0_Msk = 0x2
	// Bit SEC0.
	GPIO_SECCFGR_SEC0 = 0x2
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC0_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC0_Secure = 0x1
	// Position of SEC1 field.
	GPIO_SECCFGR_SEC1_Pos = 0x2
	// Bit mask of SEC1 field.
	GPIO_SECCFGR_SEC1_Msk = 0x4
	// Bit SEC1.
	GPIO_SECCFGR_SEC1 = 0x4
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC1_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC1_Secure = 0x1
	// Position of SEC2 field.
	GPIO_SECCFGR_SEC2_Pos = 0x3
	// Bit mask of SEC2 field.
	GPIO_SECCFGR_SEC2_Msk = 0x8
	// Bit SEC2.
	GPIO_SECCFGR_SEC2 = 0x8
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC2_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC2_Secure = 0x1
	// Position of SEC3 field.
	GPIO_SECCFGR_SEC3_Pos = 0x4
	// Bit mask of SEC3 field.
	GPIO_SECCFGR_SEC3_Msk = 0x10
	// Bit SEC3.
	GPIO_SECCFGR_SEC3 = 0x10
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC3_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC3_Secure = 0x1
	// Position of SEC4 field.
	GPIO_SECCFGR_SEC4_Pos = 0x5
	// Bit mask of SEC4 field.
	GPIO_SECCFGR_SEC4_Msk = 0x20
	// Bit SEC4.
	GPIO_SECCFGR_SEC4 = 0x20
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC4_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC4_Secure = 0x1
	// Position of SEC5 field.
	GPIO_SECCFGR_SEC5_Pos = 0x6
	// Bit mask of SEC5 field.
	GPIO_SECCFGR_SEC5_Msk = 0x40
	// Bit SEC5.
	GPIO_SECCFGR_SEC5 = 0x40
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC5_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC5_Secure = 0x1
	// Position of SEC6 field.
	GPIO_SECCFGR_SEC6_Pos = 0x7
	// Bit mask of SEC6 field.
	GPIO_SECCFGR_SEC6_Msk = 0x80
	// Bit SEC6.
	GPIO_SECCFGR_SEC6 = 0x80
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC6_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC6_Secure = 0x1
	// Position of SEC7 field.
	GPIO_SECCFGR_SEC7_Pos = 0x8
	// Bit mask of SEC7 field.
	GPIO_SECCFGR_SEC7_Msk = 0x100
	// Bit SEC7.
	GPIO_SECCFGR_SEC7 = 0x100
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC7_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC7_Secure = 0x1
	// Position of SEC8 field.
	GPIO_SECCFGR_SEC8_Pos = 0x9
	// Bit mask of SEC8 field.
	GPIO_SECCFGR_SEC8_Msk = 0x200
	// Bit SEC8.
	GPIO_SECCFGR_SEC8 = 0x200
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC8_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC8_Secure = 0x1
	// Position of SEC9 field.
	GPIO_SECCFGR_SEC9_Pos = 0xa
	// Bit mask of SEC9 field.
	GPIO_SECCFGR_SEC9_Msk = 0x400
	// Bit SEC9.
	GPIO_SECCFGR_SEC9 = 0x400
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC9_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC9_Secure = 0x1
	// Position of SEC10 field.
	GPIO_SECCFGR_SEC10_Pos = 0xb
	// Bit mask of SEC10 field.
	GPIO_SECCFGR_SEC10_Msk = 0x800
	// Bit SEC10.
	GPIO_SECCFGR_SEC10 = 0x800
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC10_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC10_Secure = 0x1
	// Position of SEC11 field.
	GPIO_SECCFGR_SEC11_Pos = 0xc
	// Bit mask of SEC11 field.
	GPIO_SECCFGR_SEC11_Msk = 0x1000
	// Bit SEC11.
	GPIO_SECCFGR_SEC11 = 0x1000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC11_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC11_Secure = 0x1
	// Position of SEC12 field.
	GPIO_SECCFGR_SEC12_Pos = 0xd
	// Bit mask of SEC12 field.
	GPIO_SECCFGR_SEC12_Msk = 0x2000
	// Bit SEC12.
	GPIO_SECCFGR_SEC12 = 0x2000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC12_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC12_Secure = 0x1
	// Position of SEC13 field.
	GPIO_SECCFGR_SEC13_Pos = 0xe
	// Bit mask of SEC13 field.
	GPIO_SECCFGR_SEC13_Msk = 0x4000
	// Bit SEC13.
	GPIO_SECCFGR_SEC13 = 0x4000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC13_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC13_Secure = 0x1
	// Position of SEC14 field.
	GPIO_SECCFGR_SEC14_Pos = 0xf
	// Bit mask of SEC14 field.
	GPIO_SECCFGR_SEC14_Msk = 0x8000
	// Bit SEC14.
	GPIO_SECCFGR_SEC14 = 0x8000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC14_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC14_Secure = 0x1
	// Position of SEC15 field.
	GPIO_SECCFGR_SEC15_Pos = 0x10
	// Bit mask of SEC15 field.
	GPIO_SECCFGR_SEC15_Msk = 0x10000
	// Bit SEC15.
	GPIO_SECCFGR_SEC15 = 0x10000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC15_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC15_Secure = 0x1
)

// Constants for GTZC1_TZIC: GTZC1_TZIC
const (
	// IER1: TZIC interrupt enable register 1
	// Position of TIM2IE field.
	GTZC_IER1_TIM2IE_Pos = 0x0
	// Bit mask of TIM2IE field.
	GTZC_IER1_TIM2IE_Msk = 0x1
	// Bit TIM2IE.
	GTZC_IER1_TIM2IE = 0x1
	// Position of TIM3IE field.
	GTZC_IER1_TIM3IE_Pos = 0x1
	// Bit mask of TIM3IE field.
	GTZC_IER1_TIM3IE_Msk = 0x2
	// Bit TIM3IE.
	GTZC_IER1_TIM3IE = 0x2
	// Position of TIM4IE field.
	GTZC_IER1_TIM4IE_Pos = 0x2
	// Bit mask of TIM4IE field.
	GTZC_IER1_TIM4IE_Msk = 0x4
	// Bit TIM4IE.
	GTZC_IER1_TIM4IE = 0x4
	// Position of TIM5IE field.
	GTZC_IER1_TIM5IE_Pos = 0x3
	// Bit mask of TIM5IE field.
	GTZC_IER1_TIM5IE_Msk = 0x8
	// Bit TIM5IE.
	GTZC_IER1_TIM5IE = 0x8
	// Position of TIM6IE field.
	GTZC_IER1_TIM6IE_Pos = 0x4
	// Bit mask of TIM6IE field.
	GTZC_IER1_TIM6IE_Msk = 0x10
	// Bit TIM6IE.
	GTZC_IER1_TIM6IE = 0x10
	// Position of TIM7IE field.
	GTZC_IER1_TIM7IE_Pos = 0x5
	// Bit mask of TIM7IE field.
	GTZC_IER1_TIM7IE_Msk = 0x20
	// Bit TIM7IE.
	GTZC_IER1_TIM7IE = 0x20
	// Position of WWDGIE field.
	GTZC_IER1_WWDGIE_Pos = 0x6
	// Bit mask of WWDGIE field.
	GTZC_IER1_WWDGIE_Msk = 0x40
	// Bit WWDGIE.
	GTZC_IER1_WWDGIE = 0x40
	// Position of IWDGIE field.
	GTZC_IER1_IWDGIE_Pos = 0x7
	// Bit mask of IWDGIE field.
	GTZC_IER1_IWDGIE_Msk = 0x80
	// Bit IWDGIE.
	GTZC_IER1_IWDGIE = 0x80
	// Position of SPI2IE field.
	GTZC_IER1_SPI2IE_Pos = 0x8
	// Bit mask of SPI2IE field.
	GTZC_IER1_SPI2IE_Msk = 0x100
	// Bit SPI2IE.
	GTZC_IER1_SPI2IE = 0x100
	// Position of USART2IE field.
	GTZC_IER1_USART2IE_Pos = 0x9
	// Bit mask of USART2IE field.
	GTZC_IER1_USART2IE_Msk = 0x200
	// Bit USART2IE.
	GTZC_IER1_USART2IE = 0x200
	// Position of USART3IE field.
	GTZC_IER1_USART3IE_Pos = 0xa
	// Bit mask of USART3IE field.
	GTZC_IER1_USART3IE_Msk = 0x400
	// Bit USART3IE.
	GTZC_IER1_USART3IE = 0x400
	// Position of USART4IE field.
	GTZC_IER1_USART4IE_Pos = 0xb
	// Bit mask of USART4IE field.
	GTZC_IER1_USART4IE_Msk = 0x800
	// Bit USART4IE.
	GTZC_IER1_USART4IE = 0x800
	// Position of UART5IE field.
	GTZC_IER1_UART5IE_Pos = 0xc
	// Bit mask of UART5IE field.
	GTZC_IER1_UART5IE_Msk = 0x1000
	// Bit UART5IE.
	GTZC_IER1_UART5IE = 0x1000
	// Position of I2C1IE field.
	GTZC_IER1_I2C1IE_Pos = 0xd
	// Bit mask of I2C1IE field.
	GTZC_IER1_I2C1IE_Msk = 0x2000
	// Bit I2C1IE.
	GTZC_IER1_I2C1IE = 0x2000
	// Position of I2C2IE field.
	GTZC_IER1_I2C2IE_Pos = 0xe
	// Bit mask of I2C2IE field.
	GTZC_IER1_I2C2IE_Msk = 0x4000
	// Bit I2C2IE.
	GTZC_IER1_I2C2IE = 0x4000
	// Position of CRSIE field.
	GTZC_IER1_CRSIE_Pos = 0xf
	// Bit mask of CRSIE field.
	GTZC_IER1_CRSIE_Msk = 0x8000
	// Bit CRSIE.
	GTZC_IER1_CRSIE = 0x8000
	// Position of I2C4IE field.
	GTZC_IER1_I2C4IE_Pos = 0x10
	// Bit mask of I2C4IE field.
	GTZC_IER1_I2C4IE_Msk = 0x10000
	// Bit I2C4IE.
	GTZC_IER1_I2C4IE = 0x10000
	// Position of LPTIM2IE field.
	GTZC_IER1_LPTIM2IE_Pos = 0x11
	// Bit mask of LPTIM2IE field.
	GTZC_IER1_LPTIM2IE_Msk = 0x20000
	// Bit LPTIM2IE.
	GTZC_IER1_LPTIM2IE = 0x20000
	// Position of FDCAN1IE field.
	GTZC_IER1_FDCAN1IE_Pos = 0x12
	// Bit mask of FDCAN1IE field.
	GTZC_IER1_FDCAN1IE_Msk = 0x40000
	// Bit FDCAN1IE.
	GTZC_IER1_FDCAN1IE = 0x40000
	// Position of UCPD1IE field.
	GTZC_IER1_UCPD1IE_Pos = 0x13
	// Bit mask of UCPD1IE field.
	GTZC_IER1_UCPD1IE_Msk = 0x80000
	// Bit UCPD1IE.
	GTZC_IER1_UCPD1IE = 0x80000
	// Position of USART6IE field.
	GTZC_IER1_USART6IE_Pos = 0x15
	// Bit mask of USART6IE field.
	GTZC_IER1_USART6IE_Msk = 0x200000
	// Bit USART6IE.
	GTZC_IER1_USART6IE = 0x200000
	// Position of I2C5IE field.
	GTZC_IER1_I2C5IE_Pos = 0x16
	// Bit mask of I2C5IE field.
	GTZC_IER1_I2C5IE_Msk = 0x400000
	// Bit I2C5IE.
	GTZC_IER1_I2C5IE = 0x400000
	// Position of I2C6IE field.
	GTZC_IER1_I2C6IE_Pos = 0x17
	// Bit mask of I2C6IE field.
	GTZC_IER1_I2C6IE_Msk = 0x800000
	// Bit I2C6IE.
	GTZC_IER1_I2C6IE = 0x800000

	// IER2: TZIC interrupt enable register 2
	// Position of TIM1IE field.
	GTZC_IER2_TIM1IE_Pos = 0x0
	// Bit mask of TIM1IE field.
	GTZC_IER2_TIM1IE_Msk = 0x1
	// Bit TIM1IE.
	GTZC_IER2_TIM1IE = 0x1
	// Position of SPI1IE field.
	GTZC_IER2_SPI1IE_Pos = 0x1
	// Bit mask of SPI1IE field.
	GTZC_IER2_SPI1IE_Msk = 0x2
	// Bit SPI1IE.
	GTZC_IER2_SPI1IE = 0x2
	// Position of TIM8IE field.
	GTZC_IER2_TIM8IE_Pos = 0x2
	// Bit mask of TIM8IE field.
	GTZC_IER2_TIM8IE_Msk = 0x4
	// Bit TIM8IE.
	GTZC_IER2_TIM8IE = 0x4
	// Position of USART1IE field.
	GTZC_IER2_USART1IE_Pos = 0x3
	// Bit mask of USART1IE field.
	GTZC_IER2_USART1IE_Msk = 0x8
	// Bit USART1IE.
	GTZC_IER2_USART1IE = 0x8
	// Position of TIM15IE field.
	GTZC_IER2_TIM15IE_Pos = 0x4
	// Bit mask of TIM15IE field.
	GTZC_IER2_TIM15IE_Msk = 0x10
	// Bit TIM15IE.
	GTZC_IER2_TIM15IE = 0x10
	// Position of TIM16IE field.
	GTZC_IER2_TIM16IE_Pos = 0x5
	// Bit mask of TIM16IE field.
	GTZC_IER2_TIM16IE_Msk = 0x20
	// Bit TIM16IE.
	GTZC_IER2_TIM16IE = 0x20
	// Position of TIM17IE field.
	GTZC_IER2_TIM17IE_Pos = 0x6
	// Bit mask of TIM17IE field.
	GTZC_IER2_TIM17IE_Msk = 0x40
	// Bit TIM17IE.
	GTZC_IER2_TIM17IE = 0x40
	// Position of SAI1IE field.
	GTZC_IER2_SAI1IE_Pos = 0x7
	// Bit mask of SAI1IE field.
	GTZC_IER2_SAI1IE_Msk = 0x80
	// Bit SAI1IE.
	GTZC_IER2_SAI1IE = 0x80
	// Position of SAI2IE field.
	GTZC_IER2_SAI2IE_Pos = 0x8
	// Bit mask of SAI2IE field.
	GTZC_IER2_SAI2IE_Msk = 0x100
	// Bit SAI2IE.
	GTZC_IER2_SAI2IE = 0x100

	// IER3: TZIC interrupt enable register 3
	// Position of MDF1IE field.
	GTZC_IER3_MDF1IE_Pos = 0x0
	// Bit mask of MDF1IE field.
	GTZC_IER3_MDF1IE_Msk = 0x1
	// Bit MDF1IE.
	GTZC_IER3_MDF1IE = 0x1
	// Position of CORDICIE field.
	GTZC_IER3_CORDICIE_Pos = 0x1
	// Bit mask of CORDICIE field.
	GTZC_IER3_CORDICIE_Msk = 0x2
	// Bit CORDICIE.
	GTZC_IER3_CORDICIE = 0x2
	// Position of FMACIE field.
	GTZC_IER3_FMACIE_Pos = 0x2
	// Bit mask of FMACIE field.
	GTZC_IER3_FMACIE_Msk = 0x4
	// Bit FMACIE.
	GTZC_IER3_FMACIE = 0x4
	// Position of CRCIE field.
	GTZC_IER3_CRCIE_Pos = 0x3
	// Bit mask of CRCIE field.
	GTZC_IER3_CRCIE_Msk = 0x8
	// Bit CRCIE.
	GTZC_IER3_CRCIE = 0x8
	// Position of TSCIE field.
	GTZC_IER3_TSCIE_Pos = 0x4
	// Bit mask of TSCIE field.
	GTZC_IER3_TSCIE_Msk = 0x10
	// Bit TSCIE.
	GTZC_IER3_TSCIE = 0x10
	// Position of DMA2DIE field.
	GTZC_IER3_DMA2DIE_Pos = 0x5
	// Bit mask of DMA2DIE field.
	GTZC_IER3_DMA2DIE_Msk = 0x20
	// Bit DMA2DIE.
	GTZC_IER3_DMA2DIE = 0x20
	// Position of ICACHE_REGIE field.
	GTZC_IER3_ICACHE_REGIE_Pos = 0x6
	// Bit mask of ICACHE_REGIE field.
	GTZC_IER3_ICACHE_REGIE_Msk = 0x40
	// Bit ICACHE_REGIE.
	GTZC_IER3_ICACHE_REGIE = 0x40
	// Position of DCACHE1_REGIE field.
	GTZC_IER3_DCACHE1_REGIE_Pos = 0x7
	// Bit mask of DCACHE1_REGIE field.
	GTZC_IER3_DCACHE1_REGIE_Msk = 0x80
	// Bit DCACHE1_REGIE.
	GTZC_IER3_DCACHE1_REGIE = 0x80
	// Position of ADC1I2E field.
	GTZC_IER3_ADC1I2E_Pos = 0x8
	// Bit mask of ADC1I2E field.
	GTZC_IER3_ADC1I2E_Msk = 0x100
	// Bit ADC1I2E.
	GTZC_IER3_ADC1I2E = 0x100
	// Position of DCMIIE field.
	GTZC_IER3_DCMIIE_Pos = 0x9
	// Bit mask of DCMIIE field.
	GTZC_IER3_DCMIIE_Msk = 0x200
	// Bit DCMIIE.
	GTZC_IER3_DCMIIE = 0x200
	// Position of OTGIE field.
	GTZC_IER3_OTGIE_Pos = 0xa
	// Bit mask of OTGIE field.
	GTZC_IER3_OTGIE_Msk = 0x400
	// Bit OTGIE.
	GTZC_IER3_OTGIE = 0x400
	// Position of AESIE field.
	GTZC_IER3_AESIE_Pos = 0xb
	// Bit mask of AESIE field.
	GTZC_IER3_AESIE_Msk = 0x800
	// Bit AESIE.
	GTZC_IER3_AESIE = 0x800
	// Position of HASHIE field.
	GTZC_IER3_HASHIE_Pos = 0xc
	// Bit mask of HASHIE field.
	GTZC_IER3_HASHIE_Msk = 0x1000
	// Bit HASHIE.
	GTZC_IER3_HASHIE = 0x1000
	// Position of RNGIE field.
	GTZC_IER3_RNGIE_Pos = 0xd
	// Bit mask of RNGIE field.
	GTZC_IER3_RNGIE_Msk = 0x2000
	// Bit RNGIE.
	GTZC_IER3_RNGIE = 0x2000
	// Position of PKAIE field.
	GTZC_IER3_PKAIE_Pos = 0xe
	// Bit mask of PKAIE field.
	GTZC_IER3_PKAIE_Msk = 0x4000
	// Bit PKAIE.
	GTZC_IER3_PKAIE = 0x4000
	// Position of SAESIE field.
	GTZC_IER3_SAESIE_Pos = 0xf
	// Bit mask of SAESIE field.
	GTZC_IER3_SAESIE_Msk = 0x8000
	// Bit SAESIE.
	GTZC_IER3_SAESIE = 0x8000
	// Position of OCTOSPIMIE field.
	GTZC_IER3_OCTOSPIMIE_Pos = 0x10
	// Bit mask of OCTOSPIMIE field.
	GTZC_IER3_OCTOSPIMIE_Msk = 0x10000
	// Bit OCTOSPIMIE.
	GTZC_IER3_OCTOSPIMIE = 0x10000
	// Position of SDMMC1IE field.
	GTZC_IER3_SDMMC1IE_Pos = 0x11
	// Bit mask of SDMMC1IE field.
	GTZC_IER3_SDMMC1IE_Msk = 0x20000
	// Bit SDMMC1IE.
	GTZC_IER3_SDMMC1IE = 0x20000
	// Position of SDMMC2IE field.
	GTZC_IER3_SDMMC2IE_Pos = 0x12
	// Bit mask of SDMMC2IE field.
	GTZC_IER3_SDMMC2IE_Msk = 0x40000
	// Bit SDMMC2IE.
	GTZC_IER3_SDMMC2IE = 0x40000
	// Position of FSMC_REGIE field.
	GTZC_IER3_FSMC_REGIE_Pos = 0x13
	// Bit mask of FSMC_REGIE field.
	GTZC_IER3_FSMC_REGIE_Msk = 0x80000
	// Bit FSMC_REGIE.
	GTZC_IER3_FSMC_REGIE = 0x80000
	// Position of OCTOSPI1_REGIE field.
	GTZC_IER3_OCTOSPI1_REGIE_Pos = 0x14
	// Bit mask of OCTOSPI1_REGIE field.
	GTZC_IER3_OCTOSPI1_REGIE_Msk = 0x100000
	// Bit OCTOSPI1_REGIE.
	GTZC_IER3_OCTOSPI1_REGIE = 0x100000
	// Position of OCTOSPI2_REGIE field.
	GTZC_IER3_OCTOSPI2_REGIE_Pos = 0x15
	// Bit mask of OCTOSPI2_REGIE field.
	GTZC_IER3_OCTOSPI2_REGIE_Msk = 0x200000
	// Bit OCTOSPI2_REGIE.
	GTZC_IER3_OCTOSPI2_REGIE = 0x200000
	// Position of RAMCFGIE field.
	GTZC_IER3_RAMCFGIE_Pos = 0x16
	// Bit mask of RAMCFGIE field.
	GTZC_IER3_RAMCFGIE_Msk = 0x400000
	// Bit RAMCFGIE.
	GTZC_IER3_RAMCFGIE = 0x400000
	// Position of HSPI1_REGIE field.
	GTZC_IER3_HSPI1_REGIE_Pos = 0x1a
	// Bit mask of HSPI1_REGIE field.
	GTZC_IER3_HSPI1_REGIE_Msk = 0x4000000
	// Bit HSPI1_REGIE.
	GTZC_IER3_HSPI1_REGIE = 0x4000000

	// IER4: TZIC interrupt enable register 4
	// Position of GPDMA1IE field.
	GTZC_IER4_GPDMA1IE_Pos = 0x0
	// Bit mask of GPDMA1IE field.
	GTZC_IER4_GPDMA1IE_Msk = 0x1
	// Bit GPDMA1IE.
	GTZC_IER4_GPDMA1IE = 0x1
	// Position of FLASH_REGIE field.
	GTZC_IER4_FLASH_REGIE_Pos = 0x1
	// Bit mask of FLASH_REGIE field.
	GTZC_IER4_FLASH_REGIE_Msk = 0x2
	// Bit FLASH_REGIE.
	GTZC_IER4_FLASH_REGIE = 0x2
	// Position of FLASHIE field.
	GTZC_IER4_FLASHIE_Pos = 0x2
	// Bit mask of FLASHIE field.
	GTZC_IER4_FLASHIE_Msk = 0x4
	// Bit FLASHIE.
	GTZC_IER4_FLASHIE = 0x4
	// Position of OTFDEC1IE field.
	GTZC_IER4_OTFDEC1IE_Pos = 0x3
	// Bit mask of OTFDEC1IE field.
	GTZC_IER4_OTFDEC1IE_Msk = 0x8
	// Bit OTFDEC1IE.
	GTZC_IER4_OTFDEC1IE = 0x8
	// Position of OTFDEC2IE field.
	GTZC_IER4_OTFDEC2IE_Pos = 0x4
	// Bit mask of OTFDEC2IE field.
	GTZC_IER4_OTFDEC2IE_Msk = 0x10
	// Bit OTFDEC2IE.
	GTZC_IER4_OTFDEC2IE = 0x10
	// Position of TZSC1IE field.
	GTZC_IER4_TZSC1IE_Pos = 0xe
	// Bit mask of TZSC1IE field.
	GTZC_IER4_TZSC1IE_Msk = 0x4000
	// Bit TZSC1IE.
	GTZC_IER4_TZSC1IE = 0x4000
	// Position of TZIC1IE field.
	GTZC_IER4_TZIC1IE_Pos = 0xf
	// Bit mask of TZIC1IE field.
	GTZC_IER4_TZIC1IE_Msk = 0x8000
	// Bit TZIC1IE.
	GTZC_IER4_TZIC1IE = 0x8000
	// Position of OCTOSPI1_MEMIE field.
	GTZC_IER4_OCTOSPI1_MEMIE_Pos = 0x10
	// Bit mask of OCTOSPI1_MEMIE field.
	GTZC_IER4_OCTOSPI1_MEMIE_Msk = 0x10000
	// Bit OCTOSPI1_MEMIE.
	GTZC_IER4_OCTOSPI1_MEMIE = 0x10000
	// Position of FSMC_MEMIE field.
	GTZC_IER4_FSMC_MEMIE_Pos = 0x11
	// Bit mask of FSMC_MEMIE field.
	GTZC_IER4_FSMC_MEMIE_Msk = 0x20000
	// Bit FSMC_MEMIE.
	GTZC_IER4_FSMC_MEMIE = 0x20000
	// Position of BKPSRAMIE field.
	GTZC_IER4_BKPSRAMIE_Pos = 0x12
	// Bit mask of BKPSRAMIE field.
	GTZC_IER4_BKPSRAMIE_Msk = 0x40000
	// Bit BKPSRAMIE.
	GTZC_IER4_BKPSRAMIE = 0x40000
	// Position of OCTOSPI2_MEMIE field.
	GTZC_IER4_OCTOSPI2_MEMIE_Pos = 0x13
	// Bit mask of OCTOSPI2_MEMIE field.
	GTZC_IER4_OCTOSPI2_MEMIE_Msk = 0x80000
	// Bit OCTOSPI2_MEMIE.
	GTZC_IER4_OCTOSPI2_MEMIE = 0x80000
	// Position of HSPI1_MEMIE field.
	GTZC_IER4_HSPI1_MEMIE_Pos = 0x14
	// Bit mask of HSPI1_MEMIE field.
	GTZC_IER4_HSPI1_MEMIE_Msk = 0x100000
	// Bit HSPI1_MEMIE.
	GTZC_IER4_HSPI1_MEMIE = 0x100000
	// Position of SRAM1IE field.
	GTZC_IER4_SRAM1IE_Pos = 0x18
	// Bit mask of SRAM1IE field.
	GTZC_IER4_SRAM1IE_Msk = 0x1000000
	// Bit SRAM1IE.
	GTZC_IER4_SRAM1IE = 0x1000000
	// Position of MPCBB1_REGIE field.
	GTZC_IER4_MPCBB1_REGIE_Pos = 0x19
	// Bit mask of MPCBB1_REGIE field.
	GTZC_IER4_MPCBB1_REGIE_Msk = 0x2000000
	// Bit MPCBB1_REGIE.
	GTZC_IER4_MPCBB1_REGIE = 0x2000000
	// Position of SRAM2IE field.
	GTZC_IER4_SRAM2IE_Pos = 0x1a
	// Bit mask of SRAM2IE field.
	GTZC_IER4_SRAM2IE_Msk = 0x4000000
	// Bit SRAM2IE.
	GTZC_IER4_SRAM2IE = 0x4000000
	// Position of MPCBB2_REGIE field.
	GTZC_IER4_MPCBB2_REGIE_Pos = 0x1b
	// Bit mask of MPCBB2_REGIE field.
	GTZC_IER4_MPCBB2_REGIE_Msk = 0x8000000
	// Bit MPCBB2_REGIE.
	GTZC_IER4_MPCBB2_REGIE = 0x8000000
	// Position of SRAM3IE field.
	GTZC_IER4_SRAM3IE_Pos = 0x1c
	// Bit mask of SRAM3IE field.
	GTZC_IER4_SRAM3IE_Msk = 0x10000000
	// Bit SRAM3IE.
	GTZC_IER4_SRAM3IE = 0x10000000
	// Position of MPCBB3_REGIE field.
	GTZC_IER4_MPCBB3_REGIE_Pos = 0x1d
	// Bit mask of MPCBB3_REGIE field.
	GTZC_IER4_MPCBB3_REGIE_Msk = 0x20000000
	// Bit MPCBB3_REGIE.
	GTZC_IER4_MPCBB3_REGIE = 0x20000000
	// Position of SRAM5IE field.
	GTZC_IER4_SRAM5IE_Pos = 0x1e
	// Bit mask of SRAM5IE field.
	GTZC_IER4_SRAM5IE_Msk = 0x40000000
	// Bit SRAM5IE.
	GTZC_IER4_SRAM5IE = 0x40000000
	// Position of MPCBB5_REGIE field.
	GTZC_IER4_MPCBB5_REGIE_Pos = 0x1f
	// Bit mask of MPCBB5_REGIE field.
	GTZC_IER4_MPCBB5_REGIE_Msk = 0x80000000
	// Bit MPCBB5_REGIE.
	GTZC_IER4_MPCBB5_REGIE = 0x80000000

	// SR1: TZIC status register 1
	// Position of TIM2F field.
	GTZC_SR1_TIM2F_Pos = 0x0
	// Bit mask of TIM2F field.
	GTZC_SR1_TIM2F_Msk = 0x1
	// Bit TIM2F.
	GTZC_SR1_TIM2F = 0x1
	// Position of TIM3F field.
	GTZC_SR1_TIM3F_Pos = 0x1
	// Bit mask of TIM3F field.
	GTZC_SR1_TIM3F_Msk = 0x2
	// Bit TIM3F.
	GTZC_SR1_TIM3F = 0x2
	// Position of TIM4F field.
	GTZC_SR1_TIM4F_Pos = 0x2
	// Bit mask of TIM4F field.
	GTZC_SR1_TIM4F_Msk = 0x4
	// Bit TIM4F.
	GTZC_SR1_TIM4F = 0x4
	// Position of TIM5F field.
	GTZC_SR1_TIM5F_Pos = 0x3
	// Bit mask of TIM5F field.
	GTZC_SR1_TIM5F_Msk = 0x8
	// Bit TIM5F.
	GTZC_SR1_TIM5F = 0x8
	// Position of TIM6F field.
	GTZC_SR1_TIM6F_Pos = 0x4
	// Bit mask of TIM6F field.
	GTZC_SR1_TIM6F_Msk = 0x10
	// Bit TIM6F.
	GTZC_SR1_TIM6F = 0x10
	// Position of TIM7F field.
	GTZC_SR1_TIM7F_Pos = 0x5
	// Bit mask of TIM7F field.
	GTZC_SR1_TIM7F_Msk = 0x20
	// Bit TIM7F.
	GTZC_SR1_TIM7F = 0x20
	// Position of WWDGF field.
	GTZC_SR1_WWDGF_Pos = 0x6
	// Bit mask of WWDGF field.
	GTZC_SR1_WWDGF_Msk = 0x40
	// Bit WWDGF.
	GTZC_SR1_WWDGF = 0x40
	// Position of IWDGF field.
	GTZC_SR1_IWDGF_Pos = 0x7
	// Bit mask of IWDGF field.
	GTZC_SR1_IWDGF_Msk = 0x80
	// Bit IWDGF.
	GTZC_SR1_IWDGF = 0x80
	// Position of SPI2F field.
	GTZC_SR1_SPI2F_Pos = 0x8
	// Bit mask of SPI2F field.
	GTZC_SR1_SPI2F_Msk = 0x100
	// Bit SPI2F.
	GTZC_SR1_SPI2F = 0x100
	// Position of USART2F field.
	GTZC_SR1_USART2F_Pos = 0x9
	// Bit mask of USART2F field.
	GTZC_SR1_USART2F_Msk = 0x200
	// Bit USART2F.
	GTZC_SR1_USART2F = 0x200
	// Position of USART3F field.
	GTZC_SR1_USART3F_Pos = 0xa
	// Bit mask of USART3F field.
	GTZC_SR1_USART3F_Msk = 0x400
	// Bit USART3F.
	GTZC_SR1_USART3F = 0x400
	// Position of UART4F field.
	GTZC_SR1_UART4F_Pos = 0xb
	// Bit mask of UART4F field.
	GTZC_SR1_UART4F_Msk = 0x800
	// Bit UART4F.
	GTZC_SR1_UART4F = 0x800
	// Position of UART5F field.
	GTZC_SR1_UART5F_Pos = 0xc
	// Bit mask of UART5F field.
	GTZC_SR1_UART5F_Msk = 0x1000
	// Bit UART5F.
	GTZC_SR1_UART5F = 0x1000
	// Position of I2C1F field.
	GTZC_SR1_I2C1F_Pos = 0xd
	// Bit mask of I2C1F field.
	GTZC_SR1_I2C1F_Msk = 0x2000
	// Bit I2C1F.
	GTZC_SR1_I2C1F = 0x2000
	// Position of I2C2F field.
	GTZC_SR1_I2C2F_Pos = 0xe
	// Bit mask of I2C2F field.
	GTZC_SR1_I2C2F_Msk = 0x4000
	// Bit I2C2F.
	GTZC_SR1_I2C2F = 0x4000
	// Position of CRSF field.
	GTZC_SR1_CRSF_Pos = 0xf
	// Bit mask of CRSF field.
	GTZC_SR1_CRSF_Msk = 0x8000
	// Bit CRSF.
	GTZC_SR1_CRSF = 0x8000
	// Position of I2C4F field.
	GTZC_SR1_I2C4F_Pos = 0x10
	// Bit mask of I2C4F field.
	GTZC_SR1_I2C4F_Msk = 0x10000
	// Bit I2C4F.
	GTZC_SR1_I2C4F = 0x10000
	// Position of LPTIM2F field.
	GTZC_SR1_LPTIM2F_Pos = 0x11
	// Bit mask of LPTIM2F field.
	GTZC_SR1_LPTIM2F_Msk = 0x20000
	// Bit LPTIM2F.
	GTZC_SR1_LPTIM2F = 0x20000
	// Position of FDCAN1F field.
	GTZC_SR1_FDCAN1F_Pos = 0x12
	// Bit mask of FDCAN1F field.
	GTZC_SR1_FDCAN1F_Msk = 0x40000
	// Bit FDCAN1F.
	GTZC_SR1_FDCAN1F = 0x40000
	// Position of UCPD1F field.
	GTZC_SR1_UCPD1F_Pos = 0x13
	// Bit mask of UCPD1F field.
	GTZC_SR1_UCPD1F_Msk = 0x80000
	// Bit UCPD1F.
	GTZC_SR1_UCPD1F = 0x80000
	// Position of USART6F field.
	GTZC_SR1_USART6F_Pos = 0x15
	// Bit mask of USART6F field.
	GTZC_SR1_USART6F_Msk = 0x200000
	// Bit USART6F.
	GTZC_SR1_USART6F = 0x200000
	// Position of I2C5F field.
	GTZC_SR1_I2C5F_Pos = 0x16
	// Bit mask of I2C5F field.
	GTZC_SR1_I2C5F_Msk = 0x400000
	// Bit I2C5F.
	GTZC_SR1_I2C5F = 0x400000
	// Position of I2C6F field.
	GTZC_SR1_I2C6F_Pos = 0x17
	// Bit mask of I2C6F field.
	GTZC_SR1_I2C6F_Msk = 0x800000
	// Bit I2C6F.
	GTZC_SR1_I2C6F = 0x800000

	// SR2: TZIC status register 2
	// Position of TIM1F field.
	GTZC_SR2_TIM1F_Pos = 0x0
	// Bit mask of TIM1F field.
	GTZC_SR2_TIM1F_Msk = 0x1
	// Bit TIM1F.
	GTZC_SR2_TIM1F = 0x1
	// Position of SPI1F field.
	GTZC_SR2_SPI1F_Pos = 0x1
	// Bit mask of SPI1F field.
	GTZC_SR2_SPI1F_Msk = 0x2
	// Bit SPI1F.
	GTZC_SR2_SPI1F = 0x2
	// Position of TIM8F field.
	GTZC_SR2_TIM8F_Pos = 0x2
	// Bit mask of TIM8F field.
	GTZC_SR2_TIM8F_Msk = 0x4
	// Bit TIM8F.
	GTZC_SR2_TIM8F = 0x4
	// Position of USART1F field.
	GTZC_SR2_USART1F_Pos = 0x3
	// Bit mask of USART1F field.
	GTZC_SR2_USART1F_Msk = 0x8
	// Bit USART1F.
	GTZC_SR2_USART1F = 0x8
	// Position of TIM15F field.
	GTZC_SR2_TIM15F_Pos = 0x4
	// Bit mask of TIM15F field.
	GTZC_SR2_TIM15F_Msk = 0x10
	// Bit TIM15F.
	GTZC_SR2_TIM15F = 0x10
	// Position of TIM16F field.
	GTZC_SR2_TIM16F_Pos = 0x5
	// Bit mask of TIM16F field.
	GTZC_SR2_TIM16F_Msk = 0x20
	// Bit TIM16F.
	GTZC_SR2_TIM16F = 0x20
	// Position of TIM17F field.
	GTZC_SR2_TIM17F_Pos = 0x6
	// Bit mask of TIM17F field.
	GTZC_SR2_TIM17F_Msk = 0x40
	// Bit TIM17F.
	GTZC_SR2_TIM17F = 0x40
	// Position of SAI1F field.
	GTZC_SR2_SAI1F_Pos = 0x7
	// Bit mask of SAI1F field.
	GTZC_SR2_SAI1F_Msk = 0x80
	// Bit SAI1F.
	GTZC_SR2_SAI1F = 0x80
	// Position of SAI2F field.
	GTZC_SR2_SAI2F_Pos = 0x8
	// Bit mask of SAI2F field.
	GTZC_SR2_SAI2F_Msk = 0x100
	// Bit SAI2F.
	GTZC_SR2_SAI2F = 0x100

	// SR3: TZIC status register 3
	// Position of MDF1F field.
	GTZC_SR3_MDF1F_Pos = 0x0
	// Bit mask of MDF1F field.
	GTZC_SR3_MDF1F_Msk = 0x1
	// Bit MDF1F.
	GTZC_SR3_MDF1F = 0x1
	// Position of CORDICF field.
	GTZC_SR3_CORDICF_Pos = 0x1
	// Bit mask of CORDICF field.
	GTZC_SR3_CORDICF_Msk = 0x2
	// Bit CORDICF.
	GTZC_SR3_CORDICF = 0x2
	// Position of FMACF field.
	GTZC_SR3_FMACF_Pos = 0x2
	// Bit mask of FMACF field.
	GTZC_SR3_FMACF_Msk = 0x4
	// Bit FMACF.
	GTZC_SR3_FMACF = 0x4
	// Position of CRCF field.
	GTZC_SR3_CRCF_Pos = 0x3
	// Bit mask of CRCF field.
	GTZC_SR3_CRCF_Msk = 0x8
	// Bit CRCF.
	GTZC_SR3_CRCF = 0x8
	// Position of TSCF field.
	GTZC_SR3_TSCF_Pos = 0x4
	// Bit mask of TSCF field.
	GTZC_SR3_TSCF_Msk = 0x10
	// Bit TSCF.
	GTZC_SR3_TSCF = 0x10
	// Position of DMA2DF field.
	GTZC_SR3_DMA2DF_Pos = 0x5
	// Bit mask of DMA2DF field.
	GTZC_SR3_DMA2DF_Msk = 0x20
	// Bit DMA2DF.
	GTZC_SR3_DMA2DF = 0x20
	// Position of ICACHE_REGF field.
	GTZC_SR3_ICACHE_REGF_Pos = 0x6
	// Bit mask of ICACHE_REGF field.
	GTZC_SR3_ICACHE_REGF_Msk = 0x40
	// Bit ICACHE_REGF.
	GTZC_SR3_ICACHE_REGF = 0x40
	// Position of DCACHE1_REGF field.
	GTZC_SR3_DCACHE1_REGF_Pos = 0x7
	// Bit mask of DCACHE1_REGF field.
	GTZC_SR3_DCACHE1_REGF_Msk = 0x80
	// Bit DCACHE1_REGF.
	GTZC_SR3_DCACHE1_REGF = 0x80
	// Position of ADC12F field.
	GTZC_SR3_ADC12F_Pos = 0x8
	// Bit mask of ADC12F field.
	GTZC_SR3_ADC12F_Msk = 0x100
	// Bit ADC12F.
	GTZC_SR3_ADC12F = 0x100
	// Position of DCMIF field.
	GTZC_SR3_DCMIF_Pos = 0x9
	// Bit mask of DCMIF field.
	GTZC_SR3_DCMIF_Msk = 0x200
	// Bit DCMIF.
	GTZC_SR3_DCMIF = 0x200
	// Position of OTGF field.
	GTZC_SR3_OTGF_Pos = 0xa
	// Bit mask of OTGF field.
	GTZC_SR3_OTGF_Msk = 0x400
	// Bit OTGF.
	GTZC_SR3_OTGF = 0x400
	// Position of AESF field.
	GTZC_SR3_AESF_Pos = 0xb
	// Bit mask of AESF field.
	GTZC_SR3_AESF_Msk = 0x800
	// Bit AESF.
	GTZC_SR3_AESF = 0x800
	// Position of HASHF field.
	GTZC_SR3_HASHF_Pos = 0xc
	// Bit mask of HASHF field.
	GTZC_SR3_HASHF_Msk = 0x1000
	// Bit HASHF.
	GTZC_SR3_HASHF = 0x1000
	// Position of RNGF field.
	GTZC_SR3_RNGF_Pos = 0xd
	// Bit mask of RNGF field.
	GTZC_SR3_RNGF_Msk = 0x2000
	// Bit RNGF.
	GTZC_SR3_RNGF = 0x2000
	// Position of PKAF field.
	GTZC_SR3_PKAF_Pos = 0xe
	// Bit mask of PKAF field.
	GTZC_SR3_PKAF_Msk = 0x4000
	// Bit PKAF.
	GTZC_SR3_PKAF = 0x4000
	// Position of SAESF field.
	GTZC_SR3_SAESF_Pos = 0xf
	// Bit mask of SAESF field.
	GTZC_SR3_SAESF_Msk = 0x8000
	// Bit SAESF.
	GTZC_SR3_SAESF = 0x8000
	// Position of OCTOSPIMF field.
	GTZC_SR3_OCTOSPIMF_Pos = 0x10
	// Bit mask of OCTOSPIMF field.
	GTZC_SR3_OCTOSPIMF_Msk = 0x10000
	// Bit OCTOSPIMF.
	GTZC_SR3_OCTOSPIMF = 0x10000
	// Position of SDMMC1F field.
	GTZC_SR3_SDMMC1F_Pos = 0x11
	// Bit mask of SDMMC1F field.
	GTZC_SR3_SDMMC1F_Msk = 0x20000
	// Bit SDMMC1F.
	GTZC_SR3_SDMMC1F = 0x20000
	// Position of SDMMC2F field.
	GTZC_SR3_SDMMC2F_Pos = 0x12
	// Bit mask of SDMMC2F field.
	GTZC_SR3_SDMMC2F_Msk = 0x40000
	// Bit SDMMC2F.
	GTZC_SR3_SDMMC2F = 0x40000
	// Position of FSMC_REGF field.
	GTZC_SR3_FSMC_REGF_Pos = 0x13
	// Bit mask of FSMC_REGF field.
	GTZC_SR3_FSMC_REGF_Msk = 0x80000
	// Bit FSMC_REGF.
	GTZC_SR3_FSMC_REGF = 0x80000
	// Position of OCTOSPI1_REGF field.
	GTZC_SR3_OCTOSPI1_REGF_Pos = 0x14
	// Bit mask of OCTOSPI1_REGF field.
	GTZC_SR3_OCTOSPI1_REGF_Msk = 0x100000
	// Bit OCTOSPI1_REGF.
	GTZC_SR3_OCTOSPI1_REGF = 0x100000
	// Position of OCTOSPI2_REGF field.
	GTZC_SR3_OCTOSPI2_REGF_Pos = 0x15
	// Bit mask of OCTOSPI2_REGF field.
	GTZC_SR3_OCTOSPI2_REGF_Msk = 0x200000
	// Bit OCTOSPI2_REGF.
	GTZC_SR3_OCTOSPI2_REGF = 0x200000
	// Position of RAMCFGF field.
	GTZC_SR3_RAMCFGF_Pos = 0x16
	// Bit mask of RAMCFGF field.
	GTZC_SR3_RAMCFGF_Msk = 0x400000
	// Bit RAMCFGF.
	GTZC_SR3_RAMCFGF = 0x400000
	// Position of HSPI1_REGF field.
	GTZC_SR3_HSPI1_REGF_Pos = 0x1a
	// Bit mask of HSPI1_REGF field.
	GTZC_SR3_HSPI1_REGF_Msk = 0x4000000
	// Bit HSPI1_REGF.
	GTZC_SR3_HSPI1_REGF = 0x4000000

	// SR4: TZIC status register 4
	// Position of GPDMA1F field.
	GTZC_SR4_GPDMA1F_Pos = 0x0
	// Bit mask of GPDMA1F field.
	GTZC_SR4_GPDMA1F_Msk = 0x1
	// Bit GPDMA1F.
	GTZC_SR4_GPDMA1F = 0x1
	// Position of FLASH_REGF field.
	GTZC_SR4_FLASH_REGF_Pos = 0x1
	// Bit mask of FLASH_REGF field.
	GTZC_SR4_FLASH_REGF_Msk = 0x2
	// Bit FLASH_REGF.
	GTZC_SR4_FLASH_REGF = 0x2
	// Position of FLASHF field.
	GTZC_SR4_FLASHF_Pos = 0x2
	// Bit mask of FLASHF field.
	GTZC_SR4_FLASHF_Msk = 0x4
	// Bit FLASHF.
	GTZC_SR4_FLASHF = 0x4
	// Position of OTFDEC1F field.
	GTZC_SR4_OTFDEC1F_Pos = 0x3
	// Bit mask of OTFDEC1F field.
	GTZC_SR4_OTFDEC1F_Msk = 0x8
	// Bit OTFDEC1F.
	GTZC_SR4_OTFDEC1F = 0x8
	// Position of OTFDEC2F field.
	GTZC_SR4_OTFDEC2F_Pos = 0x4
	// Bit mask of OTFDEC2F field.
	GTZC_SR4_OTFDEC2F_Msk = 0x10
	// Bit OTFDEC2F.
	GTZC_SR4_OTFDEC2F = 0x10
	// Position of TZSC1F field.
	GTZC_SR4_TZSC1F_Pos = 0xe
	// Bit mask of TZSC1F field.
	GTZC_SR4_TZSC1F_Msk = 0x4000
	// Bit TZSC1F.
	GTZC_SR4_TZSC1F = 0x4000
	// Position of TZIC1F field.
	GTZC_SR4_TZIC1F_Pos = 0xf
	// Bit mask of TZIC1F field.
	GTZC_SR4_TZIC1F_Msk = 0x8000
	// Bit TZIC1F.
	GTZC_SR4_TZIC1F = 0x8000
	// Position of OCTOSPI1_MEMF field.
	GTZC_SR4_OCTOSPI1_MEMF_Pos = 0x10
	// Bit mask of OCTOSPI1_MEMF field.
	GTZC_SR4_OCTOSPI1_MEMF_Msk = 0x10000
	// Bit OCTOSPI1_MEMF.
	GTZC_SR4_OCTOSPI1_MEMF = 0x10000
	// Position of FSMC_MEMF field.
	GTZC_SR4_FSMC_MEMF_Pos = 0x11
	// Bit mask of FSMC_MEMF field.
	GTZC_SR4_FSMC_MEMF_Msk = 0x20000
	// Bit FSMC_MEMF.
	GTZC_SR4_FSMC_MEMF = 0x20000
	// Position of BKPSRAMF field.
	GTZC_SR4_BKPSRAMF_Pos = 0x12
	// Bit mask of BKPSRAMF field.
	GTZC_SR4_BKPSRAMF_Msk = 0x40000
	// Bit BKPSRAMF.
	GTZC_SR4_BKPSRAMF = 0x40000
	// Position of OCTOSPI2_MEMF field.
	GTZC_SR4_OCTOSPI2_MEMF_Pos = 0x13
	// Bit mask of OCTOSPI2_MEMF field.
	GTZC_SR4_OCTOSPI2_MEMF_Msk = 0x80000
	// Bit OCTOSPI2_MEMF.
	GTZC_SR4_OCTOSPI2_MEMF = 0x80000
	// Position of HSPI1_MEMF field.
	GTZC_SR4_HSPI1_MEMF_Pos = 0x14
	// Bit mask of HSPI1_MEMF field.
	GTZC_SR4_HSPI1_MEMF_Msk = 0x100000
	// Bit HSPI1_MEMF.
	GTZC_SR4_HSPI1_MEMF = 0x100000
	// Position of SRAM1F field.
	GTZC_SR4_SRAM1F_Pos = 0x18
	// Bit mask of SRAM1F field.
	GTZC_SR4_SRAM1F_Msk = 0x1000000
	// Bit SRAM1F.
	GTZC_SR4_SRAM1F = 0x1000000
	// Position of MPCBB1_REGF field.
	GTZC_SR4_MPCBB1_REGF_Pos = 0x19
	// Bit mask of MPCBB1_REGF field.
	GTZC_SR4_MPCBB1_REGF_Msk = 0x2000000
	// Bit MPCBB1_REGF.
	GTZC_SR4_MPCBB1_REGF = 0x2000000
	// Position of SRAM2F field.
	GTZC_SR4_SRAM2F_Pos = 0x1a
	// Bit mask of SRAM2F field.
	GTZC_SR4_SRAM2F_Msk = 0x4000000
	// Bit SRAM2F.
	GTZC_SR4_SRAM2F = 0x4000000
	// Position of MPCBB2_REGF field.
	GTZC_SR4_MPCBB2_REGF_Pos = 0x1b
	// Bit mask of MPCBB2_REGF field.
	GTZC_SR4_MPCBB2_REGF_Msk = 0x8000000
	// Bit MPCBB2_REGF.
	GTZC_SR4_MPCBB2_REGF = 0x8000000
	// Position of SRAM3F field.
	GTZC_SR4_SRAM3F_Pos = 0x1c
	// Bit mask of SRAM3F field.
	GTZC_SR4_SRAM3F_Msk = 0x10000000
	// Bit SRAM3F.
	GTZC_SR4_SRAM3F = 0x10000000
	// Position of MPCBB3_REGF field.
	GTZC_SR4_MPCBB3_REGF_Pos = 0x1d
	// Bit mask of MPCBB3_REGF field.
	GTZC_SR4_MPCBB3_REGF_Msk = 0x20000000
	// Bit MPCBB3_REGF.
	GTZC_SR4_MPCBB3_REGF = 0x20000000
	// Position of SRAM5F field.
	GTZC_SR4_SRAM5F_Pos = 0x1e
	// Bit mask of SRAM5F field.
	GTZC_SR4_SRAM5F_Msk = 0x40000000
	// Bit SRAM5F.
	GTZC_SR4_SRAM5F = 0x40000000
	// Position of MPCBB5_REGF field.
	GTZC_SR4_MPCBB5_REGF_Pos = 0x1f
	// Bit mask of MPCBB5_REGF field.
	GTZC_SR4_MPCBB5_REGF_Msk = 0x80000000
	// Bit MPCBB5_REGF.
	GTZC_SR4_MPCBB5_REGF = 0x80000000

	// FCR1: TZIC flag clear register 1
	// Position of CTIM2F field.
	GTZC_FCR1_CTIM2F_Pos = 0x0
	// Bit mask of CTIM2F field.
	GTZC_FCR1_CTIM2F_Msk = 0x1
	// Bit CTIM2F.
	GTZC_FCR1_CTIM2F = 0x1
	// Position of CTIM3F field.
	GTZC_FCR1_CTIM3F_Pos = 0x1
	// Bit mask of CTIM3F field.
	GTZC_FCR1_CTIM3F_Msk = 0x2
	// Bit CTIM3F.
	GTZC_FCR1_CTIM3F = 0x2
	// Position of CTIM4F field.
	GTZC_FCR1_CTIM4F_Pos = 0x2
	// Bit mask of CTIM4F field.
	GTZC_FCR1_CTIM4F_Msk = 0x4
	// Bit CTIM4F.
	GTZC_FCR1_CTIM4F = 0x4
	// Position of CTIM5F field.
	GTZC_FCR1_CTIM5F_Pos = 0x3
	// Bit mask of CTIM5F field.
	GTZC_FCR1_CTIM5F_Msk = 0x8
	// Bit CTIM5F.
	GTZC_FCR1_CTIM5F = 0x8
	// Position of CTIM6F field.
	GTZC_FCR1_CTIM6F_Pos = 0x4
	// Bit mask of CTIM6F field.
	GTZC_FCR1_CTIM6F_Msk = 0x10
	// Bit CTIM6F.
	GTZC_FCR1_CTIM6F = 0x10
	// Position of CTIM7F field.
	GTZC_FCR1_CTIM7F_Pos = 0x5
	// Bit mask of CTIM7F field.
	GTZC_FCR1_CTIM7F_Msk = 0x20
	// Bit CTIM7F.
	GTZC_FCR1_CTIM7F = 0x20
	// Position of CWWDGF field.
	GTZC_FCR1_CWWDGF_Pos = 0x6
	// Bit mask of CWWDGF field.
	GTZC_FCR1_CWWDGF_Msk = 0x40
	// Bit CWWDGF.
	GTZC_FCR1_CWWDGF = 0x40
	// Position of CIWDGF field.
	GTZC_FCR1_CIWDGF_Pos = 0x7
	// Bit mask of CIWDGF field.
	GTZC_FCR1_CIWDGF_Msk = 0x80
	// Bit CIWDGF.
	GTZC_FCR1_CIWDGF = 0x80
	// Position of CSPI2F field.
	GTZC_FCR1_CSPI2F_Pos = 0x8
	// Bit mask of CSPI2F field.
	GTZC_FCR1_CSPI2F_Msk = 0x100
	// Bit CSPI2F.
	GTZC_FCR1_CSPI2F = 0x100
	// Position of CUSART2F field.
	GTZC_FCR1_CUSART2F_Pos = 0x9
	// Bit mask of CUSART2F field.
	GTZC_FCR1_CUSART2F_Msk = 0x200
	// Bit CUSART2F.
	GTZC_FCR1_CUSART2F = 0x200
	// Position of CUSART3F field.
	GTZC_FCR1_CUSART3F_Pos = 0xa
	// Bit mask of CUSART3F field.
	GTZC_FCR1_CUSART3F_Msk = 0x400
	// Bit CUSART3F.
	GTZC_FCR1_CUSART3F = 0x400
	// Position of CUART4F field.
	GTZC_FCR1_CUART4F_Pos = 0xb
	// Bit mask of CUART4F field.
	GTZC_FCR1_CUART4F_Msk = 0x800
	// Bit CUART4F.
	GTZC_FCR1_CUART4F = 0x800
	// Position of CUART5F field.
	GTZC_FCR1_CUART5F_Pos = 0xc
	// Bit mask of CUART5F field.
	GTZC_FCR1_CUART5F_Msk = 0x1000
	// Bit CUART5F.
	GTZC_FCR1_CUART5F = 0x1000
	// Position of CI2C1F field.
	GTZC_FCR1_CI2C1F_Pos = 0xd
	// Bit mask of CI2C1F field.
	GTZC_FCR1_CI2C1F_Msk = 0x2000
	// Bit CI2C1F.
	GTZC_FCR1_CI2C1F = 0x2000
	// Position of CI2C2F field.
	GTZC_FCR1_CI2C2F_Pos = 0xe
	// Bit mask of CI2C2F field.
	GTZC_FCR1_CI2C2F_Msk = 0x4000
	// Bit CI2C2F.
	GTZC_FCR1_CI2C2F = 0x4000
	// Position of CCRSF field.
	GTZC_FCR1_CCRSF_Pos = 0xf
	// Bit mask of CCRSF field.
	GTZC_FCR1_CCRSF_Msk = 0x8000
	// Bit CCRSF.
	GTZC_FCR1_CCRSF = 0x8000
	// Position of CI2C4F field.
	GTZC_FCR1_CI2C4F_Pos = 0x10
	// Bit mask of CI2C4F field.
	GTZC_FCR1_CI2C4F_Msk = 0x10000
	// Bit CI2C4F.
	GTZC_FCR1_CI2C4F = 0x10000
	// Position of CLPTIM2F field.
	GTZC_FCR1_CLPTIM2F_Pos = 0x11
	// Bit mask of CLPTIM2F field.
	GTZC_FCR1_CLPTIM2F_Msk = 0x20000
	// Bit CLPTIM2F.
	GTZC_FCR1_CLPTIM2F = 0x20000
	// Position of CFDCAN1F field.
	GTZC_FCR1_CFDCAN1F_Pos = 0x12
	// Bit mask of CFDCAN1F field.
	GTZC_FCR1_CFDCAN1F_Msk = 0x40000
	// Bit CFDCAN1F.
	GTZC_FCR1_CFDCAN1F = 0x40000
	// Position of CUCPD1F field.
	GTZC_FCR1_CUCPD1F_Pos = 0x13
	// Bit mask of CUCPD1F field.
	GTZC_FCR1_CUCPD1F_Msk = 0x80000
	// Bit CUCPD1F.
	GTZC_FCR1_CUCPD1F = 0x80000
	// Position of CUSART6F field.
	GTZC_FCR1_CUSART6F_Pos = 0x15
	// Bit mask of CUSART6F field.
	GTZC_FCR1_CUSART6F_Msk = 0x200000
	// Bit CUSART6F.
	GTZC_FCR1_CUSART6F = 0x200000
	// Position of CI2C5F field.
	GTZC_FCR1_CI2C5F_Pos = 0x16
	// Bit mask of CI2C5F field.
	GTZC_FCR1_CI2C5F_Msk = 0x400000
	// Bit CI2C5F.
	GTZC_FCR1_CI2C5F = 0x400000
	// Position of CI2C6F field.
	GTZC_FCR1_CI2C6F_Pos = 0x17
	// Bit mask of CI2C6F field.
	GTZC_FCR1_CI2C6F_Msk = 0x800000
	// Bit CI2C6F.
	GTZC_FCR1_CI2C6F = 0x800000

	// FCR2: TZIC flag clear register 2
	// Position of CTIM1F field.
	GTZC_FCR2_CTIM1F_Pos = 0x0
	// Bit mask of CTIM1F field.
	GTZC_FCR2_CTIM1F_Msk = 0x1
	// Bit CTIM1F.
	GTZC_FCR2_CTIM1F = 0x1
	// Position of CSPI1F field.
	GTZC_FCR2_CSPI1F_Pos = 0x1
	// Bit mask of CSPI1F field.
	GTZC_FCR2_CSPI1F_Msk = 0x2
	// Bit CSPI1F.
	GTZC_FCR2_CSPI1F = 0x2
	// Position of CTIM8F field.
	GTZC_FCR2_CTIM8F_Pos = 0x2
	// Bit mask of CTIM8F field.
	GTZC_FCR2_CTIM8F_Msk = 0x4
	// Bit CTIM8F.
	GTZC_FCR2_CTIM8F = 0x4
	// Position of CUSART1F field.
	GTZC_FCR2_CUSART1F_Pos = 0x3
	// Bit mask of CUSART1F field.
	GTZC_FCR2_CUSART1F_Msk = 0x8
	// Bit CUSART1F.
	GTZC_FCR2_CUSART1F = 0x8
	// Position of CTIM15F field.
	GTZC_FCR2_CTIM15F_Pos = 0x4
	// Bit mask of CTIM15F field.
	GTZC_FCR2_CTIM15F_Msk = 0x10
	// Bit CTIM15F.
	GTZC_FCR2_CTIM15F = 0x10
	// Position of CTIM16F field.
	GTZC_FCR2_CTIM16F_Pos = 0x5
	// Bit mask of CTIM16F field.
	GTZC_FCR2_CTIM16F_Msk = 0x20
	// Bit CTIM16F.
	GTZC_FCR2_CTIM16F = 0x20
	// Position of CTIM17F field.
	GTZC_FCR2_CTIM17F_Pos = 0x6
	// Bit mask of CTIM17F field.
	GTZC_FCR2_CTIM17F_Msk = 0x40
	// Bit CTIM17F.
	GTZC_FCR2_CTIM17F = 0x40
	// Position of CSAI1F field.
	GTZC_FCR2_CSAI1F_Pos = 0x7
	// Bit mask of CSAI1F field.
	GTZC_FCR2_CSAI1F_Msk = 0x80
	// Bit CSAI1F.
	GTZC_FCR2_CSAI1F = 0x80
	// Position of CSAI2F field.
	GTZC_FCR2_CSAI2F_Pos = 0x8
	// Bit mask of CSAI2F field.
	GTZC_FCR2_CSAI2F_Msk = 0x100
	// Bit CSAI2F.
	GTZC_FCR2_CSAI2F = 0x100

	// FCR3: TZIC flag clear register 3
	// Position of CMDF1F field.
	GTZC_FCR3_CMDF1F_Pos = 0x0
	// Bit mask of CMDF1F field.
	GTZC_FCR3_CMDF1F_Msk = 0x1
	// Bit CMDF1F.
	GTZC_FCR3_CMDF1F = 0x1
	// Position of CCORDICF field.
	GTZC_FCR3_CCORDICF_Pos = 0x1
	// Bit mask of CCORDICF field.
	GTZC_FCR3_CCORDICF_Msk = 0x2
	// Bit CCORDICF.
	GTZC_FCR3_CCORDICF = 0x2
	// Position of CFMACF field.
	GTZC_FCR3_CFMACF_Pos = 0x2
	// Bit mask of CFMACF field.
	GTZC_FCR3_CFMACF_Msk = 0x4
	// Bit CFMACF.
	GTZC_FCR3_CFMACF = 0x4
	// Position of CCRCF field.
	GTZC_FCR3_CCRCF_Pos = 0x3
	// Bit mask of CCRCF field.
	GTZC_FCR3_CCRCF_Msk = 0x8
	// Bit CCRCF.
	GTZC_FCR3_CCRCF = 0x8
	// Position of CTSCF field.
	GTZC_FCR3_CTSCF_Pos = 0x4
	// Bit mask of CTSCF field.
	GTZC_FCR3_CTSCF_Msk = 0x10
	// Bit CTSCF.
	GTZC_FCR3_CTSCF = 0x10
	// Position of CDMA2DF field.
	GTZC_FCR3_CDMA2DF_Pos = 0x5
	// Bit mask of CDMA2DF field.
	GTZC_FCR3_CDMA2DF_Msk = 0x20
	// Bit CDMA2DF.
	GTZC_FCR3_CDMA2DF = 0x20
	// Position of CICACHE_REGF field.
	GTZC_FCR3_CICACHE_REGF_Pos = 0x6
	// Bit mask of CICACHE_REGF field.
	GTZC_FCR3_CICACHE_REGF_Msk = 0x40
	// Bit CICACHE_REGF.
	GTZC_FCR3_CICACHE_REGF = 0x40
	// Position of CDCACHE1_REGF field.
	GTZC_FCR3_CDCACHE1_REGF_Pos = 0x7
	// Bit mask of CDCACHE1_REGF field.
	GTZC_FCR3_CDCACHE1_REGF_Msk = 0x80
	// Bit CDCACHE1_REGF.
	GTZC_FCR3_CDCACHE1_REGF = 0x80
	// Position of CADC12F field.
	GTZC_FCR3_CADC12F_Pos = 0x8
	// Bit mask of CADC12F field.
	GTZC_FCR3_CADC12F_Msk = 0x100
	// Bit CADC12F.
	GTZC_FCR3_CADC12F = 0x100
	// Position of CDCMIF field.
	GTZC_FCR3_CDCMIF_Pos = 0x9
	// Bit mask of CDCMIF field.
	GTZC_FCR3_CDCMIF_Msk = 0x200
	// Bit CDCMIF.
	GTZC_FCR3_CDCMIF = 0x200
	// Position of COTGF field.
	GTZC_FCR3_COTGF_Pos = 0xa
	// Bit mask of COTGF field.
	GTZC_FCR3_COTGF_Msk = 0x400
	// Bit COTGF.
	GTZC_FCR3_COTGF = 0x400
	// Position of CAESF field.
	GTZC_FCR3_CAESF_Pos = 0xb
	// Bit mask of CAESF field.
	GTZC_FCR3_CAESF_Msk = 0x800
	// Bit CAESF.
	GTZC_FCR3_CAESF = 0x800
	// Position of CHASHF field.
	GTZC_FCR3_CHASHF_Pos = 0xc
	// Bit mask of CHASHF field.
	GTZC_FCR3_CHASHF_Msk = 0x1000
	// Bit CHASHF.
	GTZC_FCR3_CHASHF = 0x1000
	// Position of CRNGF field.
	GTZC_FCR3_CRNGF_Pos = 0xd
	// Bit mask of CRNGF field.
	GTZC_FCR3_CRNGF_Msk = 0x2000
	// Bit CRNGF.
	GTZC_FCR3_CRNGF = 0x2000
	// Position of CPKAF field.
	GTZC_FCR3_CPKAF_Pos = 0xe
	// Bit mask of CPKAF field.
	GTZC_FCR3_CPKAF_Msk = 0x4000
	// Bit CPKAF.
	GTZC_FCR3_CPKAF = 0x4000
	// Position of CSAESF field.
	GTZC_FCR3_CSAESF_Pos = 0xf
	// Bit mask of CSAESF field.
	GTZC_FCR3_CSAESF_Msk = 0x8000
	// Bit CSAESF.
	GTZC_FCR3_CSAESF = 0x8000
	// Position of COCTOSPIMF field.
	GTZC_FCR3_COCTOSPIMF_Pos = 0x10
	// Bit mask of COCTOSPIMF field.
	GTZC_FCR3_COCTOSPIMF_Msk = 0x10000
	// Bit COCTOSPIMF.
	GTZC_FCR3_COCTOSPIMF = 0x10000
	// Position of CSDMMC1F field.
	GTZC_FCR3_CSDMMC1F_Pos = 0x11
	// Bit mask of CSDMMC1F field.
	GTZC_FCR3_CSDMMC1F_Msk = 0x20000
	// Bit CSDMMC1F.
	GTZC_FCR3_CSDMMC1F = 0x20000
	// Position of CSDMMC2F field.
	GTZC_FCR3_CSDMMC2F_Pos = 0x12
	// Bit mask of CSDMMC2F field.
	GTZC_FCR3_CSDMMC2F_Msk = 0x40000
	// Bit CSDMMC2F.
	GTZC_FCR3_CSDMMC2F = 0x40000
	// Position of CFSMC_REGF field.
	GTZC_FCR3_CFSMC_REGF_Pos = 0x13
	// Bit mask of CFSMC_REGF field.
	GTZC_FCR3_CFSMC_REGF_Msk = 0x80000
	// Bit CFSMC_REGF.
	GTZC_FCR3_CFSMC_REGF = 0x80000
	// Position of COCTOSPI1_REGF field.
	GTZC_FCR3_COCTOSPI1_REGF_Pos = 0x14
	// Bit mask of COCTOSPI1_REGF field.
	GTZC_FCR3_COCTOSPI1_REGF_Msk = 0x100000
	// Bit COCTOSPI1_REGF.
	GTZC_FCR3_COCTOSPI1_REGF = 0x100000
	// Position of COCTOSPI2_REGF field.
	GTZC_FCR3_COCTOSPI2_REGF_Pos = 0x15
	// Bit mask of COCTOSPI2_REGF field.
	GTZC_FCR3_COCTOSPI2_REGF_Msk = 0x200000
	// Bit COCTOSPI2_REGF.
	GTZC_FCR3_COCTOSPI2_REGF = 0x200000
	// Position of CRAMCFGF field.
	GTZC_FCR3_CRAMCFGF_Pos = 0x16
	// Bit mask of CRAMCFGF field.
	GTZC_FCR3_CRAMCFGF_Msk = 0x400000
	// Bit CRAMCFGF.
	GTZC_FCR3_CRAMCFGF = 0x400000

	// FCR4: TZIC flag clear register 4
	// Position of CGPDMA1F field.
	GTZC_FCR4_CGPDMA1F_Pos = 0x0
	// Bit mask of CGPDMA1F field.
	GTZC_FCR4_CGPDMA1F_Msk = 0x1
	// Bit CGPDMA1F.
	GTZC_FCR4_CGPDMA1F = 0x1
	// Position of CFLASH_REGF field.
	GTZC_FCR4_CFLASH_REGF_Pos = 0x1
	// Bit mask of CFLASH_REGF field.
	GTZC_FCR4_CFLASH_REGF_Msk = 0x2
	// Bit CFLASH_REGF.
	GTZC_FCR4_CFLASH_REGF = 0x2
	// Position of CFLASHF field.
	GTZC_FCR4_CFLASHF_Pos = 0x2
	// Bit mask of CFLASHF field.
	GTZC_FCR4_CFLASHF_Msk = 0x4
	// Bit CFLASHF.
	GTZC_FCR4_CFLASHF = 0x4
	// Position of COTFDEC1F field.
	GTZC_FCR4_COTFDEC1F_Pos = 0x3
	// Bit mask of COTFDEC1F field.
	GTZC_FCR4_COTFDEC1F_Msk = 0x8
	// Bit COTFDEC1F.
	GTZC_FCR4_COTFDEC1F = 0x8
	// Position of COTFDEC2F field.
	GTZC_FCR4_COTFDEC2F_Pos = 0x4
	// Bit mask of COTFDEC2F field.
	GTZC_FCR4_COTFDEC2F_Msk = 0x10
	// Bit COTFDEC2F.
	GTZC_FCR4_COTFDEC2F = 0x10
	// Position of CTZSC1F field.
	GTZC_FCR4_CTZSC1F_Pos = 0xe
	// Bit mask of CTZSC1F field.
	GTZC_FCR4_CTZSC1F_Msk = 0x4000
	// Bit CTZSC1F.
	GTZC_FCR4_CTZSC1F = 0x4000
	// Position of CTZIC1F field.
	GTZC_FCR4_CTZIC1F_Pos = 0xf
	// Bit mask of CTZIC1F field.
	GTZC_FCR4_CTZIC1F_Msk = 0x8000
	// Bit CTZIC1F.
	GTZC_FCR4_CTZIC1F = 0x8000
	// Position of COCTOSPI1_MEMF field.
	GTZC_FCR4_COCTOSPI1_MEMF_Pos = 0x10
	// Bit mask of COCTOSPI1_MEMF field.
	GTZC_FCR4_COCTOSPI1_MEMF_Msk = 0x10000
	// Bit COCTOSPI1_MEMF.
	GTZC_FCR4_COCTOSPI1_MEMF = 0x10000
	// Position of CFSMC_MEMF field.
	GTZC_FCR4_CFSMC_MEMF_Pos = 0x11
	// Bit mask of CFSMC_MEMF field.
	GTZC_FCR4_CFSMC_MEMF_Msk = 0x20000
	// Bit CFSMC_MEMF.
	GTZC_FCR4_CFSMC_MEMF = 0x20000
	// Position of CBKPSRAMF field.
	GTZC_FCR4_CBKPSRAMF_Pos = 0x12
	// Bit mask of CBKPSRAMF field.
	GTZC_FCR4_CBKPSRAMF_Msk = 0x40000
	// Bit CBKPSRAMF.
	GTZC_FCR4_CBKPSRAMF = 0x40000
	// Position of COCTOSPI2_MEMF field.
	GTZC_FCR4_COCTOSPI2_MEMF_Pos = 0x13
	// Bit mask of COCTOSPI2_MEMF field.
	GTZC_FCR4_COCTOSPI2_MEMF_Msk = 0x80000
	// Bit COCTOSPI2_MEMF.
	GTZC_FCR4_COCTOSPI2_MEMF = 0x80000
	// Position of CHSPI1_MEMF field.
	GTZC_FCR4_CHSPI1_MEMF_Pos = 0x14
	// Bit mask of CHSPI1_MEMF field.
	GTZC_FCR4_CHSPI1_MEMF_Msk = 0x100000
	// Bit CHSPI1_MEMF.
	GTZC_FCR4_CHSPI1_MEMF = 0x100000
	// Position of CSRAM1F field.
	GTZC_FCR4_CSRAM1F_Pos = 0x18
	// Bit mask of CSRAM1F field.
	GTZC_FCR4_CSRAM1F_Msk = 0x1000000
	// Bit CSRAM1F.
	GTZC_FCR4_CSRAM1F = 0x1000000
	// Position of CMPCBB1_REGF field.
	GTZC_FCR4_CMPCBB1_REGF_Pos = 0x19
	// Bit mask of CMPCBB1_REGF field.
	GTZC_FCR4_CMPCBB1_REGF_Msk = 0x2000000
	// Bit CMPCBB1_REGF.
	GTZC_FCR4_CMPCBB1_REGF = 0x2000000
	// Position of CSRAM2F field.
	GTZC_FCR4_CSRAM2F_Pos = 0x1a
	// Bit mask of CSRAM2F field.
	GTZC_FCR4_CSRAM2F_Msk = 0x4000000
	// Bit CSRAM2F.
	GTZC_FCR4_CSRAM2F = 0x4000000
	// Position of CMPCBB2_REGF field.
	GTZC_FCR4_CMPCBB2_REGF_Pos = 0x1b
	// Bit mask of CMPCBB2_REGF field.
	GTZC_FCR4_CMPCBB2_REGF_Msk = 0x8000000
	// Bit CMPCBB2_REGF.
	GTZC_FCR4_CMPCBB2_REGF = 0x8000000
	// Position of CSRAM3F field.
	GTZC_FCR4_CSRAM3F_Pos = 0x1c
	// Bit mask of CSRAM3F field.
	GTZC_FCR4_CSRAM3F_Msk = 0x10000000
	// Bit CSRAM3F.
	GTZC_FCR4_CSRAM3F = 0x10000000
	// Position of CMPCBB3_REGF field.
	GTZC_FCR4_CMPCBB3_REGF_Pos = 0x1d
	// Bit mask of CMPCBB3_REGF field.
	GTZC_FCR4_CMPCBB3_REGF_Msk = 0x20000000
	// Bit CMPCBB3_REGF.
	GTZC_FCR4_CMPCBB3_REGF = 0x20000000
	// Position of CSRAM5F field.
	GTZC_FCR4_CSRAM5F_Pos = 0x1e
	// Bit mask of CSRAM5F field.
	GTZC_FCR4_CSRAM5F_Msk = 0x40000000
	// Bit CSRAM5F.
	GTZC_FCR4_CSRAM5F = 0x40000000
	// Position of CMPCBB5_REGF field.
	GTZC_FCR4_CMPCBB5_REGF_Pos = 0x1f
	// Bit mask of CMPCBB5_REGF field.
	GTZC_FCR4_CMPCBB5_REGF_Msk = 0x80000000
	// Bit CMPCBB5_REGF.
	GTZC_FCR4_CMPCBB5_REGF = 0x80000000
)

// Constants for HASH: Hash processor
const (
	// CR: control register
	// Position of INIT field.
	HASH_CR_INIT_Pos = 0x2
	// Bit mask of INIT field.
	HASH_CR_INIT_Msk = 0x4
	// Bit INIT.
	HASH_CR_INIT = 0x4
	// Position of DMAE field.
	HASH_CR_DMAE_Pos = 0x3
	// Bit mask of DMAE field.
	HASH_CR_DMAE_Msk = 0x8
	// Bit DMAE.
	HASH_CR_DMAE = 0x8
	// Position of DATATYPE field.
	HASH_CR_DATATYPE_Pos = 0x4
	// Bit mask of DATATYPE field.
	HASH_CR_DATATYPE_Msk = 0x30
	// Position of MODE field.
	HASH_CR_MODE_Pos = 0x6
	// Bit mask of MODE field.
	HASH_CR_MODE_Msk = 0x40
	// Bit MODE.
	HASH_CR_MODE = 0x40
	// Position of ALGO field.
	HASH_CR_ALGO_Pos = 0x11
	// Bit mask of ALGO field.
	HASH_CR_ALGO_Msk = 0x60000
	// Position of NBW field.
	HASH_CR_NBW_Pos = 0x8
	// Bit mask of NBW field.
	HASH_CR_NBW_Msk = 0xf00
	// Position of DINNE field.
	HASH_CR_DINNE_Pos = 0xc
	// Bit mask of DINNE field.
	HASH_CR_DINNE_Msk = 0x1000
	// Bit DINNE.
	HASH_CR_DINNE = 0x1000
	// Position of MDMAT field.
	HASH_CR_MDMAT_Pos = 0xd
	// Bit mask of MDMAT field.
	HASH_CR_MDMAT_Msk = 0x2000
	// Bit MDMAT.
	HASH_CR_MDMAT = 0x2000
	// Position of LKEY field.
	HASH_CR_LKEY_Pos = 0x10
	// Bit mask of LKEY field.
	HASH_CR_LKEY_Msk = 0x10000
	// Bit LKEY.
	HASH_CR_LKEY = 0x10000

	// DIN: data input register
	// Position of DATAIN field.
	HASH_DIN_DATAIN_Pos = 0x0
	// Bit mask of DATAIN field.
	HASH_DIN_DATAIN_Msk = 0xffffffff

	// STR: start register
	// Position of DCAL field.
	HASH_STR_DCAL_Pos = 0x8
	// Bit mask of DCAL field.
	HASH_STR_DCAL_Msk = 0x100
	// Bit DCAL.
	HASH_STR_DCAL = 0x100
	// Position of NBLW field.
	HASH_STR_NBLW_Pos = 0x0
	// Bit mask of NBLW field.
	HASH_STR_NBLW_Msk = 0x1f

	// HRA0: HASH aliased digest register 0
	// Position of H0 field.
	HASH_HRA0_H0_Pos = 0x0
	// Bit mask of H0 field.
	HASH_HRA0_H0_Msk = 0xffffffff

	// HRA1: HASH aliased digest register 1
	// Position of H1 field.
	HASH_HRA1_H1_Pos = 0x0
	// Bit mask of H1 field.
	HASH_HRA1_H1_Msk = 0xffffffff

	// HRA2: HASH aliased digest register 2
	// Position of H2 field.
	HASH_HRA2_H2_Pos = 0x0
	// Bit mask of H2 field.
	HASH_HRA2_H2_Msk = 0xffffffff

	// HRA3: HASH aliased digest register 3
	// Position of H3 field.
	HASH_HRA3_H3_Pos = 0x0
	// Bit mask of H3 field.
	HASH_HRA3_H3_Msk = 0xffffffff

	// HRA4: HASH aliased digest register 4
	// Position of H4 field.
	HASH_HRA4_H4_Pos = 0x0
	// Bit mask of H4 field.
	HASH_HRA4_H4_Msk = 0xffffffff

	// IMR: interrupt enable register
	// Position of DCIE field.
	HASH_IMR_DCIE_Pos = 0x1
	// Bit mask of DCIE field.
	HASH_IMR_DCIE_Msk = 0x2
	// Bit DCIE.
	HASH_IMR_DCIE = 0x2
	// Position of DINIE field.
	HASH_IMR_DINIE_Pos = 0x0
	// Bit mask of DINIE field.
	HASH_IMR_DINIE_Msk = 0x1
	// Bit DINIE.
	HASH_IMR_DINIE = 0x1

	// SR: status register
	// Position of BUSY field.
	HASH_SR_BUSY_Pos = 0x3
	// Bit mask of BUSY field.
	HASH_SR_BUSY_Msk = 0x8
	// Bit BUSY.
	HASH_SR_BUSY = 0x8
	// Position of DMAS field.
	HASH_SR_DMAS_Pos = 0x2
	// Bit mask of DMAS field.
	HASH_SR_DMAS_Msk = 0x4
	// Bit DMAS.
	HASH_SR_DMAS = 0x4
	// Position of DCIS field.
	HASH_SR_DCIS_Pos = 0x1
	// Bit mask of DCIS field.
	HASH_SR_DCIS_Msk = 0x2
	// Bit DCIS.
	HASH_SR_DCIS = 0x2
	// Position of DINIS field.
	HASH_SR_DINIS_Pos = 0x0
	// Bit mask of DINIS field.
	HASH_SR_DINIS_Msk = 0x1
	// Bit DINIS.
	HASH_SR_DINIS = 0x1
	// Position of NBWE field.
	HASH_SR_NBWE_Pos = 0x10
	// Bit mask of NBWE field.
	HASH_SR_NBWE_Msk = 0x1f0000
	// Position of DINNE field.
	HASH_SR_DINNE_Pos = 0xf
	// Bit mask of DINNE field.
	HASH_SR_DINNE_Msk = 0x8000
	// Bit DINNE.
	HASH_SR_DINNE = 0x8000
	// Position of NBWP field.
	HASH_SR_NBWP_Pos = 0x9
	// Bit mask of NBWP field.
	HASH_SR_NBWP_Msk = 0x3e00

	// CSR0: context swap registers
	// Position of CS0 field.
	HASH_CSR0_CS0_Pos = 0x0
	// Bit mask of CS0 field.
	HASH_CSR0_CS0_Msk = 0xffffffff

	// CSR1: context swap registers
	// Position of CS1 field.
	HASH_CSR1_CS1_Pos = 0x0
	// Bit mask of CS1 field.
	HASH_CSR1_CS1_Msk = 0xffffffff

	// CSR2: context swap registers
	// Position of CS2 field.
	HASH_CSR2_CS2_Pos = 0x0
	// Bit mask of CS2 field.
	HASH_CSR2_CS2_Msk = 0xffffffff

	// CSR3: context swap registers
	// Position of CS3 field.
	HASH_CSR3_CS3_Pos = 0x0
	// Bit mask of CS3 field.
	HASH_CSR3_CS3_Msk = 0xffffffff

	// CSR4: context swap registers
	// Position of CS4 field.
	HASH_CSR4_CS4_Pos = 0x0
	// Bit mask of CS4 field.
	HASH_CSR4_CS4_Msk = 0xffffffff

	// CSR5: context swap registers
	// Position of CS5 field.
	HASH_CSR5_CS5_Pos = 0x0
	// Bit mask of CS5 field.
	HASH_CSR5_CS5_Msk = 0xffffffff

	// CSR6: context swap registers
	// Position of CS6 field.
	HASH_CSR6_CS6_Pos = 0x0
	// Bit mask of CS6 field.
	HASH_CSR6_CS6_Msk = 0xffffffff

	// CSR7: context swap registers
	// Position of CS7 field.
	HASH_CSR7_CS7_Pos = 0x0
	// Bit mask of CS7 field.
	HASH_CSR7_CS7_Msk = 0xffffffff

	// CSR8: context swap registers
	// Position of CS8 field.
	HASH_CSR8_CS8_Pos = 0x0
	// Bit mask of CS8 field.
	HASH_CSR8_CS8_Msk = 0xffffffff

	// CSR9: context swap registers
	// Position of CS9 field.
	HASH_CSR9_CS9_Pos = 0x0
	// Bit mask of CS9 field.
	HASH_CSR9_CS9_Msk = 0xffffffff

	// CSR10: context swap registers
	// Position of CS10 field.
	HASH_CSR10_CS10_Pos = 0x0
	// Bit mask of CS10 field.
	HASH_CSR10_CS10_Msk = 0xffffffff

	// CSR11: context swap registers
	// Position of CS11 field.
	HASH_CSR11_CS11_Pos = 0x0
	// Bit mask of CS11 field.
	HASH_CSR11_CS11_Msk = 0xffffffff

	// CSR12: context swap registers
	// Position of CS12 field.
	HASH_CSR12_CS12_Pos = 0x0
	// Bit mask of CS12 field.
	HASH_CSR12_CS12_Msk = 0xffffffff

	// CSR13: context swap registers
	// Position of CS13 field.
	HASH_CSR13_CS13_Pos = 0x0
	// Bit mask of CS13 field.
	HASH_CSR13_CS13_Msk = 0xffffffff

	// CSR14: context swap registers
	// Position of CS14 field.
	HASH_CSR14_CS14_Pos = 0x0
	// Bit mask of CS14 field.
	HASH_CSR14_CS14_Msk = 0xffffffff

	// CSR15: context swap registers
	// Position of CS15 field.
	HASH_CSR15_CS15_Pos = 0x0
	// Bit mask of CS15 field.
	HASH_CSR15_CS15_Msk = 0xffffffff

	// CSR16: context swap registers
	// Position of CS16 field.
	HASH_CSR16_CS16_Pos = 0x0
	// Bit mask of CS16 field.
	HASH_CSR16_CS16_Msk = 0xffffffff

	// CSR17: context swap registers
	// Position of CS17 field.
	HASH_CSR17_CS17_Pos = 0x0
	// Bit mask of CS17 field.
	HASH_CSR17_CS17_Msk = 0xffffffff

	// CSR18: context swap registers
	// Position of CS18 field.
	HASH_CSR18_CS18_Pos = 0x0
	// Bit mask of CS18 field.
	HASH_CSR18_CS18_Msk = 0xffffffff

	// CSR19: context swap registers
	// Position of CS19 field.
	HASH_CSR19_CS19_Pos = 0x0
	// Bit mask of CS19 field.
	HASH_CSR19_CS19_Msk = 0xffffffff

	// CSR20: context swap registers
	// Position of CS20 field.
	HASH_CSR20_CS20_Pos = 0x0
	// Bit mask of CS20 field.
	HASH_CSR20_CS20_Msk = 0xffffffff

	// CSR21: context swap registers
	// Position of CS21 field.
	HASH_CSR21_CS21_Pos = 0x0
	// Bit mask of CS21 field.
	HASH_CSR21_CS21_Msk = 0xffffffff

	// CSR22: context swap registers
	// Position of CS22 field.
	HASH_CSR22_CS22_Pos = 0x0
	// Bit mask of CS22 field.
	HASH_CSR22_CS22_Msk = 0xffffffff

	// CSR23: context swap registers
	// Position of CS23 field.
	HASH_CSR23_CS23_Pos = 0x0
	// Bit mask of CS23 field.
	HASH_CSR23_CS23_Msk = 0xffffffff

	// CSR24: context swap registers
	// Position of CS24 field.
	HASH_CSR24_CS24_Pos = 0x0
	// Bit mask of CS24 field.
	HASH_CSR24_CS24_Msk = 0xffffffff

	// CSR25: context swap registers
	// Position of CS25 field.
	HASH_CSR25_CS25_Pos = 0x0
	// Bit mask of CS25 field.
	HASH_CSR25_CS25_Msk = 0xffffffff

	// CSR26: context swap registers
	// Position of CS26 field.
	HASH_CSR26_CS26_Pos = 0x0
	// Bit mask of CS26 field.
	HASH_CSR26_CS26_Msk = 0xffffffff

	// CSR27: context swap registers
	// Position of CS27 field.
	HASH_CSR27_CS27_Pos = 0x0
	// Bit mask of CS27 field.
	HASH_CSR27_CS27_Msk = 0xffffffff

	// CSR28: context swap registers
	// Position of CS28 field.
	HASH_CSR28_CS28_Pos = 0x0
	// Bit mask of CS28 field.
	HASH_CSR28_CS28_Msk = 0xffffffff

	// CSR29: context swap registers
	// Position of CS29 field.
	HASH_CSR29_CS29_Pos = 0x0
	// Bit mask of CS29 field.
	HASH_CSR29_CS29_Msk = 0xffffffff

	// CSR30: context swap registers
	// Position of CS30 field.
	HASH_CSR30_CS30_Pos = 0x0
	// Bit mask of CS30 field.
	HASH_CSR30_CS30_Msk = 0xffffffff

	// CSR31: context swap registers
	// Position of CS31 field.
	HASH_CSR31_CS31_Pos = 0x0
	// Bit mask of CS31 field.
	HASH_CSR31_CS31_Msk = 0xffffffff

	// CSR32: context swap registers
	// Position of CS32 field.
	HASH_CSR32_CS32_Pos = 0x0
	// Bit mask of CS32 field.
	HASH_CSR32_CS32_Msk = 0xffffffff

	// CSR33: context swap registers
	// Position of CS33 field.
	HASH_CSR33_CS33_Pos = 0x0
	// Bit mask of CS33 field.
	HASH_CSR33_CS33_Msk = 0xffffffff

	// CSR34: context swap registers
	// Position of CS34 field.
	HASH_CSR34_CS34_Pos = 0x0
	// Bit mask of CS34 field.
	HASH_CSR34_CS34_Msk = 0xffffffff

	// CSR35: context swap registers
	// Position of CS35 field.
	HASH_CSR35_CS35_Pos = 0x0
	// Bit mask of CS35 field.
	HASH_CSR35_CS35_Msk = 0xffffffff

	// CSR36: context swap registers
	// Position of CS36 field.
	HASH_CSR36_CS36_Pos = 0x0
	// Bit mask of CS36 field.
	HASH_CSR36_CS36_Msk = 0xffffffff

	// CSR37: context swap registers
	// Position of CS37 field.
	HASH_CSR37_CS37_Pos = 0x0
	// Bit mask of CS37 field.
	HASH_CSR37_CS37_Msk = 0xffffffff

	// CSR38: context swap registers
	// Position of CS38 field.
	HASH_CSR38_CS38_Pos = 0x0
	// Bit mask of CS38 field.
	HASH_CSR38_CS38_Msk = 0xffffffff

	// CSR39: context swap registers
	// Position of CS39 field.
	HASH_CSR39_CS39_Pos = 0x0
	// Bit mask of CS39 field.
	HASH_CSR39_CS39_Msk = 0xffffffff

	// CSR40: context swap registers
	// Position of CS40 field.
	HASH_CSR40_CS40_Pos = 0x0
	// Bit mask of CS40 field.
	HASH_CSR40_CS40_Msk = 0xffffffff

	// CSR41: context swap registers
	// Position of CS41 field.
	HASH_CSR41_CS41_Pos = 0x0
	// Bit mask of CS41 field.
	HASH_CSR41_CS41_Msk = 0xffffffff

	// CSR42: context swap registers
	// Position of CS42 field.
	HASH_CSR42_CS42_Pos = 0x0
	// Bit mask of CS42 field.
	HASH_CSR42_CS42_Msk = 0xffffffff

	// CSR43: context swap registers
	// Position of CS43 field.
	HASH_CSR43_CS43_Pos = 0x0
	// Bit mask of CS43 field.
	HASH_CSR43_CS43_Msk = 0xffffffff

	// CSR44: context swap registers
	// Position of CS44 field.
	HASH_CSR44_CS44_Pos = 0x0
	// Bit mask of CS44 field.
	HASH_CSR44_CS44_Msk = 0xffffffff

	// CSR45: context swap registers
	// Position of CS45 field.
	HASH_CSR45_CS45_Pos = 0x0
	// Bit mask of CS45 field.
	HASH_CSR45_CS45_Msk = 0xffffffff

	// CSR46: context swap registers
	// Position of CS46 field.
	HASH_CSR46_CS46_Pos = 0x0
	// Bit mask of CS46 field.
	HASH_CSR46_CS46_Msk = 0xffffffff

	// CSR47: context swap registers
	// Position of CS47 field.
	HASH_CSR47_CS47_Pos = 0x0
	// Bit mask of CS47 field.
	HASH_CSR47_CS47_Msk = 0xffffffff

	// CSR48: context swap registers
	// Position of CS48 field.
	HASH_CSR48_CS48_Pos = 0x0
	// Bit mask of CS48 field.
	HASH_CSR48_CS48_Msk = 0xffffffff

	// CSR49: context swap registers
	// Position of CS49 field.
	HASH_CSR49_CS49_Pos = 0x0
	// Bit mask of CS49 field.
	HASH_CSR49_CS49_Msk = 0xffffffff

	// CSR50: context swap registers
	// Position of CS50 field.
	HASH_CSR50_CS50_Pos = 0x0
	// Bit mask of CS50 field.
	HASH_CSR50_CS50_Msk = 0xffffffff

	// CSR51: context swap registers
	// Position of CS51 field.
	HASH_CSR51_CS51_Pos = 0x0
	// Bit mask of CS51 field.
	HASH_CSR51_CS51_Msk = 0xffffffff

	// CSR52: context swap registers
	// Position of CS52 field.
	HASH_CSR52_CS52_Pos = 0x0
	// Bit mask of CS52 field.
	HASH_CSR52_CS52_Msk = 0xffffffff

	// CSR53: context swap registers
	// Position of CS53 field.
	HASH_CSR53_CS53_Pos = 0x0
	// Bit mask of CS53 field.
	HASH_CSR53_CS53_Msk = 0xffffffff

	// HR0: digest register 0
	// Position of H0 field.
	HASH_HR0_H0_Pos = 0x0
	// Bit mask of H0 field.
	HASH_HR0_H0_Msk = 0xffffffff

	// HR1: digest register 1
	// Position of H1 field.
	HASH_HR1_H1_Pos = 0x0
	// Bit mask of H1 field.
	HASH_HR1_H1_Msk = 0xffffffff

	// HR2: digest register 4
	// Position of H2 field.
	HASH_HR2_H2_Pos = 0x0
	// Bit mask of H2 field.
	HASH_HR2_H2_Msk = 0xffffffff

	// HR3: digest register 3
	// Position of H3 field.
	HASH_HR3_H3_Pos = 0x0
	// Bit mask of H3 field.
	HASH_HR3_H3_Msk = 0xffffffff

	// HR4: digest register 4
	// Position of H4 field.
	HASH_HR4_H4_Pos = 0x0
	// Bit mask of H4 field.
	HASH_HR4_H4_Msk = 0xffffffff

	// HR5: supplementary digest register 5
	// Position of H5 field.
	HASH_HR5_H5_Pos = 0x0
	// Bit mask of H5 field.
	HASH_HR5_H5_Msk = 0xffffffff

	// HR6: supplementary digest register 6
	// Position of H6 field.
	HASH_HR6_H6_Pos = 0x0
	// Bit mask of H6 field.
	HASH_HR6_H6_Msk = 0xffffffff

	// HR7: supplementary digest register 7
	// Position of H7 field.
	HASH_HR7_H7_Pos = 0x0
	// Bit mask of H7 field.
	HASH_HR7_H7_Msk = 0xffffffff
)

// Constants for I2C1: Inter-integrated circuit
const (
	// CR1: Control register 1
	// Position of PE field.
	I2C_CR1_PE_Pos = 0x0
	// Bit mask of PE field.
	I2C_CR1_PE_Msk = 0x1
	// Bit PE.
	I2C_CR1_PE = 0x1
	// Peripheral disabled
	I2C_CR1_PE_Disabled = 0x0
	// Peripheral enabled
	I2C_CR1_PE_Enabled = 0x1
	// Position of TXIE field.
	I2C_CR1_TXIE_Pos = 0x1
	// Bit mask of TXIE field.
	I2C_CR1_TXIE_Msk = 0x2
	// Bit TXIE.
	I2C_CR1_TXIE = 0x2
	// Transmit (TXIS) interrupt disabled
	I2C_CR1_TXIE_Disabled = 0x0
	// Transmit (TXIS) interrupt enabled
	I2C_CR1_TXIE_Enabled = 0x1
	// Position of RXIE field.
	I2C_CR1_RXIE_Pos = 0x2
	// Bit mask of RXIE field.
	I2C_CR1_RXIE_Msk = 0x4
	// Bit RXIE.
	I2C_CR1_RXIE = 0x4
	// Receive (RXNE) interrupt disabled
	I2C_CR1_RXIE_Disabled = 0x0
	// Receive (RXNE) interrupt enabled
	I2C_CR1_RXIE_Enabled = 0x1
	// Position of ADDRIE field.
	I2C_CR1_ADDRIE_Pos = 0x3
	// Bit mask of ADDRIE field.
	I2C_CR1_ADDRIE_Msk = 0x8
	// Bit ADDRIE.
	I2C_CR1_ADDRIE = 0x8
	// Address match (ADDR) interrupts disabled
	I2C_CR1_ADDRIE_Disabled = 0x0
	// Address match (ADDR) interrupts enabled
	I2C_CR1_ADDRIE_Enabled = 0x1
	// Position of NACKIE field.
	I2C_CR1_NACKIE_Pos = 0x4
	// Bit mask of NACKIE field.
	I2C_CR1_NACKIE_Msk = 0x10
	// Bit NACKIE.
	I2C_CR1_NACKIE = 0x10
	// Not acknowledge (NACKF) received interrupts disabled
	I2C_CR1_NACKIE_Disabled = 0x0
	// Not acknowledge (NACKF) received interrupts enabled
	I2C_CR1_NACKIE_Enabled = 0x1
	// Position of STOPIE field.
	I2C_CR1_STOPIE_Pos = 0x5
	// Bit mask of STOPIE field.
	I2C_CR1_STOPIE_Msk = 0x20
	// Bit STOPIE.
	I2C_CR1_STOPIE = 0x20
	// Stop detection (STOPF) interrupt disabled
	I2C_CR1_STOPIE_Disabled = 0x0
	// Stop detection (STOPF) interrupt enabled
	I2C_CR1_STOPIE_Enabled = 0x1
	// Position of TCIE field.
	I2C_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	I2C_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	I2C_CR1_TCIE = 0x40
	// Transfer Complete interrupt disabled
	I2C_CR1_TCIE_Disabled = 0x0
	// Transfer Complete interrupt enabled
	I2C_CR1_TCIE_Enabled = 0x1
	// Position of ERRIE field.
	I2C_CR1_ERRIE_Pos = 0x7
	// Bit mask of ERRIE field.
	I2C_CR1_ERRIE_Msk = 0x80
	// Bit ERRIE.
	I2C_CR1_ERRIE = 0x80
	// Error detection interrupts disabled
	I2C_CR1_ERRIE_Disabled = 0x0
	// Error detection interrupts enabled
	I2C_CR1_ERRIE_Enabled = 0x1
	// Position of DNF field.
	I2C_CR1_DNF_Pos = 0x8
	// Bit mask of DNF field.
	I2C_CR1_DNF_Msk = 0xf00
	// Digital filter disabled
	I2C_CR1_DNF_NoFilter = 0x0
	// Digital filter enabled and filtering capability up to 1 tI2CCLK
	I2C_CR1_DNF_Filter1 = 0x1
	// Digital filter enabled and filtering capability up to 2 tI2CCLK
	I2C_CR1_DNF_Filter2 = 0x2
	// Digital filter enabled and filtering capability up to 3 tI2CCLK
	I2C_CR1_DNF_Filter3 = 0x3
	// Digital filter enabled and filtering capability up to 4 tI2CCLK
	I2C_CR1_DNF_Filter4 = 0x4
	// Digital filter enabled and filtering capability up to 5 tI2CCLK
	I2C_CR1_DNF_Filter5 = 0x5
	// Digital filter enabled and filtering capability up to 6 tI2CCLK
	I2C_CR1_DNF_Filter6 = 0x6
	// Digital filter enabled and filtering capability up to 7 tI2CCLK
	I2C_CR1_DNF_Filter7 = 0x7
	// Digital filter enabled and filtering capability up to 8 tI2CCLK
	I2C_CR1_DNF_Filter8 = 0x8
	// Digital filter enabled and filtering capability up to 9 tI2CCLK
	I2C_CR1_DNF_Filter9 = 0x9
	// Digital filter enabled and filtering capability up to 10 tI2CCLK
	I2C_CR1_DNF_Filter10 = 0xa
	// Digital filter enabled and filtering capability up to 11 tI2CCLK
	I2C_CR1_DNF_Filter11 = 0xb
	// Digital filter enabled and filtering capability up to 12 tI2CCLK
	I2C_CR1_DNF_Filter12 = 0xc
	// Digital filter enabled and filtering capability up to 13 tI2CCLK
	I2C_CR1_DNF_Filter13 = 0xd
	// Digital filter enabled and filtering capability up to 14 tI2CCLK
	I2C_CR1_DNF_Filter14 = 0xe
	// Digital filter enabled and filtering capability up to 15 tI2CCLK
	I2C_CR1_DNF_Filter15 = 0xf
	// Position of ANFOFF field.
	I2C_CR1_ANFOFF_Pos = 0xc
	// Bit mask of ANFOFF field.
	I2C_CR1_ANFOFF_Msk = 0x1000
	// Bit ANFOFF.
	I2C_CR1_ANFOFF = 0x1000
	// Analog noise filter enabled
	I2C_CR1_ANFOFF_Enabled = 0x0
	// Analog noise filter disabled
	I2C_CR1_ANFOFF_Disabled = 0x1
	// Position of TXDMAEN field.
	I2C_CR1_TXDMAEN_Pos = 0xe
	// Bit mask of TXDMAEN field.
	I2C_CR1_TXDMAEN_Msk = 0x4000
	// Bit TXDMAEN.
	I2C_CR1_TXDMAEN = 0x4000
	// DMA mode disabled for transmission
	I2C_CR1_TXDMAEN_Disabled = 0x0
	// DMA mode enabled for transmission
	I2C_CR1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	I2C_CR1_RXDMAEN_Pos = 0xf
	// Bit mask of RXDMAEN field.
	I2C_CR1_RXDMAEN_Msk = 0x8000
	// Bit RXDMAEN.
	I2C_CR1_RXDMAEN = 0x8000
	// DMA mode disabled for reception
	I2C_CR1_RXDMAEN_Disabled = 0x0
	// DMA mode enabled for reception
	I2C_CR1_RXDMAEN_Enabled = 0x1
	// Position of SBC field.
	I2C_CR1_SBC_Pos = 0x10
	// Bit mask of SBC field.
	I2C_CR1_SBC_Msk = 0x10000
	// Bit SBC.
	I2C_CR1_SBC = 0x10000
	// Slave byte control disabled
	I2C_CR1_SBC_Disabled = 0x0
	// Slave byte control enabled
	I2C_CR1_SBC_Enabled = 0x1
	// Position of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Pos = 0x11
	// Bit mask of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Msk = 0x20000
	// Bit NOSTRETCH.
	I2C_CR1_NOSTRETCH = 0x20000
	// Clock stretching enabled
	I2C_CR1_NOSTRETCH_Enabled = 0x0
	// Clock stretching disabled
	I2C_CR1_NOSTRETCH_Disabled = 0x1
	// Position of WUPEN field.
	I2C_CR1_WUPEN_Pos = 0x12
	// Bit mask of WUPEN field.
	I2C_CR1_WUPEN_Msk = 0x40000
	// Bit WUPEN.
	I2C_CR1_WUPEN = 0x40000
	// Wakeup from Stop mode disabled
	I2C_CR1_WUPEN_Disabled = 0x0
	// Wakeup from Stop mode enabled
	I2C_CR1_WUPEN_Enabled = 0x1
	// Position of GCEN field.
	I2C_CR1_GCEN_Pos = 0x13
	// Bit mask of GCEN field.
	I2C_CR1_GCEN_Msk = 0x80000
	// Bit GCEN.
	I2C_CR1_GCEN = 0x80000
	// General call disabled. Address 0b00000000 is NACKed
	I2C_CR1_GCEN_Disabled = 0x0
	// General call enabled. Address 0b00000000 is ACKed
	I2C_CR1_GCEN_Enabled = 0x1
	// Position of SMBHEN field.
	I2C_CR1_SMBHEN_Pos = 0x14
	// Bit mask of SMBHEN field.
	I2C_CR1_SMBHEN_Msk = 0x100000
	// Bit SMBHEN.
	I2C_CR1_SMBHEN = 0x100000
	// Host address disabled. Address 0b0001000x is NACKed
	I2C_CR1_SMBHEN_Disabled = 0x0
	// Host address enabled. Address 0b0001000x is ACKed
	I2C_CR1_SMBHEN_Enabled = 0x1
	// Position of SMBDEN field.
	I2C_CR1_SMBDEN_Pos = 0x15
	// Bit mask of SMBDEN field.
	I2C_CR1_SMBDEN_Msk = 0x200000
	// Bit SMBDEN.
	I2C_CR1_SMBDEN = 0x200000
	// Device default address disabled. Address 0b1100001x is NACKed
	I2C_CR1_SMBDEN_Disabled = 0x0
	// Device default address enabled. Address 0b1100001x is ACKed
	I2C_CR1_SMBDEN_Enabled = 0x1
	// Position of ALERTEN field.
	I2C_CR1_ALERTEN_Pos = 0x16
	// Bit mask of ALERTEN field.
	I2C_CR1_ALERTEN_Msk = 0x400000
	// Bit ALERTEN.
	I2C_CR1_ALERTEN = 0x400000
	// In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
	I2C_CR1_ALERTEN_Disabled = 0x0
	// In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
	I2C_CR1_ALERTEN_Enabled = 0x1
	// Position of PECEN field.
	I2C_CR1_PECEN_Pos = 0x17
	// Bit mask of PECEN field.
	I2C_CR1_PECEN_Msk = 0x800000
	// Bit PECEN.
	I2C_CR1_PECEN = 0x800000
	// PEC calculation disabled
	I2C_CR1_PECEN_Disabled = 0x0
	// PEC calculation enabled
	I2C_CR1_PECEN_Enabled = 0x1
	// Position of FMP field.
	I2C_CR1_FMP_Pos = 0x18
	// Bit mask of FMP field.
	I2C_CR1_FMP_Msk = 0x1000000
	// Bit FMP.
	I2C_CR1_FMP = 0x1000000
	// 20 mA I/O drive disabled
	I2C_CR1_FMP_Disabled = 0x0
	// 20 mA I/O drive enabled
	I2C_CR1_FMP_Enabled = 0x1
	// Position of ADDRACLR field.
	I2C_CR1_ADDRACLR_Pos = 0x1e
	// Bit mask of ADDRACLR field.
	I2C_CR1_ADDRACLR_Msk = 0x40000000
	// Bit ADDRACLR.
	I2C_CR1_ADDRACLR = 0x40000000
	// ADDR flag is set by hardware, cleared by software
	I2C_CR1_ADDRACLR_Disabled = 0x0
	// ADDR flag remains cleared by hardware
	I2C_CR1_ADDRACLR_Enabled = 0x1
	// Position of STOPFACLR field.
	I2C_CR1_STOPFACLR_Pos = 0x1f
	// Bit mask of STOPFACLR field.
	I2C_CR1_STOPFACLR_Msk = 0x80000000
	// Bit STOPFACLR.
	I2C_CR1_STOPFACLR = 0x80000000
	// STOPF flag is set by hardware, cleared by software
	I2C_CR1_STOPFACLR_Disabled = 0x0
	// STOPF flag remains cleared by hardware
	I2C_CR1_STOPFACLR_Enabled = 0x1

	// CR2: Control register 2
	// Position of PECBYTE field.
	I2C_CR2_PECBYTE_Pos = 0x1a
	// Bit mask of PECBYTE field.
	I2C_CR2_PECBYTE_Msk = 0x4000000
	// Bit PECBYTE.
	I2C_CR2_PECBYTE = 0x4000000
	// No PEC transfer
	I2C_CR2_PECBYTE_NoPec = 0x0
	// PEC transmission/reception is requested
	I2C_CR2_PECBYTE_Pec = 0x1
	// Position of AUTOEND field.
	I2C_CR2_AUTOEND_Pos = 0x19
	// Bit mask of AUTOEND field.
	I2C_CR2_AUTOEND_Msk = 0x2000000
	// Bit AUTOEND.
	I2C_CR2_AUTOEND = 0x2000000
	// Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
	I2C_CR2_AUTOEND_Software = 0x0
	// Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
	I2C_CR2_AUTOEND_Automatic = 0x1
	// Position of RELOAD field.
	I2C_CR2_RELOAD_Pos = 0x18
	// Bit mask of RELOAD field.
	I2C_CR2_RELOAD_Msk = 0x1000000
	// Bit RELOAD.
	I2C_CR2_RELOAD = 0x1000000
	// The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
	I2C_CR2_RELOAD_Completed = 0x0
	// The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
	I2C_CR2_RELOAD_NotCompleted = 0x1
	// Position of NBYTES field.
	I2C_CR2_NBYTES_Pos = 0x10
	// Bit mask of NBYTES field.
	I2C_CR2_NBYTES_Msk = 0xff0000
	// Position of NACK field.
	I2C_CR2_NACK_Pos = 0xf
	// Bit mask of NACK field.
	I2C_CR2_NACK_Msk = 0x8000
	// Bit NACK.
	I2C_CR2_NACK = 0x8000
	// an ACK is sent after current received byte
	I2C_CR2_NACK_Ack = 0x0
	// a NACK is sent after current received byte
	I2C_CR2_NACK_Nack = 0x1
	// Position of STOP field.
	I2C_CR2_STOP_Pos = 0xe
	// Bit mask of STOP field.
	I2C_CR2_STOP_Msk = 0x4000
	// Bit STOP.
	I2C_CR2_STOP = 0x4000
	// No Stop generation
	I2C_CR2_STOP_NoStop = 0x0
	// Stop generation after current byte transfer
	I2C_CR2_STOP_Stop = 0x1
	// Position of START field.
	I2C_CR2_START_Pos = 0xd
	// Bit mask of START field.
	I2C_CR2_START_Msk = 0x2000
	// Bit START.
	I2C_CR2_START = 0x2000
	// No Start generation
	I2C_CR2_START_NoStart = 0x0
	// Restart/Start generation
	I2C_CR2_START_Start = 0x1
	// Position of HEAD10R field.
	I2C_CR2_HEAD10R_Pos = 0xc
	// Bit mask of HEAD10R field.
	I2C_CR2_HEAD10R_Msk = 0x1000
	// Bit HEAD10R.
	I2C_CR2_HEAD10R = 0x1000
	// The master sends the complete 10 bit slave address read sequence
	I2C_CR2_HEAD10R_Complete = 0x0
	// The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
	I2C_CR2_HEAD10R_Partial = 0x1
	// Position of ADD10 field.
	I2C_CR2_ADD10_Pos = 0xb
	// Bit mask of ADD10 field.
	I2C_CR2_ADD10_Msk = 0x800
	// Bit ADD10.
	I2C_CR2_ADD10 = 0x800
	// The master operates in 7-bit addressing mode
	I2C_CR2_ADD10_Bit7 = 0x0
	// The master operates in 10-bit addressing mode
	I2C_CR2_ADD10_Bit10 = 0x1
	// Position of RD_WRN field.
	I2C_CR2_RD_WRN_Pos = 0xa
	// Bit mask of RD_WRN field.
	I2C_CR2_RD_WRN_Msk = 0x400
	// Bit RD_WRN.
	I2C_CR2_RD_WRN = 0x400
	// Master requests a write transfer
	I2C_CR2_RD_WRN_Write = 0x0
	// Master requests a read transfer
	I2C_CR2_RD_WRN_Read = 0x1
	// Position of SADD field.
	I2C_CR2_SADD_Pos = 0x0
	// Bit mask of SADD field.
	I2C_CR2_SADD_Msk = 0x3ff

	// OAR1: Own address register 1
	// Position of OA1 field.
	I2C_OAR1_OA1_Pos = 0x0
	// Bit mask of OA1 field.
	I2C_OAR1_OA1_Msk = 0x3ff
	// Position of OA1MODE field.
	I2C_OAR1_OA1MODE_Pos = 0xa
	// Bit mask of OA1MODE field.
	I2C_OAR1_OA1MODE_Msk = 0x400
	// Bit OA1MODE.
	I2C_OAR1_OA1MODE = 0x400
	// Own address 1 is a 7-bit address
	I2C_OAR1_OA1MODE_Bit7 = 0x0
	// Own address 1 is a 10-bit address
	I2C_OAR1_OA1MODE_Bit10 = 0x1
	// Position of OA1EN field.
	I2C_OAR1_OA1EN_Pos = 0xf
	// Bit mask of OA1EN field.
	I2C_OAR1_OA1EN_Msk = 0x8000
	// Bit OA1EN.
	I2C_OAR1_OA1EN = 0x8000
	// Own address 1 disabled. The received slave address OA1 is NACKed
	I2C_OAR1_OA1EN_Disabled = 0x0
	// Own address 1 enabled. The received slave address OA1 is ACKed
	I2C_OAR1_OA1EN_Enabled = 0x1

	// OAR2: Own address register 2
	// Position of OA2 field.
	I2C_OAR2_OA2_Pos = 0x1
	// Bit mask of OA2 field.
	I2C_OAR2_OA2_Msk = 0xfe
	// Position of OA2MSK field.
	I2C_OAR2_OA2MSK_Pos = 0x8
	// Bit mask of OA2MSK field.
	I2C_OAR2_OA2MSK_Msk = 0x700
	// No mask
	I2C_OAR2_OA2MSK_NoMask = 0x0
	// OA2[1] is masked and don’t care. Only OA2[7:2] are compared
	I2C_OAR2_OA2MSK_Mask1 = 0x1
	// OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
	I2C_OAR2_OA2MSK_Mask2 = 0x2
	// OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
	I2C_OAR2_OA2MSK_Mask3 = 0x3
	// OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
	I2C_OAR2_OA2MSK_Mask4 = 0x4
	// OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
	I2C_OAR2_OA2MSK_Mask5 = 0x5
	// OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
	I2C_OAR2_OA2MSK_Mask6 = 0x6
	// OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
	I2C_OAR2_OA2MSK_Mask7 = 0x7
	// Position of OA2EN field.
	I2C_OAR2_OA2EN_Pos = 0xf
	// Bit mask of OA2EN field.
	I2C_OAR2_OA2EN_Msk = 0x8000
	// Bit OA2EN.
	I2C_OAR2_OA2EN = 0x8000
	// Own address 2 disabled. The received slave address OA2 is NACKed
	I2C_OAR2_OA2EN_Disabled = 0x0
	// Own address 2 enabled. The received slave address OA2 is ACKed
	I2C_OAR2_OA2EN_Enabled = 0x1

	// TIMINGR: Timing register
	// Position of SCLL field.
	I2C_TIMINGR_SCLL_Pos = 0x0
	// Bit mask of SCLL field.
	I2C_TIMINGR_SCLL_Msk = 0xff
	// Position of SCLH field.
	I2C_TIMINGR_SCLH_Pos = 0x8
	// Bit mask of SCLH field.
	I2C_TIMINGR_SCLH_Msk = 0xff00
	// Position of SDADEL field.
	I2C_TIMINGR_SDADEL_Pos = 0x10
	// Bit mask of SDADEL field.
	I2C_TIMINGR_SDADEL_Msk = 0xf0000
	// Position of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Pos = 0x14
	// Bit mask of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Msk = 0xf00000
	// Position of PRESC field.
	I2C_TIMINGR_PRESC_Pos = 0x1c
	// Bit mask of PRESC field.
	I2C_TIMINGR_PRESC_Msk = 0xf0000000

	// TIMEOUTR: Status register 1
	// Position of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0
	// Bit mask of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff
	// Position of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Pos = 0xc
	// Bit mask of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Msk = 0x1000
	// Bit TIDLE.
	I2C_TIMEOUTR_TIDLE = 0x1000
	// TIMEOUTA is used to detect SCL low timeout
	I2C_TIMEOUTR_TIDLE_Disabled = 0x0
	// TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
	I2C_TIMEOUTR_TIDLE_Enabled = 0x1
	// Position of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf
	// Bit mask of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000
	// Bit TIMOUTEN.
	I2C_TIMEOUTR_TIMOUTEN = 0x8000
	// SCL timeout detection is disabled
	I2C_TIMEOUTR_TIMOUTEN_Disabled = 0x0
	// SCL timeout detection is enabled
	I2C_TIMEOUTR_TIMOUTEN_Enabled = 0x1
	// Position of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10
	// Bit mask of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000
	// Position of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Pos = 0x1f
	// Bit mask of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Msk = 0x80000000
	// Bit TEXTEN.
	I2C_TIMEOUTR_TEXTEN = 0x80000000
	// Extended clock timeout detection is disabled
	I2C_TIMEOUTR_TEXTEN_Disabled = 0x0
	// Extended clock timeout detection is enabled
	I2C_TIMEOUTR_TEXTEN_Enabled = 0x1

	// ISR: Interrupt and Status register
	// Position of ADDCODE field.
	I2C_ISR_ADDCODE_Pos = 0x11
	// Bit mask of ADDCODE field.
	I2C_ISR_ADDCODE_Msk = 0xfe0000
	// Position of DIR field.
	I2C_ISR_DIR_Pos = 0x10
	// Bit mask of DIR field.
	I2C_ISR_DIR_Msk = 0x10000
	// Bit DIR.
	I2C_ISR_DIR = 0x10000
	// Write transfer, slave enters receiver mode
	I2C_ISR_DIR_Write = 0x0
	// Read transfer, slave enters transmitter mode
	I2C_ISR_DIR_Read = 0x1
	// Position of BUSY field.
	I2C_ISR_BUSY_Pos = 0xf
	// Bit mask of BUSY field.
	I2C_ISR_BUSY_Msk = 0x8000
	// Bit BUSY.
	I2C_ISR_BUSY = 0x8000
	// No communication is in progress on the bus
	I2C_ISR_BUSY_NotBusy = 0x0
	// A communication is in progress on the bus
	I2C_ISR_BUSY_Busy = 0x1
	// Position of ALERT field.
	I2C_ISR_ALERT_Pos = 0xd
	// Bit mask of ALERT field.
	I2C_ISR_ALERT_Msk = 0x2000
	// Bit ALERT.
	I2C_ISR_ALERT = 0x2000
	// SMBA alert is not detected
	I2C_ISR_ALERT_NoAlert = 0x0
	// SMBA alert event is detected on SMBA pin
	I2C_ISR_ALERT_Alert = 0x1
	// Position of TIMEOUT field.
	I2C_ISR_TIMEOUT_Pos = 0xc
	// Bit mask of TIMEOUT field.
	I2C_ISR_TIMEOUT_Msk = 0x1000
	// Bit TIMEOUT.
	I2C_ISR_TIMEOUT = 0x1000
	// No timeout occured
	I2C_ISR_TIMEOUT_NoTimeout = 0x0
	// Timeout occured
	I2C_ISR_TIMEOUT_Timeout = 0x1
	// Position of PECERR field.
	I2C_ISR_PECERR_Pos = 0xb
	// Bit mask of PECERR field.
	I2C_ISR_PECERR_Msk = 0x800
	// Bit PECERR.
	I2C_ISR_PECERR = 0x800
	// Received PEC does match with PEC register
	I2C_ISR_PECERR_Match = 0x0
	// Received PEC does not match with PEC register
	I2C_ISR_PECERR_NoMatch = 0x1
	// Position of OVR field.
	I2C_ISR_OVR_Pos = 0xa
	// Bit mask of OVR field.
	I2C_ISR_OVR_Msk = 0x400
	// Bit OVR.
	I2C_ISR_OVR = 0x400
	// No overrun/underrun error occurs
	I2C_ISR_OVR_NoOverrun = 0x0
	// slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
	I2C_ISR_OVR_Overrun = 0x1
	// Position of ARLO field.
	I2C_ISR_ARLO_Pos = 0x9
	// Bit mask of ARLO field.
	I2C_ISR_ARLO_Msk = 0x200
	// Bit ARLO.
	I2C_ISR_ARLO = 0x200
	// No arbitration lost
	I2C_ISR_ARLO_NotLost = 0x0
	// Arbitration lost
	I2C_ISR_ARLO_Lost = 0x1
	// Position of BERR field.
	I2C_ISR_BERR_Pos = 0x8
	// Bit mask of BERR field.
	I2C_ISR_BERR_Msk = 0x100
	// Bit BERR.
	I2C_ISR_BERR = 0x100
	// No bus error
	I2C_ISR_BERR_NoError = 0x0
	// Misplaced Start and Stop condition is detected
	I2C_ISR_BERR_Error = 0x1
	// Position of TCR field.
	I2C_ISR_TCR_Pos = 0x7
	// Bit mask of TCR field.
	I2C_ISR_TCR_Msk = 0x80
	// Bit TCR.
	I2C_ISR_TCR = 0x80
	// Transfer is not complete
	I2C_ISR_TCR_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TCR_Complete = 0x1
	// Position of TC field.
	I2C_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	I2C_ISR_TC_Msk = 0x40
	// Bit TC.
	I2C_ISR_TC = 0x40
	// Transfer is not complete
	I2C_ISR_TC_NotComplete = 0x0
	// NBYTES has been transfered
	I2C_ISR_TC_Complete = 0x1
	// Position of STOPF field.
	I2C_ISR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	I2C_ISR_STOPF_Msk = 0x20
	// Bit STOPF.
	I2C_ISR_STOPF = 0x20
	// No Stop condition detected
	I2C_ISR_STOPF_NoStop = 0x0
	// Stop condition detected
	I2C_ISR_STOPF_Stop = 0x1
	// Position of NACKF field.
	I2C_ISR_NACKF_Pos = 0x4
	// Bit mask of NACKF field.
	I2C_ISR_NACKF_Msk = 0x10
	// Bit NACKF.
	I2C_ISR_NACKF = 0x10
	// No NACK has been received
	I2C_ISR_NACKF_NoNack = 0x0
	// NACK has been received
	I2C_ISR_NACKF_Nack = 0x1
	// Position of ADDR field.
	I2C_ISR_ADDR_Pos = 0x3
	// Bit mask of ADDR field.
	I2C_ISR_ADDR_Msk = 0x8
	// Bit ADDR.
	I2C_ISR_ADDR = 0x8
	// Adress mismatched or not received
	I2C_ISR_ADDR_NotMatch = 0x0
	// Received slave address matched with one of the enabled slave addresses
	I2C_ISR_ADDR_Match = 0x1
	// Position of RXNE field.
	I2C_ISR_RXNE_Pos = 0x2
	// Bit mask of RXNE field.
	I2C_ISR_RXNE_Msk = 0x4
	// Bit RXNE.
	I2C_ISR_RXNE = 0x4
	// The RXDR register is empty
	I2C_ISR_RXNE_Empty = 0x0
	// Received data is copied into the RXDR register, and is ready to be read
	I2C_ISR_RXNE_NotEmpty = 0x1
	// Position of TXIS field.
	I2C_ISR_TXIS_Pos = 0x1
	// Bit mask of TXIS field.
	I2C_ISR_TXIS_Msk = 0x2
	// Bit TXIS.
	I2C_ISR_TXIS = 0x2
	// The TXDR register is not empty
	I2C_ISR_TXIS_NotEmpty = 0x0
	// The TXDR register is empty and the data to be transmitted must be written in the TXDR register
	I2C_ISR_TXIS_Empty = 0x1
	// Generate a TXIS event
	I2C_ISR_TXIS_Trigger = 0x1
	// Position of TXE field.
	I2C_ISR_TXE_Pos = 0x0
	// Bit mask of TXE field.
	I2C_ISR_TXE_Msk = 0x1
	// Bit TXE.
	I2C_ISR_TXE = 0x1
	// TXDR register not empty
	I2C_ISR_TXE_NotEmpty = 0x0
	// TXDR register empty
	I2C_ISR_TXE_Empty = 0x1
	// Flush the transmit data register
	I2C_ISR_TXE_Flush = 0x1

	// ICR: Interrupt clear register
	// Position of ALERTCF field.
	I2C_ICR_ALERTCF_Pos = 0xd
	// Bit mask of ALERTCF field.
	I2C_ICR_ALERTCF_Msk = 0x2000
	// Bit ALERTCF.
	I2C_ICR_ALERTCF = 0x2000
	// Clears the ALERT flag in ISR register
	I2C_ICR_ALERTCF_Clear = 0x1
	// Position of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Pos = 0xc
	// Bit mask of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Msk = 0x1000
	// Bit TIMOUTCF.
	I2C_ICR_TIMOUTCF = 0x1000
	// Clears the TIMOUT flag in ISR register
	I2C_ICR_TIMOUTCF_Clear = 0x1
	// Position of PECCF field.
	I2C_ICR_PECCF_Pos = 0xb
	// Bit mask of PECCF field.
	I2C_ICR_PECCF_Msk = 0x800
	// Bit PECCF.
	I2C_ICR_PECCF = 0x800
	// Clears the PEC flag in ISR register
	I2C_ICR_PECCF_Clear = 0x1
	// Position of OVRCF field.
	I2C_ICR_OVRCF_Pos = 0xa
	// Bit mask of OVRCF field.
	I2C_ICR_OVRCF_Msk = 0x400
	// Bit OVRCF.
	I2C_ICR_OVRCF = 0x400
	// Clears the OVR flag in ISR register
	I2C_ICR_OVRCF_Clear = 0x1
	// Position of ARLOCF field.
	I2C_ICR_ARLOCF_Pos = 0x9
	// Bit mask of ARLOCF field.
	I2C_ICR_ARLOCF_Msk = 0x200
	// Bit ARLOCF.
	I2C_ICR_ARLOCF = 0x200
	// Clears the ARLO flag in ISR register
	I2C_ICR_ARLOCF_Clear = 0x1
	// Position of BERRCF field.
	I2C_ICR_BERRCF_Pos = 0x8
	// Bit mask of BERRCF field.
	I2C_ICR_BERRCF_Msk = 0x100
	// Bit BERRCF.
	I2C_ICR_BERRCF = 0x100
	// Clears the BERR flag in ISR register
	I2C_ICR_BERRCF_Clear = 0x1
	// Position of STOPCF field.
	I2C_ICR_STOPCF_Pos = 0x5
	// Bit mask of STOPCF field.
	I2C_ICR_STOPCF_Msk = 0x20
	// Bit STOPCF.
	I2C_ICR_STOPCF = 0x20
	// Clears the STOP flag in ISR register
	I2C_ICR_STOPCF_Clear = 0x1
	// Position of NACKCF field.
	I2C_ICR_NACKCF_Pos = 0x4
	// Bit mask of NACKCF field.
	I2C_ICR_NACKCF_Msk = 0x10
	// Bit NACKCF.
	I2C_ICR_NACKCF = 0x10
	// Clears the NACK flag in ISR register
	I2C_ICR_NACKCF_Clear = 0x1
	// Position of ADDRCF field.
	I2C_ICR_ADDRCF_Pos = 0x3
	// Bit mask of ADDRCF field.
	I2C_ICR_ADDRCF_Msk = 0x8
	// Bit ADDRCF.
	I2C_ICR_ADDRCF = 0x8
	// Clears the ADDR flag in ISR register
	I2C_ICR_ADDRCF_Clear = 0x1

	// PECR: PEC register
	// Position of PEC field.
	I2C_PECR_PEC_Pos = 0x0
	// Bit mask of PEC field.
	I2C_PECR_PEC_Msk = 0xff

	// RXDR: Receive data register
	// Position of RXDATA field.
	I2C_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	I2C_RXDR_RXDATA_Msk = 0xff

	// TXDR: Transmit data register
	// Position of TXDATA field.
	I2C_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	I2C_TXDR_TXDATA_Msk = 0xff

	// AUTOCR: I2C Autonomous mode control register
	// Position of TCDMAEN field.
	I2C_AUTOCR_TCDMAEN_Pos = 0x6
	// Bit mask of TCDMAEN field.
	I2C_AUTOCR_TCDMAEN_Msk = 0x40
	// Bit TCDMAEN.
	I2C_AUTOCR_TCDMAEN = 0x40
	// Position of TCRDMAEN field.
	I2C_AUTOCR_TCRDMAEN_Pos = 0x7
	// Bit mask of TCRDMAEN field.
	I2C_AUTOCR_TCRDMAEN_Msk = 0x80
	// Bit TCRDMAEN.
	I2C_AUTOCR_TCRDMAEN = 0x80
	// Position of TRIGSEL field.
	I2C_AUTOCR_TRIGSEL_Pos = 0x10
	// Bit mask of TRIGSEL field.
	I2C_AUTOCR_TRIGSEL_Msk = 0xf0000
	// Position of TRIGPOL field.
	I2C_AUTOCR_TRIGPOL_Pos = 0x14
	// Bit mask of TRIGPOL field.
	I2C_AUTOCR_TRIGPOL_Msk = 0x100000
	// Bit TRIGPOL.
	I2C_AUTOCR_TRIGPOL = 0x100000
	// Position of TRIGEN field.
	I2C_AUTOCR_TRIGEN_Pos = 0x15
	// Bit mask of TRIGEN field.
	I2C_AUTOCR_TRIGEN_Msk = 0x200000
	// Bit TRIGEN.
	I2C_AUTOCR_TRIGEN = 0x200000
)

// Constants for ICACHE: ICache
const (
	// CR: ICACHE control register
	// Position of EN field.
	ICache_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	ICache_CR_EN_Msk = 0x1
	// Bit EN.
	ICache_CR_EN = 0x1
	// Position of CACHEINV field.
	ICache_CR_CACHEINV_Pos = 0x1
	// Bit mask of CACHEINV field.
	ICache_CR_CACHEINV_Msk = 0x2
	// Bit CACHEINV.
	ICache_CR_CACHEINV = 0x2
	// Position of WAYSEL field.
	ICache_CR_WAYSEL_Pos = 0x2
	// Bit mask of WAYSEL field.
	ICache_CR_WAYSEL_Msk = 0x4
	// Bit WAYSEL.
	ICache_CR_WAYSEL = 0x4
	// Position of HITMEN field.
	ICache_CR_HITMEN_Pos = 0x10
	// Bit mask of HITMEN field.
	ICache_CR_HITMEN_Msk = 0x10000
	// Bit HITMEN.
	ICache_CR_HITMEN = 0x10000
	// Position of MISSMEN field.
	ICache_CR_MISSMEN_Pos = 0x11
	// Bit mask of MISSMEN field.
	ICache_CR_MISSMEN_Msk = 0x20000
	// Bit MISSMEN.
	ICache_CR_MISSMEN = 0x20000
	// Position of HITMRST field.
	ICache_CR_HITMRST_Pos = 0x12
	// Bit mask of HITMRST field.
	ICache_CR_HITMRST_Msk = 0x40000
	// Bit HITMRST.
	ICache_CR_HITMRST = 0x40000
	// Position of MISSMRST field.
	ICache_CR_MISSMRST_Pos = 0x13
	// Bit mask of MISSMRST field.
	ICache_CR_MISSMRST_Msk = 0x80000
	// Bit MISSMRST.
	ICache_CR_MISSMRST = 0x80000

	// SR: ICACHE status register
	// Position of BUSYF field.
	ICache_SR_BUSYF_Pos = 0x0
	// Bit mask of BUSYF field.
	ICache_SR_BUSYF_Msk = 0x1
	// Bit BUSYF.
	ICache_SR_BUSYF = 0x1
	// Position of BSYENDF field.
	ICache_SR_BSYENDF_Pos = 0x1
	// Bit mask of BSYENDF field.
	ICache_SR_BSYENDF_Msk = 0x2
	// Bit BSYENDF.
	ICache_SR_BSYENDF = 0x2
	// Position of ERRF field.
	ICache_SR_ERRF_Pos = 0x2
	// Bit mask of ERRF field.
	ICache_SR_ERRF_Msk = 0x4
	// Bit ERRF.
	ICache_SR_ERRF = 0x4

	// IER: ICACHE interrupt enable register
	// Position of BSYENDIE field.
	ICache_IER_BSYENDIE_Pos = 0x1
	// Bit mask of BSYENDIE field.
	ICache_IER_BSYENDIE_Msk = 0x2
	// Bit BSYENDIE.
	ICache_IER_BSYENDIE = 0x2
	// Position of ERRIE field.
	ICache_IER_ERRIE_Pos = 0x2
	// Bit mask of ERRIE field.
	ICache_IER_ERRIE_Msk = 0x4
	// Bit ERRIE.
	ICache_IER_ERRIE = 0x4

	// FCR: ICACHE flag clear register
	// Position of CBSYENDF field.
	ICache_FCR_CBSYENDF_Pos = 0x1
	// Bit mask of CBSYENDF field.
	ICache_FCR_CBSYENDF_Msk = 0x2
	// Bit CBSYENDF.
	ICache_FCR_CBSYENDF = 0x2
	// Position of CERRF field.
	ICache_FCR_CERRF_Pos = 0x2
	// Bit mask of CERRF field.
	ICache_FCR_CERRF_Msk = 0x4
	// Bit CERRF.
	ICache_FCR_CERRF = 0x4

	// HMONR: ICACHE hit monitor register
	// Position of HITMON field.
	ICache_HMONR_HITMON_Pos = 0x0
	// Bit mask of HITMON field.
	ICache_HMONR_HITMON_Msk = 0xffffffff

	// MMONR: ICACHE miss monitor register
	// Position of MISSMON field.
	ICache_MMONR_MISSMON_Pos = 0x0
	// Bit mask of MISSMON field.
	ICache_MMONR_MISSMON_Msk = 0xffff

	// CRR0: ICACHE region configuration register
	// Position of BASEADDR field.
	ICache_CRR0_BASEADDR_Pos = 0x0
	// Bit mask of BASEADDR field.
	ICache_CRR0_BASEADDR_Msk = 0xff
	// Position of RSIZE field.
	ICache_CRR0_RSIZE_Pos = 0x9
	// Bit mask of RSIZE field.
	ICache_CRR0_RSIZE_Msk = 0xe00
	// Position of REN field.
	ICache_CRR0_REN_Pos = 0xf
	// Bit mask of REN field.
	ICache_CRR0_REN_Msk = 0x8000
	// Bit REN.
	ICache_CRR0_REN = 0x8000
	// Position of REMAPADDR field.
	ICache_CRR0_REMAPADDR_Pos = 0x10
	// Bit mask of REMAPADDR field.
	ICache_CRR0_REMAPADDR_Msk = 0x7ff0000
	// Position of MSTSEL field.
	ICache_CRR0_MSTSEL_Pos = 0x1c
	// Bit mask of MSTSEL field.
	ICache_CRR0_MSTSEL_Msk = 0x10000000
	// Bit MSTSEL.
	ICache_CRR0_MSTSEL = 0x10000000
	// Position of HBURST field.
	ICache_CRR0_HBURST_Pos = 0x1f
	// Bit mask of HBURST field.
	ICache_CRR0_HBURST_Msk = 0x80000000
	// Bit HBURST.
	ICache_CRR0_HBURST = 0x80000000

	// CRR1: ICACHE region configuration register
	// Position of BASEADDR field.
	ICache_CRR1_BASEADDR_Pos = 0x0
	// Bit mask of BASEADDR field.
	ICache_CRR1_BASEADDR_Msk = 0xff
	// Position of RSIZE field.
	ICache_CRR1_RSIZE_Pos = 0x9
	// Bit mask of RSIZE field.
	ICache_CRR1_RSIZE_Msk = 0xe00
	// Position of REN field.
	ICache_CRR1_REN_Pos = 0xf
	// Bit mask of REN field.
	ICache_CRR1_REN_Msk = 0x8000
	// Bit REN.
	ICache_CRR1_REN = 0x8000
	// Position of REMAPADDR field.
	ICache_CRR1_REMAPADDR_Pos = 0x10
	// Bit mask of REMAPADDR field.
	ICache_CRR1_REMAPADDR_Msk = 0x7ff0000
	// Position of MSTSEL field.
	ICache_CRR1_MSTSEL_Pos = 0x1c
	// Bit mask of MSTSEL field.
	ICache_CRR1_MSTSEL_Msk = 0x10000000
	// Bit MSTSEL.
	ICache_CRR1_MSTSEL = 0x10000000
	// Position of HBURST field.
	ICache_CRR1_HBURST_Pos = 0x1f
	// Bit mask of HBURST field.
	ICache_CRR1_HBURST_Msk = 0x80000000
	// Bit HBURST.
	ICache_CRR1_HBURST = 0x80000000

	// CRR2: ICACHE region configuration register
	// Position of BASEADDR field.
	ICache_CRR2_BASEADDR_Pos = 0x0
	// Bit mask of BASEADDR field.
	ICache_CRR2_BASEADDR_Msk = 0xff
	// Position of RSIZE field.
	ICache_CRR2_RSIZE_Pos = 0x9
	// Bit mask of RSIZE field.
	ICache_CRR2_RSIZE_Msk = 0xe00
	// Position of REN field.
	ICache_CRR2_REN_Pos = 0xf
	// Bit mask of REN field.
	ICache_CRR2_REN_Msk = 0x8000
	// Bit REN.
	ICache_CRR2_REN = 0x8000
	// Position of REMAPADDR field.
	ICache_CRR2_REMAPADDR_Pos = 0x10
	// Bit mask of REMAPADDR field.
	ICache_CRR2_REMAPADDR_Msk = 0x7ff0000
	// Position of MSTSEL field.
	ICache_CRR2_MSTSEL_Pos = 0x1c
	// Bit mask of MSTSEL field.
	ICache_CRR2_MSTSEL_Msk = 0x10000000
	// Bit MSTSEL.
	ICache_CRR2_MSTSEL = 0x10000000
	// Position of HBURST field.
	ICache_CRR2_HBURST_Pos = 0x1f
	// Bit mask of HBURST field.
	ICache_CRR2_HBURST_Msk = 0x80000000
	// Bit HBURST.
	ICache_CRR2_HBURST = 0x80000000

	// CRR3: ICACHE region configuration register
	// Position of BASEADDR field.
	ICache_CRR3_BASEADDR_Pos = 0x0
	// Bit mask of BASEADDR field.
	ICache_CRR3_BASEADDR_Msk = 0xff
	// Position of RSIZE field.
	ICache_CRR3_RSIZE_Pos = 0x9
	// Bit mask of RSIZE field.
	ICache_CRR3_RSIZE_Msk = 0xe00
	// Position of REN field.
	ICache_CRR3_REN_Pos = 0xf
	// Bit mask of REN field.
	ICache_CRR3_REN_Msk = 0x8000
	// Bit REN.
	ICache_CRR3_REN = 0x8000
	// Position of REMAPADDR field.
	ICache_CRR3_REMAPADDR_Pos = 0x10
	// Bit mask of REMAPADDR field.
	ICache_CRR3_REMAPADDR_Msk = 0x7ff0000
	// Position of MSTSEL field.
	ICache_CRR3_MSTSEL_Pos = 0x1c
	// Bit mask of MSTSEL field.
	ICache_CRR3_MSTSEL_Msk = 0x10000000
	// Bit MSTSEL.
	ICache_CRR3_MSTSEL = 0x10000000
	// Position of HBURST field.
	ICache_CRR3_HBURST_Pos = 0x1f
	// Bit mask of HBURST field.
	ICache_CRR3_HBURST_Msk = 0x80000000
	// Bit HBURST.
	ICache_CRR3_HBURST = 0x80000000
)

// Constants for IWDG: Independent watchdog
const (
	// KR: Key register
	// Position of KEY field.
	IWDG_KR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	IWDG_KR_KEY_Msk = 0xffff

	// PR: Prescaler register
	// Position of PR field.
	IWDG_PR_PR_Pos = 0x0
	// Bit mask of PR field.
	IWDG_PR_PR_Msk = 0xf

	// RLR: Reload register
	// Position of RL field.
	IWDG_RLR_RL_Pos = 0x0
	// Bit mask of RL field.
	IWDG_RLR_RL_Msk = 0xfff

	// SR: Status register
	// Position of EWIF field.
	IWDG_SR_EWIF_Pos = 0xe
	// Bit mask of EWIF field.
	IWDG_SR_EWIF_Msk = 0x4000
	// Bit EWIF.
	IWDG_SR_EWIF = 0x4000
	// Position of EWU field.
	IWDG_SR_EWU_Pos = 0x3
	// Bit mask of EWU field.
	IWDG_SR_EWU_Msk = 0x8
	// Bit EWU.
	IWDG_SR_EWU = 0x8
	// Position of WVU field.
	IWDG_SR_WVU_Pos = 0x2
	// Bit mask of WVU field.
	IWDG_SR_WVU_Msk = 0x4
	// Bit WVU.
	IWDG_SR_WVU = 0x4
	// Position of RVU field.
	IWDG_SR_RVU_Pos = 0x1
	// Bit mask of RVU field.
	IWDG_SR_RVU_Msk = 0x2
	// Bit RVU.
	IWDG_SR_RVU = 0x2
	// Position of PVU field.
	IWDG_SR_PVU_Pos = 0x0
	// Bit mask of PVU field.
	IWDG_SR_PVU_Msk = 0x1
	// Bit PVU.
	IWDG_SR_PVU = 0x1

	// WINR: Window register
	// Position of WIN field.
	IWDG_WINR_WIN_Pos = 0x0
	// Bit mask of WIN field.
	IWDG_WINR_WIN_Msk = 0xfff

	// EWCR: IWDG early wakeup interrupt register
	// Position of EWIT field.
	IWDG_EWCR_EWIT_Pos = 0x0
	// Bit mask of EWIT field.
	IWDG_EWCR_EWIT_Msk = 0xfff
	// Position of EWIC field.
	IWDG_EWCR_EWIC_Pos = 0xe
	// Bit mask of EWIC field.
	IWDG_EWCR_EWIC_Msk = 0x4000
	// Bit EWIC.
	IWDG_EWCR_EWIC = 0x4000
	// Position of EWIE field.
	IWDG_EWCR_EWIE_Pos = 0xf
	// Bit mask of EWIE field.
	IWDG_EWCR_EWIE_Msk = 0x8000
	// Bit EWIE.
	IWDG_EWCR_EWIE = 0x8000
)

// Constants for LPDMA1: LPDMA1
const (
	// SECCFGR: LPDMA secure configuration register
	// Position of SEC0 field.
	LPDMA_SECCFGR_SEC0_Pos = 0x1
	// Bit mask of SEC0 field.
	LPDMA_SECCFGR_SEC0_Msk = 0x2
	// Bit SEC0.
	LPDMA_SECCFGR_SEC0 = 0x2
	// Position of SEC1 field.
	LPDMA_SECCFGR_SEC1_Pos = 0x2
	// Bit mask of SEC1 field.
	LPDMA_SECCFGR_SEC1_Msk = 0x4
	// Bit SEC1.
	LPDMA_SECCFGR_SEC1 = 0x4
	// Position of SEC2 field.
	LPDMA_SECCFGR_SEC2_Pos = 0x3
	// Bit mask of SEC2 field.
	LPDMA_SECCFGR_SEC2_Msk = 0x8
	// Bit SEC2.
	LPDMA_SECCFGR_SEC2 = 0x8
	// Position of SEC3 field.
	LPDMA_SECCFGR_SEC3_Pos = 0x4
	// Bit mask of SEC3 field.
	LPDMA_SECCFGR_SEC3_Msk = 0x10
	// Bit SEC3.
	LPDMA_SECCFGR_SEC3 = 0x10

	// PRIVCFGR: LPDMA privileged configuration register
	// Position of PRIV0 field.
	LPDMA_PRIVCFGR_PRIV0_Pos = 0x1
	// Bit mask of PRIV0 field.
	LPDMA_PRIVCFGR_PRIV0_Msk = 0x2
	// Bit PRIV0.
	LPDMA_PRIVCFGR_PRIV0 = 0x2
	// Position of PRIV1 field.
	LPDMA_PRIVCFGR_PRIV1_Pos = 0x2
	// Bit mask of PRIV1 field.
	LPDMA_PRIVCFGR_PRIV1_Msk = 0x4
	// Bit PRIV1.
	LPDMA_PRIVCFGR_PRIV1 = 0x4
	// Position of PRIV2 field.
	LPDMA_PRIVCFGR_PRIV2_Pos = 0x3
	// Bit mask of PRIV2 field.
	LPDMA_PRIVCFGR_PRIV2_Msk = 0x8
	// Bit PRIV2.
	LPDMA_PRIVCFGR_PRIV2 = 0x8
	// Position of PRIV3 field.
	LPDMA_PRIVCFGR_PRIV3_Pos = 0x4
	// Bit mask of PRIV3 field.
	LPDMA_PRIVCFGR_PRIV3_Msk = 0x10
	// Bit PRIV3.
	LPDMA_PRIVCFGR_PRIV3 = 0x10

	// MISR: LPDMA non-secure masked interrupt status register
	// Position of MIS0 field.
	LPDMA_MISR_MIS0_Pos = 0x1
	// Bit mask of MIS0 field.
	LPDMA_MISR_MIS0_Msk = 0x2
	// Bit MIS0.
	LPDMA_MISR_MIS0 = 0x2
	// Position of MIS1 field.
	LPDMA_MISR_MIS1_Pos = 0x2
	// Bit mask of MIS1 field.
	LPDMA_MISR_MIS1_Msk = 0x4
	// Bit MIS1.
	LPDMA_MISR_MIS1 = 0x4
	// Position of MIS2 field.
	LPDMA_MISR_MIS2_Pos = 0x3
	// Bit mask of MIS2 field.
	LPDMA_MISR_MIS2_Msk = 0x8
	// Bit MIS2.
	LPDMA_MISR_MIS2 = 0x8
	// Position of MIS3 field.
	LPDMA_MISR_MIS3_Pos = 0x4
	// Bit mask of MIS3 field.
	LPDMA_MISR_MIS3_Msk = 0x10
	// Bit MIS3.
	LPDMA_MISR_MIS3 = 0x10

	// SMISR: LPDMA secure masked interrupt status register
	// Position of MIS0 field.
	LPDMA_SMISR_MIS0_Pos = 0x1
	// Bit mask of MIS0 field.
	LPDMA_SMISR_MIS0_Msk = 0x2
	// Bit MIS0.
	LPDMA_SMISR_MIS0 = 0x2
	// Position of MIS1 field.
	LPDMA_SMISR_MIS1_Pos = 0x2
	// Bit mask of MIS1 field.
	LPDMA_SMISR_MIS1_Msk = 0x4
	// Bit MIS1.
	LPDMA_SMISR_MIS1 = 0x4
	// Position of MIS2 field.
	LPDMA_SMISR_MIS2_Pos = 0x3
	// Bit mask of MIS2 field.
	LPDMA_SMISR_MIS2_Msk = 0x8
	// Bit MIS2.
	LPDMA_SMISR_MIS2 = 0x8
	// Position of MIS3 field.
	LPDMA_SMISR_MIS3_Pos = 0x4
	// Bit mask of MIS3 field.
	LPDMA_SMISR_MIS3_Msk = 0x10
	// Bit MIS3.
	LPDMA_SMISR_MIS3 = 0x10

	// CH.LBAR: channel x linked-list base address register
	// Position of LBA field.
	LPDMA_CH_LBAR_LBA_Pos = 0x10
	// Bit mask of LBA field.
	LPDMA_CH_LBAR_LBA_Msk = 0xffff0000

	// CH.FCR: LPDMA channel x flag clear register
	// Position of TCF field.
	LPDMA_CH_FCR_TCF_Pos = 0x8
	// Bit mask of TCF field.
	LPDMA_CH_FCR_TCF_Msk = 0x100
	// Bit TCF.
	LPDMA_CH_FCR_TCF = 0x100
	// Position of HTF field.
	LPDMA_CH_FCR_HTF_Pos = 0x9
	// Bit mask of HTF field.
	LPDMA_CH_FCR_HTF_Msk = 0x200
	// Bit HTF.
	LPDMA_CH_FCR_HTF = 0x200
	// Position of DTEF field.
	LPDMA_CH_FCR_DTEF_Pos = 0xa
	// Bit mask of DTEF field.
	LPDMA_CH_FCR_DTEF_Msk = 0x400
	// Bit DTEF.
	LPDMA_CH_FCR_DTEF = 0x400
	// Position of ULEF field.
	LPDMA_CH_FCR_ULEF_Pos = 0xb
	// Bit mask of ULEF field.
	LPDMA_CH_FCR_ULEF_Msk = 0x800
	// Bit ULEF.
	LPDMA_CH_FCR_ULEF = 0x800
	// Position of USEF field.
	LPDMA_CH_FCR_USEF_Pos = 0xc
	// Bit mask of USEF field.
	LPDMA_CH_FCR_USEF_Msk = 0x1000
	// Bit USEF.
	LPDMA_CH_FCR_USEF = 0x1000
	// Position of SUSPF field.
	LPDMA_CH_FCR_SUSPF_Pos = 0xd
	// Bit mask of SUSPF field.
	LPDMA_CH_FCR_SUSPF_Msk = 0x2000
	// Bit SUSPF.
	LPDMA_CH_FCR_SUSPF = 0x2000

	// CH.SR: channel x status register
	// Position of IDLEF field.
	LPDMA_CH_SR_IDLEF_Pos = 0x0
	// Bit mask of IDLEF field.
	LPDMA_CH_SR_IDLEF_Msk = 0x1
	// Bit IDLEF.
	LPDMA_CH_SR_IDLEF = 0x1
	// Position of TCF field.
	LPDMA_CH_SR_TCF_Pos = 0x8
	// Bit mask of TCF field.
	LPDMA_CH_SR_TCF_Msk = 0x100
	// Bit TCF.
	LPDMA_CH_SR_TCF = 0x100
	// Position of HTF field.
	LPDMA_CH_SR_HTF_Pos = 0x9
	// Bit mask of HTF field.
	LPDMA_CH_SR_HTF_Msk = 0x200
	// Bit HTF.
	LPDMA_CH_SR_HTF = 0x200
	// Position of DTEF field.
	LPDMA_CH_SR_DTEF_Pos = 0xa
	// Bit mask of DTEF field.
	LPDMA_CH_SR_DTEF_Msk = 0x400
	// Bit DTEF.
	LPDMA_CH_SR_DTEF = 0x400
	// Position of ULEF field.
	LPDMA_CH_SR_ULEF_Pos = 0xb
	// Bit mask of ULEF field.
	LPDMA_CH_SR_ULEF_Msk = 0x800
	// Bit ULEF.
	LPDMA_CH_SR_ULEF = 0x800
	// Position of USEF field.
	LPDMA_CH_SR_USEF_Pos = 0xc
	// Bit mask of USEF field.
	LPDMA_CH_SR_USEF_Msk = 0x1000
	// Bit USEF.
	LPDMA_CH_SR_USEF = 0x1000
	// Position of SUSPF field.
	LPDMA_CH_SR_SUSPF_Pos = 0xd
	// Bit mask of SUSPF field.
	LPDMA_CH_SR_SUSPF_Msk = 0x2000
	// Bit SUSPF.
	LPDMA_CH_SR_SUSPF = 0x2000

	// CH.CR: channel x control register
	// Position of EN field.
	LPDMA_CH_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	LPDMA_CH_CR_EN_Msk = 0x1
	// Bit EN.
	LPDMA_CH_CR_EN = 0x1
	// Position of RESET field.
	LPDMA_CH_CR_RESET_Pos = 0x1
	// Bit mask of RESET field.
	LPDMA_CH_CR_RESET_Msk = 0x2
	// Bit RESET.
	LPDMA_CH_CR_RESET = 0x2
	// Position of SUSP field.
	LPDMA_CH_CR_SUSP_Pos = 0x2
	// Bit mask of SUSP field.
	LPDMA_CH_CR_SUSP_Msk = 0x4
	// Bit SUSP.
	LPDMA_CH_CR_SUSP = 0x4
	// Position of TCIE field.
	LPDMA_CH_CR_TCIE_Pos = 0x8
	// Bit mask of TCIE field.
	LPDMA_CH_CR_TCIE_Msk = 0x100
	// Bit TCIE.
	LPDMA_CH_CR_TCIE = 0x100
	// Position of HTIE field.
	LPDMA_CH_CR_HTIE_Pos = 0x9
	// Bit mask of HTIE field.
	LPDMA_CH_CR_HTIE_Msk = 0x200
	// Bit HTIE.
	LPDMA_CH_CR_HTIE = 0x200
	// Position of DTEIE field.
	LPDMA_CH_CR_DTEIE_Pos = 0xa
	// Bit mask of DTEIE field.
	LPDMA_CH_CR_DTEIE_Msk = 0x400
	// Bit DTEIE.
	LPDMA_CH_CR_DTEIE = 0x400
	// Position of ULEIE field.
	LPDMA_CH_CR_ULEIE_Pos = 0xb
	// Bit mask of ULEIE field.
	LPDMA_CH_CR_ULEIE_Msk = 0x800
	// Bit ULEIE.
	LPDMA_CH_CR_ULEIE = 0x800
	// Position of USEIE field.
	LPDMA_CH_CR_USEIE_Pos = 0xc
	// Bit mask of USEIE field.
	LPDMA_CH_CR_USEIE_Msk = 0x1000
	// Bit USEIE.
	LPDMA_CH_CR_USEIE = 0x1000
	// Position of SUSPIE field.
	LPDMA_CH_CR_SUSPIE_Pos = 0xd
	// Bit mask of SUSPIE field.
	LPDMA_CH_CR_SUSPIE_Msk = 0x2000
	// Bit SUSPIE.
	LPDMA_CH_CR_SUSPIE = 0x2000
	// Position of LSM field.
	LPDMA_CH_CR_LSM_Pos = 0x10
	// Bit mask of LSM field.
	LPDMA_CH_CR_LSM_Msk = 0x10000
	// Bit LSM.
	LPDMA_CH_CR_LSM = 0x10000
	// Position of PRIO field.
	LPDMA_CH_CR_PRIO_Pos = 0x16
	// Bit mask of PRIO field.
	LPDMA_CH_CR_PRIO_Msk = 0xc00000

	// CH.TR1: LPDMA channel x transfer register 1
	// Position of SDW_LOG2 field.
	LPDMA_CH_TR1_SDW_LOG2_Pos = 0x0
	// Bit mask of SDW_LOG2 field.
	LPDMA_CH_TR1_SDW_LOG2_Msk = 0x3
	// Position of SINC field.
	LPDMA_CH_TR1_SINC_Pos = 0x3
	// Bit mask of SINC field.
	LPDMA_CH_TR1_SINC_Msk = 0x8
	// Bit SINC.
	LPDMA_CH_TR1_SINC = 0x8
	// Position of PAM field.
	LPDMA_CH_TR1_PAM_Pos = 0xb
	// Bit mask of PAM field.
	LPDMA_CH_TR1_PAM_Msk = 0x1800
	// Position of SSEC field.
	LPDMA_CH_TR1_SSEC_Pos = 0xf
	// Bit mask of SSEC field.
	LPDMA_CH_TR1_SSEC_Msk = 0x8000
	// Bit SSEC.
	LPDMA_CH_TR1_SSEC = 0x8000
	// Position of DDW_LOG2 field.
	LPDMA_CH_TR1_DDW_LOG2_Pos = 0x10
	// Bit mask of DDW_LOG2 field.
	LPDMA_CH_TR1_DDW_LOG2_Msk = 0x30000
	// Position of DINC field.
	LPDMA_CH_TR1_DINC_Pos = 0x13
	// Bit mask of DINC field.
	LPDMA_CH_TR1_DINC_Msk = 0x80000
	// Bit DINC.
	LPDMA_CH_TR1_DINC = 0x80000
	// Position of DSEC field.
	LPDMA_CH_TR1_DSEC_Pos = 0x1f
	// Bit mask of DSEC field.
	LPDMA_CH_TR1_DSEC_Msk = 0x80000000
	// Bit DSEC.
	LPDMA_CH_TR1_DSEC = 0x80000000

	// CH.TR2: LPDMA channel x transfer register 2
	// Position of REQSEL field.
	LPDMA_CH_TR2_REQSEL_Pos = 0x0
	// Bit mask of REQSEL field.
	LPDMA_CH_TR2_REQSEL_Msk = 0x1f
	// Position of SWREQ field.
	LPDMA_CH_TR2_SWREQ_Pos = 0x9
	// Bit mask of SWREQ field.
	LPDMA_CH_TR2_SWREQ_Msk = 0x200
	// Bit SWREQ.
	LPDMA_CH_TR2_SWREQ = 0x200
	// Position of BREQ field.
	LPDMA_CH_TR2_BREQ_Pos = 0xb
	// Bit mask of BREQ field.
	LPDMA_CH_TR2_BREQ_Msk = 0x800
	// Bit BREQ.
	LPDMA_CH_TR2_BREQ = 0x800
	// Position of TRIGM field.
	LPDMA_CH_TR2_TRIGM_Pos = 0xe
	// Bit mask of TRIGM field.
	LPDMA_CH_TR2_TRIGM_Msk = 0xc000
	// Position of TRIGSEL field.
	LPDMA_CH_TR2_TRIGSEL_Pos = 0x10
	// Bit mask of TRIGSEL field.
	LPDMA_CH_TR2_TRIGSEL_Msk = 0x1f0000
	// Position of TRIGPOL field.
	LPDMA_CH_TR2_TRIGPOL_Pos = 0x18
	// Bit mask of TRIGPOL field.
	LPDMA_CH_TR2_TRIGPOL_Msk = 0x3000000
	// Position of TCEM field.
	LPDMA_CH_TR2_TCEM_Pos = 0x1e
	// Bit mask of TCEM field.
	LPDMA_CH_TR2_TCEM_Msk = 0xc0000000

	// CH.BR1: LPDMA channel x block register 1
	// Position of BNDT field.
	LPDMA_CH_BR1_BNDT_Pos = 0x0
	// Bit mask of BNDT field.
	LPDMA_CH_BR1_BNDT_Msk = 0xffff

	// CH.SAR: LPDMA channel x source address register
	// Position of SA field.
	LPDMA_CH_SAR_SA_Pos = 0x0
	// Bit mask of SA field.
	LPDMA_CH_SAR_SA_Msk = 0xffffffff

	// CH.DAR: LPDMA channel x destination address register
	// Position of DA field.
	LPDMA_CH_DAR_DA_Pos = 0x0
	// Bit mask of DA field.
	LPDMA_CH_DAR_DA_Msk = 0xffffffff

	// CH.LLR: LPDMA channel x linked-list address register
	// Position of LA field.
	LPDMA_CH_LLR_LA_Pos = 0x2
	// Bit mask of LA field.
	LPDMA_CH_LLR_LA_Msk = 0xfffc
	// Position of ULL field.
	LPDMA_CH_LLR_ULL_Pos = 0x10
	// Bit mask of ULL field.
	LPDMA_CH_LLR_ULL_Msk = 0x10000
	// Bit ULL.
	LPDMA_CH_LLR_ULL = 0x10000
	// Position of UDA field.
	LPDMA_CH_LLR_UDA_Pos = 0x1b
	// Bit mask of UDA field.
	LPDMA_CH_LLR_UDA_Msk = 0x8000000
	// Bit UDA.
	LPDMA_CH_LLR_UDA = 0x8000000
	// Position of USA field.
	LPDMA_CH_LLR_USA_Pos = 0x1c
	// Bit mask of USA field.
	LPDMA_CH_LLR_USA_Msk = 0x10000000
	// Bit USA.
	LPDMA_CH_LLR_USA = 0x10000000
	// Position of UB1 field.
	LPDMA_CH_LLR_UB1_Pos = 0x1d
	// Bit mask of UB1 field.
	LPDMA_CH_LLR_UB1_Msk = 0x20000000
	// Bit UB1.
	LPDMA_CH_LLR_UB1 = 0x20000000
	// Position of UT2 field.
	LPDMA_CH_LLR_UT2_Pos = 0x1e
	// Bit mask of UT2 field.
	LPDMA_CH_LLR_UT2_Msk = 0x40000000
	// Bit UT2.
	LPDMA_CH_LLR_UT2 = 0x40000000
	// Position of UT1 field.
	LPDMA_CH_LLR_UT1_Pos = 0x1f
	// Bit mask of UT1 field.
	LPDMA_CH_LLR_UT1_Msk = 0x80000000
	// Bit UT1.
	LPDMA_CH_LLR_UT1 = 0x80000000
)

// Constants for LPGPIO1: LPGPIO1
const (
	// MODER: LPGPIO port mode register
	// Position of MODE0 field.
	LPGPIO_MODER_MODE0_Pos = 0x1
	// Bit mask of MODE0 field.
	LPGPIO_MODER_MODE0_Msk = 0x2
	// Bit MODE0.
	LPGPIO_MODER_MODE0 = 0x2
	// Position of MODE1 field.
	LPGPIO_MODER_MODE1_Pos = 0x2
	// Bit mask of MODE1 field.
	LPGPIO_MODER_MODE1_Msk = 0x4
	// Bit MODE1.
	LPGPIO_MODER_MODE1 = 0x4
	// Position of MODE2 field.
	LPGPIO_MODER_MODE2_Pos = 0x3
	// Bit mask of MODE2 field.
	LPGPIO_MODER_MODE2_Msk = 0x8
	// Bit MODE2.
	LPGPIO_MODER_MODE2 = 0x8
	// Position of MODE3 field.
	LPGPIO_MODER_MODE3_Pos = 0x4
	// Bit mask of MODE3 field.
	LPGPIO_MODER_MODE3_Msk = 0x10
	// Bit MODE3.
	LPGPIO_MODER_MODE3 = 0x10
	// Position of MODE4 field.
	LPGPIO_MODER_MODE4_Pos = 0x5
	// Bit mask of MODE4 field.
	LPGPIO_MODER_MODE4_Msk = 0x20
	// Bit MODE4.
	LPGPIO_MODER_MODE4 = 0x20
	// Position of MODE5 field.
	LPGPIO_MODER_MODE5_Pos = 0x6
	// Bit mask of MODE5 field.
	LPGPIO_MODER_MODE5_Msk = 0x40
	// Bit MODE5.
	LPGPIO_MODER_MODE5 = 0x40
	// Position of MODE6 field.
	LPGPIO_MODER_MODE6_Pos = 0x7
	// Bit mask of MODE6 field.
	LPGPIO_MODER_MODE6_Msk = 0x80
	// Bit MODE6.
	LPGPIO_MODER_MODE6 = 0x80
	// Position of MODE7 field.
	LPGPIO_MODER_MODE7_Pos = 0x8
	// Bit mask of MODE7 field.
	LPGPIO_MODER_MODE7_Msk = 0x100
	// Bit MODE7.
	LPGPIO_MODER_MODE7 = 0x100
	// Position of MODE8 field.
	LPGPIO_MODER_MODE8_Pos = 0x9
	// Bit mask of MODE8 field.
	LPGPIO_MODER_MODE8_Msk = 0x200
	// Bit MODE8.
	LPGPIO_MODER_MODE8 = 0x200
	// Position of MODE9 field.
	LPGPIO_MODER_MODE9_Pos = 0xa
	// Bit mask of MODE9 field.
	LPGPIO_MODER_MODE9_Msk = 0x400
	// Bit MODE9.
	LPGPIO_MODER_MODE9 = 0x400
	// Position of MODE10 field.
	LPGPIO_MODER_MODE10_Pos = 0xb
	// Bit mask of MODE10 field.
	LPGPIO_MODER_MODE10_Msk = 0x800
	// Bit MODE10.
	LPGPIO_MODER_MODE10 = 0x800
	// Position of MODE11 field.
	LPGPIO_MODER_MODE11_Pos = 0xc
	// Bit mask of MODE11 field.
	LPGPIO_MODER_MODE11_Msk = 0x1000
	// Bit MODE11.
	LPGPIO_MODER_MODE11 = 0x1000
	// Position of MODE12 field.
	LPGPIO_MODER_MODE12_Pos = 0xd
	// Bit mask of MODE12 field.
	LPGPIO_MODER_MODE12_Msk = 0x2000
	// Bit MODE12.
	LPGPIO_MODER_MODE12 = 0x2000
	// Position of MODE13 field.
	LPGPIO_MODER_MODE13_Pos = 0xe
	// Bit mask of MODE13 field.
	LPGPIO_MODER_MODE13_Msk = 0x4000
	// Bit MODE13.
	LPGPIO_MODER_MODE13 = 0x4000
	// Position of MODE14 field.
	LPGPIO_MODER_MODE14_Pos = 0xf
	// Bit mask of MODE14 field.
	LPGPIO_MODER_MODE14_Msk = 0x8000
	// Bit MODE14.
	LPGPIO_MODER_MODE14 = 0x8000
	// Position of MODE15 field.
	LPGPIO_MODER_MODE15_Pos = 0x10
	// Bit mask of MODE15 field.
	LPGPIO_MODER_MODE15_Msk = 0x10000
	// Bit MODE15.
	LPGPIO_MODER_MODE15 = 0x10000

	// IDR: LPGPIO port input data register
	// Position of ID0 field.
	LPGPIO_IDR_ID0_Pos = 0x1
	// Bit mask of ID0 field.
	LPGPIO_IDR_ID0_Msk = 0x2
	// Bit ID0.
	LPGPIO_IDR_ID0 = 0x2
	// Position of ID1 field.
	LPGPIO_IDR_ID1_Pos = 0x2
	// Bit mask of ID1 field.
	LPGPIO_IDR_ID1_Msk = 0x4
	// Bit ID1.
	LPGPIO_IDR_ID1 = 0x4
	// Position of ID2 field.
	LPGPIO_IDR_ID2_Pos = 0x3
	// Bit mask of ID2 field.
	LPGPIO_IDR_ID2_Msk = 0x8
	// Bit ID2.
	LPGPIO_IDR_ID2 = 0x8
	// Position of ID3 field.
	LPGPIO_IDR_ID3_Pos = 0x4
	// Bit mask of ID3 field.
	LPGPIO_IDR_ID3_Msk = 0x10
	// Bit ID3.
	LPGPIO_IDR_ID3 = 0x10
	// Position of ID4 field.
	LPGPIO_IDR_ID4_Pos = 0x5
	// Bit mask of ID4 field.
	LPGPIO_IDR_ID4_Msk = 0x20
	// Bit ID4.
	LPGPIO_IDR_ID4 = 0x20
	// Position of ID5 field.
	LPGPIO_IDR_ID5_Pos = 0x6
	// Bit mask of ID5 field.
	LPGPIO_IDR_ID5_Msk = 0x40
	// Bit ID5.
	LPGPIO_IDR_ID5 = 0x40
	// Position of ID6 field.
	LPGPIO_IDR_ID6_Pos = 0x7
	// Bit mask of ID6 field.
	LPGPIO_IDR_ID6_Msk = 0x80
	// Bit ID6.
	LPGPIO_IDR_ID6 = 0x80
	// Position of ID7 field.
	LPGPIO_IDR_ID7_Pos = 0x8
	// Bit mask of ID7 field.
	LPGPIO_IDR_ID7_Msk = 0x100
	// Bit ID7.
	LPGPIO_IDR_ID7 = 0x100
	// Position of ID8 field.
	LPGPIO_IDR_ID8_Pos = 0x9
	// Bit mask of ID8 field.
	LPGPIO_IDR_ID8_Msk = 0x200
	// Bit ID8.
	LPGPIO_IDR_ID8 = 0x200
	// Position of ID9 field.
	LPGPIO_IDR_ID9_Pos = 0xa
	// Bit mask of ID9 field.
	LPGPIO_IDR_ID9_Msk = 0x400
	// Bit ID9.
	LPGPIO_IDR_ID9 = 0x400
	// Position of ID10 field.
	LPGPIO_IDR_ID10_Pos = 0xb
	// Bit mask of ID10 field.
	LPGPIO_IDR_ID10_Msk = 0x800
	// Bit ID10.
	LPGPIO_IDR_ID10 = 0x800
	// Position of ID11 field.
	LPGPIO_IDR_ID11_Pos = 0xc
	// Bit mask of ID11 field.
	LPGPIO_IDR_ID11_Msk = 0x1000
	// Bit ID11.
	LPGPIO_IDR_ID11 = 0x1000
	// Position of ID12 field.
	LPGPIO_IDR_ID12_Pos = 0xd
	// Bit mask of ID12 field.
	LPGPIO_IDR_ID12_Msk = 0x2000
	// Bit ID12.
	LPGPIO_IDR_ID12 = 0x2000
	// Position of ID13 field.
	LPGPIO_IDR_ID13_Pos = 0xe
	// Bit mask of ID13 field.
	LPGPIO_IDR_ID13_Msk = 0x4000
	// Bit ID13.
	LPGPIO_IDR_ID13 = 0x4000
	// Position of ID14 field.
	LPGPIO_IDR_ID14_Pos = 0xf
	// Bit mask of ID14 field.
	LPGPIO_IDR_ID14_Msk = 0x8000
	// Bit ID14.
	LPGPIO_IDR_ID14 = 0x8000
	// Position of ID15 field.
	LPGPIO_IDR_ID15_Pos = 0x10
	// Bit mask of ID15 field.
	LPGPIO_IDR_ID15_Msk = 0x10000
	// Bit ID15.
	LPGPIO_IDR_ID15 = 0x10000

	// ODR: LPGPIO port output data register
	// Position of OD0 field.
	LPGPIO_ODR_OD0_Pos = 0x1
	// Bit mask of OD0 field.
	LPGPIO_ODR_OD0_Msk = 0x2
	// Bit OD0.
	LPGPIO_ODR_OD0 = 0x2
	// Position of OD1 field.
	LPGPIO_ODR_OD1_Pos = 0x2
	// Bit mask of OD1 field.
	LPGPIO_ODR_OD1_Msk = 0x4
	// Bit OD1.
	LPGPIO_ODR_OD1 = 0x4
	// Position of OD2 field.
	LPGPIO_ODR_OD2_Pos = 0x3
	// Bit mask of OD2 field.
	LPGPIO_ODR_OD2_Msk = 0x8
	// Bit OD2.
	LPGPIO_ODR_OD2 = 0x8
	// Position of OD3 field.
	LPGPIO_ODR_OD3_Pos = 0x4
	// Bit mask of OD3 field.
	LPGPIO_ODR_OD3_Msk = 0x10
	// Bit OD3.
	LPGPIO_ODR_OD3 = 0x10
	// Position of OD4 field.
	LPGPIO_ODR_OD4_Pos = 0x5
	// Bit mask of OD4 field.
	LPGPIO_ODR_OD4_Msk = 0x20
	// Bit OD4.
	LPGPIO_ODR_OD4 = 0x20
	// Position of OD5 field.
	LPGPIO_ODR_OD5_Pos = 0x6
	// Bit mask of OD5 field.
	LPGPIO_ODR_OD5_Msk = 0x40
	// Bit OD5.
	LPGPIO_ODR_OD5 = 0x40
	// Position of OD6 field.
	LPGPIO_ODR_OD6_Pos = 0x7
	// Bit mask of OD6 field.
	LPGPIO_ODR_OD6_Msk = 0x80
	// Bit OD6.
	LPGPIO_ODR_OD6 = 0x80
	// Position of OD7 field.
	LPGPIO_ODR_OD7_Pos = 0x8
	// Bit mask of OD7 field.
	LPGPIO_ODR_OD7_Msk = 0x100
	// Bit OD7.
	LPGPIO_ODR_OD7 = 0x100
	// Position of OD8 field.
	LPGPIO_ODR_OD8_Pos = 0x9
	// Bit mask of OD8 field.
	LPGPIO_ODR_OD8_Msk = 0x200
	// Bit OD8.
	LPGPIO_ODR_OD8 = 0x200
	// Position of OD9 field.
	LPGPIO_ODR_OD9_Pos = 0xa
	// Bit mask of OD9 field.
	LPGPIO_ODR_OD9_Msk = 0x400
	// Bit OD9.
	LPGPIO_ODR_OD9 = 0x400
	// Position of OD10 field.
	LPGPIO_ODR_OD10_Pos = 0xb
	// Bit mask of OD10 field.
	LPGPIO_ODR_OD10_Msk = 0x800
	// Bit OD10.
	LPGPIO_ODR_OD10 = 0x800
	// Position of OD11 field.
	LPGPIO_ODR_OD11_Pos = 0xc
	// Bit mask of OD11 field.
	LPGPIO_ODR_OD11_Msk = 0x1000
	// Bit OD11.
	LPGPIO_ODR_OD11 = 0x1000
	// Position of OD12 field.
	LPGPIO_ODR_OD12_Pos = 0xd
	// Bit mask of OD12 field.
	LPGPIO_ODR_OD12_Msk = 0x2000
	// Bit OD12.
	LPGPIO_ODR_OD12 = 0x2000
	// Position of OD13 field.
	LPGPIO_ODR_OD13_Pos = 0xe
	// Bit mask of OD13 field.
	LPGPIO_ODR_OD13_Msk = 0x4000
	// Bit OD13.
	LPGPIO_ODR_OD13 = 0x4000
	// Position of OD14 field.
	LPGPIO_ODR_OD14_Pos = 0xf
	// Bit mask of OD14 field.
	LPGPIO_ODR_OD14_Msk = 0x8000
	// Bit OD14.
	LPGPIO_ODR_OD14 = 0x8000
	// Position of OD15 field.
	LPGPIO_ODR_OD15_Pos = 0x10
	// Bit mask of OD15 field.
	LPGPIO_ODR_OD15_Msk = 0x10000
	// Bit OD15.
	LPGPIO_ODR_OD15 = 0x10000

	// BSRR: LPGPIO port bit set/reset register
	// Position of BR0 field.
	LPGPIO_BSRR_BR0_Pos = 0x11
	// Bit mask of BR0 field.
	LPGPIO_BSRR_BR0_Msk = 0x20000
	// Bit BR0.
	LPGPIO_BSRR_BR0 = 0x20000
	// Position of BR1 field.
	LPGPIO_BSRR_BR1_Pos = 0x12
	// Bit mask of BR1 field.
	LPGPIO_BSRR_BR1_Msk = 0x40000
	// Bit BR1.
	LPGPIO_BSRR_BR1 = 0x40000
	// Position of BR2 field.
	LPGPIO_BSRR_BR2_Pos = 0x13
	// Bit mask of BR2 field.
	LPGPIO_BSRR_BR2_Msk = 0x80000
	// Bit BR2.
	LPGPIO_BSRR_BR2 = 0x80000
	// Position of BR3 field.
	LPGPIO_BSRR_BR3_Pos = 0x14
	// Bit mask of BR3 field.
	LPGPIO_BSRR_BR3_Msk = 0x100000
	// Bit BR3.
	LPGPIO_BSRR_BR3 = 0x100000
	// Position of BR4 field.
	LPGPIO_BSRR_BR4_Pos = 0x15
	// Bit mask of BR4 field.
	LPGPIO_BSRR_BR4_Msk = 0x200000
	// Bit BR4.
	LPGPIO_BSRR_BR4 = 0x200000
	// Position of BR5 field.
	LPGPIO_BSRR_BR5_Pos = 0x16
	// Bit mask of BR5 field.
	LPGPIO_BSRR_BR5_Msk = 0x400000
	// Bit BR5.
	LPGPIO_BSRR_BR5 = 0x400000
	// Position of BR6 field.
	LPGPIO_BSRR_BR6_Pos = 0x17
	// Bit mask of BR6 field.
	LPGPIO_BSRR_BR6_Msk = 0x800000
	// Bit BR6.
	LPGPIO_BSRR_BR6 = 0x800000
	// Position of BR7 field.
	LPGPIO_BSRR_BR7_Pos = 0x18
	// Bit mask of BR7 field.
	LPGPIO_BSRR_BR7_Msk = 0x1000000
	// Bit BR7.
	LPGPIO_BSRR_BR7 = 0x1000000
	// Position of BR8 field.
	LPGPIO_BSRR_BR8_Pos = 0x19
	// Bit mask of BR8 field.
	LPGPIO_BSRR_BR8_Msk = 0x2000000
	// Bit BR8.
	LPGPIO_BSRR_BR8 = 0x2000000
	// Position of BR9 field.
	LPGPIO_BSRR_BR9_Pos = 0x1a
	// Bit mask of BR9 field.
	LPGPIO_BSRR_BR9_Msk = 0x4000000
	// Bit BR9.
	LPGPIO_BSRR_BR9 = 0x4000000
	// Position of BR10 field.
	LPGPIO_BSRR_BR10_Pos = 0x1b
	// Bit mask of BR10 field.
	LPGPIO_BSRR_BR10_Msk = 0x8000000
	// Bit BR10.
	LPGPIO_BSRR_BR10 = 0x8000000
	// Position of BR11 field.
	LPGPIO_BSRR_BR11_Pos = 0x1c
	// Bit mask of BR11 field.
	LPGPIO_BSRR_BR11_Msk = 0x10000000
	// Bit BR11.
	LPGPIO_BSRR_BR11 = 0x10000000
	// Position of BR12 field.
	LPGPIO_BSRR_BR12_Pos = 0x1d
	// Bit mask of BR12 field.
	LPGPIO_BSRR_BR12_Msk = 0x20000000
	// Bit BR12.
	LPGPIO_BSRR_BR12 = 0x20000000
	// Position of BR13 field.
	LPGPIO_BSRR_BR13_Pos = 0x1e
	// Bit mask of BR13 field.
	LPGPIO_BSRR_BR13_Msk = 0x40000000
	// Bit BR13.
	LPGPIO_BSRR_BR13 = 0x40000000
	// Position of BR14 field.
	LPGPIO_BSRR_BR14_Pos = 0x1f
	// Bit mask of BR14 field.
	LPGPIO_BSRR_BR14_Msk = 0x80000000
	// Bit BR14.
	LPGPIO_BSRR_BR14 = 0x80000000
	// Position of BR15 field.
	LPGPIO_BSRR_BR15_Pos = 0x20
	// Bit mask of BR15 field.
	LPGPIO_BSRR_BR15_Msk = 0x100000000
	// Bit BR15.
	LPGPIO_BSRR_BR15 = 0x100000000
	// Position of BS0 field.
	LPGPIO_BSRR_BS0_Pos = 0x1
	// Bit mask of BS0 field.
	LPGPIO_BSRR_BS0_Msk = 0x2
	// Bit BS0.
	LPGPIO_BSRR_BS0 = 0x2
	// Position of BS1 field.
	LPGPIO_BSRR_BS1_Pos = 0x2
	// Bit mask of BS1 field.
	LPGPIO_BSRR_BS1_Msk = 0x4
	// Bit BS1.
	LPGPIO_BSRR_BS1 = 0x4
	// Position of BS2 field.
	LPGPIO_BSRR_BS2_Pos = 0x3
	// Bit mask of BS2 field.
	LPGPIO_BSRR_BS2_Msk = 0x8
	// Bit BS2.
	LPGPIO_BSRR_BS2 = 0x8
	// Position of BS3 field.
	LPGPIO_BSRR_BS3_Pos = 0x4
	// Bit mask of BS3 field.
	LPGPIO_BSRR_BS3_Msk = 0x10
	// Bit BS3.
	LPGPIO_BSRR_BS3 = 0x10
	// Position of BS4 field.
	LPGPIO_BSRR_BS4_Pos = 0x5
	// Bit mask of BS4 field.
	LPGPIO_BSRR_BS4_Msk = 0x20
	// Bit BS4.
	LPGPIO_BSRR_BS4 = 0x20
	// Position of BS5 field.
	LPGPIO_BSRR_BS5_Pos = 0x6
	// Bit mask of BS5 field.
	LPGPIO_BSRR_BS5_Msk = 0x40
	// Bit BS5.
	LPGPIO_BSRR_BS5 = 0x40
	// Position of BS6 field.
	LPGPIO_BSRR_BS6_Pos = 0x7
	// Bit mask of BS6 field.
	LPGPIO_BSRR_BS6_Msk = 0x80
	// Bit BS6.
	LPGPIO_BSRR_BS6 = 0x80
	// Position of BS7 field.
	LPGPIO_BSRR_BS7_Pos = 0x8
	// Bit mask of BS7 field.
	LPGPIO_BSRR_BS7_Msk = 0x100
	// Bit BS7.
	LPGPIO_BSRR_BS7 = 0x100
	// Position of BS8 field.
	LPGPIO_BSRR_BS8_Pos = 0x9
	// Bit mask of BS8 field.
	LPGPIO_BSRR_BS8_Msk = 0x200
	// Bit BS8.
	LPGPIO_BSRR_BS8 = 0x200
	// Position of BS9 field.
	LPGPIO_BSRR_BS9_Pos = 0xa
	// Bit mask of BS9 field.
	LPGPIO_BSRR_BS9_Msk = 0x400
	// Bit BS9.
	LPGPIO_BSRR_BS9 = 0x400
	// Position of BS10 field.
	LPGPIO_BSRR_BS10_Pos = 0xb
	// Bit mask of BS10 field.
	LPGPIO_BSRR_BS10_Msk = 0x800
	// Bit BS10.
	LPGPIO_BSRR_BS10 = 0x800
	// Position of BS11 field.
	LPGPIO_BSRR_BS11_Pos = 0xc
	// Bit mask of BS11 field.
	LPGPIO_BSRR_BS11_Msk = 0x1000
	// Bit BS11.
	LPGPIO_BSRR_BS11 = 0x1000
	// Position of BS12 field.
	LPGPIO_BSRR_BS12_Pos = 0xd
	// Bit mask of BS12 field.
	LPGPIO_BSRR_BS12_Msk = 0x2000
	// Bit BS12.
	LPGPIO_BSRR_BS12 = 0x2000
	// Position of BS13 field.
	LPGPIO_BSRR_BS13_Pos = 0xe
	// Bit mask of BS13 field.
	LPGPIO_BSRR_BS13_Msk = 0x4000
	// Bit BS13.
	LPGPIO_BSRR_BS13 = 0x4000
	// Position of BS14 field.
	LPGPIO_BSRR_BS14_Pos = 0xf
	// Bit mask of BS14 field.
	LPGPIO_BSRR_BS14_Msk = 0x8000
	// Bit BS14.
	LPGPIO_BSRR_BS14 = 0x8000
	// Position of BS15 field.
	LPGPIO_BSRR_BS15_Pos = 0x10
	// Bit mask of BS15 field.
	LPGPIO_BSRR_BS15_Msk = 0x10000
	// Bit BS15.
	LPGPIO_BSRR_BS15 = 0x10000

	// BRR: LPGPIO port bit reset register
	// Position of BR0 field.
	LPGPIO_BRR_BR0_Pos = 0x1
	// Bit mask of BR0 field.
	LPGPIO_BRR_BR0_Msk = 0x2
	// Bit BR0.
	LPGPIO_BRR_BR0 = 0x2
	// Position of BR1 field.
	LPGPIO_BRR_BR1_Pos = 0x2
	// Bit mask of BR1 field.
	LPGPIO_BRR_BR1_Msk = 0x4
	// Bit BR1.
	LPGPIO_BRR_BR1 = 0x4
	// Position of BR2 field.
	LPGPIO_BRR_BR2_Pos = 0x3
	// Bit mask of BR2 field.
	LPGPIO_BRR_BR2_Msk = 0x8
	// Bit BR2.
	LPGPIO_BRR_BR2 = 0x8
	// Position of BR3 field.
	LPGPIO_BRR_BR3_Pos = 0x4
	// Bit mask of BR3 field.
	LPGPIO_BRR_BR3_Msk = 0x10
	// Bit BR3.
	LPGPIO_BRR_BR3 = 0x10
	// Position of BR4 field.
	LPGPIO_BRR_BR4_Pos = 0x5
	// Bit mask of BR4 field.
	LPGPIO_BRR_BR4_Msk = 0x20
	// Bit BR4.
	LPGPIO_BRR_BR4 = 0x20
	// Position of BR5 field.
	LPGPIO_BRR_BR5_Pos = 0x6
	// Bit mask of BR5 field.
	LPGPIO_BRR_BR5_Msk = 0x40
	// Bit BR5.
	LPGPIO_BRR_BR5 = 0x40
	// Position of BR6 field.
	LPGPIO_BRR_BR6_Pos = 0x7
	// Bit mask of BR6 field.
	LPGPIO_BRR_BR6_Msk = 0x80
	// Bit BR6.
	LPGPIO_BRR_BR6 = 0x80
	// Position of BR7 field.
	LPGPIO_BRR_BR7_Pos = 0x8
	// Bit mask of BR7 field.
	LPGPIO_BRR_BR7_Msk = 0x100
	// Bit BR7.
	LPGPIO_BRR_BR7 = 0x100
	// Position of BR8 field.
	LPGPIO_BRR_BR8_Pos = 0x9
	// Bit mask of BR8 field.
	LPGPIO_BRR_BR8_Msk = 0x200
	// Bit BR8.
	LPGPIO_BRR_BR8 = 0x200
	// Position of BR9 field.
	LPGPIO_BRR_BR9_Pos = 0xa
	// Bit mask of BR9 field.
	LPGPIO_BRR_BR9_Msk = 0x400
	// Bit BR9.
	LPGPIO_BRR_BR9 = 0x400
	// Position of BR10 field.
	LPGPIO_BRR_BR10_Pos = 0xb
	// Bit mask of BR10 field.
	LPGPIO_BRR_BR10_Msk = 0x800
	// Bit BR10.
	LPGPIO_BRR_BR10 = 0x800
	// Position of BR11 field.
	LPGPIO_BRR_BR11_Pos = 0xc
	// Bit mask of BR11 field.
	LPGPIO_BRR_BR11_Msk = 0x1000
	// Bit BR11.
	LPGPIO_BRR_BR11 = 0x1000
	// Position of BR12 field.
	LPGPIO_BRR_BR12_Pos = 0xd
	// Bit mask of BR12 field.
	LPGPIO_BRR_BR12_Msk = 0x2000
	// Bit BR12.
	LPGPIO_BRR_BR12 = 0x2000
	// Position of BR13 field.
	LPGPIO_BRR_BR13_Pos = 0xe
	// Bit mask of BR13 field.
	LPGPIO_BRR_BR13_Msk = 0x4000
	// Bit BR13.
	LPGPIO_BRR_BR13 = 0x4000
	// Position of BR14 field.
	LPGPIO_BRR_BR14_Pos = 0xf
	// Bit mask of BR14 field.
	LPGPIO_BRR_BR14_Msk = 0x8000
	// Bit BR14.
	LPGPIO_BRR_BR14 = 0x8000
	// Position of BR15 field.
	LPGPIO_BRR_BR15_Pos = 0x10
	// Bit mask of BR15 field.
	LPGPIO_BRR_BR15_Msk = 0x10000
	// Bit BR15.
	LPGPIO_BRR_BR15 = 0x10000
)

// Constants for LPTIM1: Low power timer
const (
	// ISR_output: Interrupt and Status Register (output mode)
	// Position of DIEROK field.
	LPTIM_ISR_output_DIEROK_Pos = 0x18
	// Bit mask of DIEROK field.
	LPTIM_ISR_output_DIEROK_Msk = 0x1000000
	// Bit DIEROK.
	LPTIM_ISR_output_DIEROK = 0x1000000
	// Position of CMP2OK field.
	LPTIM_ISR_output_CMP2OK_Pos = 0x13
	// Bit mask of CMP2OK field.
	LPTIM_ISR_output_CMP2OK_Msk = 0x80000
	// Bit CMP2OK.
	LPTIM_ISR_output_CMP2OK = 0x80000
	// Position of CC2IF field.
	LPTIM_ISR_output_CC2IF_Pos = 0x9
	// Bit mask of CC2IF field.
	LPTIM_ISR_output_CC2IF_Msk = 0x200
	// Bit CC2IF.
	LPTIM_ISR_output_CC2IF = 0x200
	// Position of REPOK field.
	LPTIM_ISR_output_REPOK_Pos = 0x8
	// Bit mask of REPOK field.
	LPTIM_ISR_output_REPOK_Msk = 0x100
	// Bit REPOK.
	LPTIM_ISR_output_REPOK = 0x100
	// Position of UE field.
	LPTIM_ISR_output_UE_Pos = 0x7
	// Bit mask of UE field.
	LPTIM_ISR_output_UE_Msk = 0x80
	// Bit UE.
	LPTIM_ISR_output_UE = 0x80
	// Position of DOWN field.
	LPTIM_ISR_output_DOWN_Pos = 0x6
	// Bit mask of DOWN field.
	LPTIM_ISR_output_DOWN_Msk = 0x40
	// Bit DOWN.
	LPTIM_ISR_output_DOWN = 0x40
	// Position of UP field.
	LPTIM_ISR_output_UP_Pos = 0x5
	// Bit mask of UP field.
	LPTIM_ISR_output_UP_Msk = 0x20
	// Bit UP.
	LPTIM_ISR_output_UP = 0x20
	// Position of ARROK field.
	LPTIM_ISR_output_ARROK_Pos = 0x4
	// Bit mask of ARROK field.
	LPTIM_ISR_output_ARROK_Msk = 0x10
	// Bit ARROK.
	LPTIM_ISR_output_ARROK = 0x10
	// Position of CMP1OK field.
	LPTIM_ISR_output_CMP1OK_Pos = 0x3
	// Bit mask of CMP1OK field.
	LPTIM_ISR_output_CMP1OK_Msk = 0x8
	// Bit CMP1OK.
	LPTIM_ISR_output_CMP1OK = 0x8
	// Position of EXTTRIG field.
	LPTIM_ISR_output_EXTTRIG_Pos = 0x2
	// Bit mask of EXTTRIG field.
	LPTIM_ISR_output_EXTTRIG_Msk = 0x4
	// Bit EXTTRIG.
	LPTIM_ISR_output_EXTTRIG = 0x4
	// Position of ARRM field.
	LPTIM_ISR_output_ARRM_Pos = 0x1
	// Bit mask of ARRM field.
	LPTIM_ISR_output_ARRM_Msk = 0x2
	// Bit ARRM.
	LPTIM_ISR_output_ARRM = 0x2
	// Position of CC1IF field.
	LPTIM_ISR_output_CC1IF_Pos = 0x0
	// Bit mask of CC1IF field.
	LPTIM_ISR_output_CC1IF_Msk = 0x1
	// Bit CC1IF.
	LPTIM_ISR_output_CC1IF = 0x1

	// ISR_input: Interrupt and Status Register (intput mode)
	// Position of DIEROK field.
	LPTIM_ISR_input_DIEROK_Pos = 0x18
	// Bit mask of DIEROK field.
	LPTIM_ISR_input_DIEROK_Msk = 0x1000000
	// Bit DIEROK.
	LPTIM_ISR_input_DIEROK = 0x1000000
	// Position of CC2OF field.
	LPTIM_ISR_input_CC2OF_Pos = 0xd
	// Bit mask of CC2OF field.
	LPTIM_ISR_input_CC2OF_Msk = 0x2000
	// Bit CC2OF.
	LPTIM_ISR_input_CC2OF = 0x2000
	// Position of CC1OF field.
	LPTIM_ISR_input_CC1OF_Pos = 0xc
	// Bit mask of CC1OF field.
	LPTIM_ISR_input_CC1OF_Msk = 0x1000
	// Bit CC1OF.
	LPTIM_ISR_input_CC1OF = 0x1000
	// Position of CC2IF field.
	LPTIM_ISR_input_CC2IF_Pos = 0x9
	// Bit mask of CC2IF field.
	LPTIM_ISR_input_CC2IF_Msk = 0x200
	// Bit CC2IF.
	LPTIM_ISR_input_CC2IF = 0x200
	// Position of REPOK field.
	LPTIM_ISR_input_REPOK_Pos = 0x8
	// Bit mask of REPOK field.
	LPTIM_ISR_input_REPOK_Msk = 0x100
	// Bit REPOK.
	LPTIM_ISR_input_REPOK = 0x100
	// Position of UE field.
	LPTIM_ISR_input_UE_Pos = 0x7
	// Bit mask of UE field.
	LPTIM_ISR_input_UE_Msk = 0x80
	// Bit UE.
	LPTIM_ISR_input_UE = 0x80
	// Position of DOWN field.
	LPTIM_ISR_input_DOWN_Pos = 0x6
	// Bit mask of DOWN field.
	LPTIM_ISR_input_DOWN_Msk = 0x40
	// Bit DOWN.
	LPTIM_ISR_input_DOWN = 0x40
	// Position of UP field.
	LPTIM_ISR_input_UP_Pos = 0x5
	// Bit mask of UP field.
	LPTIM_ISR_input_UP_Msk = 0x20
	// Bit UP.
	LPTIM_ISR_input_UP = 0x20
	// Position of ARROK field.
	LPTIM_ISR_input_ARROK_Pos = 0x4
	// Bit mask of ARROK field.
	LPTIM_ISR_input_ARROK_Msk = 0x10
	// Bit ARROK.
	LPTIM_ISR_input_ARROK = 0x10
	// Position of EXTTRIG field.
	LPTIM_ISR_input_EXTTRIG_Pos = 0x2
	// Bit mask of EXTTRIG field.
	LPTIM_ISR_input_EXTTRIG_Msk = 0x4
	// Bit EXTTRIG.
	LPTIM_ISR_input_EXTTRIG = 0x4
	// Position of ARRM field.
	LPTIM_ISR_input_ARRM_Pos = 0x1
	// Bit mask of ARRM field.
	LPTIM_ISR_input_ARRM_Msk = 0x2
	// Bit ARRM.
	LPTIM_ISR_input_ARRM = 0x2
	// Position of CC1IF field.
	LPTIM_ISR_input_CC1IF_Pos = 0x0
	// Bit mask of CC1IF field.
	LPTIM_ISR_input_CC1IF_Msk = 0x1
	// Bit CC1IF.
	LPTIM_ISR_input_CC1IF = 0x1

	// ICR_output: Interrupt Clear Register (output mode)
	// Position of DIEROKCF field.
	LPTIM_ICR_output_DIEROKCF_Pos = 0x18
	// Bit mask of DIEROKCF field.
	LPTIM_ICR_output_DIEROKCF_Msk = 0x1000000
	// Bit DIEROKCF.
	LPTIM_ICR_output_DIEROKCF = 0x1000000
	// Position of CMP2OKCF field.
	LPTIM_ICR_output_CMP2OKCF_Pos = 0x13
	// Bit mask of CMP2OKCF field.
	LPTIM_ICR_output_CMP2OKCF_Msk = 0x80000
	// Bit CMP2OKCF.
	LPTIM_ICR_output_CMP2OKCF = 0x80000
	// Position of CC2CF field.
	LPTIM_ICR_output_CC2CF_Pos = 0x9
	// Bit mask of CC2CF field.
	LPTIM_ICR_output_CC2CF_Msk = 0x200
	// Bit CC2CF.
	LPTIM_ICR_output_CC2CF = 0x200
	// Position of REPOKCF field.
	LPTIM_ICR_output_REPOKCF_Pos = 0x8
	// Bit mask of REPOKCF field.
	LPTIM_ICR_output_REPOKCF_Msk = 0x100
	// Bit REPOKCF.
	LPTIM_ICR_output_REPOKCF = 0x100
	// Position of UECF field.
	LPTIM_ICR_output_UECF_Pos = 0x7
	// Bit mask of UECF field.
	LPTIM_ICR_output_UECF_Msk = 0x80
	// Bit UECF.
	LPTIM_ICR_output_UECF = 0x80
	// Position of DOWNCF field.
	LPTIM_ICR_output_DOWNCF_Pos = 0x6
	// Bit mask of DOWNCF field.
	LPTIM_ICR_output_DOWNCF_Msk = 0x40
	// Bit DOWNCF.
	LPTIM_ICR_output_DOWNCF = 0x40
	// Position of UPCF field.
	LPTIM_ICR_output_UPCF_Pos = 0x5
	// Bit mask of UPCF field.
	LPTIM_ICR_output_UPCF_Msk = 0x20
	// Bit UPCF.
	LPTIM_ICR_output_UPCF = 0x20
	// Position of ARROKCF field.
	LPTIM_ICR_output_ARROKCF_Pos = 0x4
	// Bit mask of ARROKCF field.
	LPTIM_ICR_output_ARROKCF_Msk = 0x10
	// Bit ARROKCF.
	LPTIM_ICR_output_ARROKCF = 0x10
	// Position of CMP1OKCF field.
	LPTIM_ICR_output_CMP1OKCF_Pos = 0x3
	// Bit mask of CMP1OKCF field.
	LPTIM_ICR_output_CMP1OKCF_Msk = 0x8
	// Bit CMP1OKCF.
	LPTIM_ICR_output_CMP1OKCF = 0x8
	// Position of EXTTRIGCF field.
	LPTIM_ICR_output_EXTTRIGCF_Pos = 0x2
	// Bit mask of EXTTRIGCF field.
	LPTIM_ICR_output_EXTTRIGCF_Msk = 0x4
	// Bit EXTTRIGCF.
	LPTIM_ICR_output_EXTTRIGCF = 0x4
	// Position of ARRMCF field.
	LPTIM_ICR_output_ARRMCF_Pos = 0x1
	// Bit mask of ARRMCF field.
	LPTIM_ICR_output_ARRMCF_Msk = 0x2
	// Bit ARRMCF.
	LPTIM_ICR_output_ARRMCF = 0x2
	// Position of CC1IF field.
	LPTIM_ICR_output_CC1IF_Pos = 0x0
	// Bit mask of CC1IF field.
	LPTIM_ICR_output_CC1IF_Msk = 0x1
	// Bit CC1IF.
	LPTIM_ICR_output_CC1IF = 0x1

	// ICR_input: Interrupt Clear Register (intput mode)
	// Position of DIEROKCF field.
	LPTIM_ICR_input_DIEROKCF_Pos = 0x18
	// Bit mask of DIEROKCF field.
	LPTIM_ICR_input_DIEROKCF_Msk = 0x1000000
	// Bit DIEROKCF.
	LPTIM_ICR_input_DIEROKCF = 0x1000000
	// Position of CC2OCF field.
	LPTIM_ICR_input_CC2OCF_Pos = 0xd
	// Bit mask of CC2OCF field.
	LPTIM_ICR_input_CC2OCF_Msk = 0x2000
	// Bit CC2OCF.
	LPTIM_ICR_input_CC2OCF = 0x2000
	// Position of CC1OCF field.
	LPTIM_ICR_input_CC1OCF_Pos = 0xc
	// Bit mask of CC1OCF field.
	LPTIM_ICR_input_CC1OCF_Msk = 0x1000
	// Bit CC1OCF.
	LPTIM_ICR_input_CC1OCF = 0x1000
	// Position of CC2CF field.
	LPTIM_ICR_input_CC2CF_Pos = 0x9
	// Bit mask of CC2CF field.
	LPTIM_ICR_input_CC2CF_Msk = 0x200
	// Bit CC2CF.
	LPTIM_ICR_input_CC2CF = 0x200
	// Position of REPOKCF field.
	LPTIM_ICR_input_REPOKCF_Pos = 0x8
	// Bit mask of REPOKCF field.
	LPTIM_ICR_input_REPOKCF_Msk = 0x100
	// Bit REPOKCF.
	LPTIM_ICR_input_REPOKCF = 0x100
	// Position of UECF field.
	LPTIM_ICR_input_UECF_Pos = 0x7
	// Bit mask of UECF field.
	LPTIM_ICR_input_UECF_Msk = 0x80
	// Bit UECF.
	LPTIM_ICR_input_UECF = 0x80
	// Position of DOWNCF field.
	LPTIM_ICR_input_DOWNCF_Pos = 0x6
	// Bit mask of DOWNCF field.
	LPTIM_ICR_input_DOWNCF_Msk = 0x40
	// Bit DOWNCF.
	LPTIM_ICR_input_DOWNCF = 0x40
	// Position of UPCF field.
	LPTIM_ICR_input_UPCF_Pos = 0x5
	// Bit mask of UPCF field.
	LPTIM_ICR_input_UPCF_Msk = 0x20
	// Bit UPCF.
	LPTIM_ICR_input_UPCF = 0x20
	// Position of ARROKCF field.
	LPTIM_ICR_input_ARROKCF_Pos = 0x4
	// Bit mask of ARROKCF field.
	LPTIM_ICR_input_ARROKCF_Msk = 0x10
	// Bit ARROKCF.
	LPTIM_ICR_input_ARROKCF = 0x10
	// Position of EXTTRIGCF field.
	LPTIM_ICR_input_EXTTRIGCF_Pos = 0x2
	// Bit mask of EXTTRIGCF field.
	LPTIM_ICR_input_EXTTRIGCF_Msk = 0x4
	// Bit EXTTRIGCF.
	LPTIM_ICR_input_EXTTRIGCF = 0x4
	// Position of ARRMCF field.
	LPTIM_ICR_input_ARRMCF_Pos = 0x1
	// Bit mask of ARRMCF field.
	LPTIM_ICR_input_ARRMCF_Msk = 0x2
	// Bit ARRMCF.
	LPTIM_ICR_input_ARRMCF = 0x2
	// Position of CC1IF field.
	LPTIM_ICR_input_CC1IF_Pos = 0x0
	// Bit mask of CC1IF field.
	LPTIM_ICR_input_CC1IF_Msk = 0x1
	// Bit CC1IF.
	LPTIM_ICR_input_CC1IF = 0x1

	// DIER_output: LPTIM interrupt Enable Register (output mode)
	// Position of UEDE field.
	LPTIM_DIER_output_UEDE_Pos = 0x17
	// Bit mask of UEDE field.
	LPTIM_DIER_output_UEDE_Msk = 0x800000
	// Bit UEDE.
	LPTIM_DIER_output_UEDE = 0x800000
	// Position of CMP2OKIE field.
	LPTIM_DIER_output_CMP2OKIE_Pos = 0x13
	// Bit mask of CMP2OKIE field.
	LPTIM_DIER_output_CMP2OKIE_Msk = 0x80000
	// Bit CMP2OKIE.
	LPTIM_DIER_output_CMP2OKIE = 0x80000
	// Position of CC2IE field.
	LPTIM_DIER_output_CC2IE_Pos = 0x9
	// Bit mask of CC2IE field.
	LPTIM_DIER_output_CC2IE_Msk = 0x200
	// Bit CC2IE.
	LPTIM_DIER_output_CC2IE = 0x200
	// Position of REPOKIE field.
	LPTIM_DIER_output_REPOKIE_Pos = 0x8
	// Bit mask of REPOKIE field.
	LPTIM_DIER_output_REPOKIE_Msk = 0x100
	// Bit REPOKIE.
	LPTIM_DIER_output_REPOKIE = 0x100
	// Position of UEIE field.
	LPTIM_DIER_output_UEIE_Pos = 0x7
	// Bit mask of UEIE field.
	LPTIM_DIER_output_UEIE_Msk = 0x80
	// Bit UEIE.
	LPTIM_DIER_output_UEIE = 0x80
	// Position of DOWNIE field.
	LPTIM_DIER_output_DOWNIE_Pos = 0x6
	// Bit mask of DOWNIE field.
	LPTIM_DIER_output_DOWNIE_Msk = 0x40
	// Bit DOWNIE.
	LPTIM_DIER_output_DOWNIE = 0x40
	// Position of UPIE field.
	LPTIM_DIER_output_UPIE_Pos = 0x5
	// Bit mask of UPIE field.
	LPTIM_DIER_output_UPIE_Msk = 0x20
	// Bit UPIE.
	LPTIM_DIER_output_UPIE = 0x20
	// Position of ARROKIE field.
	LPTIM_DIER_output_ARROKIE_Pos = 0x4
	// Bit mask of ARROKIE field.
	LPTIM_DIER_output_ARROKIE_Msk = 0x10
	// Bit ARROKIE.
	LPTIM_DIER_output_ARROKIE = 0x10
	// Position of CMP1OKIE field.
	LPTIM_DIER_output_CMP1OKIE_Pos = 0x3
	// Bit mask of CMP1OKIE field.
	LPTIM_DIER_output_CMP1OKIE_Msk = 0x8
	// Bit CMP1OKIE.
	LPTIM_DIER_output_CMP1OKIE = 0x8
	// Position of EXTTRIGIE field.
	LPTIM_DIER_output_EXTTRIGIE_Pos = 0x2
	// Bit mask of EXTTRIGIE field.
	LPTIM_DIER_output_EXTTRIGIE_Msk = 0x4
	// Bit EXTTRIGIE.
	LPTIM_DIER_output_EXTTRIGIE = 0x4
	// Position of ARRMIE field.
	LPTIM_DIER_output_ARRMIE_Pos = 0x1
	// Bit mask of ARRMIE field.
	LPTIM_DIER_output_ARRMIE_Msk = 0x2
	// Bit ARRMIE.
	LPTIM_DIER_output_ARRMIE = 0x2
	// Position of CC1IF field.
	LPTIM_DIER_output_CC1IF_Pos = 0x0
	// Bit mask of CC1IF field.
	LPTIM_DIER_output_CC1IF_Msk = 0x1
	// Bit CC1IF.
	LPTIM_DIER_output_CC1IF = 0x1

	// DIER_input: LPTIM interrupt Enable Register (intput mode)
	// Position of CC2DE field.
	LPTIM_DIER_input_CC2DE_Pos = 0x19
	// Bit mask of CC2DE field.
	LPTIM_DIER_input_CC2DE_Msk = 0x2000000
	// Bit CC2DE.
	LPTIM_DIER_input_CC2DE = 0x2000000
	// Position of CC1DE field.
	LPTIM_DIER_input_CC1DE_Pos = 0x10
	// Bit mask of CC1DE field.
	LPTIM_DIER_input_CC1DE_Msk = 0x10000
	// Bit CC1DE.
	LPTIM_DIER_input_CC1DE = 0x10000
	// Position of CC2OIE field.
	LPTIM_DIER_input_CC2OIE_Pos = 0xd
	// Bit mask of CC2OIE field.
	LPTIM_DIER_input_CC2OIE_Msk = 0x2000
	// Bit CC2OIE.
	LPTIM_DIER_input_CC2OIE = 0x2000
	// Position of CC1OIE field.
	LPTIM_DIER_input_CC1OIE_Pos = 0xc
	// Bit mask of CC1OIE field.
	LPTIM_DIER_input_CC1OIE_Msk = 0x1000
	// Bit CC1OIE.
	LPTIM_DIER_input_CC1OIE = 0x1000
	// Position of CC2IE field.
	LPTIM_DIER_input_CC2IE_Pos = 0x9
	// Bit mask of CC2IE field.
	LPTIM_DIER_input_CC2IE_Msk = 0x200
	// Bit CC2IE.
	LPTIM_DIER_input_CC2IE = 0x200
	// Position of REPOKIE field.
	LPTIM_DIER_input_REPOKIE_Pos = 0x8
	// Bit mask of REPOKIE field.
	LPTIM_DIER_input_REPOKIE_Msk = 0x100
	// Bit REPOKIE.
	LPTIM_DIER_input_REPOKIE = 0x100
	// Position of UEIE field.
	LPTIM_DIER_input_UEIE_Pos = 0x7
	// Bit mask of UEIE field.
	LPTIM_DIER_input_UEIE_Msk = 0x80
	// Bit UEIE.
	LPTIM_DIER_input_UEIE = 0x80
	// Position of DOWNIE field.
	LPTIM_DIER_input_DOWNIE_Pos = 0x6
	// Bit mask of DOWNIE field.
	LPTIM_DIER_input_DOWNIE_Msk = 0x40
	// Bit DOWNIE.
	LPTIM_DIER_input_DOWNIE = 0x40
	// Position of UPIE field.
	LPTIM_DIER_input_UPIE_Pos = 0x5
	// Bit mask of UPIE field.
	LPTIM_DIER_input_UPIE_Msk = 0x20
	// Bit UPIE.
	LPTIM_DIER_input_UPIE = 0x20
	// Position of ARROKIE field.
	LPTIM_DIER_input_ARROKIE_Pos = 0x4
	// Bit mask of ARROKIE field.
	LPTIM_DIER_input_ARROKIE_Msk = 0x10
	// Bit ARROKIE.
	LPTIM_DIER_input_ARROKIE = 0x10
	// Position of EXTTRIGIE field.
	LPTIM_DIER_input_EXTTRIGIE_Pos = 0x2
	// Bit mask of EXTTRIGIE field.
	LPTIM_DIER_input_EXTTRIGIE_Msk = 0x4
	// Bit EXTTRIGIE.
	LPTIM_DIER_input_EXTTRIGIE = 0x4
	// Position of ARRMIE field.
	LPTIM_DIER_input_ARRMIE_Pos = 0x1
	// Bit mask of ARRMIE field.
	LPTIM_DIER_input_ARRMIE_Msk = 0x2
	// Bit ARRMIE.
	LPTIM_DIER_input_ARRMIE = 0x2
	// Position of CC1IF field.
	LPTIM_DIER_input_CC1IF_Pos = 0x0
	// Bit mask of CC1IF field.
	LPTIM_DIER_input_CC1IF_Msk = 0x1
	// Bit CC1IF.
	LPTIM_DIER_input_CC1IF = 0x1

	// CFGR: Configuration Register
	// Position of ENC field.
	LPTIM_CFGR_ENC_Pos = 0x18
	// Bit mask of ENC field.
	LPTIM_CFGR_ENC_Msk = 0x1000000
	// Bit ENC.
	LPTIM_CFGR_ENC = 0x1000000
	// Position of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Pos = 0x17
	// Bit mask of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Msk = 0x800000
	// Bit COUNTMODE.
	LPTIM_CFGR_COUNTMODE = 0x800000
	// Position of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Pos = 0x16
	// Bit mask of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Msk = 0x400000
	// Bit PRELOAD.
	LPTIM_CFGR_PRELOAD = 0x400000
	// Position of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Pos = 0x15
	// Bit mask of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Msk = 0x200000
	// Bit WAVPOL.
	LPTIM_CFGR_WAVPOL = 0x200000
	// Position of WAVE field.
	LPTIM_CFGR_WAVE_Pos = 0x14
	// Bit mask of WAVE field.
	LPTIM_CFGR_WAVE_Msk = 0x100000
	// Bit WAVE.
	LPTIM_CFGR_WAVE = 0x100000
	// Position of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Pos = 0x13
	// Bit mask of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Msk = 0x80000
	// Bit TIMOUT.
	LPTIM_CFGR_TIMOUT = 0x80000
	// Position of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Pos = 0x11
	// Bit mask of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Msk = 0x60000
	// Position of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Pos = 0xd
	// Bit mask of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Msk = 0xe000
	// Position of PRESC field.
	LPTIM_CFGR_PRESC_Pos = 0x9
	// Bit mask of PRESC field.
	LPTIM_CFGR_PRESC_Msk = 0xe00
	// Position of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Pos = 0x6
	// Bit mask of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Msk = 0xc0
	// Position of CKFLT field.
	LPTIM_CFGR_CKFLT_Pos = 0x3
	// Bit mask of CKFLT field.
	LPTIM_CFGR_CKFLT_Msk = 0x18
	// Position of CKPOL field.
	LPTIM_CFGR_CKPOL_Pos = 0x1
	// Bit mask of CKPOL field.
	LPTIM_CFGR_CKPOL_Msk = 0x6
	// Position of CKSEL field.
	LPTIM_CFGR_CKSEL_Pos = 0x0
	// Bit mask of CKSEL field.
	LPTIM_CFGR_CKSEL_Msk = 0x1
	// Bit CKSEL.
	LPTIM_CFGR_CKSEL = 0x1

	// CR: Control Register
	// Position of RSTARE field.
	LPTIM_CR_RSTARE_Pos = 0x4
	// Bit mask of RSTARE field.
	LPTIM_CR_RSTARE_Msk = 0x10
	// Bit RSTARE.
	LPTIM_CR_RSTARE = 0x10
	// Position of COUNTRST field.
	LPTIM_CR_COUNTRST_Pos = 0x3
	// Bit mask of COUNTRST field.
	LPTIM_CR_COUNTRST_Msk = 0x8
	// Bit COUNTRST.
	LPTIM_CR_COUNTRST = 0x8
	// Position of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Pos = 0x2
	// Bit mask of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Msk = 0x4
	// Bit CNTSTRT.
	LPTIM_CR_CNTSTRT = 0x4
	// Position of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Pos = 0x1
	// Bit mask of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Msk = 0x2
	// Bit SNGSTRT.
	LPTIM_CR_SNGSTRT = 0x2
	// Position of ENABLE field.
	LPTIM_CR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	LPTIM_CR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	LPTIM_CR_ENABLE = 0x1

	// CCR1: Compare Register
	// Position of CCR1 field.
	LPTIM_CCR1_CCR1_Pos = 0x0
	// Bit mask of CCR1 field.
	LPTIM_CCR1_CCR1_Msk = 0xffff

	// ARR: Autoreload Register
	// Position of ARR field.
	LPTIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	LPTIM_ARR_ARR_Msk = 0xffff

	// CNT: Counter Register
	// Position of CNT field.
	LPTIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	LPTIM_CNT_CNT_Msk = 0xffff

	// CFGR2: LPTIM configuration register 2
	// Position of IC2SEL field.
	LPTIM_CFGR2_IC2SEL_Pos = 0x14
	// Bit mask of IC2SEL field.
	LPTIM_CFGR2_IC2SEL_Msk = 0x300000
	// Position of IC1SEL field.
	LPTIM_CFGR2_IC1SEL_Pos = 0x10
	// Bit mask of IC1SEL field.
	LPTIM_CFGR2_IC1SEL_Msk = 0x30000
	// Position of IN2SEL field.
	LPTIM_CFGR2_IN2SEL_Pos = 0x4
	// Bit mask of IN2SEL field.
	LPTIM_CFGR2_IN2SEL_Msk = 0x30
	// Position of IN1SEL field.
	LPTIM_CFGR2_IN1SEL_Pos = 0x0
	// Bit mask of IN1SEL field.
	LPTIM_CFGR2_IN1SEL_Msk = 0x3

	// RCR: LPTIM repetition register
	// Position of REP field.
	LPTIM_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	LPTIM_RCR_REP_Msk = 0xff

	// CCMR1: LPTIM capture/compare mode register 1
	// Position of CC1SEL field.
	LPTIM_CCMR1_CC1SEL_Pos = 0x0
	// Bit mask of CC1SEL field.
	LPTIM_CCMR1_CC1SEL_Msk = 0x1
	// Bit CC1SEL.
	LPTIM_CCMR1_CC1SEL = 0x1
	// Position of CC1E field.
	LPTIM_CCMR1_CC1E_Pos = 0x1
	// Bit mask of CC1E field.
	LPTIM_CCMR1_CC1E_Msk = 0x2
	// Bit CC1E.
	LPTIM_CCMR1_CC1E = 0x2
	// Position of CC1P field.
	LPTIM_CCMR1_CC1P_Pos = 0x2
	// Bit mask of CC1P field.
	LPTIM_CCMR1_CC1P_Msk = 0xc
	// Position of IC1PSC field.
	LPTIM_CCMR1_IC1PSC_Pos = 0x8
	// Bit mask of IC1PSC field.
	LPTIM_CCMR1_IC1PSC_Msk = 0x300
	// Position of IC1F field.
	LPTIM_CCMR1_IC1F_Pos = 0xc
	// Bit mask of IC1F field.
	LPTIM_CCMR1_IC1F_Msk = 0x3000
	// Position of CC2SEL field.
	LPTIM_CCMR1_CC2SEL_Pos = 0x10
	// Bit mask of CC2SEL field.
	LPTIM_CCMR1_CC2SEL_Msk = 0x10000
	// Bit CC2SEL.
	LPTIM_CCMR1_CC2SEL = 0x10000
	// Position of CC2E field.
	LPTIM_CCMR1_CC2E_Pos = 0x11
	// Bit mask of CC2E field.
	LPTIM_CCMR1_CC2E_Msk = 0x20000
	// Bit CC2E.
	LPTIM_CCMR1_CC2E = 0x20000
	// Position of CC2P field.
	LPTIM_CCMR1_CC2P_Pos = 0x12
	// Bit mask of CC2P field.
	LPTIM_CCMR1_CC2P_Msk = 0xc0000
	// Position of IC2PSC field.
	LPTIM_CCMR1_IC2PSC_Pos = 0x18
	// Bit mask of IC2PSC field.
	LPTIM_CCMR1_IC2PSC_Msk = 0x3000000
	// Position of IC2F field.
	LPTIM_CCMR1_IC2F_Pos = 0x1c
	// Bit mask of IC2F field.
	LPTIM_CCMR1_IC2F_Msk = 0x30000000

	// CCR2: LPTIM Compare Register 2
	// Position of CCR2 field.
	LPTIM_CCR2_CCR2_Pos = 0x0
	// Bit mask of CCR2 field.
	LPTIM_CCR2_CCR2_Msk = 0xffff
)

// Constants for LPUART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	// Position of RXFFIE field.
	LPUART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	LPUART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	LPUART_CR1_RXFFIE = 0x80000000
	// Position of TXFEIE field.
	LPUART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	LPUART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	LPUART_CR1_TXFEIE = 0x40000000
	// Position of FIFOEN field.
	LPUART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	LPUART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	LPUART_CR1_FIFOEN = 0x20000000
	// Position of M1 field.
	LPUART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	LPUART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	LPUART_CR1_M1 = 0x10000000
	// Position of DEAT field.
	LPUART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	LPUART_CR1_DEAT_Msk = 0x3e00000
	// Position of DEDT field.
	LPUART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	LPUART_CR1_DEDT_Msk = 0x1f0000
	// Position of CMIE field.
	LPUART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	LPUART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	LPUART_CR1_CMIE = 0x4000
	// Position of MME field.
	LPUART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	LPUART_CR1_MME_Msk = 0x2000
	// Bit MME.
	LPUART_CR1_MME = 0x2000
	// Position of M0 field.
	LPUART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	LPUART_CR1_M0_Msk = 0x1000
	// Bit M0.
	LPUART_CR1_M0 = 0x1000
	// Position of WAKE field.
	LPUART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	LPUART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	LPUART_CR1_WAKE = 0x800
	// Position of PCE field.
	LPUART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	LPUART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	LPUART_CR1_PCE = 0x400
	// Position of PS field.
	LPUART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	LPUART_CR1_PS_Msk = 0x200
	// Bit PS.
	LPUART_CR1_PS = 0x200
	// Position of PEIE field.
	LPUART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	LPUART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	LPUART_CR1_PEIE = 0x100
	// Position of TXEIE field.
	LPUART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	LPUART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	LPUART_CR1_TXEIE = 0x80
	// Position of TCIE field.
	LPUART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	LPUART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	LPUART_CR1_TCIE = 0x40
	// Position of RXNEIE field.
	LPUART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	LPUART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	LPUART_CR1_RXNEIE = 0x20
	// Position of IDLEIE field.
	LPUART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	LPUART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	LPUART_CR1_IDLEIE = 0x10
	// Position of TE field.
	LPUART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	LPUART_CR1_TE_Msk = 0x8
	// Bit TE.
	LPUART_CR1_TE = 0x8
	// Position of RE field.
	LPUART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	LPUART_CR1_RE_Msk = 0x4
	// Bit RE.
	LPUART_CR1_RE = 0x4
	// Position of UESM field.
	LPUART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	LPUART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	LPUART_CR1_UESM = 0x2
	// Position of UE field.
	LPUART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	LPUART_CR1_UE_Msk = 0x1
	// Bit UE.
	LPUART_CR1_UE = 0x1

	// CR2: Control register 2
	// Position of ADD field.
	LPUART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	LPUART_CR2_ADD_Msk = 0xff000000
	// Position of MSBFIRST field.
	LPUART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	LPUART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	LPUART_CR2_MSBFIRST = 0x80000
	// Position of DATAINV field.
	LPUART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	LPUART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	LPUART_CR2_DATAINV = 0x40000
	// Position of TXINV field.
	LPUART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	LPUART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	LPUART_CR2_TXINV = 0x20000
	// Position of RXINV field.
	LPUART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	LPUART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	LPUART_CR2_RXINV = 0x10000
	// Position of SWAP field.
	LPUART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	LPUART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	LPUART_CR2_SWAP = 0x8000
	// Position of STOP field.
	LPUART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	LPUART_CR2_STOP_Msk = 0x3000
	// Position of ADDM7 field.
	LPUART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	LPUART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	LPUART_CR2_ADDM7 = 0x10

	// CR3: Control register 3
	// Position of TXFTCFG field.
	LPUART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	LPUART_CR3_TXFTCFG_Msk = 0xe0000000
	// Position of RXFTIE field.
	LPUART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	LPUART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	LPUART_CR3_RXFTIE = 0x10000000
	// Position of RXFTCFG field.
	LPUART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	LPUART_CR3_RXFTCFG_Msk = 0xe000000
	// Position of TXFTIE field.
	LPUART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	LPUART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	LPUART_CR3_TXFTIE = 0x800000
	// Position of DEP field.
	LPUART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	LPUART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	LPUART_CR3_DEP = 0x8000
	// Position of DEM field.
	LPUART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	LPUART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	LPUART_CR3_DEM = 0x4000
	// Position of DDRE field.
	LPUART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	LPUART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	LPUART_CR3_DDRE = 0x2000
	// Position of OVRDIS field.
	LPUART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	LPUART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	LPUART_CR3_OVRDIS = 0x1000
	// Position of CTSIE field.
	LPUART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	LPUART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	LPUART_CR3_CTSIE = 0x400
	// Position of CTSE field.
	LPUART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	LPUART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	LPUART_CR3_CTSE = 0x200
	// Position of RTSE field.
	LPUART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	LPUART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	LPUART_CR3_RTSE = 0x100
	// Position of DMAT field.
	LPUART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	LPUART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	LPUART_CR3_DMAT = 0x80
	// Position of DMAR field.
	LPUART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	LPUART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	LPUART_CR3_DMAR = 0x40
	// Position of HDSEL field.
	LPUART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	LPUART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	LPUART_CR3_HDSEL = 0x8
	// Position of EIE field.
	LPUART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	LPUART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	LPUART_CR3_EIE = 0x1

	// BRR: Baud rate register
	// Position of BRR field.
	LPUART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	LPUART_BRR_BRR_Msk = 0xfffff

	// RQR: Request register
	// Position of TXFRQ field.
	LPUART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	LPUART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	LPUART_RQR_TXFRQ = 0x10
	// Position of RXFRQ field.
	LPUART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	LPUART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	LPUART_RQR_RXFRQ = 0x8
	// Position of MMRQ field.
	LPUART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	LPUART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	LPUART_RQR_MMRQ = 0x4
	// Position of SBKRQ field.
	LPUART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	LPUART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	LPUART_RQR_SBKRQ = 0x2

	// ISR: Interrupt and status register
	// Position of TXFT field.
	LPUART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	LPUART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	LPUART_ISR_TXFT = 0x8000000
	// Position of RXFT field.
	LPUART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	LPUART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	LPUART_ISR_RXFT = 0x4000000
	// Position of RXFF field.
	LPUART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	LPUART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	LPUART_ISR_RXFF = 0x1000000
	// Position of TXFF field.
	LPUART_ISR_TXFF_Pos = 0x17
	// Bit mask of TXFF field.
	LPUART_ISR_TXFF_Msk = 0x800000
	// Bit TXFF.
	LPUART_ISR_TXFF = 0x800000
	// Position of REACK field.
	LPUART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	LPUART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	LPUART_ISR_REACK = 0x400000
	// Position of TEACK field.
	LPUART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	LPUART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	LPUART_ISR_TEACK = 0x200000
	// Position of RWU field.
	LPUART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	LPUART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	LPUART_ISR_RWU = 0x80000
	// Position of SBKF field.
	LPUART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	LPUART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	LPUART_ISR_SBKF = 0x40000
	// Position of CMF field.
	LPUART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	LPUART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	LPUART_ISR_CMF = 0x20000
	// Position of BUSY field.
	LPUART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	LPUART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	LPUART_ISR_BUSY = 0x10000
	// Position of CTS field.
	LPUART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	LPUART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	LPUART_ISR_CTS = 0x400
	// Position of CTSIF field.
	LPUART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	LPUART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	LPUART_ISR_CTSIF = 0x200
	// Position of TXFNF field.
	LPUART_ISR_TXFNF_Pos = 0x7
	// Bit mask of TXFNF field.
	LPUART_ISR_TXFNF_Msk = 0x80
	// Bit TXFNF.
	LPUART_ISR_TXFNF = 0x80
	// Position of TC field.
	LPUART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	LPUART_ISR_TC_Msk = 0x40
	// Bit TC.
	LPUART_ISR_TC = 0x40
	// Position of RXFNE field.
	LPUART_ISR_RXFNE_Pos = 0x5
	// Bit mask of RXFNE field.
	LPUART_ISR_RXFNE_Msk = 0x20
	// Bit RXFNE.
	LPUART_ISR_RXFNE = 0x20
	// Position of IDLE field.
	LPUART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	LPUART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	LPUART_ISR_IDLE = 0x10
	// Position of ORE field.
	LPUART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	LPUART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	LPUART_ISR_ORE = 0x8
	// Position of NE field.
	LPUART_ISR_NE_Pos = 0x2
	// Bit mask of NE field.
	LPUART_ISR_NE_Msk = 0x4
	// Bit NE.
	LPUART_ISR_NE = 0x4
	// Position of FE field.
	LPUART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	LPUART_ISR_FE_Msk = 0x2
	// Bit FE.
	LPUART_ISR_FE = 0x2
	// Position of PE field.
	LPUART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	LPUART_ISR_PE_Msk = 0x1
	// Bit PE.
	LPUART_ISR_PE = 0x1

	// ICR: Interrupt flag clear register
	// Position of CMCF field.
	LPUART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	LPUART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	LPUART_ICR_CMCF = 0x20000
	// Position of CTSCF field.
	LPUART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	LPUART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	LPUART_ICR_CTSCF = 0x200
	// Position of TCCF field.
	LPUART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	LPUART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	LPUART_ICR_TCCF = 0x40
	// Position of IDLECF field.
	LPUART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	LPUART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	LPUART_ICR_IDLECF = 0x10
	// Position of ORECF field.
	LPUART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	LPUART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	LPUART_ICR_ORECF = 0x8
	// Position of NECF field.
	LPUART_ICR_NECF_Pos = 0x2
	// Bit mask of NECF field.
	LPUART_ICR_NECF_Msk = 0x4
	// Bit NECF.
	LPUART_ICR_NECF = 0x4
	// Position of FECF field.
	LPUART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	LPUART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	LPUART_ICR_FECF = 0x2
	// Position of PECF field.
	LPUART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	LPUART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	LPUART_ICR_PECF = 0x1

	// RDR: Receive data register
	// Position of RDR field.
	LPUART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	LPUART_RDR_RDR_Msk = 0x1ff

	// TDR: Transmit data register
	// Position of TDR field.
	LPUART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	LPUART_TDR_TDR_Msk = 0x1ff

	// PRESC: prescaler register
	// Position of PRESCALER field.
	LPUART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	LPUART_PRESC_PRESCALER_Msk = 0xf

	// AUTOCR: Autonomous mode control register
	// Position of TDN field.
	LPUART_AUTOCR_TDN_Pos = 0x0
	// Bit mask of TDN field.
	LPUART_AUTOCR_TDN_Msk = 0xffff
	// Position of TRIGPOL field.
	LPUART_AUTOCR_TRIGPOL_Pos = 0x10
	// Bit mask of TRIGPOL field.
	LPUART_AUTOCR_TRIGPOL_Msk = 0x10000
	// Bit TRIGPOL.
	LPUART_AUTOCR_TRIGPOL = 0x10000
	// Position of TRIGEN field.
	LPUART_AUTOCR_TRIGEN_Pos = 0x11
	// Bit mask of TRIGEN field.
	LPUART_AUTOCR_TRIGEN_Msk = 0x20000
	// Bit TRIGEN.
	LPUART_AUTOCR_TRIGEN = 0x20000
	// Position of IDLEDIS field.
	LPUART_AUTOCR_IDLEDIS_Pos = 0x12
	// Bit mask of IDLEDIS field.
	LPUART_AUTOCR_IDLEDIS_Msk = 0x40000
	// Bit IDLEDIS.
	LPUART_AUTOCR_IDLEDIS = 0x40000
	// Position of TRIGSEL field.
	LPUART_AUTOCR_TRIGSEL_Pos = 0x13
	// Bit mask of TRIGSEL field.
	LPUART_AUTOCR_TRIGSEL_Msk = 0x780000
)

// Constants for MDF1: Multi-function digital filter
const (
	// GCR: MDF global control register
	// Position of TRGO field.
	MDF_GCR_TRGO_Pos = 0x0
	// Bit mask of TRGO field.
	MDF_GCR_TRGO_Msk = 0x1
	// Bit TRGO.
	MDF_GCR_TRGO = 0x1
	// Position of ILVNB field.
	MDF_GCR_ILVNB_Pos = 0x4
	// Bit mask of ILVNB field.
	MDF_GCR_ILVNB_Msk = 0xf0

	// CKGCR: MDF clock generator control register
	// Position of CKGDEN field.
	MDF_CKGCR_CKGDEN_Pos = 0x0
	// Bit mask of CKGDEN field.
	MDF_CKGCR_CKGDEN_Msk = 0x1
	// Bit CKGDEN.
	MDF_CKGCR_CKGDEN = 0x1
	// Position of CCK0EN field.
	MDF_CKGCR_CCK0EN_Pos = 0x1
	// Bit mask of CCK0EN field.
	MDF_CKGCR_CCK0EN_Msk = 0x2
	// Bit CCK0EN.
	MDF_CKGCR_CCK0EN = 0x2
	// Position of CCK1EN field.
	MDF_CKGCR_CCK1EN_Pos = 0x2
	// Bit mask of CCK1EN field.
	MDF_CKGCR_CCK1EN_Msk = 0x4
	// Bit CCK1EN.
	MDF_CKGCR_CCK1EN = 0x4
	// Position of CKGMOD field.
	MDF_CKGCR_CKGMOD_Pos = 0x4
	// Bit mask of CKGMOD field.
	MDF_CKGCR_CKGMOD_Msk = 0x10
	// Bit CKGMOD.
	MDF_CKGCR_CKGMOD = 0x10
	// Position of CCK0DIR field.
	MDF_CKGCR_CCK0DIR_Pos = 0x5
	// Bit mask of CCK0DIR field.
	MDF_CKGCR_CCK0DIR_Msk = 0x20
	// Bit CCK0DIR.
	MDF_CKGCR_CCK0DIR = 0x20
	// Position of CCK1DIR field.
	MDF_CKGCR_CCK1DIR_Pos = 0x6
	// Bit mask of CCK1DIR field.
	MDF_CKGCR_CCK1DIR_Msk = 0x40
	// Bit CCK1DIR.
	MDF_CKGCR_CCK1DIR = 0x40
	// Position of TRGSENS field.
	MDF_CKGCR_TRGSENS_Pos = 0x8
	// Bit mask of TRGSENS field.
	MDF_CKGCR_TRGSENS_Msk = 0x100
	// Bit TRGSENS.
	MDF_CKGCR_TRGSENS = 0x100
	// Position of TRGSRC field.
	MDF_CKGCR_TRGSRC_Pos = 0xc
	// Bit mask of TRGSRC field.
	MDF_CKGCR_TRGSRC_Msk = 0xf000
	// Position of CCKDIV field.
	MDF_CKGCR_CCKDIV_Pos = 0x10
	// Bit mask of CCKDIV field.
	MDF_CKGCR_CCKDIV_Msk = 0xf0000
	// Position of PROCDIV field.
	MDF_CKGCR_PROCDIV_Pos = 0x18
	// Bit mask of PROCDIV field.
	MDF_CKGCR_PROCDIV_Msk = 0x7f000000
	// Position of CKGACTIVE field.
	MDF_CKGCR_CKGACTIVE_Pos = 0x1f
	// Bit mask of CKGACTIVE field.
	MDF_CKGCR_CKGACTIVE_Msk = 0x80000000
	// Bit CKGACTIVE.
	MDF_CKGCR_CKGACTIVE = 0x80000000

	// FLT.SITFCR: This register is used to control the serial interfaces (SITFx).
	// Position of SITFEN field.
	MDF_FLT_SITFCR_SITFEN_Pos = 0x0
	// Bit mask of SITFEN field.
	MDF_FLT_SITFCR_SITFEN_Msk = 0x1
	// Bit SITFEN.
	MDF_FLT_SITFCR_SITFEN = 0x1
	// Position of SCKSRC field.
	MDF_FLT_SITFCR_SCKSRC_Pos = 0x1
	// Bit mask of SCKSRC field.
	MDF_FLT_SITFCR_SCKSRC_Msk = 0x6
	// Position of SITFMOD field.
	MDF_FLT_SITFCR_SITFMOD_Pos = 0x4
	// Bit mask of SITFMOD field.
	MDF_FLT_SITFCR_SITFMOD_Msk = 0x30
	// Position of STH field.
	MDF_FLT_SITFCR_STH_Pos = 0x8
	// Bit mask of STH field.
	MDF_FLT_SITFCR_STH_Msk = 0x1f00
	// Position of SITFACTIVE field.
	MDF_FLT_SITFCR_SITFACTIVE_Pos = 0x1f
	// Bit mask of SITFACTIVE field.
	MDF_FLT_SITFCR_SITFACTIVE_Msk = 0x80000000
	// Bit SITFACTIVE.
	MDF_FLT_SITFCR_SITFACTIVE = 0x80000000

	// FLT.BSMXCR: This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD.
	// Position of BSSEL field.
	MDF_FLT_BSMXCR_BSSEL_Pos = 0x0
	// Bit mask of BSSEL field.
	MDF_FLT_BSMXCR_BSSEL_Msk = 0x1f
	// Position of BSMXACTIVE field.
	MDF_FLT_BSMXCR_BSMXACTIVE_Pos = 0x1f
	// Bit mask of BSMXACTIVE field.
	MDF_FLT_BSMXCR_BSMXACTIVE_Msk = 0x80000000
	// Bit BSMXACTIVE.
	MDF_FLT_BSMXCR_BSMXACTIVE = 0x80000000

	// FLT.DFLTCR: This register is used to control the digital filter x.
	// Position of DFLTEN field.
	MDF_FLT_DFLTCR_DFLTEN_Pos = 0x0
	// Bit mask of DFLTEN field.
	MDF_FLT_DFLTCR_DFLTEN_Msk = 0x1
	// Bit DFLTEN.
	MDF_FLT_DFLTCR_DFLTEN = 0x1
	// Position of DMAEN field.
	MDF_FLT_DFLTCR_DMAEN_Pos = 0x1
	// Bit mask of DMAEN field.
	MDF_FLT_DFLTCR_DMAEN_Msk = 0x2
	// Bit DMAEN.
	MDF_FLT_DFLTCR_DMAEN = 0x2
	// Position of FTH field.
	MDF_FLT_DFLTCR_FTH_Pos = 0x2
	// Bit mask of FTH field.
	MDF_FLT_DFLTCR_FTH_Msk = 0x4
	// Bit FTH.
	MDF_FLT_DFLTCR_FTH = 0x4
	// Position of ACQMOD field.
	MDF_FLT_DFLTCR_ACQMOD_Pos = 0x4
	// Bit mask of ACQMOD field.
	MDF_FLT_DFLTCR_ACQMOD_Msk = 0x70
	// Position of TRGSENS field.
	MDF_FLT_DFLTCR_TRGSENS_Pos = 0x8
	// Bit mask of TRGSENS field.
	MDF_FLT_DFLTCR_TRGSENS_Msk = 0x100
	// Bit TRGSENS.
	MDF_FLT_DFLTCR_TRGSENS = 0x100
	// Position of TRGSRC field.
	MDF_FLT_DFLTCR_TRGSRC_Pos = 0xc
	// Bit mask of TRGSRC field.
	MDF_FLT_DFLTCR_TRGSRC_Msk = 0xf000
	// Position of SNPSFMT field.
	MDF_FLT_DFLTCR_SNPSFMT_Pos = 0x10
	// Bit mask of SNPSFMT field.
	MDF_FLT_DFLTCR_SNPSFMT_Msk = 0x10000
	// Bit SNPSFMT.
	MDF_FLT_DFLTCR_SNPSFMT = 0x10000
	// Position of NBDIS field.
	MDF_FLT_DFLTCR_NBDIS_Pos = 0x14
	// Bit mask of NBDIS field.
	MDF_FLT_DFLTCR_NBDIS_Msk = 0xff00000
	// Position of DFLTRUN field.
	MDF_FLT_DFLTCR_DFLTRUN_Pos = 0x1e
	// Bit mask of DFLTRUN field.
	MDF_FLT_DFLTCR_DFLTRUN_Msk = 0x40000000
	// Bit DFLTRUN.
	MDF_FLT_DFLTCR_DFLTRUN = 0x40000000
	// Position of DFLTACTIVE field.
	MDF_FLT_DFLTCR_DFLTACTIVE_Pos = 0x1f
	// Bit mask of DFLTACTIVE field.
	MDF_FLT_DFLTCR_DFLTACTIVE_Msk = 0x80000000
	// Bit DFLTACTIVE.
	MDF_FLT_DFLTCR_DFLTACTIVE = 0x80000000

	// FLT.DFLTCICR: This register is used to control the main CIC filter.
	// Position of DATSRC field.
	MDF_FLT_DFLTCICR_DATSRC_Pos = 0x0
	// Bit mask of DATSRC field.
	MDF_FLT_DFLTCICR_DATSRC_Msk = 0x3
	// Position of CICMOD field.
	MDF_FLT_DFLTCICR_CICMOD_Pos = 0x4
	// Bit mask of CICMOD field.
	MDF_FLT_DFLTCICR_CICMOD_Msk = 0x70
	// Position of MCICD field.
	MDF_FLT_DFLTCICR_MCICD_Pos = 0x8
	// Bit mask of MCICD field.
	MDF_FLT_DFLTCICR_MCICD_Msk = 0x1ff00
	// Position of SCALE field.
	MDF_FLT_DFLTCICR_SCALE_Pos = 0x14
	// Bit mask of SCALE field.
	MDF_FLT_DFLTCICR_SCALE_Msk = 0x3f00000

	// FLT.DFLTRSFR: This register is used to control the reshape and HPF filters.
	// Position of RSFLTBYP field.
	MDF_FLT_DFLTRSFR_RSFLTBYP_Pos = 0x0
	// Bit mask of RSFLTBYP field.
	MDF_FLT_DFLTRSFR_RSFLTBYP_Msk = 0x1
	// Bit RSFLTBYP.
	MDF_FLT_DFLTRSFR_RSFLTBYP = 0x1
	// Position of RSFLTD field.
	MDF_FLT_DFLTRSFR_RSFLTD_Pos = 0x4
	// Bit mask of RSFLTD field.
	MDF_FLT_DFLTRSFR_RSFLTD_Msk = 0x10
	// Bit RSFLTD.
	MDF_FLT_DFLTRSFR_RSFLTD = 0x10
	// Position of HPFBYP field.
	MDF_FLT_DFLTRSFR_HPFBYP_Pos = 0x7
	// Bit mask of HPFBYP field.
	MDF_FLT_DFLTRSFR_HPFBYP_Msk = 0x80
	// Bit HPFBYP.
	MDF_FLT_DFLTRSFR_HPFBYP = 0x80
	// Position of HPFC field.
	MDF_FLT_DFLTRSFR_HPFC_Pos = 0x8
	// Bit mask of HPFC field.
	MDF_FLT_DFLTRSFR_HPFC_Msk = 0x300

	// FLT.DFLTINTR: This register is used to the integrator (INT) settings.
	// Position of INTDIV field.
	MDF_FLT_DFLTINTR_INTDIV_Pos = 0x0
	// Bit mask of INTDIV field.
	MDF_FLT_DFLTINTR_INTDIV_Msk = 0x3
	// Position of INTVAL field.
	MDF_FLT_DFLTINTR_INTVAL_Pos = 0x4
	// Bit mask of INTVAL field.
	MDF_FLT_DFLTINTR_INTVAL_Msk = 0x7f0

	// FLT.OLDCR: This register is used to configure the Out-of Limit Detector function.
	// Position of OLDEN field.
	MDF_FLT_OLDCR_OLDEN_Pos = 0x0
	// Bit mask of OLDEN field.
	MDF_FLT_OLDCR_OLDEN_Msk = 0x1
	// Bit OLDEN.
	MDF_FLT_OLDCR_OLDEN = 0x1
	// Position of THINB field.
	MDF_FLT_OLDCR_THINB_Pos = 0x1
	// Bit mask of THINB field.
	MDF_FLT_OLDCR_THINB_Msk = 0x2
	// Bit THINB.
	MDF_FLT_OLDCR_THINB = 0x2
	// Position of BKOLD field.
	MDF_FLT_OLDCR_BKOLD_Pos = 0x4
	// Bit mask of BKOLD field.
	MDF_FLT_OLDCR_BKOLD_Msk = 0xf0
	// Position of ACICN field.
	MDF_FLT_OLDCR_ACICN_Pos = 0xc
	// Bit mask of ACICN field.
	MDF_FLT_OLDCR_ACICN_Msk = 0x3000
	// Position of ACICD field.
	MDF_FLT_OLDCR_ACICD_Pos = 0x11
	// Bit mask of ACICD field.
	MDF_FLT_OLDCR_ACICD_Msk = 0x3e0000
	// Position of OLDACTIVE field.
	MDF_FLT_OLDCR_OLDACTIVE_Pos = 0x1f
	// Bit mask of OLDACTIVE field.
	MDF_FLT_OLDCR_OLDACTIVE_Msk = 0x80000000
	// Bit OLDACTIVE.
	MDF_FLT_OLDCR_OLDACTIVE = 0x80000000

	// FLT.OLDTHLR: This register is used for the adjustment of the Out-off Limit low threshold.
	// Position of OLDTHL field.
	MDF_FLT_OLDTHLR_OLDTHL_Pos = 0x0
	// Bit mask of OLDTHL field.
	MDF_FLT_OLDTHLR_OLDTHL_Msk = 0x3ffffff

	// FLT.OLDTHHR: This register is used for the adjustment of the Out-off Limit high threshold.
	// Position of OLDTHH field.
	MDF_FLT_OLDTHHR_OLDTHH_Pos = 0x0
	// Bit mask of OLDTHH field.
	MDF_FLT_OLDTHHR_OLDTHH_Msk = 0x3ffffff

	// FLT.DLYCR: This register is used for the adjustment stream delays.
	// Position of SKPDLY field.
	MDF_FLT_DLYCR_SKPDLY_Pos = 0x0
	// Bit mask of SKPDLY field.
	MDF_FLT_DLYCR_SKPDLY_Msk = 0x7f
	// Position of SKPBF field.
	MDF_FLT_DLYCR_SKPBF_Pos = 0x1f
	// Bit mask of SKPBF field.
	MDF_FLT_DLYCR_SKPBF_Msk = 0x80000000
	// Bit SKPBF.
	MDF_FLT_DLYCR_SKPBF = 0x80000000

	// FLT.SCDCR: This register is used for the adjustment stream delays.
	// Position of SCDEN field.
	MDF_FLT_SCDCR_SCDEN_Pos = 0x0
	// Bit mask of SCDEN field.
	MDF_FLT_SCDCR_SCDEN_Msk = 0x1
	// Bit SCDEN.
	MDF_FLT_SCDCR_SCDEN = 0x1
	// Position of BKSCD field.
	MDF_FLT_SCDCR_BKSCD_Pos = 0x4
	// Bit mask of BKSCD field.
	MDF_FLT_SCDCR_BKSCD_Msk = 0xf0
	// Position of SCDT field.
	MDF_FLT_SCDCR_SCDT_Pos = 0xc
	// Bit mask of SCDT field.
	MDF_FLT_SCDCR_SCDT_Msk = 0xff000
	// Position of SCDACTIVE field.
	MDF_FLT_SCDCR_SCDACTIVE_Pos = 0x1f
	// Bit mask of SCDACTIVE field.
	MDF_FLT_SCDCR_SCDACTIVE_Msk = 0x80000000
	// Bit SCDACTIVE.
	MDF_FLT_SCDCR_SCDACTIVE = 0x80000000

	// FLT.DFLTIER: This register is used for allowing or not the events to generate an interrupt.
	// Position of FTHIE field.
	MDF_FLT_DFLTIER_FTHIE_Pos = 0x0
	// Bit mask of FTHIE field.
	MDF_FLT_DFLTIER_FTHIE_Msk = 0x1
	// Bit FTHIE.
	MDF_FLT_DFLTIER_FTHIE = 0x1
	// Position of DOVRIE field.
	MDF_FLT_DFLTIER_DOVRIE_Pos = 0x1
	// Bit mask of DOVRIE field.
	MDF_FLT_DFLTIER_DOVRIE_Msk = 0x2
	// Bit DOVRIE.
	MDF_FLT_DFLTIER_DOVRIE = 0x2
	// Position of SSDRIE field.
	MDF_FLT_DFLTIER_SSDRIE_Pos = 0x2
	// Bit mask of SSDRIE field.
	MDF_FLT_DFLTIER_SSDRIE_Msk = 0x4
	// Bit SSDRIE.
	MDF_FLT_DFLTIER_SSDRIE = 0x4
	// Position of OLDIE field.
	MDF_FLT_DFLTIER_OLDIE_Pos = 0x4
	// Bit mask of OLDIE field.
	MDF_FLT_DFLTIER_OLDIE_Msk = 0x10
	// Bit OLDIE.
	MDF_FLT_DFLTIER_OLDIE = 0x10
	// Position of SSOVRIE field.
	MDF_FLT_DFLTIER_SSOVRIE_Pos = 0x7
	// Bit mask of SSOVRIE field.
	MDF_FLT_DFLTIER_SSOVRIE_Msk = 0x80
	// Bit SSOVRIE.
	MDF_FLT_DFLTIER_SSOVRIE = 0x80
	// Position of SCDIE field.
	MDF_FLT_DFLTIER_SCDIE_Pos = 0x8
	// Bit mask of SCDIE field.
	MDF_FLT_DFLTIER_SCDIE_Msk = 0x100
	// Bit SCDIE.
	MDF_FLT_DFLTIER_SCDIE = 0x100
	// Position of SATIE field.
	MDF_FLT_DFLTIER_SATIE_Pos = 0x9
	// Bit mask of SATIE field.
	MDF_FLT_DFLTIER_SATIE_Msk = 0x200
	// Bit SATIE.
	MDF_FLT_DFLTIER_SATIE = 0x200
	// Position of CKABIE field.
	MDF_FLT_DFLTIER_CKABIE_Pos = 0xa
	// Bit mask of CKABIE field.
	MDF_FLT_DFLTIER_CKABIE_Msk = 0x400
	// Bit CKABIE.
	MDF_FLT_DFLTIER_CKABIE = 0x400
	// Position of RFOVRIE field.
	MDF_FLT_DFLTIER_RFOVRIE_Pos = 0xb
	// Bit mask of RFOVRIE field.
	MDF_FLT_DFLTIER_RFOVRIE_Msk = 0x800
	// Bit RFOVRIE.
	MDF_FLT_DFLTIER_RFOVRIE = 0x800

	// FLT.DFLTISR: MDF DFLT0 interrupt status register 0
	// Position of FTHF field.
	MDF_FLT_DFLTISR_FTHF_Pos = 0x0
	// Bit mask of FTHF field.
	MDF_FLT_DFLTISR_FTHF_Msk = 0x1
	// Bit FTHF.
	MDF_FLT_DFLTISR_FTHF = 0x1
	// Position of DOVRF field.
	MDF_FLT_DFLTISR_DOVRF_Pos = 0x1
	// Bit mask of DOVRF field.
	MDF_FLT_DFLTISR_DOVRF_Msk = 0x2
	// Bit DOVRF.
	MDF_FLT_DFLTISR_DOVRF = 0x2
	// Position of SSDRF field.
	MDF_FLT_DFLTISR_SSDRF_Pos = 0x2
	// Bit mask of SSDRF field.
	MDF_FLT_DFLTISR_SSDRF_Msk = 0x4
	// Bit SSDRF.
	MDF_FLT_DFLTISR_SSDRF = 0x4
	// Position of RXNEF field.
	MDF_FLT_DFLTISR_RXNEF_Pos = 0x3
	// Bit mask of RXNEF field.
	MDF_FLT_DFLTISR_RXNEF_Msk = 0x8
	// Bit RXNEF.
	MDF_FLT_DFLTISR_RXNEF = 0x8
	// Position of OLDF field.
	MDF_FLT_DFLTISR_OLDF_Pos = 0x4
	// Bit mask of OLDF field.
	MDF_FLT_DFLTISR_OLDF_Msk = 0x10
	// Bit OLDF.
	MDF_FLT_DFLTISR_OLDF = 0x10
	// Position of THLF field.
	MDF_FLT_DFLTISR_THLF_Pos = 0x5
	// Bit mask of THLF field.
	MDF_FLT_DFLTISR_THLF_Msk = 0x20
	// Bit THLF.
	MDF_FLT_DFLTISR_THLF = 0x20
	// Position of THHF field.
	MDF_FLT_DFLTISR_THHF_Pos = 0x6
	// Bit mask of THHF field.
	MDF_FLT_DFLTISR_THHF_Msk = 0x40
	// Bit THHF.
	MDF_FLT_DFLTISR_THHF = 0x40
	// Position of SSOVRF field.
	MDF_FLT_DFLTISR_SSOVRF_Pos = 0x7
	// Bit mask of SSOVRF field.
	MDF_FLT_DFLTISR_SSOVRF_Msk = 0x80
	// Bit SSOVRF.
	MDF_FLT_DFLTISR_SSOVRF = 0x80
	// Position of SCDF field.
	MDF_FLT_DFLTISR_SCDF_Pos = 0x8
	// Bit mask of SCDF field.
	MDF_FLT_DFLTISR_SCDF_Msk = 0x100
	// Bit SCDF.
	MDF_FLT_DFLTISR_SCDF = 0x100
	// Position of SATF field.
	MDF_FLT_DFLTISR_SATF_Pos = 0x9
	// Bit mask of SATF field.
	MDF_FLT_DFLTISR_SATF_Msk = 0x200
	// Bit SATF.
	MDF_FLT_DFLTISR_SATF = 0x200
	// Position of CKABF field.
	MDF_FLT_DFLTISR_CKABF_Pos = 0xa
	// Bit mask of CKABF field.
	MDF_FLT_DFLTISR_CKABF_Msk = 0x400
	// Bit CKABF.
	MDF_FLT_DFLTISR_CKABF = 0x400
	// Position of RFOVRF field.
	MDF_FLT_DFLTISR_RFOVRF_Pos = 0xb
	// Bit mask of RFOVRF field.
	MDF_FLT_DFLTISR_RFOVRF_Msk = 0x800
	// Bit RFOVRF.
	MDF_FLT_DFLTISR_RFOVRF = 0x800

	// FLT.OECCR: This register contains the offset compensation value.
	// Position of OFFSET field.
	MDF_FLT_OECCR_OFFSET_Pos = 0x0
	// Bit mask of OFFSET field.
	MDF_FLT_OECCR_OFFSET_Msk = 0x3ffffff

	// FLT.SNPSDR: This register is used to read the data processed by each digital filter in snapshot mode.
	// Position of MCICDC field.
	MDF_FLT_SNPSDR_MCICDC_Pos = 0x0
	// Bit mask of MCICDC field.
	MDF_FLT_SNPSDR_MCICDC_Msk = 0x1ff
	// Position of EXTSDR field.
	MDF_FLT_SNPSDR_EXTSDR_Pos = 0x9
	// Bit mask of EXTSDR field.
	MDF_FLT_SNPSDR_EXTSDR_Msk = 0xfe00
	// Position of SDR field.
	MDF_FLT_SNPSDR_SDR_Pos = 0x10
	// Bit mask of SDR field.
	MDF_FLT_SNPSDR_SDR_Msk = 0xffff0000

	// FLT.DFLTDR: This register is used to read the data processed by each digital filter.
	// Position of DR field.
	MDF_FLT_DFLTDR_DR_Pos = 0x8
	// Bit mask of DR field.
	MDF_FLT_DFLTDR_DR_Msk = 0xffffff00
)

// Constants for OCTOSPI1: OctoSPI
const (
	// CR: control register
	// Position of FMODE field.
	OctoSPI_CR_FMODE_Pos = 0x1c
	// Bit mask of FMODE field.
	OctoSPI_CR_FMODE_Msk = 0x30000000
	// Indirect-write mode
	OctoSPI_CR_FMODE_IndirectWrite = 0x0
	// Indirect-read mode
	OctoSPI_CR_FMODE_IndirectRead = 0x1
	// Automatic status-polling mode
	OctoSPI_CR_FMODE_AutomaticPolling = 0x2
	// Memory-mapped mode
	OctoSPI_CR_FMODE_MemoryMapped = 0x3
	// Position of PMM field.
	OctoSPI_CR_PMM_Pos = 0x17
	// Bit mask of PMM field.
	OctoSPI_CR_PMM_Msk = 0x800000
	// Bit PMM.
	OctoSPI_CR_PMM = 0x800000
	// AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register
	OctoSPI_CR_PMM_ANDMatchMode = 0x0
	// OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register
	OctoSPI_CR_PMM_ORMatchmode = 0x1
	// Position of APMS field.
	OctoSPI_CR_APMS_Pos = 0x16
	// Bit mask of APMS field.
	OctoSPI_CR_APMS_Msk = 0x400000
	// Bit APMS.
	OctoSPI_CR_APMS = 0x400000
	// Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI
	OctoSPI_CR_APMS_Running = 0x0
	// Automatic status-polling mode stops as soon as there is a match
	OctoSPI_CR_APMS_StopMatch = 0x1
	// Position of TEIE field.
	OctoSPI_CR_TEIE_Pos = 0x10
	// Bit mask of TEIE field.
	OctoSPI_CR_TEIE_Msk = 0x10000
	// Bit TEIE.
	OctoSPI_CR_TEIE = 0x10000
	// Interrupt disabled
	OctoSPI_CR_TEIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_TEIE_Enabled = 0x1
	// Position of TOIE field.
	OctoSPI_CR_TOIE_Pos = 0x14
	// Bit mask of TOIE field.
	OctoSPI_CR_TOIE_Msk = 0x100000
	// Bit TOIE.
	OctoSPI_CR_TOIE = 0x100000
	// Interrupt disabled
	OctoSPI_CR_TOIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_TOIE_Enabled = 0x1
	// Position of SMIE field.
	OctoSPI_CR_SMIE_Pos = 0x13
	// Bit mask of SMIE field.
	OctoSPI_CR_SMIE_Msk = 0x80000
	// Bit SMIE.
	OctoSPI_CR_SMIE = 0x80000
	// Interrupt disabled
	OctoSPI_CR_SMIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_SMIE_Enabled = 0x1
	// Position of FTIE field.
	OctoSPI_CR_FTIE_Pos = 0x12
	// Bit mask of FTIE field.
	OctoSPI_CR_FTIE_Msk = 0x40000
	// Bit FTIE.
	OctoSPI_CR_FTIE = 0x40000
	// Interrupt disabled
	OctoSPI_CR_FTIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_FTIE_Enabled = 0x1
	// Position of TCIE field.
	OctoSPI_CR_TCIE_Pos = 0x11
	// Bit mask of TCIE field.
	OctoSPI_CR_TCIE_Msk = 0x20000
	// Bit TCIE.
	OctoSPI_CR_TCIE = 0x20000
	// Interrupt disabled
	OctoSPI_CR_TCIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_TCIE_Enabled = 0x1
	// Position of FTHRES field.
	OctoSPI_CR_FTHRES_Pos = 0x8
	// Bit mask of FTHRES field.
	OctoSPI_CR_FTHRES_Msk = 0x1f00
	// Position of MSEL field.
	OctoSPI_CR_MSEL_Pos = 0x7
	// Bit mask of MSEL field.
	OctoSPI_CR_MSEL_Msk = 0x80
	// Bit MSEL.
	OctoSPI_CR_MSEL = 0x80
	// External memory 1 selected (data exchanged over IO[3:0])
	OctoSPI_CR_MSEL_EXT1 = 0x0
	// External memory 2 selected (data exchanged over IO[7:4])
	OctoSPI_CR_MSEL_EXT2 = 0x1
	// Position of DMM field.
	OctoSPI_CR_DMM_Pos = 0x6
	// Bit mask of DMM field.
	OctoSPI_CR_DMM_Msk = 0x40
	// Bit DMM.
	OctoSPI_CR_DMM = 0x40
	// Dual-memory configuration disabled
	OctoSPI_CR_DMM_Disabled = 0x0
	// Dual-memory configuration enabled
	OctoSPI_CR_DMM_Enabled = 0x1
	// Position of TCEN field.
	OctoSPI_CR_TCEN_Pos = 0x3
	// Bit mask of TCEN field.
	OctoSPI_CR_TCEN_Msk = 0x8
	// Bit TCEN.
	OctoSPI_CR_TCEN = 0x8
	// Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode
	OctoSPI_CR_TCEN_Disabled = 0x0
	// Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity
	OctoSPI_CR_TCEN_Enabled = 0x1
	// Position of DMAEN field.
	OctoSPI_CR_DMAEN_Pos = 0x2
	// Bit mask of DMAEN field.
	OctoSPI_CR_DMAEN_Msk = 0x4
	// Bit DMAEN.
	OctoSPI_CR_DMAEN = 0x4
	// DMA disabled for Indirect mode
	OctoSPI_CR_DMAEN_Disabled = 0x0
	// DMA enabled for Indirect mode
	OctoSPI_CR_DMAEN_Enabled = 0x1
	// Position of ABORT field.
	OctoSPI_CR_ABORT_Pos = 0x1
	// Bit mask of ABORT field.
	OctoSPI_CR_ABORT_Msk = 0x2
	// Bit ABORT.
	OctoSPI_CR_ABORT = 0x2
	// No abort requested
	OctoSPI_CR_ABORT_NotRequested = 0x0
	// Abort requested
	OctoSPI_CR_ABORT_Requested = 0x1
	// Position of EN field.
	OctoSPI_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	OctoSPI_CR_EN_Msk = 0x1
	// Bit EN.
	OctoSPI_CR_EN = 0x1
	// OCTOSPI disabled
	OctoSPI_CR_EN_Disabled = 0x0
	// OCTOSPI enabled
	OctoSPI_CR_EN_Enabled = 0x1

	// DCR1: device configuration register 1
	// Position of CKMODE field.
	OctoSPI_DCR1_CKMODE_Pos = 0x0
	// Bit mask of CKMODE field.
	OctoSPI_DCR1_CKMODE_Msk = 0x1
	// Bit CKMODE.
	OctoSPI_DCR1_CKMODE = 0x1
	// CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0
	OctoSPI_DCR1_CKMODE_Mode0 = 0x0
	// CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3
	OctoSPI_DCR1_CKMODE_Mode3 = 0x1
	// Position of FRCK field.
	OctoSPI_DCR1_FRCK_Pos = 0x1
	// Bit mask of FRCK field.
	OctoSPI_DCR1_FRCK_Msk = 0x2
	// Bit FRCK.
	OctoSPI_DCR1_FRCK = 0x2
	// CLK is not free running
	OctoSPI_DCR1_FRCK_Disabled = 0x0
	// CLK is free running (always provided)
	OctoSPI_DCR1_FRCK_Enabled = 0x1
	// Position of DLYBYP field.
	OctoSPI_DCR1_DLYBYP_Pos = 0x3
	// Bit mask of DLYBYP field.
	OctoSPI_DCR1_DLYBYP_Msk = 0x8
	// Bit DLYBYP.
	OctoSPI_DCR1_DLYBYP = 0x8
	// The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral)
	OctoSPI_DCR1_DLYBYP_DelayBlockEnabled = 0x0
	// The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block
	OctoSPI_DCR1_DLYBYP_DelayBlockBypassed = 0x1
	// Position of CSHT field.
	OctoSPI_DCR1_CSHT_Pos = 0x8
	// Bit mask of CSHT field.
	OctoSPI_DCR1_CSHT_Msk = 0x3f00
	// Position of DEVSIZE field.
	OctoSPI_DCR1_DEVSIZE_Pos = 0x10
	// Bit mask of DEVSIZE field.
	OctoSPI_DCR1_DEVSIZE_Msk = 0x1f0000
	// Position of MTYP field.
	OctoSPI_DCR1_MTYP_Pos = 0x18
	// Bit mask of MTYP field.
	OctoSPI_DCR1_MTYP_Msk = 0x7000000
	// Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes
	OctoSPI_DCR1_MTYP_MicronMode = 0x0
	// Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes
	OctoSPI_DCR1_MTYP_MacronixMode = 0x1
	// Standard Mode
	OctoSPI_DCR1_MTYP_StandardMode = 0x2
	// Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping
	OctoSPI_DCR1_MTYP_MacronixRamMode = 0x3
	// HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected
	OctoSPI_DCR1_MTYP_HyperBusMemoryMode = 0x4
	// HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used
	OctoSPI_DCR1_MTYP_HyperBusMode = 0x5

	// DCR2: device configuration register 2
	// Position of PRESCALER field.
	OctoSPI_DCR2_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	OctoSPI_DCR2_PRESCALER_Msk = 0xff
	// Position of WRAPSIZE field.
	OctoSPI_DCR2_WRAPSIZE_Pos = 0x10
	// Bit mask of WRAPSIZE field.
	OctoSPI_DCR2_WRAPSIZE_Msk = 0x70000
	// Wrapped reads are not supported by the memory
	OctoSPI_DCR2_WRAPSIZE_NoWrappingSupport = 0x0
	// External memory supports wrap size of 16 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize16 = 0x2
	// External memory supports wrap size of 32 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize32 = 0x3
	// External memory supports wrap size of 64 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize64 = 0x4
	// External memory supports wrap size of 128 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize128 = 0x5

	// DCR3: device configuration register 3
	// Position of MAXTRAN field.
	OctoSPI_DCR3_MAXTRAN_Pos = 0x0
	// Bit mask of MAXTRAN field.
	OctoSPI_DCR3_MAXTRAN_Msk = 0xff
	// Position of CSBOUND field.
	OctoSPI_DCR3_CSBOUND_Pos = 0x10
	// Bit mask of CSBOUND field.
	OctoSPI_DCR3_CSBOUND_Msk = 0x1f0000

	// DCR4: DCR4
	// Position of REFRESH field.
	OctoSPI_DCR4_REFRESH_Pos = 0x0
	// Bit mask of REFRESH field.
	OctoSPI_DCR4_REFRESH_Msk = 0xffffffff

	// SR: status register
	// Position of TEF field.
	OctoSPI_SR_TEF_Pos = 0x0
	// Bit mask of TEF field.
	OctoSPI_SR_TEF_Msk = 0x1
	// Bit TEF.
	OctoSPI_SR_TEF = 0x1
	// This bit is cleared by writing 1 to CTEF
	OctoSPI_SR_TEF_Cleared = 0x0
	// This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode
	OctoSPI_SR_TEF_InvalidAddressAccessed = 0x1
	// Position of TCF field.
	OctoSPI_SR_TCF_Pos = 0x1
	// Bit mask of TCF field.
	OctoSPI_SR_TCF_Msk = 0x2
	// Bit TCF.
	OctoSPI_SR_TCF = 0x2
	// This bit is cleared by writing 1 to CTCF
	OctoSPI_SR_TCF_Cleared = 0x0
	// This bit is set when the programmed number of data has been transferred
	OctoSPI_SR_TCF_TransferCompleted = 0x1
	// Position of FTF field.
	OctoSPI_SR_FTF_Pos = 0x2
	// Bit mask of FTF field.
	OctoSPI_SR_FTF_Msk = 0x4
	// Bit FTF.
	OctoSPI_SR_FTF = 0x4
	// It is cleared automatically as soon as the threshold condition is no longer true
	OctoSPI_SR_FTF_Cleared = 0x0
	// This bit is set when the FIFO threshold has been reached
	OctoSPI_SR_FTF_ThresholdReached = 0x1
	// Position of SMF field.
	OctoSPI_SR_SMF_Pos = 0x3
	// Bit mask of SMF field.
	OctoSPI_SR_SMF_Msk = 0x8
	// Bit SMF.
	OctoSPI_SR_SMF = 0x8
	// It is cleared by writing 1 to CSMF
	OctoSPI_SR_SMF_Cleared = 0x0
	// This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR)
	OctoSPI_SR_SMF_Matched = 0x1
	// Position of TOF field.
	OctoSPI_SR_TOF_Pos = 0x4
	// Bit mask of TOF field.
	OctoSPI_SR_TOF_Msk = 0x10
	// Bit TOF.
	OctoSPI_SR_TOF = 0x10
	// This bit is cleared by writing 1 to CTOF
	OctoSPI_SR_TOF_Cleared = 0x0
	// This bit is set when timeout occurs
	OctoSPI_SR_TOF_Timeout = 0x1
	// Position of BUSY field.
	OctoSPI_SR_BUSY_Pos = 0x5
	// Bit mask of BUSY field.
	OctoSPI_SR_BUSY_Msk = 0x20
	// Bit BUSY.
	OctoSPI_SR_BUSY = 0x20
	// This bit is cleared automatically when the operation with the external device is finished and the FIFO is empty
	OctoSPI_SR_BUSY_Cleared = 0x0
	// This bit is set when an operation is ongoing
	OctoSPI_SR_BUSY_Busy = 0x1
	// Position of FLEVEL field.
	OctoSPI_SR_FLEVEL_Pos = 0x8
	// Bit mask of FLEVEL field.
	OctoSPI_SR_FLEVEL_Msk = 0x3f00

	// FCR: flag clear register
	// Position of CTEF field.
	OctoSPI_FCR_CTEF_Pos = 0x0
	// Bit mask of CTEF field.
	OctoSPI_FCR_CTEF_Msk = 0x1
	// Bit CTEF.
	OctoSPI_FCR_CTEF = 0x1
	// Writing 1 clears the TEF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CTEF_Clear = 0x1
	// Position of CTCF field.
	OctoSPI_FCR_CTCF_Pos = 0x1
	// Bit mask of CTCF field.
	OctoSPI_FCR_CTCF_Msk = 0x2
	// Bit CTCF.
	OctoSPI_FCR_CTCF = 0x2
	// Writing 1 clears the TCF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CTCF_Clear = 0x1
	// Position of CSMF field.
	OctoSPI_FCR_CSMF_Pos = 0x3
	// Bit mask of CSMF field.
	OctoSPI_FCR_CSMF_Msk = 0x8
	// Bit CSMF.
	OctoSPI_FCR_CSMF = 0x8
	// Writing 1 clears the SMF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CSMF_Clear = 0x1
	// Position of CTOF field.
	OctoSPI_FCR_CTOF_Pos = 0x4
	// Bit mask of CTOF field.
	OctoSPI_FCR_CTOF_Msk = 0x10
	// Bit CTOF.
	OctoSPI_FCR_CTOF = 0x10
	// Writing 1 clears the TOF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CTOF_Clear = 0x1

	// DLR: data length register
	// Position of DL field.
	OctoSPI_DLR_DL_Pos = 0x0
	// Bit mask of DL field.
	OctoSPI_DLR_DL_Msk = 0xffffffff

	// AR: address register
	// Position of ADDRESS field.
	OctoSPI_AR_ADDRESS_Pos = 0x0
	// Bit mask of ADDRESS field.
	OctoSPI_AR_ADDRESS_Msk = 0xffffffff

	// DR: data register
	// Position of DATA field.
	OctoSPI_DR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	OctoSPI_DR_DATA_Msk = 0xffffffff

	// PSMKR: polling status mask register
	// Position of MASK field.
	OctoSPI_PSMKR_MASK_Pos = 0x0
	// Bit mask of MASK field.
	OctoSPI_PSMKR_MASK_Msk = 0xffffffff

	// PSMAR: polling status match register
	// Position of MATCH field.
	OctoSPI_PSMAR_MATCH_Pos = 0x0
	// Bit mask of MATCH field.
	OctoSPI_PSMAR_MATCH_Msk = 0xffffffff

	// PIR: polling interval register
	// Position of INTERVAL field.
	OctoSPI_PIR_INTERVAL_Pos = 0x0
	// Bit mask of INTERVAL field.
	OctoSPI_PIR_INTERVAL_Msk = 0xffff

	// CCR: communication configuration register
	// Position of IMODE field.
	OctoSPI_CCR_IMODE_Pos = 0x0
	// Bit mask of IMODE field.
	OctoSPI_CCR_IMODE_Msk = 0x7
	// No instruction
	OctoSPI_CCR_IMODE_NoInstruction = 0x0
	// Instruction on a single line
	OctoSPI_CCR_IMODE_SingleLine = 0x1
	// Instruction on two lines
	OctoSPI_CCR_IMODE_TwoLines = 0x2
	// Instruction on four lines
	OctoSPI_CCR_IMODE_FourLines = 0x3
	// Instruction on eight lines
	OctoSPI_CCR_IMODE_EightLines = 0x4
	// Position of IDTR field.
	OctoSPI_CCR_IDTR_Pos = 0x3
	// Bit mask of IDTR field.
	OctoSPI_CCR_IDTR_Msk = 0x8
	// Bit IDTR.
	OctoSPI_CCR_IDTR = 0x8
	// DTR mode disabled for instruction phase
	OctoSPI_CCR_IDTR_Disabled = 0x0
	// DTR mode enabled for instruction phase
	OctoSPI_CCR_IDTR_Enabled = 0x1
	// Position of ISIZE field.
	OctoSPI_CCR_ISIZE_Pos = 0x4
	// Bit mask of ISIZE field.
	OctoSPI_CCR_ISIZE_Msk = 0x30
	// 8-bit instruction
	OctoSPI_CCR_ISIZE_Bits8 = 0x0
	// 16-bit instruction
	OctoSPI_CCR_ISIZE_Bits16 = 0x1
	// 24-bit instruction
	OctoSPI_CCR_ISIZE_Bits24 = 0x2
	// 32-bit instruction
	OctoSPI_CCR_ISIZE_Bits32 = 0x3
	// Position of ADMODE field.
	OctoSPI_CCR_ADMODE_Pos = 0x8
	// Bit mask of ADMODE field.
	OctoSPI_CCR_ADMODE_Msk = 0x700
	// No address
	OctoSPI_CCR_ADMODE_NoAddress = 0x0
	// Address on a single line
	OctoSPI_CCR_ADMODE_SingleLine = 0x1
	// Address on two lines
	OctoSPI_CCR_ADMODE_TwoLines = 0x2
	// Address on four lines
	OctoSPI_CCR_ADMODE_FourLines = 0x3
	// Address on eight lines
	OctoSPI_CCR_ADMODE_EightLines = 0x4
	// Position of ADDTR field.
	OctoSPI_CCR_ADDTR_Pos = 0xb
	// Bit mask of ADDTR field.
	OctoSPI_CCR_ADDTR_Msk = 0x800
	// Bit ADDTR.
	OctoSPI_CCR_ADDTR = 0x800
	// DTR mode disabled for address phase
	OctoSPI_CCR_ADDTR_Disabled = 0x0
	// DTR mode enabled for address phase
	OctoSPI_CCR_ADDTR_Enabled = 0x1
	// Position of ADSIZE field.
	OctoSPI_CCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	OctoSPI_CCR_ADSIZE_Msk = 0x3000
	// 8-bit address
	OctoSPI_CCR_ADSIZE_Bits8 = 0x0
	// 16-bit address
	OctoSPI_CCR_ADSIZE_Bits16 = 0x1
	// 24-bit address
	OctoSPI_CCR_ADSIZE_Bits24 = 0x2
	// 32-bit address
	OctoSPI_CCR_ADSIZE_Bits32 = 0x3
	// Position of ABMODE field.
	OctoSPI_CCR_ABMODE_Pos = 0x10
	// Bit mask of ABMODE field.
	OctoSPI_CCR_ABMODE_Msk = 0x70000
	// No alternate bytes
	OctoSPI_CCR_ABMODE_NoAlternateBytes = 0x0
	// Alternate bytes on a single line
	OctoSPI_CCR_ABMODE_SingleLine = 0x1
	// Alternate bytes on two lines
	OctoSPI_CCR_ABMODE_TwoLines = 0x2
	// Alternate bytes on four lines
	OctoSPI_CCR_ABMODE_FourLines = 0x3
	// Alternate bytes on eight lines
	OctoSPI_CCR_ABMODE_EightLines = 0x4
	// Position of ABDTR field.
	OctoSPI_CCR_ABDTR_Pos = 0x13
	// Bit mask of ABDTR field.
	OctoSPI_CCR_ABDTR_Msk = 0x80000
	// Bit ABDTR.
	OctoSPI_CCR_ABDTR = 0x80000
	// DTR mode disabled for alternate bytes phase
	OctoSPI_CCR_ABDTR_Disabled = 0x0
	// DTR mode enabled for alternate bytes phase
	OctoSPI_CCR_ABDTR_Enabled = 0x1
	// Position of ABSIZE field.
	OctoSPI_CCR_ABSIZE_Pos = 0x14
	// Bit mask of ABSIZE field.
	OctoSPI_CCR_ABSIZE_Msk = 0x300000
	// 8-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits8 = 0x0
	// 16-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits16 = 0x1
	// 24-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits24 = 0x2
	// 32-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits32 = 0x3
	// Position of DMODE field.
	OctoSPI_CCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	OctoSPI_CCR_DMODE_Msk = 0x7000000
	// No data
	OctoSPI_CCR_DMODE_NoData = 0x0
	// Data on a single line
	OctoSPI_CCR_DMODE_SingleLine = 0x1
	// Data on two lines
	OctoSPI_CCR_DMODE_TwoLines = 0x2
	// Data on four lines
	OctoSPI_CCR_DMODE_FourLines = 0x3
	// Data on eight lines
	OctoSPI_CCR_DMODE_EightLines = 0x4
	// Position of DDTR field.
	OctoSPI_CCR_DDTR_Pos = 0x1b
	// Bit mask of DDTR field.
	OctoSPI_CCR_DDTR_Msk = 0x8000000
	// Bit DDTR.
	OctoSPI_CCR_DDTR = 0x8000000
	// DTR mode disabled for data phase
	OctoSPI_CCR_DDTR_Disabled = 0x0
	// DTR mode enabled for data phase
	OctoSPI_CCR_DDTR_Enabled = 0x1
	// Position of DQSE field.
	OctoSPI_CCR_DQSE_Pos = 0x1d
	// Bit mask of DQSE field.
	OctoSPI_CCR_DQSE_Msk = 0x20000000
	// Bit DQSE.
	OctoSPI_CCR_DQSE = 0x20000000
	// DQS disabled
	OctoSPI_CCR_DQSE_Disabled = 0x0
	// DQS enabled
	OctoSPI_CCR_DQSE_Enabled = 0x1
	// Position of SIOO field.
	OctoSPI_CCR_SIOO_Pos = 0x1f
	// Bit mask of SIOO field.
	OctoSPI_CCR_SIOO_Msk = 0x80000000
	// Bit SIOO.
	OctoSPI_CCR_SIOO = 0x80000000
	// Send instruction on every transaction
	OctoSPI_CCR_SIOO_SendEveryTransaction = 0x0
	// Send instruction only for the first command
	OctoSPI_CCR_SIOO_SendOnlyFirstCmd = 0x1

	// TCR: timing configuration register
	// Position of DCYC field.
	OctoSPI_TCR_DCYC_Pos = 0x0
	// Bit mask of DCYC field.
	OctoSPI_TCR_DCYC_Msk = 0x1f
	// Position of DHQC field.
	OctoSPI_TCR_DHQC_Pos = 0x1c
	// Bit mask of DHQC field.
	OctoSPI_TCR_DHQC_Msk = 0x10000000
	// Bit DHQC.
	OctoSPI_TCR_DHQC = 0x10000000
	// No delay hold
	OctoSPI_TCR_DHQC_NoDelay = 0x0
	// 1/4 cycle hold
	OctoSPI_TCR_DHQC_QuarterCycleHold = 0x1
	// Position of SSHIFT field.
	OctoSPI_TCR_SSHIFT_Pos = 0x1e
	// Bit mask of SSHIFT field.
	OctoSPI_TCR_SSHIFT_Msk = 0x40000000
	// Bit SSHIFT.
	OctoSPI_TCR_SSHIFT = 0x40000000
	// No shift
	OctoSPI_TCR_SSHIFT_NoShift = 0x0
	// 1/2 cycle shift
	OctoSPI_TCR_SSHIFT_HalfCycleShift = 0x1

	// IR: instruction register
	// Position of INSTRUCTION field.
	OctoSPI_IR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	OctoSPI_IR_INSTRUCTION_Msk = 0xffffffff

	// ABR: alternate bytes register
	// Position of ALTERNATE field.
	OctoSPI_ABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	OctoSPI_ABR_ALTERNATE_Msk = 0xffffffff

	// LPTR: low-power timeout register
	// Position of TIMEOUT field.
	OctoSPI_LPTR_TIMEOUT_Pos = 0x0
	// Bit mask of TIMEOUT field.
	OctoSPI_LPTR_TIMEOUT_Msk = 0xffff

	// WPCCR: wrap communication configuration register
	// Position of IMODE field.
	OctoSPI_WPCCR_IMODE_Pos = 0x0
	// Bit mask of IMODE field.
	OctoSPI_WPCCR_IMODE_Msk = 0x7
	// No instruction
	OctoSPI_WPCCR_IMODE_NoInstruction = 0x0
	// Instruction on a single line
	OctoSPI_WPCCR_IMODE_SingleLine = 0x1
	// Instruction on two lines
	OctoSPI_WPCCR_IMODE_TwoLines = 0x2
	// Instruction on four lines
	OctoSPI_WPCCR_IMODE_FourLines = 0x3
	// Instruction on eight lines
	OctoSPI_WPCCR_IMODE_EightLines = 0x4
	// Position of IDTR field.
	OctoSPI_WPCCR_IDTR_Pos = 0x3
	// Bit mask of IDTR field.
	OctoSPI_WPCCR_IDTR_Msk = 0x8
	// Bit IDTR.
	OctoSPI_WPCCR_IDTR = 0x8
	// DTR mode disabled for instruction phase
	OctoSPI_WPCCR_IDTR_Disabled = 0x0
	// DTR mode enabled for instruction phase
	OctoSPI_WPCCR_IDTR_Enabled = 0x1
	// Position of ISIZE field.
	OctoSPI_WPCCR_ISIZE_Pos = 0x4
	// Bit mask of ISIZE field.
	OctoSPI_WPCCR_ISIZE_Msk = 0x30
	// 8-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits8 = 0x0
	// 16-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits16 = 0x1
	// 24-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits24 = 0x2
	// 32-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits32 = 0x3
	// Position of ADMODE field.
	OctoSPI_WPCCR_ADMODE_Pos = 0x8
	// Bit mask of ADMODE field.
	OctoSPI_WPCCR_ADMODE_Msk = 0x700
	// No address
	OctoSPI_WPCCR_ADMODE_NoAddress = 0x0
	// Address on a single line
	OctoSPI_WPCCR_ADMODE_SingleLine = 0x1
	// Address on two lines
	OctoSPI_WPCCR_ADMODE_TwoLines = 0x2
	// Address on four lines
	OctoSPI_WPCCR_ADMODE_FourLines = 0x3
	// Address on eight lines
	OctoSPI_WPCCR_ADMODE_EightLines = 0x4
	// Position of ADDTR field.
	OctoSPI_WPCCR_ADDTR_Pos = 0xb
	// Bit mask of ADDTR field.
	OctoSPI_WPCCR_ADDTR_Msk = 0x800
	// Bit ADDTR.
	OctoSPI_WPCCR_ADDTR = 0x800
	// DTR mode disabled for address phase
	OctoSPI_WPCCR_ADDTR_Disabled = 0x0
	// DTR mode enabled for address phase
	OctoSPI_WPCCR_ADDTR_Enabled = 0x1
	// Position of ADSIZE field.
	OctoSPI_WPCCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	OctoSPI_WPCCR_ADSIZE_Msk = 0x3000
	// 8-bit address
	OctoSPI_WPCCR_ADSIZE_Bits8 = 0x0
	// 16-bit address
	OctoSPI_WPCCR_ADSIZE_Bits16 = 0x1
	// 24-bit address
	OctoSPI_WPCCR_ADSIZE_Bits24 = 0x2
	// 32-bit address
	OctoSPI_WPCCR_ADSIZE_Bits32 = 0x3
	// Position of ABMODE field.
	OctoSPI_WPCCR_ABMODE_Pos = 0x10
	// Bit mask of ABMODE field.
	OctoSPI_WPCCR_ABMODE_Msk = 0x70000
	// No alternate bytes
	OctoSPI_WPCCR_ABMODE_NoAlternateBytes = 0x0
	// Alternate bytes on a single line
	OctoSPI_WPCCR_ABMODE_SingleLine = 0x1
	// Alternate bytes on two lines
	OctoSPI_WPCCR_ABMODE_TwoLines = 0x2
	// Alternate bytes on four lines
	OctoSPI_WPCCR_ABMODE_FourLines = 0x3
	// Alternate bytes on eight lines
	OctoSPI_WPCCR_ABMODE_EightLines = 0x4
	// Position of ABDTR field.
	OctoSPI_WPCCR_ABDTR_Pos = 0x13
	// Bit mask of ABDTR field.
	OctoSPI_WPCCR_ABDTR_Msk = 0x80000
	// Bit ABDTR.
	OctoSPI_WPCCR_ABDTR = 0x80000
	// DTR mode disabled for alternate bytes phase
	OctoSPI_WPCCR_ABDTR_Disabled = 0x0
	// DTR mode enabled for alternate bytes phase
	OctoSPI_WPCCR_ABDTR_Enabled = 0x1
	// Position of ABSIZE field.
	OctoSPI_WPCCR_ABSIZE_Pos = 0x14
	// Bit mask of ABSIZE field.
	OctoSPI_WPCCR_ABSIZE_Msk = 0x300000
	// 8-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits8 = 0x0
	// 16-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits16 = 0x1
	// 24-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits24 = 0x2
	// 32-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits32 = 0x3
	// Position of DMODE field.
	OctoSPI_WPCCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	OctoSPI_WPCCR_DMODE_Msk = 0x7000000
	// No data
	OctoSPI_WPCCR_DMODE_NoData = 0x0
	// Data on a single line
	OctoSPI_WPCCR_DMODE_SingleLine = 0x1
	// Data on two lines
	OctoSPI_WPCCR_DMODE_TwoLines = 0x2
	// Data on four lines
	OctoSPI_WPCCR_DMODE_FourLines = 0x3
	// Data on eight lines
	OctoSPI_WPCCR_DMODE_EightLines = 0x4
	// Position of DDTR field.
	OctoSPI_WPCCR_DDTR_Pos = 0x1b
	// Bit mask of DDTR field.
	OctoSPI_WPCCR_DDTR_Msk = 0x8000000
	// Bit DDTR.
	OctoSPI_WPCCR_DDTR = 0x8000000
	// DTR mode disabled for data phase
	OctoSPI_WPCCR_DDTR_Disabled = 0x0
	// DTR mode enabled for data phase
	OctoSPI_WPCCR_DDTR_Enabled = 0x1
	// Position of DQSE field.
	OctoSPI_WPCCR_DQSE_Pos = 0x1d
	// Bit mask of DQSE field.
	OctoSPI_WPCCR_DQSE_Msk = 0x20000000
	// Bit DQSE.
	OctoSPI_WPCCR_DQSE = 0x20000000
	// DQS disabled
	OctoSPI_WPCCR_DQSE_Disabled = 0x0
	// DQS enabled
	OctoSPI_WPCCR_DQSE_Enabled = 0x1

	// WPTCR: wrap timing configuration register
	// Position of DCYC field.
	OctoSPI_WPTCR_DCYC_Pos = 0x0
	// Bit mask of DCYC field.
	OctoSPI_WPTCR_DCYC_Msk = 0x1f
	// Position of DHQC field.
	OctoSPI_WPTCR_DHQC_Pos = 0x1c
	// Bit mask of DHQC field.
	OctoSPI_WPTCR_DHQC_Msk = 0x10000000
	// Bit DHQC.
	OctoSPI_WPTCR_DHQC = 0x10000000
	// No delay hold
	OctoSPI_WPTCR_DHQC_NoDelay = 0x0
	// 1/4 cycle hold
	OctoSPI_WPTCR_DHQC_QuarterCycleHold = 0x1
	// Position of SSHIFT field.
	OctoSPI_WPTCR_SSHIFT_Pos = 0x1e
	// Bit mask of SSHIFT field.
	OctoSPI_WPTCR_SSHIFT_Msk = 0x40000000
	// Bit SSHIFT.
	OctoSPI_WPTCR_SSHIFT = 0x40000000
	// No shift
	OctoSPI_WPTCR_SSHIFT_NoShift = 0x0
	// 1/2 cycle shift
	OctoSPI_WPTCR_SSHIFT_HalfCycleShift = 0x1

	// WPIR: wrap instruction register
	// Position of INSTRUCTION field.
	OctoSPI_WPIR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	OctoSPI_WPIR_INSTRUCTION_Msk = 0xffffffff

	// WPABR: wrap alternate bytes register
	// Position of ALTERNATE field.
	OctoSPI_WPABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	OctoSPI_WPABR_ALTERNATE_Msk = 0xffffffff

	// WCCR: write communication configuration register
	// Position of IMODE field.
	OctoSPI_WCCR_IMODE_Pos = 0x0
	// Bit mask of IMODE field.
	OctoSPI_WCCR_IMODE_Msk = 0x7
	// No instruction
	OctoSPI_WCCR_IMODE_NoInstruction = 0x0
	// Instruction on a single line
	OctoSPI_WCCR_IMODE_SingleLine = 0x1
	// Instruction on two lines
	OctoSPI_WCCR_IMODE_TwoLines = 0x2
	// Instruction on four lines
	OctoSPI_WCCR_IMODE_FourLines = 0x3
	// Instruction on eight lines
	OctoSPI_WCCR_IMODE_EightLines = 0x4
	// Position of IDTR field.
	OctoSPI_WCCR_IDTR_Pos = 0x3
	// Bit mask of IDTR field.
	OctoSPI_WCCR_IDTR_Msk = 0x8
	// Bit IDTR.
	OctoSPI_WCCR_IDTR = 0x8
	// DTR mode disabled for instruction phase
	OctoSPI_WCCR_IDTR_Disabled = 0x0
	// DTR mode enabled for instruction phase
	OctoSPI_WCCR_IDTR_Enabled = 0x1
	// Position of ISIZE field.
	OctoSPI_WCCR_ISIZE_Pos = 0x4
	// Bit mask of ISIZE field.
	OctoSPI_WCCR_ISIZE_Msk = 0x30
	// 8-bit instruction
	OctoSPI_WCCR_ISIZE_Bits8 = 0x0
	// 16-bit instruction
	OctoSPI_WCCR_ISIZE_Bits16 = 0x1
	// 24-bit instruction
	OctoSPI_WCCR_ISIZE_Bits24 = 0x2
	// 32-bit instruction
	OctoSPI_WCCR_ISIZE_Bits32 = 0x3
	// Position of ADMODE field.
	OctoSPI_WCCR_ADMODE_Pos = 0x8
	// Bit mask of ADMODE field.
	OctoSPI_WCCR_ADMODE_Msk = 0x700
	// No address
	OctoSPI_WCCR_ADMODE_NoAddress = 0x0
	// Address on a single line
	OctoSPI_WCCR_ADMODE_SingleLine = 0x1
	// Address on two lines
	OctoSPI_WCCR_ADMODE_TwoLines = 0x2
	// Address on four lines
	OctoSPI_WCCR_ADMODE_FourLines = 0x3
	// Address on eight lines
	OctoSPI_WCCR_ADMODE_EightLines = 0x4
	// Position of ADDTR field.
	OctoSPI_WCCR_ADDTR_Pos = 0xb
	// Bit mask of ADDTR field.
	OctoSPI_WCCR_ADDTR_Msk = 0x800
	// Bit ADDTR.
	OctoSPI_WCCR_ADDTR = 0x800
	// DTR mode disabled for address phase
	OctoSPI_WCCR_ADDTR_Disabled = 0x0
	// DTR mode enabled for address phase
	OctoSPI_WCCR_ADDTR_Enabled = 0x1
	// Position of ADSIZE field.
	OctoSPI_WCCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	OctoSPI_WCCR_ADSIZE_Msk = 0x3000
	// 8-bit address
	OctoSPI_WCCR_ADSIZE_Bits8 = 0x0
	// 16-bit address
	OctoSPI_WCCR_ADSIZE_Bits16 = 0x1
	// 24-bit address
	OctoSPI_WCCR_ADSIZE_Bits24 = 0x2
	// 32-bit address
	OctoSPI_WCCR_ADSIZE_Bits32 = 0x3
	// Position of ABMODE field.
	OctoSPI_WCCR_ABMODE_Pos = 0x10
	// Bit mask of ABMODE field.
	OctoSPI_WCCR_ABMODE_Msk = 0x70000
	// No alternate bytes
	OctoSPI_WCCR_ABMODE_NoAlternateBytes = 0x0
	// Alternate bytes on a single line
	OctoSPI_WCCR_ABMODE_SingleLine = 0x1
	// Alternate bytes on two lines
	OctoSPI_WCCR_ABMODE_TwoLines = 0x2
	// Alternate bytes on four lines
	OctoSPI_WCCR_ABMODE_FourLines = 0x3
	// Alternate bytes on eight lines
	OctoSPI_WCCR_ABMODE_EightLines = 0x4
	// Position of ABDTR field.
	OctoSPI_WCCR_ABDTR_Pos = 0x13
	// Bit mask of ABDTR field.
	OctoSPI_WCCR_ABDTR_Msk = 0x80000
	// Bit ABDTR.
	OctoSPI_WCCR_ABDTR = 0x80000
	// DTR mode disabled for alternate bytes phase
	OctoSPI_WCCR_ABDTR_Disabled = 0x0
	// DTR mode enabled for alternate bytes phase
	OctoSPI_WCCR_ABDTR_Enabled = 0x1
	// Position of ABSIZE field.
	OctoSPI_WCCR_ABSIZE_Pos = 0x14
	// Bit mask of ABSIZE field.
	OctoSPI_WCCR_ABSIZE_Msk = 0x300000
	// 8-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits8 = 0x0
	// 16-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits16 = 0x1
	// 24-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits24 = 0x2
	// 32-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits32 = 0x3
	// Position of DMODE field.
	OctoSPI_WCCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	OctoSPI_WCCR_DMODE_Msk = 0x7000000
	// No data
	OctoSPI_WCCR_DMODE_NoData = 0x0
	// Data on a single line
	OctoSPI_WCCR_DMODE_SingleLine = 0x1
	// Data on two lines
	OctoSPI_WCCR_DMODE_TwoLines = 0x2
	// Data on four lines
	OctoSPI_WCCR_DMODE_FourLines = 0x3
	// Data on eight lines
	OctoSPI_WCCR_DMODE_EightLines = 0x4
	// Position of DDTR field.
	OctoSPI_WCCR_DDTR_Pos = 0x1b
	// Bit mask of DDTR field.
	OctoSPI_WCCR_DDTR_Msk = 0x8000000
	// Bit DDTR.
	OctoSPI_WCCR_DDTR = 0x8000000
	// DTR mode disabled for data phase
	OctoSPI_WCCR_DDTR_Disabled = 0x0
	// DTR mode enabled for data phase
	OctoSPI_WCCR_DDTR_Enabled = 0x1
	// Position of DQSE field.
	OctoSPI_WCCR_DQSE_Pos = 0x1d
	// Bit mask of DQSE field.
	OctoSPI_WCCR_DQSE_Msk = 0x20000000
	// Bit DQSE.
	OctoSPI_WCCR_DQSE = 0x20000000
	// DQS disabled
	OctoSPI_WCCR_DQSE_Disabled = 0x0
	// DQS enabled
	OctoSPI_WCCR_DQSE_Enabled = 0x1

	// WTCR: write timing configuration register
	// Position of DCYC field.
	OctoSPI_WTCR_DCYC_Pos = 0x0
	// Bit mask of DCYC field.
	OctoSPI_WTCR_DCYC_Msk = 0x1f

	// WIR: write instruction register
	// Position of INSTRUCTION field.
	OctoSPI_WIR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	OctoSPI_WIR_INSTRUCTION_Msk = 0xffffffff

	// WABR: write alternate bytes register
	// Position of ALTERNATE field.
	OctoSPI_WABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	OctoSPI_WABR_ALTERNATE_Msk = 0xffffffff

	// HLCR: HyperBus latency configuration register
	// Position of LM field.
	OctoSPI_HLCR_LM_Pos = 0x0
	// Bit mask of LM field.
	OctoSPI_HLCR_LM_Msk = 0x1
	// Bit LM.
	OctoSPI_HLCR_LM = 0x1
	// Variable initial latency
	OctoSPI_HLCR_LM_Variable = 0x0
	// Fixed latency
	OctoSPI_HLCR_LM_Fixed = 0x1
	// Position of WZL field.
	OctoSPI_HLCR_WZL_Pos = 0x1
	// Bit mask of WZL field.
	OctoSPI_HLCR_WZL_Msk = 0x2
	// Bit WZL.
	OctoSPI_HLCR_WZL = 0x2
	// Latency on write accesses
	OctoSPI_HLCR_WZL_Disabled = 0x0
	// No latency on write accesses
	OctoSPI_HLCR_WZL_Enabled = 0x1
	// Position of TACC field.
	OctoSPI_HLCR_TACC_Pos = 0x8
	// Bit mask of TACC field.
	OctoSPI_HLCR_TACC_Msk = 0xff00
	// Position of TRWR field.
	OctoSPI_HLCR_TRWR_Pos = 0x10
	// Bit mask of TRWR field.
	OctoSPI_HLCR_TRWR_Msk = 0xff0000
)

// Constants for OPAMP: Operational amplifiers
const (
	// OPAMP1_CSR: OPAMP1 control/status register
	// Position of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Pos = 0x0
	// Bit mask of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Msk = 0x1
	// Bit OPAEN.
	OPAMP_OPAMP1_CSR_OPAEN = 0x1
	// Position of OPALPM field.
	OPAMP_OPAMP1_CSR_OPALPM_Pos = 0x1
	// Bit mask of OPALPM field.
	OPAMP_OPAMP1_CSR_OPALPM_Msk = 0x2
	// Bit OPALPM.
	OPAMP_OPAMP1_CSR_OPALPM = 0x2
	// Position of OPAMODE field.
	OPAMP_OPAMP1_CSR_OPAMODE_Pos = 0x2
	// Bit mask of OPAMODE field.
	OPAMP_OPAMP1_CSR_OPAMODE_Msk = 0xc
	// Position of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Pos = 0x4
	// Bit mask of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Msk = 0x30
	// Position of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Pos = 0x8
	// Bit mask of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Msk = 0x300
	// Position of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Pos = 0xa
	// Bit mask of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Msk = 0x400
	// Bit VP_SEL.
	OPAMP_OPAMP1_CSR_VP_SEL = 0x400
	// Position of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Pos = 0xc
	// Bit mask of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Msk = 0x1000
	// Bit CALON.
	OPAMP_OPAMP1_CSR_CALON = 0x1000
	// Position of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Pos = 0xd
	// Bit mask of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Msk = 0x2000
	// Bit CALSEL.
	OPAMP_OPAMP1_CSR_CALSEL = 0x2000
	// Position of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Pos = 0xe
	// Bit mask of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Msk = 0x4000
	// Bit USERTRIM.
	OPAMP_OPAMP1_CSR_USERTRIM = 0x4000
	// Position of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Pos = 0xf
	// Bit mask of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Msk = 0x8000
	// Bit CALOUT.
	OPAMP_OPAMP1_CSR_CALOUT = 0x8000
	// Position of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM_Pos = 0x1e
	// Bit mask of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM_Msk = 0x40000000
	// Bit OPAHSM.
	OPAMP_OPAMP1_CSR_OPAHSM = 0x40000000
	// Position of OPA_RANGE field.
	OPAMP_OPAMP1_CSR_OPA_RANGE_Pos = 0x1f
	// Bit mask of OPA_RANGE field.
	OPAMP_OPAMP1_CSR_OPA_RANGE_Msk = 0x80000000
	// Bit OPA_RANGE.
	OPAMP_OPAMP1_CSR_OPA_RANGE = 0x80000000

	// OPAMP1_OTR: OPAMP1 offset trimming register in normal mode
	// Position of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Pos = 0x0
	// Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Msk = 0x1f
	// Position of TRIMOFFSETP field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Pos = 0x8
	// Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Msk = 0x1f00

	// OPAMP1_LPOTR: OPAMP1 offset trimming register in low-power mode
	// Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETN_Pos = 0x0
	// Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETN_Msk = 0x1f
	// Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETP_Pos = 0x8
	// Bit mask of TRIMLPOFFSETP field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETP_Msk = 0x1f00

	// OPAMP2_CRS: OPAMP2 control/status register
	// Position of OPAEN field.
	OPAMP_OPAMP2_CRS_OPAEN_Pos = 0x0
	// Bit mask of OPAEN field.
	OPAMP_OPAMP2_CRS_OPAEN_Msk = 0x1
	// Bit OPAEN.
	OPAMP_OPAMP2_CRS_OPAEN = 0x1
	// Position of OPALPM field.
	OPAMP_OPAMP2_CRS_OPALPM_Pos = 0x1
	// Bit mask of OPALPM field.
	OPAMP_OPAMP2_CRS_OPALPM_Msk = 0x2
	// Bit OPALPM.
	OPAMP_OPAMP2_CRS_OPALPM = 0x2
	// Position of OPAMODE field.
	OPAMP_OPAMP2_CRS_OPAMODE_Pos = 0x2
	// Bit mask of OPAMODE field.
	OPAMP_OPAMP2_CRS_OPAMODE_Msk = 0xc
	// Position of PGA_GAIN field.
	OPAMP_OPAMP2_CRS_PGA_GAIN_Pos = 0x4
	// Bit mask of PGA_GAIN field.
	OPAMP_OPAMP2_CRS_PGA_GAIN_Msk = 0x30
	// Position of VM_SEL field.
	OPAMP_OPAMP2_CRS_VM_SEL_Pos = 0x8
	// Bit mask of VM_SEL field.
	OPAMP_OPAMP2_CRS_VM_SEL_Msk = 0x300
	// Position of VP_SEL field.
	OPAMP_OPAMP2_CRS_VP_SEL_Pos = 0xa
	// Bit mask of VP_SEL field.
	OPAMP_OPAMP2_CRS_VP_SEL_Msk = 0x400
	// Bit VP_SEL.
	OPAMP_OPAMP2_CRS_VP_SEL = 0x400
	// Position of CALON field.
	OPAMP_OPAMP2_CRS_CALON_Pos = 0xc
	// Bit mask of CALON field.
	OPAMP_OPAMP2_CRS_CALON_Msk = 0x1000
	// Bit CALON.
	OPAMP_OPAMP2_CRS_CALON = 0x1000
	// Position of CALSEL field.
	OPAMP_OPAMP2_CRS_CALSEL_Pos = 0xd
	// Bit mask of CALSEL field.
	OPAMP_OPAMP2_CRS_CALSEL_Msk = 0x2000
	// Bit CALSEL.
	OPAMP_OPAMP2_CRS_CALSEL = 0x2000
	// Position of USERTRIM field.
	OPAMP_OPAMP2_CRS_USERTRIM_Pos = 0xe
	// Bit mask of USERTRIM field.
	OPAMP_OPAMP2_CRS_USERTRIM_Msk = 0x4000
	// Bit USERTRIM.
	OPAMP_OPAMP2_CRS_USERTRIM = 0x4000
	// Position of CALOUT field.
	OPAMP_OPAMP2_CRS_CALOUT_Pos = 0xf
	// Bit mask of CALOUT field.
	OPAMP_OPAMP2_CRS_CALOUT_Msk = 0x8000
	// Bit CALOUT.
	OPAMP_OPAMP2_CRS_CALOUT = 0x8000
	// Position of OPAHSM field.
	OPAMP_OPAMP2_CRS_OPAHSM_Pos = 0x1e
	// Bit mask of OPAHSM field.
	OPAMP_OPAMP2_CRS_OPAHSM_Msk = 0x40000000
	// Bit OPAHSM.
	OPAMP_OPAMP2_CRS_OPAHSM = 0x40000000

	// OPAMP2_OTR: OPAMP2 offset trimming register in normal mode
	// Position of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Pos = 0x0
	// Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Msk = 0x1f
	// Position of TRIMOFFSETP field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Pos = 0x8
	// Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Msk = 0x1f00

	// OPAMP2_LPOTR: OPAMP2 offset trimming register in low-power mode
	// Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETN_Pos = 0x0
	// Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETN_Msk = 0x1f
	// Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETP_Pos = 0x8
	// Bit mask of TRIMLPOFFSETP field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETP_Msk = 0x1f00
)

// Constants for OTFDEC1: On-The-Fly Decryption engine
const (
	// CR: OTFDEC control register
	// Position of ENC field.
	OTFDEC_CR_ENC_Pos = 0x0
	// Bit mask of ENC field.
	OTFDEC_CR_ENC_Msk = 0x1
	// Bit ENC.
	OTFDEC_CR_ENC = 0x1

	// PRIVCFGR: OTFDEC privileged access control configuration register
	// Position of PRIV field.
	OTFDEC_PRIVCFGR_PRIV_Pos = 0x0
	// Bit mask of PRIV field.
	OTFDEC_PRIVCFGR_PRIV_Msk = 0x1
	// Bit PRIV.
	OTFDEC_PRIVCFGR_PRIV = 0x1

	// R1CFGR: OTFDEC region x configuration register
	// Position of REG_EN field.
	OTFDEC_R1CFGR_REG_EN_Pos = 0x0
	// Bit mask of REG_EN field.
	OTFDEC_R1CFGR_REG_EN_Msk = 0x1
	// Bit REG_EN.
	OTFDEC_R1CFGR_REG_EN = 0x1
	// Position of CONFIGLOCK field.
	OTFDEC_R1CFGR_CONFIGLOCK_Pos = 0x1
	// Bit mask of CONFIGLOCK field.
	OTFDEC_R1CFGR_CONFIGLOCK_Msk = 0x2
	// Bit CONFIGLOCK.
	OTFDEC_R1CFGR_CONFIGLOCK = 0x2
	// Position of KEYLOCK field.
	OTFDEC_R1CFGR_KEYLOCK_Pos = 0x2
	// Bit mask of KEYLOCK field.
	OTFDEC_R1CFGR_KEYLOCK_Msk = 0x4
	// Bit KEYLOCK.
	OTFDEC_R1CFGR_KEYLOCK = 0x4
	// Position of MODE field.
	OTFDEC_R1CFGR_MODE_Pos = 0x4
	// Bit mask of MODE field.
	OTFDEC_R1CFGR_MODE_Msk = 0x30
	// Position of KEYCRC field.
	OTFDEC_R1CFGR_KEYCRC_Pos = 0x8
	// Bit mask of KEYCRC field.
	OTFDEC_R1CFGR_KEYCRC_Msk = 0xff00
	// Position of REG1_VERSION field.
	OTFDEC_R1CFGR_REG1_VERSION_Pos = 0x10
	// Bit mask of REG1_VERSION field.
	OTFDEC_R1CFGR_REG1_VERSION_Msk = 0xffff0000

	// R1STARTADDR: OTFDEC region x start address register
	// Position of REG1_START_ADDR field.
	OTFDEC_R1STARTADDR_REG1_START_ADDR_Pos = 0x0
	// Bit mask of REG1_START_ADDR field.
	OTFDEC_R1STARTADDR_REG1_START_ADDR_Msk = 0xffffffff

	// R1ENDADDR: OTFDEC region x end address register
	// Position of REG1_END_ADDR field.
	OTFDEC_R1ENDADDR_REG1_END_ADDR_Pos = 0x0
	// Bit mask of REG1_END_ADDR field.
	OTFDEC_R1ENDADDR_REG1_END_ADDR_Msk = 0xffffffff

	// R1NONCER0: OTFDEC region x nonce register 0
	// Position of REG1_NONCE field.
	OTFDEC_R1NONCER0_REG1_NONCE_Pos = 0x0
	// Bit mask of REG1_NONCE field.
	OTFDEC_R1NONCER0_REG1_NONCE_Msk = 0xffffffff

	// R1NONCER1: OTFDEC region x nonce register 1
	// Position of REG1_NONCE field.
	OTFDEC_R1NONCER1_REG1_NONCE_Pos = 0x0
	// Bit mask of REG1_NONCE field.
	OTFDEC_R1NONCER1_REG1_NONCE_Msk = 0xffffffff

	// R1KEYR0: OTFDEC region x key register 0
	// Position of REG1_KEY field.
	OTFDEC_R1KEYR0_REG1_KEY_Pos = 0x0
	// Bit mask of REG1_KEY field.
	OTFDEC_R1KEYR0_REG1_KEY_Msk = 0xffffffff

	// R1KEYR1: OTFDEC region x key register 1
	// Position of REG1_KEY field.
	OTFDEC_R1KEYR1_REG1_KEY_Pos = 0x0
	// Bit mask of REG1_KEY field.
	OTFDEC_R1KEYR1_REG1_KEY_Msk = 0xffffffff

	// R1KEYR2: OTFDEC region x key register 2
	// Position of REG1_KEY field.
	OTFDEC_R1KEYR2_REG1_KEY_Pos = 0x0
	// Bit mask of REG1_KEY field.
	OTFDEC_R1KEYR2_REG1_KEY_Msk = 0xffffffff

	// R1KEYR3: OTFDEC region x key register 3
	// Position of REG1_KEY field.
	OTFDEC_R1KEYR3_REG1_KEY_Pos = 0x0
	// Bit mask of REG1_KEY field.
	OTFDEC_R1KEYR3_REG1_KEY_Msk = 0xffffffff

	// R2CFGR: OTFDEC region x configuration register
	// Position of REG_EN field.
	OTFDEC_R2CFGR_REG_EN_Pos = 0x0
	// Bit mask of REG_EN field.
	OTFDEC_R2CFGR_REG_EN_Msk = 0x1
	// Bit REG_EN.
	OTFDEC_R2CFGR_REG_EN = 0x1
	// Position of CONFIGLOCK field.
	OTFDEC_R2CFGR_CONFIGLOCK_Pos = 0x1
	// Bit mask of CONFIGLOCK field.
	OTFDEC_R2CFGR_CONFIGLOCK_Msk = 0x2
	// Bit CONFIGLOCK.
	OTFDEC_R2CFGR_CONFIGLOCK = 0x2
	// Position of KEYLOCK field.
	OTFDEC_R2CFGR_KEYLOCK_Pos = 0x2
	// Bit mask of KEYLOCK field.
	OTFDEC_R2CFGR_KEYLOCK_Msk = 0x4
	// Bit KEYLOCK.
	OTFDEC_R2CFGR_KEYLOCK = 0x4
	// Position of MODE field.
	OTFDEC_R2CFGR_MODE_Pos = 0x4
	// Bit mask of MODE field.
	OTFDEC_R2CFGR_MODE_Msk = 0x30
	// Position of KEYCRC field.
	OTFDEC_R2CFGR_KEYCRC_Pos = 0x8
	// Bit mask of KEYCRC field.
	OTFDEC_R2CFGR_KEYCRC_Msk = 0xff00
	// Position of REG2_VERSION field.
	OTFDEC_R2CFGR_REG2_VERSION_Pos = 0x10
	// Bit mask of REG2_VERSION field.
	OTFDEC_R2CFGR_REG2_VERSION_Msk = 0xffff0000

	// R2STARTADDR: OTFDEC region x start address register
	// Position of REG2_START_ADDR field.
	OTFDEC_R2STARTADDR_REG2_START_ADDR_Pos = 0x0
	// Bit mask of REG2_START_ADDR field.
	OTFDEC_R2STARTADDR_REG2_START_ADDR_Msk = 0xffffffff

	// R2ENDADDR: OTFDEC region x end address register
	// Position of REG2_END_ADDR field.
	OTFDEC_R2ENDADDR_REG2_END_ADDR_Pos = 0x0
	// Bit mask of REG2_END_ADDR field.
	OTFDEC_R2ENDADDR_REG2_END_ADDR_Msk = 0xffffffff

	// R2NONCER0: OTFDEC region x nonce register 0
	// Position of REG2_NONCE field.
	OTFDEC_R2NONCER0_REG2_NONCE_Pos = 0x0
	// Bit mask of REG2_NONCE field.
	OTFDEC_R2NONCER0_REG2_NONCE_Msk = 0xffffffff

	// R2NONCER1: OTFDEC region x nonce register 1
	// Position of REG2_NONCE field.
	OTFDEC_R2NONCER1_REG2_NONCE_Pos = 0x0
	// Bit mask of REG2_NONCE field.
	OTFDEC_R2NONCER1_REG2_NONCE_Msk = 0xffffffff

	// R2KEYR0: OTFDEC region x key register 0
	// Position of REG2_KEY field.
	OTFDEC_R2KEYR0_REG2_KEY_Pos = 0x0
	// Bit mask of REG2_KEY field.
	OTFDEC_R2KEYR0_REG2_KEY_Msk = 0xffffffff

	// R2KEYR1: OTFDEC region x key register 1
	// Position of REG2_KEY field.
	OTFDEC_R2KEYR1_REG2_KEY_Pos = 0x0
	// Bit mask of REG2_KEY field.
	OTFDEC_R2KEYR1_REG2_KEY_Msk = 0xffffffff

	// R2KEYR2: OTFDEC region x key register 2
	// Position of REG2_KEY_ field.
	OTFDEC_R2KEYR2_REG2_KEY__Pos = 0x0
	// Bit mask of REG2_KEY_ field.
	OTFDEC_R2KEYR2_REG2_KEY__Msk = 0xffffffff

	// R2KEYR3: OTFDEC region x key register 3
	// Position of REG2_KEY field.
	OTFDEC_R2KEYR3_REG2_KEY_Pos = 0x0
	// Bit mask of REG2_KEY field.
	OTFDEC_R2KEYR3_REG2_KEY_Msk = 0xffffffff

	// R3CFGR: OTFDEC region x configuration register
	// Position of REG_EN field.
	OTFDEC_R3CFGR_REG_EN_Pos = 0x0
	// Bit mask of REG_EN field.
	OTFDEC_R3CFGR_REG_EN_Msk = 0x1
	// Bit REG_EN.
	OTFDEC_R3CFGR_REG_EN = 0x1
	// Position of CONFIGLOCK field.
	OTFDEC_R3CFGR_CONFIGLOCK_Pos = 0x1
	// Bit mask of CONFIGLOCK field.
	OTFDEC_R3CFGR_CONFIGLOCK_Msk = 0x2
	// Bit CONFIGLOCK.
	OTFDEC_R3CFGR_CONFIGLOCK = 0x2
	// Position of KEYLOCK field.
	OTFDEC_R3CFGR_KEYLOCK_Pos = 0x2
	// Bit mask of KEYLOCK field.
	OTFDEC_R3CFGR_KEYLOCK_Msk = 0x4
	// Bit KEYLOCK.
	OTFDEC_R3CFGR_KEYLOCK = 0x4
	// Position of MODE field.
	OTFDEC_R3CFGR_MODE_Pos = 0x4
	// Bit mask of MODE field.
	OTFDEC_R3CFGR_MODE_Msk = 0x30
	// Position of KEYCRC field.
	OTFDEC_R3CFGR_KEYCRC_Pos = 0x8
	// Bit mask of KEYCRC field.
	OTFDEC_R3CFGR_KEYCRC_Msk = 0xff00
	// Position of REG3_VERSION field.
	OTFDEC_R3CFGR_REG3_VERSION_Pos = 0x10
	// Bit mask of REG3_VERSION field.
	OTFDEC_R3CFGR_REG3_VERSION_Msk = 0xffff0000

	// R3STARTADDR: OTFDEC region x start address register
	// Position of REG3_START_ADDR field.
	OTFDEC_R3STARTADDR_REG3_START_ADDR_Pos = 0x0
	// Bit mask of REG3_START_ADDR field.
	OTFDEC_R3STARTADDR_REG3_START_ADDR_Msk = 0xffffffff

	// R3ENDADDR: OTFDEC region x end address register
	// Position of REG3_END_ADDR field.
	OTFDEC_R3ENDADDR_REG3_END_ADDR_Pos = 0x0
	// Bit mask of REG3_END_ADDR field.
	OTFDEC_R3ENDADDR_REG3_END_ADDR_Msk = 0xffffffff

	// R3NONCER0: OTFDEC region x nonce register 0
	// Position of REG3_NONCE field.
	OTFDEC_R3NONCER0_REG3_NONCE_Pos = 0x0
	// Bit mask of REG3_NONCE field.
	OTFDEC_R3NONCER0_REG3_NONCE_Msk = 0xffffffff

	// R3NONCER1: OTFDEC region x nonce register 1
	// Position of REG3_NONCE field.
	OTFDEC_R3NONCER1_REG3_NONCE_Pos = 0x0
	// Bit mask of REG3_NONCE field.
	OTFDEC_R3NONCER1_REG3_NONCE_Msk = 0xffffffff

	// R3KEYR0: OTFDEC region x key register 0
	// Position of REG3_KEY field.
	OTFDEC_R3KEYR0_REG3_KEY_Pos = 0x0
	// Bit mask of REG3_KEY field.
	OTFDEC_R3KEYR0_REG3_KEY_Msk = 0xffffffff

	// R3KEYR1: OTFDEC region x key register 1
	// Position of REG3_KEY field.
	OTFDEC_R3KEYR1_REG3_KEY_Pos = 0x0
	// Bit mask of REG3_KEY field.
	OTFDEC_R3KEYR1_REG3_KEY_Msk = 0xffffffff

	// R3KEYR2: OTFDEC region x key register 2
	// Position of REG3_KEY field.
	OTFDEC_R3KEYR2_REG3_KEY_Pos = 0x0
	// Bit mask of REG3_KEY field.
	OTFDEC_R3KEYR2_REG3_KEY_Msk = 0xffffffff

	// R3KEYR3: OTFDEC region x key register 3
	// Position of REG3_KEY field.
	OTFDEC_R3KEYR3_REG3_KEY_Pos = 0x0
	// Bit mask of REG3_KEY field.
	OTFDEC_R3KEYR3_REG3_KEY_Msk = 0xffffffff

	// R4CFGR: OTFDEC region x configuration register
	// Position of REG_EN field.
	OTFDEC_R4CFGR_REG_EN_Pos = 0x0
	// Bit mask of REG_EN field.
	OTFDEC_R4CFGR_REG_EN_Msk = 0x1
	// Bit REG_EN.
	OTFDEC_R4CFGR_REG_EN = 0x1
	// Position of CONFIGLOCK field.
	OTFDEC_R4CFGR_CONFIGLOCK_Pos = 0x1
	// Bit mask of CONFIGLOCK field.
	OTFDEC_R4CFGR_CONFIGLOCK_Msk = 0x2
	// Bit CONFIGLOCK.
	OTFDEC_R4CFGR_CONFIGLOCK = 0x2
	// Position of KEYLOCK field.
	OTFDEC_R4CFGR_KEYLOCK_Pos = 0x2
	// Bit mask of KEYLOCK field.
	OTFDEC_R4CFGR_KEYLOCK_Msk = 0x4
	// Bit KEYLOCK.
	OTFDEC_R4CFGR_KEYLOCK = 0x4
	// Position of MODE field.
	OTFDEC_R4CFGR_MODE_Pos = 0x4
	// Bit mask of MODE field.
	OTFDEC_R4CFGR_MODE_Msk = 0x30
	// Position of KEYCRC field.
	OTFDEC_R4CFGR_KEYCRC_Pos = 0x8
	// Bit mask of KEYCRC field.
	OTFDEC_R4CFGR_KEYCRC_Msk = 0xff00
	// Position of REG4_VERSION field.
	OTFDEC_R4CFGR_REG4_VERSION_Pos = 0x10
	// Bit mask of REG4_VERSION field.
	OTFDEC_R4CFGR_REG4_VERSION_Msk = 0xffff0000

	// R4STARTADDR: OTFDEC region x start address register
	// Position of REG4_START_ADDR field.
	OTFDEC_R4STARTADDR_REG4_START_ADDR_Pos = 0x0
	// Bit mask of REG4_START_ADDR field.
	OTFDEC_R4STARTADDR_REG4_START_ADDR_Msk = 0xffffffff

	// R4ENDADDR: OTFDEC region x end address register
	// Position of REG4_END_ADDR field.
	OTFDEC_R4ENDADDR_REG4_END_ADDR_Pos = 0x0
	// Bit mask of REG4_END_ADDR field.
	OTFDEC_R4ENDADDR_REG4_END_ADDR_Msk = 0xffffffff

	// R4NONCER0: OTFDEC region x nonce register 0
	// Position of REG4_NONCE field.
	OTFDEC_R4NONCER0_REG4_NONCE_Pos = 0x0
	// Bit mask of REG4_NONCE field.
	OTFDEC_R4NONCER0_REG4_NONCE_Msk = 0xffffffff

	// R4NONCER1: OTFDEC region x nonce register 1
	// Position of REG4_NONCE field.
	OTFDEC_R4NONCER1_REG4_NONCE_Pos = 0x0
	// Bit mask of REG4_NONCE field.
	OTFDEC_R4NONCER1_REG4_NONCE_Msk = 0xffffffff

	// R4KEYR0: OTFDEC region x key register 0
	// Position of REG4_KEY field.
	OTFDEC_R4KEYR0_REG4_KEY_Pos = 0x0
	// Bit mask of REG4_KEY field.
	OTFDEC_R4KEYR0_REG4_KEY_Msk = 0xffffffff

	// R4KEYR1: OTFDEC region x key register 1
	// Position of REG4_KEY field.
	OTFDEC_R4KEYR1_REG4_KEY_Pos = 0x0
	// Bit mask of REG4_KEY field.
	OTFDEC_R4KEYR1_REG4_KEY_Msk = 0xffffffff

	// R4KEYR2: OTFDEC region x key register 2
	// Position of REG4_KEY field.
	OTFDEC_R4KEYR2_REG4_KEY_Pos = 0x0
	// Bit mask of REG4_KEY field.
	OTFDEC_R4KEYR2_REG4_KEY_Msk = 0xffffffff

	// R4KEYR3: OTFDEC region x key register 3
	// Position of REG4_KEY field.
	OTFDEC_R4KEYR3_REG4_KEY_Pos = 0x0
	// Bit mask of REG4_KEY field.
	OTFDEC_R4KEYR3_REG4_KEY_Msk = 0xffffffff

	// ISR: OTFDEC interrupt status register
	// Position of SEIF field.
	OTFDEC_ISR_SEIF_Pos = 0x0
	// Bit mask of SEIF field.
	OTFDEC_ISR_SEIF_Msk = 0x1
	// Bit SEIF.
	OTFDEC_ISR_SEIF = 0x1
	// Position of XONEIF field.
	OTFDEC_ISR_XONEIF_Pos = 0x1
	// Bit mask of XONEIF field.
	OTFDEC_ISR_XONEIF_Msk = 0x2
	// Bit XONEIF.
	OTFDEC_ISR_XONEIF = 0x2
	// Position of KEIF field.
	OTFDEC_ISR_KEIF_Pos = 0x2
	// Bit mask of KEIF field.
	OTFDEC_ISR_KEIF_Msk = 0x4
	// Bit KEIF.
	OTFDEC_ISR_KEIF = 0x4

	// ICR: OTFDEC interrupt clear register
	// Position of SEIF field.
	OTFDEC_ICR_SEIF_Pos = 0x0
	// Bit mask of SEIF field.
	OTFDEC_ICR_SEIF_Msk = 0x1
	// Bit SEIF.
	OTFDEC_ICR_SEIF = 0x1
	// Position of XONEIF field.
	OTFDEC_ICR_XONEIF_Pos = 0x1
	// Bit mask of XONEIF field.
	OTFDEC_ICR_XONEIF_Msk = 0x2
	// Bit XONEIF.
	OTFDEC_ICR_XONEIF = 0x2
	// Position of KEIF field.
	OTFDEC_ICR_KEIF_Pos = 0x2
	// Bit mask of KEIF field.
	OTFDEC_ICR_KEIF_Msk = 0x4
	// Bit KEIF.
	OTFDEC_ICR_KEIF = 0x4

	// IER: OTFDEC interrupt enable register
	// Position of SEIE field.
	OTFDEC_IER_SEIE_Pos = 0x0
	// Bit mask of SEIE field.
	OTFDEC_IER_SEIE_Msk = 0x1
	// Bit SEIE.
	OTFDEC_IER_SEIE = 0x1
	// Position of XONEIE field.
	OTFDEC_IER_XONEIE_Pos = 0x1
	// Bit mask of XONEIE field.
	OTFDEC_IER_XONEIE_Msk = 0x2
	// Bit XONEIE.
	OTFDEC_IER_XONEIE = 0x2
	// Position of KEIE field.
	OTFDEC_IER_KEIE_Pos = 0x2
	// Bit mask of KEIE field.
	OTFDEC_IER_KEIE_Msk = 0x4
	// Bit KEIE.
	OTFDEC_IER_KEIE = 0x4
)

// Constants for OTG_HS: OTG_HS
const (
	// GOTGCTL: The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
	// Position of SRQSCS field.
	OTG_HS_GOTGCTL_SRQSCS_Pos = 0x0
	// Bit mask of SRQSCS field.
	OTG_HS_GOTGCTL_SRQSCS_Msk = 0x1
	// Bit SRQSCS.
	OTG_HS_GOTGCTL_SRQSCS = 0x1
	// Position of SRQ field.
	OTG_HS_GOTGCTL_SRQ_Pos = 0x1
	// Bit mask of SRQ field.
	OTG_HS_GOTGCTL_SRQ_Msk = 0x2
	// Bit SRQ.
	OTG_HS_GOTGCTL_SRQ = 0x2
	// Position of VBVALOEN field.
	OTG_HS_GOTGCTL_VBVALOEN_Pos = 0x2
	// Bit mask of VBVALOEN field.
	OTG_HS_GOTGCTL_VBVALOEN_Msk = 0x4
	// Bit VBVALOEN.
	OTG_HS_GOTGCTL_VBVALOEN = 0x4
	// Position of VBVALOVAL field.
	OTG_HS_GOTGCTL_VBVALOVAL_Pos = 0x3
	// Bit mask of VBVALOVAL field.
	OTG_HS_GOTGCTL_VBVALOVAL_Msk = 0x8
	// Bit VBVALOVAL.
	OTG_HS_GOTGCTL_VBVALOVAL = 0x8
	// Position of AVALOEN field.
	OTG_HS_GOTGCTL_AVALOEN_Pos = 0x4
	// Bit mask of AVALOEN field.
	OTG_HS_GOTGCTL_AVALOEN_Msk = 0x10
	// Bit AVALOEN.
	OTG_HS_GOTGCTL_AVALOEN = 0x10
	// Position of AVALOVAL field.
	OTG_HS_GOTGCTL_AVALOVAL_Pos = 0x5
	// Bit mask of AVALOVAL field.
	OTG_HS_GOTGCTL_AVALOVAL_Msk = 0x20
	// Bit AVALOVAL.
	OTG_HS_GOTGCTL_AVALOVAL = 0x20
	// Position of BVALOEN field.
	OTG_HS_GOTGCTL_BVALOEN_Pos = 0x6
	// Bit mask of BVALOEN field.
	OTG_HS_GOTGCTL_BVALOEN_Msk = 0x40
	// Bit BVALOEN.
	OTG_HS_GOTGCTL_BVALOEN = 0x40
	// Position of BVALOVAL field.
	OTG_HS_GOTGCTL_BVALOVAL_Pos = 0x7
	// Bit mask of BVALOVAL field.
	OTG_HS_GOTGCTL_BVALOVAL_Msk = 0x80
	// Bit BVALOVAL.
	OTG_HS_GOTGCTL_BVALOVAL = 0x80
	// Position of HNGSCS field.
	OTG_HS_GOTGCTL_HNGSCS_Pos = 0x8
	// Bit mask of HNGSCS field.
	OTG_HS_GOTGCTL_HNGSCS_Msk = 0x100
	// Bit HNGSCS.
	OTG_HS_GOTGCTL_HNGSCS = 0x100
	// Position of HNPRQ field.
	OTG_HS_GOTGCTL_HNPRQ_Pos = 0x9
	// Bit mask of HNPRQ field.
	OTG_HS_GOTGCTL_HNPRQ_Msk = 0x200
	// Bit HNPRQ.
	OTG_HS_GOTGCTL_HNPRQ = 0x200
	// Position of HSHNPEN field.
	OTG_HS_GOTGCTL_HSHNPEN_Pos = 0xa
	// Bit mask of HSHNPEN field.
	OTG_HS_GOTGCTL_HSHNPEN_Msk = 0x400
	// Bit HSHNPEN.
	OTG_HS_GOTGCTL_HSHNPEN = 0x400
	// Position of DHNPEN field.
	OTG_HS_GOTGCTL_DHNPEN_Pos = 0xb
	// Bit mask of DHNPEN field.
	OTG_HS_GOTGCTL_DHNPEN_Msk = 0x800
	// Bit DHNPEN.
	OTG_HS_GOTGCTL_DHNPEN = 0x800
	// Position of EHEN field.
	OTG_HS_GOTGCTL_EHEN_Pos = 0xc
	// Bit mask of EHEN field.
	OTG_HS_GOTGCTL_EHEN_Msk = 0x1000
	// Bit EHEN.
	OTG_HS_GOTGCTL_EHEN = 0x1000
	// Position of CIDSTS field.
	OTG_HS_GOTGCTL_CIDSTS_Pos = 0x10
	// Bit mask of CIDSTS field.
	OTG_HS_GOTGCTL_CIDSTS_Msk = 0x10000
	// Bit CIDSTS.
	OTG_HS_GOTGCTL_CIDSTS = 0x10000
	// Position of DBCT field.
	OTG_HS_GOTGCTL_DBCT_Pos = 0x11
	// Bit mask of DBCT field.
	OTG_HS_GOTGCTL_DBCT_Msk = 0x20000
	// Bit DBCT.
	OTG_HS_GOTGCTL_DBCT = 0x20000
	// Position of ASVLD field.
	OTG_HS_GOTGCTL_ASVLD_Pos = 0x12
	// Bit mask of ASVLD field.
	OTG_HS_GOTGCTL_ASVLD_Msk = 0x40000
	// Bit ASVLD.
	OTG_HS_GOTGCTL_ASVLD = 0x40000
	// Position of BSVLD field.
	OTG_HS_GOTGCTL_BSVLD_Pos = 0x13
	// Bit mask of BSVLD field.
	OTG_HS_GOTGCTL_BSVLD_Msk = 0x80000
	// Bit BSVLD.
	OTG_HS_GOTGCTL_BSVLD = 0x80000
	// Position of OTGVER field.
	OTG_HS_GOTGCTL_OTGVER_Pos = 0x14
	// Bit mask of OTGVER field.
	OTG_HS_GOTGCTL_OTGVER_Msk = 0x100000
	// Bit OTGVER.
	OTG_HS_GOTGCTL_OTGVER = 0x100000
	// Position of CURMOD field.
	OTG_HS_GOTGCTL_CURMOD_Pos = 0x15
	// Bit mask of CURMOD field.
	OTG_HS_GOTGCTL_CURMOD_Msk = 0x200000
	// Bit CURMOD.
	OTG_HS_GOTGCTL_CURMOD = 0x200000

	// GOTGINT: The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
	// Position of SEDET field.
	OTG_HS_GOTGINT_SEDET_Pos = 0x2
	// Bit mask of SEDET field.
	OTG_HS_GOTGINT_SEDET_Msk = 0x4
	// Bit SEDET.
	OTG_HS_GOTGINT_SEDET = 0x4
	// Position of SRSSCHG field.
	OTG_HS_GOTGINT_SRSSCHG_Pos = 0x8
	// Bit mask of SRSSCHG field.
	OTG_HS_GOTGINT_SRSSCHG_Msk = 0x100
	// Bit SRSSCHG.
	OTG_HS_GOTGINT_SRSSCHG = 0x100
	// Position of HNSSCHG field.
	OTG_HS_GOTGINT_HNSSCHG_Pos = 0x9
	// Bit mask of HNSSCHG field.
	OTG_HS_GOTGINT_HNSSCHG_Msk = 0x200
	// Bit HNSSCHG.
	OTG_HS_GOTGINT_HNSSCHG = 0x200
	// Position of HNGDET field.
	OTG_HS_GOTGINT_HNGDET_Pos = 0x11
	// Bit mask of HNGDET field.
	OTG_HS_GOTGINT_HNGDET_Msk = 0x20000
	// Bit HNGDET.
	OTG_HS_GOTGINT_HNGDET = 0x20000
	// Position of ADTOCHG field.
	OTG_HS_GOTGINT_ADTOCHG_Pos = 0x12
	// Bit mask of ADTOCHG field.
	OTG_HS_GOTGINT_ADTOCHG_Msk = 0x40000
	// Bit ADTOCHG.
	OTG_HS_GOTGINT_ADTOCHG = 0x40000
	// Position of DBCDNE field.
	OTG_HS_GOTGINT_DBCDNE_Pos = 0x13
	// Bit mask of DBCDNE field.
	OTG_HS_GOTGINT_DBCDNE_Msk = 0x80000
	// Bit DBCDNE.
	OTG_HS_GOTGINT_DBCDNE = 0x80000

	// GAHBCFG: This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
	// Position of GINTMSK field.
	OTG_HS_GAHBCFG_GINTMSK_Pos = 0x0
	// Bit mask of GINTMSK field.
	OTG_HS_GAHBCFG_GINTMSK_Msk = 0x1
	// Bit GINTMSK.
	OTG_HS_GAHBCFG_GINTMSK = 0x1
	// Position of TXFELVL field.
	OTG_HS_GAHBCFG_TXFELVL_Pos = 0x7
	// Bit mask of TXFELVL field.
	OTG_HS_GAHBCFG_TXFELVL_Msk = 0x80
	// Bit TXFELVL.
	OTG_HS_GAHBCFG_TXFELVL = 0x80
	// Position of PTXFELVL field.
	OTG_HS_GAHBCFG_PTXFELVL_Pos = 0x8
	// Bit mask of PTXFELVL field.
	OTG_HS_GAHBCFG_PTXFELVL_Msk = 0x100
	// Bit PTXFELVL.
	OTG_HS_GAHBCFG_PTXFELVL = 0x100

	// GUSBCFG: This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
	// Position of TOCAL field.
	OTG_HS_GUSBCFG_TOCAL_Pos = 0x0
	// Bit mask of TOCAL field.
	OTG_HS_GUSBCFG_TOCAL_Msk = 0x7
	// Position of PHYSEL field.
	OTG_HS_GUSBCFG_PHYSEL_Pos = 0x6
	// Bit mask of PHYSEL field.
	OTG_HS_GUSBCFG_PHYSEL_Msk = 0x40
	// Bit PHYSEL.
	OTG_HS_GUSBCFG_PHYSEL = 0x40
	// Position of SRPCAP field.
	OTG_HS_GUSBCFG_SRPCAP_Pos = 0x8
	// Bit mask of SRPCAP field.
	OTG_HS_GUSBCFG_SRPCAP_Msk = 0x100
	// Bit SRPCAP.
	OTG_HS_GUSBCFG_SRPCAP = 0x100
	// Position of HNPCAP field.
	OTG_HS_GUSBCFG_HNPCAP_Pos = 0x9
	// Bit mask of HNPCAP field.
	OTG_HS_GUSBCFG_HNPCAP_Msk = 0x200
	// Bit HNPCAP.
	OTG_HS_GUSBCFG_HNPCAP = 0x200
	// Position of TRDT field.
	OTG_HS_GUSBCFG_TRDT_Pos = 0xa
	// Bit mask of TRDT field.
	OTG_HS_GUSBCFG_TRDT_Msk = 0x3c00
	// Position of PHYLPC field.
	OTG_HS_GUSBCFG_PHYLPC_Pos = 0xf
	// Bit mask of PHYLPC field.
	OTG_HS_GUSBCFG_PHYLPC_Msk = 0x8000
	// Bit PHYLPC.
	OTG_HS_GUSBCFG_PHYLPC = 0x8000
	// Position of TSDPS field.
	OTG_HS_GUSBCFG_TSDPS_Pos = 0x16
	// Bit mask of TSDPS field.
	OTG_HS_GUSBCFG_TSDPS_Msk = 0x400000
	// Bit TSDPS.
	OTG_HS_GUSBCFG_TSDPS = 0x400000
	// Position of FHMOD field.
	OTG_HS_GUSBCFG_FHMOD_Pos = 0x1d
	// Bit mask of FHMOD field.
	OTG_HS_GUSBCFG_FHMOD_Msk = 0x20000000
	// Bit FHMOD.
	OTG_HS_GUSBCFG_FHMOD = 0x20000000
	// Position of FDMOD field.
	OTG_HS_GUSBCFG_FDMOD_Pos = 0x1e
	// Bit mask of FDMOD field.
	OTG_HS_GUSBCFG_FDMOD_Msk = 0x40000000
	// Bit FDMOD.
	OTG_HS_GUSBCFG_FDMOD = 0x40000000

	// GRSTCTL: The application uses this register to reset various hardware features inside the core.
	// Position of CSRST field.
	OTG_HS_GRSTCTL_CSRST_Pos = 0x0
	// Bit mask of CSRST field.
	OTG_HS_GRSTCTL_CSRST_Msk = 0x1
	// Bit CSRST.
	OTG_HS_GRSTCTL_CSRST = 0x1
	// Position of PSRST field.
	OTG_HS_GRSTCTL_PSRST_Pos = 0x1
	// Bit mask of PSRST field.
	OTG_HS_GRSTCTL_PSRST_Msk = 0x2
	// Bit PSRST.
	OTG_HS_GRSTCTL_PSRST = 0x2
	// Position of FSRST field.
	OTG_HS_GRSTCTL_FSRST_Pos = 0x2
	// Bit mask of FSRST field.
	OTG_HS_GRSTCTL_FSRST_Msk = 0x4
	// Bit FSRST.
	OTG_HS_GRSTCTL_FSRST = 0x4
	// Position of RXFFLSH field.
	OTG_HS_GRSTCTL_RXFFLSH_Pos = 0x4
	// Bit mask of RXFFLSH field.
	OTG_HS_GRSTCTL_RXFFLSH_Msk = 0x10
	// Bit RXFFLSH.
	OTG_HS_GRSTCTL_RXFFLSH = 0x10
	// Position of TXFFLSH field.
	OTG_HS_GRSTCTL_TXFFLSH_Pos = 0x5
	// Bit mask of TXFFLSH field.
	OTG_HS_GRSTCTL_TXFFLSH_Msk = 0x20
	// Bit TXFFLSH.
	OTG_HS_GRSTCTL_TXFFLSH = 0x20
	// Position of TXFNUM field.
	OTG_HS_GRSTCTL_TXFNUM_Pos = 0x6
	// Bit mask of TXFNUM field.
	OTG_HS_GRSTCTL_TXFNUM_Msk = 0x7c0
	// Position of DMAREQ field.
	OTG_HS_GRSTCTL_DMAREQ_Pos = 0x1e
	// Bit mask of DMAREQ field.
	OTG_HS_GRSTCTL_DMAREQ_Msk = 0x40000000
	// Bit DMAREQ.
	OTG_HS_GRSTCTL_DMAREQ = 0x40000000
	// Position of AHBIDL field.
	OTG_HS_GRSTCTL_AHBIDL_Pos = 0x1f
	// Bit mask of AHBIDL field.
	OTG_HS_GRSTCTL_AHBIDL_Msk = 0x80000000
	// Bit AHBIDL.
	OTG_HS_GRSTCTL_AHBIDL = 0x80000000

	// GINTSTS: This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
	// Position of CMOD field.
	OTG_HS_GINTSTS_CMOD_Pos = 0x0
	// Bit mask of CMOD field.
	OTG_HS_GINTSTS_CMOD_Msk = 0x1
	// Bit CMOD.
	OTG_HS_GINTSTS_CMOD = 0x1
	// Position of MMIS field.
	OTG_HS_GINTSTS_MMIS_Pos = 0x1
	// Bit mask of MMIS field.
	OTG_HS_GINTSTS_MMIS_Msk = 0x2
	// Bit MMIS.
	OTG_HS_GINTSTS_MMIS = 0x2
	// Position of OTGINT field.
	OTG_HS_GINTSTS_OTGINT_Pos = 0x2
	// Bit mask of OTGINT field.
	OTG_HS_GINTSTS_OTGINT_Msk = 0x4
	// Bit OTGINT.
	OTG_HS_GINTSTS_OTGINT = 0x4
	// Position of SOF field.
	OTG_HS_GINTSTS_SOF_Pos = 0x3
	// Bit mask of SOF field.
	OTG_HS_GINTSTS_SOF_Msk = 0x8
	// Bit SOF.
	OTG_HS_GINTSTS_SOF = 0x8
	// Position of RXFLVL field.
	OTG_HS_GINTSTS_RXFLVL_Pos = 0x4
	// Bit mask of RXFLVL field.
	OTG_HS_GINTSTS_RXFLVL_Msk = 0x10
	// Bit RXFLVL.
	OTG_HS_GINTSTS_RXFLVL = 0x10
	// Position of NPTXFE field.
	OTG_HS_GINTSTS_NPTXFE_Pos = 0x5
	// Bit mask of NPTXFE field.
	OTG_HS_GINTSTS_NPTXFE_Msk = 0x20
	// Bit NPTXFE.
	OTG_HS_GINTSTS_NPTXFE = 0x20
	// Position of GINAKEFF field.
	OTG_HS_GINTSTS_GINAKEFF_Pos = 0x6
	// Bit mask of GINAKEFF field.
	OTG_HS_GINTSTS_GINAKEFF_Msk = 0x40
	// Bit GINAKEFF.
	OTG_HS_GINTSTS_GINAKEFF = 0x40
	// Position of GONAKEFF field.
	OTG_HS_GINTSTS_GONAKEFF_Pos = 0x7
	// Bit mask of GONAKEFF field.
	OTG_HS_GINTSTS_GONAKEFF_Msk = 0x80
	// Bit GONAKEFF.
	OTG_HS_GINTSTS_GONAKEFF = 0x80
	// Position of ESUSP field.
	OTG_HS_GINTSTS_ESUSP_Pos = 0xa
	// Bit mask of ESUSP field.
	OTG_HS_GINTSTS_ESUSP_Msk = 0x400
	// Bit ESUSP.
	OTG_HS_GINTSTS_ESUSP = 0x400
	// Position of USBSUSP field.
	OTG_HS_GINTSTS_USBSUSP_Pos = 0xb
	// Bit mask of USBSUSP field.
	OTG_HS_GINTSTS_USBSUSP_Msk = 0x800
	// Bit USBSUSP.
	OTG_HS_GINTSTS_USBSUSP = 0x800
	// Position of USBRST field.
	OTG_HS_GINTSTS_USBRST_Pos = 0xc
	// Bit mask of USBRST field.
	OTG_HS_GINTSTS_USBRST_Msk = 0x1000
	// Bit USBRST.
	OTG_HS_GINTSTS_USBRST = 0x1000
	// Position of ENUMDNE field.
	OTG_HS_GINTSTS_ENUMDNE_Pos = 0xd
	// Bit mask of ENUMDNE field.
	OTG_HS_GINTSTS_ENUMDNE_Msk = 0x2000
	// Bit ENUMDNE.
	OTG_HS_GINTSTS_ENUMDNE = 0x2000
	// Position of ISOODRP field.
	OTG_HS_GINTSTS_ISOODRP_Pos = 0xe
	// Bit mask of ISOODRP field.
	OTG_HS_GINTSTS_ISOODRP_Msk = 0x4000
	// Bit ISOODRP.
	OTG_HS_GINTSTS_ISOODRP = 0x4000
	// Position of EOPF field.
	OTG_HS_GINTSTS_EOPF_Pos = 0xf
	// Bit mask of EOPF field.
	OTG_HS_GINTSTS_EOPF_Msk = 0x8000
	// Bit EOPF.
	OTG_HS_GINTSTS_EOPF = 0x8000
	// Position of IEPINT field.
	OTG_HS_GINTSTS_IEPINT_Pos = 0x12
	// Bit mask of IEPINT field.
	OTG_HS_GINTSTS_IEPINT_Msk = 0x40000
	// Bit IEPINT.
	OTG_HS_GINTSTS_IEPINT = 0x40000
	// Position of OEPINT field.
	OTG_HS_GINTSTS_OEPINT_Pos = 0x13
	// Bit mask of OEPINT field.
	OTG_HS_GINTSTS_OEPINT_Msk = 0x80000
	// Bit OEPINT.
	OTG_HS_GINTSTS_OEPINT = 0x80000
	// Position of IISOIXFR field.
	OTG_HS_GINTSTS_IISOIXFR_Pos = 0x14
	// Bit mask of IISOIXFR field.
	OTG_HS_GINTSTS_IISOIXFR_Msk = 0x100000
	// Bit IISOIXFR.
	OTG_HS_GINTSTS_IISOIXFR = 0x100000
	// Position of IPXFR field.
	OTG_HS_GINTSTS_IPXFR_Pos = 0x15
	// Bit mask of IPXFR field.
	OTG_HS_GINTSTS_IPXFR_Msk = 0x200000
	// Bit IPXFR.
	OTG_HS_GINTSTS_IPXFR = 0x200000
	// Position of DATAFSUSP field.
	OTG_HS_GINTSTS_DATAFSUSP_Pos = 0x16
	// Bit mask of DATAFSUSP field.
	OTG_HS_GINTSTS_DATAFSUSP_Msk = 0x400000
	// Bit DATAFSUSP.
	OTG_HS_GINTSTS_DATAFSUSP = 0x400000
	// Position of RSTDET field.
	OTG_HS_GINTSTS_RSTDET_Pos = 0x17
	// Bit mask of RSTDET field.
	OTG_HS_GINTSTS_RSTDET_Msk = 0x800000
	// Bit RSTDET.
	OTG_HS_GINTSTS_RSTDET = 0x800000
	// Position of HPRTINT field.
	OTG_HS_GINTSTS_HPRTINT_Pos = 0x18
	// Bit mask of HPRTINT field.
	OTG_HS_GINTSTS_HPRTINT_Msk = 0x1000000
	// Bit HPRTINT.
	OTG_HS_GINTSTS_HPRTINT = 0x1000000
	// Position of HCINT field.
	OTG_HS_GINTSTS_HCINT_Pos = 0x19
	// Bit mask of HCINT field.
	OTG_HS_GINTSTS_HCINT_Msk = 0x2000000
	// Bit HCINT.
	OTG_HS_GINTSTS_HCINT = 0x2000000
	// Position of PTXFE field.
	OTG_HS_GINTSTS_PTXFE_Pos = 0x1a
	// Bit mask of PTXFE field.
	OTG_HS_GINTSTS_PTXFE_Msk = 0x4000000
	// Bit PTXFE.
	OTG_HS_GINTSTS_PTXFE = 0x4000000
	// Position of LPMINT field.
	OTG_HS_GINTSTS_LPMINT_Pos = 0x1b
	// Bit mask of LPMINT field.
	OTG_HS_GINTSTS_LPMINT_Msk = 0x8000000
	// Bit LPMINT.
	OTG_HS_GINTSTS_LPMINT = 0x8000000
	// Position of CIDSCHG field.
	OTG_HS_GINTSTS_CIDSCHG_Pos = 0x1c
	// Bit mask of CIDSCHG field.
	OTG_HS_GINTSTS_CIDSCHG_Msk = 0x10000000
	// Bit CIDSCHG.
	OTG_HS_GINTSTS_CIDSCHG = 0x10000000
	// Position of DISCINT field.
	OTG_HS_GINTSTS_DISCINT_Pos = 0x1d
	// Bit mask of DISCINT field.
	OTG_HS_GINTSTS_DISCINT_Msk = 0x20000000
	// Bit DISCINT.
	OTG_HS_GINTSTS_DISCINT = 0x20000000
	// Position of SRQINT field.
	OTG_HS_GINTSTS_SRQINT_Pos = 0x1e
	// Bit mask of SRQINT field.
	OTG_HS_GINTSTS_SRQINT_Msk = 0x40000000
	// Bit SRQINT.
	OTG_HS_GINTSTS_SRQINT = 0x40000000
	// Position of WKUPINT field.
	OTG_HS_GINTSTS_WKUPINT_Pos = 0x1f
	// Bit mask of WKUPINT field.
	OTG_HS_GINTSTS_WKUPINT_Msk = 0x80000000
	// Bit WKUPINT.
	OTG_HS_GINTSTS_WKUPINT = 0x80000000

	// GINTMSK: This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set.
	// Position of MMISM field.
	OTG_HS_GINTMSK_MMISM_Pos = 0x1
	// Bit mask of MMISM field.
	OTG_HS_GINTMSK_MMISM_Msk = 0x2
	// Bit MMISM.
	OTG_HS_GINTMSK_MMISM = 0x2
	// Position of OTGINT field.
	OTG_HS_GINTMSK_OTGINT_Pos = 0x2
	// Bit mask of OTGINT field.
	OTG_HS_GINTMSK_OTGINT_Msk = 0x4
	// Bit OTGINT.
	OTG_HS_GINTMSK_OTGINT = 0x4
	// Position of SOFM field.
	OTG_HS_GINTMSK_SOFM_Pos = 0x3
	// Bit mask of SOFM field.
	OTG_HS_GINTMSK_SOFM_Msk = 0x8
	// Bit SOFM.
	OTG_HS_GINTMSK_SOFM = 0x8
	// Position of RXFLVLM field.
	OTG_HS_GINTMSK_RXFLVLM_Pos = 0x4
	// Bit mask of RXFLVLM field.
	OTG_HS_GINTMSK_RXFLVLM_Msk = 0x10
	// Bit RXFLVLM.
	OTG_HS_GINTMSK_RXFLVLM = 0x10
	// Position of NPTXFEM field.
	OTG_HS_GINTMSK_NPTXFEM_Pos = 0x5
	// Bit mask of NPTXFEM field.
	OTG_HS_GINTMSK_NPTXFEM_Msk = 0x20
	// Bit NPTXFEM.
	OTG_HS_GINTMSK_NPTXFEM = 0x20
	// Position of GINAKEFFM field.
	OTG_HS_GINTMSK_GINAKEFFM_Pos = 0x6
	// Bit mask of GINAKEFFM field.
	OTG_HS_GINTMSK_GINAKEFFM_Msk = 0x40
	// Bit GINAKEFFM.
	OTG_HS_GINTMSK_GINAKEFFM = 0x40
	// Position of GONAKEFFM field.
	OTG_HS_GINTMSK_GONAKEFFM_Pos = 0x7
	// Bit mask of GONAKEFFM field.
	OTG_HS_GINTMSK_GONAKEFFM_Msk = 0x80
	// Bit GONAKEFFM.
	OTG_HS_GINTMSK_GONAKEFFM = 0x80
	// Position of ESUSPM field.
	OTG_HS_GINTMSK_ESUSPM_Pos = 0xa
	// Bit mask of ESUSPM field.
	OTG_HS_GINTMSK_ESUSPM_Msk = 0x400
	// Bit ESUSPM.
	OTG_HS_GINTMSK_ESUSPM = 0x400
	// Position of USBSUSPM field.
	OTG_HS_GINTMSK_USBSUSPM_Pos = 0xb
	// Bit mask of USBSUSPM field.
	OTG_HS_GINTMSK_USBSUSPM_Msk = 0x800
	// Bit USBSUSPM.
	OTG_HS_GINTMSK_USBSUSPM = 0x800
	// Position of USBRST field.
	OTG_HS_GINTMSK_USBRST_Pos = 0xc
	// Bit mask of USBRST field.
	OTG_HS_GINTMSK_USBRST_Msk = 0x1000
	// Bit USBRST.
	OTG_HS_GINTMSK_USBRST = 0x1000
	// Position of ENUMDNEM field.
	OTG_HS_GINTMSK_ENUMDNEM_Pos = 0xd
	// Bit mask of ENUMDNEM field.
	OTG_HS_GINTMSK_ENUMDNEM_Msk = 0x2000
	// Bit ENUMDNEM.
	OTG_HS_GINTMSK_ENUMDNEM = 0x2000
	// Position of ISOODRPM field.
	OTG_HS_GINTMSK_ISOODRPM_Pos = 0xe
	// Bit mask of ISOODRPM field.
	OTG_HS_GINTMSK_ISOODRPM_Msk = 0x4000
	// Bit ISOODRPM.
	OTG_HS_GINTMSK_ISOODRPM = 0x4000
	// Position of EOPFM field.
	OTG_HS_GINTMSK_EOPFM_Pos = 0xf
	// Bit mask of EOPFM field.
	OTG_HS_GINTMSK_EOPFM_Msk = 0x8000
	// Bit EOPFM.
	OTG_HS_GINTMSK_EOPFM = 0x8000
	// Position of IEPINT field.
	OTG_HS_GINTMSK_IEPINT_Pos = 0x12
	// Bit mask of IEPINT field.
	OTG_HS_GINTMSK_IEPINT_Msk = 0x40000
	// Bit IEPINT.
	OTG_HS_GINTMSK_IEPINT = 0x40000
	// Position of OEPINT field.
	OTG_HS_GINTMSK_OEPINT_Pos = 0x13
	// Bit mask of OEPINT field.
	OTG_HS_GINTMSK_OEPINT_Msk = 0x80000
	// Bit OEPINT.
	OTG_HS_GINTMSK_OEPINT = 0x80000
	// Position of IISOIXFRM field.
	OTG_HS_GINTMSK_IISOIXFRM_Pos = 0x14
	// Bit mask of IISOIXFRM field.
	OTG_HS_GINTMSK_IISOIXFRM_Msk = 0x100000
	// Bit IISOIXFRM.
	OTG_HS_GINTMSK_IISOIXFRM = 0x100000
	// Position of IPXFRM field.
	OTG_HS_GINTMSK_IPXFRM_Pos = 0x15
	// Bit mask of IPXFRM field.
	OTG_HS_GINTMSK_IPXFRM_Msk = 0x200000
	// Bit IPXFRM.
	OTG_HS_GINTMSK_IPXFRM = 0x200000
	// Position of FSUSPM field.
	OTG_HS_GINTMSK_FSUSPM_Pos = 0x16
	// Bit mask of FSUSPM field.
	OTG_HS_GINTMSK_FSUSPM_Msk = 0x400000
	// Bit FSUSPM.
	OTG_HS_GINTMSK_FSUSPM = 0x400000
	// Position of RSTDETM field.
	OTG_HS_GINTMSK_RSTDETM_Pos = 0x17
	// Bit mask of RSTDETM field.
	OTG_HS_GINTMSK_RSTDETM_Msk = 0x800000
	// Bit RSTDETM.
	OTG_HS_GINTMSK_RSTDETM = 0x800000
	// Position of PRTIM field.
	OTG_HS_GINTMSK_PRTIM_Pos = 0x18
	// Bit mask of PRTIM field.
	OTG_HS_GINTMSK_PRTIM_Msk = 0x1000000
	// Bit PRTIM.
	OTG_HS_GINTMSK_PRTIM = 0x1000000
	// Position of HCIM field.
	OTG_HS_GINTMSK_HCIM_Pos = 0x19
	// Bit mask of HCIM field.
	OTG_HS_GINTMSK_HCIM_Msk = 0x2000000
	// Bit HCIM.
	OTG_HS_GINTMSK_HCIM = 0x2000000
	// Position of PTXFEM field.
	OTG_HS_GINTMSK_PTXFEM_Pos = 0x1a
	// Bit mask of PTXFEM field.
	OTG_HS_GINTMSK_PTXFEM_Msk = 0x4000000
	// Bit PTXFEM.
	OTG_HS_GINTMSK_PTXFEM = 0x4000000
	// Position of LPMINTM field.
	OTG_HS_GINTMSK_LPMINTM_Pos = 0x1b
	// Bit mask of LPMINTM field.
	OTG_HS_GINTMSK_LPMINTM_Msk = 0x8000000
	// Bit LPMINTM.
	OTG_HS_GINTMSK_LPMINTM = 0x8000000
	// Position of CIDSCHGM field.
	OTG_HS_GINTMSK_CIDSCHGM_Pos = 0x1c
	// Bit mask of CIDSCHGM field.
	OTG_HS_GINTMSK_CIDSCHGM_Msk = 0x10000000
	// Bit CIDSCHGM.
	OTG_HS_GINTMSK_CIDSCHGM = 0x10000000
	// Position of DISCINT field.
	OTG_HS_GINTMSK_DISCINT_Pos = 0x1d
	// Bit mask of DISCINT field.
	OTG_HS_GINTMSK_DISCINT_Msk = 0x20000000
	// Bit DISCINT.
	OTG_HS_GINTMSK_DISCINT = 0x20000000
	// Position of SRQIM field.
	OTG_HS_GINTMSK_SRQIM_Pos = 0x1e
	// Bit mask of SRQIM field.
	OTG_HS_GINTMSK_SRQIM_Msk = 0x40000000
	// Bit SRQIM.
	OTG_HS_GINTMSK_SRQIM = 0x40000000
	// Position of WUIM field.
	OTG_HS_GINTMSK_WUIM_Pos = 0x1f
	// Bit mask of WUIM field.
	OTG_HS_GINTMSK_WUIM_Msk = 0x80000000
	// Bit WUIM.
	OTG_HS_GINTMSK_WUIM = 0x80000000

	// GRXSTSR_DEVICE: This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
	// Position of EPNUM field.
	OTG_HS_GRXSTSR_DEVICE_EPNUM_Pos = 0x0
	// Bit mask of EPNUM field.
	OTG_HS_GRXSTSR_DEVICE_EPNUM_Msk = 0xf
	// Position of BCNT field.
	OTG_HS_GRXSTSR_DEVICE_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	OTG_HS_GRXSTSR_DEVICE_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	OTG_HS_GRXSTSR_DEVICE_DPID_Pos = 0xf
	// Bit mask of DPID field.
	OTG_HS_GRXSTSR_DEVICE_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	OTG_HS_GRXSTSR_DEVICE_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	OTG_HS_GRXSTSR_DEVICE_PKTSTS_Msk = 0x1e0000
	// Position of FRMNUM field.
	OTG_HS_GRXSTSR_DEVICE_FRMNUM_Pos = 0x15
	// Bit mask of FRMNUM field.
	OTG_HS_GRXSTSR_DEVICE_FRMNUM_Msk = 0x1e00000
	// Position of STSPHST field.
	OTG_HS_GRXSTSR_DEVICE_STSPHST_Pos = 0x1b
	// Bit mask of STSPHST field.
	OTG_HS_GRXSTSR_DEVICE_STSPHST_Msk = 0x8000000
	// Bit STSPHST.
	OTG_HS_GRXSTSR_DEVICE_STSPHST = 0x8000000

	// GRXSTSR_HOST: This description is for register GRXSTSR in Host mode
	// Position of CHNUM field.
	OTG_HS_GRXSTSR_HOST_CHNUM_Pos = 0x0
	// Bit mask of CHNUM field.
	OTG_HS_GRXSTSR_HOST_CHNUM_Msk = 0xf
	// Position of BCNT field.
	OTG_HS_GRXSTSR_HOST_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	OTG_HS_GRXSTSR_HOST_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	OTG_HS_GRXSTSR_HOST_DPID_Pos = 0xf
	// Bit mask of DPID field.
	OTG_HS_GRXSTSR_HOST_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	OTG_HS_GRXSTSR_HOST_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	OTG_HS_GRXSTSR_HOST_PKTSTS_Msk = 0x1e0000

	// GRXSTSP_DEVICE: This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in GINTSTS) is asserted.
	// Position of EPNUM field.
	OTG_HS_GRXSTSP_DEVICE_EPNUM_Pos = 0x0
	// Bit mask of EPNUM field.
	OTG_HS_GRXSTSP_DEVICE_EPNUM_Msk = 0xf
	// Position of BCNT field.
	OTG_HS_GRXSTSP_DEVICE_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	OTG_HS_GRXSTSP_DEVICE_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	OTG_HS_GRXSTSP_DEVICE_DPID_Pos = 0xf
	// Bit mask of DPID field.
	OTG_HS_GRXSTSP_DEVICE_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	OTG_HS_GRXSTSP_DEVICE_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	OTG_HS_GRXSTSP_DEVICE_PKTSTS_Msk = 0x1e0000
	// Position of FRMNUM field.
	OTG_HS_GRXSTSP_DEVICE_FRMNUM_Pos = 0x15
	// Bit mask of FRMNUM field.
	OTG_HS_GRXSTSP_DEVICE_FRMNUM_Msk = 0x1e00000
	// Position of STSPHST field.
	OTG_HS_GRXSTSP_DEVICE_STSPHST_Pos = 0x1b
	// Bit mask of STSPHST field.
	OTG_HS_GRXSTSP_DEVICE_STSPHST_Msk = 0x8000000
	// Bit STSPHST.
	OTG_HS_GRXSTSP_DEVICE_STSPHST = 0x8000000

	// GRXSTSP_HOST: This description is for register GRXSTSP in HOST mode
	// Position of CHNUM field.
	OTG_HS_GRXSTSP_HOST_CHNUM_Pos = 0x0
	// Bit mask of CHNUM field.
	OTG_HS_GRXSTSP_HOST_CHNUM_Msk = 0xf
	// Position of BCNT field.
	OTG_HS_GRXSTSP_HOST_BCNT_Pos = 0x4
	// Bit mask of BCNT field.
	OTG_HS_GRXSTSP_HOST_BCNT_Msk = 0x7ff0
	// Position of DPID field.
	OTG_HS_GRXSTSP_HOST_DPID_Pos = 0xf
	// Bit mask of DPID field.
	OTG_HS_GRXSTSP_HOST_DPID_Msk = 0x18000
	// Position of PKTSTS field.
	OTG_HS_GRXSTSP_HOST_PKTSTS_Pos = 0x11
	// Bit mask of PKTSTS field.
	OTG_HS_GRXSTSP_HOST_PKTSTS_Msk = 0x1e0000

	// GRXFSIZ: The application can program the RAM size that must be allocated to the Rx FIFO.
	// Position of RXFD field.
	OTG_HS_GRXFSIZ_RXFD_Pos = 0x0
	// Bit mask of RXFD field.
	OTG_HS_GRXFSIZ_RXFD_Msk = 0xffff

	// HNPTXFSIZ: Host mode
	// Position of NPTXFSA field.
	OTG_HS_HNPTXFSIZ_NPTXFSA_Pos = 0x0
	// Bit mask of NPTXFSA field.
	OTG_HS_HNPTXFSIZ_NPTXFSA_Msk = 0xffff
	// Position of NPTXFD field.
	OTG_HS_HNPTXFSIZ_NPTXFD_Pos = 0x10
	// Bit mask of NPTXFD field.
	OTG_HS_HNPTXFSIZ_NPTXFD_Msk = 0xffff0000

	// HNPTXSTS: In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
	// Position of NPTXFSAV field.
	OTG_HS_HNPTXSTS_NPTXFSAV_Pos = 0x0
	// Bit mask of NPTXFSAV field.
	OTG_HS_HNPTXSTS_NPTXFSAV_Msk = 0xffff
	// Position of NPTQXSAV field.
	OTG_HS_HNPTXSTS_NPTQXSAV_Pos = 0x10
	// Bit mask of NPTQXSAV field.
	OTG_HS_HNPTXSTS_NPTQXSAV_Msk = 0xff0000
	// Position of NPTXQTOP field.
	OTG_HS_HNPTXSTS_NPTXQTOP_Pos = 0x18
	// Bit mask of NPTXQTOP field.
	OTG_HS_HNPTXSTS_NPTXQTOP_Msk = 0x7f000000

	// GCCFG: OTG general core configuration register
	// Position of DCDET field.
	OTG_HS_GCCFG_DCDET_Pos = 0x0
	// Bit mask of DCDET field.
	OTG_HS_GCCFG_DCDET_Msk = 0x1
	// Bit DCDET.
	OTG_HS_GCCFG_DCDET = 0x1
	// Position of PDET field.
	OTG_HS_GCCFG_PDET_Pos = 0x1
	// Bit mask of PDET field.
	OTG_HS_GCCFG_PDET_Msk = 0x2
	// Bit PDET.
	OTG_HS_GCCFG_PDET = 0x2
	// Position of SDET field.
	OTG_HS_GCCFG_SDET_Pos = 0x2
	// Bit mask of SDET field.
	OTG_HS_GCCFG_SDET_Msk = 0x4
	// Bit SDET.
	OTG_HS_GCCFG_SDET = 0x4
	// Position of PS2DET field.
	OTG_HS_GCCFG_PS2DET_Pos = 0x3
	// Bit mask of PS2DET field.
	OTG_HS_GCCFG_PS2DET_Msk = 0x8
	// Bit PS2DET.
	OTG_HS_GCCFG_PS2DET = 0x8
	// Position of PWRDWN field.
	OTG_HS_GCCFG_PWRDWN_Pos = 0x10
	// Bit mask of PWRDWN field.
	OTG_HS_GCCFG_PWRDWN_Msk = 0x10000
	// Bit PWRDWN.
	OTG_HS_GCCFG_PWRDWN = 0x10000
	// Position of BCDEN field.
	OTG_HS_GCCFG_BCDEN_Pos = 0x11
	// Bit mask of BCDEN field.
	OTG_HS_GCCFG_BCDEN_Msk = 0x20000
	// Bit BCDEN.
	OTG_HS_GCCFG_BCDEN = 0x20000
	// Position of DCDEN field.
	OTG_HS_GCCFG_DCDEN_Pos = 0x12
	// Bit mask of DCDEN field.
	OTG_HS_GCCFG_DCDEN_Msk = 0x40000
	// Bit DCDEN.
	OTG_HS_GCCFG_DCDEN = 0x40000
	// Position of PDEN field.
	OTG_HS_GCCFG_PDEN_Pos = 0x13
	// Bit mask of PDEN field.
	OTG_HS_GCCFG_PDEN_Msk = 0x80000
	// Bit PDEN.
	OTG_HS_GCCFG_PDEN = 0x80000
	// Position of SDEN field.
	OTG_HS_GCCFG_SDEN_Pos = 0x14
	// Bit mask of SDEN field.
	OTG_HS_GCCFG_SDEN_Msk = 0x100000
	// Bit SDEN.
	OTG_HS_GCCFG_SDEN = 0x100000
	// Position of VBDEN field.
	OTG_HS_GCCFG_VBDEN_Pos = 0x15
	// Bit mask of VBDEN field.
	OTG_HS_GCCFG_VBDEN_Msk = 0x200000
	// Bit VBDEN.
	OTG_HS_GCCFG_VBDEN = 0x200000

	// CID: This is a register containing the Product ID as reset value.
	// Position of PRODUCT_ID field.
	OTG_HS_CID_PRODUCT_ID_Pos = 0x0
	// Bit mask of PRODUCT_ID field.
	OTG_HS_CID_PRODUCT_ID_Msk = 0xffffffff

	// GLPMCFG: OTG core LPM configuration register
	// Position of LPMEN field.
	OTG_HS_GLPMCFG_LPMEN_Pos = 0x0
	// Bit mask of LPMEN field.
	OTG_HS_GLPMCFG_LPMEN_Msk = 0x1
	// Bit LPMEN.
	OTG_HS_GLPMCFG_LPMEN = 0x1
	// Position of LPMACK field.
	OTG_HS_GLPMCFG_LPMACK_Pos = 0x1
	// Bit mask of LPMACK field.
	OTG_HS_GLPMCFG_LPMACK_Msk = 0x2
	// Bit LPMACK.
	OTG_HS_GLPMCFG_LPMACK = 0x2
	// Position of BESL field.
	OTG_HS_GLPMCFG_BESL_Pos = 0x2
	// Bit mask of BESL field.
	OTG_HS_GLPMCFG_BESL_Msk = 0x3c
	// Position of REMWAKE field.
	OTG_HS_GLPMCFG_REMWAKE_Pos = 0x6
	// Bit mask of REMWAKE field.
	OTG_HS_GLPMCFG_REMWAKE_Msk = 0x40
	// Bit REMWAKE.
	OTG_HS_GLPMCFG_REMWAKE = 0x40
	// Position of L1SSEN field.
	OTG_HS_GLPMCFG_L1SSEN_Pos = 0x7
	// Bit mask of L1SSEN field.
	OTG_HS_GLPMCFG_L1SSEN_Msk = 0x80
	// Bit L1SSEN.
	OTG_HS_GLPMCFG_L1SSEN = 0x80
	// Position of BESLTHRS field.
	OTG_HS_GLPMCFG_BESLTHRS_Pos = 0x8
	// Bit mask of BESLTHRS field.
	OTG_HS_GLPMCFG_BESLTHRS_Msk = 0xf00
	// Position of L1DSEN field.
	OTG_HS_GLPMCFG_L1DSEN_Pos = 0xc
	// Bit mask of L1DSEN field.
	OTG_HS_GLPMCFG_L1DSEN_Msk = 0x1000
	// Bit L1DSEN.
	OTG_HS_GLPMCFG_L1DSEN = 0x1000
	// Position of LPMRSP field.
	OTG_HS_GLPMCFG_LPMRSP_Pos = 0xd
	// Bit mask of LPMRSP field.
	OTG_HS_GLPMCFG_LPMRSP_Msk = 0x6000
	// Position of SLPSTS field.
	OTG_HS_GLPMCFG_SLPSTS_Pos = 0xf
	// Bit mask of SLPSTS field.
	OTG_HS_GLPMCFG_SLPSTS_Msk = 0x8000
	// Bit SLPSTS.
	OTG_HS_GLPMCFG_SLPSTS = 0x8000
	// Position of L1RSMOK field.
	OTG_HS_GLPMCFG_L1RSMOK_Pos = 0x10
	// Bit mask of L1RSMOK field.
	OTG_HS_GLPMCFG_L1RSMOK_Msk = 0x10000
	// Bit L1RSMOK.
	OTG_HS_GLPMCFG_L1RSMOK = 0x10000
	// Position of LPMCHIDX field.
	OTG_HS_GLPMCFG_LPMCHIDX_Pos = 0x11
	// Bit mask of LPMCHIDX field.
	OTG_HS_GLPMCFG_LPMCHIDX_Msk = 0x1e0000
	// Position of LPMRCNT field.
	OTG_HS_GLPMCFG_LPMRCNT_Pos = 0x15
	// Bit mask of LPMRCNT field.
	OTG_HS_GLPMCFG_LPMRCNT_Msk = 0xe00000
	// Position of SNDLPM field.
	OTG_HS_GLPMCFG_SNDLPM_Pos = 0x18
	// Bit mask of SNDLPM field.
	OTG_HS_GLPMCFG_SNDLPM_Msk = 0x1000000
	// Bit SNDLPM.
	OTG_HS_GLPMCFG_SNDLPM = 0x1000000
	// Position of LPMRCNTSTS field.
	OTG_HS_GLPMCFG_LPMRCNTSTS_Pos = 0x19
	// Bit mask of LPMRCNTSTS field.
	OTG_HS_GLPMCFG_LPMRCNTSTS_Msk = 0xe000000
	// Position of ENBESL field.
	OTG_HS_GLPMCFG_ENBESL_Pos = 0x1c
	// Bit mask of ENBESL field.
	OTG_HS_GLPMCFG_ENBESL_Msk = 0x10000000
	// Bit ENBESL.
	OTG_HS_GLPMCFG_ENBESL = 0x10000000

	// HPTXFSIZ: OTG host periodic transmit FIFO size register
	// Position of PTXSA field.
	OTG_HS_HPTXFSIZ_PTXSA_Pos = 0x0
	// Bit mask of PTXSA field.
	OTG_HS_HPTXFSIZ_PTXSA_Msk = 0xffff
	// Position of PTXFSIZ field.
	OTG_HS_HPTXFSIZ_PTXFSIZ_Pos = 0x10
	// Bit mask of PTXFSIZ field.
	OTG_HS_HPTXFSIZ_PTXFSIZ_Msk = 0xffff0000

	// DIEPTXF1: OTG device IN endpoint transmit FIFO 1 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF1_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF1_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF1_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF1_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF2: OTG device IN endpoint transmit FIFO 2 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF2_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF2_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF2_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF2_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF3: OTG device IN endpoint transmit FIFO 3 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF3_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF3_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF3_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF3_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF4: OTG device IN endpoint transmit FIFO 4 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF4_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF4_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF4_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF4_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF5: OTG device IN endpoint transmit FIFO 5 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF5_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF5_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF5_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF5_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF6: OTG device IN endpoint transmit FIFO 6 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF6_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF6_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF6_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF6_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF7: OTG device IN endpoint transmit FIFO 7 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF7_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF7_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF7_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF7_INEPTXFD_Msk = 0xffff0000

	// DIEPTXF8: OTG device IN endpoint transmit FIFO 8 size register
	// Position of INEPTXSA field.
	OTG_HS_DIEPTXF8_INEPTXSA_Pos = 0x0
	// Bit mask of INEPTXSA field.
	OTG_HS_DIEPTXF8_INEPTXSA_Msk = 0xffff
	// Position of INEPTXFD field.
	OTG_HS_DIEPTXF8_INEPTXFD_Pos = 0x10
	// Bit mask of INEPTXFD field.
	OTG_HS_DIEPTXF8_INEPTXFD_Msk = 0xffff0000

	// HCFG: This register configures the core after power-on. Do not make changes to this register after initializing the host.
	// Position of FSLSPCS field.
	OTG_HS_HCFG_FSLSPCS_Pos = 0x0
	// Bit mask of FSLSPCS field.
	OTG_HS_HCFG_FSLSPCS_Msk = 0x3
	// Position of FSLSS field.
	OTG_HS_HCFG_FSLSS_Pos = 0x2
	// Bit mask of FSLSS field.
	OTG_HS_HCFG_FSLSS_Msk = 0x4
	// Bit FSLSS.
	OTG_HS_HCFG_FSLSS = 0x4

	// HFIR: This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
	// Position of FRIVL field.
	OTG_HS_HFIR_FRIVL_Pos = 0x0
	// Bit mask of FRIVL field.
	OTG_HS_HFIR_FRIVL_Msk = 0xffff
	// Position of RLDCTRL field.
	OTG_HS_HFIR_RLDCTRL_Pos = 0x10
	// Bit mask of RLDCTRL field.
	OTG_HS_HFIR_RLDCTRL_Msk = 0x10000
	// Bit RLDCTRL.
	OTG_HS_HFIR_RLDCTRL = 0x10000

	// HFNUM: This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
	// Position of FRNUM field.
	OTG_HS_HFNUM_FRNUM_Pos = 0x0
	// Bit mask of FRNUM field.
	OTG_HS_HFNUM_FRNUM_Msk = 0xffff
	// Position of FTREM field.
	OTG_HS_HFNUM_FTREM_Pos = 0x10
	// Bit mask of FTREM field.
	OTG_HS_HFNUM_FTREM_Msk = 0xffff0000

	// HPTXSTS: This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
	// Position of PTXFSAVL field.
	OTG_HS_HPTXSTS_PTXFSAVL_Pos = 0x0
	// Bit mask of PTXFSAVL field.
	OTG_HS_HPTXSTS_PTXFSAVL_Msk = 0xffff
	// Position of PTXQSAV field.
	OTG_HS_HPTXSTS_PTXQSAV_Pos = 0x10
	// Bit mask of PTXQSAV field.
	OTG_HS_HPTXSTS_PTXQSAV_Msk = 0xff0000
	// Position of PTXQTOP field.
	OTG_HS_HPTXSTS_PTXQTOP_Pos = 0x18
	// Bit mask of PTXQTOP field.
	OTG_HS_HPTXSTS_PTXQTOP_Msk = 0xff000000

	// HAINT: When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
	// Position of HAINT field.
	OTG_HS_HAINT_HAINT_Pos = 0x0
	// Bit mask of HAINT field.
	OTG_HS_HAINT_HAINT_Msk = 0xffff

	// HAINTMSK: The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
	// Position of HAINTM field.
	OTG_HS_HAINTMSK_HAINTM_Pos = 0x0
	// Bit mask of HAINTM field.
	OTG_HS_HAINTMSK_HAINTM_Msk = 0xffff

	// HPRT: This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
	// Position of PCSTS field.
	OTG_HS_HPRT_PCSTS_Pos = 0x0
	// Bit mask of PCSTS field.
	OTG_HS_HPRT_PCSTS_Msk = 0x1
	// Bit PCSTS.
	OTG_HS_HPRT_PCSTS = 0x1
	// Position of PCDET field.
	OTG_HS_HPRT_PCDET_Pos = 0x1
	// Bit mask of PCDET field.
	OTG_HS_HPRT_PCDET_Msk = 0x2
	// Bit PCDET.
	OTG_HS_HPRT_PCDET = 0x2
	// Position of PENA field.
	OTG_HS_HPRT_PENA_Pos = 0x2
	// Bit mask of PENA field.
	OTG_HS_HPRT_PENA_Msk = 0x4
	// Bit PENA.
	OTG_HS_HPRT_PENA = 0x4
	// Position of PENCHNG field.
	OTG_HS_HPRT_PENCHNG_Pos = 0x3
	// Bit mask of PENCHNG field.
	OTG_HS_HPRT_PENCHNG_Msk = 0x8
	// Bit PENCHNG.
	OTG_HS_HPRT_PENCHNG = 0x8
	// Position of POCA field.
	OTG_HS_HPRT_POCA_Pos = 0x4
	// Bit mask of POCA field.
	OTG_HS_HPRT_POCA_Msk = 0x10
	// Bit POCA.
	OTG_HS_HPRT_POCA = 0x10
	// Position of POCCHNG field.
	OTG_HS_HPRT_POCCHNG_Pos = 0x5
	// Bit mask of POCCHNG field.
	OTG_HS_HPRT_POCCHNG_Msk = 0x20
	// Bit POCCHNG.
	OTG_HS_HPRT_POCCHNG = 0x20
	// Position of PRES field.
	OTG_HS_HPRT_PRES_Pos = 0x6
	// Bit mask of PRES field.
	OTG_HS_HPRT_PRES_Msk = 0x40
	// Bit PRES.
	OTG_HS_HPRT_PRES = 0x40
	// Position of PSUSP field.
	OTG_HS_HPRT_PSUSP_Pos = 0x7
	// Bit mask of PSUSP field.
	OTG_HS_HPRT_PSUSP_Msk = 0x80
	// Bit PSUSP.
	OTG_HS_HPRT_PSUSP = 0x80
	// Position of PRST field.
	OTG_HS_HPRT_PRST_Pos = 0x8
	// Bit mask of PRST field.
	OTG_HS_HPRT_PRST_Msk = 0x100
	// Bit PRST.
	OTG_HS_HPRT_PRST = 0x100
	// Position of PLSTS field.
	OTG_HS_HPRT_PLSTS_Pos = 0xa
	// Bit mask of PLSTS field.
	OTG_HS_HPRT_PLSTS_Msk = 0xc00
	// Position of PPWR field.
	OTG_HS_HPRT_PPWR_Pos = 0xc
	// Bit mask of PPWR field.
	OTG_HS_HPRT_PPWR_Msk = 0x1000
	// Bit PPWR.
	OTG_HS_HPRT_PPWR = 0x1000
	// Position of PTCTL field.
	OTG_HS_HPRT_PTCTL_Pos = 0xd
	// Bit mask of PTCTL field.
	OTG_HS_HPRT_PTCTL_Msk = 0x1e000
	// Position of PSPD field.
	OTG_HS_HPRT_PSPD_Pos = 0x11
	// Bit mask of PSPD field.
	OTG_HS_HPRT_PSPD_Msk = 0x60000

	// HCCHAR0: OTG host channel 0 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR0_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR0_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR0_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR0_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR0_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR0_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR0_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR0_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR0_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR0_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR0_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR0_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR0_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR0_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR0_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR0_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR0_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR0_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR0_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR0_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR0_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR0_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR0_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR0_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR0_CHENA = 0x80000000

	// HCSPLT0: OTG host channel 0 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT0_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT0_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT0_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT0_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT0_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT0_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT0_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT0_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT0_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT0_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT0_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT0_SPLITEN = 0x80000000

	// HCINT0: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT0_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT0_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT0_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT0_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT0_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT0_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT0_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT0_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT0_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT0_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT0_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT0_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT0_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT0_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT0_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT0_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT0_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT0_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT0_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT0_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT0_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT0_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT0_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT0_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT0_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT0_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT0_DTERR = 0x400

	// HCINTMSK0: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK0_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK0_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK0_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK0_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK0_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK0_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK0_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK0_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK0_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK0_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK0_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK0_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK0_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK0_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK0_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK0_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK0_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK0_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK0_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK0_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK0_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK0_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK0_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK0_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK0_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK0_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK0_DTERRM = 0x400

	// HCTSIZ0: OTG host channel 0 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ0_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ0_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ0_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ0_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ0_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ0_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ0_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ0_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ0_DOPNG = 0x80000000

	// HCDMA0: OTG host channel 0 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA0_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA0_DMAADDR_Msk = 0xffffffff

	// HCCHAR1: OTG host channel 1 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR1_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR1_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR1_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR1_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR1_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR1_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR1_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR1_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR1_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR1_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR1_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR1_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR1_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR1_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR1_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR1_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR1_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR1_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR1_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR1_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR1_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR1_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR1_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR1_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR1_CHENA = 0x80000000

	// HCSPLT1: OTG host channel 1 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT1_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT1_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT1_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT1_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT1_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT1_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT1_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT1_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT1_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT1_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT1_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT1_SPLITEN = 0x80000000

	// HCINT1_DEVICE: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT1_DEVICE_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT1_DEVICE_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT1_DEVICE_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT1_DEVICE_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT1_DEVICE_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT1_DEVICE_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT1_DEVICE_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT1_DEVICE_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT1_DEVICE_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT1_DEVICE_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT1_DEVICE_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT1_DEVICE_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT1_DEVICE_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT1_DEVICE_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT1_DEVICE_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT1_DEVICE_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT1_DEVICE_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT1_DEVICE_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT1_DEVICE_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT1_DEVICE_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT1_DEVICE_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT1_DEVICE_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT1_DEVICE_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT1_DEVICE_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT1_DEVICE_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT1_DEVICE_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT1_DEVICE_DTERR = 0x400

	// HCINTMSK1: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK1_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK1_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK1_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK1_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK1_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK1_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK1_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK1_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK1_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK1_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK1_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK1_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK1_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK1_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK1_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK1_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK1_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK1_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK1_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK1_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK1_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK1_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK1_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK1_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK1_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK1_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK1_DTERRM = 0x400

	// HCTSIZ1: OTG host channel 1 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ1_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ1_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ1_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ1_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ1_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ1_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ1_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ1_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ1_DOPNG = 0x80000000

	// HCDMA1: OTG host channel 1 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA1_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA1_DMAADDR_Msk = 0xffffffff

	// HCCHAR2: OTG host channel 2 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR2_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR2_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR2_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR2_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR2_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR2_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR2_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR2_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR2_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR2_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR2_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR2_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR2_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR2_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR2_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR2_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR2_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR2_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR2_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR2_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR2_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR2_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR2_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR2_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR2_CHENA = 0x80000000

	// HCSPLT2: OTG host channel 2 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT2_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT2_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT2_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT2_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT2_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT2_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT2_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT2_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT2_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT2_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT2_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT2_SPLITEN = 0x80000000

	// HCINT2: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT2_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT2_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT2_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT2_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT2_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT2_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT2_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT2_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT2_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT2_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT2_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT2_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT2_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT2_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT2_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT2_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT2_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT2_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT2_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT2_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT2_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT2_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT2_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT2_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT2_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT2_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT2_DTERR = 0x400

	// HCINTMSK2: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK2_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK2_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK2_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK2_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK2_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK2_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK2_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK2_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK2_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK2_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK2_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK2_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK2_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK2_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK2_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK2_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK2_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK2_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK2_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK2_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK2_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK2_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK2_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK2_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK2_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK2_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK2_DTERRM = 0x400

	// HCTSIZ2: OTG host channel 2 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ2_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ2_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ2_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ2_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ2_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ2_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ2_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ2_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ2_DOPNG = 0x80000000

	// HCDMA2: OTG host channel 2 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA2_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA2_DMAADDR_Msk = 0xffffffff

	// HCCHAR3: OTG host channel 3 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR3_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR3_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR3_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR3_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR3_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR3_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR3_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR3_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR3_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR3_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR3_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR3_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR3_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR3_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR3_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR3_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR3_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR3_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR3_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR3_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR3_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR3_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR3_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR3_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR3_CHENA = 0x80000000

	// HCSPLT3: OTG host channel 3 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT3_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT3_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT3_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT3_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT3_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT3_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT3_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT3_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT3_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT3_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT3_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT3_SPLITEN = 0x80000000

	// HCINT3: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT3_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT3_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT3_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT3_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT3_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT3_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT3_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT3_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT3_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT3_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT3_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT3_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT3_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT3_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT3_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT3_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT3_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT3_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT3_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT3_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT3_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT3_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT3_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT3_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT3_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT3_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT3_DTERR = 0x400

	// HCINTMSK3: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK3_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK3_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK3_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK3_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK3_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK3_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK3_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK3_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK3_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK3_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK3_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK3_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK3_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK3_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK3_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK3_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK3_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK3_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK3_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK3_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK3_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK3_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK3_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK3_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK3_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK3_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK3_DTERRM = 0x400

	// HCTSIZ3: OTG host channel 3 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ3_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ3_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ3_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ3_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ3_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ3_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ3_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ3_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ3_DOPNG = 0x80000000

	// HCDMA3: OTG host channel 3 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA3_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA3_DMAADDR_Msk = 0xffffffff

	// HCCHAR4: OTG host channel 4 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR4_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR4_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR4_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR4_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR4_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR4_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR4_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR4_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR4_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR4_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR4_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR4_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR4_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR4_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR4_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR4_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR4_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR4_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR4_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR4_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR4_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR4_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR4_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR4_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR4_CHENA = 0x80000000

	// HCSPLT4: OTG host channel 4 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT4_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT4_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT4_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT4_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT4_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT4_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT4_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT4_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT4_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT4_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT4_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT4_SPLITEN = 0x80000000

	// HCINT4: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT4_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT4_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT4_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT4_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT4_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT4_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT4_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT4_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT4_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT4_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT4_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT4_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT4_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT4_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT4_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT4_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT4_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT4_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT4_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT4_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT4_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT4_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT4_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT4_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT4_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT4_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT4_DTERR = 0x400

	// HCINTMSK4: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK4_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK4_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK4_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK4_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK4_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK4_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK4_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK4_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK4_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK4_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK4_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK4_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK4_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK4_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK4_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK4_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK4_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK4_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK4_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK4_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK4_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK4_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK4_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK4_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK4_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK4_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK4_DTERRM = 0x400

	// HCTSIZ4: OTG host channel 4 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ4_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ4_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ4_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ4_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ4_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ4_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ4_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ4_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ4_DOPNG = 0x80000000

	// HCDMA4: OTG host channel 4 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA4_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA4_DMAADDR_Msk = 0xffffffff

	// HCCHAR5: OTG host channel 5 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR5_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR5_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR5_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR5_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR5_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR5_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR5_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR5_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR5_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR5_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR5_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR5_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR5_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR5_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR5_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR5_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR5_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR5_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR5_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR5_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR5_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR5_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR5_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR5_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR5_CHENA = 0x80000000

	// HCSPLT5: OTG host channel 5 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT5_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT5_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT5_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT5_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT5_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT5_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT5_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT5_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT5_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT5_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT5_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT5_SPLITEN = 0x80000000

	// HCINT5: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT5_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT5_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT5_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT5_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT5_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT5_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT5_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT5_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT5_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT5_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT5_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT5_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT5_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT5_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT5_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT5_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT5_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT5_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT5_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT5_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT5_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT5_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT5_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT5_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT5_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT5_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT5_DTERR = 0x400

	// HCINTMSK5: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK5_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK5_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK5_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK5_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK5_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK5_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK5_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK5_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK5_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK5_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK5_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK5_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK5_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK5_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK5_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK5_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK5_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK5_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK5_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK5_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK5_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK5_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK5_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK5_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK5_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK5_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK5_DTERRM = 0x400

	// HCTSIZ5: OTG host channel 5 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ5_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ5_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ5_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ5_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ5_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ5_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ5_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ5_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ5_DOPNG = 0x80000000

	// HCDMA5: OTG host channel 5 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA5_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA5_DMAADDR_Msk = 0xffffffff

	// HCCHAR6: OTG host channel 6 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR6_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR6_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR6_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR6_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR6_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR6_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR6_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR6_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR6_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR6_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR6_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR6_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR6_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR6_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR6_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR6_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR6_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR6_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR6_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR6_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR6_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR6_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR6_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR6_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR6_CHENA = 0x80000000

	// HCSPLT6: OTG host channel 6 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT6_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT6_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT6_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT6_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT6_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT6_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT6_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT6_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT6_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT6_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT6_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT6_SPLITEN = 0x80000000

	// HCINT6: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT6_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT6_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT6_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT6_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT6_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT6_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT6_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT6_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT6_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT6_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT6_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT6_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT6_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT6_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT6_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT6_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT6_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT6_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT6_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT6_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT6_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT6_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT6_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT6_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT6_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT6_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT6_DTERR = 0x400

	// HCINTMSK6: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK6_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK6_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK6_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK6_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK6_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK6_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK6_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK6_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK6_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK6_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK6_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK6_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK6_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK6_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK6_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK6_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK6_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK6_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK6_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK6_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK6_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK6_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK6_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK6_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK6_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK6_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK6_DTERRM = 0x400

	// HCTSIZ6: OTG host channel 6 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ6_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ6_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ6_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ6_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ6_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ6_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ6_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ6_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ6_DOPNG = 0x80000000

	// HCDMA6: OTG host channel 6 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA6_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA6_DMAADDR_Msk = 0xffffffff

	// HCCHAR7: OTG host channel 7 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR7_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR7_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR7_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR7_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR7_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR7_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR7_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR7_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR7_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR7_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR7_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR7_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR7_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR7_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR7_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR7_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR7_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR7_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR7_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR7_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR7_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR7_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR7_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR7_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR7_CHENA = 0x80000000

	// HCSPLT7: OTG host channel 7 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT7_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT7_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT7_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT7_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT7_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT7_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT7_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT7_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT7_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT7_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT7_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT7_SPLITEN = 0x80000000

	// HCINT7: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT7_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT7_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT7_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT7_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT7_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT7_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT7_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT7_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT7_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT7_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT7_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT7_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT7_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT7_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT7_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT7_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT7_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT7_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT7_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT7_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT7_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT7_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT7_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT7_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT7_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT7_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT7_DTERR = 0x400

	// HCINTMSK7: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK7_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK7_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK7_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK7_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK7_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK7_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK7_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK7_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK7_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK7_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK7_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK7_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK7_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK7_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK7_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK7_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK7_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK7_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK7_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK7_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK7_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK7_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK7_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK7_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK7_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK7_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK7_DTERRM = 0x400

	// HCTSIZ7: OTG host channel 7 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ7_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ7_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ7_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ7_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ7_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ7_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ7_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ7_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ7_DOPNG = 0x80000000

	// HCDMA7: OTG host channel 7 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA7_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA7_DMAADDR_Msk = 0xffffffff

	// HCCHAR8: OTG host channel 8 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR8_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR8_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR8_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR8_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR8_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR8_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR8_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR8_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR8_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR8_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR8_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR8_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR8_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR8_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR8_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR8_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR8_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR8_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR8_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR8_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR8_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR8_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR8_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR8_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR8_CHENA = 0x80000000

	// HCSPLT8: OTG host channel 8 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT8_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT8_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT8_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT8_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT8_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT8_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT8_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT8_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT8_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT8_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT8_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT8_SPLITEN = 0x80000000

	// HCINT8: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT8_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT8_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT8_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT8_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT8_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT8_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT8_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT8_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT8_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT8_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT8_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT8_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT8_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT8_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT8_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT8_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT8_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT8_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT8_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT8_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT8_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT8_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT8_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT8_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT8_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT8_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT8_DTERR = 0x400

	// HCINTMSK8: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK8_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK8_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK8_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK8_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK8_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK8_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK8_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK8_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK8_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK8_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK8_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK8_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK8_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK8_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK8_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK8_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK8_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK8_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK8_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK8_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK8_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK8_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK8_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK8_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK8_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK8_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK8_DTERRM = 0x400

	// HCTSIZ8: OTG host channel 8 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ8_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ8_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ8_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ8_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ8_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ8_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ8_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ8_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ8_DOPNG = 0x80000000

	// HCDMA8: OTG host channel 8 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA8_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA8_DMAADDR_Msk = 0xffffffff

	// HCCHAR9: OTG host channel 9 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR9_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR9_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR9_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR9_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR9_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR9_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR9_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR9_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR9_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR9_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR9_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR9_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR9_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR9_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR9_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR9_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR9_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR9_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR9_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR9_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR9_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR9_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR9_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR9_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR9_CHENA = 0x80000000

	// HCSPLT9: OTG host channel 9 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT9_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT9_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT9_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT9_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT9_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT9_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT9_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT9_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT9_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT9_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT9_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT9_SPLITEN = 0x80000000

	// HCINT9: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT9_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT9_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT9_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT9_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT9_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT9_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT9_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT9_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT9_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT9_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT9_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT9_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT9_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT9_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT9_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT9_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT9_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT9_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT9_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT9_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT9_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT9_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT9_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT9_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT9_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT9_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT9_DTERR = 0x400

	// HCINTMSK9: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK9_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK9_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK9_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK9_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK9_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK9_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK9_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK9_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK9_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK9_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK9_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK9_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK9_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK9_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK9_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK9_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK9_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK9_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK9_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK9_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK9_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK9_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK9_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK9_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK9_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK9_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK9_DTERRM = 0x400

	// HCTSIZ9: OTG host channel 9 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ9_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ9_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ9_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ9_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ9_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ9_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ9_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ9_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ9_DOPNG = 0x80000000

	// HCDMA9: OTG host channel 9 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA9_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA9_DMAADDR_Msk = 0xffffffff

	// HCCHAR10: OTG host channel 10 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR10_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR10_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR10_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR10_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR10_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR10_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR10_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR10_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR10_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR10_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR10_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR10_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR10_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR10_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR10_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR10_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR10_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR10_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR10_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR10_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR10_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR10_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR10_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR10_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR10_CHENA = 0x80000000

	// HCSPLT10: OTG host channel 10 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT10_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT10_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT10_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT10_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT10_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT10_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT10_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT10_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT10_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT10_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT10_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT10_SPLITEN = 0x80000000

	// HCINT10: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT10_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT10_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT10_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT10_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT10_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT10_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT10_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT10_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT10_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT10_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT10_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT10_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT10_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT10_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT10_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT10_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT10_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT10_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT10_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT10_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT10_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT10_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT10_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT10_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT10_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT10_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT10_DTERR = 0x400

	// HCINTMSK10: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK10_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK10_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK10_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK10_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK10_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK10_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK10_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK10_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK10_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK10_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK10_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK10_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK10_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK10_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK10_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK10_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK10_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK10_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK10_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK10_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK10_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK10_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK10_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK10_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK10_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK10_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK10_DTERRM = 0x400

	// HCTSIZ10: OTG host channel 10 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ10_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ10_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ10_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ10_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ10_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ10_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ10_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ10_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ10_DOPNG = 0x80000000

	// HCDMA10: OTG host channel 10 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA10_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA10_DMAADDR_Msk = 0xffffffff

	// HCCHAR11: OTG host channel 11 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR11_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR11_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR11_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR11_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR11_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR11_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR11_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR11_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR11_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR11_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR11_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR11_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR11_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR11_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR11_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR11_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR11_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR11_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR11_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR11_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR11_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR11_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR11_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR11_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR11_CHENA = 0x80000000

	// HCSPLT11: OTG host channel 11 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT11_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT11_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT11_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT11_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT11_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT11_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT11_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT11_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT11_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT11_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT11_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT11_SPLITEN = 0x80000000

	// HCINT11: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT11_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT11_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT11_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT11_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT11_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT11_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT11_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT11_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT11_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT11_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT11_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT11_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT11_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT11_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT11_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT11_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT11_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT11_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT11_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT11_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT11_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT11_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT11_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT11_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT11_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT11_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT11_DTERR = 0x400

	// HCINTMSK11: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK11_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK11_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK11_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK11_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK11_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK11_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK11_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK11_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK11_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK11_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK11_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK11_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK11_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK11_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK11_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK11_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK11_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK11_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK11_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK11_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK11_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK11_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK11_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK11_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK11_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK11_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK11_DTERRM = 0x400

	// HCTSIZ11: OTG host channel 11 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ11_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ11_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ11_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ11_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ11_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ11_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ11_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ11_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ11_DOPNG = 0x80000000

	// HCDMA11: OTG host channel 11 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA11_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA11_DMAADDR_Msk = 0xffffffff

	// HCCHAR12: OTG host channel 12 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR12_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR12_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR12_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR12_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR12_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR12_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR12_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR12_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR12_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR12_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR12_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR12_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR12_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR12_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR12_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR12_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR12_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR12_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR12_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR12_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR12_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR12_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR12_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR12_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR12_CHENA = 0x80000000

	// HCSPLT12: OTG host channel 0 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT12_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT12_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT12_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT12_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT12_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT12_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT12_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT12_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT12_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT12_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT12_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT12_SPLITEN = 0x80000000

	// HCINT12: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT12_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT12_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT12_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT12_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT12_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT12_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT12_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT12_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT12_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT12_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT12_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT12_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT12_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT12_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT12_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT12_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT12_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT12_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT12_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT12_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT12_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT12_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT12_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT12_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT12_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT12_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT12_DTERR = 0x400

	// HCINTMSK12: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK12_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK12_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK12_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK12_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK12_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK12_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK12_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK12_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK12_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK12_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK12_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK12_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK12_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK12_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK12_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK12_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK12_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK12_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK12_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK12_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK12_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK12_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK12_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK12_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK12_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK12_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK12_DTERRM = 0x400

	// HCTSIZ12: OTG host channel 12 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ12_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ12_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ12_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ12_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ12_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ12_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ12_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ12_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ12_DOPNG = 0x80000000

	// HCDMA12: OTG host channel 12 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA12_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA12_DMAADDR_Msk = 0xffffffff

	// HCCHAR13: OTG host channel 13 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR13_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR13_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR13_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR13_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR13_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR13_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR13_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR13_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR13_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR13_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR13_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR13_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR13_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR13_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR13_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR13_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR13_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR13_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR13_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR13_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR13_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR13_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR13_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR13_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR13_CHENA = 0x80000000

	// HCSPLT13: OTG host channel 13 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT13_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT13_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT13_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT13_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT13_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT13_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT13_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT13_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT13_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT13_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT13_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT13_SPLITEN = 0x80000000

	// HCINT13: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT13_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT13_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT13_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT13_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT13_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT13_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT13_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT13_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT13_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT13_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT13_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT13_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT13_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT13_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT13_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT13_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT13_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT13_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT13_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT13_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT13_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT13_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT13_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT13_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT13_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT13_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT13_DTERR = 0x400

	// HCINTMSK13: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK13_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK13_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK13_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK13_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK13_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK13_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK13_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK13_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK13_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK13_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK13_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK13_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK13_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK13_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK13_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK13_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK13_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK13_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK13_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK13_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK13_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK13_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK13_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK13_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK13_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK13_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK13_DTERRM = 0x400

	// HCTSIZ13: OTG host channel 13 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ13_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ13_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ13_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ13_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ13_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ13_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ13_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ13_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ13_DOPNG = 0x80000000

	// HCDMA13: OTG host channel 13 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA13_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA13_DMAADDR_Msk = 0xffffffff

	// HCCHAR14: OTG host channel 14 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR14_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR14_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR14_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR14_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR14_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR14_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR14_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR14_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR14_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR14_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR14_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR14_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR14_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR14_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR14_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR14_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR14_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR14_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR14_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR14_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR14_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR14_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR14_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR14_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR14_CHENA = 0x80000000

	// HCSPLT14: OTG host channel 14 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT14_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT14_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT14_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT14_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT14_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT14_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT14_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT14_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT14_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT14_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT14_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT14_SPLITEN = 0x80000000

	// HCINT14: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT14_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT14_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT14_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT14_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT14_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT14_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT14_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT14_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT14_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT14_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT14_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT14_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT14_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT14_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT14_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT14_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT14_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT14_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT14_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT14_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT14_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT14_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT14_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT14_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT14_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT14_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT14_DTERR = 0x400

	// HCINTMSK14: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK14_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK14_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK14_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK14_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK14_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK14_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK14_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK14_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK14_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK14_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK14_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK14_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK14_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK14_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK14_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK14_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK14_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK14_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK14_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK14_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK14_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK14_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK14_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK14_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK14_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK14_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK14_DTERRM = 0x400

	// HCTSIZ14: OTG host channel 14 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ14_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ14_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ14_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ14_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ14_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ14_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ14_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ14_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ14_DOPNG = 0x80000000

	// HCDMA14: OTG host channel 14 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA14_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA14_DMAADDR_Msk = 0xffffffff

	// HCCHAR15: OTG host channel 15 characteristics register
	// Position of MPSIZ field.
	OTG_HS_HCCHAR15_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_HCCHAR15_MPSIZ_Msk = 0x7ff
	// Position of EPNUM field.
	OTG_HS_HCCHAR15_EPNUM_Pos = 0xb
	// Bit mask of EPNUM field.
	OTG_HS_HCCHAR15_EPNUM_Msk = 0x7800
	// Position of EPDIR field.
	OTG_HS_HCCHAR15_EPDIR_Pos = 0xf
	// Bit mask of EPDIR field.
	OTG_HS_HCCHAR15_EPDIR_Msk = 0x8000
	// Bit EPDIR.
	OTG_HS_HCCHAR15_EPDIR = 0x8000
	// Position of LSDEV field.
	OTG_HS_HCCHAR15_LSDEV_Pos = 0x11
	// Bit mask of LSDEV field.
	OTG_HS_HCCHAR15_LSDEV_Msk = 0x20000
	// Bit LSDEV.
	OTG_HS_HCCHAR15_LSDEV = 0x20000
	// Position of EPTYP field.
	OTG_HS_HCCHAR15_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_HCCHAR15_EPTYP_Msk = 0xc0000
	// Position of MCNT field.
	OTG_HS_HCCHAR15_MCNT_Pos = 0x14
	// Bit mask of MCNT field.
	OTG_HS_HCCHAR15_MCNT_Msk = 0x300000
	// Position of DAD field.
	OTG_HS_HCCHAR15_DAD_Pos = 0x16
	// Bit mask of DAD field.
	OTG_HS_HCCHAR15_DAD_Msk = 0x1fc00000
	// Position of ODDFRM field.
	OTG_HS_HCCHAR15_ODDFRM_Pos = 0x1d
	// Bit mask of ODDFRM field.
	OTG_HS_HCCHAR15_ODDFRM_Msk = 0x20000000
	// Bit ODDFRM.
	OTG_HS_HCCHAR15_ODDFRM = 0x20000000
	// Position of CHDIS field.
	OTG_HS_HCCHAR15_CHDIS_Pos = 0x1e
	// Bit mask of CHDIS field.
	OTG_HS_HCCHAR15_CHDIS_Msk = 0x40000000
	// Bit CHDIS.
	OTG_HS_HCCHAR15_CHDIS = 0x40000000
	// Position of CHENA field.
	OTG_HS_HCCHAR15_CHENA_Pos = 0x1f
	// Bit mask of CHENA field.
	OTG_HS_HCCHAR15_CHENA_Msk = 0x80000000
	// Bit CHENA.
	OTG_HS_HCCHAR15_CHENA = 0x80000000

	// HCSPLT15: OTG host channel 15 split control register
	// Position of PRTADDR field.
	OTG_HS_HCSPLT15_PRTADDR_Pos = 0x0
	// Bit mask of PRTADDR field.
	OTG_HS_HCSPLT15_PRTADDR_Msk = 0x7f
	// Position of HUBADDR field.
	OTG_HS_HCSPLT15_HUBADDR_Pos = 0x7
	// Bit mask of HUBADDR field.
	OTG_HS_HCSPLT15_HUBADDR_Msk = 0x3f80
	// Position of XACTPOS field.
	OTG_HS_HCSPLT15_XACTPOS_Pos = 0xe
	// Bit mask of XACTPOS field.
	OTG_HS_HCSPLT15_XACTPOS_Msk = 0xc000
	// Position of COMPLSPLT field.
	OTG_HS_HCSPLT15_COMPLSPLT_Pos = 0x10
	// Bit mask of COMPLSPLT field.
	OTG_HS_HCSPLT15_COMPLSPLT_Msk = 0x10000
	// Bit COMPLSPLT.
	OTG_HS_HCSPLT15_COMPLSPLT = 0x10000
	// Position of SPLITEN field.
	OTG_HS_HCSPLT15_SPLITEN_Pos = 0x1f
	// Bit mask of SPLITEN field.
	OTG_HS_HCSPLT15_SPLITEN_Msk = 0x80000000
	// Bit SPLITEN.
	OTG_HS_HCSPLT15_SPLITEN = 0x80000000

	// HCINT15: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_HCINT15_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_HCINT15_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_HCINT15_XFRC = 0x1
	// Position of CHH field.
	OTG_HS_HCINT15_CHH_Pos = 0x1
	// Bit mask of CHH field.
	OTG_HS_HCINT15_CHH_Msk = 0x2
	// Bit CHH.
	OTG_HS_HCINT15_CHH = 0x2
	// Position of STALL field.
	OTG_HS_HCINT15_STALL_Pos = 0x3
	// Bit mask of STALL field.
	OTG_HS_HCINT15_STALL_Msk = 0x8
	// Bit STALL.
	OTG_HS_HCINT15_STALL = 0x8
	// Position of NAK field.
	OTG_HS_HCINT15_NAK_Pos = 0x4
	// Bit mask of NAK field.
	OTG_HS_HCINT15_NAK_Msk = 0x10
	// Bit NAK.
	OTG_HS_HCINT15_NAK = 0x10
	// Position of ACK field.
	OTG_HS_HCINT15_ACK_Pos = 0x5
	// Bit mask of ACK field.
	OTG_HS_HCINT15_ACK_Msk = 0x20
	// Bit ACK.
	OTG_HS_HCINT15_ACK = 0x20
	// Position of TXERR field.
	OTG_HS_HCINT15_TXERR_Pos = 0x7
	// Bit mask of TXERR field.
	OTG_HS_HCINT15_TXERR_Msk = 0x80
	// Bit TXERR.
	OTG_HS_HCINT15_TXERR = 0x80
	// Position of BBERR field.
	OTG_HS_HCINT15_BBERR_Pos = 0x8
	// Bit mask of BBERR field.
	OTG_HS_HCINT15_BBERR_Msk = 0x100
	// Bit BBERR.
	OTG_HS_HCINT15_BBERR = 0x100
	// Position of FRMOR field.
	OTG_HS_HCINT15_FRMOR_Pos = 0x9
	// Bit mask of FRMOR field.
	OTG_HS_HCINT15_FRMOR_Msk = 0x200
	// Bit FRMOR.
	OTG_HS_HCINT15_FRMOR = 0x200
	// Position of DTERR field.
	OTG_HS_HCINT15_DTERR_Pos = 0xa
	// Bit mask of DTERR field.
	OTG_HS_HCINT15_DTERR_Msk = 0x400
	// Bit DTERR.
	OTG_HS_HCINT15_DTERR = 0x400

	// HCINTMSK15: This register reflects the mask for each channel status described in the previous section.
	// Position of XFRCM field.
	OTG_HS_HCINTMSK15_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HCINTMSK15_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HCINTMSK15_XFRCM = 0x1
	// Position of CHHM field.
	OTG_HS_HCINTMSK15_CHHM_Pos = 0x1
	// Bit mask of CHHM field.
	OTG_HS_HCINTMSK15_CHHM_Msk = 0x2
	// Bit CHHM.
	OTG_HS_HCINTMSK15_CHHM = 0x2
	// Position of STALLM field.
	OTG_HS_HCINTMSK15_STALLM_Pos = 0x3
	// Bit mask of STALLM field.
	OTG_HS_HCINTMSK15_STALLM_Msk = 0x8
	// Bit STALLM.
	OTG_HS_HCINTMSK15_STALLM = 0x8
	// Position of NAKM field.
	OTG_HS_HCINTMSK15_NAKM_Pos = 0x4
	// Bit mask of NAKM field.
	OTG_HS_HCINTMSK15_NAKM_Msk = 0x10
	// Bit NAKM.
	OTG_HS_HCINTMSK15_NAKM = 0x10
	// Position of ACKM field.
	OTG_HS_HCINTMSK15_ACKM_Pos = 0x5
	// Bit mask of ACKM field.
	OTG_HS_HCINTMSK15_ACKM_Msk = 0x20
	// Bit ACKM.
	OTG_HS_HCINTMSK15_ACKM = 0x20
	// Position of TXERRM field.
	OTG_HS_HCINTMSK15_TXERRM_Pos = 0x7
	// Bit mask of TXERRM field.
	OTG_HS_HCINTMSK15_TXERRM_Msk = 0x80
	// Bit TXERRM.
	OTG_HS_HCINTMSK15_TXERRM = 0x80
	// Position of BBERRM field.
	OTG_HS_HCINTMSK15_BBERRM_Pos = 0x8
	// Bit mask of BBERRM field.
	OTG_HS_HCINTMSK15_BBERRM_Msk = 0x100
	// Bit BBERRM.
	OTG_HS_HCINTMSK15_BBERRM = 0x100
	// Position of FRMORM field.
	OTG_HS_HCINTMSK15_FRMORM_Pos = 0x9
	// Bit mask of FRMORM field.
	OTG_HS_HCINTMSK15_FRMORM_Msk = 0x200
	// Bit FRMORM.
	OTG_HS_HCINTMSK15_FRMORM = 0x200
	// Position of DTERRM field.
	OTG_HS_HCINTMSK15_DTERRM_Pos = 0xa
	// Bit mask of DTERRM field.
	OTG_HS_HCINTMSK15_DTERRM_Msk = 0x400
	// Bit DTERRM.
	OTG_HS_HCINTMSK15_DTERRM = 0x400

	// HCTSIZ15: OTG host channel 15 transfer size register
	// Position of XFRSIZ field.
	OTG_HS_HCTSIZ15_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_HCTSIZ15_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_HCTSIZ15_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_HCTSIZ15_PKTCNT_Msk = 0x1ff80000
	// Position of DPID field.
	OTG_HS_HCTSIZ15_DPID_Pos = 0x1d
	// Bit mask of DPID field.
	OTG_HS_HCTSIZ15_DPID_Msk = 0x60000000
	// Position of DOPNG field.
	OTG_HS_HCTSIZ15_DOPNG_Pos = 0x1f
	// Bit mask of DOPNG field.
	OTG_HS_HCTSIZ15_DOPNG_Msk = 0x80000000
	// Bit DOPNG.
	OTG_HS_HCTSIZ15_DOPNG = 0x80000000

	// HCDMA15: OTG host channel 15 DMA address register
	// Position of DMAADDR field.
	OTG_HS_HCDMA15_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_HCDMA15_DMAADDR_Msk = 0xffffffff

	// DCFG: This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
	// Position of DSPD field.
	OTG_HS_DCFG_DSPD_Pos = 0x0
	// Bit mask of DSPD field.
	OTG_HS_DCFG_DSPD_Msk = 0x3
	// Position of NZLSOHSK field.
	OTG_HS_DCFG_NZLSOHSK_Pos = 0x2
	// Bit mask of NZLSOHSK field.
	OTG_HS_DCFG_NZLSOHSK_Msk = 0x4
	// Bit NZLSOHSK.
	OTG_HS_DCFG_NZLSOHSK = 0x4
	// Position of DAD field.
	OTG_HS_DCFG_DAD_Pos = 0x4
	// Bit mask of DAD field.
	OTG_HS_DCFG_DAD_Msk = 0x7f0
	// Position of PFIVL field.
	OTG_HS_DCFG_PFIVL_Pos = 0xb
	// Bit mask of PFIVL field.
	OTG_HS_DCFG_PFIVL_Msk = 0x1800
	// Position of ERRATIM field.
	OTG_HS_DCFG_ERRATIM_Pos = 0xf
	// Bit mask of ERRATIM field.
	OTG_HS_DCFG_ERRATIM_Msk = 0x8000
	// Bit ERRATIM.
	OTG_HS_DCFG_ERRATIM = 0x8000

	// DCTL: OTG device control register
	// Position of RWUSIG field.
	OTG_HS_DCTL_RWUSIG_Pos = 0x0
	// Bit mask of RWUSIG field.
	OTG_HS_DCTL_RWUSIG_Msk = 0x1
	// Bit RWUSIG.
	OTG_HS_DCTL_RWUSIG = 0x1
	// Position of SDIS field.
	OTG_HS_DCTL_SDIS_Pos = 0x1
	// Bit mask of SDIS field.
	OTG_HS_DCTL_SDIS_Msk = 0x2
	// Bit SDIS.
	OTG_HS_DCTL_SDIS = 0x2
	// Position of GINSTS field.
	OTG_HS_DCTL_GINSTS_Pos = 0x2
	// Bit mask of GINSTS field.
	OTG_HS_DCTL_GINSTS_Msk = 0x4
	// Bit GINSTS.
	OTG_HS_DCTL_GINSTS = 0x4
	// Position of GONSTS field.
	OTG_HS_DCTL_GONSTS_Pos = 0x3
	// Bit mask of GONSTS field.
	OTG_HS_DCTL_GONSTS_Msk = 0x8
	// Bit GONSTS.
	OTG_HS_DCTL_GONSTS = 0x8
	// Position of TCTL field.
	OTG_HS_DCTL_TCTL_Pos = 0x4
	// Bit mask of TCTL field.
	OTG_HS_DCTL_TCTL_Msk = 0x70
	// Position of SGINAK field.
	OTG_HS_DCTL_SGINAK_Pos = 0x7
	// Bit mask of SGINAK field.
	OTG_HS_DCTL_SGINAK_Msk = 0x80
	// Bit SGINAK.
	OTG_HS_DCTL_SGINAK = 0x80
	// Position of CGINAK field.
	OTG_HS_DCTL_CGINAK_Pos = 0x8
	// Bit mask of CGINAK field.
	OTG_HS_DCTL_CGINAK_Msk = 0x100
	// Bit CGINAK.
	OTG_HS_DCTL_CGINAK = 0x100
	// Position of SGONAK field.
	OTG_HS_DCTL_SGONAK_Pos = 0x9
	// Bit mask of SGONAK field.
	OTG_HS_DCTL_SGONAK_Msk = 0x200
	// Bit SGONAK.
	OTG_HS_DCTL_SGONAK = 0x200
	// Position of CGONAK field.
	OTG_HS_DCTL_CGONAK_Pos = 0xa
	// Bit mask of CGONAK field.
	OTG_HS_DCTL_CGONAK_Msk = 0x400
	// Bit CGONAK.
	OTG_HS_DCTL_CGONAK = 0x400
	// Position of POPRGDNE field.
	OTG_HS_DCTL_POPRGDNE_Pos = 0xb
	// Bit mask of POPRGDNE field.
	OTG_HS_DCTL_POPRGDNE_Msk = 0x800
	// Bit POPRGDNE.
	OTG_HS_DCTL_POPRGDNE = 0x800
	// Position of DSBESLRJCT field.
	OTG_HS_DCTL_DSBESLRJCT_Pos = 0x12
	// Bit mask of DSBESLRJCT field.
	OTG_HS_DCTL_DSBESLRJCT_Msk = 0x40000
	// Bit DSBESLRJCT.
	OTG_HS_DCTL_DSBESLRJCT = 0x40000

	// DSTS: This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register.
	// Position of SUSPSTS field.
	OTG_HS_DSTS_SUSPSTS_Pos = 0x0
	// Bit mask of SUSPSTS field.
	OTG_HS_DSTS_SUSPSTS_Msk = 0x1
	// Bit SUSPSTS.
	OTG_HS_DSTS_SUSPSTS = 0x1
	// Position of ENUMSPD field.
	OTG_HS_DSTS_ENUMSPD_Pos = 0x1
	// Bit mask of ENUMSPD field.
	OTG_HS_DSTS_ENUMSPD_Msk = 0x6
	// Position of EERR field.
	OTG_HS_DSTS_EERR_Pos = 0x3
	// Bit mask of EERR field.
	OTG_HS_DSTS_EERR_Msk = 0x8
	// Bit EERR.
	OTG_HS_DSTS_EERR = 0x8
	// Position of FNSOF field.
	OTG_HS_DSTS_FNSOF_Pos = 0x8
	// Bit mask of FNSOF field.
	OTG_HS_DSTS_FNSOF_Msk = 0x3fff00
	// Position of DEVLNSTS field.
	OTG_HS_DSTS_DEVLNSTS_Pos = 0x16
	// Bit mask of DEVLNSTS field.
	OTG_HS_DSTS_DEVLNSTS_Msk = 0xc00000

	// DIEPMSK: This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
	// Position of XFRCM field.
	OTG_HS_DIEPMSK_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_DIEPMSK_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_DIEPMSK_XFRCM = 0x1
	// Position of EPDM field.
	OTG_HS_DIEPMSK_EPDM_Pos = 0x1
	// Bit mask of EPDM field.
	OTG_HS_DIEPMSK_EPDM_Msk = 0x2
	// Bit EPDM.
	OTG_HS_DIEPMSK_EPDM = 0x2
	// Position of AHBERRM field.
	OTG_HS_DIEPMSK_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_HS_DIEPMSK_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_HS_DIEPMSK_AHBERRM = 0x4
	// Position of TOM field.
	OTG_HS_DIEPMSK_TOM_Pos = 0x3
	// Bit mask of TOM field.
	OTG_HS_DIEPMSK_TOM_Msk = 0x8
	// Bit TOM.
	OTG_HS_DIEPMSK_TOM = 0x8
	// Position of ITTXFEMSK field.
	OTG_HS_DIEPMSK_ITTXFEMSK_Pos = 0x4
	// Bit mask of ITTXFEMSK field.
	OTG_HS_DIEPMSK_ITTXFEMSK_Msk = 0x10
	// Bit ITTXFEMSK.
	OTG_HS_DIEPMSK_ITTXFEMSK = 0x10
	// Position of INEPNMM field.
	OTG_HS_DIEPMSK_INEPNMM_Pos = 0x5
	// Bit mask of INEPNMM field.
	OTG_HS_DIEPMSK_INEPNMM_Msk = 0x20
	// Bit INEPNMM.
	OTG_HS_DIEPMSK_INEPNMM = 0x20
	// Position of INEPNEM field.
	OTG_HS_DIEPMSK_INEPNEM_Pos = 0x6
	// Bit mask of INEPNEM field.
	OTG_HS_DIEPMSK_INEPNEM_Msk = 0x40
	// Bit INEPNEM.
	OTG_HS_DIEPMSK_INEPNEM = 0x40
	// Position of TXFURM field.
	OTG_HS_DIEPMSK_TXFURM_Pos = 0x8
	// Bit mask of TXFURM field.
	OTG_HS_DIEPMSK_TXFURM_Msk = 0x100
	// Bit TXFURM.
	OTG_HS_DIEPMSK_TXFURM = 0x100
	// Position of NAKM field.
	OTG_HS_DIEPMSK_NAKM_Pos = 0xd
	// Bit mask of NAKM field.
	OTG_HS_DIEPMSK_NAKM_Msk = 0x2000
	// Bit NAKM.
	OTG_HS_DIEPMSK_NAKM = 0x2000

	// DOEPMSK: This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
	// Position of XFRCM field.
	OTG_HS_DOEPMSK_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_DOEPMSK_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_DOEPMSK_XFRCM = 0x1
	// Position of EPDM field.
	OTG_HS_DOEPMSK_EPDM_Pos = 0x1
	// Bit mask of EPDM field.
	OTG_HS_DOEPMSK_EPDM_Msk = 0x2
	// Bit EPDM.
	OTG_HS_DOEPMSK_EPDM = 0x2
	// Position of AHBERRM field.
	OTG_HS_DOEPMSK_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_HS_DOEPMSK_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_HS_DOEPMSK_AHBERRM = 0x4
	// Position of STUPM field.
	OTG_HS_DOEPMSK_STUPM_Pos = 0x3
	// Bit mask of STUPM field.
	OTG_HS_DOEPMSK_STUPM_Msk = 0x8
	// Bit STUPM.
	OTG_HS_DOEPMSK_STUPM = 0x8
	// Position of OTEPDM field.
	OTG_HS_DOEPMSK_OTEPDM_Pos = 0x4
	// Bit mask of OTEPDM field.
	OTG_HS_DOEPMSK_OTEPDM_Msk = 0x10
	// Bit OTEPDM.
	OTG_HS_DOEPMSK_OTEPDM = 0x10
	// Position of STSPHSRXM field.
	OTG_HS_DOEPMSK_STSPHSRXM_Pos = 0x5
	// Bit mask of STSPHSRXM field.
	OTG_HS_DOEPMSK_STSPHSRXM_Msk = 0x20
	// Bit STSPHSRXM.
	OTG_HS_DOEPMSK_STSPHSRXM = 0x20
	// Position of B2BSTUPM field.
	OTG_HS_DOEPMSK_B2BSTUPM_Pos = 0x6
	// Bit mask of B2BSTUPM field.
	OTG_HS_DOEPMSK_B2BSTUPM_Msk = 0x40
	// Bit B2BSTUPM.
	OTG_HS_DOEPMSK_B2BSTUPM = 0x40
	// Position of OUTPKTERRM field.
	OTG_HS_DOEPMSK_OUTPKTERRM_Pos = 0x8
	// Bit mask of OUTPKTERRM field.
	OTG_HS_DOEPMSK_OUTPKTERRM_Msk = 0x100
	// Bit OUTPKTERRM.
	OTG_HS_DOEPMSK_OUTPKTERRM = 0x100
	// Position of BERRM field.
	OTG_HS_DOEPMSK_BERRM_Pos = 0xc
	// Bit mask of BERRM field.
	OTG_HS_DOEPMSK_BERRM_Msk = 0x1000
	// Bit BERRM.
	OTG_HS_DOEPMSK_BERRM = 0x1000
	// Position of NAKMSK field.
	OTG_HS_DOEPMSK_NAKMSK_Pos = 0xd
	// Bit mask of NAKMSK field.
	OTG_HS_DOEPMSK_NAKMSK_Msk = 0x2000
	// Bit NAKMSK.
	OTG_HS_DOEPMSK_NAKMSK = 0x2000
	// Position of NYETMSK field.
	OTG_HS_DOEPMSK_NYETMSK_Pos = 0xe
	// Bit mask of NYETMSK field.
	OTG_HS_DOEPMSK_NYETMSK_Msk = 0x4000
	// Bit NYETMSK.
	OTG_HS_DOEPMSK_NYETMSK = 0x4000

	// DAINT: When a significant event occurs on an endpoint, a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (DIEPINTx/DOEPINTx).
	// Position of IEPINT field.
	OTG_HS_DAINT_IEPINT_Pos = 0x0
	// Bit mask of IEPINT field.
	OTG_HS_DAINT_IEPINT_Msk = 0xffff
	// Position of OEPINT field.
	OTG_HS_DAINT_OEPINT_Pos = 0x10
	// Bit mask of OEPINT field.
	OTG_HS_DAINT_OEPINT_Msk = 0xffff0000

	// DAINTMSK: The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the DAINT register bit corresponding to that interrupt is still set.
	// Position of IEPM field.
	OTG_HS_DAINTMSK_IEPM_Pos = 0x0
	// Bit mask of IEPM field.
	OTG_HS_DAINTMSK_IEPM_Msk = 0xffff
	// Position of OEPM field.
	OTG_HS_DAINTMSK_OEPM_Pos = 0x10
	// Bit mask of OEPM field.
	OTG_HS_DAINTMSK_OEPM_Msk = 0xffff0000

	// DVBUSDIS: This register specifies the VBUS discharge time after VBUS pulsing during SRP.
	// Position of VBUSDT field.
	OTG_HS_DVBUSDIS_VBUSDT_Pos = 0x0
	// Bit mask of VBUSDT field.
	OTG_HS_DVBUSDIS_VBUSDT_Msk = 0xffff

	// DVBUSPULSE: This register specifies the VBUS pulsing time during SRP.
	// Position of DVBUSP field.
	OTG_HS_DVBUSPULSE_DVBUSP_Pos = 0x0
	// Bit mask of DVBUSP field.
	OTG_HS_DVBUSPULSE_DVBUSP_Msk = 0xffff

	// DTHRCTL: OTG device threshold control register
	// Position of NONISOTHREN field.
	OTG_HS_DTHRCTL_NONISOTHREN_Pos = 0x0
	// Bit mask of NONISOTHREN field.
	OTG_HS_DTHRCTL_NONISOTHREN_Msk = 0x1
	// Bit NONISOTHREN.
	OTG_HS_DTHRCTL_NONISOTHREN = 0x1
	// Position of ISOTHREN field.
	OTG_HS_DTHRCTL_ISOTHREN_Pos = 0x1
	// Bit mask of ISOTHREN field.
	OTG_HS_DTHRCTL_ISOTHREN_Msk = 0x2
	// Bit ISOTHREN.
	OTG_HS_DTHRCTL_ISOTHREN = 0x2
	// Position of TXTHRLEN field.
	OTG_HS_DTHRCTL_TXTHRLEN_Pos = 0x2
	// Bit mask of TXTHRLEN field.
	OTG_HS_DTHRCTL_TXTHRLEN_Msk = 0x7fc
	// Position of RXTHREN field.
	OTG_HS_DTHRCTL_RXTHREN_Pos = 0x10
	// Bit mask of RXTHREN field.
	OTG_HS_DTHRCTL_RXTHREN_Msk = 0x10000
	// Bit RXTHREN.
	OTG_HS_DTHRCTL_RXTHREN = 0x10000
	// Position of RXTHRLEN field.
	OTG_HS_DTHRCTL_RXTHRLEN_Pos = 0x11
	// Bit mask of RXTHRLEN field.
	OTG_HS_DTHRCTL_RXTHRLEN_Msk = 0x3fe0000
	// Position of ARPEN field.
	OTG_HS_DTHRCTL_ARPEN_Pos = 0x1b
	// Bit mask of ARPEN field.
	OTG_HS_DTHRCTL_ARPEN_Msk = 0x8000000
	// Bit ARPEN.
	OTG_HS_DTHRCTL_ARPEN = 0x8000000

	// DIEPEMPMSK: This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).
	// Position of INEPTXFEM field.
	OTG_HS_DIEPEMPMSK_INEPTXFEM_Pos = 0x0
	// Bit mask of INEPTXFEM field.
	OTG_HS_DIEPEMPMSK_INEPTXFEM_Msk = 0xffff

	// HS_DOEPEACHMSK1: OTG device each OUT endpoint-1 interrupt mask register
	// Position of XFRCM field.
	OTG_HS_HS_DOEPEACHMSK1_XFRCM_Pos = 0x0
	// Bit mask of XFRCM field.
	OTG_HS_HS_DOEPEACHMSK1_XFRCM_Msk = 0x1
	// Bit XFRCM.
	OTG_HS_HS_DOEPEACHMSK1_XFRCM = 0x1
	// Position of EPDM field.
	OTG_HS_HS_DOEPEACHMSK1_EPDM_Pos = 0x1
	// Bit mask of EPDM field.
	OTG_HS_HS_DOEPEACHMSK1_EPDM_Msk = 0x2
	// Bit EPDM.
	OTG_HS_HS_DOEPEACHMSK1_EPDM = 0x2
	// Position of AHBERRM field.
	OTG_HS_HS_DOEPEACHMSK1_AHBERRM_Pos = 0x2
	// Bit mask of AHBERRM field.
	OTG_HS_HS_DOEPEACHMSK1_AHBERRM_Msk = 0x4
	// Bit AHBERRM.
	OTG_HS_HS_DOEPEACHMSK1_AHBERRM = 0x4
	// Position of STUPM field.
	OTG_HS_HS_DOEPEACHMSK1_STUPM_Pos = 0x3
	// Bit mask of STUPM field.
	OTG_HS_HS_DOEPEACHMSK1_STUPM_Msk = 0x8
	// Bit STUPM.
	OTG_HS_HS_DOEPEACHMSK1_STUPM = 0x8
	// Position of OTEPDM field.
	OTG_HS_HS_DOEPEACHMSK1_OTEPDM_Pos = 0x4
	// Bit mask of OTEPDM field.
	OTG_HS_HS_DOEPEACHMSK1_OTEPDM_Msk = 0x10
	// Bit OTEPDM.
	OTG_HS_HS_DOEPEACHMSK1_OTEPDM = 0x10
	// Position of B2BSTUPM field.
	OTG_HS_HS_DOEPEACHMSK1_B2BSTUPM_Pos = 0x6
	// Bit mask of B2BSTUPM field.
	OTG_HS_HS_DOEPEACHMSK1_B2BSTUPM_Msk = 0x40
	// Bit B2BSTUPM.
	OTG_HS_HS_DOEPEACHMSK1_B2BSTUPM = 0x40
	// Position of OUTPKTERRM field.
	OTG_HS_HS_DOEPEACHMSK1_OUTPKTERRM_Pos = 0x8
	// Bit mask of OUTPKTERRM field.
	OTG_HS_HS_DOEPEACHMSK1_OUTPKTERRM_Msk = 0x100
	// Bit OUTPKTERRM.
	OTG_HS_HS_DOEPEACHMSK1_OUTPKTERRM = 0x100
	// Position of BNAM field.
	OTG_HS_HS_DOEPEACHMSK1_BNAM_Pos = 0x9
	// Bit mask of BNAM field.
	OTG_HS_HS_DOEPEACHMSK1_BNAM_Msk = 0x200
	// Bit BNAM.
	OTG_HS_HS_DOEPEACHMSK1_BNAM = 0x200
	// Position of BERRM field.
	OTG_HS_HS_DOEPEACHMSK1_BERRM_Pos = 0xc
	// Bit mask of BERRM field.
	OTG_HS_HS_DOEPEACHMSK1_BERRM_Msk = 0x1000
	// Bit BERRM.
	OTG_HS_HS_DOEPEACHMSK1_BERRM = 0x1000
	// Position of NAKMSK field.
	OTG_HS_HS_DOEPEACHMSK1_NAKMSK_Pos = 0xd
	// Bit mask of NAKMSK field.
	OTG_HS_HS_DOEPEACHMSK1_NAKMSK_Msk = 0x2000
	// Bit NAKMSK.
	OTG_HS_HS_DOEPEACHMSK1_NAKMSK = 0x2000
	// Position of NYETMSK field.
	OTG_HS_HS_DOEPEACHMSK1_NYETMSK_Pos = 0xe
	// Bit mask of NYETMSK field.
	OTG_HS_HS_DOEPEACHMSK1_NYETMSK_Msk = 0x4000
	// Bit NYETMSK.
	OTG_HS_HS_DOEPEACHMSK1_NYETMSK = 0x4000

	// DIEPCTL0: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DIEPCTL0_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DIEPCTL0_MPSIZ_Msk = 0x3
	// Position of USBAEP field.
	OTG_HS_DIEPCTL0_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DIEPCTL0_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DIEPCTL0_USBAEP = 0x8000
	// Position of NAKSTS field.
	OTG_HS_DIEPCTL0_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DIEPCTL0_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DIEPCTL0_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DIEPCTL0_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DIEPCTL0_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_HS_DIEPCTL0_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DIEPCTL0_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DIEPCTL0_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_HS_DIEPCTL0_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_HS_DIEPCTL0_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_HS_DIEPCTL0_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DIEPCTL0_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DIEPCTL0_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DIEPCTL0_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DIEPCTL0_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DIEPCTL0_SNAK = 0x8000000
	// Position of EPDIS field.
	OTG_HS_DIEPCTL0_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DIEPCTL0_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DIEPCTL0_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DIEPCTL0_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DIEPCTL0_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DIEPCTL0_EPENA = 0x80000000

	// DIEPINT0: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT0_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT0_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT0_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT0_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT0_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT0_EPDISD = 0x2
	// Position of TOC field.
	OTG_HS_DIEPINT0_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT0_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT0_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT0_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT0_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT0_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT0_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT0_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT0_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT0_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT0_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT0_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT0_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT0_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT0_TXFE = 0x80
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT0_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT0_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT0_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT0_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT0_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT0_NAK = 0x2000

	// DIEPTSIZ0: The application must modify this register before enabling endpoint 0.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ0_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ0_XFRSIZ_Msk = 0x7f
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ0_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ0_PKTCNT_Msk = 0x180000

	// DTXFSTS0: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_HS_DTXFSTS0_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_HS_DTXFSTS0_INEPTFSAV_Msk = 0xffff

	// DIEPCTL1: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DIEPCTL1_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DIEPCTL1_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DIEPCTL1_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DIEPCTL1_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DIEPCTL1_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DIEPCTL1_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DIEPCTL1_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DIEPCTL1_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DIEPCTL1_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DIEPCTL1_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DIEPCTL1_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DIEPCTL1_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DIEPCTL1_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_HS_DIEPCTL1_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DIEPCTL1_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DIEPCTL1_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_HS_DIEPCTL1_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_HS_DIEPCTL1_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_HS_DIEPCTL1_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DIEPCTL1_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DIEPCTL1_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DIEPCTL1_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DIEPCTL1_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DIEPCTL1_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL1_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL1_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DIEPCTL1_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_HS_DIEPCTL1_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_HS_DIEPCTL1_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_HS_DIEPCTL1_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DIEPCTL1_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DIEPCTL1_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DIEPCTL1_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DIEPCTL1_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DIEPCTL1_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DIEPCTL1_EPENA = 0x80000000

	// DIEPINT1: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT1_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT1_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT1_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT1_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT1_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT1_EPDISD = 0x2
	// Position of TOC field.
	OTG_HS_DIEPINT1_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT1_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT1_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT1_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT1_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT1_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT1_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT1_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT1_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT1_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT1_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT1_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT1_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT1_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT1_TXFE = 0x80
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT1_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT1_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT1_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT1_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT1_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT1_NAK = 0x2000

	// DIEPTSIZ1: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ1_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ1_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ1_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ1_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ1_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ1_MCNT_Msk = 0x60000000

	// DIEPDMA1: OTG device IN endpoint 1 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA1_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA1_DMAADDR_Msk = 0xffffffff

	// DTXFSTS1: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_HS_DTXFSTS1_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_HS_DTXFSTS1_INEPTFSAV_Msk = 0xffff

	// DIEPCTL2: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DIEPCTL2_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DIEPCTL2_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DIEPCTL2_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DIEPCTL2_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DIEPCTL2_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DIEPCTL2_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DIEPCTL2_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DIEPCTL2_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DIEPCTL2_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DIEPCTL2_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DIEPCTL2_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DIEPCTL2_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DIEPCTL2_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_HS_DIEPCTL2_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DIEPCTL2_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DIEPCTL2_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_HS_DIEPCTL2_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_HS_DIEPCTL2_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_HS_DIEPCTL2_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DIEPCTL2_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DIEPCTL2_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DIEPCTL2_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DIEPCTL2_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DIEPCTL2_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL2_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL2_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DIEPCTL2_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_HS_DIEPCTL2_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_HS_DIEPCTL2_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_HS_DIEPCTL2_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DIEPCTL2_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DIEPCTL2_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DIEPCTL2_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DIEPCTL2_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DIEPCTL2_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DIEPCTL2_EPENA = 0x80000000

	// DIEPINT2: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT2_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT2_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT2_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT2_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT2_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT2_EPDISD = 0x2
	// Position of TOC field.
	OTG_HS_DIEPINT2_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT2_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT2_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT2_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT2_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT2_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT2_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT2_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT2_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT2_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT2_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT2_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT2_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT2_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT2_TXFE = 0x80
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT2_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT2_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT2_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT2_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT2_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT2_NAK = 0x2000

	// DIEPTSIZ2: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ2_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ2_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ2_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ2_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ2_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ2_MCNT_Msk = 0x60000000

	// DIEPDMA2: OTG device IN endpoint 2 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA2_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA2_DMAADDR_Msk = 0xffffffff

	// DTXFSTS2: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_HS_DTXFSTS2_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_HS_DTXFSTS2_INEPTFSAV_Msk = 0xffff

	// DIEPCTL3: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DIEPCTL3_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DIEPCTL3_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DIEPCTL3_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DIEPCTL3_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DIEPCTL3_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DIEPCTL3_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DIEPCTL3_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DIEPCTL3_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DIEPCTL3_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DIEPCTL3_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DIEPCTL3_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DIEPCTL3_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DIEPCTL3_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_HS_DIEPCTL3_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DIEPCTL3_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DIEPCTL3_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_HS_DIEPCTL3_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_HS_DIEPCTL3_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_HS_DIEPCTL3_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DIEPCTL3_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DIEPCTL3_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DIEPCTL3_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DIEPCTL3_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DIEPCTL3_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL3_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL3_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DIEPCTL3_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_HS_DIEPCTL3_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_HS_DIEPCTL3_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_HS_DIEPCTL3_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DIEPCTL3_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DIEPCTL3_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DIEPCTL3_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DIEPCTL3_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DIEPCTL3_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DIEPCTL3_EPENA = 0x80000000

	// DIEPINT3: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT3_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT3_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT3_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT3_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT3_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT3_EPDISD = 0x2
	// Position of TOC field.
	OTG_HS_DIEPINT3_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT3_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT3_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT3_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT3_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT3_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT3_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT3_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT3_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT3_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT3_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT3_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT3_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT3_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT3_TXFE = 0x80
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT3_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT3_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT3_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT3_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT3_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT3_NAK = 0x2000

	// DIEPTSIZ3: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ3_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ3_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ3_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ3_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ3_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ3_MCNT_Msk = 0x60000000

	// DIEPDMA3: OTG device IN endpoint 3 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA3_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA3_DMAADDR_Msk = 0xffffffff

	// DTXFSTS3: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_HS_DTXFSTS3_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_HS_DTXFSTS3_INEPTFSAV_Msk = 0xffff

	// DIEPCTL4: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DIEPCTL4_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DIEPCTL4_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DIEPCTL4_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DIEPCTL4_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DIEPCTL4_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DIEPCTL4_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DIEPCTL4_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DIEPCTL4_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DIEPCTL4_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DIEPCTL4_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DIEPCTL4_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DIEPCTL4_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DIEPCTL4_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_HS_DIEPCTL4_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DIEPCTL4_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DIEPCTL4_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_HS_DIEPCTL4_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_HS_DIEPCTL4_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_HS_DIEPCTL4_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DIEPCTL4_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DIEPCTL4_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DIEPCTL4_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DIEPCTL4_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DIEPCTL4_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL4_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL4_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DIEPCTL4_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_HS_DIEPCTL4_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_HS_DIEPCTL4_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_HS_DIEPCTL4_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DIEPCTL4_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DIEPCTL4_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DIEPCTL4_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DIEPCTL4_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DIEPCTL4_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DIEPCTL4_EPENA = 0x80000000

	// DIEPINT4: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT4_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT4_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT4_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT4_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT4_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT4_EPDISD = 0x2
	// Position of TOC field.
	OTG_HS_DIEPINT4_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT4_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT4_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT4_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT4_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT4_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT4_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT4_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT4_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT4_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT4_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT4_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT4_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT4_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT4_TXFE = 0x80
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT4_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT4_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT4_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT4_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT4_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT4_NAK = 0x2000

	// DIEPTSIZ4: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ4_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ4_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ4_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ4_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ4_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ4_MCNT_Msk = 0x60000000

	// DIEPDMA4: OTG device IN endpoint 4 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA4_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA4_DMAADDR_Msk = 0xffffffff

	// DTXFSTS4: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_HS_DTXFSTS4_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_HS_DTXFSTS4_INEPTFSAV_Msk = 0xffff

	// DIEPCTL5: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DIEPCTL5_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DIEPCTL5_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DIEPCTL5_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DIEPCTL5_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DIEPCTL5_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DIEPCTL5_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DIEPCTL5_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DIEPCTL5_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DIEPCTL5_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DIEPCTL5_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DIEPCTL5_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DIEPCTL5_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DIEPCTL5_EPTYP_Msk = 0xc0000
	// Position of STALL field.
	OTG_HS_DIEPCTL5_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DIEPCTL5_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DIEPCTL5_STALL = 0x200000
	// Position of TXFNUM field.
	OTG_HS_DIEPCTL5_TXFNUM_Pos = 0x16
	// Bit mask of TXFNUM field.
	OTG_HS_DIEPCTL5_TXFNUM_Msk = 0x3c00000
	// Position of CNAK field.
	OTG_HS_DIEPCTL5_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DIEPCTL5_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DIEPCTL5_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DIEPCTL5_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DIEPCTL5_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DIEPCTL5_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL5_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DIEPCTL5_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DIEPCTL5_SD0PID_SEVNFRM = 0x10000000
	// Position of SODDFRM field.
	OTG_HS_DIEPCTL5_SODDFRM_Pos = 0x1d
	// Bit mask of SODDFRM field.
	OTG_HS_DIEPCTL5_SODDFRM_Msk = 0x20000000
	// Bit SODDFRM.
	OTG_HS_DIEPCTL5_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DIEPCTL5_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DIEPCTL5_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DIEPCTL5_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DIEPCTL5_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DIEPCTL5_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DIEPCTL5_EPENA = 0x80000000

	// DIEPINT5: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT5_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT5_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT5_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT5_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT5_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT5_EPDISD = 0x2
	// Position of TOC field.
	OTG_HS_DIEPINT5_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT5_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT5_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT5_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT5_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT5_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT5_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT5_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT5_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT5_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT5_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT5_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT5_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT5_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT5_TXFE = 0x80
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT5_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT5_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT5_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT5_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT5_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT5_NAK = 0x2000

	// DIEPTSIZ5: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ5_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ5_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ5_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ5_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ5_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ5_MCNT_Msk = 0x60000000

	// DIEPDMA5: OTG device IN endpoint 5 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA5_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA5_DMAADDR_Msk = 0xffffffff

	// DTXFSTS5: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
	// Position of INEPTFSAV field.
	OTG_HS_DTXFSTS5_INEPTFSAV_Pos = 0x0
	// Bit mask of INEPTFSAV field.
	OTG_HS_DTXFSTS5_INEPTFSAV_Msk = 0xffff

	// DIEPINT6: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT6_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT6_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT6_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT6_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT6_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT6_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DIEPINT6_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DIEPINT6_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DIEPINT6_AHBERR = 0x4
	// Position of TOC field.
	OTG_HS_DIEPINT6_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT6_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT6_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT6_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT6_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT6_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT6_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT6_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT6_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT6_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT6_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT6_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT6_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT6_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT6_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_HS_DIEPINT6_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_HS_DIEPINT6_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_HS_DIEPINT6_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_HS_DIEPINT6_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DIEPINT6_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DIEPINT6_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT6_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT6_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT6_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT6_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT6_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT6_NAK = 0x2000

	// DIEPTSIZ6: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ6_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ6_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ6_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ6_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ6_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ6_MCNT_Msk = 0x60000000

	// DIEPDMA6: OTG device IN endpoint 6 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA6_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA6_DMAADDR_Msk = 0xffffffff

	// DIEPINT7: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT7_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT7_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT7_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT7_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT7_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT7_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DIEPINT7_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DIEPINT7_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DIEPINT7_AHBERR = 0x4
	// Position of TOC field.
	OTG_HS_DIEPINT7_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT7_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT7_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT7_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT7_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT7_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT7_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT7_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT7_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT7_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT7_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT7_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT7_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT7_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT7_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_HS_DIEPINT7_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_HS_DIEPINT7_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_HS_DIEPINT7_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_HS_DIEPINT7_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DIEPINT7_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DIEPINT7_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT7_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT7_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT7_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT7_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT7_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT7_NAK = 0x2000

	// DIEPTSIZ7: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ7_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ7_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ7_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ7_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ7_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ7_MCNT_Msk = 0x60000000

	// DIEPDMA7: OTG device IN endpoint 7 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA7_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA7_DMAADDR_Msk = 0xffffffff

	// DIEPINT8: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DIEPINT8_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DIEPINT8_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DIEPINT8_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DIEPINT8_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DIEPINT8_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DIEPINT8_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DIEPINT8_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DIEPINT8_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DIEPINT8_AHBERR = 0x4
	// Position of TOC field.
	OTG_HS_DIEPINT8_TOC_Pos = 0x3
	// Bit mask of TOC field.
	OTG_HS_DIEPINT8_TOC_Msk = 0x8
	// Bit TOC.
	OTG_HS_DIEPINT8_TOC = 0x8
	// Position of ITTXFE field.
	OTG_HS_DIEPINT8_ITTXFE_Pos = 0x4
	// Bit mask of ITTXFE field.
	OTG_HS_DIEPINT8_ITTXFE_Msk = 0x10
	// Bit ITTXFE.
	OTG_HS_DIEPINT8_ITTXFE = 0x10
	// Position of INEPNM field.
	OTG_HS_DIEPINT8_INEPNM_Pos = 0x5
	// Bit mask of INEPNM field.
	OTG_HS_DIEPINT8_INEPNM_Msk = 0x20
	// Bit INEPNM.
	OTG_HS_DIEPINT8_INEPNM = 0x20
	// Position of INEPNE field.
	OTG_HS_DIEPINT8_INEPNE_Pos = 0x6
	// Bit mask of INEPNE field.
	OTG_HS_DIEPINT8_INEPNE_Msk = 0x40
	// Bit INEPNE.
	OTG_HS_DIEPINT8_INEPNE = 0x40
	// Position of TXFE field.
	OTG_HS_DIEPINT8_TXFE_Pos = 0x7
	// Bit mask of TXFE field.
	OTG_HS_DIEPINT8_TXFE_Msk = 0x80
	// Bit TXFE.
	OTG_HS_DIEPINT8_TXFE = 0x80
	// Position of TXFIFOUDRN field.
	OTG_HS_DIEPINT8_TXFIFOUDRN_Pos = 0x8
	// Bit mask of TXFIFOUDRN field.
	OTG_HS_DIEPINT8_TXFIFOUDRN_Msk = 0x100
	// Bit TXFIFOUDRN.
	OTG_HS_DIEPINT8_TXFIFOUDRN = 0x100
	// Position of BNA field.
	OTG_HS_DIEPINT8_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DIEPINT8_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DIEPINT8_BNA = 0x200
	// Position of PKTDRPSTS field.
	OTG_HS_DIEPINT8_PKTDRPSTS_Pos = 0xb
	// Bit mask of PKTDRPSTS field.
	OTG_HS_DIEPINT8_PKTDRPSTS_Msk = 0x800
	// Bit PKTDRPSTS.
	OTG_HS_DIEPINT8_PKTDRPSTS = 0x800
	// Position of NAK field.
	OTG_HS_DIEPINT8_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DIEPINT8_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DIEPINT8_NAK = 0x2000

	// DIEPTSIZ8: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DIEPTSIZ8_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DIEPTSIZ8_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DIEPTSIZ8_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DIEPTSIZ8_PKTCNT_Msk = 0x1ff80000
	// Position of MCNT field.
	OTG_HS_DIEPTSIZ8_MCNT_Pos = 0x1d
	// Bit mask of MCNT field.
	OTG_HS_DIEPTSIZ8_MCNT_Msk = 0x60000000

	// DIEPDMA8: OTG device IN endpoint 8 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DIEPDMA8_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DIEPDMA8_DMAADDR_Msk = 0xffffffff

	// DOEPCTL0: This section describes the DOEPCTL0 register.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL0_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL0_MPSIZ_Msk = 0x3
	// Position of USBAEP field.
	OTG_HS_DOEPCTL0_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL0_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL0_USBAEP = 0x8000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL0_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL0_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL0_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL0_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL0_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL0_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL0_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL0_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL0_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL0_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL0_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL0_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL0_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL0_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL0_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL0_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL0_SNAK = 0x8000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL0_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL0_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL0_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL0_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL0_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL0_EPENA = 0x80000000

	// DOEPINT0: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT0_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT0_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT0_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT0_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT0_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT0_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT0_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT0_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT0_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT0_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT0_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT0_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT0_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT0_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT0_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT0_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT0_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT0_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT0_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT0_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT0_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT0_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT0_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT0_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT0_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT0_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT0_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT0_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT0_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT0_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT0_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT0_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT0_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT0_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT0_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT0_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT0_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT0_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT0_STPKTRX = 0x8000

	// DOEPTSIZ0: The application must modify this register before enabling endpoint 0.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ0_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ0_XFRSIZ_Msk = 0x7f
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ0_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ0_PKTCNT_Msk = 0x80000
	// Bit PKTCNT.
	OTG_HS_DOEPTSIZ0_PKTCNT = 0x80000
	// Position of STUPCNT field.
	OTG_HS_DOEPTSIZ0_STUPCNT_Pos = 0x1d
	// Bit mask of STUPCNT field.
	OTG_HS_DOEPTSIZ0_STUPCNT_Msk = 0x60000000

	// DOEPDMA0: OTG device OUT endpoint 0 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA0_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA0_DMAADDR_Msk = 0xffffffff

	// DOEPCTL1: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL1_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL1_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL1_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL1_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL1_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL1_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL1_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL1_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL1_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL1_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL1_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL1_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL1_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL1_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL1_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL1_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL1_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL1_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL1_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL1_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL1_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL1_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL1_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL1_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL1_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL1_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL1_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL1_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL1_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL1_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL1_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL1_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL1_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL1_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL1_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL1_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL1_EPENA = 0x80000000

	// DOEPINT1: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT1_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT1_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT1_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT1_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT1_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT1_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT1_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT1_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT1_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT1_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT1_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT1_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT1_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT1_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT1_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT1_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT1_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT1_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT1_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT1_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT1_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT1_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT1_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT1_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT1_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT1_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT1_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT1_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT1_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT1_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT1_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT1_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT1_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT1_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT1_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT1_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT1_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT1_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT1_STPKTRX = 0x8000

	// DOEPTSIZ1: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ1_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ1_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ1_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ1_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ1_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ1_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA1: OTG device OUT endpoint 1 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA1_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA1_DMAADDR_Msk = 0xffffffff

	// DOEPCTL2: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL2_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL2_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL2_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL2_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL2_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL2_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL2_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL2_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL2_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL2_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL2_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL2_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL2_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL2_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL2_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL2_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL2_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL2_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL2_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL2_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL2_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL2_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL2_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL2_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL2_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL2_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL2_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL2_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL2_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL2_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL2_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL2_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL2_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL2_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL2_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL2_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL2_EPENA = 0x80000000

	// DOEPINT2: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT2_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT2_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT2_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT2_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT2_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT2_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT2_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT2_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT2_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT2_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT2_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT2_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT2_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT2_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT2_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT2_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT2_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT2_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT2_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT2_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT2_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT2_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT2_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT2_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT2_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT2_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT2_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT2_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT2_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT2_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT2_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT2_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT2_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT2_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT2_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT2_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT2_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT2_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT2_STPKTRX = 0x8000

	// DOEPTSIZ2: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ2_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ2_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ2_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ2_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ2_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ2_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA2: OTG device OUT endpoint 2 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA2_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA2_DMAADDR_Msk = 0xffffffff

	// DOEPCTL3: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL3_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL3_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL3_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL3_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL3_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL3_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL3_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL3_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL3_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL3_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL3_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL3_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL3_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL3_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL3_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL3_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL3_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL3_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL3_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL3_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL3_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL3_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL3_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL3_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL3_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL3_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL3_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL3_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL3_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL3_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL3_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL3_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL3_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL3_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL3_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL3_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL3_EPENA = 0x80000000

	// DOEPINT3: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT3_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT3_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT3_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT3_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT3_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT3_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT3_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT3_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT3_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT3_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT3_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT3_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT3_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT3_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT3_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT3_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT3_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT3_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT3_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT3_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT3_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT3_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT3_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT3_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT3_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT3_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT3_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT3_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT3_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT3_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT3_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT3_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT3_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT3_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT3_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT3_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT3_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT3_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT3_STPKTRX = 0x8000

	// DOEPTSIZ3: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ3_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ3_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ3_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ3_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ3_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ3_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA3: OTG device OUT endpoint 3 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA3_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA3_DMAADDR_Msk = 0xffffffff

	// DOEPCTL4: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL4_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL4_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL4_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL4_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL4_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL4_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL4_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL4_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL4_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL4_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL4_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL4_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL4_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL4_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL4_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL4_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL4_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL4_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL4_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL4_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL4_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL4_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL4_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL4_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL4_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL4_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL4_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL4_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL4_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL4_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL4_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL4_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL4_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL4_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL4_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL4_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL4_EPENA = 0x80000000

	// DOEPINT4: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT4_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT4_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT4_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT4_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT4_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT4_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT4_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT4_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT4_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT4_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT4_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT4_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT4_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT4_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT4_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT4_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT4_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT4_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT4_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT4_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT4_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT4_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT4_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT4_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT4_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT4_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT4_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT4_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT4_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT4_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT4_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT4_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT4_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT4_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT4_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT4_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT4_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT4_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT4_STPKTRX = 0x8000

	// DOEPTSIZ4: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ4_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ4_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ4_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ4_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ4_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ4_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA4: OTG device OUT endpoint 4 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA4_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA4_DMAADDR_Msk = 0xffffffff

	// DOEPCTL5: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL5_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL5_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL5_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL5_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL5_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL5_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL5_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL5_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL5_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL5_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL5_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL5_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL5_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL5_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL5_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL5_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL5_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL5_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL5_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL5_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL5_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL5_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL5_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL5_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL5_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL5_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL5_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL5_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL5_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL5_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL5_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL5_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL5_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL5_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL5_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL5_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL5_EPENA = 0x80000000

	// DOEPINT5: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT5_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT5_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT5_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT5_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT5_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT5_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT5_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT5_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT5_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT5_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT5_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT5_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT5_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT5_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT5_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT5_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT5_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT5_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT5_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT5_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT5_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT5_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT5_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT5_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT5_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT5_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT5_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT5_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT5_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT5_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT5_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT5_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT5_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT5_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT5_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT5_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT5_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT5_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT5_STPKTRX = 0x8000

	// DOEPTSIZ5: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ5_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ5_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ5_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ5_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ5_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ5_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA5: OTG device OUT endpoint 5 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA5_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA5_DMAADDR_Msk = 0xffffffff

	// DOEPCTL6: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL6_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL6_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL6_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL6_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL6_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL6_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL6_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL6_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL6_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL6_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL6_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL6_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL6_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL6_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL6_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL6_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL6_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL6_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL6_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL6_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL6_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL6_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL6_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL6_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL6_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL6_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL6_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL6_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL6_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL6_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL6_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL6_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL6_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL6_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL6_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL6_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL6_EPENA = 0x80000000

	// DOEPINT6: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT6_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT6_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT6_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT6_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT6_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT6_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT6_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT6_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT6_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT6_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT6_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT6_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT6_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT6_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT6_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT6_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT6_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT6_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT6_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT6_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT6_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT6_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT6_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT6_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT6_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT6_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT6_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT6_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT6_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT6_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT6_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT6_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT6_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT6_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT6_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT6_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT6_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT6_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT6_STPKTRX = 0x8000

	// DOEPTSIZ6: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ6_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ6_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ6_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ6_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ6_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ6_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA6: OTG device OUT endpoint 6 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA6_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA6_DMAADDR_Msk = 0xffffffff

	// DOEPCTL7: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL7_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL7_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL7_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL7_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL7_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL7_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL7_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL7_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL7_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL7_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL7_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL7_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL7_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL7_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL7_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL7_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL7_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL7_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL7_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL7_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL7_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL7_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL7_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL7_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL7_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL7_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL7_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL7_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL7_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL7_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL7_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL7_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL7_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL7_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL7_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL7_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL7_EPENA = 0x80000000

	// DOEPINT7: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT7_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT7_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT7_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT7_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT7_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT7_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT7_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT7_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT7_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT7_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT7_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT7_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT7_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT7_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT7_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT7_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT7_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT7_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT7_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT7_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT7_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT7_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT7_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT7_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT7_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT7_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT7_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT7_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT7_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT7_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT7_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT7_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT7_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT7_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT7_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT7_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT7_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT7_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT7_STPKTRX = 0x8000

	// DOEPTSIZ7: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ7_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ7_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ7_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ7_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ7_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ7_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA7: OTG device OUT endpoint 7 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA7_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA7_DMAADDR_Msk = 0xffffffff

	// DOEPCTL8: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
	// Position of MPSIZ field.
	OTG_HS_DOEPCTL8_MPSIZ_Pos = 0x0
	// Bit mask of MPSIZ field.
	OTG_HS_DOEPCTL8_MPSIZ_Msk = 0x7ff
	// Position of USBAEP field.
	OTG_HS_DOEPCTL8_USBAEP_Pos = 0xf
	// Bit mask of USBAEP field.
	OTG_HS_DOEPCTL8_USBAEP_Msk = 0x8000
	// Bit USBAEP.
	OTG_HS_DOEPCTL8_USBAEP = 0x8000
	// Position of EONUM_DPIP field.
	OTG_HS_DOEPCTL8_EONUM_DPIP_Pos = 0x10
	// Bit mask of EONUM_DPIP field.
	OTG_HS_DOEPCTL8_EONUM_DPIP_Msk = 0x10000
	// Bit EONUM_DPIP.
	OTG_HS_DOEPCTL8_EONUM_DPIP = 0x10000
	// Position of NAKSTS field.
	OTG_HS_DOEPCTL8_NAKSTS_Pos = 0x11
	// Bit mask of NAKSTS field.
	OTG_HS_DOEPCTL8_NAKSTS_Msk = 0x20000
	// Bit NAKSTS.
	OTG_HS_DOEPCTL8_NAKSTS = 0x20000
	// Position of EPTYP field.
	OTG_HS_DOEPCTL8_EPTYP_Pos = 0x12
	// Bit mask of EPTYP field.
	OTG_HS_DOEPCTL8_EPTYP_Msk = 0xc0000
	// Position of SNPM field.
	OTG_HS_DOEPCTL8_SNPM_Pos = 0x14
	// Bit mask of SNPM field.
	OTG_HS_DOEPCTL8_SNPM_Msk = 0x100000
	// Bit SNPM.
	OTG_HS_DOEPCTL8_SNPM = 0x100000
	// Position of STALL field.
	OTG_HS_DOEPCTL8_STALL_Pos = 0x15
	// Bit mask of STALL field.
	OTG_HS_DOEPCTL8_STALL_Msk = 0x200000
	// Bit STALL.
	OTG_HS_DOEPCTL8_STALL = 0x200000
	// Position of CNAK field.
	OTG_HS_DOEPCTL8_CNAK_Pos = 0x1a
	// Bit mask of CNAK field.
	OTG_HS_DOEPCTL8_CNAK_Msk = 0x4000000
	// Bit CNAK.
	OTG_HS_DOEPCTL8_CNAK = 0x4000000
	// Position of SNAK field.
	OTG_HS_DOEPCTL8_SNAK_Pos = 0x1b
	// Bit mask of SNAK field.
	OTG_HS_DOEPCTL8_SNAK_Msk = 0x8000000
	// Bit SNAK.
	OTG_HS_DOEPCTL8_SNAK = 0x8000000
	// Position of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL8_SD0PID_SEVNFRM_Pos = 0x1c
	// Bit mask of SD0PID_SEVNFRM field.
	OTG_HS_DOEPCTL8_SD0PID_SEVNFRM_Msk = 0x10000000
	// Bit SD0PID_SEVNFRM.
	OTG_HS_DOEPCTL8_SD0PID_SEVNFRM = 0x10000000
	// Position of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL8_SD1PID_SODDFRM_Pos = 0x1d
	// Bit mask of SD1PID_SODDFRM field.
	OTG_HS_DOEPCTL8_SD1PID_SODDFRM_Msk = 0x20000000
	// Bit SD1PID_SODDFRM.
	OTG_HS_DOEPCTL8_SD1PID_SODDFRM = 0x20000000
	// Position of EPDIS field.
	OTG_HS_DOEPCTL8_EPDIS_Pos = 0x1e
	// Bit mask of EPDIS field.
	OTG_HS_DOEPCTL8_EPDIS_Msk = 0x40000000
	// Bit EPDIS.
	OTG_HS_DOEPCTL8_EPDIS = 0x40000000
	// Position of EPENA field.
	OTG_HS_DOEPCTL8_EPENA_Pos = 0x1f
	// Bit mask of EPENA field.
	OTG_HS_DOEPCTL8_EPENA_Msk = 0x80000000
	// Bit EPENA.
	OTG_HS_DOEPCTL8_EPENA = 0x80000000

	// DOEPINT8: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
	// Position of XFRC field.
	OTG_HS_DOEPINT8_XFRC_Pos = 0x0
	// Bit mask of XFRC field.
	OTG_HS_DOEPINT8_XFRC_Msk = 0x1
	// Bit XFRC.
	OTG_HS_DOEPINT8_XFRC = 0x1
	// Position of EPDISD field.
	OTG_HS_DOEPINT8_EPDISD_Pos = 0x1
	// Bit mask of EPDISD field.
	OTG_HS_DOEPINT8_EPDISD_Msk = 0x2
	// Bit EPDISD.
	OTG_HS_DOEPINT8_EPDISD = 0x2
	// Position of AHBERR field.
	OTG_HS_DOEPINT8_AHBERR_Pos = 0x2
	// Bit mask of AHBERR field.
	OTG_HS_DOEPINT8_AHBERR_Msk = 0x4
	// Bit AHBERR.
	OTG_HS_DOEPINT8_AHBERR = 0x4
	// Position of STUP field.
	OTG_HS_DOEPINT8_STUP_Pos = 0x3
	// Bit mask of STUP field.
	OTG_HS_DOEPINT8_STUP_Msk = 0x8
	// Bit STUP.
	OTG_HS_DOEPINT8_STUP = 0x8
	// Position of OTEPDIS field.
	OTG_HS_DOEPINT8_OTEPDIS_Pos = 0x4
	// Bit mask of OTEPDIS field.
	OTG_HS_DOEPINT8_OTEPDIS_Msk = 0x10
	// Bit OTEPDIS.
	OTG_HS_DOEPINT8_OTEPDIS = 0x10
	// Position of STSPHSRX field.
	OTG_HS_DOEPINT8_STSPHSRX_Pos = 0x5
	// Bit mask of STSPHSRX field.
	OTG_HS_DOEPINT8_STSPHSRX_Msk = 0x20
	// Bit STSPHSRX.
	OTG_HS_DOEPINT8_STSPHSRX = 0x20
	// Position of B2BSTUP field.
	OTG_HS_DOEPINT8_B2BSTUP_Pos = 0x6
	// Bit mask of B2BSTUP field.
	OTG_HS_DOEPINT8_B2BSTUP_Msk = 0x40
	// Bit B2BSTUP.
	OTG_HS_DOEPINT8_B2BSTUP = 0x40
	// Position of OUTPKTERR field.
	OTG_HS_DOEPINT8_OUTPKTERR_Pos = 0x8
	// Bit mask of OUTPKTERR field.
	OTG_HS_DOEPINT8_OUTPKTERR_Msk = 0x100
	// Bit OUTPKTERR.
	OTG_HS_DOEPINT8_OUTPKTERR = 0x100
	// Position of BNA field.
	OTG_HS_DOEPINT8_BNA_Pos = 0x9
	// Bit mask of BNA field.
	OTG_HS_DOEPINT8_BNA_Msk = 0x200
	// Bit BNA.
	OTG_HS_DOEPINT8_BNA = 0x200
	// Position of BERR field.
	OTG_HS_DOEPINT8_BERR_Pos = 0xc
	// Bit mask of BERR field.
	OTG_HS_DOEPINT8_BERR_Msk = 0x1000
	// Bit BERR.
	OTG_HS_DOEPINT8_BERR = 0x1000
	// Position of NAK field.
	OTG_HS_DOEPINT8_NAK_Pos = 0xd
	// Bit mask of NAK field.
	OTG_HS_DOEPINT8_NAK_Msk = 0x2000
	// Bit NAK.
	OTG_HS_DOEPINT8_NAK = 0x2000
	// Position of NYET field.
	OTG_HS_DOEPINT8_NYET_Pos = 0xe
	// Bit mask of NYET field.
	OTG_HS_DOEPINT8_NYET_Msk = 0x4000
	// Bit NYET.
	OTG_HS_DOEPINT8_NYET = 0x4000
	// Position of STPKTRX field.
	OTG_HS_DOEPINT8_STPKTRX_Pos = 0xf
	// Bit mask of STPKTRX field.
	OTG_HS_DOEPINT8_STPKTRX_Msk = 0x8000
	// Bit STPKTRX.
	OTG_HS_DOEPINT8_STPKTRX = 0x8000

	// DOEPTSIZ8: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
	// Position of XFRSIZ field.
	OTG_HS_DOEPTSIZ8_XFRSIZ_Pos = 0x0
	// Bit mask of XFRSIZ field.
	OTG_HS_DOEPTSIZ8_XFRSIZ_Msk = 0x7ffff
	// Position of PKTCNT field.
	OTG_HS_DOEPTSIZ8_PKTCNT_Pos = 0x13
	// Bit mask of PKTCNT field.
	OTG_HS_DOEPTSIZ8_PKTCNT_Msk = 0x1ff80000
	// Position of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ8_RXDPID_STUPCNT_Pos = 0x1d
	// Bit mask of RXDPID_STUPCNT field.
	OTG_HS_DOEPTSIZ8_RXDPID_STUPCNT_Msk = 0x60000000

	// DOEPDMA8: OTG device OUT endpoint 8 DMA address register
	// Position of DMAADDR field.
	OTG_HS_DOEPDMA8_DMAADDR_Pos = 0x0
	// Bit mask of DMAADDR field.
	OTG_HS_DOEPDMA8_DMAADDR_Msk = 0xffffffff

	// PCGCCTL: This register is available in host and device modes.
	// Position of STPPCLK field.
	OTG_HS_PCGCCTL_STPPCLK_Pos = 0x0
	// Bit mask of STPPCLK field.
	OTG_HS_PCGCCTL_STPPCLK_Msk = 0x1
	// Bit STPPCLK.
	OTG_HS_PCGCCTL_STPPCLK = 0x1
	// Position of GATEHCLK field.
	OTG_HS_PCGCCTL_GATEHCLK_Pos = 0x1
	// Bit mask of GATEHCLK field.
	OTG_HS_PCGCCTL_GATEHCLK_Msk = 0x2
	// Bit GATEHCLK.
	OTG_HS_PCGCCTL_GATEHCLK = 0x2
	// Position of PHYSUSP field.
	OTG_HS_PCGCCTL_PHYSUSP_Pos = 0x4
	// Bit mask of PHYSUSP field.
	OTG_HS_PCGCCTL_PHYSUSP_Msk = 0x10
	// Bit PHYSUSP.
	OTG_HS_PCGCCTL_PHYSUSP = 0x10
	// Position of ENL1GTG field.
	OTG_HS_PCGCCTL_ENL1GTG_Pos = 0x5
	// Bit mask of ENL1GTG field.
	OTG_HS_PCGCCTL_ENL1GTG_Msk = 0x20
	// Bit ENL1GTG.
	OTG_HS_PCGCCTL_ENL1GTG = 0x20
	// Position of PHYSLEEP field.
	OTG_HS_PCGCCTL_PHYSLEEP_Pos = 0x6
	// Bit mask of PHYSLEEP field.
	OTG_HS_PCGCCTL_PHYSLEEP_Msk = 0x40
	// Bit PHYSLEEP.
	OTG_HS_PCGCCTL_PHYSLEEP = 0x40
	// Position of SUSP field.
	OTG_HS_PCGCCTL_SUSP_Pos = 0x7
	// Bit mask of SUSP field.
	OTG_HS_PCGCCTL_SUSP_Msk = 0x80
	// Bit SUSP.
	OTG_HS_PCGCCTL_SUSP = 0x80
)

// Constants for PKA: Private key accelerator
const (
	// CR: Control register
	// Position of OPERRIE field.
	PKA_CR_OPERRIE_Pos = 0x15
	// Bit mask of OPERRIE field.
	PKA_CR_OPERRIE_Msk = 0x200000
	// Bit OPERRIE.
	PKA_CR_OPERRIE = 0x200000
	// Position of ADDRERRIE field.
	PKA_CR_ADDRERRIE_Pos = 0x14
	// Bit mask of ADDRERRIE field.
	PKA_CR_ADDRERRIE_Msk = 0x100000
	// Bit ADDRERRIE.
	PKA_CR_ADDRERRIE = 0x100000
	// Position of RAMERRIE field.
	PKA_CR_RAMERRIE_Pos = 0x13
	// Bit mask of RAMERRIE field.
	PKA_CR_RAMERRIE_Msk = 0x80000
	// Bit RAMERRIE.
	PKA_CR_RAMERRIE = 0x80000
	// Position of PROCENDIE field.
	PKA_CR_PROCENDIE_Pos = 0x11
	// Bit mask of PROCENDIE field.
	PKA_CR_PROCENDIE_Msk = 0x20000
	// Bit PROCENDIE.
	PKA_CR_PROCENDIE = 0x20000
	// Position of MODE field.
	PKA_CR_MODE_Pos = 0x8
	// Bit mask of MODE field.
	PKA_CR_MODE_Msk = 0x3f00
	// Position of START field.
	PKA_CR_START_Pos = 0x1
	// Bit mask of START field.
	PKA_CR_START_Msk = 0x2
	// Bit START.
	PKA_CR_START = 0x2
	// Position of EN field.
	PKA_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	PKA_CR_EN_Msk = 0x1
	// Bit EN.
	PKA_CR_EN = 0x1

	// SR: PKA status register
	// Position of INITOK field.
	PKA_SR_INITOK_Pos = 0x0
	// Bit mask of INITOK field.
	PKA_SR_INITOK_Msk = 0x1
	// Bit INITOK.
	PKA_SR_INITOK = 0x1
	// Position of BUSY field.
	PKA_SR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	PKA_SR_BUSY_Msk = 0x10000
	// Bit BUSY.
	PKA_SR_BUSY = 0x10000
	// Position of PROCENDF field.
	PKA_SR_PROCENDF_Pos = 0x11
	// Bit mask of PROCENDF field.
	PKA_SR_PROCENDF_Msk = 0x20000
	// Bit PROCENDF.
	PKA_SR_PROCENDF = 0x20000
	// Position of RAMERRF field.
	PKA_SR_RAMERRF_Pos = 0x13
	// Bit mask of RAMERRF field.
	PKA_SR_RAMERRF_Msk = 0x80000
	// Bit RAMERRF.
	PKA_SR_RAMERRF = 0x80000
	// Position of ADDRERRF field.
	PKA_SR_ADDRERRF_Pos = 0x14
	// Bit mask of ADDRERRF field.
	PKA_SR_ADDRERRF_Msk = 0x100000
	// Bit ADDRERRF.
	PKA_SR_ADDRERRF = 0x100000
	// Position of OPERRF field.
	PKA_SR_OPERRF_Pos = 0x15
	// Bit mask of OPERRF field.
	PKA_SR_OPERRF_Msk = 0x200000
	// Bit OPERRF.
	PKA_SR_OPERRF = 0x200000

	// CLRFR: PKA clear flag register
	// Position of PROCENDFC field.
	PKA_CLRFR_PROCENDFC_Pos = 0x11
	// Bit mask of PROCENDFC field.
	PKA_CLRFR_PROCENDFC_Msk = 0x20000
	// Bit PROCENDFC.
	PKA_CLRFR_PROCENDFC = 0x20000
	// Position of RAMERRFC field.
	PKA_CLRFR_RAMERRFC_Pos = 0x13
	// Bit mask of RAMERRFC field.
	PKA_CLRFR_RAMERRFC_Msk = 0x80000
	// Bit RAMERRFC.
	PKA_CLRFR_RAMERRFC = 0x80000
	// Position of ADDRERRFC field.
	PKA_CLRFR_ADDRERRFC_Pos = 0x14
	// Bit mask of ADDRERRFC field.
	PKA_CLRFR_ADDRERRFC_Msk = 0x100000
	// Bit ADDRERRFC.
	PKA_CLRFR_ADDRERRFC = 0x100000
	// Position of OPERRFC field.
	PKA_CLRFR_OPERRFC_Pos = 0x15
	// Bit mask of OPERRFC field.
	PKA_CLRFR_OPERRFC_Msk = 0x200000
	// Bit OPERRFC.
	PKA_CLRFR_OPERRFC = 0x200000
)

// Constants for PSSI: PSSI
const (
	// CR: PSSI control register
	// Position of CKPOL field.
	PSSI_CR_CKPOL_Pos = 0x5
	// Bit mask of CKPOL field.
	PSSI_CR_CKPOL_Msk = 0x20
	// Bit CKPOL.
	PSSI_CR_CKPOL = 0x20
	// Falling edge active for inputs or rising edge active for outputs
	PSSI_CR_CKPOL_FallingEdge = 0x0
	// Rising edge active for inputs or falling edge active for outputs
	PSSI_CR_CKPOL_RisingEdge = 0x1
	// Position of DEPOL field.
	PSSI_CR_DEPOL_Pos = 0x6
	// Bit mask of DEPOL field.
	PSSI_CR_DEPOL_Msk = 0x40
	// Bit DEPOL.
	PSSI_CR_DEPOL = 0x40
	// PSSI_DE active low (0 indicates that data is valid)
	PSSI_CR_DEPOL_ActiveLow = 0x0
	// PSSI_DE active high (1 indicates that data is valid)
	PSSI_CR_DEPOL_ActiveHigh = 0x1
	// Position of RDYPOL field.
	PSSI_CR_RDYPOL_Pos = 0x8
	// Bit mask of RDYPOL field.
	PSSI_CR_RDYPOL_Msk = 0x100
	// Bit RDYPOL.
	PSSI_CR_RDYPOL = 0x100
	// PSSI_RDY active low (0 indicates that the receiver is ready to receive)
	PSSI_CR_RDYPOL_ActiveLow = 0x0
	// PSSI_RDY active high (1 indicates that the receiver is ready to receive)
	PSSI_CR_RDYPOL_ActiveHigh = 0x1
	// Position of EDM field.
	PSSI_CR_EDM_Pos = 0xa
	// Bit mask of EDM field.
	PSSI_CR_EDM_Msk = 0xc00
	// Interface captures 8-bit data on every parallel data clock
	PSSI_CR_EDM_BitWidth8 = 0x0
	// The interface captures 16-bit data on every parallel data clock
	PSSI_CR_EDM_BitWidth16 = 0x3
	// Position of ENABLE field.
	PSSI_CR_ENABLE_Pos = 0xe
	// Bit mask of ENABLE field.
	PSSI_CR_ENABLE_Msk = 0x4000
	// Bit ENABLE.
	PSSI_CR_ENABLE = 0x4000
	// PSSI disabled
	PSSI_CR_ENABLE_Disabled = 0x0
	// PSSI enabled
	PSSI_CR_ENABLE_Enabled = 0x1
	// Position of DERDYCFG field.
	PSSI_CR_DERDYCFG_Pos = 0x12
	// Bit mask of DERDYCFG field.
	PSSI_CR_DERDYCFG_Msk = 0x1c0000
	// PSSI_DE and PSSI_RDY both disabled
	PSSI_CR_DERDYCFG_Disabled = 0x0
	// Only PSSI_RDY enabled
	PSSI_CR_DERDYCFG_Rdy = 0x1
	// Only PSSI_DE enabled
	PSSI_CR_DERDYCFG_De = 0x2
	// Both PSSI_RDY and PSSI_DE alternate functions enabled
	PSSI_CR_DERDYCFG_RdyDeAlt = 0x3
	// Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin
	PSSI_CR_DERDYCFG_RdyDe = 0x4
	// Only PSSI_RDY function enabled, but mapped to PSSI_DE pin
	PSSI_CR_DERDYCFG_RdyRemapped = 0x5
	// Only PSSI_DE function enabled, but mapped to PSSI_RDY pin
	PSSI_CR_DERDYCFG_DeRemapped = 0x6
	// Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin
	PSSI_CR_DERDYCFG_RdyDeBidi = 0x7
	// Position of DMAEN field.
	PSSI_CR_DMAEN_Pos = 0x1e
	// Bit mask of DMAEN field.
	PSSI_CR_DMAEN_Msk = 0x40000000
	// Bit DMAEN.
	PSSI_CR_DMAEN = 0x40000000
	// DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled.
	PSSI_CR_DMAEN_Disabled = 0x0
	// DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR
	PSSI_CR_DMAEN_Enabled = 0x1
	// Position of OUTEN field.
	PSSI_CR_OUTEN_Pos = 0x1f
	// Bit mask of OUTEN field.
	PSSI_CR_OUTEN_Msk = 0x80000000
	// Bit OUTEN.
	PSSI_CR_OUTEN = 0x80000000
	// Data is input synchronously with PSSI_PDCK
	PSSI_CR_OUTEN_ReceiveMode = 0x0
	// Data is output synchronously with PSSI_PDCK
	PSSI_CR_OUTEN_TransmitMode = 0x1

	// SR: PSSI status register
	// Position of RTT4B field.
	PSSI_SR_RTT4B_Pos = 0x2
	// Bit mask of RTT4B field.
	PSSI_SR_RTT4B_Msk = 0x4
	// Bit RTT4B.
	PSSI_SR_RTT4B = 0x4
	// FIFO is not ready for a four-byte transfer
	PSSI_SR_RTT4B_NotReady = 0x0
	// FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO
	PSSI_SR_RTT4B_Ready = 0x1
	// Position of RTT1B field.
	PSSI_SR_RTT1B_Pos = 0x3
	// Bit mask of RTT1B field.
	PSSI_SR_RTT1B_Msk = 0x8
	// Bit RTT1B.
	PSSI_SR_RTT1B = 0x8
	// FIFO is not ready for a 1-byte transfer
	PSSI_SR_RTT1B_NotReady = 0x0
	// FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO
	PSSI_SR_RTT1B_Ready = 0x1

	// RIS: PSSI raw interrupt status register
	// Position of OVR_RIS field.
	PSSI_RIS_OVR_RIS_Pos = 0x1
	// Bit mask of OVR_RIS field.
	PSSI_RIS_OVR_RIS_Msk = 0x2
	// Bit OVR_RIS.
	PSSI_RIS_OVR_RIS = 0x2
	// No overrun/underrun occurred
	PSSI_RIS_OVR_RIS_Cleared = 0x0
	// An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR
	PSSI_RIS_OVR_RIS_Occurred = 0x1

	// IER: PSSI interrupt enable register
	// Position of OVR_IE field.
	PSSI_IER_OVR_IE_Pos = 0x1
	// Bit mask of OVR_IE field.
	PSSI_IER_OVR_IE_Msk = 0x2
	// Bit OVR_IE.
	PSSI_IER_OVR_IE = 0x2
	// No interrupt generation
	PSSI_IER_OVR_IE_Disabled = 0x0
	// An interrupt is generated if either an overrun or an underrun error occurred
	PSSI_IER_OVR_IE_Enabled = 0x1

	// MIS: PSSI masked interrupt status register
	// Position of OVR_MIS field.
	PSSI_MIS_OVR_MIS_Pos = 0x1
	// Bit mask of OVR_MIS field.
	PSSI_MIS_OVR_MIS_Msk = 0x2
	// Bit OVR_MIS.
	PSSI_MIS_OVR_MIS = 0x2
	// No interrupt is generated when an overrun/underrun error occurs
	PSSI_MIS_OVR_MIS_Disabled = 0x0
	// An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER
	PSSI_MIS_OVR_MIS_Enabled = 0x1

	// ICR: PSSI interrupt clear register
	// Position of OVR_ISC field.
	PSSI_ICR_OVR_ISC_Pos = 0x1
	// Bit mask of OVR_ISC field.
	PSSI_ICR_OVR_ISC_Msk = 0x2
	// Bit OVR_ISC.
	PSSI_ICR_OVR_ISC = 0x2
	// Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS
	PSSI_ICR_OVR_ISC_Clear = 0x1

	// DR: PSSI data register
	// Position of BYTE0 field.
	PSSI_DR_BYTE0_Pos = 0x0
	// Bit mask of BYTE0 field.
	PSSI_DR_BYTE0_Msk = 0xff
	// Position of BYTE1 field.
	PSSI_DR_BYTE1_Pos = 0x8
	// Bit mask of BYTE1 field.
	PSSI_DR_BYTE1_Msk = 0xff00
	// Position of BYTE2 field.
	PSSI_DR_BYTE2_Pos = 0x10
	// Bit mask of BYTE2 field.
	PSSI_DR_BYTE2_Msk = 0xff0000
	// Position of BYTE3 field.
	PSSI_DR_BYTE3_Pos = 0x18
	// Bit mask of BYTE3 field.
	PSSI_DR_BYTE3_Msk = 0xff000000
)

// Constants for PWR: Power control
const (
	// CR1: PWR control register 1
	// Position of LPMS field.
	PWR_CR1_LPMS_Pos = 0x0
	// Bit mask of LPMS field.
	PWR_CR1_LPMS_Msk = 0x7
	// Stop 0 mode
	PWR_CR1_LPMS_Stop0 = 0x0
	// Stop 1 mode
	PWR_CR1_LPMS_Stop1 = 0x1
	// Stop 2 mode
	PWR_CR1_LPMS_Stop2 = 0x2
	// Stop 3 mode
	PWR_CR1_LPMS_Stop3 = 0x3
	// Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1)
	PWR_CR1_LPMS_Standby = 0x4
	// Shutdown mode if BREN = 0 in PWR_BDCR1
	PWR_CR1_LPMS_Shutdown = 0x6
	// Position of RRSB1 field.
	PWR_CR1_RRSB1_Pos = 0x5
	// Bit mask of RRSB1 field.
	PWR_CR1_RRSB1_Msk = 0x20
	// Bit RRSB1.
	PWR_CR1_RRSB1 = 0x20
	// SRAM2 page1 content not retained in Stop3 and Standby modes
	PWR_CR1_RRSB1_Disabled = 0x0
	// SRAM2 page1 content retained in Stop 3 and Standby modes
	PWR_CR1_RRSB1_Enabled = 0x1
	// Position of RRSB2 field.
	PWR_CR1_RRSB2_Pos = 0x6
	// Bit mask of RRSB2 field.
	PWR_CR1_RRSB2_Msk = 0x40
	// Bit RRSB2.
	PWR_CR1_RRSB2 = 0x40
	// SRAM2 page2 content not retained in Stop3 and Standby modes
	PWR_CR1_RRSB2_Disabled = 0x0
	// SRAM2 page2 content retained in Stop 3 and Standby modes
	PWR_CR1_RRSB2_Enabled = 0x1
	// Position of ULPMEN field.
	PWR_CR1_ULPMEN_Pos = 0x7
	// Bit mask of ULPMEN field.
	PWR_CR1_ULPMEN_Msk = 0x80
	// Bit ULPMEN.
	PWR_CR1_ULPMEN = 0x80
	// BOR level 0 operating in continuous (normal) mode in Standby mode
	PWR_CR1_ULPMEN_Disabled = 0x0
	// BOR level 0 operating in discontinuous (ultra-low power) mode in Standby mode
	PWR_CR1_ULPMEN_Enabled = 0x1
	// Position of SRAM1PD field.
	PWR_CR1_SRAM1PD_Pos = 0x8
	// Bit mask of SRAM1PD field.
	PWR_CR1_SRAM1PD_Msk = 0x100
	// Bit SRAM1PD.
	PWR_CR1_SRAM1PD = 0x100
	// SRAMx powered on
	PWR_CR1_SRAM1PD_On = 0x0
	// SRAMx powered off
	PWR_CR1_SRAM1PD_Off = 0x1
	// Position of SRAM2PD field.
	PWR_CR1_SRAM2PD_Pos = 0x9
	// Bit mask of SRAM2PD field.
	PWR_CR1_SRAM2PD_Msk = 0x200
	// Bit SRAM2PD.
	PWR_CR1_SRAM2PD = 0x200
	// SRAMx powered on
	PWR_CR1_SRAM2PD_On = 0x0
	// SRAMx powered off
	PWR_CR1_SRAM2PD_Off = 0x1
	// Position of SRAM3PD field.
	PWR_CR1_SRAM3PD_Pos = 0xa
	// Bit mask of SRAM3PD field.
	PWR_CR1_SRAM3PD_Msk = 0x400
	// Bit SRAM3PD.
	PWR_CR1_SRAM3PD = 0x400
	// SRAMx powered on
	PWR_CR1_SRAM3PD_On = 0x0
	// SRAMx powered off
	PWR_CR1_SRAM3PD_Off = 0x1
	// Position of SRAM4PD field.
	PWR_CR1_SRAM4PD_Pos = 0xb
	// Bit mask of SRAM4PD field.
	PWR_CR1_SRAM4PD_Msk = 0x800
	// Bit SRAM4PD.
	PWR_CR1_SRAM4PD = 0x800
	// SRAMx powered on
	PWR_CR1_SRAM4PD_On = 0x0
	// SRAMx powered off
	PWR_CR1_SRAM4PD_Off = 0x1
	// Position of SRAM5PD field.
	PWR_CR1_SRAM5PD_Pos = 0xc
	// Bit mask of SRAM5PD field.
	PWR_CR1_SRAM5PD_Msk = 0x1000
	// Bit SRAM5PD.
	PWR_CR1_SRAM5PD = 0x1000
	// SRAMx powered on
	PWR_CR1_SRAM5PD_On = 0x0
	// SRAMx powered off
	PWR_CR1_SRAM5PD_Off = 0x1
	// Position of FORCE_USBPWR field.
	PWR_CR1_FORCE_USBPWR_Pos = 0xf
	// Bit mask of FORCE_USBPWR field.
	PWR_CR1_FORCE_USBPWR_Msk = 0x8000
	// Bit FORCE_USBPWR.
	PWR_CR1_FORCE_USBPWR = 0x8000
	// OTG_HS PHY power is not maintained during low-power modes
	PWR_CR1_FORCE_USBPWR_Disabled = 0x0
	// OTG_HS PHY power is maintained during low-power modes
	PWR_CR1_FORCE_USBPWR_Enabled = 0x1

	// CR2: PWR control register 2
	// Position of SRAM1PDS1 field.
	PWR_CR2_SRAM1PDS1_Pos = 0x0
	// Bit mask of SRAM1PDS1 field.
	PWR_CR2_SRAM1PDS1_Msk = 0x1
	// Bit SRAM1PDS1.
	PWR_CR2_SRAM1PDS1 = 0x1
	// SRAM1 page x content retained in Stop modes
	PWR_CR2_SRAM1PDS1_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR2_SRAM1PDS1_Enabled = 0x1
	// Position of SRAM1PDS2 field.
	PWR_CR2_SRAM1PDS2_Pos = 0x1
	// Bit mask of SRAM1PDS2 field.
	PWR_CR2_SRAM1PDS2_Msk = 0x2
	// Bit SRAM1PDS2.
	PWR_CR2_SRAM1PDS2 = 0x2
	// SRAM1 page x content retained in Stop modes
	PWR_CR2_SRAM1PDS2_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR2_SRAM1PDS2_Enabled = 0x1
	// Position of SRAM1PDS3 field.
	PWR_CR2_SRAM1PDS3_Pos = 0x2
	// Bit mask of SRAM1PDS3 field.
	PWR_CR2_SRAM1PDS3_Msk = 0x4
	// Bit SRAM1PDS3.
	PWR_CR2_SRAM1PDS3 = 0x4
	// SRAM1 page x content retained in Stop modes
	PWR_CR2_SRAM1PDS3_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR2_SRAM1PDS3_Enabled = 0x1
	// Position of SRAM2PDS1 field.
	PWR_CR2_SRAM2PDS1_Pos = 0x4
	// Bit mask of SRAM2PDS1 field.
	PWR_CR2_SRAM2PDS1_Msk = 0x10
	// Bit SRAM2PDS1.
	PWR_CR2_SRAM2PDS1 = 0x10
	// SRAM2 page x content retained in Stop modes
	PWR_CR2_SRAM2PDS1_Disabled = 0x0
	// SRAM2 page x content lost in Stop modes
	PWR_CR2_SRAM2PDS1_Enabled = 0x1
	// Position of SRAM2PDS2 field.
	PWR_CR2_SRAM2PDS2_Pos = 0x5
	// Bit mask of SRAM2PDS2 field.
	PWR_CR2_SRAM2PDS2_Msk = 0x20
	// Bit SRAM2PDS2.
	PWR_CR2_SRAM2PDS2 = 0x20
	// SRAM2 page x content retained in Stop modes
	PWR_CR2_SRAM2PDS2_Disabled = 0x0
	// SRAM2 page x content lost in Stop modes
	PWR_CR2_SRAM2PDS2_Enabled = 0x1
	// Position of SRAM4PDS field.
	PWR_CR2_SRAM4PDS_Pos = 0x6
	// Bit mask of SRAM4PDS field.
	PWR_CR2_SRAM4PDS_Msk = 0x40
	// Bit SRAM4PDS.
	PWR_CR2_SRAM4PDS = 0x40
	// SRAM4 content retained in Stop modes
	PWR_CR2_SRAM4PDS_Disabled = 0x0
	// SRAM4 content lost in Stop modes
	PWR_CR2_SRAM4PDS_Enabled = 0x1
	// Position of ICRAMPDS field.
	PWR_CR2_ICRAMPDS_Pos = 0x8
	// Bit mask of ICRAMPDS field.
	PWR_CR2_ICRAMPDS_Msk = 0x100
	// Bit ICRAMPDS.
	PWR_CR2_ICRAMPDS = 0x100
	// ICACHE SRAM content retained in Stop modes
	PWR_CR2_ICRAMPDS_Disabled = 0x0
	// ICACHE SRAM content lost in Stop modes
	PWR_CR2_ICRAMPDS_Enabled = 0x1
	// Position of DC1RAMPDS field.
	PWR_CR2_DC1RAMPDS_Pos = 0x9
	// Bit mask of DC1RAMPDS field.
	PWR_CR2_DC1RAMPDS_Msk = 0x200
	// Bit DC1RAMPDS.
	PWR_CR2_DC1RAMPDS = 0x200
	// DCACHE1 SRAM content retained in Stop modes
	PWR_CR2_DC1RAMPDS_Disabled = 0x0
	// DCACHE1 SRAM content lost in Stop modes
	PWR_CR2_DC1RAMPDS_Enabled = 0x1
	// Position of DMA2DRAMPDS field.
	PWR_CR2_DMA2DRAMPDS_Pos = 0xa
	// Bit mask of DMA2DRAMPDS field.
	PWR_CR2_DMA2DRAMPDS_Msk = 0x400
	// Bit DMA2DRAMPDS.
	PWR_CR2_DMA2DRAMPDS = 0x400
	// DMA2D SRAM content retained in Stop modes
	PWR_CR2_DMA2DRAMPDS_Disabled = 0x0
	// DMA2D SRAM content lost in Stop modes
	PWR_CR2_DMA2DRAMPDS_Enabled = 0x1
	// Position of PRAMPDS field.
	PWR_CR2_PRAMPDS_Pos = 0xb
	// Bit mask of PRAMPDS field.
	PWR_CR2_PRAMPDS_Msk = 0x800
	// Bit PRAMPDS.
	PWR_CR2_PRAMPDS = 0x800
	// FMAC, FDCAN, and USB/OTG_FS/OTG_HS SRAM content retained in Stop modes
	PWR_CR2_PRAMPDS_Disabled = 0x0
	// FMAC, FDCAN, and USB/OTG_FS/OTG_HS SRAM content lost in Stop modes
	PWR_CR2_PRAMPDS_Enabled = 0x1
	// Position of PKARAMPDS field.
	PWR_CR2_PKARAMPDS_Pos = 0xc
	// Bit mask of PKARAMPDS field.
	PWR_CR2_PKARAMPDS_Msk = 0x1000
	// Bit PKARAMPDS.
	PWR_CR2_PKARAMPDS = 0x1000
	// PKA SRAM content retained in Stop modes
	PWR_CR2_PKARAMPDS_Disabled = 0x0
	// PKA SRAM content lost in Stop modes
	PWR_CR2_PKARAMPDS_Enabled = 0x1
	// Position of SRAM4FWU field.
	PWR_CR2_SRAM4FWU_Pos = 0xd
	// Bit mask of SRAM4FWU field.
	PWR_CR2_SRAM4FWU_Msk = 0x2000
	// Bit SRAM4FWU.
	PWR_CR2_SRAM4FWU = 0x2000
	// SRAM4 enters low-power mode in Stop 0/1/2 modes (source biasing for lower-power consumption)
	PWR_CR2_SRAM4FWU_Disabled = 0x0
	// SRAM4 remains in normal mode in Stop 0/1/2 modes (higher consumption but no SRAM4 wake-up time)
	PWR_CR2_SRAM4FWU_Enabled = 0x1
	// Position of FLASHFWU field.
	PWR_CR2_FLASHFWU_Pos = 0xe
	// Bit mask of FLASHFWU field.
	PWR_CR2_FLASHFWU_Msk = 0x4000
	// Bit FLASHFWU.
	PWR_CR2_FLASHFWU = 0x4000
	// Flash memory enters low-power mode in Stop 0/1 modes (lower-power consumption)
	PWR_CR2_FLASHFWU_Disabled = 0x0
	// Flash memory remains in normal mode in Stop 0/1 modes (faster wake-up time)
	PWR_CR2_FLASHFWU_Enabled = 0x1
	// Position of SRAM3PDS1 field.
	PWR_CR2_SRAM3PDS1_Pos = 0x10
	// Bit mask of SRAM3PDS1 field.
	PWR_CR2_SRAM3PDS1_Msk = 0x10000
	// Bit SRAM3PDS1.
	PWR_CR2_SRAM3PDS1 = 0x10000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS1_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS1_Enabled = 0x1
	// Position of SRAM3PDS2 field.
	PWR_CR2_SRAM3PDS2_Pos = 0x11
	// Bit mask of SRAM3PDS2 field.
	PWR_CR2_SRAM3PDS2_Msk = 0x20000
	// Bit SRAM3PDS2.
	PWR_CR2_SRAM3PDS2 = 0x20000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS2_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS2_Enabled = 0x1
	// Position of SRAM3PDS3 field.
	PWR_CR2_SRAM3PDS3_Pos = 0x12
	// Bit mask of SRAM3PDS3 field.
	PWR_CR2_SRAM3PDS3_Msk = 0x40000
	// Bit SRAM3PDS3.
	PWR_CR2_SRAM3PDS3 = 0x40000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS3_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS3_Enabled = 0x1
	// Position of SRAM3PDS4 field.
	PWR_CR2_SRAM3PDS4_Pos = 0x13
	// Bit mask of SRAM3PDS4 field.
	PWR_CR2_SRAM3PDS4_Msk = 0x80000
	// Bit SRAM3PDS4.
	PWR_CR2_SRAM3PDS4 = 0x80000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS4_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS4_Enabled = 0x1
	// Position of SRAM3PDS5 field.
	PWR_CR2_SRAM3PDS5_Pos = 0x14
	// Bit mask of SRAM3PDS5 field.
	PWR_CR2_SRAM3PDS5_Msk = 0x100000
	// Bit SRAM3PDS5.
	PWR_CR2_SRAM3PDS5 = 0x100000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS5_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS5_Enabled = 0x1
	// Position of SRAM3PDS6 field.
	PWR_CR2_SRAM3PDS6_Pos = 0x15
	// Bit mask of SRAM3PDS6 field.
	PWR_CR2_SRAM3PDS6_Msk = 0x200000
	// Bit SRAM3PDS6.
	PWR_CR2_SRAM3PDS6 = 0x200000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS6_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS6_Enabled = 0x1
	// Position of SRAM3PDS7 field.
	PWR_CR2_SRAM3PDS7_Pos = 0x16
	// Bit mask of SRAM3PDS7 field.
	PWR_CR2_SRAM3PDS7_Msk = 0x400000
	// Bit SRAM3PDS7.
	PWR_CR2_SRAM3PDS7 = 0x400000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS7_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS7_Enabled = 0x1
	// Position of SRAM3PDS8 field.
	PWR_CR2_SRAM3PDS8_Pos = 0x17
	// Bit mask of SRAM3PDS8 field.
	PWR_CR2_SRAM3PDS8_Msk = 0x800000
	// Bit SRAM3PDS8.
	PWR_CR2_SRAM3PDS8 = 0x800000
	// SRAM3 page x content retained in Stop modes
	PWR_CR2_SRAM3PDS8_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR2_SRAM3PDS8_Enabled = 0x1
	// Position of SRDRUN field.
	PWR_CR2_SRDRUN_Pos = 0x1f
	// Bit mask of SRDRUN field.
	PWR_CR2_SRDRUN_Msk = 0x80000000
	// Bit SRDRUN.
	PWR_CR2_SRDRUN = 0x80000000
	// SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0/1/2 modes
	PWR_CR2_SRDRUN_Disabled = 0x0
	// SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0/1/2 modes
	PWR_CR2_SRDRUN_Enabled = 0x1

	// CR3: PWR control register 3
	// Position of REGSEL field.
	PWR_CR3_REGSEL_Pos = 0x1
	// Bit mask of REGSEL field.
	PWR_CR3_REGSEL_Msk = 0x2
	// Bit REGSEL.
	PWR_CR3_REGSEL = 0x2
	// LDO selected
	PWR_CR3_REGSEL_LDO = 0x0
	// SMPS selected
	PWR_CR3_REGSEL_SMPS = 0x1
	// Position of FSTEN field.
	PWR_CR3_FSTEN_Pos = 0x2
	// Bit mask of FSTEN field.
	PWR_CR3_FSTEN_Msk = 0x4
	// Bit FSTEN.
	PWR_CR3_FSTEN = 0x4
	// LDO/SMPS fast startup disabled (limited inrush current)
	PWR_CR3_FSTEN_Disabled = 0x0
	// LDO/SMPS fast startup enabled
	PWR_CR3_FSTEN_Enabled = 0x1

	// VOSR: PWR voltage scaling register
	// Position of USBBOOSTRDY field.
	PWR_VOSR_USBBOOSTRDY_Pos = 0xd
	// Bit mask of USBBOOSTRDY field.
	PWR_VOSR_USBBOOSTRDY_Msk = 0x2000
	// Bit USBBOOSTRDY.
	PWR_VOSR_USBBOOSTRDY = 0x2000
	// OTG_HS power booster not ready
	PWR_VOSR_USBBOOSTRDY_NotReady = 0x0
	// OTG_HS power booster ready
	PWR_VOSR_USBBOOSTRDY_Ready = 0x1
	// Position of BOOSTRDY field.
	PWR_VOSR_BOOSTRDY_Pos = 0xe
	// Bit mask of BOOSTRDY field.
	PWR_VOSR_BOOSTRDY_Msk = 0x4000
	// Bit BOOSTRDY.
	PWR_VOSR_BOOSTRDY = 0x4000
	// Power booster not ready
	PWR_VOSR_BOOSTRDY_NotReady = 0x0
	// Power booster ready
	PWR_VOSR_BOOSTRDY_Ready = 0x1
	// Position of VOSRDY field.
	PWR_VOSR_VOSRDY_Pos = 0xf
	// Bit mask of VOSRDY field.
	PWR_VOSR_VOSRDY_Msk = 0x8000
	// Bit VOSRDY.
	PWR_VOSR_VOSRDY = 0x8000
	// Not ready, voltage level < VOS selected level
	PWR_VOSR_VOSRDY_NotReady = 0x0
	// Ready, voltage level ≥ VOS selected level
	PWR_VOSR_VOSRDY_Ready = 0x1
	// Position of VOS field.
	PWR_VOSR_VOS_Pos = 0x10
	// Bit mask of VOS field.
	PWR_VOSR_VOS_Msk = 0x30000
	// Range 4 (lowest power)
	PWR_VOSR_VOS_Range4 = 0x0
	// Range 3
	PWR_VOSR_VOS_Range3 = 0x1
	// Range 2
	PWR_VOSR_VOS_Range2 = 0x2
	// Range 1 (highest frequency)
	PWR_VOSR_VOS_Range1 = 0x3
	// Position of BOOSTEN field.
	PWR_VOSR_BOOSTEN_Pos = 0x12
	// Bit mask of BOOSTEN field.
	PWR_VOSR_BOOSTEN_Msk = 0x40000
	// Bit BOOSTEN.
	PWR_VOSR_BOOSTEN = 0x40000
	// Booster disabled
	PWR_VOSR_BOOSTEN_Disabled = 0x0
	// Booster enabled
	PWR_VOSR_BOOSTEN_Enabled = 0x1
	// Position of USBPWREN field.
	PWR_VOSR_USBPWREN_Pos = 0x13
	// Bit mask of USBPWREN field.
	PWR_VOSR_USBPWREN_Msk = 0x80000
	// Bit USBPWREN.
	PWR_VOSR_USBPWREN = 0x80000
	// OTG_HS power disabled
	PWR_VOSR_USBPWREN_Disabled = 0x0
	// OTG_HS power enabled
	PWR_VOSR_USBPWREN_Enabled = 0x1
	// Position of USBBOOSTEN field.
	PWR_VOSR_USBBOOSTEN_Pos = 0x14
	// Bit mask of USBBOOSTEN field.
	PWR_VOSR_USBBOOSTEN_Msk = 0x100000
	// Bit USBBOOSTEN.
	PWR_VOSR_USBBOOSTEN = 0x100000
	// OTG_HS booster disabled
	PWR_VOSR_USBBOOSTEN_Disabled = 0x0
	// OTG_HS booster enabled
	PWR_VOSR_USBBOOSTEN_Enabled = 0x1
	// Position of VDD11USBDIS field.
	PWR_VOSR_VDD11USBDIS_Pos = 0x15
	// Bit mask of VDD11USBDIS field.
	PWR_VOSR_VDD11USBDIS_Msk = 0x200000
	// Bit VDD11USBDIS.
	PWR_VOSR_VDD11USBDIS = 0x200000
	// VDD11USB enabled
	PWR_VOSR_VDD11USBDIS_Enabled = 0x0
	// VDD11USB disabled
	PWR_VOSR_VDD11USBDIS_Disabled = 0x1

	// SVMCR: PWR supply voltage monitoring control register
	// Position of PVDE field.
	PWR_SVMCR_PVDE_Pos = 0x4
	// Bit mask of PVDE field.
	PWR_SVMCR_PVDE_Msk = 0x10
	// Bit PVDE.
	PWR_SVMCR_PVDE = 0x10
	// PVD disabled
	PWR_SVMCR_PVDE_Disabled = 0x0
	// PVD enabled
	PWR_SVMCR_PVDE_Enabled = 0x1
	// Position of PVDLS field.
	PWR_SVMCR_PVDLS_Pos = 0x5
	// Bit mask of PVDLS field.
	PWR_SVMCR_PVDLS_Msk = 0xe0
	// VPVD0 around 2.0 V
	PWR_SVMCR_PVDLS_VPVD0 = 0x0
	// VPVD1 around 2.2 V
	PWR_SVMCR_PVDLS_VPVD1 = 0x1
	// VPVD2 around 2.4 V
	PWR_SVMCR_PVDLS_VPVD2 = 0x2
	// VPVD3 around 2.5 V
	PWR_SVMCR_PVDLS_VPVD3 = 0x3
	// VPVD4 around 2.6 V
	PWR_SVMCR_PVDLS_VPVD4 = 0x4
	// VPVD5 around 2.8 V
	PWR_SVMCR_PVDLS_VPVD5 = 0x5
	// VPVD6 around 2.9 V
	PWR_SVMCR_PVDLS_VPVD6 = 0x6
	// External input analog voltage PVD_IN (compared internally to VREFINT)
	PWR_SVMCR_PVDLS_PVDIN = 0x7
	// Position of UVMEN field.
	PWR_SVMCR_UVMEN_Pos = 0x18
	// Bit mask of UVMEN field.
	PWR_SVMCR_UVMEN_Msk = 0x1000000
	// Bit UVMEN.
	PWR_SVMCR_UVMEN = 0x1000000
	// VDDUSB voltage monitor disabled
	PWR_SVMCR_UVMEN_Disabled = 0x0
	// VDDUSB voltage monitor enabled
	PWR_SVMCR_UVMEN_Enabled = 0x1
	// Position of IO2VMEN field.
	PWR_SVMCR_IO2VMEN_Pos = 0x19
	// Bit mask of IO2VMEN field.
	PWR_SVMCR_IO2VMEN_Msk = 0x2000000
	// Bit IO2VMEN.
	PWR_SVMCR_IO2VMEN = 0x2000000
	// VDDIO2 voltage monitor disabled
	PWR_SVMCR_IO2VMEN_Disabled = 0x0
	// VDDIO2 voltage monitor enabled
	PWR_SVMCR_IO2VMEN_Enabled = 0x1
	// Position of AVM1EN field.
	PWR_SVMCR_AVM1EN_Pos = 0x1a
	// Bit mask of AVM1EN field.
	PWR_SVMCR_AVM1EN_Msk = 0x4000000
	// Bit AVM1EN.
	PWR_SVMCR_AVM1EN = 0x4000000
	// VDDA voltage monitor 1 disabled
	PWR_SVMCR_AVM1EN_Disabled = 0x0
	// VDDA voltage monitor 1 enabled
	PWR_SVMCR_AVM1EN_Enabled = 0x1
	// Position of AVM2EN field.
	PWR_SVMCR_AVM2EN_Pos = 0x1b
	// Bit mask of AVM2EN field.
	PWR_SVMCR_AVM2EN_Msk = 0x8000000
	// Bit AVM2EN.
	PWR_SVMCR_AVM2EN = 0x8000000
	// VDDA voltage monitor 2 disabled
	PWR_SVMCR_AVM2EN_Disabled = 0x0
	// VDDA voltage monitor 2 enabled
	PWR_SVMCR_AVM2EN_Enabled = 0x1
	// Position of USV field.
	PWR_SVMCR_USV_Pos = 0x1c
	// Bit mask of USV field.
	PWR_SVMCR_USV_Msk = 0x10000000
	// Bit USV.
	PWR_SVMCR_USV = 0x10000000
	// VDDUSB not present: logical and electrical isolation is applied to ignore this supply
	PWR_SVMCR_USV_NotPresent = 0x0
	// VDDUSB valid
	PWR_SVMCR_USV_Present = 0x1
	// Position of IO2SV field.
	PWR_SVMCR_IO2SV_Pos = 0x1d
	// Bit mask of IO2SV field.
	PWR_SVMCR_IO2SV_Msk = 0x20000000
	// Bit IO2SV.
	PWR_SVMCR_IO2SV = 0x20000000
	// VDDIO2 not present: logical and electrical isolation is applied to ignore this supply
	PWR_SVMCR_IO2SV_NotPresent = 0x0
	// VDDIO2 valid
	PWR_SVMCR_IO2SV_Present = 0x1
	// Position of ASV field.
	PWR_SVMCR_ASV_Pos = 0x1e
	// Bit mask of ASV field.
	PWR_SVMCR_ASV_Msk = 0x40000000
	// Bit ASV.
	PWR_SVMCR_ASV = 0x40000000
	// VDDA not present: logical and electrical isolation is applied to ignore this supply
	PWR_SVMCR_ASV_NotPresent = 0x0
	// VDDA valid
	PWR_SVMCR_ASV_Present = 0x1

	// WUCR1: PWR wakeup control register 1
	// Position of WUPEN1 field.
	PWR_WUCR1_WUPEN1_Pos = 0x0
	// Bit mask of WUPEN1 field.
	PWR_WUCR1_WUPEN1_Msk = 0x1
	// Bit WUPEN1.
	PWR_WUCR1_WUPEN1 = 0x1
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN1_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN1_Enabled = 0x1
	// Position of WUPEN2 field.
	PWR_WUCR1_WUPEN2_Pos = 0x1
	// Bit mask of WUPEN2 field.
	PWR_WUCR1_WUPEN2_Msk = 0x2
	// Bit WUPEN2.
	PWR_WUCR1_WUPEN2 = 0x2
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN2_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN2_Enabled = 0x1
	// Position of WUPEN3 field.
	PWR_WUCR1_WUPEN3_Pos = 0x2
	// Bit mask of WUPEN3 field.
	PWR_WUCR1_WUPEN3_Msk = 0x4
	// Bit WUPEN3.
	PWR_WUCR1_WUPEN3 = 0x4
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN3_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN3_Enabled = 0x1
	// Position of WUPEN4 field.
	PWR_WUCR1_WUPEN4_Pos = 0x3
	// Bit mask of WUPEN4 field.
	PWR_WUCR1_WUPEN4_Msk = 0x8
	// Bit WUPEN4.
	PWR_WUCR1_WUPEN4 = 0x8
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN4_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN4_Enabled = 0x1
	// Position of WUPEN5 field.
	PWR_WUCR1_WUPEN5_Pos = 0x4
	// Bit mask of WUPEN5 field.
	PWR_WUCR1_WUPEN5_Msk = 0x10
	// Bit WUPEN5.
	PWR_WUCR1_WUPEN5 = 0x10
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN5_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN5_Enabled = 0x1
	// Position of WUPEN6 field.
	PWR_WUCR1_WUPEN6_Pos = 0x5
	// Bit mask of WUPEN6 field.
	PWR_WUCR1_WUPEN6_Msk = 0x20
	// Bit WUPEN6.
	PWR_WUCR1_WUPEN6 = 0x20
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN6_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN6_Enabled = 0x1
	// Position of WUPEN7 field.
	PWR_WUCR1_WUPEN7_Pos = 0x6
	// Bit mask of WUPEN7 field.
	PWR_WUCR1_WUPEN7_Msk = 0x40
	// Bit WUPEN7.
	PWR_WUCR1_WUPEN7 = 0x40
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN7_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN7_Enabled = 0x1
	// Position of WUPEN8 field.
	PWR_WUCR1_WUPEN8_Pos = 0x7
	// Bit mask of WUPEN8 field.
	PWR_WUCR1_WUPEN8_Msk = 0x80
	// Bit WUPEN8.
	PWR_WUCR1_WUPEN8 = 0x80
	// Wakeup pin disabled
	PWR_WUCR1_WUPEN8_Disabled = 0x0
	// Wakeup pin enabled
	PWR_WUCR1_WUPEN8_Enabled = 0x1

	// WUCR2: PWR wakeup control register 2
	// Position of WUPP1 field.
	PWR_WUCR2_WUPP1_Pos = 0x0
	// Bit mask of WUPP1 field.
	PWR_WUCR2_WUPP1_Msk = 0x1
	// Bit WUPP1.
	PWR_WUCR2_WUPP1 = 0x1
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP1_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP1_FallingEdge = 0x1
	// Position of WUPP2 field.
	PWR_WUCR2_WUPP2_Pos = 0x1
	// Bit mask of WUPP2 field.
	PWR_WUCR2_WUPP2_Msk = 0x2
	// Bit WUPP2.
	PWR_WUCR2_WUPP2 = 0x2
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP2_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP2_FallingEdge = 0x1
	// Position of WUPP3 field.
	PWR_WUCR2_WUPP3_Pos = 0x2
	// Bit mask of WUPP3 field.
	PWR_WUCR2_WUPP3_Msk = 0x4
	// Bit WUPP3.
	PWR_WUCR2_WUPP3 = 0x4
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP3_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP3_FallingEdge = 0x1
	// Position of WUPP4 field.
	PWR_WUCR2_WUPP4_Pos = 0x3
	// Bit mask of WUPP4 field.
	PWR_WUCR2_WUPP4_Msk = 0x8
	// Bit WUPP4.
	PWR_WUCR2_WUPP4 = 0x8
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP4_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP4_FallingEdge = 0x1
	// Position of WUPP5 field.
	PWR_WUCR2_WUPP5_Pos = 0x4
	// Bit mask of WUPP5 field.
	PWR_WUCR2_WUPP5_Msk = 0x10
	// Bit WUPP5.
	PWR_WUCR2_WUPP5 = 0x10
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP5_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP5_FallingEdge = 0x1
	// Position of WUPP6 field.
	PWR_WUCR2_WUPP6_Pos = 0x5
	// Bit mask of WUPP6 field.
	PWR_WUCR2_WUPP6_Msk = 0x20
	// Bit WUPP6.
	PWR_WUCR2_WUPP6 = 0x20
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP6_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP6_FallingEdge = 0x1
	// Position of WUPP7 field.
	PWR_WUCR2_WUPP7_Pos = 0x6
	// Bit mask of WUPP7 field.
	PWR_WUCR2_WUPP7_Msk = 0x40
	// Bit WUPP7.
	PWR_WUCR2_WUPP7 = 0x40
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP7_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP7_FallingEdge = 0x1
	// Position of WUPP8 field.
	PWR_WUCR2_WUPP8_Pos = 0x7
	// Bit mask of WUPP8 field.
	PWR_WUCR2_WUPP8_Msk = 0x80
	// Bit WUPP8.
	PWR_WUCR2_WUPP8 = 0x80
	// Detection on high level (rising edge)
	PWR_WUCR2_WUPP8_RisingEdge = 0x0
	// Detection on low level (falling edge)
	PWR_WUCR2_WUPP8_FallingEdge = 0x1

	// WUCR3: PWR wakeup control register 3
	// Position of WUSEL1 field.
	PWR_WUCR3_WUSEL1_Pos = 0x0
	// Bit mask of WUSEL1 field.
	PWR_WUCR3_WUSEL1_Msk = 0x3
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL1_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL1_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL1_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL1_WKUPx_3 = 0x3
	// Position of WUSEL2 field.
	PWR_WUCR3_WUSEL2_Pos = 0x2
	// Bit mask of WUSEL2 field.
	PWR_WUCR3_WUSEL2_Msk = 0xc
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL2_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL2_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL2_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL2_WKUPx_3 = 0x3
	// Position of WUSEL3 field.
	PWR_WUCR3_WUSEL3_Pos = 0x4
	// Bit mask of WUSEL3 field.
	PWR_WUCR3_WUSEL3_Msk = 0x30
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL3_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL3_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL3_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL3_WKUPx_3 = 0x3
	// Position of WUSEL4 field.
	PWR_WUCR3_WUSEL4_Pos = 0x6
	// Bit mask of WUSEL4 field.
	PWR_WUCR3_WUSEL4_Msk = 0xc0
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL4_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL4_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL4_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL4_WKUPx_3 = 0x3
	// Position of WUSEL5 field.
	PWR_WUCR3_WUSEL5_Pos = 0x8
	// Bit mask of WUSEL5 field.
	PWR_WUCR3_WUSEL5_Msk = 0x300
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL5_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL5_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL5_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL5_WKUPx_3 = 0x3
	// Position of WUSEL6 field.
	PWR_WUCR3_WUSEL6_Pos = 0xa
	// Bit mask of WUSEL6 field.
	PWR_WUCR3_WUSEL6_Msk = 0xc00
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL6_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL6_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL6_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL6_WKUPx_3 = 0x3
	// Position of WUSEL7 field.
	PWR_WUCR3_WUSEL7_Pos = 0xc
	// Bit mask of WUSEL7 field.
	PWR_WUCR3_WUSEL7_Msk = 0x3000
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL7_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL7_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL7_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL7_WKUPx_3 = 0x3
	// Position of WUSEL8 field.
	PWR_WUCR3_WUSEL8_Pos = 0xe
	// Bit mask of WUSEL8 field.
	PWR_WUCR3_WUSEL8_Msk = 0xc000
	// Wakeup pin WKUPx_0 selected
	PWR_WUCR3_WUSEL8_WKUPx_0 = 0x0
	// Wakeup pin WKUPx_1 selected
	PWR_WUCR3_WUSEL8_WKUPx_1 = 0x1
	// Wakeup pin WKUPx_2 selected
	PWR_WUCR3_WUSEL8_WKUPx_2 = 0x2
	// Wakeup pin WKUPx_3 selected
	PWR_WUCR3_WUSEL8_WKUPx_3 = 0x3

	// BDCR1: PWR Backup domain control register 1
	// Position of BREN field.
	PWR_BDCR1_BREN_Pos = 0x0
	// Bit mask of BREN field.
	PWR_BDCR1_BREN_Msk = 0x1
	// Bit BREN.
	PWR_BDCR1_BREN = 0x1
	// Backup RAM content lost in Standby and VBAT modes
	PWR_BDCR1_BREN_Disabled = 0x0
	// Backup RAM content preserved in Standby and VBAT modes
	PWR_BDCR1_BREN_Enabled = 0x1
	// Position of MONEN field.
	PWR_BDCR1_MONEN_Pos = 0x4
	// Bit mask of MONEN field.
	PWR_BDCR1_MONEN_Msk = 0x10
	// Bit MONEN.
	PWR_BDCR1_MONEN = 0x10
	// Backup domain voltage and temperature monitoring disabled
	PWR_BDCR1_MONEN_Disabled = 0x0
	// Backup domain voltage and temperature monitoring enabled
	PWR_BDCR1_MONEN_Enabled = 0x1

	// BDCR2: PWR Backup domain control register 2
	// Position of VBE field.
	PWR_BDCR2_VBE_Pos = 0x0
	// Bit mask of VBE field.
	PWR_BDCR2_VBE_Msk = 0x1
	// Bit VBE.
	PWR_BDCR2_VBE = 0x1
	// VBAT battery charging disabled
	PWR_BDCR2_VBE_Disabled = 0x0
	// VBAT battery charging enabled
	PWR_BDCR2_VBE_Enabled = 0x1
	// Position of VBRS field.
	PWR_BDCR2_VBRS_Pos = 0x1
	// Bit mask of VBRS field.
	PWR_BDCR2_VBRS_Msk = 0x2
	// Bit VBRS.
	PWR_BDCR2_VBRS = 0x2
	// Charge VBAT through a 5 kOhm resistor
	PWR_BDCR2_VBRS_R_5k = 0x0
	// Charge VBAT through a 1.5 kOhm resistor
	PWR_BDCR2_VBRS_R_1k5 = 0x1

	// DBPR: PWR disable Backup domain register
	// Position of DBP field.
	PWR_DBPR_DBP_Pos = 0x0
	// Bit mask of DBP field.
	PWR_DBPR_DBP_Msk = 0x1
	// Bit DBP.
	PWR_DBPR_DBP = 0x1
	// Write access to backup domain disabled
	PWR_DBPR_DBP_Disabled = 0x0
	// Write access to backup domain enabled
	PWR_DBPR_DBP_Enabled = 0x1

	// UCPDR: PWR USB Type-C™ and Power Delivery register
	// Position of UCPD_DBDIS field.
	PWR_UCPDR_UCPD_DBDIS_Pos = 0x0
	// Bit mask of UCPD_DBDIS field.
	PWR_UCPDR_UCPD_DBDIS_Msk = 0x1
	// Bit UCPD_DBDIS.
	PWR_UCPDR_UCPD_DBDIS = 0x1
	// UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins
	PWR_UCPDR_UCPD_DBDIS_Enabled = 0x0
	// UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins
	PWR_UCPDR_UCPD_DBDIS_Disabled = 0x1
	// Position of UCPD_STBY field.
	PWR_UCPDR_UCPD_STBY_Pos = 0x1
	// Bit mask of UCPD_STBY field.
	PWR_UCPDR_UCPD_STBY_Msk = 0x2
	// Bit UCPD_STBY.
	PWR_UCPDR_UCPD_STBY = 0x2
	// UCPD configuration is not memorized in Standby mode (Must be in this state after exiting Stop 3 or Standby mode, and before writing any UCPD registers)
	PWR_UCPDR_UCPD_STBY_Disabled = 0x0
	// UCPD configuration is memorized in Stop 3 and Standby modes
	PWR_UCPDR_UCPD_STBY_Enabled = 0x1

	// SECCFGR: PWR security configuration register
	// Position of WUP1SEC field.
	PWR_SECCFGR_WUP1SEC_Pos = 0x0
	// Bit mask of WUP1SEC field.
	PWR_SECCFGR_WUP1SEC_Msk = 0x1
	// Bit WUP1SEC.
	PWR_SECCFGR_WUP1SEC = 0x1
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP1SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP1SEC_Secure = 0x1
	// Position of WUP2SEC field.
	PWR_SECCFGR_WUP2SEC_Pos = 0x1
	// Bit mask of WUP2SEC field.
	PWR_SECCFGR_WUP2SEC_Msk = 0x2
	// Bit WUP2SEC.
	PWR_SECCFGR_WUP2SEC = 0x2
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP2SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP2SEC_Secure = 0x1
	// Position of WUP3SEC field.
	PWR_SECCFGR_WUP3SEC_Pos = 0x2
	// Bit mask of WUP3SEC field.
	PWR_SECCFGR_WUP3SEC_Msk = 0x4
	// Bit WUP3SEC.
	PWR_SECCFGR_WUP3SEC = 0x4
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP3SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP3SEC_Secure = 0x1
	// Position of WUP4SEC field.
	PWR_SECCFGR_WUP4SEC_Pos = 0x3
	// Bit mask of WUP4SEC field.
	PWR_SECCFGR_WUP4SEC_Msk = 0x8
	// Bit WUP4SEC.
	PWR_SECCFGR_WUP4SEC = 0x8
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP4SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP4SEC_Secure = 0x1
	// Position of WUP5SEC field.
	PWR_SECCFGR_WUP5SEC_Pos = 0x4
	// Bit mask of WUP5SEC field.
	PWR_SECCFGR_WUP5SEC_Msk = 0x10
	// Bit WUP5SEC.
	PWR_SECCFGR_WUP5SEC = 0x10
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP5SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP5SEC_Secure = 0x1
	// Position of WUP6SEC field.
	PWR_SECCFGR_WUP6SEC_Pos = 0x5
	// Bit mask of WUP6SEC field.
	PWR_SECCFGR_WUP6SEC_Msk = 0x20
	// Bit WUP6SEC.
	PWR_SECCFGR_WUP6SEC = 0x20
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP6SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP6SEC_Secure = 0x1
	// Position of WUP7SEC field.
	PWR_SECCFGR_WUP7SEC_Pos = 0x6
	// Bit mask of WUP7SEC field.
	PWR_SECCFGR_WUP7SEC_Msk = 0x40
	// Bit WUP7SEC.
	PWR_SECCFGR_WUP7SEC = 0x40
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP7SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP7SEC_Secure = 0x1
	// Position of WUP8SEC field.
	PWR_SECCFGR_WUP8SEC_Pos = 0x7
	// Bit mask of WUP8SEC field.
	PWR_SECCFGR_WUP8SEC_Msk = 0x80
	// Bit WUP8SEC.
	PWR_SECCFGR_WUP8SEC = 0x80
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_WUP8SEC_NonSecure = 0x0
	// Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access
	PWR_SECCFGR_WUP8SEC_Secure = 0x1
	// Position of LPMSEC field.
	PWR_SECCFGR_LPMSEC_Pos = 0xc
	// Bit mask of LPMSEC field.
	PWR_SECCFGR_LPMSEC_Msk = 0x1000
	// Bit LPMSEC.
	PWR_SECCFGR_LPMSEC = 0x1000
	// PWR_CR1, PWR_CR2 and CSSF in the PWR_SR can be read and written with secure or nonsecure access
	PWR_SECCFGR_LPMSEC_NonSecure = 0x0
	// PWR_CR1, PWR_CR2, and CSSF in the PWR_SR can be read and written only with secure access
	PWR_SECCFGR_LPMSEC_Secure = 0x1
	// Position of VDMSEC field.
	PWR_SECCFGR_VDMSEC_Pos = 0xd
	// Bit mask of VDMSEC field.
	PWR_SECCFGR_VDMSEC_Msk = 0x2000
	// Bit VDMSEC.
	PWR_SECCFGR_VDMSEC = 0x2000
	// PWR_SVMCR and PWR_CR3 can be read and written with secure or nonsecure access
	PWR_SECCFGR_VDMSEC_NonSecure = 0x0
	// PWR_SVMCR and PWR_CR3 can be read and written only with secure access
	PWR_SECCFGR_VDMSEC_Secure = 0x1
	// Position of VBSEC field.
	PWR_SECCFGR_VBSEC_Pos = 0xe
	// Bit mask of VBSEC field.
	PWR_SECCFGR_VBSEC_Msk = 0x4000
	// Bit VBSEC.
	PWR_SECCFGR_VBSEC = 0x4000
	// PWR_BDCR1, PWR_BDCR2, and PWR_DBPR can be read and written with secure or nonsecure access
	PWR_SECCFGR_VBSEC_NonSecure = 0x0
	// PWR_BDCR1, PWR_BDCR2, and PWR_DBPR can be read and written only with secure access
	PWR_SECCFGR_VBSEC_Secure = 0x1
	// Position of APCSEC field.
	PWR_SECCFGR_APCSEC_Pos = 0xf
	// Bit mask of APCSEC field.
	PWR_SECCFGR_APCSEC_Msk = 0x8000
	// Bit APCSEC.
	PWR_SECCFGR_APCSEC = 0x8000
	// PWR_APCR can be read and written with secure or nonsecure access
	PWR_SECCFGR_APCSEC_NonSecure = 0x0
	// PWR_APCR can be read and written only with secure access
	PWR_SECCFGR_APCSEC_Secure = 0x1

	// PRIVCFGR: PWR privilege control register
	// Position of SPRIV field.
	PWR_PRIVCFGR_SPRIV_Pos = 0x0
	// Bit mask of SPRIV field.
	PWR_PRIVCFGR_SPRIV_Msk = 0x1
	// Bit SPRIV.
	PWR_PRIVCFGR_SPRIV = 0x1
	// Read and write to PWR secure functions can be done by privileged or unprivileged access
	PWR_PRIVCFGR_SPRIV_NonSecure = 0x0
	// Read and write to PWR secure functions can be done by privileged access only
	PWR_PRIVCFGR_SPRIV_Secure = 0x1
	// Position of NSPRIV field.
	PWR_PRIVCFGR_NSPRIV_Pos = 0x1
	// Bit mask of NSPRIV field.
	PWR_PRIVCFGR_NSPRIV_Msk = 0x2
	// Bit NSPRIV.
	PWR_PRIVCFGR_NSPRIV = 0x2
	// Read and write to PWR nonsecure functions can be done by privileged or unprivileged access
	PWR_PRIVCFGR_NSPRIV_NonSecure = 0x0
	// Read and write to PWR nonsecure functions can be done by privileged access only
	PWR_PRIVCFGR_NSPRIV_Secure = 0x1

	// SR: PWR status register
	// Position of CSSF field.
	PWR_SR_CSSF_Pos = 0x0
	// Bit mask of CSSF field.
	PWR_SR_CSSF_Msk = 0x1
	// Bit CSSF.
	PWR_SR_CSSF = 0x1
	// Clear the STOPF and SBF flags
	PWR_SR_CSSF_Clear = 0x1
	// Position of STOPF field.
	PWR_SR_STOPF_Pos = 0x1
	// Bit mask of STOPF field.
	PWR_SR_STOPF_Msk = 0x2
	// Bit STOPF.
	PWR_SR_STOPF = 0x2
	// The device did not enter any Stop mode
	PWR_SR_STOPF_NoStop = 0x0
	// The device entered a Stop mode
	PWR_SR_STOPF_Stop = 0x1
	// Position of SBF field.
	PWR_SR_SBF_Pos = 0x2
	// Bit mask of SBF field.
	PWR_SR_SBF_Msk = 0x4
	// Bit SBF.
	PWR_SR_SBF = 0x4
	// The device did not enter Standby mode
	PWR_SR_SBF_NoStandby = 0x0
	// The device entered Standby mode
	PWR_SR_SBF_Standby = 0x1

	// SVMSR: PWR supply voltage monitoring status register
	// Position of REGS field.
	PWR_SVMSR_REGS_Pos = 0x1
	// Bit mask of REGS field.
	PWR_SVMSR_REGS_Msk = 0x2
	// Bit REGS.
	PWR_SVMSR_REGS = 0x2
	// LDO selected
	PWR_SVMSR_REGS_LDO = 0x0
	// SMPS selected
	PWR_SVMSR_REGS_SMPS = 0x1
	// Position of PVDO field.
	PWR_SVMSR_PVDO_Pos = 0x4
	// Bit mask of PVDO field.
	PWR_SVMSR_PVDO_Msk = 0x10
	// Bit PVDO.
	PWR_SVMSR_PVDO = 0x10
	// VDD is equal or above the PVD threshold selected by PVDLS[2:0]
	PWR_SVMSR_PVDO_EqualOrAboveThreshold = 0x0
	// VDD is below the PVD threshold selected by PVDLS[2:0]
	PWR_SVMSR_PVDO_BelowThreshold = 0x1
	// Position of ACTVOSRDY field.
	PWR_SVMSR_ACTVOSRDY_Pos = 0xf
	// Bit mask of ACTVOSRDY field.
	PWR_SVMSR_ACTVOSRDY_Msk = 0x8000
	// Bit ACTVOSRDY.
	PWR_SVMSR_ACTVOSRDY = 0x8000
	// VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]
	PWR_SVMSR_ACTVOSRDY_NotReady = 0x0
	// VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]
	PWR_SVMSR_ACTVOSRDY_Ready = 0x1
	// Position of ACTVOS field.
	PWR_SVMSR_ACTVOS_Pos = 0x10
	// Bit mask of ACTVOS field.
	PWR_SVMSR_ACTVOS_Msk = 0x30000
	// Range 4 (lowest power)
	PWR_SVMSR_ACTVOS_Range4 = 0x0
	// Range 3
	PWR_SVMSR_ACTVOS_Range3 = 0x1
	// Range 2
	PWR_SVMSR_ACTVOS_Range2 = 0x2
	// Range 1 (highest frequency)
	PWR_SVMSR_ACTVOS_Range1 = 0x3
	// Position of VDDUSBRDY field.
	PWR_SVMSR_VDDUSBRDY_Pos = 0x18
	// Bit mask of VDDUSBRDY field.
	PWR_SVMSR_VDDUSBRDY_Msk = 0x1000000
	// Bit VDDUSBRDY.
	PWR_SVMSR_VDDUSBRDY = 0x1000000
	// VDDUSB is below the threshold of the VDDUSB voltage monitor
	PWR_SVMSR_VDDUSBRDY_BelowThreshold = 0x0
	// VDDUSB is equal or above the threshold of the VDDUSB voltage monitor
	PWR_SVMSR_VDDUSBRDY_EqualOrAboveThreshold = 0x1
	// Position of VDDIO2RDY field.
	PWR_SVMSR_VDDIO2RDY_Pos = 0x19
	// Bit mask of VDDIO2RDY field.
	PWR_SVMSR_VDDIO2RDY_Msk = 0x2000000
	// Bit VDDIO2RDY.
	PWR_SVMSR_VDDIO2RDY = 0x2000000
	// VDDIO2 is below the threshold of the VDDIO2 voltage monitor
	PWR_SVMSR_VDDIO2RDY_BelowThreshold = 0x0
	// VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor
	PWR_SVMSR_VDDIO2RDY_EqualOrAboveThreshold = 0x1
	// Position of VDDA1RDY field.
	PWR_SVMSR_VDDA1RDY_Pos = 0x1a
	// Bit mask of VDDA1RDY field.
	PWR_SVMSR_VDDA1RDY_Msk = 0x4000000
	// Bit VDDA1RDY.
	PWR_SVMSR_VDDA1RDY = 0x4000000
	// VDDA is below the threshold of the VDDA voltage monitor 1 (around 1.6 V)
	PWR_SVMSR_VDDA1RDY_BelowThreshold = 0x0
	// VDDA is equal or above the threshold of the VDDA voltage monitor 1 (around 1.6 V)
	PWR_SVMSR_VDDA1RDY_EqualOrAboveThreshold = 0x1
	// Position of VDDA2RDY field.
	PWR_SVMSR_VDDA2RDY_Pos = 0x1b
	// Bit mask of VDDA2RDY field.
	PWR_SVMSR_VDDA2RDY_Msk = 0x8000000
	// Bit VDDA2RDY.
	PWR_SVMSR_VDDA2RDY = 0x8000000
	// VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V)
	PWR_SVMSR_VDDA2RDY_BelowThreshold = 0x0
	// VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V)
	PWR_SVMSR_VDDA2RDY_AboveThreshold = 0x1

	// BDSR: PWR Backup domain status register
	// Position of VBATH field.
	PWR_BDSR_VBATH_Pos = 0x1
	// Bit mask of VBATH field.
	PWR_BDSR_VBATH_Msk = 0x2
	// Bit VBATH.
	PWR_BDSR_VBATH = 0x2
	// VBAT < high threshold
	PWR_BDSR_VBATH_BelowHigh = 0x0
	// VBAT ≥ high threshold
	PWR_BDSR_VBATH_AboveHigh = 0x1
	// Position of TEMPL field.
	PWR_BDSR_TEMPL_Pos = 0x2
	// Bit mask of TEMPL field.
	PWR_BDSR_TEMPL_Msk = 0x4
	// Bit TEMPL.
	PWR_BDSR_TEMPL = 0x4
	// Temperature > low threshold
	PWR_BDSR_TEMPL_AboveLow = 0x0
	// Temperature ≤ low threshold
	PWR_BDSR_TEMPL_BelowLow = 0x1
	// Position of TEMPH field.
	PWR_BDSR_TEMPH_Pos = 0x3
	// Bit mask of TEMPH field.
	PWR_BDSR_TEMPH_Msk = 0x8
	// Bit TEMPH.
	PWR_BDSR_TEMPH = 0x8
	// Temperature < high threshold
	PWR_BDSR_TEMPH_BelowHigh = 0x0
	// Temperature ≥ high threshold
	PWR_BDSR_TEMPH_AboveHigh = 0x1

	// WUSR: PWR wakeup status register
	// Position of WUF1 field.
	PWR_WUSR_WUF1_Pos = 0x0
	// Bit mask of WUF1 field.
	PWR_WUSR_WUF1_Msk = 0x1
	// Bit WUF1.
	PWR_WUSR_WUF1 = 0x1
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF1_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF1_Wakeup = 0x1
	// Position of WUF2 field.
	PWR_WUSR_WUF2_Pos = 0x1
	// Bit mask of WUF2 field.
	PWR_WUSR_WUF2_Msk = 0x2
	// Bit WUF2.
	PWR_WUSR_WUF2 = 0x2
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF2_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF2_Wakeup = 0x1
	// Position of WUF3 field.
	PWR_WUSR_WUF3_Pos = 0x2
	// Bit mask of WUF3 field.
	PWR_WUSR_WUF3_Msk = 0x4
	// Bit WUF3.
	PWR_WUSR_WUF3 = 0x4
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF3_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF3_Wakeup = 0x1
	// Position of WUF4 field.
	PWR_WUSR_WUF4_Pos = 0x3
	// Bit mask of WUF4 field.
	PWR_WUSR_WUF4_Msk = 0x8
	// Bit WUF4.
	PWR_WUSR_WUF4 = 0x8
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF4_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF4_Wakeup = 0x1
	// Position of WUF5 field.
	PWR_WUSR_WUF5_Pos = 0x4
	// Bit mask of WUF5 field.
	PWR_WUSR_WUF5_Msk = 0x10
	// Bit WUF5.
	PWR_WUSR_WUF5 = 0x10
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF5_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF5_Wakeup = 0x1
	// Position of WUF6 field.
	PWR_WUSR_WUF6_Pos = 0x5
	// Bit mask of WUF6 field.
	PWR_WUSR_WUF6_Msk = 0x20
	// Bit WUF6.
	PWR_WUSR_WUF6 = 0x20
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF6_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF6_Wakeup = 0x1
	// Position of WUF7 field.
	PWR_WUSR_WUF7_Pos = 0x6
	// Bit mask of WUF7 field.
	PWR_WUSR_WUF7_Msk = 0x40
	// Bit WUF7.
	PWR_WUSR_WUF7 = 0x40
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF7_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF7_Wakeup = 0x1
	// Position of WUF8 field.
	PWR_WUSR_WUF8_Pos = 0x7
	// Bit mask of WUF8 field.
	PWR_WUSR_WUF8_Msk = 0x80
	// Bit WUF8.
	PWR_WUSR_WUF8 = 0x80
	// No wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF8_NoWakeup = 0x0
	// A wakeup event occurred on WKUPx pin
	PWR_WUSR_WUF8_Wakeup = 0x1

	// WUSCR: PWR wakeup status clear register
	// Position of CWUF1 field.
	PWR_WUSCR_CWUF1_Pos = 0x0
	// Bit mask of CWUF1 field.
	PWR_WUSCR_CWUF1_Msk = 0x1
	// Bit CWUF1.
	PWR_WUSCR_CWUF1 = 0x1
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF1_Clear = 0x1
	// Position of CWUF2 field.
	PWR_WUSCR_CWUF2_Pos = 0x1
	// Bit mask of CWUF2 field.
	PWR_WUSCR_CWUF2_Msk = 0x2
	// Bit CWUF2.
	PWR_WUSCR_CWUF2 = 0x2
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF2_Clear = 0x1
	// Position of CWUF3 field.
	PWR_WUSCR_CWUF3_Pos = 0x2
	// Bit mask of CWUF3 field.
	PWR_WUSCR_CWUF3_Msk = 0x4
	// Bit CWUF3.
	PWR_WUSCR_CWUF3 = 0x4
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF3_Clear = 0x1
	// Position of CWUF4 field.
	PWR_WUSCR_CWUF4_Pos = 0x3
	// Bit mask of CWUF4 field.
	PWR_WUSCR_CWUF4_Msk = 0x8
	// Bit CWUF4.
	PWR_WUSCR_CWUF4 = 0x8
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF4_Clear = 0x1
	// Position of CWUF5 field.
	PWR_WUSCR_CWUF5_Pos = 0x4
	// Bit mask of CWUF5 field.
	PWR_WUSCR_CWUF5_Msk = 0x10
	// Bit CWUF5.
	PWR_WUSCR_CWUF5 = 0x10
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF5_Clear = 0x1
	// Position of CWUF6 field.
	PWR_WUSCR_CWUF6_Pos = 0x5
	// Bit mask of CWUF6 field.
	PWR_WUSCR_CWUF6_Msk = 0x20
	// Bit CWUF6.
	PWR_WUSCR_CWUF6 = 0x20
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF6_Clear = 0x1
	// Position of CWUF7 field.
	PWR_WUSCR_CWUF7_Pos = 0x6
	// Bit mask of CWUF7 field.
	PWR_WUSCR_CWUF7_Msk = 0x40
	// Bit CWUF7.
	PWR_WUSCR_CWUF7 = 0x40
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF7_Clear = 0x1
	// Position of CWUF8 field.
	PWR_WUSCR_CWUF8_Pos = 0x7
	// Bit mask of CWUF8 field.
	PWR_WUSCR_CWUF8_Msk = 0x80
	// Bit CWUF8.
	PWR_WUSCR_CWUF8 = 0x80
	// Clear the WUFx flag in PWR_WUSR
	PWR_WUSCR_CWUF8_Clear = 0x1

	// APCR: PWR apply pull configuration register
	// Position of APC field.
	PWR_APCR_APC_Pos = 0x0
	// Bit mask of APC field.
	PWR_APCR_APC_Msk = 0x1
	// Bit APC.
	PWR_APCR_APC = 0x1
	// PWR_PUCRx and PWR_PDCRx are not applied to the I/Os
	PWR_APCR_APC_Disabled = 0x0
	// I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied
	PWR_APCR_APC_Enabled = 0x1

	// PUCRA: PWR port A pull-up control register
	// Position of PU0 field.
	PWR_PUCRA_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRA_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRA_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRA_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRA_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRA_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRA_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRA_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRA_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRA_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRA_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRA_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRA_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRA_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRA_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRA_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRA_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRA_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRA_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRA_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRA_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRA_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRA_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRA_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRA_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRA_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRA_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRA_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRA_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRA_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRA_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRA_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRA_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRA_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRA_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRA_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRA_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRA_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRA_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRA_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRA_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRA_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRA_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRA_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRA_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRA_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRA_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRA_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRA_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRA_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRA_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRA_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRA_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRA_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRA_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRA_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU13_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRA_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRA_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRA_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRA_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRA_PU15_Enabled = 0x1

	// PDCRA: PWR port A pull-down control register
	// Position of PD0 field.
	PWR_PDCRA_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRA_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRA_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRA_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRA_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRA_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRA_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRA_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRA_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRA_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRA_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRA_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRA_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRA_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRA_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRA_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRA_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRA_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRA_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRA_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRA_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRA_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRA_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRA_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRA_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRA_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRA_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRA_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRA_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRA_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRA_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRA_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRA_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRA_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRA_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRA_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRA_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRA_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRA_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRA_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRA_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRA_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRA_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRA_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRA_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRA_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRA_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRA_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRA_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRA_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRA_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRA_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD12_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRA_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRA_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRA_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRA_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRA_PD14_Enabled = 0x1

	// PUCRB: PWR port B pull-up control register
	// Position of PU0 field.
	PWR_PUCRB_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRB_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRB_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRB_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRB_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRB_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRB_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRB_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRB_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRB_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRB_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRB_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRB_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRB_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRB_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRB_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRB_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRB_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRB_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRB_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRB_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRB_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRB_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRB_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRB_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRB_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRB_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRB_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRB_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRB_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRB_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRB_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRB_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRB_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRB_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRB_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRB_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRB_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRB_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRB_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRB_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRB_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRB_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRB_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRB_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRB_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRB_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRB_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRB_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRB_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRB_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRB_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRB_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRB_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRB_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRB_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRB_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRB_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRB_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRB_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRB_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRB_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRB_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRB_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRB_PU15_Enabled = 0x1

	// PDCRB: PWR port B pull-down control register
	// Position of PD0 field.
	PWR_PDCRB_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRB_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRB_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRB_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRB_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRB_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRB_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRB_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRB_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRB_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRB_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRB_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRB_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRB_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRB_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRB_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD3_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRB_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRB_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRB_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRB_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRB_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRB_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRB_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRB_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRB_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRB_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRB_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRB_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRB_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRB_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRB_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRB_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRB_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRB_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRB_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRB_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRB_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRB_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRB_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRB_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRB_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRB_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRB_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRB_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRB_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRB_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRB_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRB_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRB_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRB_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRB_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRB_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRB_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRB_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRB_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRB_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRB_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRB_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRB_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRB_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRB_PD15_Enabled = 0x1

	// PUCRC: Power port C pull up control register
	// Position of PU0 field.
	PWR_PUCRC_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRC_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRC_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRC_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRC_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRC_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRC_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRC_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRC_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRC_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRC_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRC_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRC_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRC_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRC_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRC_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRC_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRC_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRC_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRC_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRC_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRC_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRC_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRC_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRC_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRC_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRC_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRC_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRC_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRC_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRC_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRC_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRC_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRC_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRC_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRC_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRC_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRC_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRC_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRC_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRC_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRC_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRC_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRC_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRC_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRC_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRC_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRC_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRC_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRC_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRC_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRC_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRC_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRC_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRC_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRC_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRC_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRC_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRC_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRC_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRC_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRC_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRC_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRC_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRC_PU15_Enabled = 0x1

	// PDCRC: PWR port C pull-down control register
	// Position of PD0 field.
	PWR_PDCRC_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRC_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRC_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRC_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRC_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRC_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRC_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRC_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRC_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRC_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRC_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRC_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRC_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRC_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRC_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRC_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRC_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRC_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRC_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRC_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRC_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRC_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRC_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRC_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRC_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRC_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRC_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRC_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRC_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRC_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRC_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRC_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRC_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRC_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRC_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRC_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRC_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRC_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRC_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRC_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRC_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRC_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRC_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRC_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRC_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRC_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRC_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRC_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRC_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRC_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRC_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRC_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRC_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRC_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRC_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRC_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRC_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRC_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRC_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRC_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRC_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRC_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRC_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRC_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRC_PD15_Enabled = 0x1

	// PUCRD: PWR port D pull-up control register
	// Position of PU0 field.
	PWR_PUCRD_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRD_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRD_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRD_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRD_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRD_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRD_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRD_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRD_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRD_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRD_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRD_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRD_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRD_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRD_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRD_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRD_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRD_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRD_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRD_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRD_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRD_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRD_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRD_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRD_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRD_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRD_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRD_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRD_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRD_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRD_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRD_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRD_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRD_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRD_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRD_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRD_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRD_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRD_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRD_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRD_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRD_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRD_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRD_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRD_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRD_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRD_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRD_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRD_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRD_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRD_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRD_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRD_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRD_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRD_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRD_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRD_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRD_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRD_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRD_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRD_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRD_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRD_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRD_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRD_PU15_Enabled = 0x1

	// PDCRD: PWR port D pull-down control register
	// Position of PD0 field.
	PWR_PDCRD_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRD_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRD_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRD_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRD_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRD_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRD_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRD_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRD_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRD_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRD_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRD_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRD_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRD_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRD_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRD_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRD_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRD_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRD_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRD_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRD_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRD_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRD_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRD_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRD_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRD_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRD_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRD_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRD_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRD_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRD_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRD_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRD_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRD_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRD_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRD_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRD_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRD_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRD_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRD_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRD_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRD_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRD_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRD_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRD_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRD_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRD_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRD_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRD_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRD_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRD_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRD_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRD_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRD_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRD_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRD_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRD_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRD_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRD_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRD_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRD_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRD_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRD_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRD_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRD_PD15_Enabled = 0x1

	// PUCRE: PWR port E pull-up control register
	// Position of PU0 field.
	PWR_PUCRE_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRE_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRE_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRE_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRE_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRE_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRE_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRE_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRE_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRE_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRE_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRE_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRE_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRE_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRE_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRE_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRE_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRE_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRE_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRE_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRE_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRE_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRE_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRE_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRE_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRE_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRE_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRE_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRE_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRE_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRE_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRE_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRE_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRE_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRE_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRE_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRE_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRE_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRE_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRE_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRE_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRE_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRE_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRE_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRE_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRE_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRE_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRE_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRE_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRE_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRE_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRE_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRE_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRE_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRE_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRE_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRE_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRE_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRE_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRE_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRE_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRE_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRE_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRE_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRE_PU15_Enabled = 0x1

	// PDCRE: PWR port E pull-down control register
	// Position of PD0 field.
	PWR_PDCRE_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRE_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRE_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRE_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRE_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRE_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRE_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRE_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRE_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRE_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRE_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRE_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRE_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRE_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRE_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRE_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRE_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRE_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRE_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRE_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRE_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRE_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRE_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRE_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRE_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRE_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRE_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRE_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRE_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRE_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRE_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRE_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRE_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRE_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRE_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRE_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRE_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRE_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRE_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRE_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRE_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRE_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRE_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRE_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRE_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRE_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRE_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRE_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRE_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRE_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRE_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRE_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRE_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRE_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRE_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRE_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRE_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRE_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRE_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRE_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRE_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRE_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRE_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRE_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRE_PD15_Enabled = 0x1

	// PUCRF: PWR port F pull-up control register
	// Position of PU0 field.
	PWR_PUCRF_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRF_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRF_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRF_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRF_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRF_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRF_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRF_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRF_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRF_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRF_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRF_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRF_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRF_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRF_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRF_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRF_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRF_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRF_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRF_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRF_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRF_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRF_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRF_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRF_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRF_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRF_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRF_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRF_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRF_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRF_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRF_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRF_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRF_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRF_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRF_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRF_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRF_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRF_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRF_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRF_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRF_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRF_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRF_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRF_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRF_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRF_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRF_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRF_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRF_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRF_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRF_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRF_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRF_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRF_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRF_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRF_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRF_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRF_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRF_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRF_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRF_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRF_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRF_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRF_PU15_Enabled = 0x1

	// PDCRF: PWR port F pull-down control register
	// Position of PD0 field.
	PWR_PDCRF_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRF_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRF_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRF_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRF_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRF_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRF_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRF_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRF_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRF_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRF_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRF_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRF_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRF_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRF_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRF_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRF_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRF_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRF_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRF_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRF_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRF_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRF_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRF_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRF_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRF_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRF_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRF_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRF_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRF_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRF_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRF_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRF_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRF_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRF_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRF_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRF_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRF_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRF_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRF_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRF_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRF_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRF_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRF_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRF_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRF_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRF_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRF_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRF_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRF_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRF_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRF_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRF_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRF_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRF_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRF_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRF_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRF_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRF_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRF_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRF_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRF_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRF_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRF_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRF_PD15_Enabled = 0x1

	// PUCRG: PWR port G pull-up control register
	// Position of PU0 field.
	PWR_PUCRG_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRG_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRG_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRG_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRG_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRG_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRG_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRG_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRG_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRG_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRG_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRG_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRG_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRG_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRG_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRG_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRG_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRG_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRG_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRG_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRG_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRG_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRG_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRG_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRG_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRG_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRG_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRG_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRG_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRG_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRG_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRG_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRG_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRG_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRG_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRG_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRG_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRG_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRG_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRG_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRG_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRG_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRG_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRG_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRG_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRG_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRG_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRG_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRG_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRG_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRG_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRG_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRG_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRG_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRG_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRG_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRG_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRG_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRG_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRG_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRG_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRG_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRG_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRG_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRG_PU15_Enabled = 0x1

	// PDCRG: PWR port G pull-down control register
	// Position of PD0 field.
	PWR_PDCRG_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRG_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRG_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRG_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRG_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRG_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRG_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRG_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRG_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRG_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRG_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRG_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRG_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRG_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRG_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRG_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRG_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRG_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRG_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRG_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRG_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRG_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRG_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRG_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRG_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRG_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRG_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRG_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRG_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRG_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRG_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRG_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRG_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRG_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRG_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRG_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRG_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRG_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRG_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRG_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRG_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRG_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRG_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRG_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRG_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRG_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRG_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRG_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRG_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRG_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRG_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRG_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRG_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRG_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRG_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRG_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRG_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRG_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRG_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRG_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRG_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRG_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRG_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRG_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRG_PD15_Enabled = 0x1

	// PUCRH: PWR port H pull-up control register
	// Position of PU0 field.
	PWR_PUCRH_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRH_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRH_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRH_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRH_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRH_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRH_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRH_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRH_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRH_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRH_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRH_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRH_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRH_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRH_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRH_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRH_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRH_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRH_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRH_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRH_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRH_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRH_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRH_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRH_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRH_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRH_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRH_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRH_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRH_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRH_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRH_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRH_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRH_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRH_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRH_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRH_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRH_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRH_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRH_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRH_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRH_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRH_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRH_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRH_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRH_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRH_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRH_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRH_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRH_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRH_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRH_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRH_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRH_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRH_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRH_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRH_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRH_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRH_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRH_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRH_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRH_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRH_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRH_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRH_PU15_Enabled = 0x1

	// PDCRH: PWR port H pull-down control register
	// Position of PD0 field.
	PWR_PDCRH_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRH_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRH_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRH_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRH_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRH_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRH_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRH_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRH_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRH_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRH_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRH_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRH_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRH_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRH_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRH_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRH_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRH_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRH_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRH_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRH_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRH_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRH_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRH_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRH_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRH_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRH_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRH_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRH_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRH_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRH_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRH_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRH_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRH_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRH_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRH_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRH_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRH_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRH_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRH_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRH_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRH_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRH_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRH_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRH_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRH_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRH_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRH_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRH_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRH_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRH_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRH_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRH_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRH_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRH_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRH_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRH_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRH_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRH_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRH_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRH_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRH_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRH_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRH_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRH_PD15_Enabled = 0x1

	// PUCRI: PWR port I pull-up control register
	// Position of PU0 field.
	PWR_PUCRI_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRI_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRI_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRI_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRI_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRI_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRI_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRI_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRI_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRI_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRI_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRI_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRI_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRI_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRI_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRI_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRI_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRI_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRI_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRI_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRI_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRI_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRI_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRI_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRI_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRI_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRI_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRI_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRI_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRI_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRI_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRI_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRI_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRI_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRI_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRI_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRI_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRI_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRI_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRI_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRI_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRI_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRI_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRI_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRI_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRI_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRI_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRI_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU11_Enabled = 0x1
	// Position of PU12 field.
	PWR_PUCRI_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRI_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRI_PU12 = 0x1000
	// Pull-up disabled
	PWR_PUCRI_PU12_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU12_Enabled = 0x1
	// Position of PU13 field.
	PWR_PUCRI_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRI_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRI_PU13 = 0x2000
	// Pull-up disabled
	PWR_PUCRI_PU13_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU13_Enabled = 0x1
	// Position of PU14 field.
	PWR_PUCRI_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRI_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRI_PU14 = 0x4000
	// Pull-up disabled
	PWR_PUCRI_PU14_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU14_Enabled = 0x1
	// Position of PU15 field.
	PWR_PUCRI_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRI_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRI_PU15 = 0x8000
	// Pull-up disabled
	PWR_PUCRI_PU15_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRI_PU15_Enabled = 0x1

	// PDCRI: PWR port I pull-down control register
	// Position of PD0 field.
	PWR_PDCRI_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRI_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRI_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRI_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRI_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRI_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRI_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRI_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRI_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRI_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRI_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRI_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRI_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRI_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRI_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRI_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRI_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRI_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRI_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRI_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRI_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRI_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRI_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRI_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRI_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRI_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRI_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRI_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRI_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRI_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRI_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRI_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRI_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRI_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRI_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRI_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRI_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRI_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRI_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRI_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRI_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRI_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRI_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRI_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRI_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRI_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRI_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRI_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD11_Enabled = 0x1
	// Position of PD12 field.
	PWR_PDCRI_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRI_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRI_PD12 = 0x1000
	// Pull-down disabled
	PWR_PDCRI_PD12_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD12_Enabled = 0x1
	// Position of PD13 field.
	PWR_PDCRI_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRI_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRI_PD13 = 0x2000
	// Pull-down disabled
	PWR_PDCRI_PD13_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD13_Enabled = 0x1
	// Position of PD14 field.
	PWR_PDCRI_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRI_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRI_PD14 = 0x4000
	// Pull-down disabled
	PWR_PDCRI_PD14_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD14_Enabled = 0x1
	// Position of PD15 field.
	PWR_PDCRI_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRI_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRI_PD15 = 0x8000
	// Pull-down disabled
	PWR_PDCRI_PD15_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRI_PD15_Enabled = 0x1

	// PUCRJ: PWR port J pull-up control register
	// Position of PU0 field.
	PWR_PUCRJ_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRJ_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRJ_PU0 = 0x1
	// Pull-up disabled
	PWR_PUCRJ_PU0_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU0_Enabled = 0x1
	// Position of PU1 field.
	PWR_PUCRJ_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRJ_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRJ_PU1 = 0x2
	// Pull-up disabled
	PWR_PUCRJ_PU1_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU1_Enabled = 0x1
	// Position of PU2 field.
	PWR_PUCRJ_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRJ_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRJ_PU2 = 0x4
	// Pull-up disabled
	PWR_PUCRJ_PU2_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU2_Enabled = 0x1
	// Position of PU3 field.
	PWR_PUCRJ_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRJ_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRJ_PU3 = 0x8
	// Pull-up disabled
	PWR_PUCRJ_PU3_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU3_Enabled = 0x1
	// Position of PU4 field.
	PWR_PUCRJ_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRJ_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRJ_PU4 = 0x10
	// Pull-up disabled
	PWR_PUCRJ_PU4_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU4_Enabled = 0x1
	// Position of PU5 field.
	PWR_PUCRJ_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRJ_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRJ_PU5 = 0x20
	// Pull-up disabled
	PWR_PUCRJ_PU5_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU5_Enabled = 0x1
	// Position of PU6 field.
	PWR_PUCRJ_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRJ_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRJ_PU6 = 0x40
	// Pull-up disabled
	PWR_PUCRJ_PU6_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU6_Enabled = 0x1
	// Position of PU7 field.
	PWR_PUCRJ_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRJ_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRJ_PU7 = 0x80
	// Pull-up disabled
	PWR_PUCRJ_PU7_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU7_Enabled = 0x1
	// Position of PU8 field.
	PWR_PUCRJ_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRJ_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRJ_PU8 = 0x100
	// Pull-up disabled
	PWR_PUCRJ_PU8_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU8_Enabled = 0x1
	// Position of PU9 field.
	PWR_PUCRJ_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRJ_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRJ_PU9 = 0x200
	// Pull-up disabled
	PWR_PUCRJ_PU9_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU9_Enabled = 0x1
	// Position of PU10 field.
	PWR_PUCRJ_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRJ_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRJ_PU10 = 0x400
	// Pull-up disabled
	PWR_PUCRJ_PU10_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU10_Enabled = 0x1
	// Position of PU11 field.
	PWR_PUCRJ_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRJ_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRJ_PU11 = 0x800
	// Pull-up disabled
	PWR_PUCRJ_PU11_Disabled = 0x0
	// Pull-up enabled
	PWR_PUCRJ_PU11_Enabled = 0x1

	// PDCRJ: PWR port J pull-down control register
	// Position of PD0 field.
	PWR_PDCRJ_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRJ_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRJ_PD0 = 0x1
	// Pull-down disabled
	PWR_PDCRJ_PD0_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD0_Enabled = 0x1
	// Position of PD1 field.
	PWR_PDCRJ_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRJ_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRJ_PD1 = 0x2
	// Pull-down disabled
	PWR_PDCRJ_PD1_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD1_Enabled = 0x1
	// Position of PD2 field.
	PWR_PDCRJ_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRJ_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRJ_PD2 = 0x4
	// Pull-down disabled
	PWR_PDCRJ_PD2_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD2_Enabled = 0x1
	// Position of PD3 field.
	PWR_PDCRJ_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRJ_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRJ_PD3 = 0x8
	// Pull-down disabled
	PWR_PDCRJ_PD3_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD3_Enabled = 0x1
	// Position of PD4 field.
	PWR_PDCRJ_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRJ_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRJ_PD4 = 0x10
	// Pull-down disabled
	PWR_PDCRJ_PD4_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD4_Enabled = 0x1
	// Position of PD5 field.
	PWR_PDCRJ_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRJ_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRJ_PD5 = 0x20
	// Pull-down disabled
	PWR_PDCRJ_PD5_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD5_Enabled = 0x1
	// Position of PD6 field.
	PWR_PDCRJ_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRJ_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRJ_PD6 = 0x40
	// Pull-down disabled
	PWR_PDCRJ_PD6_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD6_Enabled = 0x1
	// Position of PD7 field.
	PWR_PDCRJ_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRJ_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRJ_PD7 = 0x80
	// Pull-down disabled
	PWR_PDCRJ_PD7_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD7_Enabled = 0x1
	// Position of PD8 field.
	PWR_PDCRJ_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRJ_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRJ_PD8 = 0x100
	// Pull-down disabled
	PWR_PDCRJ_PD8_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD8_Enabled = 0x1
	// Position of PD9 field.
	PWR_PDCRJ_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRJ_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRJ_PD9 = 0x200
	// Pull-down disabled
	PWR_PDCRJ_PD9_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD9_Enabled = 0x1
	// Position of PD10 field.
	PWR_PDCRJ_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRJ_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRJ_PD10 = 0x400
	// Pull-down disabled
	PWR_PDCRJ_PD10_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD10_Enabled = 0x1
	// Position of PD11 field.
	PWR_PDCRJ_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRJ_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRJ_PD11 = 0x800
	// Pull-down disabled
	PWR_PDCRJ_PD11_Disabled = 0x0
	// Pull-down enabled
	PWR_PDCRJ_PD11_Enabled = 0x1

	// CR4: PWR control register 4
	// Position of SRAM1PDS4 field.
	PWR_CR4_SRAM1PDS4_Pos = 0x0
	// Bit mask of SRAM1PDS4 field.
	PWR_CR4_SRAM1PDS4_Msk = 0x1
	// Bit SRAM1PDS4.
	PWR_CR4_SRAM1PDS4 = 0x1
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS4_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS4_Enabled = 0x1
	// Position of SRAM1PDS5 field.
	PWR_CR4_SRAM1PDS5_Pos = 0x1
	// Bit mask of SRAM1PDS5 field.
	PWR_CR4_SRAM1PDS5_Msk = 0x2
	// Bit SRAM1PDS5.
	PWR_CR4_SRAM1PDS5 = 0x2
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS5_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS5_Enabled = 0x1
	// Position of SRAM1PDS6 field.
	PWR_CR4_SRAM1PDS6_Pos = 0x2
	// Bit mask of SRAM1PDS6 field.
	PWR_CR4_SRAM1PDS6_Msk = 0x4
	// Bit SRAM1PDS6.
	PWR_CR4_SRAM1PDS6 = 0x4
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS6_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS6_Enabled = 0x1
	// Position of SRAM1PDS7 field.
	PWR_CR4_SRAM1PDS7_Pos = 0x3
	// Bit mask of SRAM1PDS7 field.
	PWR_CR4_SRAM1PDS7_Msk = 0x8
	// Bit SRAM1PDS7.
	PWR_CR4_SRAM1PDS7 = 0x8
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS7_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS7_Enabled = 0x1
	// Position of SRAM1PDS8 field.
	PWR_CR4_SRAM1PDS8_Pos = 0x4
	// Bit mask of SRAM1PDS8 field.
	PWR_CR4_SRAM1PDS8_Msk = 0x10
	// Bit SRAM1PDS8.
	PWR_CR4_SRAM1PDS8 = 0x10
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS8_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS8_Enabled = 0x1
	// Position of SRAM1PDS9 field.
	PWR_CR4_SRAM1PDS9_Pos = 0x5
	// Bit mask of SRAM1PDS9 field.
	PWR_CR4_SRAM1PDS9_Msk = 0x20
	// Bit SRAM1PDS9.
	PWR_CR4_SRAM1PDS9 = 0x20
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS9_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS9_Enabled = 0x1
	// Position of SRAM1PDS10 field.
	PWR_CR4_SRAM1PDS10_Pos = 0x6
	// Bit mask of SRAM1PDS10 field.
	PWR_CR4_SRAM1PDS10_Msk = 0x40
	// Bit SRAM1PDS10.
	PWR_CR4_SRAM1PDS10 = 0x40
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS10_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS10_Enabled = 0x1
	// Position of SRAM1PDS11 field.
	PWR_CR4_SRAM1PDS11_Pos = 0x7
	// Bit mask of SRAM1PDS11 field.
	PWR_CR4_SRAM1PDS11_Msk = 0x80
	// Bit SRAM1PDS11.
	PWR_CR4_SRAM1PDS11 = 0x80
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS11_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS11_Enabled = 0x1
	// Position of SRAM1PDS12 field.
	PWR_CR4_SRAM1PDS12_Pos = 0x8
	// Bit mask of SRAM1PDS12 field.
	PWR_CR4_SRAM1PDS12_Msk = 0x100
	// Bit SRAM1PDS12.
	PWR_CR4_SRAM1PDS12 = 0x100
	// SRAM1 page x content retained in Stop modes
	PWR_CR4_SRAM1PDS12_Disabled = 0x0
	// SRAM1 page x content lost in Stop modes
	PWR_CR4_SRAM1PDS12_Enabled = 0x1
	// Position of SRAM3PDS9 field.
	PWR_CR4_SRAM3PDS9_Pos = 0xa
	// Bit mask of SRAM3PDS9 field.
	PWR_CR4_SRAM3PDS9_Msk = 0x400
	// Bit SRAM3PDS9.
	PWR_CR4_SRAM3PDS9 = 0x400
	// SRAM3 page x content retained in Stop modes
	PWR_CR4_SRAM3PDS9_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR4_SRAM3PDS9_Enabled = 0x1
	// Position of SRAM3PDS10 field.
	PWR_CR4_SRAM3PDS10_Pos = 0xb
	// Bit mask of SRAM3PDS10 field.
	PWR_CR4_SRAM3PDS10_Msk = 0x800
	// Bit SRAM3PDS10.
	PWR_CR4_SRAM3PDS10 = 0x800
	// SRAM3 page x content retained in Stop modes
	PWR_CR4_SRAM3PDS10_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR4_SRAM3PDS10_Enabled = 0x1
	// Position of SRAM3PDS11 field.
	PWR_CR4_SRAM3PDS11_Pos = 0xc
	// Bit mask of SRAM3PDS11 field.
	PWR_CR4_SRAM3PDS11_Msk = 0x1000
	// Bit SRAM3PDS11.
	PWR_CR4_SRAM3PDS11 = 0x1000
	// SRAM3 page x content retained in Stop modes
	PWR_CR4_SRAM3PDS11_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR4_SRAM3PDS11_Enabled = 0x1
	// Position of SRAM3PDS12 field.
	PWR_CR4_SRAM3PDS12_Pos = 0xd
	// Bit mask of SRAM3PDS12 field.
	PWR_CR4_SRAM3PDS12_Msk = 0x2000
	// Bit SRAM3PDS12.
	PWR_CR4_SRAM3PDS12 = 0x2000
	// SRAM3 page x content retained in Stop modes
	PWR_CR4_SRAM3PDS12_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR4_SRAM3PDS12_Enabled = 0x1
	// Position of SRAM3PDS13 field.
	PWR_CR4_SRAM3PDS13_Pos = 0xe
	// Bit mask of SRAM3PDS13 field.
	PWR_CR4_SRAM3PDS13_Msk = 0x4000
	// Bit SRAM3PDS13.
	PWR_CR4_SRAM3PDS13 = 0x4000
	// SRAM3 page x content retained in Stop modes
	PWR_CR4_SRAM3PDS13_Disabled = 0x0
	// SRAM3 page x content lost in Stop modes
	PWR_CR4_SRAM3PDS13_Enabled = 0x1
	// Position of SRAM5PDS1 field.
	PWR_CR4_SRAM5PDS1_Pos = 0x10
	// Bit mask of SRAM5PDS1 field.
	PWR_CR4_SRAM5PDS1_Msk = 0x10000
	// Bit SRAM5PDS1.
	PWR_CR4_SRAM5PDS1 = 0x10000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS1_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS1_Enabled = 0x1
	// Position of SRAM5PDS2 field.
	PWR_CR4_SRAM5PDS2_Pos = 0x11
	// Bit mask of SRAM5PDS2 field.
	PWR_CR4_SRAM5PDS2_Msk = 0x20000
	// Bit SRAM5PDS2.
	PWR_CR4_SRAM5PDS2 = 0x20000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS2_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS2_Enabled = 0x1
	// Position of SRAM5PDS3 field.
	PWR_CR4_SRAM5PDS3_Pos = 0x12
	// Bit mask of SRAM5PDS3 field.
	PWR_CR4_SRAM5PDS3_Msk = 0x40000
	// Bit SRAM5PDS3.
	PWR_CR4_SRAM5PDS3 = 0x40000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS3_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS3_Enabled = 0x1
	// Position of SRAM5PDS4 field.
	PWR_CR4_SRAM5PDS4_Pos = 0x13
	// Bit mask of SRAM5PDS4 field.
	PWR_CR4_SRAM5PDS4_Msk = 0x80000
	// Bit SRAM5PDS4.
	PWR_CR4_SRAM5PDS4 = 0x80000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS4_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS4_Enabled = 0x1
	// Position of SRAM5PDS5 field.
	PWR_CR4_SRAM5PDS5_Pos = 0x14
	// Bit mask of SRAM5PDS5 field.
	PWR_CR4_SRAM5PDS5_Msk = 0x100000
	// Bit SRAM5PDS5.
	PWR_CR4_SRAM5PDS5 = 0x100000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS5_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS5_Enabled = 0x1
	// Position of SRAM5PDS6 field.
	PWR_CR4_SRAM5PDS6_Pos = 0x15
	// Bit mask of SRAM5PDS6 field.
	PWR_CR4_SRAM5PDS6_Msk = 0x200000
	// Bit SRAM5PDS6.
	PWR_CR4_SRAM5PDS6 = 0x200000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS6_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS6_Enabled = 0x1
	// Position of SRAM5PDS7 field.
	PWR_CR4_SRAM5PDS7_Pos = 0x16
	// Bit mask of SRAM5PDS7 field.
	PWR_CR4_SRAM5PDS7_Msk = 0x400000
	// Bit SRAM5PDS7.
	PWR_CR4_SRAM5PDS7 = 0x400000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS7_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS7_Enabled = 0x1
	// Position of SRAM5PDS8 field.
	PWR_CR4_SRAM5PDS8_Pos = 0x17
	// Bit mask of SRAM5PDS8 field.
	PWR_CR4_SRAM5PDS8_Msk = 0x800000
	// Bit SRAM5PDS8.
	PWR_CR4_SRAM5PDS8 = 0x800000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS8_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS8_Enabled = 0x1
	// Position of SRAM5PDS9 field.
	PWR_CR4_SRAM5PDS9_Pos = 0x18
	// Bit mask of SRAM5PDS9 field.
	PWR_CR4_SRAM5PDS9_Msk = 0x1000000
	// Bit SRAM5PDS9.
	PWR_CR4_SRAM5PDS9 = 0x1000000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS9_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS9_Enabled = 0x1
	// Position of SRAM5PDS10 field.
	PWR_CR4_SRAM5PDS10_Pos = 0x19
	// Bit mask of SRAM5PDS10 field.
	PWR_CR4_SRAM5PDS10_Msk = 0x2000000
	// Bit SRAM5PDS10.
	PWR_CR4_SRAM5PDS10 = 0x2000000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS10_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS10_Enabled = 0x1
	// Position of SRAM5PDS11 field.
	PWR_CR4_SRAM5PDS11_Pos = 0x1a
	// Bit mask of SRAM5PDS11 field.
	PWR_CR4_SRAM5PDS11_Msk = 0x4000000
	// Bit SRAM5PDS11.
	PWR_CR4_SRAM5PDS11 = 0x4000000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS11_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS11_Enabled = 0x1
	// Position of SRAM5PDS12 field.
	PWR_CR4_SRAM5PDS12_Pos = 0x1b
	// Bit mask of SRAM5PDS12 field.
	PWR_CR4_SRAM5PDS12_Msk = 0x8000000
	// Bit SRAM5PDS12.
	PWR_CR4_SRAM5PDS12 = 0x8000000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS12_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS12_Enabled = 0x1
	// Position of SRAM5PDS13 field.
	PWR_CR4_SRAM5PDS13_Pos = 0x1c
	// Bit mask of SRAM5PDS13 field.
	PWR_CR4_SRAM5PDS13_Msk = 0x10000000
	// Bit SRAM5PDS13.
	PWR_CR4_SRAM5PDS13 = 0x10000000
	// SRAM5 page x content retained in Stop modes
	PWR_CR4_SRAM5PDS13_Disabled = 0x0
	// SRAM5 page x content lost in Stop modes
	PWR_CR4_SRAM5PDS13_Enabled = 0x1
)

// Constants for RAMCFG: RAMCFG
const (
	// M1CR: RAMCFG SRAM x control register
	// Position of ECCE field.
	RAMCFG_M1CR_ECCE_Pos = 0x0
	// Bit mask of ECCE field.
	RAMCFG_M1CR_ECCE_Msk = 0x1
	// Bit ECCE.
	RAMCFG_M1CR_ECCE = 0x1
	// Position of ALE field.
	RAMCFG_M1CR_ALE_Pos = 0x4
	// Bit mask of ALE field.
	RAMCFG_M1CR_ALE_Msk = 0x10
	// Bit ALE.
	RAMCFG_M1CR_ALE = 0x10
	// Position of SRAMER field.
	RAMCFG_M1CR_SRAMER_Pos = 0x8
	// Bit mask of SRAMER field.
	RAMCFG_M1CR_SRAMER_Msk = 0x100
	// Bit SRAMER.
	RAMCFG_M1CR_SRAMER = 0x100
	// Position of WSC field.
	RAMCFG_M1CR_WSC_Pos = 0x10
	// Bit mask of WSC field.
	RAMCFG_M1CR_WSC_Msk = 0x70000

	// M1ISR: RAMCFG RAMx interrupt status register
	// Position of SEDC field.
	RAMCFG_M1ISR_SEDC_Pos = 0x0
	// Bit mask of SEDC field.
	RAMCFG_M1ISR_SEDC_Msk = 0x1
	// Bit SEDC.
	RAMCFG_M1ISR_SEDC = 0x1
	// Position of DED field.
	RAMCFG_M1ISR_DED_Pos = 0x1
	// Bit mask of DED field.
	RAMCFG_M1ISR_DED_Msk = 0x2
	// Bit DED.
	RAMCFG_M1ISR_DED = 0x2
	// Position of SRAMBUSY field.
	RAMCFG_M1ISR_SRAMBUSY_Pos = 0x8
	// Bit mask of SRAMBUSY field.
	RAMCFG_M1ISR_SRAMBUSY_Msk = 0x100
	// Bit SRAMBUSY.
	RAMCFG_M1ISR_SRAMBUSY = 0x100

	// RAM1ERKEYR: RAMCFG SRAM x erase key register
	// Position of ERASEKEY field.
	RAMCFG_RAM1ERKEYR_ERASEKEY_Pos = 0x0
	// Bit mask of ERASEKEY field.
	RAMCFG_RAM1ERKEYR_ERASEKEY_Msk = 0xff

	// M2CR: RAMCFG SRAM x control register
	// Position of ECCE field.
	RAMCFG_M2CR_ECCE_Pos = 0x0
	// Bit mask of ECCE field.
	RAMCFG_M2CR_ECCE_Msk = 0x1
	// Bit ECCE.
	RAMCFG_M2CR_ECCE = 0x1
	// Position of ALE field.
	RAMCFG_M2CR_ALE_Pos = 0x4
	// Bit mask of ALE field.
	RAMCFG_M2CR_ALE_Msk = 0x10
	// Bit ALE.
	RAMCFG_M2CR_ALE = 0x10
	// Position of SRAMER field.
	RAMCFG_M2CR_SRAMER_Pos = 0x8
	// Bit mask of SRAMER field.
	RAMCFG_M2CR_SRAMER_Msk = 0x100
	// Bit SRAMER.
	RAMCFG_M2CR_SRAMER = 0x100
	// Position of WSC field.
	RAMCFG_M2CR_WSC_Pos = 0x10
	// Bit mask of WSC field.
	RAMCFG_M2CR_WSC_Msk = 0x70000

	// M2IER: RAMCFG SRAM x interrupt enable register
	// Position of SEIE field.
	RAMCFG_M2IER_SEIE_Pos = 0x0
	// Bit mask of SEIE field.
	RAMCFG_M2IER_SEIE_Msk = 0x1
	// Bit SEIE.
	RAMCFG_M2IER_SEIE = 0x1
	// Position of DEIE field.
	RAMCFG_M2IER_DEIE_Pos = 0x1
	// Bit mask of DEIE field.
	RAMCFG_M2IER_DEIE_Msk = 0x2
	// Bit DEIE.
	RAMCFG_M2IER_DEIE = 0x2
	// Position of ECCNMI field.
	RAMCFG_M2IER_ECCNMI_Pos = 0x3
	// Bit mask of ECCNMI field.
	RAMCFG_M2IER_ECCNMI_Msk = 0x8
	// Bit ECCNMI.
	RAMCFG_M2IER_ECCNMI = 0x8

	// M2ISR: RAMCFG RAMx interrupt status register
	// Position of SEDC field.
	RAMCFG_M2ISR_SEDC_Pos = 0x0
	// Bit mask of SEDC field.
	RAMCFG_M2ISR_SEDC_Msk = 0x1
	// Bit SEDC.
	RAMCFG_M2ISR_SEDC = 0x1
	// Position of DED field.
	RAMCFG_M2ISR_DED_Pos = 0x1
	// Bit mask of DED field.
	RAMCFG_M2ISR_DED_Msk = 0x2
	// Bit DED.
	RAMCFG_M2ISR_DED = 0x2
	// Position of SRAMBUSY field.
	RAMCFG_M2ISR_SRAMBUSY_Pos = 0x8
	// Bit mask of SRAMBUSY field.
	RAMCFG_M2ISR_SRAMBUSY_Msk = 0x100
	// Bit SRAMBUSY.
	RAMCFG_M2ISR_SRAMBUSY = 0x100

	// M2SEAR: RAMCFG RAM x ECC single error address register
	// Position of ESEA field.
	RAMCFG_M2SEAR_ESEA_Pos = 0x0
	// Bit mask of ESEA field.
	RAMCFG_M2SEAR_ESEA_Msk = 0xffffffff

	// M2DEAR: RAMCFG RAM x ECC double error address register
	// Position of EDEA field.
	RAMCFG_M2DEAR_EDEA_Pos = 0x0
	// Bit mask of EDEA field.
	RAMCFG_M2DEAR_EDEA_Msk = 0xffffffff

	// M2ICR: RAMCFG RAM x interrupt clear register x
	// Position of CSEDC field.
	RAMCFG_M2ICR_CSEDC_Pos = 0x0
	// Bit mask of CSEDC field.
	RAMCFG_M2ICR_CSEDC_Msk = 0x1
	// Bit CSEDC.
	RAMCFG_M2ICR_CSEDC = 0x1
	// Position of CDED field.
	RAMCFG_M2ICR_CDED_Pos = 0x1
	// Bit mask of CDED field.
	RAMCFG_M2ICR_CDED_Msk = 0x2
	// Bit CDED.
	RAMCFG_M2ICR_CDED = 0x2

	// M2WPR1: RAMCFG SRAM2 write protection register 1
	// Position of P0WP field.
	RAMCFG_M2WPR1_P0WP_Pos = 0x0
	// Bit mask of P0WP field.
	RAMCFG_M2WPR1_P0WP_Msk = 0x1
	// Bit P0WP.
	RAMCFG_M2WPR1_P0WP = 0x1
	// Position of P1WP field.
	RAMCFG_M2WPR1_P1WP_Pos = 0x1
	// Bit mask of P1WP field.
	RAMCFG_M2WPR1_P1WP_Msk = 0x2
	// Bit P1WP.
	RAMCFG_M2WPR1_P1WP = 0x2
	// Position of P2WP field.
	RAMCFG_M2WPR1_P2WP_Pos = 0x2
	// Bit mask of P2WP field.
	RAMCFG_M2WPR1_P2WP_Msk = 0x4
	// Bit P2WP.
	RAMCFG_M2WPR1_P2WP = 0x4
	// Position of P3WP field.
	RAMCFG_M2WPR1_P3WP_Pos = 0x3
	// Bit mask of P3WP field.
	RAMCFG_M2WPR1_P3WP_Msk = 0x8
	// Bit P3WP.
	RAMCFG_M2WPR1_P3WP = 0x8
	// Position of P4WP field.
	RAMCFG_M2WPR1_P4WP_Pos = 0x4
	// Bit mask of P4WP field.
	RAMCFG_M2WPR1_P4WP_Msk = 0x10
	// Bit P4WP.
	RAMCFG_M2WPR1_P4WP = 0x10
	// Position of P5WP field.
	RAMCFG_M2WPR1_P5WP_Pos = 0x5
	// Bit mask of P5WP field.
	RAMCFG_M2WPR1_P5WP_Msk = 0x20
	// Bit P5WP.
	RAMCFG_M2WPR1_P5WP = 0x20
	// Position of P6WP field.
	RAMCFG_M2WPR1_P6WP_Pos = 0x6
	// Bit mask of P6WP field.
	RAMCFG_M2WPR1_P6WP_Msk = 0x40
	// Bit P6WP.
	RAMCFG_M2WPR1_P6WP = 0x40
	// Position of P7WP field.
	RAMCFG_M2WPR1_P7WP_Pos = 0x7
	// Bit mask of P7WP field.
	RAMCFG_M2WPR1_P7WP_Msk = 0x80
	// Bit P7WP.
	RAMCFG_M2WPR1_P7WP = 0x80
	// Position of P8WP field.
	RAMCFG_M2WPR1_P8WP_Pos = 0x8
	// Bit mask of P8WP field.
	RAMCFG_M2WPR1_P8WP_Msk = 0x100
	// Bit P8WP.
	RAMCFG_M2WPR1_P8WP = 0x100
	// Position of P9WP field.
	RAMCFG_M2WPR1_P9WP_Pos = 0x9
	// Bit mask of P9WP field.
	RAMCFG_M2WPR1_P9WP_Msk = 0x200
	// Bit P9WP.
	RAMCFG_M2WPR1_P9WP = 0x200
	// Position of P10WP field.
	RAMCFG_M2WPR1_P10WP_Pos = 0xa
	// Bit mask of P10WP field.
	RAMCFG_M2WPR1_P10WP_Msk = 0x400
	// Bit P10WP.
	RAMCFG_M2WPR1_P10WP = 0x400
	// Position of P11WP field.
	RAMCFG_M2WPR1_P11WP_Pos = 0xb
	// Bit mask of P11WP field.
	RAMCFG_M2WPR1_P11WP_Msk = 0x800
	// Bit P11WP.
	RAMCFG_M2WPR1_P11WP = 0x800
	// Position of P12WP field.
	RAMCFG_M2WPR1_P12WP_Pos = 0xc
	// Bit mask of P12WP field.
	RAMCFG_M2WPR1_P12WP_Msk = 0x1000
	// Bit P12WP.
	RAMCFG_M2WPR1_P12WP = 0x1000
	// Position of P13WP field.
	RAMCFG_M2WPR1_P13WP_Pos = 0xd
	// Bit mask of P13WP field.
	RAMCFG_M2WPR1_P13WP_Msk = 0x2000
	// Bit P13WP.
	RAMCFG_M2WPR1_P13WP = 0x2000
	// Position of P14WP field.
	RAMCFG_M2WPR1_P14WP_Pos = 0xe
	// Bit mask of P14WP field.
	RAMCFG_M2WPR1_P14WP_Msk = 0x4000
	// Bit P14WP.
	RAMCFG_M2WPR1_P14WP = 0x4000
	// Position of P15WP field.
	RAMCFG_M2WPR1_P15WP_Pos = 0xf
	// Bit mask of P15WP field.
	RAMCFG_M2WPR1_P15WP_Msk = 0x8000
	// Bit P15WP.
	RAMCFG_M2WPR1_P15WP = 0x8000
	// Position of P16WP field.
	RAMCFG_M2WPR1_P16WP_Pos = 0x10
	// Bit mask of P16WP field.
	RAMCFG_M2WPR1_P16WP_Msk = 0x10000
	// Bit P16WP.
	RAMCFG_M2WPR1_P16WP = 0x10000
	// Position of P17WP field.
	RAMCFG_M2WPR1_P17WP_Pos = 0x11
	// Bit mask of P17WP field.
	RAMCFG_M2WPR1_P17WP_Msk = 0x20000
	// Bit P17WP.
	RAMCFG_M2WPR1_P17WP = 0x20000
	// Position of P18WP field.
	RAMCFG_M2WPR1_P18WP_Pos = 0x12
	// Bit mask of P18WP field.
	RAMCFG_M2WPR1_P18WP_Msk = 0x40000
	// Bit P18WP.
	RAMCFG_M2WPR1_P18WP = 0x40000
	// Position of P19WP field.
	RAMCFG_M2WPR1_P19WP_Pos = 0x13
	// Bit mask of P19WP field.
	RAMCFG_M2WPR1_P19WP_Msk = 0x80000
	// Bit P19WP.
	RAMCFG_M2WPR1_P19WP = 0x80000
	// Position of P20WP field.
	RAMCFG_M2WPR1_P20WP_Pos = 0x14
	// Bit mask of P20WP field.
	RAMCFG_M2WPR1_P20WP_Msk = 0x100000
	// Bit P20WP.
	RAMCFG_M2WPR1_P20WP = 0x100000
	// Position of P21WP field.
	RAMCFG_M2WPR1_P21WP_Pos = 0x15
	// Bit mask of P21WP field.
	RAMCFG_M2WPR1_P21WP_Msk = 0x200000
	// Bit P21WP.
	RAMCFG_M2WPR1_P21WP = 0x200000
	// Position of P22WP field.
	RAMCFG_M2WPR1_P22WP_Pos = 0x16
	// Bit mask of P22WP field.
	RAMCFG_M2WPR1_P22WP_Msk = 0x400000
	// Bit P22WP.
	RAMCFG_M2WPR1_P22WP = 0x400000
	// Position of P23WP field.
	RAMCFG_M2WPR1_P23WP_Pos = 0x17
	// Bit mask of P23WP field.
	RAMCFG_M2WPR1_P23WP_Msk = 0x800000
	// Bit P23WP.
	RAMCFG_M2WPR1_P23WP = 0x800000
	// Position of P24WP field.
	RAMCFG_M2WPR1_P24WP_Pos = 0x18
	// Bit mask of P24WP field.
	RAMCFG_M2WPR1_P24WP_Msk = 0x1000000
	// Bit P24WP.
	RAMCFG_M2WPR1_P24WP = 0x1000000
	// Position of P25WP field.
	RAMCFG_M2WPR1_P25WP_Pos = 0x19
	// Bit mask of P25WP field.
	RAMCFG_M2WPR1_P25WP_Msk = 0x2000000
	// Bit P25WP.
	RAMCFG_M2WPR1_P25WP = 0x2000000
	// Position of P26WP field.
	RAMCFG_M2WPR1_P26WP_Pos = 0x1a
	// Bit mask of P26WP field.
	RAMCFG_M2WPR1_P26WP_Msk = 0x4000000
	// Bit P26WP.
	RAMCFG_M2WPR1_P26WP = 0x4000000
	// Position of P27WP field.
	RAMCFG_M2WPR1_P27WP_Pos = 0x1b
	// Bit mask of P27WP field.
	RAMCFG_M2WPR1_P27WP_Msk = 0x8000000
	// Bit P27WP.
	RAMCFG_M2WPR1_P27WP = 0x8000000
	// Position of P28WP field.
	RAMCFG_M2WPR1_P28WP_Pos = 0x1c
	// Bit mask of P28WP field.
	RAMCFG_M2WPR1_P28WP_Msk = 0x10000000
	// Bit P28WP.
	RAMCFG_M2WPR1_P28WP = 0x10000000
	// Position of P29WP field.
	RAMCFG_M2WPR1_P29WP_Pos = 0x1d
	// Bit mask of P29WP field.
	RAMCFG_M2WPR1_P29WP_Msk = 0x20000000
	// Bit P29WP.
	RAMCFG_M2WPR1_P29WP = 0x20000000
	// Position of P30WP field.
	RAMCFG_M2WPR1_P30WP_Pos = 0x1e
	// Bit mask of P30WP field.
	RAMCFG_M2WPR1_P30WP_Msk = 0x40000000
	// Bit P30WP.
	RAMCFG_M2WPR1_P30WP = 0x40000000
	// Position of P31WP field.
	RAMCFG_M2WPR1_P31WP_Pos = 0x1f
	// Bit mask of P31WP field.
	RAMCFG_M2WPR1_P31WP_Msk = 0x80000000
	// Bit P31WP.
	RAMCFG_M2WPR1_P31WP = 0x80000000

	// M2WPR2: RAMCFG SRAM2 write protection register 2
	// Position of P32WP field.
	RAMCFG_M2WPR2_P32WP_Pos = 0x0
	// Bit mask of P32WP field.
	RAMCFG_M2WPR2_P32WP_Msk = 0x1
	// Bit P32WP.
	RAMCFG_M2WPR2_P32WP = 0x1
	// Position of P33WP field.
	RAMCFG_M2WPR2_P33WP_Pos = 0x1
	// Bit mask of P33WP field.
	RAMCFG_M2WPR2_P33WP_Msk = 0x2
	// Bit P33WP.
	RAMCFG_M2WPR2_P33WP = 0x2
	// Position of P34WP field.
	RAMCFG_M2WPR2_P34WP_Pos = 0x2
	// Bit mask of P34WP field.
	RAMCFG_M2WPR2_P34WP_Msk = 0x4
	// Bit P34WP.
	RAMCFG_M2WPR2_P34WP = 0x4
	// Position of P35WP field.
	RAMCFG_M2WPR2_P35WP_Pos = 0x3
	// Bit mask of P35WP field.
	RAMCFG_M2WPR2_P35WP_Msk = 0x8
	// Bit P35WP.
	RAMCFG_M2WPR2_P35WP = 0x8
	// Position of P36WP field.
	RAMCFG_M2WPR2_P36WP_Pos = 0x4
	// Bit mask of P36WP field.
	RAMCFG_M2WPR2_P36WP_Msk = 0x10
	// Bit P36WP.
	RAMCFG_M2WPR2_P36WP = 0x10
	// Position of P37WP field.
	RAMCFG_M2WPR2_P37WP_Pos = 0x5
	// Bit mask of P37WP field.
	RAMCFG_M2WPR2_P37WP_Msk = 0x20
	// Bit P37WP.
	RAMCFG_M2WPR2_P37WP = 0x20
	// Position of P38WP field.
	RAMCFG_M2WPR2_P38WP_Pos = 0x6
	// Bit mask of P38WP field.
	RAMCFG_M2WPR2_P38WP_Msk = 0x40
	// Bit P38WP.
	RAMCFG_M2WPR2_P38WP = 0x40
	// Position of P39WP field.
	RAMCFG_M2WPR2_P39WP_Pos = 0x7
	// Bit mask of P39WP field.
	RAMCFG_M2WPR2_P39WP_Msk = 0x80
	// Bit P39WP.
	RAMCFG_M2WPR2_P39WP = 0x80
	// Position of P40WP field.
	RAMCFG_M2WPR2_P40WP_Pos = 0x8
	// Bit mask of P40WP field.
	RAMCFG_M2WPR2_P40WP_Msk = 0x100
	// Bit P40WP.
	RAMCFG_M2WPR2_P40WP = 0x100
	// Position of P41WP field.
	RAMCFG_M2WPR2_P41WP_Pos = 0x9
	// Bit mask of P41WP field.
	RAMCFG_M2WPR2_P41WP_Msk = 0x200
	// Bit P41WP.
	RAMCFG_M2WPR2_P41WP = 0x200
	// Position of P42WP field.
	RAMCFG_M2WPR2_P42WP_Pos = 0xa
	// Bit mask of P42WP field.
	RAMCFG_M2WPR2_P42WP_Msk = 0x400
	// Bit P42WP.
	RAMCFG_M2WPR2_P42WP = 0x400
	// Position of P43WP field.
	RAMCFG_M2WPR2_P43WP_Pos = 0xb
	// Bit mask of P43WP field.
	RAMCFG_M2WPR2_P43WP_Msk = 0x800
	// Bit P43WP.
	RAMCFG_M2WPR2_P43WP = 0x800
	// Position of P44WP field.
	RAMCFG_M2WPR2_P44WP_Pos = 0xc
	// Bit mask of P44WP field.
	RAMCFG_M2WPR2_P44WP_Msk = 0x1000
	// Bit P44WP.
	RAMCFG_M2WPR2_P44WP = 0x1000
	// Position of P45WP field.
	RAMCFG_M2WPR2_P45WP_Pos = 0xd
	// Bit mask of P45WP field.
	RAMCFG_M2WPR2_P45WP_Msk = 0x2000
	// Bit P45WP.
	RAMCFG_M2WPR2_P45WP = 0x2000
	// Position of P46WP field.
	RAMCFG_M2WPR2_P46WP_Pos = 0xe
	// Bit mask of P46WP field.
	RAMCFG_M2WPR2_P46WP_Msk = 0x4000
	// Bit P46WP.
	RAMCFG_M2WPR2_P46WP = 0x4000
	// Position of P47WP field.
	RAMCFG_M2WPR2_P47WP_Pos = 0xf
	// Bit mask of P47WP field.
	RAMCFG_M2WPR2_P47WP_Msk = 0x8000
	// Bit P47WP.
	RAMCFG_M2WPR2_P47WP = 0x8000
	// Position of P48WP field.
	RAMCFG_M2WPR2_P48WP_Pos = 0x10
	// Bit mask of P48WP field.
	RAMCFG_M2WPR2_P48WP_Msk = 0x10000
	// Bit P48WP.
	RAMCFG_M2WPR2_P48WP = 0x10000
	// Position of P49WP field.
	RAMCFG_M2WPR2_P49WP_Pos = 0x11
	// Bit mask of P49WP field.
	RAMCFG_M2WPR2_P49WP_Msk = 0x20000
	// Bit P49WP.
	RAMCFG_M2WPR2_P49WP = 0x20000
	// Position of P50WP field.
	RAMCFG_M2WPR2_P50WP_Pos = 0x12
	// Bit mask of P50WP field.
	RAMCFG_M2WPR2_P50WP_Msk = 0x40000
	// Bit P50WP.
	RAMCFG_M2WPR2_P50WP = 0x40000
	// Position of P51WP field.
	RAMCFG_M2WPR2_P51WP_Pos = 0x13
	// Bit mask of P51WP field.
	RAMCFG_M2WPR2_P51WP_Msk = 0x80000
	// Bit P51WP.
	RAMCFG_M2WPR2_P51WP = 0x80000
	// Position of P52WP field.
	RAMCFG_M2WPR2_P52WP_Pos = 0x14
	// Bit mask of P52WP field.
	RAMCFG_M2WPR2_P52WP_Msk = 0x100000
	// Bit P52WP.
	RAMCFG_M2WPR2_P52WP = 0x100000
	// Position of P53WP field.
	RAMCFG_M2WPR2_P53WP_Pos = 0x15
	// Bit mask of P53WP field.
	RAMCFG_M2WPR2_P53WP_Msk = 0x200000
	// Bit P53WP.
	RAMCFG_M2WPR2_P53WP = 0x200000
	// Position of P54WP field.
	RAMCFG_M2WPR2_P54WP_Pos = 0x16
	// Bit mask of P54WP field.
	RAMCFG_M2WPR2_P54WP_Msk = 0x400000
	// Bit P54WP.
	RAMCFG_M2WPR2_P54WP = 0x400000
	// Position of P55WP field.
	RAMCFG_M2WPR2_P55WP_Pos = 0x17
	// Bit mask of P55WP field.
	RAMCFG_M2WPR2_P55WP_Msk = 0x800000
	// Bit P55WP.
	RAMCFG_M2WPR2_P55WP = 0x800000
	// Position of P56WP field.
	RAMCFG_M2WPR2_P56WP_Pos = 0x18
	// Bit mask of P56WP field.
	RAMCFG_M2WPR2_P56WP_Msk = 0x1000000
	// Bit P56WP.
	RAMCFG_M2WPR2_P56WP = 0x1000000
	// Position of P57WP field.
	RAMCFG_M2WPR2_P57WP_Pos = 0x19
	// Bit mask of P57WP field.
	RAMCFG_M2WPR2_P57WP_Msk = 0x2000000
	// Bit P57WP.
	RAMCFG_M2WPR2_P57WP = 0x2000000
	// Position of P58WP field.
	RAMCFG_M2WPR2_P58WP_Pos = 0x1a
	// Bit mask of P58WP field.
	RAMCFG_M2WPR2_P58WP_Msk = 0x4000000
	// Bit P58WP.
	RAMCFG_M2WPR2_P58WP = 0x4000000
	// Position of P59WP field.
	RAMCFG_M2WPR2_P59WP_Pos = 0x1b
	// Bit mask of P59WP field.
	RAMCFG_M2WPR2_P59WP_Msk = 0x8000000
	// Bit P59WP.
	RAMCFG_M2WPR2_P59WP = 0x8000000
	// Position of P60WP field.
	RAMCFG_M2WPR2_P60WP_Pos = 0x1c
	// Bit mask of P60WP field.
	RAMCFG_M2WPR2_P60WP_Msk = 0x10000000
	// Bit P60WP.
	RAMCFG_M2WPR2_P60WP = 0x10000000
	// Position of P61WP field.
	RAMCFG_M2WPR2_P61WP_Pos = 0x1d
	// Bit mask of P61WP field.
	RAMCFG_M2WPR2_P61WP_Msk = 0x20000000
	// Bit P61WP.
	RAMCFG_M2WPR2_P61WP = 0x20000000
	// Position of P62WP field.
	RAMCFG_M2WPR2_P62WP_Pos = 0x1e
	// Bit mask of P62WP field.
	RAMCFG_M2WPR2_P62WP_Msk = 0x40000000
	// Bit P62WP.
	RAMCFG_M2WPR2_P62WP = 0x40000000
	// Position of P63WP field.
	RAMCFG_M2WPR2_P63WP_Pos = 0x1f
	// Bit mask of P63WP field.
	RAMCFG_M2WPR2_P63WP_Msk = 0x80000000
	// Bit P63WP.
	RAMCFG_M2WPR2_P63WP = 0x80000000

	// M2ECCKEYR: RAMCFG SRAM x ECC key register
	// Position of ECCKEY field.
	RAMCFG_M2ECCKEYR_ECCKEY_Pos = 0x0
	// Bit mask of ECCKEY field.
	RAMCFG_M2ECCKEYR_ECCKEY_Msk = 0xff

	// M2ERKEYR: RAMCFG SRAM x erase key register
	// Position of ERASEKEY field.
	RAMCFG_M2ERKEYR_ERASEKEY_Pos = 0x0
	// Bit mask of ERASEKEY field.
	RAMCFG_M2ERKEYR_ERASEKEY_Msk = 0xff

	// M3CR: RAMCFG SRAM x control register
	// Position of ECCE field.
	RAMCFG_M3CR_ECCE_Pos = 0x0
	// Bit mask of ECCE field.
	RAMCFG_M3CR_ECCE_Msk = 0x1
	// Bit ECCE.
	RAMCFG_M3CR_ECCE = 0x1
	// Position of ALE field.
	RAMCFG_M3CR_ALE_Pos = 0x4
	// Bit mask of ALE field.
	RAMCFG_M3CR_ALE_Msk = 0x10
	// Bit ALE.
	RAMCFG_M3CR_ALE = 0x10
	// Position of SRAMER field.
	RAMCFG_M3CR_SRAMER_Pos = 0x8
	// Bit mask of SRAMER field.
	RAMCFG_M3CR_SRAMER_Msk = 0x100
	// Bit SRAMER.
	RAMCFG_M3CR_SRAMER = 0x100
	// Position of WSC field.
	RAMCFG_M3CR_WSC_Pos = 0x10
	// Bit mask of WSC field.
	RAMCFG_M3CR_WSC_Msk = 0x70000

	// M3IER: RAMCFG SRAM x interrupt enable register
	// Position of SEIE field.
	RAMCFG_M3IER_SEIE_Pos = 0x0
	// Bit mask of SEIE field.
	RAMCFG_M3IER_SEIE_Msk = 0x1
	// Bit SEIE.
	RAMCFG_M3IER_SEIE = 0x1
	// Position of DEIE field.
	RAMCFG_M3IER_DEIE_Pos = 0x1
	// Bit mask of DEIE field.
	RAMCFG_M3IER_DEIE_Msk = 0x2
	// Bit DEIE.
	RAMCFG_M3IER_DEIE = 0x2
	// Position of ECCNMI field.
	RAMCFG_M3IER_ECCNMI_Pos = 0x3
	// Bit mask of ECCNMI field.
	RAMCFG_M3IER_ECCNMI_Msk = 0x8
	// Bit ECCNMI.
	RAMCFG_M3IER_ECCNMI = 0x8

	// M3ISR: RAMCFG RAMx interrupt status register
	// Position of SEDC field.
	RAMCFG_M3ISR_SEDC_Pos = 0x0
	// Bit mask of SEDC field.
	RAMCFG_M3ISR_SEDC_Msk = 0x1
	// Bit SEDC.
	RAMCFG_M3ISR_SEDC = 0x1
	// Position of DED field.
	RAMCFG_M3ISR_DED_Pos = 0x1
	// Bit mask of DED field.
	RAMCFG_M3ISR_DED_Msk = 0x2
	// Bit DED.
	RAMCFG_M3ISR_DED = 0x2
	// Position of SRAMBUSY field.
	RAMCFG_M3ISR_SRAMBUSY_Pos = 0x8
	// Bit mask of SRAMBUSY field.
	RAMCFG_M3ISR_SRAMBUSY_Msk = 0x100
	// Bit SRAMBUSY.
	RAMCFG_M3ISR_SRAMBUSY = 0x100

	// M3SEAR: RAMCFG RAM x ECC single error address register
	// Position of ESEA field.
	RAMCFG_M3SEAR_ESEA_Pos = 0x0
	// Bit mask of ESEA field.
	RAMCFG_M3SEAR_ESEA_Msk = 0xffffffff

	// M3DEAR: RAMCFG RAM x ECC double error address register
	// Position of EDEA field.
	RAMCFG_M3DEAR_EDEA_Pos = 0x0
	// Bit mask of EDEA field.
	RAMCFG_M3DEAR_EDEA_Msk = 0xffffffff

	// M3ICR: RAMCFG RAM x interrupt clear register x
	// Position of CSEDC field.
	RAMCFG_M3ICR_CSEDC_Pos = 0x0
	// Bit mask of CSEDC field.
	RAMCFG_M3ICR_CSEDC_Msk = 0x1
	// Bit CSEDC.
	RAMCFG_M3ICR_CSEDC = 0x1
	// Position of CDED field.
	RAMCFG_M3ICR_CDED_Pos = 0x1
	// Bit mask of CDED field.
	RAMCFG_M3ICR_CDED_Msk = 0x2
	// Bit CDED.
	RAMCFG_M3ICR_CDED = 0x2

	// M3ECCKEYR: RAMCFG SRAM x ECC key register
	// Position of ECCKEY field.
	RAMCFG_M3ECCKEYR_ECCKEY_Pos = 0x0
	// Bit mask of ECCKEY field.
	RAMCFG_M3ECCKEYR_ECCKEY_Msk = 0xff

	// M3ERKEYR: RAMCFG SRAM x erase key register
	// Position of ERASEKEY field.
	RAMCFG_M3ERKEYR_ERASEKEY_Pos = 0x0
	// Bit mask of ERASEKEY field.
	RAMCFG_M3ERKEYR_ERASEKEY_Msk = 0xff

	// M4CR: RAMCFG SRAM x control register
	// Position of ECCE field.
	RAMCFG_M4CR_ECCE_Pos = 0x0
	// Bit mask of ECCE field.
	RAMCFG_M4CR_ECCE_Msk = 0x1
	// Bit ECCE.
	RAMCFG_M4CR_ECCE = 0x1
	// Position of ALE field.
	RAMCFG_M4CR_ALE_Pos = 0x4
	// Bit mask of ALE field.
	RAMCFG_M4CR_ALE_Msk = 0x10
	// Bit ALE.
	RAMCFG_M4CR_ALE = 0x10
	// Position of SRAMER field.
	RAMCFG_M4CR_SRAMER_Pos = 0x8
	// Bit mask of SRAMER field.
	RAMCFG_M4CR_SRAMER_Msk = 0x100
	// Bit SRAMER.
	RAMCFG_M4CR_SRAMER = 0x100
	// Position of WSC field.
	RAMCFG_M4CR_WSC_Pos = 0x10
	// Bit mask of WSC field.
	RAMCFG_M4CR_WSC_Msk = 0x70000

	// M4ISR: RAMCFG RAMx interrupt status register
	// Position of SEDC field.
	RAMCFG_M4ISR_SEDC_Pos = 0x0
	// Bit mask of SEDC field.
	RAMCFG_M4ISR_SEDC_Msk = 0x1
	// Bit SEDC.
	RAMCFG_M4ISR_SEDC = 0x1
	// Position of DED field.
	RAMCFG_M4ISR_DED_Pos = 0x1
	// Bit mask of DED field.
	RAMCFG_M4ISR_DED_Msk = 0x2
	// Bit DED.
	RAMCFG_M4ISR_DED = 0x2
	// Position of SRAMBUSY field.
	RAMCFG_M4ISR_SRAMBUSY_Pos = 0x8
	// Bit mask of SRAMBUSY field.
	RAMCFG_M4ISR_SRAMBUSY_Msk = 0x100
	// Bit SRAMBUSY.
	RAMCFG_M4ISR_SRAMBUSY = 0x100

	// M4ERKEYR: RAMCFG SRAM x erase key register
	// Position of ERASEKEY field.
	RAMCFG_M4ERKEYR_ERASEKEY_Pos = 0x0
	// Bit mask of ERASEKEY field.
	RAMCFG_M4ERKEYR_ERASEKEY_Msk = 0xff

	// M5CR: RAMCFG SRAM x control register
	// Position of ECCE field.
	RAMCFG_M5CR_ECCE_Pos = 0x0
	// Bit mask of ECCE field.
	RAMCFG_M5CR_ECCE_Msk = 0x1
	// Bit ECCE.
	RAMCFG_M5CR_ECCE = 0x1
	// Position of ALE field.
	RAMCFG_M5CR_ALE_Pos = 0x4
	// Bit mask of ALE field.
	RAMCFG_M5CR_ALE_Msk = 0x10
	// Bit ALE.
	RAMCFG_M5CR_ALE = 0x10
	// Position of SRAMER field.
	RAMCFG_M5CR_SRAMER_Pos = 0x8
	// Bit mask of SRAMER field.
	RAMCFG_M5CR_SRAMER_Msk = 0x100
	// Bit SRAMER.
	RAMCFG_M5CR_SRAMER = 0x100
	// Position of WSC field.
	RAMCFG_M5CR_WSC_Pos = 0x10
	// Bit mask of WSC field.
	RAMCFG_M5CR_WSC_Msk = 0x70000

	// M5IER: RAMCFG SRAM x interrupt enable register
	// Position of SEIE field.
	RAMCFG_M5IER_SEIE_Pos = 0x0
	// Bit mask of SEIE field.
	RAMCFG_M5IER_SEIE_Msk = 0x1
	// Bit SEIE.
	RAMCFG_M5IER_SEIE = 0x1
	// Position of DEIE field.
	RAMCFG_M5IER_DEIE_Pos = 0x1
	// Bit mask of DEIE field.
	RAMCFG_M5IER_DEIE_Msk = 0x2
	// Bit DEIE.
	RAMCFG_M5IER_DEIE = 0x2
	// Position of ECCNMI field.
	RAMCFG_M5IER_ECCNMI_Pos = 0x3
	// Bit mask of ECCNMI field.
	RAMCFG_M5IER_ECCNMI_Msk = 0x8
	// Bit ECCNMI.
	RAMCFG_M5IER_ECCNMI = 0x8

	// M5ISR: RAMCFG RAMx interrupt status register
	// Position of SEDC field.
	RAMCFG_M5ISR_SEDC_Pos = 0x0
	// Bit mask of SEDC field.
	RAMCFG_M5ISR_SEDC_Msk = 0x1
	// Bit SEDC.
	RAMCFG_M5ISR_SEDC = 0x1
	// Position of DED field.
	RAMCFG_M5ISR_DED_Pos = 0x1
	// Bit mask of DED field.
	RAMCFG_M5ISR_DED_Msk = 0x2
	// Bit DED.
	RAMCFG_M5ISR_DED = 0x2
	// Position of SRAMBUSY field.
	RAMCFG_M5ISR_SRAMBUSY_Pos = 0x8
	// Bit mask of SRAMBUSY field.
	RAMCFG_M5ISR_SRAMBUSY_Msk = 0x100
	// Bit SRAMBUSY.
	RAMCFG_M5ISR_SRAMBUSY = 0x100

	// M5SEAR: RAMCFG RAM x ECC single error address register
	// Position of ESEA field.
	RAMCFG_M5SEAR_ESEA_Pos = 0x0
	// Bit mask of ESEA field.
	RAMCFG_M5SEAR_ESEA_Msk = 0xffffffff

	// M5DEAR: RAMCFG RAM x ECC double error address register
	// Position of EDEA field.
	RAMCFG_M5DEAR_EDEA_Pos = 0x0
	// Bit mask of EDEA field.
	RAMCFG_M5DEAR_EDEA_Msk = 0xffffffff

	// M5ICR: RAMCFG RAM x interrupt clear register x
	// Position of CSEDC field.
	RAMCFG_M5ICR_CSEDC_Pos = 0x0
	// Bit mask of CSEDC field.
	RAMCFG_M5ICR_CSEDC_Msk = 0x1
	// Bit CSEDC.
	RAMCFG_M5ICR_CSEDC = 0x1
	// Position of CDED field.
	RAMCFG_M5ICR_CDED_Pos = 0x1
	// Bit mask of CDED field.
	RAMCFG_M5ICR_CDED_Msk = 0x2
	// Bit CDED.
	RAMCFG_M5ICR_CDED = 0x2

	// M5ECCKEYR: RAMCFG RAM x interrupt clear register x
	// Position of ECCKEY field.
	RAMCFG_M5ECCKEYR_ECCKEY_Pos = 0x0
	// Bit mask of ECCKEY field.
	RAMCFG_M5ECCKEYR_ECCKEY_Msk = 0xff

	// M5ERKEYR
	// Position of ERASEKEY field.
	RAMCFG_M5ERKEYR_ERASEKEY_Pos = 0x0
	// Bit mask of ERASEKEY field.
	RAMCFG_M5ERKEYR_ERASEKEY_Msk = 0xff

	// M6CR: memory x control register
	// Position of ECCE field.
	RAMCFG_M6CR_ECCE_Pos = 0x0
	// Bit mask of ECCE field.
	RAMCFG_M6CR_ECCE_Msk = 0x1
	// Bit ECCE.
	RAMCFG_M6CR_ECCE = 0x1
	// Position of ALE field.
	RAMCFG_M6CR_ALE_Pos = 0x4
	// Bit mask of ALE field.
	RAMCFG_M6CR_ALE_Msk = 0x10
	// Bit ALE.
	RAMCFG_M6CR_ALE = 0x10
	// Position of SRAMER field.
	RAMCFG_M6CR_SRAMER_Pos = 0x8
	// Bit mask of SRAMER field.
	RAMCFG_M6CR_SRAMER_Msk = 0x100
	// Bit SRAMER.
	RAMCFG_M6CR_SRAMER = 0x100
	// Position of WSC field.
	RAMCFG_M6CR_WSC_Pos = 0x10
	// Bit mask of WSC field.
	RAMCFG_M6CR_WSC_Msk = 0x70000

	// M6ISR
	// Position of SEDC field.
	RAMCFG_M6ISR_SEDC_Pos = 0x0
	// Bit mask of SEDC field.
	RAMCFG_M6ISR_SEDC_Msk = 0x1
	// Bit SEDC.
	RAMCFG_M6ISR_SEDC = 0x1
	// Position of DED field.
	RAMCFG_M6ISR_DED_Pos = 0x1
	// Bit mask of DED field.
	RAMCFG_M6ISR_DED_Msk = 0x2
	// Bit DED.
	RAMCFG_M6ISR_DED = 0x2
	// Position of SRAMBUSY field.
	RAMCFG_M6ISR_SRAMBUSY_Pos = 0x8
	// Bit mask of SRAMBUSY field.
	RAMCFG_M6ISR_SRAMBUSY_Msk = 0x100
	// Bit SRAMBUSY.
	RAMCFG_M6ISR_SRAMBUSY = 0x100

	// M6ERKEYR
	// Position of ERASEKEY field.
	RAMCFG_M6ERKEYR_ERASEKEY_Pos = 0x0
	// Bit mask of ERASEKEY field.
	RAMCFG_M6ERKEYR_ERASEKEY_Msk = 0xff
)

// Constants for RCC: Reset and clock control
const (
	// CR: RCC clock control register
	// Position of MSISON field.
	RCC_CR_MSISON_Pos = 0x0
	// Bit mask of MSISON field.
	RCC_CR_MSISON_Msk = 0x1
	// Bit MSISON.
	RCC_CR_MSISON = 0x1
	// MSIS (MSI system) oscillator off
	RCC_CR_MSISON_Disabled = 0x0
	// MSIS (MSI system) oscillator on
	RCC_CR_MSISON_Enabled = 0x1
	// Position of MSIKERON field.
	RCC_CR_MSIKERON_Pos = 0x1
	// Bit mask of MSIKERON field.
	RCC_CR_MSIKERON_Msk = 0x2
	// Bit MSIKERON.
	RCC_CR_MSIKERON = 0x2
	// No effect on MSI oscillator
	RCC_CR_MSIKERON_NotForced = 0x0
	// MSI oscillator forced ON even in Stop mode
	RCC_CR_MSIKERON_Forced = 0x1
	// Position of MSISRDY field.
	RCC_CR_MSISRDY_Pos = 0x2
	// Bit mask of MSISRDY field.
	RCC_CR_MSISRDY_Msk = 0x4
	// Bit MSISRDY.
	RCC_CR_MSISRDY = 0x4
	// MSIS (MSI system) oscillator not ready
	RCC_CR_MSISRDY_NotReady = 0x0
	// MSIS (MSI system) oscillator ready
	RCC_CR_MSISRDY_Ready = 0x1
	// Position of MSIPLLEN field.
	RCC_CR_MSIPLLEN_Pos = 0x3
	// Bit mask of MSIPLLEN field.
	RCC_CR_MSIPLLEN_Msk = 0x8
	// Bit MSIPLLEN.
	RCC_CR_MSIPLLEN = 0x8
	// MSI PLL-mode OFF
	RCC_CR_MSIPLLEN_Disabled = 0x0
	// MSI PLL-mode ON
	RCC_CR_MSIPLLEN_Enabled = 0x1
	// Position of MSIKON field.
	RCC_CR_MSIKON_Pos = 0x4
	// Bit mask of MSIKON field.
	RCC_CR_MSIKON_Msk = 0x10
	// Bit MSIKON.
	RCC_CR_MSIKON = 0x10
	// MSIK (MSI kernel) oscillator disabled
	RCC_CR_MSIKON_Disabled = 0x0
	// MSIK (MSI kernel) oscillator enabled
	RCC_CR_MSIKON_Enabled = 0x1
	// Position of MSIKRDY field.
	RCC_CR_MSIKRDY_Pos = 0x5
	// Bit mask of MSIKRDY field.
	RCC_CR_MSIKRDY_Msk = 0x20
	// Bit MSIKRDY.
	RCC_CR_MSIKRDY = 0x20
	// MSIK (MSI kernel) oscillator not ready
	RCC_CR_MSIKRDY_NotReady = 0x0
	// MSIK (MSI kernel) oscillator ready
	RCC_CR_MSIKRDY_Ready = 0x1
	// Position of MSIPLLSEL field.
	RCC_CR_MSIPLLSEL_Pos = 0x6
	// Bit mask of MSIPLLSEL field.
	RCC_CR_MSIPLLSEL_Msk = 0x40
	// Bit MSIPLLSEL.
	RCC_CR_MSIPLLSEL = 0x40
	// PLL mode applied to MSIK (MSI kernel) clock output
	RCC_CR_MSIPLLSEL_MSIK = 0x0
	// PLL mode applied to MSIS (MSI system) clock output
	RCC_CR_MSIPLLSEL_MSIS = 0x1
	// Position of MSIPLLFAST field.
	RCC_CR_MSIPLLFAST_Pos = 0x7
	// Bit mask of MSIPLLFAST field.
	RCC_CR_MSIPLLFAST_Msk = 0x80
	// Bit MSIPLLFAST.
	RCC_CR_MSIPLLFAST = 0x80
	// MSI PLL normal start-up
	RCC_CR_MSIPLLFAST_Normal = 0x0
	// MSI PLL fast start-up
	RCC_CR_MSIPLLFAST_Fast = 0x1
	// Position of HSION field.
	RCC_CR_HSION_Pos = 0x8
	// Bit mask of HSION field.
	RCC_CR_HSION_Msk = 0x100
	// Bit HSION.
	RCC_CR_HSION = 0x100
	// HSI16 oscillator off
	RCC_CR_HSION_Disabled = 0x0
	// HSI16 oscillator on
	RCC_CR_HSION_Enabled = 0x1
	// Position of HSIKERON field.
	RCC_CR_HSIKERON_Pos = 0x9
	// Bit mask of HSIKERON field.
	RCC_CR_HSIKERON_Msk = 0x200
	// Bit HSIKERON.
	RCC_CR_HSIKERON = 0x200
	// No effect on HSI16 oscillator
	RCC_CR_HSIKERON_NotForced = 0x0
	// HSI16 oscillator forced on even in Stop mode
	RCC_CR_HSIKERON_Forced = 0x1
	// Position of HSIRDY field.
	RCC_CR_HSIRDY_Pos = 0xa
	// Bit mask of HSIRDY field.
	RCC_CR_HSIRDY_Msk = 0x400
	// Bit HSIRDY.
	RCC_CR_HSIRDY = 0x400
	// HSI16 oscillator not ready
	RCC_CR_HSIRDY_NotReady = 0x0
	// HSI16 oscillator ready
	RCC_CR_HSIRDY_Ready = 0x1
	// Position of HSI48ON field.
	RCC_CR_HSI48ON_Pos = 0xc
	// Bit mask of HSI48ON field.
	RCC_CR_HSI48ON_Msk = 0x1000
	// Bit HSI48ON.
	RCC_CR_HSI48ON = 0x1000
	// HSI48 oscillator off
	RCC_CR_HSI48ON_Disabled = 0x0
	// HSI48 oscillator on
	RCC_CR_HSI48ON_Enabled = 0x1
	// Position of HSI48RDY field.
	RCC_CR_HSI48RDY_Pos = 0xd
	// Bit mask of HSI48RDY field.
	RCC_CR_HSI48RDY_Msk = 0x2000
	// Bit HSI48RDY.
	RCC_CR_HSI48RDY = 0x2000
	// HSI48 oscillator not ready
	RCC_CR_HSI48RDY_NotReady = 0x0
	// HSI48 oscillator ready
	RCC_CR_HSI48RDY_Ready = 0x1
	// Position of SHSION field.
	RCC_CR_SHSION_Pos = 0xe
	// Bit mask of SHSION field.
	RCC_CR_SHSION_Msk = 0x4000
	// Bit SHSION.
	RCC_CR_SHSION = 0x4000
	// SHSI oscillator off
	RCC_CR_SHSION_Disabled = 0x0
	// SHSI oscillator on
	RCC_CR_SHSION_Enabled = 0x1
	// Position of SHSIRDY field.
	RCC_CR_SHSIRDY_Pos = 0xf
	// Bit mask of SHSIRDY field.
	RCC_CR_SHSIRDY_Msk = 0x8000
	// Bit SHSIRDY.
	RCC_CR_SHSIRDY = 0x8000
	// SHSI oscillator not ready
	RCC_CR_SHSIRDY_NotReady = 0x0
	// SHSI oscillator ready
	RCC_CR_SHSIRDY_Ready = 0x1
	// Position of HSEON field.
	RCC_CR_HSEON_Pos = 0x10
	// Bit mask of HSEON field.
	RCC_CR_HSEON_Msk = 0x10000
	// Bit HSEON.
	RCC_CR_HSEON = 0x10000
	// HSE oscillator off
	RCC_CR_HSEON_Disabled = 0x0
	// HSE oscillator on
	RCC_CR_HSEON_Enabled = 0x1
	// Position of HSERDY field.
	RCC_CR_HSERDY_Pos = 0x11
	// Bit mask of HSERDY field.
	RCC_CR_HSERDY_Msk = 0x20000
	// Bit HSERDY.
	RCC_CR_HSERDY = 0x20000
	// HSE oscillator not ready
	RCC_CR_HSERDY_NotReady = 0x0
	// HSE oscillator ready
	RCC_CR_HSERDY_Ready = 0x1
	// Position of HSEBYP field.
	RCC_CR_HSEBYP_Pos = 0x12
	// Bit mask of HSEBYP field.
	RCC_CR_HSEBYP_Msk = 0x40000
	// Bit HSEBYP.
	RCC_CR_HSEBYP = 0x40000
	// HSE crystal oscillator not bypassed
	RCC_CR_HSEBYP_NotBypassed = 0x0
	// HSE crystal oscillator bypassed with external clock
	RCC_CR_HSEBYP_Bypassed = 0x1
	// Position of CSSON field.
	RCC_CR_CSSON_Pos = 0x13
	// Bit mask of CSSON field.
	RCC_CR_CSSON_Msk = 0x80000
	// Bit CSSON.
	RCC_CR_CSSON = 0x80000
	// Clock security system OFF (clock detector OFF)
	RCC_CR_CSSON_Disabled = 0x0
	// Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not)
	RCC_CR_CSSON_Enabled = 0x1
	// Position of HSEEXT field.
	RCC_CR_HSEEXT_Pos = 0x14
	// Bit mask of HSEEXT field.
	RCC_CR_HSEEXT_Msk = 0x100000
	// Bit HSEEXT.
	RCC_CR_HSEEXT = 0x100000
	// external HSE clock analog mode
	RCC_CR_HSEEXT_Analog = 0x0
	// external HSE clock digital mode (through I/O Schmitt trigger)
	RCC_CR_HSEEXT_Digital = 0x1
	// Position of PLL1ON field.
	RCC_CR_PLL1ON_Pos = 0x18
	// Bit mask of PLL1ON field.
	RCC_CR_PLL1ON_Msk = 0x1000000
	// Bit PLL1ON.
	RCC_CR_PLL1ON = 0x1000000
	// PLL1 OFF
	RCC_CR_PLL1ON_Disabled = 0x0
	// PLL1 ON
	RCC_CR_PLL1ON_Enabled = 0x1
	// Position of PLL1RDY field.
	RCC_CR_PLL1RDY_Pos = 0x19
	// Bit mask of PLL1RDY field.
	RCC_CR_PLL1RDY_Msk = 0x2000000
	// Bit PLL1RDY.
	RCC_CR_PLL1RDY = 0x2000000
	// PLL1 unlocked
	RCC_CR_PLL1RDY_Unlocked = 0x0
	// PLL1 locked
	RCC_CR_PLL1RDY_Locked = 0x1
	// Position of PLL2ON field.
	RCC_CR_PLL2ON_Pos = 0x1a
	// Bit mask of PLL2ON field.
	RCC_CR_PLL2ON_Msk = 0x4000000
	// Bit PLL2ON.
	RCC_CR_PLL2ON = 0x4000000
	// PLL2 OFF
	RCC_CR_PLL2ON_Disabled = 0x0
	// PLL2 ON
	RCC_CR_PLL2ON_Enabled = 0x1
	// Position of PLL2RDY field.
	RCC_CR_PLL2RDY_Pos = 0x1b
	// Bit mask of PLL2RDY field.
	RCC_CR_PLL2RDY_Msk = 0x8000000
	// Bit PLL2RDY.
	RCC_CR_PLL2RDY = 0x8000000
	// PLL2 unlocked
	RCC_CR_PLL2RDY_Unlocked = 0x0
	// PLL2 locked
	RCC_CR_PLL2RDY_Locked = 0x1
	// Position of PLL3ON field.
	RCC_CR_PLL3ON_Pos = 0x1c
	// Bit mask of PLL3ON field.
	RCC_CR_PLL3ON_Msk = 0x10000000
	// Bit PLL3ON.
	RCC_CR_PLL3ON = 0x10000000
	// PLL3 OFF
	RCC_CR_PLL3ON_Disabled = 0x0
	// PLL3 ON
	RCC_CR_PLL3ON_Enabled = 0x1
	// Position of PLL3RDY field.
	RCC_CR_PLL3RDY_Pos = 0x1d
	// Bit mask of PLL3RDY field.
	RCC_CR_PLL3RDY_Msk = 0x20000000
	// Bit PLL3RDY.
	RCC_CR_PLL3RDY = 0x20000000
	// PLL3 unlocked
	RCC_CR_PLL3RDY_Unlocked = 0x0
	// PLL3 locked
	RCC_CR_PLL3RDY_Locked = 0x1

	// ICSCR1: RCC internal clock sources calibration register 1
	// Position of MSICAL3 field.
	RCC_ICSCR1_MSICAL3_Pos = 0x0
	// Bit mask of MSICAL3 field.
	RCC_ICSCR1_MSICAL3_Msk = 0x1f
	// Position of MSICAL2 field.
	RCC_ICSCR1_MSICAL2_Pos = 0x5
	// Bit mask of MSICAL2 field.
	RCC_ICSCR1_MSICAL2_Msk = 0x3e0
	// Position of MSICAL1 field.
	RCC_ICSCR1_MSICAL1_Pos = 0xa
	// Bit mask of MSICAL1 field.
	RCC_ICSCR1_MSICAL1_Msk = 0x7c00
	// Position of MSICAL0 field.
	RCC_ICSCR1_MSICAL0_Pos = 0xf
	// Bit mask of MSICAL0 field.
	RCC_ICSCR1_MSICAL0_Msk = 0xf8000
	// Position of MSIBIAS field.
	RCC_ICSCR1_MSIBIAS_Pos = 0x16
	// Bit mask of MSIBIAS field.
	RCC_ICSCR1_MSIBIAS_Msk = 0x400000
	// Bit MSIBIAS.
	RCC_ICSCR1_MSIBIAS = 0x400000
	// MSI bias continuous mode (clock accuracy fast settling time)
	RCC_ICSCR1_MSIBIAS_Continuous = 0x0
	// MSI bias sampling mode when the regulator is in range 4, or when the device is in Stop 1 or Stop 2 (ultra-low-power mode)
	RCC_ICSCR1_MSIBIAS_Sampling = 0x1
	// Position of MSIRGSEL field.
	RCC_ICSCR1_MSIRGSEL_Pos = 0x17
	// Bit mask of MSIRGSEL field.
	RCC_ICSCR1_MSIRGSEL_Msk = 0x800000
	// Bit MSIRGSEL.
	RCC_ICSCR1_MSIRGSEL = 0x800000
	// MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR
	RCC_ICSCR1_MSIRGSEL_CSR = 0x0
	// MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1
	RCC_ICSCR1_MSIRGSEL_ICSCR1 = 0x1
	// Position of MSIKRANGE field.
	RCC_ICSCR1_MSIKRANGE_Pos = 0x18
	// Bit mask of MSIKRANGE field.
	RCC_ICSCR1_MSIKRANGE_Msk = 0xf000000
	// Range 0 around 48 MHz
	RCC_ICSCR1_MSIKRANGE_F_48MHZ = 0x0
	// Range 1 around 24 MHz
	RCC_ICSCR1_MSIKRANGE_F_24MHZ = 0x1
	// Range 2 around 16 MHz
	RCC_ICSCR1_MSIKRANGE_F_16MHZ = 0x2
	// Range 3 around 12 MHz
	RCC_ICSCR1_MSIKRANGE_F_12MHZ = 0x3
	// Range 4 around 4 MHz
	RCC_ICSCR1_MSIKRANGE_F_4MHZ = 0x4
	// Range 5 around 2 MHz
	RCC_ICSCR1_MSIKRANGE_F_2MHZ = 0x5
	// Range 6 around 1.33 MHz
	RCC_ICSCR1_MSIKRANGE_F_1_333MHZ = 0x6
	// Range 7 around 1 MHz
	RCC_ICSCR1_MSIKRANGE_F_1MHZ = 0x7
	// Range 8 around 3.072 MHz
	RCC_ICSCR1_MSIKRANGE_F_3_072MHZ = 0x8
	// Range 9 around 1.536 MHz
	RCC_ICSCR1_MSIKRANGE_F_1_536MHZ = 0x9
	// Range 10 around 1.024 MHz
	RCC_ICSCR1_MSIKRANGE_F_1_024MHZ = 0xa
	// Range 11 around 768 kHz
	RCC_ICSCR1_MSIKRANGE_F_768KHZ = 0xb
	// Range 12 around 400 kHz
	RCC_ICSCR1_MSIKRANGE_F_400KHZ = 0xc
	// Range 13 around 200 kHz
	RCC_ICSCR1_MSIKRANGE_F_200KHZ = 0xd
	// Range 14 around 133 kHz
	RCC_ICSCR1_MSIKRANGE_F_133KHZ = 0xe
	// Range 15 around 100 kHz
	RCC_ICSCR1_MSIKRANGE_F_100KHZ = 0xf
	// Position of MSISRANGE field.
	RCC_ICSCR1_MSISRANGE_Pos = 0x1c
	// Bit mask of MSISRANGE field.
	RCC_ICSCR1_MSISRANGE_Msk = 0xf0000000
	// Range 0 around 48 MHz
	RCC_ICSCR1_MSISRANGE_F_48MHZ = 0x0
	// Range 1 around 24 MHz
	RCC_ICSCR1_MSISRANGE_F_24MHZ = 0x1
	// Range 2 around 16 MHz
	RCC_ICSCR1_MSISRANGE_F_16MHZ = 0x2
	// Range 3 around 12 MHz
	RCC_ICSCR1_MSISRANGE_F_12MHZ = 0x3
	// Range 4 around 4 MHz
	RCC_ICSCR1_MSISRANGE_F_4MHZ = 0x4
	// Range 5 around 2 MHz
	RCC_ICSCR1_MSISRANGE_F_2MHZ = 0x5
	// Range 6 around 1.33 MHz
	RCC_ICSCR1_MSISRANGE_F_1_333MHZ = 0x6
	// Range 7 around 1 MHz
	RCC_ICSCR1_MSISRANGE_F_1MHZ = 0x7
	// Range 8 around 3.072 MHz
	RCC_ICSCR1_MSISRANGE_F_3_072MHZ = 0x8
	// Range 9 around 1.536 MHz
	RCC_ICSCR1_MSISRANGE_F_1_536MHZ = 0x9
	// Range 10 around 1.024 MHz
	RCC_ICSCR1_MSISRANGE_F_1_024MHZ = 0xa
	// Range 11 around 768 kHz
	RCC_ICSCR1_MSISRANGE_F_768KHZ = 0xb
	// Range 12 around 400 kHz
	RCC_ICSCR1_MSISRANGE_F_400KHZ = 0xc
	// Range 13 around 200 kHz
	RCC_ICSCR1_MSISRANGE_F_200KHZ = 0xd
	// Range 14 around 133 kHz
	RCC_ICSCR1_MSISRANGE_F_133KHZ = 0xe
	// Range 15 around 100 kHz
	RCC_ICSCR1_MSISRANGE_F_100KHZ = 0xf

	// ICSCR2: RCC internal clock sources calibration register 2
	// Position of MSITRIM3 field.
	RCC_ICSCR2_MSITRIM3_Pos = 0x0
	// Bit mask of MSITRIM3 field.
	RCC_ICSCR2_MSITRIM3_Msk = 0x1f
	// Position of MSITRIM2 field.
	RCC_ICSCR2_MSITRIM2_Pos = 0x5
	// Bit mask of MSITRIM2 field.
	RCC_ICSCR2_MSITRIM2_Msk = 0x3e0
	// Position of MSITRIM1 field.
	RCC_ICSCR2_MSITRIM1_Pos = 0xa
	// Bit mask of MSITRIM1 field.
	RCC_ICSCR2_MSITRIM1_Msk = 0x7c00
	// Position of MSITRIM0 field.
	RCC_ICSCR2_MSITRIM0_Pos = 0xf
	// Bit mask of MSITRIM0 field.
	RCC_ICSCR2_MSITRIM0_Msk = 0xf8000

	// ICSCR3: RCC internal clock sources calibration register 3
	// Position of HSICAL field.
	RCC_ICSCR3_HSICAL_Pos = 0x0
	// Bit mask of HSICAL field.
	RCC_ICSCR3_HSICAL_Msk = 0xfff
	// Position of HSITRIM field.
	RCC_ICSCR3_HSITRIM_Pos = 0x10
	// Bit mask of HSITRIM field.
	RCC_ICSCR3_HSITRIM_Msk = 0x1f0000

	// CRRCR: RCC clock recovery RC register
	// Position of HSI48CAL field.
	RCC_CRRCR_HSI48CAL_Pos = 0x0
	// Bit mask of HSI48CAL field.
	RCC_CRRCR_HSI48CAL_Msk = 0x1ff

	// CFGR1: RCC clock configuration register 1
	// Position of SW field.
	RCC_CFGR1_SW_Pos = 0x0
	// Bit mask of SW field.
	RCC_CFGR1_SW_Msk = 0x3
	// MSIS selected as system clock
	RCC_CFGR1_SW_MSIS = 0x0
	// HSI16 selected as system clock
	RCC_CFGR1_SW_HSI16 = 0x1
	// HSE selected as system clock
	RCC_CFGR1_SW_HSE = 0x2
	// PLL pll1_r_ck selected as system clock
	RCC_CFGR1_SW_PLL = 0x3
	// Position of SWS field.
	RCC_CFGR1_SWS_Pos = 0x2
	// Bit mask of SWS field.
	RCC_CFGR1_SWS_Msk = 0xc
	// MSIS oscillator used as system clock
	RCC_CFGR1_SWS_MSIS = 0x0
	// HSI16 oscillator used as system clock
	RCC_CFGR1_SWS_HSI16 = 0x1
	// HSE used as system clock
	RCC_CFGR1_SWS_HSE = 0x2
	// PLL pll1_r_ck used as system clock
	RCC_CFGR1_SWS_PLL = 0x3
	// Position of STOPWUCK field.
	RCC_CFGR1_STOPWUCK_Pos = 0x4
	// Bit mask of STOPWUCK field.
	RCC_CFGR1_STOPWUCK_Msk = 0x10
	// Bit STOPWUCK.
	RCC_CFGR1_STOPWUCK = 0x10
	// MSIS oscillator selected as wake-up from stop clock and CSS backup clock
	RCC_CFGR1_STOPWUCK_MSIS = 0x0
	// HSI16 oscillator selected as wake-up from stop clock and CSS backup clock
	RCC_CFGR1_STOPWUCK_HSI16 = 0x1
	// Position of STOPKERWUCK field.
	RCC_CFGR1_STOPKERWUCK_Pos = 0x5
	// Bit mask of STOPKERWUCK field.
	RCC_CFGR1_STOPKERWUCK_Msk = 0x20
	// Bit STOPKERWUCK.
	RCC_CFGR1_STOPKERWUCK = 0x20
	// MSIK oscillator automatically enabled when exiting Stop mode or when a CSS on HSE event occurs.
	RCC_CFGR1_STOPKERWUCK_MSIK = 0x0
	// HSI16 oscillator automatically enabled when exiting Stop mode or when a CSS on HSE event occurs.
	RCC_CFGR1_STOPKERWUCK_HSI16 = 0x1
	// Position of MCOSEL field.
	RCC_CFGR1_MCOSEL_Pos = 0x18
	// Bit mask of MCOSEL field.
	RCC_CFGR1_MCOSEL_Msk = 0xf000000
	// MCO output disabled, no clock on MCO
	RCC_CFGR1_MCOSEL_None = 0x0
	// SYSCLK system clock selected
	RCC_CFGR1_MCOSEL_SYSCLK = 0x1
	// MSIS clock selected
	RCC_CFGR1_MCOSEL_MSIS = 0x2
	// HSI16 clock selected
	RCC_CFGR1_MCOSEL_HSI16 = 0x3
	// HSE clock selected
	RCC_CFGR1_MCOSEL_HSE = 0x4
	// Main PLL clock pll1_r_ck selected
	RCC_CFGR1_MCOSEL_PLL = 0x5
	// LSI clock selected
	RCC_CFGR1_MCOSEL_LSI = 0x6
	// LSE clock selected
	RCC_CFGR1_MCOSEL_LSE = 0x7
	// Internal HSI48 clock selected
	RCC_CFGR1_MCOSEL_HSI48 = 0x8
	// MSIK clock selected
	RCC_CFGR1_MCOSEL_MSIK = 0x9
	// Position of MCOPRE field.
	RCC_CFGR1_MCOPRE_Pos = 0x1c
	// Bit mask of MCOPRE field.
	RCC_CFGR1_MCOPRE_Msk = 0x70000000
	// MCO divided by 1
	RCC_CFGR1_MCOPRE_Div1 = 0x0
	// MCO divided by 2
	RCC_CFGR1_MCOPRE_Div2 = 0x1
	// MCO divided by 4
	RCC_CFGR1_MCOPRE_Div4 = 0x2
	// MCO divided by 8
	RCC_CFGR1_MCOPRE_Div8 = 0x3
	// MCO divided by 16
	RCC_CFGR1_MCOPRE_Div16 = 0x4

	// CFGR2: RCC clock configuration register 2
	// Position of HPRE field.
	RCC_CFGR2_HPRE_Pos = 0x0
	// Bit mask of HPRE field.
	RCC_CFGR2_HPRE_Msk = 0xf
	// HCLK not divided
	RCC_CFGR2_HPRE_Div1 = 0x0
	// HCLK divided by 2
	RCC_CFGR2_HPRE_Div2 = 0x8
	// HCLK divided by 4
	RCC_CFGR2_HPRE_Div4 = 0x9
	// HCLK divided by 8
	RCC_CFGR2_HPRE_Div8 = 0xa
	// HCLK divided by 16
	RCC_CFGR2_HPRE_Div16 = 0xb
	// HCLK divided by 64
	RCC_CFGR2_HPRE_Div64 = 0xc
	// HCLK divided by 128
	RCC_CFGR2_HPRE_Div128 = 0xd
	// HCLK divided by 256
	RCC_CFGR2_HPRE_Div256 = 0xe
	// HCLK divided by 512
	RCC_CFGR2_HPRE_Div512 = 0xf
	// Position of PPRE1 field.
	RCC_CFGR2_PPRE1_Pos = 0x4
	// Bit mask of PPRE1 field.
	RCC_CFGR2_PPRE1_Msk = 0x70
	// PCLK not divided
	RCC_CFGR2_PPRE1_Div1 = 0x0
	// PCLK divided by 2
	RCC_CFGR2_PPRE1_Div2 = 0x4
	// PCLK divided by 4
	RCC_CFGR2_PPRE1_Div4 = 0x5
	// PCLK divided by 8
	RCC_CFGR2_PPRE1_Div8 = 0x6
	// PCLK divided by 16
	RCC_CFGR2_PPRE1_Div16 = 0x7
	// Position of PPRE2 field.
	RCC_CFGR2_PPRE2_Pos = 0x8
	// Bit mask of PPRE2 field.
	RCC_CFGR2_PPRE2_Msk = 0x700
	// PCLK not divided
	RCC_CFGR2_PPRE2_Div1 = 0x0
	// PCLK divided by 2
	RCC_CFGR2_PPRE2_Div2 = 0x4
	// PCLK divided by 4
	RCC_CFGR2_PPRE2_Div4 = 0x5
	// PCLK divided by 8
	RCC_CFGR2_PPRE2_Div8 = 0x6
	// PCLK divided by 16
	RCC_CFGR2_PPRE2_Div16 = 0x7
	// Position of DPRE field.
	RCC_CFGR2_DPRE_Pos = 0xc
	// Bit mask of DPRE field.
	RCC_CFGR2_DPRE_Msk = 0x7000
	// DCLK not divided
	RCC_CFGR2_DPRE_Div1 = 0x0
	// DCLK divided by 2
	RCC_CFGR2_DPRE_Div2 = 0x4
	// DCLK divided by 4
	RCC_CFGR2_DPRE_Div4 = 0x5
	// DCLK divided by 8
	RCC_CFGR2_DPRE_Div8 = 0x6
	// DCLK divided by 16
	RCC_CFGR2_DPRE_Div16 = 0x7
	// Position of AHB1DIS field.
	RCC_CFGR2_AHB1DIS_Pos = 0x10
	// Bit mask of AHB1DIS field.
	RCC_CFGR2_AHB1DIS_Msk = 0x10000
	// Bit AHB1DIS.
	RCC_CFGR2_AHB1DIS = 0x10000
	// AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
	RCC_CFGR2_AHB1DIS_Enabled = 0x0
	// AHB1 clock disabled
	RCC_CFGR2_AHB1DIS_Disabled = 0x1
	// Position of AHB2DIS1 field.
	RCC_CFGR2_AHB2DIS1_Pos = 0x11
	// Bit mask of AHB2DIS1 field.
	RCC_CFGR2_AHB2DIS1_Msk = 0x20000
	// Bit AHB2DIS1.
	RCC_CFGR2_AHB2DIS1 = 0x20000
	// AHB2_1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
	RCC_CFGR2_AHB2DIS1_Enabled = 0x0
	// AHB2_1 clock disabled
	RCC_CFGR2_AHB2DIS1_Disabled = 0x1
	// Position of AHB2DIS2 field.
	RCC_CFGR2_AHB2DIS2_Pos = 0x12
	// Bit mask of AHB2DIS2 field.
	RCC_CFGR2_AHB2DIS2_Msk = 0x40000
	// Bit AHB2DIS2.
	RCC_CFGR2_AHB2DIS2 = 0x40000
	// AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
	RCC_CFGR2_AHB2DIS2_Enabled = 0x0
	// AHB2_2 clock disabled
	RCC_CFGR2_AHB2DIS2_Disabled = 0x1
	// Position of APB1DIS field.
	RCC_CFGR2_APB1DIS_Pos = 0x13
	// Bit mask of APB1DIS field.
	RCC_CFGR2_APB1DIS_Msk = 0x80000
	// Bit APB1DIS.
	RCC_CFGR2_APB1DIS = 0x80000
	// APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
	RCC_CFGR2_APB1DIS_Enabled = 0x0
	// APB1 clock disabled
	RCC_CFGR2_APB1DIS_Disabled = 0x1
	// Position of APB2DIS field.
	RCC_CFGR2_APB2DIS_Pos = 0x14
	// Bit mask of APB2DIS field.
	RCC_CFGR2_APB2DIS_Msk = 0x100000
	// Bit APB2DIS.
	RCC_CFGR2_APB2DIS = 0x100000
	// APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
	RCC_CFGR2_APB2DIS_Enabled = 0x0
	// APB2 clock disabled
	RCC_CFGR2_APB2DIS_Disabled = 0x1

	// CFGR3: RCC clock configuration register 3
	// Position of PPRE3 field.
	RCC_CFGR3_PPRE3_Pos = 0x4
	// Bit mask of PPRE3 field.
	RCC_CFGR3_PPRE3_Msk = 0x70
	// PCLK not divided
	RCC_CFGR3_PPRE3_Div1 = 0x0
	// PCLK divided by 2
	RCC_CFGR3_PPRE3_Div2 = 0x4
	// PCLK divided by 4
	RCC_CFGR3_PPRE3_Div4 = 0x5
	// PCLK divided by 8
	RCC_CFGR3_PPRE3_Div8 = 0x6
	// PCLK divided by 16
	RCC_CFGR3_PPRE3_Div16 = 0x7
	// Position of AHB3DIS field.
	RCC_CFGR3_AHB3DIS_Pos = 0x10
	// Bit mask of AHB3DIS field.
	RCC_CFGR3_AHB3DIS_Msk = 0x10000
	// Bit AHB3DIS.
	RCC_CFGR3_AHB3DIS = 0x10000
	// AHB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
	RCC_CFGR3_AHB3DIS_Enabled = 0x0
	// AHB3 clock disabled
	RCC_CFGR3_AHB3DIS_Disabled = 0x1
	// Position of APB3DIS field.
	RCC_CFGR3_APB3DIS_Pos = 0x11
	// Bit mask of APB3DIS field.
	RCC_CFGR3_APB3DIS_Msk = 0x20000
	// Bit APB3DIS.
	RCC_CFGR3_APB3DIS = 0x20000
	// APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits
	RCC_CFGR3_APB3DIS_Enabled = 0x0
	// APB3 clock disabled
	RCC_CFGR3_APB3DIS_Disabled = 0x1

	// PLL1CFGR: RCC PLL1 configuration register
	// Position of PLL1SRC field.
	RCC_PLL1CFGR_PLL1SRC_Pos = 0x0
	// Bit mask of PLL1SRC field.
	RCC_PLL1CFGR_PLL1SRC_Msk = 0x3
	// No clock sent to PLLx
	RCC_PLL1CFGR_PLL1SRC_NoClock = 0x0
	// MSIS clock selected as PLLx clock entry
	RCC_PLL1CFGR_PLL1SRC_MSIS = 0x1
	// HSI16 clock selected as PLLx clock entry
	RCC_PLL1CFGR_PLL1SRC_HSI16 = 0x2
	// HSE clock selected as PLLx clock entry
	RCC_PLL1CFGR_PLL1SRC_HSE = 0x3
	// Position of PLL1RGE field.
	RCC_PLL1CFGR_PLL1RGE_Pos = 0x2
	// Bit mask of PLL1RGE field.
	RCC_PLL1CFGR_PLL1RGE_Msk = 0xc
	// PLLx input (refx_ck) clock range frequency between 4 and 8 MHz
	RCC_PLL1CFGR_PLL1RGE_Range1 = 0x0
	// PLLx input (refx_ck) clock range frequency between 8 and 16 MHz
	RCC_PLL1CFGR_PLL1RGE_Range2 = 0x3
	// Position of PLL1FRACEN field.
	RCC_PLL1CFGR_PLL1FRACEN_Pos = 0x4
	// Bit mask of PLL1FRACEN field.
	RCC_PLL1CFGR_PLL1FRACEN_Msk = 0x10
	// Bit PLL1FRACEN.
	RCC_PLL1CFGR_PLL1FRACEN = 0x10
	// No effect
	RCC_PLL1CFGR_PLL1FRACEN_NoEffect = 0x0
	// Content of PLLxFRACN latched in the Σ∆ modulator on PLLxFRACEN transition from 0 to 1
	RCC_PLL1CFGR_PLL1FRACEN_Latch = 0x1
	// Position of PLL1M field.
	RCC_PLL1CFGR_PLL1M_Pos = 0x8
	// Bit mask of PLL1M field.
	RCC_PLL1CFGR_PLL1M_Msk = 0xf00
	// division by 1 (bypass)
	RCC_PLL1CFGR_PLL1M_Div1 = 0x0
	// division by 2
	RCC_PLL1CFGR_PLL1M_Div2 = 0x1
	// division by 3
	RCC_PLL1CFGR_PLL1M_Div3 = 0x2
	// division by 4
	RCC_PLL1CFGR_PLL1M_Div4 = 0x3
	// division by 5
	RCC_PLL1CFGR_PLL1M_Div5 = 0x4
	// division by 6
	RCC_PLL1CFGR_PLL1M_Div6 = 0x5
	// division by 7
	RCC_PLL1CFGR_PLL1M_Div7 = 0x6
	// division by 8
	RCC_PLL1CFGR_PLL1M_Div8 = 0x7
	// division by 9
	RCC_PLL1CFGR_PLL1M_Div9 = 0x8
	// division by 10
	RCC_PLL1CFGR_PLL1M_Div10 = 0x9
	// division by 11
	RCC_PLL1CFGR_PLL1M_Div11 = 0xa
	// division by 12
	RCC_PLL1CFGR_PLL1M_Div12 = 0xb
	// division by 13
	RCC_PLL1CFGR_PLL1M_Div13 = 0xc
	// division by 14
	RCC_PLL1CFGR_PLL1M_Div14 = 0xd
	// division by 15
	RCC_PLL1CFGR_PLL1M_Div15 = 0xe
	// division by 16
	RCC_PLL1CFGR_PLL1M_Div16 = 0xf
	// Position of PLL1MBOOST field.
	RCC_PLL1CFGR_PLL1MBOOST_Pos = 0xc
	// Bit mask of PLL1MBOOST field.
	RCC_PLL1CFGR_PLL1MBOOST_Msk = 0xf000
	// division by 1 (bypass)
	RCC_PLL1CFGR_PLL1MBOOST_Div1 = 0x0
	// division by 2
	RCC_PLL1CFGR_PLL1MBOOST_Div2 = 0x1
	// division by 4
	RCC_PLL1CFGR_PLL1MBOOST_Div4 = 0x2
	// division by 6
	RCC_PLL1CFGR_PLL1MBOOST_Div6 = 0x3
	// division by 8
	RCC_PLL1CFGR_PLL1MBOOST_Div8 = 0x4
	// division by 10
	RCC_PLL1CFGR_PLL1MBOOST_Div10 = 0x5
	// division by 12
	RCC_PLL1CFGR_PLL1MBOOST_Div12 = 0x6
	// division by 14
	RCC_PLL1CFGR_PLL1MBOOST_Div14 = 0x7
	// division by 16
	RCC_PLL1CFGR_PLL1MBOOST_Div16 = 0x8
	// Position of PLL1PEN field.
	RCC_PLL1CFGR_PLL1PEN_Pos = 0x10
	// Bit mask of PLL1PEN field.
	RCC_PLL1CFGR_PLL1PEN_Msk = 0x10000
	// Bit PLL1PEN.
	RCC_PLL1CFGR_PLL1PEN = 0x10000
	// pllx_p_ck output disabled
	RCC_PLL1CFGR_PLL1PEN_Disabled = 0x0
	// pllx_p_ck output enabled
	RCC_PLL1CFGR_PLL1PEN_Enabled = 0x1
	// Position of PLL1QEN field.
	RCC_PLL1CFGR_PLL1QEN_Pos = 0x11
	// Bit mask of PLL1QEN field.
	RCC_PLL1CFGR_PLL1QEN_Msk = 0x20000
	// Bit PLL1QEN.
	RCC_PLL1CFGR_PLL1QEN = 0x20000
	// pllx_q_ck output disabled
	RCC_PLL1CFGR_PLL1QEN_Disabled = 0x0
	// pllx_q_ck output enabled
	RCC_PLL1CFGR_PLL1QEN_Enabled = 0x1
	// Position of PLL1REN field.
	RCC_PLL1CFGR_PLL1REN_Pos = 0x12
	// Bit mask of PLL1REN field.
	RCC_PLL1CFGR_PLL1REN_Msk = 0x40000
	// Bit PLL1REN.
	RCC_PLL1CFGR_PLL1REN = 0x40000
	// pllx_r_ck ready interrupt disabled
	RCC_PLL1CFGR_PLL1REN_Disabled = 0x0
	// pllx_r_ck ready interrupt enabled
	RCC_PLL1CFGR_PLL1REN_Enabled = 0x1

	// PLL2CFGR: RCC PLL2 configuration register
	// Position of PLL2SRC field.
	RCC_PLL2CFGR_PLL2SRC_Pos = 0x0
	// Bit mask of PLL2SRC field.
	RCC_PLL2CFGR_PLL2SRC_Msk = 0x3
	// No clock sent to PLLx
	RCC_PLL2CFGR_PLL2SRC_NoClock = 0x0
	// MSIS clock selected as PLLx clock entry
	RCC_PLL2CFGR_PLL2SRC_MSIS = 0x1
	// HSI16 clock selected as PLLx clock entry
	RCC_PLL2CFGR_PLL2SRC_HSI16 = 0x2
	// HSE clock selected as PLLx clock entry
	RCC_PLL2CFGR_PLL2SRC_HSE = 0x3
	// Position of PLL2RGE field.
	RCC_PLL2CFGR_PLL2RGE_Pos = 0x2
	// Bit mask of PLL2RGE field.
	RCC_PLL2CFGR_PLL2RGE_Msk = 0xc
	// PLLx input (refx_ck) clock range frequency between 4 and 8 MHz
	RCC_PLL2CFGR_PLL2RGE_Range1 = 0x0
	// PLLx input (refx_ck) clock range frequency between 8 and 16 MHz
	RCC_PLL2CFGR_PLL2RGE_Range2 = 0x3
	// Position of PLL2FRACEN field.
	RCC_PLL2CFGR_PLL2FRACEN_Pos = 0x4
	// Bit mask of PLL2FRACEN field.
	RCC_PLL2CFGR_PLL2FRACEN_Msk = 0x10
	// Bit PLL2FRACEN.
	RCC_PLL2CFGR_PLL2FRACEN = 0x10
	// No effect
	RCC_PLL2CFGR_PLL2FRACEN_NoEffect = 0x0
	// Content of PLLxFRACN latched in the Σ∆ modulator on PLLxFRACEN transition from 0 to 1
	RCC_PLL2CFGR_PLL2FRACEN_Latch = 0x1
	// Position of PLL2M field.
	RCC_PLL2CFGR_PLL2M_Pos = 0x8
	// Bit mask of PLL2M field.
	RCC_PLL2CFGR_PLL2M_Msk = 0xf00
	// division by 1 (bypass)
	RCC_PLL2CFGR_PLL2M_Div1 = 0x0
	// division by 2
	RCC_PLL2CFGR_PLL2M_Div2 = 0x1
	// division by 3
	RCC_PLL2CFGR_PLL2M_Div3 = 0x2
	// division by 4
	RCC_PLL2CFGR_PLL2M_Div4 = 0x3
	// division by 5
	RCC_PLL2CFGR_PLL2M_Div5 = 0x4
	// division by 6
	RCC_PLL2CFGR_PLL2M_Div6 = 0x5
	// division by 7
	RCC_PLL2CFGR_PLL2M_Div7 = 0x6
	// division by 8
	RCC_PLL2CFGR_PLL2M_Div8 = 0x7
	// division by 9
	RCC_PLL2CFGR_PLL2M_Div9 = 0x8
	// division by 10
	RCC_PLL2CFGR_PLL2M_Div10 = 0x9
	// division by 11
	RCC_PLL2CFGR_PLL2M_Div11 = 0xa
	// division by 12
	RCC_PLL2CFGR_PLL2M_Div12 = 0xb
	// division by 13
	RCC_PLL2CFGR_PLL2M_Div13 = 0xc
	// division by 14
	RCC_PLL2CFGR_PLL2M_Div14 = 0xd
	// division by 15
	RCC_PLL2CFGR_PLL2M_Div15 = 0xe
	// division by 16
	RCC_PLL2CFGR_PLL2M_Div16 = 0xf
	// Position of PLL2PEN field.
	RCC_PLL2CFGR_PLL2PEN_Pos = 0x10
	// Bit mask of PLL2PEN field.
	RCC_PLL2CFGR_PLL2PEN_Msk = 0x10000
	// Bit PLL2PEN.
	RCC_PLL2CFGR_PLL2PEN = 0x10000
	// pllx_p_ck output disabled
	RCC_PLL2CFGR_PLL2PEN_Disabled = 0x0
	// pllx_p_ck output enabled
	RCC_PLL2CFGR_PLL2PEN_Enabled = 0x1
	// Position of PLL2QEN field.
	RCC_PLL2CFGR_PLL2QEN_Pos = 0x11
	// Bit mask of PLL2QEN field.
	RCC_PLL2CFGR_PLL2QEN_Msk = 0x20000
	// Bit PLL2QEN.
	RCC_PLL2CFGR_PLL2QEN = 0x20000
	// pllx_q_ck output disabled
	RCC_PLL2CFGR_PLL2QEN_Disabled = 0x0
	// pllx_q_ck output enabled
	RCC_PLL2CFGR_PLL2QEN_Enabled = 0x1
	// Position of PLL2REN field.
	RCC_PLL2CFGR_PLL2REN_Pos = 0x12
	// Bit mask of PLL2REN field.
	RCC_PLL2CFGR_PLL2REN_Msk = 0x40000
	// Bit PLL2REN.
	RCC_PLL2CFGR_PLL2REN = 0x40000
	// pllx_r_ck ready interrupt disabled
	RCC_PLL2CFGR_PLL2REN_Disabled = 0x0
	// pllx_r_ck ready interrupt enabled
	RCC_PLL2CFGR_PLL2REN_Enabled = 0x1

	// PLL3CFGR: RCC PLL3 configuration register
	// Position of PLL3SRC field.
	RCC_PLL3CFGR_PLL3SRC_Pos = 0x0
	// Bit mask of PLL3SRC field.
	RCC_PLL3CFGR_PLL3SRC_Msk = 0x3
	// No clock sent to PLLx
	RCC_PLL3CFGR_PLL3SRC_NoClock = 0x0
	// MSIS clock selected as PLLx clock entry
	RCC_PLL3CFGR_PLL3SRC_MSIS = 0x1
	// HSI16 clock selected as PLLx clock entry
	RCC_PLL3CFGR_PLL3SRC_HSI16 = 0x2
	// HSE clock selected as PLLx clock entry
	RCC_PLL3CFGR_PLL3SRC_HSE = 0x3
	// Position of PLL3RGE field.
	RCC_PLL3CFGR_PLL3RGE_Pos = 0x2
	// Bit mask of PLL3RGE field.
	RCC_PLL3CFGR_PLL3RGE_Msk = 0xc
	// PLLx input (refx_ck) clock range frequency between 4 and 8 MHz
	RCC_PLL3CFGR_PLL3RGE_Range1 = 0x0
	// PLLx input (refx_ck) clock range frequency between 8 and 16 MHz
	RCC_PLL3CFGR_PLL3RGE_Range2 = 0x3
	// Position of PLL3FRACEN field.
	RCC_PLL3CFGR_PLL3FRACEN_Pos = 0x4
	// Bit mask of PLL3FRACEN field.
	RCC_PLL3CFGR_PLL3FRACEN_Msk = 0x10
	// Bit PLL3FRACEN.
	RCC_PLL3CFGR_PLL3FRACEN = 0x10
	// No effect
	RCC_PLL3CFGR_PLL3FRACEN_NoEffect = 0x0
	// Content of PLLxFRACN latched in the Σ∆ modulator on PLLxFRACEN transition from 0 to 1
	RCC_PLL3CFGR_PLL3FRACEN_Latch = 0x1
	// Position of PLL3M field.
	RCC_PLL3CFGR_PLL3M_Pos = 0x8
	// Bit mask of PLL3M field.
	RCC_PLL3CFGR_PLL3M_Msk = 0xf00
	// division by 1 (bypass)
	RCC_PLL3CFGR_PLL3M_Div1 = 0x0
	// division by 2
	RCC_PLL3CFGR_PLL3M_Div2 = 0x1
	// division by 3
	RCC_PLL3CFGR_PLL3M_Div3 = 0x2
	// division by 4
	RCC_PLL3CFGR_PLL3M_Div4 = 0x3
	// division by 5
	RCC_PLL3CFGR_PLL3M_Div5 = 0x4
	// division by 6
	RCC_PLL3CFGR_PLL3M_Div6 = 0x5
	// division by 7
	RCC_PLL3CFGR_PLL3M_Div7 = 0x6
	// division by 8
	RCC_PLL3CFGR_PLL3M_Div8 = 0x7
	// division by 9
	RCC_PLL3CFGR_PLL3M_Div9 = 0x8
	// division by 10
	RCC_PLL3CFGR_PLL3M_Div10 = 0x9
	// division by 11
	RCC_PLL3CFGR_PLL3M_Div11 = 0xa
	// division by 12
	RCC_PLL3CFGR_PLL3M_Div12 = 0xb
	// division by 13
	RCC_PLL3CFGR_PLL3M_Div13 = 0xc
	// division by 14
	RCC_PLL3CFGR_PLL3M_Div14 = 0xd
	// division by 15
	RCC_PLL3CFGR_PLL3M_Div15 = 0xe
	// division by 16
	RCC_PLL3CFGR_PLL3M_Div16 = 0xf
	// Position of PLL3PEN field.
	RCC_PLL3CFGR_PLL3PEN_Pos = 0x10
	// Bit mask of PLL3PEN field.
	RCC_PLL3CFGR_PLL3PEN_Msk = 0x10000
	// Bit PLL3PEN.
	RCC_PLL3CFGR_PLL3PEN = 0x10000
	// pllx_p_ck output disabled
	RCC_PLL3CFGR_PLL3PEN_Disabled = 0x0
	// pllx_p_ck output enabled
	RCC_PLL3CFGR_PLL3PEN_Enabled = 0x1
	// Position of PLL3QEN field.
	RCC_PLL3CFGR_PLL3QEN_Pos = 0x11
	// Bit mask of PLL3QEN field.
	RCC_PLL3CFGR_PLL3QEN_Msk = 0x20000
	// Bit PLL3QEN.
	RCC_PLL3CFGR_PLL3QEN = 0x20000
	// pllx_q_ck output disabled
	RCC_PLL3CFGR_PLL3QEN_Disabled = 0x0
	// pllx_q_ck output enabled
	RCC_PLL3CFGR_PLL3QEN_Enabled = 0x1
	// Position of PLL3REN field.
	RCC_PLL3CFGR_PLL3REN_Pos = 0x12
	// Bit mask of PLL3REN field.
	RCC_PLL3CFGR_PLL3REN_Msk = 0x40000
	// Bit PLL3REN.
	RCC_PLL3CFGR_PLL3REN = 0x40000
	// pllx_r_ck ready interrupt disabled
	RCC_PLL3CFGR_PLL3REN_Disabled = 0x0
	// pllx_r_ck ready interrupt enabled
	RCC_PLL3CFGR_PLL3REN_Enabled = 0x1

	// PLL1DIVR: RCC PLL1 dividers register
	// Position of PLL1N field.
	RCC_PLL1DIVR_PLL1N_Pos = 0x0
	// Bit mask of PLL1N field.
	RCC_PLL1DIVR_PLL1N_Msk = 0x1ff
	// Position of PLL1P field.
	RCC_PLL1DIVR_PLL1P_Pos = 0x9
	// Bit mask of PLL1P field.
	RCC_PLL1DIVR_PLL1P_Msk = 0xfe00
	// pllx_p_ck = vcox_ck
	RCC_PLL1DIVR_PLL1P_Div1 = 0x0
	// pllx_p_ck = vcox_ck / 2
	RCC_PLL1DIVR_PLL1P_Div2 = 0x1
	// pllx_p_ck = vcox_ck / 4
	RCC_PLL1DIVR_PLL1P_Div4 = 0x3
	// pllx_p_ck = vcox_ck / 6
	RCC_PLL1DIVR_PLL1P_Div6 = 0x5
	// pllx_p_ck = vcox_ck / 8
	RCC_PLL1DIVR_PLL1P_Div8 = 0x7
	// pllx_p_ck = vcox_ck / 10
	RCC_PLL1DIVR_PLL1P_Div10 = 0x9
	// pllx_p_ck = vcox_ck / 12
	RCC_PLL1DIVR_PLL1P_Div12 = 0xb
	// pllx_p_ck = vcox_ck / 14
	RCC_PLL1DIVR_PLL1P_Div14 = 0xd
	// pllx_p_ck = vcox_ck / 16
	RCC_PLL1DIVR_PLL1P_Div16 = 0xf
	// pllx_p_ck = vcox_ck / 18
	RCC_PLL1DIVR_PLL1P_Div18 = 0x11
	// pllx_p_ck = vcox_ck / 20
	RCC_PLL1DIVR_PLL1P_Div20 = 0x13
	// pllx_p_ck = vcox_ck / 22
	RCC_PLL1DIVR_PLL1P_Div22 = 0x15
	// pllx_p_ck = vcox_ck / 24
	RCC_PLL1DIVR_PLL1P_Div24 = 0x17
	// pllx_p_ck = vcox_ck / 26
	RCC_PLL1DIVR_PLL1P_Div26 = 0x19
	// pllx_p_ck = vcox_ck / 28
	RCC_PLL1DIVR_PLL1P_Div28 = 0x1b
	// pllx_p_ck = vcox_ck / 30
	RCC_PLL1DIVR_PLL1P_Div30 = 0x1d
	// pllx_p_ck = vcox_ck / 32
	RCC_PLL1DIVR_PLL1P_Div32 = 0x1f
	// pllx_p_ck = vcox_ck / 34
	RCC_PLL1DIVR_PLL1P_Div34 = 0x21
	// pllx_p_ck = vcox_ck / 36
	RCC_PLL1DIVR_PLL1P_Div36 = 0x23
	// pllx_p_ck = vcox_ck / 38
	RCC_PLL1DIVR_PLL1P_Div38 = 0x25
	// pllx_p_ck = vcox_ck / 40
	RCC_PLL1DIVR_PLL1P_Div40 = 0x27
	// pllx_p_ck = vcox_ck / 42
	RCC_PLL1DIVR_PLL1P_Div42 = 0x29
	// pllx_p_ck = vcox_ck / 44
	RCC_PLL1DIVR_PLL1P_Div44 = 0x2b
	// pllx_p_ck = vcox_ck / 46
	RCC_PLL1DIVR_PLL1P_Div46 = 0x2d
	// pllx_p_ck = vcox_ck / 48
	RCC_PLL1DIVR_PLL1P_Div48 = 0x2f
	// pllx_p_ck = vcox_ck / 50
	RCC_PLL1DIVR_PLL1P_Div50 = 0x31
	// pllx_p_ck = vcox_ck / 52
	RCC_PLL1DIVR_PLL1P_Div52 = 0x33
	// pllx_p_ck = vcox_ck / 54
	RCC_PLL1DIVR_PLL1P_Div54 = 0x35
	// pllx_p_ck = vcox_ck / 56
	RCC_PLL1DIVR_PLL1P_Div56 = 0x37
	// pllx_p_ck = vcox_ck / 58
	RCC_PLL1DIVR_PLL1P_Div58 = 0x39
	// pllx_p_ck = vcox_ck / 60
	RCC_PLL1DIVR_PLL1P_Div60 = 0x3b
	// pllx_p_ck = vcox_ck / 62
	RCC_PLL1DIVR_PLL1P_Div62 = 0x3d
	// pllx_p_ck = vcox_ck / 64
	RCC_PLL1DIVR_PLL1P_Div64 = 0x3f
	// pllx_p_ck = vcox_ck / 66
	RCC_PLL1DIVR_PLL1P_Div66 = 0x41
	// pllx_p_ck = vcox_ck / 68
	RCC_PLL1DIVR_PLL1P_Div68 = 0x43
	// pllx_p_ck = vcox_ck / 70
	RCC_PLL1DIVR_PLL1P_Div70 = 0x45
	// pllx_p_ck = vcox_ck / 72
	RCC_PLL1DIVR_PLL1P_Div72 = 0x47
	// pllx_p_ck = vcox_ck / 74
	RCC_PLL1DIVR_PLL1P_Div74 = 0x49
	// pllx_p_ck = vcox_ck / 76
	RCC_PLL1DIVR_PLL1P_Div76 = 0x4b
	// pllx_p_ck = vcox_ck / 78
	RCC_PLL1DIVR_PLL1P_Div78 = 0x4d
	// pllx_p_ck = vcox_ck / 80
	RCC_PLL1DIVR_PLL1P_Div80 = 0x4f
	// pllx_p_ck = vcox_ck / 82
	RCC_PLL1DIVR_PLL1P_Div82 = 0x51
	// pllx_p_ck = vcox_ck / 84
	RCC_PLL1DIVR_PLL1P_Div84 = 0x53
	// pllx_p_ck = vcox_ck / 86
	RCC_PLL1DIVR_PLL1P_Div86 = 0x55
	// pllx_p_ck = vcox_ck / 88
	RCC_PLL1DIVR_PLL1P_Div88 = 0x57
	// pllx_p_ck = vcox_ck / 90
	RCC_PLL1DIVR_PLL1P_Div90 = 0x59
	// pllx_p_ck = vcox_ck / 92
	RCC_PLL1DIVR_PLL1P_Div92 = 0x5b
	// pllx_p_ck = vcox_ck / 94
	RCC_PLL1DIVR_PLL1P_Div94 = 0x5d
	// pllx_p_ck = vcox_ck / 96
	RCC_PLL1DIVR_PLL1P_Div96 = 0x5f
	// pllx_p_ck = vcox_ck / 98
	RCC_PLL1DIVR_PLL1P_Div98 = 0x61
	// pllx_p_ck = vcox_ck / 100
	RCC_PLL1DIVR_PLL1P_Div100 = 0x63
	// pllx_p_ck = vcox_ck / 102
	RCC_PLL1DIVR_PLL1P_Div102 = 0x65
	// pllx_p_ck = vcox_ck / 104
	RCC_PLL1DIVR_PLL1P_Div104 = 0x67
	// pllx_p_ck = vcox_ck / 106
	RCC_PLL1DIVR_PLL1P_Div106 = 0x69
	// pllx_p_ck = vcox_ck / 108
	RCC_PLL1DIVR_PLL1P_Div108 = 0x6b
	// pllx_p_ck = vcox_ck / 110
	RCC_PLL1DIVR_PLL1P_Div110 = 0x6d
	// pllx_p_ck = vcox_ck / 112
	RCC_PLL1DIVR_PLL1P_Div112 = 0x6f
	// pllx_p_ck = vcox_ck / 114
	RCC_PLL1DIVR_PLL1P_Div114 = 0x71
	// pllx_p_ck = vcox_ck / 116
	RCC_PLL1DIVR_PLL1P_Div116 = 0x73
	// pllx_p_ck = vcox_ck / 118
	RCC_PLL1DIVR_PLL1P_Div118 = 0x75
	// pllx_p_ck = vcox_ck / 120
	RCC_PLL1DIVR_PLL1P_Div120 = 0x77
	// pllx_p_ck = vcox_ck / 122
	RCC_PLL1DIVR_PLL1P_Div122 = 0x79
	// pllx_p_ck = vcox_ck / 124
	RCC_PLL1DIVR_PLL1P_Div124 = 0x7b
	// pllx_p_ck = vcox_ck / 126
	RCC_PLL1DIVR_PLL1P_Div126 = 0x7d
	// pllx_p_ck = vcox_ck / 128
	RCC_PLL1DIVR_PLL1P_Div128 = 0x7f
	// Position of PLL1Q field.
	RCC_PLL1DIVR_PLL1Q_Pos = 0x10
	// Bit mask of PLL1Q field.
	RCC_PLL1DIVR_PLL1Q_Msk = 0x7f0000
	// pllx_q_ck = vcox_ck
	RCC_PLL1DIVR_PLL1Q_Div1 = 0x0
	// pllx_q_ck = vcox_ck / 2
	RCC_PLL1DIVR_PLL1Q_Div2 = 0x1
	// pllx_q_ck = vcox_ck / 4
	RCC_PLL1DIVR_PLL1Q_Div4 = 0x3
	// pllx_q_ck = vcox_ck / 6
	RCC_PLL1DIVR_PLL1Q_Div6 = 0x5
	// pllx_q_ck = vcox_ck / 8
	RCC_PLL1DIVR_PLL1Q_Div8 = 0x7
	// pllx_q_ck = vcox_ck / 10
	RCC_PLL1DIVR_PLL1Q_Div10 = 0x9
	// pllx_q_ck = vcox_ck / 12
	RCC_PLL1DIVR_PLL1Q_Div12 = 0xb
	// pllx_q_ck = vcox_ck / 14
	RCC_PLL1DIVR_PLL1Q_Div14 = 0xd
	// pllx_q_ck = vcox_ck / 16
	RCC_PLL1DIVR_PLL1Q_Div16 = 0xf
	// pllx_q_ck = vcox_ck / 18
	RCC_PLL1DIVR_PLL1Q_Div18 = 0x11
	// pllx_q_ck = vcox_ck / 20
	RCC_PLL1DIVR_PLL1Q_Div20 = 0x13
	// pllx_q_ck = vcox_ck / 22
	RCC_PLL1DIVR_PLL1Q_Div22 = 0x15
	// pllx_q_ck = vcox_ck / 24
	RCC_PLL1DIVR_PLL1Q_Div24 = 0x17
	// pllx_q_ck = vcox_ck / 26
	RCC_PLL1DIVR_PLL1Q_Div26 = 0x19
	// pllx_q_ck = vcox_ck / 28
	RCC_PLL1DIVR_PLL1Q_Div28 = 0x1b
	// pllx_q_ck = vcox_ck / 30
	RCC_PLL1DIVR_PLL1Q_Div30 = 0x1d
	// pllx_q_ck = vcox_ck / 32
	RCC_PLL1DIVR_PLL1Q_Div32 = 0x1f
	// pllx_q_ck = vcox_ck / 34
	RCC_PLL1DIVR_PLL1Q_Div34 = 0x21
	// pllx_q_ck = vcox_ck / 36
	RCC_PLL1DIVR_PLL1Q_Div36 = 0x23
	// pllx_q_ck = vcox_ck / 38
	RCC_PLL1DIVR_PLL1Q_Div38 = 0x25
	// pllx_q_ck = vcox_ck / 40
	RCC_PLL1DIVR_PLL1Q_Div40 = 0x27
	// pllx_q_ck = vcox_ck / 42
	RCC_PLL1DIVR_PLL1Q_Div42 = 0x29
	// pllx_q_ck = vcox_ck / 44
	RCC_PLL1DIVR_PLL1Q_Div44 = 0x2b
	// pllx_q_ck = vcox_ck / 46
	RCC_PLL1DIVR_PLL1Q_Div46 = 0x2d
	// pllx_q_ck = vcox_ck / 48
	RCC_PLL1DIVR_PLL1Q_Div48 = 0x2f
	// pllx_q_ck = vcox_ck / 50
	RCC_PLL1DIVR_PLL1Q_Div50 = 0x31
	// pllx_q_ck = vcox_ck / 52
	RCC_PLL1DIVR_PLL1Q_Div52 = 0x33
	// pllx_q_ck = vcox_ck / 54
	RCC_PLL1DIVR_PLL1Q_Div54 = 0x35
	// pllx_q_ck = vcox_ck / 56
	RCC_PLL1DIVR_PLL1Q_Div56 = 0x37
	// pllx_q_ck = vcox_ck / 58
	RCC_PLL1DIVR_PLL1Q_Div58 = 0x39
	// pllx_q_ck = vcox_ck / 60
	RCC_PLL1DIVR_PLL1Q_Div60 = 0x3b
	// pllx_q_ck = vcox_ck / 62
	RCC_PLL1DIVR_PLL1Q_Div62 = 0x3d
	// pllx_q_ck = vcox_ck / 64
	RCC_PLL1DIVR_PLL1Q_Div64 = 0x3f
	// pllx_q_ck = vcox_ck / 66
	RCC_PLL1DIVR_PLL1Q_Div66 = 0x41
	// pllx_q_ck = vcox_ck / 68
	RCC_PLL1DIVR_PLL1Q_Div68 = 0x43
	// pllx_q_ck = vcox_ck / 70
	RCC_PLL1DIVR_PLL1Q_Div70 = 0x45
	// pllx_q_ck = vcox_ck / 72
	RCC_PLL1DIVR_PLL1Q_Div72 = 0x47
	// pllx_q_ck = vcox_ck / 74
	RCC_PLL1DIVR_PLL1Q_Div74 = 0x49
	// pllx_q_ck = vcox_ck / 76
	RCC_PLL1DIVR_PLL1Q_Div76 = 0x4b
	// pllx_q_ck = vcox_ck / 78
	RCC_PLL1DIVR_PLL1Q_Div78 = 0x4d
	// pllx_q_ck = vcox_ck / 80
	RCC_PLL1DIVR_PLL1Q_Div80 = 0x4f
	// pllx_q_ck = vcox_ck / 82
	RCC_PLL1DIVR_PLL1Q_Div82 = 0x51
	// pllx_q_ck = vcox_ck / 84
	RCC_PLL1DIVR_PLL1Q_Div84 = 0x53
	// pllx_q_ck = vcox_ck / 86
	RCC_PLL1DIVR_PLL1Q_Div86 = 0x55
	// pllx_q_ck = vcox_ck / 88
	RCC_PLL1DIVR_PLL1Q_Div88 = 0x57
	// pllx_q_ck = vcox_ck / 90
	RCC_PLL1DIVR_PLL1Q_Div90 = 0x59
	// pllx_q_ck = vcox_ck / 92
	RCC_PLL1DIVR_PLL1Q_Div92 = 0x5b
	// pllx_q_ck = vcox_ck / 94
	RCC_PLL1DIVR_PLL1Q_Div94 = 0x5d
	// pllx_q_ck = vcox_ck / 96
	RCC_PLL1DIVR_PLL1Q_Div96 = 0x5f
	// pllx_q_ck = vcox_ck / 98
	RCC_PLL1DIVR_PLL1Q_Div98 = 0x61
	// pllx_q_ck = vcox_ck / 100
	RCC_PLL1DIVR_PLL1Q_Div100 = 0x63
	// pllx_q_ck = vcox_ck / 102
	RCC_PLL1DIVR_PLL1Q_Div102 = 0x65
	// pllx_q_ck = vcox_ck / 104
	RCC_PLL1DIVR_PLL1Q_Div104 = 0x67
	// pllx_q_ck = vcox_ck / 106
	RCC_PLL1DIVR_PLL1Q_Div106 = 0x69
	// pllx_q_ck = vcox_ck / 108
	RCC_PLL1DIVR_PLL1Q_Div108 = 0x6b
	// pllx_q_ck = vcox_ck / 110
	RCC_PLL1DIVR_PLL1Q_Div110 = 0x6d
	// pllx_q_ck = vcox_ck / 112
	RCC_PLL1DIVR_PLL1Q_Div112 = 0x6f
	// pllx_q_ck = vcox_ck / 114
	RCC_PLL1DIVR_PLL1Q_Div114 = 0x71
	// pllx_q_ck = vcox_ck / 116
	RCC_PLL1DIVR_PLL1Q_Div116 = 0x73
	// pllx_q_ck = vcox_ck / 118
	RCC_PLL1DIVR_PLL1Q_Div118 = 0x75
	// pllx_q_ck = vcox_ck / 120
	RCC_PLL1DIVR_PLL1Q_Div120 = 0x77
	// pllx_q_ck = vcox_ck / 122
	RCC_PLL1DIVR_PLL1Q_Div122 = 0x79
	// pllx_q_ck = vcox_ck / 124
	RCC_PLL1DIVR_PLL1Q_Div124 = 0x7b
	// pllx_q_ck = vcox_ck / 126
	RCC_PLL1DIVR_PLL1Q_Div126 = 0x7d
	// pllx_q_ck = vcox_ck / 128
	RCC_PLL1DIVR_PLL1Q_Div128 = 0x7f
	// Position of PLL1R field.
	RCC_PLL1DIVR_PLL1R_Pos = 0x18
	// Bit mask of PLL1R field.
	RCC_PLL1DIVR_PLL1R_Msk = 0x7f000000
	// pllx_r_ck = vcox_ck
	RCC_PLL1DIVR_PLL1R_Div1 = 0x0
	// pllx_r_ck = vcox_ck / 2
	RCC_PLL1DIVR_PLL1R_Div2 = 0x1
	// pllx_r_ck = vcox_ck / 4
	RCC_PLL1DIVR_PLL1R_Div4 = 0x3
	// pllx_r_ck = vcox_ck / 6
	RCC_PLL1DIVR_PLL1R_Div6 = 0x5
	// pllx_r_ck = vcox_ck / 8
	RCC_PLL1DIVR_PLL1R_Div8 = 0x7
	// pllx_r_ck = vcox_ck / 10
	RCC_PLL1DIVR_PLL1R_Div10 = 0x9
	// pllx_r_ck = vcox_ck / 12
	RCC_PLL1DIVR_PLL1R_Div12 = 0xb
	// pllx_r_ck = vcox_ck / 14
	RCC_PLL1DIVR_PLL1R_Div14 = 0xd
	// pllx_r_ck = vcox_ck / 16
	RCC_PLL1DIVR_PLL1R_Div16 = 0xf
	// pllx_r_ck = vcox_ck / 18
	RCC_PLL1DIVR_PLL1R_Div18 = 0x11
	// pllx_r_ck = vcox_ck / 20
	RCC_PLL1DIVR_PLL1R_Div20 = 0x13
	// pllx_r_ck = vcox_ck / 22
	RCC_PLL1DIVR_PLL1R_Div22 = 0x15
	// pllx_r_ck = vcox_ck / 24
	RCC_PLL1DIVR_PLL1R_Div24 = 0x17
	// pllx_r_ck = vcox_ck / 26
	RCC_PLL1DIVR_PLL1R_Div26 = 0x19
	// pllx_r_ck = vcox_ck / 28
	RCC_PLL1DIVR_PLL1R_Div28 = 0x1b
	// pllx_r_ck = vcox_ck / 30
	RCC_PLL1DIVR_PLL1R_Div30 = 0x1d
	// pllx_r_ck = vcox_ck / 32
	RCC_PLL1DIVR_PLL1R_Div32 = 0x1f
	// pllx_r_ck = vcox_ck / 34
	RCC_PLL1DIVR_PLL1R_Div34 = 0x21
	// pllx_r_ck = vcox_ck / 36
	RCC_PLL1DIVR_PLL1R_Div36 = 0x23
	// pllx_r_ck = vcox_ck / 38
	RCC_PLL1DIVR_PLL1R_Div38 = 0x25
	// pllx_r_ck = vcox_ck / 40
	RCC_PLL1DIVR_PLL1R_Div40 = 0x27
	// pllx_r_ck = vcox_ck / 42
	RCC_PLL1DIVR_PLL1R_Div42 = 0x29
	// pllx_r_ck = vcox_ck / 44
	RCC_PLL1DIVR_PLL1R_Div44 = 0x2b
	// pllx_r_ck = vcox_ck / 46
	RCC_PLL1DIVR_PLL1R_Div46 = 0x2d
	// pllx_r_ck = vcox_ck / 48
	RCC_PLL1DIVR_PLL1R_Div48 = 0x2f
	// pllx_r_ck = vcox_ck / 50
	RCC_PLL1DIVR_PLL1R_Div50 = 0x31
	// pllx_r_ck = vcox_ck / 52
	RCC_PLL1DIVR_PLL1R_Div52 = 0x33
	// pllx_r_ck = vcox_ck / 54
	RCC_PLL1DIVR_PLL1R_Div54 = 0x35
	// pllx_r_ck = vcox_ck / 56
	RCC_PLL1DIVR_PLL1R_Div56 = 0x37
	// pllx_r_ck = vcox_ck / 58
	RCC_PLL1DIVR_PLL1R_Div58 = 0x39
	// pllx_r_ck = vcox_ck / 60
	RCC_PLL1DIVR_PLL1R_Div60 = 0x3b
	// pllx_r_ck = vcox_ck / 62
	RCC_PLL1DIVR_PLL1R_Div62 = 0x3d
	// pllx_r_ck = vcox_ck / 64
	RCC_PLL1DIVR_PLL1R_Div64 = 0x3f
	// pllx_r_ck = vcox_ck / 66
	RCC_PLL1DIVR_PLL1R_Div66 = 0x41
	// pllx_r_ck = vcox_ck / 68
	RCC_PLL1DIVR_PLL1R_Div68 = 0x43
	// pllx_r_ck = vcox_ck / 70
	RCC_PLL1DIVR_PLL1R_Div70 = 0x45
	// pllx_r_ck = vcox_ck / 72
	RCC_PLL1DIVR_PLL1R_Div72 = 0x47
	// pllx_r_ck = vcox_ck / 74
	RCC_PLL1DIVR_PLL1R_Div74 = 0x49
	// pllx_r_ck = vcox_ck / 76
	RCC_PLL1DIVR_PLL1R_Div76 = 0x4b
	// pllx_r_ck = vcox_ck / 78
	RCC_PLL1DIVR_PLL1R_Div78 = 0x4d
	// pllx_r_ck = vcox_ck / 80
	RCC_PLL1DIVR_PLL1R_Div80 = 0x4f
	// pllx_r_ck = vcox_ck / 82
	RCC_PLL1DIVR_PLL1R_Div82 = 0x51
	// pllx_r_ck = vcox_ck / 84
	RCC_PLL1DIVR_PLL1R_Div84 = 0x53
	// pllx_r_ck = vcox_ck / 86
	RCC_PLL1DIVR_PLL1R_Div86 = 0x55
	// pllx_r_ck = vcox_ck / 88
	RCC_PLL1DIVR_PLL1R_Div88 = 0x57
	// pllx_r_ck = vcox_ck / 90
	RCC_PLL1DIVR_PLL1R_Div90 = 0x59
	// pllx_r_ck = vcox_ck / 92
	RCC_PLL1DIVR_PLL1R_Div92 = 0x5b
	// pllx_r_ck = vcox_ck / 94
	RCC_PLL1DIVR_PLL1R_Div94 = 0x5d
	// pllx_r_ck = vcox_ck / 96
	RCC_PLL1DIVR_PLL1R_Div96 = 0x5f
	// pllx_r_ck = vcox_ck / 98
	RCC_PLL1DIVR_PLL1R_Div98 = 0x61
	// pllx_r_ck = vcox_ck / 100
	RCC_PLL1DIVR_PLL1R_Div100 = 0x63
	// pllx_r_ck = vcox_ck / 102
	RCC_PLL1DIVR_PLL1R_Div102 = 0x65
	// pllx_r_ck = vcox_ck / 104
	RCC_PLL1DIVR_PLL1R_Div104 = 0x67
	// pllx_r_ck = vcox_ck / 106
	RCC_PLL1DIVR_PLL1R_Div106 = 0x69
	// pllx_r_ck = vcox_ck / 108
	RCC_PLL1DIVR_PLL1R_Div108 = 0x6b
	// pllx_r_ck = vcox_ck / 110
	RCC_PLL1DIVR_PLL1R_Div110 = 0x6d
	// pllx_r_ck = vcox_ck / 112
	RCC_PLL1DIVR_PLL1R_Div112 = 0x6f
	// pllx_r_ck = vcox_ck / 114
	RCC_PLL1DIVR_PLL1R_Div114 = 0x71
	// pllx_r_ck = vcox_ck / 116
	RCC_PLL1DIVR_PLL1R_Div116 = 0x73
	// pllx_r_ck = vcox_ck / 118
	RCC_PLL1DIVR_PLL1R_Div118 = 0x75
	// pllx_r_ck = vcox_ck / 120
	RCC_PLL1DIVR_PLL1R_Div120 = 0x77
	// pllx_r_ck = vcox_ck / 122
	RCC_PLL1DIVR_PLL1R_Div122 = 0x79
	// pllx_r_ck = vcox_ck / 124
	RCC_PLL1DIVR_PLL1R_Div124 = 0x7b
	// pllx_r_ck = vcox_ck / 126
	RCC_PLL1DIVR_PLL1R_Div126 = 0x7d
	// pllx_r_ck = vcox_ck / 128
	RCC_PLL1DIVR_PLL1R_Div128 = 0x7f

	// PLL1FRACR: RCC PLL1 fractional divider register
	// Position of PLL1FRACN field.
	RCC_PLL1FRACR_PLL1FRACN_Pos = 0x3
	// Bit mask of PLL1FRACN field.
	RCC_PLL1FRACR_PLL1FRACN_Msk = 0xfff8

	// PLL2DIVR: RCC PLL2 dividers configuration register
	// Position of PLL2N field.
	RCC_PLL2DIVR_PLL2N_Pos = 0x0
	// Bit mask of PLL2N field.
	RCC_PLL2DIVR_PLL2N_Msk = 0x1ff
	// Position of PLL2P field.
	RCC_PLL2DIVR_PLL2P_Pos = 0x9
	// Bit mask of PLL2P field.
	RCC_PLL2DIVR_PLL2P_Msk = 0xfe00
	// pllx_p_ck = vcox_ck
	RCC_PLL2DIVR_PLL2P_Div1 = 0x0
	// pllx_p_ck = vcox_ck / 2
	RCC_PLL2DIVR_PLL2P_Div2 = 0x1
	// pllx_p_ck = vcox_ck / 4
	RCC_PLL2DIVR_PLL2P_Div4 = 0x3
	// pllx_p_ck = vcox_ck / 6
	RCC_PLL2DIVR_PLL2P_Div6 = 0x5
	// pllx_p_ck = vcox_ck / 8
	RCC_PLL2DIVR_PLL2P_Div8 = 0x7
	// pllx_p_ck = vcox_ck / 10
	RCC_PLL2DIVR_PLL2P_Div10 = 0x9
	// pllx_p_ck = vcox_ck / 12
	RCC_PLL2DIVR_PLL2P_Div12 = 0xb
	// pllx_p_ck = vcox_ck / 14
	RCC_PLL2DIVR_PLL2P_Div14 = 0xd
	// pllx_p_ck = vcox_ck / 16
	RCC_PLL2DIVR_PLL2P_Div16 = 0xf
	// pllx_p_ck = vcox_ck / 18
	RCC_PLL2DIVR_PLL2P_Div18 = 0x11
	// pllx_p_ck = vcox_ck / 20
	RCC_PLL2DIVR_PLL2P_Div20 = 0x13
	// pllx_p_ck = vcox_ck / 22
	RCC_PLL2DIVR_PLL2P_Div22 = 0x15
	// pllx_p_ck = vcox_ck / 24
	RCC_PLL2DIVR_PLL2P_Div24 = 0x17
	// pllx_p_ck = vcox_ck / 26
	RCC_PLL2DIVR_PLL2P_Div26 = 0x19
	// pllx_p_ck = vcox_ck / 28
	RCC_PLL2DIVR_PLL2P_Div28 = 0x1b
	// pllx_p_ck = vcox_ck / 30
	RCC_PLL2DIVR_PLL2P_Div30 = 0x1d
	// pllx_p_ck = vcox_ck / 32
	RCC_PLL2DIVR_PLL2P_Div32 = 0x1f
	// pllx_p_ck = vcox_ck / 34
	RCC_PLL2DIVR_PLL2P_Div34 = 0x21
	// pllx_p_ck = vcox_ck / 36
	RCC_PLL2DIVR_PLL2P_Div36 = 0x23
	// pllx_p_ck = vcox_ck / 38
	RCC_PLL2DIVR_PLL2P_Div38 = 0x25
	// pllx_p_ck = vcox_ck / 40
	RCC_PLL2DIVR_PLL2P_Div40 = 0x27
	// pllx_p_ck = vcox_ck / 42
	RCC_PLL2DIVR_PLL2P_Div42 = 0x29
	// pllx_p_ck = vcox_ck / 44
	RCC_PLL2DIVR_PLL2P_Div44 = 0x2b
	// pllx_p_ck = vcox_ck / 46
	RCC_PLL2DIVR_PLL2P_Div46 = 0x2d
	// pllx_p_ck = vcox_ck / 48
	RCC_PLL2DIVR_PLL2P_Div48 = 0x2f
	// pllx_p_ck = vcox_ck / 50
	RCC_PLL2DIVR_PLL2P_Div50 = 0x31
	// pllx_p_ck = vcox_ck / 52
	RCC_PLL2DIVR_PLL2P_Div52 = 0x33
	// pllx_p_ck = vcox_ck / 54
	RCC_PLL2DIVR_PLL2P_Div54 = 0x35
	// pllx_p_ck = vcox_ck / 56
	RCC_PLL2DIVR_PLL2P_Div56 = 0x37
	// pllx_p_ck = vcox_ck / 58
	RCC_PLL2DIVR_PLL2P_Div58 = 0x39
	// pllx_p_ck = vcox_ck / 60
	RCC_PLL2DIVR_PLL2P_Div60 = 0x3b
	// pllx_p_ck = vcox_ck / 62
	RCC_PLL2DIVR_PLL2P_Div62 = 0x3d
	// pllx_p_ck = vcox_ck / 64
	RCC_PLL2DIVR_PLL2P_Div64 = 0x3f
	// pllx_p_ck = vcox_ck / 66
	RCC_PLL2DIVR_PLL2P_Div66 = 0x41
	// pllx_p_ck = vcox_ck / 68
	RCC_PLL2DIVR_PLL2P_Div68 = 0x43
	// pllx_p_ck = vcox_ck / 70
	RCC_PLL2DIVR_PLL2P_Div70 = 0x45
	// pllx_p_ck = vcox_ck / 72
	RCC_PLL2DIVR_PLL2P_Div72 = 0x47
	// pllx_p_ck = vcox_ck / 74
	RCC_PLL2DIVR_PLL2P_Div74 = 0x49
	// pllx_p_ck = vcox_ck / 76
	RCC_PLL2DIVR_PLL2P_Div76 = 0x4b
	// pllx_p_ck = vcox_ck / 78
	RCC_PLL2DIVR_PLL2P_Div78 = 0x4d
	// pllx_p_ck = vcox_ck / 80
	RCC_PLL2DIVR_PLL2P_Div80 = 0x4f
	// pllx_p_ck = vcox_ck / 82
	RCC_PLL2DIVR_PLL2P_Div82 = 0x51
	// pllx_p_ck = vcox_ck / 84
	RCC_PLL2DIVR_PLL2P_Div84 = 0x53
	// pllx_p_ck = vcox_ck / 86
	RCC_PLL2DIVR_PLL2P_Div86 = 0x55
	// pllx_p_ck = vcox_ck / 88
	RCC_PLL2DIVR_PLL2P_Div88 = 0x57
	// pllx_p_ck = vcox_ck / 90
	RCC_PLL2DIVR_PLL2P_Div90 = 0x59
	// pllx_p_ck = vcox_ck / 92
	RCC_PLL2DIVR_PLL2P_Div92 = 0x5b
	// pllx_p_ck = vcox_ck / 94
	RCC_PLL2DIVR_PLL2P_Div94 = 0x5d
	// pllx_p_ck = vcox_ck / 96
	RCC_PLL2DIVR_PLL2P_Div96 = 0x5f
	// pllx_p_ck = vcox_ck / 98
	RCC_PLL2DIVR_PLL2P_Div98 = 0x61
	// pllx_p_ck = vcox_ck / 100
	RCC_PLL2DIVR_PLL2P_Div100 = 0x63
	// pllx_p_ck = vcox_ck / 102
	RCC_PLL2DIVR_PLL2P_Div102 = 0x65
	// pllx_p_ck = vcox_ck / 104
	RCC_PLL2DIVR_PLL2P_Div104 = 0x67
	// pllx_p_ck = vcox_ck / 106
	RCC_PLL2DIVR_PLL2P_Div106 = 0x69
	// pllx_p_ck = vcox_ck / 108
	RCC_PLL2DIVR_PLL2P_Div108 = 0x6b
	// pllx_p_ck = vcox_ck / 110
	RCC_PLL2DIVR_PLL2P_Div110 = 0x6d
	// pllx_p_ck = vcox_ck / 112
	RCC_PLL2DIVR_PLL2P_Div112 = 0x6f
	// pllx_p_ck = vcox_ck / 114
	RCC_PLL2DIVR_PLL2P_Div114 = 0x71
	// pllx_p_ck = vcox_ck / 116
	RCC_PLL2DIVR_PLL2P_Div116 = 0x73
	// pllx_p_ck = vcox_ck / 118
	RCC_PLL2DIVR_PLL2P_Div118 = 0x75
	// pllx_p_ck = vcox_ck / 120
	RCC_PLL2DIVR_PLL2P_Div120 = 0x77
	// pllx_p_ck = vcox_ck / 122
	RCC_PLL2DIVR_PLL2P_Div122 = 0x79
	// pllx_p_ck = vcox_ck / 124
	RCC_PLL2DIVR_PLL2P_Div124 = 0x7b
	// pllx_p_ck = vcox_ck / 126
	RCC_PLL2DIVR_PLL2P_Div126 = 0x7d
	// pllx_p_ck = vcox_ck / 128
	RCC_PLL2DIVR_PLL2P_Div128 = 0x7f
	// Position of PLL2Q field.
	RCC_PLL2DIVR_PLL2Q_Pos = 0x10
	// Bit mask of PLL2Q field.
	RCC_PLL2DIVR_PLL2Q_Msk = 0x7f0000
	// pllx_q_ck = vcox_ck
	RCC_PLL2DIVR_PLL2Q_Div1 = 0x0
	// pllx_q_ck = vcox_ck / 2
	RCC_PLL2DIVR_PLL2Q_Div2 = 0x1
	// pllx_q_ck = vcox_ck / 4
	RCC_PLL2DIVR_PLL2Q_Div4 = 0x3
	// pllx_q_ck = vcox_ck / 6
	RCC_PLL2DIVR_PLL2Q_Div6 = 0x5
	// pllx_q_ck = vcox_ck / 8
	RCC_PLL2DIVR_PLL2Q_Div8 = 0x7
	// pllx_q_ck = vcox_ck / 10
	RCC_PLL2DIVR_PLL2Q_Div10 = 0x9
	// pllx_q_ck = vcox_ck / 12
	RCC_PLL2DIVR_PLL2Q_Div12 = 0xb
	// pllx_q_ck = vcox_ck / 14
	RCC_PLL2DIVR_PLL2Q_Div14 = 0xd
	// pllx_q_ck = vcox_ck / 16
	RCC_PLL2DIVR_PLL2Q_Div16 = 0xf
	// pllx_q_ck = vcox_ck / 18
	RCC_PLL2DIVR_PLL2Q_Div18 = 0x11
	// pllx_q_ck = vcox_ck / 20
	RCC_PLL2DIVR_PLL2Q_Div20 = 0x13
	// pllx_q_ck = vcox_ck / 22
	RCC_PLL2DIVR_PLL2Q_Div22 = 0x15
	// pllx_q_ck = vcox_ck / 24
	RCC_PLL2DIVR_PLL2Q_Div24 = 0x17
	// pllx_q_ck = vcox_ck / 26
	RCC_PLL2DIVR_PLL2Q_Div26 = 0x19
	// pllx_q_ck = vcox_ck / 28
	RCC_PLL2DIVR_PLL2Q_Div28 = 0x1b
	// pllx_q_ck = vcox_ck / 30
	RCC_PLL2DIVR_PLL2Q_Div30 = 0x1d
	// pllx_q_ck = vcox_ck / 32
	RCC_PLL2DIVR_PLL2Q_Div32 = 0x1f
	// pllx_q_ck = vcox_ck / 34
	RCC_PLL2DIVR_PLL2Q_Div34 = 0x21
	// pllx_q_ck = vcox_ck / 36
	RCC_PLL2DIVR_PLL2Q_Div36 = 0x23
	// pllx_q_ck = vcox_ck / 38
	RCC_PLL2DIVR_PLL2Q_Div38 = 0x25
	// pllx_q_ck = vcox_ck / 40
	RCC_PLL2DIVR_PLL2Q_Div40 = 0x27
	// pllx_q_ck = vcox_ck / 42
	RCC_PLL2DIVR_PLL2Q_Div42 = 0x29
	// pllx_q_ck = vcox_ck / 44
	RCC_PLL2DIVR_PLL2Q_Div44 = 0x2b
	// pllx_q_ck = vcox_ck / 46
	RCC_PLL2DIVR_PLL2Q_Div46 = 0x2d
	// pllx_q_ck = vcox_ck / 48
	RCC_PLL2DIVR_PLL2Q_Div48 = 0x2f
	// pllx_q_ck = vcox_ck / 50
	RCC_PLL2DIVR_PLL2Q_Div50 = 0x31
	// pllx_q_ck = vcox_ck / 52
	RCC_PLL2DIVR_PLL2Q_Div52 = 0x33
	// pllx_q_ck = vcox_ck / 54
	RCC_PLL2DIVR_PLL2Q_Div54 = 0x35
	// pllx_q_ck = vcox_ck / 56
	RCC_PLL2DIVR_PLL2Q_Div56 = 0x37
	// pllx_q_ck = vcox_ck / 58
	RCC_PLL2DIVR_PLL2Q_Div58 = 0x39
	// pllx_q_ck = vcox_ck / 60
	RCC_PLL2DIVR_PLL2Q_Div60 = 0x3b
	// pllx_q_ck = vcox_ck / 62
	RCC_PLL2DIVR_PLL2Q_Div62 = 0x3d
	// pllx_q_ck = vcox_ck / 64
	RCC_PLL2DIVR_PLL2Q_Div64 = 0x3f
	// pllx_q_ck = vcox_ck / 66
	RCC_PLL2DIVR_PLL2Q_Div66 = 0x41
	// pllx_q_ck = vcox_ck / 68
	RCC_PLL2DIVR_PLL2Q_Div68 = 0x43
	// pllx_q_ck = vcox_ck / 70
	RCC_PLL2DIVR_PLL2Q_Div70 = 0x45
	// pllx_q_ck = vcox_ck / 72
	RCC_PLL2DIVR_PLL2Q_Div72 = 0x47
	// pllx_q_ck = vcox_ck / 74
	RCC_PLL2DIVR_PLL2Q_Div74 = 0x49
	// pllx_q_ck = vcox_ck / 76
	RCC_PLL2DIVR_PLL2Q_Div76 = 0x4b
	// pllx_q_ck = vcox_ck / 78
	RCC_PLL2DIVR_PLL2Q_Div78 = 0x4d
	// pllx_q_ck = vcox_ck / 80
	RCC_PLL2DIVR_PLL2Q_Div80 = 0x4f
	// pllx_q_ck = vcox_ck / 82
	RCC_PLL2DIVR_PLL2Q_Div82 = 0x51
	// pllx_q_ck = vcox_ck / 84
	RCC_PLL2DIVR_PLL2Q_Div84 = 0x53
	// pllx_q_ck = vcox_ck / 86
	RCC_PLL2DIVR_PLL2Q_Div86 = 0x55
	// pllx_q_ck = vcox_ck / 88
	RCC_PLL2DIVR_PLL2Q_Div88 = 0x57
	// pllx_q_ck = vcox_ck / 90
	RCC_PLL2DIVR_PLL2Q_Div90 = 0x59
	// pllx_q_ck = vcox_ck / 92
	RCC_PLL2DIVR_PLL2Q_Div92 = 0x5b
	// pllx_q_ck = vcox_ck / 94
	RCC_PLL2DIVR_PLL2Q_Div94 = 0x5d
	// pllx_q_ck = vcox_ck / 96
	RCC_PLL2DIVR_PLL2Q_Div96 = 0x5f
	// pllx_q_ck = vcox_ck / 98
	RCC_PLL2DIVR_PLL2Q_Div98 = 0x61
	// pllx_q_ck = vcox_ck / 100
	RCC_PLL2DIVR_PLL2Q_Div100 = 0x63
	// pllx_q_ck = vcox_ck / 102
	RCC_PLL2DIVR_PLL2Q_Div102 = 0x65
	// pllx_q_ck = vcox_ck / 104
	RCC_PLL2DIVR_PLL2Q_Div104 = 0x67
	// pllx_q_ck = vcox_ck / 106
	RCC_PLL2DIVR_PLL2Q_Div106 = 0x69
	// pllx_q_ck = vcox_ck / 108
	RCC_PLL2DIVR_PLL2Q_Div108 = 0x6b
	// pllx_q_ck = vcox_ck / 110
	RCC_PLL2DIVR_PLL2Q_Div110 = 0x6d
	// pllx_q_ck = vcox_ck / 112
	RCC_PLL2DIVR_PLL2Q_Div112 = 0x6f
	// pllx_q_ck = vcox_ck / 114
	RCC_PLL2DIVR_PLL2Q_Div114 = 0x71
	// pllx_q_ck = vcox_ck / 116
	RCC_PLL2DIVR_PLL2Q_Div116 = 0x73
	// pllx_q_ck = vcox_ck / 118
	RCC_PLL2DIVR_PLL2Q_Div118 = 0x75
	// pllx_q_ck = vcox_ck / 120
	RCC_PLL2DIVR_PLL2Q_Div120 = 0x77
	// pllx_q_ck = vcox_ck / 122
	RCC_PLL2DIVR_PLL2Q_Div122 = 0x79
	// pllx_q_ck = vcox_ck / 124
	RCC_PLL2DIVR_PLL2Q_Div124 = 0x7b
	// pllx_q_ck = vcox_ck / 126
	RCC_PLL2DIVR_PLL2Q_Div126 = 0x7d
	// pllx_q_ck = vcox_ck / 128
	RCC_PLL2DIVR_PLL2Q_Div128 = 0x7f
	// Position of PLL2R field.
	RCC_PLL2DIVR_PLL2R_Pos = 0x18
	// Bit mask of PLL2R field.
	RCC_PLL2DIVR_PLL2R_Msk = 0x7f000000
	// pllx_r_ck = vcox_ck
	RCC_PLL2DIVR_PLL2R_Div1 = 0x0
	// pllx_r_ck = vcox_ck / 2
	RCC_PLL2DIVR_PLL2R_Div2 = 0x1
	// pllx_r_ck = vcox_ck / 4
	RCC_PLL2DIVR_PLL2R_Div4 = 0x3
	// pllx_r_ck = vcox_ck / 6
	RCC_PLL2DIVR_PLL2R_Div6 = 0x5
	// pllx_r_ck = vcox_ck / 8
	RCC_PLL2DIVR_PLL2R_Div8 = 0x7
	// pllx_r_ck = vcox_ck / 10
	RCC_PLL2DIVR_PLL2R_Div10 = 0x9
	// pllx_r_ck = vcox_ck / 12
	RCC_PLL2DIVR_PLL2R_Div12 = 0xb
	// pllx_r_ck = vcox_ck / 14
	RCC_PLL2DIVR_PLL2R_Div14 = 0xd
	// pllx_r_ck = vcox_ck / 16
	RCC_PLL2DIVR_PLL2R_Div16 = 0xf
	// pllx_r_ck = vcox_ck / 18
	RCC_PLL2DIVR_PLL2R_Div18 = 0x11
	// pllx_r_ck = vcox_ck / 20
	RCC_PLL2DIVR_PLL2R_Div20 = 0x13
	// pllx_r_ck = vcox_ck / 22
	RCC_PLL2DIVR_PLL2R_Div22 = 0x15
	// pllx_r_ck = vcox_ck / 24
	RCC_PLL2DIVR_PLL2R_Div24 = 0x17
	// pllx_r_ck = vcox_ck / 26
	RCC_PLL2DIVR_PLL2R_Div26 = 0x19
	// pllx_r_ck = vcox_ck / 28
	RCC_PLL2DIVR_PLL2R_Div28 = 0x1b
	// pllx_r_ck = vcox_ck / 30
	RCC_PLL2DIVR_PLL2R_Div30 = 0x1d
	// pllx_r_ck = vcox_ck / 32
	RCC_PLL2DIVR_PLL2R_Div32 = 0x1f
	// pllx_r_ck = vcox_ck / 34
	RCC_PLL2DIVR_PLL2R_Div34 = 0x21
	// pllx_r_ck = vcox_ck / 36
	RCC_PLL2DIVR_PLL2R_Div36 = 0x23
	// pllx_r_ck = vcox_ck / 38
	RCC_PLL2DIVR_PLL2R_Div38 = 0x25
	// pllx_r_ck = vcox_ck / 40
	RCC_PLL2DIVR_PLL2R_Div40 = 0x27
	// pllx_r_ck = vcox_ck / 42
	RCC_PLL2DIVR_PLL2R_Div42 = 0x29
	// pllx_r_ck = vcox_ck / 44
	RCC_PLL2DIVR_PLL2R_Div44 = 0x2b
	// pllx_r_ck = vcox_ck / 46
	RCC_PLL2DIVR_PLL2R_Div46 = 0x2d
	// pllx_r_ck = vcox_ck / 48
	RCC_PLL2DIVR_PLL2R_Div48 = 0x2f
	// pllx_r_ck = vcox_ck / 50
	RCC_PLL2DIVR_PLL2R_Div50 = 0x31
	// pllx_r_ck = vcox_ck / 52
	RCC_PLL2DIVR_PLL2R_Div52 = 0x33
	// pllx_r_ck = vcox_ck / 54
	RCC_PLL2DIVR_PLL2R_Div54 = 0x35
	// pllx_r_ck = vcox_ck / 56
	RCC_PLL2DIVR_PLL2R_Div56 = 0x37
	// pllx_r_ck = vcox_ck / 58
	RCC_PLL2DIVR_PLL2R_Div58 = 0x39
	// pllx_r_ck = vcox_ck / 60
	RCC_PLL2DIVR_PLL2R_Div60 = 0x3b
	// pllx_r_ck = vcox_ck / 62
	RCC_PLL2DIVR_PLL2R_Div62 = 0x3d
	// pllx_r_ck = vcox_ck / 64
	RCC_PLL2DIVR_PLL2R_Div64 = 0x3f
	// pllx_r_ck = vcox_ck / 66
	RCC_PLL2DIVR_PLL2R_Div66 = 0x41
	// pllx_r_ck = vcox_ck / 68
	RCC_PLL2DIVR_PLL2R_Div68 = 0x43
	// pllx_r_ck = vcox_ck / 70
	RCC_PLL2DIVR_PLL2R_Div70 = 0x45
	// pllx_r_ck = vcox_ck / 72
	RCC_PLL2DIVR_PLL2R_Div72 = 0x47
	// pllx_r_ck = vcox_ck / 74
	RCC_PLL2DIVR_PLL2R_Div74 = 0x49
	// pllx_r_ck = vcox_ck / 76
	RCC_PLL2DIVR_PLL2R_Div76 = 0x4b
	// pllx_r_ck = vcox_ck / 78
	RCC_PLL2DIVR_PLL2R_Div78 = 0x4d
	// pllx_r_ck = vcox_ck / 80
	RCC_PLL2DIVR_PLL2R_Div80 = 0x4f
	// pllx_r_ck = vcox_ck / 82
	RCC_PLL2DIVR_PLL2R_Div82 = 0x51
	// pllx_r_ck = vcox_ck / 84
	RCC_PLL2DIVR_PLL2R_Div84 = 0x53
	// pllx_r_ck = vcox_ck / 86
	RCC_PLL2DIVR_PLL2R_Div86 = 0x55
	// pllx_r_ck = vcox_ck / 88
	RCC_PLL2DIVR_PLL2R_Div88 = 0x57
	// pllx_r_ck = vcox_ck / 90
	RCC_PLL2DIVR_PLL2R_Div90 = 0x59
	// pllx_r_ck = vcox_ck / 92
	RCC_PLL2DIVR_PLL2R_Div92 = 0x5b
	// pllx_r_ck = vcox_ck / 94
	RCC_PLL2DIVR_PLL2R_Div94 = 0x5d
	// pllx_r_ck = vcox_ck / 96
	RCC_PLL2DIVR_PLL2R_Div96 = 0x5f
	// pllx_r_ck = vcox_ck / 98
	RCC_PLL2DIVR_PLL2R_Div98 = 0x61
	// pllx_r_ck = vcox_ck / 100
	RCC_PLL2DIVR_PLL2R_Div100 = 0x63
	// pllx_r_ck = vcox_ck / 102
	RCC_PLL2DIVR_PLL2R_Div102 = 0x65
	// pllx_r_ck = vcox_ck / 104
	RCC_PLL2DIVR_PLL2R_Div104 = 0x67
	// pllx_r_ck = vcox_ck / 106
	RCC_PLL2DIVR_PLL2R_Div106 = 0x69
	// pllx_r_ck = vcox_ck / 108
	RCC_PLL2DIVR_PLL2R_Div108 = 0x6b
	// pllx_r_ck = vcox_ck / 110
	RCC_PLL2DIVR_PLL2R_Div110 = 0x6d
	// pllx_r_ck = vcox_ck / 112
	RCC_PLL2DIVR_PLL2R_Div112 = 0x6f
	// pllx_r_ck = vcox_ck / 114
	RCC_PLL2DIVR_PLL2R_Div114 = 0x71
	// pllx_r_ck = vcox_ck / 116
	RCC_PLL2DIVR_PLL2R_Div116 = 0x73
	// pllx_r_ck = vcox_ck / 118
	RCC_PLL2DIVR_PLL2R_Div118 = 0x75
	// pllx_r_ck = vcox_ck / 120
	RCC_PLL2DIVR_PLL2R_Div120 = 0x77
	// pllx_r_ck = vcox_ck / 122
	RCC_PLL2DIVR_PLL2R_Div122 = 0x79
	// pllx_r_ck = vcox_ck / 124
	RCC_PLL2DIVR_PLL2R_Div124 = 0x7b
	// pllx_r_ck = vcox_ck / 126
	RCC_PLL2DIVR_PLL2R_Div126 = 0x7d
	// pllx_r_ck = vcox_ck / 128
	RCC_PLL2DIVR_PLL2R_Div128 = 0x7f

	// PLL2FRACR: RCC PLL2 fractional divider register
	// Position of PLL2FRACN field.
	RCC_PLL2FRACR_PLL2FRACN_Pos = 0x3
	// Bit mask of PLL2FRACN field.
	RCC_PLL2FRACR_PLL2FRACN_Msk = 0xfff8

	// PLL3DIVR: RCC PLL3 dividers configuration register
	// Position of PLL3N field.
	RCC_PLL3DIVR_PLL3N_Pos = 0x0
	// Bit mask of PLL3N field.
	RCC_PLL3DIVR_PLL3N_Msk = 0x1ff
	// Position of PLL3P field.
	RCC_PLL3DIVR_PLL3P_Pos = 0x9
	// Bit mask of PLL3P field.
	RCC_PLL3DIVR_PLL3P_Msk = 0xfe00
	// pllx_p_ck = vcox_ck
	RCC_PLL3DIVR_PLL3P_Div1 = 0x0
	// pllx_p_ck = vcox_ck / 2
	RCC_PLL3DIVR_PLL3P_Div2 = 0x1
	// pllx_p_ck = vcox_ck / 4
	RCC_PLL3DIVR_PLL3P_Div4 = 0x3
	// pllx_p_ck = vcox_ck / 6
	RCC_PLL3DIVR_PLL3P_Div6 = 0x5
	// pllx_p_ck = vcox_ck / 8
	RCC_PLL3DIVR_PLL3P_Div8 = 0x7
	// pllx_p_ck = vcox_ck / 10
	RCC_PLL3DIVR_PLL3P_Div10 = 0x9
	// pllx_p_ck = vcox_ck / 12
	RCC_PLL3DIVR_PLL3P_Div12 = 0xb
	// pllx_p_ck = vcox_ck / 14
	RCC_PLL3DIVR_PLL3P_Div14 = 0xd
	// pllx_p_ck = vcox_ck / 16
	RCC_PLL3DIVR_PLL3P_Div16 = 0xf
	// pllx_p_ck = vcox_ck / 18
	RCC_PLL3DIVR_PLL3P_Div18 = 0x11
	// pllx_p_ck = vcox_ck / 20
	RCC_PLL3DIVR_PLL3P_Div20 = 0x13
	// pllx_p_ck = vcox_ck / 22
	RCC_PLL3DIVR_PLL3P_Div22 = 0x15
	// pllx_p_ck = vcox_ck / 24
	RCC_PLL3DIVR_PLL3P_Div24 = 0x17
	// pllx_p_ck = vcox_ck / 26
	RCC_PLL3DIVR_PLL3P_Div26 = 0x19
	// pllx_p_ck = vcox_ck / 28
	RCC_PLL3DIVR_PLL3P_Div28 = 0x1b
	// pllx_p_ck = vcox_ck / 30
	RCC_PLL3DIVR_PLL3P_Div30 = 0x1d
	// pllx_p_ck = vcox_ck / 32
	RCC_PLL3DIVR_PLL3P_Div32 = 0x1f
	// pllx_p_ck = vcox_ck / 34
	RCC_PLL3DIVR_PLL3P_Div34 = 0x21
	// pllx_p_ck = vcox_ck / 36
	RCC_PLL3DIVR_PLL3P_Div36 = 0x23
	// pllx_p_ck = vcox_ck / 38
	RCC_PLL3DIVR_PLL3P_Div38 = 0x25
	// pllx_p_ck = vcox_ck / 40
	RCC_PLL3DIVR_PLL3P_Div40 = 0x27
	// pllx_p_ck = vcox_ck / 42
	RCC_PLL3DIVR_PLL3P_Div42 = 0x29
	// pllx_p_ck = vcox_ck / 44
	RCC_PLL3DIVR_PLL3P_Div44 = 0x2b
	// pllx_p_ck = vcox_ck / 46
	RCC_PLL3DIVR_PLL3P_Div46 = 0x2d
	// pllx_p_ck = vcox_ck / 48
	RCC_PLL3DIVR_PLL3P_Div48 = 0x2f
	// pllx_p_ck = vcox_ck / 50
	RCC_PLL3DIVR_PLL3P_Div50 = 0x31
	// pllx_p_ck = vcox_ck / 52
	RCC_PLL3DIVR_PLL3P_Div52 = 0x33
	// pllx_p_ck = vcox_ck / 54
	RCC_PLL3DIVR_PLL3P_Div54 = 0x35
	// pllx_p_ck = vcox_ck / 56
	RCC_PLL3DIVR_PLL3P_Div56 = 0x37
	// pllx_p_ck = vcox_ck / 58
	RCC_PLL3DIVR_PLL3P_Div58 = 0x39
	// pllx_p_ck = vcox_ck / 60
	RCC_PLL3DIVR_PLL3P_Div60 = 0x3b
	// pllx_p_ck = vcox_ck / 62
	RCC_PLL3DIVR_PLL3P_Div62 = 0x3d
	// pllx_p_ck = vcox_ck / 64
	RCC_PLL3DIVR_PLL3P_Div64 = 0x3f
	// pllx_p_ck = vcox_ck / 66
	RCC_PLL3DIVR_PLL3P_Div66 = 0x41
	// pllx_p_ck = vcox_ck / 68
	RCC_PLL3DIVR_PLL3P_Div68 = 0x43
	// pllx_p_ck = vcox_ck / 70
	RCC_PLL3DIVR_PLL3P_Div70 = 0x45
	// pllx_p_ck = vcox_ck / 72
	RCC_PLL3DIVR_PLL3P_Div72 = 0x47
	// pllx_p_ck = vcox_ck / 74
	RCC_PLL3DIVR_PLL3P_Div74 = 0x49
	// pllx_p_ck = vcox_ck / 76
	RCC_PLL3DIVR_PLL3P_Div76 = 0x4b
	// pllx_p_ck = vcox_ck / 78
	RCC_PLL3DIVR_PLL3P_Div78 = 0x4d
	// pllx_p_ck = vcox_ck / 80
	RCC_PLL3DIVR_PLL3P_Div80 = 0x4f
	// pllx_p_ck = vcox_ck / 82
	RCC_PLL3DIVR_PLL3P_Div82 = 0x51
	// pllx_p_ck = vcox_ck / 84
	RCC_PLL3DIVR_PLL3P_Div84 = 0x53
	// pllx_p_ck = vcox_ck / 86
	RCC_PLL3DIVR_PLL3P_Div86 = 0x55
	// pllx_p_ck = vcox_ck / 88
	RCC_PLL3DIVR_PLL3P_Div88 = 0x57
	// pllx_p_ck = vcox_ck / 90
	RCC_PLL3DIVR_PLL3P_Div90 = 0x59
	// pllx_p_ck = vcox_ck / 92
	RCC_PLL3DIVR_PLL3P_Div92 = 0x5b
	// pllx_p_ck = vcox_ck / 94
	RCC_PLL3DIVR_PLL3P_Div94 = 0x5d
	// pllx_p_ck = vcox_ck / 96
	RCC_PLL3DIVR_PLL3P_Div96 = 0x5f
	// pllx_p_ck = vcox_ck / 98
	RCC_PLL3DIVR_PLL3P_Div98 = 0x61
	// pllx_p_ck = vcox_ck / 100
	RCC_PLL3DIVR_PLL3P_Div100 = 0x63
	// pllx_p_ck = vcox_ck / 102
	RCC_PLL3DIVR_PLL3P_Div102 = 0x65
	// pllx_p_ck = vcox_ck / 104
	RCC_PLL3DIVR_PLL3P_Div104 = 0x67
	// pllx_p_ck = vcox_ck / 106
	RCC_PLL3DIVR_PLL3P_Div106 = 0x69
	// pllx_p_ck = vcox_ck / 108
	RCC_PLL3DIVR_PLL3P_Div108 = 0x6b
	// pllx_p_ck = vcox_ck / 110
	RCC_PLL3DIVR_PLL3P_Div110 = 0x6d
	// pllx_p_ck = vcox_ck / 112
	RCC_PLL3DIVR_PLL3P_Div112 = 0x6f
	// pllx_p_ck = vcox_ck / 114
	RCC_PLL3DIVR_PLL3P_Div114 = 0x71
	// pllx_p_ck = vcox_ck / 116
	RCC_PLL3DIVR_PLL3P_Div116 = 0x73
	// pllx_p_ck = vcox_ck / 118
	RCC_PLL3DIVR_PLL3P_Div118 = 0x75
	// pllx_p_ck = vcox_ck / 120
	RCC_PLL3DIVR_PLL3P_Div120 = 0x77
	// pllx_p_ck = vcox_ck / 122
	RCC_PLL3DIVR_PLL3P_Div122 = 0x79
	// pllx_p_ck = vcox_ck / 124
	RCC_PLL3DIVR_PLL3P_Div124 = 0x7b
	// pllx_p_ck = vcox_ck / 126
	RCC_PLL3DIVR_PLL3P_Div126 = 0x7d
	// pllx_p_ck = vcox_ck / 128
	RCC_PLL3DIVR_PLL3P_Div128 = 0x7f
	// Position of PLL3Q field.
	RCC_PLL3DIVR_PLL3Q_Pos = 0x10
	// Bit mask of PLL3Q field.
	RCC_PLL3DIVR_PLL3Q_Msk = 0x7f0000
	// pllx_q_ck = vcox_ck
	RCC_PLL3DIVR_PLL3Q_Div1 = 0x0
	// pllx_q_ck = vcox_ck / 2
	RCC_PLL3DIVR_PLL3Q_Div2 = 0x1
	// pllx_q_ck = vcox_ck / 4
	RCC_PLL3DIVR_PLL3Q_Div4 = 0x3
	// pllx_q_ck = vcox_ck / 6
	RCC_PLL3DIVR_PLL3Q_Div6 = 0x5
	// pllx_q_ck = vcox_ck / 8
	RCC_PLL3DIVR_PLL3Q_Div8 = 0x7
	// pllx_q_ck = vcox_ck / 10
	RCC_PLL3DIVR_PLL3Q_Div10 = 0x9
	// pllx_q_ck = vcox_ck / 12
	RCC_PLL3DIVR_PLL3Q_Div12 = 0xb
	// pllx_q_ck = vcox_ck / 14
	RCC_PLL3DIVR_PLL3Q_Div14 = 0xd
	// pllx_q_ck = vcox_ck / 16
	RCC_PLL3DIVR_PLL3Q_Div16 = 0xf
	// pllx_q_ck = vcox_ck / 18
	RCC_PLL3DIVR_PLL3Q_Div18 = 0x11
	// pllx_q_ck = vcox_ck / 20
	RCC_PLL3DIVR_PLL3Q_Div20 = 0x13
	// pllx_q_ck = vcox_ck / 22
	RCC_PLL3DIVR_PLL3Q_Div22 = 0x15
	// pllx_q_ck = vcox_ck / 24
	RCC_PLL3DIVR_PLL3Q_Div24 = 0x17
	// pllx_q_ck = vcox_ck / 26
	RCC_PLL3DIVR_PLL3Q_Div26 = 0x19
	// pllx_q_ck = vcox_ck / 28
	RCC_PLL3DIVR_PLL3Q_Div28 = 0x1b
	// pllx_q_ck = vcox_ck / 30
	RCC_PLL3DIVR_PLL3Q_Div30 = 0x1d
	// pllx_q_ck = vcox_ck / 32
	RCC_PLL3DIVR_PLL3Q_Div32 = 0x1f
	// pllx_q_ck = vcox_ck / 34
	RCC_PLL3DIVR_PLL3Q_Div34 = 0x21
	// pllx_q_ck = vcox_ck / 36
	RCC_PLL3DIVR_PLL3Q_Div36 = 0x23
	// pllx_q_ck = vcox_ck / 38
	RCC_PLL3DIVR_PLL3Q_Div38 = 0x25
	// pllx_q_ck = vcox_ck / 40
	RCC_PLL3DIVR_PLL3Q_Div40 = 0x27
	// pllx_q_ck = vcox_ck / 42
	RCC_PLL3DIVR_PLL3Q_Div42 = 0x29
	// pllx_q_ck = vcox_ck / 44
	RCC_PLL3DIVR_PLL3Q_Div44 = 0x2b
	// pllx_q_ck = vcox_ck / 46
	RCC_PLL3DIVR_PLL3Q_Div46 = 0x2d
	// pllx_q_ck = vcox_ck / 48
	RCC_PLL3DIVR_PLL3Q_Div48 = 0x2f
	// pllx_q_ck = vcox_ck / 50
	RCC_PLL3DIVR_PLL3Q_Div50 = 0x31
	// pllx_q_ck = vcox_ck / 52
	RCC_PLL3DIVR_PLL3Q_Div52 = 0x33
	// pllx_q_ck = vcox_ck / 54
	RCC_PLL3DIVR_PLL3Q_Div54 = 0x35
	// pllx_q_ck = vcox_ck / 56
	RCC_PLL3DIVR_PLL3Q_Div56 = 0x37
	// pllx_q_ck = vcox_ck / 58
	RCC_PLL3DIVR_PLL3Q_Div58 = 0x39
	// pllx_q_ck = vcox_ck / 60
	RCC_PLL3DIVR_PLL3Q_Div60 = 0x3b
	// pllx_q_ck = vcox_ck / 62
	RCC_PLL3DIVR_PLL3Q_Div62 = 0x3d
	// pllx_q_ck = vcox_ck / 64
	RCC_PLL3DIVR_PLL3Q_Div64 = 0x3f
	// pllx_q_ck = vcox_ck / 66
	RCC_PLL3DIVR_PLL3Q_Div66 = 0x41
	// pllx_q_ck = vcox_ck / 68
	RCC_PLL3DIVR_PLL3Q_Div68 = 0x43
	// pllx_q_ck = vcox_ck / 70
	RCC_PLL3DIVR_PLL3Q_Div70 = 0x45
	// pllx_q_ck = vcox_ck / 72
	RCC_PLL3DIVR_PLL3Q_Div72 = 0x47
	// pllx_q_ck = vcox_ck / 74
	RCC_PLL3DIVR_PLL3Q_Div74 = 0x49
	// pllx_q_ck = vcox_ck / 76
	RCC_PLL3DIVR_PLL3Q_Div76 = 0x4b
	// pllx_q_ck = vcox_ck / 78
	RCC_PLL3DIVR_PLL3Q_Div78 = 0x4d
	// pllx_q_ck = vcox_ck / 80
	RCC_PLL3DIVR_PLL3Q_Div80 = 0x4f
	// pllx_q_ck = vcox_ck / 82
	RCC_PLL3DIVR_PLL3Q_Div82 = 0x51
	// pllx_q_ck = vcox_ck / 84
	RCC_PLL3DIVR_PLL3Q_Div84 = 0x53
	// pllx_q_ck = vcox_ck / 86
	RCC_PLL3DIVR_PLL3Q_Div86 = 0x55
	// pllx_q_ck = vcox_ck / 88
	RCC_PLL3DIVR_PLL3Q_Div88 = 0x57
	// pllx_q_ck = vcox_ck / 90
	RCC_PLL3DIVR_PLL3Q_Div90 = 0x59
	// pllx_q_ck = vcox_ck / 92
	RCC_PLL3DIVR_PLL3Q_Div92 = 0x5b
	// pllx_q_ck = vcox_ck / 94
	RCC_PLL3DIVR_PLL3Q_Div94 = 0x5d
	// pllx_q_ck = vcox_ck / 96
	RCC_PLL3DIVR_PLL3Q_Div96 = 0x5f
	// pllx_q_ck = vcox_ck / 98
	RCC_PLL3DIVR_PLL3Q_Div98 = 0x61
	// pllx_q_ck = vcox_ck / 100
	RCC_PLL3DIVR_PLL3Q_Div100 = 0x63
	// pllx_q_ck = vcox_ck / 102
	RCC_PLL3DIVR_PLL3Q_Div102 = 0x65
	// pllx_q_ck = vcox_ck / 104
	RCC_PLL3DIVR_PLL3Q_Div104 = 0x67
	// pllx_q_ck = vcox_ck / 106
	RCC_PLL3DIVR_PLL3Q_Div106 = 0x69
	// pllx_q_ck = vcox_ck / 108
	RCC_PLL3DIVR_PLL3Q_Div108 = 0x6b
	// pllx_q_ck = vcox_ck / 110
	RCC_PLL3DIVR_PLL3Q_Div110 = 0x6d
	// pllx_q_ck = vcox_ck / 112
	RCC_PLL3DIVR_PLL3Q_Div112 = 0x6f
	// pllx_q_ck = vcox_ck / 114
	RCC_PLL3DIVR_PLL3Q_Div114 = 0x71
	// pllx_q_ck = vcox_ck / 116
	RCC_PLL3DIVR_PLL3Q_Div116 = 0x73
	// pllx_q_ck = vcox_ck / 118
	RCC_PLL3DIVR_PLL3Q_Div118 = 0x75
	// pllx_q_ck = vcox_ck / 120
	RCC_PLL3DIVR_PLL3Q_Div120 = 0x77
	// pllx_q_ck = vcox_ck / 122
	RCC_PLL3DIVR_PLL3Q_Div122 = 0x79
	// pllx_q_ck = vcox_ck / 124
	RCC_PLL3DIVR_PLL3Q_Div124 = 0x7b
	// pllx_q_ck = vcox_ck / 126
	RCC_PLL3DIVR_PLL3Q_Div126 = 0x7d
	// pllx_q_ck = vcox_ck / 128
	RCC_PLL3DIVR_PLL3Q_Div128 = 0x7f
	// Position of PLL3R field.
	RCC_PLL3DIVR_PLL3R_Pos = 0x18
	// Bit mask of PLL3R field.
	RCC_PLL3DIVR_PLL3R_Msk = 0x7f000000
	// pllx_r_ck = vcox_ck
	RCC_PLL3DIVR_PLL3R_Div1 = 0x0
	// pllx_r_ck = vcox_ck / 2
	RCC_PLL3DIVR_PLL3R_Div2 = 0x1
	// pllx_r_ck = vcox_ck / 4
	RCC_PLL3DIVR_PLL3R_Div4 = 0x3
	// pllx_r_ck = vcox_ck / 6
	RCC_PLL3DIVR_PLL3R_Div6 = 0x5
	// pllx_r_ck = vcox_ck / 8
	RCC_PLL3DIVR_PLL3R_Div8 = 0x7
	// pllx_r_ck = vcox_ck / 10
	RCC_PLL3DIVR_PLL3R_Div10 = 0x9
	// pllx_r_ck = vcox_ck / 12
	RCC_PLL3DIVR_PLL3R_Div12 = 0xb
	// pllx_r_ck = vcox_ck / 14
	RCC_PLL3DIVR_PLL3R_Div14 = 0xd
	// pllx_r_ck = vcox_ck / 16
	RCC_PLL3DIVR_PLL3R_Div16 = 0xf
	// pllx_r_ck = vcox_ck / 18
	RCC_PLL3DIVR_PLL3R_Div18 = 0x11
	// pllx_r_ck = vcox_ck / 20
	RCC_PLL3DIVR_PLL3R_Div20 = 0x13
	// pllx_r_ck = vcox_ck / 22
	RCC_PLL3DIVR_PLL3R_Div22 = 0x15
	// pllx_r_ck = vcox_ck / 24
	RCC_PLL3DIVR_PLL3R_Div24 = 0x17
	// pllx_r_ck = vcox_ck / 26
	RCC_PLL3DIVR_PLL3R_Div26 = 0x19
	// pllx_r_ck = vcox_ck / 28
	RCC_PLL3DIVR_PLL3R_Div28 = 0x1b
	// pllx_r_ck = vcox_ck / 30
	RCC_PLL3DIVR_PLL3R_Div30 = 0x1d
	// pllx_r_ck = vcox_ck / 32
	RCC_PLL3DIVR_PLL3R_Div32 = 0x1f
	// pllx_r_ck = vcox_ck / 34
	RCC_PLL3DIVR_PLL3R_Div34 = 0x21
	// pllx_r_ck = vcox_ck / 36
	RCC_PLL3DIVR_PLL3R_Div36 = 0x23
	// pllx_r_ck = vcox_ck / 38
	RCC_PLL3DIVR_PLL3R_Div38 = 0x25
	// pllx_r_ck = vcox_ck / 40
	RCC_PLL3DIVR_PLL3R_Div40 = 0x27
	// pllx_r_ck = vcox_ck / 42
	RCC_PLL3DIVR_PLL3R_Div42 = 0x29
	// pllx_r_ck = vcox_ck / 44
	RCC_PLL3DIVR_PLL3R_Div44 = 0x2b
	// pllx_r_ck = vcox_ck / 46
	RCC_PLL3DIVR_PLL3R_Div46 = 0x2d
	// pllx_r_ck = vcox_ck / 48
	RCC_PLL3DIVR_PLL3R_Div48 = 0x2f
	// pllx_r_ck = vcox_ck / 50
	RCC_PLL3DIVR_PLL3R_Div50 = 0x31
	// pllx_r_ck = vcox_ck / 52
	RCC_PLL3DIVR_PLL3R_Div52 = 0x33
	// pllx_r_ck = vcox_ck / 54
	RCC_PLL3DIVR_PLL3R_Div54 = 0x35
	// pllx_r_ck = vcox_ck / 56
	RCC_PLL3DIVR_PLL3R_Div56 = 0x37
	// pllx_r_ck = vcox_ck / 58
	RCC_PLL3DIVR_PLL3R_Div58 = 0x39
	// pllx_r_ck = vcox_ck / 60
	RCC_PLL3DIVR_PLL3R_Div60 = 0x3b
	// pllx_r_ck = vcox_ck / 62
	RCC_PLL3DIVR_PLL3R_Div62 = 0x3d
	// pllx_r_ck = vcox_ck / 64
	RCC_PLL3DIVR_PLL3R_Div64 = 0x3f
	// pllx_r_ck = vcox_ck / 66
	RCC_PLL3DIVR_PLL3R_Div66 = 0x41
	// pllx_r_ck = vcox_ck / 68
	RCC_PLL3DIVR_PLL3R_Div68 = 0x43
	// pllx_r_ck = vcox_ck / 70
	RCC_PLL3DIVR_PLL3R_Div70 = 0x45
	// pllx_r_ck = vcox_ck / 72
	RCC_PLL3DIVR_PLL3R_Div72 = 0x47
	// pllx_r_ck = vcox_ck / 74
	RCC_PLL3DIVR_PLL3R_Div74 = 0x49
	// pllx_r_ck = vcox_ck / 76
	RCC_PLL3DIVR_PLL3R_Div76 = 0x4b
	// pllx_r_ck = vcox_ck / 78
	RCC_PLL3DIVR_PLL3R_Div78 = 0x4d
	// pllx_r_ck = vcox_ck / 80
	RCC_PLL3DIVR_PLL3R_Div80 = 0x4f
	// pllx_r_ck = vcox_ck / 82
	RCC_PLL3DIVR_PLL3R_Div82 = 0x51
	// pllx_r_ck = vcox_ck / 84
	RCC_PLL3DIVR_PLL3R_Div84 = 0x53
	// pllx_r_ck = vcox_ck / 86
	RCC_PLL3DIVR_PLL3R_Div86 = 0x55
	// pllx_r_ck = vcox_ck / 88
	RCC_PLL3DIVR_PLL3R_Div88 = 0x57
	// pllx_r_ck = vcox_ck / 90
	RCC_PLL3DIVR_PLL3R_Div90 = 0x59
	// pllx_r_ck = vcox_ck / 92
	RCC_PLL3DIVR_PLL3R_Div92 = 0x5b
	// pllx_r_ck = vcox_ck / 94
	RCC_PLL3DIVR_PLL3R_Div94 = 0x5d
	// pllx_r_ck = vcox_ck / 96
	RCC_PLL3DIVR_PLL3R_Div96 = 0x5f
	// pllx_r_ck = vcox_ck / 98
	RCC_PLL3DIVR_PLL3R_Div98 = 0x61
	// pllx_r_ck = vcox_ck / 100
	RCC_PLL3DIVR_PLL3R_Div100 = 0x63
	// pllx_r_ck = vcox_ck / 102
	RCC_PLL3DIVR_PLL3R_Div102 = 0x65
	// pllx_r_ck = vcox_ck / 104
	RCC_PLL3DIVR_PLL3R_Div104 = 0x67
	// pllx_r_ck = vcox_ck / 106
	RCC_PLL3DIVR_PLL3R_Div106 = 0x69
	// pllx_r_ck = vcox_ck / 108
	RCC_PLL3DIVR_PLL3R_Div108 = 0x6b
	// pllx_r_ck = vcox_ck / 110
	RCC_PLL3DIVR_PLL3R_Div110 = 0x6d
	// pllx_r_ck = vcox_ck / 112
	RCC_PLL3DIVR_PLL3R_Div112 = 0x6f
	// pllx_r_ck = vcox_ck / 114
	RCC_PLL3DIVR_PLL3R_Div114 = 0x71
	// pllx_r_ck = vcox_ck / 116
	RCC_PLL3DIVR_PLL3R_Div116 = 0x73
	// pllx_r_ck = vcox_ck / 118
	RCC_PLL3DIVR_PLL3R_Div118 = 0x75
	// pllx_r_ck = vcox_ck / 120
	RCC_PLL3DIVR_PLL3R_Div120 = 0x77
	// pllx_r_ck = vcox_ck / 122
	RCC_PLL3DIVR_PLL3R_Div122 = 0x79
	// pllx_r_ck = vcox_ck / 124
	RCC_PLL3DIVR_PLL3R_Div124 = 0x7b
	// pllx_r_ck = vcox_ck / 126
	RCC_PLL3DIVR_PLL3R_Div126 = 0x7d
	// pllx_r_ck = vcox_ck / 128
	RCC_PLL3DIVR_PLL3R_Div128 = 0x7f

	// PLL3FRACR: RCC PLL3 fractional divider register
	// Position of PLL3FRACN field.
	RCC_PLL3FRACR_PLL3FRACN_Pos = 0x3
	// Bit mask of PLL3FRACN field.
	RCC_PLL3FRACR_PLL3FRACN_Msk = 0xfff8

	// CIER: RCC clock interrupt enable register
	// Position of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Pos = 0x0
	// Bit mask of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Msk = 0x1
	// Bit LSIRDYIE.
	RCC_CIER_LSIRDYIE = 0x1
	// Interrupt disabled
	RCC_CIER_LSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_LSIRDYIE_Enabled = 0x1
	// Position of LSERDYIE field.
	RCC_CIER_LSERDYIE_Pos = 0x1
	// Bit mask of LSERDYIE field.
	RCC_CIER_LSERDYIE_Msk = 0x2
	// Bit LSERDYIE.
	RCC_CIER_LSERDYIE = 0x2
	// Interrupt disabled
	RCC_CIER_LSERDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_LSERDYIE_Enabled = 0x1
	// Position of MSISRDYIE field.
	RCC_CIER_MSISRDYIE_Pos = 0x2
	// Bit mask of MSISRDYIE field.
	RCC_CIER_MSISRDYIE_Msk = 0x4
	// Bit MSISRDYIE.
	RCC_CIER_MSISRDYIE = 0x4
	// Interrupt disabled
	RCC_CIER_MSISRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_MSISRDYIE_Enabled = 0x1
	// Position of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Pos = 0x3
	// Bit mask of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Msk = 0x8
	// Bit HSIRDYIE.
	RCC_CIER_HSIRDYIE = 0x8
	// Interrupt disabled
	RCC_CIER_HSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSIRDYIE_Enabled = 0x1
	// Position of HSERDYIE field.
	RCC_CIER_HSERDYIE_Pos = 0x4
	// Bit mask of HSERDYIE field.
	RCC_CIER_HSERDYIE_Msk = 0x10
	// Bit HSERDYIE.
	RCC_CIER_HSERDYIE = 0x10
	// Interrupt disabled
	RCC_CIER_HSERDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSERDYIE_Enabled = 0x1
	// Position of HSI48RDYIE field.
	RCC_CIER_HSI48RDYIE_Pos = 0x5
	// Bit mask of HSI48RDYIE field.
	RCC_CIER_HSI48RDYIE_Msk = 0x20
	// Bit HSI48RDYIE.
	RCC_CIER_HSI48RDYIE = 0x20
	// Interrupt disabled
	RCC_CIER_HSI48RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_HSI48RDYIE_Enabled = 0x1
	// Position of PLL1RDYIE field.
	RCC_CIER_PLL1RDYIE_Pos = 0x6
	// Bit mask of PLL1RDYIE field.
	RCC_CIER_PLL1RDYIE_Msk = 0x40
	// Bit PLL1RDYIE.
	RCC_CIER_PLL1RDYIE = 0x40
	// Interrupt disabled
	RCC_CIER_PLL1RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_PLL1RDYIE_Enabled = 0x1
	// Position of PLL2RDYIE field.
	RCC_CIER_PLL2RDYIE_Pos = 0x7
	// Bit mask of PLL2RDYIE field.
	RCC_CIER_PLL2RDYIE_Msk = 0x80
	// Bit PLL2RDYIE.
	RCC_CIER_PLL2RDYIE = 0x80
	// Interrupt disabled
	RCC_CIER_PLL2RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_PLL2RDYIE_Enabled = 0x1
	// Position of PLL3RDYIE field.
	RCC_CIER_PLL3RDYIE_Pos = 0x8
	// Bit mask of PLL3RDYIE field.
	RCC_CIER_PLL3RDYIE_Msk = 0x100
	// Bit PLL3RDYIE.
	RCC_CIER_PLL3RDYIE = 0x100
	// Interrupt disabled
	RCC_CIER_PLL3RDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_PLL3RDYIE_Enabled = 0x1
	// Position of MSIKRDYIE field.
	RCC_CIER_MSIKRDYIE_Pos = 0xb
	// Bit mask of MSIKRDYIE field.
	RCC_CIER_MSIKRDYIE_Msk = 0x800
	// Bit MSIKRDYIE.
	RCC_CIER_MSIKRDYIE = 0x800
	// Interrupt disabled
	RCC_CIER_MSIKRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_MSIKRDYIE_Enabled = 0x1
	// Position of SHSIRDYIE field.
	RCC_CIER_SHSIRDYIE_Pos = 0xc
	// Bit mask of SHSIRDYIE field.
	RCC_CIER_SHSIRDYIE_Msk = 0x1000
	// Bit SHSIRDYIE.
	RCC_CIER_SHSIRDYIE = 0x1000
	// Interrupt disabled
	RCC_CIER_SHSIRDYIE_Disabled = 0x0
	// Interrupt enabled
	RCC_CIER_SHSIRDYIE_Enabled = 0x1

	// CIFR: RCC clock interrupt flag register
	// Position of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Pos = 0x0
	// Bit mask of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Msk = 0x1
	// Bit LSIRDYF.
	RCC_CIFR_LSIRDYF = 0x1
	// No clock ready interrupt
	RCC_CIFR_LSIRDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_LSIRDYF_Interrupted = 0x1
	// Position of LSERDYF field.
	RCC_CIFR_LSERDYF_Pos = 0x1
	// Bit mask of LSERDYF field.
	RCC_CIFR_LSERDYF_Msk = 0x2
	// Bit LSERDYF.
	RCC_CIFR_LSERDYF = 0x2
	// No clock ready interrupt
	RCC_CIFR_LSERDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_LSERDYF_Interrupted = 0x1
	// Position of MSISRDYF field.
	RCC_CIFR_MSISRDYF_Pos = 0x2
	// Bit mask of MSISRDYF field.
	RCC_CIFR_MSISRDYF_Msk = 0x4
	// Bit MSISRDYF.
	RCC_CIFR_MSISRDYF = 0x4
	// No clock ready interrupt
	RCC_CIFR_MSISRDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_MSISRDYF_Interrupted = 0x1
	// Position of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Pos = 0x3
	// Bit mask of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Msk = 0x8
	// Bit HSIRDYF.
	RCC_CIFR_HSIRDYF = 0x8
	// No clock ready interrupt
	RCC_CIFR_HSIRDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_HSIRDYF_Interrupted = 0x1
	// Position of HSERDYF field.
	RCC_CIFR_HSERDYF_Pos = 0x4
	// Bit mask of HSERDYF field.
	RCC_CIFR_HSERDYF_Msk = 0x10
	// Bit HSERDYF.
	RCC_CIFR_HSERDYF = 0x10
	// No clock ready interrupt
	RCC_CIFR_HSERDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_HSERDYF_Interrupted = 0x1
	// Position of HSI48RDYF field.
	RCC_CIFR_HSI48RDYF_Pos = 0x5
	// Bit mask of HSI48RDYF field.
	RCC_CIFR_HSI48RDYF_Msk = 0x20
	// Bit HSI48RDYF.
	RCC_CIFR_HSI48RDYF = 0x20
	// No clock ready interrupt
	RCC_CIFR_HSI48RDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_HSI48RDYF_Interrupted = 0x1
	// Position of PLL1RDYF field.
	RCC_CIFR_PLL1RDYF_Pos = 0x6
	// Bit mask of PLL1RDYF field.
	RCC_CIFR_PLL1RDYF_Msk = 0x40
	// Bit PLL1RDYF.
	RCC_CIFR_PLL1RDYF = 0x40
	// No clock ready interrupt
	RCC_CIFR_PLL1RDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_PLL1RDYF_Interrupted = 0x1
	// Position of PLL2RDYF field.
	RCC_CIFR_PLL2RDYF_Pos = 0x7
	// Bit mask of PLL2RDYF field.
	RCC_CIFR_PLL2RDYF_Msk = 0x80
	// Bit PLL2RDYF.
	RCC_CIFR_PLL2RDYF = 0x80
	// No clock ready interrupt
	RCC_CIFR_PLL2RDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_PLL2RDYF_Interrupted = 0x1
	// Position of PLL3RDYF field.
	RCC_CIFR_PLL3RDYF_Pos = 0x8
	// Bit mask of PLL3RDYF field.
	RCC_CIFR_PLL3RDYF_Msk = 0x100
	// Bit PLL3RDYF.
	RCC_CIFR_PLL3RDYF = 0x100
	// No clock ready interrupt
	RCC_CIFR_PLL3RDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_PLL3RDYF_Interrupted = 0x1
	// Position of CSSF field.
	RCC_CIFR_CSSF_Pos = 0xa
	// Bit mask of CSSF field.
	RCC_CIFR_CSSF_Msk = 0x400
	// Bit CSSF.
	RCC_CIFR_CSSF = 0x400
	// Position of MSIKRDYF field.
	RCC_CIFR_MSIKRDYF_Pos = 0xb
	// Bit mask of MSIKRDYF field.
	RCC_CIFR_MSIKRDYF_Msk = 0x800
	// Bit MSIKRDYF.
	RCC_CIFR_MSIKRDYF = 0x800
	// No clock ready interrupt
	RCC_CIFR_MSIKRDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_MSIKRDYF_Interrupted = 0x1
	// Position of SHSIRDYF field.
	RCC_CIFR_SHSIRDYF_Pos = 0xc
	// Bit mask of SHSIRDYF field.
	RCC_CIFR_SHSIRDYF_Msk = 0x1000
	// Bit SHSIRDYF.
	RCC_CIFR_SHSIRDYF = 0x1000
	// No clock ready interrupt
	RCC_CIFR_SHSIRDYF_NotInterrupted = 0x0
	// Clock ready interrupt
	RCC_CIFR_SHSIRDYF_Interrupted = 0x1

	// CICR: RCC clock interrupt clear register
	// Position of LSIRDYC field.
	RCC_CICR_LSIRDYC_Pos = 0x0
	// Bit mask of LSIRDYC field.
	RCC_CICR_LSIRDYC_Msk = 0x1
	// Bit LSIRDYC.
	RCC_CICR_LSIRDYC = 0x1
	// Clear flag
	RCC_CICR_LSIRDYC_Clear = 0x1
	// Position of LSERDYC field.
	RCC_CICR_LSERDYC_Pos = 0x1
	// Bit mask of LSERDYC field.
	RCC_CICR_LSERDYC_Msk = 0x2
	// Bit LSERDYC.
	RCC_CICR_LSERDYC = 0x2
	// Clear flag
	RCC_CICR_LSERDYC_Clear = 0x1
	// Position of MSISRDYC field.
	RCC_CICR_MSISRDYC_Pos = 0x2
	// Bit mask of MSISRDYC field.
	RCC_CICR_MSISRDYC_Msk = 0x4
	// Bit MSISRDYC.
	RCC_CICR_MSISRDYC = 0x4
	// Clear flag
	RCC_CICR_MSISRDYC_Clear = 0x1
	// Position of HSIRDYC field.
	RCC_CICR_HSIRDYC_Pos = 0x3
	// Bit mask of HSIRDYC field.
	RCC_CICR_HSIRDYC_Msk = 0x8
	// Bit HSIRDYC.
	RCC_CICR_HSIRDYC = 0x8
	// Clear flag
	RCC_CICR_HSIRDYC_Clear = 0x1
	// Position of HSERDYC field.
	RCC_CICR_HSERDYC_Pos = 0x4
	// Bit mask of HSERDYC field.
	RCC_CICR_HSERDYC_Msk = 0x10
	// Bit HSERDYC.
	RCC_CICR_HSERDYC = 0x10
	// Clear flag
	RCC_CICR_HSERDYC_Clear = 0x1
	// Position of HSI48RDYC field.
	RCC_CICR_HSI48RDYC_Pos = 0x5
	// Bit mask of HSI48RDYC field.
	RCC_CICR_HSI48RDYC_Msk = 0x20
	// Bit HSI48RDYC.
	RCC_CICR_HSI48RDYC = 0x20
	// Clear flag
	RCC_CICR_HSI48RDYC_Clear = 0x1
	// Position of PLL1RDYC field.
	RCC_CICR_PLL1RDYC_Pos = 0x6
	// Bit mask of PLL1RDYC field.
	RCC_CICR_PLL1RDYC_Msk = 0x40
	// Bit PLL1RDYC.
	RCC_CICR_PLL1RDYC = 0x40
	// Clear flag
	RCC_CICR_PLL1RDYC_Clear = 0x1
	// Position of PLL2RDYC field.
	RCC_CICR_PLL2RDYC_Pos = 0x7
	// Bit mask of PLL2RDYC field.
	RCC_CICR_PLL2RDYC_Msk = 0x80
	// Bit PLL2RDYC.
	RCC_CICR_PLL2RDYC = 0x80
	// Clear flag
	RCC_CICR_PLL2RDYC_Clear = 0x1
	// Position of PLL3RDYC field.
	RCC_CICR_PLL3RDYC_Pos = 0x8
	// Bit mask of PLL3RDYC field.
	RCC_CICR_PLL3RDYC_Msk = 0x100
	// Bit PLL3RDYC.
	RCC_CICR_PLL3RDYC = 0x100
	// Clear flag
	RCC_CICR_PLL3RDYC_Clear = 0x1
	// Position of CSSC field.
	RCC_CICR_CSSC_Pos = 0xa
	// Bit mask of CSSC field.
	RCC_CICR_CSSC_Msk = 0x400
	// Bit CSSC.
	RCC_CICR_CSSC = 0x400
	// Position of MSIKRDYC field.
	RCC_CICR_MSIKRDYC_Pos = 0xb
	// Bit mask of MSIKRDYC field.
	RCC_CICR_MSIKRDYC_Msk = 0x800
	// Bit MSIKRDYC.
	RCC_CICR_MSIKRDYC = 0x800
	// Clear flag
	RCC_CICR_MSIKRDYC_Clear = 0x1
	// Position of SHSIRDYC field.
	RCC_CICR_SHSIRDYC_Pos = 0xc
	// Bit mask of SHSIRDYC field.
	RCC_CICR_SHSIRDYC_Msk = 0x1000
	// Bit SHSIRDYC.
	RCC_CICR_SHSIRDYC = 0x1000
	// Clear flag
	RCC_CICR_SHSIRDYC_Clear = 0x1

	// AHB1RSTR: RCC AHB1 peripheral reset register
	// Position of GPDMA1RST field.
	RCC_AHB1RSTR_GPDMA1RST_Pos = 0x0
	// Bit mask of GPDMA1RST field.
	RCC_AHB1RSTR_GPDMA1RST_Msk = 0x1
	// Bit GPDMA1RST.
	RCC_AHB1RSTR_GPDMA1RST = 0x1
	// No effect
	RCC_AHB1RSTR_GPDMA1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_GPDMA1RST_Reset = 0x1
	// Position of CORDICRST field.
	RCC_AHB1RSTR_CORDICRST_Pos = 0x1
	// Bit mask of CORDICRST field.
	RCC_AHB1RSTR_CORDICRST_Msk = 0x2
	// Bit CORDICRST.
	RCC_AHB1RSTR_CORDICRST = 0x2
	// No effect
	RCC_AHB1RSTR_CORDICRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_CORDICRST_Reset = 0x1
	// Position of FMACRST field.
	RCC_AHB1RSTR_FMACRST_Pos = 0x2
	// Bit mask of FMACRST field.
	RCC_AHB1RSTR_FMACRST_Msk = 0x4
	// Bit FMACRST.
	RCC_AHB1RSTR_FMACRST = 0x4
	// No effect
	RCC_AHB1RSTR_FMACRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_FMACRST_Reset = 0x1
	// Position of MDF1RST field.
	RCC_AHB1RSTR_MDF1RST_Pos = 0x3
	// Bit mask of MDF1RST field.
	RCC_AHB1RSTR_MDF1RST_Msk = 0x8
	// Bit MDF1RST.
	RCC_AHB1RSTR_MDF1RST = 0x8
	// No effect
	RCC_AHB1RSTR_MDF1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_MDF1RST_Reset = 0x1
	// Position of CRCRST field.
	RCC_AHB1RSTR_CRCRST_Pos = 0xc
	// Bit mask of CRCRST field.
	RCC_AHB1RSTR_CRCRST_Msk = 0x1000
	// Bit CRCRST.
	RCC_AHB1RSTR_CRCRST = 0x1000
	// No effect
	RCC_AHB1RSTR_CRCRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_CRCRST_Reset = 0x1
	// Position of JPEGRST field.
	RCC_AHB1RSTR_JPEGRST_Pos = 0xf
	// Bit mask of JPEGRST field.
	RCC_AHB1RSTR_JPEGRST_Msk = 0x8000
	// Bit JPEGRST.
	RCC_AHB1RSTR_JPEGRST = 0x8000
	// No effect
	RCC_AHB1RSTR_JPEGRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_JPEGRST_Reset = 0x1
	// Position of TSCRST field.
	RCC_AHB1RSTR_TSCRST_Pos = 0x10
	// Bit mask of TSCRST field.
	RCC_AHB1RSTR_TSCRST_Msk = 0x10000
	// Bit TSCRST.
	RCC_AHB1RSTR_TSCRST = 0x10000
	// No effect
	RCC_AHB1RSTR_TSCRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_TSCRST_Reset = 0x1
	// Position of RAMCFGRST field.
	RCC_AHB1RSTR_RAMCFGRST_Pos = 0x11
	// Bit mask of RAMCFGRST field.
	RCC_AHB1RSTR_RAMCFGRST_Msk = 0x20000
	// Bit RAMCFGRST.
	RCC_AHB1RSTR_RAMCFGRST = 0x20000
	// No effect
	RCC_AHB1RSTR_RAMCFGRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_RAMCFGRST_Reset = 0x1
	// Position of DMA2DRST field.
	RCC_AHB1RSTR_DMA2DRST_Pos = 0x12
	// Bit mask of DMA2DRST field.
	RCC_AHB1RSTR_DMA2DRST_Msk = 0x40000
	// Bit DMA2DRST.
	RCC_AHB1RSTR_DMA2DRST = 0x40000
	// No effect
	RCC_AHB1RSTR_DMA2DRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_DMA2DRST_Reset = 0x1
	// Position of GFXMMURST field.
	RCC_AHB1RSTR_GFXMMURST_Pos = 0x13
	// Bit mask of GFXMMURST field.
	RCC_AHB1RSTR_GFXMMURST_Msk = 0x80000
	// Bit GFXMMURST.
	RCC_AHB1RSTR_GFXMMURST = 0x80000
	// No effect
	RCC_AHB1RSTR_GFXMMURST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_GFXMMURST_Reset = 0x1
	// Position of GPU2DRST field.
	RCC_AHB1RSTR_GPU2DRST_Pos = 0x14
	// Bit mask of GPU2DRST field.
	RCC_AHB1RSTR_GPU2DRST_Msk = 0x100000
	// Bit GPU2DRST.
	RCC_AHB1RSTR_GPU2DRST = 0x100000
	// No effect
	RCC_AHB1RSTR_GPU2DRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB1RSTR_GPU2DRST_Reset = 0x1

	// AHB2RSTR1: RCC AHB2 peripheral reset register 1
	// Position of GPIOARST field.
	RCC_AHB2RSTR1_GPIOARST_Pos = 0x0
	// Bit mask of GPIOARST field.
	RCC_AHB2RSTR1_GPIOARST_Msk = 0x1
	// Bit GPIOARST.
	RCC_AHB2RSTR1_GPIOARST = 0x1
	// No effect
	RCC_AHB2RSTR1_GPIOARST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOARST_Reset = 0x1
	// Position of GPIOBRST field.
	RCC_AHB2RSTR1_GPIOBRST_Pos = 0x1
	// Bit mask of GPIOBRST field.
	RCC_AHB2RSTR1_GPIOBRST_Msk = 0x2
	// Bit GPIOBRST.
	RCC_AHB2RSTR1_GPIOBRST = 0x2
	// No effect
	RCC_AHB2RSTR1_GPIOBRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOBRST_Reset = 0x1
	// Position of GPIOCRST field.
	RCC_AHB2RSTR1_GPIOCRST_Pos = 0x2
	// Bit mask of GPIOCRST field.
	RCC_AHB2RSTR1_GPIOCRST_Msk = 0x4
	// Bit GPIOCRST.
	RCC_AHB2RSTR1_GPIOCRST = 0x4
	// No effect
	RCC_AHB2RSTR1_GPIOCRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOCRST_Reset = 0x1
	// Position of GPIODRST field.
	RCC_AHB2RSTR1_GPIODRST_Pos = 0x3
	// Bit mask of GPIODRST field.
	RCC_AHB2RSTR1_GPIODRST_Msk = 0x8
	// Bit GPIODRST.
	RCC_AHB2RSTR1_GPIODRST = 0x8
	// No effect
	RCC_AHB2RSTR1_GPIODRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIODRST_Reset = 0x1
	// Position of GPIOERST field.
	RCC_AHB2RSTR1_GPIOERST_Pos = 0x4
	// Bit mask of GPIOERST field.
	RCC_AHB2RSTR1_GPIOERST_Msk = 0x10
	// Bit GPIOERST.
	RCC_AHB2RSTR1_GPIOERST = 0x10
	// No effect
	RCC_AHB2RSTR1_GPIOERST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOERST_Reset = 0x1
	// Position of GPIOFRST field.
	RCC_AHB2RSTR1_GPIOFRST_Pos = 0x5
	// Bit mask of GPIOFRST field.
	RCC_AHB2RSTR1_GPIOFRST_Msk = 0x20
	// Bit GPIOFRST.
	RCC_AHB2RSTR1_GPIOFRST = 0x20
	// No effect
	RCC_AHB2RSTR1_GPIOFRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOFRST_Reset = 0x1
	// Position of GPIOGRST field.
	RCC_AHB2RSTR1_GPIOGRST_Pos = 0x6
	// Bit mask of GPIOGRST field.
	RCC_AHB2RSTR1_GPIOGRST_Msk = 0x40
	// Bit GPIOGRST.
	RCC_AHB2RSTR1_GPIOGRST = 0x40
	// No effect
	RCC_AHB2RSTR1_GPIOGRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOGRST_Reset = 0x1
	// Position of GPIOHRST field.
	RCC_AHB2RSTR1_GPIOHRST_Pos = 0x7
	// Bit mask of GPIOHRST field.
	RCC_AHB2RSTR1_GPIOHRST_Msk = 0x80
	// Bit GPIOHRST.
	RCC_AHB2RSTR1_GPIOHRST = 0x80
	// No effect
	RCC_AHB2RSTR1_GPIOHRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOHRST_Reset = 0x1
	// Position of GPIOIRST field.
	RCC_AHB2RSTR1_GPIOIRST_Pos = 0x8
	// Bit mask of GPIOIRST field.
	RCC_AHB2RSTR1_GPIOIRST_Msk = 0x100
	// Bit GPIOIRST.
	RCC_AHB2RSTR1_GPIOIRST = 0x100
	// No effect
	RCC_AHB2RSTR1_GPIOIRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOIRST_Reset = 0x1
	// Position of GPIOJRST field.
	RCC_AHB2RSTR1_GPIOJRST_Pos = 0x9
	// Bit mask of GPIOJRST field.
	RCC_AHB2RSTR1_GPIOJRST_Msk = 0x200
	// Bit GPIOJRST.
	RCC_AHB2RSTR1_GPIOJRST = 0x200
	// No effect
	RCC_AHB2RSTR1_GPIOJRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_GPIOJRST_Reset = 0x1
	// Position of ADC12RST field.
	RCC_AHB2RSTR1_ADC12RST_Pos = 0xa
	// Bit mask of ADC12RST field.
	RCC_AHB2RSTR1_ADC12RST_Msk = 0x400
	// Bit ADC12RST.
	RCC_AHB2RSTR1_ADC12RST = 0x400
	// No effect
	RCC_AHB2RSTR1_ADC12RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_ADC12RST_Reset = 0x1
	// Position of DCMI_PSSIRST field.
	RCC_AHB2RSTR1_DCMI_PSSIRST_Pos = 0xc
	// Bit mask of DCMI_PSSIRST field.
	RCC_AHB2RSTR1_DCMI_PSSIRST_Msk = 0x1000
	// Bit DCMI_PSSIRST.
	RCC_AHB2RSTR1_DCMI_PSSIRST = 0x1000
	// No effect
	RCC_AHB2RSTR1_DCMI_PSSIRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_DCMI_PSSIRST_Reset = 0x1
	// Position of OTGRST field.
	RCC_AHB2RSTR1_OTGRST_Pos = 0xe
	// Bit mask of OTGRST field.
	RCC_AHB2RSTR1_OTGRST_Msk = 0x4000
	// Bit OTGRST.
	RCC_AHB2RSTR1_OTGRST = 0x4000
	// No effect
	RCC_AHB2RSTR1_OTGRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_OTGRST_Reset = 0x1
	// Position of AESRST field.
	RCC_AHB2RSTR1_AESRST_Pos = 0x10
	// Bit mask of AESRST field.
	RCC_AHB2RSTR1_AESRST_Msk = 0x10000
	// Bit AESRST.
	RCC_AHB2RSTR1_AESRST = 0x10000
	// No effect
	RCC_AHB2RSTR1_AESRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_AESRST_Reset = 0x1
	// Position of HASHRST field.
	RCC_AHB2RSTR1_HASHRST_Pos = 0x11
	// Bit mask of HASHRST field.
	RCC_AHB2RSTR1_HASHRST_Msk = 0x20000
	// Bit HASHRST.
	RCC_AHB2RSTR1_HASHRST = 0x20000
	// No effect
	RCC_AHB2RSTR1_HASHRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_HASHRST_Reset = 0x1
	// Position of RNGRST field.
	RCC_AHB2RSTR1_RNGRST_Pos = 0x12
	// Bit mask of RNGRST field.
	RCC_AHB2RSTR1_RNGRST_Msk = 0x40000
	// Bit RNGRST.
	RCC_AHB2RSTR1_RNGRST = 0x40000
	// No effect
	RCC_AHB2RSTR1_RNGRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_RNGRST_Reset = 0x1
	// Position of PKARST field.
	RCC_AHB2RSTR1_PKARST_Pos = 0x13
	// Bit mask of PKARST field.
	RCC_AHB2RSTR1_PKARST_Msk = 0x80000
	// Bit PKARST.
	RCC_AHB2RSTR1_PKARST = 0x80000
	// No effect
	RCC_AHB2RSTR1_PKARST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_PKARST_Reset = 0x1
	// Position of SAESRST field.
	RCC_AHB2RSTR1_SAESRST_Pos = 0x14
	// Bit mask of SAESRST field.
	RCC_AHB2RSTR1_SAESRST_Msk = 0x100000
	// Bit SAESRST.
	RCC_AHB2RSTR1_SAESRST = 0x100000
	// No effect
	RCC_AHB2RSTR1_SAESRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_SAESRST_Reset = 0x1
	// Position of OCTOSPIMRST field.
	RCC_AHB2RSTR1_OCTOSPIMRST_Pos = 0x15
	// Bit mask of OCTOSPIMRST field.
	RCC_AHB2RSTR1_OCTOSPIMRST_Msk = 0x200000
	// Bit OCTOSPIMRST.
	RCC_AHB2RSTR1_OCTOSPIMRST = 0x200000
	// No effect
	RCC_AHB2RSTR1_OCTOSPIMRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_OCTOSPIMRST_Reset = 0x1
	// Position of OTFDEC1RST field.
	RCC_AHB2RSTR1_OTFDEC1RST_Pos = 0x17
	// Bit mask of OTFDEC1RST field.
	RCC_AHB2RSTR1_OTFDEC1RST_Msk = 0x800000
	// Bit OTFDEC1RST.
	RCC_AHB2RSTR1_OTFDEC1RST = 0x800000
	// No effect
	RCC_AHB2RSTR1_OTFDEC1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_OTFDEC1RST_Reset = 0x1
	// Position of OTFDEC2RST field.
	RCC_AHB2RSTR1_OTFDEC2RST_Pos = 0x18
	// Bit mask of OTFDEC2RST field.
	RCC_AHB2RSTR1_OTFDEC2RST_Msk = 0x1000000
	// Bit OTFDEC2RST.
	RCC_AHB2RSTR1_OTFDEC2RST = 0x1000000
	// No effect
	RCC_AHB2RSTR1_OTFDEC2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_OTFDEC2RST_Reset = 0x1
	// Position of SDMMC1RST field.
	RCC_AHB2RSTR1_SDMMC1RST_Pos = 0x1b
	// Bit mask of SDMMC1RST field.
	RCC_AHB2RSTR1_SDMMC1RST_Msk = 0x8000000
	// Bit SDMMC1RST.
	RCC_AHB2RSTR1_SDMMC1RST = 0x8000000
	// No effect
	RCC_AHB2RSTR1_SDMMC1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_SDMMC1RST_Reset = 0x1
	// Position of SDMMC2RST field.
	RCC_AHB2RSTR1_SDMMC2RST_Pos = 0x1c
	// Bit mask of SDMMC2RST field.
	RCC_AHB2RSTR1_SDMMC2RST_Msk = 0x10000000
	// Bit SDMMC2RST.
	RCC_AHB2RSTR1_SDMMC2RST = 0x10000000
	// No effect
	RCC_AHB2RSTR1_SDMMC2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR1_SDMMC2RST_Reset = 0x1

	// AHB2RSTR2: RCC AHB2 peripheral reset register 2
	// Position of FSMCRST field.
	RCC_AHB2RSTR2_FSMCRST_Pos = 0x0
	// Bit mask of FSMCRST field.
	RCC_AHB2RSTR2_FSMCRST_Msk = 0x1
	// Bit FSMCRST.
	RCC_AHB2RSTR2_FSMCRST = 0x1
	// No effect
	RCC_AHB2RSTR2_FSMCRST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR2_FSMCRST_Reset = 0x1
	// Position of OCTOSPI1RST field.
	RCC_AHB2RSTR2_OCTOSPI1RST_Pos = 0x4
	// Bit mask of OCTOSPI1RST field.
	RCC_AHB2RSTR2_OCTOSPI1RST_Msk = 0x10
	// Bit OCTOSPI1RST.
	RCC_AHB2RSTR2_OCTOSPI1RST = 0x10
	// No effect
	RCC_AHB2RSTR2_OCTOSPI1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR2_OCTOSPI1RST_Reset = 0x1
	// Position of OCTOSPI2RST field.
	RCC_AHB2RSTR2_OCTOSPI2RST_Pos = 0x8
	// Bit mask of OCTOSPI2RST field.
	RCC_AHB2RSTR2_OCTOSPI2RST_Msk = 0x100
	// Bit OCTOSPI2RST.
	RCC_AHB2RSTR2_OCTOSPI2RST = 0x100
	// No effect
	RCC_AHB2RSTR2_OCTOSPI2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR2_OCTOSPI2RST_Reset = 0x1
	// Position of HSPI1RST field.
	RCC_AHB2RSTR2_HSPI1RST_Pos = 0xc
	// Bit mask of HSPI1RST field.
	RCC_AHB2RSTR2_HSPI1RST_Msk = 0x1000
	// Bit HSPI1RST.
	RCC_AHB2RSTR2_HSPI1RST = 0x1000
	// No effect
	RCC_AHB2RSTR2_HSPI1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB2RSTR2_HSPI1RST_Reset = 0x1

	// AHB3RSTR: RCC AHB3 peripheral reset register
	// Position of LPGPIO1RST field.
	RCC_AHB3RSTR_LPGPIO1RST_Pos = 0x0
	// Bit mask of LPGPIO1RST field.
	RCC_AHB3RSTR_LPGPIO1RST_Msk = 0x1
	// Bit LPGPIO1RST.
	RCC_AHB3RSTR_LPGPIO1RST = 0x1
	// No effect
	RCC_AHB3RSTR_LPGPIO1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB3RSTR_LPGPIO1RST_Reset = 0x1
	// Position of ADC4RST field.
	RCC_AHB3RSTR_ADC4RST_Pos = 0x5
	// Bit mask of ADC4RST field.
	RCC_AHB3RSTR_ADC4RST_Msk = 0x20
	// Bit ADC4RST.
	RCC_AHB3RSTR_ADC4RST = 0x20
	// No effect
	RCC_AHB3RSTR_ADC4RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB3RSTR_ADC4RST_Reset = 0x1
	// Position of DAC1RST field.
	RCC_AHB3RSTR_DAC1RST_Pos = 0x6
	// Bit mask of DAC1RST field.
	RCC_AHB3RSTR_DAC1RST_Msk = 0x40
	// Bit DAC1RST.
	RCC_AHB3RSTR_DAC1RST = 0x40
	// No effect
	RCC_AHB3RSTR_DAC1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB3RSTR_DAC1RST_Reset = 0x1
	// Position of LPDMA1RST field.
	RCC_AHB3RSTR_LPDMA1RST_Pos = 0x9
	// Bit mask of LPDMA1RST field.
	RCC_AHB3RSTR_LPDMA1RST_Msk = 0x200
	// Bit LPDMA1RST.
	RCC_AHB3RSTR_LPDMA1RST = 0x200
	// No effect
	RCC_AHB3RSTR_LPDMA1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB3RSTR_LPDMA1RST_Reset = 0x1
	// Position of ADF1RST field.
	RCC_AHB3RSTR_ADF1RST_Pos = 0xa
	// Bit mask of ADF1RST field.
	RCC_AHB3RSTR_ADF1RST_Msk = 0x400
	// Bit ADF1RST.
	RCC_AHB3RSTR_ADF1RST = 0x400
	// No effect
	RCC_AHB3RSTR_ADF1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_AHB3RSTR_ADF1RST_Reset = 0x1

	// APB1RSTR1: RCC APB1 peripheral reset register 1
	// Position of TIM2RST field.
	RCC_APB1RSTR1_TIM2RST_Pos = 0x0
	// Bit mask of TIM2RST field.
	RCC_APB1RSTR1_TIM2RST_Msk = 0x1
	// Bit TIM2RST.
	RCC_APB1RSTR1_TIM2RST = 0x1
	// No effect
	RCC_APB1RSTR1_TIM2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_TIM2RST_Reset = 0x1
	// Position of TIM3RST field.
	RCC_APB1RSTR1_TIM3RST_Pos = 0x1
	// Bit mask of TIM3RST field.
	RCC_APB1RSTR1_TIM3RST_Msk = 0x2
	// Bit TIM3RST.
	RCC_APB1RSTR1_TIM3RST = 0x2
	// No effect
	RCC_APB1RSTR1_TIM3RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_TIM3RST_Reset = 0x1
	// Position of TIM4RST field.
	RCC_APB1RSTR1_TIM4RST_Pos = 0x2
	// Bit mask of TIM4RST field.
	RCC_APB1RSTR1_TIM4RST_Msk = 0x4
	// Bit TIM4RST.
	RCC_APB1RSTR1_TIM4RST = 0x4
	// No effect
	RCC_APB1RSTR1_TIM4RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_TIM4RST_Reset = 0x1
	// Position of TIM5RST field.
	RCC_APB1RSTR1_TIM5RST_Pos = 0x3
	// Bit mask of TIM5RST field.
	RCC_APB1RSTR1_TIM5RST_Msk = 0x8
	// Bit TIM5RST.
	RCC_APB1RSTR1_TIM5RST = 0x8
	// No effect
	RCC_APB1RSTR1_TIM5RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_TIM5RST_Reset = 0x1
	// Position of TIM6RST field.
	RCC_APB1RSTR1_TIM6RST_Pos = 0x4
	// Bit mask of TIM6RST field.
	RCC_APB1RSTR1_TIM6RST_Msk = 0x10
	// Bit TIM6RST.
	RCC_APB1RSTR1_TIM6RST = 0x10
	// No effect
	RCC_APB1RSTR1_TIM6RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_TIM6RST_Reset = 0x1
	// Position of TIM7RST field.
	RCC_APB1RSTR1_TIM7RST_Pos = 0x5
	// Bit mask of TIM7RST field.
	RCC_APB1RSTR1_TIM7RST_Msk = 0x20
	// Bit TIM7RST.
	RCC_APB1RSTR1_TIM7RST = 0x20
	// No effect
	RCC_APB1RSTR1_TIM7RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_TIM7RST_Reset = 0x1
	// Position of SPI2RST field.
	RCC_APB1RSTR1_SPI2RST_Pos = 0xe
	// Bit mask of SPI2RST field.
	RCC_APB1RSTR1_SPI2RST_Msk = 0x4000
	// Bit SPI2RST.
	RCC_APB1RSTR1_SPI2RST = 0x4000
	// No effect
	RCC_APB1RSTR1_SPI2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_SPI2RST_Reset = 0x1
	// Position of USART2RST field.
	RCC_APB1RSTR1_USART2RST_Pos = 0x11
	// Bit mask of USART2RST field.
	RCC_APB1RSTR1_USART2RST_Msk = 0x20000
	// Bit USART2RST.
	RCC_APB1RSTR1_USART2RST = 0x20000
	// No effect
	RCC_APB1RSTR1_USART2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_USART2RST_Reset = 0x1
	// Position of USART3RST field.
	RCC_APB1RSTR1_USART3RST_Pos = 0x12
	// Bit mask of USART3RST field.
	RCC_APB1RSTR1_USART3RST_Msk = 0x40000
	// Bit USART3RST.
	RCC_APB1RSTR1_USART3RST = 0x40000
	// No effect
	RCC_APB1RSTR1_USART3RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_USART3RST_Reset = 0x1
	// Position of UART4RST field.
	RCC_APB1RSTR1_UART4RST_Pos = 0x13
	// Bit mask of UART4RST field.
	RCC_APB1RSTR1_UART4RST_Msk = 0x80000
	// Bit UART4RST.
	RCC_APB1RSTR1_UART4RST = 0x80000
	// No effect
	RCC_APB1RSTR1_UART4RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_UART4RST_Reset = 0x1
	// Position of UART5RST field.
	RCC_APB1RSTR1_UART5RST_Pos = 0x14
	// Bit mask of UART5RST field.
	RCC_APB1RSTR1_UART5RST_Msk = 0x100000
	// Bit UART5RST.
	RCC_APB1RSTR1_UART5RST = 0x100000
	// No effect
	RCC_APB1RSTR1_UART5RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_UART5RST_Reset = 0x1
	// Position of I2C1RST field.
	RCC_APB1RSTR1_I2C1RST_Pos = 0x15
	// Bit mask of I2C1RST field.
	RCC_APB1RSTR1_I2C1RST_Msk = 0x200000
	// Bit I2C1RST.
	RCC_APB1RSTR1_I2C1RST = 0x200000
	// No effect
	RCC_APB1RSTR1_I2C1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_I2C1RST_Reset = 0x1
	// Position of I2C2RST field.
	RCC_APB1RSTR1_I2C2RST_Pos = 0x16
	// Bit mask of I2C2RST field.
	RCC_APB1RSTR1_I2C2RST_Msk = 0x400000
	// Bit I2C2RST.
	RCC_APB1RSTR1_I2C2RST = 0x400000
	// No effect
	RCC_APB1RSTR1_I2C2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_I2C2RST_Reset = 0x1
	// Position of CRSRST field.
	RCC_APB1RSTR1_CRSRST_Pos = 0x18
	// Bit mask of CRSRST field.
	RCC_APB1RSTR1_CRSRST_Msk = 0x1000000
	// Bit CRSRST.
	RCC_APB1RSTR1_CRSRST = 0x1000000
	// No effect
	RCC_APB1RSTR1_CRSRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_CRSRST_Reset = 0x1
	// Position of USART6RST field.
	RCC_APB1RSTR1_USART6RST_Pos = 0x19
	// Bit mask of USART6RST field.
	RCC_APB1RSTR1_USART6RST_Msk = 0x2000000
	// Bit USART6RST.
	RCC_APB1RSTR1_USART6RST = 0x2000000
	// No effect
	RCC_APB1RSTR1_USART6RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR1_USART6RST_Reset = 0x1

	// APB1RSTR2: RCC APB1 peripheral reset register 2
	// Position of I2C4RST field.
	RCC_APB1RSTR2_I2C4RST_Pos = 0x1
	// Bit mask of I2C4RST field.
	RCC_APB1RSTR2_I2C4RST_Msk = 0x2
	// Bit I2C4RST.
	RCC_APB1RSTR2_I2C4RST = 0x2
	// No effect
	RCC_APB1RSTR2_I2C4RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR2_I2C4RST_Reset = 0x1
	// Position of LPTIM2RST field.
	RCC_APB1RSTR2_LPTIM2RST_Pos = 0x5
	// Bit mask of LPTIM2RST field.
	RCC_APB1RSTR2_LPTIM2RST_Msk = 0x20
	// Bit LPTIM2RST.
	RCC_APB1RSTR2_LPTIM2RST = 0x20
	// No effect
	RCC_APB1RSTR2_LPTIM2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR2_LPTIM2RST_Reset = 0x1
	// Position of I2C5RST field.
	RCC_APB1RSTR2_I2C5RST_Pos = 0x6
	// Bit mask of I2C5RST field.
	RCC_APB1RSTR2_I2C5RST_Msk = 0x40
	// Bit I2C5RST.
	RCC_APB1RSTR2_I2C5RST = 0x40
	// No effect
	RCC_APB1RSTR2_I2C5RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR2_I2C5RST_Reset = 0x1
	// Position of I2C6RST field.
	RCC_APB1RSTR2_I2C6RST_Pos = 0x7
	// Bit mask of I2C6RST field.
	RCC_APB1RSTR2_I2C6RST_Msk = 0x80
	// Bit I2C6RST.
	RCC_APB1RSTR2_I2C6RST = 0x80
	// No effect
	RCC_APB1RSTR2_I2C6RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR2_I2C6RST_Reset = 0x1
	// Position of FDCAN1RST field.
	RCC_APB1RSTR2_FDCAN1RST_Pos = 0x9
	// Bit mask of FDCAN1RST field.
	RCC_APB1RSTR2_FDCAN1RST_Msk = 0x200
	// Bit FDCAN1RST.
	RCC_APB1RSTR2_FDCAN1RST = 0x200
	// No effect
	RCC_APB1RSTR2_FDCAN1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR2_FDCAN1RST_Reset = 0x1
	// Position of UCPD1RST field.
	RCC_APB1RSTR2_UCPD1RST_Pos = 0x17
	// Bit mask of UCPD1RST field.
	RCC_APB1RSTR2_UCPD1RST_Msk = 0x800000
	// Bit UCPD1RST.
	RCC_APB1RSTR2_UCPD1RST = 0x800000
	// No effect
	RCC_APB1RSTR2_UCPD1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB1RSTR2_UCPD1RST_Reset = 0x1

	// APB2RSTR: RCC APB2 peripheral reset register
	// Position of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Pos = 0xb
	// Bit mask of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Msk = 0x800
	// Bit TIM1RST.
	RCC_APB2RSTR_TIM1RST = 0x800
	// No effect
	RCC_APB2RSTR_TIM1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_TIM1RST_Reset = 0x1
	// Position of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Pos = 0xc
	// Bit mask of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Msk = 0x1000
	// Bit SPI1RST.
	RCC_APB2RSTR_SPI1RST = 0x1000
	// No effect
	RCC_APB2RSTR_SPI1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_SPI1RST_Reset = 0x1
	// Position of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Pos = 0xd
	// Bit mask of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Msk = 0x2000
	// Bit TIM8RST.
	RCC_APB2RSTR_TIM8RST = 0x2000
	// No effect
	RCC_APB2RSTR_TIM8RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_TIM8RST_Reset = 0x1
	// Position of USART1RST field.
	RCC_APB2RSTR_USART1RST_Pos = 0xe
	// Bit mask of USART1RST field.
	RCC_APB2RSTR_USART1RST_Msk = 0x4000
	// Bit USART1RST.
	RCC_APB2RSTR_USART1RST = 0x4000
	// No effect
	RCC_APB2RSTR_USART1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_USART1RST_Reset = 0x1
	// Position of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Pos = 0x10
	// Bit mask of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Msk = 0x10000
	// Bit TIM15RST.
	RCC_APB2RSTR_TIM15RST = 0x10000
	// No effect
	RCC_APB2RSTR_TIM15RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_TIM15RST_Reset = 0x1
	// Position of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Pos = 0x11
	// Bit mask of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Msk = 0x20000
	// Bit TIM16RST.
	RCC_APB2RSTR_TIM16RST = 0x20000
	// No effect
	RCC_APB2RSTR_TIM16RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_TIM16RST_Reset = 0x1
	// Position of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Pos = 0x12
	// Bit mask of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Msk = 0x40000
	// Bit TIM17RST.
	RCC_APB2RSTR_TIM17RST = 0x40000
	// No effect
	RCC_APB2RSTR_TIM17RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_TIM17RST_Reset = 0x1
	// Position of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Pos = 0x15
	// Bit mask of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Msk = 0x200000
	// Bit SAI1RST.
	RCC_APB2RSTR_SAI1RST = 0x200000
	// No effect
	RCC_APB2RSTR_SAI1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_SAI1RST_Reset = 0x1
	// Position of SAI2RST field.
	RCC_APB2RSTR_SAI2RST_Pos = 0x16
	// Bit mask of SAI2RST field.
	RCC_APB2RSTR_SAI2RST_Msk = 0x400000
	// Bit SAI2RST.
	RCC_APB2RSTR_SAI2RST = 0x400000
	// No effect
	RCC_APB2RSTR_SAI2RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_SAI2RST_Reset = 0x1
	// Position of USBRST field.
	RCC_APB2RSTR_USBRST_Pos = 0x18
	// Bit mask of USBRST field.
	RCC_APB2RSTR_USBRST_Msk = 0x1000000
	// Bit USBRST.
	RCC_APB2RSTR_USBRST = 0x1000000
	// No effect
	RCC_APB2RSTR_USBRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_USBRST_Reset = 0x1
	// Position of GFXTIMRST field.
	RCC_APB2RSTR_GFXTIMRST_Pos = 0x19
	// Bit mask of GFXTIMRST field.
	RCC_APB2RSTR_GFXTIMRST_Msk = 0x2000000
	// Bit GFXTIMRST.
	RCC_APB2RSTR_GFXTIMRST = 0x2000000
	// No effect
	RCC_APB2RSTR_GFXTIMRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_GFXTIMRST_Reset = 0x1
	// Position of LTDCRST field.
	RCC_APB2RSTR_LTDCRST_Pos = 0x1a
	// Bit mask of LTDCRST field.
	RCC_APB2RSTR_LTDCRST_Msk = 0x4000000
	// Bit LTDCRST.
	RCC_APB2RSTR_LTDCRST = 0x4000000
	// No effect
	RCC_APB2RSTR_LTDCRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_LTDCRST_Reset = 0x1
	// Position of DSIRST field.
	RCC_APB2RSTR_DSIRST_Pos = 0x1b
	// Bit mask of DSIRST field.
	RCC_APB2RSTR_DSIRST_Msk = 0x8000000
	// Bit DSIRST.
	RCC_APB2RSTR_DSIRST = 0x8000000
	// No effect
	RCC_APB2RSTR_DSIRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB2RSTR_DSIRST_Reset = 0x1

	// APB3RSTR: RCC APB3 peripheral reset register
	// Position of SYSCFGRST field.
	RCC_APB3RSTR_SYSCFGRST_Pos = 0x1
	// Bit mask of SYSCFGRST field.
	RCC_APB3RSTR_SYSCFGRST_Msk = 0x2
	// Bit SYSCFGRST.
	RCC_APB3RSTR_SYSCFGRST = 0x2
	// No effect
	RCC_APB3RSTR_SYSCFGRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_SYSCFGRST_Reset = 0x1
	// Position of SPI3RST field.
	RCC_APB3RSTR_SPI3RST_Pos = 0x5
	// Bit mask of SPI3RST field.
	RCC_APB3RSTR_SPI3RST_Msk = 0x20
	// Bit SPI3RST.
	RCC_APB3RSTR_SPI3RST = 0x20
	// No effect
	RCC_APB3RSTR_SPI3RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_SPI3RST_Reset = 0x1
	// Position of LPUART1RST field.
	RCC_APB3RSTR_LPUART1RST_Pos = 0x6
	// Bit mask of LPUART1RST field.
	RCC_APB3RSTR_LPUART1RST_Msk = 0x40
	// Bit LPUART1RST.
	RCC_APB3RSTR_LPUART1RST = 0x40
	// No effect
	RCC_APB3RSTR_LPUART1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_LPUART1RST_Reset = 0x1
	// Position of I2C3RST field.
	RCC_APB3RSTR_I2C3RST_Pos = 0x7
	// Bit mask of I2C3RST field.
	RCC_APB3RSTR_I2C3RST_Msk = 0x80
	// Bit I2C3RST.
	RCC_APB3RSTR_I2C3RST = 0x80
	// No effect
	RCC_APB3RSTR_I2C3RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_I2C3RST_Reset = 0x1
	// Position of LPTIM1RST field.
	RCC_APB3RSTR_LPTIM1RST_Pos = 0xb
	// Bit mask of LPTIM1RST field.
	RCC_APB3RSTR_LPTIM1RST_Msk = 0x800
	// Bit LPTIM1RST.
	RCC_APB3RSTR_LPTIM1RST = 0x800
	// No effect
	RCC_APB3RSTR_LPTIM1RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_LPTIM1RST_Reset = 0x1
	// Position of LPTIM3RST field.
	RCC_APB3RSTR_LPTIM3RST_Pos = 0xc
	// Bit mask of LPTIM3RST field.
	RCC_APB3RSTR_LPTIM3RST_Msk = 0x1000
	// Bit LPTIM3RST.
	RCC_APB3RSTR_LPTIM3RST = 0x1000
	// No effect
	RCC_APB3RSTR_LPTIM3RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_LPTIM3RST_Reset = 0x1
	// Position of LPTIM4RST field.
	RCC_APB3RSTR_LPTIM4RST_Pos = 0xd
	// Bit mask of LPTIM4RST field.
	RCC_APB3RSTR_LPTIM4RST_Msk = 0x2000
	// Bit LPTIM4RST.
	RCC_APB3RSTR_LPTIM4RST = 0x2000
	// No effect
	RCC_APB3RSTR_LPTIM4RST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_LPTIM4RST_Reset = 0x1
	// Position of OPAMPRST field.
	RCC_APB3RSTR_OPAMPRST_Pos = 0xe
	// Bit mask of OPAMPRST field.
	RCC_APB3RSTR_OPAMPRST_Msk = 0x4000
	// Bit OPAMPRST.
	RCC_APB3RSTR_OPAMPRST = 0x4000
	// No effect
	RCC_APB3RSTR_OPAMPRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_OPAMPRST_Reset = 0x1
	// Position of COMPRST field.
	RCC_APB3RSTR_COMPRST_Pos = 0xf
	// Bit mask of COMPRST field.
	RCC_APB3RSTR_COMPRST_Msk = 0x8000
	// Bit COMPRST.
	RCC_APB3RSTR_COMPRST = 0x8000
	// No effect
	RCC_APB3RSTR_COMPRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_COMPRST_Reset = 0x1
	// Position of VREFRST field.
	RCC_APB3RSTR_VREFRST_Pos = 0x14
	// Bit mask of VREFRST field.
	RCC_APB3RSTR_VREFRST_Msk = 0x100000
	// Bit VREFRST.
	RCC_APB3RSTR_VREFRST = 0x100000
	// No effect
	RCC_APB3RSTR_VREFRST_NoEffect = 0x0
	// Reset peripheral
	RCC_APB3RSTR_VREFRST_Reset = 0x1

	// AHB1ENR: RCC AHB1 peripheral clock enable register
	// Position of GPDMA1EN field.
	RCC_AHB1ENR_GPDMA1EN_Pos = 0x0
	// Bit mask of GPDMA1EN field.
	RCC_AHB1ENR_GPDMA1EN_Msk = 0x1
	// Bit GPDMA1EN.
	RCC_AHB1ENR_GPDMA1EN = 0x1
	// Peripheral clock disabled
	RCC_AHB1ENR_GPDMA1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_GPDMA1EN_Enabled = 0x1
	// Position of CORDICEN field.
	RCC_AHB1ENR_CORDICEN_Pos = 0x1
	// Bit mask of CORDICEN field.
	RCC_AHB1ENR_CORDICEN_Msk = 0x2
	// Bit CORDICEN.
	RCC_AHB1ENR_CORDICEN = 0x2
	// Peripheral clock disabled
	RCC_AHB1ENR_CORDICEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_CORDICEN_Enabled = 0x1
	// Position of FMACEN field.
	RCC_AHB1ENR_FMACEN_Pos = 0x2
	// Bit mask of FMACEN field.
	RCC_AHB1ENR_FMACEN_Msk = 0x4
	// Bit FMACEN.
	RCC_AHB1ENR_FMACEN = 0x4
	// Peripheral clock disabled
	RCC_AHB1ENR_FMACEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_FMACEN_Enabled = 0x1
	// Position of MDF1EN field.
	RCC_AHB1ENR_MDF1EN_Pos = 0x3
	// Bit mask of MDF1EN field.
	RCC_AHB1ENR_MDF1EN_Msk = 0x8
	// Bit MDF1EN.
	RCC_AHB1ENR_MDF1EN = 0x8
	// Peripheral clock disabled
	RCC_AHB1ENR_MDF1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_MDF1EN_Enabled = 0x1
	// Position of FLASHEN field.
	RCC_AHB1ENR_FLASHEN_Pos = 0x8
	// Bit mask of FLASHEN field.
	RCC_AHB1ENR_FLASHEN_Msk = 0x100
	// Bit FLASHEN.
	RCC_AHB1ENR_FLASHEN = 0x100
	// Peripheral clock disabled
	RCC_AHB1ENR_FLASHEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_FLASHEN_Enabled = 0x1
	// Position of CRCEN field.
	RCC_AHB1ENR_CRCEN_Pos = 0xc
	// Bit mask of CRCEN field.
	RCC_AHB1ENR_CRCEN_Msk = 0x1000
	// Bit CRCEN.
	RCC_AHB1ENR_CRCEN = 0x1000
	// Peripheral clock disabled
	RCC_AHB1ENR_CRCEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_CRCEN_Enabled = 0x1
	// Position of JPEGEN field.
	RCC_AHB1ENR_JPEGEN_Pos = 0xf
	// Bit mask of JPEGEN field.
	RCC_AHB1ENR_JPEGEN_Msk = 0x8000
	// Bit JPEGEN.
	RCC_AHB1ENR_JPEGEN = 0x8000
	// Peripheral clock disabled
	RCC_AHB1ENR_JPEGEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_JPEGEN_Enabled = 0x1
	// Position of TSCEN field.
	RCC_AHB1ENR_TSCEN_Pos = 0x10
	// Bit mask of TSCEN field.
	RCC_AHB1ENR_TSCEN_Msk = 0x10000
	// Bit TSCEN.
	RCC_AHB1ENR_TSCEN = 0x10000
	// Peripheral clock disabled
	RCC_AHB1ENR_TSCEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_TSCEN_Enabled = 0x1
	// Position of RAMCFGEN field.
	RCC_AHB1ENR_RAMCFGEN_Pos = 0x11
	// Bit mask of RAMCFGEN field.
	RCC_AHB1ENR_RAMCFGEN_Msk = 0x20000
	// Bit RAMCFGEN.
	RCC_AHB1ENR_RAMCFGEN = 0x20000
	// Peripheral clock disabled
	RCC_AHB1ENR_RAMCFGEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_RAMCFGEN_Enabled = 0x1
	// Position of DMA2DEN field.
	RCC_AHB1ENR_DMA2DEN_Pos = 0x12
	// Bit mask of DMA2DEN field.
	RCC_AHB1ENR_DMA2DEN_Msk = 0x40000
	// Bit DMA2DEN.
	RCC_AHB1ENR_DMA2DEN = 0x40000
	// Peripheral clock disabled
	RCC_AHB1ENR_DMA2DEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_DMA2DEN_Enabled = 0x1
	// Position of GFXMMUEN field.
	RCC_AHB1ENR_GFXMMUEN_Pos = 0x13
	// Bit mask of GFXMMUEN field.
	RCC_AHB1ENR_GFXMMUEN_Msk = 0x80000
	// Bit GFXMMUEN.
	RCC_AHB1ENR_GFXMMUEN = 0x80000
	// Peripheral clock disabled
	RCC_AHB1ENR_GFXMMUEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_GFXMMUEN_Enabled = 0x1
	// Position of GPU2DEN field.
	RCC_AHB1ENR_GPU2DEN_Pos = 0x14
	// Bit mask of GPU2DEN field.
	RCC_AHB1ENR_GPU2DEN_Msk = 0x100000
	// Bit GPU2DEN.
	RCC_AHB1ENR_GPU2DEN = 0x100000
	// Peripheral clock disabled
	RCC_AHB1ENR_GPU2DEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_GPU2DEN_Enabled = 0x1
	// Position of DCACHE2EN field.
	RCC_AHB1ENR_DCACHE2EN_Pos = 0x15
	// Bit mask of DCACHE2EN field.
	RCC_AHB1ENR_DCACHE2EN_Msk = 0x200000
	// Bit DCACHE2EN.
	RCC_AHB1ENR_DCACHE2EN = 0x200000
	// Peripheral clock disabled
	RCC_AHB1ENR_DCACHE2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_DCACHE2EN_Enabled = 0x1
	// Position of GTZC1EN field.
	RCC_AHB1ENR_GTZC1EN_Pos = 0x18
	// Bit mask of GTZC1EN field.
	RCC_AHB1ENR_GTZC1EN_Msk = 0x1000000
	// Bit GTZC1EN.
	RCC_AHB1ENR_GTZC1EN = 0x1000000
	// Peripheral clock disabled
	RCC_AHB1ENR_GTZC1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_GTZC1EN_Enabled = 0x1
	// Position of BKPSRAMEN field.
	RCC_AHB1ENR_BKPSRAMEN_Pos = 0x1c
	// Bit mask of BKPSRAMEN field.
	RCC_AHB1ENR_BKPSRAMEN_Msk = 0x10000000
	// Bit BKPSRAMEN.
	RCC_AHB1ENR_BKPSRAMEN = 0x10000000
	// Peripheral clock disabled
	RCC_AHB1ENR_BKPSRAMEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_BKPSRAMEN_Enabled = 0x1
	// Position of DCACHE1EN field.
	RCC_AHB1ENR_DCACHE1EN_Pos = 0x1e
	// Bit mask of DCACHE1EN field.
	RCC_AHB1ENR_DCACHE1EN_Msk = 0x40000000
	// Bit DCACHE1EN.
	RCC_AHB1ENR_DCACHE1EN = 0x40000000
	// Peripheral clock disabled
	RCC_AHB1ENR_DCACHE1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_DCACHE1EN_Enabled = 0x1
	// Position of SRAM1EN field.
	RCC_AHB1ENR_SRAM1EN_Pos = 0x1f
	// Bit mask of SRAM1EN field.
	RCC_AHB1ENR_SRAM1EN_Msk = 0x80000000
	// Bit SRAM1EN.
	RCC_AHB1ENR_SRAM1EN = 0x80000000
	// Peripheral clock disabled
	RCC_AHB1ENR_SRAM1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB1ENR_SRAM1EN_Enabled = 0x1

	// AHB2ENR1: RCC AHB2 peripheral clock enable register 1
	// Position of GPIOAEN field.
	RCC_AHB2ENR1_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_AHB2ENR1_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_AHB2ENR1_GPIOAEN = 0x1
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOAEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOAEN_Enabled = 0x1
	// Position of GPIOBEN field.
	RCC_AHB2ENR1_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_AHB2ENR1_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_AHB2ENR1_GPIOBEN = 0x2
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOBEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOBEN_Enabled = 0x1
	// Position of GPIOCEN field.
	RCC_AHB2ENR1_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_AHB2ENR1_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_AHB2ENR1_GPIOCEN = 0x4
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOCEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOCEN_Enabled = 0x1
	// Position of GPIODEN field.
	RCC_AHB2ENR1_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_AHB2ENR1_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_AHB2ENR1_GPIODEN = 0x8
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIODEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIODEN_Enabled = 0x1
	// Position of GPIOEEN field.
	RCC_AHB2ENR1_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_AHB2ENR1_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_AHB2ENR1_GPIOEEN = 0x10
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOEEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOEEN_Enabled = 0x1
	// Position of GPIOFEN field.
	RCC_AHB2ENR1_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_AHB2ENR1_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_AHB2ENR1_GPIOFEN = 0x20
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOFEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOFEN_Enabled = 0x1
	// Position of GPIOGEN field.
	RCC_AHB2ENR1_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_AHB2ENR1_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_AHB2ENR1_GPIOGEN = 0x40
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOGEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOGEN_Enabled = 0x1
	// Position of GPIOHEN field.
	RCC_AHB2ENR1_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_AHB2ENR1_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_AHB2ENR1_GPIOHEN = 0x80
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOHEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOHEN_Enabled = 0x1
	// Position of GPIOIEN field.
	RCC_AHB2ENR1_GPIOIEN_Pos = 0x8
	// Bit mask of GPIOIEN field.
	RCC_AHB2ENR1_GPIOIEN_Msk = 0x100
	// Bit GPIOIEN.
	RCC_AHB2ENR1_GPIOIEN = 0x100
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOIEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOIEN_Enabled = 0x1
	// Position of GPIOJEN field.
	RCC_AHB2ENR1_GPIOJEN_Pos = 0x9
	// Bit mask of GPIOJEN field.
	RCC_AHB2ENR1_GPIOJEN_Msk = 0x200
	// Bit GPIOJEN.
	RCC_AHB2ENR1_GPIOJEN = 0x200
	// Peripheral clock disabled
	RCC_AHB2ENR1_GPIOJEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_GPIOJEN_Enabled = 0x1
	// Position of ADC12EN field.
	RCC_AHB2ENR1_ADC12EN_Pos = 0xa
	// Bit mask of ADC12EN field.
	RCC_AHB2ENR1_ADC12EN_Msk = 0x400
	// Bit ADC12EN.
	RCC_AHB2ENR1_ADC12EN = 0x400
	// Peripheral clock disabled
	RCC_AHB2ENR1_ADC12EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_ADC12EN_Enabled = 0x1
	// Position of DCMI_PSSIEN field.
	RCC_AHB2ENR1_DCMI_PSSIEN_Pos = 0xc
	// Bit mask of DCMI_PSSIEN field.
	RCC_AHB2ENR1_DCMI_PSSIEN_Msk = 0x1000
	// Bit DCMI_PSSIEN.
	RCC_AHB2ENR1_DCMI_PSSIEN = 0x1000
	// Peripheral clock disabled
	RCC_AHB2ENR1_DCMI_PSSIEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_DCMI_PSSIEN_Enabled = 0x1
	// Position of OTGEN field.
	RCC_AHB2ENR1_OTGEN_Pos = 0xe
	// Bit mask of OTGEN field.
	RCC_AHB2ENR1_OTGEN_Msk = 0x4000
	// Bit OTGEN.
	RCC_AHB2ENR1_OTGEN = 0x4000
	// Peripheral clock disabled
	RCC_AHB2ENR1_OTGEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_OTGEN_Enabled = 0x1
	// Position of OTGHSPHYEN field.
	RCC_AHB2ENR1_OTGHSPHYEN_Pos = 0xf
	// Bit mask of OTGHSPHYEN field.
	RCC_AHB2ENR1_OTGHSPHYEN_Msk = 0x8000
	// Bit OTGHSPHYEN.
	RCC_AHB2ENR1_OTGHSPHYEN = 0x8000
	// Peripheral clock disabled
	RCC_AHB2ENR1_OTGHSPHYEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_OTGHSPHYEN_Enabled = 0x1
	// Position of AESEN field.
	RCC_AHB2ENR1_AESEN_Pos = 0x10
	// Bit mask of AESEN field.
	RCC_AHB2ENR1_AESEN_Msk = 0x10000
	// Bit AESEN.
	RCC_AHB2ENR1_AESEN = 0x10000
	// Peripheral clock disabled
	RCC_AHB2ENR1_AESEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_AESEN_Enabled = 0x1
	// Position of HASHEN field.
	RCC_AHB2ENR1_HASHEN_Pos = 0x11
	// Bit mask of HASHEN field.
	RCC_AHB2ENR1_HASHEN_Msk = 0x20000
	// Bit HASHEN.
	RCC_AHB2ENR1_HASHEN = 0x20000
	// Peripheral clock disabled
	RCC_AHB2ENR1_HASHEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_HASHEN_Enabled = 0x1
	// Position of RNGEN field.
	RCC_AHB2ENR1_RNGEN_Pos = 0x12
	// Bit mask of RNGEN field.
	RCC_AHB2ENR1_RNGEN_Msk = 0x40000
	// Bit RNGEN.
	RCC_AHB2ENR1_RNGEN = 0x40000
	// Peripheral clock disabled
	RCC_AHB2ENR1_RNGEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_RNGEN_Enabled = 0x1
	// Position of PKAEN field.
	RCC_AHB2ENR1_PKAEN_Pos = 0x13
	// Bit mask of PKAEN field.
	RCC_AHB2ENR1_PKAEN_Msk = 0x80000
	// Bit PKAEN.
	RCC_AHB2ENR1_PKAEN = 0x80000
	// Peripheral clock disabled
	RCC_AHB2ENR1_PKAEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_PKAEN_Enabled = 0x1
	// Position of SAESEN field.
	RCC_AHB2ENR1_SAESEN_Pos = 0x14
	// Bit mask of SAESEN field.
	RCC_AHB2ENR1_SAESEN_Msk = 0x100000
	// Bit SAESEN.
	RCC_AHB2ENR1_SAESEN = 0x100000
	// Peripheral clock disabled
	RCC_AHB2ENR1_SAESEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_SAESEN_Enabled = 0x1
	// Position of OCTOSPIMEN field.
	RCC_AHB2ENR1_OCTOSPIMEN_Pos = 0x15
	// Bit mask of OCTOSPIMEN field.
	RCC_AHB2ENR1_OCTOSPIMEN_Msk = 0x200000
	// Bit OCTOSPIMEN.
	RCC_AHB2ENR1_OCTOSPIMEN = 0x200000
	// Peripheral clock disabled
	RCC_AHB2ENR1_OCTOSPIMEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_OCTOSPIMEN_Enabled = 0x1
	// Position of OTFDEC1EN field.
	RCC_AHB2ENR1_OTFDEC1EN_Pos = 0x17
	// Bit mask of OTFDEC1EN field.
	RCC_AHB2ENR1_OTFDEC1EN_Msk = 0x800000
	// Bit OTFDEC1EN.
	RCC_AHB2ENR1_OTFDEC1EN = 0x800000
	// Peripheral clock disabled
	RCC_AHB2ENR1_OTFDEC1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_OTFDEC1EN_Enabled = 0x1
	// Position of OTFDEC2EN field.
	RCC_AHB2ENR1_OTFDEC2EN_Pos = 0x18
	// Bit mask of OTFDEC2EN field.
	RCC_AHB2ENR1_OTFDEC2EN_Msk = 0x1000000
	// Bit OTFDEC2EN.
	RCC_AHB2ENR1_OTFDEC2EN = 0x1000000
	// Peripheral clock disabled
	RCC_AHB2ENR1_OTFDEC2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_OTFDEC2EN_Enabled = 0x1
	// Position of SDMMC1EN field.
	RCC_AHB2ENR1_SDMMC1EN_Pos = 0x1b
	// Bit mask of SDMMC1EN field.
	RCC_AHB2ENR1_SDMMC1EN_Msk = 0x8000000
	// Bit SDMMC1EN.
	RCC_AHB2ENR1_SDMMC1EN = 0x8000000
	// Peripheral clock disabled
	RCC_AHB2ENR1_SDMMC1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_SDMMC1EN_Enabled = 0x1
	// Position of SDMMC2EN field.
	RCC_AHB2ENR1_SDMMC2EN_Pos = 0x1c
	// Bit mask of SDMMC2EN field.
	RCC_AHB2ENR1_SDMMC2EN_Msk = 0x10000000
	// Bit SDMMC2EN.
	RCC_AHB2ENR1_SDMMC2EN = 0x10000000
	// Peripheral clock disabled
	RCC_AHB2ENR1_SDMMC2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_SDMMC2EN_Enabled = 0x1
	// Position of SRAM2EN field.
	RCC_AHB2ENR1_SRAM2EN_Pos = 0x1e
	// Bit mask of SRAM2EN field.
	RCC_AHB2ENR1_SRAM2EN_Msk = 0x40000000
	// Bit SRAM2EN.
	RCC_AHB2ENR1_SRAM2EN = 0x40000000
	// Peripheral clock disabled
	RCC_AHB2ENR1_SRAM2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_SRAM2EN_Enabled = 0x1
	// Position of SRAM3EN field.
	RCC_AHB2ENR1_SRAM3EN_Pos = 0x1f
	// Bit mask of SRAM3EN field.
	RCC_AHB2ENR1_SRAM3EN_Msk = 0x80000000
	// Bit SRAM3EN.
	RCC_AHB2ENR1_SRAM3EN = 0x80000000
	// Peripheral clock disabled
	RCC_AHB2ENR1_SRAM3EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR1_SRAM3EN_Enabled = 0x1

	// AHB2ENR2: RCC AHB2 peripheral clock enable register 2
	// Position of FSMCEN field.
	RCC_AHB2ENR2_FSMCEN_Pos = 0x0
	// Bit mask of FSMCEN field.
	RCC_AHB2ENR2_FSMCEN_Msk = 0x1
	// Bit FSMCEN.
	RCC_AHB2ENR2_FSMCEN = 0x1
	// Peripheral clock disabled
	RCC_AHB2ENR2_FSMCEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR2_FSMCEN_Enabled = 0x1
	// Position of OCTOSPI1EN field.
	RCC_AHB2ENR2_OCTOSPI1EN_Pos = 0x4
	// Bit mask of OCTOSPI1EN field.
	RCC_AHB2ENR2_OCTOSPI1EN_Msk = 0x10
	// Bit OCTOSPI1EN.
	RCC_AHB2ENR2_OCTOSPI1EN = 0x10
	// Peripheral clock disabled
	RCC_AHB2ENR2_OCTOSPI1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR2_OCTOSPI1EN_Enabled = 0x1
	// Position of OCTOSPI2EN field.
	RCC_AHB2ENR2_OCTOSPI2EN_Pos = 0x8
	// Bit mask of OCTOSPI2EN field.
	RCC_AHB2ENR2_OCTOSPI2EN_Msk = 0x100
	// Bit OCTOSPI2EN.
	RCC_AHB2ENR2_OCTOSPI2EN = 0x100
	// Peripheral clock disabled
	RCC_AHB2ENR2_OCTOSPI2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR2_OCTOSPI2EN_Enabled = 0x1
	// Position of HSPI1EN field.
	RCC_AHB2ENR2_HSPI1EN_Pos = 0xc
	// Bit mask of HSPI1EN field.
	RCC_AHB2ENR2_HSPI1EN_Msk = 0x1000
	// Bit HSPI1EN.
	RCC_AHB2ENR2_HSPI1EN = 0x1000
	// Peripheral clock disabled
	RCC_AHB2ENR2_HSPI1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR2_HSPI1EN_Enabled = 0x1
	// Position of SRAM6EN field.
	RCC_AHB2ENR2_SRAM6EN_Pos = 0x1e
	// Bit mask of SRAM6EN field.
	RCC_AHB2ENR2_SRAM6EN_Msk = 0x40000000
	// Bit SRAM6EN.
	RCC_AHB2ENR2_SRAM6EN = 0x40000000
	// Peripheral clock disabled
	RCC_AHB2ENR2_SRAM6EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR2_SRAM6EN_Enabled = 0x1
	// Position of SRAM5EN field.
	RCC_AHB2ENR2_SRAM5EN_Pos = 0x1f
	// Bit mask of SRAM5EN field.
	RCC_AHB2ENR2_SRAM5EN_Msk = 0x80000000
	// Bit SRAM5EN.
	RCC_AHB2ENR2_SRAM5EN = 0x80000000
	// Peripheral clock disabled
	RCC_AHB2ENR2_SRAM5EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB2ENR2_SRAM5EN_Enabled = 0x1

	// AHB3ENR: RCC AHB3 peripheral clock enable register
	// Position of LPGPIO1EN field.
	RCC_AHB3ENR_LPGPIO1EN_Pos = 0x0
	// Bit mask of LPGPIO1EN field.
	RCC_AHB3ENR_LPGPIO1EN_Msk = 0x1
	// Bit LPGPIO1EN.
	RCC_AHB3ENR_LPGPIO1EN = 0x1
	// Peripheral clock disabled
	RCC_AHB3ENR_LPGPIO1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_LPGPIO1EN_Enabled = 0x1
	// Position of PWREN field.
	RCC_AHB3ENR_PWREN_Pos = 0x2
	// Bit mask of PWREN field.
	RCC_AHB3ENR_PWREN_Msk = 0x4
	// Bit PWREN.
	RCC_AHB3ENR_PWREN = 0x4
	// Peripheral clock disabled
	RCC_AHB3ENR_PWREN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_PWREN_Enabled = 0x1
	// Position of ADC4EN field.
	RCC_AHB3ENR_ADC4EN_Pos = 0x5
	// Bit mask of ADC4EN field.
	RCC_AHB3ENR_ADC4EN_Msk = 0x20
	// Bit ADC4EN.
	RCC_AHB3ENR_ADC4EN = 0x20
	// Peripheral clock disabled
	RCC_AHB3ENR_ADC4EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_ADC4EN_Enabled = 0x1
	// Position of DAC1EN field.
	RCC_AHB3ENR_DAC1EN_Pos = 0x6
	// Bit mask of DAC1EN field.
	RCC_AHB3ENR_DAC1EN_Msk = 0x40
	// Bit DAC1EN.
	RCC_AHB3ENR_DAC1EN = 0x40
	// Peripheral clock disabled
	RCC_AHB3ENR_DAC1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_DAC1EN_Enabled = 0x1
	// Position of LPDMA1EN field.
	RCC_AHB3ENR_LPDMA1EN_Pos = 0x9
	// Bit mask of LPDMA1EN field.
	RCC_AHB3ENR_LPDMA1EN_Msk = 0x200
	// Bit LPDMA1EN.
	RCC_AHB3ENR_LPDMA1EN = 0x200
	// Peripheral clock disabled
	RCC_AHB3ENR_LPDMA1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_LPDMA1EN_Enabled = 0x1
	// Position of ADF1EN field.
	RCC_AHB3ENR_ADF1EN_Pos = 0xa
	// Bit mask of ADF1EN field.
	RCC_AHB3ENR_ADF1EN_Msk = 0x400
	// Bit ADF1EN.
	RCC_AHB3ENR_ADF1EN = 0x400
	// Peripheral clock disabled
	RCC_AHB3ENR_ADF1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_ADF1EN_Enabled = 0x1
	// Position of GTZC2EN field.
	RCC_AHB3ENR_GTZC2EN_Pos = 0xc
	// Bit mask of GTZC2EN field.
	RCC_AHB3ENR_GTZC2EN_Msk = 0x1000
	// Bit GTZC2EN.
	RCC_AHB3ENR_GTZC2EN = 0x1000
	// Peripheral clock disabled
	RCC_AHB3ENR_GTZC2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_GTZC2EN_Enabled = 0x1
	// Position of SRAM4EN field.
	RCC_AHB3ENR_SRAM4EN_Pos = 0x1f
	// Bit mask of SRAM4EN field.
	RCC_AHB3ENR_SRAM4EN_Msk = 0x80000000
	// Bit SRAM4EN.
	RCC_AHB3ENR_SRAM4EN = 0x80000000
	// Peripheral clock disabled
	RCC_AHB3ENR_SRAM4EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_AHB3ENR_SRAM4EN_Enabled = 0x1

	// APB1ENR1: RCC APB1 peripheral clock enable register 1
	// Position of TIM2EN field.
	RCC_APB1ENR1_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_APB1ENR1_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_APB1ENR1_TIM2EN = 0x1
	// Peripheral clock disabled
	RCC_APB1ENR1_TIM2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_TIM2EN_Enabled = 0x1
	// Position of TIM3EN field.
	RCC_APB1ENR1_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_APB1ENR1_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_APB1ENR1_TIM3EN = 0x2
	// Peripheral clock disabled
	RCC_APB1ENR1_TIM3EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_TIM3EN_Enabled = 0x1
	// Position of TIM4EN field.
	RCC_APB1ENR1_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_APB1ENR1_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_APB1ENR1_TIM4EN = 0x4
	// Peripheral clock disabled
	RCC_APB1ENR1_TIM4EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_TIM4EN_Enabled = 0x1
	// Position of TIM5EN field.
	RCC_APB1ENR1_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_APB1ENR1_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_APB1ENR1_TIM5EN = 0x8
	// Peripheral clock disabled
	RCC_APB1ENR1_TIM5EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_TIM5EN_Enabled = 0x1
	// Position of TIM6EN field.
	RCC_APB1ENR1_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_APB1ENR1_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_APB1ENR1_TIM6EN = 0x10
	// Peripheral clock disabled
	RCC_APB1ENR1_TIM6EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_TIM6EN_Enabled = 0x1
	// Position of TIM7EN field.
	RCC_APB1ENR1_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_APB1ENR1_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_APB1ENR1_TIM7EN = 0x20
	// Peripheral clock disabled
	RCC_APB1ENR1_TIM7EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_TIM7EN_Enabled = 0x1
	// Position of WWDGEN field.
	RCC_APB1ENR1_WWDGEN_Pos = 0xb
	// Bit mask of WWDGEN field.
	RCC_APB1ENR1_WWDGEN_Msk = 0x800
	// Bit WWDGEN.
	RCC_APB1ENR1_WWDGEN = 0x800
	// Peripheral clock disabled
	RCC_APB1ENR1_WWDGEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_WWDGEN_Enabled = 0x1
	// Position of SPI2EN field.
	RCC_APB1ENR1_SPI2EN_Pos = 0xe
	// Bit mask of SPI2EN field.
	RCC_APB1ENR1_SPI2EN_Msk = 0x4000
	// Bit SPI2EN.
	RCC_APB1ENR1_SPI2EN = 0x4000
	// Peripheral clock disabled
	RCC_APB1ENR1_SPI2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_SPI2EN_Enabled = 0x1
	// Position of USART2EN field.
	RCC_APB1ENR1_USART2EN_Pos = 0x11
	// Bit mask of USART2EN field.
	RCC_APB1ENR1_USART2EN_Msk = 0x20000
	// Bit USART2EN.
	RCC_APB1ENR1_USART2EN = 0x20000
	// Peripheral clock disabled
	RCC_APB1ENR1_USART2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_USART2EN_Enabled = 0x1
	// Position of USART3EN field.
	RCC_APB1ENR1_USART3EN_Pos = 0x12
	// Bit mask of USART3EN field.
	RCC_APB1ENR1_USART3EN_Msk = 0x40000
	// Bit USART3EN.
	RCC_APB1ENR1_USART3EN = 0x40000
	// Peripheral clock disabled
	RCC_APB1ENR1_USART3EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_USART3EN_Enabled = 0x1
	// Position of UART4EN field.
	RCC_APB1ENR1_UART4EN_Pos = 0x13
	// Bit mask of UART4EN field.
	RCC_APB1ENR1_UART4EN_Msk = 0x80000
	// Bit UART4EN.
	RCC_APB1ENR1_UART4EN = 0x80000
	// Peripheral clock disabled
	RCC_APB1ENR1_UART4EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_UART4EN_Enabled = 0x1
	// Position of UART5EN field.
	RCC_APB1ENR1_UART5EN_Pos = 0x14
	// Bit mask of UART5EN field.
	RCC_APB1ENR1_UART5EN_Msk = 0x100000
	// Bit UART5EN.
	RCC_APB1ENR1_UART5EN = 0x100000
	// Peripheral clock disabled
	RCC_APB1ENR1_UART5EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_UART5EN_Enabled = 0x1
	// Position of I2C1EN field.
	RCC_APB1ENR1_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_APB1ENR1_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_APB1ENR1_I2C1EN = 0x200000
	// Peripheral clock disabled
	RCC_APB1ENR1_I2C1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_I2C1EN_Enabled = 0x1
	// Position of I2C2EN field.
	RCC_APB1ENR1_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_APB1ENR1_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_APB1ENR1_I2C2EN = 0x400000
	// Peripheral clock disabled
	RCC_APB1ENR1_I2C2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_I2C2EN_Enabled = 0x1
	// Position of CRSEN field.
	RCC_APB1ENR1_CRSEN_Pos = 0x18
	// Bit mask of CRSEN field.
	RCC_APB1ENR1_CRSEN_Msk = 0x1000000
	// Bit CRSEN.
	RCC_APB1ENR1_CRSEN = 0x1000000
	// Peripheral clock disabled
	RCC_APB1ENR1_CRSEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_CRSEN_Enabled = 0x1
	// Position of USART6EN field.
	RCC_APB1ENR1_USART6EN_Pos = 0x19
	// Bit mask of USART6EN field.
	RCC_APB1ENR1_USART6EN_Msk = 0x2000000
	// Bit USART6EN.
	RCC_APB1ENR1_USART6EN = 0x2000000
	// Peripheral clock disabled
	RCC_APB1ENR1_USART6EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR1_USART6EN_Enabled = 0x1

	// APB1ENR2: RCC APB1 peripheral clock enable register 2
	// Position of I2C4EN field.
	RCC_APB1ENR2_I2C4EN_Pos = 0x1
	// Bit mask of I2C4EN field.
	RCC_APB1ENR2_I2C4EN_Msk = 0x2
	// Bit I2C4EN.
	RCC_APB1ENR2_I2C4EN = 0x2
	// Peripheral clock disabled
	RCC_APB1ENR2_I2C4EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR2_I2C4EN_Enabled = 0x1
	// Position of LPTIM2EN field.
	RCC_APB1ENR2_LPTIM2EN_Pos = 0x5
	// Bit mask of LPTIM2EN field.
	RCC_APB1ENR2_LPTIM2EN_Msk = 0x20
	// Bit LPTIM2EN.
	RCC_APB1ENR2_LPTIM2EN = 0x20
	// Peripheral clock disabled
	RCC_APB1ENR2_LPTIM2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR2_LPTIM2EN_Enabled = 0x1
	// Position of I2C5EN field.
	RCC_APB1ENR2_I2C5EN_Pos = 0x6
	// Bit mask of I2C5EN field.
	RCC_APB1ENR2_I2C5EN_Msk = 0x40
	// Bit I2C5EN.
	RCC_APB1ENR2_I2C5EN = 0x40
	// Peripheral clock disabled
	RCC_APB1ENR2_I2C5EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR2_I2C5EN_Enabled = 0x1
	// Position of I2C6EN field.
	RCC_APB1ENR2_I2C6EN_Pos = 0x7
	// Bit mask of I2C6EN field.
	RCC_APB1ENR2_I2C6EN_Msk = 0x80
	// Bit I2C6EN.
	RCC_APB1ENR2_I2C6EN = 0x80
	// Peripheral clock disabled
	RCC_APB1ENR2_I2C6EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR2_I2C6EN_Enabled = 0x1
	// Position of FDCAN1EN field.
	RCC_APB1ENR2_FDCAN1EN_Pos = 0x9
	// Bit mask of FDCAN1EN field.
	RCC_APB1ENR2_FDCAN1EN_Msk = 0x200
	// Bit FDCAN1EN.
	RCC_APB1ENR2_FDCAN1EN = 0x200
	// Peripheral clock disabled
	RCC_APB1ENR2_FDCAN1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR2_FDCAN1EN_Enabled = 0x1
	// Position of UCPD1EN field.
	RCC_APB1ENR2_UCPD1EN_Pos = 0x17
	// Bit mask of UCPD1EN field.
	RCC_APB1ENR2_UCPD1EN_Msk = 0x800000
	// Bit UCPD1EN.
	RCC_APB1ENR2_UCPD1EN = 0x800000
	// Peripheral clock disabled
	RCC_APB1ENR2_UCPD1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB1ENR2_UCPD1EN_Enabled = 0x1

	// APB2ENR: RCC APB2 peripheral clock enable register
	// Position of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Pos = 0xb
	// Bit mask of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Msk = 0x800
	// Bit TIM1EN.
	RCC_APB2ENR_TIM1EN = 0x800
	// Peripheral clock disabled
	RCC_APB2ENR_TIM1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_TIM1EN_Enabled = 0x1
	// Position of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Pos = 0xc
	// Bit mask of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Msk = 0x1000
	// Bit SPI1EN.
	RCC_APB2ENR_SPI1EN = 0x1000
	// Peripheral clock disabled
	RCC_APB2ENR_SPI1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_SPI1EN_Enabled = 0x1
	// Position of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Pos = 0xd
	// Bit mask of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Msk = 0x2000
	// Bit TIM8EN.
	RCC_APB2ENR_TIM8EN = 0x2000
	// Peripheral clock disabled
	RCC_APB2ENR_TIM8EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_TIM8EN_Enabled = 0x1
	// Position of USART1EN field.
	RCC_APB2ENR_USART1EN_Pos = 0xe
	// Bit mask of USART1EN field.
	RCC_APB2ENR_USART1EN_Msk = 0x4000
	// Bit USART1EN.
	RCC_APB2ENR_USART1EN = 0x4000
	// Peripheral clock disabled
	RCC_APB2ENR_USART1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_USART1EN_Enabled = 0x1
	// Position of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Pos = 0x10
	// Bit mask of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Msk = 0x10000
	// Bit TIM15EN.
	RCC_APB2ENR_TIM15EN = 0x10000
	// Peripheral clock disabled
	RCC_APB2ENR_TIM15EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_TIM15EN_Enabled = 0x1
	// Position of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Pos = 0x11
	// Bit mask of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Msk = 0x20000
	// Bit TIM16EN.
	RCC_APB2ENR_TIM16EN = 0x20000
	// Peripheral clock disabled
	RCC_APB2ENR_TIM16EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_TIM16EN_Enabled = 0x1
	// Position of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Pos = 0x12
	// Bit mask of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Msk = 0x40000
	// Bit TIM17EN.
	RCC_APB2ENR_TIM17EN = 0x40000
	// Peripheral clock disabled
	RCC_APB2ENR_TIM17EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_TIM17EN_Enabled = 0x1
	// Position of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Pos = 0x15
	// Bit mask of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Msk = 0x200000
	// Bit SAI1EN.
	RCC_APB2ENR_SAI1EN = 0x200000
	// Peripheral clock disabled
	RCC_APB2ENR_SAI1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_SAI1EN_Enabled = 0x1
	// Position of SAI2EN field.
	RCC_APB2ENR_SAI2EN_Pos = 0x16
	// Bit mask of SAI2EN field.
	RCC_APB2ENR_SAI2EN_Msk = 0x400000
	// Bit SAI2EN.
	RCC_APB2ENR_SAI2EN = 0x400000
	// Peripheral clock disabled
	RCC_APB2ENR_SAI2EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_SAI2EN_Enabled = 0x1
	// Position of USBEN field.
	RCC_APB2ENR_USBEN_Pos = 0x18
	// Bit mask of USBEN field.
	RCC_APB2ENR_USBEN_Msk = 0x1000000
	// Bit USBEN.
	RCC_APB2ENR_USBEN = 0x1000000
	// Peripheral clock disabled
	RCC_APB2ENR_USBEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_USBEN_Enabled = 0x1
	// Position of GFXTIMEN field.
	RCC_APB2ENR_GFXTIMEN_Pos = 0x19
	// Bit mask of GFXTIMEN field.
	RCC_APB2ENR_GFXTIMEN_Msk = 0x2000000
	// Bit GFXTIMEN.
	RCC_APB2ENR_GFXTIMEN = 0x2000000
	// Peripheral clock disabled
	RCC_APB2ENR_GFXTIMEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_GFXTIMEN_Enabled = 0x1
	// Position of LTDCEN field.
	RCC_APB2ENR_LTDCEN_Pos = 0x1a
	// Bit mask of LTDCEN field.
	RCC_APB2ENR_LTDCEN_Msk = 0x4000000
	// Bit LTDCEN.
	RCC_APB2ENR_LTDCEN = 0x4000000
	// Peripheral clock disabled
	RCC_APB2ENR_LTDCEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_LTDCEN_Enabled = 0x1
	// Position of DSIEN field.
	RCC_APB2ENR_DSIEN_Pos = 0x1b
	// Bit mask of DSIEN field.
	RCC_APB2ENR_DSIEN_Msk = 0x8000000
	// Bit DSIEN.
	RCC_APB2ENR_DSIEN = 0x8000000
	// Peripheral clock disabled
	RCC_APB2ENR_DSIEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB2ENR_DSIEN_Enabled = 0x1

	// APB3ENR: RCC APB3 peripheral clock enable register
	// Position of SYSCFGEN field.
	RCC_APB3ENR_SYSCFGEN_Pos = 0x1
	// Bit mask of SYSCFGEN field.
	RCC_APB3ENR_SYSCFGEN_Msk = 0x2
	// Bit SYSCFGEN.
	RCC_APB3ENR_SYSCFGEN = 0x2
	// Peripheral clock disabled
	RCC_APB3ENR_SYSCFGEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_SYSCFGEN_Enabled = 0x1
	// Position of SPI3EN field.
	RCC_APB3ENR_SPI3EN_Pos = 0x5
	// Bit mask of SPI3EN field.
	RCC_APB3ENR_SPI3EN_Msk = 0x20
	// Bit SPI3EN.
	RCC_APB3ENR_SPI3EN = 0x20
	// Peripheral clock disabled
	RCC_APB3ENR_SPI3EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_SPI3EN_Enabled = 0x1
	// Position of LPUART1EN field.
	RCC_APB3ENR_LPUART1EN_Pos = 0x6
	// Bit mask of LPUART1EN field.
	RCC_APB3ENR_LPUART1EN_Msk = 0x40
	// Bit LPUART1EN.
	RCC_APB3ENR_LPUART1EN = 0x40
	// Peripheral clock disabled
	RCC_APB3ENR_LPUART1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_LPUART1EN_Enabled = 0x1
	// Position of I2C3EN field.
	RCC_APB3ENR_I2C3EN_Pos = 0x7
	// Bit mask of I2C3EN field.
	RCC_APB3ENR_I2C3EN_Msk = 0x80
	// Bit I2C3EN.
	RCC_APB3ENR_I2C3EN = 0x80
	// Peripheral clock disabled
	RCC_APB3ENR_I2C3EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_I2C3EN_Enabled = 0x1
	// Position of LPTIM1EN field.
	RCC_APB3ENR_LPTIM1EN_Pos = 0xb
	// Bit mask of LPTIM1EN field.
	RCC_APB3ENR_LPTIM1EN_Msk = 0x800
	// Bit LPTIM1EN.
	RCC_APB3ENR_LPTIM1EN = 0x800
	// Peripheral clock disabled
	RCC_APB3ENR_LPTIM1EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_LPTIM1EN_Enabled = 0x1
	// Position of LPTIM3EN field.
	RCC_APB3ENR_LPTIM3EN_Pos = 0xc
	// Bit mask of LPTIM3EN field.
	RCC_APB3ENR_LPTIM3EN_Msk = 0x1000
	// Bit LPTIM3EN.
	RCC_APB3ENR_LPTIM3EN = 0x1000
	// Peripheral clock disabled
	RCC_APB3ENR_LPTIM3EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_LPTIM3EN_Enabled = 0x1
	// Position of LPTIM4EN field.
	RCC_APB3ENR_LPTIM4EN_Pos = 0xd
	// Bit mask of LPTIM4EN field.
	RCC_APB3ENR_LPTIM4EN_Msk = 0x2000
	// Bit LPTIM4EN.
	RCC_APB3ENR_LPTIM4EN = 0x2000
	// Peripheral clock disabled
	RCC_APB3ENR_LPTIM4EN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_LPTIM4EN_Enabled = 0x1
	// Position of OPAMPEN field.
	RCC_APB3ENR_OPAMPEN_Pos = 0xe
	// Bit mask of OPAMPEN field.
	RCC_APB3ENR_OPAMPEN_Msk = 0x4000
	// Bit OPAMPEN.
	RCC_APB3ENR_OPAMPEN = 0x4000
	// Peripheral clock disabled
	RCC_APB3ENR_OPAMPEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_OPAMPEN_Enabled = 0x1
	// Position of COMPEN field.
	RCC_APB3ENR_COMPEN_Pos = 0xf
	// Bit mask of COMPEN field.
	RCC_APB3ENR_COMPEN_Msk = 0x8000
	// Bit COMPEN.
	RCC_APB3ENR_COMPEN = 0x8000
	// Peripheral clock disabled
	RCC_APB3ENR_COMPEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_COMPEN_Enabled = 0x1
	// Position of VREFEN field.
	RCC_APB3ENR_VREFEN_Pos = 0x14
	// Bit mask of VREFEN field.
	RCC_APB3ENR_VREFEN_Msk = 0x100000
	// Bit VREFEN.
	RCC_APB3ENR_VREFEN = 0x100000
	// Peripheral clock disabled
	RCC_APB3ENR_VREFEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_VREFEN_Enabled = 0x1
	// Position of RTCAPBEN field.
	RCC_APB3ENR_RTCAPBEN_Pos = 0x15
	// Bit mask of RTCAPBEN field.
	RCC_APB3ENR_RTCAPBEN_Msk = 0x200000
	// Bit RTCAPBEN.
	RCC_APB3ENR_RTCAPBEN = 0x200000
	// Peripheral clock disabled
	RCC_APB3ENR_RTCAPBEN_Disabled = 0x0
	// Peripheral clock enabled
	RCC_APB3ENR_RTCAPBEN_Enabled = 0x1

	// AHB1SMENR: RCC AHB1 peripheral clock enable in Sleep and Stop modes register
	// Position of GPDMA1SMEN field.
	RCC_AHB1SMENR_GPDMA1SMEN_Pos = 0x0
	// Bit mask of GPDMA1SMEN field.
	RCC_AHB1SMENR_GPDMA1SMEN_Msk = 0x1
	// Bit GPDMA1SMEN.
	RCC_AHB1SMENR_GPDMA1SMEN = 0x1
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GPDMA1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GPDMA1SMEN_Enabled = 0x1
	// Position of CORDICSMEN field.
	RCC_AHB1SMENR_CORDICSMEN_Pos = 0x1
	// Bit mask of CORDICSMEN field.
	RCC_AHB1SMENR_CORDICSMEN_Msk = 0x2
	// Bit CORDICSMEN.
	RCC_AHB1SMENR_CORDICSMEN = 0x2
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_CORDICSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_CORDICSMEN_Enabled = 0x1
	// Position of FMACSMEN field.
	RCC_AHB1SMENR_FMACSMEN_Pos = 0x2
	// Bit mask of FMACSMEN field.
	RCC_AHB1SMENR_FMACSMEN_Msk = 0x4
	// Bit FMACSMEN.
	RCC_AHB1SMENR_FMACSMEN = 0x4
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_FMACSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_FMACSMEN_Enabled = 0x1
	// Position of MDF1SMEN field.
	RCC_AHB1SMENR_MDF1SMEN_Pos = 0x3
	// Bit mask of MDF1SMEN field.
	RCC_AHB1SMENR_MDF1SMEN_Msk = 0x8
	// Bit MDF1SMEN.
	RCC_AHB1SMENR_MDF1SMEN = 0x8
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_MDF1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_MDF1SMEN_Enabled = 0x1
	// Position of FLASHSMEN field.
	RCC_AHB1SMENR_FLASHSMEN_Pos = 0x8
	// Bit mask of FLASHSMEN field.
	RCC_AHB1SMENR_FLASHSMEN_Msk = 0x100
	// Bit FLASHSMEN.
	RCC_AHB1SMENR_FLASHSMEN = 0x100
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_FLASHSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_FLASHSMEN_Enabled = 0x1
	// Position of CRCSMEN field.
	RCC_AHB1SMENR_CRCSMEN_Pos = 0xc
	// Bit mask of CRCSMEN field.
	RCC_AHB1SMENR_CRCSMEN_Msk = 0x1000
	// Bit CRCSMEN.
	RCC_AHB1SMENR_CRCSMEN = 0x1000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_CRCSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_CRCSMEN_Enabled = 0x1
	// Position of JPEGSMEN field.
	RCC_AHB1SMENR_JPEGSMEN_Pos = 0xf
	// Bit mask of JPEGSMEN field.
	RCC_AHB1SMENR_JPEGSMEN_Msk = 0x8000
	// Bit JPEGSMEN.
	RCC_AHB1SMENR_JPEGSMEN = 0x8000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_JPEGSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_JPEGSMEN_Enabled = 0x1
	// Position of TSCSMEN field.
	RCC_AHB1SMENR_TSCSMEN_Pos = 0x10
	// Bit mask of TSCSMEN field.
	RCC_AHB1SMENR_TSCSMEN_Msk = 0x10000
	// Bit TSCSMEN.
	RCC_AHB1SMENR_TSCSMEN = 0x10000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_TSCSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_TSCSMEN_Enabled = 0x1
	// Position of RAMCFGSMEN field.
	RCC_AHB1SMENR_RAMCFGSMEN_Pos = 0x11
	// Bit mask of RAMCFGSMEN field.
	RCC_AHB1SMENR_RAMCFGSMEN_Msk = 0x20000
	// Bit RAMCFGSMEN.
	RCC_AHB1SMENR_RAMCFGSMEN = 0x20000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_RAMCFGSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_RAMCFGSMEN_Enabled = 0x1
	// Position of DMA2DSMEN field.
	RCC_AHB1SMENR_DMA2DSMEN_Pos = 0x12
	// Bit mask of DMA2DSMEN field.
	RCC_AHB1SMENR_DMA2DSMEN_Msk = 0x40000
	// Bit DMA2DSMEN.
	RCC_AHB1SMENR_DMA2DSMEN = 0x40000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_DMA2DSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_DMA2DSMEN_Enabled = 0x1
	// Position of GFXMMUSMEN field.
	RCC_AHB1SMENR_GFXMMUSMEN_Pos = 0x13
	// Bit mask of GFXMMUSMEN field.
	RCC_AHB1SMENR_GFXMMUSMEN_Msk = 0x80000
	// Bit GFXMMUSMEN.
	RCC_AHB1SMENR_GFXMMUSMEN = 0x80000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GFXMMUSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GFXMMUSMEN_Enabled = 0x1
	// Position of GPU2DSMEN field.
	RCC_AHB1SMENR_GPU2DSMEN_Pos = 0x14
	// Bit mask of GPU2DSMEN field.
	RCC_AHB1SMENR_GPU2DSMEN_Msk = 0x100000
	// Bit GPU2DSMEN.
	RCC_AHB1SMENR_GPU2DSMEN = 0x100000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GPU2DSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GPU2DSMEN_Enabled = 0x1
	// Position of DCACHE2SMEN field.
	RCC_AHB1SMENR_DCACHE2SMEN_Pos = 0x15
	// Bit mask of DCACHE2SMEN field.
	RCC_AHB1SMENR_DCACHE2SMEN_Msk = 0x200000
	// Bit DCACHE2SMEN.
	RCC_AHB1SMENR_DCACHE2SMEN = 0x200000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_DCACHE2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_DCACHE2SMEN_Enabled = 0x1
	// Position of GTZC1SMEN field.
	RCC_AHB1SMENR_GTZC1SMEN_Pos = 0x18
	// Bit mask of GTZC1SMEN field.
	RCC_AHB1SMENR_GTZC1SMEN_Msk = 0x1000000
	// Bit GTZC1SMEN.
	RCC_AHB1SMENR_GTZC1SMEN = 0x1000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GTZC1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_GTZC1SMEN_Enabled = 0x1
	// Position of BKPSRAMSMEN field.
	RCC_AHB1SMENR_BKPSRAMSMEN_Pos = 0x1c
	// Bit mask of BKPSRAMSMEN field.
	RCC_AHB1SMENR_BKPSRAMSMEN_Msk = 0x10000000
	// Bit BKPSRAMSMEN.
	RCC_AHB1SMENR_BKPSRAMSMEN = 0x10000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_BKPSRAMSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_BKPSRAMSMEN_Enabled = 0x1
	// Position of ICACHESMEN field.
	RCC_AHB1SMENR_ICACHESMEN_Pos = 0x1d
	// Bit mask of ICACHESMEN field.
	RCC_AHB1SMENR_ICACHESMEN_Msk = 0x20000000
	// Bit ICACHESMEN.
	RCC_AHB1SMENR_ICACHESMEN = 0x20000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_ICACHESMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_ICACHESMEN_Enabled = 0x1
	// Position of DCACHE1SMEN field.
	RCC_AHB1SMENR_DCACHE1SMEN_Pos = 0x1e
	// Bit mask of DCACHE1SMEN field.
	RCC_AHB1SMENR_DCACHE1SMEN_Msk = 0x40000000
	// Bit DCACHE1SMEN.
	RCC_AHB1SMENR_DCACHE1SMEN = 0x40000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_DCACHE1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_DCACHE1SMEN_Enabled = 0x1
	// Position of SRAM1SMEN field.
	RCC_AHB1SMENR_SRAM1SMEN_Pos = 0x1f
	// Bit mask of SRAM1SMEN field.
	RCC_AHB1SMENR_SRAM1SMEN_Msk = 0x80000000
	// Bit SRAM1SMEN.
	RCC_AHB1SMENR_SRAM1SMEN = 0x80000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_SRAM1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB1SMENR_SRAM1SMEN_Enabled = 0x1

	// AHB2SMENR1: RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1
	// Position of GPIOASMEN field.
	RCC_AHB2SMENR1_GPIOASMEN_Pos = 0x0
	// Bit mask of GPIOASMEN field.
	RCC_AHB2SMENR1_GPIOASMEN_Msk = 0x1
	// Bit GPIOASMEN.
	RCC_AHB2SMENR1_GPIOASMEN = 0x1
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOASMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOASMEN_Enabled = 0x1
	// Position of GPIOBSMEN field.
	RCC_AHB2SMENR1_GPIOBSMEN_Pos = 0x1
	// Bit mask of GPIOBSMEN field.
	RCC_AHB2SMENR1_GPIOBSMEN_Msk = 0x2
	// Bit GPIOBSMEN.
	RCC_AHB2SMENR1_GPIOBSMEN = 0x2
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOBSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOBSMEN_Enabled = 0x1
	// Position of GPIOCSMEN field.
	RCC_AHB2SMENR1_GPIOCSMEN_Pos = 0x2
	// Bit mask of GPIOCSMEN field.
	RCC_AHB2SMENR1_GPIOCSMEN_Msk = 0x4
	// Bit GPIOCSMEN.
	RCC_AHB2SMENR1_GPIOCSMEN = 0x4
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOCSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOCSMEN_Enabled = 0x1
	// Position of GPIODSMEN field.
	RCC_AHB2SMENR1_GPIODSMEN_Pos = 0x3
	// Bit mask of GPIODSMEN field.
	RCC_AHB2SMENR1_GPIODSMEN_Msk = 0x8
	// Bit GPIODSMEN.
	RCC_AHB2SMENR1_GPIODSMEN = 0x8
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIODSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIODSMEN_Enabled = 0x1
	// Position of GPIOESMEN field.
	RCC_AHB2SMENR1_GPIOESMEN_Pos = 0x4
	// Bit mask of GPIOESMEN field.
	RCC_AHB2SMENR1_GPIOESMEN_Msk = 0x10
	// Bit GPIOESMEN.
	RCC_AHB2SMENR1_GPIOESMEN = 0x10
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOESMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOESMEN_Enabled = 0x1
	// Position of GPIOFSMEN field.
	RCC_AHB2SMENR1_GPIOFSMEN_Pos = 0x5
	// Bit mask of GPIOFSMEN field.
	RCC_AHB2SMENR1_GPIOFSMEN_Msk = 0x20
	// Bit GPIOFSMEN.
	RCC_AHB2SMENR1_GPIOFSMEN = 0x20
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOFSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOFSMEN_Enabled = 0x1
	// Position of GPIOGSMEN field.
	RCC_AHB2SMENR1_GPIOGSMEN_Pos = 0x6
	// Bit mask of GPIOGSMEN field.
	RCC_AHB2SMENR1_GPIOGSMEN_Msk = 0x40
	// Bit GPIOGSMEN.
	RCC_AHB2SMENR1_GPIOGSMEN = 0x40
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOGSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOGSMEN_Enabled = 0x1
	// Position of GPIOHSMEN field.
	RCC_AHB2SMENR1_GPIOHSMEN_Pos = 0x7
	// Bit mask of GPIOHSMEN field.
	RCC_AHB2SMENR1_GPIOHSMEN_Msk = 0x80
	// Bit GPIOHSMEN.
	RCC_AHB2SMENR1_GPIOHSMEN = 0x80
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOHSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOHSMEN_Enabled = 0x1
	// Position of GPIOISMEN field.
	RCC_AHB2SMENR1_GPIOISMEN_Pos = 0x8
	// Bit mask of GPIOISMEN field.
	RCC_AHB2SMENR1_GPIOISMEN_Msk = 0x100
	// Bit GPIOISMEN.
	RCC_AHB2SMENR1_GPIOISMEN = 0x100
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOISMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOISMEN_Enabled = 0x1
	// Position of GPIOJSMEN field.
	RCC_AHB2SMENR1_GPIOJSMEN_Pos = 0x9
	// Bit mask of GPIOJSMEN field.
	RCC_AHB2SMENR1_GPIOJSMEN_Msk = 0x200
	// Bit GPIOJSMEN.
	RCC_AHB2SMENR1_GPIOJSMEN = 0x200
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOJSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_GPIOJSMEN_Enabled = 0x1
	// Position of ADC12SMEN field.
	RCC_AHB2SMENR1_ADC12SMEN_Pos = 0xa
	// Bit mask of ADC12SMEN field.
	RCC_AHB2SMENR1_ADC12SMEN_Msk = 0x400
	// Bit ADC12SMEN.
	RCC_AHB2SMENR1_ADC12SMEN = 0x400
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_ADC12SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_ADC12SMEN_Enabled = 0x1
	// Position of DCMI_PSSISMEN field.
	RCC_AHB2SMENR1_DCMI_PSSISMEN_Pos = 0xc
	// Bit mask of DCMI_PSSISMEN field.
	RCC_AHB2SMENR1_DCMI_PSSISMEN_Msk = 0x1000
	// Bit DCMI_PSSISMEN.
	RCC_AHB2SMENR1_DCMI_PSSISMEN = 0x1000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_DCMI_PSSISMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_DCMI_PSSISMEN_Enabled = 0x1
	// Position of OTGSMEN field.
	RCC_AHB2SMENR1_OTGSMEN_Pos = 0xe
	// Bit mask of OTGSMEN field.
	RCC_AHB2SMENR1_OTGSMEN_Msk = 0x4000
	// Bit OTGSMEN.
	RCC_AHB2SMENR1_OTGSMEN = 0x4000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTGSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTGSMEN_Enabled = 0x1
	// Position of OTGHSPHYSMEN field.
	RCC_AHB2SMENR1_OTGHSPHYSMEN_Pos = 0xf
	// Bit mask of OTGHSPHYSMEN field.
	RCC_AHB2SMENR1_OTGHSPHYSMEN_Msk = 0x8000
	// Bit OTGHSPHYSMEN.
	RCC_AHB2SMENR1_OTGHSPHYSMEN = 0x8000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTGHSPHYSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTGHSPHYSMEN_Enabled = 0x1
	// Position of AESSMEN field.
	RCC_AHB2SMENR1_AESSMEN_Pos = 0x10
	// Bit mask of AESSMEN field.
	RCC_AHB2SMENR1_AESSMEN_Msk = 0x10000
	// Bit AESSMEN.
	RCC_AHB2SMENR1_AESSMEN = 0x10000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_AESSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_AESSMEN_Enabled = 0x1
	// Position of HASHSMEN field.
	RCC_AHB2SMENR1_HASHSMEN_Pos = 0x11
	// Bit mask of HASHSMEN field.
	RCC_AHB2SMENR1_HASHSMEN_Msk = 0x20000
	// Bit HASHSMEN.
	RCC_AHB2SMENR1_HASHSMEN = 0x20000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_HASHSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_HASHSMEN_Enabled = 0x1
	// Position of RNGSMEN field.
	RCC_AHB2SMENR1_RNGSMEN_Pos = 0x12
	// Bit mask of RNGSMEN field.
	RCC_AHB2SMENR1_RNGSMEN_Msk = 0x40000
	// Bit RNGSMEN.
	RCC_AHB2SMENR1_RNGSMEN = 0x40000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_RNGSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_RNGSMEN_Enabled = 0x1
	// Position of PKASMEN field.
	RCC_AHB2SMENR1_PKASMEN_Pos = 0x13
	// Bit mask of PKASMEN field.
	RCC_AHB2SMENR1_PKASMEN_Msk = 0x80000
	// Bit PKASMEN.
	RCC_AHB2SMENR1_PKASMEN = 0x80000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_PKASMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_PKASMEN_Enabled = 0x1
	// Position of SAESSMEN field.
	RCC_AHB2SMENR1_SAESSMEN_Pos = 0x14
	// Bit mask of SAESSMEN field.
	RCC_AHB2SMENR1_SAESSMEN_Msk = 0x100000
	// Bit SAESSMEN.
	RCC_AHB2SMENR1_SAESSMEN = 0x100000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SAESSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SAESSMEN_Enabled = 0x1
	// Position of OCTOSPIMSMEN field.
	RCC_AHB2SMENR1_OCTOSPIMSMEN_Pos = 0x15
	// Bit mask of OCTOSPIMSMEN field.
	RCC_AHB2SMENR1_OCTOSPIMSMEN_Msk = 0x200000
	// Bit OCTOSPIMSMEN.
	RCC_AHB2SMENR1_OCTOSPIMSMEN = 0x200000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OCTOSPIMSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OCTOSPIMSMEN_Enabled = 0x1
	// Position of OTFDEC1SMEN field.
	RCC_AHB2SMENR1_OTFDEC1SMEN_Pos = 0x17
	// Bit mask of OTFDEC1SMEN field.
	RCC_AHB2SMENR1_OTFDEC1SMEN_Msk = 0x800000
	// Bit OTFDEC1SMEN.
	RCC_AHB2SMENR1_OTFDEC1SMEN = 0x800000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTFDEC1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTFDEC1SMEN_Enabled = 0x1
	// Position of OTFDEC2SMEN field.
	RCC_AHB2SMENR1_OTFDEC2SMEN_Pos = 0x18
	// Bit mask of OTFDEC2SMEN field.
	RCC_AHB2SMENR1_OTFDEC2SMEN_Msk = 0x1000000
	// Bit OTFDEC2SMEN.
	RCC_AHB2SMENR1_OTFDEC2SMEN = 0x1000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTFDEC2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_OTFDEC2SMEN_Enabled = 0x1
	// Position of SDMMC1SMEN field.
	RCC_AHB2SMENR1_SDMMC1SMEN_Pos = 0x1b
	// Bit mask of SDMMC1SMEN field.
	RCC_AHB2SMENR1_SDMMC1SMEN_Msk = 0x8000000
	// Bit SDMMC1SMEN.
	RCC_AHB2SMENR1_SDMMC1SMEN = 0x8000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SDMMC1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SDMMC1SMEN_Enabled = 0x1
	// Position of SDMMC2SMEN field.
	RCC_AHB2SMENR1_SDMMC2SMEN_Pos = 0x1c
	// Bit mask of SDMMC2SMEN field.
	RCC_AHB2SMENR1_SDMMC2SMEN_Msk = 0x10000000
	// Bit SDMMC2SMEN.
	RCC_AHB2SMENR1_SDMMC2SMEN = 0x10000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SDMMC2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SDMMC2SMEN_Enabled = 0x1
	// Position of SRAM2SMEN field.
	RCC_AHB2SMENR1_SRAM2SMEN_Pos = 0x1e
	// Bit mask of SRAM2SMEN field.
	RCC_AHB2SMENR1_SRAM2SMEN_Msk = 0x40000000
	// Bit SRAM2SMEN.
	RCC_AHB2SMENR1_SRAM2SMEN = 0x40000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SRAM2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SRAM2SMEN_Enabled = 0x1
	// Position of SRAM3SMEN field.
	RCC_AHB2SMENR1_SRAM3SMEN_Pos = 0x1f
	// Bit mask of SRAM3SMEN field.
	RCC_AHB2SMENR1_SRAM3SMEN_Msk = 0x80000000
	// Bit SRAM3SMEN.
	RCC_AHB2SMENR1_SRAM3SMEN = 0x80000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SRAM3SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR1_SRAM3SMEN_Enabled = 0x1

	// AHB2SMENR2: RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2
	// Position of FSMCSMEN field.
	RCC_AHB2SMENR2_FSMCSMEN_Pos = 0x0
	// Bit mask of FSMCSMEN field.
	RCC_AHB2SMENR2_FSMCSMEN_Msk = 0x1
	// Bit FSMCSMEN.
	RCC_AHB2SMENR2_FSMCSMEN = 0x1
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_FSMCSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_FSMCSMEN_Enabled = 0x1
	// Position of OCTOSPI1SMEN field.
	RCC_AHB2SMENR2_OCTOSPI1SMEN_Pos = 0x4
	// Bit mask of OCTOSPI1SMEN field.
	RCC_AHB2SMENR2_OCTOSPI1SMEN_Msk = 0x10
	// Bit OCTOSPI1SMEN.
	RCC_AHB2SMENR2_OCTOSPI1SMEN = 0x10
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_OCTOSPI1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_OCTOSPI1SMEN_Enabled = 0x1
	// Position of OCTOSPI2SMEN field.
	RCC_AHB2SMENR2_OCTOSPI2SMEN_Pos = 0x8
	// Bit mask of OCTOSPI2SMEN field.
	RCC_AHB2SMENR2_OCTOSPI2SMEN_Msk = 0x100
	// Bit OCTOSPI2SMEN.
	RCC_AHB2SMENR2_OCTOSPI2SMEN = 0x100
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_OCTOSPI2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_OCTOSPI2SMEN_Enabled = 0x1
	// Position of HSPI1SMEN field.
	RCC_AHB2SMENR2_HSPI1SMEN_Pos = 0xc
	// Bit mask of HSPI1SMEN field.
	RCC_AHB2SMENR2_HSPI1SMEN_Msk = 0x1000
	// Bit HSPI1SMEN.
	RCC_AHB2SMENR2_HSPI1SMEN = 0x1000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_HSPI1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_HSPI1SMEN_Enabled = 0x1
	// Position of SRAM6SMEN field.
	RCC_AHB2SMENR2_SRAM6SMEN_Pos = 0x1e
	// Bit mask of SRAM6SMEN field.
	RCC_AHB2SMENR2_SRAM6SMEN_Msk = 0x40000000
	// Bit SRAM6SMEN.
	RCC_AHB2SMENR2_SRAM6SMEN = 0x40000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_SRAM6SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_SRAM6SMEN_Enabled = 0x1
	// Position of SRAM5SMEN field.
	RCC_AHB2SMENR2_SRAM5SMEN_Pos = 0x1f
	// Bit mask of SRAM5SMEN field.
	RCC_AHB2SMENR2_SRAM5SMEN_Msk = 0x80000000
	// Bit SRAM5SMEN.
	RCC_AHB2SMENR2_SRAM5SMEN = 0x80000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_SRAM5SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB2SMENR2_SRAM5SMEN_Enabled = 0x1

	// AHB3SMENR: RCC AHB3 peripheral clock enable in Sleep and Stop modes register
	// Position of LPGPIO1SMEN field.
	RCC_AHB3SMENR_LPGPIO1SMEN_Pos = 0x0
	// Bit mask of LPGPIO1SMEN field.
	RCC_AHB3SMENR_LPGPIO1SMEN_Msk = 0x1
	// Bit LPGPIO1SMEN.
	RCC_AHB3SMENR_LPGPIO1SMEN = 0x1
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_LPGPIO1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_LPGPIO1SMEN_Enabled = 0x1
	// Position of PWRSMEN field.
	RCC_AHB3SMENR_PWRSMEN_Pos = 0x2
	// Bit mask of PWRSMEN field.
	RCC_AHB3SMENR_PWRSMEN_Msk = 0x4
	// Bit PWRSMEN.
	RCC_AHB3SMENR_PWRSMEN = 0x4
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_PWRSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_PWRSMEN_Enabled = 0x1
	// Position of ADC4SMEN field.
	RCC_AHB3SMENR_ADC4SMEN_Pos = 0x5
	// Bit mask of ADC4SMEN field.
	RCC_AHB3SMENR_ADC4SMEN_Msk = 0x20
	// Bit ADC4SMEN.
	RCC_AHB3SMENR_ADC4SMEN = 0x20
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_ADC4SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_ADC4SMEN_Enabled = 0x1
	// Position of DAC1SMEN field.
	RCC_AHB3SMENR_DAC1SMEN_Pos = 0x6
	// Bit mask of DAC1SMEN field.
	RCC_AHB3SMENR_DAC1SMEN_Msk = 0x40
	// Bit DAC1SMEN.
	RCC_AHB3SMENR_DAC1SMEN = 0x40
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_DAC1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_DAC1SMEN_Enabled = 0x1
	// Position of LPDMA1SMEN field.
	RCC_AHB3SMENR_LPDMA1SMEN_Pos = 0x9
	// Bit mask of LPDMA1SMEN field.
	RCC_AHB3SMENR_LPDMA1SMEN_Msk = 0x200
	// Bit LPDMA1SMEN.
	RCC_AHB3SMENR_LPDMA1SMEN = 0x200
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_LPDMA1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_LPDMA1SMEN_Enabled = 0x1
	// Position of ADF1SMEN field.
	RCC_AHB3SMENR_ADF1SMEN_Pos = 0xa
	// Bit mask of ADF1SMEN field.
	RCC_AHB3SMENR_ADF1SMEN_Msk = 0x400
	// Bit ADF1SMEN.
	RCC_AHB3SMENR_ADF1SMEN = 0x400
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_ADF1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_ADF1SMEN_Enabled = 0x1
	// Position of GTZC2SMEN field.
	RCC_AHB3SMENR_GTZC2SMEN_Pos = 0xc
	// Bit mask of GTZC2SMEN field.
	RCC_AHB3SMENR_GTZC2SMEN_Msk = 0x1000
	// Bit GTZC2SMEN.
	RCC_AHB3SMENR_GTZC2SMEN = 0x1000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_GTZC2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_GTZC2SMEN_Enabled = 0x1
	// Position of SRAM4SMEN field.
	RCC_AHB3SMENR_SRAM4SMEN_Pos = 0x1f
	// Bit mask of SRAM4SMEN field.
	RCC_AHB3SMENR_SRAM4SMEN_Msk = 0x80000000
	// Bit SRAM4SMEN.
	RCC_AHB3SMENR_SRAM4SMEN = 0x80000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_SRAM4SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_AHB3SMENR_SRAM4SMEN_Enabled = 0x1

	// APB1SMENR1: RCC APB1 peripheral clock enable in Sleep and Stop modes register 1
	// Position of TIM2SMEN field.
	RCC_APB1SMENR1_TIM2SMEN_Pos = 0x0
	// Bit mask of TIM2SMEN field.
	RCC_APB1SMENR1_TIM2SMEN_Msk = 0x1
	// Bit TIM2SMEN.
	RCC_APB1SMENR1_TIM2SMEN = 0x1
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM2SMEN_Enabled = 0x1
	// Position of TIM3SMEN field.
	RCC_APB1SMENR1_TIM3SMEN_Pos = 0x1
	// Bit mask of TIM3SMEN field.
	RCC_APB1SMENR1_TIM3SMEN_Msk = 0x2
	// Bit TIM3SMEN.
	RCC_APB1SMENR1_TIM3SMEN = 0x2
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM3SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM3SMEN_Enabled = 0x1
	// Position of TIM4SMEN field.
	RCC_APB1SMENR1_TIM4SMEN_Pos = 0x2
	// Bit mask of TIM4SMEN field.
	RCC_APB1SMENR1_TIM4SMEN_Msk = 0x4
	// Bit TIM4SMEN.
	RCC_APB1SMENR1_TIM4SMEN = 0x4
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM4SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM4SMEN_Enabled = 0x1
	// Position of TIM5SMEN field.
	RCC_APB1SMENR1_TIM5SMEN_Pos = 0x3
	// Bit mask of TIM5SMEN field.
	RCC_APB1SMENR1_TIM5SMEN_Msk = 0x8
	// Bit TIM5SMEN.
	RCC_APB1SMENR1_TIM5SMEN = 0x8
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM5SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM5SMEN_Enabled = 0x1
	// Position of TIM6SMEN field.
	RCC_APB1SMENR1_TIM6SMEN_Pos = 0x4
	// Bit mask of TIM6SMEN field.
	RCC_APB1SMENR1_TIM6SMEN_Msk = 0x10
	// Bit TIM6SMEN.
	RCC_APB1SMENR1_TIM6SMEN = 0x10
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM6SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM6SMEN_Enabled = 0x1
	// Position of TIM7SMEN field.
	RCC_APB1SMENR1_TIM7SMEN_Pos = 0x5
	// Bit mask of TIM7SMEN field.
	RCC_APB1SMENR1_TIM7SMEN_Msk = 0x20
	// Bit TIM7SMEN.
	RCC_APB1SMENR1_TIM7SMEN = 0x20
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM7SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_TIM7SMEN_Enabled = 0x1
	// Position of WWDGSMEN field.
	RCC_APB1SMENR1_WWDGSMEN_Pos = 0xb
	// Bit mask of WWDGSMEN field.
	RCC_APB1SMENR1_WWDGSMEN_Msk = 0x800
	// Bit WWDGSMEN.
	RCC_APB1SMENR1_WWDGSMEN = 0x800
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_WWDGSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_WWDGSMEN_Enabled = 0x1
	// Position of SPI2SMEN field.
	RCC_APB1SMENR1_SPI2SMEN_Pos = 0xe
	// Bit mask of SPI2SMEN field.
	RCC_APB1SMENR1_SPI2SMEN_Msk = 0x4000
	// Bit SPI2SMEN.
	RCC_APB1SMENR1_SPI2SMEN = 0x4000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_SPI2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_SPI2SMEN_Enabled = 0x1
	// Position of USART2SMEN field.
	RCC_APB1SMENR1_USART2SMEN_Pos = 0x11
	// Bit mask of USART2SMEN field.
	RCC_APB1SMENR1_USART2SMEN_Msk = 0x20000
	// Bit USART2SMEN.
	RCC_APB1SMENR1_USART2SMEN = 0x20000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_USART2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_USART2SMEN_Enabled = 0x1
	// Position of USART3SMEN field.
	RCC_APB1SMENR1_USART3SMEN_Pos = 0x12
	// Bit mask of USART3SMEN field.
	RCC_APB1SMENR1_USART3SMEN_Msk = 0x40000
	// Bit USART3SMEN.
	RCC_APB1SMENR1_USART3SMEN = 0x40000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_USART3SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_USART3SMEN_Enabled = 0x1
	// Position of UART4SMEN field.
	RCC_APB1SMENR1_UART4SMEN_Pos = 0x13
	// Bit mask of UART4SMEN field.
	RCC_APB1SMENR1_UART4SMEN_Msk = 0x80000
	// Bit UART4SMEN.
	RCC_APB1SMENR1_UART4SMEN = 0x80000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_UART4SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_UART4SMEN_Enabled = 0x1
	// Position of UART5SMEN field.
	RCC_APB1SMENR1_UART5SMEN_Pos = 0x14
	// Bit mask of UART5SMEN field.
	RCC_APB1SMENR1_UART5SMEN_Msk = 0x100000
	// Bit UART5SMEN.
	RCC_APB1SMENR1_UART5SMEN = 0x100000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_UART5SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_UART5SMEN_Enabled = 0x1
	// Position of I2C1SMEN field.
	RCC_APB1SMENR1_I2C1SMEN_Pos = 0x15
	// Bit mask of I2C1SMEN field.
	RCC_APB1SMENR1_I2C1SMEN_Msk = 0x200000
	// Bit I2C1SMEN.
	RCC_APB1SMENR1_I2C1SMEN = 0x200000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_I2C1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_I2C1SMEN_Enabled = 0x1
	// Position of I2C2SMEN field.
	RCC_APB1SMENR1_I2C2SMEN_Pos = 0x16
	// Bit mask of I2C2SMEN field.
	RCC_APB1SMENR1_I2C2SMEN_Msk = 0x400000
	// Bit I2C2SMEN.
	RCC_APB1SMENR1_I2C2SMEN = 0x400000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_I2C2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_I2C2SMEN_Enabled = 0x1
	// Position of CRSSMEN field.
	RCC_APB1SMENR1_CRSSMEN_Pos = 0x18
	// Bit mask of CRSSMEN field.
	RCC_APB1SMENR1_CRSSMEN_Msk = 0x1000000
	// Bit CRSSMEN.
	RCC_APB1SMENR1_CRSSMEN = 0x1000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_CRSSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_CRSSMEN_Enabled = 0x1
	// Position of USART6SMEN field.
	RCC_APB1SMENR1_USART6SMEN_Pos = 0x19
	// Bit mask of USART6SMEN field.
	RCC_APB1SMENR1_USART6SMEN_Msk = 0x2000000
	// Bit USART6SMEN.
	RCC_APB1SMENR1_USART6SMEN = 0x2000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_USART6SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR1_USART6SMEN_Enabled = 0x1

	// APB1SMENR2: RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2
	// Position of I2C4SMEN field.
	RCC_APB1SMENR2_I2C4SMEN_Pos = 0x1
	// Bit mask of I2C4SMEN field.
	RCC_APB1SMENR2_I2C4SMEN_Msk = 0x2
	// Bit I2C4SMEN.
	RCC_APB1SMENR2_I2C4SMEN = 0x2
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_I2C4SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_I2C4SMEN_Enabled = 0x1
	// Position of LPTIM2SMEN field.
	RCC_APB1SMENR2_LPTIM2SMEN_Pos = 0x5
	// Bit mask of LPTIM2SMEN field.
	RCC_APB1SMENR2_LPTIM2SMEN_Msk = 0x20
	// Bit LPTIM2SMEN.
	RCC_APB1SMENR2_LPTIM2SMEN = 0x20
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_LPTIM2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_LPTIM2SMEN_Enabled = 0x1
	// Position of I2C5SMEN field.
	RCC_APB1SMENR2_I2C5SMEN_Pos = 0x6
	// Bit mask of I2C5SMEN field.
	RCC_APB1SMENR2_I2C5SMEN_Msk = 0x40
	// Bit I2C5SMEN.
	RCC_APB1SMENR2_I2C5SMEN = 0x40
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_I2C5SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_I2C5SMEN_Enabled = 0x1
	// Position of I2C6SMEN field.
	RCC_APB1SMENR2_I2C6SMEN_Pos = 0x7
	// Bit mask of I2C6SMEN field.
	RCC_APB1SMENR2_I2C6SMEN_Msk = 0x80
	// Bit I2C6SMEN.
	RCC_APB1SMENR2_I2C6SMEN = 0x80
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_I2C6SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_I2C6SMEN_Enabled = 0x1
	// Position of FDCAN1SMEN field.
	RCC_APB1SMENR2_FDCAN1SMEN_Pos = 0x9
	// Bit mask of FDCAN1SMEN field.
	RCC_APB1SMENR2_FDCAN1SMEN_Msk = 0x200
	// Bit FDCAN1SMEN.
	RCC_APB1SMENR2_FDCAN1SMEN = 0x200
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_FDCAN1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_FDCAN1SMEN_Enabled = 0x1
	// Position of UCPD1SMEN field.
	RCC_APB1SMENR2_UCPD1SMEN_Pos = 0x17
	// Bit mask of UCPD1SMEN field.
	RCC_APB1SMENR2_UCPD1SMEN_Msk = 0x800000
	// Bit UCPD1SMEN.
	RCC_APB1SMENR2_UCPD1SMEN = 0x800000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_UCPD1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB1SMENR2_UCPD1SMEN_Enabled = 0x1

	// APB2SMENR: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
	// Position of TIM1SMEN field.
	RCC_APB2SMENR_TIM1SMEN_Pos = 0xb
	// Bit mask of TIM1SMEN field.
	RCC_APB2SMENR_TIM1SMEN_Msk = 0x800
	// Bit TIM1SMEN.
	RCC_APB2SMENR_TIM1SMEN = 0x800
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM1SMEN_Enabled = 0x1
	// Position of SPI1SMEN field.
	RCC_APB2SMENR_SPI1SMEN_Pos = 0xc
	// Bit mask of SPI1SMEN field.
	RCC_APB2SMENR_SPI1SMEN_Msk = 0x1000
	// Bit SPI1SMEN.
	RCC_APB2SMENR_SPI1SMEN = 0x1000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_SPI1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_SPI1SMEN_Enabled = 0x1
	// Position of TIM8SMEN field.
	RCC_APB2SMENR_TIM8SMEN_Pos = 0xd
	// Bit mask of TIM8SMEN field.
	RCC_APB2SMENR_TIM8SMEN_Msk = 0x2000
	// Bit TIM8SMEN.
	RCC_APB2SMENR_TIM8SMEN = 0x2000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM8SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM8SMEN_Enabled = 0x1
	// Position of USART1SMEN field.
	RCC_APB2SMENR_USART1SMEN_Pos = 0xe
	// Bit mask of USART1SMEN field.
	RCC_APB2SMENR_USART1SMEN_Msk = 0x4000
	// Bit USART1SMEN.
	RCC_APB2SMENR_USART1SMEN = 0x4000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_USART1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_USART1SMEN_Enabled = 0x1
	// Position of TIM15SMEN field.
	RCC_APB2SMENR_TIM15SMEN_Pos = 0x10
	// Bit mask of TIM15SMEN field.
	RCC_APB2SMENR_TIM15SMEN_Msk = 0x10000
	// Bit TIM15SMEN.
	RCC_APB2SMENR_TIM15SMEN = 0x10000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM15SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM15SMEN_Enabled = 0x1
	// Position of TIM16SMEN field.
	RCC_APB2SMENR_TIM16SMEN_Pos = 0x11
	// Bit mask of TIM16SMEN field.
	RCC_APB2SMENR_TIM16SMEN_Msk = 0x20000
	// Bit TIM16SMEN.
	RCC_APB2SMENR_TIM16SMEN = 0x20000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM16SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM16SMEN_Enabled = 0x1
	// Position of TIM17SMEN field.
	RCC_APB2SMENR_TIM17SMEN_Pos = 0x12
	// Bit mask of TIM17SMEN field.
	RCC_APB2SMENR_TIM17SMEN_Msk = 0x40000
	// Bit TIM17SMEN.
	RCC_APB2SMENR_TIM17SMEN = 0x40000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM17SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_TIM17SMEN_Enabled = 0x1
	// Position of SAI1SMEN field.
	RCC_APB2SMENR_SAI1SMEN_Pos = 0x15
	// Bit mask of SAI1SMEN field.
	RCC_APB2SMENR_SAI1SMEN_Msk = 0x200000
	// Bit SAI1SMEN.
	RCC_APB2SMENR_SAI1SMEN = 0x200000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_SAI1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_SAI1SMEN_Enabled = 0x1
	// Position of SAI2SMEN field.
	RCC_APB2SMENR_SAI2SMEN_Pos = 0x16
	// Bit mask of SAI2SMEN field.
	RCC_APB2SMENR_SAI2SMEN_Msk = 0x400000
	// Bit SAI2SMEN.
	RCC_APB2SMENR_SAI2SMEN = 0x400000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_SAI2SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_SAI2SMEN_Enabled = 0x1
	// Position of USBSMEN field.
	RCC_APB2SMENR_USBSMEN_Pos = 0x18
	// Bit mask of USBSMEN field.
	RCC_APB2SMENR_USBSMEN_Msk = 0x1000000
	// Bit USBSMEN.
	RCC_APB2SMENR_USBSMEN = 0x1000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_USBSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_USBSMEN_Enabled = 0x1
	// Position of GFXTIMSMEN field.
	RCC_APB2SMENR_GFXTIMSMEN_Pos = 0x19
	// Bit mask of GFXTIMSMEN field.
	RCC_APB2SMENR_GFXTIMSMEN_Msk = 0x2000000
	// Bit GFXTIMSMEN.
	RCC_APB2SMENR_GFXTIMSMEN = 0x2000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_GFXTIMSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_GFXTIMSMEN_Enabled = 0x1
	// Position of LTDCSMEN field.
	RCC_APB2SMENR_LTDCSMEN_Pos = 0x1a
	// Bit mask of LTDCSMEN field.
	RCC_APB2SMENR_LTDCSMEN_Msk = 0x4000000
	// Bit LTDCSMEN.
	RCC_APB2SMENR_LTDCSMEN = 0x4000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_LTDCSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_LTDCSMEN_Enabled = 0x1
	// Position of DSISMEN field.
	RCC_APB2SMENR_DSISMEN_Pos = 0x1b
	// Bit mask of DSISMEN field.
	RCC_APB2SMENR_DSISMEN_Msk = 0x8000000
	// Bit DSISMEN.
	RCC_APB2SMENR_DSISMEN = 0x8000000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_DSISMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB2SMENR_DSISMEN_Enabled = 0x1

	// APB3SMENR: RCC APB3 peripheral clock enable in Sleep and Stop modes register
	// Position of SYSCFGSMEN field.
	RCC_APB3SMENR_SYSCFGSMEN_Pos = 0x1
	// Bit mask of SYSCFGSMEN field.
	RCC_APB3SMENR_SYSCFGSMEN_Msk = 0x2
	// Bit SYSCFGSMEN.
	RCC_APB3SMENR_SYSCFGSMEN = 0x2
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_SYSCFGSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_SYSCFGSMEN_Enabled = 0x1
	// Position of SPI3SMEN field.
	RCC_APB3SMENR_SPI3SMEN_Pos = 0x5
	// Bit mask of SPI3SMEN field.
	RCC_APB3SMENR_SPI3SMEN_Msk = 0x20
	// Bit SPI3SMEN.
	RCC_APB3SMENR_SPI3SMEN = 0x20
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_SPI3SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_SPI3SMEN_Enabled = 0x1
	// Position of LPUART1SMEN field.
	RCC_APB3SMENR_LPUART1SMEN_Pos = 0x6
	// Bit mask of LPUART1SMEN field.
	RCC_APB3SMENR_LPUART1SMEN_Msk = 0x40
	// Bit LPUART1SMEN.
	RCC_APB3SMENR_LPUART1SMEN = 0x40
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPUART1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPUART1SMEN_Enabled = 0x1
	// Position of I2C3SMEN field.
	RCC_APB3SMENR_I2C3SMEN_Pos = 0x7
	// Bit mask of I2C3SMEN field.
	RCC_APB3SMENR_I2C3SMEN_Msk = 0x80
	// Bit I2C3SMEN.
	RCC_APB3SMENR_I2C3SMEN = 0x80
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_I2C3SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_I2C3SMEN_Enabled = 0x1
	// Position of LPTIM1SMEN field.
	RCC_APB3SMENR_LPTIM1SMEN_Pos = 0xb
	// Bit mask of LPTIM1SMEN field.
	RCC_APB3SMENR_LPTIM1SMEN_Msk = 0x800
	// Bit LPTIM1SMEN.
	RCC_APB3SMENR_LPTIM1SMEN = 0x800
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPTIM1SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPTIM1SMEN_Enabled = 0x1
	// Position of LPTIM3SMEN field.
	RCC_APB3SMENR_LPTIM3SMEN_Pos = 0xc
	// Bit mask of LPTIM3SMEN field.
	RCC_APB3SMENR_LPTIM3SMEN_Msk = 0x1000
	// Bit LPTIM3SMEN.
	RCC_APB3SMENR_LPTIM3SMEN = 0x1000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPTIM3SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPTIM3SMEN_Enabled = 0x1
	// Position of LPTIM4SMEN field.
	RCC_APB3SMENR_LPTIM4SMEN_Pos = 0xd
	// Bit mask of LPTIM4SMEN field.
	RCC_APB3SMENR_LPTIM4SMEN_Msk = 0x2000
	// Bit LPTIM4SMEN.
	RCC_APB3SMENR_LPTIM4SMEN = 0x2000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPTIM4SMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_LPTIM4SMEN_Enabled = 0x1
	// Position of OPAMPSMEN field.
	RCC_APB3SMENR_OPAMPSMEN_Pos = 0xe
	// Bit mask of OPAMPSMEN field.
	RCC_APB3SMENR_OPAMPSMEN_Msk = 0x4000
	// Bit OPAMPSMEN.
	RCC_APB3SMENR_OPAMPSMEN = 0x4000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_OPAMPSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_OPAMPSMEN_Enabled = 0x1
	// Position of COMPSMEN field.
	RCC_APB3SMENR_COMPSMEN_Pos = 0xf
	// Bit mask of COMPSMEN field.
	RCC_APB3SMENR_COMPSMEN_Msk = 0x8000
	// Bit COMPSMEN.
	RCC_APB3SMENR_COMPSMEN = 0x8000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_COMPSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_COMPSMEN_Enabled = 0x1
	// Position of VREFSMEN field.
	RCC_APB3SMENR_VREFSMEN_Pos = 0x14
	// Bit mask of VREFSMEN field.
	RCC_APB3SMENR_VREFSMEN_Msk = 0x100000
	// Bit VREFSMEN.
	RCC_APB3SMENR_VREFSMEN = 0x100000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_VREFSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_VREFSMEN_Enabled = 0x1
	// Position of RTCAPBSMEN field.
	RCC_APB3SMENR_RTCAPBSMEN_Pos = 0x15
	// Bit mask of RTCAPBSMEN field.
	RCC_APB3SMENR_RTCAPBSMEN_Msk = 0x200000
	// Bit RTCAPBSMEN.
	RCC_APB3SMENR_RTCAPBSMEN = 0x200000
	// Peripheral clocks disabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_RTCAPBSMEN_Disabled = 0x0
	// Peripheral clocks enabled by the clock gating during Sleep and Stop modes
	RCC_APB3SMENR_RTCAPBSMEN_Enabled = 0x1

	// SRDAMR: RCC SmartRun domain peripheral autonomous mode register
	// Position of SPI3AMEN field.
	RCC_SRDAMR_SPI3AMEN_Pos = 0x5
	// Bit mask of SPI3AMEN field.
	RCC_SRDAMR_SPI3AMEN_Msk = 0x20
	// Bit SPI3AMEN.
	RCC_SRDAMR_SPI3AMEN = 0x20
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_SPI3AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_SPI3AMEN_Enabled = 0x1
	// Position of LPUART1AMEN field.
	RCC_SRDAMR_LPUART1AMEN_Pos = 0x6
	// Bit mask of LPUART1AMEN field.
	RCC_SRDAMR_LPUART1AMEN_Msk = 0x40
	// Bit LPUART1AMEN.
	RCC_SRDAMR_LPUART1AMEN = 0x40
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPUART1AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPUART1AMEN_Enabled = 0x1
	// Position of I2C3AMEN field.
	RCC_SRDAMR_I2C3AMEN_Pos = 0x7
	// Bit mask of I2C3AMEN field.
	RCC_SRDAMR_I2C3AMEN_Msk = 0x80
	// Bit I2C3AMEN.
	RCC_SRDAMR_I2C3AMEN = 0x80
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_I2C3AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_I2C3AMEN_Enabled = 0x1
	// Position of LPTIM1AMEN field.
	RCC_SRDAMR_LPTIM1AMEN_Pos = 0xb
	// Bit mask of LPTIM1AMEN field.
	RCC_SRDAMR_LPTIM1AMEN_Msk = 0x800
	// Bit LPTIM1AMEN.
	RCC_SRDAMR_LPTIM1AMEN = 0x800
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPTIM1AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPTIM1AMEN_Enabled = 0x1
	// Position of LPTIM3AMEN field.
	RCC_SRDAMR_LPTIM3AMEN_Pos = 0xc
	// Bit mask of LPTIM3AMEN field.
	RCC_SRDAMR_LPTIM3AMEN_Msk = 0x1000
	// Bit LPTIM3AMEN.
	RCC_SRDAMR_LPTIM3AMEN = 0x1000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPTIM3AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPTIM3AMEN_Enabled = 0x1
	// Position of LPTIM4AMEN field.
	RCC_SRDAMR_LPTIM4AMEN_Pos = 0xd
	// Bit mask of LPTIM4AMEN field.
	RCC_SRDAMR_LPTIM4AMEN_Msk = 0x2000
	// Bit LPTIM4AMEN.
	RCC_SRDAMR_LPTIM4AMEN = 0x2000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPTIM4AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPTIM4AMEN_Enabled = 0x1
	// Position of OPAMPAMEN field.
	RCC_SRDAMR_OPAMPAMEN_Pos = 0xe
	// Bit mask of OPAMPAMEN field.
	RCC_SRDAMR_OPAMPAMEN_Msk = 0x4000
	// Bit OPAMPAMEN.
	RCC_SRDAMR_OPAMPAMEN = 0x4000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_OPAMPAMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_OPAMPAMEN_Enabled = 0x1
	// Position of COMPAMEN field.
	RCC_SRDAMR_COMPAMEN_Pos = 0xf
	// Bit mask of COMPAMEN field.
	RCC_SRDAMR_COMPAMEN_Msk = 0x8000
	// Bit COMPAMEN.
	RCC_SRDAMR_COMPAMEN = 0x8000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_COMPAMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_COMPAMEN_Enabled = 0x1
	// Position of VREFAMEN field.
	RCC_SRDAMR_VREFAMEN_Pos = 0x14
	// Bit mask of VREFAMEN field.
	RCC_SRDAMR_VREFAMEN_Msk = 0x100000
	// Bit VREFAMEN.
	RCC_SRDAMR_VREFAMEN = 0x100000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_VREFAMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_VREFAMEN_Enabled = 0x1
	// Position of RTCAPBAMEN field.
	RCC_SRDAMR_RTCAPBAMEN_Pos = 0x15
	// Bit mask of RTCAPBAMEN field.
	RCC_SRDAMR_RTCAPBAMEN_Msk = 0x200000
	// Bit RTCAPBAMEN.
	RCC_SRDAMR_RTCAPBAMEN = 0x200000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_RTCAPBAMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_RTCAPBAMEN_Enabled = 0x1
	// Position of ADC4AMEN field.
	RCC_SRDAMR_ADC4AMEN_Pos = 0x19
	// Bit mask of ADC4AMEN field.
	RCC_SRDAMR_ADC4AMEN_Msk = 0x2000000
	// Bit ADC4AMEN.
	RCC_SRDAMR_ADC4AMEN = 0x2000000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_ADC4AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_ADC4AMEN_Enabled = 0x1
	// Position of LPGPIO1AMEN field.
	RCC_SRDAMR_LPGPIO1AMEN_Pos = 0x1a
	// Bit mask of LPGPIO1AMEN field.
	RCC_SRDAMR_LPGPIO1AMEN_Msk = 0x4000000
	// Bit LPGPIO1AMEN.
	RCC_SRDAMR_LPGPIO1AMEN = 0x4000000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPGPIO1AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPGPIO1AMEN_Enabled = 0x1
	// Position of DAC1AMEN field.
	RCC_SRDAMR_DAC1AMEN_Pos = 0x1b
	// Bit mask of DAC1AMEN field.
	RCC_SRDAMR_DAC1AMEN_Msk = 0x8000000
	// Bit DAC1AMEN.
	RCC_SRDAMR_DAC1AMEN = 0x8000000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_DAC1AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_DAC1AMEN_Enabled = 0x1
	// Position of LPDMA1AMEN field.
	RCC_SRDAMR_LPDMA1AMEN_Pos = 0x1c
	// Bit mask of LPDMA1AMEN field.
	RCC_SRDAMR_LPDMA1AMEN_Msk = 0x10000000
	// Bit LPDMA1AMEN.
	RCC_SRDAMR_LPDMA1AMEN = 0x10000000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPDMA1AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_LPDMA1AMEN_Enabled = 0x1
	// Position of ADF1AMEN field.
	RCC_SRDAMR_ADF1AMEN_Pos = 0x1d
	// Bit mask of ADF1AMEN field.
	RCC_SRDAMR_ADF1AMEN_Msk = 0x20000000
	// Bit ADF1AMEN.
	RCC_SRDAMR_ADF1AMEN = 0x20000000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_ADF1AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_ADF1AMEN_Enabled = 0x1
	// Position of SRAM4AMEN field.
	RCC_SRDAMR_SRAM4AMEN_Pos = 0x1f
	// Bit mask of SRAM4AMEN field.
	RCC_SRDAMR_SRAM4AMEN_Msk = 0x80000000
	// Bit SRAM4AMEN.
	RCC_SRDAMR_SRAM4AMEN = 0x80000000
	// Peripheral autonomous mode disabled during Stop 0/1/2 mode
	RCC_SRDAMR_SRAM4AMEN_Disabled = 0x0
	// Peripheral autonomous mode enabled during Stop 0/1/2 mode
	RCC_SRDAMR_SRAM4AMEN_Enabled = 0x1

	// CCIPR1: RCC peripherals independent clock configuration register 1
	// Position of USART1SEL field.
	RCC_CCIPR1_USART1SEL_Pos = 0x0
	// Bit mask of USART1SEL field.
	RCC_CCIPR1_USART1SEL_Msk = 0x3
	// PCLKx selected
	RCC_CCIPR1_USART1SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_USART1SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_USART1SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_USART1SEL_MSIK = 0x3
	// Position of USART2SEL field.
	RCC_CCIPR1_USART2SEL_Pos = 0x2
	// Bit mask of USART2SEL field.
	RCC_CCIPR1_USART2SEL_Msk = 0xc
	// PCLKx selected
	RCC_CCIPR1_USART2SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_USART2SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_USART2SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_USART2SEL_MSIK = 0x3
	// Position of USART3SEL field.
	RCC_CCIPR1_USART3SEL_Pos = 0x4
	// Bit mask of USART3SEL field.
	RCC_CCIPR1_USART3SEL_Msk = 0x30
	// PCLKx selected
	RCC_CCIPR1_USART3SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_USART3SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_USART3SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_USART3SEL_MSIK = 0x3
	// Position of UART4SEL field.
	RCC_CCIPR1_UART4SEL_Pos = 0x6
	// Bit mask of UART4SEL field.
	RCC_CCIPR1_UART4SEL_Msk = 0xc0
	// PCLKx selected
	RCC_CCIPR1_UART4SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_UART4SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_UART4SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_UART4SEL_MSIK = 0x3
	// Position of UART5SEL field.
	RCC_CCIPR1_UART5SEL_Pos = 0x8
	// Bit mask of UART5SEL field.
	RCC_CCIPR1_UART5SEL_Msk = 0x300
	// PCLKx selected
	RCC_CCIPR1_UART5SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_UART5SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_UART5SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_UART5SEL_MSIK = 0x3
	// Position of I2C1SEL field.
	RCC_CCIPR1_I2C1SEL_Pos = 0xa
	// Bit mask of I2C1SEL field.
	RCC_CCIPR1_I2C1SEL_Msk = 0xc00
	// PCLKx selected
	RCC_CCIPR1_I2C1SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_I2C1SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_I2C1SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_I2C1SEL_MSIK = 0x3
	// Position of I2C2SEL field.
	RCC_CCIPR1_I2C2SEL_Pos = 0xc
	// Bit mask of I2C2SEL field.
	RCC_CCIPR1_I2C2SEL_Msk = 0x3000
	// PCLKx selected
	RCC_CCIPR1_I2C2SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_I2C2SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_I2C2SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_I2C2SEL_MSIK = 0x3
	// Position of I2C4SEL field.
	RCC_CCIPR1_I2C4SEL_Pos = 0xe
	// Bit mask of I2C4SEL field.
	RCC_CCIPR1_I2C4SEL_Msk = 0xc000
	// PCLKx selected
	RCC_CCIPR1_I2C4SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_I2C4SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_I2C4SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_I2C4SEL_MSIK = 0x3
	// Position of SPI2SEL field.
	RCC_CCIPR1_SPI2SEL_Pos = 0x10
	// Bit mask of SPI2SEL field.
	RCC_CCIPR1_SPI2SEL_Msk = 0x30000
	// PCLKx selected
	RCC_CCIPR1_SPI2SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_SPI2SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_SPI2SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_SPI2SEL_MSIK = 0x3
	// Position of LPTIM2SEL field.
	RCC_CCIPR1_LPTIM2SEL_Pos = 0x12
	// Bit mask of LPTIM2SEL field.
	RCC_CCIPR1_LPTIM2SEL_Msk = 0xc0000
	// PCLK1 selected
	RCC_CCIPR1_LPTIM2SEL_PCLK1 = 0x0
	// LSI selected
	RCC_CCIPR1_LPTIM2SEL_LSI = 0x1
	// HSI16 selected
	RCC_CCIPR1_LPTIM2SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_LPTIM2SEL_MSIK = 0x3
	// Position of SPI1SEL field.
	RCC_CCIPR1_SPI1SEL_Pos = 0x14
	// Bit mask of SPI1SEL field.
	RCC_CCIPR1_SPI1SEL_Msk = 0x300000
	// PCLKx selected
	RCC_CCIPR1_SPI1SEL_PCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR1_SPI1SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR1_SPI1SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR1_SPI1SEL_MSIK = 0x3
	// Position of SYSTICKSEL field.
	RCC_CCIPR1_SYSTICKSEL_Pos = 0x16
	// Bit mask of SYSTICKSEL field.
	RCC_CCIPR1_SYSTICKSEL_Msk = 0xc00000
	// HCLK/8 selected
	RCC_CCIPR1_SYSTICKSEL_HCLK_Div8 = 0x0
	// LSI selected
	RCC_CCIPR1_SYSTICKSEL_LSI = 0x1
	// LSE selected
	RCC_CCIPR1_SYSTICKSEL_LSE = 0x2
	// Position of FDCAN1SEL field.
	RCC_CCIPR1_FDCAN1SEL_Pos = 0x18
	// Bit mask of FDCAN1SEL field.
	RCC_CCIPR1_FDCAN1SEL_Msk = 0x3000000
	// HSE clock selected
	RCC_CCIPR1_FDCAN1SEL_HSE = 0x0
	// PLL1 "Q" (pll2_q_ck) selected
	RCC_CCIPR1_FDCAN1SEL_PLL1Q = 0x1
	// PLL2 "P" (pll1_p_ck) selected
	RCC_CCIPR1_FDCAN1SEL_PLL2P = 0x2
	// Position of ICLKSEL field.
	RCC_CCIPR1_ICLKSEL_Pos = 0x1a
	// Bit mask of ICLKSEL field.
	RCC_CCIPR1_ICLKSEL_Msk = 0xc000000
	// HSI48 clock selected
	RCC_CCIPR1_ICLKSEL_HSI = 0x0
	// PLL2 "Q" (pll2_q_ck) selected
	RCC_CCIPR1_ICLKSEL_PLL2Q = 0x1
	// PLL1 "Q" (pll1_q_ck) selected
	RCC_CCIPR1_ICLKSEL_PLL1Q = 0x2
	// MSIK clock selected
	RCC_CCIPR1_ICLKSEL_MSIK = 0x3
	// Position of TIMICSEL field.
	RCC_CCIPR1_TIMICSEL_Pos = 0x1d
	// Bit mask of TIMICSEL field.
	RCC_CCIPR1_TIMICSEL_Msk = 0xe0000000
	// HSI, MSIK and MSIS dividers disabled
	RCC_CCIPR1_TIMICSEL_Disabled = 0x0
	// HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture
	RCC_CCIPR1_TIMICSEL_HsiMsisMsis = 0x4
	// HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture
	RCC_CCIPR1_TIMICSEL_HsiMsisMsik = 0x5
	// HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture
	RCC_CCIPR1_TIMICSEL_HsiMsikMsis = 0x6
	// HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture
	RCC_CCIPR1_TIMICSEL_HsiMsikMsik = 0x7

	// CCIPR2: RCC peripherals independent clock configuration register 2
	// Position of MDF1SEL field.
	RCC_CCIPR2_MDF1SEL_Pos = 0x0
	// Bit mask of MDF1SEL field.
	RCC_CCIPR2_MDF1SEL_Msk = 0x7
	// HCLK selected
	RCC_CCIPR2_MDF1SEL_HCLK = 0x0
	// PLL1 "P" (pll1_p_ck) selected
	RCC_CCIPR2_MDF1SEL_PLL1P = 0x1
	// PLL3 "Q" (pll3_q_ck) selected
	RCC_CCIPR2_MDF1SEL_PLL3Q = 0x2
	// input pin AUDIOCLK selected
	RCC_CCIPR2_MDF1SEL_AUDIOCLK = 0x3
	// MSIK clock selected
	RCC_CCIPR2_MDF1SEL_MSIK = 0x4
	// Position of SAI1SEL field.
	RCC_CCIPR2_SAI1SEL_Pos = 0x5
	// Bit mask of SAI1SEL field.
	RCC_CCIPR2_SAI1SEL_Msk = 0xe0
	// PLL2 "P" (pll2_p_ck) selected
	RCC_CCIPR2_SAI1SEL_PLL2P = 0x0
	// PLL3 "P" (pll3_p_ck) selected
	RCC_CCIPR2_SAI1SEL_PLL3P = 0x1
	// PLL1 "P" (pll1_p_ck) selected
	RCC_CCIPR2_SAI1SEL_PLL1P = 0x2
	// input pin AUDIOCLK selected
	RCC_CCIPR2_SAI1SEL_AUDIOCLK = 0x3
	// HSI16 clock selected
	RCC_CCIPR2_SAI1SEL_HSI16 = 0x4
	// Position of SAI2SEL field.
	RCC_CCIPR2_SAI2SEL_Pos = 0x8
	// Bit mask of SAI2SEL field.
	RCC_CCIPR2_SAI2SEL_Msk = 0x700
	// PLL2 "P" (pll2_p_ck) selected
	RCC_CCIPR2_SAI2SEL_PLL2P = 0x0
	// PLL3 "P" (pll3_p_ck) selected
	RCC_CCIPR2_SAI2SEL_PLL3P = 0x1
	// PLL1 "P" (pll1_p_ck) selected
	RCC_CCIPR2_SAI2SEL_PLL1P = 0x2
	// input pin AUDIOCLK selected
	RCC_CCIPR2_SAI2SEL_AUDIOCLK = 0x3
	// HSI16 clock selected
	RCC_CCIPR2_SAI2SEL_HSI16 = 0x4
	// Position of SAESSEL field.
	RCC_CCIPR2_SAESSEL_Pos = 0xb
	// Bit mask of SAESSEL field.
	RCC_CCIPR2_SAESSEL_Msk = 0x800
	// Bit SAESSEL.
	RCC_CCIPR2_SAESSEL = 0x800
	// SHSI selected
	RCC_CCIPR2_SAESSEL_SHSI = 0x0
	// SHSI / 2 selected, can be used in range 4
	RCC_CCIPR2_SAESSEL_SHSI_Div2 = 0x1
	// Position of RNGSEL field.
	RCC_CCIPR2_RNGSEL_Pos = 0xc
	// Bit mask of RNGSEL field.
	RCC_CCIPR2_RNGSEL_Msk = 0x3000
	// HSI48 clock selected
	RCC_CCIPR2_RNGSEL_HSI48 = 0x0
	// HSI48 / 2 selected, can be used in range 4
	RCC_CCIPR2_RNGSEL_HSI48_Div2 = 0x1
	// HSI16 selected
	RCC_CCIPR2_RNGSEL_HSI16 = 0x2
	// Position of SDMMCSEL field.
	RCC_CCIPR2_SDMMCSEL_Pos = 0xe
	// Bit mask of SDMMCSEL field.
	RCC_CCIPR2_SDMMCSEL_Msk = 0x4000
	// Bit SDMMCSEL.
	RCC_CCIPR2_SDMMCSEL = 0x4000
	// ICLK clock selected
	RCC_CCIPR2_SDMMCSEL_ICLK = 0x0
	// PLL1 "P" (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)
	RCC_CCIPR2_SDMMCSEL_PLL1P = 0x1
	// Position of DSISEL field.
	RCC_CCIPR2_DSISEL_Pos = 0xf
	// Bit mask of DSISEL field.
	RCC_CCIPR2_DSISEL_Msk = 0x8000
	// Bit DSISEL.
	RCC_CCIPR2_DSISEL = 0x8000
	// PLL3 "P" (pll3_p_ck) selected
	RCC_CCIPR2_DSISEL_PLL3P = 0x0
	// DSI PHY PLL output selected
	RCC_CCIPR2_DSISEL_DSI_PHY_PLL = 0x1
	// Position of USART6SEL field.
	RCC_CCIPR2_USART6SEL_Pos = 0x10
	// Bit mask of USART6SEL field.
	RCC_CCIPR2_USART6SEL_Msk = 0x30000
	// PCLK1 selected
	RCC_CCIPR2_USART6SEL_PCLK1 = 0x0
	// SYSCLK selected
	RCC_CCIPR2_USART6SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR2_USART6SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR2_USART6SEL_MSIK = 0x3
	// Position of LTDCSEL field.
	RCC_CCIPR2_LTDCSEL_Pos = 0x12
	// Bit mask of LTDCSEL field.
	RCC_CCIPR2_LTDCSEL_Msk = 0x40000
	// Bit LTDCSEL.
	RCC_CCIPR2_LTDCSEL = 0x40000
	// PLL3 "R" (pll3_r_ck) selected
	RCC_CCIPR2_LTDCSEL_PLL3R = 0x0
	// PLL2 "R" (pll2_r_ck) selected
	RCC_CCIPR2_LTDCSEL_PLL2R = 0x1
	// Position of OCTOSPISEL field.
	RCC_CCIPR2_OCTOSPISEL_Pos = 0x14
	// Bit mask of OCTOSPISEL field.
	RCC_CCIPR2_OCTOSPISEL_Msk = 0x300000
	// SYSCLK selected
	RCC_CCIPR2_OCTOSPISEL_SYSCLK = 0x0
	// MSIK selected
	RCC_CCIPR2_OCTOSPISEL_MSIK = 0x1
	// PLL1 "Q" (pll1_q_ck) selected, can be up to 200 MHz
	RCC_CCIPR2_OCTOSPISEL_PLL1Q = 0x2
	// PLL2 "Q" (pll2_q_ck) selected, can be up to 200 MHz
	RCC_CCIPR2_OCTOSPISEL_PLL2Q = 0x3
	// Position of HSPI1SEL field.
	RCC_CCIPR2_HSPI1SEL_Pos = 0x16
	// Bit mask of HSPI1SEL field.
	RCC_CCIPR2_HSPI1SEL_Msk = 0xc00000
	// SYSCLK selected
	RCC_CCIPR2_HSPI1SEL_SYSCLK = 0x0
	// PLL1 "Q" (pll1_q_ck) selected, can be up to 200 MHz
	RCC_CCIPR2_HSPI1SEL_PLL1Q = 0x1
	// PLL2 "Q" (pll2_q_ck) selected, can be up to 200 MHz
	RCC_CCIPR2_HSPI1SEL_PLL2Q = 0x2
	// PLL3 "R" (pll3_r_ck) selected, can be up to 200 MHz
	RCC_CCIPR2_HSPI1SEL_PLL3R = 0x3
	// Position of I2C5SEL field.
	RCC_CCIPR2_I2C5SEL_Pos = 0x18
	// Bit mask of I2C5SEL field.
	RCC_CCIPR2_I2C5SEL_Msk = 0x3000000
	// PCLK1 selected
	RCC_CCIPR2_I2C5SEL_PCLK1 = 0x0
	// SYSCLK selected
	RCC_CCIPR2_I2C5SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR2_I2C5SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR2_I2C5SEL_MSIK = 0x3
	// Position of I2C6SEL field.
	RCC_CCIPR2_I2C6SEL_Pos = 0x1a
	// Bit mask of I2C6SEL field.
	RCC_CCIPR2_I2C6SEL_Msk = 0xc000000
	// PCLK1 selected
	RCC_CCIPR2_I2C6SEL_PCLK1 = 0x0
	// SYSCLK selected
	RCC_CCIPR2_I2C6SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR2_I2C6SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR2_I2C6SEL_MSIK = 0x3
	// Position of OTGHSSEL field.
	RCC_CCIPR2_OTGHSSEL_Pos = 0x1e
	// Bit mask of OTGHSSEL field.
	RCC_CCIPR2_OTGHSSEL_Msk = 0xc0000000
	// HSE selected
	RCC_CCIPR2_OTGHSSEL_HSE = 0x0
	// PLL1 "Q" (pll1_q_ck) selected
	RCC_CCIPR2_OTGHSSEL_PLL1P = 0x1
	// HSE/2 selected
	RCC_CCIPR2_OTGHSSEL_HSE2 = 0x2
	// PLL1 "P" divided by 2 (pll1_p_ck/2) selected
	RCC_CCIPR2_OTGHSSEL_PLL1P_Div2 = 0x3

	// CCIPR3: RCC peripherals independent clock configuration register 3
	// Position of LPUART1SEL field.
	RCC_CCIPR3_LPUART1SEL_Pos = 0x0
	// Bit mask of LPUART1SEL field.
	RCC_CCIPR3_LPUART1SEL_Msk = 0x7
	// PCLK3 selected
	RCC_CCIPR3_LPUART1SEL_PCLK3 = 0x0
	// SYSCLK selected
	RCC_CCIPR3_LPUART1SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR3_LPUART1SEL_HSI16 = 0x2
	// LSE selected
	RCC_CCIPR3_LPUART1SEL_LSE = 0x3
	// MSIK selected
	RCC_CCIPR3_LPUART1SEL_MSIK = 0x4
	// Position of SPI3SEL field.
	RCC_CCIPR3_SPI3SEL_Pos = 0x3
	// Bit mask of SPI3SEL field.
	RCC_CCIPR3_SPI3SEL_Msk = 0x18
	// PCLK3 selected
	RCC_CCIPR3_SPI3SEL_PCLK3 = 0x0
	// SYSCLK selected
	RCC_CCIPR3_SPI3SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR3_SPI3SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR3_SPI3SEL_MSIK = 0x3
	// Position of I2C3SEL field.
	RCC_CCIPR3_I2C3SEL_Pos = 0x6
	// Bit mask of I2C3SEL field.
	RCC_CCIPR3_I2C3SEL_Msk = 0xc0
	// PCLK3 selected
	RCC_CCIPR3_I2C3SEL_PCLK3 = 0x0
	// SYSCLK selected
	RCC_CCIPR3_I2C3SEL_SYSCLK = 0x1
	// HSI16 selected
	RCC_CCIPR3_I2C3SEL_HSI16 = 0x2
	// MSIK selected
	RCC_CCIPR3_I2C3SEL_MSIK = 0x3
	// Position of LPTIM34SEL field.
	RCC_CCIPR3_LPTIM34SEL_Pos = 0x8
	// Bit mask of LPTIM34SEL field.
	RCC_CCIPR3_LPTIM34SEL_Msk = 0x300
	// MSIK clock selected
	RCC_CCIPR3_LPTIM34SEL_MSIK = 0x0
	// LSI selected
	RCC_CCIPR3_LPTIM34SEL_LSI = 0x1
	// HSI selected
	RCC_CCIPR3_LPTIM34SEL_HSI = 0x2
	// LSE selected
	RCC_CCIPR3_LPTIM34SEL_LSE = 0x3
	// Position of LPTIM1SEL field.
	RCC_CCIPR3_LPTIM1SEL_Pos = 0xa
	// Bit mask of LPTIM1SEL field.
	RCC_CCIPR3_LPTIM1SEL_Msk = 0xc00
	// MSIK clock selected
	RCC_CCIPR3_LPTIM1SEL_MSIK = 0x0
	// LSI selected
	RCC_CCIPR3_LPTIM1SEL_LSI = 0x1
	// HSI16 selected
	RCC_CCIPR3_LPTIM1SEL_HSI16 = 0x2
	// LSE selected
	RCC_CCIPR3_LPTIM1SEL_LSE = 0x3
	// Position of ADCDACSEL field.
	RCC_CCIPR3_ADCDACSEL_Pos = 0xc
	// Bit mask of ADCDACSEL field.
	RCC_CCIPR3_ADCDACSEL_Msk = 0x7000
	// HCLK clock selected
	RCC_CCIPR3_ADCDACSEL_HCLK = 0x0
	// SYSCLK selected
	RCC_CCIPR3_ADCDACSEL_SYSCLK = 0x1
	// PLL2 "R" (pll2_r_ck) selected
	RCC_CCIPR3_ADCDACSEL_PLL2R = 0x2
	// HSE clock selected
	RCC_CCIPR3_ADCDACSEL_HSE = 0x3
	// HSI16 clock selected
	RCC_CCIPR3_ADCDACSEL_HSI16 = 0x4
	// MSIK clock selected
	RCC_CCIPR3_ADCDACSEL_MSIK = 0x5
	// Position of DAC1SEL field.
	RCC_CCIPR3_DAC1SEL_Pos = 0xf
	// Bit mask of DAC1SEL field.
	RCC_CCIPR3_DAC1SEL_Msk = 0x8000
	// Bit DAC1SEL.
	RCC_CCIPR3_DAC1SEL = 0x8000
	// LSE selected
	RCC_CCIPR3_DAC1SEL_LSE = 0x0
	// LSI selected
	RCC_CCIPR3_DAC1SEL_LSI = 0x1
	// Position of ADF1SEL field.
	RCC_CCIPR3_ADF1SEL_Pos = 0x10
	// Bit mask of ADF1SEL field.
	RCC_CCIPR3_ADF1SEL_Msk = 0x70000
	// HCLK selected
	RCC_CCIPR3_ADF1SEL_HCLK = 0x0
	// PLL1 "P" (pll1_p_ck) selected
	RCC_CCIPR3_ADF1SEL_PLL1P = 0x1
	// PLL3 "Q" (pll3_q_ck) selected
	RCC_CCIPR3_ADF1SEL_PLL3Q = 0x2
	// input pin AUDIOCLK selected
	RCC_CCIPR3_ADF1SEL_AUDIOCLK = 0x3
	// MSIK clock selected
	RCC_CCIPR3_ADF1SEL_MSIK = 0x4

	// BDCR: RCC backup domain control register
	// Position of LSEON field.
	RCC_BDCR_LSEON_Pos = 0x0
	// Bit mask of LSEON field.
	RCC_BDCR_LSEON_Msk = 0x1
	// Bit LSEON.
	RCC_BDCR_LSEON = 0x1
	// LSE oscillator off
	RCC_BDCR_LSEON_Disabled = 0x0
	// LSE oscillator on
	RCC_BDCR_LSEON_Enabled = 0x1
	// Position of LSERDY field.
	RCC_BDCR_LSERDY_Pos = 0x1
	// Bit mask of LSERDY field.
	RCC_BDCR_LSERDY_Msk = 0x2
	// Bit LSERDY.
	RCC_BDCR_LSERDY = 0x2
	// LSE oscillator not ready
	RCC_BDCR_LSERDY_NotReady = 0x0
	// LSE oscillator ready
	RCC_BDCR_LSERDY_Ready = 0x1
	// Position of LSEBYP field.
	RCC_BDCR_LSEBYP_Pos = 0x2
	// Bit mask of LSEBYP field.
	RCC_BDCR_LSEBYP_Msk = 0x4
	// Bit LSEBYP.
	RCC_BDCR_LSEBYP = 0x4
	// LSE oscillator not bypassed
	RCC_BDCR_LSEBYP_NotBypassed = 0x0
	// LSE oscillator bypassed
	RCC_BDCR_LSEBYP_Bypassed = 0x1
	// Position of LSEDRV field.
	RCC_BDCR_LSEDRV_Pos = 0x3
	// Bit mask of LSEDRV field.
	RCC_BDCR_LSEDRV_Msk = 0x18
	// 'Xtal mode' lower driving capability
	RCC_BDCR_LSEDRV_Lower = 0x0
	// 'Xtal mode' medium-low driving capability
	RCC_BDCR_LSEDRV_MediumLow = 0x1
	// 'Xtal mode' medium-high driving capability
	RCC_BDCR_LSEDRV_MediumHigh = 0x2
	// 'Xtal mode' higher driving capability
	RCC_BDCR_LSEDRV_Higher = 0x3
	// Position of LSECSSON field.
	RCC_BDCR_LSECSSON_Pos = 0x5
	// Bit mask of LSECSSON field.
	RCC_BDCR_LSECSSON_Msk = 0x20
	// Bit LSECSSON.
	RCC_BDCR_LSECSSON = 0x20
	// CSS on LSE OFF
	RCC_BDCR_LSECSSON_Disabled = 0x0
	// CSS on LSE ON
	RCC_BDCR_LSECSSON_Enabled = 0x1
	// Position of LSECSSD field.
	RCC_BDCR_LSECSSD_Pos = 0x6
	// Bit mask of LSECSSD field.
	RCC_BDCR_LSECSSD_Msk = 0x40
	// Bit LSECSSD.
	RCC_BDCR_LSECSSD = 0x40
	// No failure detected on LSE
	RCC_BDCR_LSECSSD_NoFailure = 0x0
	// Failure detected on LSE
	RCC_BDCR_LSECSSD_Failure = 0x1
	// Position of LSESYSEN field.
	RCC_BDCR_LSESYSEN_Pos = 0x7
	// Bit mask of LSESYSEN field.
	RCC_BDCR_LSESYSEN_Msk = 0x80
	// Bit LSESYSEN.
	RCC_BDCR_LSESYSEN = 0x80
	// LSE can be used only for RTC, TAMP, and CSS on LSE
	RCC_BDCR_LSESYSEN_Disabled = 0x0
	// LSE can be used by any other peripheral or function
	RCC_BDCR_LSESYSEN_Enabled = 0x1
	// Position of RTCSEL field.
	RCC_BDCR_RTCSEL_Pos = 0x8
	// Bit mask of RTCSEL field.
	RCC_BDCR_RTCSEL_Msk = 0x300
	// No clock selected
	RCC_BDCR_RTCSEL_NoClock = 0x0
	// LSE oscillator clock selected
	RCC_BDCR_RTCSEL_LSE = 0x1
	// LSI oscillator clock selected
	RCC_BDCR_RTCSEL_LSI = 0x2
	// HSE oscillator clock divided by 32 selected
	RCC_BDCR_RTCSEL_HSE_Div32 = 0x3
	// Position of LSESYSRDY field.
	RCC_BDCR_LSESYSRDY_Pos = 0xb
	// Bit mask of LSESYSRDY field.
	RCC_BDCR_LSESYSRDY_Msk = 0x800
	// Bit LSESYSRDY.
	RCC_BDCR_LSESYSRDY = 0x800
	// LSESYS clock not ready
	RCC_BDCR_LSESYSRDY_NotReady = 0x0
	// LSESYS clock ready
	RCC_BDCR_LSESYSRDY_Ready = 0x1
	// Position of LSEGFON field.
	RCC_BDCR_LSEGFON_Pos = 0xc
	// Bit mask of LSEGFON field.
	RCC_BDCR_LSEGFON_Msk = 0x1000
	// Bit LSEGFON.
	RCC_BDCR_LSEGFON = 0x1000
	// LSE glitch filter disabled
	RCC_BDCR_LSEGFON_Disabled = 0x0
	// LSE glitch filter enabled
	RCC_BDCR_LSEGFON_Enabled = 0x1
	// Position of RTCEN field.
	RCC_BDCR_RTCEN_Pos = 0xf
	// Bit mask of RTCEN field.
	RCC_BDCR_RTCEN_Msk = 0x8000
	// Bit RTCEN.
	RCC_BDCR_RTCEN = 0x8000
	// RTC and TAMP clock disabled
	RCC_BDCR_RTCEN_Disabled = 0x0
	// RTC and TAMP clock enabled
	RCC_BDCR_RTCEN_Enabled = 0x1
	// Position of BDRST field.
	RCC_BDCR_BDRST_Pos = 0x10
	// Bit mask of BDRST field.
	RCC_BDCR_BDRST_Msk = 0x10000
	// Bit BDRST.
	RCC_BDCR_BDRST = 0x10000
	// Reset not activated
	RCC_BDCR_BDRST_NoReset = 0x0
	// Reset the entire backup domain
	RCC_BDCR_BDRST_Reset = 0x1
	// Position of LSCOEN field.
	RCC_BDCR_LSCOEN_Pos = 0x18
	// Bit mask of LSCOEN field.
	RCC_BDCR_LSCOEN_Msk = 0x1000000
	// Bit LSCOEN.
	RCC_BDCR_LSCOEN = 0x1000000
	// LSCO disabled
	RCC_BDCR_LSCOEN_Disabled = 0x0
	// LSCO enabled
	RCC_BDCR_LSCOEN_Enabled = 0x1
	// Position of LSCOSEL field.
	RCC_BDCR_LSCOSEL_Pos = 0x19
	// Bit mask of LSCOSEL field.
	RCC_BDCR_LSCOSEL_Msk = 0x2000000
	// Bit LSCOSEL.
	RCC_BDCR_LSCOSEL = 0x2000000
	// LSI clock selected
	RCC_BDCR_LSCOSEL_LSI = 0x0
	// LSE clock selected
	RCC_BDCR_LSCOSEL_LSE = 0x1
	// Position of LSION field.
	RCC_BDCR_LSION_Pos = 0x1a
	// Bit mask of LSION field.
	RCC_BDCR_LSION_Msk = 0x4000000
	// Bit LSION.
	RCC_BDCR_LSION = 0x4000000
	// LSI oscillator OFF
	RCC_BDCR_LSION_Disabled = 0x0
	// LSI oscillator ON
	RCC_BDCR_LSION_Enabled = 0x1
	// Position of LSIRDY field.
	RCC_BDCR_LSIRDY_Pos = 0x1b
	// Bit mask of LSIRDY field.
	RCC_BDCR_LSIRDY_Msk = 0x8000000
	// Bit LSIRDY.
	RCC_BDCR_LSIRDY = 0x8000000
	// LSI oscillator not ready
	RCC_BDCR_LSIRDY_NotReady = 0x0
	// LSI oscillator ready
	RCC_BDCR_LSIRDY_Ready = 0x1
	// Position of LSIPREDIV field.
	RCC_BDCR_LSIPREDIV_Pos = 0x1c
	// Bit mask of LSIPREDIV field.
	RCC_BDCR_LSIPREDIV_Msk = 0x10000000
	// Bit LSIPREDIV.
	RCC_BDCR_LSIPREDIV = 0x10000000
	// LSI not divided
	RCC_BDCR_LSIPREDIV_Div1 = 0x0
	// LSI divided by 128
	RCC_BDCR_LSIPREDIV_Div128 = 0x1

	// CSR: RCC control/status register
	// Position of MSIKSRANGE field.
	RCC_CSR_MSIKSRANGE_Pos = 0x8
	// Bit mask of MSIKSRANGE field.
	RCC_CSR_MSIKSRANGE_Msk = 0xf00
	// Range 4 around 4 MHz
	RCC_CSR_MSIKSRANGE_F_4MHZ = 0x4
	// Range 5 around 2 MHz
	RCC_CSR_MSIKSRANGE_F_2MHZ = 0x5
	// Range 6 around 1.33 MHz
	RCC_CSR_MSIKSRANGE_F_1_33MHZ = 0x6
	// Range 7 around 1 MHz
	RCC_CSR_MSIKSRANGE_F_1MHZ = 0x7
	// Range 8 around 3.072 MHz
	RCC_CSR_MSIKSRANGE_F_3_072MHZ = 0x8
	// Position of MSISSRANGE field.
	RCC_CSR_MSISSRANGE_Pos = 0xc
	// Bit mask of MSISSRANGE field.
	RCC_CSR_MSISSRANGE_Msk = 0xf000
	// Range 4 around 4 MHz
	RCC_CSR_MSISSRANGE_F_4MHZ = 0x4
	// Range 5 around 2 MHz
	RCC_CSR_MSISSRANGE_F_2MHZ = 0x5
	// Range 6 around 1.33 MHz
	RCC_CSR_MSISSRANGE_F_1_33MHZ = 0x6
	// Range 7 around 1 MHz
	RCC_CSR_MSISSRANGE_F_1MHZ = 0x7
	// Range 8 around 3.072 MHz
	RCC_CSR_MSISSRANGE_F_3_072MHZ = 0x8
	// Position of RMVF field.
	RCC_CSR_RMVF_Pos = 0x17
	// Bit mask of RMVF field.
	RCC_CSR_RMVF_Msk = 0x800000
	// Bit RMVF.
	RCC_CSR_RMVF = 0x800000
	// Clear the reset flags
	RCC_CSR_RMVF_Clear = 0x1
	// Position of OBLRSTF field.
	RCC_CSR_OBLRSTF_Pos = 0x19
	// Bit mask of OBLRSTF field.
	RCC_CSR_OBLRSTF_Msk = 0x2000000
	// Bit OBLRSTF.
	RCC_CSR_OBLRSTF = 0x2000000
	// No reset from option-byte loading occurred
	RCC_CSR_OBLRSTF_NotOccured = 0x0
	// Reset from option-byte loading occurred
	RCC_CSR_OBLRSTF_Occured = 0x1
	// Position of PINRSTF field.
	RCC_CSR_PINRSTF_Pos = 0x1a
	// Bit mask of PINRSTF field.
	RCC_CSR_PINRSTF_Msk = 0x4000000
	// Bit PINRSTF.
	RCC_CSR_PINRSTF = 0x4000000
	// No reset from NRST pin occurred
	RCC_CSR_PINRSTF_NotOccured = 0x0
	// Reset from NRST pin occurred
	RCC_CSR_PINRSTF_Occured = 0x1
	// Position of BORRSTF field.
	RCC_CSR_BORRSTF_Pos = 0x1b
	// Bit mask of BORRSTF field.
	RCC_CSR_BORRSTF_Msk = 0x8000000
	// Bit BORRSTF.
	RCC_CSR_BORRSTF = 0x8000000
	// No BOR/exit from Shutdown mode reset occurred
	RCC_CSR_BORRSTF_NotOccured = 0x0
	// BOR/exit from Shutdown mode reset occurred
	RCC_CSR_BORRSTF_Occured = 0x1
	// Position of SFTRSTF field.
	RCC_CSR_SFTRSTF_Pos = 0x1c
	// Bit mask of SFTRSTF field.
	RCC_CSR_SFTRSTF_Msk = 0x10000000
	// Bit SFTRSTF.
	RCC_CSR_SFTRSTF = 0x10000000
	// No software reset occurred
	RCC_CSR_SFTRSTF_NotOccured = 0x0
	// Software reset occurred
	RCC_CSR_SFTRSTF_Occured = 0x1
	// Position of IWDGRSTF field.
	RCC_CSR_IWDGRSTF_Pos = 0x1d
	// Bit mask of IWDGRSTF field.
	RCC_CSR_IWDGRSTF_Msk = 0x20000000
	// Bit IWDGRSTF.
	RCC_CSR_IWDGRSTF = 0x20000000
	// No independent watchdog reset occurred
	RCC_CSR_IWDGRSTF_NotOccured = 0x0
	// Independent watchdog reset occurred
	RCC_CSR_IWDGRSTF_Occured = 0x1
	// Position of WWDGRSTF field.
	RCC_CSR_WWDGRSTF_Pos = 0x1e
	// Bit mask of WWDGRSTF field.
	RCC_CSR_WWDGRSTF_Msk = 0x40000000
	// Bit WWDGRSTF.
	RCC_CSR_WWDGRSTF = 0x40000000
	// No window watchdog reset occurred
	RCC_CSR_WWDGRSTF_NotOccured = 0x0
	// Window watchdog reset occurred
	RCC_CSR_WWDGRSTF_Occured = 0x1
	// Position of LPWRRSTF field.
	RCC_CSR_LPWRRSTF_Pos = 0x1f
	// Bit mask of LPWRRSTF field.
	RCC_CSR_LPWRRSTF_Msk = 0x80000000
	// Bit LPWRRSTF.
	RCC_CSR_LPWRRSTF = 0x80000000
	// No illegal low-power mode reset occurred
	RCC_CSR_LPWRRSTF_NotOccured = 0x0
	// Illegal low-power mode reset occurred
	RCC_CSR_LPWRRSTF_Occured = 0x1

	// SECCFGR: RCC secure configuration register
	// Position of HSISEC field.
	RCC_SECCFGR_HSISEC_Pos = 0x0
	// Bit mask of HSISEC field.
	RCC_SECCFGR_HSISEC_Msk = 0x1
	// Bit HSISEC.
	RCC_SECCFGR_HSISEC = 0x1
	// Nonsecure
	RCC_SECCFGR_HSISEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_HSISEC_Secure = 0x1
	// Position of HSESEC field.
	RCC_SECCFGR_HSESEC_Pos = 0x1
	// Bit mask of HSESEC field.
	RCC_SECCFGR_HSESEC_Msk = 0x2
	// Bit HSESEC.
	RCC_SECCFGR_HSESEC = 0x2
	// Nonsecure
	RCC_SECCFGR_HSESEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_HSESEC_Secure = 0x1
	// Position of MSISEC field.
	RCC_SECCFGR_MSISEC_Pos = 0x2
	// Bit mask of MSISEC field.
	RCC_SECCFGR_MSISEC_Msk = 0x4
	// Bit MSISEC.
	RCC_SECCFGR_MSISEC = 0x4
	// Nonsecure
	RCC_SECCFGR_MSISEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_MSISEC_Secure = 0x1
	// Position of LSISEC field.
	RCC_SECCFGR_LSISEC_Pos = 0x3
	// Bit mask of LSISEC field.
	RCC_SECCFGR_LSISEC_Msk = 0x8
	// Bit LSISEC.
	RCC_SECCFGR_LSISEC = 0x8
	// Nonsecure
	RCC_SECCFGR_LSISEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_LSISEC_Secure = 0x1
	// Position of LSESEC field.
	RCC_SECCFGR_LSESEC_Pos = 0x4
	// Bit mask of LSESEC field.
	RCC_SECCFGR_LSESEC_Msk = 0x10
	// Bit LSESEC.
	RCC_SECCFGR_LSESEC = 0x10
	// Nonsecure
	RCC_SECCFGR_LSESEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_LSESEC_Secure = 0x1
	// Position of SYSCLKSEC field.
	RCC_SECCFGR_SYSCLKSEC_Pos = 0x5
	// Bit mask of SYSCLKSEC field.
	RCC_SECCFGR_SYSCLKSEC_Msk = 0x20
	// Bit SYSCLKSEC.
	RCC_SECCFGR_SYSCLKSEC = 0x20
	// Nonsecure
	RCC_SECCFGR_SYSCLKSEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_SYSCLKSEC_Secure = 0x1
	// Position of PRESCSEC field.
	RCC_SECCFGR_PRESCSEC_Pos = 0x6
	// Bit mask of PRESCSEC field.
	RCC_SECCFGR_PRESCSEC_Msk = 0x40
	// Bit PRESCSEC.
	RCC_SECCFGR_PRESCSEC = 0x40
	// Nonsecure
	RCC_SECCFGR_PRESCSEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_PRESCSEC_Secure = 0x1
	// Position of PLL1SEC field.
	RCC_SECCFGR_PLL1SEC_Pos = 0x7
	// Bit mask of PLL1SEC field.
	RCC_SECCFGR_PLL1SEC_Msk = 0x80
	// Bit PLL1SEC.
	RCC_SECCFGR_PLL1SEC = 0x80
	// Nonsecure
	RCC_SECCFGR_PLL1SEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_PLL1SEC_Secure = 0x1
	// Position of PLL2SEC field.
	RCC_SECCFGR_PLL2SEC_Pos = 0x8
	// Bit mask of PLL2SEC field.
	RCC_SECCFGR_PLL2SEC_Msk = 0x100
	// Bit PLL2SEC.
	RCC_SECCFGR_PLL2SEC = 0x100
	// Nonsecure
	RCC_SECCFGR_PLL2SEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_PLL2SEC_Secure = 0x1
	// Position of PLL3SEC field.
	RCC_SECCFGR_PLL3SEC_Pos = 0x9
	// Bit mask of PLL3SEC field.
	RCC_SECCFGR_PLL3SEC_Msk = 0x200
	// Bit PLL3SEC.
	RCC_SECCFGR_PLL3SEC = 0x200
	// Nonsecure
	RCC_SECCFGR_PLL3SEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_PLL3SEC_Secure = 0x1
	// Position of ICLKSEC field.
	RCC_SECCFGR_ICLKSEC_Pos = 0xa
	// Bit mask of ICLKSEC field.
	RCC_SECCFGR_ICLKSEC_Msk = 0x400
	// Bit ICLKSEC.
	RCC_SECCFGR_ICLKSEC = 0x400
	// Nonsecure
	RCC_SECCFGR_ICLKSEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_ICLKSEC_Secure = 0x1
	// Position of HSI48SEC field.
	RCC_SECCFGR_HSI48SEC_Pos = 0xb
	// Bit mask of HSI48SEC field.
	RCC_SECCFGR_HSI48SEC_Msk = 0x800
	// Bit HSI48SEC.
	RCC_SECCFGR_HSI48SEC = 0x800
	// Nonsecure
	RCC_SECCFGR_HSI48SEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_HSI48SEC_Secure = 0x1
	// Position of RMVFSEC field.
	RCC_SECCFGR_RMVFSEC_Pos = 0xc
	// Bit mask of RMVFSEC field.
	RCC_SECCFGR_RMVFSEC_Msk = 0x1000
	// Bit RMVFSEC.
	RCC_SECCFGR_RMVFSEC = 0x1000
	// Nonsecure
	RCC_SECCFGR_RMVFSEC_NonSecure = 0x0
	// Secure
	RCC_SECCFGR_RMVFSEC_Secure = 0x1

	// PRIVCFGR: RCC privilege configuration register
	// Position of SPRIV field.
	RCC_PRIVCFGR_SPRIV_Pos = 0x0
	// Bit mask of SPRIV field.
	RCC_PRIVCFGR_SPRIV_Msk = 0x1
	// Bit SPRIV.
	RCC_PRIVCFGR_SPRIV = 0x1
	// Read and write to RCC secure functions can be done by privileged or unprivileged access
	RCC_PRIVCFGR_SPRIV_Unprivileged = 0x0
	// Read and write to RCC secure functions can be done by privileged access only
	RCC_PRIVCFGR_SPRIV_Privileged = 0x1
	// Position of NSPRIV field.
	RCC_PRIVCFGR_NSPRIV_Pos = 0x1
	// Bit mask of NSPRIV field.
	RCC_PRIVCFGR_NSPRIV_Msk = 0x2
	// Bit NSPRIV.
	RCC_PRIVCFGR_NSPRIV = 0x2
	// Read and write to RCC nonsecure functions can be done by privileged or unprivileged access
	RCC_PRIVCFGR_NSPRIV_Unprivileged = 0x0
	// Read and write to RCC nonsecure functions can be done by privileged access only
	RCC_PRIVCFGR_NSPRIV_Privileged = 0x1
)

// Constants for RNG: Random number generator
const (
	// CR: control register
	// Position of CONFIGLOCK field.
	RNG_CR_CONFIGLOCK_Pos = 0x1f
	// Bit mask of CONFIGLOCK field.
	RNG_CR_CONFIGLOCK_Msk = 0x80000000
	// Bit CONFIGLOCK.
	RNG_CR_CONFIGLOCK = 0x80000000
	// Writes to the RNG_CR configuration bits [29:4] are allowed
	RNG_CR_CONFIGLOCK_Enabled = 0x0
	// Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset
	RNG_CR_CONFIGLOCK_Disabled = 0x1
	// Position of CONDRST field.
	RNG_CR_CONDRST_Pos = 0x1e
	// Bit mask of CONDRST field.
	RNG_CR_CONDRST_Msk = 0x40000000
	// Bit CONDRST.
	RNG_CR_CONDRST = 0x40000000
	// Position of RNG_CONFIG1 field.
	RNG_CR_RNG_CONFIG1_Pos = 0x14
	// Bit mask of RNG_CONFIG1 field.
	RNG_CR_RNG_CONFIG1_Msk = 0x3f00000
	// Recommended value for config A (NIST certifiable)
	RNG_CR_RNG_CONFIG1_ConfigA = 0xf
	// Recommended value for config B (not NIST certifiable)
	RNG_CR_RNG_CONFIG1_ConfigB = 0x18
	// Position of CLKDIV field.
	RNG_CR_CLKDIV_Pos = 0x10
	// Bit mask of CLKDIV field.
	RNG_CR_CLKDIV_Msk = 0xf0000
	// Internal RNG clock after divider is similar to incoming RNG clock
	RNG_CR_CLKDIV_Div1 = 0x0
	// Divide RNG clock by 2^1
	RNG_CR_CLKDIV_Div2 = 0x1
	// Divide RNG clock by 2^2
	RNG_CR_CLKDIV_Div4 = 0x2
	// Divide RNG clock by 2^3
	RNG_CR_CLKDIV_Div8 = 0x3
	// Divide RNG clock by 2^4
	RNG_CR_CLKDIV_Div16 = 0x4
	// Divide RNG clock by 2^5
	RNG_CR_CLKDIV_Div32 = 0x5
	// Divide RNG clock by 2^6
	RNG_CR_CLKDIV_Div64 = 0x6
	// Divide RNG clock by 2^7
	RNG_CR_CLKDIV_Div128 = 0x7
	// Divide RNG clock by 2^8
	RNG_CR_CLKDIV_Div256 = 0x8
	// Divide RNG clock by 2^9
	RNG_CR_CLKDIV_Div512 = 0x9
	// Divide RNG clock by 2^10
	RNG_CR_CLKDIV_Div1024 = 0xa
	// Divide RNG clock by 2^11
	RNG_CR_CLKDIV_Div2048 = 0xb
	// Divide RNG clock by 2^12
	RNG_CR_CLKDIV_Div4096 = 0xc
	// Divide RNG clock by 2^13
	RNG_CR_CLKDIV_Div8192 = 0xd
	// Divide RNG clock by 2^14
	RNG_CR_CLKDIV_Div16384 = 0xe
	// Divide RNG clock by 2^15
	RNG_CR_CLKDIV_Div32768 = 0xf
	// Position of RNG_CONFIG2 field.
	RNG_CR_RNG_CONFIG2_Pos = 0xd
	// Bit mask of RNG_CONFIG2 field.
	RNG_CR_RNG_CONFIG2_Msk = 0xe000
	// Recommended value for config A and B
	RNG_CR_RNG_CONFIG2_ConfigA_B = 0x0
	// Position of NISTC field.
	RNG_CR_NISTC_Pos = 0xc
	// Bit mask of NISTC field.
	RNG_CR_NISTC_Msk = 0x1000
	// Bit NISTC.
	RNG_CR_NISTC = 0x1000
	// Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used
	RNG_CR_NISTC_Default = 0x0
	// Custom values for NIST compliant RNG
	RNG_CR_NISTC_Custom = 0x1
	// Position of RNG_CONFIG3 field.
	RNG_CR_RNG_CONFIG3_Pos = 0x8
	// Bit mask of RNG_CONFIG3 field.
	RNG_CR_RNG_CONFIG3_Msk = 0xf00
	// Recommended value for config B (not NIST certifiable)
	RNG_CR_RNG_CONFIG3_ConfigB = 0x0
	// Recommended value for config A (NIST certifiable)
	RNG_CR_RNG_CONFIG3_ConfigA = 0xd
	// Position of ARDIS field.
	RNG_CR_ARDIS_Pos = 0x7
	// Bit mask of ARDIS field.
	RNG_CR_ARDIS_Msk = 0x80
	// Bit ARDIS.
	RNG_CR_ARDIS = 0x80
	// Position of CED field.
	RNG_CR_CED_Pos = 0x5
	// Bit mask of CED field.
	RNG_CR_CED_Msk = 0x20
	// Bit CED.
	RNG_CR_CED = 0x20
	// Clock error detection is enabled
	RNG_CR_CED_Enabled = 0x0
	// Clock error detection is disabled
	RNG_CR_CED_Disabled = 0x1
	// Position of IE field.
	RNG_CR_IE_Pos = 0x3
	// Bit mask of IE field.
	RNG_CR_IE_Msk = 0x8
	// Bit IE.
	RNG_CR_IE = 0x8
	// RNG interrupt is disabled
	RNG_CR_IE_Disabled = 0x0
	// RNG interrupt is enabled
	RNG_CR_IE_Enabled = 0x1
	// Position of RNGEN field.
	RNG_CR_RNGEN_Pos = 0x2
	// Bit mask of RNGEN field.
	RNG_CR_RNGEN_Msk = 0x4
	// Bit RNGEN.
	RNG_CR_RNGEN = 0x4
	// Random number generator is disabled
	RNG_CR_RNGEN_Disabled = 0x0
	// Random number generator is enabled
	RNG_CR_RNGEN_Enabled = 0x1

	// SR: status register
	// Position of CEIS field.
	RNG_SR_CEIS_Pos = 0x5
	// Bit mask of CEIS field.
	RNG_SR_CEIS_Msk = 0x20
	// Bit CEIS.
	RNG_SR_CEIS = 0x20
	// Clear flag
	RNG_SR_CEIS_Clear = 0x0
	// The RNG clock is correct
	RNG_SR_CEIS_Correct = 0x0
	// The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register
	RNG_SR_CEIS_Slow = 0x1
	// Position of SEIS field.
	RNG_SR_SEIS_Pos = 0x6
	// Bit mask of SEIS field.
	RNG_SR_SEIS_Msk = 0x40
	// Bit SEIS.
	RNG_SR_SEIS = 0x40
	// Clear flag
	RNG_SR_SEIS_Clear = 0x0
	// No faulty sequence detected
	RNG_SR_SEIS_NoFault = 0x0
	// At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register.
	RNG_SR_SEIS_Fault = 0x1
	// Position of SECS field.
	RNG_SR_SECS_Pos = 0x2
	// Bit mask of SECS field.
	RNG_SR_SECS_Msk = 0x4
	// Bit SECS.
	RNG_SR_SECS = 0x4
	// No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.
	RNG_SR_SECS_NoFault = 0x0
	// At least one faulty sequence has been detected - see ref manual for details
	RNG_SR_SECS_Fault = 0x1
	// Position of CECS field.
	RNG_SR_CECS_Pos = 0x1
	// Bit mask of CECS field.
	RNG_SR_CECS_Msk = 0x2
	// Bit CECS.
	RNG_SR_CECS = 0x2
	// The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
	RNG_SR_CECS_Correct = 0x0
	// The RNG clock is too slow
	RNG_SR_CECS_Slow = 0x1
	// Position of DRDY field.
	RNG_SR_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	RNG_SR_DRDY_Msk = 0x1
	// Bit DRDY.
	RNG_SR_DRDY = 0x1
	// The RNG_DR register is not yet valid, no random data is available
	RNG_SR_DRDY_Invalid = 0x0
	// The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated.
	RNG_SR_DRDY_Valid = 0x1

	// DR: data register
	// Position of RNDATA field.
	RNG_DR_RNDATA_Pos = 0x0
	// Bit mask of RNDATA field.
	RNG_DR_RNDATA_Msk = 0xffffffff

	// HTCR: health test control register
	// Position of HTCFG field.
	RNG_HTCR_HTCFG_Pos = 0x0
	// Bit mask of HTCFG field.
	RNG_HTCR_HTCFG_Msk = 0xffffffff
	// Recommended value for RNG certification (0x0000_AA74)
	RNG_HTCR_HTCFG_Recommended = 0xaa74
	// Magic number to be written before any write (0x1759_0ABC)
	RNG_HTCR_HTCFG_Magic = 0x17590abc
)

// Constants for RTC: Real-time clock
const (
	// TR: time register
	// Position of PM field.
	RTC_TR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_TR_PM_Msk = 0x400000
	// Bit PM.
	RTC_TR_PM = 0x400000
	// AM or 24-hour format
	RTC_TR_PM_AM = 0x0
	// PM
	RTC_TR_PM_PM = 0x1
	// Position of HT field.
	RTC_TR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_TR_HT_Msk = 0x300000
	// Position of HU field.
	RTC_TR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_TR_HU_Msk = 0xf0000
	// Position of MNT field.
	RTC_TR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_TR_MNT_Msk = 0x7000
	// Position of MNU field.
	RTC_TR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_TR_MNU_Msk = 0xf00
	// Position of ST field.
	RTC_TR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_TR_ST_Msk = 0x70
	// Position of SU field.
	RTC_TR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_TR_SU_Msk = 0xf

	// DR: date register
	// Position of YT field.
	RTC_DR_YT_Pos = 0x14
	// Bit mask of YT field.
	RTC_DR_YT_Msk = 0xf00000
	// Position of YU field.
	RTC_DR_YU_Pos = 0x10
	// Bit mask of YU field.
	RTC_DR_YU_Msk = 0xf0000
	// Position of WDU field.
	RTC_DR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_DR_WDU_Msk = 0xe000
	// Position of MT field.
	RTC_DR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_DR_MT_Msk = 0x1000
	// Bit MT.
	RTC_DR_MT = 0x1000
	// Position of MU field.
	RTC_DR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_DR_MU_Msk = 0xf00
	// Position of DT field.
	RTC_DR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_DR_DT_Msk = 0x30
	// Position of DU field.
	RTC_DR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_DR_DU_Msk = 0xf

	// SSR: RTC sub second register
	// Position of SS field.
	RTC_SSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_SSR_SS_Msk = 0xffffffff

	// ICSR: RTC initialization control and status register
	// Position of WUTWF field.
	RTC_ICSR_WUTWF_Pos = 0x2
	// Bit mask of WUTWF field.
	RTC_ICSR_WUTWF_Msk = 0x4
	// Bit WUTWF.
	RTC_ICSR_WUTWF = 0x4
	// Wakeup timer configuration update not allowed
	RTC_ICSR_WUTWF_UpdateNotAllowed = 0x0
	// Wakeup timer configuration update allowed
	RTC_ICSR_WUTWF_UpdateAllowed = 0x1
	// Position of SHPF field.
	RTC_ICSR_SHPF_Pos = 0x3
	// Bit mask of SHPF field.
	RTC_ICSR_SHPF_Msk = 0x8
	// Bit SHPF.
	RTC_ICSR_SHPF = 0x8
	// No shift operation is pending
	RTC_ICSR_SHPF_NoShiftPending = 0x0
	// A shift operation is pending
	RTC_ICSR_SHPF_ShiftPending = 0x1
	// Position of INITS field.
	RTC_ICSR_INITS_Pos = 0x4
	// Bit mask of INITS field.
	RTC_ICSR_INITS_Msk = 0x10
	// Bit INITS.
	RTC_ICSR_INITS = 0x10
	// Calendar has not been initialized
	RTC_ICSR_INITS_NotInitalized = 0x0
	// Calendar has been initialized
	RTC_ICSR_INITS_Initalized = 0x1
	// Position of RSF field.
	RTC_ICSR_RSF_Pos = 0x5
	// Bit mask of RSF field.
	RTC_ICSR_RSF_Msk = 0x20
	// Bit RSF.
	RTC_ICSR_RSF = 0x20
	// Calendar shadow registers not yet synchronized
	RTC_ICSR_RSF_NotSynced = 0x0
	// Calendar shadow registers synchronized
	RTC_ICSR_RSF_Synced = 0x1
	// This flag is cleared by software by writing 0
	RTC_ICSR_RSF_Clear = 0x0
	// Position of INITF field.
	RTC_ICSR_INITF_Pos = 0x6
	// Bit mask of INITF field.
	RTC_ICSR_INITF_Msk = 0x40
	// Bit INITF.
	RTC_ICSR_INITF = 0x40
	// Calendar registers update is not allowed
	RTC_ICSR_INITF_NotAllowed = 0x0
	// Calendar registers update is allowed
	RTC_ICSR_INITF_Allowed = 0x1
	// Position of INIT field.
	RTC_ICSR_INIT_Pos = 0x7
	// Bit mask of INIT field.
	RTC_ICSR_INIT_Msk = 0x80
	// Bit INIT.
	RTC_ICSR_INIT = 0x80
	// Free running mode
	RTC_ICSR_INIT_FreeRunningMode = 0x0
	// Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
	RTC_ICSR_INIT_InitMode = 0x1
	// Position of BIN field.
	RTC_ICSR_BIN_Pos = 0x8
	// Bit mask of BIN field.
	RTC_ICSR_BIN_Msk = 0x300
	// Position of BCDU field.
	RTC_ICSR_BCDU_Pos = 0xa
	// Bit mask of BCDU field.
	RTC_ICSR_BCDU_Msk = 0x1c00
	// Position of RECALPF field.
	RTC_ICSR_RECALPF_Pos = 0x10
	// Bit mask of RECALPF field.
	RTC_ICSR_RECALPF_Msk = 0x10000
	// Bit RECALPF.
	RTC_ICSR_RECALPF = 0x10000
	// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
	RTC_ICSR_RECALPF_Pending = 0x1

	// PRER: prescaler register
	// Position of PREDIV_A field.
	RTC_PRER_PREDIV_A_Pos = 0x10
	// Bit mask of PREDIV_A field.
	RTC_PRER_PREDIV_A_Msk = 0x7f0000
	// Position of PREDIV_S field.
	RTC_PRER_PREDIV_S_Pos = 0x0
	// Bit mask of PREDIV_S field.
	RTC_PRER_PREDIV_S_Msk = 0x7fff

	// WUTR: wakeup timer register
	// Position of WUT field.
	RTC_WUTR_WUT_Pos = 0x0
	// Bit mask of WUT field.
	RTC_WUTR_WUT_Msk = 0xffff
	// Position of WUTOCLR field.
	RTC_WUTR_WUTOCLR_Pos = 0x10
	// Bit mask of WUTOCLR field.
	RTC_WUTR_WUTOCLR_Msk = 0xffff0000

	// CR: RTC control register
	// Position of WUCKSEL field.
	RTC_CR_WUCKSEL_Pos = 0x0
	// Bit mask of WUCKSEL field.
	RTC_CR_WUCKSEL_Msk = 0x7
	// RTC/16 clock is selected
	RTC_CR_WUCKSEL_Div16 = 0x0
	// RTC/8 clock is selected
	RTC_CR_WUCKSEL_Div8 = 0x1
	// RTC/4 clock is selected
	RTC_CR_WUCKSEL_Div4 = 0x2
	// RTC/2 clock is selected
	RTC_CR_WUCKSEL_Div2 = 0x3
	// ck_spre (usually 1 Hz) clock is selected
	RTC_CR_WUCKSEL_ClockSpare = 0x4
	// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
	RTC_CR_WUCKSEL_ClockSpareWithOffset = 0x6
	// Position of TSEDGE field.
	RTC_CR_TSEDGE_Pos = 0x3
	// Bit mask of TSEDGE field.
	RTC_CR_TSEDGE_Msk = 0x8
	// Bit TSEDGE.
	RTC_CR_TSEDGE = 0x8
	// RTC_TS input rising edge generates a time-stamp event
	RTC_CR_TSEDGE_RisingEdge = 0x0
	// RTC_TS input falling edge generates a time-stamp event
	RTC_CR_TSEDGE_FallingEdge = 0x1
	// Position of REFCKON field.
	RTC_CR_REFCKON_Pos = 0x4
	// Bit mask of REFCKON field.
	RTC_CR_REFCKON_Msk = 0x10
	// Bit REFCKON.
	RTC_CR_REFCKON = 0x10
	// RTC_REFIN detection disabled
	RTC_CR_REFCKON_Disabled = 0x0
	// RTC_REFIN detection enabled
	RTC_CR_REFCKON_Enabled = 0x1
	// Position of BYPSHAD field.
	RTC_CR_BYPSHAD_Pos = 0x5
	// Bit mask of BYPSHAD field.
	RTC_CR_BYPSHAD_Msk = 0x20
	// Bit BYPSHAD.
	RTC_CR_BYPSHAD = 0x20
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
	RTC_CR_BYPSHAD_ShadowReg = 0x0
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
	RTC_CR_BYPSHAD_BypassShadowReg = 0x1
	// Position of FMT field.
	RTC_CR_FMT_Pos = 0x6
	// Bit mask of FMT field.
	RTC_CR_FMT_Msk = 0x40
	// Bit FMT.
	RTC_CR_FMT = 0x40
	// 24 hour/day format
	RTC_CR_FMT_TwentyFourHour = 0x0
	// AM/PM hour format
	RTC_CR_FMT_AmPm = 0x1
	// Position of SSRUIE field.
	RTC_CR_SSRUIE_Pos = 0x7
	// Bit mask of SSRUIE field.
	RTC_CR_SSRUIE_Msk = 0x80
	// Bit SSRUIE.
	RTC_CR_SSRUIE = 0x80
	// Position of ALRAE field.
	RTC_CR_ALRAE_Pos = 0x9
	// Bit mask of ALRAE field.
	RTC_CR_ALRAE_Msk = 0x200
	// Bit ALRAE.
	RTC_CR_ALRAE = 0x200
	// Alarm disabled
	RTC_CR_ALRAE_Disabled = 0x0
	// Alarm enabled
	RTC_CR_ALRAE_Enabled = 0x1
	// Position of ALRBE field.
	RTC_CR_ALRBE_Pos = 0xa
	// Bit mask of ALRBE field.
	RTC_CR_ALRBE_Msk = 0x400
	// Bit ALRBE.
	RTC_CR_ALRBE = 0x400
	// Alarm disabled
	RTC_CR_ALRBE_Disabled = 0x0
	// Alarm enabled
	RTC_CR_ALRBE_Enabled = 0x1
	// Position of WUTE field.
	RTC_CR_WUTE_Pos = 0xa
	// Bit mask of WUTE field.
	RTC_CR_WUTE_Msk = 0x400
	// Bit WUTE.
	RTC_CR_WUTE = 0x400
	// Wakeup timer disabled
	RTC_CR_WUTE_Disabled = 0x0
	// Wakeup timer enabled
	RTC_CR_WUTE_Enabled = 0x1
	// Position of TSE field.
	RTC_CR_TSE_Pos = 0xb
	// Bit mask of TSE field.
	RTC_CR_TSE_Msk = 0x800
	// Bit TSE.
	RTC_CR_TSE = 0x800
	// Timestamp disabled
	RTC_CR_TSE_Disabled = 0x0
	// Timestamp enabled
	RTC_CR_TSE_Enabled = 0x1
	// Position of ALRAIE field.
	RTC_CR_ALRAIE_Pos = 0xd
	// Bit mask of ALRAIE field.
	RTC_CR_ALRAIE_Msk = 0x2000
	// Bit ALRAIE.
	RTC_CR_ALRAIE = 0x2000
	// Alarm Interrupt disabled
	RTC_CR_ALRAIE_Disabled = 0x0
	// Alarm Interrupt enabled
	RTC_CR_ALRAIE_Enabled = 0x1
	// Position of ALRBIE field.
	RTC_CR_ALRBIE_Pos = 0xe
	// Bit mask of ALRBIE field.
	RTC_CR_ALRBIE_Msk = 0x4000
	// Bit ALRBIE.
	RTC_CR_ALRBIE = 0x4000
	// Alarm Interrupt disabled
	RTC_CR_ALRBIE_Disabled = 0x0
	// Alarm Interrupt enabled
	RTC_CR_ALRBIE_Enabled = 0x1
	// Position of WUTIE field.
	RTC_CR_WUTIE_Pos = 0xe
	// Bit mask of WUTIE field.
	RTC_CR_WUTIE_Msk = 0x4000
	// Bit WUTIE.
	RTC_CR_WUTIE = 0x4000
	// Wakeup timer interrupt disabled
	RTC_CR_WUTIE_Disabled = 0x0
	// Wakeup timer interrupt enabled
	RTC_CR_WUTIE_Enabled = 0x1
	// Position of TSIE field.
	RTC_CR_TSIE_Pos = 0xf
	// Bit mask of TSIE field.
	RTC_CR_TSIE_Msk = 0x8000
	// Bit TSIE.
	RTC_CR_TSIE = 0x8000
	// Time-stamp Interrupt disabled
	RTC_CR_TSIE_Disabled = 0x0
	// Time-stamp Interrupt enabled
	RTC_CR_TSIE_Enabled = 0x1
	// Position of ADD1H field.
	RTC_CR_ADD1H_Pos = 0x10
	// Bit mask of ADD1H field.
	RTC_CR_ADD1H_Msk = 0x10000
	// Bit ADD1H.
	RTC_CR_ADD1H = 0x10000
	// Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
	RTC_CR_ADD1H_Add1 = 0x1
	// Position of SUB1H field.
	RTC_CR_SUB1H_Pos = 0x11
	// Bit mask of SUB1H field.
	RTC_CR_SUB1H_Msk = 0x20000
	// Bit SUB1H.
	RTC_CR_SUB1H = 0x20000
	// Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
	RTC_CR_SUB1H_Sub1 = 0x1
	// Position of BKP field.
	RTC_CR_BKP_Pos = 0x12
	// Bit mask of BKP field.
	RTC_CR_BKP_Msk = 0x40000
	// Bit BKP.
	RTC_CR_BKP = 0x40000
	// Daylight Saving Time change has not been performed
	RTC_CR_BKP_DSTNotChanged = 0x0
	// Daylight Saving Time change has been performed
	RTC_CR_BKP_DSTChanged = 0x1
	// Position of COSEL field.
	RTC_CR_COSEL_Pos = 0x13
	// Bit mask of COSEL field.
	RTC_CR_COSEL_Msk = 0x80000
	// Bit COSEL.
	RTC_CR_COSEL = 0x80000
	// Calibration output is 512 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_512Hz = 0x0
	// Calibration output is 1 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_1Hz = 0x1
	// Position of POL field.
	RTC_CR_POL_Pos = 0x14
	// Bit mask of POL field.
	RTC_CR_POL_Msk = 0x100000
	// Bit POL.
	RTC_CR_POL = 0x100000
	// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_High = 0x0
	// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_Low = 0x1
	// Position of OSEL field.
	RTC_CR_OSEL_Pos = 0x15
	// Bit mask of OSEL field.
	RTC_CR_OSEL_Msk = 0x600000
	// Output disabled
	RTC_CR_OSEL_Disabled = 0x0
	// Alarm A output enabled
	RTC_CR_OSEL_AlarmA = 0x1
	// Alarm B output enabled
	RTC_CR_OSEL_AlarmB = 0x2
	// Wakeup output enabled
	RTC_CR_OSEL_Wakeup = 0x3
	// Position of COE field.
	RTC_CR_COE_Pos = 0x17
	// Bit mask of COE field.
	RTC_CR_COE_Msk = 0x800000
	// Bit COE.
	RTC_CR_COE = 0x800000
	// Calibration output disabled
	RTC_CR_COE_Disabled = 0x0
	// Calibration output enabled
	RTC_CR_COE_Enabled = 0x1
	// Position of ITSE field.
	RTC_CR_ITSE_Pos = 0x18
	// Bit mask of ITSE field.
	RTC_CR_ITSE_Msk = 0x1000000
	// Bit ITSE.
	RTC_CR_ITSE = 0x1000000
	// Internal event timestamp disabled
	RTC_CR_ITSE_Disabled = 0x0
	// Internal event timestamp enabled
	RTC_CR_ITSE_Enabled = 0x1
	// Position of TAMPTS field.
	RTC_CR_TAMPTS_Pos = 0x19
	// Bit mask of TAMPTS field.
	RTC_CR_TAMPTS_Msk = 0x2000000
	// Bit TAMPTS.
	RTC_CR_TAMPTS = 0x2000000
	// Tamper detection event does not cause a RTC timestamp to be saved
	RTC_CR_TAMPTS_Disabled = 0x0
	// Save RTC timestamp on tamper detection event
	RTC_CR_TAMPTS_Enabled = 0x1
	// Position of TAMPOE field.
	RTC_CR_TAMPOE_Pos = 0x1a
	// Bit mask of TAMPOE field.
	RTC_CR_TAMPOE_Msk = 0x4000000
	// Bit TAMPOE.
	RTC_CR_TAMPOE = 0x4000000
	// The tamper flag is not routed on TAMPALRM
	RTC_CR_TAMPOE_Disabled = 0x0
	// The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL
	RTC_CR_TAMPOE_Enabled = 0x1
	// Position of ALRAFCLR field.
	RTC_CR_ALRAFCLR_Pos = 0x1b
	// Bit mask of ALRAFCLR field.
	RTC_CR_ALRAFCLR_Msk = 0x8000000
	// Bit ALRAFCLR.
	RTC_CR_ALRAFCLR = 0x8000000
	// Position of ALRBFCLR field.
	RTC_CR_ALRBFCLR_Pos = 0x1c
	// Bit mask of ALRBFCLR field.
	RTC_CR_ALRBFCLR_Msk = 0x10000000
	// Bit ALRBFCLR.
	RTC_CR_ALRBFCLR = 0x10000000
	// Position of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU_Pos = 0x1d
	// Bit mask of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU_Msk = 0x20000000
	// Bit TAMPALRM_PU.
	RTC_CR_TAMPALRM_PU = 0x20000000
	// No pull-up is applied on TAMPALRM output
	RTC_CR_TAMPALRM_PU_NoPullUp = 0x0
	// A pull-up is applied on TAMPALRM output
	RTC_CR_TAMPALRM_PU_PullUp = 0x1
	// Position of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE_Pos = 0x1e
	// Bit mask of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE_Msk = 0x40000000
	// Bit TAMPALRM_TYPE.
	RTC_CR_TAMPALRM_TYPE = 0x40000000
	// TAMPALRM is push-pull output
	RTC_CR_TAMPALRM_TYPE_PushPull = 0x0
	// TAMPALRM is open-drain output
	RTC_CR_TAMPALRM_TYPE_OpenDrain = 0x1
	// Position of OUT2EN field.
	RTC_CR_OUT2EN_Pos = 0x1f
	// Bit mask of OUT2EN field.
	RTC_CR_OUT2EN_Msk = 0x80000000
	// Bit OUT2EN.
	RTC_CR_OUT2EN = 0x80000000
	// RTC output 2 disable
	RTC_CR_OUT2EN_Disabled = 0x0
	// RTC output 2 enable
	RTC_CR_OUT2EN_Enabled = 0x1

	// PRIVCR: RTC privilege mode control register
	// Position of PRIV field.
	RTC_PRIVCR_PRIV_Pos = 0xf
	// Bit mask of PRIV field.
	RTC_PRIVCR_PRIV_Msk = 0x8000
	// Bit PRIV.
	RTC_PRIVCR_PRIV = 0x8000
	// Position of INITPRIV field.
	RTC_PRIVCR_INITPRIV_Pos = 0xe
	// Bit mask of INITPRIV field.
	RTC_PRIVCR_INITPRIV_Msk = 0x4000
	// Bit INITPRIV.
	RTC_PRIVCR_INITPRIV = 0x4000
	// Position of CALPRIV field.
	RTC_PRIVCR_CALPRIV_Pos = 0xd
	// Bit mask of CALPRIV field.
	RTC_PRIVCR_CALPRIV_Msk = 0x2000
	// Bit CALPRIV.
	RTC_PRIVCR_CALPRIV = 0x2000
	// Position of TSPRIV field.
	RTC_PRIVCR_TSPRIV_Pos = 0x3
	// Bit mask of TSPRIV field.
	RTC_PRIVCR_TSPRIV_Msk = 0x8
	// Bit TSPRIV.
	RTC_PRIVCR_TSPRIV = 0x8
	// Position of WUTPRIV field.
	RTC_PRIVCR_WUTPRIV_Pos = 0x2
	// Bit mask of WUTPRIV field.
	RTC_PRIVCR_WUTPRIV_Msk = 0x4
	// Bit WUTPRIV.
	RTC_PRIVCR_WUTPRIV = 0x4
	// Position of ALRBPRIV field.
	RTC_PRIVCR_ALRBPRIV_Pos = 0x1
	// Bit mask of ALRBPRIV field.
	RTC_PRIVCR_ALRBPRIV_Msk = 0x2
	// Bit ALRBPRIV.
	RTC_PRIVCR_ALRBPRIV = 0x2
	// Position of ALRAPRIV field.
	RTC_PRIVCR_ALRAPRIV_Pos = 0x0
	// Bit mask of ALRAPRIV field.
	RTC_PRIVCR_ALRAPRIV_Msk = 0x1
	// Bit ALRAPRIV.
	RTC_PRIVCR_ALRAPRIV = 0x1

	// SECCFGR: RTC secure mode control register
	// Position of SEC field.
	RTC_SECCFGR_SEC_Pos = 0xf
	// Bit mask of SEC field.
	RTC_SECCFGR_SEC_Msk = 0x8000
	// Bit SEC.
	RTC_SECCFGR_SEC = 0x8000
	// Position of INITSEC field.
	RTC_SECCFGR_INITSEC_Pos = 0xe
	// Bit mask of INITSEC field.
	RTC_SECCFGR_INITSEC_Msk = 0x4000
	// Bit INITSEC.
	RTC_SECCFGR_INITSEC = 0x4000
	// Position of CALSEC field.
	RTC_SECCFGR_CALSEC_Pos = 0xd
	// Bit mask of CALSEC field.
	RTC_SECCFGR_CALSEC_Msk = 0x2000
	// Bit CALSEC.
	RTC_SECCFGR_CALSEC = 0x2000
	// Position of TSSEC field.
	RTC_SECCFGR_TSSEC_Pos = 0x3
	// Bit mask of TSSEC field.
	RTC_SECCFGR_TSSEC_Msk = 0x8
	// Bit TSSEC.
	RTC_SECCFGR_TSSEC = 0x8
	// Position of WUTSEC field.
	RTC_SECCFGR_WUTSEC_Pos = 0x2
	// Bit mask of WUTSEC field.
	RTC_SECCFGR_WUTSEC_Msk = 0x4
	// Bit WUTSEC.
	RTC_SECCFGR_WUTSEC = 0x4
	// Position of ALRBSEC field.
	RTC_SECCFGR_ALRBSEC_Pos = 0x1
	// Bit mask of ALRBSEC field.
	RTC_SECCFGR_ALRBSEC_Msk = 0x2
	// Bit ALRBSEC.
	RTC_SECCFGR_ALRBSEC = 0x2
	// Position of ALRASEC field.
	RTC_SECCFGR_ALRASEC_Pos = 0x0
	// Bit mask of ALRASEC field.
	RTC_SECCFGR_ALRASEC_Msk = 0x1
	// Bit ALRASEC.
	RTC_SECCFGR_ALRASEC = 0x1

	// WPR: write protection register
	// Position of KEY field.
	RTC_WPR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	RTC_WPR_KEY_Msk = 0xff
	// Activate write protection (any value that is not the keys)
	RTC_WPR_KEY_Activate = 0x0
	// Key 2
	RTC_WPR_KEY_Deactivate2 = 0x53
	// Key 1
	RTC_WPR_KEY_Deactivate1 = 0xca

	// CALR: calibration register
	// Position of CALP field.
	RTC_CALR_CALP_Pos = 0xf
	// Bit mask of CALP field.
	RTC_CALR_CALP_Msk = 0x8000
	// Bit CALP.
	RTC_CALR_CALP = 0x8000
	// No RTCCLK pulses are added
	RTC_CALR_CALP_NoChange = 0x0
	// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
	RTC_CALR_CALP_IncreaseFreq = 0x1
	// Position of CALW8 field.
	RTC_CALR_CALW8_Pos = 0xe
	// Bit mask of CALW8 field.
	RTC_CALR_CALW8_Msk = 0x4000
	// Bit CALW8.
	RTC_CALR_CALW8 = 0x4000
	// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
	RTC_CALR_CALW8_EightSeconds = 0x1
	// Position of CALW16 field.
	RTC_CALR_CALW16_Pos = 0xd
	// Bit mask of CALW16 field.
	RTC_CALR_CALW16_Msk = 0x2000
	// Bit CALW16.
	RTC_CALR_CALW16 = 0x2000
	// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
	RTC_CALR_CALW16_SixteenSeconds = 0x1
	// Position of LPCAL field.
	RTC_CALR_LPCAL_Pos = 0xc
	// Bit mask of LPCAL field.
	RTC_CALR_LPCAL_Msk = 0x1000
	// Bit LPCAL.
	RTC_CALR_LPCAL = 0x1000
	// Position of CALM field.
	RTC_CALR_CALM_Pos = 0x0
	// Bit mask of CALM field.
	RTC_CALR_CALM_Msk = 0x1ff

	// SHIFTR: shift control register
	// Position of ADD1S field.
	RTC_SHIFTR_ADD1S_Pos = 0x1f
	// Bit mask of ADD1S field.
	RTC_SHIFTR_ADD1S_Msk = 0x80000000
	// Bit ADD1S.
	RTC_SHIFTR_ADD1S = 0x80000000
	// Add one second to the clock/calendar
	RTC_SHIFTR_ADD1S_Add1 = 0x1
	// Position of SUBFS field.
	RTC_SHIFTR_SUBFS_Pos = 0x0
	// Bit mask of SUBFS field.
	RTC_SHIFTR_SUBFS_Msk = 0x7fff

	// ALRMAR: Alarm %s register
	// Position of MSK1 field.
	RTC_ALRMR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_ALRMR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_ALRMR_MSK1 = 0x80
	// Alarm set if the date/day match
	RTC_ALRMR_MSK1_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK1_NotMask = 0x1
	// Position of MSK4 field.
	RTC_ALRMR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_ALRMR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_ALRMR_MSK4 = 0x80000000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK4_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK4_NotMask = 0x1
	// Position of WDSEL field.
	RTC_ALRMR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_ALRMR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_ALRMR_WDSEL = 0x40000000
	// DU[3:0] represents the date units
	RTC_ALRMR_WDSEL_DateUnits = 0x0
	// DU[3:0] represents the week day. DT[1:0] is don’t care.
	RTC_ALRMR_WDSEL_WeekDay = 0x1
	// Position of DT field.
	RTC_ALRMR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_ALRMR_DT_Msk = 0x30000000
	// Position of DU field.
	RTC_ALRMR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_ALRMR_DU_Msk = 0xf000000
	// Position of MSK3 field.
	RTC_ALRMR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_ALRMR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_ALRMR_MSK3 = 0x800000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK3_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK3_NotMask = 0x1
	// Position of PM field.
	RTC_ALRMR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_ALRMR_PM_Msk = 0x400000
	// Bit PM.
	RTC_ALRMR_PM = 0x400000
	// AM or 24-hour format
	RTC_ALRMR_PM_AM = 0x0
	// PM
	RTC_ALRMR_PM_PM = 0x1
	// Position of HT field.
	RTC_ALRMR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_ALRMR_HT_Msk = 0x300000
	// Position of HU field.
	RTC_ALRMR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_ALRMR_HU_Msk = 0xf0000
	// Position of MSK2 field.
	RTC_ALRMR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_ALRMR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_ALRMR_MSK2 = 0x8000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK2_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK2_NotMask = 0x1
	// Position of MNT field.
	RTC_ALRMR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_ALRMR_MNT_Msk = 0x7000
	// Position of MNU field.
	RTC_ALRMR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_ALRMR_MNU_Msk = 0xf00
	// Position of ST field.
	RTC_ALRMR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_ALRMR_ST_Msk = 0x70
	// Position of SU field.
	RTC_ALRMR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_ALRMR_SU_Msk = 0xf

	// ALRMASSR: Alarm %s sub-second register
	// Position of SSCLR field.
	RTC_ALRMSSR_SSCLR_Pos = 0x1f
	// Bit mask of SSCLR field.
	RTC_ALRMSSR_SSCLR_Msk = 0x80000000
	// Bit SSCLR.
	RTC_ALRMSSR_SSCLR = 0x80000000
	// Position of MASKSS field.
	RTC_ALRMSSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_ALRMSSR_MASKSS_Msk = 0x3f000000
	// Position of SS field.
	RTC_ALRMSSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_ALRMSSR_SS_Msk = 0x7fff

	// SR: RTC status register
	// Position of ALRAF field.
	RTC_SR_ALRAF_Pos = 0x1
	// Bit mask of ALRAF field.
	RTC_SR_ALRAF_Msk = 0x2
	// Bit ALRAF.
	RTC_SR_ALRAF = 0x2
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)
	RTC_SR_ALRAF_Match = 0x1
	// Position of ALRBF field.
	RTC_SR_ALRBF_Pos = 0x2
	// Bit mask of ALRBF field.
	RTC_SR_ALRBF_Msk = 0x4
	// Bit ALRBF.
	RTC_SR_ALRBF = 0x4
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)
	RTC_SR_ALRBF_Match = 0x1
	// Position of WUTF field.
	RTC_SR_WUTF_Pos = 0x2
	// Bit mask of WUTF field.
	RTC_SR_WUTF_Msk = 0x4
	// Bit WUTF.
	RTC_SR_WUTF = 0x4
	// This flag is set by hardware when the wakeup auto-reload counter reaches 0
	RTC_SR_WUTF_Zero = 0x1
	// Position of TSF field.
	RTC_SR_TSF_Pos = 0x3
	// Bit mask of TSF field.
	RTC_SR_TSF_Msk = 0x8
	// Bit TSF.
	RTC_SR_TSF = 0x8
	// This flag is set by hardware when a time-stamp event occurs
	RTC_SR_TSF_TimestampEvent = 0x1
	// Position of TSOVF field.
	RTC_SR_TSOVF_Pos = 0x4
	// Bit mask of TSOVF field.
	RTC_SR_TSOVF_Msk = 0x10
	// Bit TSOVF.
	RTC_SR_TSOVF = 0x10
	// This flag is set by hardware when a time-stamp event occurs while TSF is already set
	RTC_SR_TSOVF_Overflow = 0x1
	// Position of ITSF field.
	RTC_SR_ITSF_Pos = 0x5
	// Bit mask of ITSF field.
	RTC_SR_ITSF_Msk = 0x20
	// Bit ITSF.
	RTC_SR_ITSF = 0x20
	// This flag is set by hardware when a timestamp on the internal event occurs
	RTC_SR_ITSF_TimestampEvent = 0x1
	// Position of SSRUF field.
	RTC_SR_SSRUF_Pos = 0x6
	// Bit mask of SSRUF field.
	RTC_SR_SSRUF_Msk = 0x40
	// Bit SSRUF.
	RTC_SR_SSRUF = 0x40

	// MISR: RTC non-secure masked interrupt status register
	// Position of ALRAMF field.
	RTC_MISR_ALRAMF_Pos = 0x1
	// Bit mask of ALRAMF field.
	RTC_MISR_ALRAMF_Msk = 0x2
	// Bit ALRAMF.
	RTC_MISR_ALRAMF = 0x2
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
	RTC_MISR_ALRAMF_Match = 0x1
	// Position of ALRBMF field.
	RTC_MISR_ALRBMF_Pos = 0x2
	// Bit mask of ALRBMF field.
	RTC_MISR_ALRBMF_Msk = 0x4
	// Bit ALRBMF.
	RTC_MISR_ALRBMF = 0x4
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
	RTC_MISR_ALRBMF_Match = 0x1
	// Position of WUTMF field.
	RTC_MISR_WUTMF_Pos = 0x2
	// Bit mask of WUTMF field.
	RTC_MISR_WUTMF_Msk = 0x4
	// Bit WUTMF.
	RTC_MISR_WUTMF = 0x4
	// This flag is set by hardware when the wakeup auto-reload counter reaches 0
	RTC_MISR_WUTMF_Zero = 0x1
	// Position of TSMF field.
	RTC_MISR_TSMF_Pos = 0x3
	// Bit mask of TSMF field.
	RTC_MISR_TSMF_Msk = 0x8
	// Bit TSMF.
	RTC_MISR_TSMF = 0x8
	// This flag is set by hardware when a time-stamp event occurs
	RTC_MISR_TSMF_TimestampEvent = 0x1
	// Position of TSOVMF field.
	RTC_MISR_TSOVMF_Pos = 0x4
	// Bit mask of TSOVMF field.
	RTC_MISR_TSOVMF_Msk = 0x10
	// Bit TSOVMF.
	RTC_MISR_TSOVMF = 0x10
	// This flag is set by hardware when a time-stamp event occurs while TSF is already set
	RTC_MISR_TSOVMF_Overflow = 0x1
	// Position of ITSMF field.
	RTC_MISR_ITSMF_Pos = 0x5
	// Bit mask of ITSMF field.
	RTC_MISR_ITSMF_Msk = 0x20
	// Bit ITSMF.
	RTC_MISR_ITSMF = 0x20
	// This flag is set by hardware when a timestamp on the internal event occurs
	RTC_MISR_ITSMF_TimestampEvent = 0x1
	// Position of SSRUMF field.
	RTC_MISR_SSRUMF_Pos = 0x6
	// Bit mask of SSRUMF field.
	RTC_MISR_SSRUMF_Msk = 0x40
	// Bit SSRUMF.
	RTC_MISR_SSRUMF = 0x40

	// SMISR: RTC secure masked interrupt status register
	// Position of ALRAMF field.
	RTC_SMISR_ALRAMF_Pos = 0x0
	// Bit mask of ALRAMF field.
	RTC_SMISR_ALRAMF_Msk = 0x1
	// Bit ALRAMF.
	RTC_SMISR_ALRAMF = 0x1
	// Position of ALRBMF field.
	RTC_SMISR_ALRBMF_Pos = 0x1
	// Bit mask of ALRBMF field.
	RTC_SMISR_ALRBMF_Msk = 0x2
	// Bit ALRBMF.
	RTC_SMISR_ALRBMF = 0x2
	// Position of WUTMF field.
	RTC_SMISR_WUTMF_Pos = 0x2
	// Bit mask of WUTMF field.
	RTC_SMISR_WUTMF_Msk = 0x4
	// Bit WUTMF.
	RTC_SMISR_WUTMF = 0x4
	// Position of TSMF field.
	RTC_SMISR_TSMF_Pos = 0x3
	// Bit mask of TSMF field.
	RTC_SMISR_TSMF_Msk = 0x8
	// Bit TSMF.
	RTC_SMISR_TSMF = 0x8
	// Position of TSOVMF field.
	RTC_SMISR_TSOVMF_Pos = 0x4
	// Bit mask of TSOVMF field.
	RTC_SMISR_TSOVMF_Msk = 0x10
	// Bit TSOVMF.
	RTC_SMISR_TSOVMF = 0x10
	// Position of ITSMF field.
	RTC_SMISR_ITSMF_Pos = 0x5
	// Bit mask of ITSMF field.
	RTC_SMISR_ITSMF_Msk = 0x20
	// Bit ITSMF.
	RTC_SMISR_ITSMF = 0x20
	// Position of SSRUMF field.
	RTC_SMISR_SSRUMF_Pos = 0x6
	// Bit mask of SSRUMF field.
	RTC_SMISR_SSRUMF_Msk = 0x40
	// Bit SSRUMF.
	RTC_SMISR_SSRUMF = 0x40

	// SCR: RTC status clear register
	// Position of CALRAF field.
	RTC_SCR_CALRAF_Pos = 0x0
	// Bit mask of CALRAF field.
	RTC_SCR_CALRAF_Msk = 0x1
	// Bit CALRAF.
	RTC_SCR_CALRAF = 0x1
	// Clear interrupt flag
	RTC_SCR_CALRAF_Clear = 0x1
	// Position of CALRBF field.
	RTC_SCR_CALRBF_Pos = 0x1
	// Bit mask of CALRBF field.
	RTC_SCR_CALRBF_Msk = 0x2
	// Bit CALRBF.
	RTC_SCR_CALRBF = 0x2
	// Clear interrupt flag
	RTC_SCR_CALRBF_Clear = 0x1
	// Position of CWUTF field.
	RTC_SCR_CWUTF_Pos = 0x2
	// Bit mask of CWUTF field.
	RTC_SCR_CWUTF_Msk = 0x4
	// Bit CWUTF.
	RTC_SCR_CWUTF = 0x4
	// Clear interrupt flag
	RTC_SCR_CWUTF_Clear = 0x1
	// Position of CTSF field.
	RTC_SCR_CTSF_Pos = 0x3
	// Bit mask of CTSF field.
	RTC_SCR_CTSF_Msk = 0x8
	// Bit CTSF.
	RTC_SCR_CTSF = 0x8
	// Clear interrupt flag
	RTC_SCR_CTSF_Clear = 0x1
	// Position of CTSOVF field.
	RTC_SCR_CTSOVF_Pos = 0x4
	// Bit mask of CTSOVF field.
	RTC_SCR_CTSOVF_Msk = 0x10
	// Bit CTSOVF.
	RTC_SCR_CTSOVF = 0x10
	// Clear interrupt flag
	RTC_SCR_CTSOVF_Clear = 0x1
	// Position of CITSF field.
	RTC_SCR_CITSF_Pos = 0x5
	// Bit mask of CITSF field.
	RTC_SCR_CITSF_Msk = 0x20
	// Bit CITSF.
	RTC_SCR_CITSF = 0x20
	// Clear interrupt flag
	RTC_SCR_CITSF_Clear = 0x1
	// Position of CSSRUF field.
	RTC_SCR_CSSRUF_Pos = 0x6
	// Bit mask of CSSRUF field.
	RTC_SCR_CSSRUF_Msk = 0x40
	// Bit CSSRUF.
	RTC_SCR_CSSRUF = 0x40
	// Clear interrupt flag
	RTC_SCR_CSSRUF_Clear = 0x1

	// ALRABINR: Alarm %s binary mode register
	// Position of SS field.
	RTC_ALRBINR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_ALRBINR_SS_Msk = 0xffffffff
)

// Constants for SAES: Secure AES coprocessor
const (
	// CR: control register
	// Position of IPRST field.
	SAES_CR_IPRST_Pos = 0x1f
	// Bit mask of IPRST field.
	SAES_CR_IPRST_Msk = 0x80000000
	// Bit IPRST.
	SAES_CR_IPRST = 0x80000000
	// Position of KEYSEL field.
	SAES_CR_KEYSEL_Pos = 0x1c
	// Bit mask of KEYSEL field.
	SAES_CR_KEYSEL_Msk = 0x70000000
	// Position of KSHAREID field.
	SAES_CR_KSHAREID_Pos = 0x1a
	// Bit mask of KSHAREID field.
	SAES_CR_KSHAREID_Msk = 0xc000000
	// Position of KMOD field.
	SAES_CR_KMOD_Pos = 0x18
	// Bit mask of KMOD field.
	SAES_CR_KMOD_Msk = 0x3000000
	// Position of KEYPROT field.
	SAES_CR_KEYPROT_Pos = 0x13
	// Bit mask of KEYPROT field.
	SAES_CR_KEYPROT_Msk = 0x80000
	// Bit KEYPROT.
	SAES_CR_KEYPROT = 0x80000
	// Position of KEYSIZE field.
	SAES_CR_KEYSIZE_Pos = 0x12
	// Bit mask of KEYSIZE field.
	SAES_CR_KEYSIZE_Msk = 0x40000
	// Bit KEYSIZE.
	SAES_CR_KEYSIZE = 0x40000
	// Position of DMAOUTEN field.
	SAES_CR_DMAOUTEN_Pos = 0xc
	// Bit mask of DMAOUTEN field.
	SAES_CR_DMAOUTEN_Msk = 0x1000
	// Bit DMAOUTEN.
	SAES_CR_DMAOUTEN = 0x1000
	// Position of DMAINEN field.
	SAES_CR_DMAINEN_Pos = 0xb
	// Bit mask of DMAINEN field.
	SAES_CR_DMAINEN_Msk = 0x800
	// Bit DMAINEN.
	SAES_CR_DMAINEN = 0x800
	// Position of CHMOD field.
	SAES_CR_CHMOD_Pos = 0x5
	// Bit mask of CHMOD field.
	SAES_CR_CHMOD_Msk = 0x60
	// Position of MODE field.
	SAES_CR_MODE_Pos = 0x3
	// Bit mask of MODE field.
	SAES_CR_MODE_Msk = 0x18
	// Position of DATATYPE field.
	SAES_CR_DATATYPE_Pos = 0x1
	// Bit mask of DATATYPE field.
	SAES_CR_DATATYPE_Msk = 0x6
	// Position of EN field.
	SAES_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	SAES_CR_EN_Msk = 0x1
	// Bit EN.
	SAES_CR_EN = 0x1

	// SR: status register
	// Position of KEYVALID field.
	SAES_SR_KEYVALID_Pos = 0x7
	// Bit mask of KEYVALID field.
	SAES_SR_KEYVALID_Msk = 0x80
	// Bit KEYVALID.
	SAES_SR_KEYVALID = 0x80
	// Position of BUSY field.
	SAES_SR_BUSY_Pos = 0x3
	// Bit mask of BUSY field.
	SAES_SR_BUSY_Msk = 0x8
	// Bit BUSY.
	SAES_SR_BUSY = 0x8
	// Position of WRERR field.
	SAES_SR_WRERR_Pos = 0x2
	// Bit mask of WRERR field.
	SAES_SR_WRERR_Msk = 0x4
	// Bit WRERR.
	SAES_SR_WRERR = 0x4
	// Position of RDERR field.
	SAES_SR_RDERR_Pos = 0x1
	// Bit mask of RDERR field.
	SAES_SR_RDERR_Msk = 0x2
	// Bit RDERR.
	SAES_SR_RDERR = 0x2
	// Position of CCF field.
	SAES_SR_CCF_Pos = 0x0
	// Bit mask of CCF field.
	SAES_SR_CCF_Msk = 0x1
	// Bit CCF.
	SAES_SR_CCF = 0x1

	// DINR: data input register
	// Position of DIN field.
	SAES_DINR_DIN_Pos = 0x0
	// Bit mask of DIN field.
	SAES_DINR_DIN_Msk = 0xffffffff

	// DOUTR: data output register
	// Position of DOUT field.
	SAES_DOUTR_DOUT_Pos = 0x0
	// Bit mask of DOUT field.
	SAES_DOUTR_DOUT_Msk = 0xffffffff

	// KEYR0: key register 0
	// Position of KEY field.
	SAES_KEYR0_KEY_Pos = 0x0
	// Bit mask of KEY field.
	SAES_KEYR0_KEY_Msk = 0xffffffff

	// KEYR1: key register 1
	// Position of KEY field.
	SAES_KEYR1_KEY_Pos = 0x0
	// Bit mask of KEY field.
	SAES_KEYR1_KEY_Msk = 0xffffffff

	// KEYR2: key register 2
	// Position of KEYR field.
	SAES_KEYR2_KEYR_Pos = 0x0
	// Bit mask of KEYR field.
	SAES_KEYR2_KEYR_Msk = 0xffffffff

	// KEYR3: key register 3
	// Position of SAES_KEYR3 field.
	SAES_KEYR3_SAES_KEYR3_Pos = 0x0
	// Bit mask of SAES_KEYR3 field.
	SAES_KEYR3_SAES_KEYR3_Msk = 0xffffffff

	// IVR0: initialization vector register 0
	// Position of IVI field.
	SAES_IVR0_IVI_Pos = 0x0
	// Bit mask of IVI field.
	SAES_IVR0_IVI_Msk = 0xffffffff

	// IVR1: initialization vector register 1
	// Position of IVI field.
	SAES_IVR1_IVI_Pos = 0x0
	// Bit mask of IVI field.
	SAES_IVR1_IVI_Msk = 0xffffffff

	// IVR2: initialization vector register 2
	// Position of IVI field.
	SAES_IVR2_IVI_Pos = 0x0
	// Bit mask of IVI field.
	SAES_IVR2_IVI_Msk = 0xffffffff

	// IVR3: initialization vector register 3
	// Position of IVI field.
	SAES_IVR3_IVI_Pos = 0x0
	// Bit mask of IVI field.
	SAES_IVR3_IVI_Msk = 0xffffffff

	// KEYR4: key register 4
	// Position of KEY field.
	SAES_KEYR4_KEY_Pos = 0x0
	// Bit mask of KEY field.
	SAES_KEYR4_KEY_Msk = 0xffffffff

	// KEYR5: key register 5
	// Position of KEY field.
	SAES_KEYR5_KEY_Pos = 0x0
	// Bit mask of KEY field.
	SAES_KEYR5_KEY_Msk = 0xffffffff

	// KEYR6: key register 6
	// Position of KEY field.
	SAES_KEYR6_KEY_Pos = 0x0
	// Bit mask of KEY field.
	SAES_KEYR6_KEY_Msk = 0xffffffff

	// KEYR7: key register 7
	// Position of KEY field.
	SAES_KEYR7_KEY_Pos = 0x0
	// Bit mask of KEY field.
	SAES_KEYR7_KEY_Msk = 0xffffffff

	// DPACFGR: configuration register
	// Position of CONFIGLOCK field.
	SAES_DPACFGR_CONFIGLOCK_Pos = 0x1f
	// Bit mask of CONFIGLOCK field.
	SAES_DPACFGR_CONFIGLOCK_Msk = 0x80000000
	// Bit CONFIGLOCK.
	SAES_DPACFGR_CONFIGLOCK = 0x80000000
	// Position of TRIMCFG field.
	SAES_DPACFGR_TRIMCFG_Pos = 0x3
	// Bit mask of TRIMCFG field.
	SAES_DPACFGR_TRIMCFG_Msk = 0x18
	// Position of RESEED field.
	SAES_DPACFGR_RESEED_Pos = 0x2
	// Bit mask of RESEED field.
	SAES_DPACFGR_RESEED_Msk = 0x4
	// Bit RESEED.
	SAES_DPACFGR_RESEED = 0x4
	// Position of REDCFG field.
	SAES_DPACFGR_REDCFG_Pos = 0x1
	// Bit mask of REDCFG field.
	SAES_DPACFGR_REDCFG_Msk = 0x2
	// Bit REDCFG.
	SAES_DPACFGR_REDCFG = 0x2

	// IER: interrupt enable register
	// Position of RNGEIE field.
	SAES_IER_RNGEIE_Pos = 0x3
	// Bit mask of RNGEIE field.
	SAES_IER_RNGEIE_Msk = 0x8
	// Bit RNGEIE.
	SAES_IER_RNGEIE = 0x8
	// Position of KEIE field.
	SAES_IER_KEIE_Pos = 0x2
	// Bit mask of KEIE field.
	SAES_IER_KEIE_Msk = 0x4
	// Bit KEIE.
	SAES_IER_KEIE = 0x4
	// Position of RWEIE field.
	SAES_IER_RWEIE_Pos = 0x1
	// Bit mask of RWEIE field.
	SAES_IER_RWEIE_Msk = 0x2
	// Bit RWEIE.
	SAES_IER_RWEIE = 0x2
	// Position of CCFIE field.
	SAES_IER_CCFIE_Pos = 0x0
	// Bit mask of CCFIE field.
	SAES_IER_CCFIE_Msk = 0x1
	// Bit CCFIE.
	SAES_IER_CCFIE = 0x1

	// ISR: interrupt status register
	// Position of RNGEIF field.
	SAES_ISR_RNGEIF_Pos = 0x3
	// Bit mask of RNGEIF field.
	SAES_ISR_RNGEIF_Msk = 0x8
	// Bit RNGEIF.
	SAES_ISR_RNGEIF = 0x8
	// Position of KEIF field.
	SAES_ISR_KEIF_Pos = 0x2
	// Bit mask of KEIF field.
	SAES_ISR_KEIF_Msk = 0x4
	// Bit KEIF.
	SAES_ISR_KEIF = 0x4
	// Position of RWEIF field.
	SAES_ISR_RWEIF_Pos = 0x1
	// Bit mask of RWEIF field.
	SAES_ISR_RWEIF_Msk = 0x2
	// Bit RWEIF.
	SAES_ISR_RWEIF = 0x2
	// Position of CCF field.
	SAES_ISR_CCF_Pos = 0x0
	// Bit mask of CCF field.
	SAES_ISR_CCF_Msk = 0x1
	// Bit CCF.
	SAES_ISR_CCF = 0x1

	// ICR: interrupt clear register
	// Position of RNGEIF field.
	SAES_ICR_RNGEIF_Pos = 0x3
	// Bit mask of RNGEIF field.
	SAES_ICR_RNGEIF_Msk = 0x8
	// Bit RNGEIF.
	SAES_ICR_RNGEIF = 0x8
	// Position of KEIF field.
	SAES_ICR_KEIF_Pos = 0x2
	// Bit mask of KEIF field.
	SAES_ICR_KEIF_Msk = 0x4
	// Bit KEIF.
	SAES_ICR_KEIF = 0x4
	// Position of RWEIF field.
	SAES_ICR_RWEIF_Pos = 0x1
	// Bit mask of RWEIF field.
	SAES_ICR_RWEIF_Msk = 0x2
	// Bit RWEIF.
	SAES_ICR_RWEIF = 0x2
	// Position of CCF field.
	SAES_ICR_CCF_Pos = 0x0
	// Bit mask of CCF field.
	SAES_ICR_CCF_Msk = 0x1
	// Bit CCF.
	SAES_ICR_CCF = 0x1
)

// Constants for SAI1: Serial audio interface
const (
	// GCR: Global configuration register
	// Position of SYNCIN field.
	SAI_GCR_SYNCIN_Pos = 0x0
	// Bit mask of SYNCIN field.
	SAI_GCR_SYNCIN_Msk = 0x3
	// Position of SYNCOUT field.
	SAI_GCR_SYNCOUT_Pos = 0x4
	// Bit mask of SYNCOUT field.
	SAI_GCR_SYNCOUT_Msk = 0x30

	// ACR1: A Configuration register 1
	// Position of MCKEN field.
	SAI_ACR1_MCKEN_Pos = 0x1b
	// Bit mask of MCKEN field.
	SAI_ACR1_MCKEN_Msk = 0x8000000
	// Bit MCKEN.
	SAI_ACR1_MCKEN = 0x8000000
	// Position of OSR field.
	SAI_ACR1_OSR_Pos = 0x1a
	// Bit mask of OSR field.
	SAI_ACR1_OSR_Msk = 0x4000000
	// Bit OSR.
	SAI_ACR1_OSR = 0x4000000
	// Position of MCKDIV field.
	SAI_ACR1_MCKDIV_Pos = 0x14
	// Bit mask of MCKDIV field.
	SAI_ACR1_MCKDIV_Msk = 0x3f00000
	// Position of NODIV field.
	SAI_ACR1_NODIV_Pos = 0x13
	// Bit mask of NODIV field.
	SAI_ACR1_NODIV_Msk = 0x80000
	// Bit NODIV.
	SAI_ACR1_NODIV = 0x80000
	// Position of DMAEN field.
	SAI_ACR1_DMAEN_Pos = 0x11
	// Bit mask of DMAEN field.
	SAI_ACR1_DMAEN_Msk = 0x20000
	// Bit DMAEN.
	SAI_ACR1_DMAEN = 0x20000
	// Position of SAIAEN field.
	SAI_ACR1_SAIAEN_Pos = 0x10
	// Bit mask of SAIAEN field.
	SAI_ACR1_SAIAEN_Msk = 0x10000
	// Bit SAIAEN.
	SAI_ACR1_SAIAEN = 0x10000
	// Position of OUTDRIV field.
	SAI_ACR1_OUTDRIV_Pos = 0xd
	// Bit mask of OUTDRIV field.
	SAI_ACR1_OUTDRIV_Msk = 0x2000
	// Bit OUTDRIV.
	SAI_ACR1_OUTDRIV = 0x2000
	// Position of MONO field.
	SAI_ACR1_MONO_Pos = 0xc
	// Bit mask of MONO field.
	SAI_ACR1_MONO_Msk = 0x1000
	// Bit MONO.
	SAI_ACR1_MONO = 0x1000
	// Position of SYNCEN field.
	SAI_ACR1_SYNCEN_Pos = 0xa
	// Bit mask of SYNCEN field.
	SAI_ACR1_SYNCEN_Msk = 0xc00
	// Position of CKSTR field.
	SAI_ACR1_CKSTR_Pos = 0x9
	// Bit mask of CKSTR field.
	SAI_ACR1_CKSTR_Msk = 0x200
	// Bit CKSTR.
	SAI_ACR1_CKSTR = 0x200
	// Position of LSBFIRST field.
	SAI_ACR1_LSBFIRST_Pos = 0x8
	// Bit mask of LSBFIRST field.
	SAI_ACR1_LSBFIRST_Msk = 0x100
	// Bit LSBFIRST.
	SAI_ACR1_LSBFIRST = 0x100
	// Position of DS field.
	SAI_ACR1_DS_Pos = 0x5
	// Bit mask of DS field.
	SAI_ACR1_DS_Msk = 0xe0
	// Position of PRTCFG field.
	SAI_ACR1_PRTCFG_Pos = 0x2
	// Bit mask of PRTCFG field.
	SAI_ACR1_PRTCFG_Msk = 0xc
	// Position of MODE field.
	SAI_ACR1_MODE_Pos = 0x0
	// Bit mask of MODE field.
	SAI_ACR1_MODE_Msk = 0x3

	// ACR2: A Configuration register 2
	// Position of COMP field.
	SAI_ACR2_COMP_Pos = 0xe
	// Bit mask of COMP field.
	SAI_ACR2_COMP_Msk = 0xc000
	// Position of CPL field.
	SAI_ACR2_CPL_Pos = 0xd
	// Bit mask of CPL field.
	SAI_ACR2_CPL_Msk = 0x2000
	// Bit CPL.
	SAI_ACR2_CPL = 0x2000
	// Position of MUTECN field.
	SAI_ACR2_MUTECN_Pos = 0x7
	// Bit mask of MUTECN field.
	SAI_ACR2_MUTECN_Msk = 0x1f80
	// Position of MUTEVAL field.
	SAI_ACR2_MUTEVAL_Pos = 0x6
	// Bit mask of MUTEVAL field.
	SAI_ACR2_MUTEVAL_Msk = 0x40
	// Bit MUTEVAL.
	SAI_ACR2_MUTEVAL = 0x40
	// Position of MUTE field.
	SAI_ACR2_MUTE_Pos = 0x5
	// Bit mask of MUTE field.
	SAI_ACR2_MUTE_Msk = 0x20
	// Bit MUTE.
	SAI_ACR2_MUTE = 0x20
	// Position of TRIS field.
	SAI_ACR2_TRIS_Pos = 0x4
	// Bit mask of TRIS field.
	SAI_ACR2_TRIS_Msk = 0x10
	// Bit TRIS.
	SAI_ACR2_TRIS = 0x10
	// Position of FFLUSH field.
	SAI_ACR2_FFLUSH_Pos = 0x3
	// Bit mask of FFLUSH field.
	SAI_ACR2_FFLUSH_Msk = 0x8
	// Bit FFLUSH.
	SAI_ACR2_FFLUSH = 0x8
	// Position of FTH field.
	SAI_ACR2_FTH_Pos = 0x0
	// Bit mask of FTH field.
	SAI_ACR2_FTH_Msk = 0x7

	// AFRCR: A frame configuration register
	// Position of FSOFF field.
	SAI_AFRCR_FSOFF_Pos = 0x12
	// Bit mask of FSOFF field.
	SAI_AFRCR_FSOFF_Msk = 0x40000
	// Bit FSOFF.
	SAI_AFRCR_FSOFF = 0x40000
	// Position of FSPOL field.
	SAI_AFRCR_FSPOL_Pos = 0x11
	// Bit mask of FSPOL field.
	SAI_AFRCR_FSPOL_Msk = 0x20000
	// Bit FSPOL.
	SAI_AFRCR_FSPOL = 0x20000
	// Position of FSDEF field.
	SAI_AFRCR_FSDEF_Pos = 0x10
	// Bit mask of FSDEF field.
	SAI_AFRCR_FSDEF_Msk = 0x10000
	// Bit FSDEF.
	SAI_AFRCR_FSDEF = 0x10000
	// Position of FSALL field.
	SAI_AFRCR_FSALL_Pos = 0x8
	// Bit mask of FSALL field.
	SAI_AFRCR_FSALL_Msk = 0x7f00
	// Position of FRL field.
	SAI_AFRCR_FRL_Pos = 0x0
	// Bit mask of FRL field.
	SAI_AFRCR_FRL_Msk = 0xff

	// ASLOTR: A Slot register
	// Position of SLOTEN field.
	SAI_ASLOTR_SLOTEN_Pos = 0x10
	// Bit mask of SLOTEN field.
	SAI_ASLOTR_SLOTEN_Msk = 0xffff0000
	// Position of NBSLOT field.
	SAI_ASLOTR_NBSLOT_Pos = 0x8
	// Bit mask of NBSLOT field.
	SAI_ASLOTR_NBSLOT_Msk = 0xf00
	// Position of SLOTSZ field.
	SAI_ASLOTR_SLOTSZ_Pos = 0x6
	// Bit mask of SLOTSZ field.
	SAI_ASLOTR_SLOTSZ_Msk = 0xc0
	// Position of FBOFF field.
	SAI_ASLOTR_FBOFF_Pos = 0x0
	// Bit mask of FBOFF field.
	SAI_ASLOTR_FBOFF_Msk = 0x1f

	// AIM: A Interrupt mask register
	// Position of LFSDETIE field.
	SAI_AIM_LFSDETIE_Pos = 0x6
	// Bit mask of LFSDETIE field.
	SAI_AIM_LFSDETIE_Msk = 0x40
	// Bit LFSDETIE.
	SAI_AIM_LFSDETIE = 0x40
	// Position of AFSDETIE field.
	SAI_AIM_AFSDETIE_Pos = 0x5
	// Bit mask of AFSDETIE field.
	SAI_AIM_AFSDETIE_Msk = 0x20
	// Bit AFSDETIE.
	SAI_AIM_AFSDETIE = 0x20
	// Position of CNRDYIE field.
	SAI_AIM_CNRDYIE_Pos = 0x4
	// Bit mask of CNRDYIE field.
	SAI_AIM_CNRDYIE_Msk = 0x10
	// Bit CNRDYIE.
	SAI_AIM_CNRDYIE = 0x10
	// Position of FREQIE field.
	SAI_AIM_FREQIE_Pos = 0x3
	// Bit mask of FREQIE field.
	SAI_AIM_FREQIE_Msk = 0x8
	// Bit FREQIE.
	SAI_AIM_FREQIE = 0x8
	// Position of WCKCFGIE field.
	SAI_AIM_WCKCFGIE_Pos = 0x2
	// Bit mask of WCKCFGIE field.
	SAI_AIM_WCKCFGIE_Msk = 0x4
	// Bit WCKCFGIE.
	SAI_AIM_WCKCFGIE = 0x4
	// Position of MUTEDETIE field.
	SAI_AIM_MUTEDETIE_Pos = 0x1
	// Bit mask of MUTEDETIE field.
	SAI_AIM_MUTEDETIE_Msk = 0x2
	// Bit MUTEDETIE.
	SAI_AIM_MUTEDETIE = 0x2
	// Position of OVRUDRIE field.
	SAI_AIM_OVRUDRIE_Pos = 0x0
	// Bit mask of OVRUDRIE field.
	SAI_AIM_OVRUDRIE_Msk = 0x1
	// Bit OVRUDRIE.
	SAI_AIM_OVRUDRIE = 0x1

	// ASR: A Status register
	// Position of FLVL field.
	SAI_ASR_FLVL_Pos = 0x10
	// Bit mask of FLVL field.
	SAI_ASR_FLVL_Msk = 0x70000
	// Position of LFSDET field.
	SAI_ASR_LFSDET_Pos = 0x6
	// Bit mask of LFSDET field.
	SAI_ASR_LFSDET_Msk = 0x40
	// Bit LFSDET.
	SAI_ASR_LFSDET = 0x40
	// Position of AFSDET field.
	SAI_ASR_AFSDET_Pos = 0x5
	// Bit mask of AFSDET field.
	SAI_ASR_AFSDET_Msk = 0x20
	// Bit AFSDET.
	SAI_ASR_AFSDET = 0x20
	// Position of CNRDY field.
	SAI_ASR_CNRDY_Pos = 0x4
	// Bit mask of CNRDY field.
	SAI_ASR_CNRDY_Msk = 0x10
	// Bit CNRDY.
	SAI_ASR_CNRDY = 0x10
	// Position of FREQ field.
	SAI_ASR_FREQ_Pos = 0x3
	// Bit mask of FREQ field.
	SAI_ASR_FREQ_Msk = 0x8
	// Bit FREQ.
	SAI_ASR_FREQ = 0x8
	// Position of WCKCFG field.
	SAI_ASR_WCKCFG_Pos = 0x2
	// Bit mask of WCKCFG field.
	SAI_ASR_WCKCFG_Msk = 0x4
	// Bit WCKCFG.
	SAI_ASR_WCKCFG = 0x4
	// Position of MUTEDET field.
	SAI_ASR_MUTEDET_Pos = 0x1
	// Bit mask of MUTEDET field.
	SAI_ASR_MUTEDET_Msk = 0x2
	// Bit MUTEDET.
	SAI_ASR_MUTEDET = 0x2
	// Position of OVRUDR field.
	SAI_ASR_OVRUDR_Pos = 0x0
	// Bit mask of OVRUDR field.
	SAI_ASR_OVRUDR_Msk = 0x1
	// Bit OVRUDR.
	SAI_ASR_OVRUDR = 0x1

	// ACLRFR: A Clear flag register
	// Position of CLFSDET field.
	SAI_ACLRFR_CLFSDET_Pos = 0x6
	// Bit mask of CLFSDET field.
	SAI_ACLRFR_CLFSDET_Msk = 0x40
	// Bit CLFSDET.
	SAI_ACLRFR_CLFSDET = 0x40
	// Position of CAFSDET field.
	SAI_ACLRFR_CAFSDET_Pos = 0x5
	// Bit mask of CAFSDET field.
	SAI_ACLRFR_CAFSDET_Msk = 0x20
	// Bit CAFSDET.
	SAI_ACLRFR_CAFSDET = 0x20
	// Position of CCNRDY field.
	SAI_ACLRFR_CCNRDY_Pos = 0x4
	// Bit mask of CCNRDY field.
	SAI_ACLRFR_CCNRDY_Msk = 0x10
	// Bit CCNRDY.
	SAI_ACLRFR_CCNRDY = 0x10
	// Position of CWCKCFG field.
	SAI_ACLRFR_CWCKCFG_Pos = 0x2
	// Bit mask of CWCKCFG field.
	SAI_ACLRFR_CWCKCFG_Msk = 0x4
	// Bit CWCKCFG.
	SAI_ACLRFR_CWCKCFG = 0x4
	// Position of CMUTEDET field.
	SAI_ACLRFR_CMUTEDET_Pos = 0x1
	// Bit mask of CMUTEDET field.
	SAI_ACLRFR_CMUTEDET_Msk = 0x2
	// Bit CMUTEDET.
	SAI_ACLRFR_CMUTEDET = 0x2
	// Position of COVRUDR field.
	SAI_ACLRFR_COVRUDR_Pos = 0x0
	// Bit mask of COVRUDR field.
	SAI_ACLRFR_COVRUDR_Msk = 0x1
	// Bit COVRUDR.
	SAI_ACLRFR_COVRUDR = 0x1

	// ADR: A Data register
	// Position of DATA field.
	SAI_ADR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SAI_ADR_DATA_Msk = 0xffffffff

	// BCR1: B Configuration register 1
	// Position of MCKEN field.
	SAI_BCR1_MCKEN_Pos = 0x1b
	// Bit mask of MCKEN field.
	SAI_BCR1_MCKEN_Msk = 0x8000000
	// Bit MCKEN.
	SAI_BCR1_MCKEN = 0x8000000
	// Position of OSR field.
	SAI_BCR1_OSR_Pos = 0x1a
	// Bit mask of OSR field.
	SAI_BCR1_OSR_Msk = 0x4000000
	// Bit OSR.
	SAI_BCR1_OSR = 0x4000000
	// Position of MCKDIV field.
	SAI_BCR1_MCKDIV_Pos = 0x14
	// Bit mask of MCKDIV field.
	SAI_BCR1_MCKDIV_Msk = 0x3f00000
	// Position of NODIV field.
	SAI_BCR1_NODIV_Pos = 0x13
	// Bit mask of NODIV field.
	SAI_BCR1_NODIV_Msk = 0x80000
	// Bit NODIV.
	SAI_BCR1_NODIV = 0x80000
	// Position of DMAEN field.
	SAI_BCR1_DMAEN_Pos = 0x11
	// Bit mask of DMAEN field.
	SAI_BCR1_DMAEN_Msk = 0x20000
	// Bit DMAEN.
	SAI_BCR1_DMAEN = 0x20000
	// Position of SAIAEN field.
	SAI_BCR1_SAIAEN_Pos = 0x10
	// Bit mask of SAIAEN field.
	SAI_BCR1_SAIAEN_Msk = 0x10000
	// Bit SAIAEN.
	SAI_BCR1_SAIAEN = 0x10000
	// Position of OUTDRIV field.
	SAI_BCR1_OUTDRIV_Pos = 0xd
	// Bit mask of OUTDRIV field.
	SAI_BCR1_OUTDRIV_Msk = 0x2000
	// Bit OUTDRIV.
	SAI_BCR1_OUTDRIV = 0x2000
	// Position of MONO field.
	SAI_BCR1_MONO_Pos = 0xc
	// Bit mask of MONO field.
	SAI_BCR1_MONO_Msk = 0x1000
	// Bit MONO.
	SAI_BCR1_MONO = 0x1000
	// Position of SYNCEN field.
	SAI_BCR1_SYNCEN_Pos = 0xa
	// Bit mask of SYNCEN field.
	SAI_BCR1_SYNCEN_Msk = 0xc00
	// Position of CKSTR field.
	SAI_BCR1_CKSTR_Pos = 0x9
	// Bit mask of CKSTR field.
	SAI_BCR1_CKSTR_Msk = 0x200
	// Bit CKSTR.
	SAI_BCR1_CKSTR = 0x200
	// Position of LSBFIRST field.
	SAI_BCR1_LSBFIRST_Pos = 0x8
	// Bit mask of LSBFIRST field.
	SAI_BCR1_LSBFIRST_Msk = 0x100
	// Bit LSBFIRST.
	SAI_BCR1_LSBFIRST = 0x100
	// Position of DS field.
	SAI_BCR1_DS_Pos = 0x5
	// Bit mask of DS field.
	SAI_BCR1_DS_Msk = 0xe0
	// Position of PRTCFG field.
	SAI_BCR1_PRTCFG_Pos = 0x2
	// Bit mask of PRTCFG field.
	SAI_BCR1_PRTCFG_Msk = 0xc
	// Position of MODE field.
	SAI_BCR1_MODE_Pos = 0x0
	// Bit mask of MODE field.
	SAI_BCR1_MODE_Msk = 0x3

	// BCR2: B Configuration register 2
	// Position of COMP field.
	SAI_BCR2_COMP_Pos = 0xe
	// Bit mask of COMP field.
	SAI_BCR2_COMP_Msk = 0xc000
	// Position of CPL field.
	SAI_BCR2_CPL_Pos = 0xd
	// Bit mask of CPL field.
	SAI_BCR2_CPL_Msk = 0x2000
	// Bit CPL.
	SAI_BCR2_CPL = 0x2000
	// Position of MUTECN field.
	SAI_BCR2_MUTECN_Pos = 0x7
	// Bit mask of MUTECN field.
	SAI_BCR2_MUTECN_Msk = 0x1f80
	// Position of MUTEVAL field.
	SAI_BCR2_MUTEVAL_Pos = 0x6
	// Bit mask of MUTEVAL field.
	SAI_BCR2_MUTEVAL_Msk = 0x40
	// Bit MUTEVAL.
	SAI_BCR2_MUTEVAL = 0x40
	// Position of MUTE field.
	SAI_BCR2_MUTE_Pos = 0x5
	// Bit mask of MUTE field.
	SAI_BCR2_MUTE_Msk = 0x20
	// Bit MUTE.
	SAI_BCR2_MUTE = 0x20
	// Position of TRIS field.
	SAI_BCR2_TRIS_Pos = 0x4
	// Bit mask of TRIS field.
	SAI_BCR2_TRIS_Msk = 0x10
	// Bit TRIS.
	SAI_BCR2_TRIS = 0x10
	// Position of FFLUSH field.
	SAI_BCR2_FFLUSH_Pos = 0x3
	// Bit mask of FFLUSH field.
	SAI_BCR2_FFLUSH_Msk = 0x8
	// Bit FFLUSH.
	SAI_BCR2_FFLUSH = 0x8
	// Position of FTH field.
	SAI_BCR2_FTH_Pos = 0x0
	// Bit mask of FTH field.
	SAI_BCR2_FTH_Msk = 0x7

	// BFRCR: B frame configuration register
	// Position of FSOFF field.
	SAI_BFRCR_FSOFF_Pos = 0x12
	// Bit mask of FSOFF field.
	SAI_BFRCR_FSOFF_Msk = 0x40000
	// Bit FSOFF.
	SAI_BFRCR_FSOFF = 0x40000
	// Position of FSPOL field.
	SAI_BFRCR_FSPOL_Pos = 0x11
	// Bit mask of FSPOL field.
	SAI_BFRCR_FSPOL_Msk = 0x20000
	// Bit FSPOL.
	SAI_BFRCR_FSPOL = 0x20000
	// Position of FSDEF field.
	SAI_BFRCR_FSDEF_Pos = 0x10
	// Bit mask of FSDEF field.
	SAI_BFRCR_FSDEF_Msk = 0x10000
	// Bit FSDEF.
	SAI_BFRCR_FSDEF = 0x10000
	// Position of FSALL field.
	SAI_BFRCR_FSALL_Pos = 0x8
	// Bit mask of FSALL field.
	SAI_BFRCR_FSALL_Msk = 0x7f00
	// Position of FRL field.
	SAI_BFRCR_FRL_Pos = 0x0
	// Bit mask of FRL field.
	SAI_BFRCR_FRL_Msk = 0xff

	// BSLOTR: B Slot register
	// Position of SLOTEN field.
	SAI_BSLOTR_SLOTEN_Pos = 0x10
	// Bit mask of SLOTEN field.
	SAI_BSLOTR_SLOTEN_Msk = 0xffff0000
	// Position of NBSLOT field.
	SAI_BSLOTR_NBSLOT_Pos = 0x8
	// Bit mask of NBSLOT field.
	SAI_BSLOTR_NBSLOT_Msk = 0xf00
	// Position of SLOTSZ field.
	SAI_BSLOTR_SLOTSZ_Pos = 0x6
	// Bit mask of SLOTSZ field.
	SAI_BSLOTR_SLOTSZ_Msk = 0xc0
	// Position of FBOFF field.
	SAI_BSLOTR_FBOFF_Pos = 0x0
	// Bit mask of FBOFF field.
	SAI_BSLOTR_FBOFF_Msk = 0x1f

	// BIM: B Interrupt mask register
	// Position of LFSDETIE field.
	SAI_BIM_LFSDETIE_Pos = 0x6
	// Bit mask of LFSDETIE field.
	SAI_BIM_LFSDETIE_Msk = 0x40
	// Bit LFSDETIE.
	SAI_BIM_LFSDETIE = 0x40
	// Position of AFSDETIE field.
	SAI_BIM_AFSDETIE_Pos = 0x5
	// Bit mask of AFSDETIE field.
	SAI_BIM_AFSDETIE_Msk = 0x20
	// Bit AFSDETIE.
	SAI_BIM_AFSDETIE = 0x20
	// Position of CNRDYIE field.
	SAI_BIM_CNRDYIE_Pos = 0x4
	// Bit mask of CNRDYIE field.
	SAI_BIM_CNRDYIE_Msk = 0x10
	// Bit CNRDYIE.
	SAI_BIM_CNRDYIE = 0x10
	// Position of FREQIE field.
	SAI_BIM_FREQIE_Pos = 0x3
	// Bit mask of FREQIE field.
	SAI_BIM_FREQIE_Msk = 0x8
	// Bit FREQIE.
	SAI_BIM_FREQIE = 0x8
	// Position of WCKCFGIE field.
	SAI_BIM_WCKCFGIE_Pos = 0x2
	// Bit mask of WCKCFGIE field.
	SAI_BIM_WCKCFGIE_Msk = 0x4
	// Bit WCKCFGIE.
	SAI_BIM_WCKCFGIE = 0x4
	// Position of MUTEDETIE field.
	SAI_BIM_MUTEDETIE_Pos = 0x1
	// Bit mask of MUTEDETIE field.
	SAI_BIM_MUTEDETIE_Msk = 0x2
	// Bit MUTEDETIE.
	SAI_BIM_MUTEDETIE = 0x2
	// Position of OVRUDRIE field.
	SAI_BIM_OVRUDRIE_Pos = 0x0
	// Bit mask of OVRUDRIE field.
	SAI_BIM_OVRUDRIE_Msk = 0x1
	// Bit OVRUDRIE.
	SAI_BIM_OVRUDRIE = 0x1

	// BSR: B Status register
	// Position of FLVL field.
	SAI_BSR_FLVL_Pos = 0x10
	// Bit mask of FLVL field.
	SAI_BSR_FLVL_Msk = 0x70000
	// Position of LFSDET field.
	SAI_BSR_LFSDET_Pos = 0x6
	// Bit mask of LFSDET field.
	SAI_BSR_LFSDET_Msk = 0x40
	// Bit LFSDET.
	SAI_BSR_LFSDET = 0x40
	// Position of AFSDET field.
	SAI_BSR_AFSDET_Pos = 0x5
	// Bit mask of AFSDET field.
	SAI_BSR_AFSDET_Msk = 0x20
	// Bit AFSDET.
	SAI_BSR_AFSDET = 0x20
	// Position of CNRDY field.
	SAI_BSR_CNRDY_Pos = 0x4
	// Bit mask of CNRDY field.
	SAI_BSR_CNRDY_Msk = 0x10
	// Bit CNRDY.
	SAI_BSR_CNRDY = 0x10
	// Position of FREQ field.
	SAI_BSR_FREQ_Pos = 0x3
	// Bit mask of FREQ field.
	SAI_BSR_FREQ_Msk = 0x8
	// Bit FREQ.
	SAI_BSR_FREQ = 0x8
	// Position of WCKCFG field.
	SAI_BSR_WCKCFG_Pos = 0x2
	// Bit mask of WCKCFG field.
	SAI_BSR_WCKCFG_Msk = 0x4
	// Bit WCKCFG.
	SAI_BSR_WCKCFG = 0x4
	// Position of MUTEDET field.
	SAI_BSR_MUTEDET_Pos = 0x1
	// Bit mask of MUTEDET field.
	SAI_BSR_MUTEDET_Msk = 0x2
	// Bit MUTEDET.
	SAI_BSR_MUTEDET = 0x2
	// Position of OVRUDR field.
	SAI_BSR_OVRUDR_Pos = 0x0
	// Bit mask of OVRUDR field.
	SAI_BSR_OVRUDR_Msk = 0x1
	// Bit OVRUDR.
	SAI_BSR_OVRUDR = 0x1

	// BCLRFR: B Clear flag register
	// Position of CLFSDET field.
	SAI_BCLRFR_CLFSDET_Pos = 0x6
	// Bit mask of CLFSDET field.
	SAI_BCLRFR_CLFSDET_Msk = 0x40
	// Bit CLFSDET.
	SAI_BCLRFR_CLFSDET = 0x40
	// Position of CAFSDET field.
	SAI_BCLRFR_CAFSDET_Pos = 0x5
	// Bit mask of CAFSDET field.
	SAI_BCLRFR_CAFSDET_Msk = 0x20
	// Bit CAFSDET.
	SAI_BCLRFR_CAFSDET = 0x20
	// Position of CCNRDY field.
	SAI_BCLRFR_CCNRDY_Pos = 0x4
	// Bit mask of CCNRDY field.
	SAI_BCLRFR_CCNRDY_Msk = 0x10
	// Bit CCNRDY.
	SAI_BCLRFR_CCNRDY = 0x10
	// Position of CWCKCFG field.
	SAI_BCLRFR_CWCKCFG_Pos = 0x2
	// Bit mask of CWCKCFG field.
	SAI_BCLRFR_CWCKCFG_Msk = 0x4
	// Bit CWCKCFG.
	SAI_BCLRFR_CWCKCFG = 0x4
	// Position of CMUTEDET field.
	SAI_BCLRFR_CMUTEDET_Pos = 0x1
	// Bit mask of CMUTEDET field.
	SAI_BCLRFR_CMUTEDET_Msk = 0x2
	// Bit CMUTEDET.
	SAI_BCLRFR_CMUTEDET = 0x2
	// Position of COVRUDR field.
	SAI_BCLRFR_COVRUDR_Pos = 0x0
	// Bit mask of COVRUDR field.
	SAI_BCLRFR_COVRUDR_Msk = 0x1
	// Bit COVRUDR.
	SAI_BCLRFR_COVRUDR = 0x1

	// BDR: B Data register
	// Position of DATA field.
	SAI_BDR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SAI_BDR_DATA_Msk = 0xffffffff

	// PDMCR: PDM control register
	// Position of PDMEN field.
	SAI_PDMCR_PDMEN_Pos = 0x0
	// Bit mask of PDMEN field.
	SAI_PDMCR_PDMEN_Msk = 0x1
	// Bit PDMEN.
	SAI_PDMCR_PDMEN = 0x1
	// Position of MICNBR field.
	SAI_PDMCR_MICNBR_Pos = 0x4
	// Bit mask of MICNBR field.
	SAI_PDMCR_MICNBR_Msk = 0x30
	// Position of CKEN1 field.
	SAI_PDMCR_CKEN1_Pos = 0x8
	// Bit mask of CKEN1 field.
	SAI_PDMCR_CKEN1_Msk = 0x100
	// Bit CKEN1.
	SAI_PDMCR_CKEN1 = 0x100
	// Position of CKEN2 field.
	SAI_PDMCR_CKEN2_Pos = 0x9
	// Bit mask of CKEN2 field.
	SAI_PDMCR_CKEN2_Msk = 0x200
	// Bit CKEN2.
	SAI_PDMCR_CKEN2 = 0x200
	// Position of CKEN3 field.
	SAI_PDMCR_CKEN3_Pos = 0xa
	// Bit mask of CKEN3 field.
	SAI_PDMCR_CKEN3_Msk = 0x400
	// Bit CKEN3.
	SAI_PDMCR_CKEN3 = 0x400
	// Position of CKEN4 field.
	SAI_PDMCR_CKEN4_Pos = 0xb
	// Bit mask of CKEN4 field.
	SAI_PDMCR_CKEN4_Msk = 0x800
	// Bit CKEN4.
	SAI_PDMCR_CKEN4 = 0x800

	// PDMDLY: PDM delay register
	// Position of DLYM1L field.
	SAI_PDMDLY_DLYM1L_Pos = 0x0
	// Bit mask of DLYM1L field.
	SAI_PDMDLY_DLYM1L_Msk = 0x7
	// Position of DLYM1R field.
	SAI_PDMDLY_DLYM1R_Pos = 0x4
	// Bit mask of DLYM1R field.
	SAI_PDMDLY_DLYM1R_Msk = 0x70
	// Position of DLYM2L field.
	SAI_PDMDLY_DLYM2L_Pos = 0x8
	// Bit mask of DLYM2L field.
	SAI_PDMDLY_DLYM2L_Msk = 0x700
	// Position of DLYM2R field.
	SAI_PDMDLY_DLYM2R_Pos = 0xc
	// Bit mask of DLYM2R field.
	SAI_PDMDLY_DLYM2R_Msk = 0x7000
	// Position of DLYM3L field.
	SAI_PDMDLY_DLYM3L_Pos = 0x10
	// Bit mask of DLYM3L field.
	SAI_PDMDLY_DLYM3L_Msk = 0x70000
	// Position of DLYM3R field.
	SAI_PDMDLY_DLYM3R_Pos = 0x14
	// Bit mask of DLYM3R field.
	SAI_PDMDLY_DLYM3R_Msk = 0x700000
	// Position of DLYM4L field.
	SAI_PDMDLY_DLYM4L_Pos = 0x18
	// Bit mask of DLYM4L field.
	SAI_PDMDLY_DLYM4L_Msk = 0x7000000
	// Position of DLYM4R field.
	SAI_PDMDLY_DLYM4R_Pos = 0x1c
	// Bit mask of DLYM4R field.
	SAI_PDMDLY_DLYM4R_Msk = 0x70000000
)

// Constants for SDMMC1: Secure digital input/output MultiMediaCard interface
const (
	// POWER: power control register
	// Position of PWRCTRL field.
	SDMMC_POWER_PWRCTRL_Pos = 0x0
	// Bit mask of PWRCTRL field.
	SDMMC_POWER_PWRCTRL_Msk = 0x3
	// Position of VSWITCH field.
	SDMMC_POWER_VSWITCH_Pos = 0x2
	// Bit mask of VSWITCH field.
	SDMMC_POWER_VSWITCH_Msk = 0x4
	// Bit VSWITCH.
	SDMMC_POWER_VSWITCH = 0x4
	// Position of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN_Pos = 0x3
	// Bit mask of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN_Msk = 0x8
	// Bit VSWITCHEN.
	SDMMC_POWER_VSWITCHEN = 0x8
	// Position of DIRPOL field.
	SDMMC_POWER_DIRPOL_Pos = 0x4
	// Bit mask of DIRPOL field.
	SDMMC_POWER_DIRPOL_Msk = 0x10
	// Bit DIRPOL.
	SDMMC_POWER_DIRPOL = 0x10

	// CLKCR: clock control register
	// Position of SELCLKRX field.
	SDMMC_CLKCR_SELCLKRX_Pos = 0x14
	// Bit mask of SELCLKRX field.
	SDMMC_CLKCR_SELCLKRX_Msk = 0x300000
	// Position of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED_Pos = 0x13
	// Bit mask of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED_Msk = 0x80000
	// Bit BUSSPEED.
	SDMMC_CLKCR_BUSSPEED = 0x80000
	// Position of DDR field.
	SDMMC_CLKCR_DDR_Pos = 0x12
	// Bit mask of DDR field.
	SDMMC_CLKCR_DDR_Msk = 0x40000
	// Bit DDR.
	SDMMC_CLKCR_DDR = 0x40000
	// Position of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN_Pos = 0x11
	// Bit mask of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN_Msk = 0x20000
	// Bit HWFC_EN.
	SDMMC_CLKCR_HWFC_EN = 0x20000
	// Position of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE_Pos = 0x10
	// Bit mask of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE_Msk = 0x10000
	// Bit NEGEDGE.
	SDMMC_CLKCR_NEGEDGE = 0x10000
	// Position of WIDBUS field.
	SDMMC_CLKCR_WIDBUS_Pos = 0xe
	// Bit mask of WIDBUS field.
	SDMMC_CLKCR_WIDBUS_Msk = 0xc000
	// Position of PWRSAV field.
	SDMMC_CLKCR_PWRSAV_Pos = 0xc
	// Bit mask of PWRSAV field.
	SDMMC_CLKCR_PWRSAV_Msk = 0x1000
	// Bit PWRSAV.
	SDMMC_CLKCR_PWRSAV = 0x1000
	// Position of CLKDIV field.
	SDMMC_CLKCR_CLKDIV_Pos = 0x0
	// Bit mask of CLKDIV field.
	SDMMC_CLKCR_CLKDIV_Msk = 0x3ff

	// ARGR: argument register
	// Position of CMDARG field.
	SDMMC_ARGR_CMDARG_Pos = 0x0
	// Bit mask of CMDARG field.
	SDMMC_ARGR_CMDARG_Msk = 0xffffffff

	// CMDR: command register
	// Position of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND_Pos = 0x10
	// Bit mask of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND_Msk = 0x10000
	// Bit CMDSUSPEND.
	SDMMC_CMDR_CMDSUSPEND = 0x10000
	// Position of BOOTEN field.
	SDMMC_CMDR_BOOTEN_Pos = 0xf
	// Bit mask of BOOTEN field.
	SDMMC_CMDR_BOOTEN_Msk = 0x8000
	// Bit BOOTEN.
	SDMMC_CMDR_BOOTEN = 0x8000
	// Position of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE_Pos = 0xe
	// Bit mask of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE_Msk = 0x4000
	// Bit BOOTMODE.
	SDMMC_CMDR_BOOTMODE = 0x4000
	// Position of DTHOLD field.
	SDMMC_CMDR_DTHOLD_Pos = 0xd
	// Bit mask of DTHOLD field.
	SDMMC_CMDR_DTHOLD_Msk = 0x2000
	// Bit DTHOLD.
	SDMMC_CMDR_DTHOLD = 0x2000
	// Position of CPSMEN field.
	SDMMC_CMDR_CPSMEN_Pos = 0xc
	// Bit mask of CPSMEN field.
	SDMMC_CMDR_CPSMEN_Msk = 0x1000
	// Bit CPSMEN.
	SDMMC_CMDR_CPSMEN = 0x1000
	// Position of WAITPEND field.
	SDMMC_CMDR_WAITPEND_Pos = 0xb
	// Bit mask of WAITPEND field.
	SDMMC_CMDR_WAITPEND_Msk = 0x800
	// Bit WAITPEND.
	SDMMC_CMDR_WAITPEND = 0x800
	// Position of WAITINT field.
	SDMMC_CMDR_WAITINT_Pos = 0xa
	// Bit mask of WAITINT field.
	SDMMC_CMDR_WAITINT_Msk = 0x400
	// Bit WAITINT.
	SDMMC_CMDR_WAITINT = 0x400
	// Position of WAITRESP field.
	SDMMC_CMDR_WAITRESP_Pos = 0x8
	// Bit mask of WAITRESP field.
	SDMMC_CMDR_WAITRESP_Msk = 0x300
	// Position of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP_Pos = 0x7
	// Bit mask of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP_Msk = 0x80
	// Bit CMDSTOP.
	SDMMC_CMDR_CMDSTOP = 0x80
	// Position of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS_Pos = 0x6
	// Bit mask of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS_Msk = 0x40
	// Bit CMDTRANS.
	SDMMC_CMDR_CMDTRANS = 0x40
	// Position of CMDINDEX field.
	SDMMC_CMDR_CMDINDEX_Pos = 0x0
	// Bit mask of CMDINDEX field.
	SDMMC_CMDR_CMDINDEX_Msk = 0x3f

	// RESPCMDR: command response register
	// Position of RESPCMD field.
	SDMMC_RESPCMDR_RESPCMD_Pos = 0x0
	// Bit mask of RESPCMD field.
	SDMMC_RESPCMDR_RESPCMD_Msk = 0x3f

	// RESP1: SDIO response %s register
	// Position of CARDSTATUS field.
	SDMMC_RESP_CARDSTATUS_Pos = 0x0
	// Bit mask of CARDSTATUS field.
	SDMMC_RESP_CARDSTATUS_Msk = 0xffffffff

	// DTIMER: data timer register
	// Position of DATATIME field.
	SDMMC_DTIMER_DATATIME_Pos = 0x0
	// Bit mask of DATATIME field.
	SDMMC_DTIMER_DATATIME_Msk = 0xffffffff

	// DLENR: data length register
	// Position of DATALENGTH field.
	SDMMC_DLENR_DATALENGTH_Pos = 0x0
	// Bit mask of DATALENGTH field.
	SDMMC_DLENR_DATALENGTH_Msk = 0x1ffffff

	// DCTRL: data control register
	// Position of FIFORST field.
	SDMMC_DCTRL_FIFORST_Pos = 0xd
	// Bit mask of FIFORST field.
	SDMMC_DCTRL_FIFORST_Msk = 0x2000
	// Bit FIFORST.
	SDMMC_DCTRL_FIFORST = 0x2000
	// Position of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN_Pos = 0xc
	// Bit mask of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN_Msk = 0x1000
	// Bit BOOTACKEN.
	SDMMC_DCTRL_BOOTACKEN = 0x1000
	// Position of SDIOEN field.
	SDMMC_DCTRL_SDIOEN_Pos = 0xb
	// Bit mask of SDIOEN field.
	SDMMC_DCTRL_SDIOEN_Msk = 0x800
	// Bit SDIOEN.
	SDMMC_DCTRL_SDIOEN = 0x800
	// Position of RWMOD field.
	SDMMC_DCTRL_RWMOD_Pos = 0xa
	// Bit mask of RWMOD field.
	SDMMC_DCTRL_RWMOD_Msk = 0x400
	// Bit RWMOD.
	SDMMC_DCTRL_RWMOD = 0x400
	// Position of RWSTOP field.
	SDMMC_DCTRL_RWSTOP_Pos = 0x9
	// Bit mask of RWSTOP field.
	SDMMC_DCTRL_RWSTOP_Msk = 0x200
	// Bit RWSTOP.
	SDMMC_DCTRL_RWSTOP = 0x200
	// Position of RWSTART field.
	SDMMC_DCTRL_RWSTART_Pos = 0x8
	// Bit mask of RWSTART field.
	SDMMC_DCTRL_RWSTART_Msk = 0x100
	// Bit RWSTART.
	SDMMC_DCTRL_RWSTART = 0x100
	// Position of DBLOCKSIZE field.
	SDMMC_DCTRL_DBLOCKSIZE_Pos = 0x4
	// Bit mask of DBLOCKSIZE field.
	SDMMC_DCTRL_DBLOCKSIZE_Msk = 0xf0
	// Position of DTMODE field.
	SDMMC_DCTRL_DTMODE_Pos = 0x2
	// Bit mask of DTMODE field.
	SDMMC_DCTRL_DTMODE_Msk = 0xc
	// Position of DTDIR field.
	SDMMC_DCTRL_DTDIR_Pos = 0x1
	// Bit mask of DTDIR field.
	SDMMC_DCTRL_DTDIR_Msk = 0x2
	// Bit DTDIR.
	SDMMC_DCTRL_DTDIR = 0x2
	// Position of DTEN field.
	SDMMC_DCTRL_DTEN_Pos = 0x0
	// Bit mask of DTEN field.
	SDMMC_DCTRL_DTEN_Msk = 0x1
	// Bit DTEN.
	SDMMC_DCTRL_DTEN = 0x1

	// DCNTR: data counter register
	// Position of DATACOUNT field.
	SDMMC_DCNTR_DATACOUNT_Pos = 0x0
	// Bit mask of DATACOUNT field.
	SDMMC_DCNTR_DATACOUNT_Msk = 0x1ffffff

	// STAR: status register
	// Position of IDMABTC field.
	SDMMC_STAR_IDMABTC_Pos = 0x1c
	// Bit mask of IDMABTC field.
	SDMMC_STAR_IDMABTC_Msk = 0x10000000
	// Bit IDMABTC.
	SDMMC_STAR_IDMABTC = 0x10000000
	// Position of IDMATE field.
	SDMMC_STAR_IDMATE_Pos = 0x1b
	// Bit mask of IDMATE field.
	SDMMC_STAR_IDMATE_Msk = 0x8000000
	// Bit IDMATE.
	SDMMC_STAR_IDMATE = 0x8000000
	// Position of CKSTOP field.
	SDMMC_STAR_CKSTOP_Pos = 0x1a
	// Bit mask of CKSTOP field.
	SDMMC_STAR_CKSTOP_Msk = 0x4000000
	// Bit CKSTOP.
	SDMMC_STAR_CKSTOP = 0x4000000
	// Position of VSWEND field.
	SDMMC_STAR_VSWEND_Pos = 0x19
	// Bit mask of VSWEND field.
	SDMMC_STAR_VSWEND_Msk = 0x2000000
	// Bit VSWEND.
	SDMMC_STAR_VSWEND = 0x2000000
	// Position of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT_Pos = 0x18
	// Bit mask of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT_Msk = 0x1000000
	// Bit ACKTIMEOUT.
	SDMMC_STAR_ACKTIMEOUT = 0x1000000
	// Position of ACKFAIL field.
	SDMMC_STAR_ACKFAIL_Pos = 0x17
	// Bit mask of ACKFAIL field.
	SDMMC_STAR_ACKFAIL_Msk = 0x800000
	// Bit ACKFAIL.
	SDMMC_STAR_ACKFAIL = 0x800000
	// Position of SDIOIT field.
	SDMMC_STAR_SDIOIT_Pos = 0x16
	// Bit mask of SDIOIT field.
	SDMMC_STAR_SDIOIT_Msk = 0x400000
	// Bit SDIOIT.
	SDMMC_STAR_SDIOIT = 0x400000
	// Position of BUSYD0END field.
	SDMMC_STAR_BUSYD0END_Pos = 0x15
	// Bit mask of BUSYD0END field.
	SDMMC_STAR_BUSYD0END_Msk = 0x200000
	// Bit BUSYD0END.
	SDMMC_STAR_BUSYD0END = 0x200000
	// Position of BUSYD0 field.
	SDMMC_STAR_BUSYD0_Pos = 0x14
	// Bit mask of BUSYD0 field.
	SDMMC_STAR_BUSYD0_Msk = 0x100000
	// Bit BUSYD0.
	SDMMC_STAR_BUSYD0 = 0x100000
	// Position of RXFIFOE field.
	SDMMC_STAR_RXFIFOE_Pos = 0x13
	// Bit mask of RXFIFOE field.
	SDMMC_STAR_RXFIFOE_Msk = 0x80000
	// Bit RXFIFOE.
	SDMMC_STAR_RXFIFOE = 0x80000
	// Position of TXFIFOE field.
	SDMMC_STAR_TXFIFOE_Pos = 0x12
	// Bit mask of TXFIFOE field.
	SDMMC_STAR_TXFIFOE_Msk = 0x40000
	// Bit TXFIFOE.
	SDMMC_STAR_TXFIFOE = 0x40000
	// Position of RXFIFOF field.
	SDMMC_STAR_RXFIFOF_Pos = 0x11
	// Bit mask of RXFIFOF field.
	SDMMC_STAR_RXFIFOF_Msk = 0x20000
	// Bit RXFIFOF.
	SDMMC_STAR_RXFIFOF = 0x20000
	// Position of TXFIFOF field.
	SDMMC_STAR_TXFIFOF_Pos = 0x10
	// Bit mask of TXFIFOF field.
	SDMMC_STAR_TXFIFOF_Msk = 0x10000
	// Bit TXFIFOF.
	SDMMC_STAR_TXFIFOF = 0x10000
	// Position of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF_Pos = 0xf
	// Bit mask of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF_Msk = 0x8000
	// Bit RXFIFOHF.
	SDMMC_STAR_RXFIFOHF = 0x8000
	// Position of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE_Pos = 0xe
	// Bit mask of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE_Msk = 0x4000
	// Bit TXFIFOHE.
	SDMMC_STAR_TXFIFOHE = 0x4000
	// Position of CPSMACT field.
	SDMMC_STAR_CPSMACT_Pos = 0xd
	// Bit mask of CPSMACT field.
	SDMMC_STAR_CPSMACT_Msk = 0x2000
	// Bit CPSMACT.
	SDMMC_STAR_CPSMACT = 0x2000
	// Position of DPSMACT field.
	SDMMC_STAR_DPSMACT_Pos = 0xc
	// Bit mask of DPSMACT field.
	SDMMC_STAR_DPSMACT_Msk = 0x1000
	// Bit DPSMACT.
	SDMMC_STAR_DPSMACT = 0x1000
	// Position of DABORT field.
	SDMMC_STAR_DABORT_Pos = 0xb
	// Bit mask of DABORT field.
	SDMMC_STAR_DABORT_Msk = 0x800
	// Bit DABORT.
	SDMMC_STAR_DABORT = 0x800
	// Position of DBCKEND field.
	SDMMC_STAR_DBCKEND_Pos = 0xa
	// Bit mask of DBCKEND field.
	SDMMC_STAR_DBCKEND_Msk = 0x400
	// Bit DBCKEND.
	SDMMC_STAR_DBCKEND = 0x400
	// Position of DHOLD field.
	SDMMC_STAR_DHOLD_Pos = 0x9
	// Bit mask of DHOLD field.
	SDMMC_STAR_DHOLD_Msk = 0x200
	// Bit DHOLD.
	SDMMC_STAR_DHOLD = 0x200
	// Position of DATAEND field.
	SDMMC_STAR_DATAEND_Pos = 0x8
	// Bit mask of DATAEND field.
	SDMMC_STAR_DATAEND_Msk = 0x100
	// Bit DATAEND.
	SDMMC_STAR_DATAEND = 0x100
	// Position of CMDSENT field.
	SDMMC_STAR_CMDSENT_Pos = 0x7
	// Bit mask of CMDSENT field.
	SDMMC_STAR_CMDSENT_Msk = 0x80
	// Bit CMDSENT.
	SDMMC_STAR_CMDSENT = 0x80
	// Position of CMDREND field.
	SDMMC_STAR_CMDREND_Pos = 0x6
	// Bit mask of CMDREND field.
	SDMMC_STAR_CMDREND_Msk = 0x40
	// Bit CMDREND.
	SDMMC_STAR_CMDREND = 0x40
	// Position of RXOVERR field.
	SDMMC_STAR_RXOVERR_Pos = 0x5
	// Bit mask of RXOVERR field.
	SDMMC_STAR_RXOVERR_Msk = 0x20
	// Bit RXOVERR.
	SDMMC_STAR_RXOVERR = 0x20
	// Position of TXUNDERR field.
	SDMMC_STAR_TXUNDERR_Pos = 0x4
	// Bit mask of TXUNDERR field.
	SDMMC_STAR_TXUNDERR_Msk = 0x10
	// Bit TXUNDERR.
	SDMMC_STAR_TXUNDERR = 0x10
	// Position of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT_Pos = 0x3
	// Bit mask of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT_Msk = 0x8
	// Bit DTIMEOUT.
	SDMMC_STAR_DTIMEOUT = 0x8
	// Position of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT_Pos = 0x2
	// Bit mask of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT_Msk = 0x4
	// Bit CTIMEOUT.
	SDMMC_STAR_CTIMEOUT = 0x4
	// Position of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL_Pos = 0x1
	// Bit mask of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL_Msk = 0x2
	// Bit DCRCFAIL.
	SDMMC_STAR_DCRCFAIL = 0x2
	// Position of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL_Pos = 0x0
	// Bit mask of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL_Msk = 0x1
	// Bit CCRCFAIL.
	SDMMC_STAR_CCRCFAIL = 0x1

	// ICR: interrupt clear register
	// Position of IDMABTCC field.
	SDMMC_ICR_IDMABTCC_Pos = 0x1c
	// Bit mask of IDMABTCC field.
	SDMMC_ICR_IDMABTCC_Msk = 0x10000000
	// Bit IDMABTCC.
	SDMMC_ICR_IDMABTCC = 0x10000000
	// Position of IDMATEC field.
	SDMMC_ICR_IDMATEC_Pos = 0x1b
	// Bit mask of IDMATEC field.
	SDMMC_ICR_IDMATEC_Msk = 0x8000000
	// Bit IDMATEC.
	SDMMC_ICR_IDMATEC = 0x8000000
	// Position of CKSTOPC field.
	SDMMC_ICR_CKSTOPC_Pos = 0x1a
	// Bit mask of CKSTOPC field.
	SDMMC_ICR_CKSTOPC_Msk = 0x4000000
	// Bit CKSTOPC.
	SDMMC_ICR_CKSTOPC = 0x4000000
	// Position of VSWENDC field.
	SDMMC_ICR_VSWENDC_Pos = 0x19
	// Bit mask of VSWENDC field.
	SDMMC_ICR_VSWENDC_Msk = 0x2000000
	// Bit VSWENDC.
	SDMMC_ICR_VSWENDC = 0x2000000
	// Position of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC_Pos = 0x18
	// Bit mask of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC_Msk = 0x1000000
	// Bit ACKTIMEOUTC.
	SDMMC_ICR_ACKTIMEOUTC = 0x1000000
	// Position of ACKFAILC field.
	SDMMC_ICR_ACKFAILC_Pos = 0x17
	// Bit mask of ACKFAILC field.
	SDMMC_ICR_ACKFAILC_Msk = 0x800000
	// Bit ACKFAILC.
	SDMMC_ICR_ACKFAILC = 0x800000
	// Position of SDIOITC field.
	SDMMC_ICR_SDIOITC_Pos = 0x16
	// Bit mask of SDIOITC field.
	SDMMC_ICR_SDIOITC_Msk = 0x400000
	// Bit SDIOITC.
	SDMMC_ICR_SDIOITC = 0x400000
	// Position of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC_Pos = 0x15
	// Bit mask of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC_Msk = 0x200000
	// Bit BUSYD0ENDC.
	SDMMC_ICR_BUSYD0ENDC = 0x200000
	// Position of DABORTC field.
	SDMMC_ICR_DABORTC_Pos = 0xb
	// Bit mask of DABORTC field.
	SDMMC_ICR_DABORTC_Msk = 0x800
	// Bit DABORTC.
	SDMMC_ICR_DABORTC = 0x800
	// Position of DBCKENDC field.
	SDMMC_ICR_DBCKENDC_Pos = 0xa
	// Bit mask of DBCKENDC field.
	SDMMC_ICR_DBCKENDC_Msk = 0x400
	// Bit DBCKENDC.
	SDMMC_ICR_DBCKENDC = 0x400
	// Position of DHOLDC field.
	SDMMC_ICR_DHOLDC_Pos = 0x9
	// Bit mask of DHOLDC field.
	SDMMC_ICR_DHOLDC_Msk = 0x200
	// Bit DHOLDC.
	SDMMC_ICR_DHOLDC = 0x200
	// Position of DATAENDC field.
	SDMMC_ICR_DATAENDC_Pos = 0x8
	// Bit mask of DATAENDC field.
	SDMMC_ICR_DATAENDC_Msk = 0x100
	// Bit DATAENDC.
	SDMMC_ICR_DATAENDC = 0x100
	// Position of CMDSENTC field.
	SDMMC_ICR_CMDSENTC_Pos = 0x7
	// Bit mask of CMDSENTC field.
	SDMMC_ICR_CMDSENTC_Msk = 0x80
	// Bit CMDSENTC.
	SDMMC_ICR_CMDSENTC = 0x80
	// Position of CMDRENDC field.
	SDMMC_ICR_CMDRENDC_Pos = 0x6
	// Bit mask of CMDRENDC field.
	SDMMC_ICR_CMDRENDC_Msk = 0x40
	// Bit CMDRENDC.
	SDMMC_ICR_CMDRENDC = 0x40
	// Position of RXOVERRC field.
	SDMMC_ICR_RXOVERRC_Pos = 0x5
	// Bit mask of RXOVERRC field.
	SDMMC_ICR_RXOVERRC_Msk = 0x20
	// Bit RXOVERRC.
	SDMMC_ICR_RXOVERRC = 0x20
	// Position of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC_Pos = 0x4
	// Bit mask of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC_Msk = 0x10
	// Bit TXUNDERRC.
	SDMMC_ICR_TXUNDERRC = 0x10
	// Position of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC_Pos = 0x3
	// Bit mask of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC_Msk = 0x8
	// Bit DTIMEOUTC.
	SDMMC_ICR_DTIMEOUTC = 0x8
	// Position of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC_Pos = 0x2
	// Bit mask of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC_Msk = 0x4
	// Bit CTIMEOUTC.
	SDMMC_ICR_CTIMEOUTC = 0x4
	// Position of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC_Pos = 0x1
	// Bit mask of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC_Msk = 0x2
	// Bit DCRCFAILC.
	SDMMC_ICR_DCRCFAILC = 0x2
	// Position of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC_Pos = 0x0
	// Bit mask of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC_Msk = 0x1
	// Bit CCRCFAILC.
	SDMMC_ICR_CCRCFAILC = 0x1

	// MASKR: mask register
	// Position of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE_Pos = 0x1c
	// Bit mask of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE_Msk = 0x10000000
	// Bit IDMABTCIE.
	SDMMC_MASKR_IDMABTCIE = 0x10000000
	// Position of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE_Pos = 0x1a
	// Bit mask of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE_Msk = 0x4000000
	// Bit CKSTOPIE.
	SDMMC_MASKR_CKSTOPIE = 0x4000000
	// Position of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE_Pos = 0x19
	// Bit mask of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE_Msk = 0x2000000
	// Bit VSWENDIE.
	SDMMC_MASKR_VSWENDIE = 0x2000000
	// Position of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE_Pos = 0x18
	// Bit mask of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE_Msk = 0x1000000
	// Bit ACKTIMEOUTIE.
	SDMMC_MASKR_ACKTIMEOUTIE = 0x1000000
	// Position of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE_Pos = 0x17
	// Bit mask of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE_Msk = 0x800000
	// Bit ACKFAILIE.
	SDMMC_MASKR_ACKFAILIE = 0x800000
	// Position of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE_Pos = 0x16
	// Bit mask of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE_Msk = 0x400000
	// Bit SDIOITIE.
	SDMMC_MASKR_SDIOITIE = 0x400000
	// Position of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE_Pos = 0x15
	// Bit mask of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE_Msk = 0x200000
	// Bit BUSYD0ENDIE.
	SDMMC_MASKR_BUSYD0ENDIE = 0x200000
	// Position of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE_Pos = 0x12
	// Bit mask of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE_Msk = 0x40000
	// Bit TXFIFOEIE.
	SDMMC_MASKR_TXFIFOEIE = 0x40000
	// Position of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE_Pos = 0x11
	// Bit mask of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE_Msk = 0x20000
	// Bit RXFIFOFIE.
	SDMMC_MASKR_RXFIFOFIE = 0x20000
	// Position of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE_Pos = 0xf
	// Bit mask of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE_Msk = 0x8000
	// Bit RXFIFOHFIE.
	SDMMC_MASKR_RXFIFOHFIE = 0x8000
	// Position of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE_Pos = 0xe
	// Bit mask of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE_Msk = 0x4000
	// Bit TXFIFOHEIE.
	SDMMC_MASKR_TXFIFOHEIE = 0x4000
	// Position of DABORTIE field.
	SDMMC_MASKR_DABORTIE_Pos = 0xb
	// Bit mask of DABORTIE field.
	SDMMC_MASKR_DABORTIE_Msk = 0x800
	// Bit DABORTIE.
	SDMMC_MASKR_DABORTIE = 0x800
	// Position of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE_Pos = 0xa
	// Bit mask of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE_Msk = 0x400
	// Bit DBCKENDIE.
	SDMMC_MASKR_DBCKENDIE = 0x400
	// Position of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE_Pos = 0x9
	// Bit mask of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE_Msk = 0x200
	// Bit DHOLDIE.
	SDMMC_MASKR_DHOLDIE = 0x200
	// Position of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE_Pos = 0x8
	// Bit mask of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE_Msk = 0x100
	// Bit DATAENDIE.
	SDMMC_MASKR_DATAENDIE = 0x100
	// Position of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE_Pos = 0x7
	// Bit mask of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE_Msk = 0x80
	// Bit CMDSENTIE.
	SDMMC_MASKR_CMDSENTIE = 0x80
	// Position of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE_Pos = 0x6
	// Bit mask of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE_Msk = 0x40
	// Bit CMDRENDIE.
	SDMMC_MASKR_CMDRENDIE = 0x40
	// Position of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE_Pos = 0x5
	// Bit mask of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE_Msk = 0x20
	// Bit RXOVERRIE.
	SDMMC_MASKR_RXOVERRIE = 0x20
	// Position of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE_Pos = 0x4
	// Bit mask of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE_Msk = 0x10
	// Bit TXUNDERRIE.
	SDMMC_MASKR_TXUNDERRIE = 0x10
	// Position of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE_Pos = 0x3
	// Bit mask of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE_Msk = 0x8
	// Bit DTIMEOUTIE.
	SDMMC_MASKR_DTIMEOUTIE = 0x8
	// Position of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE_Pos = 0x2
	// Bit mask of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE_Msk = 0x4
	// Bit CTIMEOUTIE.
	SDMMC_MASKR_CTIMEOUTIE = 0x4
	// Position of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE_Pos = 0x1
	// Bit mask of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE_Msk = 0x2
	// Bit DCRCFAILIE.
	SDMMC_MASKR_DCRCFAILIE = 0x2
	// Position of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE_Pos = 0x0
	// Bit mask of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE_Msk = 0x1
	// Bit CCRCFAILIE.
	SDMMC_MASKR_CCRCFAILIE = 0x1

	// ACKTIMER: acknowledgment timer register
	// Position of ACKTIME field.
	SDMMC_ACKTIMER_ACKTIME_Pos = 0x0
	// Bit mask of ACKTIME field.
	SDMMC_ACKTIMER_ACKTIME_Msk = 0x1ffffff

	// IDMACTRLR: DMA control register
	// Position of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN_Pos = 0x0
	// Bit mask of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN_Msk = 0x1
	// Bit IDMAEN.
	SDMMC_IDMACTRLR_IDMAEN = 0x1
	// Position of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE_Pos = 0x1
	// Bit mask of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE_Msk = 0x2
	// Bit IDMABMODE.
	SDMMC_IDMACTRLR_IDMABMODE = 0x2

	// IDMABSIZER: buffer size register
	// Position of IDMABNDT field.
	SDMMC_IDMABSIZER_IDMABNDT_Pos = 0x5
	// Bit mask of IDMABNDT field.
	SDMMC_IDMABSIZER_IDMABNDT_Msk = 0x1ffe0

	// IDMABASER: buffer base address register
	// Position of IDMABASE field.
	SDMMC_IDMABASER_IDMABASE_Pos = 0x0
	// Bit mask of IDMABASE field.
	SDMMC_IDMABASER_IDMABASE_Msk = 0xffffffff

	// IDMALAR: linked list address register
	// Position of ULA field.
	SDMMC_IDMALAR_ULA_Pos = 0x1f
	// Bit mask of ULA field.
	SDMMC_IDMALAR_ULA_Msk = 0x80000000
	// Bit ULA.
	SDMMC_IDMALAR_ULA = 0x80000000
	// Position of ULS field.
	SDMMC_IDMALAR_ULS_Pos = 0x1e
	// Bit mask of ULS field.
	SDMMC_IDMALAR_ULS_Msk = 0x40000000
	// Bit ULS.
	SDMMC_IDMALAR_ULS = 0x40000000
	// Position of ABR field.
	SDMMC_IDMALAR_ABR_Pos = 0x1d
	// Bit mask of ABR field.
	SDMMC_IDMALAR_ABR_Msk = 0x20000000
	// Bit ABR.
	SDMMC_IDMALAR_ABR = 0x20000000
	// Position of IDMALA field.
	SDMMC_IDMALAR_IDMALA_Pos = 0x2
	// Bit mask of IDMALA field.
	SDMMC_IDMALAR_IDMALA_Msk = 0xfffc

	// IDMABAR: linked list memory base register
	// Position of IDMABA field.
	SDMMC_IDMABAR_IDMABA_Pos = 0x2
	// Bit mask of IDMABA field.
	SDMMC_IDMABAR_IDMABA_Msk = 0xfffffffc

	// FIFOR0: data FIFO register %s
	// Position of FIFODATA field.
	SDMMC_FIFOR_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC_FIFOR_FIFODATA_Msk = 0xffffffff
)

// Constants for SPI1: Serial peripheral interface
const (
	// CR1: control register 1
	// Position of IOLOCK field.
	SPI_CR1_IOLOCK_Pos = 0x10
	// Bit mask of IOLOCK field.
	SPI_CR1_IOLOCK_Msk = 0x10000
	// Bit IOLOCK.
	SPI_CR1_IOLOCK = 0x10000
	// IO configuration unlocked
	SPI_CR1_IOLOCK_Unlocked = 0x0
	// IO configuration locked
	SPI_CR1_IOLOCK_Locked = 0x1
	// Position of TCRCINI field.
	SPI_CR1_TCRCINI_Pos = 0xf
	// Bit mask of TCRCINI field.
	SPI_CR1_TCRCINI_Msk = 0x8000
	// Bit TCRCINI.
	SPI_CR1_TCRCINI = 0x8000
	// All zeros TX CRC initialization pattern
	SPI_CR1_TCRCINI_AllZeros = 0x0
	// All ones TX CRC initialization pattern
	SPI_CR1_TCRCINI_AllOnes = 0x1
	// Position of RCRCINI field.
	SPI_CR1_RCRCINI_Pos = 0xe
	// Bit mask of RCRCINI field.
	SPI_CR1_RCRCINI_Msk = 0x4000
	// Bit RCRCINI.
	SPI_CR1_RCRCINI = 0x4000
	// All zeros RX CRC initialization pattern
	SPI_CR1_RCRCINI_AllZeros = 0x0
	// All ones RX CRC initialization pattern
	SPI_CR1_RCRCINI_AllOnes = 0x1
	// Position of CRC33_17 field.
	SPI_CR1_CRC33_17_Pos = 0xd
	// Bit mask of CRC33_17 field.
	SPI_CR1_CRC33_17_Msk = 0x2000
	// Bit CRC33_17.
	SPI_CR1_CRC33_17 = 0x2000
	// Full size (33/17 bit) CRC polynomial is not used
	SPI_CR1_CRC33_17_Disabled = 0x0
	// Full size (33/17 bit) CRC polynomial is used
	SPI_CR1_CRC33_17_Enabled = 0x1
	// Position of SSI field.
	SPI_CR1_SSI_Pos = 0xc
	// Bit mask of SSI field.
	SPI_CR1_SSI_Msk = 0x1000
	// Bit SSI.
	SPI_CR1_SSI = 0x1000
	// 0 is forced onto the SS signal and the I/O value of the SS pin is ignored
	SPI_CR1_SSI_SlaveSelected = 0x0
	// 1 is forced onto the SS signal and the I/O value of the SS pin is ignored
	SPI_CR1_SSI_SlaveNotSelected = 0x1
	// Position of HDDIR field.
	SPI_CR1_HDDIR_Pos = 0xb
	// Bit mask of HDDIR field.
	SPI_CR1_HDDIR_Msk = 0x800
	// Bit HDDIR.
	SPI_CR1_HDDIR = 0x800
	// Receiver in half duplex mode
	SPI_CR1_HDDIR_Receiver = 0x0
	// Transmitter in half duplex mode
	SPI_CR1_HDDIR_Transmitter = 0x1
	// Position of CSUSP field.
	SPI_CR1_CSUSP_Pos = 0xa
	// Bit mask of CSUSP field.
	SPI_CR1_CSUSP_Msk = 0x400
	// Bit CSUSP.
	SPI_CR1_CSUSP = 0x400
	// Do not request master suspend
	SPI_CR1_CSUSP_NotRequested = 0x0
	// Request master suspend
	SPI_CR1_CSUSP_Requested = 0x1
	// Position of CSTART field.
	SPI_CR1_CSTART_Pos = 0x9
	// Bit mask of CSTART field.
	SPI_CR1_CSTART_Msk = 0x200
	// Bit CSTART.
	SPI_CR1_CSTART = 0x200
	// Do not start master transfer
	SPI_CR1_CSTART_NotStarted = 0x0
	// Start master transfer
	SPI_CR1_CSTART_Started = 0x1
	// Position of MASRX field.
	SPI_CR1_MASRX_Pos = 0x8
	// Bit mask of MASRX field.
	SPI_CR1_MASRX_Msk = 0x100
	// Bit MASRX.
	SPI_CR1_MASRX = 0x100
	// Automatic suspend in master receive-only mode disabled
	SPI_CR1_MASRX_Disabled = 0x0
	// Automatic suspend in master receive-only mode enabled
	SPI_CR1_MASRX_Enabled = 0x1
	// Position of SPE field.
	SPI_CR1_SPE_Pos = 0x0
	// Bit mask of SPE field.
	SPI_CR1_SPE_Msk = 0x1
	// Bit SPE.
	SPI_CR1_SPE = 0x1
	// Peripheral disabled
	SPI_CR1_SPE_Disabled = 0x0
	// Peripheral enabled
	SPI_CR1_SPE_Enabled = 0x1

	// CR2: control register 2
	// Position of TSIZE field.
	SPI_CR2_TSIZE_Pos = 0x0
	// Bit mask of TSIZE field.
	SPI_CR2_TSIZE_Msk = 0xffff

	// CFG1: configuration register 1
	// Position of BPASS field.
	SPI_CFG1_BPASS_Pos = 0x1f
	// Bit mask of BPASS field.
	SPI_CFG1_BPASS_Msk = 0x80000000
	// Bit BPASS.
	SPI_CFG1_BPASS = 0x80000000
	// Bypass is disabled
	SPI_CFG1_BPASS_Disabled = 0x0
	// Bypass is enabled
	SPI_CFG1_BPASS_Enabled = 0x1
	// Position of MBR field.
	SPI_CFG1_MBR_Pos = 0x1c
	// Bit mask of MBR field.
	SPI_CFG1_MBR_Msk = 0x70000000
	// f_spi_ker_ck / 2
	SPI_CFG1_MBR_Div2 = 0x0
	// f_spi_ker_ck / 4
	SPI_CFG1_MBR_Div4 = 0x1
	// f_spi_ker_ck / 8
	SPI_CFG1_MBR_Div8 = 0x2
	// f_spi_ker_ck / 16
	SPI_CFG1_MBR_Div16 = 0x3
	// f_spi_ker_ck / 32
	SPI_CFG1_MBR_Div32 = 0x4
	// f_spi_ker_ck / 64
	SPI_CFG1_MBR_Div64 = 0x5
	// f_spi_ker_ck / 128
	SPI_CFG1_MBR_Div128 = 0x6
	// f_spi_ker_ck / 256
	SPI_CFG1_MBR_Div256 = 0x7
	// Position of CRCEN field.
	SPI_CFG1_CRCEN_Pos = 0x16
	// Bit mask of CRCEN field.
	SPI_CFG1_CRCEN_Msk = 0x400000
	// Bit CRCEN.
	SPI_CFG1_CRCEN = 0x400000
	// CRC calculation disabled
	SPI_CFG1_CRCEN_Disabled = 0x0
	// CRC calculation enabled
	SPI_CFG1_CRCEN_Enabled = 0x1
	// Position of CRCSIZE field.
	SPI_CFG1_CRCSIZE_Pos = 0x10
	// Bit mask of CRCSIZE field.
	SPI_CFG1_CRCSIZE_Msk = 0x1f0000
	// Position of TXDMAEN field.
	SPI_CFG1_TXDMAEN_Pos = 0xf
	// Bit mask of TXDMAEN field.
	SPI_CFG1_TXDMAEN_Msk = 0x8000
	// Bit TXDMAEN.
	SPI_CFG1_TXDMAEN = 0x8000
	// Tx buffer DMA disabled
	SPI_CFG1_TXDMAEN_Disabled = 0x0
	// Tx buffer DMA enabled
	SPI_CFG1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	SPI_CFG1_RXDMAEN_Pos = 0xe
	// Bit mask of RXDMAEN field.
	SPI_CFG1_RXDMAEN_Msk = 0x4000
	// Bit RXDMAEN.
	SPI_CFG1_RXDMAEN = 0x4000
	// Rx buffer DMA disabled
	SPI_CFG1_RXDMAEN_Disabled = 0x0
	// Rx buffer DMA enabled
	SPI_CFG1_RXDMAEN_Enabled = 0x1
	// Position of UDRCFG field.
	SPI_CFG1_UDRCFG_Pos = 0x9
	// Bit mask of UDRCFG field.
	SPI_CFG1_UDRCFG_Msk = 0x200
	// Bit UDRCFG.
	SPI_CFG1_UDRCFG = 0x200
	// Slave sends a constant underrun pattern
	SPI_CFG1_UDRCFG_Constant = 0x0
	// Slave repeats last received data frame from master
	SPI_CFG1_UDRCFG_RepeatReceived = 0x1
	// Position of FTHLV field.
	SPI_CFG1_FTHLV_Pos = 0x5
	// Bit mask of FTHLV field.
	SPI_CFG1_FTHLV_Msk = 0x1e0
	// 1 frame
	SPI_CFG1_FTHLV_OneFrame = 0x0
	// 2 frames
	SPI_CFG1_FTHLV_TwoFrames = 0x1
	// 3 frames
	SPI_CFG1_FTHLV_ThreeFrames = 0x2
	// 4 frames
	SPI_CFG1_FTHLV_FourFrames = 0x3
	// 5 frames
	SPI_CFG1_FTHLV_FiveFrames = 0x4
	// 6 frames
	SPI_CFG1_FTHLV_SixFrames = 0x5
	// 7 frames
	SPI_CFG1_FTHLV_SevenFrames = 0x6
	// 8 frames
	SPI_CFG1_FTHLV_EightFrames = 0x7
	// 9 frames
	SPI_CFG1_FTHLV_NineFrames = 0x8
	// 10 frames
	SPI_CFG1_FTHLV_TenFrames = 0x9
	// 11 frames
	SPI_CFG1_FTHLV_ElevenFrames = 0xa
	// 12 frames
	SPI_CFG1_FTHLV_TwelveFrames = 0xb
	// 13 frames
	SPI_CFG1_FTHLV_ThirteenFrames = 0xc
	// 14 frames
	SPI_CFG1_FTHLV_FourteenFrames = 0xd
	// 15 frames
	SPI_CFG1_FTHLV_FifteenFrames = 0xe
	// 16 frames
	SPI_CFG1_FTHLV_SixteenFrames = 0xf
	// Position of DSIZE field.
	SPI_CFG1_DSIZE_Pos = 0x0
	// Bit mask of DSIZE field.
	SPI_CFG1_DSIZE_Msk = 0x1f

	// CFG2: configuration register 2
	// Position of AFCNTR field.
	SPI_CFG2_AFCNTR_Pos = 0x1f
	// Bit mask of AFCNTR field.
	SPI_CFG2_AFCNTR_Msk = 0x80000000
	// Bit AFCNTR.
	SPI_CFG2_AFCNTR = 0x80000000
	// Peripheral takes no control of GPIOs while disabled
	SPI_CFG2_AFCNTR_NotControlled = 0x0
	// Peripheral controls GPIOs while disabled
	SPI_CFG2_AFCNTR_Controlled = 0x1
	// Position of SSOM field.
	SPI_CFG2_SSOM_Pos = 0x1e
	// Bit mask of SSOM field.
	SPI_CFG2_SSOM_Msk = 0x40000000
	// Bit SSOM.
	SPI_CFG2_SSOM = 0x40000000
	// SS is asserted until data transfer complete
	SPI_CFG2_SSOM_Asserted = 0x0
	// Data frames interleaved with SS not asserted during MIDI
	SPI_CFG2_SSOM_NotAsserted = 0x1
	// Position of SSOE field.
	SPI_CFG2_SSOE_Pos = 0x1d
	// Bit mask of SSOE field.
	SPI_CFG2_SSOE_Msk = 0x20000000
	// Bit SSOE.
	SPI_CFG2_SSOE = 0x20000000
	// SS output is disabled in master mode
	SPI_CFG2_SSOE_Disabled = 0x0
	// SS output is enabled in master mode
	SPI_CFG2_SSOE_Enabled = 0x1
	// Position of SSIOP field.
	SPI_CFG2_SSIOP_Pos = 0x1c
	// Bit mask of SSIOP field.
	SPI_CFG2_SSIOP_Msk = 0x10000000
	// Bit SSIOP.
	SPI_CFG2_SSIOP = 0x10000000
	// Low level is active for SS signal
	SPI_CFG2_SSIOP_ActiveLow = 0x0
	// High level is active for SS signal
	SPI_CFG2_SSIOP_ActiveHigh = 0x1
	// Position of SSM field.
	SPI_CFG2_SSM_Pos = 0x1a
	// Bit mask of SSM field.
	SPI_CFG2_SSM_Msk = 0x4000000
	// Bit SSM.
	SPI_CFG2_SSM = 0x4000000
	// Software slave management disabled
	SPI_CFG2_SSM_Disabled = 0x0
	// Software slave management enabled
	SPI_CFG2_SSM_Enabled = 0x1
	// Position of CPOL field.
	SPI_CFG2_CPOL_Pos = 0x19
	// Bit mask of CPOL field.
	SPI_CFG2_CPOL_Msk = 0x2000000
	// Bit CPOL.
	SPI_CFG2_CPOL = 0x2000000
	// CK to 0 when idle
	SPI_CFG2_CPOL_IdleLow = 0x0
	// CK to 1 when idle
	SPI_CFG2_CPOL_IdleHigh = 0x1
	// Position of CPHA field.
	SPI_CFG2_CPHA_Pos = 0x18
	// Bit mask of CPHA field.
	SPI_CFG2_CPHA_Msk = 0x1000000
	// Bit CPHA.
	SPI_CFG2_CPHA = 0x1000000
	// The first clock transition is the first data capture edge
	SPI_CFG2_CPHA_FirstEdge = 0x0
	// The second clock transition is the first data capture edge
	SPI_CFG2_CPHA_SecondEdge = 0x1
	// Position of LSBFRST field.
	SPI_CFG2_LSBFRST_Pos = 0x17
	// Bit mask of LSBFRST field.
	SPI_CFG2_LSBFRST_Msk = 0x800000
	// Bit LSBFRST.
	SPI_CFG2_LSBFRST = 0x800000
	// Data is transmitted/received with the MSB first
	SPI_CFG2_LSBFRST_MSBFirst = 0x0
	// Data is transmitted/received with the LSB first
	SPI_CFG2_LSBFRST_LSBFirst = 0x1
	// Position of MASTER field.
	SPI_CFG2_MASTER_Pos = 0x16
	// Bit mask of MASTER field.
	SPI_CFG2_MASTER_Msk = 0x400000
	// Bit MASTER.
	SPI_CFG2_MASTER = 0x400000
	// Slave configuration
	SPI_CFG2_MASTER_Slave = 0x0
	// Master configuration
	SPI_CFG2_MASTER_Master = 0x1
	// Position of SP field.
	SPI_CFG2_SP_Pos = 0x13
	// Bit mask of SP field.
	SPI_CFG2_SP_Msk = 0x380000
	// Motorola SPI protocol
	SPI_CFG2_SP_Motorola = 0x0
	// TI SPI protocol
	SPI_CFG2_SP_TI = 0x1
	// Position of COMM field.
	SPI_CFG2_COMM_Pos = 0x11
	// Bit mask of COMM field.
	SPI_CFG2_COMM_Msk = 0x60000
	// Full duplex
	SPI_CFG2_COMM_FullDuplex = 0x0
	// Simplex transmitter only
	SPI_CFG2_COMM_Transmitter = 0x1
	// Simplex receiver only
	SPI_CFG2_COMM_Receiver = 0x2
	// Half duplex
	SPI_CFG2_COMM_HalfDuplex = 0x3
	// Position of IOSWP field.
	SPI_CFG2_IOSWP_Pos = 0xf
	// Bit mask of IOSWP field.
	SPI_CFG2_IOSWP_Msk = 0x8000
	// Bit IOSWP.
	SPI_CFG2_IOSWP = 0x8000
	// MISO and MOSI not swapped
	SPI_CFG2_IOSWP_Disabled = 0x0
	// MISO and MOSI swapped
	SPI_CFG2_IOSWP_Enabled = 0x1
	// Position of RDIOP field.
	SPI_CFG2_RDIOP_Pos = 0xe
	// Bit mask of RDIOP field.
	SPI_CFG2_RDIOP_Msk = 0x4000
	// Bit RDIOP.
	SPI_CFG2_RDIOP = 0x4000
	// high level of the signal means the slave is ready for communication
	SPI_CFG2_RDIOP_High = 0x0
	// low level of the signal means the slave is ready for communication
	SPI_CFG2_RDIOP_Low = 0x1
	// Position of RDIOM field.
	SPI_CFG2_RDIOM_Pos = 0xd
	// Bit mask of RDIOM field.
	SPI_CFG2_RDIOM_Msk = 0x2000
	// Bit RDIOM.
	SPI_CFG2_RDIOM = 0x2000
	// RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)
	SPI_CFG2_RDIOM_Active = 0x0
	// RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect)
	SPI_CFG2_RDIOM_Pin = 0x1
	// Position of MIDI field.
	SPI_CFG2_MIDI_Pos = 0x4
	// Bit mask of MIDI field.
	SPI_CFG2_MIDI_Msk = 0xf0
	// Position of MSSI field.
	SPI_CFG2_MSSI_Pos = 0x0
	// Bit mask of MSSI field.
	SPI_CFG2_MSSI_Msk = 0xf

	// IER: Interrupt Enable Register
	// Position of RXPIE field.
	SPI_IER_RXPIE_Pos = 0x0
	// Bit mask of RXPIE field.
	SPI_IER_RXPIE_Msk = 0x1
	// Bit RXPIE.
	SPI_IER_RXPIE = 0x1
	// Interrupt disabled
	SPI_IER_RXPIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_RXPIE_Enabled = 0x1
	// Position of MODFIE field.
	SPI_IER_MODFIE_Pos = 0x9
	// Bit mask of MODFIE field.
	SPI_IER_MODFIE_Msk = 0x200
	// Bit MODFIE.
	SPI_IER_MODFIE = 0x200
	// Interrupt disabled
	SPI_IER_MODFIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_MODFIE_Enabled = 0x1
	// Position of TIFREIE field.
	SPI_IER_TIFREIE_Pos = 0x8
	// Bit mask of TIFREIE field.
	SPI_IER_TIFREIE_Msk = 0x100
	// Bit TIFREIE.
	SPI_IER_TIFREIE = 0x100
	// Interrupt disabled
	SPI_IER_TIFREIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_TIFREIE_Enabled = 0x1
	// Position of CRCEIE field.
	SPI_IER_CRCEIE_Pos = 0x7
	// Bit mask of CRCEIE field.
	SPI_IER_CRCEIE_Msk = 0x80
	// Bit CRCEIE.
	SPI_IER_CRCEIE = 0x80
	// Interrupt disabled
	SPI_IER_CRCEIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_CRCEIE_Enabled = 0x1
	// Position of OVRIE field.
	SPI_IER_OVRIE_Pos = 0x6
	// Bit mask of OVRIE field.
	SPI_IER_OVRIE_Msk = 0x40
	// Bit OVRIE.
	SPI_IER_OVRIE = 0x40
	// Interrupt disabled
	SPI_IER_OVRIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_OVRIE_Enabled = 0x1
	// Position of UDRIE field.
	SPI_IER_UDRIE_Pos = 0x5
	// Bit mask of UDRIE field.
	SPI_IER_UDRIE_Msk = 0x20
	// Bit UDRIE.
	SPI_IER_UDRIE = 0x20
	// Interrupt disabled
	SPI_IER_UDRIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_UDRIE_Enabled = 0x1
	// Position of TXTFIE field.
	SPI_IER_TXTFIE_Pos = 0x4
	// Bit mask of TXTFIE field.
	SPI_IER_TXTFIE_Msk = 0x10
	// Bit TXTFIE.
	SPI_IER_TXTFIE = 0x10
	// Interrupt disabled
	SPI_IER_TXTFIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_TXTFIE_Enabled = 0x1
	// Position of EOTIE field.
	SPI_IER_EOTIE_Pos = 0x3
	// Bit mask of EOTIE field.
	SPI_IER_EOTIE_Msk = 0x8
	// Bit EOTIE.
	SPI_IER_EOTIE = 0x8
	// Interrupt disabled
	SPI_IER_EOTIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_EOTIE_Enabled = 0x1
	// Position of DXPIE field.
	SPI_IER_DXPIE_Pos = 0x2
	// Bit mask of DXPIE field.
	SPI_IER_DXPIE_Msk = 0x4
	// Bit DXPIE.
	SPI_IER_DXPIE = 0x4
	// Interrupt disabled
	SPI_IER_DXPIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_DXPIE_Enabled = 0x1
	// Position of TXPIE field.
	SPI_IER_TXPIE_Pos = 0x1
	// Bit mask of TXPIE field.
	SPI_IER_TXPIE_Msk = 0x2
	// Bit TXPIE.
	SPI_IER_TXPIE = 0x2
	// Interrupt disabled
	SPI_IER_TXPIE_Disabled = 0x0
	// Interrupt enabled
	SPI_IER_TXPIE_Enabled = 0x1

	// SR: Status Register
	// Position of CTSIZE field.
	SPI_SR_CTSIZE_Pos = 0x10
	// Bit mask of CTSIZE field.
	SPI_SR_CTSIZE_Msk = 0xffff0000
	// Position of RXWNE field.
	SPI_SR_RXWNE_Pos = 0xf
	// Bit mask of RXWNE field.
	SPI_SR_RXWNE_Msk = 0x8000
	// Bit RXWNE.
	SPI_SR_RXWNE = 0x8000
	// Less than 32-bit data frame received
	SPI_SR_RXWNE_LessThan32 = 0x0
	// At least 32-bit data frame received
	SPI_SR_RXWNE_AtLeast32 = 0x1
	// Position of RXPLVL field.
	SPI_SR_RXPLVL_Pos = 0xd
	// Bit mask of RXPLVL field.
	SPI_SR_RXPLVL_Msk = 0x6000
	// Zero frames beyond packing ratio available
	SPI_SR_RXPLVL_ZeroFrames = 0x0
	// One frame beyond packing ratio available
	SPI_SR_RXPLVL_OneFrame = 0x1
	// Two frame beyond packing ratio available
	SPI_SR_RXPLVL_TwoFrames = 0x2
	// Three frame beyond packing ratio available
	SPI_SR_RXPLVL_ThreeFrames = 0x3
	// Position of TXC field.
	SPI_SR_TXC_Pos = 0xc
	// Bit mask of TXC field.
	SPI_SR_TXC_Msk = 0x1000
	// Bit TXC.
	SPI_SR_TXC = 0x1000
	// Transmission ongoing
	SPI_SR_TXC_Ongoing = 0x0
	// Transmission completed
	SPI_SR_TXC_Completed = 0x1
	// Position of SUSP field.
	SPI_SR_SUSP_Pos = 0xb
	// Bit mask of SUSP field.
	SPI_SR_SUSP_Msk = 0x800
	// Bit SUSP.
	SPI_SR_SUSP = 0x800
	// Master not suspended
	SPI_SR_SUSP_NotSuspended = 0x0
	// Master suspended
	SPI_SR_SUSP_Suspended = 0x1
	// Position of MODF field.
	SPI_SR_MODF_Pos = 0x9
	// Bit mask of MODF field.
	SPI_SR_MODF_Msk = 0x200
	// Bit MODF.
	SPI_SR_MODF = 0x200
	// No mode fault detected
	SPI_SR_MODF_NoFault = 0x0
	// Mode fault detected
	SPI_SR_MODF_Fault = 0x1
	// Position of TIFRE field.
	SPI_SR_TIFRE_Pos = 0x8
	// Bit mask of TIFRE field.
	SPI_SR_TIFRE_Msk = 0x100
	// Bit TIFRE.
	SPI_SR_TIFRE = 0x100
	// TI frame format error detected
	SPI_SR_TIFRE_NoError = 0x0
	// TI frame format error detected
	SPI_SR_TIFRE_Error = 0x1
	// Position of CRCE field.
	SPI_SR_CRCE_Pos = 0x7
	// Bit mask of CRCE field.
	SPI_SR_CRCE_Msk = 0x80
	// Bit CRCE.
	SPI_SR_CRCE = 0x80
	// No CRC error detected
	SPI_SR_CRCE_NoError = 0x0
	// CRC error detected
	SPI_SR_CRCE_Error = 0x1
	// Position of OVR field.
	SPI_SR_OVR_Pos = 0x6
	// Bit mask of OVR field.
	SPI_SR_OVR_Msk = 0x40
	// Bit OVR.
	SPI_SR_OVR = 0x40
	// No overrun occurred
	SPI_SR_OVR_NoOverrun = 0x0
	// Overrun occurred
	SPI_SR_OVR_Overrun = 0x1
	// Position of UDR field.
	SPI_SR_UDR_Pos = 0x5
	// Bit mask of UDR field.
	SPI_SR_UDR_Msk = 0x20
	// Bit UDR.
	SPI_SR_UDR = 0x20
	// No underrun occurred
	SPI_SR_UDR_NoUnderrun = 0x0
	// Underrun occurred
	SPI_SR_UDR_Underrun = 0x1
	// Position of TXTF field.
	SPI_SR_TXTF_Pos = 0x4
	// Bit mask of TXTF field.
	SPI_SR_TXTF_Msk = 0x10
	// Bit TXTF.
	SPI_SR_TXTF = 0x10
	// Transmission buffer incomplete
	SPI_SR_TXTF_NotCompleted = 0x0
	// Transmission buffer filled with at least one transfer
	SPI_SR_TXTF_Completed = 0x1
	// Position of EOT field.
	SPI_SR_EOT_Pos = 0x3
	// Bit mask of EOT field.
	SPI_SR_EOT_Msk = 0x8
	// Bit EOT.
	SPI_SR_EOT = 0x8
	// Transfer ongoing or not started
	SPI_SR_EOT_NotCompleted = 0x0
	// Transfer complete
	SPI_SR_EOT_Completed = 0x1
	// Position of DXP field.
	SPI_SR_DXP_Pos = 0x2
	// Bit mask of DXP field.
	SPI_SR_DXP_Msk = 0x4
	// Bit DXP.
	SPI_SR_DXP = 0x4
	// Duplex packet unavailable: no space for transmission and/or no data received
	SPI_SR_DXP_Unavailable = 0x0
	// Duplex packet available: space for transmission and data received
	SPI_SR_DXP_Available = 0x1
	// Position of TXP field.
	SPI_SR_TXP_Pos = 0x1
	// Bit mask of TXP field.
	SPI_SR_TXP_Msk = 0x2
	// Bit TXP.
	SPI_SR_TXP = 0x2
	// Tx buffer full
	SPI_SR_TXP_Full = 0x0
	// Tx buffer not full
	SPI_SR_TXP_NotFull = 0x1
	// Position of RXP field.
	SPI_SR_RXP_Pos = 0x0
	// Bit mask of RXP field.
	SPI_SR_RXP_Msk = 0x1
	// Bit RXP.
	SPI_SR_RXP = 0x1
	// Rx buffer empty
	SPI_SR_RXP_Empty = 0x0
	// Rx buffer not empty
	SPI_SR_RXP_NotEmpty = 0x1

	// IFCR: Interrupt/Status Flags Clear Register
	// Position of EOTC field.
	SPI_IFCR_EOTC_Pos = 0x3
	// Bit mask of EOTC field.
	SPI_IFCR_EOTC_Msk = 0x8
	// Bit EOTC.
	SPI_IFCR_EOTC = 0x8
	// Clear interrupt flag
	SPI_IFCR_EOTC_Clear = 0x1
	// Position of SUSPC field.
	SPI_IFCR_SUSPC_Pos = 0xb
	// Bit mask of SUSPC field.
	SPI_IFCR_SUSPC_Msk = 0x800
	// Bit SUSPC.
	SPI_IFCR_SUSPC = 0x800
	// Clear interrupt flag
	SPI_IFCR_SUSPC_Clear = 0x1
	// Position of MODFC field.
	SPI_IFCR_MODFC_Pos = 0x9
	// Bit mask of MODFC field.
	SPI_IFCR_MODFC_Msk = 0x200
	// Bit MODFC.
	SPI_IFCR_MODFC = 0x200
	// Clear interrupt flag
	SPI_IFCR_MODFC_Clear = 0x1
	// Position of TIFREC field.
	SPI_IFCR_TIFREC_Pos = 0x8
	// Bit mask of TIFREC field.
	SPI_IFCR_TIFREC_Msk = 0x100
	// Bit TIFREC.
	SPI_IFCR_TIFREC = 0x100
	// Clear interrupt flag
	SPI_IFCR_TIFREC_Clear = 0x1
	// Position of CRCEC field.
	SPI_IFCR_CRCEC_Pos = 0x7
	// Bit mask of CRCEC field.
	SPI_IFCR_CRCEC_Msk = 0x80
	// Bit CRCEC.
	SPI_IFCR_CRCEC = 0x80
	// Clear interrupt flag
	SPI_IFCR_CRCEC_Clear = 0x1
	// Position of OVRC field.
	SPI_IFCR_OVRC_Pos = 0x6
	// Bit mask of OVRC field.
	SPI_IFCR_OVRC_Msk = 0x40
	// Bit OVRC.
	SPI_IFCR_OVRC = 0x40
	// Clear interrupt flag
	SPI_IFCR_OVRC_Clear = 0x1
	// Position of UDRC field.
	SPI_IFCR_UDRC_Pos = 0x5
	// Bit mask of UDRC field.
	SPI_IFCR_UDRC_Msk = 0x20
	// Bit UDRC.
	SPI_IFCR_UDRC = 0x20
	// Clear interrupt flag
	SPI_IFCR_UDRC_Clear = 0x1
	// Position of TXTFC field.
	SPI_IFCR_TXTFC_Pos = 0x4
	// Bit mask of TXTFC field.
	SPI_IFCR_TXTFC_Msk = 0x10
	// Bit TXTFC.
	SPI_IFCR_TXTFC = 0x10
	// Clear interrupt flag
	SPI_IFCR_TXTFC_Clear = 0x1

	// AUTOCR: SPI autonomous mode control register
	// Position of TRIGEN field.
	SPI_AUTOCR_TRIGEN_Pos = 0x15
	// Bit mask of TRIGEN field.
	SPI_AUTOCR_TRIGEN_Msk = 0x200000
	// Bit TRIGEN.
	SPI_AUTOCR_TRIGEN = 0x200000
	// Hardware control disabled
	SPI_AUTOCR_TRIGEN_Disabled = 0x0
	// Hardware control enabled
	SPI_AUTOCR_TRIGEN_Enabled = 0x1
	// Position of TRIGPOL field.
	SPI_AUTOCR_TRIGPOL_Pos = 0x14
	// Bit mask of TRIGPOL field.
	SPI_AUTOCR_TRIGPOL_Msk = 0x100000
	// Bit TRIGPOL.
	SPI_AUTOCR_TRIGPOL = 0x100000
	// trigger is active on raising edge
	SPI_AUTOCR_TRIGPOL_RaisingEdge = 0x0
	// trigger is active on falling edge
	SPI_AUTOCR_TRIGPOL_FallingEdge = 0x1
	// Position of TRIGSEL field.
	SPI_AUTOCR_TRIGSEL_Pos = 0x10
	// Bit mask of TRIGSEL field.
	SPI_AUTOCR_TRIGSEL_Msk = 0xf0000

	// TXDR: Transmit Data Register
	// Position of TXDR field.
	SPI_TXDR_TXDR_Pos = 0x0
	// Bit mask of TXDR field.
	SPI_TXDR_TXDR_Msk = 0xffffffff

	// TXDR16: Direct 16-bit access to transmit data register
	// Position of TXDR field.
	SPI_TXDR16_TXDR_Pos = 0x0
	// Bit mask of TXDR field.
	SPI_TXDR16_TXDR_Msk = 0xffff

	// TXDR8: Direct 8-bit access to transmit data register
	// Position of TXDR field.
	SPI_TXDR8_TXDR_Pos = 0x0
	// Bit mask of TXDR field.
	SPI_TXDR8_TXDR_Msk = 0xff

	// RXDR: Receive Data Register
	// Position of RXDR field.
	SPI_RXDR_RXDR_Pos = 0x0
	// Bit mask of RXDR field.
	SPI_RXDR_RXDR_Msk = 0xffffffff

	// RXDR16: Direct 16-bit access to receive data register
	// Position of RXDR field.
	SPI_RXDR16_RXDR_Pos = 0x0
	// Bit mask of RXDR field.
	SPI_RXDR16_RXDR_Msk = 0xffff

	// RXDR8: Direct 8-bit access to receive data register
	// Position of RXDR field.
	SPI_RXDR8_RXDR_Pos = 0x0
	// Bit mask of RXDR field.
	SPI_RXDR8_RXDR_Msk = 0xff

	// CRCPOLY: Polynomial Register
	// Position of CRCPOLY field.
	SPI_CRCPOLY_CRCPOLY_Pos = 0x0
	// Bit mask of CRCPOLY field.
	SPI_CRCPOLY_CRCPOLY_Msk = 0xffffffff

	// TXCRC: Transmitter CRC Register
	// Position of TXCRC field.
	SPI_TXCRC_TXCRC_Pos = 0x0
	// Bit mask of TXCRC field.
	SPI_TXCRC_TXCRC_Msk = 0xffffffff

	// RXCRC: Receiver CRC Register
	// Position of RXCRC field.
	SPI_RXCRC_RXCRC_Pos = 0x0
	// Bit mask of RXCRC field.
	SPI_RXCRC_RXCRC_Msk = 0xffffffff

	// UDRDR: Underrun Data Register
	// Position of UDRDR field.
	SPI_UDRDR_UDRDR_Pos = 0x0
	// Bit mask of UDRDR field.
	SPI_UDRDR_UDRDR_Msk = 0xffffffff
)

// Constants for SYSCFG: System configuration controller
const (
	// SECCFGR: SYSCFG secure configuration register
	// Position of SYSCFGSEC field.
	SYSCFG_SECCFGR_SYSCFGSEC_Pos = 0x0
	// Bit mask of SYSCFGSEC field.
	SYSCFG_SECCFGR_SYSCFGSEC_Msk = 0x1
	// Bit SYSCFGSEC.
	SYSCFG_SECCFGR_SYSCFGSEC = 0x1
	// Position of CLASSBSEC field.
	SYSCFG_SECCFGR_CLASSBSEC_Pos = 0x1
	// Bit mask of CLASSBSEC field.
	SYSCFG_SECCFGR_CLASSBSEC_Msk = 0x2
	// Bit CLASSBSEC.
	SYSCFG_SECCFGR_CLASSBSEC = 0x2
	// Position of FPUSEC field.
	SYSCFG_SECCFGR_FPUSEC_Pos = 0x3
	// Bit mask of FPUSEC field.
	SYSCFG_SECCFGR_FPUSEC_Msk = 0x8
	// Bit FPUSEC.
	SYSCFG_SECCFGR_FPUSEC = 0x8

	// CFGR1: configuration register 1
	// Position of ENDCAP field.
	SYSCFG_CFGR1_ENDCAP_Pos = 0x18
	// Bit mask of ENDCAP field.
	SYSCFG_CFGR1_ENDCAP_Msk = 0x3000000
	// Position of PB9_FMP field.
	SYSCFG_CFGR1_PB9_FMP_Pos = 0x13
	// Bit mask of PB9_FMP field.
	SYSCFG_CFGR1_PB9_FMP_Msk = 0x80000
	// Bit PB9_FMP.
	SYSCFG_CFGR1_PB9_FMP = 0x80000
	// Position of PB8_FMP field.
	SYSCFG_CFGR1_PB8_FMP_Pos = 0x12
	// Bit mask of PB8_FMP field.
	SYSCFG_CFGR1_PB8_FMP_Msk = 0x40000
	// Bit PB8_FMP.
	SYSCFG_CFGR1_PB8_FMP = 0x40000
	// Position of PB7_FMP field.
	SYSCFG_CFGR1_PB7_FMP_Pos = 0x11
	// Bit mask of PB7_FMP field.
	SYSCFG_CFGR1_PB7_FMP_Msk = 0x20000
	// Bit PB7_FMP.
	SYSCFG_CFGR1_PB7_FMP = 0x20000
	// Position of PB6_FMP field.
	SYSCFG_CFGR1_PB6_FMP_Pos = 0x10
	// Bit mask of PB6_FMP field.
	SYSCFG_CFGR1_PB6_FMP_Msk = 0x10000
	// Bit PB6_FMP.
	SYSCFG_CFGR1_PB6_FMP = 0x10000
	// Position of ANASWVDD field.
	SYSCFG_CFGR1_ANASWVDD_Pos = 0x9
	// Bit mask of ANASWVDD field.
	SYSCFG_CFGR1_ANASWVDD_Msk = 0x200
	// Bit ANASWVDD.
	SYSCFG_CFGR1_ANASWVDD = 0x200
	// Position of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN_Pos = 0x8
	// Bit mask of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN_Msk = 0x100
	// Bit BOOSTEN.
	SYSCFG_CFGR1_BOOSTEN = 0x100

	// FPUIMR: FPU interrupt mask register
	// Position of FPU_IE field.
	SYSCFG_FPUIMR_FPU_IE_Pos = 0x0
	// Bit mask of FPU_IE field.
	SYSCFG_FPUIMR_FPU_IE_Msk = 0x3f

	// CNSLCKR: SYSCFG CPU non-secure lock register
	// Position of LOCKNSVTOR field.
	SYSCFG_CNSLCKR_LOCKNSVTOR_Pos = 0x0
	// Bit mask of LOCKNSVTOR field.
	SYSCFG_CNSLCKR_LOCKNSVTOR_Msk = 0x1
	// Bit LOCKNSVTOR.
	SYSCFG_CNSLCKR_LOCKNSVTOR = 0x1
	// Position of LOCKNSMPU field.
	SYSCFG_CNSLCKR_LOCKNSMPU_Pos = 0x1
	// Bit mask of LOCKNSMPU field.
	SYSCFG_CNSLCKR_LOCKNSMPU_Msk = 0x2
	// Bit LOCKNSMPU.
	SYSCFG_CNSLCKR_LOCKNSMPU = 0x2

	// CSLOCKR: SYSCFG CPU secure lock register
	// Position of LOCKSVTAIRCR field.
	SYSCFG_CSLOCKR_LOCKSVTAIRCR_Pos = 0x0
	// Bit mask of LOCKSVTAIRCR field.
	SYSCFG_CSLOCKR_LOCKSVTAIRCR_Msk = 0x1
	// Bit LOCKSVTAIRCR.
	SYSCFG_CSLOCKR_LOCKSVTAIRCR = 0x1
	// Position of LOCKSMPU field.
	SYSCFG_CSLOCKR_LOCKSMPU_Pos = 0x1
	// Bit mask of LOCKSMPU field.
	SYSCFG_CSLOCKR_LOCKSMPU_Msk = 0x2
	// Bit LOCKSMPU.
	SYSCFG_CSLOCKR_LOCKSMPU = 0x2
	// Position of LOCKSAU field.
	SYSCFG_CSLOCKR_LOCKSAU_Pos = 0x2
	// Bit mask of LOCKSAU field.
	SYSCFG_CSLOCKR_LOCKSAU_Msk = 0x4
	// Bit LOCKSAU.
	SYSCFG_CSLOCKR_LOCKSAU = 0x4

	// CFGR2: configuration register 2
	// Position of ECCL field.
	SYSCFG_CFGR2_ECCL_Pos = 0x3
	// Bit mask of ECCL field.
	SYSCFG_CFGR2_ECCL_Msk = 0x8
	// Bit ECCL.
	SYSCFG_CFGR2_ECCL = 0x8
	// Position of PVDL field.
	SYSCFG_CFGR2_PVDL_Pos = 0x2
	// Bit mask of PVDL field.
	SYSCFG_CFGR2_PVDL_Msk = 0x4
	// Bit PVDL.
	SYSCFG_CFGR2_PVDL = 0x4
	// Position of SPL field.
	SYSCFG_CFGR2_SPL_Pos = 0x1
	// Bit mask of SPL field.
	SYSCFG_CFGR2_SPL_Msk = 0x2
	// Bit SPL.
	SYSCFG_CFGR2_SPL = 0x2
	// Position of CLL field.
	SYSCFG_CFGR2_CLL_Pos = 0x0
	// Bit mask of CLL field.
	SYSCFG_CFGR2_CLL_Msk = 0x1
	// Bit CLL.
	SYSCFG_CFGR2_CLL = 0x1

	// MESR: memory erase status register
	// Position of IPMEE field.
	SYSCFG_MESR_IPMEE_Pos = 0x10
	// Bit mask of IPMEE field.
	SYSCFG_MESR_IPMEE_Msk = 0x10000
	// Bit IPMEE.
	SYSCFG_MESR_IPMEE = 0x10000
	// Position of MCLR field.
	SYSCFG_MESR_MCLR_Pos = 0x0
	// Bit mask of MCLR field.
	SYSCFG_MESR_MCLR_Msk = 0x1
	// Bit MCLR.
	SYSCFG_MESR_MCLR = 0x1

	// CCCSR: compensation cell control/status register
	// Position of EN1 field.
	SYSCFG_CCCSR_EN1_Pos = 0x0
	// Bit mask of EN1 field.
	SYSCFG_CCCSR_EN1_Msk = 0x1
	// Bit EN1.
	SYSCFG_CCCSR_EN1 = 0x1
	// Position of CS1 field.
	SYSCFG_CCCSR_CS1_Pos = 0x1
	// Bit mask of CS1 field.
	SYSCFG_CCCSR_CS1_Msk = 0x2
	// Bit CS1.
	SYSCFG_CCCSR_CS1 = 0x2
	// Position of EN2 field.
	SYSCFG_CCCSR_EN2_Pos = 0x2
	// Bit mask of EN2 field.
	SYSCFG_CCCSR_EN2_Msk = 0x4
	// Bit EN2.
	SYSCFG_CCCSR_EN2 = 0x4
	// Position of CS2 field.
	SYSCFG_CCCSR_CS2_Pos = 0x3
	// Bit mask of CS2 field.
	SYSCFG_CCCSR_CS2_Msk = 0x8
	// Bit CS2.
	SYSCFG_CCCSR_CS2 = 0x8
	// Position of EN3 field.
	SYSCFG_CCCSR_EN3_Pos = 0x4
	// Bit mask of EN3 field.
	SYSCFG_CCCSR_EN3_Msk = 0x10
	// Bit EN3.
	SYSCFG_CCCSR_EN3 = 0x10
	// Position of CS3 field.
	SYSCFG_CCCSR_CS3_Pos = 0x5
	// Bit mask of CS3 field.
	SYSCFG_CCCSR_CS3_Msk = 0x20
	// Bit CS3.
	SYSCFG_CCCSR_CS3 = 0x20
	// Position of RDY1 field.
	SYSCFG_CCCSR_RDY1_Pos = 0x8
	// Bit mask of RDY1 field.
	SYSCFG_CCCSR_RDY1_Msk = 0x100
	// Bit RDY1.
	SYSCFG_CCCSR_RDY1 = 0x100
	// Position of RDY2 field.
	SYSCFG_CCCSR_RDY2_Pos = 0x9
	// Bit mask of RDY2 field.
	SYSCFG_CCCSR_RDY2_Msk = 0x200
	// Bit RDY2.
	SYSCFG_CCCSR_RDY2 = 0x200
	// Position of RDY3 field.
	SYSCFG_CCCSR_RDY3_Pos = 0xa
	// Bit mask of RDY3 field.
	SYSCFG_CCCSR_RDY3_Msk = 0x400
	// Bit RDY3.
	SYSCFG_CCCSR_RDY3 = 0x400

	// CCVR: compensation cell value register
	// Position of NCV1 field.
	SYSCFG_CCVR_NCV1_Pos = 0x0
	// Bit mask of NCV1 field.
	SYSCFG_CCVR_NCV1_Msk = 0xf
	// Position of PCV1 field.
	SYSCFG_CCVR_PCV1_Pos = 0x4
	// Bit mask of PCV1 field.
	SYSCFG_CCVR_PCV1_Msk = 0xf0
	// Position of NCV2 field.
	SYSCFG_CCVR_NCV2_Pos = 0x8
	// Bit mask of NCV2 field.
	SYSCFG_CCVR_NCV2_Msk = 0xf00
	// Position of PCV2 field.
	SYSCFG_CCVR_PCV2_Pos = 0xc
	// Bit mask of PCV2 field.
	SYSCFG_CCVR_PCV2_Msk = 0xf000
	// Position of NCV3 field.
	SYSCFG_CCVR_NCV3_Pos = 0x10
	// Bit mask of NCV3 field.
	SYSCFG_CCVR_NCV3_Msk = 0xf0000
	// Position of PCV3 field.
	SYSCFG_CCVR_PCV3_Pos = 0x14
	// Bit mask of PCV3 field.
	SYSCFG_CCVR_PCV3_Msk = 0xf00000

	// CCCR: compensation cell code register
	// Position of NCC1 field.
	SYSCFG_CCCR_NCC1_Pos = 0x0
	// Bit mask of NCC1 field.
	SYSCFG_CCCR_NCC1_Msk = 0xf
	// Position of PCC1 field.
	SYSCFG_CCCR_PCC1_Pos = 0x4
	// Bit mask of PCC1 field.
	SYSCFG_CCCR_PCC1_Msk = 0xf0
	// Position of NCC2 field.
	SYSCFG_CCCR_NCC2_Pos = 0x8
	// Bit mask of NCC2 field.
	SYSCFG_CCCR_NCC2_Msk = 0xf00
	// Position of PCC2 field.
	SYSCFG_CCCR_PCC2_Pos = 0xc
	// Bit mask of PCC2 field.
	SYSCFG_CCCR_PCC2_Msk = 0xf000
	// Position of NCC3 field.
	SYSCFG_CCCR_NCC3_Pos = 0x10
	// Bit mask of NCC3 field.
	SYSCFG_CCCR_NCC3_Msk = 0xf0000
	// Position of PCC3 field.
	SYSCFG_CCCR_PCC3_Pos = 0x14
	// Bit mask of PCC3 field.
	SYSCFG_CCCR_PCC3_Msk = 0xf00000

	// RSSCMDR: RSS command register
	// Position of RSSCMD field.
	SYSCFG_RSSCMDR_RSSCMD_Pos = 0x0
	// Bit mask of RSSCMD field.
	SYSCFG_RSSCMDR_RSSCMD_Msk = 0xffff

	// OTGHSPHYCR: SYSCFG USB OTG_HS PHY register
	// Position of EN field.
	SYSCFG_OTGHSPHYCR_EN_Pos = 0x0
	// Bit mask of EN field.
	SYSCFG_OTGHSPHYCR_EN_Msk = 0x1
	// Bit EN.
	SYSCFG_OTGHSPHYCR_EN = 0x1
	// Position of PDCTRL field.
	SYSCFG_OTGHSPHYCR_PDCTRL_Pos = 0x1
	// Bit mask of PDCTRL field.
	SYSCFG_OTGHSPHYCR_PDCTRL_Msk = 0x2
	// Bit PDCTRL.
	SYSCFG_OTGHSPHYCR_PDCTRL = 0x2
	// Position of CLKSEL field.
	SYSCFG_OTGHSPHYCR_CLKSEL_Pos = 0x2
	// Bit mask of CLKSEL field.
	SYSCFG_OTGHSPHYCR_CLKSEL_Msk = 0x3c
)

// Constants for TAMP: Tamper and backup registers
const (
	// CR1: control register 1
	// Position of ITAMP13E field.
	TAMP_CR1_ITAMP13E_Pos = 0x1c
	// Bit mask of ITAMP13E field.
	TAMP_CR1_ITAMP13E_Msk = 0x10000000
	// Bit ITAMP13E.
	TAMP_CR1_ITAMP13E = 0x10000000
	// Position of ITAMP12E field.
	TAMP_CR1_ITAMP12E_Pos = 0x1b
	// Bit mask of ITAMP12E field.
	TAMP_CR1_ITAMP12E_Msk = 0x8000000
	// Bit ITAMP12E.
	TAMP_CR1_ITAMP12E = 0x8000000
	// Position of ITAMP11E field.
	TAMP_CR1_ITAMP11E_Pos = 0x1a
	// Bit mask of ITAMP11E field.
	TAMP_CR1_ITAMP11E_Msk = 0x4000000
	// Bit ITAMP11E.
	TAMP_CR1_ITAMP11E = 0x4000000
	// Position of ITAMP9E field.
	TAMP_CR1_ITAMP9E_Pos = 0x18
	// Bit mask of ITAMP9E field.
	TAMP_CR1_ITAMP9E_Msk = 0x1000000
	// Bit ITAMP9E.
	TAMP_CR1_ITAMP9E = 0x1000000
	// Position of ITAMP8E field.
	TAMP_CR1_ITAMP8E_Pos = 0x17
	// Bit mask of ITAMP8E field.
	TAMP_CR1_ITAMP8E_Msk = 0x800000
	// Bit ITAMP8E.
	TAMP_CR1_ITAMP8E = 0x800000
	// Position of ITAMP7E field.
	TAMP_CR1_ITAMP7E_Pos = 0x16
	// Bit mask of ITAMP7E field.
	TAMP_CR1_ITAMP7E_Msk = 0x400000
	// Bit ITAMP7E.
	TAMP_CR1_ITAMP7E = 0x400000
	// Position of ITAMP6E field.
	TAMP_CR1_ITAMP6E_Pos = 0x15
	// Bit mask of ITAMP6E field.
	TAMP_CR1_ITAMP6E_Msk = 0x200000
	// Bit ITAMP6E.
	TAMP_CR1_ITAMP6E = 0x200000
	// Position of ITAMP5E field.
	TAMP_CR1_ITAMP5E_Pos = 0x14
	// Bit mask of ITAMP5E field.
	TAMP_CR1_ITAMP5E_Msk = 0x100000
	// Bit ITAMP5E.
	TAMP_CR1_ITAMP5E = 0x100000
	// Position of ITAMP3E field.
	TAMP_CR1_ITAMP3E_Pos = 0x12
	// Bit mask of ITAMP3E field.
	TAMP_CR1_ITAMP3E_Msk = 0x40000
	// Bit ITAMP3E.
	TAMP_CR1_ITAMP3E = 0x40000
	// Position of ITAMP2E field.
	TAMP_CR1_ITAMP2E_Pos = 0x11
	// Bit mask of ITAMP2E field.
	TAMP_CR1_ITAMP2E_Msk = 0x20000
	// Bit ITAMP2E.
	TAMP_CR1_ITAMP2E = 0x20000
	// Position of ITAMP1E field.
	TAMP_CR1_ITAMP1E_Pos = 0x10
	// Bit mask of ITAMP1E field.
	TAMP_CR1_ITAMP1E_Msk = 0x10000
	// Bit ITAMP1E.
	TAMP_CR1_ITAMP1E = 0x10000
	// Position of TAMP8E field.
	TAMP_CR1_TAMP8E_Pos = 0x7
	// Bit mask of TAMP8E field.
	TAMP_CR1_TAMP8E_Msk = 0x80
	// Bit TAMP8E.
	TAMP_CR1_TAMP8E = 0x80
	// Position of TAMP7E field.
	TAMP_CR1_TAMP7E_Pos = 0x6
	// Bit mask of TAMP7E field.
	TAMP_CR1_TAMP7E_Msk = 0x40
	// Bit TAMP7E.
	TAMP_CR1_TAMP7E = 0x40
	// Position of TAMP6E field.
	TAMP_CR1_TAMP6E_Pos = 0x5
	// Bit mask of TAMP6E field.
	TAMP_CR1_TAMP6E_Msk = 0x20
	// Bit TAMP6E.
	TAMP_CR1_TAMP6E = 0x20
	// Position of TAMP5E field.
	TAMP_CR1_TAMP5E_Pos = 0x4
	// Bit mask of TAMP5E field.
	TAMP_CR1_TAMP5E_Msk = 0x10
	// Bit TAMP5E.
	TAMP_CR1_TAMP5E = 0x10
	// Position of TAMP4E field.
	TAMP_CR1_TAMP4E_Pos = 0x3
	// Bit mask of TAMP4E field.
	TAMP_CR1_TAMP4E_Msk = 0x8
	// Bit TAMP4E.
	TAMP_CR1_TAMP4E = 0x8
	// Position of TAMP3E field.
	TAMP_CR1_TAMP3E_Pos = 0x2
	// Bit mask of TAMP3E field.
	TAMP_CR1_TAMP3E_Msk = 0x4
	// Bit TAMP3E.
	TAMP_CR1_TAMP3E = 0x4
	// Position of TAMP2E field.
	TAMP_CR1_TAMP2E_Pos = 0x1
	// Bit mask of TAMP2E field.
	TAMP_CR1_TAMP2E_Msk = 0x2
	// Bit TAMP2E.
	TAMP_CR1_TAMP2E = 0x2
	// Position of TAMP1E field.
	TAMP_CR1_TAMP1E_Pos = 0x0
	// Bit mask of TAMP1E field.
	TAMP_CR1_TAMP1E_Msk = 0x1
	// Bit TAMP1E.
	TAMP_CR1_TAMP1E = 0x1

	// CR2: control register 2
	// Position of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER_Pos = 0x0
	// Bit mask of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER_Msk = 0x1
	// Bit TAMP1NOER.
	TAMP_CR2_TAMP1NOER = 0x1
	// Position of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER_Pos = 0x1
	// Bit mask of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER_Msk = 0x2
	// Bit TAMP2NOER.
	TAMP_CR2_TAMP2NOER = 0x2
	// Position of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER_Pos = 0x2
	// Bit mask of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER_Msk = 0x4
	// Bit TAMP3NOER.
	TAMP_CR2_TAMP3NOER = 0x4
	// Position of TAMP4NOER field.
	TAMP_CR2_TAMP4NOER_Pos = 0x3
	// Bit mask of TAMP4NOER field.
	TAMP_CR2_TAMP4NOER_Msk = 0x8
	// Bit TAMP4NOER.
	TAMP_CR2_TAMP4NOER = 0x8
	// Position of TAMP5NOER field.
	TAMP_CR2_TAMP5NOER_Pos = 0x4
	// Bit mask of TAMP5NOER field.
	TAMP_CR2_TAMP5NOER_Msk = 0x10
	// Bit TAMP5NOER.
	TAMP_CR2_TAMP5NOER = 0x10
	// Position of TAMP6NOER field.
	TAMP_CR2_TAMP6NOER_Pos = 0x5
	// Bit mask of TAMP6NOER field.
	TAMP_CR2_TAMP6NOER_Msk = 0x20
	// Bit TAMP6NOER.
	TAMP_CR2_TAMP6NOER = 0x20
	// Position of TAMP7NOER field.
	TAMP_CR2_TAMP7NOER_Pos = 0x6
	// Bit mask of TAMP7NOER field.
	TAMP_CR2_TAMP7NOER_Msk = 0x40
	// Bit TAMP7NOER.
	TAMP_CR2_TAMP7NOER = 0x40
	// Position of TAMP8NOER field.
	TAMP_CR2_TAMP8NOER_Pos = 0x7
	// Bit mask of TAMP8NOER field.
	TAMP_CR2_TAMP8NOER_Msk = 0x80
	// Bit TAMP8NOER.
	TAMP_CR2_TAMP8NOER = 0x80
	// Position of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK_Pos = 0x10
	// Bit mask of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK_Msk = 0x10000
	// Bit TAMP1MSK.
	TAMP_CR2_TAMP1MSK = 0x10000
	// Position of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK_Pos = 0x11
	// Bit mask of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK_Msk = 0x20000
	// Bit TAMP2MSK.
	TAMP_CR2_TAMP2MSK = 0x20000
	// Position of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK_Pos = 0x12
	// Bit mask of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK_Msk = 0x40000
	// Bit TAMP3MSK.
	TAMP_CR2_TAMP3MSK = 0x40000
	// Position of BKBLOCK field.
	TAMP_CR2_BKBLOCK_Pos = 0x16
	// Bit mask of BKBLOCK field.
	TAMP_CR2_BKBLOCK_Msk = 0x400000
	// Bit BKBLOCK.
	TAMP_CR2_BKBLOCK = 0x400000
	// Position of BKERASE field.
	TAMP_CR2_BKERASE_Pos = 0x17
	// Bit mask of BKERASE field.
	TAMP_CR2_BKERASE_Msk = 0x800000
	// Bit BKERASE.
	TAMP_CR2_BKERASE = 0x800000
	// Position of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG_Pos = 0x18
	// Bit mask of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG_Msk = 0x1000000
	// Bit TAMP1TRG.
	TAMP_CR2_TAMP1TRG = 0x1000000
	// Position of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG_Pos = 0x19
	// Bit mask of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG_Msk = 0x2000000
	// Bit TAMP2TRG.
	TAMP_CR2_TAMP2TRG = 0x2000000
	// Position of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG_Pos = 0x1a
	// Bit mask of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG_Msk = 0x4000000
	// Bit TAMP3TRG.
	TAMP_CR2_TAMP3TRG = 0x4000000
	// Position of TAMP4TRG field.
	TAMP_CR2_TAMP4TRG_Pos = 0x1b
	// Bit mask of TAMP4TRG field.
	TAMP_CR2_TAMP4TRG_Msk = 0x8000000
	// Bit TAMP4TRG.
	TAMP_CR2_TAMP4TRG = 0x8000000
	// Position of TAMP5TRG field.
	TAMP_CR2_TAMP5TRG_Pos = 0x1c
	// Bit mask of TAMP5TRG field.
	TAMP_CR2_TAMP5TRG_Msk = 0x10000000
	// Bit TAMP5TRG.
	TAMP_CR2_TAMP5TRG = 0x10000000
	// Position of TAMP6TRG field.
	TAMP_CR2_TAMP6TRG_Pos = 0x1d
	// Bit mask of TAMP6TRG field.
	TAMP_CR2_TAMP6TRG_Msk = 0x20000000
	// Bit TAMP6TRG.
	TAMP_CR2_TAMP6TRG = 0x20000000
	// Position of TAMP7TRG field.
	TAMP_CR2_TAMP7TRG_Pos = 0x1e
	// Bit mask of TAMP7TRG field.
	TAMP_CR2_TAMP7TRG_Msk = 0x40000000
	// Bit TAMP7TRG.
	TAMP_CR2_TAMP7TRG = 0x40000000
	// Position of TAMP8TRG field.
	TAMP_CR2_TAMP8TRG_Pos = 0x1f
	// Bit mask of TAMP8TRG field.
	TAMP_CR2_TAMP8TRG_Msk = 0x80000000
	// Bit TAMP8TRG.
	TAMP_CR2_TAMP8TRG = 0x80000000

	// CR3: control register 3
	// Position of ITAMP1NOER field.
	TAMP_CR3_ITAMP1NOER_Pos = 0x0
	// Bit mask of ITAMP1NOER field.
	TAMP_CR3_ITAMP1NOER_Msk = 0x1
	// Bit ITAMP1NOER.
	TAMP_CR3_ITAMP1NOER = 0x1
	// Position of ITAMP2NOER field.
	TAMP_CR3_ITAMP2NOER_Pos = 0x1
	// Bit mask of ITAMP2NOER field.
	TAMP_CR3_ITAMP2NOER_Msk = 0x2
	// Bit ITAMP2NOER.
	TAMP_CR3_ITAMP2NOER = 0x2
	// Position of ITAMP3NOER field.
	TAMP_CR3_ITAMP3NOER_Pos = 0x2
	// Bit mask of ITAMP3NOER field.
	TAMP_CR3_ITAMP3NOER_Msk = 0x4
	// Bit ITAMP3NOER.
	TAMP_CR3_ITAMP3NOER = 0x4
	// Position of TAMP5NOER field.
	TAMP_CR3_TAMP5NOER_Pos = 0x4
	// Bit mask of TAMP5NOER field.
	TAMP_CR3_TAMP5NOER_Msk = 0x10
	// Bit TAMP5NOER.
	TAMP_CR3_TAMP5NOER = 0x10
	// Position of TAMP6NOER field.
	TAMP_CR3_TAMP6NOER_Pos = 0x5
	// Bit mask of TAMP6NOER field.
	TAMP_CR3_TAMP6NOER_Msk = 0x20
	// Bit TAMP6NOER.
	TAMP_CR3_TAMP6NOER = 0x20
	// Position of TAMP7NOER field.
	TAMP_CR3_TAMP7NOER_Pos = 0x6
	// Bit mask of TAMP7NOER field.
	TAMP_CR3_TAMP7NOER_Msk = 0x40
	// Bit TAMP7NOER.
	TAMP_CR3_TAMP7NOER = 0x40
	// Position of TAMP8NOER field.
	TAMP_CR3_TAMP8NOER_Pos = 0x7
	// Bit mask of TAMP8NOER field.
	TAMP_CR3_TAMP8NOER_Msk = 0x80
	// Bit TAMP8NOER.
	TAMP_CR3_TAMP8NOER = 0x80
	// Position of ITAMP9NOER field.
	TAMP_CR3_ITAMP9NOER_Pos = 0x8
	// Bit mask of ITAMP9NOER field.
	TAMP_CR3_ITAMP9NOER_Msk = 0x100
	// Bit ITAMP9NOER.
	TAMP_CR3_ITAMP9NOER = 0x100
	// Position of ITAMP11NOER field.
	TAMP_CR3_ITAMP11NOER_Pos = 0xa
	// Bit mask of ITAMP11NOER field.
	TAMP_CR3_ITAMP11NOER_Msk = 0x400
	// Bit ITAMP11NOER.
	TAMP_CR3_ITAMP11NOER = 0x400
	// Position of ITAMP12NOER field.
	TAMP_CR3_ITAMP12NOER_Pos = 0xb
	// Bit mask of ITAMP12NOER field.
	TAMP_CR3_ITAMP12NOER_Msk = 0x800
	// Bit ITAMP12NOER.
	TAMP_CR3_ITAMP12NOER = 0x800
	// Position of ITAMP13NOER field.
	TAMP_CR3_ITAMP13NOER_Pos = 0xc
	// Bit mask of ITAMP13NOER field.
	TAMP_CR3_ITAMP13NOER_Msk = 0x1000
	// Bit ITAMP13NOER.
	TAMP_CR3_ITAMP13NOER = 0x1000

	// FLTCR: TAMP filter control register
	// Position of TAMPFREQ field.
	TAMP_FLTCR_TAMPFREQ_Pos = 0x0
	// Bit mask of TAMPFREQ field.
	TAMP_FLTCR_TAMPFREQ_Msk = 0x7
	// Position of TAMPFLT field.
	TAMP_FLTCR_TAMPFLT_Pos = 0x3
	// Bit mask of TAMPFLT field.
	TAMP_FLTCR_TAMPFLT_Msk = 0x18
	// Position of TAMPPRCH field.
	TAMP_FLTCR_TAMPPRCH_Pos = 0x5
	// Bit mask of TAMPPRCH field.
	TAMP_FLTCR_TAMPPRCH_Msk = 0x60
	// Position of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS_Pos = 0x7
	// Bit mask of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS_Msk = 0x80
	// Bit TAMPPUDIS.
	TAMP_FLTCR_TAMPPUDIS = 0x80

	// ATCR1: TAMP active tamper control register
	// Position of TAMP1AM field.
	TAMP_ATCR1_TAMP1AM_Pos = 0x0
	// Bit mask of TAMP1AM field.
	TAMP_ATCR1_TAMP1AM_Msk = 0x1
	// Bit TAMP1AM.
	TAMP_ATCR1_TAMP1AM = 0x1
	// Position of TAMP2AM field.
	TAMP_ATCR1_TAMP2AM_Pos = 0x1
	// Bit mask of TAMP2AM field.
	TAMP_ATCR1_TAMP2AM_Msk = 0x2
	// Bit TAMP2AM.
	TAMP_ATCR1_TAMP2AM = 0x2
	// Position of TAMP3AM field.
	TAMP_ATCR1_TAMP3AM_Pos = 0x2
	// Bit mask of TAMP3AM field.
	TAMP_ATCR1_TAMP3AM_Msk = 0x4
	// Bit TAMP3AM.
	TAMP_ATCR1_TAMP3AM = 0x4
	// Position of TAMP4AM field.
	TAMP_ATCR1_TAMP4AM_Pos = 0x3
	// Bit mask of TAMP4AM field.
	TAMP_ATCR1_TAMP4AM_Msk = 0x8
	// Bit TAMP4AM.
	TAMP_ATCR1_TAMP4AM = 0x8
	// Position of TAMP5AM field.
	TAMP_ATCR1_TAMP5AM_Pos = 0x4
	// Bit mask of TAMP5AM field.
	TAMP_ATCR1_TAMP5AM_Msk = 0x10
	// Bit TAMP5AM.
	TAMP_ATCR1_TAMP5AM = 0x10
	// Position of TAMP6AM field.
	TAMP_ATCR1_TAMP6AM_Pos = 0x5
	// Bit mask of TAMP6AM field.
	TAMP_ATCR1_TAMP6AM_Msk = 0x20
	// Bit TAMP6AM.
	TAMP_ATCR1_TAMP6AM = 0x20
	// Position of TAMP7AM field.
	TAMP_ATCR1_TAMP7AM_Pos = 0x6
	// Bit mask of TAMP7AM field.
	TAMP_ATCR1_TAMP7AM_Msk = 0x40
	// Bit TAMP7AM.
	TAMP_ATCR1_TAMP7AM = 0x40
	// Position of TAMP8AM field.
	TAMP_ATCR1_TAMP8AM_Pos = 0x7
	// Bit mask of TAMP8AM field.
	TAMP_ATCR1_TAMP8AM_Msk = 0x80
	// Bit TAMP8AM.
	TAMP_ATCR1_TAMP8AM = 0x80
	// Position of ATOSEL1 field.
	TAMP_ATCR1_ATOSEL1_Pos = 0x8
	// Bit mask of ATOSEL1 field.
	TAMP_ATCR1_ATOSEL1_Msk = 0x300
	// Position of ATOSEL2 field.
	TAMP_ATCR1_ATOSEL2_Pos = 0xa
	// Bit mask of ATOSEL2 field.
	TAMP_ATCR1_ATOSEL2_Msk = 0xc00
	// Position of ATOSEL3 field.
	TAMP_ATCR1_ATOSEL3_Pos = 0xc
	// Bit mask of ATOSEL3 field.
	TAMP_ATCR1_ATOSEL3_Msk = 0x3000
	// Position of ATOSEL4 field.
	TAMP_ATCR1_ATOSEL4_Pos = 0xe
	// Bit mask of ATOSEL4 field.
	TAMP_ATCR1_ATOSEL4_Msk = 0xc000
	// Position of ATCKSEL field.
	TAMP_ATCR1_ATCKSEL_Pos = 0x10
	// Bit mask of ATCKSEL field.
	TAMP_ATCR1_ATCKSEL_Msk = 0x70000
	// Position of ATPER field.
	TAMP_ATCR1_ATPER_Pos = 0x18
	// Bit mask of ATPER field.
	TAMP_ATCR1_ATPER_Msk = 0x7000000
	// Position of ATOSHARE field.
	TAMP_ATCR1_ATOSHARE_Pos = 0x1e
	// Bit mask of ATOSHARE field.
	TAMP_ATCR1_ATOSHARE_Msk = 0x40000000
	// Bit ATOSHARE.
	TAMP_ATCR1_ATOSHARE = 0x40000000
	// Position of FLTEN field.
	TAMP_ATCR1_FLTEN_Pos = 0x1f
	// Bit mask of FLTEN field.
	TAMP_ATCR1_FLTEN_Msk = 0x80000000
	// Bit FLTEN.
	TAMP_ATCR1_FLTEN = 0x80000000

	// ATSEEDR: TAMP active tamper seed register
	// Position of SEED field.
	TAMP_ATSEEDR_SEED_Pos = 0x0
	// Bit mask of SEED field.
	TAMP_ATSEEDR_SEED_Msk = 0xffffffff

	// ATOR: TAMP active tamper output register
	// Position of PRNG field.
	TAMP_ATOR_PRNG_Pos = 0x0
	// Bit mask of PRNG field.
	TAMP_ATOR_PRNG_Msk = 0xff
	// Position of SEEDF field.
	TAMP_ATOR_SEEDF_Pos = 0xe
	// Bit mask of SEEDF field.
	TAMP_ATOR_SEEDF_Msk = 0x4000
	// Bit SEEDF.
	TAMP_ATOR_SEEDF = 0x4000
	// Position of INITS field.
	TAMP_ATOR_INITS_Pos = 0xf
	// Bit mask of INITS field.
	TAMP_ATOR_INITS_Msk = 0x8000
	// Bit INITS.
	TAMP_ATOR_INITS = 0x8000

	// ATCR2: TAMP active tamper control register 2
	// Position of ATOSEL1 field.
	TAMP_ATCR2_ATOSEL1_Pos = 0x8
	// Bit mask of ATOSEL1 field.
	TAMP_ATCR2_ATOSEL1_Msk = 0x700
	// Position of ATOSEL2 field.
	TAMP_ATCR2_ATOSEL2_Pos = 0xb
	// Bit mask of ATOSEL2 field.
	TAMP_ATCR2_ATOSEL2_Msk = 0x3800
	// Position of ATOSEL3 field.
	TAMP_ATCR2_ATOSEL3_Pos = 0xe
	// Bit mask of ATOSEL3 field.
	TAMP_ATCR2_ATOSEL3_Msk = 0x1c000
	// Position of ATOSEL4 field.
	TAMP_ATCR2_ATOSEL4_Pos = 0x11
	// Bit mask of ATOSEL4 field.
	TAMP_ATCR2_ATOSEL4_Msk = 0x60000
	// Position of ATOSEL5 field.
	TAMP_ATCR2_ATOSEL5_Pos = 0x14
	// Bit mask of ATOSEL5 field.
	TAMP_ATCR2_ATOSEL5_Msk = 0x700000
	// Position of ATOSEL6 field.
	TAMP_ATCR2_ATOSEL6_Pos = 0x17
	// Bit mask of ATOSEL6 field.
	TAMP_ATCR2_ATOSEL6_Msk = 0x3800000
	// Position of ATOSEL7 field.
	TAMP_ATCR2_ATOSEL7_Pos = 0x1a
	// Bit mask of ATOSEL7 field.
	TAMP_ATCR2_ATOSEL7_Msk = 0x1c000000
	// Position of ATOSEL8 field.
	TAMP_ATCR2_ATOSEL8_Pos = 0x1d
	// Bit mask of ATOSEL8 field.
	TAMP_ATCR2_ATOSEL8_Msk = 0xe0000000

	// SECCFGR: TAMP secure mode register
	// Position of BKPRWSEC field.
	TAMP_SECCFGR_BKPRWSEC_Pos = 0x0
	// Bit mask of BKPRWSEC field.
	TAMP_SECCFGR_BKPRWSEC_Msk = 0xff
	// Position of CNT1SEC field.
	TAMP_SECCFGR_CNT1SEC_Pos = 0xf
	// Bit mask of CNT1SEC field.
	TAMP_SECCFGR_CNT1SEC_Msk = 0x8000
	// Bit CNT1SEC.
	TAMP_SECCFGR_CNT1SEC = 0x8000
	// Position of BKPWSEC field.
	TAMP_SECCFGR_BKPWSEC_Pos = 0x10
	// Bit mask of BKPWSEC field.
	TAMP_SECCFGR_BKPWSEC_Msk = 0xff0000
	// Position of BHKLOCK field.
	TAMP_SECCFGR_BHKLOCK_Pos = 0x1e
	// Bit mask of BHKLOCK field.
	TAMP_SECCFGR_BHKLOCK_Msk = 0x40000000
	// Bit BHKLOCK.
	TAMP_SECCFGR_BHKLOCK = 0x40000000
	// Position of TAMPSEC field.
	TAMP_SECCFGR_TAMPSEC_Pos = 0x1f
	// Bit mask of TAMPSEC field.
	TAMP_SECCFGR_TAMPSEC_Msk = 0x80000000
	// Bit TAMPSEC.
	TAMP_SECCFGR_TAMPSEC = 0x80000000

	// PRIVCR: TAMP privilege mode control register
	// Position of CNT1PRIV field.
	TAMP_PRIVCR_CNT1PRIV_Pos = 0xf
	// Bit mask of CNT1PRIV field.
	TAMP_PRIVCR_CNT1PRIV_Msk = 0x8000
	// Bit CNT1PRIV.
	TAMP_PRIVCR_CNT1PRIV = 0x8000
	// Position of BKPRWPRIV field.
	TAMP_PRIVCR_BKPRWPRIV_Pos = 0x1d
	// Bit mask of BKPRWPRIV field.
	TAMP_PRIVCR_BKPRWPRIV_Msk = 0x20000000
	// Bit BKPRWPRIV.
	TAMP_PRIVCR_BKPRWPRIV = 0x20000000
	// Position of BKPWPRIV field.
	TAMP_PRIVCR_BKPWPRIV_Pos = 0x1e
	// Bit mask of BKPWPRIV field.
	TAMP_PRIVCR_BKPWPRIV_Msk = 0x40000000
	// Bit BKPWPRIV.
	TAMP_PRIVCR_BKPWPRIV = 0x40000000
	// Position of TAMPPRIV field.
	TAMP_PRIVCR_TAMPPRIV_Pos = 0x1f
	// Bit mask of TAMPPRIV field.
	TAMP_PRIVCR_TAMPPRIV_Msk = 0x80000000
	// Bit TAMPPRIV.
	TAMP_PRIVCR_TAMPPRIV = 0x80000000

	// IER: TAMP interrupt enable register
	// Position of TAMP1IE field.
	TAMP_IER_TAMP1IE_Pos = 0x0
	// Bit mask of TAMP1IE field.
	TAMP_IER_TAMP1IE_Msk = 0x1
	// Bit TAMP1IE.
	TAMP_IER_TAMP1IE = 0x1
	// Position of TAMP2IE field.
	TAMP_IER_TAMP2IE_Pos = 0x1
	// Bit mask of TAMP2IE field.
	TAMP_IER_TAMP2IE_Msk = 0x2
	// Bit TAMP2IE.
	TAMP_IER_TAMP2IE = 0x2
	// Position of TAMP3IE field.
	TAMP_IER_TAMP3IE_Pos = 0x2
	// Bit mask of TAMP3IE field.
	TAMP_IER_TAMP3IE_Msk = 0x4
	// Bit TAMP3IE.
	TAMP_IER_TAMP3IE = 0x4
	// Position of TAMP4IE field.
	TAMP_IER_TAMP4IE_Pos = 0x3
	// Bit mask of TAMP4IE field.
	TAMP_IER_TAMP4IE_Msk = 0x8
	// Bit TAMP4IE.
	TAMP_IER_TAMP4IE = 0x8
	// Position of TAMP5IE field.
	TAMP_IER_TAMP5IE_Pos = 0x4
	// Bit mask of TAMP5IE field.
	TAMP_IER_TAMP5IE_Msk = 0x10
	// Bit TAMP5IE.
	TAMP_IER_TAMP5IE = 0x10
	// Position of TAMP6IE field.
	TAMP_IER_TAMP6IE_Pos = 0x5
	// Bit mask of TAMP6IE field.
	TAMP_IER_TAMP6IE_Msk = 0x20
	// Bit TAMP6IE.
	TAMP_IER_TAMP6IE = 0x20
	// Position of TAMP7IE field.
	TAMP_IER_TAMP7IE_Pos = 0x6
	// Bit mask of TAMP7IE field.
	TAMP_IER_TAMP7IE_Msk = 0x40
	// Bit TAMP7IE.
	TAMP_IER_TAMP7IE = 0x40
	// Position of TAMP8IE field.
	TAMP_IER_TAMP8IE_Pos = 0x7
	// Bit mask of TAMP8IE field.
	TAMP_IER_TAMP8IE_Msk = 0x80
	// Bit TAMP8IE.
	TAMP_IER_TAMP8IE = 0x80
	// Position of ITAMP1IE field.
	TAMP_IER_ITAMP1IE_Pos = 0x10
	// Bit mask of ITAMP1IE field.
	TAMP_IER_ITAMP1IE_Msk = 0x10000
	// Bit ITAMP1IE.
	TAMP_IER_ITAMP1IE = 0x10000
	// Position of ITAMP2IE field.
	TAMP_IER_ITAMP2IE_Pos = 0x11
	// Bit mask of ITAMP2IE field.
	TAMP_IER_ITAMP2IE_Msk = 0x20000
	// Bit ITAMP2IE.
	TAMP_IER_ITAMP2IE = 0x20000
	// Position of ITAMP3IE field.
	TAMP_IER_ITAMP3IE_Pos = 0x12
	// Bit mask of ITAMP3IE field.
	TAMP_IER_ITAMP3IE_Msk = 0x40000
	// Bit ITAMP3IE.
	TAMP_IER_ITAMP3IE = 0x40000
	// Position of ITAMP5IE field.
	TAMP_IER_ITAMP5IE_Pos = 0x14
	// Bit mask of ITAMP5IE field.
	TAMP_IER_ITAMP5IE_Msk = 0x100000
	// Bit ITAMP5IE.
	TAMP_IER_ITAMP5IE = 0x100000
	// Position of ITAMP6IE field.
	TAMP_IER_ITAMP6IE_Pos = 0x15
	// Bit mask of ITAMP6IE field.
	TAMP_IER_ITAMP6IE_Msk = 0x200000
	// Bit ITAMP6IE.
	TAMP_IER_ITAMP6IE = 0x200000
	// Position of ITAMP7IE field.
	TAMP_IER_ITAMP7IE_Pos = 0x16
	// Bit mask of ITAMP7IE field.
	TAMP_IER_ITAMP7IE_Msk = 0x400000
	// Bit ITAMP7IE.
	TAMP_IER_ITAMP7IE = 0x400000
	// Position of ITAMP8IE field.
	TAMP_IER_ITAMP8IE_Pos = 0x17
	// Bit mask of ITAMP8IE field.
	TAMP_IER_ITAMP8IE_Msk = 0x800000
	// Bit ITAMP8IE.
	TAMP_IER_ITAMP8IE = 0x800000
	// Position of ITAMP9IE field.
	TAMP_IER_ITAMP9IE_Pos = 0x18
	// Bit mask of ITAMP9IE field.
	TAMP_IER_ITAMP9IE_Msk = 0x1000000
	// Bit ITAMP9IE.
	TAMP_IER_ITAMP9IE = 0x1000000
	// Position of ITAMP11IE field.
	TAMP_IER_ITAMP11IE_Pos = 0x1a
	// Bit mask of ITAMP11IE field.
	TAMP_IER_ITAMP11IE_Msk = 0x4000000
	// Bit ITAMP11IE.
	TAMP_IER_ITAMP11IE = 0x4000000
	// Position of ITAMP12IE field.
	TAMP_IER_ITAMP12IE_Pos = 0x1b
	// Bit mask of ITAMP12IE field.
	TAMP_IER_ITAMP12IE_Msk = 0x8000000
	// Bit ITAMP12IE.
	TAMP_IER_ITAMP12IE = 0x8000000
	// Position of ITAMP13IE field.
	TAMP_IER_ITAMP13IE_Pos = 0x1c
	// Bit mask of ITAMP13IE field.
	TAMP_IER_ITAMP13IE_Msk = 0x10000000
	// Bit ITAMP13IE.
	TAMP_IER_ITAMP13IE = 0x10000000

	// SR: TAMP status register
	// Position of TAMP1F field.
	TAMP_SR_TAMP1F_Pos = 0x0
	// Bit mask of TAMP1F field.
	TAMP_SR_TAMP1F_Msk = 0x1
	// Bit TAMP1F.
	TAMP_SR_TAMP1F = 0x1
	// Position of TAMP2F field.
	TAMP_SR_TAMP2F_Pos = 0x1
	// Bit mask of TAMP2F field.
	TAMP_SR_TAMP2F_Msk = 0x2
	// Bit TAMP2F.
	TAMP_SR_TAMP2F = 0x2
	// Position of TAMP3F field.
	TAMP_SR_TAMP3F_Pos = 0x2
	// Bit mask of TAMP3F field.
	TAMP_SR_TAMP3F_Msk = 0x4
	// Bit TAMP3F.
	TAMP_SR_TAMP3F = 0x4
	// Position of TAMP4F field.
	TAMP_SR_TAMP4F_Pos = 0x3
	// Bit mask of TAMP4F field.
	TAMP_SR_TAMP4F_Msk = 0x8
	// Bit TAMP4F.
	TAMP_SR_TAMP4F = 0x8
	// Position of TAMP5F field.
	TAMP_SR_TAMP5F_Pos = 0x4
	// Bit mask of TAMP5F field.
	TAMP_SR_TAMP5F_Msk = 0x10
	// Bit TAMP5F.
	TAMP_SR_TAMP5F = 0x10
	// Position of TAMP6F field.
	TAMP_SR_TAMP6F_Pos = 0x5
	// Bit mask of TAMP6F field.
	TAMP_SR_TAMP6F_Msk = 0x20
	// Bit TAMP6F.
	TAMP_SR_TAMP6F = 0x20
	// Position of TAMP7F field.
	TAMP_SR_TAMP7F_Pos = 0x6
	// Bit mask of TAMP7F field.
	TAMP_SR_TAMP7F_Msk = 0x40
	// Bit TAMP7F.
	TAMP_SR_TAMP7F = 0x40
	// Position of TAMP8F field.
	TAMP_SR_TAMP8F_Pos = 0x7
	// Bit mask of TAMP8F field.
	TAMP_SR_TAMP8F_Msk = 0x80
	// Bit TAMP8F.
	TAMP_SR_TAMP8F = 0x80
	// Position of CITAMP1F field.
	TAMP_SR_CITAMP1F_Pos = 0x10
	// Bit mask of CITAMP1F field.
	TAMP_SR_CITAMP1F_Msk = 0x10000
	// Bit CITAMP1F.
	TAMP_SR_CITAMP1F = 0x10000
	// Position of CITAMP2F field.
	TAMP_SR_CITAMP2F_Pos = 0x11
	// Bit mask of CITAMP2F field.
	TAMP_SR_CITAMP2F_Msk = 0x20000
	// Bit CITAMP2F.
	TAMP_SR_CITAMP2F = 0x20000
	// Position of ITAMP3F field.
	TAMP_SR_ITAMP3F_Pos = 0x12
	// Bit mask of ITAMP3F field.
	TAMP_SR_ITAMP3F_Msk = 0x40000
	// Bit ITAMP3F.
	TAMP_SR_ITAMP3F = 0x40000
	// Position of ITAMP5F field.
	TAMP_SR_ITAMP5F_Pos = 0x14
	// Bit mask of ITAMP5F field.
	TAMP_SR_ITAMP5F_Msk = 0x100000
	// Bit ITAMP5F.
	TAMP_SR_ITAMP5F = 0x100000
	// Position of ITAMP6F field.
	TAMP_SR_ITAMP6F_Pos = 0x15
	// Bit mask of ITAMP6F field.
	TAMP_SR_ITAMP6F_Msk = 0x200000
	// Bit ITAMP6F.
	TAMP_SR_ITAMP6F = 0x200000
	// Position of ITAMP7F field.
	TAMP_SR_ITAMP7F_Pos = 0x16
	// Bit mask of ITAMP7F field.
	TAMP_SR_ITAMP7F_Msk = 0x400000
	// Bit ITAMP7F.
	TAMP_SR_ITAMP7F = 0x400000
	// Position of ITAMP8F field.
	TAMP_SR_ITAMP8F_Pos = 0x17
	// Bit mask of ITAMP8F field.
	TAMP_SR_ITAMP8F_Msk = 0x800000
	// Bit ITAMP8F.
	TAMP_SR_ITAMP8F = 0x800000
	// Position of ITAMP9F field.
	TAMP_SR_ITAMP9F_Pos = 0x18
	// Bit mask of ITAMP9F field.
	TAMP_SR_ITAMP9F_Msk = 0x1000000
	// Bit ITAMP9F.
	TAMP_SR_ITAMP9F = 0x1000000
	// Position of CITAMP11F field.
	TAMP_SR_CITAMP11F_Pos = 0x1a
	// Bit mask of CITAMP11F field.
	TAMP_SR_CITAMP11F_Msk = 0x4000000
	// Bit CITAMP11F.
	TAMP_SR_CITAMP11F = 0x4000000
	// Position of ITAMP12F field.
	TAMP_SR_ITAMP12F_Pos = 0x1b
	// Bit mask of ITAMP12F field.
	TAMP_SR_ITAMP12F_Msk = 0x8000000
	// Bit ITAMP12F.
	TAMP_SR_ITAMP12F = 0x8000000
	// Position of ITAMP13IE field.
	TAMP_SR_ITAMP13IE_Pos = 0x1c
	// Bit mask of ITAMP13IE field.
	TAMP_SR_ITAMP13IE_Msk = 0x10000000
	// Bit ITAMP13IE.
	TAMP_SR_ITAMP13IE = 0x10000000

	// MISR: TAMP masked interrupt status register
	// Position of TAMP1MF field.
	TAMP_MISR_TAMP1MF_Pos = 0x0
	// Bit mask of TAMP1MF field.
	TAMP_MISR_TAMP1MF_Msk = 0x1
	// Bit TAMP1MF.
	TAMP_MISR_TAMP1MF = 0x1
	// Position of TAMP2MF field.
	TAMP_MISR_TAMP2MF_Pos = 0x1
	// Bit mask of TAMP2MF field.
	TAMP_MISR_TAMP2MF_Msk = 0x2
	// Bit TAMP2MF.
	TAMP_MISR_TAMP2MF = 0x2
	// Position of TAMP3MF field.
	TAMP_MISR_TAMP3MF_Pos = 0x2
	// Bit mask of TAMP3MF field.
	TAMP_MISR_TAMP3MF_Msk = 0x4
	// Bit TAMP3MF.
	TAMP_MISR_TAMP3MF = 0x4
	// Position of TAMP4MF field.
	TAMP_MISR_TAMP4MF_Pos = 0x3
	// Bit mask of TAMP4MF field.
	TAMP_MISR_TAMP4MF_Msk = 0x8
	// Bit TAMP4MF.
	TAMP_MISR_TAMP4MF = 0x8
	// Position of TAMP5MF field.
	TAMP_MISR_TAMP5MF_Pos = 0x4
	// Bit mask of TAMP5MF field.
	TAMP_MISR_TAMP5MF_Msk = 0x10
	// Bit TAMP5MF.
	TAMP_MISR_TAMP5MF = 0x10
	// Position of TAMP6MF field.
	TAMP_MISR_TAMP6MF_Pos = 0x5
	// Bit mask of TAMP6MF field.
	TAMP_MISR_TAMP6MF_Msk = 0x20
	// Bit TAMP6MF.
	TAMP_MISR_TAMP6MF = 0x20
	// Position of TAMP7MF field.
	TAMP_MISR_TAMP7MF_Pos = 0x6
	// Bit mask of TAMP7MF field.
	TAMP_MISR_TAMP7MF_Msk = 0x40
	// Bit TAMP7MF.
	TAMP_MISR_TAMP7MF = 0x40
	// Position of TAMP8MF field.
	TAMP_MISR_TAMP8MF_Pos = 0x7
	// Bit mask of TAMP8MF field.
	TAMP_MISR_TAMP8MF_Msk = 0x80
	// Bit TAMP8MF.
	TAMP_MISR_TAMP8MF = 0x80
	// Position of ITAMP1MF field.
	TAMP_MISR_ITAMP1MF_Pos = 0x10
	// Bit mask of ITAMP1MF field.
	TAMP_MISR_ITAMP1MF_Msk = 0x10000
	// Bit ITAMP1MF.
	TAMP_MISR_ITAMP1MF = 0x10000
	// Position of ITAMP2MF field.
	TAMP_MISR_ITAMP2MF_Pos = 0x11
	// Bit mask of ITAMP2MF field.
	TAMP_MISR_ITAMP2MF_Msk = 0x20000
	// Bit ITAMP2MF.
	TAMP_MISR_ITAMP2MF = 0x20000
	// Position of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF_Pos = 0x12
	// Bit mask of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF_Msk = 0x40000
	// Bit ITAMP3MF.
	TAMP_MISR_ITAMP3MF = 0x40000
	// Position of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF_Pos = 0x14
	// Bit mask of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF_Msk = 0x100000
	// Bit ITAMP5MF.
	TAMP_MISR_ITAMP5MF = 0x100000
	// Position of ITAMP6MF field.
	TAMP_MISR_ITAMP6MF_Pos = 0x15
	// Bit mask of ITAMP6MF field.
	TAMP_MISR_ITAMP6MF_Msk = 0x200000
	// Bit ITAMP6MF.
	TAMP_MISR_ITAMP6MF = 0x200000
	// Position of ITAMP7MF field.
	TAMP_MISR_ITAMP7MF_Pos = 0x16
	// Bit mask of ITAMP7MF field.
	TAMP_MISR_ITAMP7MF_Msk = 0x400000
	// Bit ITAMP7MF.
	TAMP_MISR_ITAMP7MF = 0x400000
	// Position of ITAMP8MF field.
	TAMP_MISR_ITAMP8MF_Pos = 0x17
	// Bit mask of ITAMP8MF field.
	TAMP_MISR_ITAMP8MF_Msk = 0x800000
	// Bit ITAMP8MF.
	TAMP_MISR_ITAMP8MF = 0x800000
	// Position of ITAMP9MF field.
	TAMP_MISR_ITAMP9MF_Pos = 0x18
	// Bit mask of ITAMP9MF field.
	TAMP_MISR_ITAMP9MF_Msk = 0x1000000
	// Bit ITAMP9MF.
	TAMP_MISR_ITAMP9MF = 0x1000000
	// Position of ITAMP11MF field.
	TAMP_MISR_ITAMP11MF_Pos = 0x1a
	// Bit mask of ITAMP11MF field.
	TAMP_MISR_ITAMP11MF_Msk = 0x4000000
	// Bit ITAMP11MF.
	TAMP_MISR_ITAMP11MF = 0x4000000
	// Position of ITAMP12MF field.
	TAMP_MISR_ITAMP12MF_Pos = 0x1b
	// Bit mask of ITAMP12MF field.
	TAMP_MISR_ITAMP12MF_Msk = 0x8000000
	// Bit ITAMP12MF.
	TAMP_MISR_ITAMP12MF = 0x8000000
	// Position of ITAMP13MF field.
	TAMP_MISR_ITAMP13MF_Pos = 0x1c
	// Bit mask of ITAMP13MF field.
	TAMP_MISR_ITAMP13MF_Msk = 0x10000000
	// Bit ITAMP13MF.
	TAMP_MISR_ITAMP13MF = 0x10000000

	// SMISR: TAMP secure masked interrupt status register
	// Position of TAMP1MF field.
	TAMP_SMISR_TAMP1MF_Pos = 0x0
	// Bit mask of TAMP1MF field.
	TAMP_SMISR_TAMP1MF_Msk = 0x1
	// Bit TAMP1MF.
	TAMP_SMISR_TAMP1MF = 0x1
	// Position of TAMP2MF field.
	TAMP_SMISR_TAMP2MF_Pos = 0x1
	// Bit mask of TAMP2MF field.
	TAMP_SMISR_TAMP2MF_Msk = 0x2
	// Bit TAMP2MF.
	TAMP_SMISR_TAMP2MF = 0x2
	// Position of TAMP3MF field.
	TAMP_SMISR_TAMP3MF_Pos = 0x2
	// Bit mask of TAMP3MF field.
	TAMP_SMISR_TAMP3MF_Msk = 0x4
	// Bit TAMP3MF.
	TAMP_SMISR_TAMP3MF = 0x4
	// Position of TAMP4MF field.
	TAMP_SMISR_TAMP4MF_Pos = 0x3
	// Bit mask of TAMP4MF field.
	TAMP_SMISR_TAMP4MF_Msk = 0x8
	// Bit TAMP4MF.
	TAMP_SMISR_TAMP4MF = 0x8
	// Position of TAMP5MF field.
	TAMP_SMISR_TAMP5MF_Pos = 0x4
	// Bit mask of TAMP5MF field.
	TAMP_SMISR_TAMP5MF_Msk = 0x10
	// Bit TAMP5MF.
	TAMP_SMISR_TAMP5MF = 0x10
	// Position of TAMP6MF field.
	TAMP_SMISR_TAMP6MF_Pos = 0x5
	// Bit mask of TAMP6MF field.
	TAMP_SMISR_TAMP6MF_Msk = 0x20
	// Bit TAMP6MF.
	TAMP_SMISR_TAMP6MF = 0x20
	// Position of TAMP7MF field.
	TAMP_SMISR_TAMP7MF_Pos = 0x6
	// Bit mask of TAMP7MF field.
	TAMP_SMISR_TAMP7MF_Msk = 0x40
	// Bit TAMP7MF.
	TAMP_SMISR_TAMP7MF = 0x40
	// Position of TAMP8MF field.
	TAMP_SMISR_TAMP8MF_Pos = 0x7
	// Bit mask of TAMP8MF field.
	TAMP_SMISR_TAMP8MF_Msk = 0x80
	// Bit TAMP8MF.
	TAMP_SMISR_TAMP8MF = 0x80
	// Position of ITAMP1MF field.
	TAMP_SMISR_ITAMP1MF_Pos = 0x10
	// Bit mask of ITAMP1MF field.
	TAMP_SMISR_ITAMP1MF_Msk = 0x10000
	// Bit ITAMP1MF.
	TAMP_SMISR_ITAMP1MF = 0x10000
	// Position of ITAMP2MF field.
	TAMP_SMISR_ITAMP2MF_Pos = 0x11
	// Bit mask of ITAMP2MF field.
	TAMP_SMISR_ITAMP2MF_Msk = 0x20000
	// Bit ITAMP2MF.
	TAMP_SMISR_ITAMP2MF = 0x20000
	// Position of ITAMP3MF field.
	TAMP_SMISR_ITAMP3MF_Pos = 0x12
	// Bit mask of ITAMP3MF field.
	TAMP_SMISR_ITAMP3MF_Msk = 0x40000
	// Bit ITAMP3MF.
	TAMP_SMISR_ITAMP3MF = 0x40000
	// Position of ITAMP5MF field.
	TAMP_SMISR_ITAMP5MF_Pos = 0x14
	// Bit mask of ITAMP5MF field.
	TAMP_SMISR_ITAMP5MF_Msk = 0x100000
	// Bit ITAMP5MF.
	TAMP_SMISR_ITAMP5MF = 0x100000
	// Position of ITAMP6MF field.
	TAMP_SMISR_ITAMP6MF_Pos = 0x15
	// Bit mask of ITAMP6MF field.
	TAMP_SMISR_ITAMP6MF_Msk = 0x200000
	// Bit ITAMP6MF.
	TAMP_SMISR_ITAMP6MF = 0x200000
	// Position of ITAMP7MF field.
	TAMP_SMISR_ITAMP7MF_Pos = 0x16
	// Bit mask of ITAMP7MF field.
	TAMP_SMISR_ITAMP7MF_Msk = 0x400000
	// Bit ITAMP7MF.
	TAMP_SMISR_ITAMP7MF = 0x400000
	// Position of ITAMP8MF field.
	TAMP_SMISR_ITAMP8MF_Pos = 0x17
	// Bit mask of ITAMP8MF field.
	TAMP_SMISR_ITAMP8MF_Msk = 0x800000
	// Bit ITAMP8MF.
	TAMP_SMISR_ITAMP8MF = 0x800000
	// Position of ITAMP9MF field.
	TAMP_SMISR_ITAMP9MF_Pos = 0x18
	// Bit mask of ITAMP9MF field.
	TAMP_SMISR_ITAMP9MF_Msk = 0x1000000
	// Bit ITAMP9MF.
	TAMP_SMISR_ITAMP9MF = 0x1000000
	// Position of ITAMP11MF field.
	TAMP_SMISR_ITAMP11MF_Pos = 0x1a
	// Bit mask of ITAMP11MF field.
	TAMP_SMISR_ITAMP11MF_Msk = 0x4000000
	// Bit ITAMP11MF.
	TAMP_SMISR_ITAMP11MF = 0x4000000
	// Position of ITAMP12MF field.
	TAMP_SMISR_ITAMP12MF_Pos = 0x1b
	// Bit mask of ITAMP12MF field.
	TAMP_SMISR_ITAMP12MF_Msk = 0x8000000
	// Bit ITAMP12MF.
	TAMP_SMISR_ITAMP12MF = 0x8000000
	// Position of ITAMP13MF field.
	TAMP_SMISR_ITAMP13MF_Pos = 0x1c
	// Bit mask of ITAMP13MF field.
	TAMP_SMISR_ITAMP13MF_Msk = 0x10000000
	// Bit ITAMP13MF.
	TAMP_SMISR_ITAMP13MF = 0x10000000

	// SCR: TAMP status clear register
	// Position of CTAMP1F field.
	TAMP_SCR_CTAMP1F_Pos = 0x0
	// Bit mask of CTAMP1F field.
	TAMP_SCR_CTAMP1F_Msk = 0x1
	// Bit CTAMP1F.
	TAMP_SCR_CTAMP1F = 0x1
	// Position of CTAMP2F field.
	TAMP_SCR_CTAMP2F_Pos = 0x1
	// Bit mask of CTAMP2F field.
	TAMP_SCR_CTAMP2F_Msk = 0x2
	// Bit CTAMP2F.
	TAMP_SCR_CTAMP2F = 0x2
	// Position of CTAMP3F field.
	TAMP_SCR_CTAMP3F_Pos = 0x2
	// Bit mask of CTAMP3F field.
	TAMP_SCR_CTAMP3F_Msk = 0x4
	// Bit CTAMP3F.
	TAMP_SCR_CTAMP3F = 0x4
	// Position of CTAMP4F field.
	TAMP_SCR_CTAMP4F_Pos = 0x3
	// Bit mask of CTAMP4F field.
	TAMP_SCR_CTAMP4F_Msk = 0x8
	// Bit CTAMP4F.
	TAMP_SCR_CTAMP4F = 0x8
	// Position of CTAMP5F field.
	TAMP_SCR_CTAMP5F_Pos = 0x4
	// Bit mask of CTAMP5F field.
	TAMP_SCR_CTAMP5F_Msk = 0x10
	// Bit CTAMP5F.
	TAMP_SCR_CTAMP5F = 0x10
	// Position of CTAMP6F field.
	TAMP_SCR_CTAMP6F_Pos = 0x5
	// Bit mask of CTAMP6F field.
	TAMP_SCR_CTAMP6F_Msk = 0x20
	// Bit CTAMP6F.
	TAMP_SCR_CTAMP6F = 0x20
	// Position of CITAMP7F field.
	TAMP_SCR_CITAMP7F_Pos = 0x6
	// Bit mask of CITAMP7F field.
	TAMP_SCR_CITAMP7F_Msk = 0x40
	// Bit CITAMP7F.
	TAMP_SCR_CITAMP7F = 0x40
	// Position of CITAMP8F field.
	TAMP_SCR_CITAMP8F_Pos = 0x7
	// Bit mask of CITAMP8F field.
	TAMP_SCR_CITAMP8F_Msk = 0x80
	// Bit CITAMP8F.
	TAMP_SCR_CITAMP8F = 0x80
	// Position of CITAMP1F field.
	TAMP_SCR_CITAMP1F_Pos = 0x10
	// Bit mask of CITAMP1F field.
	TAMP_SCR_CITAMP1F_Msk = 0x10000
	// Bit CITAMP1F.
	TAMP_SCR_CITAMP1F = 0x10000
	// Position of CITAMP2F field.
	TAMP_SCR_CITAMP2F_Pos = 0x11
	// Bit mask of CITAMP2F field.
	TAMP_SCR_CITAMP2F_Msk = 0x20000
	// Bit CITAMP2F.
	TAMP_SCR_CITAMP2F = 0x20000
	// Position of CITAMP3F field.
	TAMP_SCR_CITAMP3F_Pos = 0x12
	// Bit mask of CITAMP3F field.
	TAMP_SCR_CITAMP3F_Msk = 0x40000
	// Bit CITAMP3F.
	TAMP_SCR_CITAMP3F = 0x40000
	// Position of CITAMP5F field.
	TAMP_SCR_CITAMP5F_Pos = 0x14
	// Bit mask of CITAMP5F field.
	TAMP_SCR_CITAMP5F_Msk = 0x100000
	// Bit CITAMP5F.
	TAMP_SCR_CITAMP5F = 0x100000
	// Position of CITAMP6F_bit21 field.
	TAMP_SCR_CITAMP6F_bit21_Pos = 0x15
	// Bit mask of CITAMP6F_bit21 field.
	TAMP_SCR_CITAMP6F_bit21_Msk = 0x200000
	// Bit CITAMP6F_bit21.
	TAMP_SCR_CITAMP6F_bit21 = 0x200000
	// Position of CITAMP7F_bit22 field.
	TAMP_SCR_CITAMP7F_bit22_Pos = 0x16
	// Bit mask of CITAMP7F_bit22 field.
	TAMP_SCR_CITAMP7F_bit22_Msk = 0x400000
	// Bit CITAMP7F_bit22.
	TAMP_SCR_CITAMP7F_bit22 = 0x400000
	// Position of CITAMP8F_bit23 field.
	TAMP_SCR_CITAMP8F_bit23_Pos = 0x17
	// Bit mask of CITAMP8F_bit23 field.
	TAMP_SCR_CITAMP8F_bit23_Msk = 0x800000
	// Bit CITAMP8F_bit23.
	TAMP_SCR_CITAMP8F_bit23 = 0x800000
	// Position of CITAMP9F field.
	TAMP_SCR_CITAMP9F_Pos = 0x18
	// Bit mask of CITAMP9F field.
	TAMP_SCR_CITAMP9F_Msk = 0x1000000
	// Bit CITAMP9F.
	TAMP_SCR_CITAMP9F = 0x1000000
	// Position of CITAMP11F field.
	TAMP_SCR_CITAMP11F_Pos = 0x1a
	// Bit mask of CITAMP11F field.
	TAMP_SCR_CITAMP11F_Msk = 0x4000000
	// Bit CITAMP11F.
	TAMP_SCR_CITAMP11F = 0x4000000
	// Position of CITAMP12F field.
	TAMP_SCR_CITAMP12F_Pos = 0x1b
	// Bit mask of CITAMP12F field.
	TAMP_SCR_CITAMP12F_Msk = 0x8000000
	// Bit CITAMP12F.
	TAMP_SCR_CITAMP12F = 0x8000000
	// Position of CITAMP13F field.
	TAMP_SCR_CITAMP13F_Pos = 0x1c
	// Bit mask of CITAMP13F field.
	TAMP_SCR_CITAMP13F_Msk = 0x10000000
	// Bit CITAMP13F.
	TAMP_SCR_CITAMP13F = 0x10000000

	// COUNT1R: TAMP monotonic counter 1register
	// Position of COUNT field.
	TAMP_COUNT1R_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	TAMP_COUNT1R_COUNT_Msk = 0xffffffff

	// ERCFGR: TAMP erase configuration register
	// Position of ERCFG0 field.
	TAMP_ERCFGR_ERCFG0_Pos = 0x0
	// Bit mask of ERCFG0 field.
	TAMP_ERCFGR_ERCFG0_Msk = 0x1
	// Bit ERCFG0.
	TAMP_ERCFGR_ERCFG0 = 0x1

	// BKP0R: TAMP backup register
	// Position of BKP field.
	TAMP_BKPR_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_BKPR_BKP_Msk = 0xffffffff
)

// Constants for TIM1: Advanced-timers
const (
	// CR1: control register 1
	// Position of DITHEN field.
	TIM_CR1_DITHEN_Pos = 0xc
	// Bit mask of DITHEN field.
	TIM_CR1_DITHEN_Msk = 0x1000
	// Bit DITHEN.
	TIM_CR1_DITHEN = 0x1000
	// Dithering disabled
	TIM_CR1_DITHEN_Disabled = 0x0
	// Dithering enabled
	TIM_CR1_DITHEN_Enabled = 0x1
	// Position of UIFREMAP field.
	TIM_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM_CR1_UIFREMAP = 0x800
	// No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
	TIM_CR1_UIFREMAP_Disabled = 0x0
	// Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31
	TIM_CR1_UIFREMAP_Enabled = 0x1
	// Position of CKD field.
	TIM_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM_CR1_CKD_Msk = 0x300
	// t_DTS = t_CK_INT
	TIM_CR1_CKD_Div1 = 0x0
	// t_DTS = 2 × t_CK_INT
	TIM_CR1_CKD_Div2 = 0x1
	// t_DTS = 4 × t_CK_INT
	TIM_CR1_CKD_Div4 = 0x2
	// Position of ARPE field.
	TIM_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM_CR1_ARPE = 0x80
	// TIMx_APRR register is not buffered
	TIM_CR1_ARPE_Disabled = 0x0
	// TIMx_APRR register is buffered
	TIM_CR1_ARPE_Enabled = 0x1
	// Position of CMS field.
	TIM_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM_CR1_CMS_Msk = 0x60
	// The counter counts up or down depending on the direction bit
	TIM_CR1_CMS_EdgeAligned = 0x0
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
	TIM_CR1_CMS_CenterAligned1 = 0x1
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
	TIM_CR1_CMS_CenterAligned2 = 0x2
	// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
	TIM_CR1_CMS_CenterAligned3 = 0x3
	// Position of DIR field.
	TIM_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM_CR1_DIR = 0x10
	// Counter used as upcounter
	TIM_CR1_DIR_Up = 0x0
	// Counter used as downcounter
	TIM_CR1_DIR_Down = 0x1
	// Position of OPM field.
	TIM_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM_CR1_OPM = 0x8
	// Counter is not stopped at update event
	TIM_CR1_OPM_Disabled = 0x0
	// Counter stops counting at the next update event (clearing the CEN bit)
	TIM_CR1_OPM_Enabled = 0x1
	// Position of URS field.
	TIM_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM_CR1_URS = 0x4
	// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
	TIM_CR1_URS_AnyEvent = 0x0
	// Only counter overflow/underflow generates an update interrupt or DMA request
	TIM_CR1_URS_CounterOnly = 0x1
	// Position of UDIS field.
	TIM_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM_CR1_UDIS = 0x2
	// Update event enabled
	TIM_CR1_UDIS_Enabled = 0x0
	// Update event disabled
	TIM_CR1_UDIS_Disabled = 0x1
	// Position of CEN field.
	TIM_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM_CR1_CEN = 0x1
	// Counter disabled
	TIM_CR1_CEN_Disabled = 0x0
	// Counter enabled
	TIM_CR1_CEN_Enabled = 0x1

	// CR2: control register 2
	// Position of MMS_3 field.
	TIM_CR2_MMS_3_Pos = 0x19
	// Bit mask of MMS_3 field.
	TIM_CR2_MMS_3_Msk = 0x2000000
	// Bit MMS_3.
	TIM_CR2_MMS_3 = 0x2000000
	// Position of MMS2 field.
	TIM_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM_CR2_MMS2_Msk = 0xf00000
	// Position of OIS1 field.
	TIM_CR2_OIS1_Pos = 0xa
	// Bit mask of OIS1 field.
	TIM_CR2_OIS1_Msk = 0x400
	// Bit OIS1.
	TIM_CR2_OIS1 = 0x400
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS1_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS1_Set = 0x1
	// Position of OIS2 field.
	TIM_CR2_OIS2_Pos = 0xc
	// Bit mask of OIS2 field.
	TIM_CR2_OIS2_Msk = 0x1000
	// Bit OIS2.
	TIM_CR2_OIS2 = 0x1000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS2_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS2_Set = 0x1
	// Position of OIS3 field.
	TIM_CR2_OIS3_Pos = 0xe
	// Bit mask of OIS3 field.
	TIM_CR2_OIS3_Msk = 0x4000
	// Bit OIS3.
	TIM_CR2_OIS3 = 0x4000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS3_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS3_Set = 0x1
	// Position of OIS4 field.
	TIM_CR2_OIS4_Pos = 0x10
	// Bit mask of OIS4 field.
	TIM_CR2_OIS4_Msk = 0x10000
	// Bit OIS4.
	TIM_CR2_OIS4 = 0x10000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS4_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS4_Set = 0x1
	// Position of OIS5 field.
	TIM_CR2_OIS5_Pos = 0x12
	// Bit mask of OIS5 field.
	TIM_CR2_OIS5_Msk = 0x40000
	// Bit OIS5.
	TIM_CR2_OIS5 = 0x40000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS5_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS5_Set = 0x1
	// Position of OIS6 field.
	TIM_CR2_OIS6_Pos = 0x14
	// Bit mask of OIS6 field.
	TIM_CR2_OIS6_Msk = 0x100000
	// Bit OIS6.
	TIM_CR2_OIS6 = 0x100000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS6_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS6_Set = 0x1
	// Position of OIS1N field.
	TIM_CR2_OIS1N_Pos = 0xb
	// Bit mask of OIS1N field.
	TIM_CR2_OIS1N_Msk = 0x800
	// Bit OIS1N.
	TIM_CR2_OIS1N = 0x800
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS1N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS1N_Set = 0x1
	// Position of OIS2N field.
	TIM_CR2_OIS2N_Pos = 0xd
	// Bit mask of OIS2N field.
	TIM_CR2_OIS2N_Msk = 0x2000
	// Bit OIS2N.
	TIM_CR2_OIS2N = 0x2000
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS2N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS2N_Set = 0x1
	// Position of OIS3N field.
	TIM_CR2_OIS3N_Pos = 0xf
	// Bit mask of OIS3N field.
	TIM_CR2_OIS3N_Msk = 0x8000
	// Bit OIS3N.
	TIM_CR2_OIS3N = 0x8000
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS3N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS3N_Set = 0x1
	// Position of OIS4N field.
	TIM_CR2_OIS4N_Pos = 0x11
	// Bit mask of OIS4N field.
	TIM_CR2_OIS4N_Msk = 0x20000
	// Bit OIS4N.
	TIM_CR2_OIS4N = 0x20000
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS4N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS4N_Set = 0x1
	// Position of TI1S field.
	TIM_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM_CR2_TI1S = 0x80
	// The TIMx_CH1 pin is connected to TI1 input
	TIM_CR2_TI1S_Normal = 0x0
	// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
	TIM_CR2_TI1S_XOR = 0x1
	// Position of MMS field.
	TIM_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM_CR2_MMS_Msk = 0x70
	// Position of CCDS field.
	TIM_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM_CR2_CCDS = 0x8
	// CCx DMA request sent when CCx event occurs
	TIM_CR2_CCDS_OnCompare = 0x0
	// CCx DMA request sent when update event occurs
	TIM_CR2_CCDS_OnUpdate = 0x1
	// Position of CCUS field.
	TIM_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM_CR2_CCUS = 0x4
	// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
	TIM_CR2_CCUS_Sw = 0x0
	// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
	TIM_CR2_CCUS_SwOrEdge = 0x1
	// Position of CCPC field.
	TIM_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM_CR2_CCPC = 0x1
	// CCxE, CCxNE and OCxM bits are not preloaded
	TIM_CR2_CCPC_NotPreloaded = 0x0
	// CCxE, CCxNE and OCxM bits are preloaded
	TIM_CR2_CCPC_Preloaded = 0x1

	// SMCR: slave mode control register
	// Position of SMSPS field.
	TIM_SMCR_SMSPS_Pos = 0x19
	// Bit mask of SMSPS field.
	TIM_SMCR_SMSPS_Msk = 0x2000000
	// Bit SMSPS.
	TIM_SMCR_SMSPS = 0x2000000
	// Position of SMSPE field.
	TIM_SMCR_SMSPE_Pos = 0x18
	// Bit mask of SMSPE field.
	TIM_SMCR_SMSPE_Msk = 0x1000000
	// Bit SMSPE.
	TIM_SMCR_SMSPE = 0x1000000
	// Position of TS2 field.
	TIM_SMCR_TS2_Pos = 0x14
	// Bit mask of TS2 field.
	TIM_SMCR_TS2_Msk = 0x300000
	// Position of SMS_3 field.
	TIM_SMCR_SMS_3_Pos = 0x10
	// Bit mask of SMS_3 field.
	TIM_SMCR_SMS_3_Msk = 0x10000
	// Bit SMS_3.
	TIM_SMCR_SMS_3 = 0x10000
	// Position of ETP field.
	TIM_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM_SMCR_ETP = 0x8000
	// ETR is noninverted, active at high level or rising edge
	TIM_SMCR_ETP_NotInverted = 0x0
	// ETR is inverted, active at low level or falling edge
	TIM_SMCR_ETP_Inverted = 0x1
	// Position of ECE field.
	TIM_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM_SMCR_ECE = 0x4000
	// External clock mode 2 disabled
	TIM_SMCR_ECE_Disabled = 0x0
	// External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
	TIM_SMCR_ECE_Enabled = 0x1
	// Position of ETPS field.
	TIM_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM_SMCR_ETPS_Msk = 0x3000
	// Prescaler OFF
	TIM_SMCR_ETPS_Div1 = 0x0
	// ETRP frequency divided by 2
	TIM_SMCR_ETPS_Div2 = 0x1
	// ETRP frequency divided by 4
	TIM_SMCR_ETPS_Div4 = 0x2
	// ETRP frequency divided by 8
	TIM_SMCR_ETPS_Div8 = 0x3
	// Position of ETF field.
	TIM_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM_SMCR_ETF_Msk = 0xf00
	// No filter, sampling is done at fDTS
	TIM_SMCR_ETF_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_SMCR_ETF_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_SMCR_ETF_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_SMCR_ETF_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_SMCR_ETF_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_SMCR_ETF_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_SMCR_ETF_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_SMCR_ETF_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_SMCR_ETF_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_SMCR_ETF_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_SMCR_ETF_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_SMCR_ETF_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_SMCR_ETF_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_SMCR_ETF_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_SMCR_ETF_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_SMCR_ETF_FDTS_Div32_N8 = 0xf
	// Position of MSM field.
	TIM_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM_SMCR_MSM = 0x80
	// No action
	TIM_SMCR_MSM_NoSync = 0x0
	// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
	TIM_SMCR_MSM_Sync = 0x1
	// Position of TS field.
	TIM_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM_SMCR_TS_Msk = 0x70
	// Position of OCCS field.
	TIM_SMCR_OCCS_Pos = 0x3
	// Bit mask of OCCS field.
	TIM_SMCR_OCCS_Msk = 0x8
	// Bit OCCS.
	TIM_SMCR_OCCS = 0x8
	// Position of SMS field.
	TIM_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM_SMCR_SMS_Msk = 0x7

	// DIER: DMA/Interrupt enable register
	// Position of TERRIE field.
	TIM_DIER_TERRIE_Pos = 0x17
	// Bit mask of TERRIE field.
	TIM_DIER_TERRIE_Msk = 0x800000
	// Bit TERRIE.
	TIM_DIER_TERRIE = 0x800000
	// Position of IERRIE field.
	TIM_DIER_IERRIE_Pos = 0x16
	// Bit mask of IERRIE field.
	TIM_DIER_IERRIE_Msk = 0x400000
	// Bit IERRIE.
	TIM_DIER_IERRIE = 0x400000
	// Position of DIRIE field.
	TIM_DIER_DIRIE_Pos = 0x15
	// Bit mask of DIRIE field.
	TIM_DIER_DIRIE_Msk = 0x200000
	// Bit DIRIE.
	TIM_DIER_DIRIE = 0x200000
	// Position of IDXIE field.
	TIM_DIER_IDXIE_Pos = 0x14
	// Bit mask of IDXIE field.
	TIM_DIER_IDXIE_Msk = 0x100000
	// Bit IDXIE.
	TIM_DIER_IDXIE = 0x100000
	// Position of TDE field.
	TIM_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM_DIER_TDE = 0x4000
	// Trigger DMA request disabled
	TIM_DIER_TDE_Disabled = 0x0
	// Trigger DMA request enabled
	TIM_DIER_TDE_Enabled = 0x1
	// Position of COMDE field.
	TIM_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM_DIER_COMDE = 0x2000
	// COM DMA request disabled
	TIM_DIER_COMDE_Disabled = 0x0
	// COM DMA request enabled
	TIM_DIER_COMDE_Enabled = 0x1
	// Position of CC1DE field.
	TIM_DIER_CC1DE_Pos = 0xa
	// Bit mask of CC1DE field.
	TIM_DIER_CC1DE_Msk = 0x400
	// Bit CC1DE.
	TIM_DIER_CC1DE = 0x400
	// CCx DMA request disabled
	TIM_DIER_CC1DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC1DE_Enabled = 0x1
	// Position of CC2DE field.
	TIM_DIER_CC2DE_Pos = 0xb
	// Bit mask of CC2DE field.
	TIM_DIER_CC2DE_Msk = 0x800
	// Bit CC2DE.
	TIM_DIER_CC2DE = 0x800
	// CCx DMA request disabled
	TIM_DIER_CC2DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC2DE_Enabled = 0x1
	// Position of CC3DE field.
	TIM_DIER_CC3DE_Pos = 0xc
	// Bit mask of CC3DE field.
	TIM_DIER_CC3DE_Msk = 0x1000
	// Bit CC3DE.
	TIM_DIER_CC3DE = 0x1000
	// CCx DMA request disabled
	TIM_DIER_CC3DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC3DE_Enabled = 0x1
	// Position of CC4DE field.
	TIM_DIER_CC4DE_Pos = 0xd
	// Bit mask of CC4DE field.
	TIM_DIER_CC4DE_Msk = 0x2000
	// Bit CC4DE.
	TIM_DIER_CC4DE = 0x2000
	// CCx DMA request disabled
	TIM_DIER_CC4DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC4DE_Enabled = 0x1
	// Position of UDE field.
	TIM_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM_DIER_UDE = 0x100
	// Update DMA request disabled
	TIM_DIER_UDE_Disabled = 0x0
	// Update DMA request enabled
	TIM_DIER_UDE_Enabled = 0x1
	// Position of BIE field.
	TIM_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM_DIER_BIE = 0x80
	// Break interrupt disabled
	TIM_DIER_BIE_Disabled = 0x0
	// Break interrupt enabled
	TIM_DIER_BIE_Enabled = 0x1
	// Position of TIE field.
	TIM_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM_DIER_TIE = 0x40
	// Trigger interrupt disabled
	TIM_DIER_TIE_Disabled = 0x0
	// Trigger interrupt enabled
	TIM_DIER_TIE_Enabled = 0x1
	// Position of COMIE field.
	TIM_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM_DIER_COMIE = 0x20
	// COM interrupt disabled
	TIM_DIER_COMIE_Disabled = 0x0
	// COM interrupt enabled
	TIM_DIER_COMIE_Enabled = 0x1
	// Position of CC1IE field.
	TIM_DIER_CC1IE_Pos = 0x2
	// Bit mask of CC1IE field.
	TIM_DIER_CC1IE_Msk = 0x4
	// Bit CC1IE.
	TIM_DIER_CC1IE = 0x4
	// CCx interrupt disabled
	TIM_DIER_CC1IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC1IE_Enabled = 0x1
	// Position of CC2IE field.
	TIM_DIER_CC2IE_Pos = 0x3
	// Bit mask of CC2IE field.
	TIM_DIER_CC2IE_Msk = 0x8
	// Bit CC2IE.
	TIM_DIER_CC2IE = 0x8
	// CCx interrupt disabled
	TIM_DIER_CC2IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC2IE_Enabled = 0x1
	// Position of CC3IE field.
	TIM_DIER_CC3IE_Pos = 0x4
	// Bit mask of CC3IE field.
	TIM_DIER_CC3IE_Msk = 0x10
	// Bit CC3IE.
	TIM_DIER_CC3IE = 0x10
	// CCx interrupt disabled
	TIM_DIER_CC3IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC3IE_Enabled = 0x1
	// Position of CC4IE field.
	TIM_DIER_CC4IE_Pos = 0x5
	// Bit mask of CC4IE field.
	TIM_DIER_CC4IE_Msk = 0x20
	// Bit CC4IE.
	TIM_DIER_CC4IE = 0x20
	// CCx interrupt disabled
	TIM_DIER_CC4IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC4IE_Enabled = 0x1
	// Position of UIE field.
	TIM_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM_DIER_UIE = 0x1
	// Update interrupt disabled
	TIM_DIER_UIE_Disabled = 0x0
	// Update interrupt enabled
	TIM_DIER_UIE_Enabled = 0x1

	// SR: status register
	// Position of TERRF field.
	TIM_SR_TERRF_Pos = 0x17
	// Bit mask of TERRF field.
	TIM_SR_TERRF_Msk = 0x800000
	// Bit TERRF.
	TIM_SR_TERRF = 0x800000
	// Position of IERRF field.
	TIM_SR_IERRF_Pos = 0x16
	// Bit mask of IERRF field.
	TIM_SR_IERRF_Msk = 0x400000
	// Bit IERRF.
	TIM_SR_IERRF = 0x400000
	// Position of DIRF field.
	TIM_SR_DIRF_Pos = 0x15
	// Bit mask of DIRF field.
	TIM_SR_DIRF_Msk = 0x200000
	// Bit DIRF.
	TIM_SR_DIRF = 0x200000
	// Position of IDXF field.
	TIM_SR_IDXF_Pos = 0x14
	// Bit mask of IDXF field.
	TIM_SR_IDXF_Msk = 0x100000
	// Bit IDXF.
	TIM_SR_IDXF = 0x100000
	// Position of CC1IF field.
	TIM_SR_CC1IF_Pos = 0x2
	// Bit mask of CC1IF field.
	TIM_SR_CC1IF_Msk = 0x4
	// Bit CC1IF.
	TIM_SR_CC1IF = 0x4
	// No campture/compare has been detected
	TIM_SR_CC1IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC1IF_Match = 0x1
	// Clear flag
	TIM_SR_CC1IF_Clear = 0x0
	// Position of CC2IF field.
	TIM_SR_CC2IF_Pos = 0x3
	// Bit mask of CC2IF field.
	TIM_SR_CC2IF_Msk = 0x8
	// Bit CC2IF.
	TIM_SR_CC2IF = 0x8
	// No campture/compare has been detected
	TIM_SR_CC2IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC2IF_Match = 0x1
	// Clear flag
	TIM_SR_CC2IF_Clear = 0x0
	// Position of CC3IF field.
	TIM_SR_CC3IF_Pos = 0x4
	// Bit mask of CC3IF field.
	TIM_SR_CC3IF_Msk = 0x10
	// Bit CC3IF.
	TIM_SR_CC3IF = 0x10
	// No campture/compare has been detected
	TIM_SR_CC3IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC3IF_Match = 0x1
	// Clear flag
	TIM_SR_CC3IF_Clear = 0x0
	// Position of CC4IF field.
	TIM_SR_CC4IF_Pos = 0x5
	// Bit mask of CC4IF field.
	TIM_SR_CC4IF_Msk = 0x20
	// Bit CC4IF.
	TIM_SR_CC4IF = 0x20
	// No campture/compare has been detected
	TIM_SR_CC4IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC4IF_Match = 0x1
	// Clear flag
	TIM_SR_CC4IF_Clear = 0x0
	// Position of CC6IF field.
	TIM_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM_SR_CC6IF = 0x20000
	// No campture/compare has been detected
	TIM_SR_CC6IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC6IF_Match = 0x1
	// Clear flag
	TIM_SR_CC6IF_Clear = 0x0
	// Position of CC5IF field.
	TIM_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM_SR_CC5IF = 0x10000
	// No campture/compare has been detected
	TIM_SR_CC5IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC5IF_Match = 0x1
	// Clear flag
	TIM_SR_CC5IF_Clear = 0x0
	// Position of SBIF field.
	TIM_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM_SR_SBIF = 0x2000
	// No break event occurred
	TIM_SR_SBIF_NoTrigger = 0x0
	// An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_SBIF_Trigger = 0x1
	// Clear flag
	TIM_SR_SBIF_Clear = 0x0
	// Position of CC1OF field.
	TIM_SR_CC1OF_Pos = 0xa
	// Bit mask of CC1OF field.
	TIM_SR_CC1OF_Msk = 0x400
	// Bit CC1OF.
	TIM_SR_CC1OF = 0x400
	// No overcapture has been detected
	TIM_SR_CC1OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC1OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC1OF_Clear = 0x0
	// Position of CC2OF field.
	TIM_SR_CC2OF_Pos = 0xb
	// Bit mask of CC2OF field.
	TIM_SR_CC2OF_Msk = 0x800
	// Bit CC2OF.
	TIM_SR_CC2OF = 0x800
	// No overcapture has been detected
	TIM_SR_CC2OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC2OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC2OF_Clear = 0x0
	// Position of CC3OF field.
	TIM_SR_CC3OF_Pos = 0xc
	// Bit mask of CC3OF field.
	TIM_SR_CC3OF_Msk = 0x1000
	// Bit CC3OF.
	TIM_SR_CC3OF = 0x1000
	// No overcapture has been detected
	TIM_SR_CC3OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC3OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC3OF_Clear = 0x0
	// Position of CC4OF field.
	TIM_SR_CC4OF_Pos = 0xd
	// Bit mask of CC4OF field.
	TIM_SR_CC4OF_Msk = 0x2000
	// Bit CC4OF.
	TIM_SR_CC4OF = 0x2000
	// No overcapture has been detected
	TIM_SR_CC4OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC4OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC4OF_Clear = 0x0
	// Position of B2IF field.
	TIM_SR_B2IF_Pos = 0x8
	// Bit mask of B2IF field.
	TIM_SR_B2IF_Msk = 0x100
	// Bit B2IF.
	TIM_SR_B2IF = 0x100
	// No break event occurred
	TIM_SR_B2IF_NoTrigger = 0x0
	// An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_B2IF_Trigger = 0x1
	// Clear flag
	TIM_SR_B2IF_Clear = 0x0
	// Position of BIF field.
	TIM_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM_SR_BIF = 0x80
	// No break event occurred
	TIM_SR_BIF_NoTrigger = 0x0
	// An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_BIF_Trigger = 0x1
	// Clear flag
	TIM_SR_BIF_Clear = 0x0
	// Position of TIF field.
	TIM_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM_SR_TIF = 0x40
	// No trigger event occurred
	TIM_SR_TIF_NoTrigger = 0x0
	// Trigger interrupt pending
	TIM_SR_TIF_Trigger = 0x1
	// Clear flag
	TIM_SR_TIF_Clear = 0x0
	// Position of COMIF field.
	TIM_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM_SR_COMIF = 0x20
	// No COM event occurred
	TIM_SR_COMIF_NoCOM = 0x0
	// COM interrupt pending
	TIM_SR_COMIF_COM = 0x1
	// Clear flag
	TIM_SR_COMIF_Clear = 0x0
	// Position of UIF field.
	TIM_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM_SR_UIF = 0x1
	// No update occurred
	TIM_SR_UIF_NoUpdateOccurred = 0x0
	// Update interrupt pending
	TIM_SR_UIF_UpdatePending = 0x1
	// Clear flag
	TIM_SR_UIF_Clear = 0x0

	// EGR: event generation register
	// Position of B2G field.
	TIM_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM_EGR_B2G = 0x100
	// A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled
	TIM_EGR_B2G_Trigger = 0x1
	// Position of BG field.
	TIM_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM_EGR_BG = 0x80
	// A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
	TIM_EGR_BG_Trigger = 0x1
	// Position of TG field.
	TIM_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM_EGR_TG = 0x40
	// The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
	TIM_EGR_TG_Trigger = 0x1
	// Position of COMG field.
	TIM_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM_EGR_COMG = 0x20
	// When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
	TIM_EGR_COMG_Trigger = 0x1
	// Position of CC1G field.
	TIM_EGR_CC1G_Pos = 0x2
	// Bit mask of CC1G field.
	TIM_EGR_CC1G_Msk = 0x4
	// Bit CC1G.
	TIM_EGR_CC1G = 0x4
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC1G_Trigger = 0x1
	// Position of CC2G field.
	TIM_EGR_CC2G_Pos = 0x3
	// Bit mask of CC2G field.
	TIM_EGR_CC2G_Msk = 0x8
	// Bit CC2G.
	TIM_EGR_CC2G = 0x8
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC2G_Trigger = 0x1
	// Position of CC3G field.
	TIM_EGR_CC3G_Pos = 0x4
	// Bit mask of CC3G field.
	TIM_EGR_CC3G_Msk = 0x10
	// Bit CC3G.
	TIM_EGR_CC3G = 0x10
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC3G_Trigger = 0x1
	// Position of CC4G field.
	TIM_EGR_CC4G_Pos = 0x5
	// Bit mask of CC4G field.
	TIM_EGR_CC4G_Msk = 0x20
	// Bit CC4G.
	TIM_EGR_CC4G = 0x20
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC4G_Trigger = 0x1
	// Position of UG field.
	TIM_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM_EGR_UG = 0x1
	// Re-initializes the timer counter and generates an update of the registers.
	TIM_EGR_UG_Update = 0x1

	// CCMR1_Output: capture/compare mode register 1 (output mode)
	// Position of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Pos = 0x18
	// Bit mask of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Msk = 0x1000000
	// Bit OC1M_3.
	TIM_CCMR1_Output_OC1M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC1M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC1M_3_Extended = 0x1
	// Position of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Pos = 0x20
	// Bit mask of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Msk = 0x100000000
	// Bit OC2M_3.
	TIM_CCMR1_Output_OC2M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC2M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC2M_3_Extended = 0x1
	// Position of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Pos = 0xf
	// Bit mask of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Msk = 0x8000
	// Bit OC1CE.
	TIM_CCMR1_Output_OC1CE = 0x8000
	// OCxRef is not affected by the ocref_clr_int signal
	TIM_CCMR1_Output_OC1CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal
	TIM_CCMR1_Output_OC1CE_Enabled = 0x1
	// Position of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Pos = 0x17
	// Bit mask of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Msk = 0x800000
	// Bit OC2CE.
	TIM_CCMR1_Output_OC2CE = 0x800000
	// OCxRef is not affected by the ocref_clr_int signal
	TIM_CCMR1_Output_OC2CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal
	TIM_CCMR1_Output_OC2CE_Enabled = 0x1
	// Position of OC1M field.
	TIM_CCMR1_Output_OC1M_Pos = 0xc
	// Bit mask of OC1M field.
	TIM_CCMR1_Output_OC1M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC1M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC1M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC1M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC1M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC1M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC1M_PwmMode2 = 0x7
	// Position of OC2M field.
	TIM_CCMR1_Output_OC2M_Pos = 0x14
	// Bit mask of OC2M field.
	TIM_CCMR1_Output_OC2M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC2M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC2M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC2M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC2M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC2M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC2M_PwmMode2 = 0x7
	// Position of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Pos = 0xb
	// Bit mask of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Msk = 0x800
	// Bit OC1PE.
	TIM_CCMR1_Output_OC1PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC1PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC1PE_Enabled = 0x1
	// Position of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Pos = 0x13
	// Bit mask of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Msk = 0x80000
	// Bit OC2PE.
	TIM_CCMR1_Output_OC2PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC2PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC2PE_Enabled = 0x1
	// Position of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Pos = 0xa
	// Bit mask of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Msk = 0x400
	// Bit OC1FE.
	TIM_CCMR1_Output_OC1FE = 0x400
	// Fast output disabled
	TIM_CCMR1_Output_OC1FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC1FE_Enabled = 0x1
	// Position of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Pos = 0x12
	// Bit mask of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Msk = 0x40000
	// Bit OC2FE.
	TIM_CCMR1_Output_OC2FE = 0x40000
	// Fast output disabled
	TIM_CCMR1_Output_OC2FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC2FE_Enabled = 0x1
	// Position of CC1S field.
	TIM_CCMR1_Output_CC1S_Pos = 0x8
	// Bit mask of CC1S field.
	TIM_CCMR1_Output_CC1S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC1S_Output = 0x0
	// Position of CC2S field.
	TIM_CCMR1_Output_CC2S_Pos = 0x10
	// Bit mask of CC2S field.
	TIM_CCMR1_Output_CC2S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC2S_Output = 0x0

	// CCMR1_Input: capture/compare mode register 1 (input mode)
	// Position of IC1F field.
	TIM_CCMR1_Input_IC1F_Pos = 0xc
	// Bit mask of IC1F field.
	TIM_CCMR1_Input_IC1F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC1F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC1F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC1F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC1F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N8 = 0xf
	// Position of IC2F field.
	TIM_CCMR1_Input_IC2F_Pos = 0x14
	// Bit mask of IC2F field.
	TIM_CCMR1_Input_IC2F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC2F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC2F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC2F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC2F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N8 = 0xf
	// Position of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Pos = 0xa
	// Bit mask of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC1PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC1PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC1PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC1PSC_EightEvents = 0x3
	// Position of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Pos = 0x12
	// Bit mask of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC2PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC2PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC2PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC2PSC_EightEvents = 0x3
	// Position of CC2S field.
	TIM_CCMR1_Input_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM_CCMR1_Input_CC2S_Msk = 0x300
	// CC2 channel is configured as input, IC2 is mapped on TI2
	TIM_CCMR1_Input_CC2S_TI2 = 0x1
	// CC2 channel is configured as input, IC2 is mapped on TI1
	TIM_CCMR1_Input_CC2S_TI1 = 0x2
	// CC2 channel is configured as input, IC2 is mapped on TRC
	TIM_CCMR1_Input_CC2S_TRC = 0x3
	// Position of CC1S field.
	TIM_CCMR1_Input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM_CCMR1_Input_CC1S_Msk = 0x3
	// CC1 channel is configured as input, IC1 is mapped on TI1
	TIM_CCMR1_Input_CC1S_TI1 = 0x1
	// CC1 channel is configured as input, IC1 is mapped on TI2
	TIM_CCMR1_Input_CC1S_TI2 = 0x2
	// CC1 channel is configured as input, IC1 is mapped on TRC
	TIM_CCMR1_Input_CC1S_TRC = 0x3

	// CCMR2_Output: capture/compare mode register 2 (output mode)
	// Position of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Pos = 0x18
	// Bit mask of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Msk = 0x1000000
	// Bit OC3M_3.
	TIM_CCMR2_Output_OC3M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC3M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC3M_3_Extended = 0x1
	// Position of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Pos = 0x20
	// Bit mask of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Msk = 0x100000000
	// Bit OC4M_3.
	TIM_CCMR2_Output_OC4M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC4M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC4M_3_Extended = 0x1
	// Position of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Pos = 0xf
	// Bit mask of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Msk = 0x8000
	// Bit OC3CE.
	TIM_CCMR2_Output_OC3CE = 0x8000
	// OCxRef is not affected by the ocref_clr_int signal
	TIM_CCMR2_Output_OC3CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal
	TIM_CCMR2_Output_OC3CE_Enabled = 0x1
	// Position of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Pos = 0x17
	// Bit mask of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Msk = 0x800000
	// Bit OC4CE.
	TIM_CCMR2_Output_OC4CE = 0x800000
	// OCxRef is not affected by the ocref_clr_int signal
	TIM_CCMR2_Output_OC4CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal
	TIM_CCMR2_Output_OC4CE_Enabled = 0x1
	// Position of OC3M field.
	TIM_CCMR2_Output_OC3M_Pos = 0xc
	// Bit mask of OC3M field.
	TIM_CCMR2_Output_OC3M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC3M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC3M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC3M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC3M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC3M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC3M_PwmMode2 = 0x7
	// Position of OC4M field.
	TIM_CCMR2_Output_OC4M_Pos = 0x14
	// Bit mask of OC4M field.
	TIM_CCMR2_Output_OC4M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC4M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC4M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC4M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC4M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC4M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC4M_PwmMode2 = 0x7
	// Position of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Pos = 0xb
	// Bit mask of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Msk = 0x800
	// Bit OC3PE.
	TIM_CCMR2_Output_OC3PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC3PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC3PE_Enabled = 0x1
	// Position of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Pos = 0x13
	// Bit mask of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Msk = 0x80000
	// Bit OC4PE.
	TIM_CCMR2_Output_OC4PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC4PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC4PE_Enabled = 0x1
	// Position of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Pos = 0xa
	// Bit mask of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Msk = 0x400
	// Bit OC3FE.
	TIM_CCMR2_Output_OC3FE = 0x400
	// Fast output disabled
	TIM_CCMR2_Output_OC3FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC3FE_Enabled = 0x1
	// Position of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Pos = 0x12
	// Bit mask of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Msk = 0x40000
	// Bit OC4FE.
	TIM_CCMR2_Output_OC4FE = 0x40000
	// Fast output disabled
	TIM_CCMR2_Output_OC4FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC4FE_Enabled = 0x1
	// Position of CC3S field.
	TIM_CCMR2_Output_CC3S_Pos = 0x8
	// Bit mask of CC3S field.
	TIM_CCMR2_Output_CC3S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC3S_Output = 0x0
	// Position of CC4S field.
	TIM_CCMR2_Output_CC4S_Pos = 0x10
	// Bit mask of CC4S field.
	TIM_CCMR2_Output_CC4S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC4S_Output = 0x0

	// CCMR2_Input: capture/compare mode register 2 (input mode)
	// Position of IC3F field.
	TIM_CCMR2_Input_IC3F_Pos = 0xc
	// Bit mask of IC3F field.
	TIM_CCMR2_Input_IC3F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC3F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC3F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC3F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC3F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N8 = 0xf
	// Position of IC4F field.
	TIM_CCMR2_Input_IC4F_Pos = 0x14
	// Bit mask of IC4F field.
	TIM_CCMR2_Input_IC4F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC4F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC4F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC4F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC4F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N8 = 0xf
	// Position of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Pos = 0xa
	// Bit mask of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC3PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC3PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC3PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC3PSC_EightEvents = 0x3
	// Position of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Pos = 0x12
	// Bit mask of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC4PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC4PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC4PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC4PSC_EightEvents = 0x3
	// Position of CC4S field.
	TIM_CCMR2_Input_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM_CCMR2_Input_CC4S_Msk = 0x300
	// CC4 channel is configured as input, IC4 is mapped on TI4
	TIM_CCMR2_Input_CC4S_TI4 = 0x1
	// CC4 channel is configured as input, IC4 is mapped on TI3
	TIM_CCMR2_Input_CC4S_TI3 = 0x2
	// CC4 channel is configured as input, IC4 is mapped on TRC
	TIM_CCMR2_Input_CC4S_TRC = 0x3
	// Position of CC3S field.
	TIM_CCMR2_Input_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM_CCMR2_Input_CC3S_Msk = 0x3
	// CC3 channel is configured as input, IC3 is mapped on TI3
	TIM_CCMR2_Input_CC3S_TI3 = 0x1
	// CC3 channel is configured as input, IC3 is mapped on TI4
	TIM_CCMR2_Input_CC3S_TI4 = 0x2
	// CC3 channel is configured as input, IC3 is mapped on TRC
	TIM_CCMR2_Input_CC3S_TRC = 0x3

	// CCER: capture/compare enable register
	// Position of CC1P field.
	TIM_CCER_CC1P_Pos = 0x5
	// Bit mask of CC1P field.
	TIM_CCER_CC1P_Msk = 0x20
	// Bit CC1P.
	TIM_CCER_CC1P = 0x20
	// Noninverted/rising edge
	TIM_CCER_CC1P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC1P_FallingEdge = 0x1
	// Position of CC2P field.
	TIM_CCER_CC2P_Pos = 0x9
	// Bit mask of CC2P field.
	TIM_CCER_CC2P_Msk = 0x200
	// Bit CC2P.
	TIM_CCER_CC2P = 0x200
	// Noninverted/rising edge
	TIM_CCER_CC2P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC2P_FallingEdge = 0x1
	// Position of CC3P field.
	TIM_CCER_CC3P_Pos = 0xd
	// Bit mask of CC3P field.
	TIM_CCER_CC3P_Msk = 0x2000
	// Bit CC3P.
	TIM_CCER_CC3P = 0x2000
	// Noninverted/rising edge
	TIM_CCER_CC3P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC3P_FallingEdge = 0x1
	// Position of CC4P field.
	TIM_CCER_CC4P_Pos = 0x11
	// Bit mask of CC4P field.
	TIM_CCER_CC4P_Msk = 0x20000
	// Bit CC4P.
	TIM_CCER_CC4P = 0x20000
	// Noninverted/rising edge
	TIM_CCER_CC4P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC4P_FallingEdge = 0x1
	// Position of CC5P field.
	TIM_CCER_CC5P_Pos = 0x15
	// Bit mask of CC5P field.
	TIM_CCER_CC5P_Msk = 0x200000
	// Bit CC5P.
	TIM_CCER_CC5P = 0x200000
	// Noninverted/rising edge
	TIM_CCER_CC5P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC5P_FallingEdge = 0x1
	// Position of CC6P field.
	TIM_CCER_CC6P_Pos = 0x19
	// Bit mask of CC6P field.
	TIM_CCER_CC6P_Msk = 0x2000000
	// Bit CC6P.
	TIM_CCER_CC6P = 0x2000000
	// Noninverted/rising edge
	TIM_CCER_CC6P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC6P_FallingEdge = 0x1
	// Position of CC1E field.
	TIM_CCER_CC1E_Pos = 0x4
	// Bit mask of CC1E field.
	TIM_CCER_CC1E_Msk = 0x10
	// Bit CC1E.
	TIM_CCER_CC1E = 0x10
	// Capture disabled
	TIM_CCER_CC1E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC1E_Enabled = 0x1
	// Position of CC2E field.
	TIM_CCER_CC2E_Pos = 0x8
	// Bit mask of CC2E field.
	TIM_CCER_CC2E_Msk = 0x100
	// Bit CC2E.
	TIM_CCER_CC2E = 0x100
	// Capture disabled
	TIM_CCER_CC2E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC2E_Enabled = 0x1
	// Position of CC3E field.
	TIM_CCER_CC3E_Pos = 0xc
	// Bit mask of CC3E field.
	TIM_CCER_CC3E_Msk = 0x1000
	// Bit CC3E.
	TIM_CCER_CC3E = 0x1000
	// Capture disabled
	TIM_CCER_CC3E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC3E_Enabled = 0x1
	// Position of CC4E field.
	TIM_CCER_CC4E_Pos = 0x10
	// Bit mask of CC4E field.
	TIM_CCER_CC4E_Msk = 0x10000
	// Bit CC4E.
	TIM_CCER_CC4E = 0x10000
	// Capture disabled
	TIM_CCER_CC4E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC4E_Enabled = 0x1
	// Position of CC5E field.
	TIM_CCER_CC5E_Pos = 0x14
	// Bit mask of CC5E field.
	TIM_CCER_CC5E_Msk = 0x100000
	// Bit CC5E.
	TIM_CCER_CC5E = 0x100000
	// Capture disabled
	TIM_CCER_CC5E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC5E_Enabled = 0x1
	// Position of CC6E field.
	TIM_CCER_CC6E_Pos = 0x18
	// Bit mask of CC6E field.
	TIM_CCER_CC6E_Msk = 0x1000000
	// Bit CC6E.
	TIM_CCER_CC6E = 0x1000000
	// Capture disabled
	TIM_CCER_CC6E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC6E_Enabled = 0x1
	// Position of CC1NP field.
	TIM_CCER_CC1NP_Pos = 0x7
	// Bit mask of CC1NP field.
	TIM_CCER_CC1NP_Msk = 0x80
	// Bit CC1NP.
	TIM_CCER_CC1NP = 0x80
	// OCxN active high
	TIM_CCER_CC1NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC1NP_ActiveLow = 0x1
	// Position of CC2NP field.
	TIM_CCER_CC2NP_Pos = 0xb
	// Bit mask of CC2NP field.
	TIM_CCER_CC2NP_Msk = 0x800
	// Bit CC2NP.
	TIM_CCER_CC2NP = 0x800
	// OCxN active high
	TIM_CCER_CC2NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC2NP_ActiveLow = 0x1
	// Position of CC3NP field.
	TIM_CCER_CC3NP_Pos = 0xf
	// Bit mask of CC3NP field.
	TIM_CCER_CC3NP_Msk = 0x8000
	// Bit CC3NP.
	TIM_CCER_CC3NP = 0x8000
	// OCxN active high
	TIM_CCER_CC3NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC3NP_ActiveLow = 0x1
	// Position of CC4NP field.
	TIM_CCER_CC4NP_Pos = 0x13
	// Bit mask of CC4NP field.
	TIM_CCER_CC4NP_Msk = 0x80000
	// Bit CC4NP.
	TIM_CCER_CC4NP = 0x80000
	// OCxN active high
	TIM_CCER_CC4NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC4NP_ActiveLow = 0x1
	// Position of CC1NE field.
	TIM_CCER_CC1NE_Pos = 0x6
	// Bit mask of CC1NE field.
	TIM_CCER_CC1NE_Msk = 0x40
	// Bit CC1NE.
	TIM_CCER_CC1NE = 0x40
	// Complementary output disabled
	TIM_CCER_CC1NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC1NE_Enabled = 0x1
	// Position of CC2NE field.
	TIM_CCER_CC2NE_Pos = 0xa
	// Bit mask of CC2NE field.
	TIM_CCER_CC2NE_Msk = 0x400
	// Bit CC2NE.
	TIM_CCER_CC2NE = 0x400
	// Complementary output disabled
	TIM_CCER_CC2NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC2NE_Enabled = 0x1
	// Position of CC3NE field.
	TIM_CCER_CC3NE_Pos = 0xe
	// Bit mask of CC3NE field.
	TIM_CCER_CC3NE_Msk = 0x4000
	// Bit CC3NE.
	TIM_CCER_CC3NE = 0x4000
	// Complementary output disabled
	TIM_CCER_CC3NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC3NE_Enabled = 0x1

	// CNT: counter
	// Position of UIFCPY field.
	TIM_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM_CNT_UIFCPY = 0x80000000
	// No update occurred
	TIM_CNT_UIFCPY_NoUpdateOccurred = 0x0
	// Update interrupt pending
	TIM_CNT_UIFCPY_UpdatePending = 0x1
	// Position of CNT field.
	TIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT_CNT_Msk = 0xffff

	// PSC: prescaler
	// Position of PSC field.
	TIM_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM_PSC_PSC_Msk = 0xffff

	// ARR: auto-reload register
	// Position of ARR field.
	TIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM_ARR_ARR_Msk = 0xfffff

	// RCR: repetition counter register
	// Position of REP field.
	TIM_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM_RCR_REP_Msk = 0xffff

	// CCR1: capture/compare register
	// Position of CCR field.
	TIM_CCR_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR_CCR_Msk = 0xfffff

	// BDTR: break and dead-time register
	// Position of BK2BID field.
	TIM_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM_BDTR_BK2BID = 0x20000000
	// Position of BKBID field.
	TIM_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM_BDTR_BKBID = 0x10000000
	// Position of BK2DSRAM field.
	TIM_BDTR_BK2DSRAM_Pos = 0x1b
	// Bit mask of BK2DSRAM field.
	TIM_BDTR_BK2DSRAM_Msk = 0x8000000
	// Bit BK2DSRAM.
	TIM_BDTR_BK2DSRAM = 0x8000000
	// Position of BKDSRM field.
	TIM_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM_BDTR_BKDSRM = 0x4000000
	// Position of BKP field.
	TIM_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM_BDTR_BKP = 0x2000
	// Break input BRKx is active low
	TIM_BDTR_BKP_ActiveLow = 0x0
	// Break input BRKx is active high
	TIM_BDTR_BKP_ActiveHigh = 0x1
	// Position of BK2P field.
	TIM_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM_BDTR_BK2P = 0x2000000
	// Break input BRKx is active low
	TIM_BDTR_BK2P_ActiveLow = 0x0
	// Break input BRKx is active high
	TIM_BDTR_BK2P_ActiveHigh = 0x1
	// Position of BKE field.
	TIM_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM_BDTR_BKE = 0x1000
	// Break function x disabled
	TIM_BDTR_BKE_Disabled = 0x0
	// Break function x enabled
	TIM_BDTR_BKE_Enabled = 0x1
	// Position of BK2E field.
	TIM_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM_BDTR_BK2E = 0x1000000
	// Break function x disabled
	TIM_BDTR_BK2E_Disabled = 0x0
	// Break function x enabled
	TIM_BDTR_BK2E_Enabled = 0x1
	// Position of BK2F field.
	TIM_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM_BDTR_BK2F_Msk = 0xf00000
	// Position of BKF field.
	TIM_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM_BDTR_BKF_Msk = 0xf0000
	// Position of MOE field.
	TIM_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM_BDTR_MOE = 0x8000
	// OC/OCN are disabled or forced idle depending on OSSI
	TIM_BDTR_MOE_DisabledIdle = 0x0
	// OC/OCN are enabled if CCxE/CCxNE are set
	TIM_BDTR_MOE_Enabled = 0x1
	// Position of AOE field.
	TIM_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM_BDTR_AOE = 0x4000
	// MOE can be set only by software
	TIM_BDTR_AOE_Manual = 0x0
	// MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
	TIM_BDTR_AOE_Automatic = 0x1
	// Position of OSSR field.
	TIM_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM_BDTR_OSSR = 0x800
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSR_HiZ = 0x0
	// When inactive, OC/OCN outputs are enabled with their inactive level
	TIM_BDTR_OSSR_IdleLevel = 0x1
	// Position of OSSI field.
	TIM_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM_BDTR_OSSI = 0x400
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSI_HiZ = 0x0
	// When inactive, OC/OCN outputs are forced to idle level
	TIM_BDTR_OSSI_IdleLevel = 0x1
	// Position of LOCK field.
	TIM_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM_BDTR_LOCK_Msk = 0x300
	// No bit is write protected
	TIM_BDTR_LOCK_Off = 0x0
	// Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
	TIM_BDTR_LOCK_Level1 = 0x1
	// LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
	TIM_BDTR_LOCK_Level2 = 0x2
	// LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
	TIM_BDTR_LOCK_Level3 = 0x3
	// Position of DTG field.
	TIM_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM_BDTR_DTG_Msk = 0xff

	// CCR5: capture/compare register
	// Position of CCR field.
	TIM_CCR5_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR5_CCR_Msk = 0xfffff
	// Position of GC5C1 field.
	TIM_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM_CCR5_GC5C3 = 0x80000000

	// CCR6: capture/compare register
	// Position of CCR field.
	TIM_CCR6_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR6_CCR_Msk = 0xfffff

	// CCMR3_Output: capture/compare mode register 3
	// Position of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Pos = 0xa
	// Bit mask of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Msk = 0x400
	// Bit OC5FE.
	TIM_CCMR3_Output_OC5FE = 0x400
	// Fast output disabled
	TIM_CCMR3_Output_OC5FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR3_Output_OC5FE_Enabled = 0x1
	// Position of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Pos = 0x12
	// Bit mask of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Msk = 0x40000
	// Bit OC6FE.
	TIM_CCMR3_Output_OC6FE = 0x40000
	// Fast output disabled
	TIM_CCMR3_Output_OC6FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR3_Output_OC6FE_Enabled = 0x1
	// Position of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Pos = 0xb
	// Bit mask of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Msk = 0x800
	// Bit OC5PE.
	TIM_CCMR3_Output_OC5PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR3_Output_OC5PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR3_Output_OC5PE_Enabled = 0x1
	// Position of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Pos = 0x13
	// Bit mask of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Msk = 0x80000
	// Bit OC6PE.
	TIM_CCMR3_Output_OC6PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR3_Output_OC6PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR3_Output_OC6PE_Enabled = 0x1
	// Position of OC5M field.
	TIM_CCMR3_Output_OC5M_Pos = 0xc
	// Bit mask of OC5M field.
	TIM_CCMR3_Output_OC5M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR3_Output_OC5M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR3_Output_OC5M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR3_Output_OC5M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR3_Output_OC5M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR3_Output_OC5M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR3_Output_OC5M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR3_Output_OC5M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR3_Output_OC5M_PwmMode2 = 0x7
	// Position of OC6M field.
	TIM_CCMR3_Output_OC6M_Pos = 0x14
	// Bit mask of OC6M field.
	TIM_CCMR3_Output_OC6M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR3_Output_OC6M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR3_Output_OC6M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR3_Output_OC6M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR3_Output_OC6M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR3_Output_OC6M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR3_Output_OC6M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR3_Output_OC6M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR3_Output_OC6M_PwmMode2 = 0x7
	// Position of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Pos = 0xf
	// Bit mask of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Msk = 0x8000
	// Bit OC5CE.
	TIM_CCMR3_Output_OC5CE = 0x8000
	// OCxRef is not affected by the ocref_clr_int signal
	TIM_CCMR3_Output_OC5CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal
	TIM_CCMR3_Output_OC5CE_Enabled = 0x1
	// Position of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Pos = 0x17
	// Bit mask of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Msk = 0x800000
	// Bit OC6CE.
	TIM_CCMR3_Output_OC6CE = 0x800000
	// OCxRef is not affected by the ocref_clr_int signal
	TIM_CCMR3_Output_OC6CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal
	TIM_CCMR3_Output_OC6CE_Enabled = 0x1
	// Position of OC5M_3 field.
	TIM_CCMR3_Output_OC5M_3_Pos = 0x18
	// Bit mask of OC5M_3 field.
	TIM_CCMR3_Output_OC5M_3_Msk = 0x1000000
	// Bit OC5M_3.
	TIM_CCMR3_Output_OC5M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR3_Output_OC5M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR3_Output_OC5M_3_Extended = 0x1
	// Position of OC6M_3 field.
	TIM_CCMR3_Output_OC6M_3_Pos = 0x20
	// Bit mask of OC6M_3 field.
	TIM_CCMR3_Output_OC6M_3_Msk = 0x100000000
	// Bit OC6M_3.
	TIM_CCMR3_Output_OC6M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR3_Output_OC6M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR3_Output_OC6M_3_Extended = 0x1

	// DTR2: deadtime register 2
	// Position of DTPE field.
	TIM_DTR2_DTPE_Pos = 0x11
	// Bit mask of DTPE field.
	TIM_DTR2_DTPE_Msk = 0x20000
	// Bit DTPE.
	TIM_DTR2_DTPE = 0x20000
	// Position of DTAE field.
	TIM_DTR2_DTAE_Pos = 0x10
	// Bit mask of DTAE field.
	TIM_DTR2_DTAE_Msk = 0x10000
	// Bit DTAE.
	TIM_DTR2_DTAE = 0x10000
	// Position of DTGF field.
	TIM_DTR2_DTGF_Pos = 0x0
	// Bit mask of DTGF field.
	TIM_DTR2_DTGF_Msk = 0xff

	// ECR: encoder control register
	// Position of PWPRSC field.
	TIM_ECR_PWPRSC_Pos = 0x18
	// Bit mask of PWPRSC field.
	TIM_ECR_PWPRSC_Msk = 0x7000000
	// Position of PW field.
	TIM_ECR_PW_Pos = 0x10
	// Bit mask of PW field.
	TIM_ECR_PW_Msk = 0xff0000
	// Position of IPOS field.
	TIM_ECR_IPOS_Pos = 0x6
	// Bit mask of IPOS field.
	TIM_ECR_IPOS_Msk = 0xc0
	// Position of FIDX field.
	TIM_ECR_FIDX_Pos = 0x5
	// Bit mask of FIDX field.
	TIM_ECR_FIDX_Msk = 0x20
	// Bit FIDX.
	TIM_ECR_FIDX = 0x20
	// Position of IDIR field.
	TIM_ECR_IDIR_Pos = 0x1
	// Bit mask of IDIR field.
	TIM_ECR_IDIR_Msk = 0x6
	// Position of IE field.
	TIM_ECR_IE_Pos = 0x0
	// Bit mask of IE field.
	TIM_ECR_IE_Msk = 0x1
	// Bit IE.
	TIM_ECR_IE = 0x1

	// TISEL: timer input selection register
	// Position of TI4SEL field.
	TIM_TISEL_TI4SEL_Pos = 0x18
	// Bit mask of TI4SEL field.
	TIM_TISEL_TI4SEL_Msk = 0xf000000
	// Position of TI3SEL field.
	TIM_TISEL_TI3SEL_Pos = 0x10
	// Bit mask of TI3SEL field.
	TIM_TISEL_TI3SEL_Msk = 0xf0000
	// Position of TI2SEL field.
	TIM_TISEL_TI2SEL_Pos = 0x8
	// Bit mask of TI2SEL field.
	TIM_TISEL_TI2SEL_Msk = 0xf00
	// Position of TI1SEL field.
	TIM_TISEL_TI1SEL_Pos = 0x0
	// Bit mask of TI1SEL field.
	TIM_TISEL_TI1SEL_Msk = 0xf

	// AF1: alternate function option register 1
	// Position of ETRSEL field.
	TIM_AF1_ETRSEL_Pos = 0xe
	// Bit mask of ETRSEL field.
	TIM_AF1_ETRSEL_Msk = 0x3c000
	// Position of BKCMP4P field.
	TIM_AF1_BKCMP4P_Pos = 0xd
	// Bit mask of BKCMP4P field.
	TIM_AF1_BKCMP4P_Msk = 0x2000
	// Bit BKCMP4P.
	TIM_AF1_BKCMP4P = 0x2000
	// Position of BKCMP3P field.
	TIM_AF1_BKCMP3P_Pos = 0xc
	// Bit mask of BKCMP3P field.
	TIM_AF1_BKCMP3P_Msk = 0x1000
	// Bit BKCMP3P.
	TIM_AF1_BKCMP3P = 0x1000
	// Position of BKCMP2P field.
	TIM_AF1_BKCMP2P_Pos = 0xb
	// Bit mask of BKCMP2P field.
	TIM_AF1_BKCMP2P_Msk = 0x800
	// Bit BKCMP2P.
	TIM_AF1_BKCMP2P = 0x800
	// Position of BKCMP1P field.
	TIM_AF1_BKCMP1P_Pos = 0xa
	// Bit mask of BKCMP1P field.
	TIM_AF1_BKCMP1P_Msk = 0x400
	// Bit BKCMP1P.
	TIM_AF1_BKCMP1P = 0x400
	// Position of BKINP field.
	TIM_AF1_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIM_AF1_BKINP_Msk = 0x200
	// Bit BKINP.
	TIM_AF1_BKINP = 0x200
	// Position of BKCMP8E field.
	TIM_AF1_BKCMP8E_Pos = 0x8
	// Bit mask of BKCMP8E field.
	TIM_AF1_BKCMP8E_Msk = 0x100
	// Bit BKCMP8E.
	TIM_AF1_BKCMP8E = 0x100
	// Position of BKCMP7E field.
	TIM_AF1_BKCMP7E_Pos = 0x7
	// Bit mask of BKCMP7E field.
	TIM_AF1_BKCMP7E_Msk = 0x80
	// Bit BKCMP7E.
	TIM_AF1_BKCMP7E = 0x80
	// Position of BKCMP6E field.
	TIM_AF1_BKCMP6E_Pos = 0x6
	// Bit mask of BKCMP6E field.
	TIM_AF1_BKCMP6E_Msk = 0x40
	// Bit BKCMP6E.
	TIM_AF1_BKCMP6E = 0x40
	// Position of BKCMP5E field.
	TIM_AF1_BKCMP5E_Pos = 0x5
	// Bit mask of BKCMP5E field.
	TIM_AF1_BKCMP5E_Msk = 0x20
	// Bit BKCMP5E.
	TIM_AF1_BKCMP5E = 0x20
	// Position of BKCMP4E field.
	TIM_AF1_BKCMP4E_Pos = 0x4
	// Bit mask of BKCMP4E field.
	TIM_AF1_BKCMP4E_Msk = 0x10
	// Bit BKCMP4E.
	TIM_AF1_BKCMP4E = 0x10
	// Position of BKCMP3E field.
	TIM_AF1_BKCMP3E_Pos = 0x3
	// Bit mask of BKCMP3E field.
	TIM_AF1_BKCMP3E_Msk = 0x8
	// Bit BKCMP3E.
	TIM_AF1_BKCMP3E = 0x8
	// Position of BKCMP2E field.
	TIM_AF1_BKCMP2E_Pos = 0x2
	// Bit mask of BKCMP2E field.
	TIM_AF1_BKCMP2E_Msk = 0x4
	// Bit BKCMP2E.
	TIM_AF1_BKCMP2E = 0x4
	// Position of BKCMP1E field.
	TIM_AF1_BKCMP1E_Pos = 0x1
	// Bit mask of BKCMP1E field.
	TIM_AF1_BKCMP1E_Msk = 0x2
	// Bit BKCMP1E.
	TIM_AF1_BKCMP1E = 0x2
	// Position of BKINE field.
	TIM_AF1_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIM_AF1_BKINE_Msk = 0x1
	// Bit BKINE.
	TIM_AF1_BKINE = 0x1

	// AF2: alternate function register 2
	// Position of OCRSEL field.
	TIM_AF2_OCRSEL_Pos = 0x10
	// Bit mask of OCRSEL field.
	TIM_AF2_OCRSEL_Msk = 0x70000
	// Position of BK2CMP4P field.
	TIM_AF2_BK2CMP4P_Pos = 0xd
	// Bit mask of BK2CMP4P field.
	TIM_AF2_BK2CMP4P_Msk = 0x2000
	// Bit BK2CMP4P.
	TIM_AF2_BK2CMP4P = 0x2000
	// Position of BK2CMP3P field.
	TIM_AF2_BK2CMP3P_Pos = 0xc
	// Bit mask of BK2CMP3P field.
	TIM_AF2_BK2CMP3P_Msk = 0x1000
	// Bit BK2CMP3P.
	TIM_AF2_BK2CMP3P = 0x1000
	// Position of BK2CMP2P field.
	TIM_AF2_BK2CMP2P_Pos = 0xb
	// Bit mask of BK2CMP2P field.
	TIM_AF2_BK2CMP2P_Msk = 0x800
	// Bit BK2CMP2P.
	TIM_AF2_BK2CMP2P = 0x800
	// Position of BK2CMP1P field.
	TIM_AF2_BK2CMP1P_Pos = 0xa
	// Bit mask of BK2CMP1P field.
	TIM_AF2_BK2CMP1P_Msk = 0x400
	// Bit BK2CMP1P.
	TIM_AF2_BK2CMP1P = 0x400
	// Position of BK2INP field.
	TIM_AF2_BK2INP_Pos = 0x9
	// Bit mask of BK2INP field.
	TIM_AF2_BK2INP_Msk = 0x200
	// Bit BK2INP.
	TIM_AF2_BK2INP = 0x200
	// Position of BK2CMP8E field.
	TIM_AF2_BK2CMP8E_Pos = 0x8
	// Bit mask of BK2CMP8E field.
	TIM_AF2_BK2CMP8E_Msk = 0x100
	// Bit BK2CMP8E.
	TIM_AF2_BK2CMP8E = 0x100
	// Position of BK2CMP7E field.
	TIM_AF2_BK2CMP7E_Pos = 0x7
	// Bit mask of BK2CMP7E field.
	TIM_AF2_BK2CMP7E_Msk = 0x80
	// Bit BK2CMP7E.
	TIM_AF2_BK2CMP7E = 0x80
	// Position of BK2CMP6E field.
	TIM_AF2_BK2CMP6E_Pos = 0x6
	// Bit mask of BK2CMP6E field.
	TIM_AF2_BK2CMP6E_Msk = 0x40
	// Bit BK2CMP6E.
	TIM_AF2_BK2CMP6E = 0x40
	// Position of BK2CMP5E field.
	TIM_AF2_BK2CMP5E_Pos = 0x5
	// Bit mask of BK2CMP5E field.
	TIM_AF2_BK2CMP5E_Msk = 0x20
	// Bit BK2CMP5E.
	TIM_AF2_BK2CMP5E = 0x20
	// Position of BK2CMP4E field.
	TIM_AF2_BK2CMP4E_Pos = 0x4
	// Bit mask of BK2CMP4E field.
	TIM_AF2_BK2CMP4E_Msk = 0x10
	// Bit BK2CMP4E.
	TIM_AF2_BK2CMP4E = 0x10
	// Position of BK2CMP3E field.
	TIM_AF2_BK2CMP3E_Pos = 0x3
	// Bit mask of BK2CMP3E field.
	TIM_AF2_BK2CMP3E_Msk = 0x8
	// Bit BK2CMP3E.
	TIM_AF2_BK2CMP3E = 0x8
	// Position of BK2CMP2E field.
	TIM_AF2_BK2CMP2E_Pos = 0x2
	// Bit mask of BK2CMP2E field.
	TIM_AF2_BK2CMP2E_Msk = 0x4
	// Bit BK2CMP2E.
	TIM_AF2_BK2CMP2E = 0x4
	// Position of BK2CMP1E field.
	TIM_AF2_BK2CMP1E_Pos = 0x1
	// Bit mask of BK2CMP1E field.
	TIM_AF2_BK2CMP1E_Msk = 0x2
	// Bit BK2CMP1E.
	TIM_AF2_BK2CMP1E = 0x2
	// Position of BK2INE field.
	TIM_AF2_BK2INE_Pos = 0x0
	// Bit mask of BK2INE field.
	TIM_AF2_BK2INE_Msk = 0x1
	// Bit BK2INE.
	TIM_AF2_BK2INE = 0x1

	// DCR: DMA control register
	// Position of DBSS field.
	TIM_DCR_DBSS_Pos = 0x10
	// Bit mask of DBSS field.
	TIM_DCR_DBSS_Msk = 0xf0000
	// Position of DBL field.
	TIM_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM_DCR_DBL_Msk = 0x1f00
	// Position of DBA field.
	TIM_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM_DCR_DBA_Msk = 0x1f

	// DMAR: DMA address for full transfer
	// Position of DMAB field.
	TIM_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM_DMAR_DMAB_Msk = 0xffffffff
)

// Constants for TSC: Touch sensing controller
const (
	// CR: control register
	// Position of CTPH field.
	TSC_CR_CTPH_Pos = 0x1c
	// Bit mask of CTPH field.
	TSC_CR_CTPH_Msk = 0xf0000000
	// Position of CTPL field.
	TSC_CR_CTPL_Pos = 0x18
	// Bit mask of CTPL field.
	TSC_CR_CTPL_Msk = 0xf000000
	// Position of SSD field.
	TSC_CR_SSD_Pos = 0x11
	// Bit mask of SSD field.
	TSC_CR_SSD_Msk = 0xfe0000
	// Position of SSE field.
	TSC_CR_SSE_Pos = 0x10
	// Bit mask of SSE field.
	TSC_CR_SSE_Msk = 0x10000
	// Bit SSE.
	TSC_CR_SSE = 0x10000
	// Spread spectrum disabled
	TSC_CR_SSE_Disabled = 0x0
	// Spread spectrum enabled
	TSC_CR_SSE_Enabled = 0x1
	// Position of SSPSC field.
	TSC_CR_SSPSC_Pos = 0xf
	// Bit mask of SSPSC field.
	TSC_CR_SSPSC_Msk = 0x8000
	// Bit SSPSC.
	TSC_CR_SSPSC = 0x8000
	// Position of PGPSC field.
	TSC_CR_PGPSC_Pos = 0xc
	// Bit mask of PGPSC field.
	TSC_CR_PGPSC_Msk = 0x7000
	// Position of MCV field.
	TSC_CR_MCV_Pos = 0x5
	// Bit mask of MCV field.
	TSC_CR_MCV_Msk = 0xe0
	// Position of IODEF field.
	TSC_CR_IODEF_Pos = 0x4
	// Bit mask of IODEF field.
	TSC_CR_IODEF_Msk = 0x10
	// Bit IODEF.
	TSC_CR_IODEF = 0x10
	// I/Os are forced to output push-pull low
	TSC_CR_IODEF_PushPull = 0x0
	// I/Os are in input floating
	TSC_CR_IODEF_Floating = 0x1
	// Position of SYNCPOL field.
	TSC_CR_SYNCPOL_Pos = 0x3
	// Bit mask of SYNCPOL field.
	TSC_CR_SYNCPOL_Msk = 0x8
	// Bit SYNCPOL.
	TSC_CR_SYNCPOL = 0x8
	// Falling edge only
	TSC_CR_SYNCPOL_FallingEdge = 0x0
	// Rising edge and high level
	TSC_CR_SYNCPOL_RisingEdge = 0x1
	// Position of AM field.
	TSC_CR_AM_Pos = 0x2
	// Bit mask of AM field.
	TSC_CR_AM_Msk = 0x4
	// Bit AM.
	TSC_CR_AM = 0x4
	// Normal acquisition mode (acquisition starts as soon as START bit is set)
	TSC_CR_AM_Normal = 0x0
	// Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin)
	TSC_CR_AM_Synchronized = 0x1
	// Position of START field.
	TSC_CR_START_Pos = 0x1
	// Bit mask of START field.
	TSC_CR_START_Msk = 0x2
	// Bit START.
	TSC_CR_START = 0x2
	// Acquisition not started
	TSC_CR_START_NoStarted = 0x0
	// Start a new acquisition
	TSC_CR_START_Started = 0x1
	// Position of TSCE field.
	TSC_CR_TSCE_Pos = 0x0
	// Bit mask of TSCE field.
	TSC_CR_TSCE_Msk = 0x1
	// Bit TSCE.
	TSC_CR_TSCE = 0x1
	// Touch sensing controller disabled
	TSC_CR_TSCE_Disabled = 0x0
	// Touch sensing controller enabled
	TSC_CR_TSCE_Enabled = 0x1

	// IER: interrupt enable register
	// Position of MCEIE field.
	TSC_IER_MCEIE_Pos = 0x1
	// Bit mask of MCEIE field.
	TSC_IER_MCEIE_Msk = 0x2
	// Bit MCEIE.
	TSC_IER_MCEIE = 0x2
	// Max count error interrupt disabled
	TSC_IER_MCEIE_Disabled = 0x0
	// Max count error interrupt enabled
	TSC_IER_MCEIE_Enabled = 0x1
	// Position of EOAIE field.
	TSC_IER_EOAIE_Pos = 0x0
	// Bit mask of EOAIE field.
	TSC_IER_EOAIE_Msk = 0x1
	// Bit EOAIE.
	TSC_IER_EOAIE = 0x1
	// End of acquisition interrupt disabled
	TSC_IER_EOAIE_Disabled = 0x0
	// End of acquisition interrupt enabled
	TSC_IER_EOAIE_Enabled = 0x1

	// ICR: interrupt clear register
	// Position of MCEIC field.
	TSC_ICR_MCEIC_Pos = 0x1
	// Bit mask of MCEIC field.
	TSC_ICR_MCEIC_Msk = 0x2
	// Bit MCEIC.
	TSC_ICR_MCEIC = 0x2
	// Position of EOAIC field.
	TSC_ICR_EOAIC_Pos = 0x0
	// Bit mask of EOAIC field.
	TSC_ICR_EOAIC_Msk = 0x1
	// Bit EOAIC.
	TSC_ICR_EOAIC = 0x1

	// ISR: interrupt status register
	// Position of MCEF field.
	TSC_ISR_MCEF_Pos = 0x1
	// Bit mask of MCEF field.
	TSC_ISR_MCEF_Msk = 0x2
	// Bit MCEF.
	TSC_ISR_MCEF = 0x2
	// Position of EOAF field.
	TSC_ISR_EOAF_Pos = 0x0
	// Bit mask of EOAF field.
	TSC_ISR_EOAF_Msk = 0x1
	// Bit EOAF.
	TSC_ISR_EOAF = 0x1

	// IOHCR: I/O hysteresis control register
	// Position of G1_IO1 field.
	TSC_IOHCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOHCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOHCR_G1_IO1 = 0x10
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOHCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOHCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOHCR_G2_IO1 = 0x100
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOHCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOHCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOHCR_G3_IO1 = 0x1000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOHCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOHCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOHCR_G4_IO1 = 0x10000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOHCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOHCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOHCR_G5_IO1 = 0x100000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOHCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOHCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOHCR_G6_IO1 = 0x1000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOHCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOHCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOHCR_G7_IO1 = 0x10000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOHCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOHCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOHCR_G8_IO1 = 0x100000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOHCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOHCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOHCR_G1_IO4 = 0x80
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOHCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOHCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOHCR_G2_IO4 = 0x800
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOHCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOHCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOHCR_G3_IO4 = 0x8000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOHCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOHCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOHCR_G4_IO4 = 0x80000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOHCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOHCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOHCR_G5_IO4 = 0x800000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOHCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOHCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOHCR_G6_IO4 = 0x8000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOHCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOHCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOHCR_G7_IO4 = 0x80000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOHCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOHCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOHCR_G8_IO4 = 0x800000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOHCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOHCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOHCR_G1_IO3 = 0x40
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOHCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOHCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOHCR_G2_IO3 = 0x400
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOHCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOHCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOHCR_G3_IO3 = 0x4000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOHCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOHCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOHCR_G4_IO3 = 0x40000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOHCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOHCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOHCR_G5_IO3 = 0x400000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOHCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOHCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOHCR_G6_IO3 = 0x4000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOHCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOHCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOHCR_G7_IO3 = 0x40000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOHCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOHCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOHCR_G8_IO3 = 0x400000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOHCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOHCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOHCR_G1_IO2 = 0x20
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOHCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOHCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOHCR_G2_IO2 = 0x200
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOHCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOHCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOHCR_G3_IO2 = 0x2000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOHCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOHCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOHCR_G4_IO2 = 0x20000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOHCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOHCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOHCR_G5_IO2 = 0x200000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOHCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOHCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOHCR_G6_IO2 = 0x2000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOHCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOHCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOHCR_G7_IO2 = 0x20000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOHCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOHCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOHCR_G8_IO2 = 0x200000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO2_Enabled = 0x1

	// IOASCR: I/O analog switch control register
	// Position of G1_IO1 field.
	TSC_IOASCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOASCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOASCR_G1_IO1 = 0x10
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOASCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOASCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOASCR_G2_IO1 = 0x100
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOASCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOASCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOASCR_G3_IO1 = 0x1000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOASCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOASCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOASCR_G4_IO1 = 0x10000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOASCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOASCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOASCR_G5_IO1 = 0x100000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOASCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOASCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOASCR_G6_IO1 = 0x1000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOASCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOASCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOASCR_G7_IO1 = 0x10000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOASCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOASCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOASCR_G8_IO1 = 0x100000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOASCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOASCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOASCR_G1_IO4 = 0x80
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOASCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOASCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOASCR_G2_IO4 = 0x800
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOASCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOASCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOASCR_G3_IO4 = 0x8000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOASCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOASCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOASCR_G4_IO4 = 0x80000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOASCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOASCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOASCR_G5_IO4 = 0x800000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOASCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOASCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOASCR_G6_IO4 = 0x8000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOASCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOASCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOASCR_G7_IO4 = 0x80000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOASCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOASCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOASCR_G8_IO4 = 0x800000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOASCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOASCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOASCR_G1_IO3 = 0x40
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOASCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOASCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOASCR_G2_IO3 = 0x400
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOASCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOASCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOASCR_G3_IO3 = 0x4000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOASCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOASCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOASCR_G4_IO3 = 0x40000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOASCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOASCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOASCR_G5_IO3 = 0x400000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOASCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOASCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOASCR_G6_IO3 = 0x4000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOASCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOASCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOASCR_G7_IO3 = 0x40000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOASCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOASCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOASCR_G8_IO3 = 0x400000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOASCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOASCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOASCR_G1_IO2 = 0x20
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOASCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOASCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOASCR_G2_IO2 = 0x200
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOASCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOASCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOASCR_G3_IO2 = 0x2000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOASCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOASCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOASCR_G4_IO2 = 0x20000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOASCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOASCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOASCR_G5_IO2 = 0x200000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOASCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOASCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOASCR_G6_IO2 = 0x2000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOASCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOASCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOASCR_G7_IO2 = 0x20000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOASCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOASCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOASCR_G8_IO2 = 0x200000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO2_Enabled = 0x1

	// IOSCR: I/O sampling control register
	// Position of G1_IO1 field.
	TSC_IOSCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOSCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOSCR_G1_IO1 = 0x10
	// Gx_IOy unused
	TSC_IOSCR_G1_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOSCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOSCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOSCR_G2_IO1 = 0x100
	// Gx_IOy unused
	TSC_IOSCR_G2_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOSCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOSCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOSCR_G3_IO1 = 0x1000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOSCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOSCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOSCR_G4_IO1 = 0x10000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOSCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOSCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOSCR_G5_IO1 = 0x100000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOSCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOSCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOSCR_G6_IO1 = 0x1000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOSCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOSCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOSCR_G7_IO1 = 0x10000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOSCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOSCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOSCR_G8_IO1 = 0x100000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOSCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOSCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOSCR_G1_IO4 = 0x80
	// Gx_IOy unused
	TSC_IOSCR_G1_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOSCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOSCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOSCR_G2_IO4 = 0x800
	// Gx_IOy unused
	TSC_IOSCR_G2_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOSCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOSCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOSCR_G3_IO4 = 0x8000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOSCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOSCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOSCR_G4_IO4 = 0x80000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOSCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOSCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOSCR_G5_IO4 = 0x800000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOSCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOSCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOSCR_G6_IO4 = 0x8000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOSCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOSCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOSCR_G7_IO4 = 0x80000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOSCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOSCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOSCR_G8_IO4 = 0x800000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOSCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOSCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOSCR_G1_IO3 = 0x40
	// Gx_IOy unused
	TSC_IOSCR_G1_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOSCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOSCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOSCR_G2_IO3 = 0x400
	// Gx_IOy unused
	TSC_IOSCR_G2_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOSCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOSCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOSCR_G3_IO3 = 0x4000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOSCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOSCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOSCR_G4_IO3 = 0x40000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOSCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOSCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOSCR_G5_IO3 = 0x400000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOSCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOSCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOSCR_G6_IO3 = 0x4000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOSCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOSCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOSCR_G7_IO3 = 0x40000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOSCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOSCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOSCR_G8_IO3 = 0x400000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOSCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOSCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOSCR_G1_IO2 = 0x20
	// Gx_IOy unused
	TSC_IOSCR_G1_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOSCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOSCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOSCR_G2_IO2 = 0x200
	// Gx_IOy unused
	TSC_IOSCR_G2_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOSCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOSCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOSCR_G3_IO2 = 0x2000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOSCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOSCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOSCR_G4_IO2 = 0x20000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOSCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOSCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOSCR_G5_IO2 = 0x200000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOSCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOSCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOSCR_G6_IO2 = 0x2000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOSCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOSCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOSCR_G7_IO2 = 0x20000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOSCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOSCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOSCR_G8_IO2 = 0x200000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO2_Enabled = 0x1

	// IOCCR: I/O channel control register
	// Position of G1_IO1 field.
	TSC_IOCCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOCCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOCCR_G1_IO1 = 0x10
	// Gx_IOy unused
	TSC_IOCCR_G1_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOCCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOCCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOCCR_G2_IO1 = 0x100
	// Gx_IOy unused
	TSC_IOCCR_G2_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOCCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOCCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOCCR_G3_IO1 = 0x1000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOCCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOCCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOCCR_G4_IO1 = 0x10000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOCCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOCCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOCCR_G5_IO1 = 0x100000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOCCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOCCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOCCR_G6_IO1 = 0x1000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOCCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOCCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOCCR_G7_IO1 = 0x10000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOCCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOCCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOCCR_G8_IO1 = 0x100000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOCCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOCCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOCCR_G1_IO4 = 0x80
	// Gx_IOy unused
	TSC_IOCCR_G1_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOCCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOCCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOCCR_G2_IO4 = 0x800
	// Gx_IOy unused
	TSC_IOCCR_G2_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOCCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOCCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOCCR_G3_IO4 = 0x8000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOCCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOCCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOCCR_G4_IO4 = 0x80000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOCCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOCCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOCCR_G5_IO4 = 0x800000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOCCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOCCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOCCR_G6_IO4 = 0x8000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOCCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOCCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOCCR_G7_IO4 = 0x80000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOCCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOCCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOCCR_G8_IO4 = 0x800000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOCCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOCCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOCCR_G1_IO3 = 0x40
	// Gx_IOy unused
	TSC_IOCCR_G1_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOCCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOCCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOCCR_G2_IO3 = 0x400
	// Gx_IOy unused
	TSC_IOCCR_G2_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOCCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOCCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOCCR_G3_IO3 = 0x4000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOCCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOCCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOCCR_G4_IO3 = 0x40000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOCCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOCCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOCCR_G5_IO3 = 0x400000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOCCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOCCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOCCR_G6_IO3 = 0x4000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOCCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOCCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOCCR_G7_IO3 = 0x40000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOCCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOCCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOCCR_G8_IO3 = 0x400000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOCCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOCCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOCCR_G1_IO2 = 0x20
	// Gx_IOy unused
	TSC_IOCCR_G1_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOCCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOCCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOCCR_G2_IO2 = 0x200
	// Gx_IOy unused
	TSC_IOCCR_G2_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOCCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOCCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOCCR_G3_IO2 = 0x2000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOCCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOCCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOCCR_G4_IO2 = 0x20000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOCCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOCCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOCCR_G5_IO2 = 0x200000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOCCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOCCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOCCR_G6_IO2 = 0x2000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOCCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOCCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOCCR_G7_IO2 = 0x20000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOCCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOCCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOCCR_G8_IO2 = 0x200000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO2_Enabled = 0x1

	// IOGCSR: I/O group control status register
	// Position of G1S field.
	TSC_IOGCSR_G1S_Pos = 0x11
	// Bit mask of G1S field.
	TSC_IOGCSR_G1S_Msk = 0x20000
	// Bit G1S.
	TSC_IOGCSR_G1S = 0x20000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G1S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G1S_Complete = 0x1
	// Position of G2S field.
	TSC_IOGCSR_G2S_Pos = 0x12
	// Bit mask of G2S field.
	TSC_IOGCSR_G2S_Msk = 0x40000
	// Bit G2S.
	TSC_IOGCSR_G2S = 0x40000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G2S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G2S_Complete = 0x1
	// Position of G3S field.
	TSC_IOGCSR_G3S_Pos = 0x13
	// Bit mask of G3S field.
	TSC_IOGCSR_G3S_Msk = 0x80000
	// Bit G3S.
	TSC_IOGCSR_G3S = 0x80000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G3S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G3S_Complete = 0x1
	// Position of G4S field.
	TSC_IOGCSR_G4S_Pos = 0x14
	// Bit mask of G4S field.
	TSC_IOGCSR_G4S_Msk = 0x100000
	// Bit G4S.
	TSC_IOGCSR_G4S = 0x100000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G4S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G4S_Complete = 0x1
	// Position of G5S field.
	TSC_IOGCSR_G5S_Pos = 0x15
	// Bit mask of G5S field.
	TSC_IOGCSR_G5S_Msk = 0x200000
	// Bit G5S.
	TSC_IOGCSR_G5S = 0x200000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G5S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G5S_Complete = 0x1
	// Position of G6S field.
	TSC_IOGCSR_G6S_Pos = 0x16
	// Bit mask of G6S field.
	TSC_IOGCSR_G6S_Msk = 0x400000
	// Bit G6S.
	TSC_IOGCSR_G6S = 0x400000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G6S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G6S_Complete = 0x1
	// Position of G7S field.
	TSC_IOGCSR_G7S_Pos = 0x17
	// Bit mask of G7S field.
	TSC_IOGCSR_G7S_Msk = 0x800000
	// Bit G7S.
	TSC_IOGCSR_G7S = 0x800000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G7S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G7S_Complete = 0x1
	// Position of G8S field.
	TSC_IOGCSR_G8S_Pos = 0x18
	// Bit mask of G8S field.
	TSC_IOGCSR_G8S_Msk = 0x1000000
	// Bit G8S.
	TSC_IOGCSR_G8S = 0x1000000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G8S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G8S_Complete = 0x1
	// Position of G1E field.
	TSC_IOGCSR_G1E_Pos = 0x1
	// Bit mask of G1E field.
	TSC_IOGCSR_G1E_Msk = 0x2
	// Bit G1E.
	TSC_IOGCSR_G1E = 0x2
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G1E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G1E_Enabled = 0x1
	// Position of G2E field.
	TSC_IOGCSR_G2E_Pos = 0x2
	// Bit mask of G2E field.
	TSC_IOGCSR_G2E_Msk = 0x4
	// Bit G2E.
	TSC_IOGCSR_G2E = 0x4
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G2E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G2E_Enabled = 0x1
	// Position of G3E field.
	TSC_IOGCSR_G3E_Pos = 0x3
	// Bit mask of G3E field.
	TSC_IOGCSR_G3E_Msk = 0x8
	// Bit G3E.
	TSC_IOGCSR_G3E = 0x8
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G3E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G3E_Enabled = 0x1
	// Position of G4E field.
	TSC_IOGCSR_G4E_Pos = 0x4
	// Bit mask of G4E field.
	TSC_IOGCSR_G4E_Msk = 0x10
	// Bit G4E.
	TSC_IOGCSR_G4E = 0x10
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G4E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G4E_Enabled = 0x1
	// Position of G5E field.
	TSC_IOGCSR_G5E_Pos = 0x5
	// Bit mask of G5E field.
	TSC_IOGCSR_G5E_Msk = 0x20
	// Bit G5E.
	TSC_IOGCSR_G5E = 0x20
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G5E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G5E_Enabled = 0x1
	// Position of G6E field.
	TSC_IOGCSR_G6E_Pos = 0x6
	// Bit mask of G6E field.
	TSC_IOGCSR_G6E_Msk = 0x40
	// Bit G6E.
	TSC_IOGCSR_G6E = 0x40
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G6E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G6E_Enabled = 0x1
	// Position of G7E field.
	TSC_IOGCSR_G7E_Pos = 0x7
	// Bit mask of G7E field.
	TSC_IOGCSR_G7E_Msk = 0x80
	// Bit G7E.
	TSC_IOGCSR_G7E = 0x80
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G7E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G7E_Enabled = 0x1
	// Position of G8E field.
	TSC_IOGCSR_G8E_Pos = 0x8
	// Bit mask of G8E field.
	TSC_IOGCSR_G8E_Msk = 0x100
	// Bit G8E.
	TSC_IOGCSR_G8E = 0x100
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G8E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G8E_Enabled = 0x1

	// IOG1CR: I/O group x counter register
	// Position of CNT field.
	TSC_IOGCR_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TSC_IOGCR_CNT_Msk = 0x3fff
)

// Constants for UCPD1: USB Power Delivery interface
const (
	// CFGR1: UCPD configuration register 1
	// Position of HBITCLKDIV field.
	UCPD_CFGR1_HBITCLKDIV_Pos = 0x0
	// Bit mask of HBITCLKDIV field.
	UCPD_CFGR1_HBITCLKDIV_Msk = 0x3f
	// Position of IFRGAP field.
	UCPD_CFGR1_IFRGAP_Pos = 0x6
	// Bit mask of IFRGAP field.
	UCPD_CFGR1_IFRGAP_Msk = 0x7c0
	// Position of TRANSWIN field.
	UCPD_CFGR1_TRANSWIN_Pos = 0xb
	// Bit mask of TRANSWIN field.
	UCPD_CFGR1_TRANSWIN_Msk = 0xf800
	// Position of PSC_USBPDCLK field.
	UCPD_CFGR1_PSC_USBPDCLK_Pos = 0x11
	// Bit mask of PSC_USBPDCLK field.
	UCPD_CFGR1_PSC_USBPDCLK_Msk = 0xe0000
	// Divide by 1
	UCPD_CFGR1_PSC_USBPDCLK_Div1 = 0x0
	// Divide by 2
	UCPD_CFGR1_PSC_USBPDCLK_Div2 = 0x1
	// Divide by 4
	UCPD_CFGR1_PSC_USBPDCLK_Div4 = 0x2
	// Divide by 8
	UCPD_CFGR1_PSC_USBPDCLK_Div8 = 0x3
	// Divide by 16
	UCPD_CFGR1_PSC_USBPDCLK_Div16 = 0x4
	// Position of TXDMAEN field.
	UCPD_CFGR1_TXDMAEN_Pos = 0x1d
	// Bit mask of TXDMAEN field.
	UCPD_CFGR1_TXDMAEN_Msk = 0x20000000
	// Bit TXDMAEN.
	UCPD_CFGR1_TXDMAEN = 0x20000000
	// DMA mode for transmission disabled
	UCPD_CFGR1_TXDMAEN_Disabled = 0x0
	// DMA mode for transmission enabled
	UCPD_CFGR1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	UCPD_CFGR1_RXDMAEN_Pos = 0x1e
	// Bit mask of RXDMAEN field.
	UCPD_CFGR1_RXDMAEN_Msk = 0x40000000
	// Bit RXDMAEN.
	UCPD_CFGR1_RXDMAEN = 0x40000000
	// DMA mode for reception disabled
	UCPD_CFGR1_RXDMAEN_Disabled = 0x0
	// DMA mode for reception enabled
	UCPD_CFGR1_RXDMAEN_Enabled = 0x1
	// Position of UCPDEN field.
	UCPD_CFGR1_UCPDEN_Pos = 0x1f
	// Bit mask of UCPDEN field.
	UCPD_CFGR1_UCPDEN_Msk = 0x80000000
	// Bit UCPDEN.
	UCPD_CFGR1_UCPDEN = 0x80000000
	// UCPD peripheral disabled
	UCPD_CFGR1_UCPDEN_Disabled = 0x0
	// UCPD peripheral enabled
	UCPD_CFGR1_UCPDEN_Enabled = 0x1
	// Position of RXORDSETEN0 field.
	UCPD_CFGR1_RXORDSETEN0_Pos = 0x14
	// Bit mask of RXORDSETEN0 field.
	UCPD_CFGR1_RXORDSETEN0_Msk = 0x100000
	// Bit RXORDSETEN0.
	UCPD_CFGR1_RXORDSETEN0 = 0x100000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN0_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN0_Enabled = 0x1
	// Position of RXORDSETEN1 field.
	UCPD_CFGR1_RXORDSETEN1_Pos = 0x15
	// Bit mask of RXORDSETEN1 field.
	UCPD_CFGR1_RXORDSETEN1_Msk = 0x200000
	// Bit RXORDSETEN1.
	UCPD_CFGR1_RXORDSETEN1 = 0x200000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN1_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN1_Enabled = 0x1
	// Position of RXORDSETEN2 field.
	UCPD_CFGR1_RXORDSETEN2_Pos = 0x16
	// Bit mask of RXORDSETEN2 field.
	UCPD_CFGR1_RXORDSETEN2_Msk = 0x400000
	// Bit RXORDSETEN2.
	UCPD_CFGR1_RXORDSETEN2 = 0x400000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN2_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN2_Enabled = 0x1
	// Position of RXORDSETEN3 field.
	UCPD_CFGR1_RXORDSETEN3_Pos = 0x17
	// Bit mask of RXORDSETEN3 field.
	UCPD_CFGR1_RXORDSETEN3_Msk = 0x800000
	// Bit RXORDSETEN3.
	UCPD_CFGR1_RXORDSETEN3 = 0x800000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN3_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN3_Enabled = 0x1
	// Position of RXORDSETEN4 field.
	UCPD_CFGR1_RXORDSETEN4_Pos = 0x18
	// Bit mask of RXORDSETEN4 field.
	UCPD_CFGR1_RXORDSETEN4_Msk = 0x1000000
	// Bit RXORDSETEN4.
	UCPD_CFGR1_RXORDSETEN4 = 0x1000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN4_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN4_Enabled = 0x1
	// Position of RXORDSETEN5 field.
	UCPD_CFGR1_RXORDSETEN5_Pos = 0x19
	// Bit mask of RXORDSETEN5 field.
	UCPD_CFGR1_RXORDSETEN5_Msk = 0x2000000
	// Bit RXORDSETEN5.
	UCPD_CFGR1_RXORDSETEN5 = 0x2000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN5_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN5_Enabled = 0x1
	// Position of RXORDSETEN6 field.
	UCPD_CFGR1_RXORDSETEN6_Pos = 0x1a
	// Bit mask of RXORDSETEN6 field.
	UCPD_CFGR1_RXORDSETEN6_Msk = 0x4000000
	// Bit RXORDSETEN6.
	UCPD_CFGR1_RXORDSETEN6 = 0x4000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN6_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN6_Enabled = 0x1
	// Position of RXORDSETEN7 field.
	UCPD_CFGR1_RXORDSETEN7_Pos = 0x1b
	// Bit mask of RXORDSETEN7 field.
	UCPD_CFGR1_RXORDSETEN7_Msk = 0x8000000
	// Bit RXORDSETEN7.
	UCPD_CFGR1_RXORDSETEN7 = 0x8000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN7_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN7_Enabled = 0x1
	// Position of RXORDSETEN8 field.
	UCPD_CFGR1_RXORDSETEN8_Pos = 0x1c
	// Bit mask of RXORDSETEN8 field.
	UCPD_CFGR1_RXORDSETEN8_Msk = 0x10000000
	// Bit RXORDSETEN8.
	UCPD_CFGR1_RXORDSETEN8 = 0x10000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN8_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN8_Enabled = 0x1

	// CFGR2: UCPD configuration register 2
	// Position of RXFILTDIS field.
	UCPD_CFGR2_RXFILTDIS_Pos = 0x0
	// Bit mask of RXFILTDIS field.
	UCPD_CFGR2_RXFILTDIS_Msk = 0x1
	// Bit RXFILTDIS.
	UCPD_CFGR2_RXFILTDIS = 0x1
	// Rx pre-filter enabled
	UCPD_CFGR2_RXFILTDIS_Enabled = 0x0
	// Rx pre-filter disabled
	UCPD_CFGR2_RXFILTDIS_Disabled = 0x1
	// Position of RXFILT2N3 field.
	UCPD_CFGR2_RXFILT2N3_Pos = 0x1
	// Bit mask of RXFILT2N3 field.
	UCPD_CFGR2_RXFILT2N3_Msk = 0x2
	// Bit RXFILT2N3.
	UCPD_CFGR2_RXFILT2N3 = 0x2
	// 3 samples
	UCPD_CFGR2_RXFILT2N3_Samp3 = 0x0
	// 2 samples
	UCPD_CFGR2_RXFILT2N3_Samp2 = 0x1
	// Position of FORCECLK field.
	UCPD_CFGR2_FORCECLK_Pos = 0x2
	// Bit mask of FORCECLK field.
	UCPD_CFGR2_FORCECLK_Msk = 0x4
	// Bit FORCECLK.
	UCPD_CFGR2_FORCECLK = 0x4
	// Do not force clock request
	UCPD_CFGR2_FORCECLK_NoForce = 0x0
	// Force clock request
	UCPD_CFGR2_FORCECLK_Force = 0x1
	// Position of WUPEN field.
	UCPD_CFGR2_WUPEN_Pos = 0x3
	// Bit mask of WUPEN field.
	UCPD_CFGR2_WUPEN_Msk = 0x8
	// Bit WUPEN.
	UCPD_CFGR2_WUPEN = 0x8
	// Disabled
	UCPD_CFGR2_WUPEN_Disabled = 0x0
	// Enabled
	UCPD_CFGR2_WUPEN_Enabled = 0x1

	// CFGR3: UCPD configuration register 3
	// Position of TRIM1_NG_CCRPD field.
	UCPD_CFGR3_TRIM1_NG_CCRPD_Pos = 0x0
	// Bit mask of TRIM1_NG_CCRPD field.
	UCPD_CFGR3_TRIM1_NG_CCRPD_Msk = 0xf
	// Position of TRIM1_NG_CC3A0 field.
	UCPD_CFGR3_TRIM1_NG_CC3A0_Pos = 0x9
	// Bit mask of TRIM1_NG_CC3A0 field.
	UCPD_CFGR3_TRIM1_NG_CC3A0_Msk = 0x1e00
	// Position of TRIM2_NG_CCRPD field.
	UCPD_CFGR3_TRIM2_NG_CCRPD_Pos = 0x10
	// Bit mask of TRIM2_NG_CCRPD field.
	UCPD_CFGR3_TRIM2_NG_CCRPD_Msk = 0xf0000
	// Position of TRIM2_NG_CC3A0 field.
	UCPD_CFGR3_TRIM2_NG_CC3A0_Pos = 0x19
	// Bit mask of TRIM2_NG_CC3A0 field.
	UCPD_CFGR3_TRIM2_NG_CC3A0_Msk = 0x1e000000

	// CR: UCPD control register
	// Position of TXMODE field.
	UCPD_CR_TXMODE_Pos = 0x0
	// Bit mask of TXMODE field.
	UCPD_CR_TXMODE_Msk = 0x3
	// Transmission of Tx packet previously defined in other registers
	UCPD_CR_TXMODE_RegisterSet = 0x0
	// Cable Reset sequence
	UCPD_CR_TXMODE_CableReset = 0x1
	// BIST test sequence (BIST Carrier Mode 2)
	UCPD_CR_TXMODE_BISTTest = 0x2
	// Position of TXSEND field.
	UCPD_CR_TXSEND_Pos = 0x2
	// Bit mask of TXSEND field.
	UCPD_CR_TXSEND_Msk = 0x4
	// Bit TXSEND.
	UCPD_CR_TXSEND = 0x4
	// No effect
	UCPD_CR_TXSEND_NoEffect = 0x0
	// Start Tx packet transmission
	UCPD_CR_TXSEND_Start = 0x1
	// Position of TXHRST field.
	UCPD_CR_TXHRST_Pos = 0x3
	// Bit mask of TXHRST field.
	UCPD_CR_TXHRST_Msk = 0x8
	// Bit TXHRST.
	UCPD_CR_TXHRST = 0x8
	// No effect
	UCPD_CR_TXHRST_NoEffect = 0x0
	// Start Tx Hard Reset message
	UCPD_CR_TXHRST_Start = 0x1
	// Position of RXMODE field.
	UCPD_CR_RXMODE_Pos = 0x4
	// Bit mask of RXMODE field.
	UCPD_CR_RXMODE_Msk = 0x10
	// Bit RXMODE.
	UCPD_CR_RXMODE = 0x10
	// Normal receive mode
	UCPD_CR_RXMODE_Normal = 0x0
	// BIST receive mode (BIST test data mode)
	UCPD_CR_RXMODE_BIST = 0x1
	// Position of PHYRXEN field.
	UCPD_CR_PHYRXEN_Pos = 0x5
	// Bit mask of PHYRXEN field.
	UCPD_CR_PHYRXEN_Msk = 0x20
	// Bit PHYRXEN.
	UCPD_CR_PHYRXEN = 0x20
	// USB Power Delivery receiver disabled
	UCPD_CR_PHYRXEN_Disabled = 0x0
	// USB Power Delivery receiver enabled
	UCPD_CR_PHYRXEN_Enabled = 0x1
	// Position of PHYCCSEL field.
	UCPD_CR_PHYCCSEL_Pos = 0x6
	// Bit mask of PHYCCSEL field.
	UCPD_CR_PHYCCSEL_Msk = 0x40
	// Bit PHYCCSEL.
	UCPD_CR_PHYCCSEL = 0x40
	// Use CC1 IO for Power Delivery communication
	UCPD_CR_PHYCCSEL_CC1 = 0x0
	// Use CC2 IO for Power Delivery communication
	UCPD_CR_PHYCCSEL_CC2 = 0x1
	// Position of ANASUBMODE field.
	UCPD_CR_ANASUBMODE_Pos = 0x7
	// Bit mask of ANASUBMODE field.
	UCPD_CR_ANASUBMODE_Msk = 0x180
	// Disabled
	UCPD_CR_ANASUBMODE_Disabled = 0x0
	// Default USB Rp
	UCPD_CR_ANASUBMODE_Rp_DefaultUSB = 0x1
	// 1.5A Rp
	UCPD_CR_ANASUBMODE_Rp_1_5A = 0x2
	// 3A Rp
	UCPD_CR_ANASUBMODE_Rp_3A = 0x3
	// Position of ANAMODE field.
	UCPD_CR_ANAMODE_Pos = 0x9
	// Bit mask of ANAMODE field.
	UCPD_CR_ANAMODE_Msk = 0x200
	// Bit ANAMODE.
	UCPD_CR_ANAMODE = 0x200
	// Source
	UCPD_CR_ANAMODE_Source = 0x0
	// Sink
	UCPD_CR_ANAMODE_Sink = 0x1
	// Position of CCENABLE field.
	UCPD_CR_CCENABLE_Pos = 0xa
	// Bit mask of CCENABLE field.
	UCPD_CR_CCENABLE_Msk = 0xc00
	// Both PHYs disabled
	UCPD_CR_CCENABLE_Disabled = 0x0
	// CC1 PHY enabled
	UCPD_CR_CCENABLE_CC1Enabled = 0x1
	// CC2 PHY enabled
	UCPD_CR_CCENABLE_CC2Enabled = 0x2
	// CC1 and CC2 PHYs enabled
	UCPD_CR_CCENABLE_BothEnabled = 0x3
	// Position of FRSRXEN field.
	UCPD_CR_FRSRXEN_Pos = 0x10
	// Bit mask of FRSRXEN field.
	UCPD_CR_FRSRXEN_Msk = 0x10000
	// Bit FRSRXEN.
	UCPD_CR_FRSRXEN = 0x10000
	// FRS Rx event detection disabled
	UCPD_CR_FRSRXEN_Disabled = 0x0
	// FRS Rx event detection enabled
	UCPD_CR_FRSRXEN_Enabled = 0x1
	// Position of FRSTX field.
	UCPD_CR_FRSTX_Pos = 0x11
	// Bit mask of FRSTX field.
	UCPD_CR_FRSTX_Msk = 0x20000
	// Bit FRSTX.
	UCPD_CR_FRSTX = 0x20000
	// No effect
	UCPD_CR_FRSTX_NoEffect = 0x0
	// FRS Tx signaling enabled
	UCPD_CR_FRSTX_Enabled = 0x1
	// Position of RDCH field.
	UCPD_CR_RDCH_Pos = 0x12
	// Bit mask of RDCH field.
	UCPD_CR_RDCH_Msk = 0x40000
	// Bit RDCH.
	UCPD_CR_RDCH = 0x40000
	// No effect
	UCPD_CR_RDCH_NoEffect = 0x0
	// Rdch condition drive
	UCPD_CR_RDCH_ConditionDrive = 0x1
	// Position of CC1TCDIS field.
	UCPD_CR_CC1TCDIS_Pos = 0x14
	// Bit mask of CC1TCDIS field.
	UCPD_CR_CC1TCDIS_Msk = 0x100000
	// Bit CC1TCDIS.
	UCPD_CR_CC1TCDIS = 0x100000
	// Type-C detector on the CCx line enabled
	UCPD_CR_CC1TCDIS_Enabled = 0x0
	// Type-C detector on the CCx line disabled
	UCPD_CR_CC1TCDIS_Disabled = 0x1
	// Position of CC2TCDIS field.
	UCPD_CR_CC2TCDIS_Pos = 0x15
	// Bit mask of CC2TCDIS field.
	UCPD_CR_CC2TCDIS_Msk = 0x200000
	// Bit CC2TCDIS.
	UCPD_CR_CC2TCDIS = 0x200000
	// Type-C detector on the CCx line enabled
	UCPD_CR_CC2TCDIS_Enabled = 0x0
	// Type-C detector on the CCx line disabled
	UCPD_CR_CC2TCDIS_Disabled = 0x1

	// IMR: UCPD Interrupt Mask Register
	// Position of TXISIE field.
	UCPD_IMR_TXISIE_Pos = 0x0
	// Bit mask of TXISIE field.
	UCPD_IMR_TXISIE_Msk = 0x1
	// Bit TXISIE.
	UCPD_IMR_TXISIE = 0x1
	// Interrupt disabled
	UCPD_IMR_TXISIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXISIE_Enabled = 0x1
	// Position of TXMSGDISCIE field.
	UCPD_IMR_TXMSGDISCIE_Pos = 0x1
	// Bit mask of TXMSGDISCIE field.
	UCPD_IMR_TXMSGDISCIE_Msk = 0x2
	// Bit TXMSGDISCIE.
	UCPD_IMR_TXMSGDISCIE = 0x2
	// Interrupt disabled
	UCPD_IMR_TXMSGDISCIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXMSGDISCIE_Enabled = 0x1
	// Position of TXMSGSENTIE field.
	UCPD_IMR_TXMSGSENTIE_Pos = 0x2
	// Bit mask of TXMSGSENTIE field.
	UCPD_IMR_TXMSGSENTIE_Msk = 0x4
	// Bit TXMSGSENTIE.
	UCPD_IMR_TXMSGSENTIE = 0x4
	// Interrupt disabled
	UCPD_IMR_TXMSGSENTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXMSGSENTIE_Enabled = 0x1
	// Position of TXMSGABTIE field.
	UCPD_IMR_TXMSGABTIE_Pos = 0x3
	// Bit mask of TXMSGABTIE field.
	UCPD_IMR_TXMSGABTIE_Msk = 0x8
	// Bit TXMSGABTIE.
	UCPD_IMR_TXMSGABTIE = 0x8
	// Interrupt disabled
	UCPD_IMR_TXMSGABTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXMSGABTIE_Enabled = 0x1
	// Position of HRSTDISCIE field.
	UCPD_IMR_HRSTDISCIE_Pos = 0x4
	// Bit mask of HRSTDISCIE field.
	UCPD_IMR_HRSTDISCIE_Msk = 0x10
	// Bit HRSTDISCIE.
	UCPD_IMR_HRSTDISCIE = 0x10
	// Interrupt disabled
	UCPD_IMR_HRSTDISCIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_HRSTDISCIE_Enabled = 0x1
	// Position of HRSTSENTIE field.
	UCPD_IMR_HRSTSENTIE_Pos = 0x5
	// Bit mask of HRSTSENTIE field.
	UCPD_IMR_HRSTSENTIE_Msk = 0x20
	// Bit HRSTSENTIE.
	UCPD_IMR_HRSTSENTIE = 0x20
	// Interrupt disabled
	UCPD_IMR_HRSTSENTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_HRSTSENTIE_Enabled = 0x1
	// Position of TXUNDIE field.
	UCPD_IMR_TXUNDIE_Pos = 0x6
	// Bit mask of TXUNDIE field.
	UCPD_IMR_TXUNDIE_Msk = 0x40
	// Bit TXUNDIE.
	UCPD_IMR_TXUNDIE = 0x40
	// Interrupt disabled
	UCPD_IMR_TXUNDIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXUNDIE_Enabled = 0x1
	// Position of RXNEIE field.
	UCPD_IMR_RXNEIE_Pos = 0x8
	// Bit mask of RXNEIE field.
	UCPD_IMR_RXNEIE_Msk = 0x100
	// Bit RXNEIE.
	UCPD_IMR_RXNEIE = 0x100
	// Interrupt disabled
	UCPD_IMR_RXNEIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXNEIE_Enabled = 0x1
	// Position of RXORDDETIE field.
	UCPD_IMR_RXORDDETIE_Pos = 0x9
	// Bit mask of RXORDDETIE field.
	UCPD_IMR_RXORDDETIE_Msk = 0x200
	// Bit RXORDDETIE.
	UCPD_IMR_RXORDDETIE = 0x200
	// Interrupt disabled
	UCPD_IMR_RXORDDETIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXORDDETIE_Enabled = 0x1
	// Position of RXHRSTDETIE field.
	UCPD_IMR_RXHRSTDETIE_Pos = 0xa
	// Bit mask of RXHRSTDETIE field.
	UCPD_IMR_RXHRSTDETIE_Msk = 0x400
	// Bit RXHRSTDETIE.
	UCPD_IMR_RXHRSTDETIE = 0x400
	// Interrupt disabled
	UCPD_IMR_RXHRSTDETIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXHRSTDETIE_Enabled = 0x1
	// Position of RXOVRIE field.
	UCPD_IMR_RXOVRIE_Pos = 0xb
	// Bit mask of RXOVRIE field.
	UCPD_IMR_RXOVRIE_Msk = 0x800
	// Bit RXOVRIE.
	UCPD_IMR_RXOVRIE = 0x800
	// Interrupt disabled
	UCPD_IMR_RXOVRIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXOVRIE_Enabled = 0x1
	// Position of RXMSGENDIE field.
	UCPD_IMR_RXMSGENDIE_Pos = 0xc
	// Bit mask of RXMSGENDIE field.
	UCPD_IMR_RXMSGENDIE_Msk = 0x1000
	// Bit RXMSGENDIE.
	UCPD_IMR_RXMSGENDIE = 0x1000
	// Interrupt disabled
	UCPD_IMR_RXMSGENDIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXMSGENDIE_Enabled = 0x1
	// Position of TYPECEVT1IE field.
	UCPD_IMR_TYPECEVT1IE_Pos = 0xe
	// Bit mask of TYPECEVT1IE field.
	UCPD_IMR_TYPECEVT1IE_Msk = 0x4000
	// Bit TYPECEVT1IE.
	UCPD_IMR_TYPECEVT1IE = 0x4000
	// Interrupt disabled
	UCPD_IMR_TYPECEVT1IE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TYPECEVT1IE_Enabled = 0x1
	// Position of TYPECEVT2IE field.
	UCPD_IMR_TYPECEVT2IE_Pos = 0xf
	// Bit mask of TYPECEVT2IE field.
	UCPD_IMR_TYPECEVT2IE_Msk = 0x8000
	// Bit TYPECEVT2IE.
	UCPD_IMR_TYPECEVT2IE = 0x8000
	// Interrupt disabled
	UCPD_IMR_TYPECEVT2IE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TYPECEVT2IE_Enabled = 0x1
	// Position of FRSEVTIE field.
	UCPD_IMR_FRSEVTIE_Pos = 0x14
	// Bit mask of FRSEVTIE field.
	UCPD_IMR_FRSEVTIE_Msk = 0x100000
	// Bit FRSEVTIE.
	UCPD_IMR_FRSEVTIE = 0x100000
	// Interrupt disabled
	UCPD_IMR_FRSEVTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_FRSEVTIE_Enabled = 0x1

	// SR: UCPD Status Register
	// Position of TXIS field.
	UCPD_SR_TXIS_Pos = 0x0
	// Bit mask of TXIS field.
	UCPD_SR_TXIS_Msk = 0x1
	// Bit TXIS.
	UCPD_SR_TXIS = 0x1
	// New Tx data write not required
	UCPD_SR_TXIS_NotRequired = 0x0
	// New Tx data write required
	UCPD_SR_TXIS_Required = 0x1
	// Position of TXMSGDISC field.
	UCPD_SR_TXMSGDISC_Pos = 0x1
	// Bit mask of TXMSGDISC field.
	UCPD_SR_TXMSGDISC_Msk = 0x2
	// Bit TXMSGDISC.
	UCPD_SR_TXMSGDISC = 0x2
	// No Tx message discarded
	UCPD_SR_TXMSGDISC_NotDiscarded = 0x0
	// Tx message discarded
	UCPD_SR_TXMSGDISC_Discarded = 0x1
	// Position of TXMSGSENT field.
	UCPD_SR_TXMSGSENT_Pos = 0x2
	// Bit mask of TXMSGSENT field.
	UCPD_SR_TXMSGSENT_Msk = 0x4
	// Bit TXMSGSENT.
	UCPD_SR_TXMSGSENT = 0x4
	// No Tx message completed
	UCPD_SR_TXMSGSENT_NotCompleted = 0x0
	// Tx message completed
	UCPD_SR_TXMSGSENT_Completed = 0x1
	// Position of TXMSGABT field.
	UCPD_SR_TXMSGABT_Pos = 0x3
	// Bit mask of TXMSGABT field.
	UCPD_SR_TXMSGABT_Msk = 0x8
	// Bit TXMSGABT.
	UCPD_SR_TXMSGABT = 0x8
	// No transmit message abort
	UCPD_SR_TXMSGABT_NoAbort = 0x0
	// Transmit message abort
	UCPD_SR_TXMSGABT_Abort = 0x1
	// Position of HRSTDISC field.
	UCPD_SR_HRSTDISC_Pos = 0x4
	// Bit mask of HRSTDISC field.
	UCPD_SR_HRSTDISC_Msk = 0x10
	// Bit HRSTDISC.
	UCPD_SR_HRSTDISC = 0x10
	// No Hard Reset discarded
	UCPD_SR_HRSTDISC_NotDiscarded = 0x0
	// Hard Reset discarded
	UCPD_SR_HRSTDISC_Discarded = 0x1
	// Position of HRSTSENT field.
	UCPD_SR_HRSTSENT_Pos = 0x5
	// Bit mask of HRSTSENT field.
	UCPD_SR_HRSTSENT_Msk = 0x20
	// Bit HRSTSENT.
	UCPD_SR_HRSTSENT = 0x20
	// No Hard Reset message sent
	UCPD_SR_HRSTSENT_NotSent = 0x0
	// Hard Reset message sent
	UCPD_SR_HRSTSENT_Sent = 0x1
	// Position of TXUND field.
	UCPD_SR_TXUND_Pos = 0x6
	// Bit mask of TXUND field.
	UCPD_SR_TXUND_Msk = 0x40
	// Bit TXUND.
	UCPD_SR_TXUND = 0x40
	// No Tx data underrun detected
	UCPD_SR_TXUND_NoUnderrun = 0x0
	// Tx data underrun detected
	UCPD_SR_TXUND_Underrun = 0x1
	// Position of RXNE field.
	UCPD_SR_RXNE_Pos = 0x8
	// Bit mask of RXNE field.
	UCPD_SR_RXNE_Msk = 0x100
	// Bit RXNE.
	UCPD_SR_RXNE = 0x100
	// Rx data register empty
	UCPD_SR_RXNE_Empty = 0x0
	// Rx data register not empty
	UCPD_SR_RXNE_NotEmpty = 0x1
	// Position of RXORDDET field.
	UCPD_SR_RXORDDET_Pos = 0x9
	// Bit mask of RXORDDET field.
	UCPD_SR_RXORDDET_Msk = 0x200
	// Bit RXORDDET.
	UCPD_SR_RXORDDET = 0x200
	// No ordered set detected
	UCPD_SR_RXORDDET_NoOrderedSet = 0x0
	// Ordered set detected
	UCPD_SR_RXORDDET_OrderedSet = 0x1
	// Position of RXHRSTDET field.
	UCPD_SR_RXHRSTDET_Pos = 0xa
	// Bit mask of RXHRSTDET field.
	UCPD_SR_RXHRSTDET_Msk = 0x400
	// Bit RXHRSTDET.
	UCPD_SR_RXHRSTDET = 0x400
	// Hard Reset not received
	UCPD_SR_RXHRSTDET_NoHardReset = 0x0
	// Hard Reset received
	UCPD_SR_RXHRSTDET_HardReset = 0x1
	// Position of RXOVR field.
	UCPD_SR_RXOVR_Pos = 0xb
	// Bit mask of RXOVR field.
	UCPD_SR_RXOVR_Msk = 0x800
	// Bit RXOVR.
	UCPD_SR_RXOVR = 0x800
	// No overflow
	UCPD_SR_RXOVR_NoOverflow = 0x0
	// Overflow
	UCPD_SR_RXOVR_Overflow = 0x1
	// Position of RXMSGEND field.
	UCPD_SR_RXMSGEND_Pos = 0xc
	// Bit mask of RXMSGEND field.
	UCPD_SR_RXMSGEND_Msk = 0x1000
	// Bit RXMSGEND.
	UCPD_SR_RXMSGEND = 0x1000
	// No new Rx message received
	UCPD_SR_RXMSGEND_NoNewMessage = 0x0
	// A new Rx message received
	UCPD_SR_RXMSGEND_NewMessage = 0x1
	// Position of RXERR field.
	UCPD_SR_RXERR_Pos = 0xd
	// Bit mask of RXERR field.
	UCPD_SR_RXERR_Msk = 0x2000
	// Bit RXERR.
	UCPD_SR_RXERR = 0x2000
	// No error detected
	UCPD_SR_RXERR_NoError = 0x0
	// Error(s) detected
	UCPD_SR_RXERR_Error = 0x1
	// Position of TYPECEVT1 field.
	UCPD_SR_TYPECEVT1_Pos = 0xe
	// Bit mask of TYPECEVT1 field.
	UCPD_SR_TYPECEVT1_Msk = 0x4000
	// Bit TYPECEVT1.
	UCPD_SR_TYPECEVT1 = 0x4000
	// No new event
	UCPD_SR_TYPECEVT1_NoNewEvent = 0x0
	// A new Type-C event occurred
	UCPD_SR_TYPECEVT1_NewEvent = 0x1
	// Position of TYPECEVT2 field.
	UCPD_SR_TYPECEVT2_Pos = 0xf
	// Bit mask of TYPECEVT2 field.
	UCPD_SR_TYPECEVT2_Msk = 0x8000
	// Bit TYPECEVT2.
	UCPD_SR_TYPECEVT2 = 0x8000
	// No new event
	UCPD_SR_TYPECEVT2_NoNewEvent = 0x0
	// A new Type-C event occurred
	UCPD_SR_TYPECEVT2_NewEvent = 0x1
	// Position of TYPEC_VSTATE_CC1 field.
	UCPD_SR_TYPEC_VSTATE_CC1_Pos = 0x10
	// Bit mask of TYPEC_VSTATE_CC1 field.
	UCPD_SR_TYPEC_VSTATE_CC1_Msk = 0x30000
	// Lowest
	UCPD_SR_TYPEC_VSTATE_CC1_Lowest = 0x0
	// Low
	UCPD_SR_TYPEC_VSTATE_CC1_Low = 0x1
	// High
	UCPD_SR_TYPEC_VSTATE_CC1_High = 0x2
	// Highest
	UCPD_SR_TYPEC_VSTATE_CC1_Highest = 0x3
	// Position of TYPEC_VSTATE_CC2 field.
	UCPD_SR_TYPEC_VSTATE_CC2_Pos = 0x12
	// Bit mask of TYPEC_VSTATE_CC2 field.
	UCPD_SR_TYPEC_VSTATE_CC2_Msk = 0xc0000
	// Lowest
	UCPD_SR_TYPEC_VSTATE_CC2_Lowest = 0x0
	// Low
	UCPD_SR_TYPEC_VSTATE_CC2_Low = 0x1
	// High
	UCPD_SR_TYPEC_VSTATE_CC2_High = 0x2
	// Highest
	UCPD_SR_TYPEC_VSTATE_CC2_Highest = 0x3
	// Position of FRSEVT field.
	UCPD_SR_FRSEVT_Pos = 0x14
	// Bit mask of FRSEVT field.
	UCPD_SR_FRSEVT_Msk = 0x100000
	// Bit FRSEVT.
	UCPD_SR_FRSEVT = 0x100000
	// No new event
	UCPD_SR_FRSEVT_NoNewEvent = 0x0
	// New FRS receive event occurred
	UCPD_SR_FRSEVT_NewEvent = 0x1

	// ICR: UCPD Interrupt Clear Register
	// Position of TXMSGDISCCF field.
	UCPD_ICR_TXMSGDISCCF_Pos = 0x1
	// Bit mask of TXMSGDISCCF field.
	UCPD_ICR_TXMSGDISCCF_Msk = 0x2
	// Bit TXMSGDISCCF.
	UCPD_ICR_TXMSGDISCCF = 0x2
	// Clear flag in UCPD_SR
	UCPD_ICR_TXMSGDISCCF_Clear = 0x1
	// Position of TXMSGSENTCF field.
	UCPD_ICR_TXMSGSENTCF_Pos = 0x2
	// Bit mask of TXMSGSENTCF field.
	UCPD_ICR_TXMSGSENTCF_Msk = 0x4
	// Bit TXMSGSENTCF.
	UCPD_ICR_TXMSGSENTCF = 0x4
	// Clear flag in UCPD_SR
	UCPD_ICR_TXMSGSENTCF_Clear = 0x1
	// Position of TXMSGABTCF field.
	UCPD_ICR_TXMSGABTCF_Pos = 0x3
	// Bit mask of TXMSGABTCF field.
	UCPD_ICR_TXMSGABTCF_Msk = 0x8
	// Bit TXMSGABTCF.
	UCPD_ICR_TXMSGABTCF = 0x8
	// Clear flag in UCPD_SR
	UCPD_ICR_TXMSGABTCF_Clear = 0x1
	// Position of HRSTDISCCF field.
	UCPD_ICR_HRSTDISCCF_Pos = 0x4
	// Bit mask of HRSTDISCCF field.
	UCPD_ICR_HRSTDISCCF_Msk = 0x10
	// Bit HRSTDISCCF.
	UCPD_ICR_HRSTDISCCF = 0x10
	// Clear flag in UCPD_SR
	UCPD_ICR_HRSTDISCCF_Clear = 0x1
	// Position of HRSTSENTCF field.
	UCPD_ICR_HRSTSENTCF_Pos = 0x5
	// Bit mask of HRSTSENTCF field.
	UCPD_ICR_HRSTSENTCF_Msk = 0x20
	// Bit HRSTSENTCF.
	UCPD_ICR_HRSTSENTCF = 0x20
	// Clear flag in UCPD_SR
	UCPD_ICR_HRSTSENTCF_Clear = 0x1
	// Position of TXUNDCF field.
	UCPD_ICR_TXUNDCF_Pos = 0x6
	// Bit mask of TXUNDCF field.
	UCPD_ICR_TXUNDCF_Msk = 0x40
	// Bit TXUNDCF.
	UCPD_ICR_TXUNDCF = 0x40
	// Clear flag in UCPD_SR
	UCPD_ICR_TXUNDCF_Clear = 0x1
	// Position of RXORDDETCF field.
	UCPD_ICR_RXORDDETCF_Pos = 0x9
	// Bit mask of RXORDDETCF field.
	UCPD_ICR_RXORDDETCF_Msk = 0x200
	// Bit RXORDDETCF.
	UCPD_ICR_RXORDDETCF = 0x200
	// Clear flag in UCPD_SR
	UCPD_ICR_RXORDDETCF_Clear = 0x1
	// Position of RXHRSTDETCF field.
	UCPD_ICR_RXHRSTDETCF_Pos = 0xa
	// Bit mask of RXHRSTDETCF field.
	UCPD_ICR_RXHRSTDETCF_Msk = 0x400
	// Bit RXHRSTDETCF.
	UCPD_ICR_RXHRSTDETCF = 0x400
	// Clear flag in UCPD_SR
	UCPD_ICR_RXHRSTDETCF_Clear = 0x1
	// Position of RXOVRCF field.
	UCPD_ICR_RXOVRCF_Pos = 0xb
	// Bit mask of RXOVRCF field.
	UCPD_ICR_RXOVRCF_Msk = 0x800
	// Bit RXOVRCF.
	UCPD_ICR_RXOVRCF = 0x800
	// Clear flag in UCPD_SR
	UCPD_ICR_RXOVRCF_Clear = 0x1
	// Position of RXMSGENDCF field.
	UCPD_ICR_RXMSGENDCF_Pos = 0xc
	// Bit mask of RXMSGENDCF field.
	UCPD_ICR_RXMSGENDCF_Msk = 0x1000
	// Bit RXMSGENDCF.
	UCPD_ICR_RXMSGENDCF = 0x1000
	// Clear flag in UCPD_SR
	UCPD_ICR_RXMSGENDCF_Clear = 0x1
	// Position of TYPECEVT1CF field.
	UCPD_ICR_TYPECEVT1CF_Pos = 0xe
	// Bit mask of TYPECEVT1CF field.
	UCPD_ICR_TYPECEVT1CF_Msk = 0x4000
	// Bit TYPECEVT1CF.
	UCPD_ICR_TYPECEVT1CF = 0x4000
	// Clear flag in UCPD_SR
	UCPD_ICR_TYPECEVT1CF_Clear = 0x1
	// Position of TYPECEVT2CF field.
	UCPD_ICR_TYPECEVT2CF_Pos = 0xf
	// Bit mask of TYPECEVT2CF field.
	UCPD_ICR_TYPECEVT2CF_Msk = 0x8000
	// Bit TYPECEVT2CF.
	UCPD_ICR_TYPECEVT2CF = 0x8000
	// Clear flag in UCPD_SR
	UCPD_ICR_TYPECEVT2CF_Clear = 0x1
	// Position of FRSEVTCF field.
	UCPD_ICR_FRSEVTCF_Pos = 0x14
	// Bit mask of FRSEVTCF field.
	UCPD_ICR_FRSEVTCF_Msk = 0x100000
	// Bit FRSEVTCF.
	UCPD_ICR_FRSEVTCF = 0x100000
	// Clear flag in UCPD_SR
	UCPD_ICR_FRSEVTCF_Clear = 0x1

	// TX_ORDSETR: UCPD Tx Ordered Set Type Register
	// Position of TXORDSET field.
	UCPD_TX_ORDSETR_TXORDSET_Pos = 0x0
	// Bit mask of TXORDSET field.
	UCPD_TX_ORDSETR_TXORDSET_Msk = 0xfffff

	// TX_PAYSZR: UCPD Tx payload size Register
	// Position of TXPAYSZ field.
	UCPD_TX_PAYSZR_TXPAYSZ_Pos = 0x0
	// Bit mask of TXPAYSZ field.
	UCPD_TX_PAYSZR_TXPAYSZ_Msk = 0x3ff

	// TXDR: UCPD Tx Data Register
	// Position of TXDATA field.
	UCPD_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	UCPD_TXDR_TXDATA_Msk = 0xff

	// RX_ORDSETR: UCPD Rx Ordered Set Register
	// Position of RXORDSET field.
	UCPD_RX_ORDSETR_RXORDSET_Pos = 0x0
	// Bit mask of RXORDSET field.
	UCPD_RX_ORDSETR_RXORDSET_Msk = 0x7
	// SOP code detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOP = 0x0
	// SOP' code detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPPrime = 0x1
	// SOP'' code detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPDoublePrime = 0x2
	// SOP'_Debug detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPPrimeDebug = 0x3
	// SOP''_Debug detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPDoublePrimeDebug = 0x4
	// Cable Reset detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_CableReset = 0x5
	// SOP extension #1 detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPExtension1 = 0x6
	// SOP extension #2 detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPExtension2 = 0x7
	// Position of RXSOP3OF4 field.
	UCPD_RX_ORDSETR_RXSOP3OF4_Pos = 0x3
	// Bit mask of RXSOP3OF4 field.
	UCPD_RX_ORDSETR_RXSOP3OF4_Msk = 0x8
	// Bit RXSOP3OF4.
	UCPD_RX_ORDSETR_RXSOP3OF4 = 0x8
	// 4 correct K-codes out of 4
	UCPD_RX_ORDSETR_RXSOP3OF4_AllCorrect = 0x0
	// 3 correct K-codes out of 4
	UCPD_RX_ORDSETR_RXSOP3OF4_OneIncorrect = 0x1
	// Position of RXSOPKINVALID field.
	UCPD_RX_ORDSETR_RXSOPKINVALID_Pos = 0x4
	// Bit mask of RXSOPKINVALID field.
	UCPD_RX_ORDSETR_RXSOPKINVALID_Msk = 0x70
	// No K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_Valid = 0x0
	// First K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_FirstCorrupted = 0x1
	// Second K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_SecondCorrupted = 0x2
	// Third K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_ThirdCorrupted = 0x3
	// Fourth K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_FourthCorrupted = 0x4

	// RX_PAYSZR: UCPD Rx payload size Register
	// Position of RXPAYSZ field.
	UCPD_RX_PAYSZR_RXPAYSZ_Pos = 0x0
	// Bit mask of RXPAYSZ field.
	UCPD_RX_PAYSZR_RXPAYSZ_Msk = 0x3ff

	// RXDR: UCPD Receive Data Register
	// Position of RXDATA field.
	UCPD_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	UCPD_RXDR_RXDATA_Msk = 0xff

	// RX_ORDEXTR1: UCPD Rx Ordered Set Extension Register 1
	// Position of RXSOPX1 field.
	UCPD_RX_ORDEXTR1_RXSOPX1_Pos = 0x0
	// Bit mask of RXSOPX1 field.
	UCPD_RX_ORDEXTR1_RXSOPX1_Msk = 0xfffff

	// RX_ORDEXTR2: UCPD Rx Ordered Set Extension Register 2
	// Position of RXSOPX2 field.
	UCPD_RX_ORDEXTR2_RXSOPX2_Pos = 0x0
	// Bit mask of RXSOPX2 field.
	UCPD_RX_ORDEXTR2_RXSOPX2_Msk = 0xfffff
)

// Constants for USART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	// Position of M1 field.
	USART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	USART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	USART_CR1_M1 = 0x10000000
	// Use M0 to set the data bits
	USART_CR1_M1_M0 = 0x0
	// 1 start bit, 7 data bits, n stop bits
	USART_CR1_M1_Bit7 = 0x1
	// Position of EOBIE field.
	USART_CR1_EOBIE_Pos = 0x1b
	// Bit mask of EOBIE field.
	USART_CR1_EOBIE_Msk = 0x8000000
	// Bit EOBIE.
	USART_CR1_EOBIE = 0x8000000
	// Interrupt is inhibited
	USART_CR1_EOBIE_Disabled = 0x0
	// A USART interrupt is generated when the EOBF flag is set in the ISR register
	USART_CR1_EOBIE_Enabled = 0x1
	// Position of RTOIE field.
	USART_CR1_RTOIE_Pos = 0x1a
	// Bit mask of RTOIE field.
	USART_CR1_RTOIE_Msk = 0x4000000
	// Bit RTOIE.
	USART_CR1_RTOIE = 0x4000000
	// Interrupt is inhibited
	USART_CR1_RTOIE_Disabled = 0x0
	// An USART interrupt is generated when the RTOF bit is set in the ISR register
	USART_CR1_RTOIE_Enabled = 0x1
	// Position of DEAT field.
	USART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	USART_CR1_DEAT_Msk = 0x3e00000
	// Position of DEDT field.
	USART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	USART_CR1_DEDT_Msk = 0x1f0000
	// Position of OVER8 field.
	USART_CR1_OVER8_Pos = 0xf
	// Bit mask of OVER8 field.
	USART_CR1_OVER8_Msk = 0x8000
	// Bit OVER8.
	USART_CR1_OVER8 = 0x8000
	// Oversampling by 16
	USART_CR1_OVER8_Oversampling16 = 0x0
	// Oversampling by 8
	USART_CR1_OVER8_Oversampling8 = 0x1
	// Position of CMIE field.
	USART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	USART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	USART_CR1_CMIE = 0x4000
	// Interrupt is disabled
	USART_CR1_CMIE_Disabled = 0x0
	// Interrupt is generated when the CMF bit is set in the ISR register
	USART_CR1_CMIE_Enabled = 0x1
	// Position of MME field.
	USART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	USART_CR1_MME_Msk = 0x2000
	// Bit MME.
	USART_CR1_MME = 0x2000
	// Receiver in active mode permanently
	USART_CR1_MME_Disabled = 0x0
	// Receiver can switch between mute mode and active mode
	USART_CR1_MME_Enabled = 0x1
	// Position of M0 field.
	USART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	USART_CR1_M0_Msk = 0x1000
	// Bit M0.
	USART_CR1_M0 = 0x1000
	// 1 start bit, 8 data bits, n stop bits
	USART_CR1_M0_Bit8 = 0x0
	// 1 start bit, 9 data bits, n stop bits
	USART_CR1_M0_Bit9 = 0x1
	// Position of WAKE field.
	USART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	USART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	USART_CR1_WAKE = 0x800
	// Idle line
	USART_CR1_WAKE_Idle = 0x0
	// Address mask
	USART_CR1_WAKE_Address = 0x1
	// Position of PCE field.
	USART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	USART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	USART_CR1_PCE = 0x400
	// Parity control disabled
	USART_CR1_PCE_Disabled = 0x0
	// Parity control enabled
	USART_CR1_PCE_Enabled = 0x1
	// Position of PS field.
	USART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	USART_CR1_PS_Msk = 0x200
	// Bit PS.
	USART_CR1_PS = 0x200
	// Even parity
	USART_CR1_PS_Even = 0x0
	// Odd parity
	USART_CR1_PS_Odd = 0x1
	// Position of PEIE field.
	USART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	USART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	USART_CR1_PEIE = 0x100
	// Interrupt is disabled
	USART_CR1_PEIE_Disabled = 0x0
	// Interrupt is generated whenever PE=1 in the ISR register
	USART_CR1_PEIE_Enabled = 0x1
	// Position of TXEIE field.
	USART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	USART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	USART_CR1_TXEIE = 0x80
	// Interrupt is disabled
	USART_CR1_TXEIE_Disabled = 0x0
	// Interrupt is generated whenever TXE=1 in the ISR register
	USART_CR1_TXEIE_Enabled = 0x1
	// Position of TCIE field.
	USART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	USART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	USART_CR1_TCIE = 0x40
	// Interrupt is disabled
	USART_CR1_TCIE_Disabled = 0x0
	// Interrupt is generated whenever TC=1 in the ISR register
	USART_CR1_TCIE_Enabled = 0x1
	// Position of RXNEIE field.
	USART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	USART_CR1_RXNEIE = 0x20
	// Interrupt is disabled
	USART_CR1_RXNEIE_Disabled = 0x0
	// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
	USART_CR1_RXNEIE_Enabled = 0x1
	// Position of IDLEIE field.
	USART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	USART_CR1_IDLEIE = 0x10
	// Interrupt is disabled
	USART_CR1_IDLEIE_Disabled = 0x0
	// Interrupt is generated whenever IDLE=1 in the ISR register
	USART_CR1_IDLEIE_Enabled = 0x1
	// Position of TE field.
	USART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	USART_CR1_TE_Msk = 0x8
	// Bit TE.
	USART_CR1_TE = 0x8
	// Transmitter is disabled
	USART_CR1_TE_Disabled = 0x0
	// Transmitter is enabled
	USART_CR1_TE_Enabled = 0x1
	// Position of RE field.
	USART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	USART_CR1_RE_Msk = 0x4
	// Bit RE.
	USART_CR1_RE = 0x4
	// Receiver is disabled
	USART_CR1_RE_Disabled = 0x0
	// Receiver is enabled
	USART_CR1_RE_Enabled = 0x1
	// Position of UESM field.
	USART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	USART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	USART_CR1_UESM = 0x2
	// Position of UE field.
	USART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	USART_CR1_UE_Msk = 0x1
	// Bit UE.
	USART_CR1_UE = 0x1
	// UART is disabled
	USART_CR1_UE_Disabled = 0x0
	// UART is enabled
	USART_CR1_UE_Enabled = 0x1
	// Position of FIFOEN field.
	USART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	USART_CR1_FIFOEN = 0x20000000
	// FIFO mode is disabled
	USART_CR1_FIFOEN_Disabled = 0x0
	// FIFO mode is enabled
	USART_CR1_FIFOEN_Enabled = 0x1
	// Position of TXFEIE field.
	USART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	USART_CR1_TXFEIE = 0x40000000
	// Interrupt inhibited
	USART_CR1_TXFEIE_Disabled = 0x0
	// USART interrupt generated when TXFE = 1 in the USART_ISR register
	USART_CR1_TXFEIE_Enabled = 0x1
	// Position of RXFFIE field.
	USART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	USART_CR1_RXFFIE = 0x80000000
	// Interrupt inhibited
	USART_CR1_RXFFIE_Disabled = 0x0
	// USART interrupt generated when RXFF = 1 in the USART_ISR register
	USART_CR1_RXFFIE_Enabled = 0x1

	// CR2: Control register 2
	// Position of ADD field.
	USART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	USART_CR2_ADD_Msk = 0xff000000
	// Position of RTOEN field.
	USART_CR2_RTOEN_Pos = 0x17
	// Bit mask of RTOEN field.
	USART_CR2_RTOEN_Msk = 0x800000
	// Bit RTOEN.
	USART_CR2_RTOEN = 0x800000
	// Receiver timeout feature disabled
	USART_CR2_RTOEN_Disabled = 0x0
	// Receiver timeout feature enabled
	USART_CR2_RTOEN_Enabled = 0x1
	// Position of ABRMOD field.
	USART_CR2_ABRMOD_Pos = 0x15
	// Bit mask of ABRMOD field.
	USART_CR2_ABRMOD_Msk = 0x600000
	// Measurement of the start bit is used to detect the baud rate
	USART_CR2_ABRMOD_Start = 0x0
	// Falling edge to falling edge measurement
	USART_CR2_ABRMOD_Edge = 0x1
	// 0x7F frame detection
	USART_CR2_ABRMOD_Frame7F = 0x2
	// 0x55 frame detection
	USART_CR2_ABRMOD_Frame55 = 0x3
	// Position of ABREN field.
	USART_CR2_ABREN_Pos = 0x14
	// Bit mask of ABREN field.
	USART_CR2_ABREN_Msk = 0x100000
	// Bit ABREN.
	USART_CR2_ABREN = 0x100000
	// Auto baud rate detection is disabled
	USART_CR2_ABREN_Disabled = 0x0
	// Auto baud rate detection is enabled
	USART_CR2_ABREN_Enabled = 0x1
	// Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	USART_CR2_MSBFIRST = 0x80000
	// data is transmitted/received with data bit 0 first, following the start bit
	USART_CR2_MSBFIRST_LSB = 0x0
	// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
	USART_CR2_MSBFIRST_MSB = 0x1
	// Position of DATAINV field.
	USART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	USART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	USART_CR2_DATAINV = 0x40000
	// Logical data from the data register are send/received in positive/direct logic
	USART_CR2_DATAINV_Positive = 0x0
	// Logical data from the data register are send/received in negative/inverse logic
	USART_CR2_DATAINV_Negative = 0x1
	// Position of TXINV field.
	USART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	USART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	USART_CR2_TXINV = 0x20000
	// TX pin signal works using the standard logic levels
	USART_CR2_TXINV_Standard = 0x0
	// TX pin signal values are inverted
	USART_CR2_TXINV_Inverted = 0x1
	// Position of RXINV field.
	USART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	USART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	USART_CR2_RXINV = 0x10000
	// RX pin signal works using the standard logic levels
	USART_CR2_RXINV_Standard = 0x0
	// RX pin signal values are inverted
	USART_CR2_RXINV_Inverted = 0x1
	// Position of SWAP field.
	USART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	USART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	USART_CR2_SWAP = 0x8000
	// TX/RX pins are used as defined in standard pinout
	USART_CR2_SWAP_Standard = 0x0
	// The TX and RX pins functions are swapped
	USART_CR2_SWAP_Swapped = 0x1
	// Position of LINEN field.
	USART_CR2_LINEN_Pos = 0xe
	// Bit mask of LINEN field.
	USART_CR2_LINEN_Msk = 0x4000
	// Bit LINEN.
	USART_CR2_LINEN = 0x4000
	// LIN mode disabled
	USART_CR2_LINEN_Disabled = 0x0
	// LIN mode enabled
	USART_CR2_LINEN_Enabled = 0x1
	// Position of STOP field.
	USART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	USART_CR2_STOP_Msk = 0x3000
	// 1 stop bit
	USART_CR2_STOP_Stop1 = 0x0
	// 0.5 stop bit
	USART_CR2_STOP_Stop0p5 = 0x1
	// 2 stop bit
	USART_CR2_STOP_Stop2 = 0x2
	// 1.5 stop bit
	USART_CR2_STOP_Stop1p5 = 0x3
	// Position of CLKEN field.
	USART_CR2_CLKEN_Pos = 0xb
	// Bit mask of CLKEN field.
	USART_CR2_CLKEN_Msk = 0x800
	// Bit CLKEN.
	USART_CR2_CLKEN = 0x800
	// CK pin disabled
	USART_CR2_CLKEN_Disabled = 0x0
	// CK pin enabled
	USART_CR2_CLKEN_Enabled = 0x1
	// Position of CPOL field.
	USART_CR2_CPOL_Pos = 0xa
	// Bit mask of CPOL field.
	USART_CR2_CPOL_Msk = 0x400
	// Bit CPOL.
	USART_CR2_CPOL = 0x400
	// Steady low value on CK pin outside transmission window
	USART_CR2_CPOL_Low = 0x0
	// Steady high value on CK pin outside transmission window
	USART_CR2_CPOL_High = 0x1
	// Position of CPHA field.
	USART_CR2_CPHA_Pos = 0x9
	// Bit mask of CPHA field.
	USART_CR2_CPHA_Msk = 0x200
	// Bit CPHA.
	USART_CR2_CPHA = 0x200
	// The first clock transition is the first data capture edge
	USART_CR2_CPHA_First = 0x0
	// The second clock transition is the first data capture edge
	USART_CR2_CPHA_Second = 0x1
	// Position of LBCL field.
	USART_CR2_LBCL_Pos = 0x8
	// Bit mask of LBCL field.
	USART_CR2_LBCL_Msk = 0x100
	// Bit LBCL.
	USART_CR2_LBCL = 0x100
	// The clock pulse of the last data bit is not output to the CK pin
	USART_CR2_LBCL_NotOutput = 0x0
	// The clock pulse of the last data bit is output to the CK pin
	USART_CR2_LBCL_Output = 0x1
	// Position of LBDIE field.
	USART_CR2_LBDIE_Pos = 0x6
	// Bit mask of LBDIE field.
	USART_CR2_LBDIE_Msk = 0x40
	// Bit LBDIE.
	USART_CR2_LBDIE = 0x40
	// Interrupt is inhibited
	USART_CR2_LBDIE_Disabled = 0x0
	// An interrupt is generated whenever LBDF=1 in the ISR register
	USART_CR2_LBDIE_Enabled = 0x1
	// Position of LBDL field.
	USART_CR2_LBDL_Pos = 0x5
	// Bit mask of LBDL field.
	USART_CR2_LBDL_Msk = 0x20
	// Bit LBDL.
	USART_CR2_LBDL = 0x20
	// 10-bit break detection
	USART_CR2_LBDL_Bit10 = 0x0
	// 11-bit break detection
	USART_CR2_LBDL_Bit11 = 0x1
	// Position of ADDM7 field.
	USART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	USART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	USART_CR2_ADDM7 = 0x10
	// 4-bit address detection
	USART_CR2_ADDM7_Bit4 = 0x0
	// 7-bit address detection
	USART_CR2_ADDM7_Bit7 = 0x1
	// Position of SLVEN field.
	USART_CR2_SLVEN_Pos = 0x0
	// Bit mask of SLVEN field.
	USART_CR2_SLVEN_Msk = 0x1
	// Bit SLVEN.
	USART_CR2_SLVEN = 0x1
	// Slave mode disabled
	USART_CR2_SLVEN_Disabled = 0x0
	// Slave mode enabled
	USART_CR2_SLVEN_Enabled = 0x1
	// Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Pos = 0x3
	// Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk = 0x8
	// Bit DIS_NSS.
	USART_CR2_DIS_NSS = 0x8
	// SPI slave selection depends on NSS input pin
	USART_CR2_DIS_NSS_Disabled = 0x0
	// SPI slave is always selected and NSS input pin is ignored
	USART_CR2_DIS_NSS_Enabled = 0x1

	// CR3: Control register 3
	// Position of SCARCNT field.
	USART_CR3_SCARCNT_Pos = 0x11
	// Bit mask of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000
	// Position of DEP field.
	USART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	USART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	USART_CR3_DEP = 0x8000
	// DE signal is active high
	USART_CR3_DEP_High = 0x0
	// DE signal is active low
	USART_CR3_DEP_Low = 0x1
	// Position of DEM field.
	USART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	USART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	USART_CR3_DEM = 0x4000
	// DE function is disabled
	USART_CR3_DEM_Disabled = 0x0
	// The DE signal is output on the RTS pin
	USART_CR3_DEM_Enabled = 0x1
	// Position of DDRE field.
	USART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	USART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	USART_CR3_DDRE = 0x2000
	// DMA is not disabled in case of reception error
	USART_CR3_DDRE_NotDisabled = 0x0
	// DMA is disabled following a reception error
	USART_CR3_DDRE_Disabled = 0x1
	// Position of OVRDIS field.
	USART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	USART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	USART_CR3_OVRDIS = 0x1000
	// Overrun Error Flag, ORE, is set when received data is not read before receiving new data
	USART_CR3_OVRDIS_Enabled = 0x0
	// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
	USART_CR3_OVRDIS_Disabled = 0x1
	// Position of ONEBIT field.
	USART_CR3_ONEBIT_Pos = 0xb
	// Bit mask of ONEBIT field.
	USART_CR3_ONEBIT_Msk = 0x800
	// Bit ONEBIT.
	USART_CR3_ONEBIT = 0x800
	// Three sample bit method
	USART_CR3_ONEBIT_Sample3 = 0x0
	// One sample bit method
	USART_CR3_ONEBIT_Sample1 = 0x1
	// Position of CTSIE field.
	USART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	USART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	USART_CR3_CTSIE = 0x400
	// Interrupt is inhibited
	USART_CR3_CTSIE_Disabled = 0x0
	// An interrupt is generated whenever CTSIF=1 in the ISR register
	USART_CR3_CTSIE_Enabled = 0x1
	// Position of CTSE field.
	USART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	USART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	USART_CR3_CTSE = 0x200
	// CTS hardware flow control disabled
	USART_CR3_CTSE_Disabled = 0x0
	// CTS mode enabled, data is only transmitted when the CTS input is asserted
	USART_CR3_CTSE_Enabled = 0x1
	// Position of RTSE field.
	USART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	USART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	USART_CR3_RTSE = 0x100
	// RTS hardware flow control disabled
	USART_CR3_RTSE_Disabled = 0x0
	// RTS output enabled, data is only requested when there is space in the receive buffer
	USART_CR3_RTSE_Enabled = 0x1
	// Position of DMAT field.
	USART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	USART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	USART_CR3_DMAT = 0x80
	// DMA mode is disabled for transmission
	USART_CR3_DMAT_Disabled = 0x0
	// DMA mode is enabled for transmission
	USART_CR3_DMAT_Enabled = 0x1
	// Position of DMAR field.
	USART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	USART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	USART_CR3_DMAR = 0x40
	// DMA mode is disabled for reception
	USART_CR3_DMAR_Disabled = 0x0
	// DMA mode is enabled for reception
	USART_CR3_DMAR_Enabled = 0x1
	// Position of SCEN field.
	USART_CR3_SCEN_Pos = 0x5
	// Bit mask of SCEN field.
	USART_CR3_SCEN_Msk = 0x20
	// Bit SCEN.
	USART_CR3_SCEN = 0x20
	// Smartcard Mode disabled
	USART_CR3_SCEN_Disabled = 0x0
	// Smartcard Mode enabled
	USART_CR3_SCEN_Enabled = 0x1
	// Position of NACK field.
	USART_CR3_NACK_Pos = 0x4
	// Bit mask of NACK field.
	USART_CR3_NACK_Msk = 0x10
	// Bit NACK.
	USART_CR3_NACK = 0x10
	// NACK transmission in case of parity error is disabled
	USART_CR3_NACK_Disabled = 0x0
	// NACK transmission during parity error is enabled
	USART_CR3_NACK_Enabled = 0x1
	// Position of HDSEL field.
	USART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	USART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	USART_CR3_HDSEL = 0x8
	// Half duplex mode is not selected
	USART_CR3_HDSEL_NotSelected = 0x0
	// Half duplex mode is selected
	USART_CR3_HDSEL_Selected = 0x1
	// Position of IRLP field.
	USART_CR3_IRLP_Pos = 0x2
	// Bit mask of IRLP field.
	USART_CR3_IRLP_Msk = 0x4
	// Bit IRLP.
	USART_CR3_IRLP = 0x4
	// Normal mode
	USART_CR3_IRLP_Normal = 0x0
	// Low-power mode
	USART_CR3_IRLP_LowPower = 0x1
	// Position of IREN field.
	USART_CR3_IREN_Pos = 0x1
	// Bit mask of IREN field.
	USART_CR3_IREN_Msk = 0x2
	// Bit IREN.
	USART_CR3_IREN = 0x2
	// IrDA disabled
	USART_CR3_IREN_Disabled = 0x0
	// IrDA enabled
	USART_CR3_IREN_Enabled = 0x1
	// Position of EIE field.
	USART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	USART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	USART_CR3_EIE = 0x1
	// Interrupt is inhibited
	USART_CR3_EIE_Disabled = 0x0
	// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
	USART_CR3_EIE_Enabled = 0x1
	// Position of TXFTIE field.
	USART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	USART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	USART_CR3_TXFTIE = 0x800000
	// Interrupt inhibited
	USART_CR3_TXFTIE_Disabled = 0x0
	// USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
	USART_CR3_TXFTIE_Enabled = 0x1
	// Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Pos = 0x18
	// Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000
	// Bit TCBGTIE.
	USART_CR3_TCBGTIE = 0x1000000
	// Interrupt inhibited
	USART_CR3_TCBGTIE_Disabled = 0x0
	// USART interrupt generated whenever TCBGT=1 in the USART_ISR register
	USART_CR3_TCBGTIE_Enabled = 0x1
	// Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000
	// RXFIFO reaches 1/8 of its depth
	USART_CR3_RXFTCFG_Depth_1_8 = 0x0
	// RXFIFO reaches 1/4 of its depth
	USART_CR3_RXFTCFG_Depth_1_4 = 0x1
	// RXFIFO reaches 1/2 of its depth
	USART_CR3_RXFTCFG_Depth_1_2 = 0x2
	// RXFIFO reaches 3/4 of its depth
	USART_CR3_RXFTCFG_Depth_3_4 = 0x3
	// RXFIFO reaches 7/8 of its depth
	USART_CR3_RXFTCFG_Depth_7_8 = 0x4
	// RXFIFO becomes full
	USART_CR3_RXFTCFG_Full = 0x5
	// Position of RXFTIE field.
	USART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	USART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	USART_CR3_RXFTIE = 0x10000000
	// Interrupt inhibited
	USART_CR3_RXFTIE_Disabled = 0x0
	// USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
	USART_CR3_RXFTIE_Enabled = 0x1
	// Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000
	// TXFIFO reaches 1/8 of its depth
	USART_CR3_TXFTCFG_Depth_1_8 = 0x0
	// TXFIFO reaches 1/4 of its depth
	USART_CR3_TXFTCFG_Depth_1_4 = 0x1
	// TXFIFO reaches 1/2 of its depth
	USART_CR3_TXFTCFG_Depth_1_2 = 0x2
	// TXFIFO reaches 3/4 of its depth
	USART_CR3_TXFTCFG_Depth_3_4 = 0x3
	// TXFIFO reaches 7/8 of its depth
	USART_CR3_TXFTCFG_Depth_7_8 = 0x4
	// TXFIFO becomes empty
	USART_CR3_TXFTCFG_Empty = 0x5

	// BRR: Baud rate register
	// Position of BRR field.
	USART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	USART_BRR_BRR_Msk = 0xffff

	// GTPR: Guard time and prescaler register
	// Position of GT field.
	USART_GTPR_GT_Pos = 0x8
	// Bit mask of GT field.
	USART_GTPR_GT_Msk = 0xff00
	// Position of PSC field.
	USART_GTPR_PSC_Pos = 0x0
	// Bit mask of PSC field.
	USART_GTPR_PSC_Msk = 0xff

	// RTOR: Receiver timeout register
	// Position of BLEN field.
	USART_RTOR_BLEN_Pos = 0x18
	// Bit mask of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000
	// Position of RTO field.
	USART_RTOR_RTO_Pos = 0x0
	// Bit mask of RTO field.
	USART_RTOR_RTO_Msk = 0xffffff

	// RQR: Request register
	// Position of TXFRQ field.
	USART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	USART_RQR_TXFRQ = 0x10
	// Set the TXE flags. This allows to discard the transmit data
	USART_RQR_TXFRQ_Discard = 0x1
	// Position of RXFRQ field.
	USART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	USART_RQR_RXFRQ = 0x8
	// clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
	USART_RQR_RXFRQ_Discard = 0x1
	// Position of MMRQ field.
	USART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	USART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	USART_RQR_MMRQ = 0x4
	// Puts the USART in mute mode and sets the RWU flag
	USART_RQR_MMRQ_Mute = 0x1
	// Position of SBKRQ field.
	USART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	USART_RQR_SBKRQ = 0x2
	// sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
	USART_RQR_SBKRQ_Break = 0x1
	// Position of ABRRQ field.
	USART_RQR_ABRRQ_Pos = 0x0
	// Bit mask of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1
	// Bit ABRRQ.
	USART_RQR_ABRRQ = 0x1
	// resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
	USART_RQR_ABRRQ_Request = 0x1

	// ISR: Interrupt & status register
	// Position of REACK field.
	USART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	USART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	USART_ISR_REACK = 0x400000
	// Position of TEACK field.
	USART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	USART_ISR_TEACK = 0x200000
	// Position of RWU field.
	USART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	USART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	USART_ISR_RWU = 0x80000
	// Position of SBKF field.
	USART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	USART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	USART_ISR_SBKF = 0x40000
	// No break character transmitted
	USART_ISR_SBKF_NoBreak = 0x0
	// Break character transmitted
	USART_ISR_SBKF_Break = 0x1
	// Position of CMF field.
	USART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	USART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	USART_ISR_CMF = 0x20000
	// No Character match detected
	USART_ISR_CMF_NoMatch = 0x0
	// Character match detected
	USART_ISR_CMF_Match = 0x1
	// Position of BUSY field.
	USART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	USART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	USART_ISR_BUSY = 0x10000
	// USART is idle (no reception)
	USART_ISR_BUSY_Idle = 0x0
	// Reception on going
	USART_ISR_BUSY_Busy = 0x1
	// Position of ABRF field.
	USART_ISR_ABRF_Pos = 0xf
	// Bit mask of ABRF field.
	USART_ISR_ABRF_Msk = 0x8000
	// Bit ABRF.
	USART_ISR_ABRF = 0x8000
	// Position of ABRE field.
	USART_ISR_ABRE_Pos = 0xe
	// Bit mask of ABRE field.
	USART_ISR_ABRE_Msk = 0x4000
	// Bit ABRE.
	USART_ISR_ABRE = 0x4000
	// Position of EOBF field.
	USART_ISR_EOBF_Pos = 0xc
	// Bit mask of EOBF field.
	USART_ISR_EOBF_Msk = 0x1000
	// Bit EOBF.
	USART_ISR_EOBF = 0x1000
	// End of Block not reached
	USART_ISR_EOBF_NotReached = 0x0
	// End of Block (number of characters) reached
	USART_ISR_EOBF_Reached = 0x1
	// Position of RTOF field.
	USART_ISR_RTOF_Pos = 0xb
	// Bit mask of RTOF field.
	USART_ISR_RTOF_Msk = 0x800
	// Bit RTOF.
	USART_ISR_RTOF = 0x800
	// Timeout value not reached
	USART_ISR_RTOF_NotReached = 0x0
	// Timeout value reached without any data reception
	USART_ISR_RTOF_Reached = 0x1
	// Position of CTS field.
	USART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	USART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	USART_ISR_CTS = 0x400
	// CTS line set
	USART_ISR_CTS_Set = 0x0
	// CTS line reset
	USART_ISR_CTS_Reset = 0x1
	// Position of CTSIF field.
	USART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	USART_ISR_CTSIF = 0x200
	// No change occurred on the CTS status line
	USART_ISR_CTSIF_NotChanged = 0x0
	// A change occurred on the CTS status line
	USART_ISR_CTSIF_Changed = 0x1
	// Position of LBDF field.
	USART_ISR_LBDF_Pos = 0x8
	// Bit mask of LBDF field.
	USART_ISR_LBDF_Msk = 0x100
	// Bit LBDF.
	USART_ISR_LBDF = 0x100
	// LIN break not detected
	USART_ISR_LBDF_NotDetected = 0x0
	// LIN break detected
	USART_ISR_LBDF_Detected = 0x1
	// Position of TXFNF field.
	USART_ISR_TXFNF_Pos = 0x7
	// Bit mask of TXFNF field.
	USART_ISR_TXFNF_Msk = 0x80
	// Bit TXFNF.
	USART_ISR_TXFNF = 0x80
	// Bit TXE. (added by gen-device-svd)
	USART_ISR_TXE = 0x80
	// Transmit FIFO is full
	USART_ISR_TXFNF_Full = 0x0
	// Transmit FIFO is not full
	USART_ISR_TXFNF_NotFull = 0x1
	// Position of TC field.
	USART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	USART_ISR_TC_Msk = 0x40
	// Bit TC.
	USART_ISR_TC = 0x40
	// Transmission is not complete
	USART_ISR_TC_TxNotComplete = 0x0
	// Transmission is complete
	USART_ISR_TC_TxComplete = 0x1
	// Position of RXFNE field.
	USART_ISR_RXFNE_Pos = 0x5
	// Bit mask of RXFNE field.
	USART_ISR_RXFNE_Msk = 0x20
	// Bit RXFNE.
	USART_ISR_RXFNE = 0x20
	// Data is not received
	USART_ISR_RXFNE_NoData = 0x0
	// Received data is ready to be read
	USART_ISR_RXFNE_DataReady = 0x1
	// Position of IDLE field.
	USART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	USART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	USART_ISR_IDLE = 0x10
	// No Idle Line is detected
	USART_ISR_IDLE_NoIdle = 0x0
	// Idle Line is detected
	USART_ISR_IDLE_Idle = 0x1
	// Position of ORE field.
	USART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	USART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	USART_ISR_ORE = 0x8
	// No Overrun error
	USART_ISR_ORE_NoOverrun = 0x0
	// Overrun error is detected
	USART_ISR_ORE_Overrun = 0x1
	// Position of NE field.
	USART_ISR_NE_Pos = 0x2
	// Bit mask of NE field.
	USART_ISR_NE_Msk = 0x4
	// Bit NE.
	USART_ISR_NE = 0x4
	// No noise is detected
	USART_ISR_NE_NoNoise = 0x0
	// Noise is detected
	USART_ISR_NE_Noise = 0x1
	// Position of FE field.
	USART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	USART_ISR_FE_Msk = 0x2
	// Bit FE.
	USART_ISR_FE = 0x2
	// No Framing error is detected
	USART_ISR_FE_NoError = 0x0
	// Framing error or break character is detected
	USART_ISR_FE_Error = 0x1
	// Position of PE field.
	USART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	USART_ISR_PE_Msk = 0x1
	// Bit PE.
	USART_ISR_PE = 0x1
	// No parity error
	USART_ISR_PE_NoError = 0x0
	// Parity error
	USART_ISR_PE_Error = 0x1
	// Position of TXFE field.
	USART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	USART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	USART_ISR_TXFE = 0x800000
	// TXFIFO not empty.
	USART_ISR_TXFE_NotEmpty = 0x0
	// TXFIFO empty.
	USART_ISR_TXFE_Empty = 0x1
	// Position of RXFF field.
	USART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	USART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	USART_ISR_RXFF = 0x1000000
	// RXFIFO not full.
	USART_ISR_RXFF_NotFull = 0x0
	// RXFIFO Full.
	USART_ISR_RXFF_Full = 0x1
	// Position of TCBGT field.
	USART_ISR_TCBGT_Pos = 0x19
	// Bit mask of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000
	// Bit TCBGT.
	USART_ISR_TCBGT = 0x2000000
	// Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
	USART_ISR_TCBGT_NotCompleted = 0x0
	// Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
	USART_ISR_TCBGT_Completed = 0x1
	// Position of RXFT field.
	USART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	USART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	USART_ISR_RXFT = 0x4000000
	// Receive FIFO does not reach the programmed threshold.
	USART_ISR_RXFT_NotReached = 0x0
	// Receive FIFO reached the programmed threshold.
	USART_ISR_RXFT_Reached = 0x1
	// Position of TXFT field.
	USART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	USART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	USART_ISR_TXFT = 0x8000000
	// TXFIFO does not reach the programmed threshold.
	USART_ISR_TXFT_NotReached = 0x0
	// TXFIFO reached the programmed threshold.
	USART_ISR_TXFT_Reached = 0x1
	// Position of UDR field.
	USART_ISR_UDR_Pos = 0xd
	// Bit mask of UDR field.
	USART_ISR_UDR_Msk = 0x2000
	// Bit UDR.
	USART_ISR_UDR = 0x2000
	// No underrun error
	USART_ISR_UDR_NoUnderrun = 0x0
	// underrun error
	USART_ISR_UDR_Underrun = 0x1

	// ICR: Interrupt flag clear register
	// Position of CMCF field.
	USART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	USART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	USART_ICR_CMCF = 0x20000
	// Clears the CMF flag in the ISR register
	USART_ICR_CMCF_Clear = 0x1
	// Position of EOBCF field.
	USART_ICR_EOBCF_Pos = 0xc
	// Bit mask of EOBCF field.
	USART_ICR_EOBCF_Msk = 0x1000
	// Bit EOBCF.
	USART_ICR_EOBCF = 0x1000
	// Clears the EOBF flag in the ISR register
	USART_ICR_EOBCF_Clear = 0x1
	// Position of RTOCF field.
	USART_ICR_RTOCF_Pos = 0xb
	// Bit mask of RTOCF field.
	USART_ICR_RTOCF_Msk = 0x800
	// Bit RTOCF.
	USART_ICR_RTOCF = 0x800
	// Clears the RTOF flag in the ISR register
	USART_ICR_RTOCF_Clear = 0x1
	// Position of CTSCF field.
	USART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	USART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	USART_ICR_CTSCF = 0x200
	// Clears the CTSIF flag in the ISR register
	USART_ICR_CTSCF_Clear = 0x1
	// Position of LBDCF field.
	USART_ICR_LBDCF_Pos = 0x8
	// Bit mask of LBDCF field.
	USART_ICR_LBDCF_Msk = 0x100
	// Bit LBDCF.
	USART_ICR_LBDCF = 0x100
	// Clears the LBDF flag in the ISR register
	USART_ICR_LBDCF_Clear = 0x1
	// Position of TCCF field.
	USART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	USART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	USART_ICR_TCCF = 0x40
	// Clears the TC flag in the ISR register
	USART_ICR_TCCF_Clear = 0x1
	// Position of IDLECF field.
	USART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	USART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	USART_ICR_IDLECF = 0x10
	// Clears the IDLE flag in the ISR register
	USART_ICR_IDLECF_Clear = 0x1
	// Position of ORECF field.
	USART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	USART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	USART_ICR_ORECF = 0x8
	// Clears the ORE flag in the ISR register
	USART_ICR_ORECF_Clear = 0x1
	// Position of NECF field.
	USART_ICR_NECF_Pos = 0x2
	// Bit mask of NECF field.
	USART_ICR_NECF_Msk = 0x4
	// Bit NECF.
	USART_ICR_NECF = 0x4
	// Clears the NF flag in the ISR register
	USART_ICR_NECF_Clear = 0x1
	// Position of FECF field.
	USART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	USART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	USART_ICR_FECF = 0x2
	// Clears the FE flag in the ISR register
	USART_ICR_FECF_Clear = 0x1
	// Position of PECF field.
	USART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	USART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	USART_ICR_PECF = 0x1
	// Clears the PE flag in the ISR register
	USART_ICR_PECF_Clear = 0x1
	// Position of TXFECF field.
	USART_ICR_TXFECF_Pos = 0x5
	// Bit mask of TXFECF field.
	USART_ICR_TXFECF_Msk = 0x20
	// Bit TXFECF.
	USART_ICR_TXFECF = 0x20
	// Clear the TXFE flag in the ISR register
	USART_ICR_TXFECF_Clear = 0x1
	// Position of TCBGTCF field.
	USART_ICR_TCBGTCF_Pos = 0x7
	// Bit mask of TCBGTCF field.
	USART_ICR_TCBGTCF_Msk = 0x80
	// Bit TCBGTCF.
	USART_ICR_TCBGTCF = 0x80
	// Clear the TCBGT flag in the ISR register
	USART_ICR_TCBGTCF_Clear = 0x1
	// Position of UDRCF field.
	USART_ICR_UDRCF_Pos = 0xd
	// Bit mask of UDRCF field.
	USART_ICR_UDRCF_Msk = 0x2000
	// Bit UDRCF.
	USART_ICR_UDRCF = 0x2000
	// Clear the UDR flag in the ISR register
	USART_ICR_UDRCF_Clear = 0x1

	// RDR: Receive data register
	// Position of RDR field.
	USART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	USART_RDR_RDR_Msk = 0x1ff

	// TDR: Transmit data register
	// Position of TDR field.
	USART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	USART_TDR_TDR_Msk = 0x1ff

	// PRESC: PRESC
	// Position of PRESCALER field.
	USART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf
	// Input clock divided by 1
	USART_PRESC_PRESCALER_Div1 = 0x0
	// Input clock divided by 2
	USART_PRESC_PRESCALER_Div2 = 0x1
	// Input clock divided by 4
	USART_PRESC_PRESCALER_Div4 = 0x2
	// Input clock divided by 6
	USART_PRESC_PRESCALER_Div6 = 0x3
	// Input clock divided by 8
	USART_PRESC_PRESCALER_Div8 = 0x4
	// Input clock divided by 10
	USART_PRESC_PRESCALER_Div10 = 0x5
	// Input clock divided by 12
	USART_PRESC_PRESCALER_Div12 = 0x6
	// Input clock divided by 16
	USART_PRESC_PRESCALER_Div16 = 0x7
	// Input clock divided by 32
	USART_PRESC_PRESCALER_Div32 = 0x8
	// Input clock divided by 64
	USART_PRESC_PRESCALER_Div64 = 0x9
	// Input clock divided by 128
	USART_PRESC_PRESCALER_Div128 = 0xa
	// Input clock divided by 256
	USART_PRESC_PRESCALER_Div256 = 0xb

	// AUTOCR: AUTOCR
	// Position of TECLREN field.
	USART_AUTOCR_TECLREN_Pos = 0x1f
	// Bit mask of TECLREN field.
	USART_AUTOCR_TECLREN_Msk = 0x80000000
	// Bit TECLREN.
	USART_AUTOCR_TECLREN = 0x80000000
	// Position of IDLEDIS field.
	USART_AUTOCR_IDLEDIS_Pos = 0x12
	// Bit mask of IDLEDIS field.
	USART_AUTOCR_IDLEDIS_Msk = 0x40000
	// Bit IDLEDIS.
	USART_AUTOCR_IDLEDIS = 0x40000
	// Position of TRIGSEL field.
	USART_AUTOCR_TRIGSEL_Pos = 0x13
	// Bit mask of TRIGSEL field.
	USART_AUTOCR_TRIGSEL_Msk = 0x780000
	// Position of TRIGEN field.
	USART_AUTOCR_TRIGEN_Pos = 0x11
	// Bit mask of TRIGEN field.
	USART_AUTOCR_TRIGEN_Msk = 0x20000
	// Bit TRIGEN.
	USART_AUTOCR_TRIGEN = 0x20000
	// Position of TRIGPOL field.
	USART_AUTOCR_TRIGPOL_Pos = 0x10
	// Bit mask of TRIGPOL field.
	USART_AUTOCR_TRIGPOL_Msk = 0x10000
	// Bit TRIGPOL.
	USART_AUTOCR_TRIGPOL = 0x10000
	// Position of TDN field.
	USART_AUTOCR_TDN_Pos = 0x0
	// Bit mask of TDN field.
	USART_AUTOCR_TDN_Msk = 0xffff
)

// Constants for VREFBUF: Voltage reference buffer
const (
	// CSR: VREFBUF control and status register
	// Position of ENVR field.
	VREF_CSR_ENVR_Pos = 0x0
	// Bit mask of ENVR field.
	VREF_CSR_ENVR_Msk = 0x1
	// Bit ENVR.
	VREF_CSR_ENVR = 0x1
	// Position of HIZ field.
	VREF_CSR_HIZ_Pos = 0x1
	// Bit mask of HIZ field.
	VREF_CSR_HIZ_Msk = 0x2
	// Bit HIZ.
	VREF_CSR_HIZ = 0x2
	// Position of VRR field.
	VREF_CSR_VRR_Pos = 0x3
	// Bit mask of VRR field.
	VREF_CSR_VRR_Msk = 0x8
	// Bit VRR.
	VREF_CSR_VRR = 0x8
	// Position of VRS field.
	VREF_CSR_VRS_Pos = 0x4
	// Bit mask of VRS field.
	VREF_CSR_VRS_Msk = 0x70

	// CCR: VREFBUF calibration control register
	// Position of TRIM field.
	VREF_CCR_TRIM_Pos = 0x0
	// Bit mask of TRIM field.
	VREF_CCR_TRIM_Msk = 0x3f
)

// Constants for WWDG: System window watchdog
const (
	// CR: Control register
	// Position of WDGA field.
	WWDG_CR_WDGA_Pos = 0x7
	// Bit mask of WDGA field.
	WWDG_CR_WDGA_Msk = 0x80
	// Bit WDGA.
	WWDG_CR_WDGA = 0x80
	// Watchdog disabled
	WWDG_CR_WDGA_Disabled = 0x0
	// Watchdog enabled
	WWDG_CR_WDGA_Enabled = 0x1
	// Position of T field.
	WWDG_CR_T_Pos = 0x0
	// Bit mask of T field.
	WWDG_CR_T_Msk = 0x7f

	// CFR: Configuration register
	// Position of WDGTB field.
	WWDG_CFR_WDGTB_Pos = 0xb
	// Bit mask of WDGTB field.
	WWDG_CFR_WDGTB_Msk = 0x3800
	// Counter clock (PCLK1 div 4096) div 1
	WWDG_CFR_WDGTB_Div1 = 0x0
	// Counter clock (PCLK1 div 4096) div 2
	WWDG_CFR_WDGTB_Div2 = 0x1
	// Counter clock (PCLK1 div 4096) div 4
	WWDG_CFR_WDGTB_Div4 = 0x2
	// Counter clock (PCLK1 div 4096) div 8
	WWDG_CFR_WDGTB_Div8 = 0x3
	// Counter clock (PCLK1 div 4096) div 16
	WWDG_CFR_WDGTB_Div16 = 0x4
	// Counter clock (PCLK1 div 4096) div 32
	WWDG_CFR_WDGTB_Div32 = 0x5
	// Counter clock (PCLK1 div 4096) div 64
	WWDG_CFR_WDGTB_Div64 = 0x6
	// Counter clock (PCLK1 div 4096) div 128
	WWDG_CFR_WDGTB_Div128 = 0x7
	// Position of EWI field.
	WWDG_CFR_EWI_Pos = 0x9
	// Bit mask of EWI field.
	WWDG_CFR_EWI_Msk = 0x200
	// Bit EWI.
	WWDG_CFR_EWI = 0x200
	// interrupt occurs whenever the counter reaches the value 0x40
	WWDG_CFR_EWI_Enable = 0x1
	// Position of W field.
	WWDG_CFR_W_Pos = 0x0
	// Bit mask of W field.
	WWDG_CFR_W_Msk = 0x7f

	// SR: Status register
	// Position of EWIF field.
	WWDG_SR_EWIF_Pos = 0x0
	// Bit mask of EWIF field.
	WWDG_SR_EWIF_Msk = 0x1
	// Bit EWIF.
	WWDG_SR_EWIF = 0x1
	// The EWI Interrupt Service Routine has been serviced
	WWDG_SR_EWIF_Finished = 0x0
	// The EWI Interrupt Service Routine has been triggered
	WWDG_SR_EWIF_Pending = 0x1
)

// Constants for DCB: Debug Control Block
const (
	// DSCSR: Debug Security Control and Status Register
	// Position of CDS field.
	DCB_DSCSR_CDS_Pos = 0x10
	// Bit mask of CDS field.
	DCB_DSCSR_CDS_Msk = 0x10000
	// Bit CDS.
	DCB_DSCSR_CDS = 0x10000
)
