// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from R7FA6E2BB.svd, see https://github.com/cmsis-svd/cmsis-svd-data/tree/master/data/Renesas

//go:build renesas && r7fa6e2bb

/*
// Arm Cortex-M33 based Microcontroller RA6E2 group
*/
//     This software is supplied by Renesas Electronics Corporation and is only intended for
//     use with Renesas products. No other uses are authorized. This software is owned by
//     Renesas Electronics Corporation and is protected under all applicable laws, including
//     copyright laws.
//
//     THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
//     THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO
//     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
//     ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT
//     PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED
//     COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
//     DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
//     BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
//
//     Renesas reserves the right, without notice, to make changes to this software and to
//     discontinue the availability of this software. By using this software, you agree to
//     the additional terms and conditions found by accessing the following link:
//     http://www.renesas.com/disclaimer
//     \n
package renesas

import (
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "R7FA6E2BB"
	CPU          = "CM33"
	FPUPresent   = true
	NVICPrioBits = 4
)

// Interrupt numbers.
const (
	// Interrupt Controller
	IRQ_IEL0 = 0

	// Interrupt Controller
	IRQ_IEL1 = 1

	// Interrupt Controller
	IRQ_IEL2 = 2

	// Interrupt Controller
	IRQ_IEL3 = 3

	// Interrupt Controller
	IRQ_IEL4 = 4

	// Interrupt Controller
	IRQ_IEL5 = 5

	// Interrupt Controller
	IRQ_IEL6 = 6

	// Interrupt Controller
	IRQ_IEL7 = 7

	// Interrupt Controller
	IRQ_IEL8 = 8

	// Interrupt Controller
	IRQ_IEL9 = 9

	// Interrupt Controller
	IRQ_IEL10 = 10

	// Interrupt Controller
	IRQ_IEL11 = 11

	// Interrupt Controller
	IRQ_IEL12 = 12

	// Interrupt Controller
	IRQ_IEL13 = 13

	// Interrupt Controller
	IRQ_IEL14 = 14

	// Interrupt Controller
	IRQ_IEL15 = 15

	// Interrupt Controller
	IRQ_IEL16 = 16

	// Interrupt Controller
	IRQ_IEL17 = 17

	// Interrupt Controller
	IRQ_IEL18 = 18

	// Interrupt Controller
	IRQ_IEL19 = 19

	// Interrupt Controller
	IRQ_IEL20 = 20

	// Interrupt Controller
	IRQ_IEL21 = 21

	// Interrupt Controller
	IRQ_IEL22 = 22

	// Interrupt Controller
	IRQ_IEL23 = 23

	// Interrupt Controller
	IRQ_IEL24 = 24

	// Interrupt Controller
	IRQ_IEL25 = 25

	// Interrupt Controller
	IRQ_IEL26 = 26

	// Interrupt Controller
	IRQ_IEL27 = 27

	// Interrupt Controller
	IRQ_IEL28 = 28

	// Interrupt Controller
	IRQ_IEL29 = 29

	// Interrupt Controller
	IRQ_IEL30 = 30

	// Interrupt Controller
	IRQ_IEL31 = 31

	// Interrupt Controller
	IRQ_IEL32 = 32

	// Interrupt Controller
	IRQ_IEL33 = 33

	// Interrupt Controller
	IRQ_IEL34 = 34

	// Interrupt Controller
	IRQ_IEL35 = 35

	// Interrupt Controller
	IRQ_IEL36 = 36

	// Interrupt Controller
	IRQ_IEL37 = 37

	// Interrupt Controller
	IRQ_IEL38 = 38

	// Interrupt Controller
	IRQ_IEL39 = 39

	// Interrupt Controller
	IRQ_IEL40 = 40

	// Interrupt Controller
	IRQ_IEL41 = 41

	// Interrupt Controller
	IRQ_IEL42 = 42

	// Interrupt Controller
	IRQ_IEL43 = 43

	// Interrupt Controller
	IRQ_IEL44 = 44

	// Interrupt Controller
	IRQ_IEL45 = 45

	// Interrupt Controller
	IRQ_IEL46 = 46

	// Interrupt Controller
	IRQ_IEL47 = 47

	// Interrupt Controller
	IRQ_IEL48 = 48

	// Interrupt Controller
	IRQ_IEL49 = 49

	// Interrupt Controller
	IRQ_IEL50 = 50

	// Interrupt Controller
	IRQ_IEL51 = 51

	// Interrupt Controller
	IRQ_IEL52 = 52

	// Interrupt Controller
	IRQ_IEL53 = 53

	// Interrupt Controller
	IRQ_IEL54 = 54

	// Interrupt Controller
	IRQ_IEL55 = 55

	// Interrupt Controller
	IRQ_IEL56 = 56

	// Interrupt Controller
	IRQ_IEL57 = 57

	// Interrupt Controller
	IRQ_IEL58 = 58

	// Interrupt Controller
	IRQ_IEL59 = 59

	// Interrupt Controller
	IRQ_IEL60 = 60

	// Interrupt Controller
	IRQ_IEL61 = 61

	// Interrupt Controller
	IRQ_IEL62 = 62

	// Interrupt Controller
	IRQ_IEL63 = 63

	// Interrupt Controller
	IRQ_IEL64 = 64

	// Interrupt Controller
	IRQ_IEL65 = 65

	// Interrupt Controller
	IRQ_IEL66 = 66

	// Interrupt Controller
	IRQ_IEL67 = 67

	// Interrupt Controller
	IRQ_IEL68 = 68

	// Interrupt Controller
	IRQ_IEL69 = 69

	// Interrupt Controller
	IRQ_IEL70 = 70

	// Interrupt Controller
	IRQ_IEL71 = 71

	// Interrupt Controller
	IRQ_IEL72 = 72

	// Interrupt Controller
	IRQ_IEL73 = 73

	// Interrupt Controller
	IRQ_IEL74 = 74

	// Interrupt Controller
	IRQ_IEL75 = 75

	// Interrupt Controller
	IRQ_IEL76 = 76

	// Interrupt Controller
	IRQ_IEL77 = 77

	// Interrupt Controller
	IRQ_IEL78 = 78

	// Interrupt Controller
	IRQ_IEL79 = 79

	// Interrupt Controller
	IRQ_IEL80 = 80

	// Interrupt Controller
	IRQ_IEL81 = 81

	// Interrupt Controller
	IRQ_IEL82 = 82

	// Interrupt Controller
	IRQ_IEL83 = 83

	// Interrupt Controller
	IRQ_IEL84 = 84

	// Interrupt Controller
	IRQ_IEL85 = 85

	// Interrupt Controller
	IRQ_IEL86 = 86

	// Interrupt Controller
	IRQ_IEL87 = 87

	// Interrupt Controller
	IRQ_IEL88 = 88

	// Interrupt Controller
	IRQ_IEL89 = 89

	// Interrupt Controller
	IRQ_IEL90 = 90

	// Interrupt Controller
	IRQ_IEL91 = 91

	// Interrupt Controller
	IRQ_IEL92 = 92

	// Interrupt Controller
	IRQ_IEL93 = 93

	// Interrupt Controller
	IRQ_IEL94 = 94

	// Interrupt Controller
	IRQ_IEL95 = 95

	// Highest interrupt number on this device.
	IRQ_max = 95
)

// Pseudo function call that is replaced by the compiler with the actual
// functions registered through interrupt.New.
//
//go:linkname callHandlers runtime/interrupt.callHandlers
func callHandlers(num int)

//export IEL0_IRQHandler
func interruptIEL0() {
	callHandlers(IRQ_IEL0)
}

//export IEL1_IRQHandler
func interruptIEL1() {
	callHandlers(IRQ_IEL1)
}

//export IEL2_IRQHandler
func interruptIEL2() {
	callHandlers(IRQ_IEL2)
}

//export IEL3_IRQHandler
func interruptIEL3() {
	callHandlers(IRQ_IEL3)
}

//export IEL4_IRQHandler
func interruptIEL4() {
	callHandlers(IRQ_IEL4)
}

//export IEL5_IRQHandler
func interruptIEL5() {
	callHandlers(IRQ_IEL5)
}

//export IEL6_IRQHandler
func interruptIEL6() {
	callHandlers(IRQ_IEL6)
}

//export IEL7_IRQHandler
func interruptIEL7() {
	callHandlers(IRQ_IEL7)
}

//export IEL8_IRQHandler
func interruptIEL8() {
	callHandlers(IRQ_IEL8)
}

//export IEL9_IRQHandler
func interruptIEL9() {
	callHandlers(IRQ_IEL9)
}

//export IEL10_IRQHandler
func interruptIEL10() {
	callHandlers(IRQ_IEL10)
}

//export IEL11_IRQHandler
func interruptIEL11() {
	callHandlers(IRQ_IEL11)
}

//export IEL12_IRQHandler
func interruptIEL12() {
	callHandlers(IRQ_IEL12)
}

//export IEL13_IRQHandler
func interruptIEL13() {
	callHandlers(IRQ_IEL13)
}

//export IEL14_IRQHandler
func interruptIEL14() {
	callHandlers(IRQ_IEL14)
}

//export IEL15_IRQHandler
func interruptIEL15() {
	callHandlers(IRQ_IEL15)
}

//export IEL16_IRQHandler
func interruptIEL16() {
	callHandlers(IRQ_IEL16)
}

//export IEL17_IRQHandler
func interruptIEL17() {
	callHandlers(IRQ_IEL17)
}

//export IEL18_IRQHandler
func interruptIEL18() {
	callHandlers(IRQ_IEL18)
}

//export IEL19_IRQHandler
func interruptIEL19() {
	callHandlers(IRQ_IEL19)
}

//export IEL20_IRQHandler
func interruptIEL20() {
	callHandlers(IRQ_IEL20)
}

//export IEL21_IRQHandler
func interruptIEL21() {
	callHandlers(IRQ_IEL21)
}

//export IEL22_IRQHandler
func interruptIEL22() {
	callHandlers(IRQ_IEL22)
}

//export IEL23_IRQHandler
func interruptIEL23() {
	callHandlers(IRQ_IEL23)
}

//export IEL24_IRQHandler
func interruptIEL24() {
	callHandlers(IRQ_IEL24)
}

//export IEL25_IRQHandler
func interruptIEL25() {
	callHandlers(IRQ_IEL25)
}

//export IEL26_IRQHandler
func interruptIEL26() {
	callHandlers(IRQ_IEL26)
}

//export IEL27_IRQHandler
func interruptIEL27() {
	callHandlers(IRQ_IEL27)
}

//export IEL28_IRQHandler
func interruptIEL28() {
	callHandlers(IRQ_IEL28)
}

//export IEL29_IRQHandler
func interruptIEL29() {
	callHandlers(IRQ_IEL29)
}

//export IEL30_IRQHandler
func interruptIEL30() {
	callHandlers(IRQ_IEL30)
}

//export IEL31_IRQHandler
func interruptIEL31() {
	callHandlers(IRQ_IEL31)
}

//export IEL32_IRQHandler
func interruptIEL32() {
	callHandlers(IRQ_IEL32)
}

//export IEL33_IRQHandler
func interruptIEL33() {
	callHandlers(IRQ_IEL33)
}

//export IEL34_IRQHandler
func interruptIEL34() {
	callHandlers(IRQ_IEL34)
}

//export IEL35_IRQHandler
func interruptIEL35() {
	callHandlers(IRQ_IEL35)
}

//export IEL36_IRQHandler
func interruptIEL36() {
	callHandlers(IRQ_IEL36)
}

//export IEL37_IRQHandler
func interruptIEL37() {
	callHandlers(IRQ_IEL37)
}

//export IEL38_IRQHandler
func interruptIEL38() {
	callHandlers(IRQ_IEL38)
}

//export IEL39_IRQHandler
func interruptIEL39() {
	callHandlers(IRQ_IEL39)
}

//export IEL40_IRQHandler
func interruptIEL40() {
	callHandlers(IRQ_IEL40)
}

//export IEL41_IRQHandler
func interruptIEL41() {
	callHandlers(IRQ_IEL41)
}

//export IEL42_IRQHandler
func interruptIEL42() {
	callHandlers(IRQ_IEL42)
}

//export IEL43_IRQHandler
func interruptIEL43() {
	callHandlers(IRQ_IEL43)
}

//export IEL44_IRQHandler
func interruptIEL44() {
	callHandlers(IRQ_IEL44)
}

//export IEL45_IRQHandler
func interruptIEL45() {
	callHandlers(IRQ_IEL45)
}

//export IEL46_IRQHandler
func interruptIEL46() {
	callHandlers(IRQ_IEL46)
}

//export IEL47_IRQHandler
func interruptIEL47() {
	callHandlers(IRQ_IEL47)
}

//export IEL48_IRQHandler
func interruptIEL48() {
	callHandlers(IRQ_IEL48)
}

//export IEL49_IRQHandler
func interruptIEL49() {
	callHandlers(IRQ_IEL49)
}

//export IEL50_IRQHandler
func interruptIEL50() {
	callHandlers(IRQ_IEL50)
}

//export IEL51_IRQHandler
func interruptIEL51() {
	callHandlers(IRQ_IEL51)
}

//export IEL52_IRQHandler
func interruptIEL52() {
	callHandlers(IRQ_IEL52)
}

//export IEL53_IRQHandler
func interruptIEL53() {
	callHandlers(IRQ_IEL53)
}

//export IEL54_IRQHandler
func interruptIEL54() {
	callHandlers(IRQ_IEL54)
}

//export IEL55_IRQHandler
func interruptIEL55() {
	callHandlers(IRQ_IEL55)
}

//export IEL56_IRQHandler
func interruptIEL56() {
	callHandlers(IRQ_IEL56)
}

//export IEL57_IRQHandler
func interruptIEL57() {
	callHandlers(IRQ_IEL57)
}

//export IEL58_IRQHandler
func interruptIEL58() {
	callHandlers(IRQ_IEL58)
}

//export IEL59_IRQHandler
func interruptIEL59() {
	callHandlers(IRQ_IEL59)
}

//export IEL60_IRQHandler
func interruptIEL60() {
	callHandlers(IRQ_IEL60)
}

//export IEL61_IRQHandler
func interruptIEL61() {
	callHandlers(IRQ_IEL61)
}

//export IEL62_IRQHandler
func interruptIEL62() {
	callHandlers(IRQ_IEL62)
}

//export IEL63_IRQHandler
func interruptIEL63() {
	callHandlers(IRQ_IEL63)
}

//export IEL64_IRQHandler
func interruptIEL64() {
	callHandlers(IRQ_IEL64)
}

//export IEL65_IRQHandler
func interruptIEL65() {
	callHandlers(IRQ_IEL65)
}

//export IEL66_IRQHandler
func interruptIEL66() {
	callHandlers(IRQ_IEL66)
}

//export IEL67_IRQHandler
func interruptIEL67() {
	callHandlers(IRQ_IEL67)
}

//export IEL68_IRQHandler
func interruptIEL68() {
	callHandlers(IRQ_IEL68)
}

//export IEL69_IRQHandler
func interruptIEL69() {
	callHandlers(IRQ_IEL69)
}

//export IEL70_IRQHandler
func interruptIEL70() {
	callHandlers(IRQ_IEL70)
}

//export IEL71_IRQHandler
func interruptIEL71() {
	callHandlers(IRQ_IEL71)
}

//export IEL72_IRQHandler
func interruptIEL72() {
	callHandlers(IRQ_IEL72)
}

//export IEL73_IRQHandler
func interruptIEL73() {
	callHandlers(IRQ_IEL73)
}

//export IEL74_IRQHandler
func interruptIEL74() {
	callHandlers(IRQ_IEL74)
}

//export IEL75_IRQHandler
func interruptIEL75() {
	callHandlers(IRQ_IEL75)
}

//export IEL76_IRQHandler
func interruptIEL76() {
	callHandlers(IRQ_IEL76)
}

//export IEL77_IRQHandler
func interruptIEL77() {
	callHandlers(IRQ_IEL77)
}

//export IEL78_IRQHandler
func interruptIEL78() {
	callHandlers(IRQ_IEL78)
}

//export IEL79_IRQHandler
func interruptIEL79() {
	callHandlers(IRQ_IEL79)
}

//export IEL80_IRQHandler
func interruptIEL80() {
	callHandlers(IRQ_IEL80)
}

//export IEL81_IRQHandler
func interruptIEL81() {
	callHandlers(IRQ_IEL81)
}

//export IEL82_IRQHandler
func interruptIEL82() {
	callHandlers(IRQ_IEL82)
}

//export IEL83_IRQHandler
func interruptIEL83() {
	callHandlers(IRQ_IEL83)
}

//export IEL84_IRQHandler
func interruptIEL84() {
	callHandlers(IRQ_IEL84)
}

//export IEL85_IRQHandler
func interruptIEL85() {
	callHandlers(IRQ_IEL85)
}

//export IEL86_IRQHandler
func interruptIEL86() {
	callHandlers(IRQ_IEL86)
}

//export IEL87_IRQHandler
func interruptIEL87() {
	callHandlers(IRQ_IEL87)
}

//export IEL88_IRQHandler
func interruptIEL88() {
	callHandlers(IRQ_IEL88)
}

//export IEL89_IRQHandler
func interruptIEL89() {
	callHandlers(IRQ_IEL89)
}

//export IEL90_IRQHandler
func interruptIEL90() {
	callHandlers(IRQ_IEL90)
}

//export IEL91_IRQHandler
func interruptIEL91() {
	callHandlers(IRQ_IEL91)
}

//export IEL92_IRQHandler
func interruptIEL92() {
	callHandlers(IRQ_IEL92)
}

//export IEL93_IRQHandler
func interruptIEL93() {
	callHandlers(IRQ_IEL93)
}

//export IEL94_IRQHandler
func interruptIEL94() {
	callHandlers(IRQ_IEL94)
}

//export IEL95_IRQHandler
func interruptIEL95() {
	callHandlers(IRQ_IEL95)
}

// Peripherals.
var (
	// Renesas Memory Protection Unit
	RMPU = (*RMPU_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// TrustZone Filter
	TZF = (*TZF_Type)(unsafe.Pointer(uintptr(0x40000e00)))

	// SRAM Control
	SRAM = (*SRAM_Type)(unsafe.Pointer(uintptr(0x40002000)))

	// Bus Control
	BUS = (*BUS_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Direct memory access controller 0
	DMAC0 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x40005000)))

	// Direct memory access controller 1
	DMAC1 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x40005040)))

	// Direct memory access controller 2
	DMAC2 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x40005080)))

	// Direct memory access controller 3
	DMAC3 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x400050c0)))

	// Direct memory access controller 4
	DMAC4 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x40005100)))

	// Direct memory access controller 5
	DMAC5 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x40005140)))

	// Direct memory access controller 6
	DMAC6 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x40005180)))

	// Direct memory access controller 7
	DMAC7 = (*DMAC0_Type)(unsafe.Pointer(uintptr(0x400051c0)))

	// DMAC Module Activation
	DMA = (*DMA_Type)(unsafe.Pointer(uintptr(0x40005200)))

	// Data Transfer Controller
	DTC = (*DTC_Type)(unsafe.Pointer(uintptr(0x40005400)))

	// Interrupt Controller
	ICU = (*ICU_Type)(unsafe.Pointer(uintptr(0x40006000)))

	// CACHE
	CACHE = (*CACHE_Type)(unsafe.Pointer(uintptr(0x40007000)))

	// CPU System Security Control Unit
	CPSCU = (*CPSCU_Type)(unsafe.Pointer(uintptr(0x40008000)))

	// Debug Function
	DBG = (*DBG_Type)(unsafe.Pointer(uintptr(0x4001b000)))

	// SYSTEM/FLASH
	FCACHE = (*FCACHE_Type)(unsafe.Pointer(uintptr(0x4001c100)))

	// System Control
	SYSC = (*SYSC_Type)(unsafe.Pointer(uintptr(0x4001e000)))

	// Pmn Pin FunctionPort 0 Control RegistersPmn Pin Function Control Register
	PORT0 = (*PORT0_Type)(unsafe.Pointer(uintptr(0x40080000)))

	// Pmn Pin FunctionPort 1 Control RegistersPmn Pin Function Control Register
	PORT1 = (*PORT1_Type)(unsafe.Pointer(uintptr(0x40080020)))

	// Pmn Pin FunctionPort 2 Control RegistersPmn Pin Function Control Register
	PORT2 = (*PORT1_Type)(unsafe.Pointer(uintptr(0x40080040)))

	// Pmn Pin FunctionPort 3 Control RegistersPmn Pin Function Control Register
	PORT3 = (*PORT1_Type)(unsafe.Pointer(uintptr(0x40080060)))

	// Pmn Pin FunctionPort 4 Control RegistersPmn Pin Function Control Register
	PORT4 = (*PORT1_Type)(unsafe.Pointer(uintptr(0x40080080)))

	// Pmn Pin FunctionPort 5 Control RegistersPmn Pin Function Control Register
	PORT5 = (*PORT0_Type)(unsafe.Pointer(uintptr(0x400800a0)))

	// Pmn Pin FunctionPort 8 Control RegistersPmn Pin Function Control Register
	PORT8 = (*PORT0_Type)(unsafe.Pointer(uintptr(0x40080100)))

	// Control Register
	PFS = (*PFS_Type)(unsafe.Pointer(uintptr(0x40080800)))

	// Event Link Controller
	ELC = (*ELC_Type)(unsafe.Pointer(uintptr(0x40082000)))

	// Realtime Clock
	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x40083000)))

	// Independent Watchdog Timer
	IWDT = (*IWDT_Type)(unsafe.Pointer(uintptr(0x40083200)))

	// Watchdog Timer
	WDT = (*WDT_Type)(unsafe.Pointer(uintptr(0x40083400)))

	// Clock Frequency Accuracy Measurement Circuit
	CAC = (*CAC_Type)(unsafe.Pointer(uintptr(0x40083600)))

	// Module Stop Control
	MSTP = (*MSTP_Type)(unsafe.Pointer(uintptr(0x40084000)))

	// Port Output Enable Module for GPT
	POEG = (*POEG_Type)(unsafe.Pointer(uintptr(0x4008a000)))

	// USB 2.0 Full-Speed Module
	USBFS = (*USBFS_Type)(unsafe.Pointer(uintptr(0x40090000)))

	// Serial Sound Interface Enhanced (SSIE)
	SSIE0 = (*SSIE0_Type)(unsafe.Pointer(uintptr(0x4009d000)))

	// Consumer Electronics Control
	CEC = (*CEC_Type)(unsafe.Pointer(uintptr(0x400ac000)))

	// CANFD
	CANFD_B = (*CANFD_B_Type)(unsafe.Pointer(uintptr(0x400b0000)))

	// Peripheral Security Control Unit
	PSCU = (*PSCU_Type)(unsafe.Pointer(uintptr(0x400e0000)))

	// Low Power Asynchronous General Purpose Timer 0
	AGTW0 = (*AGTW0_Type)(unsafe.Pointer(uintptr(0x400e8000)))

	// Low Power Asynchronous General Purpose Timer 1
	AGTW1 = (*AGTW0_Type)(unsafe.Pointer(uintptr(0x400e8100)))

	// Temperature Sensor
	TSN = (*TSN_Type)(unsafe.Pointer(uintptr(0x400f3000)))

	// Cyclic Redundancy Check Calculator
	CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x40108000)))

	// Data Operation Circuit
	DOC = (*DOC_Type)(unsafe.Pointer(uintptr(0x40109000)))

	// Serial Communication Interface
	SCI0 = (*SCI0_Type)(unsafe.Pointer(uintptr(0x40118000)))

	// Serial Communication Interface
	SCI9 = (*SCI0_Type)(unsafe.Pointer(uintptr(0x40118900)))

	// Serial Peripheral Interface 0
	SPI0 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x4011a000)))

	// Serial Peripheral Interface 1
	SPI1 = (*SPI0_Type)(unsafe.Pointer(uintptr(0x4011a100)))

	// I3C Bus Interface
	I3C = (*I3C_Type)(unsafe.Pointer(uintptr(0x4011f000)))

	// ECCMB
	ECCMB = (*ECCMB_Type)(unsafe.Pointer(uintptr(0x4012f200)))

	// General PWM 16-bit Timer 0
	GPT16E0 = (*GPT16E0_Type)(unsafe.Pointer(uintptr(0x40169000)))

	// General PWM 16-bit Timer 1
	GPT16E1 = (*GPT16E0_Type)(unsafe.Pointer(uintptr(0x40169100)))

	// General PWM 16-bit Timer 2
	GPT16E2 = (*GPT16E0_Type)(unsafe.Pointer(uintptr(0x40169200)))

	// General PWM 16-bit Timer 3
	GPT16E3 = (*GPT16E0_Type)(unsafe.Pointer(uintptr(0x40169300)))

	// General PWM 16-bit Timer 4
	GPT16E4 = (*GPT16E0_Type)(unsafe.Pointer(uintptr(0x40169400)))

	// General PWM 16-bit Timer 5
	GPT16E5 = (*GPT16E0_Type)(unsafe.Pointer(uintptr(0x40169500)))

	// Output Phase Switching Controller
	GPT_OPS = (*GPT_OPS_Type)(unsafe.Pointer(uintptr(0x40169a00)))

	// 12-bit A/D Converter
	ADC120 = (*ADC120_Type)(unsafe.Pointer(uintptr(0x40170000)))

	// 12-bit D/A converter
	DAC12 = (*DAC12_Type)(unsafe.Pointer(uintptr(0x40171000)))

	// Temperature Sensor Calibration Data
	TSD = (*TSD_Type)(unsafe.Pointer(uintptr(0x407fb000)))

	// Data Flash
	FLAD = (*FLAD_Type)(unsafe.Pointer(uintptr(0x407fc000)))

	// Flash/CPU Interface
	FACI = (*FACI_Type)(unsafe.Pointer(uintptr(0x407fe000)))

	// Quad Serial Peripheral Interface
	QSPI = (*QSPI_Type)(unsafe.Pointer(uintptr(0x64000000)))
)

// Renesas Memory Protection Unit
type RMPU_Type struct {
	MMPUOAD         volatile.Register16 // 0x0
	_               [2]byte
	MMPUOADPT       volatile.Register16 // 0x4
	_               [250]byte
	MMPUENDMAC      volatile.Register16 // 0x100
	_               [2]byte
	MMPUENPTDMAC    volatile.Register16 // 0x104
	_               [2]byte
	MMPURPTDMAC     volatile.Register16 // 0x108
	_               [2]byte
	MMPURPTDMAC_SEC volatile.Register16 // 0x10C
	_               [242]byte
	MMPUACDMAC0     volatile.Register16 // 0x200
	_               [2]byte
	MMPUSDMAC0      volatile.Register32 // 0x204
	MMPUEDMAC0      volatile.Register32 // 0x208
	_               [4]byte
	MMPUACDMAC1     volatile.Register16 // 0x210
	_               [2]byte
	MMPUSDMAC1      volatile.Register32 // 0x214
	MMPUEDMAC1      volatile.Register32 // 0x218
	_               [4]byte
	MMPUACDMAC2     volatile.Register16 // 0x220
	_               [2]byte
	MMPUSDMAC2      volatile.Register32 // 0x224
	MMPUEDMAC2      volatile.Register32 // 0x228
	_               [4]byte
	MMPUACDMAC3     volatile.Register16 // 0x230
	_               [2]byte
	MMPUSDMAC3      volatile.Register32 // 0x234
	MMPUEDMAC3      volatile.Register32 // 0x238
	_               [4]byte
	MMPUACDMAC4     volatile.Register16 // 0x240
	_               [2]byte
	MMPUSDMAC4      volatile.Register32 // 0x244
	MMPUEDMAC4      volatile.Register32 // 0x248
	_               [4]byte
	MMPUACDMAC5     volatile.Register16 // 0x250
	_               [2]byte
	MMPUSDMAC5      volatile.Register32 // 0x254
	MMPUEDMAC5      volatile.Register32 // 0x258
	_               [4]byte
	MMPUACDMAC6     volatile.Register16 // 0x260
	_               [2]byte
	MMPUSDMAC6      volatile.Register32 // 0x264
	MMPUEDMAC6      volatile.Register32 // 0x268
	_               [4]byte
	MMPUACDMAC7     volatile.Register16 // 0x270
	_               [2]byte
	MMPUSDMAC7      volatile.Register32 // 0x274
	MMPUEDMAC7      volatile.Register32 // 0x278
}

// RMPU.MMPUOAD: MMPU Operation After Detection Register
func (o *RMPU_Type) SetMMPUOAD_OAD(value uint16) {
	volatile.StoreUint16(&o.MMPUOAD.Reg, volatile.LoadUint16(&o.MMPUOAD.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUOAD_OAD() uint16 {
	return volatile.LoadUint16(&o.MMPUOAD.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUOAD_KEY(value uint16) {
	volatile.StoreUint16(&o.MMPUOAD.Reg, volatile.LoadUint16(&o.MMPUOAD.Reg)&^(0xff00)|value<<8)
}
func (o *RMPU_Type) GetMMPUOAD_KEY() uint16 {
	return (volatile.LoadUint16(&o.MMPUOAD.Reg) & 0xff00) >> 8
}

// RMPU.MMPUOADPT: MMPU Operation After Detection Protect Register
func (o *RMPU_Type) SetMMPUOADPT_PROTECT(value uint16) {
	volatile.StoreUint16(&o.MMPUOADPT.Reg, volatile.LoadUint16(&o.MMPUOADPT.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUOADPT_PROTECT() uint16 {
	return volatile.LoadUint16(&o.MMPUOADPT.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUOADPT_KEY(value uint16) {
	volatile.StoreUint16(&o.MMPUOADPT.Reg, volatile.LoadUint16(&o.MMPUOADPT.Reg)&^(0xff00)|value<<8)
}
func (o *RMPU_Type) GetMMPUOADPT_KEY() uint16 {
	return (volatile.LoadUint16(&o.MMPUOADPT.Reg) & 0xff00) >> 8
}

// RMPU.MMPUENDMAC: MMPU Enable Register for DMAC
func (o *RMPU_Type) SetMMPUENDMAC_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUENDMAC.Reg, volatile.LoadUint16(&o.MMPUENDMAC.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUENDMAC_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUENDMAC.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUENDMAC_KEY(value uint16) {
	volatile.StoreUint16(&o.MMPUENDMAC.Reg, volatile.LoadUint16(&o.MMPUENDMAC.Reg)&^(0xff00)|value<<8)
}
func (o *RMPU_Type) GetMMPUENDMAC_KEY() uint16 {
	return (volatile.LoadUint16(&o.MMPUENDMAC.Reg) & 0xff00) >> 8
}

// RMPU.MMPUENPTDMAC: MMPU Enable Protect Register for DMAC
func (o *RMPU_Type) SetMMPUENPTDMAC_PROTECT(value uint16) {
	volatile.StoreUint16(&o.MMPUENPTDMAC.Reg, volatile.LoadUint16(&o.MMPUENPTDMAC.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUENPTDMAC_PROTECT() uint16 {
	return volatile.LoadUint16(&o.MMPUENPTDMAC.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUENPTDMAC_KEY(value uint16) {
	volatile.StoreUint16(&o.MMPUENPTDMAC.Reg, volatile.LoadUint16(&o.MMPUENPTDMAC.Reg)&^(0xff00)|value<<8)
}
func (o *RMPU_Type) GetMMPUENPTDMAC_KEY() uint16 {
	return (volatile.LoadUint16(&o.MMPUENPTDMAC.Reg) & 0xff00) >> 8
}

// RMPU.MMPURPTDMAC: MMPU Regions Protect Register for DMAC
func (o *RMPU_Type) SetMMPURPTDMAC_PROTECT(value uint16) {
	volatile.StoreUint16(&o.MMPURPTDMAC.Reg, volatile.LoadUint16(&o.MMPURPTDMAC.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPURPTDMAC_PROTECT() uint16 {
	return volatile.LoadUint16(&o.MMPURPTDMAC.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPURPTDMAC_KEY(value uint16) {
	volatile.StoreUint16(&o.MMPURPTDMAC.Reg, volatile.LoadUint16(&o.MMPURPTDMAC.Reg)&^(0xff00)|value<<8)
}
func (o *RMPU_Type) GetMMPURPTDMAC_KEY() uint16 {
	return (volatile.LoadUint16(&o.MMPURPTDMAC.Reg) & 0xff00) >> 8
}

// RMPU.MMPURPTDMAC_SEC: MMPU Regions Protect register for DMAC Secure
func (o *RMPU_Type) SetMMPURPTDMAC_SEC_PROTECT(value uint16) {
	volatile.StoreUint16(&o.MMPURPTDMAC_SEC.Reg, volatile.LoadUint16(&o.MMPURPTDMAC_SEC.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPURPTDMAC_SEC_PROTECT() uint16 {
	return volatile.LoadUint16(&o.MMPURPTDMAC_SEC.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPURPTDMAC_SEC_KEY(value uint16) {
	volatile.StoreUint16(&o.MMPURPTDMAC_SEC.Reg, volatile.LoadUint16(&o.MMPURPTDMAC_SEC.Reg)&^(0xff00)|value<<8)
}
func (o *RMPU_Type) GetMMPURPTDMAC_SEC_KEY() uint16 {
	return (volatile.LoadUint16(&o.MMPURPTDMAC_SEC.Reg) & 0xff00) >> 8
}

// RMPU.MMPUACDMAC0: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC0_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC0.Reg, volatile.LoadUint16(&o.MMPUACDMAC0.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC0_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC0.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC0_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC0.Reg, volatile.LoadUint16(&o.MMPUACDMAC0.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC0_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC0.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC0_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC0.Reg, volatile.LoadUint16(&o.MMPUACDMAC0.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC0_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC0.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC0: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC0_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC0.Reg, volatile.LoadUint32(&o.MMPUSDMAC0.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC0_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC0.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC0: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC0_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC0.Reg, volatile.LoadUint32(&o.MMPUEDMAC0.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC0_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC0.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUACDMAC1: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC1_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC1.Reg, volatile.LoadUint16(&o.MMPUACDMAC1.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC1_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC1.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC1_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC1.Reg, volatile.LoadUint16(&o.MMPUACDMAC1.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC1_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC1.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC1_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC1.Reg, volatile.LoadUint16(&o.MMPUACDMAC1.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC1_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC1.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC1: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC1_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC1.Reg, volatile.LoadUint32(&o.MMPUSDMAC1.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC1_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC1.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC1: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC1_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC1.Reg, volatile.LoadUint32(&o.MMPUEDMAC1.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC1_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC1.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUACDMAC2: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC2_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC2.Reg, volatile.LoadUint16(&o.MMPUACDMAC2.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC2_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC2.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC2_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC2.Reg, volatile.LoadUint16(&o.MMPUACDMAC2.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC2_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC2.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC2_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC2.Reg, volatile.LoadUint16(&o.MMPUACDMAC2.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC2_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC2.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC2: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC2_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC2.Reg, volatile.LoadUint32(&o.MMPUSDMAC2.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC2_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC2.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC2: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC2_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC2.Reg, volatile.LoadUint32(&o.MMPUEDMAC2.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC2_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC2.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUACDMAC3: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC3_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC3.Reg, volatile.LoadUint16(&o.MMPUACDMAC3.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC3_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC3.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC3_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC3.Reg, volatile.LoadUint16(&o.MMPUACDMAC3.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC3_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC3.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC3_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC3.Reg, volatile.LoadUint16(&o.MMPUACDMAC3.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC3_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC3.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC3: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC3_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC3.Reg, volatile.LoadUint32(&o.MMPUSDMAC3.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC3_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC3.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC3: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC3_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC3.Reg, volatile.LoadUint32(&o.MMPUEDMAC3.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC3_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC3.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUACDMAC4: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC4_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC4.Reg, volatile.LoadUint16(&o.MMPUACDMAC4.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC4_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC4.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC4_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC4.Reg, volatile.LoadUint16(&o.MMPUACDMAC4.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC4_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC4.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC4_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC4.Reg, volatile.LoadUint16(&o.MMPUACDMAC4.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC4_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC4.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC4: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC4_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC4.Reg, volatile.LoadUint32(&o.MMPUSDMAC4.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC4_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC4.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC4: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC4_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC4.Reg, volatile.LoadUint32(&o.MMPUEDMAC4.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC4_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC4.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUACDMAC5: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC5_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC5.Reg, volatile.LoadUint16(&o.MMPUACDMAC5.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC5_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC5.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC5_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC5.Reg, volatile.LoadUint16(&o.MMPUACDMAC5.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC5_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC5.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC5_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC5.Reg, volatile.LoadUint16(&o.MMPUACDMAC5.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC5_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC5.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC5: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC5_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC5.Reg, volatile.LoadUint32(&o.MMPUSDMAC5.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC5_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC5.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC5: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC5_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC5.Reg, volatile.LoadUint32(&o.MMPUEDMAC5.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC5_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC5.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUACDMAC6: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC6_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC6.Reg, volatile.LoadUint16(&o.MMPUACDMAC6.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC6_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC6.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC6_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC6.Reg, volatile.LoadUint16(&o.MMPUACDMAC6.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC6_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC6.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC6_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC6.Reg, volatile.LoadUint16(&o.MMPUACDMAC6.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC6_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC6.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC6: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC6_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC6.Reg, volatile.LoadUint32(&o.MMPUSDMAC6.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC6_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC6.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC6: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC6_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC6.Reg, volatile.LoadUint32(&o.MMPUEDMAC6.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC6_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC6.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUACDMAC7: MMPU Access Control Register for DMAC
func (o *RMPU_Type) SetMMPUACDMAC7_ENABLE(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC7.Reg, volatile.LoadUint16(&o.MMPUACDMAC7.Reg)&^(0x1)|value)
}
func (o *RMPU_Type) GetMMPUACDMAC7_ENABLE() uint16 {
	return volatile.LoadUint16(&o.MMPUACDMAC7.Reg) & 0x1
}
func (o *RMPU_Type) SetMMPUACDMAC7_RP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC7.Reg, volatile.LoadUint16(&o.MMPUACDMAC7.Reg)&^(0x2)|value<<1)
}
func (o *RMPU_Type) GetMMPUACDMAC7_RP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC7.Reg) & 0x2) >> 1
}
func (o *RMPU_Type) SetMMPUACDMAC7_WP(value uint16) {
	volatile.StoreUint16(&o.MMPUACDMAC7.Reg, volatile.LoadUint16(&o.MMPUACDMAC7.Reg)&^(0x4)|value<<2)
}
func (o *RMPU_Type) GetMMPUACDMAC7_WP() uint16 {
	return (volatile.LoadUint16(&o.MMPUACDMAC7.Reg) & 0x4) >> 2
}

// RMPU.MMPUSDMAC7: MMPU Start Address Register for DMAC
func (o *RMPU_Type) SetMMPUSDMAC7_MMPUS(value uint32) {
	volatile.StoreUint32(&o.MMPUSDMAC7.Reg, volatile.LoadUint32(&o.MMPUSDMAC7.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUSDMAC7_MMPUS() uint32 {
	return (volatile.LoadUint32(&o.MMPUSDMAC7.Reg) & 0xffffffe0) >> 5
}

// RMPU.MMPUEDMAC7: MMPU End Address Register for DMAC
func (o *RMPU_Type) SetMMPUEDMAC7_MMPUE(value uint32) {
	volatile.StoreUint32(&o.MMPUEDMAC7.Reg, volatile.LoadUint32(&o.MMPUEDMAC7.Reg)&^(0xffffffe0)|value<<5)
}
func (o *RMPU_Type) GetMMPUEDMAC7_MMPUE() uint32 {
	return (volatile.LoadUint32(&o.MMPUEDMAC7.Reg) & 0xffffffe0) >> 5
}

// TrustZone Filter
type TZF_Type struct {
	TZFOAD volatile.Register16 // 0x0
	_      [2]byte
	TZFPT  volatile.Register16 // 0x4
}

// TZF.TZFOAD: TrustZone Filter Operation After Detection Register
func (o *TZF_Type) SetTZFOAD_OAD(value uint16) {
	volatile.StoreUint16(&o.TZFOAD.Reg, volatile.LoadUint16(&o.TZFOAD.Reg)&^(0x1)|value)
}
func (o *TZF_Type) GetTZFOAD_OAD() uint16 {
	return volatile.LoadUint16(&o.TZFOAD.Reg) & 0x1
}
func (o *TZF_Type) SetTZFOAD_KEY(value uint16) {
	volatile.StoreUint16(&o.TZFOAD.Reg, volatile.LoadUint16(&o.TZFOAD.Reg)&^(0xff00)|value<<8)
}
func (o *TZF_Type) GetTZFOAD_KEY() uint16 {
	return (volatile.LoadUint16(&o.TZFOAD.Reg) & 0xff00) >> 8
}

// TZF.TZFPT: TrustZone Filter Protect Register
func (o *TZF_Type) SetTZFPT_PROTECT(value uint16) {
	volatile.StoreUint16(&o.TZFPT.Reg, volatile.LoadUint16(&o.TZFPT.Reg)&^(0x1)|value)
}
func (o *TZF_Type) GetTZFPT_PROTECT() uint16 {
	return volatile.LoadUint16(&o.TZFPT.Reg) & 0x1
}
func (o *TZF_Type) SetTZFPT_KEY(value uint16) {
	volatile.StoreUint16(&o.TZFPT.Reg, volatile.LoadUint16(&o.TZFPT.Reg)&^(0xff00)|value<<8)
}
func (o *TZF_Type) GetTZFPT_KEY() uint16 {
	return (volatile.LoadUint16(&o.TZFPT.Reg) & 0xff00) >> 8
}

// SRAM Control
type SRAM_Type struct {
	PARIOAD   volatile.Register8 // 0x0
	_         [3]byte
	SRAMPRCR  volatile.Register8 // 0x4
	_         [3]byte
	SRAMWTSC  volatile.Register8 // 0x8
	_         [3]byte
	SRAMPRCR2 volatile.Register8 // 0xC
	_         [179]byte
	ECCMODE   volatile.Register8 // 0xC0
	ECC2STS   volatile.Register8 // 0xC1
	ECC1STSEN volatile.Register8 // 0xC2
	ECC1STS   volatile.Register8 // 0xC3
	ECCPRCR   volatile.Register8 // 0xC4
	_         [11]byte
	ECCPRCR2  volatile.Register8 // 0xD0
	_         [3]byte
	ECCETST   volatile.Register8 // 0xD4
	_         [3]byte
	ECCOAD    volatile.Register8 // 0xD8
}

// SRAM.PARIOAD: SRAM Parity Error Operation After Detection Register
func (o *SRAM_Type) SetPARIOAD_OAD(value uint8) {
	volatile.StoreUint8(&o.PARIOAD.Reg, volatile.LoadUint8(&o.PARIOAD.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetPARIOAD_OAD() uint8 {
	return volatile.LoadUint8(&o.PARIOAD.Reg) & 0x1
}

// SRAM.SRAMPRCR: SRAM Protection Register
func (o *SRAM_Type) SetSRAMPRCR(value uint8) {
	volatile.StoreUint8(&o.SRAMPRCR.Reg, volatile.LoadUint8(&o.SRAMPRCR.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetSRAMPRCR() uint8 {
	return volatile.LoadUint8(&o.SRAMPRCR.Reg) & 0x1
}
func (o *SRAM_Type) SetSRAMPRCR_KW(value uint8) {
	volatile.StoreUint8(&o.SRAMPRCR.Reg, volatile.LoadUint8(&o.SRAMPRCR.Reg)&^(0xfe)|value<<1)
}
func (o *SRAM_Type) GetSRAMPRCR_KW() uint8 {
	return (volatile.LoadUint8(&o.SRAMPRCR.Reg) & 0xfe) >> 1
}

// SRAM.SRAMWTSC: SRAM Wait State Control Register
func (o *SRAM_Type) SetSRAMWTSC_SRAM0WTEN(value uint8) {
	volatile.StoreUint8(&o.SRAMWTSC.Reg, volatile.LoadUint8(&o.SRAMWTSC.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetSRAMWTSC_SRAM0WTEN() uint8 {
	return volatile.LoadUint8(&o.SRAMWTSC.Reg) & 0x1
}

// SRAM.SRAMPRCR2: SRAM Protection Register 2
func (o *SRAM_Type) SetSRAMPRCR2(value uint8) {
	volatile.StoreUint8(&o.SRAMPRCR2.Reg, volatile.LoadUint8(&o.SRAMPRCR2.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetSRAMPRCR2() uint8 {
	return volatile.LoadUint8(&o.SRAMPRCR2.Reg) & 0x1
}
func (o *SRAM_Type) SetSRAMPRCR2_KW(value uint8) {
	volatile.StoreUint8(&o.SRAMPRCR2.Reg, volatile.LoadUint8(&o.SRAMPRCR2.Reg)&^(0xfe)|value<<1)
}
func (o *SRAM_Type) GetSRAMPRCR2_KW() uint8 {
	return (volatile.LoadUint8(&o.SRAMPRCR2.Reg) & 0xfe) >> 1
}

// SRAM.ECCMODE: ECC Operating Mode Control Register
func (o *SRAM_Type) SetECCMODE_ECCMOD(value uint8) {
	volatile.StoreUint8(&o.ECCMODE.Reg, volatile.LoadUint8(&o.ECCMODE.Reg)&^(0x3)|value)
}
func (o *SRAM_Type) GetECCMODE_ECCMOD() uint8 {
	return volatile.LoadUint8(&o.ECCMODE.Reg) & 0x3
}

// SRAM.ECC2STS: ECC 2-Bit Error Status Register
func (o *SRAM_Type) SetECC2STS_ECC2ERR(value uint8) {
	volatile.StoreUint8(&o.ECC2STS.Reg, volatile.LoadUint8(&o.ECC2STS.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetECC2STS_ECC2ERR() uint8 {
	return volatile.LoadUint8(&o.ECC2STS.Reg) & 0x1
}

// SRAM.ECC1STSEN: ECC 1-Bit Error Information Update Enable Register
func (o *SRAM_Type) SetECC1STSEN_E1STSEN(value uint8) {
	volatile.StoreUint8(&o.ECC1STSEN.Reg, volatile.LoadUint8(&o.ECC1STSEN.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetECC1STSEN_E1STSEN() uint8 {
	return volatile.LoadUint8(&o.ECC1STSEN.Reg) & 0x1
}

// SRAM.ECC1STS: ECC 1-Bit Error Status Register
func (o *SRAM_Type) SetECC1STS_ECC1ERR(value uint8) {
	volatile.StoreUint8(&o.ECC1STS.Reg, volatile.LoadUint8(&o.ECC1STS.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetECC1STS_ECC1ERR() uint8 {
	return volatile.LoadUint8(&o.ECC1STS.Reg) & 0x1
}

// SRAM.ECCPRCR: ECC Protection Register
func (o *SRAM_Type) SetECCPRCR(value uint8) {
	volatile.StoreUint8(&o.ECCPRCR.Reg, volatile.LoadUint8(&o.ECCPRCR.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetECCPRCR() uint8 {
	return volatile.LoadUint8(&o.ECCPRCR.Reg) & 0x1
}
func (o *SRAM_Type) SetECCPRCR_KW(value uint8) {
	volatile.StoreUint8(&o.ECCPRCR.Reg, volatile.LoadUint8(&o.ECCPRCR.Reg)&^(0xfe)|value<<1)
}
func (o *SRAM_Type) GetECCPRCR_KW() uint8 {
	return (volatile.LoadUint8(&o.ECCPRCR.Reg) & 0xfe) >> 1
}

// SRAM.ECCPRCR2: ECC Protection Register 2
func (o *SRAM_Type) SetECCPRCR2(value uint8) {
	volatile.StoreUint8(&o.ECCPRCR2.Reg, volatile.LoadUint8(&o.ECCPRCR2.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetECCPRCR2() uint8 {
	return volatile.LoadUint8(&o.ECCPRCR2.Reg) & 0x1
}
func (o *SRAM_Type) SetECCPRCR2_KW2(value uint8) {
	volatile.StoreUint8(&o.ECCPRCR2.Reg, volatile.LoadUint8(&o.ECCPRCR2.Reg)&^(0xfe)|value<<1)
}
func (o *SRAM_Type) GetECCPRCR2_KW2() uint8 {
	return (volatile.LoadUint8(&o.ECCPRCR2.Reg) & 0xfe) >> 1
}

// SRAM.ECCETST: ECC Test Control Register
func (o *SRAM_Type) SetECCETST_TSTBYP(value uint8) {
	volatile.StoreUint8(&o.ECCETST.Reg, volatile.LoadUint8(&o.ECCETST.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetECCETST_TSTBYP() uint8 {
	return volatile.LoadUint8(&o.ECCETST.Reg) & 0x1
}

// SRAM.ECCOAD: SRAM ECC Error Operation After Detection Register
func (o *SRAM_Type) SetECCOAD_OAD(value uint8) {
	volatile.StoreUint8(&o.ECCOAD.Reg, volatile.LoadUint8(&o.ECCOAD.Reg)&^(0x1)|value)
}
func (o *SRAM_Type) GetECCOAD_OAD() uint8 {
	return volatile.LoadUint8(&o.ECCOAD.Reg) & 0x1
}

// Bus Control
type BUS_Type struct {
	_              [4352]byte
	BUSSCNTFHBIU   volatile.Register16 // 0x1100
	_              [2]byte
	BUSSCNTFLBIU   volatile.Register16 // 0x1104
	_              [10]byte
	BUSSCNTS0BIU   volatile.Register16 // 0x1110
	_              [14]byte
	BUSSCNTPSBIU   volatile.Register16 // 0x1120
	_              [14]byte
	BUSSCNTPLBIU   volatile.Register16 // 0x1130
	_              [2]byte
	BUSSCNTPHBIU   volatile.Register16 // 0x1134
	_              [10]byte
	BUSSCNTEQBIU   volatile.Register16 // 0x1140
	_              [1726]byte
	BUS1ERRADD     volatile.Register32 // 0x1800
	BUS1ERRRW      volatile.Register8  // 0x1804
	_              [11]byte
	BUS2ERRADD     volatile.Register32 // 0x1810
	BUS2ERRRW      volatile.Register8  // 0x1814
	_              [11]byte
	BUS3ERRADD     volatile.Register32 // 0x1820
	BUS3ERRRW      volatile.Register8  // 0x1824
	_              [219]byte
	BTZF1ERRADD    volatile.Register32 // 0x1900
	BTZF1ERRRW     volatile.Register8  // 0x1904
	_              [11]byte
	BTZF2ERRADD    volatile.Register32 // 0x1910
	BTZF2ERRRW     volatile.Register8  // 0x1914
	_              [11]byte
	BTZF3ERRADD    volatile.Register32 // 0x1920
	BTZF3ERRRW     volatile.Register8  // 0x1924
	_              [219]byte
	BUS1ERRSTAT    volatile.Register8 // 0x1A00
	_              [7]byte
	BUS1ERRCLR     volatile.Register8 // 0x1A08
	_              [7]byte
	BUS2ERRSTAT    volatile.Register8 // 0x1A10
	_              [7]byte
	BUS2ERRCLR     volatile.Register8 // 0x1A18
	_              [7]byte
	BUS3ERRSTAT    volatile.Register8 // 0x1A20
	_              [3]byte
	DMACDTCERRSTAT volatile.Register8 // 0x1A24
	_              [3]byte
	BUS3ERRCLR     volatile.Register8 // 0x1A28
	_              [3]byte
	DMACDTCERRCLR  volatile.Register8 // 0x1A2C
}

// BUS.BUSSCNTFHBIU: Slave Bus Control Register
func (o *BUS_Type) SetBUSSCNTFHBIU_ARBS(value uint16) {
	volatile.StoreUint16(&o.BUSSCNTFHBIU.Reg, volatile.LoadUint16(&o.BUSSCNTFHBIU.Reg)&^(0x3)|value)
}
func (o *BUS_Type) GetBUSSCNTFHBIU_ARBS() uint16 {
	return volatile.LoadUint16(&o.BUSSCNTFHBIU.Reg) & 0x3
}

// BUS.BUSSCNTFLBIU: Slave Bus Control Register
func (o *BUS_Type) SetBUSSCNTFLBIU_ARBS(value uint16) {
	volatile.StoreUint16(&o.BUSSCNTFLBIU.Reg, volatile.LoadUint16(&o.BUSSCNTFLBIU.Reg)&^(0x3)|value)
}
func (o *BUS_Type) GetBUSSCNTFLBIU_ARBS() uint16 {
	return volatile.LoadUint16(&o.BUSSCNTFLBIU.Reg) & 0x3
}

// BUS.BUSSCNTS0BIU: Slave Bus Control Register
func (o *BUS_Type) SetBUSSCNTS0BIU_ARBS(value uint16) {
	volatile.StoreUint16(&o.BUSSCNTS0BIU.Reg, volatile.LoadUint16(&o.BUSSCNTS0BIU.Reg)&^(0x3)|value)
}
func (o *BUS_Type) GetBUSSCNTS0BIU_ARBS() uint16 {
	return volatile.LoadUint16(&o.BUSSCNTS0BIU.Reg) & 0x3
}

// BUS.BUSSCNTPSBIU: Slave Bus Control Register
func (o *BUS_Type) SetBUSSCNTPSBIU_ARBS(value uint16) {
	volatile.StoreUint16(&o.BUSSCNTPSBIU.Reg, volatile.LoadUint16(&o.BUSSCNTPSBIU.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUSSCNTPSBIU_ARBS() uint16 {
	return volatile.LoadUint16(&o.BUSSCNTPSBIU.Reg) & 0x1
}

// BUS.BUSSCNTPLBIU: Slave Bus Control Register
func (o *BUS_Type) SetBUSSCNTPLBIU_ARBS(value uint16) {
	volatile.StoreUint16(&o.BUSSCNTPLBIU.Reg, volatile.LoadUint16(&o.BUSSCNTPLBIU.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUSSCNTPLBIU_ARBS() uint16 {
	return volatile.LoadUint16(&o.BUSSCNTPLBIU.Reg) & 0x1
}

// BUS.BUSSCNTPHBIU: Slave Bus Control Register
func (o *BUS_Type) SetBUSSCNTPHBIU_ARBS(value uint16) {
	volatile.StoreUint16(&o.BUSSCNTPHBIU.Reg, volatile.LoadUint16(&o.BUSSCNTPHBIU.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUSSCNTPHBIU_ARBS() uint16 {
	return volatile.LoadUint16(&o.BUSSCNTPHBIU.Reg) & 0x1
}

// BUS.BUSSCNTEQBIU: Slave Bus Control Register
func (o *BUS_Type) SetBUSSCNTEQBIU_ARBS(value uint16) {
	volatile.StoreUint16(&o.BUSSCNTEQBIU.Reg, volatile.LoadUint16(&o.BUSSCNTEQBIU.Reg)&^(0x3)|value)
}
func (o *BUS_Type) GetBUSSCNTEQBIU_ARBS() uint16 {
	return volatile.LoadUint16(&o.BUSSCNTEQBIU.Reg) & 0x3
}

// BUS.BUS1ERRADD: BUS Error Address Register
func (o *BUS_Type) SetBUS1ERRADD(value uint32) {
	volatile.StoreUint32(&o.BUS1ERRADD.Reg, value)
}
func (o *BUS_Type) GetBUS1ERRADD() uint32 {
	return volatile.LoadUint32(&o.BUS1ERRADD.Reg)
}

// BUS.BUS1ERRRW: BUS Error Read Write Register
func (o *BUS_Type) SetBUS1ERRRW_RWSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRRW.Reg, volatile.LoadUint8(&o.BUS1ERRRW.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS1ERRRW_RWSTAT() uint8 {
	return volatile.LoadUint8(&o.BUS1ERRRW.Reg) & 0x1
}

// BUS.BUS2ERRADD: BUS Error Address Register
func (o *BUS_Type) SetBUS2ERRADD(value uint32) {
	volatile.StoreUint32(&o.BUS2ERRADD.Reg, value)
}
func (o *BUS_Type) GetBUS2ERRADD() uint32 {
	return volatile.LoadUint32(&o.BUS2ERRADD.Reg)
}

// BUS.BUS2ERRRW: BUS Error Read Write Register
func (o *BUS_Type) SetBUS2ERRRW_RWSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRRW.Reg, volatile.LoadUint8(&o.BUS2ERRRW.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS2ERRRW_RWSTAT() uint8 {
	return volatile.LoadUint8(&o.BUS2ERRRW.Reg) & 0x1
}

// BUS.BUS3ERRADD: BUS Error Address Register
func (o *BUS_Type) SetBUS3ERRADD(value uint32) {
	volatile.StoreUint32(&o.BUS3ERRADD.Reg, value)
}
func (o *BUS_Type) GetBUS3ERRADD() uint32 {
	return volatile.LoadUint32(&o.BUS3ERRADD.Reg)
}

// BUS.BUS3ERRRW: BUS Error Read Write Register
func (o *BUS_Type) SetBUS3ERRRW_RWSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRRW.Reg, volatile.LoadUint8(&o.BUS3ERRRW.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS3ERRRW_RWSTAT() uint8 {
	return volatile.LoadUint8(&o.BUS3ERRRW.Reg) & 0x1
}

// BUS.BTZF1ERRADD: BUS TZF Error Address Register
func (o *BUS_Type) SetBTZF1ERRADD(value uint32) {
	volatile.StoreUint32(&o.BTZF1ERRADD.Reg, value)
}
func (o *BUS_Type) GetBTZF1ERRADD() uint32 {
	return volatile.LoadUint32(&o.BTZF1ERRADD.Reg)
}

// BUS.BTZF1ERRRW: BUS TZF Error Read Write Register
func (o *BUS_Type) SetBTZF1ERRRW_TRWSTAT(value uint8) {
	volatile.StoreUint8(&o.BTZF1ERRRW.Reg, volatile.LoadUint8(&o.BTZF1ERRRW.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBTZF1ERRRW_TRWSTAT() uint8 {
	return volatile.LoadUint8(&o.BTZF1ERRRW.Reg) & 0x1
}

// BUS.BTZF2ERRADD: BUS TZF Error Address Register
func (o *BUS_Type) SetBTZF2ERRADD(value uint32) {
	volatile.StoreUint32(&o.BTZF2ERRADD.Reg, value)
}
func (o *BUS_Type) GetBTZF2ERRADD() uint32 {
	return volatile.LoadUint32(&o.BTZF2ERRADD.Reg)
}

// BUS.BTZF2ERRRW: BUS TZF Error Read Write Register
func (o *BUS_Type) SetBTZF2ERRRW_TRWSTAT(value uint8) {
	volatile.StoreUint8(&o.BTZF2ERRRW.Reg, volatile.LoadUint8(&o.BTZF2ERRRW.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBTZF2ERRRW_TRWSTAT() uint8 {
	return volatile.LoadUint8(&o.BTZF2ERRRW.Reg) & 0x1
}

// BUS.BTZF3ERRADD: BUS TZF Error Address Register
func (o *BUS_Type) SetBTZF3ERRADD(value uint32) {
	volatile.StoreUint32(&o.BTZF3ERRADD.Reg, value)
}
func (o *BUS_Type) GetBTZF3ERRADD() uint32 {
	return volatile.LoadUint32(&o.BTZF3ERRADD.Reg)
}

// BUS.BTZF3ERRRW: BUS TZF Error Read Write Register
func (o *BUS_Type) SetBTZF3ERRRW_TRWSTAT(value uint8) {
	volatile.StoreUint8(&o.BTZF3ERRRW.Reg, volatile.LoadUint8(&o.BTZF3ERRRW.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBTZF3ERRRW_TRWSTAT() uint8 {
	return volatile.LoadUint8(&o.BTZF3ERRRW.Reg) & 0x1
}

// BUS.BUS1ERRSTAT: BUS Error Status Register %s
func (o *BUS_Type) SetBUS1ERRSTAT_SLERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRSTAT.Reg, volatile.LoadUint8(&o.BUS1ERRSTAT.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS1ERRSTAT_SLERRSTAT() uint8 {
	return volatile.LoadUint8(&o.BUS1ERRSTAT.Reg) & 0x1
}
func (o *BUS_Type) SetBUS1ERRSTAT_STERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRSTAT.Reg, volatile.LoadUint8(&o.BUS1ERRSTAT.Reg)&^(0x2)|value<<1)
}
func (o *BUS_Type) GetBUS1ERRSTAT_STERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS1ERRSTAT.Reg) & 0x2) >> 1
}
func (o *BUS_Type) SetBUS1ERRSTAT_MMERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRSTAT.Reg, volatile.LoadUint8(&o.BUS1ERRSTAT.Reg)&^(0x8)|value<<3)
}
func (o *BUS_Type) GetBUS1ERRSTAT_MMERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS1ERRSTAT.Reg) & 0x8) >> 3
}
func (o *BUS_Type) SetBUS1ERRSTAT_ILERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRSTAT.Reg, volatile.LoadUint8(&o.BUS1ERRSTAT.Reg)&^(0x10)|value<<4)
}
func (o *BUS_Type) GetBUS1ERRSTAT_ILERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS1ERRSTAT.Reg) & 0x10) >> 4
}

// BUS.BUS1ERRCLR: BUS Error Clear Register %s
func (o *BUS_Type) SetBUS1ERRCLR_SLERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRCLR.Reg, volatile.LoadUint8(&o.BUS1ERRCLR.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS1ERRCLR_SLERRCLR() uint8 {
	return volatile.LoadUint8(&o.BUS1ERRCLR.Reg) & 0x1
}
func (o *BUS_Type) SetBUS1ERRCLR_STERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRCLR.Reg, volatile.LoadUint8(&o.BUS1ERRCLR.Reg)&^(0x2)|value<<1)
}
func (o *BUS_Type) GetBUS1ERRCLR_STERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS1ERRCLR.Reg) & 0x2) >> 1
}
func (o *BUS_Type) SetBUS1ERRCLR_MMERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRCLR.Reg, volatile.LoadUint8(&o.BUS1ERRCLR.Reg)&^(0x8)|value<<3)
}
func (o *BUS_Type) GetBUS1ERRCLR_MMERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS1ERRCLR.Reg) & 0x8) >> 3
}
func (o *BUS_Type) SetBUS1ERRCLR_ILERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS1ERRCLR.Reg, volatile.LoadUint8(&o.BUS1ERRCLR.Reg)&^(0x10)|value<<4)
}
func (o *BUS_Type) GetBUS1ERRCLR_ILERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS1ERRCLR.Reg) & 0x10) >> 4
}

// BUS.BUS2ERRSTAT: BUS Error Status Register %s
func (o *BUS_Type) SetBUS2ERRSTAT_SLERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRSTAT.Reg, volatile.LoadUint8(&o.BUS2ERRSTAT.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS2ERRSTAT_SLERRSTAT() uint8 {
	return volatile.LoadUint8(&o.BUS2ERRSTAT.Reg) & 0x1
}
func (o *BUS_Type) SetBUS2ERRSTAT_STERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRSTAT.Reg, volatile.LoadUint8(&o.BUS2ERRSTAT.Reg)&^(0x2)|value<<1)
}
func (o *BUS_Type) GetBUS2ERRSTAT_STERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS2ERRSTAT.Reg) & 0x2) >> 1
}
func (o *BUS_Type) SetBUS2ERRSTAT_MMERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRSTAT.Reg, volatile.LoadUint8(&o.BUS2ERRSTAT.Reg)&^(0x8)|value<<3)
}
func (o *BUS_Type) GetBUS2ERRSTAT_MMERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS2ERRSTAT.Reg) & 0x8) >> 3
}
func (o *BUS_Type) SetBUS2ERRSTAT_ILERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRSTAT.Reg, volatile.LoadUint8(&o.BUS2ERRSTAT.Reg)&^(0x10)|value<<4)
}
func (o *BUS_Type) GetBUS2ERRSTAT_ILERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS2ERRSTAT.Reg) & 0x10) >> 4
}

// BUS.BUS2ERRCLR: BUS Error Clear Register %s
func (o *BUS_Type) SetBUS2ERRCLR_SLERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRCLR.Reg, volatile.LoadUint8(&o.BUS2ERRCLR.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS2ERRCLR_SLERRCLR() uint8 {
	return volatile.LoadUint8(&o.BUS2ERRCLR.Reg) & 0x1
}
func (o *BUS_Type) SetBUS2ERRCLR_STERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRCLR.Reg, volatile.LoadUint8(&o.BUS2ERRCLR.Reg)&^(0x2)|value<<1)
}
func (o *BUS_Type) GetBUS2ERRCLR_STERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS2ERRCLR.Reg) & 0x2) >> 1
}
func (o *BUS_Type) SetBUS2ERRCLR_MMERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRCLR.Reg, volatile.LoadUint8(&o.BUS2ERRCLR.Reg)&^(0x8)|value<<3)
}
func (o *BUS_Type) GetBUS2ERRCLR_MMERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS2ERRCLR.Reg) & 0x8) >> 3
}
func (o *BUS_Type) SetBUS2ERRCLR_ILERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS2ERRCLR.Reg, volatile.LoadUint8(&o.BUS2ERRCLR.Reg)&^(0x10)|value<<4)
}
func (o *BUS_Type) GetBUS2ERRCLR_ILERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS2ERRCLR.Reg) & 0x10) >> 4
}

// BUS.BUS3ERRSTAT: BUS Error Status Register %s
func (o *BUS_Type) SetBUS3ERRSTAT_SLERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRSTAT.Reg, volatile.LoadUint8(&o.BUS3ERRSTAT.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS3ERRSTAT_SLERRSTAT() uint8 {
	return volatile.LoadUint8(&o.BUS3ERRSTAT.Reg) & 0x1
}
func (o *BUS_Type) SetBUS3ERRSTAT_STERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRSTAT.Reg, volatile.LoadUint8(&o.BUS3ERRSTAT.Reg)&^(0x2)|value<<1)
}
func (o *BUS_Type) GetBUS3ERRSTAT_STERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS3ERRSTAT.Reg) & 0x2) >> 1
}
func (o *BUS_Type) SetBUS3ERRSTAT_MMERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRSTAT.Reg, volatile.LoadUint8(&o.BUS3ERRSTAT.Reg)&^(0x8)|value<<3)
}
func (o *BUS_Type) GetBUS3ERRSTAT_MMERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS3ERRSTAT.Reg) & 0x8) >> 3
}
func (o *BUS_Type) SetBUS3ERRSTAT_ILERRSTAT(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRSTAT.Reg, volatile.LoadUint8(&o.BUS3ERRSTAT.Reg)&^(0x10)|value<<4)
}
func (o *BUS_Type) GetBUS3ERRSTAT_ILERRSTAT() uint8 {
	return (volatile.LoadUint8(&o.BUS3ERRSTAT.Reg) & 0x10) >> 4
}

// BUS.DMACDTCERRSTAT: DMAC/DTC Error Status Register
func (o *BUS_Type) SetDMACDTCERRSTAT_MTERRSTAT(value uint8) {
	volatile.StoreUint8(&o.DMACDTCERRSTAT.Reg, volatile.LoadUint8(&o.DMACDTCERRSTAT.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetDMACDTCERRSTAT_MTERRSTAT() uint8 {
	return volatile.LoadUint8(&o.DMACDTCERRSTAT.Reg) & 0x1
}

// BUS.BUS3ERRCLR: BUS Error Clear Register %s
func (o *BUS_Type) SetBUS3ERRCLR_SLERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRCLR.Reg, volatile.LoadUint8(&o.BUS3ERRCLR.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetBUS3ERRCLR_SLERRCLR() uint8 {
	return volatile.LoadUint8(&o.BUS3ERRCLR.Reg) & 0x1
}
func (o *BUS_Type) SetBUS3ERRCLR_STERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRCLR.Reg, volatile.LoadUint8(&o.BUS3ERRCLR.Reg)&^(0x2)|value<<1)
}
func (o *BUS_Type) GetBUS3ERRCLR_STERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS3ERRCLR.Reg) & 0x2) >> 1
}
func (o *BUS_Type) SetBUS3ERRCLR_MMERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRCLR.Reg, volatile.LoadUint8(&o.BUS3ERRCLR.Reg)&^(0x8)|value<<3)
}
func (o *BUS_Type) GetBUS3ERRCLR_MMERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS3ERRCLR.Reg) & 0x8) >> 3
}
func (o *BUS_Type) SetBUS3ERRCLR_ILERRCLR(value uint8) {
	volatile.StoreUint8(&o.BUS3ERRCLR.Reg, volatile.LoadUint8(&o.BUS3ERRCLR.Reg)&^(0x10)|value<<4)
}
func (o *BUS_Type) GetBUS3ERRCLR_ILERRCLR() uint8 {
	return (volatile.LoadUint8(&o.BUS3ERRCLR.Reg) & 0x10) >> 4
}

// BUS.DMACDTCERRCLR: DMAC/DTC Error Clear Register
func (o *BUS_Type) SetDMACDTCERRCLR_MTERRCLR(value uint8) {
	volatile.StoreUint8(&o.DMACDTCERRCLR.Reg, volatile.LoadUint8(&o.DMACDTCERRCLR.Reg)&^(0x1)|value)
}
func (o *BUS_Type) GetDMACDTCERRCLR_MTERRCLR() uint8 {
	return volatile.LoadUint8(&o.DMACDTCERRCLR.Reg) & 0x1
}

// Direct memory access controller 0
type DMAC0_Type struct {
	DMSAR volatile.Register32 // 0x0
	DMDAR volatile.Register32 // 0x4
	DMCRA volatile.Register32 // 0x8
	DMCRB volatile.Register32 // 0xC
	DMTMD volatile.Register16 // 0x10
	_     byte
	DMINT volatile.Register8  // 0x13
	DMAMD volatile.Register16 // 0x14
	_     [2]byte
	DMOFR volatile.Register32 // 0x18
	DMCNT volatile.Register8  // 0x1C
	DMREQ volatile.Register8  // 0x1D
	DMSTS volatile.Register8  // 0x1E
	_     byte
	DMSRR volatile.Register32 // 0x20
	DMDRR volatile.Register32 // 0x24
	DMSBS volatile.Register32 // 0x28
	DMDBS volatile.Register32 // 0x2C
}

// DMAC0.DMCRA: DMA Transfer Count Register
func (o *DMAC0_Type) SetDMCRA_DMCRAL(value uint32) {
	volatile.StoreUint32(&o.DMCRA.Reg, volatile.LoadUint32(&o.DMCRA.Reg)&^(0xffff)|value)
}
func (o *DMAC0_Type) GetDMCRA_DMCRAL() uint32 {
	return volatile.LoadUint32(&o.DMCRA.Reg) & 0xffff
}
func (o *DMAC0_Type) SetDMCRA_DMCRAH(value uint32) {
	volatile.StoreUint32(&o.DMCRA.Reg, volatile.LoadUint32(&o.DMCRA.Reg)&^(0x3ff0000)|value<<16)
}
func (o *DMAC0_Type) GetDMCRA_DMCRAH() uint32 {
	return (volatile.LoadUint32(&o.DMCRA.Reg) & 0x3ff0000) >> 16
}

// DMAC0.DMCRB: DMA Block Transfer Count Register
func (o *DMAC0_Type) SetDMCRB_DMCRBL(value uint32) {
	volatile.StoreUint32(&o.DMCRB.Reg, volatile.LoadUint32(&o.DMCRB.Reg)&^(0xffff)|value)
}
func (o *DMAC0_Type) GetDMCRB_DMCRBL() uint32 {
	return volatile.LoadUint32(&o.DMCRB.Reg) & 0xffff
}
func (o *DMAC0_Type) SetDMCRB_DMCRBH(value uint32) {
	volatile.StoreUint32(&o.DMCRB.Reg, volatile.LoadUint32(&o.DMCRB.Reg)&^(0xffff0000)|value<<16)
}
func (o *DMAC0_Type) GetDMCRB_DMCRBH() uint32 {
	return (volatile.LoadUint32(&o.DMCRB.Reg) & 0xffff0000) >> 16
}

// DMAC0.DMTMD: DMA Transfer Mode Register
func (o *DMAC0_Type) SetDMTMD_DCTG(value uint16) {
	volatile.StoreUint16(&o.DMTMD.Reg, volatile.LoadUint16(&o.DMTMD.Reg)&^(0x3)|value)
}
func (o *DMAC0_Type) GetDMTMD_DCTG() uint16 {
	return volatile.LoadUint16(&o.DMTMD.Reg) & 0x3
}
func (o *DMAC0_Type) SetDMTMD_SZ(value uint16) {
	volatile.StoreUint16(&o.DMTMD.Reg, volatile.LoadUint16(&o.DMTMD.Reg)&^(0x300)|value<<8)
}
func (o *DMAC0_Type) GetDMTMD_SZ() uint16 {
	return (volatile.LoadUint16(&o.DMTMD.Reg) & 0x300) >> 8
}
func (o *DMAC0_Type) SetDMTMD_TKP(value uint16) {
	volatile.StoreUint16(&o.DMTMD.Reg, volatile.LoadUint16(&o.DMTMD.Reg)&^(0x400)|value<<10)
}
func (o *DMAC0_Type) GetDMTMD_TKP() uint16 {
	return (volatile.LoadUint16(&o.DMTMD.Reg) & 0x400) >> 10
}
func (o *DMAC0_Type) SetDMTMD_DTS(value uint16) {
	volatile.StoreUint16(&o.DMTMD.Reg, volatile.LoadUint16(&o.DMTMD.Reg)&^(0x3000)|value<<12)
}
func (o *DMAC0_Type) GetDMTMD_DTS() uint16 {
	return (volatile.LoadUint16(&o.DMTMD.Reg) & 0x3000) >> 12
}
func (o *DMAC0_Type) SetDMTMD_MD(value uint16) {
	volatile.StoreUint16(&o.DMTMD.Reg, volatile.LoadUint16(&o.DMTMD.Reg)&^(0xc000)|value<<14)
}
func (o *DMAC0_Type) GetDMTMD_MD() uint16 {
	return (volatile.LoadUint16(&o.DMTMD.Reg) & 0xc000) >> 14
}

// DMAC0.DMINT: DMA Interrupt Setting Register
func (o *DMAC0_Type) SetDMINT_DARIE(value uint8) {
	volatile.StoreUint8(&o.DMINT.Reg, volatile.LoadUint8(&o.DMINT.Reg)&^(0x1)|value)
}
func (o *DMAC0_Type) GetDMINT_DARIE() uint8 {
	return volatile.LoadUint8(&o.DMINT.Reg) & 0x1
}
func (o *DMAC0_Type) SetDMINT_SARIE(value uint8) {
	volatile.StoreUint8(&o.DMINT.Reg, volatile.LoadUint8(&o.DMINT.Reg)&^(0x2)|value<<1)
}
func (o *DMAC0_Type) GetDMINT_SARIE() uint8 {
	return (volatile.LoadUint8(&o.DMINT.Reg) & 0x2) >> 1
}
func (o *DMAC0_Type) SetDMINT_RPTIE(value uint8) {
	volatile.StoreUint8(&o.DMINT.Reg, volatile.LoadUint8(&o.DMINT.Reg)&^(0x4)|value<<2)
}
func (o *DMAC0_Type) GetDMINT_RPTIE() uint8 {
	return (volatile.LoadUint8(&o.DMINT.Reg) & 0x4) >> 2
}
func (o *DMAC0_Type) SetDMINT_ESIE(value uint8) {
	volatile.StoreUint8(&o.DMINT.Reg, volatile.LoadUint8(&o.DMINT.Reg)&^(0x8)|value<<3)
}
func (o *DMAC0_Type) GetDMINT_ESIE() uint8 {
	return (volatile.LoadUint8(&o.DMINT.Reg) & 0x8) >> 3
}
func (o *DMAC0_Type) SetDMINT_DTIE(value uint8) {
	volatile.StoreUint8(&o.DMINT.Reg, volatile.LoadUint8(&o.DMINT.Reg)&^(0x10)|value<<4)
}
func (o *DMAC0_Type) GetDMINT_DTIE() uint8 {
	return (volatile.LoadUint8(&o.DMINT.Reg) & 0x10) >> 4
}

// DMAC0.DMAMD: DMA Address Mode Register
func (o *DMAC0_Type) SetDMAMD_DARA(value uint16) {
	volatile.StoreUint16(&o.DMAMD.Reg, volatile.LoadUint16(&o.DMAMD.Reg)&^(0x1f)|value)
}
func (o *DMAC0_Type) GetDMAMD_DARA() uint16 {
	return volatile.LoadUint16(&o.DMAMD.Reg) & 0x1f
}
func (o *DMAC0_Type) SetDMAMD_DADR(value uint16) {
	volatile.StoreUint16(&o.DMAMD.Reg, volatile.LoadUint16(&o.DMAMD.Reg)&^(0x20)|value<<5)
}
func (o *DMAC0_Type) GetDMAMD_DADR() uint16 {
	return (volatile.LoadUint16(&o.DMAMD.Reg) & 0x20) >> 5
}
func (o *DMAC0_Type) SetDMAMD_DM(value uint16) {
	volatile.StoreUint16(&o.DMAMD.Reg, volatile.LoadUint16(&o.DMAMD.Reg)&^(0xc0)|value<<6)
}
func (o *DMAC0_Type) GetDMAMD_DM() uint16 {
	return (volatile.LoadUint16(&o.DMAMD.Reg) & 0xc0) >> 6
}
func (o *DMAC0_Type) SetDMAMD_SARA(value uint16) {
	volatile.StoreUint16(&o.DMAMD.Reg, volatile.LoadUint16(&o.DMAMD.Reg)&^(0x1f00)|value<<8)
}
func (o *DMAC0_Type) GetDMAMD_SARA() uint16 {
	return (volatile.LoadUint16(&o.DMAMD.Reg) & 0x1f00) >> 8
}
func (o *DMAC0_Type) SetDMAMD_SADR(value uint16) {
	volatile.StoreUint16(&o.DMAMD.Reg, volatile.LoadUint16(&o.DMAMD.Reg)&^(0x2000)|value<<13)
}
func (o *DMAC0_Type) GetDMAMD_SADR() uint16 {
	return (volatile.LoadUint16(&o.DMAMD.Reg) & 0x2000) >> 13
}
func (o *DMAC0_Type) SetDMAMD_SM(value uint16) {
	volatile.StoreUint16(&o.DMAMD.Reg, volatile.LoadUint16(&o.DMAMD.Reg)&^(0xc000)|value<<14)
}
func (o *DMAC0_Type) GetDMAMD_SM() uint16 {
	return (volatile.LoadUint16(&o.DMAMD.Reg) & 0xc000) >> 14
}

// DMAC0.DMCNT: DMA Transfer Enable Register
func (o *DMAC0_Type) SetDMCNT_DTE(value uint8) {
	volatile.StoreUint8(&o.DMCNT.Reg, volatile.LoadUint8(&o.DMCNT.Reg)&^(0x1)|value)
}
func (o *DMAC0_Type) GetDMCNT_DTE() uint8 {
	return volatile.LoadUint8(&o.DMCNT.Reg) & 0x1
}

// DMAC0.DMREQ: DMA Software Start Register
func (o *DMAC0_Type) SetDMREQ_SWREQ(value uint8) {
	volatile.StoreUint8(&o.DMREQ.Reg, volatile.LoadUint8(&o.DMREQ.Reg)&^(0x1)|value)
}
func (o *DMAC0_Type) GetDMREQ_SWREQ() uint8 {
	return volatile.LoadUint8(&o.DMREQ.Reg) & 0x1
}
func (o *DMAC0_Type) SetDMREQ_CLRS(value uint8) {
	volatile.StoreUint8(&o.DMREQ.Reg, volatile.LoadUint8(&o.DMREQ.Reg)&^(0x10)|value<<4)
}
func (o *DMAC0_Type) GetDMREQ_CLRS() uint8 {
	return (volatile.LoadUint8(&o.DMREQ.Reg) & 0x10) >> 4
}

// DMAC0.DMSTS: DMA Status Register
func (o *DMAC0_Type) SetDMSTS_ESIF(value uint8) {
	volatile.StoreUint8(&o.DMSTS.Reg, volatile.LoadUint8(&o.DMSTS.Reg)&^(0x1)|value)
}
func (o *DMAC0_Type) GetDMSTS_ESIF() uint8 {
	return volatile.LoadUint8(&o.DMSTS.Reg) & 0x1
}
func (o *DMAC0_Type) SetDMSTS_DTIF(value uint8) {
	volatile.StoreUint8(&o.DMSTS.Reg, volatile.LoadUint8(&o.DMSTS.Reg)&^(0x10)|value<<4)
}
func (o *DMAC0_Type) GetDMSTS_DTIF() uint8 {
	return (volatile.LoadUint8(&o.DMSTS.Reg) & 0x10) >> 4
}
func (o *DMAC0_Type) SetDMSTS_ACT(value uint8) {
	volatile.StoreUint8(&o.DMSTS.Reg, volatile.LoadUint8(&o.DMSTS.Reg)&^(0x80)|value<<7)
}
func (o *DMAC0_Type) GetDMSTS_ACT() uint8 {
	return (volatile.LoadUint8(&o.DMSTS.Reg) & 0x80) >> 7
}

// DMAC0.DMSBS: DMA Source Buffer Size Register
func (o *DMAC0_Type) SetDMSBS_DMSBSL(value uint32) {
	volatile.StoreUint32(&o.DMSBS.Reg, volatile.LoadUint32(&o.DMSBS.Reg)&^(0xffff)|value)
}
func (o *DMAC0_Type) GetDMSBS_DMSBSL() uint32 {
	return volatile.LoadUint32(&o.DMSBS.Reg) & 0xffff
}
func (o *DMAC0_Type) SetDMSBS_DMSBSH(value uint32) {
	volatile.StoreUint32(&o.DMSBS.Reg, volatile.LoadUint32(&o.DMSBS.Reg)&^(0xffff0000)|value<<16)
}
func (o *DMAC0_Type) GetDMSBS_DMSBSH() uint32 {
	return (volatile.LoadUint32(&o.DMSBS.Reg) & 0xffff0000) >> 16
}

// DMAC0.DMDBS: DMA Destination Buffer Size Register
func (o *DMAC0_Type) SetDMDBS_DMDBSL(value uint32) {
	volatile.StoreUint32(&o.DMDBS.Reg, volatile.LoadUint32(&o.DMDBS.Reg)&^(0xffff)|value)
}
func (o *DMAC0_Type) GetDMDBS_DMDBSL() uint32 {
	return volatile.LoadUint32(&o.DMDBS.Reg) & 0xffff
}
func (o *DMAC0_Type) SetDMDBS_DMDBSH(value uint32) {
	volatile.StoreUint32(&o.DMDBS.Reg, volatile.LoadUint32(&o.DMDBS.Reg)&^(0xffff0000)|value<<16)
}
func (o *DMAC0_Type) GetDMDBS_DMDBSH() uint32 {
	return (volatile.LoadUint32(&o.DMDBS.Reg) & 0xffff0000) >> 16
}

// DMAC Module Activation
type DMA_Type struct {
	DMAST  volatile.Register8 // 0x0
	_      [63]byte
	DMECHR volatile.Register32 // 0x40
}

// DMA.DMAST: DMA Module Activation Register
func (o *DMA_Type) SetDMAST_DMST(value uint8) {
	volatile.StoreUint8(&o.DMAST.Reg, volatile.LoadUint8(&o.DMAST.Reg)&^(0x1)|value)
}
func (o *DMA_Type) GetDMAST_DMST() uint8 {
	return volatile.LoadUint8(&o.DMAST.Reg) & 0x1
}

// DMA.DMECHR: DMAC Error Channel Register
func (o *DMA_Type) SetDMECHR_DMECH(value uint32) {
	volatile.StoreUint32(&o.DMECHR.Reg, volatile.LoadUint32(&o.DMECHR.Reg)&^(0x7)|value)
}
func (o *DMA_Type) GetDMECHR_DMECH() uint32 {
	return volatile.LoadUint32(&o.DMECHR.Reg) & 0x7
}
func (o *DMA_Type) SetDMECHR_DMECHSAM(value uint32) {
	volatile.StoreUint32(&o.DMECHR.Reg, volatile.LoadUint32(&o.DMECHR.Reg)&^(0x100)|value<<8)
}
func (o *DMA_Type) GetDMECHR_DMECHSAM() uint32 {
	return (volatile.LoadUint32(&o.DMECHR.Reg) & 0x100) >> 8
}
func (o *DMA_Type) SetDMECHR_DMESTA(value uint32) {
	volatile.StoreUint32(&o.DMECHR.Reg, volatile.LoadUint32(&o.DMECHR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_Type) GetDMECHR_DMESTA() uint32 {
	return (volatile.LoadUint32(&o.DMECHR.Reg) & 0x10000) >> 16
}

// Data Transfer Controller
type DTC_Type struct {
	DTCCR      volatile.Register8 // 0x0
	_          [3]byte
	DTCVBR     volatile.Register32 // 0x4
	_          [4]byte
	DTCST      volatile.Register8 // 0xC
	_          byte
	DTCSTS     volatile.Register16 // 0xE
	DTCCR_SEC  volatile.Register8  // 0x10
	_          [3]byte
	DTCVBR_SEC volatile.Register32 // 0x14
	_          [8]byte
	DTEVR      volatile.Register32 // 0x20
}

// DTC.DTCCR: DTC Control Register
func (o *DTC_Type) SetDTCCR_RRS(value uint8) {
	volatile.StoreUint8(&o.DTCCR.Reg, volatile.LoadUint8(&o.DTCCR.Reg)&^(0x10)|value<<4)
}
func (o *DTC_Type) GetDTCCR_RRS() uint8 {
	return (volatile.LoadUint8(&o.DTCCR.Reg) & 0x10) >> 4
}

// DTC.DTCST: DTC Module Start Register
func (o *DTC_Type) SetDTCST(value uint8) {
	volatile.StoreUint8(&o.DTCST.Reg, volatile.LoadUint8(&o.DTCST.Reg)&^(0x1)|value)
}
func (o *DTC_Type) GetDTCST() uint8 {
	return volatile.LoadUint8(&o.DTCST.Reg) & 0x1
}

// DTC.DTCSTS: DTC Status Register
func (o *DTC_Type) SetDTCSTS_VECN(value uint16) {
	volatile.StoreUint16(&o.DTCSTS.Reg, volatile.LoadUint16(&o.DTCSTS.Reg)&^(0xff)|value)
}
func (o *DTC_Type) GetDTCSTS_VECN() uint16 {
	return volatile.LoadUint16(&o.DTCSTS.Reg) & 0xff
}
func (o *DTC_Type) SetDTCSTS_ACT(value uint16) {
	volatile.StoreUint16(&o.DTCSTS.Reg, volatile.LoadUint16(&o.DTCSTS.Reg)&^(0x8000)|value<<15)
}
func (o *DTC_Type) GetDTCSTS_ACT() uint16 {
	return (volatile.LoadUint16(&o.DTCSTS.Reg) & 0x8000) >> 15
}

// DTC.DTCCR_SEC: DTC Control Register for secure Region
func (o *DTC_Type) SetDTCCR_SEC_RRS(value uint8) {
	volatile.StoreUint8(&o.DTCCR_SEC.Reg, volatile.LoadUint8(&o.DTCCR_SEC.Reg)&^(0x10)|value<<4)
}
func (o *DTC_Type) GetDTCCR_SEC_RRS() uint8 {
	return (volatile.LoadUint8(&o.DTCCR_SEC.Reg) & 0x10) >> 4
}

// DTC.DTEVR: DTC Error Vector Register
func (o *DTC_Type) SetDTEVR_DTEV(value uint32) {
	volatile.StoreUint32(&o.DTEVR.Reg, volatile.LoadUint32(&o.DTEVR.Reg)&^(0xff)|value)
}
func (o *DTC_Type) GetDTEVR_DTEV() uint32 {
	return volatile.LoadUint32(&o.DTEVR.Reg) & 0xff
}
func (o *DTC_Type) SetDTEVR_DTEVSAM(value uint32) {
	volatile.StoreUint32(&o.DTEVR.Reg, volatile.LoadUint32(&o.DTEVR.Reg)&^(0x100)|value<<8)
}
func (o *DTC_Type) GetDTEVR_DTEVSAM() uint32 {
	return (volatile.LoadUint32(&o.DTEVR.Reg) & 0x100) >> 8
}
func (o *DTC_Type) SetDTEVR_DTESTA(value uint32) {
	volatile.StoreUint32(&o.DTEVR.Reg, volatile.LoadUint32(&o.DTEVR.Reg)&^(0x10000)|value<<16)
}
func (o *DTC_Type) GetDTEVR_DTESTA() uint32 {
	return (volatile.LoadUint32(&o.DTEVR.Reg) & 0x10000) >> 16
}

// Interrupt Controller
type ICU_Type struct {
	IRQCR0  volatile.Register8 // 0x0
	IRQCR1  volatile.Register8 // 0x1
	IRQCR2  volatile.Register8 // 0x2
	IRQCR3  volatile.Register8 // 0x3
	IRQCR4  volatile.Register8 // 0x4
	IRQCR5  volatile.Register8 // 0x5
	IRQCR6  volatile.Register8 // 0x6
	IRQCR7  volatile.Register8 // 0x7
	IRQCR8  volatile.Register8 // 0x8
	IRQCR9  volatile.Register8 // 0x9
	IRQCR10 volatile.Register8 // 0xA
	IRQCR11 volatile.Register8 // 0xB
	IRQCR12 volatile.Register8 // 0xC
	IRQCR13 volatile.Register8 // 0xD
	IRQCR14 volatile.Register8 // 0xE
	_       [241]byte
	NMICR   volatile.Register8 // 0x100
	_       [31]byte
	NMIER   volatile.Register16 // 0x120
	_       [14]byte
	NMICLR  volatile.Register16 // 0x130
	_       [14]byte
	NMISR   volatile.Register16 // 0x140
	_       [94]byte
	WUPEN0  volatile.Register32 // 0x1A0
	WUPEN1  volatile.Register32 // 0x1A4
	_       [88]byte
	SELSR0  volatile.Register16 // 0x200
	_       [126]byte
	DELSR0  volatile.Register32 // 0x280
	DELSR1  volatile.Register32 // 0x284
	DELSR2  volatile.Register32 // 0x288
	DELSR3  volatile.Register32 // 0x28C
	DELSR4  volatile.Register32 // 0x290
	DELSR5  volatile.Register32 // 0x294
	DELSR6  volatile.Register32 // 0x298
	DELSR7  volatile.Register32 // 0x29C
	_       [96]byte
	IELSR0  volatile.Register32 // 0x300
	IELSR1  volatile.Register32 // 0x304
	IELSR2  volatile.Register32 // 0x308
	IELSR3  volatile.Register32 // 0x30C
	IELSR4  volatile.Register32 // 0x310
	IELSR5  volatile.Register32 // 0x314
	IELSR6  volatile.Register32 // 0x318
	IELSR7  volatile.Register32 // 0x31C
	IELSR8  volatile.Register32 // 0x320
	IELSR9  volatile.Register32 // 0x324
	IELSR10 volatile.Register32 // 0x328
	IELSR11 volatile.Register32 // 0x32C
	IELSR12 volatile.Register32 // 0x330
	IELSR13 volatile.Register32 // 0x334
	IELSR14 volatile.Register32 // 0x338
	IELSR15 volatile.Register32 // 0x33C
	IELSR16 volatile.Register32 // 0x340
	IELSR17 volatile.Register32 // 0x344
	IELSR18 volatile.Register32 // 0x348
	IELSR19 volatile.Register32 // 0x34C
	IELSR20 volatile.Register32 // 0x350
	IELSR21 volatile.Register32 // 0x354
	IELSR22 volatile.Register32 // 0x358
	IELSR23 volatile.Register32 // 0x35C
	IELSR24 volatile.Register32 // 0x360
	IELSR25 volatile.Register32 // 0x364
	IELSR26 volatile.Register32 // 0x368
	IELSR27 volatile.Register32 // 0x36C
	IELSR28 volatile.Register32 // 0x370
	IELSR29 volatile.Register32 // 0x374
	IELSR30 volatile.Register32 // 0x378
	IELSR31 volatile.Register32 // 0x37C
	IELSR32 volatile.Register32 // 0x380
	IELSR33 volatile.Register32 // 0x384
	IELSR34 volatile.Register32 // 0x388
	IELSR35 volatile.Register32 // 0x38C
	IELSR36 volatile.Register32 // 0x390
	IELSR37 volatile.Register32 // 0x394
	IELSR38 volatile.Register32 // 0x398
	IELSR39 volatile.Register32 // 0x39C
	IELSR40 volatile.Register32 // 0x3A0
	IELSR41 volatile.Register32 // 0x3A4
	IELSR42 volatile.Register32 // 0x3A8
	IELSR43 volatile.Register32 // 0x3AC
	IELSR44 volatile.Register32 // 0x3B0
	IELSR45 volatile.Register32 // 0x3B4
	IELSR46 volatile.Register32 // 0x3B8
	IELSR47 volatile.Register32 // 0x3BC
	IELSR48 volatile.Register32 // 0x3C0
	IELSR49 volatile.Register32 // 0x3C4
	IELSR50 volatile.Register32 // 0x3C8
	IELSR51 volatile.Register32 // 0x3CC
	IELSR52 volatile.Register32 // 0x3D0
	IELSR53 volatile.Register32 // 0x3D4
	IELSR54 volatile.Register32 // 0x3D8
	IELSR55 volatile.Register32 // 0x3DC
	IELSR56 volatile.Register32 // 0x3E0
	IELSR57 volatile.Register32 // 0x3E4
	IELSR58 volatile.Register32 // 0x3E8
	IELSR59 volatile.Register32 // 0x3EC
	IELSR60 volatile.Register32 // 0x3F0
	IELSR61 volatile.Register32 // 0x3F4
	IELSR62 volatile.Register32 // 0x3F8
	IELSR63 volatile.Register32 // 0x3FC
	IELSR64 volatile.Register32 // 0x400
	IELSR65 volatile.Register32 // 0x404
	IELSR66 volatile.Register32 // 0x408
	IELSR67 volatile.Register32 // 0x40C
	IELSR68 volatile.Register32 // 0x410
	IELSR69 volatile.Register32 // 0x414
	IELSR70 volatile.Register32 // 0x418
	IELSR71 volatile.Register32 // 0x41C
	IELSR72 volatile.Register32 // 0x420
	IELSR73 volatile.Register32 // 0x424
	IELSR74 volatile.Register32 // 0x428
	IELSR75 volatile.Register32 // 0x42C
	IELSR76 volatile.Register32 // 0x430
	IELSR77 volatile.Register32 // 0x434
	IELSR78 volatile.Register32 // 0x438
	IELSR79 volatile.Register32 // 0x43C
	IELSR80 volatile.Register32 // 0x440
	IELSR81 volatile.Register32 // 0x444
	IELSR82 volatile.Register32 // 0x448
	IELSR83 volatile.Register32 // 0x44C
	IELSR84 volatile.Register32 // 0x450
	IELSR85 volatile.Register32 // 0x454
	IELSR86 volatile.Register32 // 0x458
	IELSR87 volatile.Register32 // 0x45C
	IELSR88 volatile.Register32 // 0x460
	IELSR89 volatile.Register32 // 0x464
	IELSR90 volatile.Register32 // 0x468
	IELSR91 volatile.Register32 // 0x46C
	IELSR92 volatile.Register32 // 0x470
	IELSR93 volatile.Register32 // 0x474
	IELSR94 volatile.Register32 // 0x478
	IELSR95 volatile.Register32 // 0x47C
}

// ICU.IRQCR0: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR0_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR0.Reg, volatile.LoadUint8(&o.IRQCR0.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR0_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR0.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR0_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR0.Reg, volatile.LoadUint8(&o.IRQCR0.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR0_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR0.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR0_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR0.Reg, volatile.LoadUint8(&o.IRQCR0.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR0_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR0.Reg) & 0x80) >> 7
}

// ICU.IRQCR1: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR1_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR1.Reg, volatile.LoadUint8(&o.IRQCR1.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR1_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR1.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR1_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR1.Reg, volatile.LoadUint8(&o.IRQCR1.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR1_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR1.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR1_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR1.Reg, volatile.LoadUint8(&o.IRQCR1.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR1_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR1.Reg) & 0x80) >> 7
}

// ICU.IRQCR2: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR2_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR2.Reg, volatile.LoadUint8(&o.IRQCR2.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR2_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR2.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR2_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR2.Reg, volatile.LoadUint8(&o.IRQCR2.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR2_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR2.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR2_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR2.Reg, volatile.LoadUint8(&o.IRQCR2.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR2_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR2.Reg) & 0x80) >> 7
}

// ICU.IRQCR3: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR3_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR3.Reg, volatile.LoadUint8(&o.IRQCR3.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR3_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR3.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR3_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR3.Reg, volatile.LoadUint8(&o.IRQCR3.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR3_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR3.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR3_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR3.Reg, volatile.LoadUint8(&o.IRQCR3.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR3_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR3.Reg) & 0x80) >> 7
}

// ICU.IRQCR4: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR4_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR4.Reg, volatile.LoadUint8(&o.IRQCR4.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR4_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR4.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR4_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR4.Reg, volatile.LoadUint8(&o.IRQCR4.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR4_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR4.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR4_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR4.Reg, volatile.LoadUint8(&o.IRQCR4.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR4_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR4.Reg) & 0x80) >> 7
}

// ICU.IRQCR5: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR5_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR5.Reg, volatile.LoadUint8(&o.IRQCR5.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR5_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR5.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR5_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR5.Reg, volatile.LoadUint8(&o.IRQCR5.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR5_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR5.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR5_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR5.Reg, volatile.LoadUint8(&o.IRQCR5.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR5_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR5.Reg) & 0x80) >> 7
}

// ICU.IRQCR6: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR6_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR6.Reg, volatile.LoadUint8(&o.IRQCR6.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR6_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR6.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR6_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR6.Reg, volatile.LoadUint8(&o.IRQCR6.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR6_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR6.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR6_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR6.Reg, volatile.LoadUint8(&o.IRQCR6.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR6_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR6.Reg) & 0x80) >> 7
}

// ICU.IRQCR7: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR7_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR7.Reg, volatile.LoadUint8(&o.IRQCR7.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR7_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR7.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR7_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR7.Reg, volatile.LoadUint8(&o.IRQCR7.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR7_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR7.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR7_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR7.Reg, volatile.LoadUint8(&o.IRQCR7.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR7_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR7.Reg) & 0x80) >> 7
}

// ICU.IRQCR8: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR8_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR8.Reg, volatile.LoadUint8(&o.IRQCR8.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR8_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR8.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR8_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR8.Reg, volatile.LoadUint8(&o.IRQCR8.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR8_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR8.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR8_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR8.Reg, volatile.LoadUint8(&o.IRQCR8.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR8_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR8.Reg) & 0x80) >> 7
}

// ICU.IRQCR9: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR9_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR9.Reg, volatile.LoadUint8(&o.IRQCR9.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR9_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR9.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR9_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR9.Reg, volatile.LoadUint8(&o.IRQCR9.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR9_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR9.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR9_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR9.Reg, volatile.LoadUint8(&o.IRQCR9.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR9_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR9.Reg) & 0x80) >> 7
}

// ICU.IRQCR10: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR10_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR10.Reg, volatile.LoadUint8(&o.IRQCR10.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR10_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR10.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR10_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR10.Reg, volatile.LoadUint8(&o.IRQCR10.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR10_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR10.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR10_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR10.Reg, volatile.LoadUint8(&o.IRQCR10.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR10_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR10.Reg) & 0x80) >> 7
}

// ICU.IRQCR11: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR11_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR11.Reg, volatile.LoadUint8(&o.IRQCR11.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR11_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR11.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR11_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR11.Reg, volatile.LoadUint8(&o.IRQCR11.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR11_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR11.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR11_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR11.Reg, volatile.LoadUint8(&o.IRQCR11.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR11_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR11.Reg) & 0x80) >> 7
}

// ICU.IRQCR12: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR12_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR12.Reg, volatile.LoadUint8(&o.IRQCR12.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR12_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR12.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR12_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR12.Reg, volatile.LoadUint8(&o.IRQCR12.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR12_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR12.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR12_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR12.Reg, volatile.LoadUint8(&o.IRQCR12.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR12_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR12.Reg) & 0x80) >> 7
}

// ICU.IRQCR13: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR13_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR13.Reg, volatile.LoadUint8(&o.IRQCR13.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR13_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR13.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR13_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR13.Reg, volatile.LoadUint8(&o.IRQCR13.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR13_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR13.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR13_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR13.Reg, volatile.LoadUint8(&o.IRQCR13.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR13_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR13.Reg) & 0x80) >> 7
}

// ICU.IRQCR14: IRQ Control Register %s
func (o *ICU_Type) SetIRQCR14_IRQMD(value uint8) {
	volatile.StoreUint8(&o.IRQCR14.Reg, volatile.LoadUint8(&o.IRQCR14.Reg)&^(0x3)|value)
}
func (o *ICU_Type) GetIRQCR14_IRQMD() uint8 {
	return volatile.LoadUint8(&o.IRQCR14.Reg) & 0x3
}
func (o *ICU_Type) SetIRQCR14_FCLKSEL(value uint8) {
	volatile.StoreUint8(&o.IRQCR14.Reg, volatile.LoadUint8(&o.IRQCR14.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetIRQCR14_FCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.IRQCR14.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetIRQCR14_FLTEN(value uint8) {
	volatile.StoreUint8(&o.IRQCR14.Reg, volatile.LoadUint8(&o.IRQCR14.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetIRQCR14_FLTEN() uint8 {
	return (volatile.LoadUint8(&o.IRQCR14.Reg) & 0x80) >> 7
}

// ICU.NMICR: NMI Pin Interrupt Control Register
func (o *ICU_Type) SetNMICR_NMIMD(value uint8) {
	volatile.StoreUint8(&o.NMICR.Reg, volatile.LoadUint8(&o.NMICR.Reg)&^(0x1)|value)
}
func (o *ICU_Type) GetNMICR_NMIMD() uint8 {
	return volatile.LoadUint8(&o.NMICR.Reg) & 0x1
}
func (o *ICU_Type) SetNMICR_NFCLKSEL(value uint8) {
	volatile.StoreUint8(&o.NMICR.Reg, volatile.LoadUint8(&o.NMICR.Reg)&^(0x30)|value<<4)
}
func (o *ICU_Type) GetNMICR_NFCLKSEL() uint8 {
	return (volatile.LoadUint8(&o.NMICR.Reg) & 0x30) >> 4
}
func (o *ICU_Type) SetNMICR_NFLTEN(value uint8) {
	volatile.StoreUint8(&o.NMICR.Reg, volatile.LoadUint8(&o.NMICR.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetNMICR_NFLTEN() uint8 {
	return (volatile.LoadUint8(&o.NMICR.Reg) & 0x80) >> 7
}

// ICU.NMIER: Non-Maskable Interrupt Enable Register
func (o *ICU_Type) SetNMIER_IWDTEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x1)|value)
}
func (o *ICU_Type) GetNMIER_IWDTEN() uint16 {
	return volatile.LoadUint16(&o.NMIER.Reg) & 0x1
}
func (o *ICU_Type) SetNMIER_WDTEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x2)|value<<1)
}
func (o *ICU_Type) GetNMIER_WDTEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x2) >> 1
}
func (o *ICU_Type) SetNMIER_LVD1EN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x4)|value<<2)
}
func (o *ICU_Type) GetNMIER_LVD1EN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x4) >> 2
}
func (o *ICU_Type) SetNMIER_LVD2EN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x8)|value<<3)
}
func (o *ICU_Type) GetNMIER_LVD2EN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x8) >> 3
}
func (o *ICU_Type) SetNMIER_OSTEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x40)|value<<6)
}
func (o *ICU_Type) GetNMIER_OSTEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x40) >> 6
}
func (o *ICU_Type) SetNMIER_NMIEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetNMIER_NMIEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x80) >> 7
}
func (o *ICU_Type) SetNMIER_RPEEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x100)|value<<8)
}
func (o *ICU_Type) GetNMIER_RPEEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x100) >> 8
}
func (o *ICU_Type) SetNMIER_RECCEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x200)|value<<9)
}
func (o *ICU_Type) GetNMIER_RECCEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x200) >> 9
}
func (o *ICU_Type) SetNMIER_BUSMEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x800)|value<<11)
}
func (o *ICU_Type) GetNMIER_BUSMEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x800) >> 11
}
func (o *ICU_Type) SetNMIER_TZFEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x2000)|value<<13)
}
func (o *ICU_Type) GetNMIER_TZFEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x2000) >> 13
}
func (o *ICU_Type) SetNMIER_CPEEN(value uint16) {
	volatile.StoreUint16(&o.NMIER.Reg, volatile.LoadUint16(&o.NMIER.Reg)&^(0x8000)|value<<15)
}
func (o *ICU_Type) GetNMIER_CPEEN() uint16 {
	return (volatile.LoadUint16(&o.NMIER.Reg) & 0x8000) >> 15
}

// ICU.NMICLR: Non-Maskable Interrupt Status Clear Register
func (o *ICU_Type) SetNMICLR_IWDTCLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x1)|value)
}
func (o *ICU_Type) GetNMICLR_IWDTCLR() uint16 {
	return volatile.LoadUint16(&o.NMICLR.Reg) & 0x1
}
func (o *ICU_Type) SetNMICLR_WDTCLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x2)|value<<1)
}
func (o *ICU_Type) GetNMICLR_WDTCLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x2) >> 1
}
func (o *ICU_Type) SetNMICLR_LVD1CLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x4)|value<<2)
}
func (o *ICU_Type) GetNMICLR_LVD1CLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x4) >> 2
}
func (o *ICU_Type) SetNMICLR_LVD2CLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x8)|value<<3)
}
func (o *ICU_Type) GetNMICLR_LVD2CLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x8) >> 3
}
func (o *ICU_Type) SetNMICLR_OSTCLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x40)|value<<6)
}
func (o *ICU_Type) GetNMICLR_OSTCLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x40) >> 6
}
func (o *ICU_Type) SetNMICLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetNMICLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x80) >> 7
}
func (o *ICU_Type) SetNMICLR_RPECLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x100)|value<<8)
}
func (o *ICU_Type) GetNMICLR_RPECLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x100) >> 8
}
func (o *ICU_Type) SetNMICLR_RECCCLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x200)|value<<9)
}
func (o *ICU_Type) GetNMICLR_RECCCLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x200) >> 9
}
func (o *ICU_Type) SetNMICLR_BUSMCLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x800)|value<<11)
}
func (o *ICU_Type) GetNMICLR_BUSMCLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x800) >> 11
}
func (o *ICU_Type) SetNMICLR_TZFCLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x2000)|value<<13)
}
func (o *ICU_Type) GetNMICLR_TZFCLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x2000) >> 13
}
func (o *ICU_Type) SetNMICLR_CPECLR(value uint16) {
	volatile.StoreUint16(&o.NMICLR.Reg, volatile.LoadUint16(&o.NMICLR.Reg)&^(0x8000)|value<<15)
}
func (o *ICU_Type) GetNMICLR_CPECLR() uint16 {
	return (volatile.LoadUint16(&o.NMICLR.Reg) & 0x8000) >> 15
}

// ICU.NMISR: Non-Maskable Interrupt Status Register
func (o *ICU_Type) SetNMISR_IWDTST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x1)|value)
}
func (o *ICU_Type) GetNMISR_IWDTST() uint16 {
	return volatile.LoadUint16(&o.NMISR.Reg) & 0x1
}
func (o *ICU_Type) SetNMISR_WDTST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x2)|value<<1)
}
func (o *ICU_Type) GetNMISR_WDTST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x2) >> 1
}
func (o *ICU_Type) SetNMISR_LVD1ST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x4)|value<<2)
}
func (o *ICU_Type) GetNMISR_LVD1ST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x4) >> 2
}
func (o *ICU_Type) SetNMISR_LVD2ST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x8)|value<<3)
}
func (o *ICU_Type) GetNMISR_LVD2ST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x8) >> 3
}
func (o *ICU_Type) SetNMISR_OSTST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x40)|value<<6)
}
func (o *ICU_Type) GetNMISR_OSTST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x40) >> 6
}
func (o *ICU_Type) SetNMISR_NMIST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x80)|value<<7)
}
func (o *ICU_Type) GetNMISR_NMIST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x80) >> 7
}
func (o *ICU_Type) SetNMISR_RPEST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x100)|value<<8)
}
func (o *ICU_Type) GetNMISR_RPEST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x100) >> 8
}
func (o *ICU_Type) SetNMISR_RECCST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x200)|value<<9)
}
func (o *ICU_Type) GetNMISR_RECCST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x200) >> 9
}
func (o *ICU_Type) SetNMISR_BUSMST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x800)|value<<11)
}
func (o *ICU_Type) GetNMISR_BUSMST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x800) >> 11
}
func (o *ICU_Type) SetNMISR_TZFST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x2000)|value<<13)
}
func (o *ICU_Type) GetNMISR_TZFST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x2000) >> 13
}
func (o *ICU_Type) SetNMISR_CPEST(value uint16) {
	volatile.StoreUint16(&o.NMISR.Reg, volatile.LoadUint16(&o.NMISR.Reg)&^(0x8000)|value<<15)
}
func (o *ICU_Type) GetNMISR_CPEST() uint16 {
	return (volatile.LoadUint16(&o.NMISR.Reg) & 0x8000) >> 15
}

// ICU.WUPEN0: Wake Up Interrupt Enable Register 0
func (o *ICU_Type) SetWUPEN0_IRQWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x7fff)|value)
}
func (o *ICU_Type) GetWUPEN0_IRQWUPEN() uint32 {
	return volatile.LoadUint32(&o.WUPEN0.Reg) & 0x7fff
}
func (o *ICU_Type) SetWUPEN0_IWDTWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetWUPEN0_IWDTWUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x10000) >> 16
}
func (o *ICU_Type) SetWUPEN0_LVD1WUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x40000)|value<<18)
}
func (o *ICU_Type) GetWUPEN0_LVD1WUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x40000) >> 18
}
func (o *ICU_Type) SetWUPEN0_LVD2WUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x80000)|value<<19)
}
func (o *ICU_Type) GetWUPEN0_LVD2WUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x80000) >> 19
}
func (o *ICU_Type) SetWUPEN0_RTCALMWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x1000000)|value<<24)
}
func (o *ICU_Type) GetWUPEN0_RTCALMWUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x1000000) >> 24
}
func (o *ICU_Type) SetWUPEN0_RTCPRDWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x2000000)|value<<25)
}
func (o *ICU_Type) GetWUPEN0_RTCPRDWUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x2000000) >> 25
}
func (o *ICU_Type) SetWUPEN0_USBFS0WUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x8000000)|value<<27)
}
func (o *ICU_Type) GetWUPEN0_USBFS0WUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x8000000) >> 27
}
func (o *ICU_Type) SetWUPEN0_AGT1UDWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x10000000)|value<<28)
}
func (o *ICU_Type) GetWUPEN0_AGT1UDWUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x10000000) >> 28
}
func (o *ICU_Type) SetWUPEN0_AGT1CAWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x20000000)|value<<29)
}
func (o *ICU_Type) GetWUPEN0_AGT1CAWUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x20000000) >> 29
}
func (o *ICU_Type) SetWUPEN0_AGT1CBWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN0.Reg, volatile.LoadUint32(&o.WUPEN0.Reg)&^(0x40000000)|value<<30)
}
func (o *ICU_Type) GetWUPEN0_AGT1CBWUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN0.Reg) & 0x40000000) >> 30
}

// ICU.WUPEN1: Wake Up Interrupt Enable Register 1
func (o *ICU_Type) SetWUPEN1_I3CWUPEN(value uint32) {
	volatile.StoreUint32(&o.WUPEN1.Reg, volatile.LoadUint32(&o.WUPEN1.Reg)&^(0x800)|value<<11)
}
func (o *ICU_Type) GetWUPEN1_I3CWUPEN() uint32 {
	return (volatile.LoadUint32(&o.WUPEN1.Reg) & 0x800) >> 11
}

// ICU.DELSR0: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR0_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR0.Reg, volatile.LoadUint32(&o.DELSR0.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR0_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR0.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR0_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR0.Reg, volatile.LoadUint32(&o.DELSR0.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR0_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR0.Reg) & 0x10000) >> 16
}

// ICU.DELSR1: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR1_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR1.Reg, volatile.LoadUint32(&o.DELSR1.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR1_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR1.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR1_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR1.Reg, volatile.LoadUint32(&o.DELSR1.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR1_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR1.Reg) & 0x10000) >> 16
}

// ICU.DELSR2: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR2_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR2.Reg, volatile.LoadUint32(&o.DELSR2.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR2_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR2.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR2_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR2.Reg, volatile.LoadUint32(&o.DELSR2.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR2_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR2.Reg) & 0x10000) >> 16
}

// ICU.DELSR3: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR3_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR3.Reg, volatile.LoadUint32(&o.DELSR3.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR3_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR3.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR3_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR3.Reg, volatile.LoadUint32(&o.DELSR3.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR3_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR3.Reg) & 0x10000) >> 16
}

// ICU.DELSR4: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR4_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR4.Reg, volatile.LoadUint32(&o.DELSR4.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR4_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR4.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR4_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR4.Reg, volatile.LoadUint32(&o.DELSR4.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR4_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR4.Reg) & 0x10000) >> 16
}

// ICU.DELSR5: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR5_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR5.Reg, volatile.LoadUint32(&o.DELSR5.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR5_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR5.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR5_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR5.Reg, volatile.LoadUint32(&o.DELSR5.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR5_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR5.Reg) & 0x10000) >> 16
}

// ICU.DELSR6: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR6_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR6.Reg, volatile.LoadUint32(&o.DELSR6.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR6_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR6.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR6_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR6.Reg, volatile.LoadUint32(&o.DELSR6.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR6_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR6.Reg) & 0x10000) >> 16
}

// ICU.DELSR7: DMAC Event Link Setting Register %s
func (o *ICU_Type) SetDELSR7_DELS(value uint32) {
	volatile.StoreUint32(&o.DELSR7.Reg, volatile.LoadUint32(&o.DELSR7.Reg)&^(0x1ff)|value)
}
func (o *ICU_Type) GetDELSR7_DELS() uint32 {
	return volatile.LoadUint32(&o.DELSR7.Reg) & 0x1ff
}
func (o *ICU_Type) SetDELSR7_IR(value uint32) {
	volatile.StoreUint32(&o.DELSR7.Reg, volatile.LoadUint32(&o.DELSR7.Reg)&^(0x10000)|value<<16)
}
func (o *ICU_Type) GetDELSR7_IR() uint32 {
	return (volatile.LoadUint32(&o.DELSR7.Reg) & 0x10000) >> 16
}

// CACHE
type CACHE_Type struct {
	CCACTL volatile.Register32 // 0x0
	CCAFCT volatile.Register32 // 0x4
	CCALCF volatile.Register32 // 0x8
	_      [52]byte
	SCACTL volatile.Register32 // 0x40
	SCAFCT volatile.Register32 // 0x44
	SCALCF volatile.Register32 // 0x48
	_      [436]byte
	CAPOAD volatile.Register32 // 0x200
	CAPRCR volatile.Register32 // 0x204
}

// CACHE.CCACTL: C-Cache Control Register
func (o *CACHE_Type) SetCCACTL_ENC(value uint32) {
	volatile.StoreUint32(&o.CCACTL.Reg, volatile.LoadUint32(&o.CCACTL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetCCACTL_ENC() uint32 {
	return volatile.LoadUint32(&o.CCACTL.Reg) & 0x1
}

// CACHE.CCAFCT: C-Cache Flush Control Register
func (o *CACHE_Type) SetCCAFCT_FC(value uint32) {
	volatile.StoreUint32(&o.CCAFCT.Reg, volatile.LoadUint32(&o.CCAFCT.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetCCAFCT_FC() uint32 {
	return volatile.LoadUint32(&o.CCAFCT.Reg) & 0x1
}

// CACHE.CCALCF: C-Cache Line Configuration Register
func (o *CACHE_Type) SetCCALCF_CC(value uint32) {
	volatile.StoreUint32(&o.CCALCF.Reg, volatile.LoadUint32(&o.CCALCF.Reg)&^(0x3)|value)
}
func (o *CACHE_Type) GetCCALCF_CC() uint32 {
	return volatile.LoadUint32(&o.CCALCF.Reg) & 0x3
}

// CACHE.SCACTL: S-Cache Control Register
func (o *CACHE_Type) SetSCACTL_ENS(value uint32) {
	volatile.StoreUint32(&o.SCACTL.Reg, volatile.LoadUint32(&o.SCACTL.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetSCACTL_ENS() uint32 {
	return volatile.LoadUint32(&o.SCACTL.Reg) & 0x1
}

// CACHE.SCAFCT: S-Cache Flush Control Register
func (o *CACHE_Type) SetSCAFCT_FS(value uint32) {
	volatile.StoreUint32(&o.SCAFCT.Reg, volatile.LoadUint32(&o.SCAFCT.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetSCAFCT_FS() uint32 {
	return volatile.LoadUint32(&o.SCAFCT.Reg) & 0x1
}

// CACHE.SCALCF: S-Cache Line Configuration Register
func (o *CACHE_Type) SetSCALCF_CS(value uint32) {
	volatile.StoreUint32(&o.SCALCF.Reg, volatile.LoadUint32(&o.SCALCF.Reg)&^(0x3)|value)
}
func (o *CACHE_Type) GetSCALCF_CS() uint32 {
	return volatile.LoadUint32(&o.SCALCF.Reg) & 0x3
}

// CACHE.CAPOAD: Cache Parity Error Operation After Detection Register
func (o *CACHE_Type) SetCAPOAD_OAD(value uint32) {
	volatile.StoreUint32(&o.CAPOAD.Reg, volatile.LoadUint32(&o.CAPOAD.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetCAPOAD_OAD() uint32 {
	return volatile.LoadUint32(&o.CAPOAD.Reg) & 0x1
}

// CACHE.CAPRCR: Cache Protection Register
func (o *CACHE_Type) SetCAPRCR_PRCR(value uint32) {
	volatile.StoreUint32(&o.CAPRCR.Reg, volatile.LoadUint32(&o.CAPRCR.Reg)&^(0x1)|value)
}
func (o *CACHE_Type) GetCAPRCR_PRCR() uint32 {
	return volatile.LoadUint32(&o.CAPRCR.Reg) & 0x1
}
func (o *CACHE_Type) SetCAPRCR_KW(value uint32) {
	volatile.StoreUint32(&o.CAPRCR.Reg, volatile.LoadUint32(&o.CAPRCR.Reg)&^(0xfe)|value<<1)
}
func (o *CACHE_Type) GetCAPRCR_KW() uint32 {
	return (volatile.LoadUint32(&o.CAPRCR.Reg) & 0xfe) >> 1
}

// CPU System Security Control Unit
type CPSCU_Type struct {
	CSAR      volatile.Register32 // 0x0
	_         [12]byte
	SRAMSAR   volatile.Register32 // 0x10
	STBRAMSAR volatile.Register32 // 0x14
	_         [24]byte
	DTCSAR    volatile.Register32 // 0x30
	DMACSAR   volatile.Register32 // 0x34
	_         [8]byte
	ICUSARA   volatile.Register32 // 0x40
	ICUSARB   volatile.Register32 // 0x44
	ICUSARC   volatile.Register32 // 0x48
	ICUSARD   volatile.Register32 // 0x4C
	_         [4]byte
	ICUSARF   volatile.Register32 // 0x54
	_         [24]byte
	ICUSARG   volatile.Register32 // 0x70
	ICUSARH   volatile.Register32 // 0x74
	ICUSARI   volatile.Register32 // 0x78
	_         [132]byte
	BUSSARA   volatile.Register32 // 0x100
	BUSSARB   volatile.Register32 // 0x104
	_         [40]byte
	MMPUSARA  volatile.Register32 // 0x130
	MMPUSARB  volatile.Register32 // 0x134
	_         [72]byte
	TZFSAR    volatile.Register32 // 0x180
	_         [44]byte
	CPUDSAR   volatile.Register32 // 0x1B0
}

// CPSCU.CSAR: Cache Security Attribution Register
func (o *CPSCU_Type) SetCSAR_CACHESA(value uint32) {
	volatile.StoreUint32(&o.CSAR.Reg, volatile.LoadUint32(&o.CSAR.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetCSAR_CACHESA() uint32 {
	return volatile.LoadUint32(&o.CSAR.Reg) & 0x1
}
func (o *CPSCU_Type) SetCSAR_CACHELSA(value uint32) {
	volatile.StoreUint32(&o.CSAR.Reg, volatile.LoadUint32(&o.CSAR.Reg)&^(0x2)|value<<1)
}
func (o *CPSCU_Type) GetCSAR_CACHELSA() uint32 {
	return (volatile.LoadUint32(&o.CSAR.Reg) & 0x2) >> 1
}
func (o *CPSCU_Type) SetCSAR_CACHEESA(value uint32) {
	volatile.StoreUint32(&o.CSAR.Reg, volatile.LoadUint32(&o.CSAR.Reg)&^(0x4)|value<<2)
}
func (o *CPSCU_Type) GetCSAR_CACHEESA() uint32 {
	return (volatile.LoadUint32(&o.CSAR.Reg) & 0x4) >> 2
}

// CPSCU.SRAMSAR: SRAM Security Attribution Register
func (o *CPSCU_Type) SetSRAMSAR_SRAMSA0(value uint32) {
	volatile.StoreUint32(&o.SRAMSAR.Reg, volatile.LoadUint32(&o.SRAMSAR.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetSRAMSAR_SRAMSA0() uint32 {
	return volatile.LoadUint32(&o.SRAMSAR.Reg) & 0x1
}
func (o *CPSCU_Type) SetSRAMSAR_SRAMSA1(value uint32) {
	volatile.StoreUint32(&o.SRAMSAR.Reg, volatile.LoadUint32(&o.SRAMSAR.Reg)&^(0x2)|value<<1)
}
func (o *CPSCU_Type) GetSRAMSAR_SRAMSA1() uint32 {
	return (volatile.LoadUint32(&o.SRAMSAR.Reg) & 0x2) >> 1
}
func (o *CPSCU_Type) SetSRAMSAR_SRAMSA2(value uint32) {
	volatile.StoreUint32(&o.SRAMSAR.Reg, volatile.LoadUint32(&o.SRAMSAR.Reg)&^(0x4)|value<<2)
}
func (o *CPSCU_Type) GetSRAMSAR_SRAMSA2() uint32 {
	return (volatile.LoadUint32(&o.SRAMSAR.Reg) & 0x4) >> 2
}

// CPSCU.STBRAMSAR: Standby RAM memory Security Attribution Register
func (o *CPSCU_Type) SetSTBRAMSAR_NSBSTBR(value uint32) {
	volatile.StoreUint32(&o.STBRAMSAR.Reg, volatile.LoadUint32(&o.STBRAMSAR.Reg)&^(0xf)|value)
}
func (o *CPSCU_Type) GetSTBRAMSAR_NSBSTBR() uint32 {
	return volatile.LoadUint32(&o.STBRAMSAR.Reg) & 0xf
}

// CPSCU.DTCSAR: DTC Controller Security Attribution Register
func (o *CPSCU_Type) SetDTCSAR_DTCSTSA(value uint32) {
	volatile.StoreUint32(&o.DTCSAR.Reg, volatile.LoadUint32(&o.DTCSAR.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetDTCSAR_DTCSTSA() uint32 {
	return volatile.LoadUint32(&o.DTCSAR.Reg) & 0x1
}

// CPSCU.DMACSAR: DMAC Controller Security Attribution Register
func (o *CPSCU_Type) SetDMACSAR_DMASTSA(value uint32) {
	volatile.StoreUint32(&o.DMACSAR.Reg, volatile.LoadUint32(&o.DMACSAR.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetDMACSAR_DMASTSA() uint32 {
	return volatile.LoadUint32(&o.DMACSAR.Reg) & 0x1
}

// CPSCU.ICUSARA: Interrupt Controller Unit Security Attribution Register A
func (o *CPSCU_Type) SetICUSARA_SAIRQCR00(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR00() uint32 {
	return volatile.LoadUint32(&o.ICUSARA.Reg) & 0x1
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR01(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x2)|value<<1)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR01() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x2) >> 1
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR02(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x4)|value<<2)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR02() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x4) >> 2
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR03(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x8)|value<<3)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR03() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x8) >> 3
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR04(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x10)|value<<4)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR04() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x10) >> 4
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR05(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x20)|value<<5)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR05() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x20) >> 5
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR06(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x40)|value<<6)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR06() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x40) >> 6
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR07(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x80)|value<<7)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR07() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x80) >> 7
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR08(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x100)|value<<8)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR08() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x100) >> 8
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR09(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x200)|value<<9)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR09() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x200) >> 9
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR10(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x400)|value<<10)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR10() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x400) >> 10
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR11(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x800)|value<<11)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR11() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x800) >> 11
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR12(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x1000)|value<<12)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR12() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x1000) >> 12
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR13(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x2000)|value<<13)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR13() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x2000) >> 13
}
func (o *CPSCU_Type) SetICUSARA_SAIRQCR14(value uint32) {
	volatile.StoreUint32(&o.ICUSARA.Reg, volatile.LoadUint32(&o.ICUSARA.Reg)&^(0x4000)|value<<14)
}
func (o *CPSCU_Type) GetICUSARA_SAIRQCR14() uint32 {
	return (volatile.LoadUint32(&o.ICUSARA.Reg) & 0x4000) >> 14
}

// CPSCU.ICUSARB: Interrupt Controller Unit Security Attribution Register B
func (o *CPSCU_Type) SetICUSARB_SANMI(value uint32) {
	volatile.StoreUint32(&o.ICUSARB.Reg, volatile.LoadUint32(&o.ICUSARB.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetICUSARB_SANMI() uint32 {
	return volatile.LoadUint32(&o.ICUSARB.Reg) & 0x1
}

// CPSCU.ICUSARC: Interrupt Controller Unit Security Attribution Register C
func (o *CPSCU_Type) SetICUSARC_SADMAC0(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC0() uint32 {
	return volatile.LoadUint32(&o.ICUSARC.Reg) & 0x1
}
func (o *CPSCU_Type) SetICUSARC_SADMAC1(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x2)|value<<1)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC1() uint32 {
	return (volatile.LoadUint32(&o.ICUSARC.Reg) & 0x2) >> 1
}
func (o *CPSCU_Type) SetICUSARC_SADMAC2(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x4)|value<<2)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC2() uint32 {
	return (volatile.LoadUint32(&o.ICUSARC.Reg) & 0x4) >> 2
}
func (o *CPSCU_Type) SetICUSARC_SADMAC3(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x8)|value<<3)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC3() uint32 {
	return (volatile.LoadUint32(&o.ICUSARC.Reg) & 0x8) >> 3
}
func (o *CPSCU_Type) SetICUSARC_SADMAC4(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x10)|value<<4)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC4() uint32 {
	return (volatile.LoadUint32(&o.ICUSARC.Reg) & 0x10) >> 4
}
func (o *CPSCU_Type) SetICUSARC_SADMAC5(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x20)|value<<5)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC5() uint32 {
	return (volatile.LoadUint32(&o.ICUSARC.Reg) & 0x20) >> 5
}
func (o *CPSCU_Type) SetICUSARC_SADMAC6(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x40)|value<<6)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC6() uint32 {
	return (volatile.LoadUint32(&o.ICUSARC.Reg) & 0x40) >> 6
}
func (o *CPSCU_Type) SetICUSARC_SADMAC7(value uint32) {
	volatile.StoreUint32(&o.ICUSARC.Reg, volatile.LoadUint32(&o.ICUSARC.Reg)&^(0x80)|value<<7)
}
func (o *CPSCU_Type) GetICUSARC_SADMAC7() uint32 {
	return (volatile.LoadUint32(&o.ICUSARC.Reg) & 0x80) >> 7
}

// CPSCU.ICUSARD: Interrupt Controller Unit Security Attribution Register D
func (o *CPSCU_Type) SetICUSARD_SASELSR0(value uint32) {
	volatile.StoreUint32(&o.ICUSARD.Reg, volatile.LoadUint32(&o.ICUSARD.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetICUSARD_SASELSR0() uint32 {
	return volatile.LoadUint32(&o.ICUSARD.Reg) & 0x1
}

// CPSCU.ICUSARF: Interrupt Controller Unit Security Attribution Register F
func (o *CPSCU_Type) SetICUSARF_SAI3CWUP(value uint32) {
	volatile.StoreUint32(&o.ICUSARF.Reg, volatile.LoadUint32(&o.ICUSARF.Reg)&^(0x800)|value<<11)
}
func (o *CPSCU_Type) GetICUSARF_SAI3CWUP() uint32 {
	return (volatile.LoadUint32(&o.ICUSARF.Reg) & 0x800) >> 11
}

// CPSCU.ICUSARG: Interrupt Controller Unit Security Attribution Register G
func (o *CPSCU_Type) SetICUSARG_SAIELSR00(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR00() uint32 {
	return volatile.LoadUint32(&o.ICUSARG.Reg) & 0x1
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR01(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x2)|value<<1)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR01() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x2) >> 1
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR02(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x4)|value<<2)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR02() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x4) >> 2
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR03(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x8)|value<<3)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR03() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x8) >> 3
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR04(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x10)|value<<4)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR04() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x10) >> 4
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR05(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x20)|value<<5)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR05() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x20) >> 5
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR06(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x40)|value<<6)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR06() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x40) >> 6
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR07(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x80)|value<<7)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR07() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x80) >> 7
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR08(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x100)|value<<8)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR08() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x100) >> 8
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR09(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x200)|value<<9)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR09() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x200) >> 9
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR10(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x400)|value<<10)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR10() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x400) >> 10
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR11(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x800)|value<<11)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR11() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x800) >> 11
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR12(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x1000)|value<<12)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR12() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x1000) >> 12
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR13(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x2000)|value<<13)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR13() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x2000) >> 13
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR14(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x4000)|value<<14)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR14() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x4000) >> 14
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR15(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x8000)|value<<15)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR15() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x8000) >> 15
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR16(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x10000)|value<<16)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR16() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x10000) >> 16
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR17(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x20000)|value<<17)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR17() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x20000) >> 17
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR18(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x40000)|value<<18)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR18() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x40000) >> 18
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR19(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x80000)|value<<19)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR19() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x80000) >> 19
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR20(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x100000)|value<<20)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR20() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x100000) >> 20
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR21(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x200000)|value<<21)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR21() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x200000) >> 21
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR22(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x400000)|value<<22)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR22() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x400000) >> 22
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR23(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x800000)|value<<23)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR23() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x800000) >> 23
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR24(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x1000000)|value<<24)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR24() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x1000000) >> 24
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR25(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x2000000)|value<<25)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR25() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x2000000) >> 25
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR26(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x4000000)|value<<26)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR26() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x4000000) >> 26
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR27(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x8000000)|value<<27)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR27() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x8000000) >> 27
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR28(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x10000000)|value<<28)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR28() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x10000000) >> 28
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR29(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x20000000)|value<<29)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR29() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x20000000) >> 29
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR30(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x40000000)|value<<30)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR30() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x40000000) >> 30
}
func (o *CPSCU_Type) SetICUSARG_SAIELSR31(value uint32) {
	volatile.StoreUint32(&o.ICUSARG.Reg, volatile.LoadUint32(&o.ICUSARG.Reg)&^(0x80000000)|value<<31)
}
func (o *CPSCU_Type) GetICUSARG_SAIELSR31() uint32 {
	return (volatile.LoadUint32(&o.ICUSARG.Reg) & 0x80000000) >> 31
}

// CPSCU.ICUSARH: Interrupt Controller Unit Security Attribution Register H
func (o *CPSCU_Type) SetICUSARH_SAIELSR32(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR32() uint32 {
	return volatile.LoadUint32(&o.ICUSARH.Reg) & 0x1
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR33(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x2)|value<<1)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR33() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x2) >> 1
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR34(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x4)|value<<2)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR34() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x4) >> 2
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR35(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x8)|value<<3)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR35() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x8) >> 3
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR36(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x10)|value<<4)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR36() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x10) >> 4
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR37(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x20)|value<<5)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR37() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x20) >> 5
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR38(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x40)|value<<6)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR38() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x40) >> 6
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR39(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x80)|value<<7)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR39() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x80) >> 7
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR40(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x100)|value<<8)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR40() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x100) >> 8
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR41(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x200)|value<<9)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR41() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x200) >> 9
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR42(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x400)|value<<10)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR42() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x400) >> 10
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR43(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x800)|value<<11)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR43() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x800) >> 11
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR44(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x1000)|value<<12)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR44() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x1000) >> 12
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR45(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x2000)|value<<13)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR45() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x2000) >> 13
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR46(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x4000)|value<<14)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR46() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x4000) >> 14
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR47(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x8000)|value<<15)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR47() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x8000) >> 15
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR48(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x10000)|value<<16)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR48() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x10000) >> 16
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR49(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x20000)|value<<17)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR49() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x20000) >> 17
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR50(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x40000)|value<<18)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR50() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x40000) >> 18
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR51(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x80000)|value<<19)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR51() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x80000) >> 19
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR52(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x100000)|value<<20)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR52() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x100000) >> 20
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR53(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x200000)|value<<21)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR53() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x200000) >> 21
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR54(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x400000)|value<<22)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR54() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x400000) >> 22
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR55(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x800000)|value<<23)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR55() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x800000) >> 23
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR56(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x1000000)|value<<24)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR56() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x1000000) >> 24
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR57(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x2000000)|value<<25)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR57() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x2000000) >> 25
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR58(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x4000000)|value<<26)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR58() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x4000000) >> 26
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR59(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x8000000)|value<<27)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR59() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x8000000) >> 27
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR60(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x10000000)|value<<28)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR60() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x10000000) >> 28
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR61(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x20000000)|value<<29)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR61() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x20000000) >> 29
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR62(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x40000000)|value<<30)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR62() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x40000000) >> 30
}
func (o *CPSCU_Type) SetICUSARH_SAIELSR63(value uint32) {
	volatile.StoreUint32(&o.ICUSARH.Reg, volatile.LoadUint32(&o.ICUSARH.Reg)&^(0x80000000)|value<<31)
}
func (o *CPSCU_Type) GetICUSARH_SAIELSR63() uint32 {
	return (volatile.LoadUint32(&o.ICUSARH.Reg) & 0x80000000) >> 31
}

// CPSCU.ICUSARI: Interrupt Controller Unit Security Attribution Register I
func (o *CPSCU_Type) SetICUSARI_SAIELSR64(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR64() uint32 {
	return volatile.LoadUint32(&o.ICUSARI.Reg) & 0x1
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR65(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x2)|value<<1)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR65() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x2) >> 1
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR66(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x4)|value<<2)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR66() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x4) >> 2
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR67(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x8)|value<<3)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR67() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x8) >> 3
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR68(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x10)|value<<4)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR68() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x10) >> 4
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR69(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x20)|value<<5)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR69() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x20) >> 5
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR70(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x40)|value<<6)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR70() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x40) >> 6
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR71(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x80)|value<<7)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR71() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x80) >> 7
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR72(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x100)|value<<8)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR72() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x100) >> 8
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR73(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x200)|value<<9)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR73() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x200) >> 9
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR74(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x400)|value<<10)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR74() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x400) >> 10
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR75(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x800)|value<<11)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR75() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x800) >> 11
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR76(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x1000)|value<<12)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR76() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x1000) >> 12
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR77(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x2000)|value<<13)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR77() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x2000) >> 13
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR78(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x4000)|value<<14)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR78() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x4000) >> 14
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR79(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x8000)|value<<15)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR79() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x8000) >> 15
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR80(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x10000)|value<<16)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR80() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x10000) >> 16
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR81(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x20000)|value<<17)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR81() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x20000) >> 17
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR82(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x40000)|value<<18)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR82() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x40000) >> 18
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR83(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x80000)|value<<19)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR83() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x80000) >> 19
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR84(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x100000)|value<<20)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR84() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x100000) >> 20
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR85(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x200000)|value<<21)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR85() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x200000) >> 21
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR86(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x400000)|value<<22)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR86() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x400000) >> 22
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR87(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x800000)|value<<23)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR87() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x800000) >> 23
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR88(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x1000000)|value<<24)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR88() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x1000000) >> 24
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR89(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x2000000)|value<<25)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR89() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x2000000) >> 25
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR90(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x4000000)|value<<26)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR90() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x4000000) >> 26
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR91(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x8000000)|value<<27)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR91() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x8000000) >> 27
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR92(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x10000000)|value<<28)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR92() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x10000000) >> 28
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR93(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x20000000)|value<<29)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR93() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x20000000) >> 29
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR94(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x40000000)|value<<30)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR94() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x40000000) >> 30
}
func (o *CPSCU_Type) SetICUSARI_SAIELSR95(value uint32) {
	volatile.StoreUint32(&o.ICUSARI.Reg, volatile.LoadUint32(&o.ICUSARI.Reg)&^(0x80000000)|value<<31)
}
func (o *CPSCU_Type) GetICUSARI_SAIELSR95() uint32 {
	return (volatile.LoadUint32(&o.ICUSARI.Reg) & 0x80000000) >> 31
}

// CPSCU.BUSSARA: BUS Security Attribution Register A
func (o *CPSCU_Type) SetBUSSARA_BUSSA0(value uint32) {
	volatile.StoreUint32(&o.BUSSARA.Reg, volatile.LoadUint32(&o.BUSSARA.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetBUSSARA_BUSSA0() uint32 {
	return volatile.LoadUint32(&o.BUSSARA.Reg) & 0x1
}

// CPSCU.BUSSARB: BUS Security Attribution Register B
func (o *CPSCU_Type) SetBUSSARB_BUSSB0(value uint32) {
	volatile.StoreUint32(&o.BUSSARB.Reg, volatile.LoadUint32(&o.BUSSARB.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetBUSSARB_BUSSB0() uint32 {
	return volatile.LoadUint32(&o.BUSSARB.Reg) & 0x1
}

// CPSCU.MMPUSARA: Master Memory Protection Unit Security Attribution Register A
func (o *CPSCU_Type) SetMMPUSARA_MMPUASAn(value uint32) {
	volatile.StoreUint32(&o.MMPUSARA.Reg, volatile.LoadUint32(&o.MMPUSARA.Reg)&^(0xff)|value)
}
func (o *CPSCU_Type) GetMMPUSARA_MMPUASAn() uint32 {
	return volatile.LoadUint32(&o.MMPUSARA.Reg) & 0xff
}

// CPSCU.MMPUSARB: Master Memory Protection Unit Security Attribution Register B
func (o *CPSCU_Type) SetMMPUSARB_MMPUBSA0(value uint32) {
	volatile.StoreUint32(&o.MMPUSARB.Reg, volatile.LoadUint32(&o.MMPUSARB.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetMMPUSARB_MMPUBSA0() uint32 {
	return volatile.LoadUint32(&o.MMPUSARB.Reg) & 0x1
}

// CPSCU.TZFSAR: TrustZone Filter Security Attribution Register
func (o *CPSCU_Type) SetTZFSAR_TZFSA0(value uint32) {
	volatile.StoreUint32(&o.TZFSAR.Reg, volatile.LoadUint32(&o.TZFSAR.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetTZFSAR_TZFSA0() uint32 {
	return volatile.LoadUint32(&o.TZFSAR.Reg) & 0x1
}

// CPSCU.CPUDSAR: CPU Debug Security Attribution Register
func (o *CPSCU_Type) SetCPUDSAR_CPUDSA0(value uint32) {
	volatile.StoreUint32(&o.CPUDSAR.Reg, volatile.LoadUint32(&o.CPUDSAR.Reg)&^(0x1)|value)
}
func (o *CPSCU_Type) GetCPUDSAR_CPUDSA0() uint32 {
	return volatile.LoadUint32(&o.CPUDSAR.Reg) & 0x1
}

// Debug Function
type DBG_Type struct {
	DBGSTR    volatile.Register32 // 0x0
	_         [12]byte
	DBGSTOPCR volatile.Register32 // 0x10
}

// DBG.DBGSTR: Debug Status Register
func (o *DBG_Type) SetDBGSTR_CDBGPWRUPREQ(value uint32) {
	volatile.StoreUint32(&o.DBGSTR.Reg, volatile.LoadUint32(&o.DBGSTR.Reg)&^(0x10000000)|value<<28)
}
func (o *DBG_Type) GetDBGSTR_CDBGPWRUPREQ() uint32 {
	return (volatile.LoadUint32(&o.DBGSTR.Reg) & 0x10000000) >> 28
}
func (o *DBG_Type) SetDBGSTR_CDBGPWRUPACK(value uint32) {
	volatile.StoreUint32(&o.DBGSTR.Reg, volatile.LoadUint32(&o.DBGSTR.Reg)&^(0x20000000)|value<<29)
}
func (o *DBG_Type) GetDBGSTR_CDBGPWRUPACK() uint32 {
	return (volatile.LoadUint32(&o.DBGSTR.Reg) & 0x20000000) >> 29
}

// DBG.DBGSTOPCR: Debug Stop Control Register
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_IWDT(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x1)|value)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_IWDT() uint32 {
	return volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x1
}
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_WDT(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x2)|value<<1)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_WDT() uint32 {
	return (volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x2) >> 1
}
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_LVD0(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x10000)|value<<16)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_LVD0() uint32 {
	return (volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x10000) >> 16
}
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_LVD1(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x20000)|value<<17)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_LVD1() uint32 {
	return (volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x20000) >> 17
}
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_LVD2(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x40000)|value<<18)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_LVD2() uint32 {
	return (volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x40000) >> 18
}
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_RPER(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x1000000)|value<<24)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_RPER() uint32 {
	return (volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x1000000) >> 24
}
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_RECCR(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x2000000)|value<<25)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_RECCR() uint32 {
	return (volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x2000000) >> 25
}
func (o *DBG_Type) SetDBGSTOPCR_DBGSTOP_CPER(value uint32) {
	volatile.StoreUint32(&o.DBGSTOPCR.Reg, volatile.LoadUint32(&o.DBGSTOPCR.Reg)&^(0x80000000)|value<<31)
}
func (o *DBG_Type) GetDBGSTOPCR_DBGSTOP_CPER() uint32 {
	return (volatile.LoadUint32(&o.DBGSTOPCR.Reg) & 0x80000000) >> 31
}

// SYSTEM/FLASH
type FCACHE_Type struct {
	FCACHEE  volatile.Register16 // 0x0
	_        [2]byte
	FCACHEIV volatile.Register16 // 0x4
	_        [22]byte
	FLWT     volatile.Register8 // 0x1C
	_        [35]byte
	FSAR     volatile.Register16 // 0x40
}

// FCACHE.FCACHEE: Flash Cache Enable Register
func (o *FCACHE_Type) SetFCACHEE_FCACHEEN(value uint16) {
	volatile.StoreUint16(&o.FCACHEE.Reg, volatile.LoadUint16(&o.FCACHEE.Reg)&^(0x1)|value)
}
func (o *FCACHE_Type) GetFCACHEE_FCACHEEN() uint16 {
	return volatile.LoadUint16(&o.FCACHEE.Reg) & 0x1
}

// FCACHE.FCACHEIV: Flash Cache Invalidate Register
func (o *FCACHE_Type) SetFCACHEIV(value uint16) {
	volatile.StoreUint16(&o.FCACHEIV.Reg, volatile.LoadUint16(&o.FCACHEIV.Reg)&^(0x1)|value)
}
func (o *FCACHE_Type) GetFCACHEIV() uint16 {
	return volatile.LoadUint16(&o.FCACHEIV.Reg) & 0x1
}

// FCACHE.FLWT: Flash Wait Cycle Register
func (o *FCACHE_Type) SetFLWT(value uint8) {
	volatile.StoreUint8(&o.FLWT.Reg, volatile.LoadUint8(&o.FLWT.Reg)&^(0x7)|value)
}
func (o *FCACHE_Type) GetFLWT() uint8 {
	return volatile.LoadUint8(&o.FLWT.Reg) & 0x7
}

// FCACHE.FSAR: Flash Security Attribution Register
func (o *FCACHE_Type) SetFSAR_FLWTSA(value uint16) {
	volatile.StoreUint16(&o.FSAR.Reg, volatile.LoadUint16(&o.FSAR.Reg)&^(0x1)|value)
}
func (o *FCACHE_Type) GetFSAR_FLWTSA() uint16 {
	return volatile.LoadUint16(&o.FSAR.Reg) & 0x1
}
func (o *FCACHE_Type) SetFSAR_FCKMHZSA(value uint16) {
	volatile.StoreUint16(&o.FSAR.Reg, volatile.LoadUint16(&o.FSAR.Reg)&^(0x100)|value<<8)
}
func (o *FCACHE_Type) GetFSAR_FCKMHZSA() uint16 {
	return (volatile.LoadUint16(&o.FSAR.Reg) & 0x100) >> 8
}

// System Control
type SYSC_Type struct {
	_            [12]byte
	SBYCR        volatile.Register16 // 0xC
	_            [18]byte
	SCKDIVCR     volatile.Register32 // 0x20
	_            [2]byte
	SCKSCR       volatile.Register8 // 0x26
	_            byte
	PLLCCR       volatile.Register16 // 0x28
	PLLCR        volatile.Register8  // 0x2A
	_            [7]byte
	MOSCCR       volatile.Register8 // 0x32
	_            [3]byte
	HOCOCR       volatile.Register8 // 0x36
	_            byte
	MOCOCR       volatile.Register8  // 0x38
	FLLCR1       volatile.Register8  // 0x39
	FLLCR2       volatile.Register16 // 0x3A
	OSCSF        volatile.Register8  // 0x3C
	_            byte
	CKOCR        volatile.Register8 // 0x3E
	_            byte
	OSTDCR       volatile.Register8 // 0x40
	OSTDSR       volatile.Register8 // 0x41
	_            [31]byte
	MOCOUTCR     volatile.Register8 // 0x61
	HOCOUTCR     volatile.Register8 // 0x62
	_            [9]byte
	USBCKDIVCR   volatile.Register8 // 0x6C
	_            byte
	CANFDCKDIVCR volatile.Register8 // 0x6E
	_            byte
	CECCKDIVCR   volatile.Register8 // 0x70
	I3CCKDIVCR   volatile.Register8 // 0x71
	_            [2]byte
	USBCKCR      volatile.Register8 // 0x74
	_            byte
	CANFDCKCR    volatile.Register8 // 0x76
	_            byte
	CECCKCR      volatile.Register8 // 0x78
	I3CCKCR      volatile.Register8 // 0x79
	_            [24]byte
	SNZCR        volatile.Register8 // 0x92
	_            byte
	SNZEDCR0     volatile.Register8 // 0x94
	_            [3]byte
	SNZREQCR0    volatile.Register32 // 0x98
	_            [4]byte
	OPCCR        volatile.Register8 // 0xA0
	_            byte
	MOSCWTCR     volatile.Register8 // 0xA2
	_            [7]byte
	SOPCCR       volatile.Register8 // 0xAA
	_            [21]byte
	RSTSR1       volatile.Register16 // 0xC0
	_            [30]byte
	LVD1CR1      volatile.Register8 // 0xE0
	LVD1SR       volatile.Register8 // 0xE1
	LVD2CR1      volatile.Register8 // 0xE2
	LVD2SR       volatile.Register8 // 0xE3
	_            [732]byte
	CGFSAR       volatile.Register32 // 0x3C0
	RSTSAR       volatile.Register32 // 0x3C4
	LPMSAR       volatile.Register32 // 0x3C8
	LVDSAR       volatile.Register32 // 0x3CC
	_            [16]byte
	DPFSAR       volatile.Register32 // 0x3E0
	_            [26]byte
	PRCR         volatile.Register16 // 0x3FE
	DPSBYCR      volatile.Register8  // 0x400
	DPSWCR       volatile.Register8  // 0x401
	DPSIER0      volatile.Register8  // 0x402
	DPSIER1      volatile.Register8  // 0x403
	DPSIER2      volatile.Register8  // 0x404
	DPSIER3      volatile.Register8  // 0x405
	DPSIFR0      volatile.Register8  // 0x406
	DPSIFR1      volatile.Register8  // 0x407
	DPSIFR2      volatile.Register8  // 0x408
	DPSIFR3      volatile.Register8  // 0x409
	DPSIEGR0     volatile.Register8  // 0x40A
	DPSIEGR1     volatile.Register8  // 0x40B
	DPSIEGR2     volatile.Register8  // 0x40C
	_            byte
	SYOCDCR      volatile.Register8 // 0x40E
	_            byte
	RSTSR0       volatile.Register8 // 0x410
	RSTSR2       volatile.Register8 // 0x411
	_            byte
	MOMCR        volatile.Register8 // 0x413
	_            [2]byte
	FWEPROR      volatile.Register8 // 0x416
	LVD1CMPCR    volatile.Register8 // 0x417
	LVD2CMPCR    volatile.Register8 // 0x418
	_            byte
	LVD1CR0      volatile.Register8 // 0x41A
	LVD2CR0      volatile.Register8 // 0x41B
	_            [100]byte
	SOSCCR       volatile.Register8 // 0x480
	SOMCR        volatile.Register8 // 0x481
	_            [14]byte
	LOCOCR       volatile.Register8 // 0x490
	_            byte
	LOCOUTCR     volatile.Register8 // 0x492
}

// SYSC.SBYCR: Standby Control Register
func (o *SYSC_Type) SetSBYCR_SSBY(value uint16) {
	volatile.StoreUint16(&o.SBYCR.Reg, volatile.LoadUint16(&o.SBYCR.Reg)&^(0x8000)|value<<15)
}
func (o *SYSC_Type) GetSBYCR_SSBY() uint16 {
	return (volatile.LoadUint16(&o.SBYCR.Reg) & 0x8000) >> 15
}

// SYSC.SCKDIVCR: System Clock Division Control Register
func (o *SYSC_Type) SetSCKDIVCR_PCKD(value uint32) {
	volatile.StoreUint32(&o.SCKDIVCR.Reg, volatile.LoadUint32(&o.SCKDIVCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetSCKDIVCR_PCKD() uint32 {
	return volatile.LoadUint32(&o.SCKDIVCR.Reg) & 0x7
}
func (o *SYSC_Type) SetSCKDIVCR_PCKC(value uint32) {
	volatile.StoreUint32(&o.SCKDIVCR.Reg, volatile.LoadUint32(&o.SCKDIVCR.Reg)&^(0x70)|value<<4)
}
func (o *SYSC_Type) GetSCKDIVCR_PCKC() uint32 {
	return (volatile.LoadUint32(&o.SCKDIVCR.Reg) & 0x70) >> 4
}
func (o *SYSC_Type) SetSCKDIVCR_PCKB(value uint32) {
	volatile.StoreUint32(&o.SCKDIVCR.Reg, volatile.LoadUint32(&o.SCKDIVCR.Reg)&^(0x700)|value<<8)
}
func (o *SYSC_Type) GetSCKDIVCR_PCKB() uint32 {
	return (volatile.LoadUint32(&o.SCKDIVCR.Reg) & 0x700) >> 8
}
func (o *SYSC_Type) SetSCKDIVCR_PCKA(value uint32) {
	volatile.StoreUint32(&o.SCKDIVCR.Reg, volatile.LoadUint32(&o.SCKDIVCR.Reg)&^(0x7000)|value<<12)
}
func (o *SYSC_Type) GetSCKDIVCR_PCKA() uint32 {
	return (volatile.LoadUint32(&o.SCKDIVCR.Reg) & 0x7000) >> 12
}
func (o *SYSC_Type) SetSCKDIVCR_ICK(value uint32) {
	volatile.StoreUint32(&o.SCKDIVCR.Reg, volatile.LoadUint32(&o.SCKDIVCR.Reg)&^(0x7000000)|value<<24)
}
func (o *SYSC_Type) GetSCKDIVCR_ICK() uint32 {
	return (volatile.LoadUint32(&o.SCKDIVCR.Reg) & 0x7000000) >> 24
}
func (o *SYSC_Type) SetSCKDIVCR_FCK(value uint32) {
	volatile.StoreUint32(&o.SCKDIVCR.Reg, volatile.LoadUint32(&o.SCKDIVCR.Reg)&^(0x70000000)|value<<28)
}
func (o *SYSC_Type) GetSCKDIVCR_FCK() uint32 {
	return (volatile.LoadUint32(&o.SCKDIVCR.Reg) & 0x70000000) >> 28
}

// SYSC.SCKSCR: System Clock Source Control Register
func (o *SYSC_Type) SetSCKSCR_CKSEL(value uint8) {
	volatile.StoreUint8(&o.SCKSCR.Reg, volatile.LoadUint8(&o.SCKSCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetSCKSCR_CKSEL() uint8 {
	return volatile.LoadUint8(&o.SCKSCR.Reg) & 0x7
}

// SYSC.PLLCCR: PLL Clock Control Register
func (o *SYSC_Type) SetPLLCCR_PLIDIV(value uint16) {
	volatile.StoreUint16(&o.PLLCCR.Reg, volatile.LoadUint16(&o.PLLCCR.Reg)&^(0x3)|value)
}
func (o *SYSC_Type) GetPLLCCR_PLIDIV() uint16 {
	return volatile.LoadUint16(&o.PLLCCR.Reg) & 0x3
}
func (o *SYSC_Type) SetPLLCCR_PLSRCSEL(value uint16) {
	volatile.StoreUint16(&o.PLLCCR.Reg, volatile.LoadUint16(&o.PLLCCR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetPLLCCR_PLSRCSEL() uint16 {
	return (volatile.LoadUint16(&o.PLLCCR.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetPLLCCR_PLLMUL(value uint16) {
	volatile.StoreUint16(&o.PLLCCR.Reg, volatile.LoadUint16(&o.PLLCCR.Reg)&^(0x3f00)|value<<8)
}
func (o *SYSC_Type) GetPLLCCR_PLLMUL() uint16 {
	return (volatile.LoadUint16(&o.PLLCCR.Reg) & 0x3f00) >> 8
}

// SYSC.PLLCR: PLL Control Register
func (o *SYSC_Type) SetPLLCR_PLLSTP(value uint8) {
	volatile.StoreUint8(&o.PLLCR.Reg, volatile.LoadUint8(&o.PLLCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetPLLCR_PLLSTP() uint8 {
	return volatile.LoadUint8(&o.PLLCR.Reg) & 0x1
}

// SYSC.MOSCCR: Main Clock Oscillator Control Register
func (o *SYSC_Type) SetMOSCCR_MOSTP(value uint8) {
	volatile.StoreUint8(&o.MOSCCR.Reg, volatile.LoadUint8(&o.MOSCCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetMOSCCR_MOSTP() uint8 {
	return volatile.LoadUint8(&o.MOSCCR.Reg) & 0x1
}

// SYSC.HOCOCR: High-Speed On-Chip Oscillator Control Register
func (o *SYSC_Type) SetHOCOCR_HCSTP(value uint8) {
	volatile.StoreUint8(&o.HOCOCR.Reg, volatile.LoadUint8(&o.HOCOCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetHOCOCR_HCSTP() uint8 {
	return volatile.LoadUint8(&o.HOCOCR.Reg) & 0x1
}

// SYSC.MOCOCR: Middle-Speed On-Chip Oscillator Control Register
func (o *SYSC_Type) SetMOCOCR_MCSTP(value uint8) {
	volatile.StoreUint8(&o.MOCOCR.Reg, volatile.LoadUint8(&o.MOCOCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetMOCOCR_MCSTP() uint8 {
	return volatile.LoadUint8(&o.MOCOCR.Reg) & 0x1
}

// SYSC.FLLCR1: FLL Control Register1
func (o *SYSC_Type) SetFLLCR1_FLLEN(value uint8) {
	volatile.StoreUint8(&o.FLLCR1.Reg, volatile.LoadUint8(&o.FLLCR1.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetFLLCR1_FLLEN() uint8 {
	return volatile.LoadUint8(&o.FLLCR1.Reg) & 0x1
}

// SYSC.FLLCR2: FLL Control Register2
func (o *SYSC_Type) SetFLLCR2_FLLCNTL(value uint16) {
	volatile.StoreUint16(&o.FLLCR2.Reg, volatile.LoadUint16(&o.FLLCR2.Reg)&^(0x7ff)|value)
}
func (o *SYSC_Type) GetFLLCR2_FLLCNTL() uint16 {
	return volatile.LoadUint16(&o.FLLCR2.Reg) & 0x7ff
}

// SYSC.OSCSF: Oscillation Stabilization Flag Register
func (o *SYSC_Type) SetOSCSF_HOCOSF(value uint8) {
	volatile.StoreUint8(&o.OSCSF.Reg, volatile.LoadUint8(&o.OSCSF.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetOSCSF_HOCOSF() uint8 {
	return volatile.LoadUint8(&o.OSCSF.Reg) & 0x1
}
func (o *SYSC_Type) SetOSCSF_MOSCSF(value uint8) {
	volatile.StoreUint8(&o.OSCSF.Reg, volatile.LoadUint8(&o.OSCSF.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetOSCSF_MOSCSF() uint8 {
	return (volatile.LoadUint8(&o.OSCSF.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetOSCSF_PLLSF(value uint8) {
	volatile.StoreUint8(&o.OSCSF.Reg, volatile.LoadUint8(&o.OSCSF.Reg)&^(0x20)|value<<5)
}
func (o *SYSC_Type) GetOSCSF_PLLSF() uint8 {
	return (volatile.LoadUint8(&o.OSCSF.Reg) & 0x20) >> 5
}

// SYSC.CKOCR: Clock Out Control Register
func (o *SYSC_Type) SetCKOCR_CKOSEL(value uint8) {
	volatile.StoreUint8(&o.CKOCR.Reg, volatile.LoadUint8(&o.CKOCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetCKOCR_CKOSEL() uint8 {
	return volatile.LoadUint8(&o.CKOCR.Reg) & 0x7
}
func (o *SYSC_Type) SetCKOCR_CKODIV(value uint8) {
	volatile.StoreUint8(&o.CKOCR.Reg, volatile.LoadUint8(&o.CKOCR.Reg)&^(0x70)|value<<4)
}
func (o *SYSC_Type) GetCKOCR_CKODIV() uint8 {
	return (volatile.LoadUint8(&o.CKOCR.Reg) & 0x70) >> 4
}
func (o *SYSC_Type) SetCKOCR_CKOEN(value uint8) {
	volatile.StoreUint8(&o.CKOCR.Reg, volatile.LoadUint8(&o.CKOCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetCKOCR_CKOEN() uint8 {
	return (volatile.LoadUint8(&o.CKOCR.Reg) & 0x80) >> 7
}

// SYSC.OSTDCR: Oscillation Stop Detection Control Register
func (o *SYSC_Type) SetOSTDCR_OSTDIE(value uint8) {
	volatile.StoreUint8(&o.OSTDCR.Reg, volatile.LoadUint8(&o.OSTDCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetOSTDCR_OSTDIE() uint8 {
	return volatile.LoadUint8(&o.OSTDCR.Reg) & 0x1
}
func (o *SYSC_Type) SetOSTDCR_OSTDE(value uint8) {
	volatile.StoreUint8(&o.OSTDCR.Reg, volatile.LoadUint8(&o.OSTDCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetOSTDCR_OSTDE() uint8 {
	return (volatile.LoadUint8(&o.OSTDCR.Reg) & 0x80) >> 7
}

// SYSC.OSTDSR: Oscillation Stop Detection Status Register
func (o *SYSC_Type) SetOSTDSR_OSTDF(value uint8) {
	volatile.StoreUint8(&o.OSTDSR.Reg, volatile.LoadUint8(&o.OSTDSR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetOSTDSR_OSTDF() uint8 {
	return volatile.LoadUint8(&o.OSTDSR.Reg) & 0x1
}

// SYSC.MOCOUTCR: MOCO User Trimming Control Register
func (o *SYSC_Type) SetMOCOUTCR(value uint8) {
	volatile.StoreUint8(&o.MOCOUTCR.Reg, value)
}
func (o *SYSC_Type) GetMOCOUTCR() uint8 {
	return volatile.LoadUint8(&o.MOCOUTCR.Reg)
}

// SYSC.HOCOUTCR: HOCO User Trimming Control Register
func (o *SYSC_Type) SetHOCOUTCR(value uint8) {
	volatile.StoreUint8(&o.HOCOUTCR.Reg, value)
}
func (o *SYSC_Type) GetHOCOUTCR() uint8 {
	return volatile.LoadUint8(&o.HOCOUTCR.Reg)
}

// SYSC.USBCKDIVCR: USB Clock Division Control Register
func (o *SYSC_Type) SetUSBCKDIVCR_USBCKDIV(value uint8) {
	volatile.StoreUint8(&o.USBCKDIVCR.Reg, volatile.LoadUint8(&o.USBCKDIVCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetUSBCKDIVCR_USBCKDIV() uint8 {
	return volatile.LoadUint8(&o.USBCKDIVCR.Reg) & 0x7
}

// SYSC.CANFDCKDIVCR: CANFD Clock Division Control Register
func (o *SYSC_Type) SetCANFDCKDIVCR_CANFDCKDIV(value uint8) {
	volatile.StoreUint8(&o.CANFDCKDIVCR.Reg, volatile.LoadUint8(&o.CANFDCKDIVCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetCANFDCKDIVCR_CANFDCKDIV() uint8 {
	return volatile.LoadUint8(&o.CANFDCKDIVCR.Reg) & 0x7
}

// SYSC.CECCKDIVCR: CEC Clock Division Control Register
func (o *SYSC_Type) SetCECCKDIVCR_CECCKDIV(value uint8) {
	volatile.StoreUint8(&o.CECCKDIVCR.Reg, volatile.LoadUint8(&o.CECCKDIVCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetCECCKDIVCR_CECCKDIV() uint8 {
	return volatile.LoadUint8(&o.CECCKDIVCR.Reg) & 0x7
}

// SYSC.I3CCKDIVCR: I3C Clock Division Control Register
func (o *SYSC_Type) SetI3CCKDIVCR_I3CCKDIV(value uint8) {
	volatile.StoreUint8(&o.I3CCKDIVCR.Reg, volatile.LoadUint8(&o.I3CCKDIVCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetI3CCKDIVCR_I3CCKDIV() uint8 {
	return volatile.LoadUint8(&o.I3CCKDIVCR.Reg) & 0x7
}

// SYSC.USBCKCR: USB Clock Control Register
func (o *SYSC_Type) SetUSBCKCR_USBCKSEL(value uint8) {
	volatile.StoreUint8(&o.USBCKCR.Reg, volatile.LoadUint8(&o.USBCKCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetUSBCKCR_USBCKSEL() uint8 {
	return volatile.LoadUint8(&o.USBCKCR.Reg) & 0x7
}
func (o *SYSC_Type) SetUSBCKCR_USBCKSREQ(value uint8) {
	volatile.StoreUint8(&o.USBCKCR.Reg, volatile.LoadUint8(&o.USBCKCR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetUSBCKCR_USBCKSREQ() uint8 {
	return (volatile.LoadUint8(&o.USBCKCR.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetUSBCKCR_USBCKSRDY(value uint8) {
	volatile.StoreUint8(&o.USBCKCR.Reg, volatile.LoadUint8(&o.USBCKCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetUSBCKCR_USBCKSRDY() uint8 {
	return (volatile.LoadUint8(&o.USBCKCR.Reg) & 0x80) >> 7
}

// SYSC.CANFDCKCR: CANFD Clock Control Register
func (o *SYSC_Type) SetCANFDCKCR_CANFDCKSEL(value uint8) {
	volatile.StoreUint8(&o.CANFDCKCR.Reg, volatile.LoadUint8(&o.CANFDCKCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetCANFDCKCR_CANFDCKSEL() uint8 {
	return volatile.LoadUint8(&o.CANFDCKCR.Reg) & 0x7
}
func (o *SYSC_Type) SetCANFDCKCR_CANFDCKSREQ(value uint8) {
	volatile.StoreUint8(&o.CANFDCKCR.Reg, volatile.LoadUint8(&o.CANFDCKCR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetCANFDCKCR_CANFDCKSREQ() uint8 {
	return (volatile.LoadUint8(&o.CANFDCKCR.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetCANFDCKCR_CANFDCKSRDY(value uint8) {
	volatile.StoreUint8(&o.CANFDCKCR.Reg, volatile.LoadUint8(&o.CANFDCKCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetCANFDCKCR_CANFDCKSRDY() uint8 {
	return (volatile.LoadUint8(&o.CANFDCKCR.Reg) & 0x80) >> 7
}

// SYSC.CECCKCR: CEC Clock Control Register
func (o *SYSC_Type) SetCECCKCR_CECCKSEL(value uint8) {
	volatile.StoreUint8(&o.CECCKCR.Reg, volatile.LoadUint8(&o.CECCKCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetCECCKCR_CECCKSEL() uint8 {
	return volatile.LoadUint8(&o.CECCKCR.Reg) & 0x7
}
func (o *SYSC_Type) SetCECCKCR_CECCKSREQ(value uint8) {
	volatile.StoreUint8(&o.CECCKCR.Reg, volatile.LoadUint8(&o.CECCKCR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetCECCKCR_CECCKSREQ() uint8 {
	return (volatile.LoadUint8(&o.CECCKCR.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetCECCKCR_CECCKSRDY(value uint8) {
	volatile.StoreUint8(&o.CECCKCR.Reg, volatile.LoadUint8(&o.CECCKCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetCECCKCR_CECCKSRDY() uint8 {
	return (volatile.LoadUint8(&o.CECCKCR.Reg) & 0x80) >> 7
}

// SYSC.I3CCKCR: I3C Clock Control Register
func (o *SYSC_Type) SetI3CCKCR_I3CCKSEL(value uint8) {
	volatile.StoreUint8(&o.I3CCKCR.Reg, volatile.LoadUint8(&o.I3CCKCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetI3CCKCR_I3CCKSEL() uint8 {
	return volatile.LoadUint8(&o.I3CCKCR.Reg) & 0x7
}
func (o *SYSC_Type) SetI3CCKCR_I3CCKSREQ(value uint8) {
	volatile.StoreUint8(&o.I3CCKCR.Reg, volatile.LoadUint8(&o.I3CCKCR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetI3CCKCR_I3CCKSREQ() uint8 {
	return (volatile.LoadUint8(&o.I3CCKCR.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetI3CCKCR_I3CCKSRDY(value uint8) {
	volatile.StoreUint8(&o.I3CCKCR.Reg, volatile.LoadUint8(&o.I3CCKCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetI3CCKCR_I3CCKSRDY() uint8 {
	return (volatile.LoadUint8(&o.I3CCKCR.Reg) & 0x80) >> 7
}

// SYSC.SNZCR: Snooze Control Register
func (o *SYSC_Type) SetSNZCR_RXDREQEN(value uint8) {
	volatile.StoreUint8(&o.SNZCR.Reg, volatile.LoadUint8(&o.SNZCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetSNZCR_RXDREQEN() uint8 {
	return volatile.LoadUint8(&o.SNZCR.Reg) & 0x1
}
func (o *SYSC_Type) SetSNZCR_SNZDTCEN(value uint8) {
	volatile.StoreUint8(&o.SNZCR.Reg, volatile.LoadUint8(&o.SNZCR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetSNZCR_SNZDTCEN() uint8 {
	return (volatile.LoadUint8(&o.SNZCR.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetSNZCR_SNZE(value uint8) {
	volatile.StoreUint8(&o.SNZCR.Reg, volatile.LoadUint8(&o.SNZCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetSNZCR_SNZE() uint8 {
	return (volatile.LoadUint8(&o.SNZCR.Reg) & 0x80) >> 7
}

// SYSC.SNZEDCR0: Snooze End Control Register 0
func (o *SYSC_Type) SetSNZEDCR0_AGTUNFED(value uint8) {
	volatile.StoreUint8(&o.SNZEDCR0.Reg, volatile.LoadUint8(&o.SNZEDCR0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetSNZEDCR0_AGTUNFED() uint8 {
	return volatile.LoadUint8(&o.SNZEDCR0.Reg) & 0x1
}
func (o *SYSC_Type) SetSNZEDCR0_DTCZRED(value uint8) {
	volatile.StoreUint8(&o.SNZEDCR0.Reg, volatile.LoadUint8(&o.SNZEDCR0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetSNZEDCR0_DTCZRED() uint8 {
	return (volatile.LoadUint8(&o.SNZEDCR0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetSNZEDCR0_DTCNZRED(value uint8) {
	volatile.StoreUint8(&o.SNZEDCR0.Reg, volatile.LoadUint8(&o.SNZEDCR0.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetSNZEDCR0_DTCNZRED() uint8 {
	return (volatile.LoadUint8(&o.SNZEDCR0.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetSNZEDCR0_AD0MATED(value uint8) {
	volatile.StoreUint8(&o.SNZEDCR0.Reg, volatile.LoadUint8(&o.SNZEDCR0.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetSNZEDCR0_AD0MATED() uint8 {
	return (volatile.LoadUint8(&o.SNZEDCR0.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetSNZEDCR0_AD0UMTED(value uint8) {
	volatile.StoreUint8(&o.SNZEDCR0.Reg, volatile.LoadUint8(&o.SNZEDCR0.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetSNZEDCR0_AD0UMTED() uint8 {
	return (volatile.LoadUint8(&o.SNZEDCR0.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetSNZEDCR0_SCI0UMTED(value uint8) {
	volatile.StoreUint8(&o.SNZEDCR0.Reg, volatile.LoadUint8(&o.SNZEDCR0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetSNZEDCR0_SCI0UMTED() uint8 {
	return (volatile.LoadUint8(&o.SNZEDCR0.Reg) & 0x80) >> 7
}

// SYSC.SNZREQCR0: Snooze Request Control Register 0
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN0(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN0() uint32 {
	return volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x1
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN1(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN1() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN2(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN2() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN3(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN3() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN4(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN4() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN5(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x20)|value<<5)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN5() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x20) >> 5
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN6(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN6() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN7(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN7() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x80) >> 7
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN8(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x100)|value<<8)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN8() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x100) >> 8
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN9(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x200)|value<<9)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN9() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x200) >> 9
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN10(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x400)|value<<10)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN10() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x400) >> 10
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN11(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x800)|value<<11)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN11() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x800) >> 11
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN12(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x1000)|value<<12)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN12() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x1000) >> 12
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN13(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x2000)|value<<13)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN13() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x2000) >> 13
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN14(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x4000)|value<<14)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN14() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x4000) >> 14
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN24(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x1000000)|value<<24)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN24() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x1000000) >> 24
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN25(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x2000000)|value<<25)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN25() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x2000000) >> 25
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN28(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN28() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x10000000) >> 28
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN29(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN29() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x20000000) >> 29
}
func (o *SYSC_Type) SetSNZREQCR0_SNZREQEN30(value uint32) {
	volatile.StoreUint32(&o.SNZREQCR0.Reg, volatile.LoadUint32(&o.SNZREQCR0.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSC_Type) GetSNZREQCR0_SNZREQEN30() uint32 {
	return (volatile.LoadUint32(&o.SNZREQCR0.Reg) & 0x40000000) >> 30
}

// SYSC.OPCCR: Operating Power Control Register
func (o *SYSC_Type) SetOPCCR_OPCM(value uint8) {
	volatile.StoreUint8(&o.OPCCR.Reg, volatile.LoadUint8(&o.OPCCR.Reg)&^(0x3)|value)
}
func (o *SYSC_Type) GetOPCCR_OPCM() uint8 {
	return volatile.LoadUint8(&o.OPCCR.Reg) & 0x3
}
func (o *SYSC_Type) SetOPCCR_OPCMTSF(value uint8) {
	volatile.StoreUint8(&o.OPCCR.Reg, volatile.LoadUint8(&o.OPCCR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetOPCCR_OPCMTSF() uint8 {
	return (volatile.LoadUint8(&o.OPCCR.Reg) & 0x10) >> 4
}

// SYSC.MOSCWTCR: Main Clock Oscillator Wait Control Register
func (o *SYSC_Type) SetMOSCWTCR_MSTS(value uint8) {
	volatile.StoreUint8(&o.MOSCWTCR.Reg, volatile.LoadUint8(&o.MOSCWTCR.Reg)&^(0xf)|value)
}
func (o *SYSC_Type) GetMOSCWTCR_MSTS() uint8 {
	return volatile.LoadUint8(&o.MOSCWTCR.Reg) & 0xf
}

// SYSC.SOPCCR: Sub Operating Power Control Register
func (o *SYSC_Type) SetSOPCCR_SOPCM(value uint8) {
	volatile.StoreUint8(&o.SOPCCR.Reg, volatile.LoadUint8(&o.SOPCCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetSOPCCR_SOPCM() uint8 {
	return volatile.LoadUint8(&o.SOPCCR.Reg) & 0x1
}
func (o *SYSC_Type) SetSOPCCR_SOPCMTSF(value uint8) {
	volatile.StoreUint8(&o.SOPCCR.Reg, volatile.LoadUint8(&o.SOPCCR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetSOPCCR_SOPCMTSF() uint8 {
	return (volatile.LoadUint8(&o.SOPCCR.Reg) & 0x10) >> 4
}

// SYSC.RSTSR1: Reset Status Register 1
func (o *SYSC_Type) SetRSTSR1_IWDTRF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetRSTSR1_IWDTRF() uint16 {
	return volatile.LoadUint16(&o.RSTSR1.Reg) & 0x1
}
func (o *SYSC_Type) SetRSTSR1_WDTRF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetRSTSR1_WDTRF() uint16 {
	return (volatile.LoadUint16(&o.RSTSR1.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetRSTSR1_SWRF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetRSTSR1_SWRF() uint16 {
	return (volatile.LoadUint16(&o.RSTSR1.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetRSTSR1_RPERF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x100)|value<<8)
}
func (o *SYSC_Type) GetRSTSR1_RPERF() uint16 {
	return (volatile.LoadUint16(&o.RSTSR1.Reg) & 0x100) >> 8
}
func (o *SYSC_Type) SetRSTSR1_REERF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x200)|value<<9)
}
func (o *SYSC_Type) GetRSTSR1_REERF() uint16 {
	return (volatile.LoadUint16(&o.RSTSR1.Reg) & 0x200) >> 9
}
func (o *SYSC_Type) SetRSTSR1_BUSMRF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x800)|value<<11)
}
func (o *SYSC_Type) GetRSTSR1_BUSMRF() uint16 {
	return (volatile.LoadUint16(&o.RSTSR1.Reg) & 0x800) >> 11
}
func (o *SYSC_Type) SetRSTSR1_TZERF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x2000)|value<<13)
}
func (o *SYSC_Type) GetRSTSR1_TZERF() uint16 {
	return (volatile.LoadUint16(&o.RSTSR1.Reg) & 0x2000) >> 13
}
func (o *SYSC_Type) SetRSTSR1_CPERF(value uint16) {
	volatile.StoreUint16(&o.RSTSR1.Reg, volatile.LoadUint16(&o.RSTSR1.Reg)&^(0x8000)|value<<15)
}
func (o *SYSC_Type) GetRSTSR1_CPERF() uint16 {
	return (volatile.LoadUint16(&o.RSTSR1.Reg) & 0x8000) >> 15
}

// SYSC.LVD1CR1: Voltage Monitor 1 Circuit Control Register
func (o *SYSC_Type) SetLVD1CR1_IDTSEL(value uint8) {
	volatile.StoreUint8(&o.LVD1CR1.Reg, volatile.LoadUint8(&o.LVD1CR1.Reg)&^(0x3)|value)
}
func (o *SYSC_Type) GetLVD1CR1_IDTSEL() uint8 {
	return volatile.LoadUint8(&o.LVD1CR1.Reg) & 0x3
}
func (o *SYSC_Type) SetLVD1CR1_IRQSEL(value uint8) {
	volatile.StoreUint8(&o.LVD1CR1.Reg, volatile.LoadUint8(&o.LVD1CR1.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetLVD1CR1_IRQSEL() uint8 {
	return (volatile.LoadUint8(&o.LVD1CR1.Reg) & 0x4) >> 2
}

// SYSC.LVD1SR: Voltage Monitor 1 Circuit Status Register
func (o *SYSC_Type) SetLVD1SR_DET(value uint8) {
	volatile.StoreUint8(&o.LVD1SR.Reg, volatile.LoadUint8(&o.LVD1SR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetLVD1SR_DET() uint8 {
	return volatile.LoadUint8(&o.LVD1SR.Reg) & 0x1
}
func (o *SYSC_Type) SetLVD1SR_MON(value uint8) {
	volatile.StoreUint8(&o.LVD1SR.Reg, volatile.LoadUint8(&o.LVD1SR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetLVD1SR_MON() uint8 {
	return (volatile.LoadUint8(&o.LVD1SR.Reg) & 0x2) >> 1
}

// SYSC.LVD2CR1: Voltage Monitor 2 Circuit Control Register 1
func (o *SYSC_Type) SetLVD2CR1_IDTSEL(value uint8) {
	volatile.StoreUint8(&o.LVD2CR1.Reg, volatile.LoadUint8(&o.LVD2CR1.Reg)&^(0x3)|value)
}
func (o *SYSC_Type) GetLVD2CR1_IDTSEL() uint8 {
	return volatile.LoadUint8(&o.LVD2CR1.Reg) & 0x3
}
func (o *SYSC_Type) SetLVD2CR1_IRQSEL(value uint8) {
	volatile.StoreUint8(&o.LVD2CR1.Reg, volatile.LoadUint8(&o.LVD2CR1.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetLVD2CR1_IRQSEL() uint8 {
	return (volatile.LoadUint8(&o.LVD2CR1.Reg) & 0x4) >> 2
}

// SYSC.LVD2SR: Voltage Monitor 2 Circuit Status Register
func (o *SYSC_Type) SetLVD2SR_DET(value uint8) {
	volatile.StoreUint8(&o.LVD2SR.Reg, volatile.LoadUint8(&o.LVD2SR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetLVD2SR_DET() uint8 {
	return volatile.LoadUint8(&o.LVD2SR.Reg) & 0x1
}
func (o *SYSC_Type) SetLVD2SR_MON(value uint8) {
	volatile.StoreUint8(&o.LVD2SR.Reg, volatile.LoadUint8(&o.LVD2SR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetLVD2SR_MON() uint8 {
	return (volatile.LoadUint8(&o.LVD2SR.Reg) & 0x2) >> 1
}

// SYSC.CGFSAR: Clock Generation Function Security Attribute Register
func (o *SYSC_Type) SetCGFSAR_NONSEC00(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC00() uint32 {
	return volatile.LoadUint32(&o.CGFSAR.Reg) & 0x1
}
func (o *SYSC_Type) SetCGFSAR_NONSEC02(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC02() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetCGFSAR_NONSEC03(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC03() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetCGFSAR_NONSEC04(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC04() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetCGFSAR_NONSEC05(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x20)|value<<5)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC05() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x20) >> 5
}
func (o *SYSC_Type) SetCGFSAR_NONSEC06(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC06() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetCGFSAR_NONSEC07(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC07() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x80) >> 7
}
func (o *SYSC_Type) SetCGFSAR_NONSEC08(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x100)|value<<8)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC08() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x100) >> 8
}
func (o *SYSC_Type) SetCGFSAR_NONSEC11(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x800)|value<<11)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC11() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x800) >> 11
}
func (o *SYSC_Type) SetCGFSAR_NONSEC16(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC16() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x10000) >> 16
}
func (o *SYSC_Type) SetCGFSAR_NONSEC18(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x40000)|value<<18)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC18() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x40000) >> 18
}
func (o *SYSC_Type) SetCGFSAR_NONSEC20(value uint32) {
	volatile.StoreUint32(&o.CGFSAR.Reg, volatile.LoadUint32(&o.CGFSAR.Reg)&^(0x100000)|value<<20)
}
func (o *SYSC_Type) GetCGFSAR_NONSEC20() uint32 {
	return (volatile.LoadUint32(&o.CGFSAR.Reg) & 0x100000) >> 20
}

// SYSC.RSTSAR: Reset Security Attribution Register
func (o *SYSC_Type) SetRSTSAR_NONSEC0(value uint32) {
	volatile.StoreUint32(&o.RSTSAR.Reg, volatile.LoadUint32(&o.RSTSAR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetRSTSAR_NONSEC0() uint32 {
	return volatile.LoadUint32(&o.RSTSAR.Reg) & 0x1
}
func (o *SYSC_Type) SetRSTSAR_NONSEC1(value uint32) {
	volatile.StoreUint32(&o.RSTSAR.Reg, volatile.LoadUint32(&o.RSTSAR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetRSTSAR_NONSEC1() uint32 {
	return (volatile.LoadUint32(&o.RSTSAR.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetRSTSAR_NONSEC2(value uint32) {
	volatile.StoreUint32(&o.RSTSAR.Reg, volatile.LoadUint32(&o.RSTSAR.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetRSTSAR_NONSEC2() uint32 {
	return (volatile.LoadUint32(&o.RSTSAR.Reg) & 0x4) >> 2
}

// SYSC.LPMSAR: Low Power Mode Security Attribution Register
func (o *SYSC_Type) SetLPMSAR_NONSEC0(value uint32) {
	volatile.StoreUint32(&o.LPMSAR.Reg, volatile.LoadUint32(&o.LPMSAR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetLPMSAR_NONSEC0() uint32 {
	return volatile.LoadUint32(&o.LPMSAR.Reg) & 0x1
}
func (o *SYSC_Type) SetLPMSAR_NONSEC2(value uint32) {
	volatile.StoreUint32(&o.LPMSAR.Reg, volatile.LoadUint32(&o.LPMSAR.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetLPMSAR_NONSEC2() uint32 {
	return (volatile.LoadUint32(&o.LPMSAR.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetLPMSAR_NONSEC4(value uint32) {
	volatile.StoreUint32(&o.LPMSAR.Reg, volatile.LoadUint32(&o.LPMSAR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetLPMSAR_NONSEC4() uint32 {
	return (volatile.LoadUint32(&o.LPMSAR.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetLPMSAR_NONSEC8(value uint32) {
	volatile.StoreUint32(&o.LPMSAR.Reg, volatile.LoadUint32(&o.LPMSAR.Reg)&^(0x100)|value<<8)
}
func (o *SYSC_Type) GetLPMSAR_NONSEC8() uint32 {
	return (volatile.LoadUint32(&o.LPMSAR.Reg) & 0x100) >> 8
}
func (o *SYSC_Type) SetLPMSAR_NONSEC9(value uint32) {
	volatile.StoreUint32(&o.LPMSAR.Reg, volatile.LoadUint32(&o.LPMSAR.Reg)&^(0x200)|value<<9)
}
func (o *SYSC_Type) GetLPMSAR_NONSEC9() uint32 {
	return (volatile.LoadUint32(&o.LPMSAR.Reg) & 0x200) >> 9
}

// SYSC.LVDSAR: Low Voltage Detection Security Attribution Register
func (o *SYSC_Type) SetLVDSAR_NONSEC0(value uint32) {
	volatile.StoreUint32(&o.LVDSAR.Reg, volatile.LoadUint32(&o.LVDSAR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetLVDSAR_NONSEC0() uint32 {
	return volatile.LoadUint32(&o.LVDSAR.Reg) & 0x1
}
func (o *SYSC_Type) SetLVDSAR_NONSEC1(value uint32) {
	volatile.StoreUint32(&o.LVDSAR.Reg, volatile.LoadUint32(&o.LVDSAR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetLVDSAR_NONSEC1() uint32 {
	return (volatile.LoadUint32(&o.LVDSAR.Reg) & 0x2) >> 1
}

// SYSC.DPFSAR: Deep Standby Interrupt Factor Security Attribution Register
func (o *SYSC_Type) SetDPFSAR_DPFSA0(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA0() uint32 {
	return volatile.LoadUint32(&o.DPFSAR.Reg) & 0x1
}
func (o *SYSC_Type) SetDPFSAR_DPFSA1(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA1() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPFSAR_DPFSA04(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA04() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetDPFSAR_DPFSA05(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x20)|value<<5)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA05() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x20) >> 5
}
func (o *SYSC_Type) SetDPFSAR_DPFSA06(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA06() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetDPFSAR_DPFSA07(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA07() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x80) >> 7
}
func (o *SYSC_Type) SetDPFSAR_DPFSA08(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x100)|value<<8)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA08() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x100) >> 8
}
func (o *SYSC_Type) SetDPFSAR_DPFSA09(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x200)|value<<9)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA09() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x200) >> 9
}
func (o *SYSC_Type) SetDPFSAR_DPFSA10(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x400)|value<<10)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA10() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x400) >> 10
}
func (o *SYSC_Type) SetDPFSAR_DPFSA11(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x800)|value<<11)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA11() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x800) >> 11
}
func (o *SYSC_Type) SetDPFSAR_DPFSA12(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x1000)|value<<12)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA12() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x1000) >> 12
}
func (o *SYSC_Type) SetDPFSAR_DPFSA14(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x4000)|value<<14)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA14() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x4000) >> 14
}
func (o *SYSC_Type) SetDPFSAR_DPFSA16(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA16() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x10000) >> 16
}
func (o *SYSC_Type) SetDPFSAR_DPFSA17(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x20000)|value<<17)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA17() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x20000) >> 17
}
func (o *SYSC_Type) SetDPFSAR_DPFSA18(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x40000)|value<<18)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA18() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x40000) >> 18
}
func (o *SYSC_Type) SetDPFSAR_DPFSA19(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x80000)|value<<19)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA19() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x80000) >> 19
}
func (o *SYSC_Type) SetDPFSAR_DPFSA20(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x100000)|value<<20)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA20() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x100000) >> 20
}
func (o *SYSC_Type) SetDPFSAR_DPFSA24(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x1000000)|value<<24)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA24() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x1000000) >> 24
}
func (o *SYSC_Type) SetDPFSAR_DPFSA26(value uint32) {
	volatile.StoreUint32(&o.DPFSAR.Reg, volatile.LoadUint32(&o.DPFSAR.Reg)&^(0x4000000)|value<<26)
}
func (o *SYSC_Type) GetDPFSAR_DPFSA26() uint32 {
	return (volatile.LoadUint32(&o.DPFSAR.Reg) & 0x4000000) >> 26
}

// SYSC.PRCR: Protect Register
func (o *SYSC_Type) SetPRCR_PRC0(value uint16) {
	volatile.StoreUint16(&o.PRCR.Reg, volatile.LoadUint16(&o.PRCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetPRCR_PRC0() uint16 {
	return volatile.LoadUint16(&o.PRCR.Reg) & 0x1
}
func (o *SYSC_Type) SetPRCR_PRC1(value uint16) {
	volatile.StoreUint16(&o.PRCR.Reg, volatile.LoadUint16(&o.PRCR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetPRCR_PRC1() uint16 {
	return (volatile.LoadUint16(&o.PRCR.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetPRCR_PRC3(value uint16) {
	volatile.StoreUint16(&o.PRCR.Reg, volatile.LoadUint16(&o.PRCR.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetPRCR_PRC3() uint16 {
	return (volatile.LoadUint16(&o.PRCR.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetPRCR_PRC4(value uint16) {
	volatile.StoreUint16(&o.PRCR.Reg, volatile.LoadUint16(&o.PRCR.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetPRCR_PRC4() uint16 {
	return (volatile.LoadUint16(&o.PRCR.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetPRCR_PRKEY(value uint16) {
	volatile.StoreUint16(&o.PRCR.Reg, volatile.LoadUint16(&o.PRCR.Reg)&^(0xff00)|value<<8)
}
func (o *SYSC_Type) GetPRCR_PRKEY() uint16 {
	return (volatile.LoadUint16(&o.PRCR.Reg) & 0xff00) >> 8
}

// SYSC.DPSBYCR: Deep Standby Control Register
func (o *SYSC_Type) SetDPSBYCR_DEEPCUT(value uint8) {
	volatile.StoreUint8(&o.DPSBYCR.Reg, volatile.LoadUint8(&o.DPSBYCR.Reg)&^(0x3)|value)
}
func (o *SYSC_Type) GetDPSBYCR_DEEPCUT() uint8 {
	return volatile.LoadUint8(&o.DPSBYCR.Reg) & 0x3
}
func (o *SYSC_Type) SetDPSBYCR_IOKEEP(value uint8) {
	volatile.StoreUint8(&o.DPSBYCR.Reg, volatile.LoadUint8(&o.DPSBYCR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPSBYCR_IOKEEP() uint8 {
	return (volatile.LoadUint8(&o.DPSBYCR.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetDPSBYCR_DPSBY(value uint8) {
	volatile.StoreUint8(&o.DPSBYCR.Reg, volatile.LoadUint8(&o.DPSBYCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetDPSBYCR_DPSBY() uint8 {
	return (volatile.LoadUint8(&o.DPSBYCR.Reg) & 0x80) >> 7
}

// SYSC.DPSWCR: Deep Standby Wait Control Register
func (o *SYSC_Type) SetDPSWCR_WTSTS(value uint8) {
	volatile.StoreUint8(&o.DPSWCR.Reg, volatile.LoadUint8(&o.DPSWCR.Reg)&^(0x3f)|value)
}
func (o *SYSC_Type) GetDPSWCR_WTSTS() uint8 {
	return volatile.LoadUint8(&o.DPSWCR.Reg) & 0x3f
}

// SYSC.DPSIER0: Deep Standby Interrupt Enable Register 0
func (o *SYSC_Type) SetDPSIER0_DIRQ0E(value uint8) {
	volatile.StoreUint8(&o.DPSIER0.Reg, volatile.LoadUint8(&o.DPSIER0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIER0_DIRQ0E() uint8 {
	return volatile.LoadUint8(&o.DPSIER0.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIER0_DIRQ1E(value uint8) {
	volatile.StoreUint8(&o.DPSIER0.Reg, volatile.LoadUint8(&o.DPSIER0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIER0_DIRQ1E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIER0_DIRQ4E(value uint8) {
	volatile.StoreUint8(&o.DPSIER0.Reg, volatile.LoadUint8(&o.DPSIER0.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIER0_DIRQ4E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER0.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetDPSIER0_DIRQ5E(value uint8) {
	volatile.StoreUint8(&o.DPSIER0.Reg, volatile.LoadUint8(&o.DPSIER0.Reg)&^(0x20)|value<<5)
}
func (o *SYSC_Type) GetDPSIER0_DIRQ5E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER0.Reg) & 0x20) >> 5
}
func (o *SYSC_Type) SetDPSIER0_DIRQ6E(value uint8) {
	volatile.StoreUint8(&o.DPSIER0.Reg, volatile.LoadUint8(&o.DPSIER0.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPSIER0_DIRQ6E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER0.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetDPSIER0_DIRQ7E(value uint8) {
	volatile.StoreUint8(&o.DPSIER0.Reg, volatile.LoadUint8(&o.DPSIER0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetDPSIER0_DIRQ7E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER0.Reg) & 0x80) >> 7
}

// SYSC.DPSIER1: Deep Standby Interrupt Enable Register 1
func (o *SYSC_Type) SetDPSIER1_DIRQ8E(value uint8) {
	volatile.StoreUint8(&o.DPSIER1.Reg, volatile.LoadUint8(&o.DPSIER1.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIER1_DIRQ8E() uint8 {
	return volatile.LoadUint8(&o.DPSIER1.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIER1_DIRQ9E(value uint8) {
	volatile.StoreUint8(&o.DPSIER1.Reg, volatile.LoadUint8(&o.DPSIER1.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIER1_DIRQ9E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER1.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIER1_DIRQ10E(value uint8) {
	volatile.StoreUint8(&o.DPSIER1.Reg, volatile.LoadUint8(&o.DPSIER1.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetDPSIER1_DIRQ10E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER1.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetDPSIER1_DIRQ11E(value uint8) {
	volatile.StoreUint8(&o.DPSIER1.Reg, volatile.LoadUint8(&o.DPSIER1.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetDPSIER1_DIRQ11E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER1.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetDPSIER1_DIRQ12E(value uint8) {
	volatile.StoreUint8(&o.DPSIER1.Reg, volatile.LoadUint8(&o.DPSIER1.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIER1_DIRQ12E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER1.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetDPSIER1_DIRQ14E(value uint8) {
	volatile.StoreUint8(&o.DPSIER1.Reg, volatile.LoadUint8(&o.DPSIER1.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPSIER1_DIRQ14E() uint8 {
	return (volatile.LoadUint8(&o.DPSIER1.Reg) & 0x40) >> 6
}

// SYSC.DPSIER2: Deep Software Standby Interrupt Enable Register 2
func (o *SYSC_Type) SetDPSIER2_DLVD1IE(value uint8) {
	volatile.StoreUint8(&o.DPSIER2.Reg, volatile.LoadUint8(&o.DPSIER2.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIER2_DLVD1IE() uint8 {
	return volatile.LoadUint8(&o.DPSIER2.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIER2_DLVD2IE(value uint8) {
	volatile.StoreUint8(&o.DPSIER2.Reg, volatile.LoadUint8(&o.DPSIER2.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIER2_DLVD2IE() uint8 {
	return (volatile.LoadUint8(&o.DPSIER2.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIER2_DRTCIIE(value uint8) {
	volatile.StoreUint8(&o.DPSIER2.Reg, volatile.LoadUint8(&o.DPSIER2.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetDPSIER2_DRTCIIE() uint8 {
	return (volatile.LoadUint8(&o.DPSIER2.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetDPSIER2_DRTCAIE(value uint8) {
	volatile.StoreUint8(&o.DPSIER2.Reg, volatile.LoadUint8(&o.DPSIER2.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetDPSIER2_DRTCAIE() uint8 {
	return (volatile.LoadUint8(&o.DPSIER2.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetDPSIER2_DNMIE(value uint8) {
	volatile.StoreUint8(&o.DPSIER2.Reg, volatile.LoadUint8(&o.DPSIER2.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIER2_DNMIE() uint8 {
	return (volatile.LoadUint8(&o.DPSIER2.Reg) & 0x10) >> 4
}

// SYSC.DPSIER3: Deep Standby Interrupt Enable Register 3
func (o *SYSC_Type) SetDPSIER3_DUSBFS0IE(value uint8) {
	volatile.StoreUint8(&o.DPSIER3.Reg, volatile.LoadUint8(&o.DPSIER3.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIER3_DUSBFS0IE() uint8 {
	return volatile.LoadUint8(&o.DPSIER3.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIER3_DAGT1IE(value uint8) {
	volatile.StoreUint8(&o.DPSIER3.Reg, volatile.LoadUint8(&o.DPSIER3.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetDPSIER3_DAGT1IE() uint8 {
	return (volatile.LoadUint8(&o.DPSIER3.Reg) & 0x4) >> 2
}

// SYSC.DPSIFR0: Deep Standby Interrupt Flag Register 0
func (o *SYSC_Type) SetDPSIFR0_DIRQ0F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR0.Reg, volatile.LoadUint8(&o.DPSIFR0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIFR0_DIRQ0F() uint8 {
	return volatile.LoadUint8(&o.DPSIFR0.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIFR0_DIRQ1F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR0.Reg, volatile.LoadUint8(&o.DPSIFR0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIFR0_DIRQ1F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIFR0_DIRQ4F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR0.Reg, volatile.LoadUint8(&o.DPSIFR0.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIFR0_DIRQ4F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR0.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetDPSIFR0_DIRQ5F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR0.Reg, volatile.LoadUint8(&o.DPSIFR0.Reg)&^(0x20)|value<<5)
}
func (o *SYSC_Type) GetDPSIFR0_DIRQ5F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR0.Reg) & 0x20) >> 5
}
func (o *SYSC_Type) SetDPSIFR0_DIRQ6F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR0.Reg, volatile.LoadUint8(&o.DPSIFR0.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPSIFR0_DIRQ6F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR0.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetDPSIFR0_DIRQ7F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR0.Reg, volatile.LoadUint8(&o.DPSIFR0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetDPSIFR0_DIRQ7F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR0.Reg) & 0x80) >> 7
}

// SYSC.DPSIFR1: Deep Standby Interrupt Flag Register 1
func (o *SYSC_Type) SetDPSIFR1_DIRQ8F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR1.Reg, volatile.LoadUint8(&o.DPSIFR1.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIFR1_DIRQ8F() uint8 {
	return volatile.LoadUint8(&o.DPSIFR1.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIFR1_DIRQ9F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR1.Reg, volatile.LoadUint8(&o.DPSIFR1.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIFR1_DIRQ9F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR1.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIFR1_DIRQ10F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR1.Reg, volatile.LoadUint8(&o.DPSIFR1.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetDPSIFR1_DIRQ10F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR1.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetDPSIFR1_DIRQ11F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR1.Reg, volatile.LoadUint8(&o.DPSIFR1.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetDPSIFR1_DIRQ11F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR1.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetDPSIFR1_DIRQ12F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR1.Reg, volatile.LoadUint8(&o.DPSIFR1.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIFR1_DIRQ12F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR1.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetDPSIFR1_DIRQ14F(value uint8) {
	volatile.StoreUint8(&o.DPSIFR1.Reg, volatile.LoadUint8(&o.DPSIFR1.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPSIFR1_DIRQ14F() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR1.Reg) & 0x40) >> 6
}

// SYSC.DPSIFR2: Deep Software Standby Interrupt Flag Register 2
func (o *SYSC_Type) SetDPSIFR2_DLVD1IF(value uint8) {
	volatile.StoreUint8(&o.DPSIFR2.Reg, volatile.LoadUint8(&o.DPSIFR2.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIFR2_DLVD1IF() uint8 {
	return volatile.LoadUint8(&o.DPSIFR2.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIFR2_DLVD2IF(value uint8) {
	volatile.StoreUint8(&o.DPSIFR2.Reg, volatile.LoadUint8(&o.DPSIFR2.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIFR2_DLVD2IF() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR2.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIFR2_DRTCIIF(value uint8) {
	volatile.StoreUint8(&o.DPSIFR2.Reg, volatile.LoadUint8(&o.DPSIFR2.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetDPSIFR2_DRTCIIF() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR2.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetDPSIFR2_DRTCAIF(value uint8) {
	volatile.StoreUint8(&o.DPSIFR2.Reg, volatile.LoadUint8(&o.DPSIFR2.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetDPSIFR2_DRTCAIF() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR2.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetDPSIFR2_DNMIF(value uint8) {
	volatile.StoreUint8(&o.DPSIFR2.Reg, volatile.LoadUint8(&o.DPSIFR2.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIFR2_DNMIF() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR2.Reg) & 0x10) >> 4
}

// SYSC.DPSIFR3: Deep Standby Interrupt Flag Register 3
func (o *SYSC_Type) SetDPSIFR3_DUSBFS0IF(value uint8) {
	volatile.StoreUint8(&o.DPSIFR3.Reg, volatile.LoadUint8(&o.DPSIFR3.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIFR3_DUSBFS0IF() uint8 {
	return volatile.LoadUint8(&o.DPSIFR3.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIFR3_DAGT1IF(value uint8) {
	volatile.StoreUint8(&o.DPSIFR3.Reg, volatile.LoadUint8(&o.DPSIFR3.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetDPSIFR3_DAGT1IF() uint8 {
	return (volatile.LoadUint8(&o.DPSIFR3.Reg) & 0x4) >> 2
}

// SYSC.DPSIEGR0: Deep Standby Interrupt Edge Register 0
func (o *SYSC_Type) SetDPSIEGR0_DIRQ0EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR0.Reg, volatile.LoadUint8(&o.DPSIEGR0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIEGR0_DIRQ0EG() uint8 {
	return volatile.LoadUint8(&o.DPSIEGR0.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIEGR0_DIRQ1EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR0.Reg, volatile.LoadUint8(&o.DPSIEGR0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIEGR0_DIRQ1EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIEGR0_DIRQ4EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR0.Reg, volatile.LoadUint8(&o.DPSIEGR0.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIEGR0_DIRQ4EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR0.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetDPSIEGR0_DIRQ5EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR0.Reg, volatile.LoadUint8(&o.DPSIEGR0.Reg)&^(0x20)|value<<5)
}
func (o *SYSC_Type) GetDPSIEGR0_DIRQ5EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR0.Reg) & 0x20) >> 5
}
func (o *SYSC_Type) SetDPSIEGR0_DIRQ6EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR0.Reg, volatile.LoadUint8(&o.DPSIEGR0.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPSIEGR0_DIRQ6EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR0.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetDPSIEGR0_DIRQ7EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR0.Reg, volatile.LoadUint8(&o.DPSIEGR0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetDPSIEGR0_DIRQ7EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR0.Reg) & 0x80) >> 7
}

// SYSC.DPSIEGR1: Deep Standby Interrupt Edge Register 1
func (o *SYSC_Type) SetDPSIEGR1_DIRQ8EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR1.Reg, volatile.LoadUint8(&o.DPSIEGR1.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIEGR1_DIRQ8EG() uint8 {
	return volatile.LoadUint8(&o.DPSIEGR1.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIEGR1_DIRQ9EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR1.Reg, volatile.LoadUint8(&o.DPSIEGR1.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIEGR1_DIRQ9EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR1.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIEGR1_DIRQ10EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR1.Reg, volatile.LoadUint8(&o.DPSIEGR1.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetDPSIEGR1_DIRQ10EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR1.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetDPSIEGR1_DIRQ11EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR1.Reg, volatile.LoadUint8(&o.DPSIEGR1.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetDPSIEGR1_DIRQ11EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR1.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetDPSIEGR1_DIRQ12EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR1.Reg, volatile.LoadUint8(&o.DPSIEGR1.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIEGR1_DIRQ12EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR1.Reg) & 0x10) >> 4
}
func (o *SYSC_Type) SetDPSIEGR1_DIRQ14EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR1.Reg, volatile.LoadUint8(&o.DPSIEGR1.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetDPSIEGR1_DIRQ14EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR1.Reg) & 0x40) >> 6
}

// SYSC.DPSIEGR2: Deep Software Standby Interrupt Edge Register 2
func (o *SYSC_Type) SetDPSIEGR2_DLVD1EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR2.Reg, volatile.LoadUint8(&o.DPSIEGR2.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetDPSIEGR2_DLVD1EG() uint8 {
	return volatile.LoadUint8(&o.DPSIEGR2.Reg) & 0x1
}
func (o *SYSC_Type) SetDPSIEGR2_DLVD2EG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR2.Reg, volatile.LoadUint8(&o.DPSIEGR2.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetDPSIEGR2_DLVD2EG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR2.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetDPSIEGR2_DNMIEG(value uint8) {
	volatile.StoreUint8(&o.DPSIEGR2.Reg, volatile.LoadUint8(&o.DPSIEGR2.Reg)&^(0x10)|value<<4)
}
func (o *SYSC_Type) GetDPSIEGR2_DNMIEG() uint8 {
	return (volatile.LoadUint8(&o.DPSIEGR2.Reg) & 0x10) >> 4
}

// SYSC.SYOCDCR: System Control OCD Control Register
func (o *SYSC_Type) SetSYOCDCR_DOCDF(value uint8) {
	volatile.StoreUint8(&o.SYOCDCR.Reg, volatile.LoadUint8(&o.SYOCDCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetSYOCDCR_DOCDF() uint8 {
	return volatile.LoadUint8(&o.SYOCDCR.Reg) & 0x1
}
func (o *SYSC_Type) SetSYOCDCR_DBGEN(value uint8) {
	volatile.StoreUint8(&o.SYOCDCR.Reg, volatile.LoadUint8(&o.SYOCDCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetSYOCDCR_DBGEN() uint8 {
	return (volatile.LoadUint8(&o.SYOCDCR.Reg) & 0x80) >> 7
}

// SYSC.RSTSR0: Reset Status Register 0
func (o *SYSC_Type) SetRSTSR0_PORF(value uint8) {
	volatile.StoreUint8(&o.RSTSR0.Reg, volatile.LoadUint8(&o.RSTSR0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetRSTSR0_PORF() uint8 {
	return volatile.LoadUint8(&o.RSTSR0.Reg) & 0x1
}
func (o *SYSC_Type) SetRSTSR0_LVD0RF(value uint8) {
	volatile.StoreUint8(&o.RSTSR0.Reg, volatile.LoadUint8(&o.RSTSR0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetRSTSR0_LVD0RF() uint8 {
	return (volatile.LoadUint8(&o.RSTSR0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetRSTSR0_LVD1RF(value uint8) {
	volatile.StoreUint8(&o.RSTSR0.Reg, volatile.LoadUint8(&o.RSTSR0.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetRSTSR0_LVD1RF() uint8 {
	return (volatile.LoadUint8(&o.RSTSR0.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetRSTSR0_LVD2RF(value uint8) {
	volatile.StoreUint8(&o.RSTSR0.Reg, volatile.LoadUint8(&o.RSTSR0.Reg)&^(0x8)|value<<3)
}
func (o *SYSC_Type) GetRSTSR0_LVD2RF() uint8 {
	return (volatile.LoadUint8(&o.RSTSR0.Reg) & 0x8) >> 3
}
func (o *SYSC_Type) SetRSTSR0_DPSRSTF(value uint8) {
	volatile.StoreUint8(&o.RSTSR0.Reg, volatile.LoadUint8(&o.RSTSR0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetRSTSR0_DPSRSTF() uint8 {
	return (volatile.LoadUint8(&o.RSTSR0.Reg) & 0x80) >> 7
}

// SYSC.RSTSR2: Reset Status Register 2
func (o *SYSC_Type) SetRSTSR2_CWSF(value uint8) {
	volatile.StoreUint8(&o.RSTSR2.Reg, volatile.LoadUint8(&o.RSTSR2.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetRSTSR2_CWSF() uint8 {
	return volatile.LoadUint8(&o.RSTSR2.Reg) & 0x1
}

// SYSC.MOMCR: Main Clock Oscillator Mode Oscillation Control Register
func (o *SYSC_Type) SetMOMCR_MODRV(value uint8) {
	volatile.StoreUint8(&o.MOMCR.Reg, volatile.LoadUint8(&o.MOMCR.Reg)&^(0x30)|value<<4)
}
func (o *SYSC_Type) GetMOMCR_MODRV() uint8 {
	return (volatile.LoadUint8(&o.MOMCR.Reg) & 0x30) >> 4
}
func (o *SYSC_Type) SetMOMCR_MOSEL(value uint8) {
	volatile.StoreUint8(&o.MOMCR.Reg, volatile.LoadUint8(&o.MOMCR.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetMOMCR_MOSEL() uint8 {
	return (volatile.LoadUint8(&o.MOMCR.Reg) & 0x40) >> 6
}

// SYSC.FWEPROR: Flash P/E Protect Register
func (o *SYSC_Type) SetFWEPROR_FLWE(value uint8) {
	volatile.StoreUint8(&o.FWEPROR.Reg, volatile.LoadUint8(&o.FWEPROR.Reg)&^(0x3)|value)
}
func (o *SYSC_Type) GetFWEPROR_FLWE() uint8 {
	return volatile.LoadUint8(&o.FWEPROR.Reg) & 0x3
}

// SYSC.LVD1CMPCR: Voltage Monitoring 1 Comparator Control Register
func (o *SYSC_Type) SetLVD1CMPCR_LVD1LVL(value uint8) {
	volatile.StoreUint8(&o.LVD1CMPCR.Reg, volatile.LoadUint8(&o.LVD1CMPCR.Reg)&^(0x1f)|value)
}
func (o *SYSC_Type) GetLVD1CMPCR_LVD1LVL() uint8 {
	return volatile.LoadUint8(&o.LVD1CMPCR.Reg) & 0x1f
}
func (o *SYSC_Type) SetLVD1CMPCR_LVD1E(value uint8) {
	volatile.StoreUint8(&o.LVD1CMPCR.Reg, volatile.LoadUint8(&o.LVD1CMPCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetLVD1CMPCR_LVD1E() uint8 {
	return (volatile.LoadUint8(&o.LVD1CMPCR.Reg) & 0x80) >> 7
}

// SYSC.LVD2CMPCR: Voltage Monitoring 2 Comparator Control Register
func (o *SYSC_Type) SetLVD2CMPCR_LVD2LVL(value uint8) {
	volatile.StoreUint8(&o.LVD2CMPCR.Reg, volatile.LoadUint8(&o.LVD2CMPCR.Reg)&^(0x7)|value)
}
func (o *SYSC_Type) GetLVD2CMPCR_LVD2LVL() uint8 {
	return volatile.LoadUint8(&o.LVD2CMPCR.Reg) & 0x7
}
func (o *SYSC_Type) SetLVD2CMPCR_LVD2E(value uint8) {
	volatile.StoreUint8(&o.LVD2CMPCR.Reg, volatile.LoadUint8(&o.LVD2CMPCR.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetLVD2CMPCR_LVD2E() uint8 {
	return (volatile.LoadUint8(&o.LVD2CMPCR.Reg) & 0x80) >> 7
}

// SYSC.LVD1CR0: Voltage Monitor 1 Circuit Control Register 0
func (o *SYSC_Type) SetLVD1CR0_RIE(value uint8) {
	volatile.StoreUint8(&o.LVD1CR0.Reg, volatile.LoadUint8(&o.LVD1CR0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetLVD1CR0_RIE() uint8 {
	return volatile.LoadUint8(&o.LVD1CR0.Reg) & 0x1
}
func (o *SYSC_Type) SetLVD1CR0_DFDIS(value uint8) {
	volatile.StoreUint8(&o.LVD1CR0.Reg, volatile.LoadUint8(&o.LVD1CR0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetLVD1CR0_DFDIS() uint8 {
	return (volatile.LoadUint8(&o.LVD1CR0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetLVD1CR0_CMPE(value uint8) {
	volatile.StoreUint8(&o.LVD1CR0.Reg, volatile.LoadUint8(&o.LVD1CR0.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetLVD1CR0_CMPE() uint8 {
	return (volatile.LoadUint8(&o.LVD1CR0.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetLVD1CR0_FSAMP(value uint8) {
	volatile.StoreUint8(&o.LVD1CR0.Reg, volatile.LoadUint8(&o.LVD1CR0.Reg)&^(0x30)|value<<4)
}
func (o *SYSC_Type) GetLVD1CR0_FSAMP() uint8 {
	return (volatile.LoadUint8(&o.LVD1CR0.Reg) & 0x30) >> 4
}
func (o *SYSC_Type) SetLVD1CR0_RI(value uint8) {
	volatile.StoreUint8(&o.LVD1CR0.Reg, volatile.LoadUint8(&o.LVD1CR0.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetLVD1CR0_RI() uint8 {
	return (volatile.LoadUint8(&o.LVD1CR0.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetLVD1CR0_RN(value uint8) {
	volatile.StoreUint8(&o.LVD1CR0.Reg, volatile.LoadUint8(&o.LVD1CR0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetLVD1CR0_RN() uint8 {
	return (volatile.LoadUint8(&o.LVD1CR0.Reg) & 0x80) >> 7
}

// SYSC.LVD2CR0: Voltage Monitor 2 Circuit Control Register 0
func (o *SYSC_Type) SetLVD2CR0_RIE(value uint8) {
	volatile.StoreUint8(&o.LVD2CR0.Reg, volatile.LoadUint8(&o.LVD2CR0.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetLVD2CR0_RIE() uint8 {
	return volatile.LoadUint8(&o.LVD2CR0.Reg) & 0x1
}
func (o *SYSC_Type) SetLVD2CR0_DFDIS(value uint8) {
	volatile.StoreUint8(&o.LVD2CR0.Reg, volatile.LoadUint8(&o.LVD2CR0.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetLVD2CR0_DFDIS() uint8 {
	return (volatile.LoadUint8(&o.LVD2CR0.Reg) & 0x2) >> 1
}
func (o *SYSC_Type) SetLVD2CR0_CMPE(value uint8) {
	volatile.StoreUint8(&o.LVD2CR0.Reg, volatile.LoadUint8(&o.LVD2CR0.Reg)&^(0x4)|value<<2)
}
func (o *SYSC_Type) GetLVD2CR0_CMPE() uint8 {
	return (volatile.LoadUint8(&o.LVD2CR0.Reg) & 0x4) >> 2
}
func (o *SYSC_Type) SetLVD2CR0_FSAMP(value uint8) {
	volatile.StoreUint8(&o.LVD2CR0.Reg, volatile.LoadUint8(&o.LVD2CR0.Reg)&^(0x30)|value<<4)
}
func (o *SYSC_Type) GetLVD2CR0_FSAMP() uint8 {
	return (volatile.LoadUint8(&o.LVD2CR0.Reg) & 0x30) >> 4
}
func (o *SYSC_Type) SetLVD2CR0_RI(value uint8) {
	volatile.StoreUint8(&o.LVD2CR0.Reg, volatile.LoadUint8(&o.LVD2CR0.Reg)&^(0x40)|value<<6)
}
func (o *SYSC_Type) GetLVD2CR0_RI() uint8 {
	return (volatile.LoadUint8(&o.LVD2CR0.Reg) & 0x40) >> 6
}
func (o *SYSC_Type) SetLVD2CR0_RN(value uint8) {
	volatile.StoreUint8(&o.LVD2CR0.Reg, volatile.LoadUint8(&o.LVD2CR0.Reg)&^(0x80)|value<<7)
}
func (o *SYSC_Type) GetLVD2CR0_RN() uint8 {
	return (volatile.LoadUint8(&o.LVD2CR0.Reg) & 0x80) >> 7
}

// SYSC.SOSCCR: Sub-Clock Oscillator Control Register
func (o *SYSC_Type) SetSOSCCR_SOSTP(value uint8) {
	volatile.StoreUint8(&o.SOSCCR.Reg, volatile.LoadUint8(&o.SOSCCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetSOSCCR_SOSTP() uint8 {
	return volatile.LoadUint8(&o.SOSCCR.Reg) & 0x1
}

// SYSC.SOMCR: Sub-Clock Oscillator Mode Control Register
func (o *SYSC_Type) SetSOMCR_SODRV(value uint8) {
	volatile.StoreUint8(&o.SOMCR.Reg, volatile.LoadUint8(&o.SOMCR.Reg)&^(0x2)|value<<1)
}
func (o *SYSC_Type) GetSOMCR_SODRV() uint8 {
	return (volatile.LoadUint8(&o.SOMCR.Reg) & 0x2) >> 1
}

// SYSC.LOCOCR: Low-Speed On-Chip Oscillator Control Register
func (o *SYSC_Type) SetLOCOCR_LCSTP(value uint8) {
	volatile.StoreUint8(&o.LOCOCR.Reg, volatile.LoadUint8(&o.LOCOCR.Reg)&^(0x1)|value)
}
func (o *SYSC_Type) GetLOCOCR_LCSTP() uint8 {
	return volatile.LoadUint8(&o.LOCOCR.Reg) & 0x1
}

// SYSC.LOCOUTCR: LOCO User Trimming Control Register
func (o *SYSC_Type) SetLOCOUTCR(value uint8) {
	volatile.StoreUint8(&o.LOCOUTCR.Reg, value)
}
func (o *SYSC_Type) GetLOCOUTCR() uint8 {
	return volatile.LoadUint8(&o.LOCOUTCR.Reg)
}

// Pmn Pin FunctionPort 0 Control RegistersPmn Pin Function Control Register
type PORT0_Type struct {
	PCNTR1 volatile.Register32 // 0x0
	PCNTR2 volatile.Register32 // 0x4
	PCNTR3 volatile.Register32 // 0x8
}

// PORT0.PCNTR1: Port Control Register 1
func (o *PORT0_Type) SetPCNTR1_PDR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x1)|value)
}
func (o *PORT0_Type) GetPCNTR1_PDR00() uint32 {
	return volatile.LoadUint32(&o.PCNTR1.Reg) & 0x1
}
func (o *PORT0_Type) SetPCNTR1_PDR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x2)|value<<1)
}
func (o *PORT0_Type) GetPCNTR1_PDR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x2) >> 1
}
func (o *PORT0_Type) SetPCNTR1_PDR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x4)|value<<2)
}
func (o *PORT0_Type) GetPCNTR1_PDR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x4) >> 2
}
func (o *PORT0_Type) SetPCNTR1_PDR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x8)|value<<3)
}
func (o *PORT0_Type) GetPCNTR1_PDR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x8) >> 3
}
func (o *PORT0_Type) SetPCNTR1_PDR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x10)|value<<4)
}
func (o *PORT0_Type) GetPCNTR1_PDR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x10) >> 4
}
func (o *PORT0_Type) SetPCNTR1_PDR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x20)|value<<5)
}
func (o *PORT0_Type) GetPCNTR1_PDR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x20) >> 5
}
func (o *PORT0_Type) SetPCNTR1_PDR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x40)|value<<6)
}
func (o *PORT0_Type) GetPCNTR1_PDR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x40) >> 6
}
func (o *PORT0_Type) SetPCNTR1_PDR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x80)|value<<7)
}
func (o *PORT0_Type) GetPCNTR1_PDR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x80) >> 7
}
func (o *PORT0_Type) SetPCNTR1_PDR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x100)|value<<8)
}
func (o *PORT0_Type) GetPCNTR1_PDR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x100) >> 8
}
func (o *PORT0_Type) SetPCNTR1_PDR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x200)|value<<9)
}
func (o *PORT0_Type) GetPCNTR1_PDR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x200) >> 9
}
func (o *PORT0_Type) SetPCNTR1_PDR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x400)|value<<10)
}
func (o *PORT0_Type) GetPCNTR1_PDR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x400) >> 10
}
func (o *PORT0_Type) SetPCNTR1_PDR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x800)|value<<11)
}
func (o *PORT0_Type) GetPCNTR1_PDR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x800) >> 11
}
func (o *PORT0_Type) SetPCNTR1_PDR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x1000)|value<<12)
}
func (o *PORT0_Type) GetPCNTR1_PDR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x1000) >> 12
}
func (o *PORT0_Type) SetPCNTR1_PDR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x2000)|value<<13)
}
func (o *PORT0_Type) GetPCNTR1_PDR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x2000) >> 13
}
func (o *PORT0_Type) SetPCNTR1_PDR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x4000)|value<<14)
}
func (o *PORT0_Type) GetPCNTR1_PDR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x4000) >> 14
}
func (o *PORT0_Type) SetPCNTR1_PDR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x8000)|value<<15)
}
func (o *PORT0_Type) GetPCNTR1_PDR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x8000) >> 15
}
func (o *PORT0_Type) SetPCNTR1_PODR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x10000)|value<<16)
}
func (o *PORT0_Type) GetPCNTR1_PODR00() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x10000) >> 16
}
func (o *PORT0_Type) SetPCNTR1_PODR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x20000)|value<<17)
}
func (o *PORT0_Type) GetPCNTR1_PODR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x20000) >> 17
}
func (o *PORT0_Type) SetPCNTR1_PODR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x40000)|value<<18)
}
func (o *PORT0_Type) GetPCNTR1_PODR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x40000) >> 18
}
func (o *PORT0_Type) SetPCNTR1_PODR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x80000)|value<<19)
}
func (o *PORT0_Type) GetPCNTR1_PODR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x80000) >> 19
}
func (o *PORT0_Type) SetPCNTR1_PODR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x100000)|value<<20)
}
func (o *PORT0_Type) GetPCNTR1_PODR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x100000) >> 20
}
func (o *PORT0_Type) SetPCNTR1_PODR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x200000)|value<<21)
}
func (o *PORT0_Type) GetPCNTR1_PODR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x200000) >> 21
}
func (o *PORT0_Type) SetPCNTR1_PODR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x400000)|value<<22)
}
func (o *PORT0_Type) GetPCNTR1_PODR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x400000) >> 22
}
func (o *PORT0_Type) SetPCNTR1_PODR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x800000)|value<<23)
}
func (o *PORT0_Type) GetPCNTR1_PODR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x800000) >> 23
}
func (o *PORT0_Type) SetPCNTR1_PODR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x1000000)|value<<24)
}
func (o *PORT0_Type) GetPCNTR1_PODR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x1000000) >> 24
}
func (o *PORT0_Type) SetPCNTR1_PODR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x2000000)|value<<25)
}
func (o *PORT0_Type) GetPCNTR1_PODR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x2000000) >> 25
}
func (o *PORT0_Type) SetPCNTR1_PODR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x4000000)|value<<26)
}
func (o *PORT0_Type) GetPCNTR1_PODR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x4000000) >> 26
}
func (o *PORT0_Type) SetPCNTR1_PODR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x8000000)|value<<27)
}
func (o *PORT0_Type) GetPCNTR1_PODR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x8000000) >> 27
}
func (o *PORT0_Type) SetPCNTR1_PODR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x10000000)|value<<28)
}
func (o *PORT0_Type) GetPCNTR1_PODR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x10000000) >> 28
}
func (o *PORT0_Type) SetPCNTR1_PODR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x20000000)|value<<29)
}
func (o *PORT0_Type) GetPCNTR1_PODR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x20000000) >> 29
}
func (o *PORT0_Type) SetPCNTR1_PODR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x40000000)|value<<30)
}
func (o *PORT0_Type) GetPCNTR1_PODR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x40000000) >> 30
}
func (o *PORT0_Type) SetPCNTR1_PODR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x80000000)|value<<31)
}
func (o *PORT0_Type) GetPCNTR1_PODR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x80000000) >> 31
}

// PORT0.PCNTR2: Port Control Register 2
func (o *PORT0_Type) SetPCNTR2_PIDR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x1)|value)
}
func (o *PORT0_Type) GetPCNTR2_PIDR00() uint32 {
	return volatile.LoadUint32(&o.PCNTR2.Reg) & 0x1
}
func (o *PORT0_Type) SetPCNTR2_PIDR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x2)|value<<1)
}
func (o *PORT0_Type) GetPCNTR2_PIDR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x2) >> 1
}
func (o *PORT0_Type) SetPCNTR2_PIDR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x4)|value<<2)
}
func (o *PORT0_Type) GetPCNTR2_PIDR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x4) >> 2
}
func (o *PORT0_Type) SetPCNTR2_PIDR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x8)|value<<3)
}
func (o *PORT0_Type) GetPCNTR2_PIDR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x8) >> 3
}
func (o *PORT0_Type) SetPCNTR2_PIDR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x10)|value<<4)
}
func (o *PORT0_Type) GetPCNTR2_PIDR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x10) >> 4
}
func (o *PORT0_Type) SetPCNTR2_PIDR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x20)|value<<5)
}
func (o *PORT0_Type) GetPCNTR2_PIDR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x20) >> 5
}
func (o *PORT0_Type) SetPCNTR2_PIDR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x40)|value<<6)
}
func (o *PORT0_Type) GetPCNTR2_PIDR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x40) >> 6
}
func (o *PORT0_Type) SetPCNTR2_PIDR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x80)|value<<7)
}
func (o *PORT0_Type) GetPCNTR2_PIDR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x80) >> 7
}
func (o *PORT0_Type) SetPCNTR2_PIDR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x100)|value<<8)
}
func (o *PORT0_Type) GetPCNTR2_PIDR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x100) >> 8
}
func (o *PORT0_Type) SetPCNTR2_PIDR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x200)|value<<9)
}
func (o *PORT0_Type) GetPCNTR2_PIDR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x200) >> 9
}
func (o *PORT0_Type) SetPCNTR2_PIDR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x400)|value<<10)
}
func (o *PORT0_Type) GetPCNTR2_PIDR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x400) >> 10
}
func (o *PORT0_Type) SetPCNTR2_PIDR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x800)|value<<11)
}
func (o *PORT0_Type) GetPCNTR2_PIDR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x800) >> 11
}
func (o *PORT0_Type) SetPCNTR2_PIDR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x1000)|value<<12)
}
func (o *PORT0_Type) GetPCNTR2_PIDR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x1000) >> 12
}
func (o *PORT0_Type) SetPCNTR2_PIDR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x2000)|value<<13)
}
func (o *PORT0_Type) GetPCNTR2_PIDR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x2000) >> 13
}
func (o *PORT0_Type) SetPCNTR2_PIDR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x4000)|value<<14)
}
func (o *PORT0_Type) GetPCNTR2_PIDR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x4000) >> 14
}
func (o *PORT0_Type) SetPCNTR2_PIDR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x8000)|value<<15)
}
func (o *PORT0_Type) GetPCNTR2_PIDR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x8000) >> 15
}

// PORT0.PCNTR3: Port Control Register 3
func (o *PORT0_Type) SetPCNTR3_POSR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x1)|value)
}
func (o *PORT0_Type) GetPCNTR3_POSR00() uint32 {
	return volatile.LoadUint32(&o.PCNTR3.Reg) & 0x1
}
func (o *PORT0_Type) SetPCNTR3_POSR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x2)|value<<1)
}
func (o *PORT0_Type) GetPCNTR3_POSR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x2) >> 1
}
func (o *PORT0_Type) SetPCNTR3_POSR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x4)|value<<2)
}
func (o *PORT0_Type) GetPCNTR3_POSR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x4) >> 2
}
func (o *PORT0_Type) SetPCNTR3_POSR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x8)|value<<3)
}
func (o *PORT0_Type) GetPCNTR3_POSR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x8) >> 3
}
func (o *PORT0_Type) SetPCNTR3_POSR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x10)|value<<4)
}
func (o *PORT0_Type) GetPCNTR3_POSR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x10) >> 4
}
func (o *PORT0_Type) SetPCNTR3_POSR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x20)|value<<5)
}
func (o *PORT0_Type) GetPCNTR3_POSR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x20) >> 5
}
func (o *PORT0_Type) SetPCNTR3_POSR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x40)|value<<6)
}
func (o *PORT0_Type) GetPCNTR3_POSR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x40) >> 6
}
func (o *PORT0_Type) SetPCNTR3_POSR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x80)|value<<7)
}
func (o *PORT0_Type) GetPCNTR3_POSR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x80) >> 7
}
func (o *PORT0_Type) SetPCNTR3_POSR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x100)|value<<8)
}
func (o *PORT0_Type) GetPCNTR3_POSR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x100) >> 8
}
func (o *PORT0_Type) SetPCNTR3_POSR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x200)|value<<9)
}
func (o *PORT0_Type) GetPCNTR3_POSR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x200) >> 9
}
func (o *PORT0_Type) SetPCNTR3_POSR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x400)|value<<10)
}
func (o *PORT0_Type) GetPCNTR3_POSR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x400) >> 10
}
func (o *PORT0_Type) SetPCNTR3_POSR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x800)|value<<11)
}
func (o *PORT0_Type) GetPCNTR3_POSR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x800) >> 11
}
func (o *PORT0_Type) SetPCNTR3_POSR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x1000)|value<<12)
}
func (o *PORT0_Type) GetPCNTR3_POSR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x1000) >> 12
}
func (o *PORT0_Type) SetPCNTR3_POSR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x2000)|value<<13)
}
func (o *PORT0_Type) GetPCNTR3_POSR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x2000) >> 13
}
func (o *PORT0_Type) SetPCNTR3_POSR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x4000)|value<<14)
}
func (o *PORT0_Type) GetPCNTR3_POSR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x4000) >> 14
}
func (o *PORT0_Type) SetPCNTR3_POSR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x8000)|value<<15)
}
func (o *PORT0_Type) GetPCNTR3_POSR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x8000) >> 15
}
func (o *PORT0_Type) SetPCNTR3_PORR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x10000)|value<<16)
}
func (o *PORT0_Type) GetPCNTR3_PORR00() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x10000) >> 16
}
func (o *PORT0_Type) SetPCNTR3_PORR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x20000)|value<<17)
}
func (o *PORT0_Type) GetPCNTR3_PORR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x20000) >> 17
}
func (o *PORT0_Type) SetPCNTR3_PORR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x40000)|value<<18)
}
func (o *PORT0_Type) GetPCNTR3_PORR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x40000) >> 18
}
func (o *PORT0_Type) SetPCNTR3_PORR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x80000)|value<<19)
}
func (o *PORT0_Type) GetPCNTR3_PORR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x80000) >> 19
}
func (o *PORT0_Type) SetPCNTR3_PORR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x100000)|value<<20)
}
func (o *PORT0_Type) GetPCNTR3_PORR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x100000) >> 20
}
func (o *PORT0_Type) SetPCNTR3_PORR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x200000)|value<<21)
}
func (o *PORT0_Type) GetPCNTR3_PORR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x200000) >> 21
}
func (o *PORT0_Type) SetPCNTR3_PORR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x400000)|value<<22)
}
func (o *PORT0_Type) GetPCNTR3_PORR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x400000) >> 22
}
func (o *PORT0_Type) SetPCNTR3_PORR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x800000)|value<<23)
}
func (o *PORT0_Type) GetPCNTR3_PORR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x800000) >> 23
}
func (o *PORT0_Type) SetPCNTR3_PORR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x1000000)|value<<24)
}
func (o *PORT0_Type) GetPCNTR3_PORR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x1000000) >> 24
}
func (o *PORT0_Type) SetPCNTR3_PORR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x2000000)|value<<25)
}
func (o *PORT0_Type) GetPCNTR3_PORR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x2000000) >> 25
}
func (o *PORT0_Type) SetPCNTR3_PORR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x4000000)|value<<26)
}
func (o *PORT0_Type) GetPCNTR3_PORR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x4000000) >> 26
}
func (o *PORT0_Type) SetPCNTR3_PORR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x8000000)|value<<27)
}
func (o *PORT0_Type) GetPCNTR3_PORR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x8000000) >> 27
}
func (o *PORT0_Type) SetPCNTR3_PORR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x10000000)|value<<28)
}
func (o *PORT0_Type) GetPCNTR3_PORR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x10000000) >> 28
}
func (o *PORT0_Type) SetPCNTR3_PORR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x20000000)|value<<29)
}
func (o *PORT0_Type) GetPCNTR3_PORR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x20000000) >> 29
}
func (o *PORT0_Type) SetPCNTR3_PORR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x40000000)|value<<30)
}
func (o *PORT0_Type) GetPCNTR3_PORR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x40000000) >> 30
}
func (o *PORT0_Type) SetPCNTR3_PORR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x80000000)|value<<31)
}
func (o *PORT0_Type) GetPCNTR3_PORR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x80000000) >> 31
}

// Pmn Pin FunctionPort 1 Control RegistersPmn Pin Function Control Register
type PORT1_Type struct {
	PCNTR1 volatile.Register32 // 0x0
	PCNTR2 volatile.Register32 // 0x4
	PCNTR3 volatile.Register32 // 0x8
	PCNTR4 volatile.Register32 // 0xC
}

// PORT1.PCNTR1: Port Control Register 1
func (o *PORT1_Type) SetPCNTR1_PDR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x1)|value)
}
func (o *PORT1_Type) GetPCNTR1_PDR00() uint32 {
	return volatile.LoadUint32(&o.PCNTR1.Reg) & 0x1
}
func (o *PORT1_Type) SetPCNTR1_PDR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x2)|value<<1)
}
func (o *PORT1_Type) GetPCNTR1_PDR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x2) >> 1
}
func (o *PORT1_Type) SetPCNTR1_PDR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x4)|value<<2)
}
func (o *PORT1_Type) GetPCNTR1_PDR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x4) >> 2
}
func (o *PORT1_Type) SetPCNTR1_PDR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x8)|value<<3)
}
func (o *PORT1_Type) GetPCNTR1_PDR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x8) >> 3
}
func (o *PORT1_Type) SetPCNTR1_PDR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x10)|value<<4)
}
func (o *PORT1_Type) GetPCNTR1_PDR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x10) >> 4
}
func (o *PORT1_Type) SetPCNTR1_PDR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x20)|value<<5)
}
func (o *PORT1_Type) GetPCNTR1_PDR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x20) >> 5
}
func (o *PORT1_Type) SetPCNTR1_PDR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x40)|value<<6)
}
func (o *PORT1_Type) GetPCNTR1_PDR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x40) >> 6
}
func (o *PORT1_Type) SetPCNTR1_PDR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x80)|value<<7)
}
func (o *PORT1_Type) GetPCNTR1_PDR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x80) >> 7
}
func (o *PORT1_Type) SetPCNTR1_PDR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x100)|value<<8)
}
func (o *PORT1_Type) GetPCNTR1_PDR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x100) >> 8
}
func (o *PORT1_Type) SetPCNTR1_PDR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x200)|value<<9)
}
func (o *PORT1_Type) GetPCNTR1_PDR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x200) >> 9
}
func (o *PORT1_Type) SetPCNTR1_PDR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x400)|value<<10)
}
func (o *PORT1_Type) GetPCNTR1_PDR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x400) >> 10
}
func (o *PORT1_Type) SetPCNTR1_PDR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x800)|value<<11)
}
func (o *PORT1_Type) GetPCNTR1_PDR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x800) >> 11
}
func (o *PORT1_Type) SetPCNTR1_PDR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x1000)|value<<12)
}
func (o *PORT1_Type) GetPCNTR1_PDR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x1000) >> 12
}
func (o *PORT1_Type) SetPCNTR1_PDR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x2000)|value<<13)
}
func (o *PORT1_Type) GetPCNTR1_PDR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x2000) >> 13
}
func (o *PORT1_Type) SetPCNTR1_PDR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x4000)|value<<14)
}
func (o *PORT1_Type) GetPCNTR1_PDR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x4000) >> 14
}
func (o *PORT1_Type) SetPCNTR1_PDR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x8000)|value<<15)
}
func (o *PORT1_Type) GetPCNTR1_PDR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x8000) >> 15
}
func (o *PORT1_Type) SetPCNTR1_PODR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x10000)|value<<16)
}
func (o *PORT1_Type) GetPCNTR1_PODR00() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x10000) >> 16
}
func (o *PORT1_Type) SetPCNTR1_PODR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x20000)|value<<17)
}
func (o *PORT1_Type) GetPCNTR1_PODR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x20000) >> 17
}
func (o *PORT1_Type) SetPCNTR1_PODR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x40000)|value<<18)
}
func (o *PORT1_Type) GetPCNTR1_PODR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x40000) >> 18
}
func (o *PORT1_Type) SetPCNTR1_PODR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x80000)|value<<19)
}
func (o *PORT1_Type) GetPCNTR1_PODR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x80000) >> 19
}
func (o *PORT1_Type) SetPCNTR1_PODR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x100000)|value<<20)
}
func (o *PORT1_Type) GetPCNTR1_PODR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x100000) >> 20
}
func (o *PORT1_Type) SetPCNTR1_PODR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x200000)|value<<21)
}
func (o *PORT1_Type) GetPCNTR1_PODR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x200000) >> 21
}
func (o *PORT1_Type) SetPCNTR1_PODR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x400000)|value<<22)
}
func (o *PORT1_Type) GetPCNTR1_PODR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x400000) >> 22
}
func (o *PORT1_Type) SetPCNTR1_PODR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x800000)|value<<23)
}
func (o *PORT1_Type) GetPCNTR1_PODR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x800000) >> 23
}
func (o *PORT1_Type) SetPCNTR1_PODR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x1000000)|value<<24)
}
func (o *PORT1_Type) GetPCNTR1_PODR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x1000000) >> 24
}
func (o *PORT1_Type) SetPCNTR1_PODR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x2000000)|value<<25)
}
func (o *PORT1_Type) GetPCNTR1_PODR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x2000000) >> 25
}
func (o *PORT1_Type) SetPCNTR1_PODR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x4000000)|value<<26)
}
func (o *PORT1_Type) GetPCNTR1_PODR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x4000000) >> 26
}
func (o *PORT1_Type) SetPCNTR1_PODR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x8000000)|value<<27)
}
func (o *PORT1_Type) GetPCNTR1_PODR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x8000000) >> 27
}
func (o *PORT1_Type) SetPCNTR1_PODR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x10000000)|value<<28)
}
func (o *PORT1_Type) GetPCNTR1_PODR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x10000000) >> 28
}
func (o *PORT1_Type) SetPCNTR1_PODR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x20000000)|value<<29)
}
func (o *PORT1_Type) GetPCNTR1_PODR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x20000000) >> 29
}
func (o *PORT1_Type) SetPCNTR1_PODR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x40000000)|value<<30)
}
func (o *PORT1_Type) GetPCNTR1_PODR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x40000000) >> 30
}
func (o *PORT1_Type) SetPCNTR1_PODR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR1.Reg, volatile.LoadUint32(&o.PCNTR1.Reg)&^(0x80000000)|value<<31)
}
func (o *PORT1_Type) GetPCNTR1_PODR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR1.Reg) & 0x80000000) >> 31
}

// PORT1.PCNTR2: Port Control Register 2
func (o *PORT1_Type) SetPCNTR2_PIDR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x1)|value)
}
func (o *PORT1_Type) GetPCNTR2_PIDR00() uint32 {
	return volatile.LoadUint32(&o.PCNTR2.Reg) & 0x1
}
func (o *PORT1_Type) SetPCNTR2_PIDR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x2)|value<<1)
}
func (o *PORT1_Type) GetPCNTR2_PIDR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x2) >> 1
}
func (o *PORT1_Type) SetPCNTR2_PIDR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x4)|value<<2)
}
func (o *PORT1_Type) GetPCNTR2_PIDR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x4) >> 2
}
func (o *PORT1_Type) SetPCNTR2_PIDR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x8)|value<<3)
}
func (o *PORT1_Type) GetPCNTR2_PIDR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x8) >> 3
}
func (o *PORT1_Type) SetPCNTR2_PIDR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x10)|value<<4)
}
func (o *PORT1_Type) GetPCNTR2_PIDR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x10) >> 4
}
func (o *PORT1_Type) SetPCNTR2_PIDR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x20)|value<<5)
}
func (o *PORT1_Type) GetPCNTR2_PIDR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x20) >> 5
}
func (o *PORT1_Type) SetPCNTR2_PIDR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x40)|value<<6)
}
func (o *PORT1_Type) GetPCNTR2_PIDR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x40) >> 6
}
func (o *PORT1_Type) SetPCNTR2_PIDR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x80)|value<<7)
}
func (o *PORT1_Type) GetPCNTR2_PIDR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x80) >> 7
}
func (o *PORT1_Type) SetPCNTR2_PIDR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x100)|value<<8)
}
func (o *PORT1_Type) GetPCNTR2_PIDR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x100) >> 8
}
func (o *PORT1_Type) SetPCNTR2_PIDR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x200)|value<<9)
}
func (o *PORT1_Type) GetPCNTR2_PIDR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x200) >> 9
}
func (o *PORT1_Type) SetPCNTR2_PIDR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x400)|value<<10)
}
func (o *PORT1_Type) GetPCNTR2_PIDR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x400) >> 10
}
func (o *PORT1_Type) SetPCNTR2_PIDR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x800)|value<<11)
}
func (o *PORT1_Type) GetPCNTR2_PIDR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x800) >> 11
}
func (o *PORT1_Type) SetPCNTR2_PIDR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x1000)|value<<12)
}
func (o *PORT1_Type) GetPCNTR2_PIDR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x1000) >> 12
}
func (o *PORT1_Type) SetPCNTR2_PIDR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x2000)|value<<13)
}
func (o *PORT1_Type) GetPCNTR2_PIDR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x2000) >> 13
}
func (o *PORT1_Type) SetPCNTR2_PIDR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x4000)|value<<14)
}
func (o *PORT1_Type) GetPCNTR2_PIDR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x4000) >> 14
}
func (o *PORT1_Type) SetPCNTR2_PIDR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x8000)|value<<15)
}
func (o *PORT1_Type) GetPCNTR2_PIDR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x8000) >> 15
}
func (o *PORT1_Type) SetPCNTR2_EIDR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x10000)|value<<16)
}
func (o *PORT1_Type) GetPCNTR2_EIDR00() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x10000) >> 16
}
func (o *PORT1_Type) SetPCNTR2_EIDR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x20000)|value<<17)
}
func (o *PORT1_Type) GetPCNTR2_EIDR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x20000) >> 17
}
func (o *PORT1_Type) SetPCNTR2_EIDR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x40000)|value<<18)
}
func (o *PORT1_Type) GetPCNTR2_EIDR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x40000) >> 18
}
func (o *PORT1_Type) SetPCNTR2_EIDR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x80000)|value<<19)
}
func (o *PORT1_Type) GetPCNTR2_EIDR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x80000) >> 19
}
func (o *PORT1_Type) SetPCNTR2_EIDR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x100000)|value<<20)
}
func (o *PORT1_Type) GetPCNTR2_EIDR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x100000) >> 20
}
func (o *PORT1_Type) SetPCNTR2_EIDR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x200000)|value<<21)
}
func (o *PORT1_Type) GetPCNTR2_EIDR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x200000) >> 21
}
func (o *PORT1_Type) SetPCNTR2_EIDR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x400000)|value<<22)
}
func (o *PORT1_Type) GetPCNTR2_EIDR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x400000) >> 22
}
func (o *PORT1_Type) SetPCNTR2_EIDR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x800000)|value<<23)
}
func (o *PORT1_Type) GetPCNTR2_EIDR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x800000) >> 23
}
func (o *PORT1_Type) SetPCNTR2_EIDR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x1000000)|value<<24)
}
func (o *PORT1_Type) GetPCNTR2_EIDR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x1000000) >> 24
}
func (o *PORT1_Type) SetPCNTR2_EIDR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x2000000)|value<<25)
}
func (o *PORT1_Type) GetPCNTR2_EIDR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x2000000) >> 25
}
func (o *PORT1_Type) SetPCNTR2_EIDR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x4000000)|value<<26)
}
func (o *PORT1_Type) GetPCNTR2_EIDR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x4000000) >> 26
}
func (o *PORT1_Type) SetPCNTR2_EIDR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x8000000)|value<<27)
}
func (o *PORT1_Type) GetPCNTR2_EIDR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x8000000) >> 27
}
func (o *PORT1_Type) SetPCNTR2_EIDR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x10000000)|value<<28)
}
func (o *PORT1_Type) GetPCNTR2_EIDR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x10000000) >> 28
}
func (o *PORT1_Type) SetPCNTR2_EIDR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x20000000)|value<<29)
}
func (o *PORT1_Type) GetPCNTR2_EIDR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x20000000) >> 29
}
func (o *PORT1_Type) SetPCNTR2_EIDR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x40000000)|value<<30)
}
func (o *PORT1_Type) GetPCNTR2_EIDR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x40000000) >> 30
}
func (o *PORT1_Type) SetPCNTR2_EIDR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR2.Reg, volatile.LoadUint32(&o.PCNTR2.Reg)&^(0x80000000)|value<<31)
}
func (o *PORT1_Type) GetPCNTR2_EIDR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR2.Reg) & 0x80000000) >> 31
}

// PORT1.PCNTR3: Port Control Register 3
func (o *PORT1_Type) SetPCNTR3_POSR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x1)|value)
}
func (o *PORT1_Type) GetPCNTR3_POSR00() uint32 {
	return volatile.LoadUint32(&o.PCNTR3.Reg) & 0x1
}
func (o *PORT1_Type) SetPCNTR3_POSR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x2)|value<<1)
}
func (o *PORT1_Type) GetPCNTR3_POSR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x2) >> 1
}
func (o *PORT1_Type) SetPCNTR3_POSR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x4)|value<<2)
}
func (o *PORT1_Type) GetPCNTR3_POSR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x4) >> 2
}
func (o *PORT1_Type) SetPCNTR3_POSR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x8)|value<<3)
}
func (o *PORT1_Type) GetPCNTR3_POSR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x8) >> 3
}
func (o *PORT1_Type) SetPCNTR3_POSR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x10)|value<<4)
}
func (o *PORT1_Type) GetPCNTR3_POSR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x10) >> 4
}
func (o *PORT1_Type) SetPCNTR3_POSR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x20)|value<<5)
}
func (o *PORT1_Type) GetPCNTR3_POSR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x20) >> 5
}
func (o *PORT1_Type) SetPCNTR3_POSR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x40)|value<<6)
}
func (o *PORT1_Type) GetPCNTR3_POSR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x40) >> 6
}
func (o *PORT1_Type) SetPCNTR3_POSR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x80)|value<<7)
}
func (o *PORT1_Type) GetPCNTR3_POSR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x80) >> 7
}
func (o *PORT1_Type) SetPCNTR3_POSR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x100)|value<<8)
}
func (o *PORT1_Type) GetPCNTR3_POSR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x100) >> 8
}
func (o *PORT1_Type) SetPCNTR3_POSR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x200)|value<<9)
}
func (o *PORT1_Type) GetPCNTR3_POSR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x200) >> 9
}
func (o *PORT1_Type) SetPCNTR3_POSR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x400)|value<<10)
}
func (o *PORT1_Type) GetPCNTR3_POSR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x400) >> 10
}
func (o *PORT1_Type) SetPCNTR3_POSR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x800)|value<<11)
}
func (o *PORT1_Type) GetPCNTR3_POSR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x800) >> 11
}
func (o *PORT1_Type) SetPCNTR3_POSR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x1000)|value<<12)
}
func (o *PORT1_Type) GetPCNTR3_POSR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x1000) >> 12
}
func (o *PORT1_Type) SetPCNTR3_POSR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x2000)|value<<13)
}
func (o *PORT1_Type) GetPCNTR3_POSR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x2000) >> 13
}
func (o *PORT1_Type) SetPCNTR3_POSR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x4000)|value<<14)
}
func (o *PORT1_Type) GetPCNTR3_POSR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x4000) >> 14
}
func (o *PORT1_Type) SetPCNTR3_POSR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x8000)|value<<15)
}
func (o *PORT1_Type) GetPCNTR3_POSR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x8000) >> 15
}
func (o *PORT1_Type) SetPCNTR3_PORR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x10000)|value<<16)
}
func (o *PORT1_Type) GetPCNTR3_PORR00() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x10000) >> 16
}
func (o *PORT1_Type) SetPCNTR3_PORR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x20000)|value<<17)
}
func (o *PORT1_Type) GetPCNTR3_PORR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x20000) >> 17
}
func (o *PORT1_Type) SetPCNTR3_PORR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x40000)|value<<18)
}
func (o *PORT1_Type) GetPCNTR3_PORR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x40000) >> 18
}
func (o *PORT1_Type) SetPCNTR3_PORR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x80000)|value<<19)
}
func (o *PORT1_Type) GetPCNTR3_PORR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x80000) >> 19
}
func (o *PORT1_Type) SetPCNTR3_PORR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x100000)|value<<20)
}
func (o *PORT1_Type) GetPCNTR3_PORR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x100000) >> 20
}
func (o *PORT1_Type) SetPCNTR3_PORR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x200000)|value<<21)
}
func (o *PORT1_Type) GetPCNTR3_PORR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x200000) >> 21
}
func (o *PORT1_Type) SetPCNTR3_PORR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x400000)|value<<22)
}
func (o *PORT1_Type) GetPCNTR3_PORR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x400000) >> 22
}
func (o *PORT1_Type) SetPCNTR3_PORR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x800000)|value<<23)
}
func (o *PORT1_Type) GetPCNTR3_PORR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x800000) >> 23
}
func (o *PORT1_Type) SetPCNTR3_PORR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x1000000)|value<<24)
}
func (o *PORT1_Type) GetPCNTR3_PORR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x1000000) >> 24
}
func (o *PORT1_Type) SetPCNTR3_PORR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x2000000)|value<<25)
}
func (o *PORT1_Type) GetPCNTR3_PORR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x2000000) >> 25
}
func (o *PORT1_Type) SetPCNTR3_PORR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x4000000)|value<<26)
}
func (o *PORT1_Type) GetPCNTR3_PORR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x4000000) >> 26
}
func (o *PORT1_Type) SetPCNTR3_PORR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x8000000)|value<<27)
}
func (o *PORT1_Type) GetPCNTR3_PORR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x8000000) >> 27
}
func (o *PORT1_Type) SetPCNTR3_PORR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x10000000)|value<<28)
}
func (o *PORT1_Type) GetPCNTR3_PORR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x10000000) >> 28
}
func (o *PORT1_Type) SetPCNTR3_PORR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x20000000)|value<<29)
}
func (o *PORT1_Type) GetPCNTR3_PORR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x20000000) >> 29
}
func (o *PORT1_Type) SetPCNTR3_PORR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x40000000)|value<<30)
}
func (o *PORT1_Type) GetPCNTR3_PORR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x40000000) >> 30
}
func (o *PORT1_Type) SetPCNTR3_PORR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR3.Reg, volatile.LoadUint32(&o.PCNTR3.Reg)&^(0x80000000)|value<<31)
}
func (o *PORT1_Type) GetPCNTR3_PORR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR3.Reg) & 0x80000000) >> 31
}

// PORT1.PCNTR4: Port Control Register 4
func (o *PORT1_Type) SetPCNTR4_EOSR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x1)|value)
}
func (o *PORT1_Type) GetPCNTR4_EOSR00() uint32 {
	return volatile.LoadUint32(&o.PCNTR4.Reg) & 0x1
}
func (o *PORT1_Type) SetPCNTR4_EOSR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x2)|value<<1)
}
func (o *PORT1_Type) GetPCNTR4_EOSR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x2) >> 1
}
func (o *PORT1_Type) SetPCNTR4_EOSR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x4)|value<<2)
}
func (o *PORT1_Type) GetPCNTR4_EOSR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x4) >> 2
}
func (o *PORT1_Type) SetPCNTR4_EOSR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x8)|value<<3)
}
func (o *PORT1_Type) GetPCNTR4_EOSR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x8) >> 3
}
func (o *PORT1_Type) SetPCNTR4_EOSR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x10)|value<<4)
}
func (o *PORT1_Type) GetPCNTR4_EOSR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x10) >> 4
}
func (o *PORT1_Type) SetPCNTR4_EOSR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x20)|value<<5)
}
func (o *PORT1_Type) GetPCNTR4_EOSR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x20) >> 5
}
func (o *PORT1_Type) SetPCNTR4_EOSR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x40)|value<<6)
}
func (o *PORT1_Type) GetPCNTR4_EOSR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x40) >> 6
}
func (o *PORT1_Type) SetPCNTR4_EOSR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x80)|value<<7)
}
func (o *PORT1_Type) GetPCNTR4_EOSR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x80) >> 7
}
func (o *PORT1_Type) SetPCNTR4_EOSR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x100)|value<<8)
}
func (o *PORT1_Type) GetPCNTR4_EOSR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x100) >> 8
}
func (o *PORT1_Type) SetPCNTR4_EOSR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x200)|value<<9)
}
func (o *PORT1_Type) GetPCNTR4_EOSR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x200) >> 9
}
func (o *PORT1_Type) SetPCNTR4_EOSR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x400)|value<<10)
}
func (o *PORT1_Type) GetPCNTR4_EOSR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x400) >> 10
}
func (o *PORT1_Type) SetPCNTR4_EOSR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x800)|value<<11)
}
func (o *PORT1_Type) GetPCNTR4_EOSR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x800) >> 11
}
func (o *PORT1_Type) SetPCNTR4_EOSR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x1000)|value<<12)
}
func (o *PORT1_Type) GetPCNTR4_EOSR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x1000) >> 12
}
func (o *PORT1_Type) SetPCNTR4_EOSR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x2000)|value<<13)
}
func (o *PORT1_Type) GetPCNTR4_EOSR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x2000) >> 13
}
func (o *PORT1_Type) SetPCNTR4_EOSR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x4000)|value<<14)
}
func (o *PORT1_Type) GetPCNTR4_EOSR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x4000) >> 14
}
func (o *PORT1_Type) SetPCNTR4_EOSR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x8000)|value<<15)
}
func (o *PORT1_Type) GetPCNTR4_EOSR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x8000) >> 15
}
func (o *PORT1_Type) SetPCNTR4_EORR00(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x10000)|value<<16)
}
func (o *PORT1_Type) GetPCNTR4_EORR00() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x10000) >> 16
}
func (o *PORT1_Type) SetPCNTR4_EORR01(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x20000)|value<<17)
}
func (o *PORT1_Type) GetPCNTR4_EORR01() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x20000) >> 17
}
func (o *PORT1_Type) SetPCNTR4_EORR02(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x40000)|value<<18)
}
func (o *PORT1_Type) GetPCNTR4_EORR02() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x40000) >> 18
}
func (o *PORT1_Type) SetPCNTR4_EORR03(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x80000)|value<<19)
}
func (o *PORT1_Type) GetPCNTR4_EORR03() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x80000) >> 19
}
func (o *PORT1_Type) SetPCNTR4_EORR04(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x100000)|value<<20)
}
func (o *PORT1_Type) GetPCNTR4_EORR04() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x100000) >> 20
}
func (o *PORT1_Type) SetPCNTR4_EORR05(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x200000)|value<<21)
}
func (o *PORT1_Type) GetPCNTR4_EORR05() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x200000) >> 21
}
func (o *PORT1_Type) SetPCNTR4_EORR06(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x400000)|value<<22)
}
func (o *PORT1_Type) GetPCNTR4_EORR06() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x400000) >> 22
}
func (o *PORT1_Type) SetPCNTR4_EORR07(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x800000)|value<<23)
}
func (o *PORT1_Type) GetPCNTR4_EORR07() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x800000) >> 23
}
func (o *PORT1_Type) SetPCNTR4_EORR08(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x1000000)|value<<24)
}
func (o *PORT1_Type) GetPCNTR4_EORR08() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x1000000) >> 24
}
func (o *PORT1_Type) SetPCNTR4_EORR09(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x2000000)|value<<25)
}
func (o *PORT1_Type) GetPCNTR4_EORR09() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x2000000) >> 25
}
func (o *PORT1_Type) SetPCNTR4_EORR10(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x4000000)|value<<26)
}
func (o *PORT1_Type) GetPCNTR4_EORR10() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x4000000) >> 26
}
func (o *PORT1_Type) SetPCNTR4_EORR11(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x8000000)|value<<27)
}
func (o *PORT1_Type) GetPCNTR4_EORR11() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x8000000) >> 27
}
func (o *PORT1_Type) SetPCNTR4_EORR12(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x10000000)|value<<28)
}
func (o *PORT1_Type) GetPCNTR4_EORR12() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x10000000) >> 28
}
func (o *PORT1_Type) SetPCNTR4_EORR13(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x20000000)|value<<29)
}
func (o *PORT1_Type) GetPCNTR4_EORR13() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x20000000) >> 29
}
func (o *PORT1_Type) SetPCNTR4_EORR14(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x40000000)|value<<30)
}
func (o *PORT1_Type) GetPCNTR4_EORR14() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x40000000) >> 30
}
func (o *PORT1_Type) SetPCNTR4_EORR15(value uint32) {
	volatile.StoreUint32(&o.PCNTR4.Reg, volatile.LoadUint32(&o.PCNTR4.Reg)&^(0x80000000)|value<<31)
}
func (o *PORT1_Type) GetPCNTR4_EORR15() uint32 {
	return (volatile.LoadUint32(&o.PCNTR4.Reg) & 0x80000000) >> 31
}

// Control Register
type PFS_Type struct {
	P000PFS  volatile.Register32 // 0x0
	P001PFS  volatile.Register32 // 0x4
	P002PFS  volatile.Register32 // 0x8
	P003PFS  volatile.Register32 // 0xC
	P004PFS  volatile.Register32 // 0x10
	P005PFS  volatile.Register32 // 0x14
	P006PFS  volatile.Register32 // 0x18
	_        [4]byte
	P008PFS  volatile.Register32 // 0x20
	_        [16]byte
	P013PFS  volatile.Register32 // 0x34
	P014PFS  volatile.Register32 // 0x38
	P015PFS  volatile.Register32 // 0x3C
	P100PFS  volatile.Register32 // 0x40
	P101PFS  volatile.Register32 // 0x44
	P102PFS  volatile.Register32 // 0x48
	P103PFS  volatile.Register32 // 0x4C
	P104PFS  volatile.Register32 // 0x50
	P105PFS  volatile.Register32 // 0x54
	P106PFS  volatile.Register32 // 0x58
	P107PFS  volatile.Register32 // 0x5C
	P108PFS  volatile.Register32 // 0x60
	P109PFS  volatile.Register32 // 0x64
	P110PFS  volatile.Register32 // 0x68
	P111PFS  volatile.Register32 // 0x6C
	P112PFS  volatile.Register32 // 0x70
	P113PFS  volatile.Register32 // 0x74
	_        [8]byte
	P200PFS  volatile.Register32 // 0x80
	P201PFS  volatile.Register32 // 0x84
	_        [12]byte
	P205PFS  volatile.Register32 // 0x94
	P206PFS  volatile.Register32 // 0x98
	P207PFS  volatile.Register32 // 0x9C
	P208PFS  volatile.Register32 // 0xA0
	_        [12]byte
	P212PFS  volatile.Register32 // 0xB0
	P213PFS  volatile.Register32 // 0xB4
	_        [8]byte
	P300PFS  volatile.Register32 // 0xC0
	P301PFS  volatile.Register32 // 0xC4
	P302PFS  volatile.Register32 // 0xC8
	P303PFS  volatile.Register32 // 0xCC
	P304PFS  volatile.Register32 // 0xD0
	_        [44]byte
	P400PFS  volatile.Register32 // 0x100
	P401PFS  volatile.Register32 // 0x104
	P402PFS  volatile.Register32 // 0x108
	P403PFS  volatile.Register32 // 0x10C
	_        [12]byte
	P407PFS  volatile.Register32 // 0x11C
	P408PFS  volatile.Register32 // 0x120
	P409PFS  volatile.Register32 // 0x124
	P410PFS  volatile.Register32 // 0x128
	P411PFS  volatile.Register32 // 0x12C
	_        [16]byte
	P500PFS  volatile.Register32 // 0x140
	_        [188]byte
	P8014PFS volatile.Register32 // 0x200
	P8015PFS volatile.Register32 // 0x204
	_        [763]byte
	PWPR     volatile.Register8 // 0x503
	_        byte
	PWPRS    volatile.Register8 // 0x505
	_        [6]byte
	PFI3C    volatile.Register8 // 0x50C
	_        [3]byte
	P0SAR    volatile.Register16 // 0x510
	P1SAR    volatile.Register16 // 0x512
	P2SAR    volatile.Register16 // 0x514
	P3SAR    volatile.Register16 // 0x516
	P4SAR    volatile.Register16 // 0x518
	P5SAR    volatile.Register16 // 0x51A
	_        [4]byte
	P8SAR    volatile.Register16 // 0x520
}

// PFS.P000PFS: Port 00%s Pin Function Select Register
func (o *PFS_Type) SetP000PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP000PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P000PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP000PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP000PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP000PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP000PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP000PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP000PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP000PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP000PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP000PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP000PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP000PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP000PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP000PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP000PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP000PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP000PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP000PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP000PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP000PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P000PFS.Reg, volatile.LoadUint32(&o.P000PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP000PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P000PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P001PFS: Port 00%s Pin Function Select Register
func (o *PFS_Type) SetP001PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP001PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P001PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP001PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP001PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP001PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP001PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP001PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP001PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP001PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP001PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP001PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP001PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP001PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP001PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP001PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP001PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP001PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP001PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP001PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP001PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP001PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P001PFS.Reg, volatile.LoadUint32(&o.P001PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP001PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P001PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P002PFS: Port 00%s Pin Function Select Register
func (o *PFS_Type) SetP002PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP002PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P002PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP002PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP002PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP002PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP002PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP002PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP002PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP002PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP002PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP002PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP002PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP002PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP002PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP002PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP002PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP002PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP002PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP002PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP002PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP002PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P002PFS.Reg, volatile.LoadUint32(&o.P002PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP002PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P002PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P003PFS: Port 00%s Pin Function Select Register
func (o *PFS_Type) SetP003PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP003PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P003PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP003PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP003PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP003PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP003PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP003PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP003PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP003PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP003PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP003PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP003PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP003PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP003PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP003PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP003PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP003PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP003PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP003PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP003PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP003PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P003PFS.Reg, volatile.LoadUint32(&o.P003PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP003PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P003PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P004PFS: Port 00%s Pin Function Select Register
func (o *PFS_Type) SetP004PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP004PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P004PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP004PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP004PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP004PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP004PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP004PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP004PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP004PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP004PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP004PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP004PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP004PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP004PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP004PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP004PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP004PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP004PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP004PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP004PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP004PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P004PFS.Reg, volatile.LoadUint32(&o.P004PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP004PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P004PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P005PFS: Port 00%s Pin Function Select Register
func (o *PFS_Type) SetP005PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP005PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P005PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP005PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP005PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP005PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP005PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP005PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP005PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP005PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP005PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP005PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP005PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP005PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP005PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP005PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP005PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP005PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP005PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP005PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP005PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP005PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P005PFS.Reg, volatile.LoadUint32(&o.P005PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP005PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P005PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P006PFS: Port 00%s Pin Function Select Register
func (o *PFS_Type) SetP006PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP006PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P006PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP006PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP006PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP006PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP006PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP006PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP006PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP006PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP006PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP006PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP006PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP006PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP006PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP006PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP006PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP006PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP006PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP006PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP006PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP006PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P006PFS.Reg, volatile.LoadUint32(&o.P006PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP006PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P006PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P008PFS: Port 008 Pin Function Select Register
func (o *PFS_Type) SetP008PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP008PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P008PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP008PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP008PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP008PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP008PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP008PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP008PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP008PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP008PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP008PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP008PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP008PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP008PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP008PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP008PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP008PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP008PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP008PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP008PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP008PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P008PFS.Reg, volatile.LoadUint32(&o.P008PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP008PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P008PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P013PFS: Port 0%s Pin Function Select Register
func (o *PFS_Type) SetP013PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP013PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P013PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP013PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP013PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP013PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP013PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP013PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP013PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP013PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP013PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP013PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP013PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP013PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP013PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP013PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP013PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP013PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP013PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP013PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP013PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP013PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P013PFS.Reg, volatile.LoadUint32(&o.P013PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP013PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P013PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P014PFS: Port 0%s Pin Function Select Register
func (o *PFS_Type) SetP014PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP014PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P014PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP014PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP014PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP014PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP014PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP014PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP014PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP014PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP014PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP014PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP014PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP014PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP014PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP014PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP014PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP014PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP014PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP014PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP014PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP014PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P014PFS.Reg, volatile.LoadUint32(&o.P014PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP014PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P014PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P015PFS: Port 0%s Pin Function Select Register
func (o *PFS_Type) SetP015PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP015PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P015PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP015PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP015PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP015PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP015PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP015PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP015PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP015PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP015PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP015PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP015PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP015PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP015PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP015PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP015PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP015PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP015PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP015PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP015PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP015PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P015PFS.Reg, volatile.LoadUint32(&o.P015PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP015PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P015PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P100PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP100PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP100PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P100PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP100PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP100PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP100PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP100PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP100PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP100PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP100PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP100PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP100PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP100PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP100PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP100PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP100PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP100PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP100PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP100PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP100PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP100PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP100PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P100PFS.Reg, volatile.LoadUint32(&o.P100PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP100PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P100PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P101PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP101PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP101PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P101PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP101PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP101PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP101PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP101PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP101PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP101PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP101PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP101PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP101PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP101PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP101PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP101PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP101PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP101PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP101PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP101PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP101PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP101PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP101PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P101PFS.Reg, volatile.LoadUint32(&o.P101PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP101PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P101PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P102PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP102PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP102PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P102PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP102PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP102PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP102PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP102PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP102PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP102PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP102PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP102PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP102PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP102PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP102PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP102PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP102PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP102PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP102PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP102PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP102PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP102PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP102PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P102PFS.Reg, volatile.LoadUint32(&o.P102PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP102PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P102PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P103PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP103PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP103PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P103PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP103PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP103PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP103PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP103PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP103PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP103PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP103PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP103PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP103PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP103PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP103PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP103PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP103PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP103PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP103PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP103PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP103PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP103PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP103PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P103PFS.Reg, volatile.LoadUint32(&o.P103PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP103PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P103PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P104PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP104PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP104PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P104PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP104PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP104PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP104PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP104PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP104PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP104PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP104PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP104PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP104PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP104PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP104PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP104PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP104PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP104PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP104PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP104PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP104PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP104PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP104PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P104PFS.Reg, volatile.LoadUint32(&o.P104PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP104PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P104PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P105PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP105PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP105PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P105PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP105PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP105PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP105PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP105PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP105PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP105PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP105PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP105PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP105PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP105PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP105PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP105PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP105PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP105PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP105PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP105PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP105PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP105PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP105PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P105PFS.Reg, volatile.LoadUint32(&o.P105PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP105PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P105PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P106PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP106PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP106PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P106PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP106PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP106PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP106PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP106PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP106PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP106PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP106PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP106PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP106PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP106PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP106PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP106PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP106PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP106PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP106PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP106PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP106PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP106PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP106PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P106PFS.Reg, volatile.LoadUint32(&o.P106PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP106PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P106PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P107PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP107PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP107PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P107PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP107PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP107PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP107PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP107PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP107PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP107PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP107PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP107PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP107PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP107PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP107PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP107PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP107PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP107PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP107PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP107PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP107PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP107PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP107PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P107PFS.Reg, volatile.LoadUint32(&o.P107PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP107PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P107PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P108PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP108PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP108PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P108PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP108PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP108PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP108PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP108PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP108PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP108PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP108PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP108PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP108PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP108PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP108PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP108PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP108PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP108PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP108PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP108PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP108PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP108PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP108PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P108PFS.Reg, volatile.LoadUint32(&o.P108PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP108PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P108PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P109PFS: Port 10%s Pin Function Select Register
func (o *PFS_Type) SetP109PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP109PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P109PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP109PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP109PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP109PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP109PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP109PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP109PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP109PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP109PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP109PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP109PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP109PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP109PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP109PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP109PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP109PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP109PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP109PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP109PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP109PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P109PFS.Reg, volatile.LoadUint32(&o.P109PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP109PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P109PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P110PFS: Port 1%s Pin Function Select Register
func (o *PFS_Type) SetP110PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP110PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P110PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP110PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP110PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP110PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP110PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP110PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP110PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP110PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP110PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP110PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP110PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP110PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP110PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP110PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP110PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP110PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP110PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP110PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP110PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP110PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P110PFS.Reg, volatile.LoadUint32(&o.P110PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP110PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P110PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P111PFS: Port 1%s Pin Function Select Register
func (o *PFS_Type) SetP111PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP111PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P111PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP111PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP111PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP111PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP111PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP111PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP111PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP111PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP111PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP111PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP111PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP111PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP111PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP111PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP111PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP111PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP111PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP111PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP111PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP111PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P111PFS.Reg, volatile.LoadUint32(&o.P111PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP111PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P111PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P112PFS: Port 1%s Pin Function Select Register
func (o *PFS_Type) SetP112PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP112PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P112PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP112PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP112PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP112PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP112PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP112PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP112PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP112PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP112PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP112PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP112PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP112PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP112PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP112PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP112PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP112PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP112PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP112PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP112PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP112PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P112PFS.Reg, volatile.LoadUint32(&o.P112PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP112PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P112PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P113PFS: Port 1%s Pin Function Select Register
func (o *PFS_Type) SetP113PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP113PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P113PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP113PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP113PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP113PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP113PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP113PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP113PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP113PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP113PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP113PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP113PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP113PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP113PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP113PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP113PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP113PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP113PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP113PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP113PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP113PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P113PFS.Reg, volatile.LoadUint32(&o.P113PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP113PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P113PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P200PFS: Port 200 Pin Function Select Register
func (o *PFS_Type) SetP200PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP200PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P200PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP200PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP200PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP200PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP200PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP200PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP200PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP200PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP200PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP200PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP200PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP200PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP200PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP200PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP200PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP200PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP200PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP200PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP200PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP200PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P200PFS.Reg, volatile.LoadUint32(&o.P200PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP200PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P200PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P201PFS: Port 201 Pin Function Select Register
func (o *PFS_Type) SetP201PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP201PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P201PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP201PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP201PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP201PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP201PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP201PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP201PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP201PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP201PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP201PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP201PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP201PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP201PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP201PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP201PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP201PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP201PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP201PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP201PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP201PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P201PFS.Reg, volatile.LoadUint32(&o.P201PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP201PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P201PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P205PFS: Port 20%s Pin Function Select Register
func (o *PFS_Type) SetP205PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP205PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P205PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP205PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP205PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP205PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP205PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP205PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP205PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP205PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP205PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP205PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP205PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP205PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP205PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP205PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP205PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP205PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP205PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP205PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP205PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP205PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P205PFS.Reg, volatile.LoadUint32(&o.P205PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP205PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P205PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P206PFS: Port 20%s Pin Function Select Register
func (o *PFS_Type) SetP206PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP206PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P206PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP206PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP206PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP206PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP206PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP206PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP206PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP206PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP206PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP206PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP206PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP206PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP206PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP206PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP206PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP206PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP206PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP206PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP206PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP206PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P206PFS.Reg, volatile.LoadUint32(&o.P206PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP206PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P206PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P207PFS: Port 20%s Pin Function Select Register
func (o *PFS_Type) SetP207PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP207PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P207PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP207PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP207PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP207PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP207PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP207PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP207PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP207PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP207PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP207PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP207PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP207PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP207PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP207PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP207PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP207PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP207PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP207PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP207PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP207PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P207PFS.Reg, volatile.LoadUint32(&o.P207PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP207PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P207PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P208PFS: Port 20%s Pin Function Select Register
func (o *PFS_Type) SetP208PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP208PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P208PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP208PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP208PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP208PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP208PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP208PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP208PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP208PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP208PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP208PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP208PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP208PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP208PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP208PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP208PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP208PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP208PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP208PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP208PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP208PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P208PFS.Reg, volatile.LoadUint32(&o.P208PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP208PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P208PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P212PFS: Port 2%s Pin Function Select Register
func (o *PFS_Type) SetP212PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP212PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P212PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP212PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP212PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP212PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP212PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP212PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP212PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP212PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP212PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP212PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP212PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP212PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP212PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP212PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP212PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP212PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP212PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP212PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP212PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP212PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P212PFS.Reg, volatile.LoadUint32(&o.P212PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP212PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P212PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P213PFS: Port 2%s Pin Function Select Register
func (o *PFS_Type) SetP213PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP213PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P213PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP213PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP213PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP213PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP213PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP213PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP213PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP213PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP213PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP213PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP213PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP213PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP213PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP213PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP213PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP213PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP213PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP213PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP213PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP213PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P213PFS.Reg, volatile.LoadUint32(&o.P213PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP213PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P213PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P300PFS: Port 300 Pin Function Select Register
func (o *PFS_Type) SetP300PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP300PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P300PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP300PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP300PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP300PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP300PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP300PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP300PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP300PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP300PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP300PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP300PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP300PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP300PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP300PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP300PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP300PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP300PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP300PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP300PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP300PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P300PFS.Reg, volatile.LoadUint32(&o.P300PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP300PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P300PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P301PFS: Port 30%s Pin Function Select Register
func (o *PFS_Type) SetP301PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP301PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P301PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP301PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP301PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP301PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP301PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP301PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP301PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP301PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP301PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP301PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP301PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP301PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP301PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP301PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP301PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP301PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP301PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP301PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP301PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP301PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P301PFS.Reg, volatile.LoadUint32(&o.P301PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP301PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P301PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P302PFS: Port 30%s Pin Function Select Register
func (o *PFS_Type) SetP302PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP302PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P302PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP302PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP302PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP302PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP302PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP302PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP302PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP302PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP302PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP302PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP302PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP302PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP302PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP302PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP302PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP302PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP302PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP302PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP302PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP302PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P302PFS.Reg, volatile.LoadUint32(&o.P302PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP302PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P302PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P303PFS: Port 30%s Pin Function Select Register
func (o *PFS_Type) SetP303PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP303PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P303PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP303PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP303PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP303PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP303PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP303PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP303PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP303PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP303PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP303PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP303PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP303PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP303PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP303PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP303PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP303PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP303PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP303PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP303PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP303PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P303PFS.Reg, volatile.LoadUint32(&o.P303PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP303PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P303PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P304PFS: Port 30%s Pin Function Select Register
func (o *PFS_Type) SetP304PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP304PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P304PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP304PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP304PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP304PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP304PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP304PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP304PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP304PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP304PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP304PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP304PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP304PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP304PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP304PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP304PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP304PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP304PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP304PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP304PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP304PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P304PFS.Reg, volatile.LoadUint32(&o.P304PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP304PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P304PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P400PFS: Port 40%s Pin Function Select Register
func (o *PFS_Type) SetP400PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP400PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P400PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP400PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP400PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP400PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP400PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP400PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP400PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP400PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP400PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP400PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP400PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP400PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP400PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP400PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP400PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP400PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP400PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP400PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP400PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP400PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P400PFS.Reg, volatile.LoadUint32(&o.P400PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP400PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P400PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P401PFS: Port 40%s Pin Function Select Register
func (o *PFS_Type) SetP401PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP401PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P401PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP401PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP401PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP401PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP401PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP401PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP401PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP401PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP401PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP401PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP401PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP401PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP401PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP401PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP401PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP401PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP401PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP401PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP401PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP401PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P401PFS.Reg, volatile.LoadUint32(&o.P401PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP401PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P401PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P402PFS: Port 40%s Pin Function Select Register
func (o *PFS_Type) SetP402PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP402PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P402PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP402PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP402PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP402PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP402PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP402PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP402PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP402PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP402PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP402PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP402PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP402PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP402PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP402PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP402PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP402PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP402PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP402PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP402PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP402PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P402PFS.Reg, volatile.LoadUint32(&o.P402PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP402PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P402PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P403PFS: Port 40%s Pin Function Select Register
func (o *PFS_Type) SetP403PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP403PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P403PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP403PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP403PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP403PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP403PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP403PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP403PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP403PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP403PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP403PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP403PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP403PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP403PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP403PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP403PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP403PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP403PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP403PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP403PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP403PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P403PFS.Reg, volatile.LoadUint32(&o.P403PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP403PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P403PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P407PFS: Port 40%s Pin Function Select Register
func (o *PFS_Type) SetP407PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP407PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P407PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP407PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP407PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP407PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP407PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP407PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP407PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP407PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP407PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP407PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP407PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP407PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP407PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP407PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP407PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP407PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP407PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP407PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP407PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP407PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P407PFS.Reg, volatile.LoadUint32(&o.P407PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP407PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P407PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P408PFS: Port 40%s Pin Function Select Register
func (o *PFS_Type) SetP408PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP408PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P408PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP408PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP408PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP408PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP408PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP408PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP408PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP408PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP408PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP408PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP408PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP408PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP408PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP408PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP408PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP408PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP408PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP408PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP408PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP408PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P408PFS.Reg, volatile.LoadUint32(&o.P408PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP408PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P408PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P409PFS: Port 40%s Pin Function Select Register
func (o *PFS_Type) SetP409PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP409PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P409PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP409PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP409PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP409PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP409PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP409PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP409PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP409PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP409PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP409PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP409PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP409PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP409PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP409PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP409PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP409PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP409PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP409PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP409PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP409PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P409PFS.Reg, volatile.LoadUint32(&o.P409PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP409PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P409PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P410PFS: Port 4%s Pin Function Select Register
func (o *PFS_Type) SetP410PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP410PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P410PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP410PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP410PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP410PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP410PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP410PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP410PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP410PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP410PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP410PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP410PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP410PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP410PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP410PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP410PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP410PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP410PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP410PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP410PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP410PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P410PFS.Reg, volatile.LoadUint32(&o.P410PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP410PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P410PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P411PFS: Port 4%s Pin Function Select Register
func (o *PFS_Type) SetP411PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP411PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P411PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP411PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP411PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP411PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP411PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP411PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP411PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP411PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP411PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP411PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP411PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP411PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP411PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP411PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP411PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP411PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP411PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP411PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP411PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP411PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P411PFS.Reg, volatile.LoadUint32(&o.P411PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP411PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P411PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P500PFS: Port 500 Pin Function Select Register
func (o *PFS_Type) SetP500PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP500PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P500PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP500PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP500PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP500PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP500PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP500PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP500PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP500PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP500PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP500PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP500PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP500PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP500PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP500PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP500PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP500PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP500PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP500PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP500PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP500PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P500PFS.Reg, volatile.LoadUint32(&o.P500PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP500PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P500PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P8014PFS: Port 80%s Pin Function Select Register
func (o *PFS_Type) SetP8014PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP8014PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P8014PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP8014PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP8014PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP8014PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP8014PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP8014PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP8014PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP8014PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP8014PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP8014PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP8014PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP8014PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP8014PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP8014PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP8014PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP8014PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP8014PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP8014PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP8014PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP8014PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P8014PFS.Reg, volatile.LoadUint32(&o.P8014PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP8014PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P8014PFS.Reg) & 0x1f000000) >> 24
}

// PFS.P8015PFS: Port 80%s Pin Function Select Register
func (o *PFS_Type) SetP8015PFS_PODR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetP8015PFS_PODR() uint32 {
	return volatile.LoadUint32(&o.P8015PFS.Reg) & 0x1
}
func (o *PFS_Type) SetP8015PFS_PIDR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x2)|value<<1)
}
func (o *PFS_Type) GetP8015PFS_PIDR() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x2) >> 1
}
func (o *PFS_Type) SetP8015PFS_PDR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x4)|value<<2)
}
func (o *PFS_Type) GetP8015PFS_PDR() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x4) >> 2
}
func (o *PFS_Type) SetP8015PFS_PCR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x10)|value<<4)
}
func (o *PFS_Type) GetP8015PFS_PCR() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x10) >> 4
}
func (o *PFS_Type) SetP8015PFS_NCODR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetP8015PFS_NCODR() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetP8015PFS_DSCR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0xc00)|value<<10)
}
func (o *PFS_Type) GetP8015PFS_DSCR() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0xc00) >> 10
}
func (o *PFS_Type) SetP8015PFS_EOFR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x3000)|value<<12)
}
func (o *PFS_Type) GetP8015PFS_EOFR() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x3000) >> 12
}
func (o *PFS_Type) SetP8015PFS_ISEL(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x4000)|value<<14)
}
func (o *PFS_Type) GetP8015PFS_ISEL() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x4000) >> 14
}
func (o *PFS_Type) SetP8015PFS_ASEL(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x8000)|value<<15)
}
func (o *PFS_Type) GetP8015PFS_ASEL() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x8000) >> 15
}
func (o *PFS_Type) SetP8015PFS_PMR(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x10000)|value<<16)
}
func (o *PFS_Type) GetP8015PFS_PMR() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x10000) >> 16
}
func (o *PFS_Type) SetP8015PFS_PSEL(value uint32) {
	volatile.StoreUint32(&o.P8015PFS.Reg, volatile.LoadUint32(&o.P8015PFS.Reg)&^(0x1f000000)|value<<24)
}
func (o *PFS_Type) GetP8015PFS_PSEL() uint32 {
	return (volatile.LoadUint32(&o.P8015PFS.Reg) & 0x1f000000) >> 24
}

// PFS.PWPR: Write-Protect Register
func (o *PFS_Type) SetPWPR_PFSWE(value uint8) {
	volatile.StoreUint8(&o.PWPR.Reg, volatile.LoadUint8(&o.PWPR.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetPWPR_PFSWE() uint8 {
	return (volatile.LoadUint8(&o.PWPR.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetPWPR_B0WI(value uint8) {
	volatile.StoreUint8(&o.PWPR.Reg, volatile.LoadUint8(&o.PWPR.Reg)&^(0x80)|value<<7)
}
func (o *PFS_Type) GetPWPR_B0WI() uint8 {
	return (volatile.LoadUint8(&o.PWPR.Reg) & 0x80) >> 7
}

// PFS.PWPRS: Write-Protect Register for Secure
func (o *PFS_Type) SetPWPRS_PFSWE(value uint8) {
	volatile.StoreUint8(&o.PWPRS.Reg, volatile.LoadUint8(&o.PWPRS.Reg)&^(0x40)|value<<6)
}
func (o *PFS_Type) GetPWPRS_PFSWE() uint8 {
	return (volatile.LoadUint8(&o.PWPRS.Reg) & 0x40) >> 6
}
func (o *PFS_Type) SetPWPRS_B0WI(value uint8) {
	volatile.StoreUint8(&o.PWPRS.Reg, volatile.LoadUint8(&o.PWPRS.Reg)&^(0x80)|value<<7)
}
func (o *PFS_Type) GetPWPRS_B0WI() uint8 {
	return (volatile.LoadUint8(&o.PWPRS.Reg) & 0x80) >> 7
}

// PFS.PFI3C: RI3C Slope Control Register
func (o *PFS_Type) SetPFI3C_I3CSLOPE0(value uint8) {
	volatile.StoreUint8(&o.PFI3C.Reg, volatile.LoadUint8(&o.PFI3C.Reg)&^(0x1)|value)
}
func (o *PFS_Type) GetPFI3C_I3CSLOPE0() uint8 {
	return volatile.LoadUint8(&o.PFI3C.Reg) & 0x1
}

// PFS.P0SAR: Port Security Attribution register
func (o *PFS_Type) SetP0SAR(value uint16) {
	volatile.StoreUint16(&o.P0SAR.Reg, value)
}
func (o *PFS_Type) GetP0SAR() uint16 {
	return volatile.LoadUint16(&o.P0SAR.Reg)
}

// PFS.P1SAR: Port Security Attribution register
func (o *PFS_Type) SetP1SAR(value uint16) {
	volatile.StoreUint16(&o.P1SAR.Reg, value)
}
func (o *PFS_Type) GetP1SAR() uint16 {
	return volatile.LoadUint16(&o.P1SAR.Reg)
}

// PFS.P2SAR: Port Security Attribution register
func (o *PFS_Type) SetP2SAR(value uint16) {
	volatile.StoreUint16(&o.P2SAR.Reg, value)
}
func (o *PFS_Type) GetP2SAR() uint16 {
	return volatile.LoadUint16(&o.P2SAR.Reg)
}

// PFS.P3SAR: Port Security Attribution register
func (o *PFS_Type) SetP3SAR(value uint16) {
	volatile.StoreUint16(&o.P3SAR.Reg, value)
}
func (o *PFS_Type) GetP3SAR() uint16 {
	return volatile.LoadUint16(&o.P3SAR.Reg)
}

// PFS.P4SAR: Port Security Attribution register
func (o *PFS_Type) SetP4SAR(value uint16) {
	volatile.StoreUint16(&o.P4SAR.Reg, value)
}
func (o *PFS_Type) GetP4SAR() uint16 {
	return volatile.LoadUint16(&o.P4SAR.Reg)
}

// PFS.P5SAR: Port Security Attribution register
func (o *PFS_Type) SetP5SAR(value uint16) {
	volatile.StoreUint16(&o.P5SAR.Reg, value)
}
func (o *PFS_Type) GetP5SAR() uint16 {
	return volatile.LoadUint16(&o.P5SAR.Reg)
}

// PFS.P8SAR: Port Security Attribution register
func (o *PFS_Type) SetP8SAR(value uint16) {
	volatile.StoreUint16(&o.P8SAR.Reg, value)
}
func (o *PFS_Type) GetP8SAR() uint16 {
	return volatile.LoadUint16(&o.P8SAR.Reg)
}

// Event Link Controller
type ELC_Type struct {
	ELCR    volatile.Register8 // 0x0
	_       byte
	ELSEGR0 volatile.Register8 // 0x2
	_       byte
	ELSEGR1 volatile.Register8 // 0x4
	_       [11]byte
	ELSR0   volatile.Register16 // 0x10
	_       [2]byte
	ELSR1   volatile.Register16 // 0x14
	_       [2]byte
	ELSR2   volatile.Register16 // 0x18
	_       [2]byte
	ELSR3   volatile.Register16 // 0x1C
	_       [2]byte
	ELSR4   volatile.Register16 // 0x20
	_       [2]byte
	ELSR5   volatile.Register16 // 0x24
	_       [2]byte
	ELSR6   volatile.Register16 // 0x28
	_       [2]byte
	ELSR7   volatile.Register16 // 0x2C
	_       [2]byte
	ELSR8   volatile.Register16 // 0x30
	_       [2]byte
	ELSR9   volatile.Register16 // 0x34
	_       [10]byte
	ELSR12  volatile.Register16 // 0x40
	_       [2]byte
	ELSR13  volatile.Register16 // 0x44
	_       [2]byte
	ELSR14  volatile.Register16 // 0x48
	_       [2]byte
	ELSR15  volatile.Register16 // 0x4C
	_       [2]byte
	ELSR16  volatile.Register16 // 0x50
	_       [2]byte
	ELSR17  volatile.Register16 // 0x54
	_       [22]byte
	ELSR23  volatile.Register16 // 0x6C
	_       [6]byte
	ELCSARA volatile.Register16 // 0x74
	_       [2]byte
	ELCSARB volatile.Register16 // 0x78
	_       [2]byte
	ELCSARC volatile.Register16 // 0x7C
}

// ELC.ELCR: Event Link Controller Register
func (o *ELC_Type) SetELCR_ELCON(value uint8) {
	volatile.StoreUint8(&o.ELCR.Reg, volatile.LoadUint8(&o.ELCR.Reg)&^(0x80)|value<<7)
}
func (o *ELC_Type) GetELCR_ELCON() uint8 {
	return (volatile.LoadUint8(&o.ELCR.Reg) & 0x80) >> 7
}

// ELC.ELSEGR0: Event Link Software Event Generation Register %s
func (o *ELC_Type) SetELSEGR0_SEG(value uint8) {
	volatile.StoreUint8(&o.ELSEGR0.Reg, volatile.LoadUint8(&o.ELSEGR0.Reg)&^(0x1)|value)
}
func (o *ELC_Type) GetELSEGR0_SEG() uint8 {
	return volatile.LoadUint8(&o.ELSEGR0.Reg) & 0x1
}
func (o *ELC_Type) SetELSEGR0_WE(value uint8) {
	volatile.StoreUint8(&o.ELSEGR0.Reg, volatile.LoadUint8(&o.ELSEGR0.Reg)&^(0x40)|value<<6)
}
func (o *ELC_Type) GetELSEGR0_WE() uint8 {
	return (volatile.LoadUint8(&o.ELSEGR0.Reg) & 0x40) >> 6
}
func (o *ELC_Type) SetELSEGR0_WI(value uint8) {
	volatile.StoreUint8(&o.ELSEGR0.Reg, volatile.LoadUint8(&o.ELSEGR0.Reg)&^(0x80)|value<<7)
}
func (o *ELC_Type) GetELSEGR0_WI() uint8 {
	return (volatile.LoadUint8(&o.ELSEGR0.Reg) & 0x80) >> 7
}

// ELC.ELSEGR1: Event Link Software Event Generation Register %s
func (o *ELC_Type) SetELSEGR1_SEG(value uint8) {
	volatile.StoreUint8(&o.ELSEGR1.Reg, volatile.LoadUint8(&o.ELSEGR1.Reg)&^(0x1)|value)
}
func (o *ELC_Type) GetELSEGR1_SEG() uint8 {
	return volatile.LoadUint8(&o.ELSEGR1.Reg) & 0x1
}
func (o *ELC_Type) SetELSEGR1_WE(value uint8) {
	volatile.StoreUint8(&o.ELSEGR1.Reg, volatile.LoadUint8(&o.ELSEGR1.Reg)&^(0x40)|value<<6)
}
func (o *ELC_Type) GetELSEGR1_WE() uint8 {
	return (volatile.LoadUint8(&o.ELSEGR1.Reg) & 0x40) >> 6
}
func (o *ELC_Type) SetELSEGR1_WI(value uint8) {
	volatile.StoreUint8(&o.ELSEGR1.Reg, volatile.LoadUint8(&o.ELSEGR1.Reg)&^(0x80)|value<<7)
}
func (o *ELC_Type) GetELSEGR1_WI() uint8 {
	return (volatile.LoadUint8(&o.ELSEGR1.Reg) & 0x80) >> 7
}

// ELC.ELSR0: Event Link Setting Register %s
func (o *ELC_Type) SetELSR0_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR0.Reg, volatile.LoadUint16(&o.ELSR0.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR0_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR0.Reg) & 0x1ff
}

// ELC.ELSR1: Event Link Setting Register %s
func (o *ELC_Type) SetELSR1_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR1.Reg, volatile.LoadUint16(&o.ELSR1.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR1_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR1.Reg) & 0x1ff
}

// ELC.ELSR2: Event Link Setting Register %s
func (o *ELC_Type) SetELSR2_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR2.Reg, volatile.LoadUint16(&o.ELSR2.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR2_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR2.Reg) & 0x1ff
}

// ELC.ELSR3: Event Link Setting Register %s
func (o *ELC_Type) SetELSR3_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR3.Reg, volatile.LoadUint16(&o.ELSR3.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR3_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR3.Reg) & 0x1ff
}

// ELC.ELSR4: Event Link Setting Register %s
func (o *ELC_Type) SetELSR4_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR4.Reg, volatile.LoadUint16(&o.ELSR4.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR4_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR4.Reg) & 0x1ff
}

// ELC.ELSR5: Event Link Setting Register %s
func (o *ELC_Type) SetELSR5_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR5.Reg, volatile.LoadUint16(&o.ELSR5.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR5_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR5.Reg) & 0x1ff
}

// ELC.ELSR6: Event Link Setting Register %s
func (o *ELC_Type) SetELSR6_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR6.Reg, volatile.LoadUint16(&o.ELSR6.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR6_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR6.Reg) & 0x1ff
}

// ELC.ELSR7: Event Link Setting Register %s
func (o *ELC_Type) SetELSR7_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR7.Reg, volatile.LoadUint16(&o.ELSR7.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR7_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR7.Reg) & 0x1ff
}

// ELC.ELSR8: Event Link Setting Register %s
func (o *ELC_Type) SetELSR8_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR8.Reg, volatile.LoadUint16(&o.ELSR8.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR8_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR8.Reg) & 0x1ff
}

// ELC.ELSR9: Event Link Setting Register %s
func (o *ELC_Type) SetELSR9_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR9.Reg, volatile.LoadUint16(&o.ELSR9.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR9_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR9.Reg) & 0x1ff
}

// ELC.ELSR12: Event Link Setting Register %s
func (o *ELC_Type) SetELSR12_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR12.Reg, volatile.LoadUint16(&o.ELSR12.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR12_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR12.Reg) & 0x1ff
}

// ELC.ELSR13: Event Link Setting Register %s
func (o *ELC_Type) SetELSR13_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR13.Reg, volatile.LoadUint16(&o.ELSR13.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR13_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR13.Reg) & 0x1ff
}

// ELC.ELSR14: Event Link Setting Register %s
func (o *ELC_Type) SetELSR14_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR14.Reg, volatile.LoadUint16(&o.ELSR14.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR14_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR14.Reg) & 0x1ff
}

// ELC.ELSR15: Event Link Setting Register %s
func (o *ELC_Type) SetELSR15_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR15.Reg, volatile.LoadUint16(&o.ELSR15.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR15_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR15.Reg) & 0x1ff
}

// ELC.ELSR16: Event Link Setting Register %s
func (o *ELC_Type) SetELSR16_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR16.Reg, volatile.LoadUint16(&o.ELSR16.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR16_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR16.Reg) & 0x1ff
}

// ELC.ELSR17: Event Link Setting Register %s
func (o *ELC_Type) SetELSR17_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR17.Reg, volatile.LoadUint16(&o.ELSR17.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR17_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR17.Reg) & 0x1ff
}

// ELC.ELSR23: Event Link Setting Register 23
func (o *ELC_Type) SetELSR23_ELS(value uint16) {
	volatile.StoreUint16(&o.ELSR23.Reg, volatile.LoadUint16(&o.ELSR23.Reg)&^(0x1ff)|value)
}
func (o *ELC_Type) GetELSR23_ELS() uint16 {
	return volatile.LoadUint16(&o.ELSR23.Reg) & 0x1ff
}

// ELC.ELCSARA: Event Link Controller Security Attribution Register A
func (o *ELC_Type) SetELCSARA_ELCR(value uint16) {
	volatile.StoreUint16(&o.ELCSARA.Reg, volatile.LoadUint16(&o.ELCSARA.Reg)&^(0x1)|value)
}
func (o *ELC_Type) GetELCSARA_ELCR() uint16 {
	return volatile.LoadUint16(&o.ELCSARA.Reg) & 0x1
}
func (o *ELC_Type) SetELCSARA_ELSEGR0(value uint16) {
	volatile.StoreUint16(&o.ELCSARA.Reg, volatile.LoadUint16(&o.ELCSARA.Reg)&^(0x2)|value<<1)
}
func (o *ELC_Type) GetELCSARA_ELSEGR0() uint16 {
	return (volatile.LoadUint16(&o.ELCSARA.Reg) & 0x2) >> 1
}
func (o *ELC_Type) SetELCSARA_ELSEGR1(value uint16) {
	volatile.StoreUint16(&o.ELCSARA.Reg, volatile.LoadUint16(&o.ELCSARA.Reg)&^(0x4)|value<<2)
}
func (o *ELC_Type) GetELCSARA_ELSEGR1() uint16 {
	return (volatile.LoadUint16(&o.ELCSARA.Reg) & 0x4) >> 2
}

// ELC.ELCSARB: Event Link Controller Security Attribution Register B
func (o *ELC_Type) SetELCSARB(value uint16) {
	volatile.StoreUint16(&o.ELCSARB.Reg, value)
}
func (o *ELC_Type) GetELCSARB() uint16 {
	return volatile.LoadUint16(&o.ELCSARB.Reg)
}

// ELC.ELCSARC: Event Link Controller Security Attribution Register C
func (o *ELC_Type) SetELCSARC_ELSR(value uint16) {
	volatile.StoreUint16(&o.ELCSARC.Reg, volatile.LoadUint16(&o.ELCSARC.Reg)&^(0xff)|value)
}
func (o *ELC_Type) GetELCSARC_ELSR() uint16 {
	return volatile.LoadUint16(&o.ELCSARC.Reg) & 0xff
}

// Realtime Clock
type RTC_Type struct {
	R64CNT   volatile.Register8 // 0x0
	_        byte
	BCNT0    volatile.Register8 // 0x2
	_        byte
	BCNT1    volatile.Register8 // 0x4
	_        byte
	BCNT2    volatile.Register8 // 0x6
	_        byte
	BCNT3    volatile.Register8 // 0x8
	_        byte
	RDAYCNT  volatile.Register8 // 0xA
	_        byte
	RMONCNT  volatile.Register8 // 0xC
	_        byte
	RYRCNT   volatile.Register16 // 0xE
	BCNT0AR  volatile.Register8  // 0x10
	_        byte
	BCNT1AR  volatile.Register8 // 0x12
	_        byte
	BCNT2AR  volatile.Register8 // 0x14
	_        byte
	BCNT3AR  volatile.Register8 // 0x16
	_        byte
	BCNT0AER volatile.Register8 // 0x18
	_        byte
	BCNT1AER volatile.Register8 // 0x1A
	_        byte
	BCNT2AER volatile.Register16 // 0x1C
	BCNT3AER volatile.Register8  // 0x1E
	_        [3]byte
	RCR1     volatile.Register8 // 0x22
	_        byte
	RCR2     volatile.Register8 // 0x24
	_        [3]byte
	RCR4     volatile.Register8 // 0x28
	_        byte
	RFRH     volatile.Register16 // 0x2A
	RFRL     volatile.Register16 // 0x2C
	RADJ     volatile.Register8  // 0x2E
	_        [17]byte
	RTCCR0   volatile.Register8 // 0x40
	_        byte
	RTCCR1   volatile.Register8 // 0x42
	_        [15]byte
	BCNT0CP0 volatile.Register8 // 0x52
	_        byte
	BCNT1CP0 volatile.Register8 // 0x54
	_        byte
	BCNT2CP0 volatile.Register8 // 0x56
	_        [3]byte
	BCNT3CP0 volatile.Register8 // 0x5A
	_        byte
	RMONCP0  volatile.Register8 // 0x5C
	_        [5]byte
	BCNT0CP1 volatile.Register8 // 0x62
	_        byte
	BCNT1CP1 volatile.Register8 // 0x64
	_        byte
	BCNT2CP1 volatile.Register8 // 0x66
	_        [3]byte
	BCNT3CP1 volatile.Register8 // 0x6A
	_        byte
	RMONCP1  volatile.Register8 // 0x6C
}

// RTC.R64CNT: 64-Hz Counter
func (o *RTC_Type) SetR64CNT_F64HZ(value uint8) {
	volatile.StoreUint8(&o.R64CNT.Reg, volatile.LoadUint8(&o.R64CNT.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetR64CNT_F64HZ() uint8 {
	return volatile.LoadUint8(&o.R64CNT.Reg) & 0x1
}
func (o *RTC_Type) SetR64CNT_F32HZ(value uint8) {
	volatile.StoreUint8(&o.R64CNT.Reg, volatile.LoadUint8(&o.R64CNT.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetR64CNT_F32HZ() uint8 {
	return (volatile.LoadUint8(&o.R64CNT.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetR64CNT_F16HZ(value uint8) {
	volatile.StoreUint8(&o.R64CNT.Reg, volatile.LoadUint8(&o.R64CNT.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetR64CNT_F16HZ() uint8 {
	return (volatile.LoadUint8(&o.R64CNT.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetR64CNT_F8HZ(value uint8) {
	volatile.StoreUint8(&o.R64CNT.Reg, volatile.LoadUint8(&o.R64CNT.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetR64CNT_F8HZ() uint8 {
	return (volatile.LoadUint8(&o.R64CNT.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetR64CNT_F4HZ(value uint8) {
	volatile.StoreUint8(&o.R64CNT.Reg, volatile.LoadUint8(&o.R64CNT.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetR64CNT_F4HZ() uint8 {
	return (volatile.LoadUint8(&o.R64CNT.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetR64CNT_F2HZ(value uint8) {
	volatile.StoreUint8(&o.R64CNT.Reg, volatile.LoadUint8(&o.R64CNT.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetR64CNT_F2HZ() uint8 {
	return (volatile.LoadUint8(&o.R64CNT.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetR64CNT_F1HZ(value uint8) {
	volatile.StoreUint8(&o.R64CNT.Reg, volatile.LoadUint8(&o.R64CNT.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetR64CNT_F1HZ() uint8 {
	return (volatile.LoadUint8(&o.R64CNT.Reg) & 0x40) >> 6
}

// RTC.BCNT0: Binary Counter %s
func (o *RTC_Type) SetBCNT0(value uint8) {
	volatile.StoreUint8(&o.BCNT0.Reg, value)
}
func (o *RTC_Type) GetBCNT0() uint8 {
	return volatile.LoadUint8(&o.BCNT0.Reg)
}

// RTC.BCNT1: Binary Counter %s
func (o *RTC_Type) SetBCNT1(value uint8) {
	volatile.StoreUint8(&o.BCNT1.Reg, value)
}
func (o *RTC_Type) GetBCNT1() uint8 {
	return volatile.LoadUint8(&o.BCNT1.Reg)
}

// RTC.BCNT2: Binary Counter %s
func (o *RTC_Type) SetBCNT2(value uint8) {
	volatile.StoreUint8(&o.BCNT2.Reg, value)
}
func (o *RTC_Type) GetBCNT2() uint8 {
	return volatile.LoadUint8(&o.BCNT2.Reg)
}

// RTC.BCNT3: Binary Counter %s
func (o *RTC_Type) SetBCNT3(value uint8) {
	volatile.StoreUint8(&o.BCNT3.Reg, value)
}
func (o *RTC_Type) GetBCNT3() uint8 {
	return volatile.LoadUint8(&o.BCNT3.Reg)
}

// RTC.RDAYCNT: Day Counter
func (o *RTC_Type) SetRDAYCNT_DATE1(value uint8) {
	volatile.StoreUint8(&o.RDAYCNT.Reg, volatile.LoadUint8(&o.RDAYCNT.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetRDAYCNT_DATE1() uint8 {
	return volatile.LoadUint8(&o.RDAYCNT.Reg) & 0xf
}
func (o *RTC_Type) SetRDAYCNT_DATE10(value uint8) {
	volatile.StoreUint8(&o.RDAYCNT.Reg, volatile.LoadUint8(&o.RDAYCNT.Reg)&^(0x30)|value<<4)
}
func (o *RTC_Type) GetRDAYCNT_DATE10() uint8 {
	return (volatile.LoadUint8(&o.RDAYCNT.Reg) & 0x30) >> 4
}

// RTC.RMONCNT: Month Counter
func (o *RTC_Type) SetRMONCNT_MON1(value uint8) {
	volatile.StoreUint8(&o.RMONCNT.Reg, volatile.LoadUint8(&o.RMONCNT.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetRMONCNT_MON1() uint8 {
	return volatile.LoadUint8(&o.RMONCNT.Reg) & 0xf
}
func (o *RTC_Type) SetRMONCNT_MON10(value uint8) {
	volatile.StoreUint8(&o.RMONCNT.Reg, volatile.LoadUint8(&o.RMONCNT.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetRMONCNT_MON10() uint8 {
	return (volatile.LoadUint8(&o.RMONCNT.Reg) & 0x10) >> 4
}

// RTC.RYRCNT: Year Counter
func (o *RTC_Type) SetRYRCNT_YR1(value uint16) {
	volatile.StoreUint16(&o.RYRCNT.Reg, volatile.LoadUint16(&o.RYRCNT.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetRYRCNT_YR1() uint16 {
	return volatile.LoadUint16(&o.RYRCNT.Reg) & 0xf
}
func (o *RTC_Type) SetRYRCNT_YR10(value uint16) {
	volatile.StoreUint16(&o.RYRCNT.Reg, volatile.LoadUint16(&o.RYRCNT.Reg)&^(0xf0)|value<<4)
}
func (o *RTC_Type) GetRYRCNT_YR10() uint16 {
	return (volatile.LoadUint16(&o.RYRCNT.Reg) & 0xf0) >> 4
}

// RTC.BCNT0AR: Binary Counter %s Alarm Register
func (o *RTC_Type) SetBCNT0AR(value uint8) {
	volatile.StoreUint8(&o.BCNT0AR.Reg, value)
}
func (o *RTC_Type) GetBCNT0AR() uint8 {
	return volatile.LoadUint8(&o.BCNT0AR.Reg)
}

// RTC.BCNT1AR: Binary Counter %s Alarm Register
func (o *RTC_Type) SetBCNT1AR(value uint8) {
	volatile.StoreUint8(&o.BCNT1AR.Reg, value)
}
func (o *RTC_Type) GetBCNT1AR() uint8 {
	return volatile.LoadUint8(&o.BCNT1AR.Reg)
}

// RTC.BCNT2AR: Binary Counter %s Alarm Register
func (o *RTC_Type) SetBCNT2AR(value uint8) {
	volatile.StoreUint8(&o.BCNT2AR.Reg, value)
}
func (o *RTC_Type) GetBCNT2AR() uint8 {
	return volatile.LoadUint8(&o.BCNT2AR.Reg)
}

// RTC.BCNT3AR: Binary Counter %s Alarm Register
func (o *RTC_Type) SetBCNT3AR(value uint8) {
	volatile.StoreUint8(&o.BCNT3AR.Reg, value)
}
func (o *RTC_Type) GetBCNT3AR() uint8 {
	return volatile.LoadUint8(&o.BCNT3AR.Reg)
}

// RTC.BCNT0AER: Binary Counter %s Alarm Enable Register
func (o *RTC_Type) SetBCNT0AER(value uint8) {
	volatile.StoreUint8(&o.BCNT0AER.Reg, value)
}
func (o *RTC_Type) GetBCNT0AER() uint8 {
	return volatile.LoadUint8(&o.BCNT0AER.Reg)
}

// RTC.BCNT1AER: Binary Counter %s Alarm Enable Register
func (o *RTC_Type) SetBCNT1AER(value uint8) {
	volatile.StoreUint8(&o.BCNT1AER.Reg, value)
}
func (o *RTC_Type) GetBCNT1AER() uint8 {
	return volatile.LoadUint8(&o.BCNT1AER.Reg)
}

// RTC.BCNT2AER: Binary Counter 2 Alarm Enable Register
func (o *RTC_Type) SetBCNT2AER_ENB(value uint16) {
	volatile.StoreUint16(&o.BCNT2AER.Reg, volatile.LoadUint16(&o.BCNT2AER.Reg)&^(0xff)|value)
}
func (o *RTC_Type) GetBCNT2AER_ENB() uint16 {
	return volatile.LoadUint16(&o.BCNT2AER.Reg) & 0xff
}

// RTC.BCNT3AER: Binary Counter 3 Alarm Enable Register
func (o *RTC_Type) SetBCNT3AER(value uint8) {
	volatile.StoreUint8(&o.BCNT3AER.Reg, value)
}
func (o *RTC_Type) GetBCNT3AER() uint8 {
	return volatile.LoadUint8(&o.BCNT3AER.Reg)
}

// RTC.RCR1: RTC Control Register 1
func (o *RTC_Type) SetRCR1_AIE(value uint8) {
	volatile.StoreUint8(&o.RCR1.Reg, volatile.LoadUint8(&o.RCR1.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetRCR1_AIE() uint8 {
	return volatile.LoadUint8(&o.RCR1.Reg) & 0x1
}
func (o *RTC_Type) SetRCR1_CIE(value uint8) {
	volatile.StoreUint8(&o.RCR1.Reg, volatile.LoadUint8(&o.RCR1.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetRCR1_CIE() uint8 {
	return (volatile.LoadUint8(&o.RCR1.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetRCR1_PIE(value uint8) {
	volatile.StoreUint8(&o.RCR1.Reg, volatile.LoadUint8(&o.RCR1.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetRCR1_PIE() uint8 {
	return (volatile.LoadUint8(&o.RCR1.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetRCR1_RTCOS(value uint8) {
	volatile.StoreUint8(&o.RCR1.Reg, volatile.LoadUint8(&o.RCR1.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetRCR1_RTCOS() uint8 {
	return (volatile.LoadUint8(&o.RCR1.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetRCR1_PES(value uint8) {
	volatile.StoreUint8(&o.RCR1.Reg, volatile.LoadUint8(&o.RCR1.Reg)&^(0xf0)|value<<4)
}
func (o *RTC_Type) GetRCR1_PES() uint8 {
	return (volatile.LoadUint8(&o.RCR1.Reg) & 0xf0) >> 4
}

// RTC.RCR2: RTC Control Register 2 (in Calendar Count Mode)
func (o *RTC_Type) SetRCR2_START(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetRCR2_START() uint8 {
	return volatile.LoadUint8(&o.RCR2.Reg) & 0x1
}
func (o *RTC_Type) SetRCR2_RESET(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetRCR2_RESET() uint8 {
	return (volatile.LoadUint8(&o.RCR2.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetRCR2_ADJ30(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetRCR2_ADJ30() uint8 {
	return (volatile.LoadUint8(&o.RCR2.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetRCR2_RTCOE(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetRCR2_RTCOE() uint8 {
	return (volatile.LoadUint8(&o.RCR2.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetRCR2_AADJE(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetRCR2_AADJE() uint8 {
	return (volatile.LoadUint8(&o.RCR2.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetRCR2_AADJP(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetRCR2_AADJP() uint8 {
	return (volatile.LoadUint8(&o.RCR2.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetRCR2_HR24(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetRCR2_HR24() uint8 {
	return (volatile.LoadUint8(&o.RCR2.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetRCR2_CNTMD(value uint8) {
	volatile.StoreUint8(&o.RCR2.Reg, volatile.LoadUint8(&o.RCR2.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetRCR2_CNTMD() uint8 {
	return (volatile.LoadUint8(&o.RCR2.Reg) & 0x80) >> 7
}

// RTC.RCR4: RTC Control Register 4
func (o *RTC_Type) SetRCR4_RCKSEL(value uint8) {
	volatile.StoreUint8(&o.RCR4.Reg, volatile.LoadUint8(&o.RCR4.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetRCR4_RCKSEL() uint8 {
	return volatile.LoadUint8(&o.RCR4.Reg) & 0x1
}

// RTC.RFRH: Frequency Register H
func (o *RTC_Type) SetRFRH_RFC16(value uint16) {
	volatile.StoreUint16(&o.RFRH.Reg, volatile.LoadUint16(&o.RFRH.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetRFRH_RFC16() uint16 {
	return volatile.LoadUint16(&o.RFRH.Reg) & 0x1
}

// RTC.RFRL: Frequency Register L
func (o *RTC_Type) SetRFRL(value uint16) {
	volatile.StoreUint16(&o.RFRL.Reg, value)
}
func (o *RTC_Type) GetRFRL() uint16 {
	return volatile.LoadUint16(&o.RFRL.Reg)
}

// RTC.RADJ: Time Error Adjustment Register
func (o *RTC_Type) SetRADJ_ADJ(value uint8) {
	volatile.StoreUint8(&o.RADJ.Reg, volatile.LoadUint8(&o.RADJ.Reg)&^(0x3f)|value)
}
func (o *RTC_Type) GetRADJ_ADJ() uint8 {
	return volatile.LoadUint8(&o.RADJ.Reg) & 0x3f
}
func (o *RTC_Type) SetRADJ_PMADJ(value uint8) {
	volatile.StoreUint8(&o.RADJ.Reg, volatile.LoadUint8(&o.RADJ.Reg)&^(0xc0)|value<<6)
}
func (o *RTC_Type) GetRADJ_PMADJ() uint8 {
	return (volatile.LoadUint8(&o.RADJ.Reg) & 0xc0) >> 6
}

// RTC.RTCCR0: Time Capture Control Register %s
func (o *RTC_Type) SetRTCCR0_TCCT(value uint8) {
	volatile.StoreUint8(&o.RTCCR0.Reg, volatile.LoadUint8(&o.RTCCR0.Reg)&^(0x3)|value)
}
func (o *RTC_Type) GetRTCCR0_TCCT() uint8 {
	return volatile.LoadUint8(&o.RTCCR0.Reg) & 0x3
}
func (o *RTC_Type) SetRTCCR0_TCST(value uint8) {
	volatile.StoreUint8(&o.RTCCR0.Reg, volatile.LoadUint8(&o.RTCCR0.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetRTCCR0_TCST() uint8 {
	return (volatile.LoadUint8(&o.RTCCR0.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetRTCCR0_TCNF(value uint8) {
	volatile.StoreUint8(&o.RTCCR0.Reg, volatile.LoadUint8(&o.RTCCR0.Reg)&^(0x30)|value<<4)
}
func (o *RTC_Type) GetRTCCR0_TCNF() uint8 {
	return (volatile.LoadUint8(&o.RTCCR0.Reg) & 0x30) >> 4
}
func (o *RTC_Type) SetRTCCR0_TCEN(value uint8) {
	volatile.StoreUint8(&o.RTCCR0.Reg, volatile.LoadUint8(&o.RTCCR0.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetRTCCR0_TCEN() uint8 {
	return (volatile.LoadUint8(&o.RTCCR0.Reg) & 0x80) >> 7
}

// RTC.RTCCR1: Time Capture Control Register %s
func (o *RTC_Type) SetRTCCR1_TCCT(value uint8) {
	volatile.StoreUint8(&o.RTCCR1.Reg, volatile.LoadUint8(&o.RTCCR1.Reg)&^(0x3)|value)
}
func (o *RTC_Type) GetRTCCR1_TCCT() uint8 {
	return volatile.LoadUint8(&o.RTCCR1.Reg) & 0x3
}
func (o *RTC_Type) SetRTCCR1_TCST(value uint8) {
	volatile.StoreUint8(&o.RTCCR1.Reg, volatile.LoadUint8(&o.RTCCR1.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetRTCCR1_TCST() uint8 {
	return (volatile.LoadUint8(&o.RTCCR1.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetRTCCR1_TCNF(value uint8) {
	volatile.StoreUint8(&o.RTCCR1.Reg, volatile.LoadUint8(&o.RTCCR1.Reg)&^(0x30)|value<<4)
}
func (o *RTC_Type) GetRTCCR1_TCNF() uint8 {
	return (volatile.LoadUint8(&o.RTCCR1.Reg) & 0x30) >> 4
}
func (o *RTC_Type) SetRTCCR1_TCEN(value uint8) {
	volatile.StoreUint8(&o.RTCCR1.Reg, volatile.LoadUint8(&o.RTCCR1.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetRTCCR1_TCEN() uint8 {
	return (volatile.LoadUint8(&o.RTCCR1.Reg) & 0x80) >> 7
}

// RTC.RMONCP0: Month Capture Register %s
func (o *RTC_Type) SetRMONCP0_MON1(value uint8) {
	volatile.StoreUint8(&o.RMONCP0.Reg, volatile.LoadUint8(&o.RMONCP0.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetRMONCP0_MON1() uint8 {
	return volatile.LoadUint8(&o.RMONCP0.Reg) & 0xf
}
func (o *RTC_Type) SetRMONCP0_MON10(value uint8) {
	volatile.StoreUint8(&o.RMONCP0.Reg, volatile.LoadUint8(&o.RMONCP0.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetRMONCP0_MON10() uint8 {
	return (volatile.LoadUint8(&o.RMONCP0.Reg) & 0x10) >> 4
}

// RTC.RMONCP1: Month Capture Register %s
func (o *RTC_Type) SetRMONCP1_MON1(value uint8) {
	volatile.StoreUint8(&o.RMONCP1.Reg, volatile.LoadUint8(&o.RMONCP1.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetRMONCP1_MON1() uint8 {
	return volatile.LoadUint8(&o.RMONCP1.Reg) & 0xf
}
func (o *RTC_Type) SetRMONCP1_MON10(value uint8) {
	volatile.StoreUint8(&o.RMONCP1.Reg, volatile.LoadUint8(&o.RMONCP1.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetRMONCP1_MON10() uint8 {
	return (volatile.LoadUint8(&o.RMONCP1.Reg) & 0x10) >> 4
}

// Independent Watchdog Timer
type IWDT_Type struct {
	IWDTRR volatile.Register8 // 0x0
	_      [3]byte
	IWDTSR volatile.Register16 // 0x4
}

// IWDT.IWDTSR: IWDT Status Register
func (o *IWDT_Type) SetIWDTSR_CNTVAL(value uint16) {
	volatile.StoreUint16(&o.IWDTSR.Reg, volatile.LoadUint16(&o.IWDTSR.Reg)&^(0x3fff)|value)
}
func (o *IWDT_Type) GetIWDTSR_CNTVAL() uint16 {
	return volatile.LoadUint16(&o.IWDTSR.Reg) & 0x3fff
}
func (o *IWDT_Type) SetIWDTSR_UNDFF(value uint16) {
	volatile.StoreUint16(&o.IWDTSR.Reg, volatile.LoadUint16(&o.IWDTSR.Reg)&^(0x4000)|value<<14)
}
func (o *IWDT_Type) GetIWDTSR_UNDFF() uint16 {
	return (volatile.LoadUint16(&o.IWDTSR.Reg) & 0x4000) >> 14
}
func (o *IWDT_Type) SetIWDTSR_REFEF(value uint16) {
	volatile.StoreUint16(&o.IWDTSR.Reg, volatile.LoadUint16(&o.IWDTSR.Reg)&^(0x8000)|value<<15)
}
func (o *IWDT_Type) GetIWDTSR_REFEF() uint16 {
	return (volatile.LoadUint16(&o.IWDTSR.Reg) & 0x8000) >> 15
}

// Watchdog Timer
type WDT_Type struct {
	WDTRR    volatile.Register8 // 0x0
	_        byte
	WDTCR    volatile.Register16 // 0x2
	WDTSR    volatile.Register16 // 0x4
	WDTRCR   volatile.Register8  // 0x6
	_        byte
	WDTCSTPR volatile.Register8 // 0x8
}

// WDT.WDTCR: WDT Control Register
func (o *WDT_Type) SetWDTCR_TOPS(value uint16) {
	volatile.StoreUint16(&o.WDTCR.Reg, volatile.LoadUint16(&o.WDTCR.Reg)&^(0x3)|value)
}
func (o *WDT_Type) GetWDTCR_TOPS() uint16 {
	return volatile.LoadUint16(&o.WDTCR.Reg) & 0x3
}
func (o *WDT_Type) SetWDTCR_CKS(value uint16) {
	volatile.StoreUint16(&o.WDTCR.Reg, volatile.LoadUint16(&o.WDTCR.Reg)&^(0xf0)|value<<4)
}
func (o *WDT_Type) GetWDTCR_CKS() uint16 {
	return (volatile.LoadUint16(&o.WDTCR.Reg) & 0xf0) >> 4
}
func (o *WDT_Type) SetWDTCR_RPES(value uint16) {
	volatile.StoreUint16(&o.WDTCR.Reg, volatile.LoadUint16(&o.WDTCR.Reg)&^(0x300)|value<<8)
}
func (o *WDT_Type) GetWDTCR_RPES() uint16 {
	return (volatile.LoadUint16(&o.WDTCR.Reg) & 0x300) >> 8
}
func (o *WDT_Type) SetWDTCR_RPSS(value uint16) {
	volatile.StoreUint16(&o.WDTCR.Reg, volatile.LoadUint16(&o.WDTCR.Reg)&^(0x3000)|value<<12)
}
func (o *WDT_Type) GetWDTCR_RPSS() uint16 {
	return (volatile.LoadUint16(&o.WDTCR.Reg) & 0x3000) >> 12
}

// WDT.WDTSR: WDT Status Register
func (o *WDT_Type) SetWDTSR_CNTVAL(value uint16) {
	volatile.StoreUint16(&o.WDTSR.Reg, volatile.LoadUint16(&o.WDTSR.Reg)&^(0x3fff)|value)
}
func (o *WDT_Type) GetWDTSR_CNTVAL() uint16 {
	return volatile.LoadUint16(&o.WDTSR.Reg) & 0x3fff
}
func (o *WDT_Type) SetWDTSR_UNDFF(value uint16) {
	volatile.StoreUint16(&o.WDTSR.Reg, volatile.LoadUint16(&o.WDTSR.Reg)&^(0x4000)|value<<14)
}
func (o *WDT_Type) GetWDTSR_UNDFF() uint16 {
	return (volatile.LoadUint16(&o.WDTSR.Reg) & 0x4000) >> 14
}
func (o *WDT_Type) SetWDTSR_REFEF(value uint16) {
	volatile.StoreUint16(&o.WDTSR.Reg, volatile.LoadUint16(&o.WDTSR.Reg)&^(0x8000)|value<<15)
}
func (o *WDT_Type) GetWDTSR_REFEF() uint16 {
	return (volatile.LoadUint16(&o.WDTSR.Reg) & 0x8000) >> 15
}

// WDT.WDTRCR: WDT Reset Control Register
func (o *WDT_Type) SetWDTRCR_RSTIRQS(value uint8) {
	volatile.StoreUint8(&o.WDTRCR.Reg, volatile.LoadUint8(&o.WDTRCR.Reg)&^(0x80)|value<<7)
}
func (o *WDT_Type) GetWDTRCR_RSTIRQS() uint8 {
	return (volatile.LoadUint8(&o.WDTRCR.Reg) & 0x80) >> 7
}

// WDT.WDTCSTPR: WDT Count Stop Control Register
func (o *WDT_Type) SetWDTCSTPR_SLCSTP(value uint8) {
	volatile.StoreUint8(&o.WDTCSTPR.Reg, volatile.LoadUint8(&o.WDTCSTPR.Reg)&^(0x80)|value<<7)
}
func (o *WDT_Type) GetWDTCSTPR_SLCSTP() uint8 {
	return (volatile.LoadUint8(&o.WDTCSTPR.Reg) & 0x80) >> 7
}

// Clock Frequency Accuracy Measurement Circuit
type CAC_Type struct {
	CACR0   volatile.Register8 // 0x0
	CACR1   volatile.Register8 // 0x1
	CACR2   volatile.Register8 // 0x2
	CAICR   volatile.Register8 // 0x3
	CASTR   volatile.Register8 // 0x4
	_       byte
	CAULVR  volatile.Register16 // 0x6
	CALLVR  volatile.Register16 // 0x8
	CACNTBR volatile.Register16 // 0xA
}

// CAC.CACR0: CAC Control Register 0
func (o *CAC_Type) SetCACR0_CFME(value uint8) {
	volatile.StoreUint8(&o.CACR0.Reg, volatile.LoadUint8(&o.CACR0.Reg)&^(0x1)|value)
}
func (o *CAC_Type) GetCACR0_CFME() uint8 {
	return volatile.LoadUint8(&o.CACR0.Reg) & 0x1
}

// CAC.CACR1: CAC Control Register 1
func (o *CAC_Type) SetCACR1_CACREFE(value uint8) {
	volatile.StoreUint8(&o.CACR1.Reg, volatile.LoadUint8(&o.CACR1.Reg)&^(0x1)|value)
}
func (o *CAC_Type) GetCACR1_CACREFE() uint8 {
	return volatile.LoadUint8(&o.CACR1.Reg) & 0x1
}
func (o *CAC_Type) SetCACR1_FMCS(value uint8) {
	volatile.StoreUint8(&o.CACR1.Reg, volatile.LoadUint8(&o.CACR1.Reg)&^(0xe)|value<<1)
}
func (o *CAC_Type) GetCACR1_FMCS() uint8 {
	return (volatile.LoadUint8(&o.CACR1.Reg) & 0xe) >> 1
}
func (o *CAC_Type) SetCACR1_TCSS(value uint8) {
	volatile.StoreUint8(&o.CACR1.Reg, volatile.LoadUint8(&o.CACR1.Reg)&^(0x30)|value<<4)
}
func (o *CAC_Type) GetCACR1_TCSS() uint8 {
	return (volatile.LoadUint8(&o.CACR1.Reg) & 0x30) >> 4
}
func (o *CAC_Type) SetCACR1_EDGES(value uint8) {
	volatile.StoreUint8(&o.CACR1.Reg, volatile.LoadUint8(&o.CACR1.Reg)&^(0xc0)|value<<6)
}
func (o *CAC_Type) GetCACR1_EDGES() uint8 {
	return (volatile.LoadUint8(&o.CACR1.Reg) & 0xc0) >> 6
}

// CAC.CACR2: CAC Control Register 2
func (o *CAC_Type) SetCACR2_RPS(value uint8) {
	volatile.StoreUint8(&o.CACR2.Reg, volatile.LoadUint8(&o.CACR2.Reg)&^(0x1)|value)
}
func (o *CAC_Type) GetCACR2_RPS() uint8 {
	return volatile.LoadUint8(&o.CACR2.Reg) & 0x1
}
func (o *CAC_Type) SetCACR2_RSCS(value uint8) {
	volatile.StoreUint8(&o.CACR2.Reg, volatile.LoadUint8(&o.CACR2.Reg)&^(0xe)|value<<1)
}
func (o *CAC_Type) GetCACR2_RSCS() uint8 {
	return (volatile.LoadUint8(&o.CACR2.Reg) & 0xe) >> 1
}
func (o *CAC_Type) SetCACR2_RCDS(value uint8) {
	volatile.StoreUint8(&o.CACR2.Reg, volatile.LoadUint8(&o.CACR2.Reg)&^(0x30)|value<<4)
}
func (o *CAC_Type) GetCACR2_RCDS() uint8 {
	return (volatile.LoadUint8(&o.CACR2.Reg) & 0x30) >> 4
}
func (o *CAC_Type) SetCACR2_DFS(value uint8) {
	volatile.StoreUint8(&o.CACR2.Reg, volatile.LoadUint8(&o.CACR2.Reg)&^(0xc0)|value<<6)
}
func (o *CAC_Type) GetCACR2_DFS() uint8 {
	return (volatile.LoadUint8(&o.CACR2.Reg) & 0xc0) >> 6
}

// CAC.CAICR: CAC Interrupt Control Register
func (o *CAC_Type) SetCAICR_FERRIE(value uint8) {
	volatile.StoreUint8(&o.CAICR.Reg, volatile.LoadUint8(&o.CAICR.Reg)&^(0x1)|value)
}
func (o *CAC_Type) GetCAICR_FERRIE() uint8 {
	return volatile.LoadUint8(&o.CAICR.Reg) & 0x1
}
func (o *CAC_Type) SetCAICR_MENDIE(value uint8) {
	volatile.StoreUint8(&o.CAICR.Reg, volatile.LoadUint8(&o.CAICR.Reg)&^(0x2)|value<<1)
}
func (o *CAC_Type) GetCAICR_MENDIE() uint8 {
	return (volatile.LoadUint8(&o.CAICR.Reg) & 0x2) >> 1
}
func (o *CAC_Type) SetCAICR_OVFIE(value uint8) {
	volatile.StoreUint8(&o.CAICR.Reg, volatile.LoadUint8(&o.CAICR.Reg)&^(0x4)|value<<2)
}
func (o *CAC_Type) GetCAICR_OVFIE() uint8 {
	return (volatile.LoadUint8(&o.CAICR.Reg) & 0x4) >> 2
}
func (o *CAC_Type) SetCAICR_FERRFCL(value uint8) {
	volatile.StoreUint8(&o.CAICR.Reg, volatile.LoadUint8(&o.CAICR.Reg)&^(0x10)|value<<4)
}
func (o *CAC_Type) GetCAICR_FERRFCL() uint8 {
	return (volatile.LoadUint8(&o.CAICR.Reg) & 0x10) >> 4
}
func (o *CAC_Type) SetCAICR_MENDFCL(value uint8) {
	volatile.StoreUint8(&o.CAICR.Reg, volatile.LoadUint8(&o.CAICR.Reg)&^(0x20)|value<<5)
}
func (o *CAC_Type) GetCAICR_MENDFCL() uint8 {
	return (volatile.LoadUint8(&o.CAICR.Reg) & 0x20) >> 5
}
func (o *CAC_Type) SetCAICR_OVFFCL(value uint8) {
	volatile.StoreUint8(&o.CAICR.Reg, volatile.LoadUint8(&o.CAICR.Reg)&^(0x40)|value<<6)
}
func (o *CAC_Type) GetCAICR_OVFFCL() uint8 {
	return (volatile.LoadUint8(&o.CAICR.Reg) & 0x40) >> 6
}

// CAC.CASTR: CAC Status Register
func (o *CAC_Type) SetCASTR_FERRF(value uint8) {
	volatile.StoreUint8(&o.CASTR.Reg, volatile.LoadUint8(&o.CASTR.Reg)&^(0x1)|value)
}
func (o *CAC_Type) GetCASTR_FERRF() uint8 {
	return volatile.LoadUint8(&o.CASTR.Reg) & 0x1
}
func (o *CAC_Type) SetCASTR_MENDF(value uint8) {
	volatile.StoreUint8(&o.CASTR.Reg, volatile.LoadUint8(&o.CASTR.Reg)&^(0x2)|value<<1)
}
func (o *CAC_Type) GetCASTR_MENDF() uint8 {
	return (volatile.LoadUint8(&o.CASTR.Reg) & 0x2) >> 1
}
func (o *CAC_Type) SetCASTR_OVFF(value uint8) {
	volatile.StoreUint8(&o.CASTR.Reg, volatile.LoadUint8(&o.CASTR.Reg)&^(0x4)|value<<2)
}
func (o *CAC_Type) GetCASTR_OVFF() uint8 {
	return (volatile.LoadUint8(&o.CASTR.Reg) & 0x4) >> 2
}

// Module Stop Control
type MSTP_Type struct {
	MSTPCRA volatile.Register32 // 0x0
	MSTPCRB volatile.Register32 // 0x4
	MSTPCRC volatile.Register32 // 0x8
	MSTPCRD volatile.Register32 // 0xC
	MSTPCRE volatile.Register32 // 0x10
}

// MSTP.MSTPCRA: Module Stop Control Register A
func (o *MSTP_Type) SetMSTPCRA_MSTPA0(value uint32) {
	volatile.StoreUint32(&o.MSTPCRA.Reg, volatile.LoadUint32(&o.MSTPCRA.Reg)&^(0x1)|value)
}
func (o *MSTP_Type) GetMSTPCRA_MSTPA0() uint32 {
	return volatile.LoadUint32(&o.MSTPCRA.Reg) & 0x1
}
func (o *MSTP_Type) SetMSTPCRA_MSTPA7(value uint32) {
	volatile.StoreUint32(&o.MSTPCRA.Reg, volatile.LoadUint32(&o.MSTPCRA.Reg)&^(0x80)|value<<7)
}
func (o *MSTP_Type) GetMSTPCRA_MSTPA7() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRA.Reg) & 0x80) >> 7
}
func (o *MSTP_Type) SetMSTPCRA_MSTPA22(value uint32) {
	volatile.StoreUint32(&o.MSTPCRA.Reg, volatile.LoadUint32(&o.MSTPCRA.Reg)&^(0x400000)|value<<22)
}
func (o *MSTP_Type) GetMSTPCRA_MSTPA22() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRA.Reg) & 0x400000) >> 22
}

// MSTP.MSTPCRB: Module Stop Control Register B
func (o *MSTP_Type) SetMSTPCRB_MSTPB3(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x8)|value<<3)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB3() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x8) >> 3
}
func (o *MSTP_Type) SetMSTPCRB_MSTPB4(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x10)|value<<4)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB4() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x10) >> 4
}
func (o *MSTP_Type) SetMSTPCRB_MSTPB6(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x40)|value<<6)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB6() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x40) >> 6
}
func (o *MSTP_Type) SetMSTPCRB_MSTPB11(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x800)|value<<11)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB11() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x800) >> 11
}
func (o *MSTP_Type) SetMSTPCRB_MSTPB18(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x40000)|value<<18)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB18() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x40000) >> 18
}
func (o *MSTP_Type) SetMSTPCRB_MSTPB19(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x80000)|value<<19)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB19() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x80000) >> 19
}
func (o *MSTP_Type) SetMSTPCRB_MSTPB22(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x400000)|value<<22)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB22() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x400000) >> 22
}
func (o *MSTP_Type) SetMSTPCRB_MSTPB31(value uint32) {
	volatile.StoreUint32(&o.MSTPCRB.Reg, volatile.LoadUint32(&o.MSTPCRB.Reg)&^(0x80000000)|value<<31)
}
func (o *MSTP_Type) GetMSTPCRB_MSTPB31() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRB.Reg) & 0x80000000) >> 31
}

// MSTP.MSTPCRC: Module Stop Control Register C
func (o *MSTP_Type) SetMSTPCRC_MSTPC0(value uint32) {
	volatile.StoreUint32(&o.MSTPCRC.Reg, volatile.LoadUint32(&o.MSTPCRC.Reg)&^(0x1)|value)
}
func (o *MSTP_Type) GetMSTPCRC_MSTPC0() uint32 {
	return volatile.LoadUint32(&o.MSTPCRC.Reg) & 0x1
}
func (o *MSTP_Type) SetMSTPCRC_MSTPC1(value uint32) {
	volatile.StoreUint32(&o.MSTPCRC.Reg, volatile.LoadUint32(&o.MSTPCRC.Reg)&^(0x2)|value<<1)
}
func (o *MSTP_Type) GetMSTPCRC_MSTPC1() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRC.Reg) & 0x2) >> 1
}
func (o *MSTP_Type) SetMSTPCRC_MSTPC8(value uint32) {
	volatile.StoreUint32(&o.MSTPCRC.Reg, volatile.LoadUint32(&o.MSTPCRC.Reg)&^(0x100)|value<<8)
}
func (o *MSTP_Type) GetMSTPCRC_MSTPC8() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRC.Reg) & 0x100) >> 8
}
func (o *MSTP_Type) SetMSTPCRC_MSTPC13(value uint32) {
	volatile.StoreUint32(&o.MSTPCRC.Reg, volatile.LoadUint32(&o.MSTPCRC.Reg)&^(0x2000)|value<<13)
}
func (o *MSTP_Type) GetMSTPCRC_MSTPC13() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRC.Reg) & 0x2000) >> 13
}
func (o *MSTP_Type) SetMSTPCRC_MSTPC14(value uint32) {
	volatile.StoreUint32(&o.MSTPCRC.Reg, volatile.LoadUint32(&o.MSTPCRC.Reg)&^(0x4000)|value<<14)
}
func (o *MSTP_Type) GetMSTPCRC_MSTPC14() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRC.Reg) & 0x4000) >> 14
}
func (o *MSTP_Type) SetMSTPCRC_MSTPC27(value uint32) {
	volatile.StoreUint32(&o.MSTPCRC.Reg, volatile.LoadUint32(&o.MSTPCRC.Reg)&^(0x8000000)|value<<27)
}
func (o *MSTP_Type) GetMSTPCRC_MSTPC27() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRC.Reg) & 0x8000000) >> 27
}
func (o *MSTP_Type) SetMSTPCRC_MSTPC28(value uint32) {
	volatile.StoreUint32(&o.MSTPCRC.Reg, volatile.LoadUint32(&o.MSTPCRC.Reg)&^(0x10000000)|value<<28)
}
func (o *MSTP_Type) GetMSTPCRC_MSTPC28() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRC.Reg) & 0x10000000) >> 28
}

// MSTP.MSTPCRD: Module Stop Control Register D
func (o *MSTP_Type) SetMSTPCRD_MSTPD2(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x4)|value<<2)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD2() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x4) >> 2
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD3(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x8)|value<<3)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD3() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x8) >> 3
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD11(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x800)|value<<11)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD11() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x800) >> 11
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD12(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x1000)|value<<12)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD12() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x1000) >> 12
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD13(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x2000)|value<<13)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD13() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x2000) >> 13
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD14(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x4000)|value<<14)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD14() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x4000) >> 14
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD16(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x10000)|value<<16)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD16() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x10000) >> 16
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD20(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x100000)|value<<20)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD20() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x100000) >> 20
}
func (o *MSTP_Type) SetMSTPCRD_MSTPD22(value uint32) {
	volatile.StoreUint32(&o.MSTPCRD.Reg, volatile.LoadUint32(&o.MSTPCRD.Reg)&^(0x400000)|value<<22)
}
func (o *MSTP_Type) GetMSTPCRD_MSTPD22() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRD.Reg) & 0x400000) >> 22
}

// MSTP.MSTPCRE: Module Stop Control Register E
func (o *MSTP_Type) SetMSTPCRE_MSTPE26(value uint32) {
	volatile.StoreUint32(&o.MSTPCRE.Reg, volatile.LoadUint32(&o.MSTPCRE.Reg)&^(0x4000000)|value<<26)
}
func (o *MSTP_Type) GetMSTPCRE_MSTPE26() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRE.Reg) & 0x4000000) >> 26
}
func (o *MSTP_Type) SetMSTPCRE_MSTPE27(value uint32) {
	volatile.StoreUint32(&o.MSTPCRE.Reg, volatile.LoadUint32(&o.MSTPCRE.Reg)&^(0x8000000)|value<<27)
}
func (o *MSTP_Type) GetMSTPCRE_MSTPE27() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRE.Reg) & 0x8000000) >> 27
}
func (o *MSTP_Type) SetMSTPCRE_MSTPE28(value uint32) {
	volatile.StoreUint32(&o.MSTPCRE.Reg, volatile.LoadUint32(&o.MSTPCRE.Reg)&^(0x10000000)|value<<28)
}
func (o *MSTP_Type) GetMSTPCRE_MSTPE28() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRE.Reg) & 0x10000000) >> 28
}
func (o *MSTP_Type) SetMSTPCRE_MSTPE29(value uint32) {
	volatile.StoreUint32(&o.MSTPCRE.Reg, volatile.LoadUint32(&o.MSTPCRE.Reg)&^(0x20000000)|value<<29)
}
func (o *MSTP_Type) GetMSTPCRE_MSTPE29() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRE.Reg) & 0x20000000) >> 29
}
func (o *MSTP_Type) SetMSTPCRE_MSTPE30(value uint32) {
	volatile.StoreUint32(&o.MSTPCRE.Reg, volatile.LoadUint32(&o.MSTPCRE.Reg)&^(0x40000000)|value<<30)
}
func (o *MSTP_Type) GetMSTPCRE_MSTPE30() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRE.Reg) & 0x40000000) >> 30
}
func (o *MSTP_Type) SetMSTPCRE_MSTPE31(value uint32) {
	volatile.StoreUint32(&o.MSTPCRE.Reg, volatile.LoadUint32(&o.MSTPCRE.Reg)&^(0x80000000)|value<<31)
}
func (o *MSTP_Type) GetMSTPCRE_MSTPE31() uint32 {
	return (volatile.LoadUint32(&o.MSTPCRE.Reg) & 0x80000000) >> 31
}

// Port Output Enable Module for GPT
type POEG_Type struct {
	POEGGA volatile.Register32 // 0x0
	_      [252]byte
	POEGGB volatile.Register32 // 0x100
	_      [252]byte
	POEGGC volatile.Register32 // 0x200
	_      [252]byte
	POEGGD volatile.Register32 // 0x300
}

// POEG.POEGGA: POEG Group A Setting Register
func (o *POEG_Type) SetPOEGGA_PIDF(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x1)|value)
}
func (o *POEG_Type) GetPOEGGA_PIDF() uint32 {
	return volatile.LoadUint32(&o.POEGGA.Reg) & 0x1
}
func (o *POEG_Type) SetPOEGGA_IOCF(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x2)|value<<1)
}
func (o *POEG_Type) GetPOEGGA_IOCF() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x2) >> 1
}
func (o *POEG_Type) SetPOEGGA_OSTPF(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x4)|value<<2)
}
func (o *POEG_Type) GetPOEGGA_OSTPF() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x4) >> 2
}
func (o *POEG_Type) SetPOEGGA_SSF(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x8)|value<<3)
}
func (o *POEG_Type) GetPOEGGA_SSF() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x8) >> 3
}
func (o *POEG_Type) SetPOEGGA_PIDE(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x10)|value<<4)
}
func (o *POEG_Type) GetPOEGGA_PIDE() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x10) >> 4
}
func (o *POEG_Type) SetPOEGGA_IOCE(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x20)|value<<5)
}
func (o *POEG_Type) GetPOEGGA_IOCE() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x20) >> 5
}
func (o *POEG_Type) SetPOEGGA_OSTPE(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x40)|value<<6)
}
func (o *POEG_Type) GetPOEGGA_OSTPE() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x40) >> 6
}
func (o *POEG_Type) SetPOEGGA_ST(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x10000)|value<<16)
}
func (o *POEG_Type) GetPOEGGA_ST() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x10000) >> 16
}
func (o *POEG_Type) SetPOEGGA_INV(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x10000000)|value<<28)
}
func (o *POEG_Type) GetPOEGGA_INV() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x10000000) >> 28
}
func (o *POEG_Type) SetPOEGGA_NFEN(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0x20000000)|value<<29)
}
func (o *POEG_Type) GetPOEGGA_NFEN() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0x20000000) >> 29
}
func (o *POEG_Type) SetPOEGGA_NFCS(value uint32) {
	volatile.StoreUint32(&o.POEGGA.Reg, volatile.LoadUint32(&o.POEGGA.Reg)&^(0xc0000000)|value<<30)
}
func (o *POEG_Type) GetPOEGGA_NFCS() uint32 {
	return (volatile.LoadUint32(&o.POEGGA.Reg) & 0xc0000000) >> 30
}

// POEG.POEGGB: POEG Group B Setting Register
func (o *POEG_Type) SetPOEGGB_PIDF(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x1)|value)
}
func (o *POEG_Type) GetPOEGGB_PIDF() uint32 {
	return volatile.LoadUint32(&o.POEGGB.Reg) & 0x1
}
func (o *POEG_Type) SetPOEGGB_IOCF(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x2)|value<<1)
}
func (o *POEG_Type) GetPOEGGB_IOCF() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x2) >> 1
}
func (o *POEG_Type) SetPOEGGB_OSTPF(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x4)|value<<2)
}
func (o *POEG_Type) GetPOEGGB_OSTPF() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x4) >> 2
}
func (o *POEG_Type) SetPOEGGB_SSF(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x8)|value<<3)
}
func (o *POEG_Type) GetPOEGGB_SSF() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x8) >> 3
}
func (o *POEG_Type) SetPOEGGB_PIDE(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x10)|value<<4)
}
func (o *POEG_Type) GetPOEGGB_PIDE() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x10) >> 4
}
func (o *POEG_Type) SetPOEGGB_IOCE(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x20)|value<<5)
}
func (o *POEG_Type) GetPOEGGB_IOCE() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x20) >> 5
}
func (o *POEG_Type) SetPOEGGB_OSTPE(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x40)|value<<6)
}
func (o *POEG_Type) GetPOEGGB_OSTPE() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x40) >> 6
}
func (o *POEG_Type) SetPOEGGB_ST(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x10000)|value<<16)
}
func (o *POEG_Type) GetPOEGGB_ST() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x10000) >> 16
}
func (o *POEG_Type) SetPOEGGB_INV(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x10000000)|value<<28)
}
func (o *POEG_Type) GetPOEGGB_INV() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x10000000) >> 28
}
func (o *POEG_Type) SetPOEGGB_NFEN(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0x20000000)|value<<29)
}
func (o *POEG_Type) GetPOEGGB_NFEN() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0x20000000) >> 29
}
func (o *POEG_Type) SetPOEGGB_NFCS(value uint32) {
	volatile.StoreUint32(&o.POEGGB.Reg, volatile.LoadUint32(&o.POEGGB.Reg)&^(0xc0000000)|value<<30)
}
func (o *POEG_Type) GetPOEGGB_NFCS() uint32 {
	return (volatile.LoadUint32(&o.POEGGB.Reg) & 0xc0000000) >> 30
}

// POEG.POEGGC: POEG Group C Setting Register
func (o *POEG_Type) SetPOEGGC_PIDF(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x1)|value)
}
func (o *POEG_Type) GetPOEGGC_PIDF() uint32 {
	return volatile.LoadUint32(&o.POEGGC.Reg) & 0x1
}
func (o *POEG_Type) SetPOEGGC_IOCF(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x2)|value<<1)
}
func (o *POEG_Type) GetPOEGGC_IOCF() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x2) >> 1
}
func (o *POEG_Type) SetPOEGGC_OSTPF(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x4)|value<<2)
}
func (o *POEG_Type) GetPOEGGC_OSTPF() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x4) >> 2
}
func (o *POEG_Type) SetPOEGGC_SSF(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x8)|value<<3)
}
func (o *POEG_Type) GetPOEGGC_SSF() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x8) >> 3
}
func (o *POEG_Type) SetPOEGGC_PIDE(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x10)|value<<4)
}
func (o *POEG_Type) GetPOEGGC_PIDE() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x10) >> 4
}
func (o *POEG_Type) SetPOEGGC_IOCE(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x20)|value<<5)
}
func (o *POEG_Type) GetPOEGGC_IOCE() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x20) >> 5
}
func (o *POEG_Type) SetPOEGGC_OSTPE(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x40)|value<<6)
}
func (o *POEG_Type) GetPOEGGC_OSTPE() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x40) >> 6
}
func (o *POEG_Type) SetPOEGGC_ST(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x10000)|value<<16)
}
func (o *POEG_Type) GetPOEGGC_ST() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x10000) >> 16
}
func (o *POEG_Type) SetPOEGGC_INV(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x10000000)|value<<28)
}
func (o *POEG_Type) GetPOEGGC_INV() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x10000000) >> 28
}
func (o *POEG_Type) SetPOEGGC_NFEN(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0x20000000)|value<<29)
}
func (o *POEG_Type) GetPOEGGC_NFEN() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0x20000000) >> 29
}
func (o *POEG_Type) SetPOEGGC_NFCS(value uint32) {
	volatile.StoreUint32(&o.POEGGC.Reg, volatile.LoadUint32(&o.POEGGC.Reg)&^(0xc0000000)|value<<30)
}
func (o *POEG_Type) GetPOEGGC_NFCS() uint32 {
	return (volatile.LoadUint32(&o.POEGGC.Reg) & 0xc0000000) >> 30
}

// POEG.POEGGD: POEG Group D Setting Register
func (o *POEG_Type) SetPOEGGD_PIDF(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x1)|value)
}
func (o *POEG_Type) GetPOEGGD_PIDF() uint32 {
	return volatile.LoadUint32(&o.POEGGD.Reg) & 0x1
}
func (o *POEG_Type) SetPOEGGD_IOCF(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x2)|value<<1)
}
func (o *POEG_Type) GetPOEGGD_IOCF() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x2) >> 1
}
func (o *POEG_Type) SetPOEGGD_OSTPF(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x4)|value<<2)
}
func (o *POEG_Type) GetPOEGGD_OSTPF() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x4) >> 2
}
func (o *POEG_Type) SetPOEGGD_SSF(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x8)|value<<3)
}
func (o *POEG_Type) GetPOEGGD_SSF() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x8) >> 3
}
func (o *POEG_Type) SetPOEGGD_PIDE(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x10)|value<<4)
}
func (o *POEG_Type) GetPOEGGD_PIDE() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x10) >> 4
}
func (o *POEG_Type) SetPOEGGD_IOCE(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x20)|value<<5)
}
func (o *POEG_Type) GetPOEGGD_IOCE() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x20) >> 5
}
func (o *POEG_Type) SetPOEGGD_OSTPE(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x40)|value<<6)
}
func (o *POEG_Type) GetPOEGGD_OSTPE() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x40) >> 6
}
func (o *POEG_Type) SetPOEGGD_ST(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x10000)|value<<16)
}
func (o *POEG_Type) GetPOEGGD_ST() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x10000) >> 16
}
func (o *POEG_Type) SetPOEGGD_INV(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x10000000)|value<<28)
}
func (o *POEG_Type) GetPOEGGD_INV() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x10000000) >> 28
}
func (o *POEG_Type) SetPOEGGD_NFEN(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0x20000000)|value<<29)
}
func (o *POEG_Type) GetPOEGGD_NFEN() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0x20000000) >> 29
}
func (o *POEG_Type) SetPOEGGD_NFCS(value uint32) {
	volatile.StoreUint32(&o.POEGGD.Reg, volatile.LoadUint32(&o.POEGGD.Reg)&^(0xc0000000)|value<<30)
}
func (o *POEG_Type) GetPOEGGD_NFCS() uint32 {
	return (volatile.LoadUint32(&o.POEGGD.Reg) & 0xc0000000) >> 30
}

// USB 2.0 Full-Speed Module
type USBFS_Type struct {
	SYSCFG    volatile.Register16 // 0x0
	_         [2]byte
	SYSSTS0   volatile.Register16 // 0x4
	_         [2]byte
	DVSTCTR0  volatile.Register16 // 0x8
	_         [10]byte
	CFIFO     volatile.Register16 // 0x14
	_         [10]byte
	CFIFOSEL  volatile.Register16 // 0x20
	CFIFOCTR  volatile.Register16 // 0x22
	_         [12]byte
	INTENB0   volatile.Register16 // 0x30
	_         [4]byte
	BRDYENB   volatile.Register16 // 0x36
	NRDYENB   volatile.Register16 // 0x38
	BEMPENB   volatile.Register16 // 0x3A
	SOFCFG    volatile.Register16 // 0x3C
	_         [2]byte
	INTSTS0   volatile.Register16 // 0x40
	_         [4]byte
	BRDYSTS   volatile.Register16 // 0x46
	NRDYSTS   volatile.Register16 // 0x48
	BEMPSTS   volatile.Register16 // 0x4A
	FRMNUM    volatile.Register16 // 0x4C
	DVCHGR    volatile.Register16 // 0x4E
	USBADDR   volatile.Register16 // 0x50
	_         [2]byte
	USBREQ    volatile.Register16 // 0x54
	USBVAL    volatile.Register16 // 0x56
	USBINDX   volatile.Register16 // 0x58
	USBLENG   volatile.Register16 // 0x5A
	DCPCFG    volatile.Register16 // 0x5C
	DCPMAXP   volatile.Register16 // 0x5E
	DCPCTR    volatile.Register16 // 0x60
	_         [2]byte
	PIPESEL   volatile.Register16 // 0x64
	_         [2]byte
	PIPECFG   volatile.Register16 // 0x68
	_         [2]byte
	PIPEMAXP  volatile.Register16 // 0x6C
	_         [8]byte
	PIPE4CTR  volatile.Register16 // 0x76
	PIPE5CTR  volatile.Register16 // 0x78
	PIPE6CTR  volatile.Register16 // 0x7A
	PIPE7CTR  volatile.Register16 // 0x7C
	_         [30]byte
	PIPE4TRE  volatile.Register16 // 0x9C
	PIPE4TRN  volatile.Register16 // 0x9E
	PIPE5TRE  volatile.Register16 // 0xA0
	PIPE5TRN  volatile.Register16 // 0xA2
	_         [80]byte
	PHYSECTRL volatile.Register32 // 0xF4
	_         [776]byte
	DPUSR0R   volatile.Register32 // 0x400
	DPUSR1R   volatile.Register32 // 0x404
}

// USBFS.SYSCFG: System Configuration Control Register
func (o *USBFS_Type) SetSYSCFG_USBE(value uint16) {
	volatile.StoreUint16(&o.SYSCFG.Reg, volatile.LoadUint16(&o.SYSCFG.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetSYSCFG_USBE() uint16 {
	return volatile.LoadUint16(&o.SYSCFG.Reg) & 0x1
}
func (o *USBFS_Type) SetSYSCFG_DPRPU(value uint16) {
	volatile.StoreUint16(&o.SYSCFG.Reg, volatile.LoadUint16(&o.SYSCFG.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetSYSCFG_DPRPU() uint16 {
	return (volatile.LoadUint16(&o.SYSCFG.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetSYSCFG_SCKE(value uint16) {
	volatile.StoreUint16(&o.SYSCFG.Reg, volatile.LoadUint16(&o.SYSCFG.Reg)&^(0x400)|value<<10)
}
func (o *USBFS_Type) GetSYSCFG_SCKE() uint16 {
	return (volatile.LoadUint16(&o.SYSCFG.Reg) & 0x400) >> 10
}

// USBFS.SYSSTS0: System Configuration Status Register 0
func (o *USBFS_Type) SetSYSSTS0_LNST(value uint16) {
	volatile.StoreUint16(&o.SYSSTS0.Reg, volatile.LoadUint16(&o.SYSSTS0.Reg)&^(0x3)|value)
}
func (o *USBFS_Type) GetSYSSTS0_LNST() uint16 {
	return volatile.LoadUint16(&o.SYSSTS0.Reg) & 0x3
}

// USBFS.DVSTCTR0: Device State Control Register 0
func (o *USBFS_Type) SetDVSTCTR0_RHST(value uint16) {
	volatile.StoreUint16(&o.DVSTCTR0.Reg, volatile.LoadUint16(&o.DVSTCTR0.Reg)&^(0x7)|value)
}
func (o *USBFS_Type) GetDVSTCTR0_RHST() uint16 {
	return volatile.LoadUint16(&o.DVSTCTR0.Reg) & 0x7
}
func (o *USBFS_Type) SetDVSTCTR0_WKUP(value uint16) {
	volatile.StoreUint16(&o.DVSTCTR0.Reg, volatile.LoadUint16(&o.DVSTCTR0.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetDVSTCTR0_WKUP() uint16 {
	return (volatile.LoadUint16(&o.DVSTCTR0.Reg) & 0x100) >> 8
}

// USBFS.CFIFO: CFIFO Port Register
func (o *USBFS_Type) SetCFIFO(value uint16) {
	volatile.StoreUint16(&o.CFIFO.Reg, value)
}
func (o *USBFS_Type) GetCFIFO() uint16 {
	return volatile.LoadUint16(&o.CFIFO.Reg)
}

// USBFS.CFIFOSEL: CFIFO Port Select Register
func (o *USBFS_Type) SetCFIFOSEL_CURPIPE(value uint16) {
	volatile.StoreUint16(&o.CFIFOSEL.Reg, volatile.LoadUint16(&o.CFIFOSEL.Reg)&^(0xf)|value)
}
func (o *USBFS_Type) GetCFIFOSEL_CURPIPE() uint16 {
	return volatile.LoadUint16(&o.CFIFOSEL.Reg) & 0xf
}
func (o *USBFS_Type) SetCFIFOSEL_ISEL(value uint16) {
	volatile.StoreUint16(&o.CFIFOSEL.Reg, volatile.LoadUint16(&o.CFIFOSEL.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetCFIFOSEL_ISEL() uint16 {
	return (volatile.LoadUint16(&o.CFIFOSEL.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetCFIFOSEL_BIGEND(value uint16) {
	volatile.StoreUint16(&o.CFIFOSEL.Reg, volatile.LoadUint16(&o.CFIFOSEL.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetCFIFOSEL_BIGEND() uint16 {
	return (volatile.LoadUint16(&o.CFIFOSEL.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetCFIFOSEL_MBW(value uint16) {
	volatile.StoreUint16(&o.CFIFOSEL.Reg, volatile.LoadUint16(&o.CFIFOSEL.Reg)&^(0x400)|value<<10)
}
func (o *USBFS_Type) GetCFIFOSEL_MBW() uint16 {
	return (volatile.LoadUint16(&o.CFIFOSEL.Reg) & 0x400) >> 10
}
func (o *USBFS_Type) SetCFIFOSEL_REW(value uint16) {
	volatile.StoreUint16(&o.CFIFOSEL.Reg, volatile.LoadUint16(&o.CFIFOSEL.Reg)&^(0x4000)|value<<14)
}
func (o *USBFS_Type) GetCFIFOSEL_REW() uint16 {
	return (volatile.LoadUint16(&o.CFIFOSEL.Reg) & 0x4000) >> 14
}
func (o *USBFS_Type) SetCFIFOSEL_RCNT(value uint16) {
	volatile.StoreUint16(&o.CFIFOSEL.Reg, volatile.LoadUint16(&o.CFIFOSEL.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetCFIFOSEL_RCNT() uint16 {
	return (volatile.LoadUint16(&o.CFIFOSEL.Reg) & 0x8000) >> 15
}

// USBFS.CFIFOCTR: CFIFO Port Control Register
func (o *USBFS_Type) SetCFIFOCTR_DTLN(value uint16) {
	volatile.StoreUint16(&o.CFIFOCTR.Reg, volatile.LoadUint16(&o.CFIFOCTR.Reg)&^(0x1ff)|value)
}
func (o *USBFS_Type) GetCFIFOCTR_DTLN() uint16 {
	return volatile.LoadUint16(&o.CFIFOCTR.Reg) & 0x1ff
}
func (o *USBFS_Type) SetCFIFOCTR_FRDY(value uint16) {
	volatile.StoreUint16(&o.CFIFOCTR.Reg, volatile.LoadUint16(&o.CFIFOCTR.Reg)&^(0x2000)|value<<13)
}
func (o *USBFS_Type) GetCFIFOCTR_FRDY() uint16 {
	return (volatile.LoadUint16(&o.CFIFOCTR.Reg) & 0x2000) >> 13
}
func (o *USBFS_Type) SetCFIFOCTR_BCLR(value uint16) {
	volatile.StoreUint16(&o.CFIFOCTR.Reg, volatile.LoadUint16(&o.CFIFOCTR.Reg)&^(0x4000)|value<<14)
}
func (o *USBFS_Type) GetCFIFOCTR_BCLR() uint16 {
	return (volatile.LoadUint16(&o.CFIFOCTR.Reg) & 0x4000) >> 14
}
func (o *USBFS_Type) SetCFIFOCTR_BVAL(value uint16) {
	volatile.StoreUint16(&o.CFIFOCTR.Reg, volatile.LoadUint16(&o.CFIFOCTR.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetCFIFOCTR_BVAL() uint16 {
	return (volatile.LoadUint16(&o.CFIFOCTR.Reg) & 0x8000) >> 15
}

// USBFS.INTENB0: Interrupt Enable Register 0
func (o *USBFS_Type) SetINTENB0_BRDYE(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetINTENB0_BRDYE() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetINTENB0_NRDYE(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetINTENB0_NRDYE() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x200) >> 9
}
func (o *USBFS_Type) SetINTENB0_BEMPE(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x400)|value<<10)
}
func (o *USBFS_Type) GetINTENB0_BEMPE() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x400) >> 10
}
func (o *USBFS_Type) SetINTENB0_CTRE(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x800)|value<<11)
}
func (o *USBFS_Type) GetINTENB0_CTRE() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x800) >> 11
}
func (o *USBFS_Type) SetINTENB0_DVSE(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x1000)|value<<12)
}
func (o *USBFS_Type) GetINTENB0_DVSE() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x1000) >> 12
}
func (o *USBFS_Type) SetINTENB0_SOFE(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x2000)|value<<13)
}
func (o *USBFS_Type) GetINTENB0_SOFE() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x2000) >> 13
}
func (o *USBFS_Type) SetINTENB0_RSME(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x4000)|value<<14)
}
func (o *USBFS_Type) GetINTENB0_RSME() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x4000) >> 14
}
func (o *USBFS_Type) SetINTENB0_VBSE(value uint16) {
	volatile.StoreUint16(&o.INTENB0.Reg, volatile.LoadUint16(&o.INTENB0.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetINTENB0_VBSE() uint16 {
	return (volatile.LoadUint16(&o.INTENB0.Reg) & 0x8000) >> 15
}

// USBFS.BRDYENB: BRDY Interrupt Enable Register
func (o *USBFS_Type) SetBRDYENB_PIPE0BRDYE(value uint16) {
	volatile.StoreUint16(&o.BRDYENB.Reg, volatile.LoadUint16(&o.BRDYENB.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetBRDYENB_PIPE0BRDYE() uint16 {
	return volatile.LoadUint16(&o.BRDYENB.Reg) & 0x1
}
func (o *USBFS_Type) SetBRDYENB_PIPE4BRDYE(value uint16) {
	volatile.StoreUint16(&o.BRDYENB.Reg, volatile.LoadUint16(&o.BRDYENB.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetBRDYENB_PIPE4BRDYE() uint16 {
	return (volatile.LoadUint16(&o.BRDYENB.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetBRDYENB_PIPE5BRDYE(value uint16) {
	volatile.StoreUint16(&o.BRDYENB.Reg, volatile.LoadUint16(&o.BRDYENB.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetBRDYENB_PIPE5BRDYE() uint16 {
	return (volatile.LoadUint16(&o.BRDYENB.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetBRDYENB_PIPE6BRDYE(value uint16) {
	volatile.StoreUint16(&o.BRDYENB.Reg, volatile.LoadUint16(&o.BRDYENB.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetBRDYENB_PIPE6BRDYE() uint16 {
	return (volatile.LoadUint16(&o.BRDYENB.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetBRDYENB_PIPE7BRDYE(value uint16) {
	volatile.StoreUint16(&o.BRDYENB.Reg, volatile.LoadUint16(&o.BRDYENB.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetBRDYENB_PIPE7BRDYE() uint16 {
	return (volatile.LoadUint16(&o.BRDYENB.Reg) & 0x80) >> 7
}

// USBFS.NRDYENB: NRDY Interrupt Enable Register
func (o *USBFS_Type) SetNRDYENB_PIPE0NRDYE(value uint16) {
	volatile.StoreUint16(&o.NRDYENB.Reg, volatile.LoadUint16(&o.NRDYENB.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetNRDYENB_PIPE0NRDYE() uint16 {
	return volatile.LoadUint16(&o.NRDYENB.Reg) & 0x1
}
func (o *USBFS_Type) SetNRDYENB_PIPE4NRDYE(value uint16) {
	volatile.StoreUint16(&o.NRDYENB.Reg, volatile.LoadUint16(&o.NRDYENB.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetNRDYENB_PIPE4NRDYE() uint16 {
	return (volatile.LoadUint16(&o.NRDYENB.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetNRDYENB_PIPE5NRDYE(value uint16) {
	volatile.StoreUint16(&o.NRDYENB.Reg, volatile.LoadUint16(&o.NRDYENB.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetNRDYENB_PIPE5NRDYE() uint16 {
	return (volatile.LoadUint16(&o.NRDYENB.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetNRDYENB_PIPE6NRDYE(value uint16) {
	volatile.StoreUint16(&o.NRDYENB.Reg, volatile.LoadUint16(&o.NRDYENB.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetNRDYENB_PIPE6NRDYE() uint16 {
	return (volatile.LoadUint16(&o.NRDYENB.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetNRDYENB_PIPE7NRDYE(value uint16) {
	volatile.StoreUint16(&o.NRDYENB.Reg, volatile.LoadUint16(&o.NRDYENB.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetNRDYENB_PIPE7NRDYE() uint16 {
	return (volatile.LoadUint16(&o.NRDYENB.Reg) & 0x80) >> 7
}

// USBFS.BEMPENB: BEMP Interrupt Enable Register
func (o *USBFS_Type) SetBEMPENB_PIPE0BEMPE(value uint16) {
	volatile.StoreUint16(&o.BEMPENB.Reg, volatile.LoadUint16(&o.BEMPENB.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetBEMPENB_PIPE0BEMPE() uint16 {
	return volatile.LoadUint16(&o.BEMPENB.Reg) & 0x1
}
func (o *USBFS_Type) SetBEMPENB_PIPE4BEMPE(value uint16) {
	volatile.StoreUint16(&o.BEMPENB.Reg, volatile.LoadUint16(&o.BEMPENB.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetBEMPENB_PIPE4BEMPE() uint16 {
	return (volatile.LoadUint16(&o.BEMPENB.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetBEMPENB_PIPE5BEMPE(value uint16) {
	volatile.StoreUint16(&o.BEMPENB.Reg, volatile.LoadUint16(&o.BEMPENB.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetBEMPENB_PIPE5BEMPE() uint16 {
	return (volatile.LoadUint16(&o.BEMPENB.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetBEMPENB_PIPE6BEMPE(value uint16) {
	volatile.StoreUint16(&o.BEMPENB.Reg, volatile.LoadUint16(&o.BEMPENB.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetBEMPENB_PIPE6BEMPE() uint16 {
	return (volatile.LoadUint16(&o.BEMPENB.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetBEMPENB_PIPE7BEMPE(value uint16) {
	volatile.StoreUint16(&o.BEMPENB.Reg, volatile.LoadUint16(&o.BEMPENB.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetBEMPENB_PIPE7BEMPE() uint16 {
	return (volatile.LoadUint16(&o.BEMPENB.Reg) & 0x80) >> 7
}

// USBFS.SOFCFG: SOF Output Configuration Register
func (o *USBFS_Type) SetSOFCFG_EDGESTS(value uint16) {
	volatile.StoreUint16(&o.SOFCFG.Reg, volatile.LoadUint16(&o.SOFCFG.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetSOFCFG_EDGESTS() uint16 {
	return (volatile.LoadUint16(&o.SOFCFG.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetSOFCFG_BRDYM(value uint16) {
	volatile.StoreUint16(&o.SOFCFG.Reg, volatile.LoadUint16(&o.SOFCFG.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetSOFCFG_BRDYM() uint16 {
	return (volatile.LoadUint16(&o.SOFCFG.Reg) & 0x40) >> 6
}

// USBFS.INTSTS0: Interrupt Status Register 0
func (o *USBFS_Type) SetINTSTS0_CTSQ(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x7)|value)
}
func (o *USBFS_Type) GetINTSTS0_CTSQ() uint16 {
	return volatile.LoadUint16(&o.INTSTS0.Reg) & 0x7
}
func (o *USBFS_Type) SetINTSTS0_VALID(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x8)|value<<3)
}
func (o *USBFS_Type) GetINTSTS0_VALID() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x8) >> 3
}
func (o *USBFS_Type) SetINTSTS0_DVSQ(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x70)|value<<4)
}
func (o *USBFS_Type) GetINTSTS0_DVSQ() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x70) >> 4
}
func (o *USBFS_Type) SetINTSTS0_VBSTS(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetINTSTS0_VBSTS() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetINTSTS0_BRDY(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetINTSTS0_BRDY() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetINTSTS0_NRDY(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetINTSTS0_NRDY() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x200) >> 9
}
func (o *USBFS_Type) SetINTSTS0_BEMP(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x400)|value<<10)
}
func (o *USBFS_Type) GetINTSTS0_BEMP() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x400) >> 10
}
func (o *USBFS_Type) SetINTSTS0_CTRT(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x800)|value<<11)
}
func (o *USBFS_Type) GetINTSTS0_CTRT() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x800) >> 11
}
func (o *USBFS_Type) SetINTSTS0_DVST(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x1000)|value<<12)
}
func (o *USBFS_Type) GetINTSTS0_DVST() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x1000) >> 12
}
func (o *USBFS_Type) SetINTSTS0_SOFR(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x2000)|value<<13)
}
func (o *USBFS_Type) GetINTSTS0_SOFR() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x2000) >> 13
}
func (o *USBFS_Type) SetINTSTS0_RESM(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x4000)|value<<14)
}
func (o *USBFS_Type) GetINTSTS0_RESM() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x4000) >> 14
}
func (o *USBFS_Type) SetINTSTS0_VBINT(value uint16) {
	volatile.StoreUint16(&o.INTSTS0.Reg, volatile.LoadUint16(&o.INTSTS0.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetINTSTS0_VBINT() uint16 {
	return (volatile.LoadUint16(&o.INTSTS0.Reg) & 0x8000) >> 15
}

// USBFS.BRDYSTS: BRDY Interrupt Status Register
func (o *USBFS_Type) SetBRDYSTS_PIPE0BRDY(value uint16) {
	volatile.StoreUint16(&o.BRDYSTS.Reg, volatile.LoadUint16(&o.BRDYSTS.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetBRDYSTS_PIPE0BRDY() uint16 {
	return volatile.LoadUint16(&o.BRDYSTS.Reg) & 0x1
}
func (o *USBFS_Type) SetBRDYSTS_PIPE4BRDY(value uint16) {
	volatile.StoreUint16(&o.BRDYSTS.Reg, volatile.LoadUint16(&o.BRDYSTS.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetBRDYSTS_PIPE4BRDY() uint16 {
	return (volatile.LoadUint16(&o.BRDYSTS.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetBRDYSTS_PIPE5BRDY(value uint16) {
	volatile.StoreUint16(&o.BRDYSTS.Reg, volatile.LoadUint16(&o.BRDYSTS.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetBRDYSTS_PIPE5BRDY() uint16 {
	return (volatile.LoadUint16(&o.BRDYSTS.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetBRDYSTS_PIPE6BRDY(value uint16) {
	volatile.StoreUint16(&o.BRDYSTS.Reg, volatile.LoadUint16(&o.BRDYSTS.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetBRDYSTS_PIPE6BRDY() uint16 {
	return (volatile.LoadUint16(&o.BRDYSTS.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetBRDYSTS_PIPE7BRDY(value uint16) {
	volatile.StoreUint16(&o.BRDYSTS.Reg, volatile.LoadUint16(&o.BRDYSTS.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetBRDYSTS_PIPE7BRDY() uint16 {
	return (volatile.LoadUint16(&o.BRDYSTS.Reg) & 0x80) >> 7
}

// USBFS.NRDYSTS: NRDY Interrupt Status Register
func (o *USBFS_Type) SetNRDYSTS_PIPE0NRDY(value uint16) {
	volatile.StoreUint16(&o.NRDYSTS.Reg, volatile.LoadUint16(&o.NRDYSTS.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetNRDYSTS_PIPE0NRDY() uint16 {
	return volatile.LoadUint16(&o.NRDYSTS.Reg) & 0x1
}
func (o *USBFS_Type) SetNRDYSTS_PIPE4NRDY(value uint16) {
	volatile.StoreUint16(&o.NRDYSTS.Reg, volatile.LoadUint16(&o.NRDYSTS.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetNRDYSTS_PIPE4NRDY() uint16 {
	return (volatile.LoadUint16(&o.NRDYSTS.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetNRDYSTS_PIPE5NRDY(value uint16) {
	volatile.StoreUint16(&o.NRDYSTS.Reg, volatile.LoadUint16(&o.NRDYSTS.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetNRDYSTS_PIPE5NRDY() uint16 {
	return (volatile.LoadUint16(&o.NRDYSTS.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetNRDYSTS_PIPE6NRDY(value uint16) {
	volatile.StoreUint16(&o.NRDYSTS.Reg, volatile.LoadUint16(&o.NRDYSTS.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetNRDYSTS_PIPE6NRDY() uint16 {
	return (volatile.LoadUint16(&o.NRDYSTS.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetNRDYSTS_PIPE7NRDY(value uint16) {
	volatile.StoreUint16(&o.NRDYSTS.Reg, volatile.LoadUint16(&o.NRDYSTS.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetNRDYSTS_PIPE7NRDY() uint16 {
	return (volatile.LoadUint16(&o.NRDYSTS.Reg) & 0x80) >> 7
}

// USBFS.BEMPSTS: BEMP Interrupt Status Register
func (o *USBFS_Type) SetBEMPSTS_PIPE0BEMP(value uint16) {
	volatile.StoreUint16(&o.BEMPSTS.Reg, volatile.LoadUint16(&o.BEMPSTS.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetBEMPSTS_PIPE0BEMP() uint16 {
	return volatile.LoadUint16(&o.BEMPSTS.Reg) & 0x1
}
func (o *USBFS_Type) SetBEMPSTS_PIPE4BEMP(value uint16) {
	volatile.StoreUint16(&o.BEMPSTS.Reg, volatile.LoadUint16(&o.BEMPSTS.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetBEMPSTS_PIPE4BEMP() uint16 {
	return (volatile.LoadUint16(&o.BEMPSTS.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetBEMPSTS_PIPE5BEMP(value uint16) {
	volatile.StoreUint16(&o.BEMPSTS.Reg, volatile.LoadUint16(&o.BEMPSTS.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetBEMPSTS_PIPE5BEMP() uint16 {
	return (volatile.LoadUint16(&o.BEMPSTS.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetBEMPSTS_PIPE6BEMP(value uint16) {
	volatile.StoreUint16(&o.BEMPSTS.Reg, volatile.LoadUint16(&o.BEMPSTS.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetBEMPSTS_PIPE6BEMP() uint16 {
	return (volatile.LoadUint16(&o.BEMPSTS.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetBEMPSTS_PIPE7BEMP(value uint16) {
	volatile.StoreUint16(&o.BEMPSTS.Reg, volatile.LoadUint16(&o.BEMPSTS.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetBEMPSTS_PIPE7BEMP() uint16 {
	return (volatile.LoadUint16(&o.BEMPSTS.Reg) & 0x80) >> 7
}

// USBFS.FRMNUM: Frame Number Register
func (o *USBFS_Type) SetFRMNUM_FRNM(value uint16) {
	volatile.StoreUint16(&o.FRMNUM.Reg, volatile.LoadUint16(&o.FRMNUM.Reg)&^(0x7ff)|value)
}
func (o *USBFS_Type) GetFRMNUM_FRNM() uint16 {
	return volatile.LoadUint16(&o.FRMNUM.Reg) & 0x7ff
}

// USBFS.DVCHGR: Device State Change Register
func (o *USBFS_Type) SetDVCHGR_DVCHG(value uint16) {
	volatile.StoreUint16(&o.DVCHGR.Reg, volatile.LoadUint16(&o.DVCHGR.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetDVCHGR_DVCHG() uint16 {
	return (volatile.LoadUint16(&o.DVCHGR.Reg) & 0x8000) >> 15
}

// USBFS.USBADDR: USB Address Register
func (o *USBFS_Type) SetUSBADDR(value uint16) {
	volatile.StoreUint16(&o.USBADDR.Reg, volatile.LoadUint16(&o.USBADDR.Reg)&^(0x7f)|value)
}
func (o *USBFS_Type) GetUSBADDR() uint16 {
	return volatile.LoadUint16(&o.USBADDR.Reg) & 0x7f
}
func (o *USBFS_Type) SetUSBADDR_STSRECOV(value uint16) {
	volatile.StoreUint16(&o.USBADDR.Reg, volatile.LoadUint16(&o.USBADDR.Reg)&^(0xf00)|value<<8)
}
func (o *USBFS_Type) GetUSBADDR_STSRECOV() uint16 {
	return (volatile.LoadUint16(&o.USBADDR.Reg) & 0xf00) >> 8
}

// USBFS.USBREQ: USB Request Type Register
func (o *USBFS_Type) SetUSBREQ_BMREQUESTTYPE(value uint16) {
	volatile.StoreUint16(&o.USBREQ.Reg, volatile.LoadUint16(&o.USBREQ.Reg)&^(0xff)|value)
}
func (o *USBFS_Type) GetUSBREQ_BMREQUESTTYPE() uint16 {
	return volatile.LoadUint16(&o.USBREQ.Reg) & 0xff
}
func (o *USBFS_Type) SetUSBREQ_BREQUEST(value uint16) {
	volatile.StoreUint16(&o.USBREQ.Reg, volatile.LoadUint16(&o.USBREQ.Reg)&^(0xff00)|value<<8)
}
func (o *USBFS_Type) GetUSBREQ_BREQUEST() uint16 {
	return (volatile.LoadUint16(&o.USBREQ.Reg) & 0xff00) >> 8
}

// USBFS.USBVAL: USB Request Value Register
func (o *USBFS_Type) SetUSBVAL(value uint16) {
	volatile.StoreUint16(&o.USBVAL.Reg, value)
}
func (o *USBFS_Type) GetUSBVAL() uint16 {
	return volatile.LoadUint16(&o.USBVAL.Reg)
}

// USBFS.USBINDX: USB Request Index Register
func (o *USBFS_Type) SetUSBINDX(value uint16) {
	volatile.StoreUint16(&o.USBINDX.Reg, value)
}
func (o *USBFS_Type) GetUSBINDX() uint16 {
	return volatile.LoadUint16(&o.USBINDX.Reg)
}

// USBFS.USBLENG: USB Request Length Register
func (o *USBFS_Type) SetUSBLENG(value uint16) {
	volatile.StoreUint16(&o.USBLENG.Reg, value)
}
func (o *USBFS_Type) GetUSBLENG() uint16 {
	return volatile.LoadUint16(&o.USBLENG.Reg)
}

// USBFS.DCPCFG: DCP Configuration Register
func (o *USBFS_Type) SetDCPCFG_SHTNAK(value uint16) {
	volatile.StoreUint16(&o.DCPCFG.Reg, volatile.LoadUint16(&o.DCPCFG.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetDCPCFG_SHTNAK() uint16 {
	return (volatile.LoadUint16(&o.DCPCFG.Reg) & 0x80) >> 7
}

// USBFS.DCPMAXP: DCP Maximum Packet Size Register
func (o *USBFS_Type) SetDCPMAXP_MXPS(value uint16) {
	volatile.StoreUint16(&o.DCPMAXP.Reg, volatile.LoadUint16(&o.DCPMAXP.Reg)&^(0x7f)|value)
}
func (o *USBFS_Type) GetDCPMAXP_MXPS() uint16 {
	return volatile.LoadUint16(&o.DCPMAXP.Reg) & 0x7f
}

// USBFS.DCPCTR: DCP Control Register
func (o *USBFS_Type) SetDCPCTR_PID(value uint16) {
	volatile.StoreUint16(&o.DCPCTR.Reg, volatile.LoadUint16(&o.DCPCTR.Reg)&^(0x3)|value)
}
func (o *USBFS_Type) GetDCPCTR_PID() uint16 {
	return volatile.LoadUint16(&o.DCPCTR.Reg) & 0x3
}
func (o *USBFS_Type) SetDCPCTR_CCPL(value uint16) {
	volatile.StoreUint16(&o.DCPCTR.Reg, volatile.LoadUint16(&o.DCPCTR.Reg)&^(0x4)|value<<2)
}
func (o *USBFS_Type) GetDCPCTR_CCPL() uint16 {
	return (volatile.LoadUint16(&o.DCPCTR.Reg) & 0x4) >> 2
}
func (o *USBFS_Type) SetDCPCTR_PBUSY(value uint16) {
	volatile.StoreUint16(&o.DCPCTR.Reg, volatile.LoadUint16(&o.DCPCTR.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetDCPCTR_PBUSY() uint16 {
	return (volatile.LoadUint16(&o.DCPCTR.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetDCPCTR_SQMON(value uint16) {
	volatile.StoreUint16(&o.DCPCTR.Reg, volatile.LoadUint16(&o.DCPCTR.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetDCPCTR_SQMON() uint16 {
	return (volatile.LoadUint16(&o.DCPCTR.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetDCPCTR_SQSET(value uint16) {
	volatile.StoreUint16(&o.DCPCTR.Reg, volatile.LoadUint16(&o.DCPCTR.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetDCPCTR_SQSET() uint16 {
	return (volatile.LoadUint16(&o.DCPCTR.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetDCPCTR_SQCLR(value uint16) {
	volatile.StoreUint16(&o.DCPCTR.Reg, volatile.LoadUint16(&o.DCPCTR.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetDCPCTR_SQCLR() uint16 {
	return (volatile.LoadUint16(&o.DCPCTR.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetDCPCTR_BSTS(value uint16) {
	volatile.StoreUint16(&o.DCPCTR.Reg, volatile.LoadUint16(&o.DCPCTR.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetDCPCTR_BSTS() uint16 {
	return (volatile.LoadUint16(&o.DCPCTR.Reg) & 0x8000) >> 15
}

// USBFS.PIPESEL: Pipe Window Select Register
func (o *USBFS_Type) SetPIPESEL(value uint16) {
	volatile.StoreUint16(&o.PIPESEL.Reg, volatile.LoadUint16(&o.PIPESEL.Reg)&^(0xf)|value)
}
func (o *USBFS_Type) GetPIPESEL() uint16 {
	return volatile.LoadUint16(&o.PIPESEL.Reg) & 0xf
}

// USBFS.PIPECFG: Pipe Configuration Register
func (o *USBFS_Type) SetPIPECFG_EPNUM(value uint16) {
	volatile.StoreUint16(&o.PIPECFG.Reg, volatile.LoadUint16(&o.PIPECFG.Reg)&^(0xf)|value)
}
func (o *USBFS_Type) GetPIPECFG_EPNUM() uint16 {
	return volatile.LoadUint16(&o.PIPECFG.Reg) & 0xf
}
func (o *USBFS_Type) SetPIPECFG_DIR(value uint16) {
	volatile.StoreUint16(&o.PIPECFG.Reg, volatile.LoadUint16(&o.PIPECFG.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetPIPECFG_DIR() uint16 {
	return (volatile.LoadUint16(&o.PIPECFG.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetPIPECFG_SHTNAK(value uint16) {
	volatile.StoreUint16(&o.PIPECFG.Reg, volatile.LoadUint16(&o.PIPECFG.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetPIPECFG_SHTNAK() uint16 {
	return (volatile.LoadUint16(&o.PIPECFG.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetPIPECFG_DBLB(value uint16) {
	volatile.StoreUint16(&o.PIPECFG.Reg, volatile.LoadUint16(&o.PIPECFG.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetPIPECFG_DBLB() uint16 {
	return (volatile.LoadUint16(&o.PIPECFG.Reg) & 0x200) >> 9
}
func (o *USBFS_Type) SetPIPECFG_BFRE(value uint16) {
	volatile.StoreUint16(&o.PIPECFG.Reg, volatile.LoadUint16(&o.PIPECFG.Reg)&^(0x400)|value<<10)
}
func (o *USBFS_Type) GetPIPECFG_BFRE() uint16 {
	return (volatile.LoadUint16(&o.PIPECFG.Reg) & 0x400) >> 10
}
func (o *USBFS_Type) SetPIPECFG_TYPE(value uint16) {
	volatile.StoreUint16(&o.PIPECFG.Reg, volatile.LoadUint16(&o.PIPECFG.Reg)&^(0xc000)|value<<14)
}
func (o *USBFS_Type) GetPIPECFG_TYPE() uint16 {
	return (volatile.LoadUint16(&o.PIPECFG.Reg) & 0xc000) >> 14
}

// USBFS.PIPEMAXP: Pipe Maximum Packet Size Register
func (o *USBFS_Type) SetPIPEMAXP_MXPS(value uint16) {
	volatile.StoreUint16(&o.PIPEMAXP.Reg, volatile.LoadUint16(&o.PIPEMAXP.Reg)&^(0x1ff)|value)
}
func (o *USBFS_Type) GetPIPEMAXP_MXPS() uint16 {
	return volatile.LoadUint16(&o.PIPEMAXP.Reg) & 0x1ff
}

// USBFS.PIPE4CTR: PIPE%s Control Registers
func (o *USBFS_Type) SetPIPE4CTR_PID(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x3)|value)
}
func (o *USBFS_Type) GetPIPE4CTR_PID() uint16 {
	return volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x3
}
func (o *USBFS_Type) SetPIPE4CTR_PBUSY(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetPIPE4CTR_PBUSY() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetPIPE4CTR_SQMON(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetPIPE4CTR_SQMON() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetPIPE4CTR_SQSET(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetPIPE4CTR_SQSET() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetPIPE4CTR_SQCLR(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetPIPE4CTR_SQCLR() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetPIPE4CTR_ACLRM(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetPIPE4CTR_ACLRM() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x200) >> 9
}
func (o *USBFS_Type) SetPIPE4CTR_ATREPM(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x400)|value<<10)
}
func (o *USBFS_Type) GetPIPE4CTR_ATREPM() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x400) >> 10
}
func (o *USBFS_Type) SetPIPE4CTR_INBUFM(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x4000)|value<<14)
}
func (o *USBFS_Type) GetPIPE4CTR_INBUFM() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x4000) >> 14
}
func (o *USBFS_Type) SetPIPE4CTR_BSTS(value uint16) {
	volatile.StoreUint16(&o.PIPE4CTR.Reg, volatile.LoadUint16(&o.PIPE4CTR.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetPIPE4CTR_BSTS() uint16 {
	return (volatile.LoadUint16(&o.PIPE4CTR.Reg) & 0x8000) >> 15
}

// USBFS.PIPE5CTR: PIPE%s Control Registers
func (o *USBFS_Type) SetPIPE5CTR_PID(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x3)|value)
}
func (o *USBFS_Type) GetPIPE5CTR_PID() uint16 {
	return volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x3
}
func (o *USBFS_Type) SetPIPE5CTR_PBUSY(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetPIPE5CTR_PBUSY() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetPIPE5CTR_SQMON(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetPIPE5CTR_SQMON() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetPIPE5CTR_SQSET(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetPIPE5CTR_SQSET() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetPIPE5CTR_SQCLR(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetPIPE5CTR_SQCLR() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetPIPE5CTR_ACLRM(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetPIPE5CTR_ACLRM() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x200) >> 9
}
func (o *USBFS_Type) SetPIPE5CTR_ATREPM(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x400)|value<<10)
}
func (o *USBFS_Type) GetPIPE5CTR_ATREPM() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x400) >> 10
}
func (o *USBFS_Type) SetPIPE5CTR_INBUFM(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x4000)|value<<14)
}
func (o *USBFS_Type) GetPIPE5CTR_INBUFM() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x4000) >> 14
}
func (o *USBFS_Type) SetPIPE5CTR_BSTS(value uint16) {
	volatile.StoreUint16(&o.PIPE5CTR.Reg, volatile.LoadUint16(&o.PIPE5CTR.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetPIPE5CTR_BSTS() uint16 {
	return (volatile.LoadUint16(&o.PIPE5CTR.Reg) & 0x8000) >> 15
}

// USBFS.PIPE6CTR: PIPE%s Control Registers
func (o *USBFS_Type) SetPIPE6CTR_PID(value uint16) {
	volatile.StoreUint16(&o.PIPE6CTR.Reg, volatile.LoadUint16(&o.PIPE6CTR.Reg)&^(0x3)|value)
}
func (o *USBFS_Type) GetPIPE6CTR_PID() uint16 {
	return volatile.LoadUint16(&o.PIPE6CTR.Reg) & 0x3
}
func (o *USBFS_Type) SetPIPE6CTR_PBUSY(value uint16) {
	volatile.StoreUint16(&o.PIPE6CTR.Reg, volatile.LoadUint16(&o.PIPE6CTR.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetPIPE6CTR_PBUSY() uint16 {
	return (volatile.LoadUint16(&o.PIPE6CTR.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetPIPE6CTR_SQMON(value uint16) {
	volatile.StoreUint16(&o.PIPE6CTR.Reg, volatile.LoadUint16(&o.PIPE6CTR.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetPIPE6CTR_SQMON() uint16 {
	return (volatile.LoadUint16(&o.PIPE6CTR.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetPIPE6CTR_SQSET(value uint16) {
	volatile.StoreUint16(&o.PIPE6CTR.Reg, volatile.LoadUint16(&o.PIPE6CTR.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetPIPE6CTR_SQSET() uint16 {
	return (volatile.LoadUint16(&o.PIPE6CTR.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetPIPE6CTR_SQCLR(value uint16) {
	volatile.StoreUint16(&o.PIPE6CTR.Reg, volatile.LoadUint16(&o.PIPE6CTR.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetPIPE6CTR_SQCLR() uint16 {
	return (volatile.LoadUint16(&o.PIPE6CTR.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetPIPE6CTR_ACLRM(value uint16) {
	volatile.StoreUint16(&o.PIPE6CTR.Reg, volatile.LoadUint16(&o.PIPE6CTR.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetPIPE6CTR_ACLRM() uint16 {
	return (volatile.LoadUint16(&o.PIPE6CTR.Reg) & 0x200) >> 9
}
func (o *USBFS_Type) SetPIPE6CTR_BSTS(value uint16) {
	volatile.StoreUint16(&o.PIPE6CTR.Reg, volatile.LoadUint16(&o.PIPE6CTR.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetPIPE6CTR_BSTS() uint16 {
	return (volatile.LoadUint16(&o.PIPE6CTR.Reg) & 0x8000) >> 15
}

// USBFS.PIPE7CTR: PIPE%s Control Registers
func (o *USBFS_Type) SetPIPE7CTR_PID(value uint16) {
	volatile.StoreUint16(&o.PIPE7CTR.Reg, volatile.LoadUint16(&o.PIPE7CTR.Reg)&^(0x3)|value)
}
func (o *USBFS_Type) GetPIPE7CTR_PID() uint16 {
	return volatile.LoadUint16(&o.PIPE7CTR.Reg) & 0x3
}
func (o *USBFS_Type) SetPIPE7CTR_PBUSY(value uint16) {
	volatile.StoreUint16(&o.PIPE7CTR.Reg, volatile.LoadUint16(&o.PIPE7CTR.Reg)&^(0x20)|value<<5)
}
func (o *USBFS_Type) GetPIPE7CTR_PBUSY() uint16 {
	return (volatile.LoadUint16(&o.PIPE7CTR.Reg) & 0x20) >> 5
}
func (o *USBFS_Type) SetPIPE7CTR_SQMON(value uint16) {
	volatile.StoreUint16(&o.PIPE7CTR.Reg, volatile.LoadUint16(&o.PIPE7CTR.Reg)&^(0x40)|value<<6)
}
func (o *USBFS_Type) GetPIPE7CTR_SQMON() uint16 {
	return (volatile.LoadUint16(&o.PIPE7CTR.Reg) & 0x40) >> 6
}
func (o *USBFS_Type) SetPIPE7CTR_SQSET(value uint16) {
	volatile.StoreUint16(&o.PIPE7CTR.Reg, volatile.LoadUint16(&o.PIPE7CTR.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetPIPE7CTR_SQSET() uint16 {
	return (volatile.LoadUint16(&o.PIPE7CTR.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetPIPE7CTR_SQCLR(value uint16) {
	volatile.StoreUint16(&o.PIPE7CTR.Reg, volatile.LoadUint16(&o.PIPE7CTR.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetPIPE7CTR_SQCLR() uint16 {
	return (volatile.LoadUint16(&o.PIPE7CTR.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetPIPE7CTR_ACLRM(value uint16) {
	volatile.StoreUint16(&o.PIPE7CTR.Reg, volatile.LoadUint16(&o.PIPE7CTR.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetPIPE7CTR_ACLRM() uint16 {
	return (volatile.LoadUint16(&o.PIPE7CTR.Reg) & 0x200) >> 9
}
func (o *USBFS_Type) SetPIPE7CTR_BSTS(value uint16) {
	volatile.StoreUint16(&o.PIPE7CTR.Reg, volatile.LoadUint16(&o.PIPE7CTR.Reg)&^(0x8000)|value<<15)
}
func (o *USBFS_Type) GetPIPE7CTR_BSTS() uint16 {
	return (volatile.LoadUint16(&o.PIPE7CTR.Reg) & 0x8000) >> 15
}

// USBFS.PIPE4TRE: PIPE%s Transaction Counter Enable Register
func (o *USBFS_Type) SetPIPE4TRE_TRCLR(value uint16) {
	volatile.StoreUint16(&o.PIPE4TRE.Reg, volatile.LoadUint16(&o.PIPE4TRE.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetPIPE4TRE_TRCLR() uint16 {
	return (volatile.LoadUint16(&o.PIPE4TRE.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetPIPE4TRE_TRENB(value uint16) {
	volatile.StoreUint16(&o.PIPE4TRE.Reg, volatile.LoadUint16(&o.PIPE4TRE.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetPIPE4TRE_TRENB() uint16 {
	return (volatile.LoadUint16(&o.PIPE4TRE.Reg) & 0x200) >> 9
}

// USBFS.PIPE4TRN: PIPE%s Transaction Counter Register
func (o *USBFS_Type) SetPIPE4TRN(value uint16) {
	volatile.StoreUint16(&o.PIPE4TRN.Reg, value)
}
func (o *USBFS_Type) GetPIPE4TRN() uint16 {
	return volatile.LoadUint16(&o.PIPE4TRN.Reg)
}

// USBFS.PIPE5TRE: PIPE%s Transaction Counter Enable Register
func (o *USBFS_Type) SetPIPE5TRE_TRCLR(value uint16) {
	volatile.StoreUint16(&o.PIPE5TRE.Reg, volatile.LoadUint16(&o.PIPE5TRE.Reg)&^(0x100)|value<<8)
}
func (o *USBFS_Type) GetPIPE5TRE_TRCLR() uint16 {
	return (volatile.LoadUint16(&o.PIPE5TRE.Reg) & 0x100) >> 8
}
func (o *USBFS_Type) SetPIPE5TRE_TRENB(value uint16) {
	volatile.StoreUint16(&o.PIPE5TRE.Reg, volatile.LoadUint16(&o.PIPE5TRE.Reg)&^(0x200)|value<<9)
}
func (o *USBFS_Type) GetPIPE5TRE_TRENB() uint16 {
	return (volatile.LoadUint16(&o.PIPE5TRE.Reg) & 0x200) >> 9
}

// USBFS.PIPE5TRN: PIPE%s Transaction Counter Register
func (o *USBFS_Type) SetPIPE5TRN(value uint16) {
	volatile.StoreUint16(&o.PIPE5TRN.Reg, value)
}
func (o *USBFS_Type) GetPIPE5TRN() uint16 {
	return volatile.LoadUint16(&o.PIPE5TRN.Reg)
}

// USBFS.PHYSECTRL: PHY Single-ended Receiver Control Register
func (o *USBFS_Type) SetPHYSECTRL_CNEN(value uint32) {
	volatile.StoreUint32(&o.PHYSECTRL.Reg, volatile.LoadUint32(&o.PHYSECTRL.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetPHYSECTRL_CNEN() uint32 {
	return (volatile.LoadUint32(&o.PHYSECTRL.Reg) & 0x10) >> 4
}

// USBFS.DPUSR0R: Deep Software Standby USB Transceiver Control/Pin Monitor Register
func (o *USBFS_Type) SetDPUSR0R_SRPC0(value uint32) {
	volatile.StoreUint32(&o.DPUSR0R.Reg, volatile.LoadUint32(&o.DPUSR0R.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetDPUSR0R_SRPC0() uint32 {
	return volatile.LoadUint32(&o.DPUSR0R.Reg) & 0x1
}
func (o *USBFS_Type) SetDPUSR0R_RPUE0(value uint32) {
	volatile.StoreUint32(&o.DPUSR0R.Reg, volatile.LoadUint32(&o.DPUSR0R.Reg)&^(0x2)|value<<1)
}
func (o *USBFS_Type) GetDPUSR0R_RPUE0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR0R.Reg) & 0x2) >> 1
}
func (o *USBFS_Type) SetDPUSR0R_FIXPHY0(value uint32) {
	volatile.StoreUint32(&o.DPUSR0R.Reg, volatile.LoadUint32(&o.DPUSR0R.Reg)&^(0x10)|value<<4)
}
func (o *USBFS_Type) GetDPUSR0R_FIXPHY0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR0R.Reg) & 0x10) >> 4
}
func (o *USBFS_Type) SetDPUSR0R_DP0(value uint32) {
	volatile.StoreUint32(&o.DPUSR0R.Reg, volatile.LoadUint32(&o.DPUSR0R.Reg)&^(0x10000)|value<<16)
}
func (o *USBFS_Type) GetDPUSR0R_DP0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR0R.Reg) & 0x10000) >> 16
}
func (o *USBFS_Type) SetDPUSR0R_DM0(value uint32) {
	volatile.StoreUint32(&o.DPUSR0R.Reg, volatile.LoadUint32(&o.DPUSR0R.Reg)&^(0x20000)|value<<17)
}
func (o *USBFS_Type) GetDPUSR0R_DM0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR0R.Reg) & 0x20000) >> 17
}
func (o *USBFS_Type) SetDPUSR0R_DVBSTS0(value uint32) {
	volatile.StoreUint32(&o.DPUSR0R.Reg, volatile.LoadUint32(&o.DPUSR0R.Reg)&^(0x800000)|value<<23)
}
func (o *USBFS_Type) GetDPUSR0R_DVBSTS0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR0R.Reg) & 0x800000) >> 23
}

// USBFS.DPUSR1R: Deep Software Standby USB Suspend/Resume Interrupt Register
func (o *USBFS_Type) SetDPUSR1R_DPINTE0(value uint32) {
	volatile.StoreUint32(&o.DPUSR1R.Reg, volatile.LoadUint32(&o.DPUSR1R.Reg)&^(0x1)|value)
}
func (o *USBFS_Type) GetDPUSR1R_DPINTE0() uint32 {
	return volatile.LoadUint32(&o.DPUSR1R.Reg) & 0x1
}
func (o *USBFS_Type) SetDPUSR1R_DMINTE0(value uint32) {
	volatile.StoreUint32(&o.DPUSR1R.Reg, volatile.LoadUint32(&o.DPUSR1R.Reg)&^(0x2)|value<<1)
}
func (o *USBFS_Type) GetDPUSR1R_DMINTE0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR1R.Reg) & 0x2) >> 1
}
func (o *USBFS_Type) SetDPUSR1R_DVBSE0(value uint32) {
	volatile.StoreUint32(&o.DPUSR1R.Reg, volatile.LoadUint32(&o.DPUSR1R.Reg)&^(0x80)|value<<7)
}
func (o *USBFS_Type) GetDPUSR1R_DVBSE0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR1R.Reg) & 0x80) >> 7
}
func (o *USBFS_Type) SetDPUSR1R_DPINT0(value uint32) {
	volatile.StoreUint32(&o.DPUSR1R.Reg, volatile.LoadUint32(&o.DPUSR1R.Reg)&^(0x10000)|value<<16)
}
func (o *USBFS_Type) GetDPUSR1R_DPINT0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR1R.Reg) & 0x10000) >> 16
}
func (o *USBFS_Type) SetDPUSR1R_DMINT0(value uint32) {
	volatile.StoreUint32(&o.DPUSR1R.Reg, volatile.LoadUint32(&o.DPUSR1R.Reg)&^(0x20000)|value<<17)
}
func (o *USBFS_Type) GetDPUSR1R_DMINT0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR1R.Reg) & 0x20000) >> 17
}
func (o *USBFS_Type) SetDPUSR1R_DVBINT0(value uint32) {
	volatile.StoreUint32(&o.DPUSR1R.Reg, volatile.LoadUint32(&o.DPUSR1R.Reg)&^(0x800000)|value<<23)
}
func (o *USBFS_Type) GetDPUSR1R_DVBINT0() uint32 {
	return (volatile.LoadUint32(&o.DPUSR1R.Reg) & 0x800000) >> 23
}

// Serial Sound Interface Enhanced (SSIE)
type SSIE0_Type struct {
	SSICR   volatile.Register32 // 0x0
	SSISR   volatile.Register32 // 0x4
	_       [8]byte
	SSIFCR  volatile.Register32 // 0x10
	SSIFSR  volatile.Register32 // 0x14
	SSIFTDR volatile.Register32 // 0x18
	SSIFRDR volatile.Register32 // 0x1C
	SSIOFR  volatile.Register32 // 0x20
	SSISCR  volatile.Register32 // 0x24
}

// SSIE0.SSICR: Control Register
func (o *SSIE0_Type) SetSSICR_REN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x1)|value)
}
func (o *SSIE0_Type) GetSSICR_REN() uint32 {
	return volatile.LoadUint32(&o.SSICR.Reg) & 0x1
}
func (o *SSIE0_Type) SetSSICR_TEN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x2)|value<<1)
}
func (o *SSIE0_Type) GetSSICR_TEN() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x2) >> 1
}
func (o *SSIE0_Type) SetSSICR_MUEN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x8)|value<<3)
}
func (o *SSIE0_Type) GetSSICR_MUEN() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x8) >> 3
}
func (o *SSIE0_Type) SetSSICR_CKDV(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0xf0)|value<<4)
}
func (o *SSIE0_Type) GetSSICR_CKDV() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0xf0) >> 4
}
func (o *SSIE0_Type) SetSSICR_DEL(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x100)|value<<8)
}
func (o *SSIE0_Type) GetSSICR_DEL() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x100) >> 8
}
func (o *SSIE0_Type) SetSSICR_PDTA(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x200)|value<<9)
}
func (o *SSIE0_Type) GetSSICR_PDTA() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x200) >> 9
}
func (o *SSIE0_Type) SetSSICR_SDTA(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x400)|value<<10)
}
func (o *SSIE0_Type) GetSSICR_SDTA() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x400) >> 10
}
func (o *SSIE0_Type) SetSSICR_SPDP(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x800)|value<<11)
}
func (o *SSIE0_Type) GetSSICR_SPDP() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x800) >> 11
}
func (o *SSIE0_Type) SetSSICR_LRCKP(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x1000)|value<<12)
}
func (o *SSIE0_Type) GetSSICR_LRCKP() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x1000) >> 12
}
func (o *SSIE0_Type) SetSSICR_BCKP(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x2000)|value<<13)
}
func (o *SSIE0_Type) GetSSICR_BCKP() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x2000) >> 13
}
func (o *SSIE0_Type) SetSSICR_MST(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x4000)|value<<14)
}
func (o *SSIE0_Type) GetSSICR_MST() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x4000) >> 14
}
func (o *SSIE0_Type) SetSSICR_SWL(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x70000)|value<<16)
}
func (o *SSIE0_Type) GetSSICR_SWL() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x70000) >> 16
}
func (o *SSIE0_Type) SetSSICR_DWL(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x380000)|value<<19)
}
func (o *SSIE0_Type) GetSSICR_DWL() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x380000) >> 19
}
func (o *SSIE0_Type) SetSSICR_FRM(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0xc00000)|value<<22)
}
func (o *SSIE0_Type) GetSSICR_FRM() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0xc00000) >> 22
}
func (o *SSIE0_Type) SetSSICR_IIEN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x2000000)|value<<25)
}
func (o *SSIE0_Type) GetSSICR_IIEN() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x2000000) >> 25
}
func (o *SSIE0_Type) SetSSICR_ROIEN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x4000000)|value<<26)
}
func (o *SSIE0_Type) GetSSICR_ROIEN() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x4000000) >> 26
}
func (o *SSIE0_Type) SetSSICR_RUIEN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x8000000)|value<<27)
}
func (o *SSIE0_Type) GetSSICR_RUIEN() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x8000000) >> 27
}
func (o *SSIE0_Type) SetSSICR_TOIEN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x10000000)|value<<28)
}
func (o *SSIE0_Type) GetSSICR_TOIEN() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x10000000) >> 28
}
func (o *SSIE0_Type) SetSSICR_TUIEN(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x20000000)|value<<29)
}
func (o *SSIE0_Type) GetSSICR_TUIEN() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x20000000) >> 29
}
func (o *SSIE0_Type) SetSSICR_CKS(value uint32) {
	volatile.StoreUint32(&o.SSICR.Reg, volatile.LoadUint32(&o.SSICR.Reg)&^(0x40000000)|value<<30)
}
func (o *SSIE0_Type) GetSSICR_CKS() uint32 {
	return (volatile.LoadUint32(&o.SSICR.Reg) & 0x40000000) >> 30
}

// SSIE0.SSISR: Status Register
func (o *SSIE0_Type) SetSSISR_IIRQ(value uint32) {
	volatile.StoreUint32(&o.SSISR.Reg, volatile.LoadUint32(&o.SSISR.Reg)&^(0x2000000)|value<<25)
}
func (o *SSIE0_Type) GetSSISR_IIRQ() uint32 {
	return (volatile.LoadUint32(&o.SSISR.Reg) & 0x2000000) >> 25
}
func (o *SSIE0_Type) SetSSISR_ROIRQ(value uint32) {
	volatile.StoreUint32(&o.SSISR.Reg, volatile.LoadUint32(&o.SSISR.Reg)&^(0x4000000)|value<<26)
}
func (o *SSIE0_Type) GetSSISR_ROIRQ() uint32 {
	return (volatile.LoadUint32(&o.SSISR.Reg) & 0x4000000) >> 26
}
func (o *SSIE0_Type) SetSSISR_RUIRQ(value uint32) {
	volatile.StoreUint32(&o.SSISR.Reg, volatile.LoadUint32(&o.SSISR.Reg)&^(0x8000000)|value<<27)
}
func (o *SSIE0_Type) GetSSISR_RUIRQ() uint32 {
	return (volatile.LoadUint32(&o.SSISR.Reg) & 0x8000000) >> 27
}
func (o *SSIE0_Type) SetSSISR_TOIRQ(value uint32) {
	volatile.StoreUint32(&o.SSISR.Reg, volatile.LoadUint32(&o.SSISR.Reg)&^(0x10000000)|value<<28)
}
func (o *SSIE0_Type) GetSSISR_TOIRQ() uint32 {
	return (volatile.LoadUint32(&o.SSISR.Reg) & 0x10000000) >> 28
}
func (o *SSIE0_Type) SetSSISR_TUIRQ(value uint32) {
	volatile.StoreUint32(&o.SSISR.Reg, volatile.LoadUint32(&o.SSISR.Reg)&^(0x20000000)|value<<29)
}
func (o *SSIE0_Type) GetSSISR_TUIRQ() uint32 {
	return (volatile.LoadUint32(&o.SSISR.Reg) & 0x20000000) >> 29
}

// SSIE0.SSIFCR: FIFO Control Register
func (o *SSIE0_Type) SetSSIFCR_RFRST(value uint32) {
	volatile.StoreUint32(&o.SSIFCR.Reg, volatile.LoadUint32(&o.SSIFCR.Reg)&^(0x1)|value)
}
func (o *SSIE0_Type) GetSSIFCR_RFRST() uint32 {
	return volatile.LoadUint32(&o.SSIFCR.Reg) & 0x1
}
func (o *SSIE0_Type) SetSSIFCR_TFRST(value uint32) {
	volatile.StoreUint32(&o.SSIFCR.Reg, volatile.LoadUint32(&o.SSIFCR.Reg)&^(0x2)|value<<1)
}
func (o *SSIE0_Type) GetSSIFCR_TFRST() uint32 {
	return (volatile.LoadUint32(&o.SSIFCR.Reg) & 0x2) >> 1
}
func (o *SSIE0_Type) SetSSIFCR_RIE(value uint32) {
	volatile.StoreUint32(&o.SSIFCR.Reg, volatile.LoadUint32(&o.SSIFCR.Reg)&^(0x4)|value<<2)
}
func (o *SSIE0_Type) GetSSIFCR_RIE() uint32 {
	return (volatile.LoadUint32(&o.SSIFCR.Reg) & 0x4) >> 2
}
func (o *SSIE0_Type) SetSSIFCR_TIE(value uint32) {
	volatile.StoreUint32(&o.SSIFCR.Reg, volatile.LoadUint32(&o.SSIFCR.Reg)&^(0x8)|value<<3)
}
func (o *SSIE0_Type) GetSSIFCR_TIE() uint32 {
	return (volatile.LoadUint32(&o.SSIFCR.Reg) & 0x8) >> 3
}
func (o *SSIE0_Type) SetSSIFCR_BSW(value uint32) {
	volatile.StoreUint32(&o.SSIFCR.Reg, volatile.LoadUint32(&o.SSIFCR.Reg)&^(0x800)|value<<11)
}
func (o *SSIE0_Type) GetSSIFCR_BSW() uint32 {
	return (volatile.LoadUint32(&o.SSIFCR.Reg) & 0x800) >> 11
}
func (o *SSIE0_Type) SetSSIFCR_SSIRST(value uint32) {
	volatile.StoreUint32(&o.SSIFCR.Reg, volatile.LoadUint32(&o.SSIFCR.Reg)&^(0x10000)|value<<16)
}
func (o *SSIE0_Type) GetSSIFCR_SSIRST() uint32 {
	return (volatile.LoadUint32(&o.SSIFCR.Reg) & 0x10000) >> 16
}
func (o *SSIE0_Type) SetSSIFCR_AUCKE(value uint32) {
	volatile.StoreUint32(&o.SSIFCR.Reg, volatile.LoadUint32(&o.SSIFCR.Reg)&^(0x80000000)|value<<31)
}
func (o *SSIE0_Type) GetSSIFCR_AUCKE() uint32 {
	return (volatile.LoadUint32(&o.SSIFCR.Reg) & 0x80000000) >> 31
}

// SSIE0.SSIFSR: FIFO Status Register
func (o *SSIE0_Type) SetSSIFSR_RDF(value uint32) {
	volatile.StoreUint32(&o.SSIFSR.Reg, volatile.LoadUint32(&o.SSIFSR.Reg)&^(0x1)|value)
}
func (o *SSIE0_Type) GetSSIFSR_RDF() uint32 {
	return volatile.LoadUint32(&o.SSIFSR.Reg) & 0x1
}
func (o *SSIE0_Type) SetSSIFSR_RDC(value uint32) {
	volatile.StoreUint32(&o.SSIFSR.Reg, volatile.LoadUint32(&o.SSIFSR.Reg)&^(0x3f00)|value<<8)
}
func (o *SSIE0_Type) GetSSIFSR_RDC() uint32 {
	return (volatile.LoadUint32(&o.SSIFSR.Reg) & 0x3f00) >> 8
}
func (o *SSIE0_Type) SetSSIFSR_TDE(value uint32) {
	volatile.StoreUint32(&o.SSIFSR.Reg, volatile.LoadUint32(&o.SSIFSR.Reg)&^(0x10000)|value<<16)
}
func (o *SSIE0_Type) GetSSIFSR_TDE() uint32 {
	return (volatile.LoadUint32(&o.SSIFSR.Reg) & 0x10000) >> 16
}
func (o *SSIE0_Type) SetSSIFSR_TDC(value uint32) {
	volatile.StoreUint32(&o.SSIFSR.Reg, volatile.LoadUint32(&o.SSIFSR.Reg)&^(0x3f000000)|value<<24)
}
func (o *SSIE0_Type) GetSSIFSR_TDC() uint32 {
	return (volatile.LoadUint32(&o.SSIFSR.Reg) & 0x3f000000) >> 24
}

// SSIE0.SSIFTDR: Transmit FIFO Data Register
func (o *SSIE0_Type) SetSSIFTDR(value uint32) {
	volatile.StoreUint32(&o.SSIFTDR.Reg, value)
}
func (o *SSIE0_Type) GetSSIFTDR() uint32 {
	return volatile.LoadUint32(&o.SSIFTDR.Reg)
}

// SSIE0.SSIFRDR: Receive FIFO Data Register
func (o *SSIE0_Type) SetSSIFRDR(value uint32) {
	volatile.StoreUint32(&o.SSIFRDR.Reg, value)
}
func (o *SSIE0_Type) GetSSIFRDR() uint32 {
	return volatile.LoadUint32(&o.SSIFRDR.Reg)
}

// SSIE0.SSIOFR: Audio Format Register
func (o *SSIE0_Type) SetSSIOFR_OMOD(value uint32) {
	volatile.StoreUint32(&o.SSIOFR.Reg, volatile.LoadUint32(&o.SSIOFR.Reg)&^(0x3)|value)
}
func (o *SSIE0_Type) GetSSIOFR_OMOD() uint32 {
	return volatile.LoadUint32(&o.SSIOFR.Reg) & 0x3
}
func (o *SSIE0_Type) SetSSIOFR_LRCONT(value uint32) {
	volatile.StoreUint32(&o.SSIOFR.Reg, volatile.LoadUint32(&o.SSIOFR.Reg)&^(0x100)|value<<8)
}
func (o *SSIE0_Type) GetSSIOFR_LRCONT() uint32 {
	return (volatile.LoadUint32(&o.SSIOFR.Reg) & 0x100) >> 8
}
func (o *SSIE0_Type) SetSSIOFR_BCKASTP(value uint32) {
	volatile.StoreUint32(&o.SSIOFR.Reg, volatile.LoadUint32(&o.SSIOFR.Reg)&^(0x200)|value<<9)
}
func (o *SSIE0_Type) GetSSIOFR_BCKASTP() uint32 {
	return (volatile.LoadUint32(&o.SSIOFR.Reg) & 0x200) >> 9
}

// SSIE0.SSISCR: Status Control Register
func (o *SSIE0_Type) SetSSISCR_RDFS(value uint32) {
	volatile.StoreUint32(&o.SSISCR.Reg, volatile.LoadUint32(&o.SSISCR.Reg)&^(0x1f)|value)
}
func (o *SSIE0_Type) GetSSISCR_RDFS() uint32 {
	return volatile.LoadUint32(&o.SSISCR.Reg) & 0x1f
}
func (o *SSIE0_Type) SetSSISCR_TDES(value uint32) {
	volatile.StoreUint32(&o.SSISCR.Reg, volatile.LoadUint32(&o.SSISCR.Reg)&^(0x1f00)|value<<8)
}
func (o *SSIE0_Type) GetSSISCR_TDES() uint32 {
	return (volatile.LoadUint32(&o.SSISCR.Reg) & 0x1f00) >> 8
}

// Consumer Electronics Control
type CEC_Type struct {
	CADR     volatile.Register16 // 0x0
	CECCTL1  volatile.Register8  // 0x2
	_        byte
	STATB    volatile.Register16 // 0x4
	STATL    volatile.Register16 // 0x6
	LGC0L    volatile.Register16 // 0x8
	LGC1L    volatile.Register16 // 0xA
	DATB     volatile.Register16 // 0xC
	NOMT     volatile.Register16 // 0xE
	STATLL   volatile.Register16 // 0x10
	STATLH   volatile.Register16 // 0x12
	STATBL   volatile.Register16 // 0x14
	STATBH   volatile.Register16 // 0x16
	LGC0LL   volatile.Register16 // 0x18
	LGC0LH   volatile.Register16 // 0x1A
	LGC1LL   volatile.Register16 // 0x1C
	LGC1LH   volatile.Register16 // 0x1E
	DATBL    volatile.Register16 // 0x20
	DATBH    volatile.Register16 // 0x22
	NOMP     volatile.Register16 // 0x24
	_        [2]byte
	CECEXMD  volatile.Register8 // 0x28
	_        byte
	CECEXMON volatile.Register8 // 0x2A
	_        [21]byte
	CTXD     volatile.Register8 // 0x40
	CRXD     volatile.Register8 // 0x41
	CECES    volatile.Register8 // 0x42
	CECS     volatile.Register8 // 0x43
	CECFC    volatile.Register8 // 0x44
	CECCTL0  volatile.Register8 // 0x45
}

// CEC.CADR: CEC Local Address Setting Register
func (o *CEC_Type) SetCADR_ADR00(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x1)|value)
}
func (o *CEC_Type) GetCADR_ADR00() uint16 {
	return volatile.LoadUint16(&o.CADR.Reg) & 0x1
}
func (o *CEC_Type) SetCADR_ADR01(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x2)|value<<1)
}
func (o *CEC_Type) GetCADR_ADR01() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x2) >> 1
}
func (o *CEC_Type) SetCADR_ADR02(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x4)|value<<2)
}
func (o *CEC_Type) GetCADR_ADR02() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x4) >> 2
}
func (o *CEC_Type) SetCADR_ADR03(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x8)|value<<3)
}
func (o *CEC_Type) GetCADR_ADR03() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x8) >> 3
}
func (o *CEC_Type) SetCADR_ADR04(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x10)|value<<4)
}
func (o *CEC_Type) GetCADR_ADR04() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x10) >> 4
}
func (o *CEC_Type) SetCADR_ADR05(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x20)|value<<5)
}
func (o *CEC_Type) GetCADR_ADR05() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x20) >> 5
}
func (o *CEC_Type) SetCADR_ADR06(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x40)|value<<6)
}
func (o *CEC_Type) GetCADR_ADR06() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x40) >> 6
}
func (o *CEC_Type) SetCADR_ADR07(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x80)|value<<7)
}
func (o *CEC_Type) GetCADR_ADR07() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x80) >> 7
}
func (o *CEC_Type) SetCADR_ADR08(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x100)|value<<8)
}
func (o *CEC_Type) GetCADR_ADR08() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x100) >> 8
}
func (o *CEC_Type) SetCADR_ADR09(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x200)|value<<9)
}
func (o *CEC_Type) GetCADR_ADR09() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x200) >> 9
}
func (o *CEC_Type) SetCADR_ADR10(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x400)|value<<10)
}
func (o *CEC_Type) GetCADR_ADR10() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x400) >> 10
}
func (o *CEC_Type) SetCADR_ADR11(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x800)|value<<11)
}
func (o *CEC_Type) GetCADR_ADR11() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x800) >> 11
}
func (o *CEC_Type) SetCADR_ADR12(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x1000)|value<<12)
}
func (o *CEC_Type) GetCADR_ADR12() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x1000) >> 12
}
func (o *CEC_Type) SetCADR_ADR13(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x2000)|value<<13)
}
func (o *CEC_Type) GetCADR_ADR13() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x2000) >> 13
}
func (o *CEC_Type) SetCADR_ADR14(value uint16) {
	volatile.StoreUint16(&o.CADR.Reg, volatile.LoadUint16(&o.CADR.Reg)&^(0x4000)|value<<14)
}
func (o *CEC_Type) GetCADR_ADR14() uint16 {
	return (volatile.LoadUint16(&o.CADR.Reg) & 0x4000) >> 14
}

// CEC.CECCTL1: CEC Control Register 1
func (o *CEC_Type) SetCECCTL1_SFT(value uint8) {
	volatile.StoreUint8(&o.CECCTL1.Reg, volatile.LoadUint8(&o.CECCTL1.Reg)&^(0x3)|value)
}
func (o *CEC_Type) GetCECCTL1_SFT() uint8 {
	return volatile.LoadUint8(&o.CECCTL1.Reg) & 0x3
}
func (o *CEC_Type) SetCECCTL1_CESEL(value uint8) {
	volatile.StoreUint8(&o.CECCTL1.Reg, volatile.LoadUint8(&o.CECCTL1.Reg)&^(0xc)|value<<2)
}
func (o *CEC_Type) GetCECCTL1_CESEL() uint8 {
	return (volatile.LoadUint8(&o.CECCTL1.Reg) & 0xc) >> 2
}
func (o *CEC_Type) SetCECCTL1_STERRD(value uint8) {
	volatile.StoreUint8(&o.CECCTL1.Reg, volatile.LoadUint8(&o.CECCTL1.Reg)&^(0x10)|value<<4)
}
func (o *CEC_Type) GetCECCTL1_STERRD() uint8 {
	return (volatile.LoadUint8(&o.CECCTL1.Reg) & 0x10) >> 4
}
func (o *CEC_Type) SetCECCTL1_BLERRD(value uint8) {
	volatile.StoreUint8(&o.CECCTL1.Reg, volatile.LoadUint8(&o.CECCTL1.Reg)&^(0x20)|value<<5)
}
func (o *CEC_Type) GetCECCTL1_BLERRD() uint8 {
	return (volatile.LoadUint8(&o.CECCTL1.Reg) & 0x20) >> 5
}
func (o *CEC_Type) SetCECCTL1_CINTMK(value uint8) {
	volatile.StoreUint8(&o.CECCTL1.Reg, volatile.LoadUint8(&o.CECCTL1.Reg)&^(0x40)|value<<6)
}
func (o *CEC_Type) GetCECCTL1_CINTMK() uint8 {
	return (volatile.LoadUint8(&o.CECCTL1.Reg) & 0x40) >> 6
}
func (o *CEC_Type) SetCECCTL1_CDFC(value uint8) {
	volatile.StoreUint8(&o.CECCTL1.Reg, volatile.LoadUint8(&o.CECCTL1.Reg)&^(0x80)|value<<7)
}
func (o *CEC_Type) GetCECCTL1_CDFC() uint8 {
	return (volatile.LoadUint8(&o.CECCTL1.Reg) & 0x80) >> 7
}

// CEC.STATB: CEC Transmission Start Bit Width Setting Register
func (o *CEC_Type) SetSTATB(value uint16) {
	volatile.StoreUint16(&o.STATB.Reg, volatile.LoadUint16(&o.STATB.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetSTATB() uint16 {
	return volatile.LoadUint16(&o.STATB.Reg) & 0x1ff
}

// CEC.STATL: CEC Transmission Start Bit Low Width Setting Register
func (o *CEC_Type) SetSTATL(value uint16) {
	volatile.StoreUint16(&o.STATL.Reg, volatile.LoadUint16(&o.STATL.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetSTATL() uint16 {
	return volatile.LoadUint16(&o.STATL.Reg) & 0x1ff
}

// CEC.LGC0L: CEC Transmission Logical 0 Low Width Setting Register
func (o *CEC_Type) SetLGC0L(value uint16) {
	volatile.StoreUint16(&o.LGC0L.Reg, volatile.LoadUint16(&o.LGC0L.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetLGC0L() uint16 {
	return volatile.LoadUint16(&o.LGC0L.Reg) & 0x1ff
}

// CEC.LGC1L: CEC Transmission Logical 1 Low Width Setting Register
func (o *CEC_Type) SetLGC1L(value uint16) {
	volatile.StoreUint16(&o.LGC1L.Reg, volatile.LoadUint16(&o.LGC1L.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetLGC1L() uint16 {
	return volatile.LoadUint16(&o.LGC1L.Reg) & 0x1ff
}

// CEC.DATB: CEC Transmission Data Bit Width Setting Register
func (o *CEC_Type) SetDATB(value uint16) {
	volatile.StoreUint16(&o.DATB.Reg, volatile.LoadUint16(&o.DATB.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetDATB() uint16 {
	return volatile.LoadUint16(&o.DATB.Reg) & 0x1ff
}

// CEC.NOMT: CEC Reception Data Sampling Time Setting Register
func (o *CEC_Type) SetNOMT(value uint16) {
	volatile.StoreUint16(&o.NOMT.Reg, volatile.LoadUint16(&o.NOMT.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetNOMT() uint16 {
	return volatile.LoadUint16(&o.NOMT.Reg) & 0x1ff
}

// CEC.STATLL: CEC Reception Start Bit Minimum Low Width Setting Register
func (o *CEC_Type) SetSTATLL(value uint16) {
	volatile.StoreUint16(&o.STATLL.Reg, volatile.LoadUint16(&o.STATLL.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetSTATLL() uint16 {
	return volatile.LoadUint16(&o.STATLL.Reg) & 0x1ff
}

// CEC.STATLH: CEC Reception Start Bit Maximum Low Width Setting Register
func (o *CEC_Type) SetSTATLH(value uint16) {
	volatile.StoreUint16(&o.STATLH.Reg, volatile.LoadUint16(&o.STATLH.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetSTATLH() uint16 {
	return volatile.LoadUint16(&o.STATLH.Reg) & 0x1ff
}

// CEC.STATBL: CEC Reception Start Bit Minimum Bit Width Setting Register
func (o *CEC_Type) SetSTATBL(value uint16) {
	volatile.StoreUint16(&o.STATBL.Reg, volatile.LoadUint16(&o.STATBL.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetSTATBL() uint16 {
	return volatile.LoadUint16(&o.STATBL.Reg) & 0x1ff
}

// CEC.STATBH: CEC Reception Start Bit Maximum Bit Width Setting Register
func (o *CEC_Type) SetSTATBH(value uint16) {
	volatile.StoreUint16(&o.STATBH.Reg, volatile.LoadUint16(&o.STATBH.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetSTATBH() uint16 {
	return volatile.LoadUint16(&o.STATBH.Reg) & 0x1ff
}

// CEC.LGC0LL: CEC Reception Logical 0 Minimum Low Width Setting Register
func (o *CEC_Type) SetLGC0LL(value uint16) {
	volatile.StoreUint16(&o.LGC0LL.Reg, volatile.LoadUint16(&o.LGC0LL.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetLGC0LL() uint16 {
	return volatile.LoadUint16(&o.LGC0LL.Reg) & 0x1ff
}

// CEC.LGC0LH: CEC Reception Logical 0 Maximum Low Width Setting Register
func (o *CEC_Type) SetLGC0LH(value uint16) {
	volatile.StoreUint16(&o.LGC0LH.Reg, volatile.LoadUint16(&o.LGC0LH.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetLGC0LH() uint16 {
	return volatile.LoadUint16(&o.LGC0LH.Reg) & 0x1ff
}

// CEC.LGC1LL: CEC Reception Logical 1 Minimum Low Width Setting Register
func (o *CEC_Type) SetLGC1LL(value uint16) {
	volatile.StoreUint16(&o.LGC1LL.Reg, volatile.LoadUint16(&o.LGC1LL.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetLGC1LL() uint16 {
	return volatile.LoadUint16(&o.LGC1LL.Reg) & 0x1ff
}

// CEC.LGC1LH: CEC Reception Logical 1 Maximum Low Width Setting Register
func (o *CEC_Type) SetLGC1LH(value uint16) {
	volatile.StoreUint16(&o.LGC1LH.Reg, volatile.LoadUint16(&o.LGC1LH.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetLGC1LH() uint16 {
	return volatile.LoadUint16(&o.LGC1LH.Reg) & 0x1ff
}

// CEC.DATBL: CEC Reception Data Bit Minimum Bit Width Setting Register
func (o *CEC_Type) SetDATBL(value uint16) {
	volatile.StoreUint16(&o.DATBL.Reg, volatile.LoadUint16(&o.DATBL.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetDATBL() uint16 {
	return volatile.LoadUint16(&o.DATBL.Reg) & 0x1ff
}

// CEC.DATBH: CEC Reception Data Bit Maximum Bit Width Setting Register
func (o *CEC_Type) SetDATBH(value uint16) {
	volatile.StoreUint16(&o.DATBH.Reg, volatile.LoadUint16(&o.DATBH.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetDATBH() uint16 {
	return volatile.LoadUint16(&o.DATBH.Reg) & 0x1ff
}

// CEC.NOMP: CEC Data Bit Reference Width Setting Register
func (o *CEC_Type) SetNOMP(value uint16) {
	volatile.StoreUint16(&o.NOMP.Reg, volatile.LoadUint16(&o.NOMP.Reg)&^(0x1ff)|value)
}
func (o *CEC_Type) GetNOMP() uint16 {
	return volatile.LoadUint16(&o.NOMP.Reg) & 0x1ff
}

// CEC.CECEXMD: CEC Extension Mode Register
func (o *CEC_Type) SetCECEXMD_LERPLEN(value uint8) {
	volatile.StoreUint8(&o.CECEXMD.Reg, volatile.LoadUint8(&o.CECEXMD.Reg)&^(0x10)|value<<4)
}
func (o *CEC_Type) GetCECEXMD_LERPLEN() uint8 {
	return (volatile.LoadUint8(&o.CECEXMD.Reg) & 0x10) >> 4
}
func (o *CEC_Type) SetCECEXMD_RERCVEN(value uint8) {
	volatile.StoreUint8(&o.CECEXMD.Reg, volatile.LoadUint8(&o.CECEXMD.Reg)&^(0x20)|value<<5)
}
func (o *CEC_Type) GetCECEXMD_RERCVEN() uint8 {
	return (volatile.LoadUint8(&o.CECEXMD.Reg) & 0x20) >> 5
}
func (o *CEC_Type) SetCECEXMD_RCVINTDSEL(value uint8) {
	volatile.StoreUint8(&o.CECEXMD.Reg, volatile.LoadUint8(&o.CECEXMD.Reg)&^(0x80)|value<<7)
}
func (o *CEC_Type) GetCECEXMD_RCVINTDSEL() uint8 {
	return (volatile.LoadUint8(&o.CECEXMD.Reg) & 0x80) >> 7
}

// CEC.CECEXMON: CEC Extension Monitor Register
func (o *CEC_Type) SetCECEXMON_CECLNMON(value uint8) {
	volatile.StoreUint8(&o.CECEXMON.Reg, volatile.LoadUint8(&o.CECEXMON.Reg)&^(0x1)|value)
}
func (o *CEC_Type) GetCECEXMON_CECLNMON() uint8 {
	return volatile.LoadUint8(&o.CECEXMON.Reg) & 0x1
}
func (o *CEC_Type) SetCECEXMON_ACKF(value uint8) {
	volatile.StoreUint8(&o.CECEXMON.Reg, volatile.LoadUint8(&o.CECEXMON.Reg)&^(0x2)|value<<1)
}
func (o *CEC_Type) GetCECEXMON_ACKF() uint8 {
	return (volatile.LoadUint8(&o.CECEXMON.Reg) & 0x2) >> 1
}

// CEC.CECES: CEC Communication Error Status Register
func (o *CEC_Type) SetCECES_OERR(value uint8) {
	volatile.StoreUint8(&o.CECES.Reg, volatile.LoadUint8(&o.CECES.Reg)&^(0x1)|value)
}
func (o *CEC_Type) GetCECES_OERR() uint8 {
	return volatile.LoadUint8(&o.CECES.Reg) & 0x1
}
func (o *CEC_Type) SetCECES_UERR(value uint8) {
	volatile.StoreUint8(&o.CECES.Reg, volatile.LoadUint8(&o.CECES.Reg)&^(0x2)|value<<1)
}
func (o *CEC_Type) GetCECES_UERR() uint8 {
	return (volatile.LoadUint8(&o.CECES.Reg) & 0x2) >> 1
}
func (o *CEC_Type) SetCECES_ACKERR(value uint8) {
	volatile.StoreUint8(&o.CECES.Reg, volatile.LoadUint8(&o.CECES.Reg)&^(0x4)|value<<2)
}
func (o *CEC_Type) GetCECES_ACKERR() uint8 {
	return (volatile.LoadUint8(&o.CECES.Reg) & 0x4) >> 2
}
func (o *CEC_Type) SetCECES_TERR(value uint8) {
	volatile.StoreUint8(&o.CECES.Reg, volatile.LoadUint8(&o.CECES.Reg)&^(0x8)|value<<3)
}
func (o *CEC_Type) GetCECES_TERR() uint8 {
	return (volatile.LoadUint8(&o.CECES.Reg) & 0x8) >> 3
}
func (o *CEC_Type) SetCECES_TXERR(value uint8) {
	volatile.StoreUint8(&o.CECES.Reg, volatile.LoadUint8(&o.CECES.Reg)&^(0x10)|value<<4)
}
func (o *CEC_Type) GetCECES_TXERR() uint8 {
	return (volatile.LoadUint8(&o.CECES.Reg) & 0x10) >> 4
}
func (o *CEC_Type) SetCECES_AERR(value uint8) {
	volatile.StoreUint8(&o.CECES.Reg, volatile.LoadUint8(&o.CECES.Reg)&^(0x20)|value<<5)
}
func (o *CEC_Type) GetCECES_AERR() uint8 {
	return (volatile.LoadUint8(&o.CECES.Reg) & 0x20) >> 5
}
func (o *CEC_Type) SetCECES_BLERR(value uint8) {
	volatile.StoreUint8(&o.CECES.Reg, volatile.LoadUint8(&o.CECES.Reg)&^(0x40)|value<<6)
}
func (o *CEC_Type) GetCECES_BLERR() uint8 {
	return (volatile.LoadUint8(&o.CECES.Reg) & 0x40) >> 6
}

// CEC.CECS: CEC Communication Status Register
func (o *CEC_Type) SetCECS_ADRF(value uint8) {
	volatile.StoreUint8(&o.CECS.Reg, volatile.LoadUint8(&o.CECS.Reg)&^(0x1)|value)
}
func (o *CEC_Type) GetCECS_ADRF() uint8 {
	return volatile.LoadUint8(&o.CECS.Reg) & 0x1
}
func (o *CEC_Type) SetCECS_BUSST(value uint8) {
	volatile.StoreUint8(&o.CECS.Reg, volatile.LoadUint8(&o.CECS.Reg)&^(0x2)|value<<1)
}
func (o *CEC_Type) GetCECS_BUSST() uint8 {
	return (volatile.LoadUint8(&o.CECS.Reg) & 0x2) >> 1
}
func (o *CEC_Type) SetCECS_TXST(value uint8) {
	volatile.StoreUint8(&o.CECS.Reg, volatile.LoadUint8(&o.CECS.Reg)&^(0x4)|value<<2)
}
func (o *CEC_Type) GetCECS_TXST() uint8 {
	return (volatile.LoadUint8(&o.CECS.Reg) & 0x4) >> 2
}
func (o *CEC_Type) SetCECS_EOMF(value uint8) {
	volatile.StoreUint8(&o.CECS.Reg, volatile.LoadUint8(&o.CECS.Reg)&^(0x8)|value<<3)
}
func (o *CEC_Type) GetCECS_EOMF() uint8 {
	return (volatile.LoadUint8(&o.CECS.Reg) & 0x8) >> 3
}
func (o *CEC_Type) SetCECS_ITCEF(value uint8) {
	volatile.StoreUint8(&o.CECS.Reg, volatile.LoadUint8(&o.CECS.Reg)&^(0x10)|value<<4)
}
func (o *CEC_Type) GetCECS_ITCEF() uint8 {
	return (volatile.LoadUint8(&o.CECS.Reg) & 0x10) >> 4
}
func (o *CEC_Type) SetCECS_SFTST(value uint8) {
	volatile.StoreUint8(&o.CECS.Reg, volatile.LoadUint8(&o.CECS.Reg)&^(0x80)|value<<7)
}
func (o *CEC_Type) GetCECS_SFTST() uint8 {
	return (volatile.LoadUint8(&o.CECS.Reg) & 0x80) >> 7
}

// CEC.CECFC: CEC Communication Error Flag Clear Trigger Register
func (o *CEC_Type) SetCECFC_OCTRG(value uint8) {
	volatile.StoreUint8(&o.CECFC.Reg, volatile.LoadUint8(&o.CECFC.Reg)&^(0x1)|value)
}
func (o *CEC_Type) GetCECFC_OCTRG() uint8 {
	return volatile.LoadUint8(&o.CECFC.Reg) & 0x1
}
func (o *CEC_Type) SetCECFC_UCTRG(value uint8) {
	volatile.StoreUint8(&o.CECFC.Reg, volatile.LoadUint8(&o.CECFC.Reg)&^(0x2)|value<<1)
}
func (o *CEC_Type) GetCECFC_UCTRG() uint8 {
	return (volatile.LoadUint8(&o.CECFC.Reg) & 0x2) >> 1
}
func (o *CEC_Type) SetCECFC_ACKCTRG(value uint8) {
	volatile.StoreUint8(&o.CECFC.Reg, volatile.LoadUint8(&o.CECFC.Reg)&^(0x4)|value<<2)
}
func (o *CEC_Type) GetCECFC_ACKCTRG() uint8 {
	return (volatile.LoadUint8(&o.CECFC.Reg) & 0x4) >> 2
}
func (o *CEC_Type) SetCECFC_TCTRG(value uint8) {
	volatile.StoreUint8(&o.CECFC.Reg, volatile.LoadUint8(&o.CECFC.Reg)&^(0x8)|value<<3)
}
func (o *CEC_Type) GetCECFC_TCTRG() uint8 {
	return (volatile.LoadUint8(&o.CECFC.Reg) & 0x8) >> 3
}
func (o *CEC_Type) SetCECFC_TXCTRG(value uint8) {
	volatile.StoreUint8(&o.CECFC.Reg, volatile.LoadUint8(&o.CECFC.Reg)&^(0x10)|value<<4)
}
func (o *CEC_Type) GetCECFC_TXCTRG() uint8 {
	return (volatile.LoadUint8(&o.CECFC.Reg) & 0x10) >> 4
}
func (o *CEC_Type) SetCECFC_ACTRG(value uint8) {
	volatile.StoreUint8(&o.CECFC.Reg, volatile.LoadUint8(&o.CECFC.Reg)&^(0x20)|value<<5)
}
func (o *CEC_Type) GetCECFC_ACTRG() uint8 {
	return (volatile.LoadUint8(&o.CECFC.Reg) & 0x20) >> 5
}
func (o *CEC_Type) SetCECFC_BLCTRG(value uint8) {
	volatile.StoreUint8(&o.CECFC.Reg, volatile.LoadUint8(&o.CECFC.Reg)&^(0x40)|value<<6)
}
func (o *CEC_Type) GetCECFC_BLCTRG() uint8 {
	return (volatile.LoadUint8(&o.CECFC.Reg) & 0x40) >> 6
}

// CEC.CECCTL0: CEC Control Register 0
func (o *CEC_Type) SetCECCTL0_EOM(value uint8) {
	volatile.StoreUint8(&o.CECCTL0.Reg, volatile.LoadUint8(&o.CECCTL0.Reg)&^(0x1)|value)
}
func (o *CEC_Type) GetCECCTL0_EOM() uint8 {
	return volatile.LoadUint8(&o.CECCTL0.Reg) & 0x1
}
func (o *CEC_Type) SetCECCTL0_CECRXEN(value uint8) {
	volatile.StoreUint8(&o.CECCTL0.Reg, volatile.LoadUint8(&o.CECCTL0.Reg)&^(0x2)|value<<1)
}
func (o *CEC_Type) GetCECCTL0_CECRXEN() uint8 {
	return (volatile.LoadUint8(&o.CECCTL0.Reg) & 0x2) >> 1
}
func (o *CEC_Type) SetCECCTL0_TXTRG(value uint8) {
	volatile.StoreUint8(&o.CECCTL0.Reg, volatile.LoadUint8(&o.CECCTL0.Reg)&^(0x4)|value<<2)
}
func (o *CEC_Type) GetCECCTL0_TXTRG() uint8 {
	return (volatile.LoadUint8(&o.CECCTL0.Reg) & 0x4) >> 2
}
func (o *CEC_Type) SetCECCTL0_CCL(value uint8) {
	volatile.StoreUint8(&o.CECCTL0.Reg, volatile.LoadUint8(&o.CECCTL0.Reg)&^(0x38)|value<<3)
}
func (o *CEC_Type) GetCECCTL0_CCL() uint8 {
	return (volatile.LoadUint8(&o.CECCTL0.Reg) & 0x38) >> 3
}
func (o *CEC_Type) SetCECCTL0_ACKTEN(value uint8) {
	volatile.StoreUint8(&o.CECCTL0.Reg, volatile.LoadUint8(&o.CECCTL0.Reg)&^(0x40)|value<<6)
}
func (o *CEC_Type) GetCECCTL0_ACKTEN() uint8 {
	return (volatile.LoadUint8(&o.CECCTL0.Reg) & 0x40) >> 6
}
func (o *CEC_Type) SetCECCTL0_CECE(value uint8) {
	volatile.StoreUint8(&o.CECCTL0.Reg, volatile.LoadUint8(&o.CECCTL0.Reg)&^(0x80)|value<<7)
}
func (o *CEC_Type) GetCECCTL0_CECE() uint8 {
	return (volatile.LoadUint8(&o.CECCTL0.Reg) & 0x80) >> 7
}

// CANFD
type CANFD_B_Type struct {
	CFDC0NCFG     volatile.Register32 // 0x0
	CFDC0CTR      volatile.Register32 // 0x4
	CFDC0STS      volatile.Register32 // 0x8
	CFDC0ERFL     volatile.Register32 // 0xC
	_             [4]byte
	CFDGCFG       volatile.Register32 // 0x14
	CFDGCTR       volatile.Register32 // 0x18
	CFDGSTS       volatile.Register32 // 0x1C
	CFDGERFL      volatile.Register32 // 0x20
	CFDGTSC       volatile.Register32 // 0x24
	CFDGAFLECTR   volatile.Register32 // 0x28
	CFDGAFLCFG    volatile.Register32 // 0x2C
	CFDRMNB       volatile.Register32 // 0x30
	CFDRMND       volatile.Register32 // 0x34
	CFDRMIEC      volatile.Register32 // 0x38
	CFDRFCC0      volatile.Register32 // 0x3C
	CFDRFCC1      volatile.Register32 // 0x40
	CFDRFSTS0     volatile.Register32 // 0x44
	CFDRFSTS1     volatile.Register32 // 0x48
	CFDRFPCTR0    volatile.Register32 // 0x4C
	CFDRFPCTR1    volatile.Register32 // 0x50
	CFDCFCC       volatile.Register32 // 0x54
	CFDCFSTS      volatile.Register32 // 0x58
	CFDCFPCTR     volatile.Register32 // 0x5C
	CFDFESTS      volatile.Register32 // 0x60
	CFDFFSTS      volatile.Register32 // 0x64
	CFDFMSTS      volatile.Register32 // 0x68
	CFDRFISTS     volatile.Register32 // 0x6C
	CFDTMC0       volatile.Register8  // 0x70
	CFDTMC1       volatile.Register8  // 0x71
	CFDTMC2       volatile.Register8  // 0x72
	CFDTMC3       volatile.Register8  // 0x73
	CFDTMSTS0     volatile.Register8  // 0x74
	CFDTMSTS1     volatile.Register8  // 0x75
	CFDTMSTS2     volatile.Register8  // 0x76
	CFDTMSTS3     volatile.Register8  // 0x77
	CFDTMTRSTS    volatile.Register32 // 0x78
	CFDTMTARSTS   volatile.Register32 // 0x7C
	CFDTMTCSTS    volatile.Register32 // 0x80
	CFDTMTASTS    volatile.Register32 // 0x84
	CFDTMIEC      volatile.Register32 // 0x88
	CFDTXQCC      volatile.Register32 // 0x8C
	CFDTXQSTS     volatile.Register32 // 0x90
	CFDTXQPCTR    volatile.Register32 // 0x94
	CFDTHLCC      volatile.Register32 // 0x98
	CFDTHLSTS     volatile.Register32 // 0x9C
	CFDTHLPCTR    volatile.Register32 // 0xA0
	CFDGTINTSTS   volatile.Register32 // 0xA4
	CFDGTSTCFG    volatile.Register32 // 0xA8
	CFDGTSTCTR    volatile.Register32 // 0xAC
	CFDGFDCFG     volatile.Register32 // 0xB0
	_             [4]byte
	CFDGLOCKK     volatile.Register32 // 0xB8
	_             [4]byte
	CFDGAFLIGNENT volatile.Register32 // 0xC0
	CFDGAFLIGNCTR volatile.Register32 // 0xC4
	CFDCDTCT      volatile.Register32 // 0xC8
	CFDCDTSTS     volatile.Register32 // 0xCC
	_             [8]byte
	CFDGRSTC      volatile.Register32 // 0xD8
	_             [36]byte
	CFDC0DCFG     volatile.Register32 // 0x100
	CFDC0FDCFG    volatile.Register32 // 0x104
	CFDC0FDCTR    volatile.Register32 // 0x108
	CFDC0FDSTS    volatile.Register32 // 0x10C
	CFDC0FDCRC    volatile.Register32 // 0x110
	_             [12]byte
	CFDGAFLID1    volatile.Register32 // 0x120
	CFDGAFLM1     volatile.Register32 // 0x124
	CFDGAFLP01    volatile.Register32 // 0x128
	CFDGAFLP11    volatile.Register32 // 0x12C
	CFDGAFLID2    volatile.Register32 // 0x130
	CFDGAFLM2     volatile.Register32 // 0x134
	CFDGAFLP02    volatile.Register32 // 0x138
	CFDGAFLP12    volatile.Register32 // 0x13C
	CFDGAFLID3    volatile.Register32 // 0x140
	CFDGAFLM3     volatile.Register32 // 0x144
	CFDGAFLP03    volatile.Register32 // 0x148
	CFDGAFLP13    volatile.Register32 // 0x14C
	CFDGAFLID4    volatile.Register32 // 0x150
	CFDGAFLM4     volatile.Register32 // 0x154
	CFDGAFLP04    volatile.Register32 // 0x158
	CFDGAFLP14    volatile.Register32 // 0x15C
	CFDGAFLID5    volatile.Register32 // 0x160
	CFDGAFLM5     volatile.Register32 // 0x164
	CFDGAFLP05    volatile.Register32 // 0x168
	CFDGAFLP15    volatile.Register32 // 0x16C
	CFDGAFLID6    volatile.Register32 // 0x170
	CFDGAFLM6     volatile.Register32 // 0x174
	CFDGAFLP06    volatile.Register32 // 0x178
	CFDGAFLP16    volatile.Register32 // 0x17C
	CFDGAFLID7    volatile.Register32 // 0x180
	CFDGAFLM7     volatile.Register32 // 0x184
	CFDGAFLP07    volatile.Register32 // 0x188
	CFDGAFLP17    volatile.Register32 // 0x18C
	CFDGAFLID8    volatile.Register32 // 0x190
	CFDGAFLM8     volatile.Register32 // 0x194
	CFDGAFLP08    volatile.Register32 // 0x198
	CFDGAFLP18    volatile.Register32 // 0x19C
	CFDGAFLID9    volatile.Register32 // 0x1A0
	CFDGAFLM9     volatile.Register32 // 0x1A4
	CFDGAFLP09    volatile.Register32 // 0x1A8
	CFDGAFLP19    volatile.Register32 // 0x1AC
	CFDGAFLID10   volatile.Register32 // 0x1B0
	CFDGAFLM10    volatile.Register32 // 0x1B4
	CFDGAFLP010   volatile.Register32 // 0x1B8
	CFDGAFLP110   volatile.Register32 // 0x1BC
	CFDGAFLID11   volatile.Register32 // 0x1C0
	CFDGAFLM11    volatile.Register32 // 0x1C4
	CFDGAFLP011   volatile.Register32 // 0x1C8
	CFDGAFLP111   volatile.Register32 // 0x1CC
	CFDGAFLID12   volatile.Register32 // 0x1D0
	CFDGAFLM12    volatile.Register32 // 0x1D4
	CFDGAFLP012   volatile.Register32 // 0x1D8
	CFDGAFLP112   volatile.Register32 // 0x1DC
	CFDGAFLID13   volatile.Register32 // 0x1E0
	CFDGAFLM13    volatile.Register32 // 0x1E4
	CFDGAFLP013   volatile.Register32 // 0x1E8
	CFDGAFLP113   volatile.Register32 // 0x1EC
	CFDGAFLID14   volatile.Register32 // 0x1F0
	CFDGAFLM14    volatile.Register32 // 0x1F4
	CFDGAFLP014   volatile.Register32 // 0x1F8
	CFDGAFLP114   volatile.Register32 // 0x1FC
	CFDGAFLID15   volatile.Register32 // 0x200
	CFDGAFLM15    volatile.Register32 // 0x204
	CFDGAFLP015   volatile.Register32 // 0x208
	CFDGAFLP115   volatile.Register32 // 0x20C
	CFDGAFLID16   volatile.Register32 // 0x210
	CFDGAFLM16    volatile.Register32 // 0x214
	CFDGAFLP016   volatile.Register32 // 0x218
	CFDGAFLP116   volatile.Register32 // 0x21C
	_             [96]byte
	CFDRPGACC0    volatile.Register32 // 0x280
	CFDRPGACC1    volatile.Register32 // 0x284
	CFDRPGACC2    volatile.Register32 // 0x288
	CFDRPGACC3    volatile.Register32 // 0x28C
	CFDRPGACC4    volatile.Register32 // 0x290
	CFDRPGACC5    volatile.Register32 // 0x294
	CFDRPGACC6    volatile.Register32 // 0x298
	CFDRPGACC7    volatile.Register32 // 0x29C
	CFDRPGACC8    volatile.Register32 // 0x2A0
	CFDRPGACC9    volatile.Register32 // 0x2A4
	CFDRPGACC10   volatile.Register32 // 0x2A8
	CFDRPGACC11   volatile.Register32 // 0x2AC
	CFDRPGACC12   volatile.Register32 // 0x2B0
	CFDRPGACC13   volatile.Register32 // 0x2B4
	CFDRPGACC14   volatile.Register32 // 0x2B8
	CFDRPGACC15   volatile.Register32 // 0x2BC
	CFDRPGACC16   volatile.Register32 // 0x2C0
	CFDRPGACC17   volatile.Register32 // 0x2C4
	CFDRPGACC18   volatile.Register32 // 0x2C8
	CFDRPGACC19   volatile.Register32 // 0x2CC
	CFDRPGACC20   volatile.Register32 // 0x2D0
	CFDRPGACC21   volatile.Register32 // 0x2D4
	CFDRPGACC22   volatile.Register32 // 0x2D8
	CFDRPGACC23   volatile.Register32 // 0x2DC
	CFDRPGACC24   volatile.Register32 // 0x2E0
	CFDRPGACC25   volatile.Register32 // 0x2E4
	CFDRPGACC26   volatile.Register32 // 0x2E8
	CFDRPGACC27   volatile.Register32 // 0x2EC
	CFDRPGACC28   volatile.Register32 // 0x2F0
	CFDRPGACC29   volatile.Register32 // 0x2F4
	CFDRPGACC30   volatile.Register32 // 0x2F8
	CFDRPGACC31   volatile.Register32 // 0x2FC
	CFDRPGACC32   volatile.Register32 // 0x300
	CFDRPGACC33   volatile.Register32 // 0x304
	CFDRPGACC34   volatile.Register32 // 0x308
	CFDRPGACC35   volatile.Register32 // 0x30C
	CFDRPGACC36   volatile.Register32 // 0x310
	CFDRPGACC37   volatile.Register32 // 0x314
	CFDRPGACC38   volatile.Register32 // 0x318
	CFDRPGACC39   volatile.Register32 // 0x31C
	CFDRPGACC40   volatile.Register32 // 0x320
	CFDRPGACC41   volatile.Register32 // 0x324
	CFDRPGACC42   volatile.Register32 // 0x328
	CFDRPGACC43   volatile.Register32 // 0x32C
	CFDRPGACC44   volatile.Register32 // 0x330
	CFDRPGACC45   volatile.Register32 // 0x334
	CFDRPGACC46   volatile.Register32 // 0x338
	CFDRPGACC47   volatile.Register32 // 0x33C
	CFDRPGACC48   volatile.Register32 // 0x340
	CFDRPGACC49   volatile.Register32 // 0x344
	CFDRPGACC50   volatile.Register32 // 0x348
	CFDRPGACC51   volatile.Register32 // 0x34C
	CFDRPGACC52   volatile.Register32 // 0x350
	CFDRPGACC53   volatile.Register32 // 0x354
	CFDRPGACC54   volatile.Register32 // 0x358
	CFDRPGACC55   volatile.Register32 // 0x35C
	CFDRPGACC56   volatile.Register32 // 0x360
	CFDRPGACC57   volatile.Register32 // 0x364
	CFDRPGACC58   volatile.Register32 // 0x368
	CFDRPGACC59   volatile.Register32 // 0x36C
	CFDRPGACC60   volatile.Register32 // 0x370
	CFDRPGACC61   volatile.Register32 // 0x374
	CFDRPGACC62   volatile.Register32 // 0x378
	CFDRPGACC63   volatile.Register32 // 0x37C
	_             [416]byte
	CFDRFID0      volatile.Register32 // 0x520
	CFDRFPTR0     volatile.Register32 // 0x524
	CFDRFFDSTS0   volatile.Register32 // 0x528
	CFDRFDF0_0    volatile.Register32 // 0x52C
	CFDRFDF0_1    volatile.Register32 // 0x530
	CFDRFDF0_2    volatile.Register32 // 0x534
	CFDRFDF0_3    volatile.Register32 // 0x538
	CFDRFDF0_4    volatile.Register32 // 0x53C
	CFDRFDF0_5    volatile.Register32 // 0x540
	CFDRFDF0_6    volatile.Register32 // 0x544
	CFDRFDF0_7    volatile.Register32 // 0x548
	CFDRFDF0_8    volatile.Register32 // 0x54C
	CFDRFDF0_9    volatile.Register32 // 0x550
	CFDRFDF0_10   volatile.Register32 // 0x554
	CFDRFDF0_11   volatile.Register32 // 0x558
	CFDRFDF0_12   volatile.Register32 // 0x55C
	CFDRFDF0_13   volatile.Register32 // 0x560
	CFDRFDF0_14   volatile.Register32 // 0x564
	CFDRFDF0_15   volatile.Register32 // 0x568
	CFDRFID1      volatile.Register32 // 0x56C
	CFDRFPTR1     volatile.Register32 // 0x570
	CFDRFFDSTS1   volatile.Register32 // 0x574
	CFDRFDF1_0    volatile.Register32 // 0x578
	CFDRFDF1_1    volatile.Register32 // 0x57C
	CFDRFDF1_2    volatile.Register32 // 0x580
	CFDRFDF1_3    volatile.Register32 // 0x584
	CFDRFDF1_4    volatile.Register32 // 0x588
	CFDRFDF1_5    volatile.Register32 // 0x58C
	CFDRFDF1_6    volatile.Register32 // 0x590
	CFDRFDF1_7    volatile.Register32 // 0x594
	CFDRFDF1_8    volatile.Register32 // 0x598
	CFDRFDF1_9    volatile.Register32 // 0x59C
	CFDRFDF1_10   volatile.Register32 // 0x5A0
	CFDRFDF1_11   volatile.Register32 // 0x5A4
	CFDRFDF1_12   volatile.Register32 // 0x5A8
	CFDRFDF1_13   volatile.Register32 // 0x5AC
	CFDRFDF1_14   volatile.Register32 // 0x5B0
	CFDRFDF1_15   volatile.Register32 // 0x5B4
	CFDCFID       volatile.Register32 // 0x5B8
	CFDCFPTR      volatile.Register32 // 0x5BC
	CFDCFFDCSTS   volatile.Register32 // 0x5C0
	CFDCFDF0      volatile.Register32 // 0x5C4
	CFDCFDF1      volatile.Register32 // 0x5C8
	CFDCFDF2      volatile.Register32 // 0x5CC
	CFDCFDF3      volatile.Register32 // 0x5D0
	CFDCFDF4      volatile.Register32 // 0x5D4
	CFDCFDF5      volatile.Register32 // 0x5D8
	CFDCFDF6      volatile.Register32 // 0x5DC
	CFDCFDF7      volatile.Register32 // 0x5E0
	CFDCFDF8      volatile.Register32 // 0x5E4
	CFDCFDF9      volatile.Register32 // 0x5E8
	CFDCFDF10     volatile.Register32 // 0x5EC
	CFDCFDF11     volatile.Register32 // 0x5F0
	CFDCFDF12     volatile.Register32 // 0x5F4
	CFDCFDF13     volatile.Register32 // 0x5F8
	CFDCFDF14     volatile.Register32 // 0x5FC
	CFDCFDF15     volatile.Register32 // 0x600
	CFDTMID0      volatile.Register32 // 0x604
	CFDTMPTR0     volatile.Register32 // 0x608
	CFDTMFDCTR0   volatile.Register32 // 0x60C
	CFDTMDF0_0    volatile.Register32 // 0x610
	CFDTMDF0_1    volatile.Register32 // 0x614
	CFDTMDF0_2    volatile.Register32 // 0x618
	CFDTMDF0_3    volatile.Register32 // 0x61C
	CFDTMDF0_4    volatile.Register32 // 0x620
	CFDTMDF0_5    volatile.Register32 // 0x624
	CFDTMDF0_6    volatile.Register32 // 0x628
	CFDTMDF0_7    volatile.Register32 // 0x62C
	CFDTMDF0_8    volatile.Register32 // 0x630
	CFDTMDF0_9    volatile.Register32 // 0x634
	CFDTMDF0_10   volatile.Register32 // 0x638
	CFDTMDF0_11   volatile.Register32 // 0x63C
	CFDTMDF0_12   volatile.Register32 // 0x640
	CFDTMDF0_13   volatile.Register32 // 0x644
	CFDTMDF0_14   volatile.Register32 // 0x648
	CFDTMDF0_15   volatile.Register32 // 0x64C
	CFDTMID1      volatile.Register32 // 0x650
	CFDTMPTR1     volatile.Register32 // 0x654
	CFDTMFDCTR1   volatile.Register32 // 0x658
	CFDTMDF1_0    volatile.Register32 // 0x65C
	CFDTMDF1_1    volatile.Register32 // 0x660
	CFDTMDF1_2    volatile.Register32 // 0x664
	CFDTMDF1_3    volatile.Register32 // 0x668
	CFDTMDF1_4    volatile.Register32 // 0x66C
	CFDTMDF1_5    volatile.Register32 // 0x670
	CFDTMDF1_6    volatile.Register32 // 0x674
	CFDTMDF1_7    volatile.Register32 // 0x678
	CFDTMDF1_8    volatile.Register32 // 0x67C
	CFDTMDF1_9    volatile.Register32 // 0x680
	CFDTMDF1_10   volatile.Register32 // 0x684
	CFDTMDF1_11   volatile.Register32 // 0x688
	CFDTMDF1_12   volatile.Register32 // 0x68C
	CFDTMDF1_13   volatile.Register32 // 0x690
	CFDTMDF1_14   volatile.Register32 // 0x694
	CFDTMDF1_15   volatile.Register32 // 0x698
	CFDTMID2      volatile.Register32 // 0x69C
	CFDTMPTR2     volatile.Register32 // 0x6A0
	CFDTMFDCTR2   volatile.Register32 // 0x6A4
	CFDTMDF2_0    volatile.Register32 // 0x6A8
	CFDTMDF2_1    volatile.Register32 // 0x6AC
	CFDTMDF2_2    volatile.Register32 // 0x6B0
	CFDTMDF2_3    volatile.Register32 // 0x6B4
	CFDTMDF2_4    volatile.Register32 // 0x6B8
	CFDTMDF2_5    volatile.Register32 // 0x6BC
	CFDTMDF2_6    volatile.Register32 // 0x6C0
	CFDTMDF2_7    volatile.Register32 // 0x6C4
	CFDTMDF2_8    volatile.Register32 // 0x6C8
	CFDTMDF2_9    volatile.Register32 // 0x6CC
	CFDTMDF2_10   volatile.Register32 // 0x6D0
	CFDTMDF2_11   volatile.Register32 // 0x6D4
	CFDTMDF2_12   volatile.Register32 // 0x6D8
	CFDTMDF2_13   volatile.Register32 // 0x6DC
	CFDTMDF2_14   volatile.Register32 // 0x6E0
	CFDTMDF2_15   volatile.Register32 // 0x6E4
	CFDTMID3      volatile.Register32 // 0x6E8
	CFDTMPTR3     volatile.Register32 // 0x6EC
	CFDTMFDCTR3   volatile.Register32 // 0x6F0
	CFDTMDF3_0    volatile.Register32 // 0x6F4
	CFDTMDF3_1    volatile.Register32 // 0x6F8
	CFDTMDF3_2    volatile.Register32 // 0x6FC
	CFDTMDF3_3    volatile.Register32 // 0x700
	CFDTMDF3_4    volatile.Register32 // 0x704
	CFDTMDF3_5    volatile.Register32 // 0x708
	CFDTMDF3_6    volatile.Register32 // 0x70C
	CFDTMDF3_7    volatile.Register32 // 0x710
	CFDTMDF3_8    volatile.Register32 // 0x714
	CFDTMDF3_9    volatile.Register32 // 0x718
	CFDTMDF3_10   volatile.Register32 // 0x71C
	CFDTMDF3_11   volatile.Register32 // 0x720
	CFDTMDF3_12   volatile.Register32 // 0x724
	CFDTMDF3_13   volatile.Register32 // 0x728
	CFDTMDF3_14   volatile.Register32 // 0x72C
	CFDTMDF3_15   volatile.Register32 // 0x730
	_             [12]byte
	CFDTHLACC0    volatile.Register32 // 0x740
	CFDTHLACC1    volatile.Register32 // 0x744
	_             [472]byte
	CFDRMID0      volatile.Register32 // 0x920
	CFDRMPTR0     volatile.Register32 // 0x924
	CFDRMFDSTS0   volatile.Register32 // 0x928
	CFDRMDF0_0    volatile.Register32 // 0x92C
	CFDRMDF0_1    volatile.Register32 // 0x930
	CFDRMDF0_2    volatile.Register32 // 0x934
	CFDRMDF0_3    volatile.Register32 // 0x938
	CFDRMDF0_4    volatile.Register32 // 0x93C
	CFDRMDF0_5    volatile.Register32 // 0x940
	CFDRMDF0_6    volatile.Register32 // 0x944
	CFDRMDF0_7    volatile.Register32 // 0x948
	CFDRMDF0_8    volatile.Register32 // 0x94C
	CFDRMDF0_9    volatile.Register32 // 0x950
	CFDRMDF0_10   volatile.Register32 // 0x954
	CFDRMDF0_11   volatile.Register32 // 0x958
	CFDRMDF0_12   volatile.Register32 // 0x95C
	CFDRMDF0_13   volatile.Register32 // 0x960
	CFDRMDF0_14   volatile.Register32 // 0x964
	CFDRMDF0_15   volatile.Register32 // 0x968
	CFDRMID1      volatile.Register32 // 0x96C
	CFDRMPTR1     volatile.Register32 // 0x970
	CFDRMFDSTS1   volatile.Register32 // 0x974
	CFDRMDF1_0    volatile.Register32 // 0x978
	CFDRMDF1_1    volatile.Register32 // 0x97C
	CFDRMDF1_2    volatile.Register32 // 0x980
	CFDRMDF1_3    volatile.Register32 // 0x984
	CFDRMDF1_4    volatile.Register32 // 0x988
	CFDRMDF1_5    volatile.Register32 // 0x98C
	CFDRMDF1_6    volatile.Register32 // 0x990
	CFDRMDF1_7    volatile.Register32 // 0x994
	CFDRMDF1_8    volatile.Register32 // 0x998
	CFDRMDF1_9    volatile.Register32 // 0x99C
	CFDRMDF1_10   volatile.Register32 // 0x9A0
	CFDRMDF1_11   volatile.Register32 // 0x9A4
	CFDRMDF1_12   volatile.Register32 // 0x9A8
	CFDRMDF1_13   volatile.Register32 // 0x9AC
	CFDRMDF1_14   volatile.Register32 // 0x9B0
	CFDRMDF1_15   volatile.Register32 // 0x9B4
	CFDRMID2      volatile.Register32 // 0x9B8
	CFDRMPTR2     volatile.Register32 // 0x9BC
	CFDRMFDSTS2   volatile.Register32 // 0x9C0
	CFDRMDF2_0    volatile.Register32 // 0x9C4
	CFDRMDF2_1    volatile.Register32 // 0x9C8
	CFDRMDF2_2    volatile.Register32 // 0x9CC
	CFDRMDF2_3    volatile.Register32 // 0x9D0
	CFDRMDF2_4    volatile.Register32 // 0x9D4
	CFDRMDF2_5    volatile.Register32 // 0x9D8
	CFDRMDF2_6    volatile.Register32 // 0x9DC
	CFDRMDF2_7    volatile.Register32 // 0x9E0
	CFDRMDF2_8    volatile.Register32 // 0x9E4
	CFDRMDF2_9    volatile.Register32 // 0x9E8
	CFDRMDF2_10   volatile.Register32 // 0x9EC
	CFDRMDF2_11   volatile.Register32 // 0x9F0
	CFDRMDF2_12   volatile.Register32 // 0x9F4
	CFDRMDF2_13   volatile.Register32 // 0x9F8
	CFDRMDF2_14   volatile.Register32 // 0x9FC
	CFDRMDF2_15   volatile.Register32 // 0xA00
	CFDRMID3      volatile.Register32 // 0xA04
	CFDRMPTR3     volatile.Register32 // 0xA08
	CFDRMFDSTS3   volatile.Register32 // 0xA0C
	CFDRMDF3_0    volatile.Register32 // 0xA10
	CFDRMDF3_1    volatile.Register32 // 0xA14
	CFDRMDF3_2    volatile.Register32 // 0xA18
	CFDRMDF3_3    volatile.Register32 // 0xA1C
	CFDRMDF3_4    volatile.Register32 // 0xA20
	CFDRMDF3_5    volatile.Register32 // 0xA24
	CFDRMDF3_6    volatile.Register32 // 0xA28
	CFDRMDF3_7    volatile.Register32 // 0xA2C
	CFDRMDF3_8    volatile.Register32 // 0xA30
	CFDRMDF3_9    volatile.Register32 // 0xA34
	CFDRMDF3_10   volatile.Register32 // 0xA38
	CFDRMDF3_11   volatile.Register32 // 0xA3C
	CFDRMDF3_12   volatile.Register32 // 0xA40
	CFDRMDF3_13   volatile.Register32 // 0xA44
	CFDRMDF3_14   volatile.Register32 // 0xA48
	CFDRMDF3_15   volatile.Register32 // 0xA4C
	CFDRMID4      volatile.Register32 // 0xA50
	CFDRMPTR4     volatile.Register32 // 0xA54
	CFDRMFDSTS4   volatile.Register32 // 0xA58
	CFDRMDF4_0    volatile.Register32 // 0xA5C
	CFDRMDF4_1    volatile.Register32 // 0xA60
	CFDRMDF4_2    volatile.Register32 // 0xA64
	CFDRMDF4_3    volatile.Register32 // 0xA68
	CFDRMDF4_4    volatile.Register32 // 0xA6C
	CFDRMDF4_5    volatile.Register32 // 0xA70
	CFDRMDF4_6    volatile.Register32 // 0xA74
	CFDRMDF4_7    volatile.Register32 // 0xA78
	CFDRMDF4_8    volatile.Register32 // 0xA7C
	CFDRMDF4_9    volatile.Register32 // 0xA80
	CFDRMDF4_10   volatile.Register32 // 0xA84
	CFDRMDF4_11   volatile.Register32 // 0xA88
	CFDRMDF4_12   volatile.Register32 // 0xA8C
	CFDRMDF4_13   volatile.Register32 // 0xA90
	CFDRMDF4_14   volatile.Register32 // 0xA94
	CFDRMDF4_15   volatile.Register32 // 0xA98
	CFDRMID5      volatile.Register32 // 0xA9C
	CFDRMPTR5     volatile.Register32 // 0xAA0
	CFDRMFDSTS5   volatile.Register32 // 0xAA4
	CFDRMDF5_0    volatile.Register32 // 0xAA8
	CFDRMDF5_1    volatile.Register32 // 0xAAC
	CFDRMDF5_2    volatile.Register32 // 0xAB0
	CFDRMDF5_3    volatile.Register32 // 0xAB4
	CFDRMDF5_4    volatile.Register32 // 0xAB8
	CFDRMDF5_5    volatile.Register32 // 0xABC
	CFDRMDF5_6    volatile.Register32 // 0xAC0
	CFDRMDF5_7    volatile.Register32 // 0xAC4
	CFDRMDF5_8    volatile.Register32 // 0xAC8
	CFDRMDF5_9    volatile.Register32 // 0xACC
	CFDRMDF5_10   volatile.Register32 // 0xAD0
	CFDRMDF5_11   volatile.Register32 // 0xAD4
	CFDRMDF5_12   volatile.Register32 // 0xAD8
	CFDRMDF5_13   volatile.Register32 // 0xADC
	CFDRMDF5_14   volatile.Register32 // 0xAE0
	CFDRMDF5_15   volatile.Register32 // 0xAE4
	CFDRMID6      volatile.Register32 // 0xAE8
	CFDRMPTR6     volatile.Register32 // 0xAEC
	CFDRMFDSTS6   volatile.Register32 // 0xAF0
	CFDRMDF6_0    volatile.Register32 // 0xAF4
	CFDRMDF6_1    volatile.Register32 // 0xAF8
	CFDRMDF6_2    volatile.Register32 // 0xAFC
	CFDRMDF6_3    volatile.Register32 // 0xB00
	CFDRMDF6_4    volatile.Register32 // 0xB04
	CFDRMDF6_5    volatile.Register32 // 0xB08
	CFDRMDF6_6    volatile.Register32 // 0xB0C
	CFDRMDF6_7    volatile.Register32 // 0xB10
	CFDRMDF6_8    volatile.Register32 // 0xB14
	CFDRMDF6_9    volatile.Register32 // 0xB18
	CFDRMDF6_10   volatile.Register32 // 0xB1C
	CFDRMDF6_11   volatile.Register32 // 0xB20
	CFDRMDF6_12   volatile.Register32 // 0xB24
	CFDRMDF6_13   volatile.Register32 // 0xB28
	CFDRMDF6_14   volatile.Register32 // 0xB2C
	CFDRMDF6_15   volatile.Register32 // 0xB30
	CFDRMID7      volatile.Register32 // 0xB34
	CFDRMPTR7     volatile.Register32 // 0xB38
	CFDRMFDSTS7   volatile.Register32 // 0xB3C
	CFDRMDF7_0    volatile.Register32 // 0xB40
	CFDRMDF7_1    volatile.Register32 // 0xB44
	CFDRMDF7_2    volatile.Register32 // 0xB48
	CFDRMDF7_3    volatile.Register32 // 0xB4C
	CFDRMDF7_4    volatile.Register32 // 0xB50
	CFDRMDF7_5    volatile.Register32 // 0xB54
	CFDRMDF7_6    volatile.Register32 // 0xB58
	CFDRMDF7_7    volatile.Register32 // 0xB5C
	CFDRMDF7_8    volatile.Register32 // 0xB60
	CFDRMDF7_9    volatile.Register32 // 0xB64
	CFDRMDF7_10   volatile.Register32 // 0xB68
	CFDRMDF7_11   volatile.Register32 // 0xB6C
	CFDRMDF7_12   volatile.Register32 // 0xB70
	CFDRMDF7_13   volatile.Register32 // 0xB74
	CFDRMDF7_14   volatile.Register32 // 0xB78
	CFDRMDF7_15   volatile.Register32 // 0xB7C
	_             [416]byte
	CFDRMID8      volatile.Register32 // 0xD20
	CFDRMPTR8     volatile.Register32 // 0xD24
	CFDRMFDSTS8   volatile.Register32 // 0xD28
	CFDRMDF8_0    volatile.Register32 // 0xD2C
	CFDRMDF8_1    volatile.Register32 // 0xD30
	CFDRMDF8_2    volatile.Register32 // 0xD34
	CFDRMDF8_3    volatile.Register32 // 0xD38
	CFDRMDF8_4    volatile.Register32 // 0xD3C
	CFDRMDF8_5    volatile.Register32 // 0xD40
	CFDRMDF8_6    volatile.Register32 // 0xD44
	CFDRMDF8_7    volatile.Register32 // 0xD48
	CFDRMDF8_8    volatile.Register32 // 0xD4C
	CFDRMDF8_9    volatile.Register32 // 0xD50
	CFDRMDF8_10   volatile.Register32 // 0xD54
	CFDRMDF8_11   volatile.Register32 // 0xD58
	CFDRMDF8_12   volatile.Register32 // 0xD5C
	CFDRMDF8_13   volatile.Register32 // 0xD60
	CFDRMDF8_14   volatile.Register32 // 0xD64
	CFDRMDF8_15   volatile.Register32 // 0xD68
	CFDRMID9      volatile.Register32 // 0xD6C
	CFDRMPTR9     volatile.Register32 // 0xD70
	CFDRMFDSTS9   volatile.Register32 // 0xD74
	CFDRMDF9_0    volatile.Register32 // 0xD78
	CFDRMDF9_1    volatile.Register32 // 0xD7C
	CFDRMDF9_2    volatile.Register32 // 0xD80
	CFDRMDF9_3    volatile.Register32 // 0xD84
	CFDRMDF9_4    volatile.Register32 // 0xD88
	CFDRMDF9_5    volatile.Register32 // 0xD8C
	CFDRMDF9_6    volatile.Register32 // 0xD90
	CFDRMDF9_7    volatile.Register32 // 0xD94
	CFDRMDF9_8    volatile.Register32 // 0xD98
	CFDRMDF9_9    volatile.Register32 // 0xD9C
	CFDRMDF9_10   volatile.Register32 // 0xDA0
	CFDRMDF9_11   volatile.Register32 // 0xDA4
	CFDRMDF9_12   volatile.Register32 // 0xDA8
	CFDRMDF9_13   volatile.Register32 // 0xDAC
	CFDRMDF9_14   volatile.Register32 // 0xDB0
	CFDRMDF9_15   volatile.Register32 // 0xDB4
	CFDRMID10     volatile.Register32 // 0xDB8
	CFDRMPTR10    volatile.Register32 // 0xDBC
	CFDRMFDSTS10  volatile.Register32 // 0xDC0
	CFDRMDF10_0   volatile.Register32 // 0xDC4
	CFDRMDF10_1   volatile.Register32 // 0xDC8
	CFDRMDF10_2   volatile.Register32 // 0xDCC
	CFDRMDF10_3   volatile.Register32 // 0xDD0
	CFDRMDF10_4   volatile.Register32 // 0xDD4
	CFDRMDF10_5   volatile.Register32 // 0xDD8
	CFDRMDF10_6   volatile.Register32 // 0xDDC
	CFDRMDF10_7   volatile.Register32 // 0xDE0
	CFDRMDF10_8   volatile.Register32 // 0xDE4
	CFDRMDF10_9   volatile.Register32 // 0xDE8
	CFDRMDF10_10  volatile.Register32 // 0xDEC
	CFDRMDF10_11  volatile.Register32 // 0xDF0
	CFDRMDF10_12  volatile.Register32 // 0xDF4
	CFDRMDF10_13  volatile.Register32 // 0xDF8
	CFDRMDF10_14  volatile.Register32 // 0xDFC
	CFDRMDF10_15  volatile.Register32 // 0xE00
	CFDRMID11     volatile.Register32 // 0xE04
	CFDRMPTR11    volatile.Register32 // 0xE08
	CFDRMFDSTS11  volatile.Register32 // 0xE0C
	CFDRMDF11_0   volatile.Register32 // 0xE10
	CFDRMDF11_1   volatile.Register32 // 0xE14
	CFDRMDF11_2   volatile.Register32 // 0xE18
	CFDRMDF11_3   volatile.Register32 // 0xE1C
	CFDRMDF11_4   volatile.Register32 // 0xE20
	CFDRMDF11_5   volatile.Register32 // 0xE24
	CFDRMDF11_6   volatile.Register32 // 0xE28
	CFDRMDF11_7   volatile.Register32 // 0xE2C
	CFDRMDF11_8   volatile.Register32 // 0xE30
	CFDRMDF11_9   volatile.Register32 // 0xE34
	CFDRMDF11_10  volatile.Register32 // 0xE38
	CFDRMDF11_11  volatile.Register32 // 0xE3C
	CFDRMDF11_12  volatile.Register32 // 0xE40
	CFDRMDF11_13  volatile.Register32 // 0xE44
	CFDRMDF11_14  volatile.Register32 // 0xE48
	CFDRMDF11_15  volatile.Register32 // 0xE4C
	CFDRMID12     volatile.Register32 // 0xE50
	CFDRMPTR12    volatile.Register32 // 0xE54
	CFDRMFDSTS12  volatile.Register32 // 0xE58
	CFDRMDF12_0   volatile.Register32 // 0xE5C
	CFDRMDF12_1   volatile.Register32 // 0xE60
	CFDRMDF12_2   volatile.Register32 // 0xE64
	CFDRMDF12_3   volatile.Register32 // 0xE68
	CFDRMDF12_4   volatile.Register32 // 0xE6C
	CFDRMDF12_5   volatile.Register32 // 0xE70
	CFDRMDF12_6   volatile.Register32 // 0xE74
	CFDRMDF12_7   volatile.Register32 // 0xE78
	CFDRMDF12_8   volatile.Register32 // 0xE7C
	CFDRMDF12_9   volatile.Register32 // 0xE80
	CFDRMDF12_10  volatile.Register32 // 0xE84
	CFDRMDF12_11  volatile.Register32 // 0xE88
	CFDRMDF12_12  volatile.Register32 // 0xE8C
	CFDRMDF12_13  volatile.Register32 // 0xE90
	CFDRMDF12_14  volatile.Register32 // 0xE94
	CFDRMDF12_15  volatile.Register32 // 0xE98
	CFDRMID13     volatile.Register32 // 0xE9C
	CFDRMPTR13    volatile.Register32 // 0xEA0
	CFDRMFDSTS13  volatile.Register32 // 0xEA4
	CFDRMDF13_0   volatile.Register32 // 0xEA8
	CFDRMDF13_1   volatile.Register32 // 0xEAC
	CFDRMDF13_2   volatile.Register32 // 0xEB0
	CFDRMDF13_3   volatile.Register32 // 0xEB4
	CFDRMDF13_4   volatile.Register32 // 0xEB8
	CFDRMDF13_5   volatile.Register32 // 0xEBC
	CFDRMDF13_6   volatile.Register32 // 0xEC0
	CFDRMDF13_7   volatile.Register32 // 0xEC4
	CFDRMDF13_8   volatile.Register32 // 0xEC8
	CFDRMDF13_9   volatile.Register32 // 0xECC
	CFDRMDF13_10  volatile.Register32 // 0xED0
	CFDRMDF13_11  volatile.Register32 // 0xED4
	CFDRMDF13_12  volatile.Register32 // 0xED8
	CFDRMDF13_13  volatile.Register32 // 0xEDC
	CFDRMDF13_14  volatile.Register32 // 0xEE0
	CFDRMDF13_15  volatile.Register32 // 0xEE4
	CFDRMID14     volatile.Register32 // 0xEE8
	CFDRMPTR14    volatile.Register32 // 0xEEC
	CFDRMFDSTS14  volatile.Register32 // 0xEF0
	CFDRMDF14_0   volatile.Register32 // 0xEF4
	CFDRMDF14_1   volatile.Register32 // 0xEF8
	CFDRMDF14_2   volatile.Register32 // 0xEFC
	CFDRMDF14_3   volatile.Register32 // 0xF00
	CFDRMDF14_4   volatile.Register32 // 0xF04
	CFDRMDF14_5   volatile.Register32 // 0xF08
	CFDRMDF14_6   volatile.Register32 // 0xF0C
	CFDRMDF14_7   volatile.Register32 // 0xF10
	CFDRMDF14_8   volatile.Register32 // 0xF14
	CFDRMDF14_9   volatile.Register32 // 0xF18
	CFDRMDF14_10  volatile.Register32 // 0xF1C
	CFDRMDF14_11  volatile.Register32 // 0xF20
	CFDRMDF14_12  volatile.Register32 // 0xF24
	CFDRMDF14_13  volatile.Register32 // 0xF28
	CFDRMDF14_14  volatile.Register32 // 0xF2C
	CFDRMDF14_15  volatile.Register32 // 0xF30
	CFDRMID15     volatile.Register32 // 0xF34
	CFDRMPTR15    volatile.Register32 // 0xF38
	CFDRMFDSTS15  volatile.Register32 // 0xF3C
	CFDRMDF15_0   volatile.Register32 // 0xF40
	CFDRMDF15_1   volatile.Register32 // 0xF44
	CFDRMDF15_2   volatile.Register32 // 0xF48
	CFDRMDF15_3   volatile.Register32 // 0xF4C
	CFDRMDF15_4   volatile.Register32 // 0xF50
	CFDRMDF15_5   volatile.Register32 // 0xF54
	CFDRMDF15_6   volatile.Register32 // 0xF58
	CFDRMDF15_7   volatile.Register32 // 0xF5C
	CFDRMDF15_8   volatile.Register32 // 0xF60
	CFDRMDF15_9   volatile.Register32 // 0xF64
	CFDRMDF15_10  volatile.Register32 // 0xF68
	CFDRMDF15_11  volatile.Register32 // 0xF6C
	CFDRMDF15_12  volatile.Register32 // 0xF70
	CFDRMDF15_13  volatile.Register32 // 0xF74
	CFDRMDF15_14  volatile.Register32 // 0xF78
	CFDRMDF15_15  volatile.Register32 // 0xF7C
	_             [416]byte
	CFDRMID16     volatile.Register32 // 0x1120
	CFDRMPTR16    volatile.Register32 // 0x1124
	CFDRMFDSTS16  volatile.Register32 // 0x1128
	CFDRMDF16_0   volatile.Register32 // 0x112C
	CFDRMDF16_1   volatile.Register32 // 0x1130
	CFDRMDF16_2   volatile.Register32 // 0x1134
	CFDRMDF16_3   volatile.Register32 // 0x1138
	CFDRMDF16_4   volatile.Register32 // 0x113C
	CFDRMDF16_5   volatile.Register32 // 0x1140
	CFDRMDF16_6   volatile.Register32 // 0x1144
	CFDRMDF16_7   volatile.Register32 // 0x1148
	CFDRMDF16_8   volatile.Register32 // 0x114C
	CFDRMDF16_9   volatile.Register32 // 0x1150
	CFDRMDF16_10  volatile.Register32 // 0x1154
	CFDRMDF16_11  volatile.Register32 // 0x1158
	CFDRMDF16_12  volatile.Register32 // 0x115C
	CFDRMDF16_13  volatile.Register32 // 0x1160
	CFDRMDF16_14  volatile.Register32 // 0x1164
	CFDRMDF16_15  volatile.Register32 // 0x1168
	CFDRMID17     volatile.Register32 // 0x116C
	CFDRMPTR17    volatile.Register32 // 0x1170
	CFDRMFDSTS17  volatile.Register32 // 0x1174
	CFDRMDF17_0   volatile.Register32 // 0x1178
	CFDRMDF17_1   volatile.Register32 // 0x117C
	CFDRMDF17_2   volatile.Register32 // 0x1180
	CFDRMDF17_3   volatile.Register32 // 0x1184
	CFDRMDF17_4   volatile.Register32 // 0x1188
	CFDRMDF17_5   volatile.Register32 // 0x118C
	CFDRMDF17_6   volatile.Register32 // 0x1190
	CFDRMDF17_7   volatile.Register32 // 0x1194
	CFDRMDF17_8   volatile.Register32 // 0x1198
	CFDRMDF17_9   volatile.Register32 // 0x119C
	CFDRMDF17_10  volatile.Register32 // 0x11A0
	CFDRMDF17_11  volatile.Register32 // 0x11A4
	CFDRMDF17_12  volatile.Register32 // 0x11A8
	CFDRMDF17_13  volatile.Register32 // 0x11AC
	CFDRMDF17_14  volatile.Register32 // 0x11B0
	CFDRMDF17_15  volatile.Register32 // 0x11B4
	CFDRMID18     volatile.Register32 // 0x11B8
	CFDRMPTR18    volatile.Register32 // 0x11BC
	CFDRMFDSTS18  volatile.Register32 // 0x11C0
	CFDRMDF18_0   volatile.Register32 // 0x11C4
	CFDRMDF18_1   volatile.Register32 // 0x11C8
	CFDRMDF18_2   volatile.Register32 // 0x11CC
	CFDRMDF18_3   volatile.Register32 // 0x11D0
	CFDRMDF18_4   volatile.Register32 // 0x11D4
	CFDRMDF18_5   volatile.Register32 // 0x11D8
	CFDRMDF18_6   volatile.Register32 // 0x11DC
	CFDRMDF18_7   volatile.Register32 // 0x11E0
	CFDRMDF18_8   volatile.Register32 // 0x11E4
	CFDRMDF18_9   volatile.Register32 // 0x11E8
	CFDRMDF18_10  volatile.Register32 // 0x11EC
	CFDRMDF18_11  volatile.Register32 // 0x11F0
	CFDRMDF18_12  volatile.Register32 // 0x11F4
	CFDRMDF18_13  volatile.Register32 // 0x11F8
	CFDRMDF18_14  volatile.Register32 // 0x11FC
	CFDRMDF18_15  volatile.Register32 // 0x1200
	CFDRMID19     volatile.Register32 // 0x1204
	CFDRMPTR19    volatile.Register32 // 0x1208
	CFDRMFDSTS19  volatile.Register32 // 0x120C
	CFDRMDF19_0   volatile.Register32 // 0x1210
	CFDRMDF19_1   volatile.Register32 // 0x1214
	CFDRMDF19_2   volatile.Register32 // 0x1218
	CFDRMDF19_3   volatile.Register32 // 0x121C
	CFDRMDF19_4   volatile.Register32 // 0x1220
	CFDRMDF19_5   volatile.Register32 // 0x1224
	CFDRMDF19_6   volatile.Register32 // 0x1228
	CFDRMDF19_7   volatile.Register32 // 0x122C
	CFDRMDF19_8   volatile.Register32 // 0x1230
	CFDRMDF19_9   volatile.Register32 // 0x1234
	CFDRMDF19_10  volatile.Register32 // 0x1238
	CFDRMDF19_11  volatile.Register32 // 0x123C
	CFDRMDF19_12  volatile.Register32 // 0x1240
	CFDRMDF19_13  volatile.Register32 // 0x1244
	CFDRMDF19_14  volatile.Register32 // 0x1248
	CFDRMDF19_15  volatile.Register32 // 0x124C
	CFDRMID20     volatile.Register32 // 0x1250
	CFDRMPTR20    volatile.Register32 // 0x1254
	CFDRMFDSTS20  volatile.Register32 // 0x1258
	CFDRMDF20_0   volatile.Register32 // 0x125C
	CFDRMDF20_1   volatile.Register32 // 0x1260
	CFDRMDF20_2   volatile.Register32 // 0x1264
	CFDRMDF20_3   volatile.Register32 // 0x1268
	CFDRMDF20_4   volatile.Register32 // 0x126C
	CFDRMDF20_5   volatile.Register32 // 0x1270
	CFDRMDF20_6   volatile.Register32 // 0x1274
	CFDRMDF20_7   volatile.Register32 // 0x1278
	CFDRMDF20_8   volatile.Register32 // 0x127C
	CFDRMDF20_9   volatile.Register32 // 0x1280
	CFDRMDF20_10  volatile.Register32 // 0x1284
	CFDRMDF20_11  volatile.Register32 // 0x1288
	CFDRMDF20_12  volatile.Register32 // 0x128C
	CFDRMDF20_13  volatile.Register32 // 0x1290
	CFDRMDF20_14  volatile.Register32 // 0x1294
	CFDRMDF20_15  volatile.Register32 // 0x1298
	CFDRMID21     volatile.Register32 // 0x129C
	CFDRMPTR21    volatile.Register32 // 0x12A0
	CFDRMFDSTS21  volatile.Register32 // 0x12A4
	CFDRMDF21_0   volatile.Register32 // 0x12A8
	CFDRMDF21_1   volatile.Register32 // 0x12AC
	CFDRMDF21_2   volatile.Register32 // 0x12B0
	CFDRMDF21_3   volatile.Register32 // 0x12B4
	CFDRMDF21_4   volatile.Register32 // 0x12B8
	CFDRMDF21_5   volatile.Register32 // 0x12BC
	CFDRMDF21_6   volatile.Register32 // 0x12C0
	CFDRMDF21_7   volatile.Register32 // 0x12C4
	CFDRMDF21_8   volatile.Register32 // 0x12C8
	CFDRMDF21_9   volatile.Register32 // 0x12CC
	CFDRMDF21_10  volatile.Register32 // 0x12D0
	CFDRMDF21_11  volatile.Register32 // 0x12D4
	CFDRMDF21_12  volatile.Register32 // 0x12D8
	CFDRMDF21_13  volatile.Register32 // 0x12DC
	CFDRMDF21_14  volatile.Register32 // 0x12E0
	CFDRMDF21_15  volatile.Register32 // 0x12E4
	CFDRMID22     volatile.Register32 // 0x12E8
	CFDRMPTR22    volatile.Register32 // 0x12EC
	CFDRMFDSTS22  volatile.Register32 // 0x12F0
	CFDRMDF22_0   volatile.Register32 // 0x12F4
	CFDRMDF22_1   volatile.Register32 // 0x12F8
	CFDRMDF22_2   volatile.Register32 // 0x12FC
	CFDRMDF22_3   volatile.Register32 // 0x1300
	CFDRMDF22_4   volatile.Register32 // 0x1304
	CFDRMDF22_5   volatile.Register32 // 0x1308
	CFDRMDF22_6   volatile.Register32 // 0x130C
	CFDRMDF22_7   volatile.Register32 // 0x1310
	CFDRMDF22_8   volatile.Register32 // 0x1314
	CFDRMDF22_9   volatile.Register32 // 0x1318
	CFDRMDF22_10  volatile.Register32 // 0x131C
	CFDRMDF22_11  volatile.Register32 // 0x1320
	CFDRMDF22_12  volatile.Register32 // 0x1324
	CFDRMDF22_13  volatile.Register32 // 0x1328
	CFDRMDF22_14  volatile.Register32 // 0x132C
	CFDRMDF22_15  volatile.Register32 // 0x1330
	CFDRMID23     volatile.Register32 // 0x1334
	CFDRMPTR23    volatile.Register32 // 0x1338
	CFDRMFDSTS23  volatile.Register32 // 0x133C
	CFDRMDF23_0   volatile.Register32 // 0x1340
	CFDRMDF23_1   volatile.Register32 // 0x1344
	CFDRMDF23_2   volatile.Register32 // 0x1348
	CFDRMDF23_3   volatile.Register32 // 0x134C
	CFDRMDF23_4   volatile.Register32 // 0x1350
	CFDRMDF23_5   volatile.Register32 // 0x1354
	CFDRMDF23_6   volatile.Register32 // 0x1358
	CFDRMDF23_7   volatile.Register32 // 0x135C
	CFDRMDF23_8   volatile.Register32 // 0x1360
	CFDRMDF23_9   volatile.Register32 // 0x1364
	CFDRMDF23_10  volatile.Register32 // 0x1368
	CFDRMDF23_11  volatile.Register32 // 0x136C
	CFDRMDF23_12  volatile.Register32 // 0x1370
	CFDRMDF23_13  volatile.Register32 // 0x1374
	CFDRMDF23_14  volatile.Register32 // 0x1378
	CFDRMDF23_15  volatile.Register32 // 0x137C
	_             [416]byte
	CFDRMID24     volatile.Register32 // 0x1520
	CFDRMPTR24    volatile.Register32 // 0x1524
	CFDRMFDSTS24  volatile.Register32 // 0x1528
	CFDRMDF24_0   volatile.Register32 // 0x152C
	CFDRMDF24_1   volatile.Register32 // 0x1530
	CFDRMDF24_2   volatile.Register32 // 0x1534
	CFDRMDF24_3   volatile.Register32 // 0x1538
	CFDRMDF24_4   volatile.Register32 // 0x153C
	CFDRMDF24_5   volatile.Register32 // 0x1540
	CFDRMDF24_6   volatile.Register32 // 0x1544
	CFDRMDF24_7   volatile.Register32 // 0x1548
	CFDRMDF24_8   volatile.Register32 // 0x154C
	CFDRMDF24_9   volatile.Register32 // 0x1550
	CFDRMDF24_10  volatile.Register32 // 0x1554
	CFDRMDF24_11  volatile.Register32 // 0x1558
	CFDRMDF24_12  volatile.Register32 // 0x155C
	CFDRMDF24_13  volatile.Register32 // 0x1560
	CFDRMDF24_14  volatile.Register32 // 0x1564
	CFDRMDF24_15  volatile.Register32 // 0x1568
	CFDRMID25     volatile.Register32 // 0x156C
	CFDRMPTR25    volatile.Register32 // 0x1570
	CFDRMFDSTS25  volatile.Register32 // 0x1574
	CFDRMDF25_0   volatile.Register32 // 0x1578
	CFDRMDF25_1   volatile.Register32 // 0x157C
	CFDRMDF25_2   volatile.Register32 // 0x1580
	CFDRMDF25_3   volatile.Register32 // 0x1584
	CFDRMDF25_4   volatile.Register32 // 0x1588
	CFDRMDF25_5   volatile.Register32 // 0x158C
	CFDRMDF25_6   volatile.Register32 // 0x1590
	CFDRMDF25_7   volatile.Register32 // 0x1594
	CFDRMDF25_8   volatile.Register32 // 0x1598
	CFDRMDF25_9   volatile.Register32 // 0x159C
	CFDRMDF25_10  volatile.Register32 // 0x15A0
	CFDRMDF25_11  volatile.Register32 // 0x15A4
	CFDRMDF25_12  volatile.Register32 // 0x15A8
	CFDRMDF25_13  volatile.Register32 // 0x15AC
	CFDRMDF25_14  volatile.Register32 // 0x15B0
	CFDRMDF25_15  volatile.Register32 // 0x15B4
	CFDRMID26     volatile.Register32 // 0x15B8
	CFDRMPTR26    volatile.Register32 // 0x15BC
	CFDRMFDSTS26  volatile.Register32 // 0x15C0
	CFDRMDF26_0   volatile.Register32 // 0x15C4
	CFDRMDF26_1   volatile.Register32 // 0x15C8
	CFDRMDF26_2   volatile.Register32 // 0x15CC
	CFDRMDF26_3   volatile.Register32 // 0x15D0
	CFDRMDF26_4   volatile.Register32 // 0x15D4
	CFDRMDF26_5   volatile.Register32 // 0x15D8
	CFDRMDF26_6   volatile.Register32 // 0x15DC
	CFDRMDF26_7   volatile.Register32 // 0x15E0
	CFDRMDF26_8   volatile.Register32 // 0x15E4
	CFDRMDF26_9   volatile.Register32 // 0x15E8
	CFDRMDF26_10  volatile.Register32 // 0x15EC
	CFDRMDF26_11  volatile.Register32 // 0x15F0
	CFDRMDF26_12  volatile.Register32 // 0x15F4
	CFDRMDF26_13  volatile.Register32 // 0x15F8
	CFDRMDF26_14  volatile.Register32 // 0x15FC
	CFDRMDF26_15  volatile.Register32 // 0x1600
	CFDRMID27     volatile.Register32 // 0x1604
	CFDRMPTR27    volatile.Register32 // 0x1608
	CFDRMFDSTS27  volatile.Register32 // 0x160C
	CFDRMDF27_0   volatile.Register32 // 0x1610
	CFDRMDF27_1   volatile.Register32 // 0x1614
	CFDRMDF27_2   volatile.Register32 // 0x1618
	CFDRMDF27_3   volatile.Register32 // 0x161C
	CFDRMDF27_4   volatile.Register32 // 0x1620
	CFDRMDF27_5   volatile.Register32 // 0x1624
	CFDRMDF27_6   volatile.Register32 // 0x1628
	CFDRMDF27_7   volatile.Register32 // 0x162C
	CFDRMDF27_8   volatile.Register32 // 0x1630
	CFDRMDF27_9   volatile.Register32 // 0x1634
	CFDRMDF27_10  volatile.Register32 // 0x1638
	CFDRMDF27_11  volatile.Register32 // 0x163C
	CFDRMDF27_12  volatile.Register32 // 0x1640
	CFDRMDF27_13  volatile.Register32 // 0x1644
	CFDRMDF27_14  volatile.Register32 // 0x1648
	CFDRMDF27_15  volatile.Register32 // 0x164C
	CFDRMID28     volatile.Register32 // 0x1650
	CFDRMPTR28    volatile.Register32 // 0x1654
	CFDRMFDSTS28  volatile.Register32 // 0x1658
	CFDRMDF28_0   volatile.Register32 // 0x165C
	CFDRMDF28_1   volatile.Register32 // 0x1660
	CFDRMDF28_2   volatile.Register32 // 0x1664
	CFDRMDF28_3   volatile.Register32 // 0x1668
	CFDRMDF28_4   volatile.Register32 // 0x166C
	CFDRMDF28_5   volatile.Register32 // 0x1670
	CFDRMDF28_6   volatile.Register32 // 0x1674
	CFDRMDF28_7   volatile.Register32 // 0x1678
	CFDRMDF28_8   volatile.Register32 // 0x167C
	CFDRMDF28_9   volatile.Register32 // 0x1680
	CFDRMDF28_10  volatile.Register32 // 0x1684
	CFDRMDF28_11  volatile.Register32 // 0x1688
	CFDRMDF28_12  volatile.Register32 // 0x168C
	CFDRMDF28_13  volatile.Register32 // 0x1690
	CFDRMDF28_14  volatile.Register32 // 0x1694
	CFDRMDF28_15  volatile.Register32 // 0x1698
	CFDRMID29     volatile.Register32 // 0x169C
	CFDRMPTR29    volatile.Register32 // 0x16A0
	CFDRMFDSTS29  volatile.Register32 // 0x16A4
	CFDRMDF29_0   volatile.Register32 // 0x16A8
	CFDRMDF29_1   volatile.Register32 // 0x16AC
	CFDRMDF29_2   volatile.Register32 // 0x16B0
	CFDRMDF29_3   volatile.Register32 // 0x16B4
	CFDRMDF29_4   volatile.Register32 // 0x16B8
	CFDRMDF29_5   volatile.Register32 // 0x16BC
	CFDRMDF29_6   volatile.Register32 // 0x16C0
	CFDRMDF29_7   volatile.Register32 // 0x16C4
	CFDRMDF29_8   volatile.Register32 // 0x16C8
	CFDRMDF29_9   volatile.Register32 // 0x16CC
	CFDRMDF29_10  volatile.Register32 // 0x16D0
	CFDRMDF29_11  volatile.Register32 // 0x16D4
	CFDRMDF29_12  volatile.Register32 // 0x16D8
	CFDRMDF29_13  volatile.Register32 // 0x16DC
	CFDRMDF29_14  volatile.Register32 // 0x16E0
	CFDRMDF29_15  volatile.Register32 // 0x16E4
	CFDRMID30     volatile.Register32 // 0x16E8
	CFDRMPTR30    volatile.Register32 // 0x16EC
	CFDRMFDSTS30  volatile.Register32 // 0x16F0
	CFDRMDF30_0   volatile.Register32 // 0x16F4
	CFDRMDF30_1   volatile.Register32 // 0x16F8
	CFDRMDF30_2   volatile.Register32 // 0x16FC
	CFDRMDF30_3   volatile.Register32 // 0x1700
	CFDRMDF30_4   volatile.Register32 // 0x1704
	CFDRMDF30_5   volatile.Register32 // 0x1708
	CFDRMDF30_6   volatile.Register32 // 0x170C
	CFDRMDF30_7   volatile.Register32 // 0x1710
	CFDRMDF30_8   volatile.Register32 // 0x1714
	CFDRMDF30_9   volatile.Register32 // 0x1718
	CFDRMDF30_10  volatile.Register32 // 0x171C
	CFDRMDF30_11  volatile.Register32 // 0x1720
	CFDRMDF30_12  volatile.Register32 // 0x1724
	CFDRMDF30_13  volatile.Register32 // 0x1728
	CFDRMDF30_14  volatile.Register32 // 0x172C
	CFDRMDF30_15  volatile.Register32 // 0x1730
	CFDRMID31     volatile.Register32 // 0x1734
	CFDRMPTR31    volatile.Register32 // 0x1738
	CFDRMFDSTS31  volatile.Register32 // 0x173C
	CFDRMDF31_0   volatile.Register32 // 0x1740
	CFDRMDF31_1   volatile.Register32 // 0x1744
	CFDRMDF31_2   volatile.Register32 // 0x1748
	CFDRMDF31_3   volatile.Register32 // 0x174C
	CFDRMDF31_4   volatile.Register32 // 0x1750
	CFDRMDF31_5   volatile.Register32 // 0x1754
	CFDRMDF31_6   volatile.Register32 // 0x1758
	CFDRMDF31_7   volatile.Register32 // 0x175C
	CFDRMDF31_8   volatile.Register32 // 0x1760
	CFDRMDF31_9   volatile.Register32 // 0x1764
	CFDRMDF31_10  volatile.Register32 // 0x1768
	CFDRMDF31_11  volatile.Register32 // 0x176C
	CFDRMDF31_12  volatile.Register32 // 0x1770
	CFDRMDF31_13  volatile.Register32 // 0x1774
	CFDRMDF31_14  volatile.Register32 // 0x1778
	CFDRMDF31_15  volatile.Register32 // 0x177C
}

// CANFD_B.CFDC0NCFG: Channel 0 Nominal Bitrate Configuration Register
func (o *CANFD_B_Type) SetCFDC0NCFG_NBRP(value uint32) {
	volatile.StoreUint32(&o.CFDC0NCFG.Reg, volatile.LoadUint32(&o.CFDC0NCFG.Reg)&^(0x3ff)|value)
}
func (o *CANFD_B_Type) GetCFDC0NCFG_NBRP() uint32 {
	return volatile.LoadUint32(&o.CFDC0NCFG.Reg) & 0x3ff
}
func (o *CANFD_B_Type) SetCFDC0NCFG_NSJW(value uint32) {
	volatile.StoreUint32(&o.CFDC0NCFG.Reg, volatile.LoadUint32(&o.CFDC0NCFG.Reg)&^(0x1fc00)|value<<10)
}
func (o *CANFD_B_Type) GetCFDC0NCFG_NSJW() uint32 {
	return (volatile.LoadUint32(&o.CFDC0NCFG.Reg) & 0x1fc00) >> 10
}
func (o *CANFD_B_Type) SetCFDC0NCFG_NTSEG1(value uint32) {
	volatile.StoreUint32(&o.CFDC0NCFG.Reg, volatile.LoadUint32(&o.CFDC0NCFG.Reg)&^(0x1fe0000)|value<<17)
}
func (o *CANFD_B_Type) GetCFDC0NCFG_NTSEG1() uint32 {
	return (volatile.LoadUint32(&o.CFDC0NCFG.Reg) & 0x1fe0000) >> 17
}
func (o *CANFD_B_Type) SetCFDC0NCFG_NTSEG2(value uint32) {
	volatile.StoreUint32(&o.CFDC0NCFG.Reg, volatile.LoadUint32(&o.CFDC0NCFG.Reg)&^(0xfe000000)|value<<25)
}
func (o *CANFD_B_Type) GetCFDC0NCFG_NTSEG2() uint32 {
	return (volatile.LoadUint32(&o.CFDC0NCFG.Reg) & 0xfe000000) >> 25
}

// CANFD_B.CFDC0CTR: Channel 0 Control Register
func (o *CANFD_B_Type) SetCFDC0CTR_CHMDC(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x3)|value)
}
func (o *CANFD_B_Type) GetCFDC0CTR_CHMDC() uint32 {
	return volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x3
}
func (o *CANFD_B_Type) SetCFDC0CTR_CSLPR(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDC0CTR_CSLPR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDC0CTR_RTBO(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDC0CTR_RTBO() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDC0CTR_BEIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDC0CTR_BEIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDC0CTR_EWIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x200)|value<<9)
}
func (o *CANFD_B_Type) GetCFDC0CTR_EWIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x200) >> 9
}
func (o *CANFD_B_Type) SetCFDC0CTR_EPIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x400)|value<<10)
}
func (o *CANFD_B_Type) GetCFDC0CTR_EPIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x400) >> 10
}
func (o *CANFD_B_Type) SetCFDC0CTR_BOEIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x800)|value<<11)
}
func (o *CANFD_B_Type) GetCFDC0CTR_BOEIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x800) >> 11
}
func (o *CANFD_B_Type) SetCFDC0CTR_BORIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x1000)|value<<12)
}
func (o *CANFD_B_Type) GetCFDC0CTR_BORIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x1000) >> 12
}
func (o *CANFD_B_Type) SetCFDC0CTR_OLIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x2000)|value<<13)
}
func (o *CANFD_B_Type) GetCFDC0CTR_OLIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x2000) >> 13
}
func (o *CANFD_B_Type) SetCFDC0CTR_BLIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x4000)|value<<14)
}
func (o *CANFD_B_Type) GetCFDC0CTR_BLIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x4000) >> 14
}
func (o *CANFD_B_Type) SetCFDC0CTR_ALIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDC0CTR_ALIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDC0CTR_TAIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x10000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDC0CTR_TAIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x10000) >> 16
}
func (o *CANFD_B_Type) SetCFDC0CTR_EOCOIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x20000)|value<<17)
}
func (o *CANFD_B_Type) GetCFDC0CTR_EOCOIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x20000) >> 17
}
func (o *CANFD_B_Type) SetCFDC0CTR_SOCOIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x40000)|value<<18)
}
func (o *CANFD_B_Type) GetCFDC0CTR_SOCOIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x40000) >> 18
}
func (o *CANFD_B_Type) SetCFDC0CTR_TDCVFIE(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x80000)|value<<19)
}
func (o *CANFD_B_Type) GetCFDC0CTR_TDCVFIE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x80000) >> 19
}
func (o *CANFD_B_Type) SetCFDC0CTR_BOM(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x600000)|value<<21)
}
func (o *CANFD_B_Type) GetCFDC0CTR_BOM() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x600000) >> 21
}
func (o *CANFD_B_Type) SetCFDC0CTR_ERRD(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x800000)|value<<23)
}
func (o *CANFD_B_Type) GetCFDC0CTR_ERRD() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x800000) >> 23
}
func (o *CANFD_B_Type) SetCFDC0CTR_CTME(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x1000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDC0CTR_CTME() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x1000000) >> 24
}
func (o *CANFD_B_Type) SetCFDC0CTR_CTMS(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x6000000)|value<<25)
}
func (o *CANFD_B_Type) GetCFDC0CTR_CTMS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x6000000) >> 25
}
func (o *CANFD_B_Type) SetCFDC0CTR_BFT(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDC0CTR_BFT() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDC0CTR_ROM(value uint32) {
	volatile.StoreUint32(&o.CFDC0CTR.Reg, volatile.LoadUint32(&o.CFDC0CTR.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDC0CTR_ROM() uint32 {
	return (volatile.LoadUint32(&o.CFDC0CTR.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDC0STS: Channel 0 Status Register
func (o *CANFD_B_Type) SetCFDC0STS_CRSTSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDC0STS_CRSTSTS() uint32 {
	return volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDC0STS_CHLTSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDC0STS_CHLTSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDC0STS_CSLPSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDC0STS_CSLPSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDC0STS_EPSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDC0STS_EPSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDC0STS_BOSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDC0STS_BOSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x10) >> 4
}
func (o *CANFD_B_Type) SetCFDC0STS_TRMSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x20)|value<<5)
}
func (o *CANFD_B_Type) GetCFDC0STS_TRMSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x20) >> 5
}
func (o *CANFD_B_Type) SetCFDC0STS_RECSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x40)|value<<6)
}
func (o *CANFD_B_Type) GetCFDC0STS_RECSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x40) >> 6
}
func (o *CANFD_B_Type) SetCFDC0STS_COMSTS(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDC0STS_COMSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDC0STS_ESIF(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDC0STS_ESIF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDC0STS_REC(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDC0STS_REC() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDC0STS_TEC(value uint32) {
	volatile.StoreUint32(&o.CFDC0STS.Reg, volatile.LoadUint32(&o.CFDC0STS.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDC0STS_TEC() uint32 {
	return (volatile.LoadUint32(&o.CFDC0STS.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDC0ERFL: Channel 0 Error Flag Register
func (o *CANFD_B_Type) SetCFDC0ERFL_BEF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_BEF() uint32 {
	return volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDC0ERFL_EWF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_EWF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDC0ERFL_EPF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_EPF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDC0ERFL_BOEF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_BOEF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDC0ERFL_BORF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_BORF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x10) >> 4
}
func (o *CANFD_B_Type) SetCFDC0ERFL_OVLF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x20)|value<<5)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_OVLF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x20) >> 5
}
func (o *CANFD_B_Type) SetCFDC0ERFL_BLF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x40)|value<<6)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_BLF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x40) >> 6
}
func (o *CANFD_B_Type) SetCFDC0ERFL_ALF(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_ALF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDC0ERFL_SERR(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_SERR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDC0ERFL_FERR(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x200)|value<<9)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_FERR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x200) >> 9
}
func (o *CANFD_B_Type) SetCFDC0ERFL_AERR(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x400)|value<<10)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_AERR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x400) >> 10
}
func (o *CANFD_B_Type) SetCFDC0ERFL_CERR(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x800)|value<<11)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_CERR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x800) >> 11
}
func (o *CANFD_B_Type) SetCFDC0ERFL_B1ERR(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x1000)|value<<12)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_B1ERR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x1000) >> 12
}
func (o *CANFD_B_Type) SetCFDC0ERFL_B0ERR(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x2000)|value<<13)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_B0ERR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x2000) >> 13
}
func (o *CANFD_B_Type) SetCFDC0ERFL_ADERR(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x4000)|value<<14)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_ADERR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x4000) >> 14
}
func (o *CANFD_B_Type) SetCFDC0ERFL_CRCREG(value uint32) {
	volatile.StoreUint32(&o.CFDC0ERFL.Reg, volatile.LoadUint32(&o.CFDC0ERFL.Reg)&^(0x7fff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDC0ERFL_CRCREG() uint32 {
	return (volatile.LoadUint32(&o.CFDC0ERFL.Reg) & 0x7fff0000) >> 16
}

// CANFD_B.CFDGCFG: Global Configuration Register
func (o *CANFD_B_Type) SetCFDGCFG_TPRI(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGCFG_TPRI() uint32 {
	return volatile.LoadUint32(&o.CFDGCFG.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGCFG_DCE(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGCFG_DCE() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGCFG_DRE(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDGCFG_DRE() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDGCFG_MME(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDGCFG_MME() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDGCFG_DCS(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDGCFG_DCS() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0x10) >> 4
}
func (o *CANFD_B_Type) SetCFDGCFG_CMPOC(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0x20)|value<<5)
}
func (o *CANFD_B_Type) GetCFDGCFG_CMPOC() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0x20) >> 5
}
func (o *CANFD_B_Type) SetCFDGCFG_TSP(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0xf00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGCFG_TSP() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0xf00) >> 8
}
func (o *CANFD_B_Type) SetCFDGCFG_TSSS(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0x1000)|value<<12)
}
func (o *CANFD_B_Type) GetCFDGCFG_TSSS() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0x1000) >> 12
}
func (o *CANFD_B_Type) SetCFDGCFG_ITRCP(value uint32) {
	volatile.StoreUint32(&o.CFDGCFG.Reg, volatile.LoadUint32(&o.CFDGCFG.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGCFG_ITRCP() uint32 {
	return (volatile.LoadUint32(&o.CFDGCFG.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGCTR: Global Control Register
func (o *CANFD_B_Type) SetCFDGCTR_GMDC(value uint32) {
	volatile.StoreUint32(&o.CFDGCTR.Reg, volatile.LoadUint32(&o.CFDGCTR.Reg)&^(0x3)|value)
}
func (o *CANFD_B_Type) GetCFDGCTR_GMDC() uint32 {
	return volatile.LoadUint32(&o.CFDGCTR.Reg) & 0x3
}
func (o *CANFD_B_Type) SetCFDGCTR_GSLPR(value uint32) {
	volatile.StoreUint32(&o.CFDGCTR.Reg, volatile.LoadUint32(&o.CFDGCTR.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDGCTR_GSLPR() uint32 {
	return (volatile.LoadUint32(&o.CFDGCTR.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDGCTR_DEIE(value uint32) {
	volatile.StoreUint32(&o.CFDGCTR.Reg, volatile.LoadUint32(&o.CFDGCTR.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGCTR_DEIE() uint32 {
	return (volatile.LoadUint32(&o.CFDGCTR.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDGCTR_MEIE(value uint32) {
	volatile.StoreUint32(&o.CFDGCTR.Reg, volatile.LoadUint32(&o.CFDGCTR.Reg)&^(0x200)|value<<9)
}
func (o *CANFD_B_Type) GetCFDGCTR_MEIE() uint32 {
	return (volatile.LoadUint32(&o.CFDGCTR.Reg) & 0x200) >> 9
}
func (o *CANFD_B_Type) SetCFDGCTR_THLEIE(value uint32) {
	volatile.StoreUint32(&o.CFDGCTR.Reg, volatile.LoadUint32(&o.CFDGCTR.Reg)&^(0x400)|value<<10)
}
func (o *CANFD_B_Type) GetCFDGCTR_THLEIE() uint32 {
	return (volatile.LoadUint32(&o.CFDGCTR.Reg) & 0x400) >> 10
}
func (o *CANFD_B_Type) SetCFDGCTR_CMPOFIE(value uint32) {
	volatile.StoreUint32(&o.CFDGCTR.Reg, volatile.LoadUint32(&o.CFDGCTR.Reg)&^(0x800)|value<<11)
}
func (o *CANFD_B_Type) GetCFDGCTR_CMPOFIE() uint32 {
	return (volatile.LoadUint32(&o.CFDGCTR.Reg) & 0x800) >> 11
}
func (o *CANFD_B_Type) SetCFDGCTR_TSRST(value uint32) {
	volatile.StoreUint32(&o.CFDGCTR.Reg, volatile.LoadUint32(&o.CFDGCTR.Reg)&^(0x10000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGCTR_TSRST() uint32 {
	return (volatile.LoadUint32(&o.CFDGCTR.Reg) & 0x10000) >> 16
}

// CANFD_B.CFDGSTS: Global Status Register
func (o *CANFD_B_Type) SetCFDGSTS_GRSTSTS(value uint32) {
	volatile.StoreUint32(&o.CFDGSTS.Reg, volatile.LoadUint32(&o.CFDGSTS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGSTS_GRSTSTS() uint32 {
	return volatile.LoadUint32(&o.CFDGSTS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGSTS_GHLTSTS(value uint32) {
	volatile.StoreUint32(&o.CFDGSTS.Reg, volatile.LoadUint32(&o.CFDGSTS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGSTS_GHLTSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDGSTS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGSTS_GSLPSTS(value uint32) {
	volatile.StoreUint32(&o.CFDGSTS.Reg, volatile.LoadUint32(&o.CFDGSTS.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDGSTS_GSLPSTS() uint32 {
	return (volatile.LoadUint32(&o.CFDGSTS.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDGSTS_GRAMINIT(value uint32) {
	volatile.StoreUint32(&o.CFDGSTS.Reg, volatile.LoadUint32(&o.CFDGSTS.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDGSTS_GRAMINIT() uint32 {
	return (volatile.LoadUint32(&o.CFDGSTS.Reg) & 0x8) >> 3
}

// CANFD_B.CFDGERFL: Global Error Flag Register
func (o *CANFD_B_Type) SetCFDGERFL_DEF(value uint32) {
	volatile.StoreUint32(&o.CFDGERFL.Reg, volatile.LoadUint32(&o.CFDGERFL.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGERFL_DEF() uint32 {
	return volatile.LoadUint32(&o.CFDGERFL.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGERFL_MES(value uint32) {
	volatile.StoreUint32(&o.CFDGERFL.Reg, volatile.LoadUint32(&o.CFDGERFL.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGERFL_MES() uint32 {
	return (volatile.LoadUint32(&o.CFDGERFL.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGERFL_THLES(value uint32) {
	volatile.StoreUint32(&o.CFDGERFL.Reg, volatile.LoadUint32(&o.CFDGERFL.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDGERFL_THLES() uint32 {
	return (volatile.LoadUint32(&o.CFDGERFL.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDGERFL_CMPOF(value uint32) {
	volatile.StoreUint32(&o.CFDGERFL.Reg, volatile.LoadUint32(&o.CFDGERFL.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDGERFL_CMPOF() uint32 {
	return (volatile.LoadUint32(&o.CFDGERFL.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDGERFL_EEF0(value uint32) {
	volatile.StoreUint32(&o.CFDGERFL.Reg, volatile.LoadUint32(&o.CFDGERFL.Reg)&^(0x10000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGERFL_EEF0() uint32 {
	return (volatile.LoadUint32(&o.CFDGERFL.Reg) & 0x10000) >> 16
}

// CANFD_B.CFDGTSC: Global Timestamp Counter Register
func (o *CANFD_B_Type) SetCFDGTSC_TS(value uint32) {
	volatile.StoreUint32(&o.CFDGTSC.Reg, volatile.LoadUint32(&o.CFDGTSC.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDGTSC_TS() uint32 {
	return volatile.LoadUint32(&o.CFDGTSC.Reg) & 0xffff
}

// CANFD_B.CFDGAFLECTR: Global Acceptance Filter List Entry Control Register
func (o *CANFD_B_Type) SetCFDGAFLECTR_AFLPN(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLECTR.Reg, volatile.LoadUint32(&o.CFDGAFLECTR.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLECTR_AFLPN() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLECTR.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLECTR_AFLDAE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLECTR.Reg, volatile.LoadUint32(&o.CFDGAFLECTR.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLECTR_AFLDAE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLECTR.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLCFG: Global Acceptance Filter List Configuration Register
func (o *CANFD_B_Type) SetCFDGAFLCFG_RNC0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLCFG.Reg, volatile.LoadUint32(&o.CFDGAFLCFG.Reg)&^(0x3f0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLCFG_RNC0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLCFG.Reg) & 0x3f0000) >> 16
}

// CANFD_B.CFDRMNB: RX Message Buffer Number Register
func (o *CANFD_B_Type) SetCFDRMNB_NRXMB(value uint32) {
	volatile.StoreUint32(&o.CFDRMNB.Reg, volatile.LoadUint32(&o.CFDRMNB.Reg)&^(0x3f)|value)
}
func (o *CANFD_B_Type) GetCFDRMNB_NRXMB() uint32 {
	return volatile.LoadUint32(&o.CFDRMNB.Reg) & 0x3f
}
func (o *CANFD_B_Type) SetCFDRMNB_RMPLS(value uint32) {
	volatile.StoreUint32(&o.CFDRMNB.Reg, volatile.LoadUint32(&o.CFDRMNB.Reg)&^(0x700)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMNB_RMPLS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMNB.Reg) & 0x700) >> 8
}

// CANFD_B.CFDRMND: RX Message Buffer New Data Register
func (o *CANFD_B_Type) SetCFDRMND(value uint32) {
	volatile.StoreUint32(&o.CFDRMND.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRMND() uint32 {
	return volatile.LoadUint32(&o.CFDRMND.Reg)
}

// CANFD_B.CFDRMIEC: RX Message Buffer Interrupt Enable Configuration Register
func (o *CANFD_B_Type) SetCFDRMIEC(value uint32) {
	volatile.StoreUint32(&o.CFDRMIEC.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRMIEC() uint32 {
	return volatile.LoadUint32(&o.CFDRMIEC.Reg)
}

// CANFD_B.CFDRFCC0: RX FIFO Configuration/Control Registers %s
func (o *CANFD_B_Type) SetCFDRFCC0_RFE(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC0.Reg, volatile.LoadUint32(&o.CFDRFCC0.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRFCC0_RFE() uint32 {
	return volatile.LoadUint32(&o.CFDRFCC0.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRFCC0_RFIE(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC0.Reg, volatile.LoadUint32(&o.CFDRFCC0.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRFCC0_RFIE() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC0.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRFCC0_RFPLS(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC0.Reg, volatile.LoadUint32(&o.CFDRFCC0.Reg)&^(0x70)|value<<4)
}
func (o *CANFD_B_Type) GetCFDRFCC0_RFPLS() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC0.Reg) & 0x70) >> 4
}
func (o *CANFD_B_Type) SetCFDRFCC0_RFDC(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC0.Reg, volatile.LoadUint32(&o.CFDRFCC0.Reg)&^(0x700)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFCC0_RFDC() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC0.Reg) & 0x700) >> 8
}
func (o *CANFD_B_Type) SetCFDRFCC0_RFIM(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC0.Reg, volatile.LoadUint32(&o.CFDRFCC0.Reg)&^(0x1000)|value<<12)
}
func (o *CANFD_B_Type) GetCFDRFCC0_RFIM() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC0.Reg) & 0x1000) >> 12
}
func (o *CANFD_B_Type) SetCFDRFCC0_RFIGCV(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC0.Reg, volatile.LoadUint32(&o.CFDRFCC0.Reg)&^(0xe000)|value<<13)
}
func (o *CANFD_B_Type) GetCFDRFCC0_RFIGCV() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC0.Reg) & 0xe000) >> 13
}

// CANFD_B.CFDRFCC1: RX FIFO Configuration/Control Registers %s
func (o *CANFD_B_Type) SetCFDRFCC1_RFE(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC1.Reg, volatile.LoadUint32(&o.CFDRFCC1.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRFCC1_RFE() uint32 {
	return volatile.LoadUint32(&o.CFDRFCC1.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRFCC1_RFIE(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC1.Reg, volatile.LoadUint32(&o.CFDRFCC1.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRFCC1_RFIE() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC1.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRFCC1_RFPLS(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC1.Reg, volatile.LoadUint32(&o.CFDRFCC1.Reg)&^(0x70)|value<<4)
}
func (o *CANFD_B_Type) GetCFDRFCC1_RFPLS() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC1.Reg) & 0x70) >> 4
}
func (o *CANFD_B_Type) SetCFDRFCC1_RFDC(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC1.Reg, volatile.LoadUint32(&o.CFDRFCC1.Reg)&^(0x700)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFCC1_RFDC() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC1.Reg) & 0x700) >> 8
}
func (o *CANFD_B_Type) SetCFDRFCC1_RFIM(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC1.Reg, volatile.LoadUint32(&o.CFDRFCC1.Reg)&^(0x1000)|value<<12)
}
func (o *CANFD_B_Type) GetCFDRFCC1_RFIM() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC1.Reg) & 0x1000) >> 12
}
func (o *CANFD_B_Type) SetCFDRFCC1_RFIGCV(value uint32) {
	volatile.StoreUint32(&o.CFDRFCC1.Reg, volatile.LoadUint32(&o.CFDRFCC1.Reg)&^(0xe000)|value<<13)
}
func (o *CANFD_B_Type) GetCFDRFCC1_RFIGCV() uint32 {
	return (volatile.LoadUint32(&o.CFDRFCC1.Reg) & 0xe000) >> 13
}

// CANFD_B.CFDRFSTS0: RX FIFO Status Registers %s
func (o *CANFD_B_Type) SetCFDRFSTS0_RFEMP(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS0.Reg, volatile.LoadUint32(&o.CFDRFSTS0.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRFSTS0_RFEMP() uint32 {
	return volatile.LoadUint32(&o.CFDRFSTS0.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRFSTS0_RFFLL(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS0.Reg, volatile.LoadUint32(&o.CFDRFSTS0.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRFSTS0_RFFLL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS0.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRFSTS0_RFMLT(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS0.Reg, volatile.LoadUint32(&o.CFDRFSTS0.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRFSTS0_RFMLT() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS0.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRFSTS0_RFIF(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS0.Reg, volatile.LoadUint32(&o.CFDRFSTS0.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDRFSTS0_RFIF() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS0.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDRFSTS0_RFMC(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS0.Reg, volatile.LoadUint32(&o.CFDRFSTS0.Reg)&^(0x3f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFSTS0_RFMC() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS0.Reg) & 0x3f00) >> 8
}

// CANFD_B.CFDRFSTS1: RX FIFO Status Registers %s
func (o *CANFD_B_Type) SetCFDRFSTS1_RFEMP(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS1.Reg, volatile.LoadUint32(&o.CFDRFSTS1.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRFSTS1_RFEMP() uint32 {
	return volatile.LoadUint32(&o.CFDRFSTS1.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRFSTS1_RFFLL(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS1.Reg, volatile.LoadUint32(&o.CFDRFSTS1.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRFSTS1_RFFLL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS1.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRFSTS1_RFMLT(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS1.Reg, volatile.LoadUint32(&o.CFDRFSTS1.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRFSTS1_RFMLT() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS1.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRFSTS1_RFIF(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS1.Reg, volatile.LoadUint32(&o.CFDRFSTS1.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDRFSTS1_RFIF() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS1.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDRFSTS1_RFMC(value uint32) {
	volatile.StoreUint32(&o.CFDRFSTS1.Reg, volatile.LoadUint32(&o.CFDRFSTS1.Reg)&^(0x3f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFSTS1_RFMC() uint32 {
	return (volatile.LoadUint32(&o.CFDRFSTS1.Reg) & 0x3f00) >> 8
}

// CANFD_B.CFDRFPCTR0: RX FIFO Pointer Control Registers %s
func (o *CANFD_B_Type) SetCFDRFPCTR0_RFPC(value uint32) {
	volatile.StoreUint32(&o.CFDRFPCTR0.Reg, volatile.LoadUint32(&o.CFDRFPCTR0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFPCTR0_RFPC() uint32 {
	return volatile.LoadUint32(&o.CFDRFPCTR0.Reg) & 0xff
}

// CANFD_B.CFDRFPCTR1: RX FIFO Pointer Control Registers %s
func (o *CANFD_B_Type) SetCFDRFPCTR1_RFPC(value uint32) {
	volatile.StoreUint32(&o.CFDRFPCTR1.Reg, volatile.LoadUint32(&o.CFDRFPCTR1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFPCTR1_RFPC() uint32 {
	return volatile.LoadUint32(&o.CFDRFPCTR1.Reg) & 0xff
}

// CANFD_B.CFDCFCC: Common FIFO Configuration/Control Register
func (o *CANFD_B_Type) SetCFDCFCC_CFE(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFE() uint32 {
	return volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDCFCC_CFRXIE(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFRXIE() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDCFCC_CFTXIE(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFTXIE() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDCFCC_CFPLS(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x70)|value<<4)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFPLS() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x70) >> 4
}
func (o *CANFD_B_Type) SetCFDCFCC_CFM(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFM() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDCFCC_CFITSS(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x400)|value<<10)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFITSS() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x400) >> 10
}
func (o *CANFD_B_Type) SetCFDCFCC_CFITR(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x800)|value<<11)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFITR() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x800) >> 11
}
func (o *CANFD_B_Type) SetCFDCFCC_CFIM(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x1000)|value<<12)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFIM() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x1000) >> 12
}
func (o *CANFD_B_Type) SetCFDCFCC_CFIGCV(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0xe000)|value<<13)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFIGCV() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0xe000) >> 13
}
func (o *CANFD_B_Type) SetCFDCFCC_CFTML(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0x30000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFTML() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0x30000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFCC_CFDC(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0xe00000)|value<<21)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFDC() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0xe00000) >> 21
}
func (o *CANFD_B_Type) SetCFDCFCC_CFITT(value uint32) {
	volatile.StoreUint32(&o.CFDCFCC.Reg, volatile.LoadUint32(&o.CFDCFCC.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFCC_CFITT() uint32 {
	return (volatile.LoadUint32(&o.CFDCFCC.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFSTS: Common FIFO Status Register
func (o *CANFD_B_Type) SetCFDCFSTS_CFEMP(value uint32) {
	volatile.StoreUint32(&o.CFDCFSTS.Reg, volatile.LoadUint32(&o.CFDCFSTS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDCFSTS_CFEMP() uint32 {
	return volatile.LoadUint32(&o.CFDCFSTS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDCFSTS_CFFLL(value uint32) {
	volatile.StoreUint32(&o.CFDCFSTS.Reg, volatile.LoadUint32(&o.CFDCFSTS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDCFSTS_CFFLL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFSTS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDCFSTS_CFMLT(value uint32) {
	volatile.StoreUint32(&o.CFDCFSTS.Reg, volatile.LoadUint32(&o.CFDCFSTS.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDCFSTS_CFMLT() uint32 {
	return (volatile.LoadUint32(&o.CFDCFSTS.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDCFSTS_CFRXIF(value uint32) {
	volatile.StoreUint32(&o.CFDCFSTS.Reg, volatile.LoadUint32(&o.CFDCFSTS.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDCFSTS_CFRXIF() uint32 {
	return (volatile.LoadUint32(&o.CFDCFSTS.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDCFSTS_CFTXIF(value uint32) {
	volatile.StoreUint32(&o.CFDCFSTS.Reg, volatile.LoadUint32(&o.CFDCFSTS.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDCFSTS_CFTXIF() uint32 {
	return (volatile.LoadUint32(&o.CFDCFSTS.Reg) & 0x10) >> 4
}
func (o *CANFD_B_Type) SetCFDCFSTS_CFMC(value uint32) {
	volatile.StoreUint32(&o.CFDCFSTS.Reg, volatile.LoadUint32(&o.CFDCFSTS.Reg)&^(0x3f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFSTS_CFMC() uint32 {
	return (volatile.LoadUint32(&o.CFDCFSTS.Reg) & 0x3f00) >> 8
}

// CANFD_B.CFDCFPCTR: Common FIFO Pointer Control Register
func (o *CANFD_B_Type) SetCFDCFPCTR_CFPC(value uint32) {
	volatile.StoreUint32(&o.CFDCFPCTR.Reg, volatile.LoadUint32(&o.CFDCFPCTR.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFPCTR_CFPC() uint32 {
	return volatile.LoadUint32(&o.CFDCFPCTR.Reg) & 0xff
}

// CANFD_B.CFDFESTS: FIFO Empty Status Register
func (o *CANFD_B_Type) SetCFDFESTS_RFXEMP(value uint32) {
	volatile.StoreUint32(&o.CFDFESTS.Reg, volatile.LoadUint32(&o.CFDFESTS.Reg)&^(0x3)|value)
}
func (o *CANFD_B_Type) GetCFDFESTS_RFXEMP() uint32 {
	return volatile.LoadUint32(&o.CFDFESTS.Reg) & 0x3
}
func (o *CANFD_B_Type) SetCFDFESTS_CFEMP(value uint32) {
	volatile.StoreUint32(&o.CFDFESTS.Reg, volatile.LoadUint32(&o.CFDFESTS.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDFESTS_CFEMP() uint32 {
	return (volatile.LoadUint32(&o.CFDFESTS.Reg) & 0x100) >> 8
}

// CANFD_B.CFDFFSTS: FIFO Full Status Register
func (o *CANFD_B_Type) SetCFDFFSTS_RFXFLL(value uint32) {
	volatile.StoreUint32(&o.CFDFFSTS.Reg, volatile.LoadUint32(&o.CFDFFSTS.Reg)&^(0x3)|value)
}
func (o *CANFD_B_Type) GetCFDFFSTS_RFXFLL() uint32 {
	return volatile.LoadUint32(&o.CFDFFSTS.Reg) & 0x3
}
func (o *CANFD_B_Type) SetCFDFFSTS_CFFLL(value uint32) {
	volatile.StoreUint32(&o.CFDFFSTS.Reg, volatile.LoadUint32(&o.CFDFFSTS.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDFFSTS_CFFLL() uint32 {
	return (volatile.LoadUint32(&o.CFDFFSTS.Reg) & 0x100) >> 8
}

// CANFD_B.CFDFMSTS: FIFO Message Lost Status Register
func (o *CANFD_B_Type) SetCFDFMSTS_RFXMLT(value uint32) {
	volatile.StoreUint32(&o.CFDFMSTS.Reg, volatile.LoadUint32(&o.CFDFMSTS.Reg)&^(0x3)|value)
}
func (o *CANFD_B_Type) GetCFDFMSTS_RFXMLT() uint32 {
	return volatile.LoadUint32(&o.CFDFMSTS.Reg) & 0x3
}
func (o *CANFD_B_Type) SetCFDFMSTS_CFMLT(value uint32) {
	volatile.StoreUint32(&o.CFDFMSTS.Reg, volatile.LoadUint32(&o.CFDFMSTS.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDFMSTS_CFMLT() uint32 {
	return (volatile.LoadUint32(&o.CFDFMSTS.Reg) & 0x100) >> 8
}

// CANFD_B.CFDRFISTS: RX FIFO Interrupt Flag Status Register
func (o *CANFD_B_Type) SetCFDRFISTS_RFXIF(value uint32) {
	volatile.StoreUint32(&o.CFDRFISTS.Reg, volatile.LoadUint32(&o.CFDRFISTS.Reg)&^(0x3)|value)
}
func (o *CANFD_B_Type) GetCFDRFISTS_RFXIF() uint32 {
	return volatile.LoadUint32(&o.CFDRFISTS.Reg) & 0x3
}

// CANFD_B.CFDTMC0: TX Message Buffer Control Registers %s
func (o *CANFD_B_Type) SetCFDTMC0_TMTR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC0.Reg, volatile.LoadUint8(&o.CFDTMC0.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMC0_TMTR() uint8 {
	return volatile.LoadUint8(&o.CFDTMC0.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMC0_TMTAR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC0.Reg, volatile.LoadUint8(&o.CFDTMC0.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMC0_TMTAR() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC0.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMC0_TMOM(value uint8) {
	volatile.StoreUint8(&o.CFDTMC0.Reg, volatile.LoadUint8(&o.CFDTMC0.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMC0_TMOM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC0.Reg) & 0x4) >> 2
}

// CANFD_B.CFDTMC1: TX Message Buffer Control Registers %s
func (o *CANFD_B_Type) SetCFDTMC1_TMTR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC1.Reg, volatile.LoadUint8(&o.CFDTMC1.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMC1_TMTR() uint8 {
	return volatile.LoadUint8(&o.CFDTMC1.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMC1_TMTAR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC1.Reg, volatile.LoadUint8(&o.CFDTMC1.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMC1_TMTAR() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC1.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMC1_TMOM(value uint8) {
	volatile.StoreUint8(&o.CFDTMC1.Reg, volatile.LoadUint8(&o.CFDTMC1.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMC1_TMOM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC1.Reg) & 0x4) >> 2
}

// CANFD_B.CFDTMC2: TX Message Buffer Control Registers %s
func (o *CANFD_B_Type) SetCFDTMC2_TMTR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC2.Reg, volatile.LoadUint8(&o.CFDTMC2.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMC2_TMTR() uint8 {
	return volatile.LoadUint8(&o.CFDTMC2.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMC2_TMTAR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC2.Reg, volatile.LoadUint8(&o.CFDTMC2.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMC2_TMTAR() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC2.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMC2_TMOM(value uint8) {
	volatile.StoreUint8(&o.CFDTMC2.Reg, volatile.LoadUint8(&o.CFDTMC2.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMC2_TMOM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC2.Reg) & 0x4) >> 2
}

// CANFD_B.CFDTMC3: TX Message Buffer Control Registers %s
func (o *CANFD_B_Type) SetCFDTMC3_TMTR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC3.Reg, volatile.LoadUint8(&o.CFDTMC3.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMC3_TMTR() uint8 {
	return volatile.LoadUint8(&o.CFDTMC3.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMC3_TMTAR(value uint8) {
	volatile.StoreUint8(&o.CFDTMC3.Reg, volatile.LoadUint8(&o.CFDTMC3.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMC3_TMTAR() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC3.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMC3_TMOM(value uint8) {
	volatile.StoreUint8(&o.CFDTMC3.Reg, volatile.LoadUint8(&o.CFDTMC3.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMC3_TMOM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMC3.Reg) & 0x4) >> 2
}

// CANFD_B.CFDTMSTS0: TX Message Buffer Status Registers %s
func (o *CANFD_B_Type) SetCFDTMSTS0_TMTSTS(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS0.Reg, volatile.LoadUint8(&o.CFDTMSTS0.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMSTS0_TMTSTS() uint8 {
	return volatile.LoadUint8(&o.CFDTMSTS0.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMSTS0_TMTRF(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS0.Reg, volatile.LoadUint8(&o.CFDTMSTS0.Reg)&^(0x6)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMSTS0_TMTRF() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS0.Reg) & 0x6) >> 1
}
func (o *CANFD_B_Type) SetCFDTMSTS0_TMTRM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS0.Reg, volatile.LoadUint8(&o.CFDTMSTS0.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDTMSTS0_TMTRM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS0.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDTMSTS0_TMTARM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS0.Reg, volatile.LoadUint8(&o.CFDTMSTS0.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDTMSTS0_TMTARM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS0.Reg) & 0x10) >> 4
}

// CANFD_B.CFDTMSTS1: TX Message Buffer Status Registers %s
func (o *CANFD_B_Type) SetCFDTMSTS1_TMTSTS(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS1.Reg, volatile.LoadUint8(&o.CFDTMSTS1.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMSTS1_TMTSTS() uint8 {
	return volatile.LoadUint8(&o.CFDTMSTS1.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMSTS1_TMTRF(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS1.Reg, volatile.LoadUint8(&o.CFDTMSTS1.Reg)&^(0x6)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMSTS1_TMTRF() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS1.Reg) & 0x6) >> 1
}
func (o *CANFD_B_Type) SetCFDTMSTS1_TMTRM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS1.Reg, volatile.LoadUint8(&o.CFDTMSTS1.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDTMSTS1_TMTRM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS1.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDTMSTS1_TMTARM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS1.Reg, volatile.LoadUint8(&o.CFDTMSTS1.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDTMSTS1_TMTARM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS1.Reg) & 0x10) >> 4
}

// CANFD_B.CFDTMSTS2: TX Message Buffer Status Registers %s
func (o *CANFD_B_Type) SetCFDTMSTS2_TMTSTS(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS2.Reg, volatile.LoadUint8(&o.CFDTMSTS2.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMSTS2_TMTSTS() uint8 {
	return volatile.LoadUint8(&o.CFDTMSTS2.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMSTS2_TMTRF(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS2.Reg, volatile.LoadUint8(&o.CFDTMSTS2.Reg)&^(0x6)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMSTS2_TMTRF() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS2.Reg) & 0x6) >> 1
}
func (o *CANFD_B_Type) SetCFDTMSTS2_TMTRM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS2.Reg, volatile.LoadUint8(&o.CFDTMSTS2.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDTMSTS2_TMTRM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS2.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDTMSTS2_TMTARM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS2.Reg, volatile.LoadUint8(&o.CFDTMSTS2.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDTMSTS2_TMTARM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS2.Reg) & 0x10) >> 4
}

// CANFD_B.CFDTMSTS3: TX Message Buffer Status Registers %s
func (o *CANFD_B_Type) SetCFDTMSTS3_TMTSTS(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS3.Reg, volatile.LoadUint8(&o.CFDTMSTS3.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMSTS3_TMTSTS() uint8 {
	return volatile.LoadUint8(&o.CFDTMSTS3.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMSTS3_TMTRF(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS3.Reg, volatile.LoadUint8(&o.CFDTMSTS3.Reg)&^(0x6)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMSTS3_TMTRF() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS3.Reg) & 0x6) >> 1
}
func (o *CANFD_B_Type) SetCFDTMSTS3_TMTRM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS3.Reg, volatile.LoadUint8(&o.CFDTMSTS3.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDTMSTS3_TMTRM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS3.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDTMSTS3_TMTARM(value uint8) {
	volatile.StoreUint8(&o.CFDTMSTS3.Reg, volatile.LoadUint8(&o.CFDTMSTS3.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDTMSTS3_TMTARM() uint8 {
	return (volatile.LoadUint8(&o.CFDTMSTS3.Reg) & 0x10) >> 4
}

// CANFD_B.CFDTMTRSTS: TX Message Buffer Transmission Request Status Register
func (o *CANFD_B_Type) SetCFDTMTRSTS(value uint32) {
	volatile.StoreUint32(&o.CFDTMTRSTS.Reg, volatile.LoadUint32(&o.CFDTMTRSTS.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDTMTRSTS() uint32 {
	return volatile.LoadUint32(&o.CFDTMTRSTS.Reg) & 0xf
}

// CANFD_B.CFDTMTARSTS: TX Message Buffer Transmission Abort Request Status Register
func (o *CANFD_B_Type) SetCFDTMTARSTS(value uint32) {
	volatile.StoreUint32(&o.CFDTMTARSTS.Reg, volatile.LoadUint32(&o.CFDTMTARSTS.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDTMTARSTS() uint32 {
	return volatile.LoadUint32(&o.CFDTMTARSTS.Reg) & 0xf
}

// CANFD_B.CFDTMTCSTS: TX Message Buffer Transmission Completion Status Register
func (o *CANFD_B_Type) SetCFDTMTCSTS(value uint32) {
	volatile.StoreUint32(&o.CFDTMTCSTS.Reg, volatile.LoadUint32(&o.CFDTMTCSTS.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDTMTCSTS() uint32 {
	return volatile.LoadUint32(&o.CFDTMTCSTS.Reg) & 0xf
}

// CANFD_B.CFDTMTASTS: TX Message Buffer Transmission Abort Status Register
func (o *CANFD_B_Type) SetCFDTMTASTS(value uint32) {
	volatile.StoreUint32(&o.CFDTMTASTS.Reg, volatile.LoadUint32(&o.CFDTMTASTS.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDTMTASTS() uint32 {
	return volatile.LoadUint32(&o.CFDTMTASTS.Reg) & 0xf
}

// CANFD_B.CFDTMIEC: TX Message Buffer Interrupt Enable Configuration Register
func (o *CANFD_B_Type) SetCFDTMIEC_TMIEg(value uint32) {
	volatile.StoreUint32(&o.CFDTMIEC.Reg, volatile.LoadUint32(&o.CFDTMIEC.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDTMIEC_TMIEg() uint32 {
	return volatile.LoadUint32(&o.CFDTMIEC.Reg) & 0xf
}

// CANFD_B.CFDTXQCC: TX Queue Configuration/Control Register
func (o *CANFD_B_Type) SetCFDTXQCC_TXQE(value uint32) {
	volatile.StoreUint32(&o.CFDTXQCC.Reg, volatile.LoadUint32(&o.CFDTXQCC.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTXQCC_TXQE() uint32 {
	return volatile.LoadUint32(&o.CFDTXQCC.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTXQCC_TXQTXIE(value uint32) {
	volatile.StoreUint32(&o.CFDTXQCC.Reg, volatile.LoadUint32(&o.CFDTXQCC.Reg)&^(0x20)|value<<5)
}
func (o *CANFD_B_Type) GetCFDTXQCC_TXQTXIE() uint32 {
	return (volatile.LoadUint32(&o.CFDTXQCC.Reg) & 0x20) >> 5
}
func (o *CANFD_B_Type) SetCFDTXQCC_TXQIM(value uint32) {
	volatile.StoreUint32(&o.CFDTXQCC.Reg, volatile.LoadUint32(&o.CFDTXQCC.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDTXQCC_TXQIM() uint32 {
	return (volatile.LoadUint32(&o.CFDTXQCC.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDTXQCC_TXQDC(value uint32) {
	volatile.StoreUint32(&o.CFDTXQCC.Reg, volatile.LoadUint32(&o.CFDTXQCC.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTXQCC_TXQDC() uint32 {
	return (volatile.LoadUint32(&o.CFDTXQCC.Reg) & 0x300) >> 8
}

// CANFD_B.CFDTXQSTS: TX Queue Status Register
func (o *CANFD_B_Type) SetCFDTXQSTS_TXQEMP(value uint32) {
	volatile.StoreUint32(&o.CFDTXQSTS.Reg, volatile.LoadUint32(&o.CFDTXQSTS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTXQSTS_TXQEMP() uint32 {
	return volatile.LoadUint32(&o.CFDTXQSTS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTXQSTS_TXQFLL(value uint32) {
	volatile.StoreUint32(&o.CFDTXQSTS.Reg, volatile.LoadUint32(&o.CFDTXQSTS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTXQSTS_TXQFLL() uint32 {
	return (volatile.LoadUint32(&o.CFDTXQSTS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTXQSTS_TXQTXIF(value uint32) {
	volatile.StoreUint32(&o.CFDTXQSTS.Reg, volatile.LoadUint32(&o.CFDTXQSTS.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTXQSTS_TXQTXIF() uint32 {
	return (volatile.LoadUint32(&o.CFDTXQSTS.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDTXQSTS_TXQMC(value uint32) {
	volatile.StoreUint32(&o.CFDTXQSTS.Reg, volatile.LoadUint32(&o.CFDTXQSTS.Reg)&^(0x700)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTXQSTS_TXQMC() uint32 {
	return (volatile.LoadUint32(&o.CFDTXQSTS.Reg) & 0x700) >> 8
}

// CANFD_B.CFDTXQPCTR: TX Queue Pointer Control Register
func (o *CANFD_B_Type) SetCFDTXQPCTR_TXQPC(value uint32) {
	volatile.StoreUint32(&o.CFDTXQPCTR.Reg, volatile.LoadUint32(&o.CFDTXQPCTR.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTXQPCTR_TXQPC() uint32 {
	return volatile.LoadUint32(&o.CFDTXQPCTR.Reg) & 0xff
}

// CANFD_B.CFDTHLCC: TX History List Configuration/Control Register
func (o *CANFD_B_Type) SetCFDTHLCC_THLE(value uint32) {
	volatile.StoreUint32(&o.CFDTHLCC.Reg, volatile.LoadUint32(&o.CFDTHLCC.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTHLCC_THLE() uint32 {
	return volatile.LoadUint32(&o.CFDTHLCC.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTHLCC_THLIE(value uint32) {
	volatile.StoreUint32(&o.CFDTHLCC.Reg, volatile.LoadUint32(&o.CFDTHLCC.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTHLCC_THLIE() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLCC.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDTHLCC_THLIM(value uint32) {
	volatile.StoreUint32(&o.CFDTHLCC.Reg, volatile.LoadUint32(&o.CFDTHLCC.Reg)&^(0x200)|value<<9)
}
func (o *CANFD_B_Type) GetCFDTHLCC_THLIM() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLCC.Reg) & 0x200) >> 9
}
func (o *CANFD_B_Type) SetCFDTHLCC_THLDTE(value uint32) {
	volatile.StoreUint32(&o.CFDTHLCC.Reg, volatile.LoadUint32(&o.CFDTHLCC.Reg)&^(0x400)|value<<10)
}
func (o *CANFD_B_Type) GetCFDTHLCC_THLDTE() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLCC.Reg) & 0x400) >> 10
}

// CANFD_B.CFDTHLSTS: TX History List Status Register
func (o *CANFD_B_Type) SetCFDTHLSTS_THLEMP(value uint32) {
	volatile.StoreUint32(&o.CFDTHLSTS.Reg, volatile.LoadUint32(&o.CFDTHLSTS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTHLSTS_THLEMP() uint32 {
	return volatile.LoadUint32(&o.CFDTHLSTS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTHLSTS_THLFLL(value uint32) {
	volatile.StoreUint32(&o.CFDTHLSTS.Reg, volatile.LoadUint32(&o.CFDTHLSTS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTHLSTS_THLFLL() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLSTS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTHLSTS_THLELT(value uint32) {
	volatile.StoreUint32(&o.CFDTHLSTS.Reg, volatile.LoadUint32(&o.CFDTHLSTS.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTHLSTS_THLELT() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLSTS.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDTHLSTS_THLIF(value uint32) {
	volatile.StoreUint32(&o.CFDTHLSTS.Reg, volatile.LoadUint32(&o.CFDTHLSTS.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDTHLSTS_THLIF() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLSTS.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDTHLSTS_THLMC(value uint32) {
	volatile.StoreUint32(&o.CFDTHLSTS.Reg, volatile.LoadUint32(&o.CFDTHLSTS.Reg)&^(0xf00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTHLSTS_THLMC() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLSTS.Reg) & 0xf00) >> 8
}

// CANFD_B.CFDTHLPCTR: TX History List Pointer Control Register
func (o *CANFD_B_Type) SetCFDTHLPCTR_THLPC(value uint32) {
	volatile.StoreUint32(&o.CFDTHLPCTR.Reg, volatile.LoadUint32(&o.CFDTHLPCTR.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTHLPCTR_THLPC() uint32 {
	return volatile.LoadUint32(&o.CFDTHLPCTR.Reg) & 0xff
}

// CANFD_B.CFDGTINTSTS: Global TX Interrupt Status Register
func (o *CANFD_B_Type) SetCFDGTINTSTS_TSIF0(value uint32) {
	volatile.StoreUint32(&o.CFDGTINTSTS.Reg, volatile.LoadUint32(&o.CFDGTINTSTS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGTINTSTS_TSIF0() uint32 {
	return volatile.LoadUint32(&o.CFDGTINTSTS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGTINTSTS_TAI0(value uint32) {
	volatile.StoreUint32(&o.CFDGTINTSTS.Reg, volatile.LoadUint32(&o.CFDGTINTSTS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGTINTSTS_TAI0() uint32 {
	return (volatile.LoadUint32(&o.CFDGTINTSTS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGTINTSTS_TQIF0(value uint32) {
	volatile.StoreUint32(&o.CFDGTINTSTS.Reg, volatile.LoadUint32(&o.CFDGTINTSTS.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDGTINTSTS_TQIF0() uint32 {
	return (volatile.LoadUint32(&o.CFDGTINTSTS.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDGTINTSTS_CFTIF0(value uint32) {
	volatile.StoreUint32(&o.CFDGTINTSTS.Reg, volatile.LoadUint32(&o.CFDGTINTSTS.Reg)&^(0x8)|value<<3)
}
func (o *CANFD_B_Type) GetCFDGTINTSTS_CFTIF0() uint32 {
	return (volatile.LoadUint32(&o.CFDGTINTSTS.Reg) & 0x8) >> 3
}
func (o *CANFD_B_Type) SetCFDGTINTSTS_THIF0(value uint32) {
	volatile.StoreUint32(&o.CFDGTINTSTS.Reg, volatile.LoadUint32(&o.CFDGTINTSTS.Reg)&^(0x10)|value<<4)
}
func (o *CANFD_B_Type) GetCFDGTINTSTS_THIF0() uint32 {
	return (volatile.LoadUint32(&o.CFDGTINTSTS.Reg) & 0x10) >> 4
}

// CANFD_B.CFDGTSTCFG: Global Test Configuration Register
func (o *CANFD_B_Type) SetCFDGTSTCFG_RTMPS(value uint32) {
	volatile.StoreUint32(&o.CFDGTSTCFG.Reg, volatile.LoadUint32(&o.CFDGTSTCFG.Reg)&^(0xf0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGTSTCFG_RTMPS() uint32 {
	return (volatile.LoadUint32(&o.CFDGTSTCFG.Reg) & 0xf0000) >> 16
}

// CANFD_B.CFDGTSTCTR: Global Test Control Register
func (o *CANFD_B_Type) SetCFDGTSTCTR_RTME(value uint32) {
	volatile.StoreUint32(&o.CFDGTSTCTR.Reg, volatile.LoadUint32(&o.CFDGTSTCTR.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDGTSTCTR_RTME() uint32 {
	return (volatile.LoadUint32(&o.CFDGTSTCTR.Reg) & 0x4) >> 2
}

// CANFD_B.CFDGFDCFG: Global FD Configuration Register
func (o *CANFD_B_Type) SetCFDGFDCFG_RPED(value uint32) {
	volatile.StoreUint32(&o.CFDGFDCFG.Reg, volatile.LoadUint32(&o.CFDGFDCFG.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGFDCFG_RPED() uint32 {
	return volatile.LoadUint32(&o.CFDGFDCFG.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGFDCFG_TSCCFG(value uint32) {
	volatile.StoreUint32(&o.CFDGFDCFG.Reg, volatile.LoadUint32(&o.CFDGFDCFG.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGFDCFG_TSCCFG() uint32 {
	return (volatile.LoadUint32(&o.CFDGFDCFG.Reg) & 0x300) >> 8
}

// CANFD_B.CFDGLOCKK: Global Lock Key Register
func (o *CANFD_B_Type) SetCFDGLOCKK_LOCK(value uint32) {
	volatile.StoreUint32(&o.CFDGLOCKK.Reg, volatile.LoadUint32(&o.CFDGLOCKK.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDGLOCKK_LOCK() uint32 {
	return volatile.LoadUint32(&o.CFDGLOCKK.Reg) & 0xffff
}

// CANFD_B.CFDGAFLIGNENT: Global AFL Ignore Entry Register
func (o *CANFD_B_Type) SetCFDGAFLIGNENT_IRN(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLIGNENT.Reg, volatile.LoadUint32(&o.CFDGAFLIGNENT.Reg)&^(0x1f)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLIGNENT_IRN() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLIGNENT.Reg) & 0x1f
}

// CANFD_B.CFDGAFLIGNCTR: Global AFL Ignore Control Register
func (o *CANFD_B_Type) SetCFDGAFLIGNCTR_IREN(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLIGNCTR.Reg, volatile.LoadUint32(&o.CFDGAFLIGNCTR.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLIGNCTR_IREN() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLIGNCTR.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLIGNCTR_KEY(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLIGNCTR.Reg, volatile.LoadUint32(&o.CFDGAFLIGNCTR.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLIGNCTR_KEY() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLIGNCTR.Reg) & 0xff00) >> 8
}

// CANFD_B.CFDCDTCT: DMA Transfer Control Register
func (o *CANFD_B_Type) SetCFDCDTCT_RFDMAE0(value uint32) {
	volatile.StoreUint32(&o.CFDCDTCT.Reg, volatile.LoadUint32(&o.CFDCDTCT.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDCDTCT_RFDMAE0() uint32 {
	return volatile.LoadUint32(&o.CFDCDTCT.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDCDTCT_RFDMAE1(value uint32) {
	volatile.StoreUint32(&o.CFDCDTCT.Reg, volatile.LoadUint32(&o.CFDCDTCT.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDCDTCT_RFDMAE1() uint32 {
	return (volatile.LoadUint32(&o.CFDCDTCT.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDCDTCT_CFDMAE(value uint32) {
	volatile.StoreUint32(&o.CFDCDTCT.Reg, volatile.LoadUint32(&o.CFDCDTCT.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCDTCT_CFDMAE() uint32 {
	return (volatile.LoadUint32(&o.CFDCDTCT.Reg) & 0x100) >> 8
}

// CANFD_B.CFDCDTSTS: DMA Transfer Status Register
func (o *CANFD_B_Type) SetCFDCDTSTS_RFDMASTS0(value uint32) {
	volatile.StoreUint32(&o.CFDCDTSTS.Reg, volatile.LoadUint32(&o.CFDCDTSTS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDCDTSTS_RFDMASTS0() uint32 {
	return volatile.LoadUint32(&o.CFDCDTSTS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDCDTSTS_RFDMASTS1(value uint32) {
	volatile.StoreUint32(&o.CFDCDTSTS.Reg, volatile.LoadUint32(&o.CFDCDTSTS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDCDTSTS_RFDMASTS1() uint32 {
	return (volatile.LoadUint32(&o.CFDCDTSTS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDCDTSTS_CFDMASTS(value uint32) {
	volatile.StoreUint32(&o.CFDCDTSTS.Reg, volatile.LoadUint32(&o.CFDCDTSTS.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCDTSTS_CFDMASTS() uint32 {
	return (volatile.LoadUint32(&o.CFDCDTSTS.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGRSTC: Global SW reset Register
func (o *CANFD_B_Type) SetCFDGRSTC_SRST(value uint32) {
	volatile.StoreUint32(&o.CFDGRSTC.Reg, volatile.LoadUint32(&o.CFDGRSTC.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGRSTC_SRST() uint32 {
	return volatile.LoadUint32(&o.CFDGRSTC.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGRSTC_KEY(value uint32) {
	volatile.StoreUint32(&o.CFDGRSTC.Reg, volatile.LoadUint32(&o.CFDGRSTC.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGRSTC_KEY() uint32 {
	return (volatile.LoadUint32(&o.CFDGRSTC.Reg) & 0xff00) >> 8
}

// CANFD_B.CFDC0DCFG: Channel 0 Data Bitrate Configuration Register
func (o *CANFD_B_Type) SetCFDC0DCFG_DBRP(value uint32) {
	volatile.StoreUint32(&o.CFDC0DCFG.Reg, volatile.LoadUint32(&o.CFDC0DCFG.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDC0DCFG_DBRP() uint32 {
	return volatile.LoadUint32(&o.CFDC0DCFG.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDC0DCFG_DTSEG1(value uint32) {
	volatile.StoreUint32(&o.CFDC0DCFG.Reg, volatile.LoadUint32(&o.CFDC0DCFG.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDC0DCFG_DTSEG1() uint32 {
	return (volatile.LoadUint32(&o.CFDC0DCFG.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDC0DCFG_DTSEG2(value uint32) {
	volatile.StoreUint32(&o.CFDC0DCFG.Reg, volatile.LoadUint32(&o.CFDC0DCFG.Reg)&^(0xf0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDC0DCFG_DTSEG2() uint32 {
	return (volatile.LoadUint32(&o.CFDC0DCFG.Reg) & 0xf0000) >> 16
}
func (o *CANFD_B_Type) SetCFDC0DCFG_DSJW(value uint32) {
	volatile.StoreUint32(&o.CFDC0DCFG.Reg, volatile.LoadUint32(&o.CFDC0DCFG.Reg)&^(0xf000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDC0DCFG_DSJW() uint32 {
	return (volatile.LoadUint32(&o.CFDC0DCFG.Reg) & 0xf000000) >> 24
}

// CANFD_B.CFDC0FDCFG: Channel 0 CANFD Configuration Register
func (o *CANFD_B_Type) SetCFDC0FDCFG_EOCCFG(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0x7)|value)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_EOCCFG() uint32 {
	return volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0x7
}
func (o *CANFD_B_Type) SetCFDC0FDCFG_TDCOC(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_TDCOC() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDC0FDCFG_TDCE(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0x200)|value<<9)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_TDCE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0x200) >> 9
}
func (o *CANFD_B_Type) SetCFDC0FDCFG_ESIC(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0x400)|value<<10)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_ESIC() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0x400) >> 10
}
func (o *CANFD_B_Type) SetCFDC0FDCFG_TDCO(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_TDCO() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDC0FDCFG_FDOE(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0x10000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_FDOE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0x10000000) >> 28
}
func (o *CANFD_B_Type) SetCFDC0FDCFG_REFE(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_REFE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDC0FDCFG_CLOE(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCFG.Reg, volatile.LoadUint32(&o.CFDC0FDCFG.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDC0FDCFG_CLOE() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCFG.Reg) & 0x40000000) >> 30
}

// CANFD_B.CFDC0FDCTR: Channel 0 CANFD Control Register
func (o *CANFD_B_Type) SetCFDC0FDCTR_EOCCLR(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCTR.Reg, volatile.LoadUint32(&o.CFDC0FDCTR.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDC0FDCTR_EOCCLR() uint32 {
	return volatile.LoadUint32(&o.CFDC0FDCTR.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDC0FDCTR_SOCCLR(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCTR.Reg, volatile.LoadUint32(&o.CFDC0FDCTR.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDC0FDCTR_SOCCLR() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCTR.Reg) & 0x2) >> 1
}

// CANFD_B.CFDC0FDSTS: Channel 0 CANFD Status Register
func (o *CANFD_B_Type) SetCFDC0FDSTS_TDCR(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDSTS.Reg, volatile.LoadUint32(&o.CFDC0FDSTS.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDC0FDSTS_TDCR() uint32 {
	return volatile.LoadUint32(&o.CFDC0FDSTS.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDC0FDSTS_EOCO(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDSTS.Reg, volatile.LoadUint32(&o.CFDC0FDSTS.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDC0FDSTS_EOCO() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDSTS.Reg) & 0x100) >> 8
}
func (o *CANFD_B_Type) SetCFDC0FDSTS_SOCO(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDSTS.Reg, volatile.LoadUint32(&o.CFDC0FDSTS.Reg)&^(0x200)|value<<9)
}
func (o *CANFD_B_Type) GetCFDC0FDSTS_SOCO() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDSTS.Reg) & 0x200) >> 9
}
func (o *CANFD_B_Type) SetCFDC0FDSTS_TDCVF(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDSTS.Reg, volatile.LoadUint32(&o.CFDC0FDSTS.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDC0FDSTS_TDCVF() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDSTS.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDC0FDSTS_EOC(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDSTS.Reg, volatile.LoadUint32(&o.CFDC0FDSTS.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDC0FDSTS_EOC() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDSTS.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDC0FDSTS_SOC(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDSTS.Reg, volatile.LoadUint32(&o.CFDC0FDSTS.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDC0FDSTS_SOC() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDSTS.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDC0FDCRC: Channel 0 CANFD CRC Register
func (o *CANFD_B_Type) SetCFDC0FDCRC_CRCREG(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCRC.Reg, volatile.LoadUint32(&o.CFDC0FDCRC.Reg)&^(0x1fffff)|value)
}
func (o *CANFD_B_Type) GetCFDC0FDCRC_CRCREG() uint32 {
	return volatile.LoadUint32(&o.CFDC0FDCRC.Reg) & 0x1fffff
}
func (o *CANFD_B_Type) SetCFDC0FDCRC_SCNT(value uint32) {
	volatile.StoreUint32(&o.CFDC0FDCRC.Reg, volatile.LoadUint32(&o.CFDC0FDCRC.Reg)&^(0xf000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDC0FDCRC_SCNT() uint32 {
	return (volatile.LoadUint32(&o.CFDC0FDCRC.Reg) & 0xf000000) >> 24
}

// CANFD_B.CFDGAFLID1: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID1_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID1.Reg, volatile.LoadUint32(&o.CFDGAFLID1.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID1_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID1.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID1_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID1.Reg, volatile.LoadUint32(&o.CFDGAFLID1.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID1_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID1.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID1_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID1.Reg, volatile.LoadUint32(&o.CFDGAFLID1.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID1_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID1.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID1_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID1.Reg, volatile.LoadUint32(&o.CFDGAFLID1.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID1_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID1.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM1: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM1_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM1.Reg, volatile.LoadUint32(&o.CFDGAFLM1.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM1_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM1.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM1_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM1.Reg, volatile.LoadUint32(&o.CFDGAFLM1.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM1_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM1.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM1_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM1.Reg, volatile.LoadUint32(&o.CFDGAFLM1.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM1_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM1.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM1_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM1.Reg, volatile.LoadUint32(&o.CFDGAFLM1.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM1_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM1.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP01: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP01_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP01.Reg, volatile.LoadUint32(&o.CFDGAFLP01.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP01_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP01.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP01_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP01.Reg, volatile.LoadUint32(&o.CFDGAFLP01.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP01_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP01.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP01_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP01.Reg, volatile.LoadUint32(&o.CFDGAFLP01.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP01_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP01.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP01_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP01.Reg, volatile.LoadUint32(&o.CFDGAFLP01.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP01_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP01.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP01_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP01.Reg, volatile.LoadUint32(&o.CFDGAFLP01.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP01_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP01.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP11: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP11_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP11.Reg, volatile.LoadUint32(&o.CFDGAFLP11.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP11_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP11.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP11_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP11.Reg, volatile.LoadUint32(&o.CFDGAFLP11.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP11_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP11.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP11_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP11.Reg, volatile.LoadUint32(&o.CFDGAFLP11.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP11_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP11.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID2: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID2_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID2.Reg, volatile.LoadUint32(&o.CFDGAFLID2.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID2_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID2.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID2_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID2.Reg, volatile.LoadUint32(&o.CFDGAFLID2.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID2_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID2.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID2_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID2.Reg, volatile.LoadUint32(&o.CFDGAFLID2.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID2_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID2.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID2_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID2.Reg, volatile.LoadUint32(&o.CFDGAFLID2.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID2_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID2.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM2: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM2_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM2.Reg, volatile.LoadUint32(&o.CFDGAFLM2.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM2_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM2.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM2_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM2.Reg, volatile.LoadUint32(&o.CFDGAFLM2.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM2_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM2.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM2_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM2.Reg, volatile.LoadUint32(&o.CFDGAFLM2.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM2_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM2.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM2_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM2.Reg, volatile.LoadUint32(&o.CFDGAFLM2.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM2_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM2.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP02: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP02_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP02.Reg, volatile.LoadUint32(&o.CFDGAFLP02.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP02_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP02.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP02_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP02.Reg, volatile.LoadUint32(&o.CFDGAFLP02.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP02_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP02.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP02_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP02.Reg, volatile.LoadUint32(&o.CFDGAFLP02.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP02_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP02.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP02_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP02.Reg, volatile.LoadUint32(&o.CFDGAFLP02.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP02_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP02.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP02_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP02.Reg, volatile.LoadUint32(&o.CFDGAFLP02.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP02_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP02.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP12: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP12_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP12.Reg, volatile.LoadUint32(&o.CFDGAFLP12.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP12_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP12.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP12_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP12.Reg, volatile.LoadUint32(&o.CFDGAFLP12.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP12_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP12.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP12_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP12.Reg, volatile.LoadUint32(&o.CFDGAFLP12.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP12_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP12.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID3: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID3_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID3.Reg, volatile.LoadUint32(&o.CFDGAFLID3.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID3_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID3.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID3_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID3.Reg, volatile.LoadUint32(&o.CFDGAFLID3.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID3_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID3.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID3_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID3.Reg, volatile.LoadUint32(&o.CFDGAFLID3.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID3_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID3.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID3_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID3.Reg, volatile.LoadUint32(&o.CFDGAFLID3.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID3_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID3.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM3: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM3_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM3.Reg, volatile.LoadUint32(&o.CFDGAFLM3.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM3_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM3.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM3_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM3.Reg, volatile.LoadUint32(&o.CFDGAFLM3.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM3_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM3.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM3_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM3.Reg, volatile.LoadUint32(&o.CFDGAFLM3.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM3_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM3.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM3_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM3.Reg, volatile.LoadUint32(&o.CFDGAFLM3.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM3_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM3.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP03: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP03_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP03.Reg, volatile.LoadUint32(&o.CFDGAFLP03.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP03_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP03.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP03_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP03.Reg, volatile.LoadUint32(&o.CFDGAFLP03.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP03_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP03.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP03_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP03.Reg, volatile.LoadUint32(&o.CFDGAFLP03.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP03_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP03.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP03_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP03.Reg, volatile.LoadUint32(&o.CFDGAFLP03.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP03_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP03.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP03_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP03.Reg, volatile.LoadUint32(&o.CFDGAFLP03.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP03_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP03.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP13: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP13_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP13.Reg, volatile.LoadUint32(&o.CFDGAFLP13.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP13_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP13.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP13_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP13.Reg, volatile.LoadUint32(&o.CFDGAFLP13.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP13_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP13.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP13_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP13.Reg, volatile.LoadUint32(&o.CFDGAFLP13.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP13_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP13.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID4: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID4_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID4.Reg, volatile.LoadUint32(&o.CFDGAFLID4.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID4_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID4.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID4_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID4.Reg, volatile.LoadUint32(&o.CFDGAFLID4.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID4_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID4.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID4_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID4.Reg, volatile.LoadUint32(&o.CFDGAFLID4.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID4_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID4.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID4_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID4.Reg, volatile.LoadUint32(&o.CFDGAFLID4.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID4_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID4.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM4: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM4_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM4.Reg, volatile.LoadUint32(&o.CFDGAFLM4.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM4_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM4.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM4_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM4.Reg, volatile.LoadUint32(&o.CFDGAFLM4.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM4_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM4.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM4_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM4.Reg, volatile.LoadUint32(&o.CFDGAFLM4.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM4_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM4.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM4_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM4.Reg, volatile.LoadUint32(&o.CFDGAFLM4.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM4_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM4.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP04: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP04_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP04.Reg, volatile.LoadUint32(&o.CFDGAFLP04.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP04_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP04.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP04_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP04.Reg, volatile.LoadUint32(&o.CFDGAFLP04.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP04_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP04.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP04_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP04.Reg, volatile.LoadUint32(&o.CFDGAFLP04.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP04_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP04.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP04_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP04.Reg, volatile.LoadUint32(&o.CFDGAFLP04.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP04_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP04.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP04_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP04.Reg, volatile.LoadUint32(&o.CFDGAFLP04.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP04_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP04.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP14: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP14_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP14.Reg, volatile.LoadUint32(&o.CFDGAFLP14.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP14_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP14.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP14_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP14.Reg, volatile.LoadUint32(&o.CFDGAFLP14.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP14_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP14.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP14_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP14.Reg, volatile.LoadUint32(&o.CFDGAFLP14.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP14_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP14.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID5: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID5_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID5.Reg, volatile.LoadUint32(&o.CFDGAFLID5.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID5_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID5.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID5_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID5.Reg, volatile.LoadUint32(&o.CFDGAFLID5.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID5_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID5.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID5_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID5.Reg, volatile.LoadUint32(&o.CFDGAFLID5.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID5_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID5.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID5_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID5.Reg, volatile.LoadUint32(&o.CFDGAFLID5.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID5_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID5.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM5: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM5_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM5.Reg, volatile.LoadUint32(&o.CFDGAFLM5.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM5_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM5.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM5_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM5.Reg, volatile.LoadUint32(&o.CFDGAFLM5.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM5_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM5.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM5_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM5.Reg, volatile.LoadUint32(&o.CFDGAFLM5.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM5_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM5.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM5_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM5.Reg, volatile.LoadUint32(&o.CFDGAFLM5.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM5_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM5.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP05: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP05_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP05.Reg, volatile.LoadUint32(&o.CFDGAFLP05.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP05_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP05.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP05_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP05.Reg, volatile.LoadUint32(&o.CFDGAFLP05.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP05_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP05.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP05_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP05.Reg, volatile.LoadUint32(&o.CFDGAFLP05.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP05_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP05.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP05_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP05.Reg, volatile.LoadUint32(&o.CFDGAFLP05.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP05_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP05.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP05_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP05.Reg, volatile.LoadUint32(&o.CFDGAFLP05.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP05_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP05.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP15: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP15_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP15.Reg, volatile.LoadUint32(&o.CFDGAFLP15.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP15_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP15.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP15_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP15.Reg, volatile.LoadUint32(&o.CFDGAFLP15.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP15_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP15.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP15_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP15.Reg, volatile.LoadUint32(&o.CFDGAFLP15.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP15_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP15.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID6: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID6_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID6.Reg, volatile.LoadUint32(&o.CFDGAFLID6.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID6_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID6.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID6_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID6.Reg, volatile.LoadUint32(&o.CFDGAFLID6.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID6_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID6.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID6_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID6.Reg, volatile.LoadUint32(&o.CFDGAFLID6.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID6_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID6.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID6_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID6.Reg, volatile.LoadUint32(&o.CFDGAFLID6.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID6_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID6.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM6: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM6_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM6.Reg, volatile.LoadUint32(&o.CFDGAFLM6.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM6_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM6.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM6_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM6.Reg, volatile.LoadUint32(&o.CFDGAFLM6.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM6_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM6.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM6_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM6.Reg, volatile.LoadUint32(&o.CFDGAFLM6.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM6_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM6.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM6_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM6.Reg, volatile.LoadUint32(&o.CFDGAFLM6.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM6_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM6.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP06: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP06_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP06.Reg, volatile.LoadUint32(&o.CFDGAFLP06.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP06_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP06.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP06_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP06.Reg, volatile.LoadUint32(&o.CFDGAFLP06.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP06_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP06.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP06_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP06.Reg, volatile.LoadUint32(&o.CFDGAFLP06.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP06_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP06.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP06_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP06.Reg, volatile.LoadUint32(&o.CFDGAFLP06.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP06_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP06.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP06_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP06.Reg, volatile.LoadUint32(&o.CFDGAFLP06.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP06_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP06.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP16: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP16_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP16.Reg, volatile.LoadUint32(&o.CFDGAFLP16.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP16_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP16.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP16_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP16.Reg, volatile.LoadUint32(&o.CFDGAFLP16.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP16_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP16.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP16_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP16.Reg, volatile.LoadUint32(&o.CFDGAFLP16.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP16_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP16.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID7: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID7_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID7.Reg, volatile.LoadUint32(&o.CFDGAFLID7.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID7_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID7.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID7_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID7.Reg, volatile.LoadUint32(&o.CFDGAFLID7.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID7_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID7.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID7_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID7.Reg, volatile.LoadUint32(&o.CFDGAFLID7.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID7_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID7.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID7_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID7.Reg, volatile.LoadUint32(&o.CFDGAFLID7.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID7_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID7.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM7: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM7_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM7.Reg, volatile.LoadUint32(&o.CFDGAFLM7.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM7_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM7.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM7_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM7.Reg, volatile.LoadUint32(&o.CFDGAFLM7.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM7_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM7.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM7_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM7.Reg, volatile.LoadUint32(&o.CFDGAFLM7.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM7_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM7.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM7_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM7.Reg, volatile.LoadUint32(&o.CFDGAFLM7.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM7_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM7.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP07: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP07_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP07.Reg, volatile.LoadUint32(&o.CFDGAFLP07.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP07_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP07.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP07_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP07.Reg, volatile.LoadUint32(&o.CFDGAFLP07.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP07_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP07.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP07_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP07.Reg, volatile.LoadUint32(&o.CFDGAFLP07.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP07_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP07.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP07_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP07.Reg, volatile.LoadUint32(&o.CFDGAFLP07.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP07_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP07.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP07_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP07.Reg, volatile.LoadUint32(&o.CFDGAFLP07.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP07_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP07.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP17: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP17_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP17.Reg, volatile.LoadUint32(&o.CFDGAFLP17.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP17_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP17.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP17_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP17.Reg, volatile.LoadUint32(&o.CFDGAFLP17.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP17_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP17.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP17_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP17.Reg, volatile.LoadUint32(&o.CFDGAFLP17.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP17_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP17.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID8: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID8_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID8.Reg, volatile.LoadUint32(&o.CFDGAFLID8.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID8_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID8.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID8_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID8.Reg, volatile.LoadUint32(&o.CFDGAFLID8.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID8_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID8.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID8_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID8.Reg, volatile.LoadUint32(&o.CFDGAFLID8.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID8_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID8.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID8_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID8.Reg, volatile.LoadUint32(&o.CFDGAFLID8.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID8_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID8.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM8: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM8_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM8.Reg, volatile.LoadUint32(&o.CFDGAFLM8.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM8_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM8.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM8_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM8.Reg, volatile.LoadUint32(&o.CFDGAFLM8.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM8_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM8.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM8_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM8.Reg, volatile.LoadUint32(&o.CFDGAFLM8.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM8_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM8.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM8_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM8.Reg, volatile.LoadUint32(&o.CFDGAFLM8.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM8_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM8.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP08: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP08_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP08.Reg, volatile.LoadUint32(&o.CFDGAFLP08.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP08_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP08.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP08_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP08.Reg, volatile.LoadUint32(&o.CFDGAFLP08.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP08_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP08.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP08_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP08.Reg, volatile.LoadUint32(&o.CFDGAFLP08.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP08_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP08.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP08_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP08.Reg, volatile.LoadUint32(&o.CFDGAFLP08.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP08_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP08.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP08_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP08.Reg, volatile.LoadUint32(&o.CFDGAFLP08.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP08_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP08.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP18: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP18_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP18.Reg, volatile.LoadUint32(&o.CFDGAFLP18.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP18_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP18.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP18_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP18.Reg, volatile.LoadUint32(&o.CFDGAFLP18.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP18_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP18.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP18_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP18.Reg, volatile.LoadUint32(&o.CFDGAFLP18.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP18_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP18.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID9: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID9_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID9.Reg, volatile.LoadUint32(&o.CFDGAFLID9.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID9_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID9.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID9_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID9.Reg, volatile.LoadUint32(&o.CFDGAFLID9.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID9_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID9.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID9_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID9.Reg, volatile.LoadUint32(&o.CFDGAFLID9.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID9_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID9.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID9_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID9.Reg, volatile.LoadUint32(&o.CFDGAFLID9.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID9_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID9.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM9: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM9_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM9.Reg, volatile.LoadUint32(&o.CFDGAFLM9.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM9_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM9.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM9_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM9.Reg, volatile.LoadUint32(&o.CFDGAFLM9.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM9_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM9.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM9_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM9.Reg, volatile.LoadUint32(&o.CFDGAFLM9.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM9_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM9.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM9_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM9.Reg, volatile.LoadUint32(&o.CFDGAFLM9.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM9_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM9.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP09: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP09_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP09.Reg, volatile.LoadUint32(&o.CFDGAFLP09.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP09_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP09.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP09_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP09.Reg, volatile.LoadUint32(&o.CFDGAFLP09.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP09_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP09.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP09_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP09.Reg, volatile.LoadUint32(&o.CFDGAFLP09.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP09_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP09.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP09_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP09.Reg, volatile.LoadUint32(&o.CFDGAFLP09.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP09_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP09.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP09_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP09.Reg, volatile.LoadUint32(&o.CFDGAFLP09.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP09_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP09.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP19: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP19_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP19.Reg, volatile.LoadUint32(&o.CFDGAFLP19.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP19_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP19.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP19_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP19.Reg, volatile.LoadUint32(&o.CFDGAFLP19.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP19_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP19.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP19_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP19.Reg, volatile.LoadUint32(&o.CFDGAFLP19.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP19_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP19.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID10: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID10_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID10.Reg, volatile.LoadUint32(&o.CFDGAFLID10.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID10_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID10.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID10_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID10.Reg, volatile.LoadUint32(&o.CFDGAFLID10.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID10_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID10.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID10_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID10.Reg, volatile.LoadUint32(&o.CFDGAFLID10.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID10_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID10.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID10_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID10.Reg, volatile.LoadUint32(&o.CFDGAFLID10.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID10_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID10.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM10: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM10_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM10.Reg, volatile.LoadUint32(&o.CFDGAFLM10.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM10_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM10.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM10_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM10.Reg, volatile.LoadUint32(&o.CFDGAFLM10.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM10_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM10.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM10_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM10.Reg, volatile.LoadUint32(&o.CFDGAFLM10.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM10_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM10.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM10_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM10.Reg, volatile.LoadUint32(&o.CFDGAFLM10.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM10_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM10.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP010: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP010_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP010.Reg, volatile.LoadUint32(&o.CFDGAFLP010.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP010_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP010.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP010_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP010.Reg, volatile.LoadUint32(&o.CFDGAFLP010.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP010_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP010.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP010_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP010.Reg, volatile.LoadUint32(&o.CFDGAFLP010.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP010_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP010.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP010_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP010.Reg, volatile.LoadUint32(&o.CFDGAFLP010.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP010_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP010.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP010_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP010.Reg, volatile.LoadUint32(&o.CFDGAFLP010.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP010_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP010.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP110: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP110_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP110.Reg, volatile.LoadUint32(&o.CFDGAFLP110.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP110_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP110.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP110_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP110.Reg, volatile.LoadUint32(&o.CFDGAFLP110.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP110_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP110.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP110_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP110.Reg, volatile.LoadUint32(&o.CFDGAFLP110.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP110_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP110.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID11: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID11_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID11.Reg, volatile.LoadUint32(&o.CFDGAFLID11.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID11_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID11.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID11_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID11.Reg, volatile.LoadUint32(&o.CFDGAFLID11.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID11_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID11.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID11_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID11.Reg, volatile.LoadUint32(&o.CFDGAFLID11.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID11_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID11.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID11_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID11.Reg, volatile.LoadUint32(&o.CFDGAFLID11.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID11_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID11.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM11: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM11_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM11.Reg, volatile.LoadUint32(&o.CFDGAFLM11.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM11_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM11.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM11_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM11.Reg, volatile.LoadUint32(&o.CFDGAFLM11.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM11_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM11.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM11_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM11.Reg, volatile.LoadUint32(&o.CFDGAFLM11.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM11_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM11.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM11_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM11.Reg, volatile.LoadUint32(&o.CFDGAFLM11.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM11_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM11.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP011: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP011_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP011.Reg, volatile.LoadUint32(&o.CFDGAFLP011.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP011_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP011.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP011_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP011.Reg, volatile.LoadUint32(&o.CFDGAFLP011.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP011_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP011.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP011_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP011.Reg, volatile.LoadUint32(&o.CFDGAFLP011.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP011_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP011.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP011_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP011.Reg, volatile.LoadUint32(&o.CFDGAFLP011.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP011_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP011.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP011_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP011.Reg, volatile.LoadUint32(&o.CFDGAFLP011.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP011_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP011.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP111: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP111_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP111.Reg, volatile.LoadUint32(&o.CFDGAFLP111.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP111_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP111.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP111_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP111.Reg, volatile.LoadUint32(&o.CFDGAFLP111.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP111_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP111.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP111_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP111.Reg, volatile.LoadUint32(&o.CFDGAFLP111.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP111_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP111.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID12: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID12_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID12.Reg, volatile.LoadUint32(&o.CFDGAFLID12.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID12_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID12.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID12_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID12.Reg, volatile.LoadUint32(&o.CFDGAFLID12.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID12_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID12.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID12_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID12.Reg, volatile.LoadUint32(&o.CFDGAFLID12.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID12_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID12.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID12_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID12.Reg, volatile.LoadUint32(&o.CFDGAFLID12.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID12_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID12.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM12: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM12_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM12.Reg, volatile.LoadUint32(&o.CFDGAFLM12.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM12_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM12.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM12_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM12.Reg, volatile.LoadUint32(&o.CFDGAFLM12.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM12_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM12.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM12_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM12.Reg, volatile.LoadUint32(&o.CFDGAFLM12.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM12_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM12.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM12_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM12.Reg, volatile.LoadUint32(&o.CFDGAFLM12.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM12_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM12.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP012: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP012_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP012.Reg, volatile.LoadUint32(&o.CFDGAFLP012.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP012_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP012.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP012_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP012.Reg, volatile.LoadUint32(&o.CFDGAFLP012.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP012_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP012.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP012_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP012.Reg, volatile.LoadUint32(&o.CFDGAFLP012.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP012_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP012.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP012_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP012.Reg, volatile.LoadUint32(&o.CFDGAFLP012.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP012_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP012.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP012_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP012.Reg, volatile.LoadUint32(&o.CFDGAFLP012.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP012_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP012.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP112: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP112_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP112.Reg, volatile.LoadUint32(&o.CFDGAFLP112.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP112_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP112.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP112_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP112.Reg, volatile.LoadUint32(&o.CFDGAFLP112.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP112_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP112.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP112_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP112.Reg, volatile.LoadUint32(&o.CFDGAFLP112.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP112_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP112.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID13: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID13_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID13.Reg, volatile.LoadUint32(&o.CFDGAFLID13.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID13_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID13.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID13_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID13.Reg, volatile.LoadUint32(&o.CFDGAFLID13.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID13_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID13.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID13_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID13.Reg, volatile.LoadUint32(&o.CFDGAFLID13.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID13_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID13.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID13_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID13.Reg, volatile.LoadUint32(&o.CFDGAFLID13.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID13_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID13.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM13: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM13_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM13.Reg, volatile.LoadUint32(&o.CFDGAFLM13.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM13_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM13.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM13_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM13.Reg, volatile.LoadUint32(&o.CFDGAFLM13.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM13_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM13.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM13_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM13.Reg, volatile.LoadUint32(&o.CFDGAFLM13.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM13_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM13.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM13_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM13.Reg, volatile.LoadUint32(&o.CFDGAFLM13.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM13_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM13.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP013: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP013_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP013.Reg, volatile.LoadUint32(&o.CFDGAFLP013.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP013_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP013.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP013_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP013.Reg, volatile.LoadUint32(&o.CFDGAFLP013.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP013_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP013.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP013_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP013.Reg, volatile.LoadUint32(&o.CFDGAFLP013.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP013_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP013.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP013_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP013.Reg, volatile.LoadUint32(&o.CFDGAFLP013.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP013_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP013.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP013_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP013.Reg, volatile.LoadUint32(&o.CFDGAFLP013.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP013_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP013.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP113: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP113_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP113.Reg, volatile.LoadUint32(&o.CFDGAFLP113.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP113_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP113.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP113_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP113.Reg, volatile.LoadUint32(&o.CFDGAFLP113.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP113_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP113.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP113_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP113.Reg, volatile.LoadUint32(&o.CFDGAFLP113.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP113_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP113.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID14: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID14_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID14.Reg, volatile.LoadUint32(&o.CFDGAFLID14.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID14_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID14.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID14_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID14.Reg, volatile.LoadUint32(&o.CFDGAFLID14.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID14_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID14.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID14_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID14.Reg, volatile.LoadUint32(&o.CFDGAFLID14.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID14_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID14.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID14_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID14.Reg, volatile.LoadUint32(&o.CFDGAFLID14.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID14_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID14.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM14: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM14_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM14.Reg, volatile.LoadUint32(&o.CFDGAFLM14.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM14_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM14.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM14_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM14.Reg, volatile.LoadUint32(&o.CFDGAFLM14.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM14_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM14.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM14_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM14.Reg, volatile.LoadUint32(&o.CFDGAFLM14.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM14_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM14.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM14_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM14.Reg, volatile.LoadUint32(&o.CFDGAFLM14.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM14_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM14.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP014: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP014_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP014.Reg, volatile.LoadUint32(&o.CFDGAFLP014.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP014_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP014.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP014_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP014.Reg, volatile.LoadUint32(&o.CFDGAFLP014.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP014_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP014.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP014_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP014.Reg, volatile.LoadUint32(&o.CFDGAFLP014.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP014_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP014.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP014_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP014.Reg, volatile.LoadUint32(&o.CFDGAFLP014.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP014_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP014.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP014_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP014.Reg, volatile.LoadUint32(&o.CFDGAFLP014.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP014_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP014.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP114: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP114_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP114.Reg, volatile.LoadUint32(&o.CFDGAFLP114.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP114_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP114.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP114_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP114.Reg, volatile.LoadUint32(&o.CFDGAFLP114.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP114_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP114.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP114_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP114.Reg, volatile.LoadUint32(&o.CFDGAFLP114.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP114_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP114.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID15: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID15_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID15.Reg, volatile.LoadUint32(&o.CFDGAFLID15.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID15_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID15.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID15_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID15.Reg, volatile.LoadUint32(&o.CFDGAFLID15.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID15_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID15.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID15_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID15.Reg, volatile.LoadUint32(&o.CFDGAFLID15.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID15_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID15.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID15_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID15.Reg, volatile.LoadUint32(&o.CFDGAFLID15.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID15_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID15.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM15: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM15_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM15.Reg, volatile.LoadUint32(&o.CFDGAFLM15.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM15_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM15.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM15_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM15.Reg, volatile.LoadUint32(&o.CFDGAFLM15.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM15_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM15.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM15_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM15.Reg, volatile.LoadUint32(&o.CFDGAFLM15.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM15_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM15.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM15_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM15.Reg, volatile.LoadUint32(&o.CFDGAFLM15.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM15_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM15.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP015: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP015_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP015.Reg, volatile.LoadUint32(&o.CFDGAFLP015.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP015_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP015.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP015_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP015.Reg, volatile.LoadUint32(&o.CFDGAFLP015.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP015_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP015.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP015_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP015.Reg, volatile.LoadUint32(&o.CFDGAFLP015.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP015_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP015.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP015_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP015.Reg, volatile.LoadUint32(&o.CFDGAFLP015.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP015_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP015.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP015_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP015.Reg, volatile.LoadUint32(&o.CFDGAFLP015.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP015_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP015.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP115: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP115_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP115.Reg, volatile.LoadUint32(&o.CFDGAFLP115.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP115_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP115.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP115_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP115.Reg, volatile.LoadUint32(&o.CFDGAFLP115.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP115_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP115.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP115_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP115.Reg, volatile.LoadUint32(&o.CFDGAFLP115.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP115_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP115.Reg) & 0x100) >> 8
}

// CANFD_B.CFDGAFLID16: Global Acceptance Filter List ID Registers
func (o *CANFD_B_Type) SetCFDGAFLID16_GAFLID(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID16.Reg, volatile.LoadUint32(&o.CFDGAFLID16.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLID16_GAFLID() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLID16.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLID16_GAFLLB(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID16.Reg, volatile.LoadUint32(&o.CFDGAFLID16.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLID16_GAFLLB() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID16.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLID16_GAFLRTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID16.Reg, volatile.LoadUint32(&o.CFDGAFLID16.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLID16_GAFLRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID16.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLID16_GAFLIDE(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLID16.Reg, volatile.LoadUint32(&o.CFDGAFLID16.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLID16_GAFLIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLID16.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLM16: Global Acceptance Filter List Mask Registers
func (o *CANFD_B_Type) SetCFDGAFLM16_GAFLIDM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM16.Reg, volatile.LoadUint32(&o.CFDGAFLM16.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLM16_GAFLIDM() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLM16.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDGAFLM16_GAFLIFL1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM16.Reg, volatile.LoadUint32(&o.CFDGAFLM16.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDGAFLM16_GAFLIFL1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM16.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDGAFLM16_GAFLRTRM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM16.Reg, volatile.LoadUint32(&o.CFDGAFLM16.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDGAFLM16_GAFLRTRM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM16.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDGAFLM16_GAFLIDEM(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLM16.Reg, volatile.LoadUint32(&o.CFDGAFLM16.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDGAFLM16_GAFLIDEM() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLM16.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDGAFLP016: Global Acceptance Filter List Pointer 0 Registers
func (o *CANFD_B_Type) SetCFDGAFLP016_GAFLDLC(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP016.Reg, volatile.LoadUint32(&o.CFDGAFLP016.Reg)&^(0xf)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP016_GAFLDLC() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP016.Reg) & 0xf
}
func (o *CANFD_B_Type) SetCFDGAFLP016_GAFLIFL0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP016.Reg, volatile.LoadUint32(&o.CFDGAFLP016.Reg)&^(0x80)|value<<7)
}
func (o *CANFD_B_Type) GetCFDGAFLP016_GAFLIFL0() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP016.Reg) & 0x80) >> 7
}
func (o *CANFD_B_Type) SetCFDGAFLP016_GAFLRMDP(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP016.Reg, volatile.LoadUint32(&o.CFDGAFLP016.Reg)&^(0x1f00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP016_GAFLRMDP() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP016.Reg) & 0x1f00) >> 8
}
func (o *CANFD_B_Type) SetCFDGAFLP016_GAFLRMV(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP016.Reg, volatile.LoadUint32(&o.CFDGAFLP016.Reg)&^(0x8000)|value<<15)
}
func (o *CANFD_B_Type) GetCFDGAFLP016_GAFLRMV() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP016.Reg) & 0x8000) >> 15
}
func (o *CANFD_B_Type) SetCFDGAFLP016_GAFLPTR(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP016.Reg, volatile.LoadUint32(&o.CFDGAFLP016.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDGAFLP016_GAFLPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP016.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDGAFLP116: Global Acceptance Filter List Pointer 1 Registers
func (o *CANFD_B_Type) SetCFDGAFLP116_GAFLFDP0(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP116.Reg, volatile.LoadUint32(&o.CFDGAFLP116.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDGAFLP116_GAFLFDP0() uint32 {
	return volatile.LoadUint32(&o.CFDGAFLP116.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDGAFLP116_GAFLFDP1(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP116.Reg, volatile.LoadUint32(&o.CFDGAFLP116.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDGAFLP116_GAFLFDP1() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP116.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDGAFLP116_GAFLFDP8(value uint32) {
	volatile.StoreUint32(&o.CFDGAFLP116.Reg, volatile.LoadUint32(&o.CFDGAFLP116.Reg)&^(0x100)|value<<8)
}
func (o *CANFD_B_Type) GetCFDGAFLP116_GAFLFDP8() uint32 {
	return (volatile.LoadUint32(&o.CFDGAFLP116.Reg) & 0x100) >> 8
}

// CANFD_B.CFDRPGACC0: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC0(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC0.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC0() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC0.Reg)
}

// CANFD_B.CFDRPGACC1: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC1(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC1.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC1() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC1.Reg)
}

// CANFD_B.CFDRPGACC2: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC2(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC2.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC2() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC2.Reg)
}

// CANFD_B.CFDRPGACC3: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC3(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC3.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC3() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC3.Reg)
}

// CANFD_B.CFDRPGACC4: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC4(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC4.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC4() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC4.Reg)
}

// CANFD_B.CFDRPGACC5: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC5(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC5.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC5() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC5.Reg)
}

// CANFD_B.CFDRPGACC6: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC6(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC6.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC6() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC6.Reg)
}

// CANFD_B.CFDRPGACC7: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC7(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC7.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC7() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC7.Reg)
}

// CANFD_B.CFDRPGACC8: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC8(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC8.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC8() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC8.Reg)
}

// CANFD_B.CFDRPGACC9: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC9(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC9.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC9() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC9.Reg)
}

// CANFD_B.CFDRPGACC10: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC10(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC10.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC10() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC10.Reg)
}

// CANFD_B.CFDRPGACC11: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC11(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC11.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC11() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC11.Reg)
}

// CANFD_B.CFDRPGACC12: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC12(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC12.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC12() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC12.Reg)
}

// CANFD_B.CFDRPGACC13: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC13(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC13.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC13() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC13.Reg)
}

// CANFD_B.CFDRPGACC14: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC14(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC14.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC14() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC14.Reg)
}

// CANFD_B.CFDRPGACC15: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC15(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC15.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC15() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC15.Reg)
}

// CANFD_B.CFDRPGACC16: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC16(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC16.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC16() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC16.Reg)
}

// CANFD_B.CFDRPGACC17: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC17(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC17.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC17() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC17.Reg)
}

// CANFD_B.CFDRPGACC18: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC18(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC18.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC18() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC18.Reg)
}

// CANFD_B.CFDRPGACC19: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC19(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC19.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC19() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC19.Reg)
}

// CANFD_B.CFDRPGACC20: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC20(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC20.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC20() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC20.Reg)
}

// CANFD_B.CFDRPGACC21: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC21(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC21.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC21() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC21.Reg)
}

// CANFD_B.CFDRPGACC22: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC22(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC22.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC22() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC22.Reg)
}

// CANFD_B.CFDRPGACC23: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC23(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC23.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC23() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC23.Reg)
}

// CANFD_B.CFDRPGACC24: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC24(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC24.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC24() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC24.Reg)
}

// CANFD_B.CFDRPGACC25: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC25(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC25.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC25() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC25.Reg)
}

// CANFD_B.CFDRPGACC26: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC26(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC26.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC26() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC26.Reg)
}

// CANFD_B.CFDRPGACC27: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC27(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC27.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC27() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC27.Reg)
}

// CANFD_B.CFDRPGACC28: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC28(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC28.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC28() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC28.Reg)
}

// CANFD_B.CFDRPGACC29: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC29(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC29.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC29() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC29.Reg)
}

// CANFD_B.CFDRPGACC30: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC30(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC30.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC30() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC30.Reg)
}

// CANFD_B.CFDRPGACC31: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC31(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC31.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC31() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC31.Reg)
}

// CANFD_B.CFDRPGACC32: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC32(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC32.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC32() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC32.Reg)
}

// CANFD_B.CFDRPGACC33: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC33(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC33.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC33() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC33.Reg)
}

// CANFD_B.CFDRPGACC34: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC34(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC34.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC34() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC34.Reg)
}

// CANFD_B.CFDRPGACC35: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC35(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC35.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC35() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC35.Reg)
}

// CANFD_B.CFDRPGACC36: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC36(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC36.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC36() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC36.Reg)
}

// CANFD_B.CFDRPGACC37: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC37(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC37.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC37() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC37.Reg)
}

// CANFD_B.CFDRPGACC38: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC38(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC38.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC38() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC38.Reg)
}

// CANFD_B.CFDRPGACC39: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC39(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC39.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC39() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC39.Reg)
}

// CANFD_B.CFDRPGACC40: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC40(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC40.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC40() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC40.Reg)
}

// CANFD_B.CFDRPGACC41: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC41(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC41.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC41() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC41.Reg)
}

// CANFD_B.CFDRPGACC42: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC42(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC42.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC42() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC42.Reg)
}

// CANFD_B.CFDRPGACC43: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC43(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC43.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC43() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC43.Reg)
}

// CANFD_B.CFDRPGACC44: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC44(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC44.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC44() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC44.Reg)
}

// CANFD_B.CFDRPGACC45: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC45(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC45.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC45() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC45.Reg)
}

// CANFD_B.CFDRPGACC46: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC46(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC46.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC46() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC46.Reg)
}

// CANFD_B.CFDRPGACC47: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC47(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC47.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC47() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC47.Reg)
}

// CANFD_B.CFDRPGACC48: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC48(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC48.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC48() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC48.Reg)
}

// CANFD_B.CFDRPGACC49: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC49(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC49.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC49() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC49.Reg)
}

// CANFD_B.CFDRPGACC50: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC50(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC50.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC50() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC50.Reg)
}

// CANFD_B.CFDRPGACC51: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC51(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC51.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC51() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC51.Reg)
}

// CANFD_B.CFDRPGACC52: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC52(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC52.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC52() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC52.Reg)
}

// CANFD_B.CFDRPGACC53: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC53(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC53.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC53() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC53.Reg)
}

// CANFD_B.CFDRPGACC54: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC54(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC54.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC54() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC54.Reg)
}

// CANFD_B.CFDRPGACC55: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC55(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC55.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC55() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC55.Reg)
}

// CANFD_B.CFDRPGACC56: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC56(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC56.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC56() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC56.Reg)
}

// CANFD_B.CFDRPGACC57: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC57(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC57.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC57() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC57.Reg)
}

// CANFD_B.CFDRPGACC58: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC58(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC58.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC58() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC58.Reg)
}

// CANFD_B.CFDRPGACC59: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC59(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC59.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC59() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC59.Reg)
}

// CANFD_B.CFDRPGACC60: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC60(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC60.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC60() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC60.Reg)
}

// CANFD_B.CFDRPGACC61: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC61(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC61.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC61() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC61.Reg)
}

// CANFD_B.CFDRPGACC62: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC62(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC62.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC62() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC62.Reg)
}

// CANFD_B.CFDRPGACC63: RAM Test Page Access Registers %s
func (o *CANFD_B_Type) SetCFDRPGACC63(value uint32) {
	volatile.StoreUint32(&o.CFDRPGACC63.Reg, value)
}
func (o *CANFD_B_Type) GetCFDRPGACC63() uint32 {
	return volatile.LoadUint32(&o.CFDRPGACC63.Reg)
}

// CANFD_B.CFDRFID0: RX FIFO Access ID Register %s
func (o *CANFD_B_Type) SetCFDRFID0_RFID(value uint32) {
	volatile.StoreUint32(&o.CFDRFID0.Reg, volatile.LoadUint32(&o.CFDRFID0.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRFID0_RFID() uint32 {
	return volatile.LoadUint32(&o.CFDRFID0.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRFID0_RFRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRFID0.Reg, volatile.LoadUint32(&o.CFDRFID0.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRFID0_RFRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRFID0.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRFID0_RFIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRFID0.Reg, volatile.LoadUint32(&o.CFDRFID0.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRFID0_RFIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRFID0.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRFPTR0: RX FIFO Access Pointer Register %s
func (o *CANFD_B_Type) SetCFDRFPTR0_RFTS(value uint32) {
	volatile.StoreUint32(&o.CFDRFPTR0.Reg, volatile.LoadUint32(&o.CFDRFPTR0.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRFPTR0_RFTS() uint32 {
	return volatile.LoadUint32(&o.CFDRFPTR0.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRFPTR0_RFDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRFPTR0.Reg, volatile.LoadUint32(&o.CFDRFPTR0.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRFPTR0_RFDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRFPTR0.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRFFDSTS0: RX FIFO Access CANFD Status Register %s
func (o *CANFD_B_Type) SetCFDRFFDSTS0_RFESI(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS0.Reg, volatile.LoadUint32(&o.CFDRFFDSTS0.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS0_RFESI() uint32 {
	return volatile.LoadUint32(&o.CFDRFFDSTS0.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRFFDSTS0_RFBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS0.Reg, volatile.LoadUint32(&o.CFDRFFDSTS0.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS0_RFBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS0.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRFFDSTS0_RFFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS0.Reg, volatile.LoadUint32(&o.CFDRFFDSTS0.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS0_RFFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS0.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRFFDSTS0_RFIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS0.Reg, volatile.LoadUint32(&o.CFDRFFDSTS0.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS0_RFIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS0.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRFFDSTS0_CFDRFPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS0.Reg, volatile.LoadUint32(&o.CFDRFFDSTS0.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS0_CFDRFPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS0.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRFDF0_0: RX FIFO Access Data Field 0 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_0_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_0.Reg, volatile.LoadUint32(&o.CFDRFDF0_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_0_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_0_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_0.Reg, volatile.LoadUint32(&o.CFDRFDF0_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_0_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_0_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_0.Reg, volatile.LoadUint32(&o.CFDRFDF0_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_0_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_0_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_0.Reg, volatile.LoadUint32(&o.CFDRFDF0_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_0_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_1: RX FIFO Access Data Field 1 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_1_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_1.Reg, volatile.LoadUint32(&o.CFDRFDF0_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_1_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_1_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_1.Reg, volatile.LoadUint32(&o.CFDRFDF0_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_1_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_1_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_1.Reg, volatile.LoadUint32(&o.CFDRFDF0_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_1_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_1_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_1.Reg, volatile.LoadUint32(&o.CFDRFDF0_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_1_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_2: RX FIFO Access Data Field 2 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_2_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_2.Reg, volatile.LoadUint32(&o.CFDRFDF0_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_2_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_2_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_2.Reg, volatile.LoadUint32(&o.CFDRFDF0_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_2_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_2_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_2.Reg, volatile.LoadUint32(&o.CFDRFDF0_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_2_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_2_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_2.Reg, volatile.LoadUint32(&o.CFDRFDF0_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_2_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_3: RX FIFO Access Data Field 3 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_3_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_3.Reg, volatile.LoadUint32(&o.CFDRFDF0_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_3_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_3_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_3.Reg, volatile.LoadUint32(&o.CFDRFDF0_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_3_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_3_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_3.Reg, volatile.LoadUint32(&o.CFDRFDF0_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_3_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_3_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_3.Reg, volatile.LoadUint32(&o.CFDRFDF0_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_3_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_4: RX FIFO Access Data Field 4 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_4_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_4.Reg, volatile.LoadUint32(&o.CFDRFDF0_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_4_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_4_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_4.Reg, volatile.LoadUint32(&o.CFDRFDF0_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_4_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_4_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_4.Reg, volatile.LoadUint32(&o.CFDRFDF0_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_4_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_4_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_4.Reg, volatile.LoadUint32(&o.CFDRFDF0_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_4_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_5: RX FIFO Access Data Field 5 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_5_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_5.Reg, volatile.LoadUint32(&o.CFDRFDF0_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_5_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_5_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_5.Reg, volatile.LoadUint32(&o.CFDRFDF0_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_5_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_5_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_5.Reg, volatile.LoadUint32(&o.CFDRFDF0_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_5_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_5_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_5.Reg, volatile.LoadUint32(&o.CFDRFDF0_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_5_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_6: RX FIFO Access Data Field 6 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_6_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_6.Reg, volatile.LoadUint32(&o.CFDRFDF0_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_6_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_6_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_6.Reg, volatile.LoadUint32(&o.CFDRFDF0_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_6_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_6_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_6.Reg, volatile.LoadUint32(&o.CFDRFDF0_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_6_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_6_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_6.Reg, volatile.LoadUint32(&o.CFDRFDF0_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_6_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_7: RX FIFO Access Data Field 7 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_7_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_7.Reg, volatile.LoadUint32(&o.CFDRFDF0_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_7_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_7_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_7.Reg, volatile.LoadUint32(&o.CFDRFDF0_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_7_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_7_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_7.Reg, volatile.LoadUint32(&o.CFDRFDF0_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_7_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_7_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_7.Reg, volatile.LoadUint32(&o.CFDRFDF0_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_7_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_8: RX FIFO Access Data Field 8 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_8_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_8.Reg, volatile.LoadUint32(&o.CFDRFDF0_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_8_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_8_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_8.Reg, volatile.LoadUint32(&o.CFDRFDF0_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_8_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_8_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_8.Reg, volatile.LoadUint32(&o.CFDRFDF0_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_8_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_8_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_8.Reg, volatile.LoadUint32(&o.CFDRFDF0_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_8_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_9: RX FIFO Access Data Field 9 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_9_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_9.Reg, volatile.LoadUint32(&o.CFDRFDF0_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_9_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_9_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_9.Reg, volatile.LoadUint32(&o.CFDRFDF0_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_9_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_9_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_9.Reg, volatile.LoadUint32(&o.CFDRFDF0_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_9_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_9_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_9.Reg, volatile.LoadUint32(&o.CFDRFDF0_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_9_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_10: RX FIFO Access Data Field 10 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_10_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_10.Reg, volatile.LoadUint32(&o.CFDRFDF0_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_10_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_10_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_10.Reg, volatile.LoadUint32(&o.CFDRFDF0_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_10_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_10_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_10.Reg, volatile.LoadUint32(&o.CFDRFDF0_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_10_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_10_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_10.Reg, volatile.LoadUint32(&o.CFDRFDF0_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_10_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_11: RX FIFO Access Data Field 11 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_11_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_11.Reg, volatile.LoadUint32(&o.CFDRFDF0_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_11_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_11_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_11.Reg, volatile.LoadUint32(&o.CFDRFDF0_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_11_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_11_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_11.Reg, volatile.LoadUint32(&o.CFDRFDF0_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_11_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_11_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_11.Reg, volatile.LoadUint32(&o.CFDRFDF0_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_11_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_12: RX FIFO Access Data Field 12 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_12_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_12.Reg, volatile.LoadUint32(&o.CFDRFDF0_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_12_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_12_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_12.Reg, volatile.LoadUint32(&o.CFDRFDF0_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_12_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_12_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_12.Reg, volatile.LoadUint32(&o.CFDRFDF0_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_12_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_12_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_12.Reg, volatile.LoadUint32(&o.CFDRFDF0_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_12_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_13: RX FIFO Access Data Field 13 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_13_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_13.Reg, volatile.LoadUint32(&o.CFDRFDF0_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_13_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_13_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_13.Reg, volatile.LoadUint32(&o.CFDRFDF0_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_13_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_13_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_13.Reg, volatile.LoadUint32(&o.CFDRFDF0_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_13_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_13_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_13.Reg, volatile.LoadUint32(&o.CFDRFDF0_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_13_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_14: RX FIFO Access Data Field 14 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_14_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_14.Reg, volatile.LoadUint32(&o.CFDRFDF0_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_14_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_14_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_14.Reg, volatile.LoadUint32(&o.CFDRFDF0_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_14_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_14_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_14.Reg, volatile.LoadUint32(&o.CFDRFDF0_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_14_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_14_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_14.Reg, volatile.LoadUint32(&o.CFDRFDF0_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_14_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF0_15: RX FIFO Access Data Field 15 Register %s
func (o *CANFD_B_Type) SetCFDRFDF0_15_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_15.Reg, volatile.LoadUint32(&o.CFDRFDF0_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF0_15_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF0_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF0_15_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_15.Reg, volatile.LoadUint32(&o.CFDRFDF0_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF0_15_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF0_15_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_15.Reg, volatile.LoadUint32(&o.CFDRFDF0_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF0_15_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF0_15_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF0_15.Reg, volatile.LoadUint32(&o.CFDRFDF0_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF0_15_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF0_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFID1: RX FIFO Access ID Register %s
func (o *CANFD_B_Type) SetCFDRFID1_RFID(value uint32) {
	volatile.StoreUint32(&o.CFDRFID1.Reg, volatile.LoadUint32(&o.CFDRFID1.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRFID1_RFID() uint32 {
	return volatile.LoadUint32(&o.CFDRFID1.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRFID1_RFRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRFID1.Reg, volatile.LoadUint32(&o.CFDRFID1.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRFID1_RFRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRFID1.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRFID1_RFIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRFID1.Reg, volatile.LoadUint32(&o.CFDRFID1.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRFID1_RFIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRFID1.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRFPTR1: RX FIFO Access Pointer Register %s
func (o *CANFD_B_Type) SetCFDRFPTR1_RFTS(value uint32) {
	volatile.StoreUint32(&o.CFDRFPTR1.Reg, volatile.LoadUint32(&o.CFDRFPTR1.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRFPTR1_RFTS() uint32 {
	return volatile.LoadUint32(&o.CFDRFPTR1.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRFPTR1_RFDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRFPTR1.Reg, volatile.LoadUint32(&o.CFDRFPTR1.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRFPTR1_RFDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRFPTR1.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRFFDSTS1: RX FIFO Access CANFD Status Register %s
func (o *CANFD_B_Type) SetCFDRFFDSTS1_RFESI(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS1.Reg, volatile.LoadUint32(&o.CFDRFFDSTS1.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS1_RFESI() uint32 {
	return volatile.LoadUint32(&o.CFDRFFDSTS1.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRFFDSTS1_RFBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS1.Reg, volatile.LoadUint32(&o.CFDRFFDSTS1.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS1_RFBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS1.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRFFDSTS1_RFFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS1.Reg, volatile.LoadUint32(&o.CFDRFFDSTS1.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS1_RFFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS1.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRFFDSTS1_RFIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS1.Reg, volatile.LoadUint32(&o.CFDRFFDSTS1.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS1_RFIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS1.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRFFDSTS1_CFDRFPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRFFDSTS1.Reg, volatile.LoadUint32(&o.CFDRFFDSTS1.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFFDSTS1_CFDRFPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRFFDSTS1.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRFDF1_0: RX FIFO Access Data Field 0 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_0_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_0.Reg, volatile.LoadUint32(&o.CFDRFDF1_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_0_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_0_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_0.Reg, volatile.LoadUint32(&o.CFDRFDF1_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_0_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_0_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_0.Reg, volatile.LoadUint32(&o.CFDRFDF1_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_0_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_0_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_0.Reg, volatile.LoadUint32(&o.CFDRFDF1_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_0_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_1: RX FIFO Access Data Field 1 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_1_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_1.Reg, volatile.LoadUint32(&o.CFDRFDF1_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_1_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_1_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_1.Reg, volatile.LoadUint32(&o.CFDRFDF1_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_1_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_1_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_1.Reg, volatile.LoadUint32(&o.CFDRFDF1_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_1_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_1_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_1.Reg, volatile.LoadUint32(&o.CFDRFDF1_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_1_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_2: RX FIFO Access Data Field 2 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_2_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_2.Reg, volatile.LoadUint32(&o.CFDRFDF1_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_2_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_2_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_2.Reg, volatile.LoadUint32(&o.CFDRFDF1_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_2_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_2_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_2.Reg, volatile.LoadUint32(&o.CFDRFDF1_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_2_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_2_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_2.Reg, volatile.LoadUint32(&o.CFDRFDF1_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_2_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_3: RX FIFO Access Data Field 3 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_3_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_3.Reg, volatile.LoadUint32(&o.CFDRFDF1_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_3_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_3_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_3.Reg, volatile.LoadUint32(&o.CFDRFDF1_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_3_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_3_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_3.Reg, volatile.LoadUint32(&o.CFDRFDF1_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_3_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_3_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_3.Reg, volatile.LoadUint32(&o.CFDRFDF1_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_3_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_4: RX FIFO Access Data Field 4 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_4_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_4.Reg, volatile.LoadUint32(&o.CFDRFDF1_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_4_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_4_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_4.Reg, volatile.LoadUint32(&o.CFDRFDF1_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_4_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_4_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_4.Reg, volatile.LoadUint32(&o.CFDRFDF1_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_4_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_4_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_4.Reg, volatile.LoadUint32(&o.CFDRFDF1_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_4_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_5: RX FIFO Access Data Field 5 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_5_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_5.Reg, volatile.LoadUint32(&o.CFDRFDF1_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_5_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_5_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_5.Reg, volatile.LoadUint32(&o.CFDRFDF1_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_5_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_5_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_5.Reg, volatile.LoadUint32(&o.CFDRFDF1_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_5_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_5_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_5.Reg, volatile.LoadUint32(&o.CFDRFDF1_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_5_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_6: RX FIFO Access Data Field 6 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_6_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_6.Reg, volatile.LoadUint32(&o.CFDRFDF1_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_6_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_6_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_6.Reg, volatile.LoadUint32(&o.CFDRFDF1_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_6_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_6_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_6.Reg, volatile.LoadUint32(&o.CFDRFDF1_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_6_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_6_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_6.Reg, volatile.LoadUint32(&o.CFDRFDF1_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_6_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_7: RX FIFO Access Data Field 7 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_7_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_7.Reg, volatile.LoadUint32(&o.CFDRFDF1_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_7_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_7_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_7.Reg, volatile.LoadUint32(&o.CFDRFDF1_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_7_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_7_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_7.Reg, volatile.LoadUint32(&o.CFDRFDF1_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_7_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_7_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_7.Reg, volatile.LoadUint32(&o.CFDRFDF1_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_7_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_8: RX FIFO Access Data Field 8 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_8_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_8.Reg, volatile.LoadUint32(&o.CFDRFDF1_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_8_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_8_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_8.Reg, volatile.LoadUint32(&o.CFDRFDF1_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_8_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_8_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_8.Reg, volatile.LoadUint32(&o.CFDRFDF1_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_8_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_8_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_8.Reg, volatile.LoadUint32(&o.CFDRFDF1_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_8_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_9: RX FIFO Access Data Field 9 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_9_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_9.Reg, volatile.LoadUint32(&o.CFDRFDF1_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_9_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_9_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_9.Reg, volatile.LoadUint32(&o.CFDRFDF1_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_9_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_9_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_9.Reg, volatile.LoadUint32(&o.CFDRFDF1_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_9_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_9_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_9.Reg, volatile.LoadUint32(&o.CFDRFDF1_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_9_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_10: RX FIFO Access Data Field 10 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_10_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_10.Reg, volatile.LoadUint32(&o.CFDRFDF1_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_10_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_10_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_10.Reg, volatile.LoadUint32(&o.CFDRFDF1_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_10_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_10_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_10.Reg, volatile.LoadUint32(&o.CFDRFDF1_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_10_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_10_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_10.Reg, volatile.LoadUint32(&o.CFDRFDF1_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_10_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_11: RX FIFO Access Data Field 11 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_11_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_11.Reg, volatile.LoadUint32(&o.CFDRFDF1_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_11_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_11_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_11.Reg, volatile.LoadUint32(&o.CFDRFDF1_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_11_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_11_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_11.Reg, volatile.LoadUint32(&o.CFDRFDF1_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_11_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_11_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_11.Reg, volatile.LoadUint32(&o.CFDRFDF1_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_11_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_12: RX FIFO Access Data Field 12 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_12_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_12.Reg, volatile.LoadUint32(&o.CFDRFDF1_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_12_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_12_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_12.Reg, volatile.LoadUint32(&o.CFDRFDF1_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_12_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_12_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_12.Reg, volatile.LoadUint32(&o.CFDRFDF1_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_12_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_12_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_12.Reg, volatile.LoadUint32(&o.CFDRFDF1_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_12_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_13: RX FIFO Access Data Field 13 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_13_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_13.Reg, volatile.LoadUint32(&o.CFDRFDF1_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_13_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_13_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_13.Reg, volatile.LoadUint32(&o.CFDRFDF1_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_13_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_13_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_13.Reg, volatile.LoadUint32(&o.CFDRFDF1_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_13_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_13_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_13.Reg, volatile.LoadUint32(&o.CFDRFDF1_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_13_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_14: RX FIFO Access Data Field 14 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_14_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_14.Reg, volatile.LoadUint32(&o.CFDRFDF1_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_14_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_14_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_14.Reg, volatile.LoadUint32(&o.CFDRFDF1_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_14_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_14_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_14.Reg, volatile.LoadUint32(&o.CFDRFDF1_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_14_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_14_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_14.Reg, volatile.LoadUint32(&o.CFDRFDF1_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_14_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRFDF1_15: RX FIFO Access Data Field 15 Register %s
func (o *CANFD_B_Type) SetCFDRFDF1_15_RFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_15.Reg, volatile.LoadUint32(&o.CFDRFDF1_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRFDF1_15_RFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRFDF1_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRFDF1_15_RFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_15.Reg, volatile.LoadUint32(&o.CFDRFDF1_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRFDF1_15_RFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRFDF1_15_RFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_15.Reg, volatile.LoadUint32(&o.CFDRFDF1_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRFDF1_15_RFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRFDF1_15_RFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRFDF1_15.Reg, volatile.LoadUint32(&o.CFDRFDF1_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRFDF1_15_RFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRFDF1_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFID: Common FIFO Access ID Register
func (o *CANFD_B_Type) SetCFDCFID_CFID(value uint32) {
	volatile.StoreUint32(&o.CFDCFID.Reg, volatile.LoadUint32(&o.CFDCFID.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDCFID_CFID() uint32 {
	return volatile.LoadUint32(&o.CFDCFID.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDCFID_THLEN(value uint32) {
	volatile.StoreUint32(&o.CFDCFID.Reg, volatile.LoadUint32(&o.CFDCFID.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDCFID_THLEN() uint32 {
	return (volatile.LoadUint32(&o.CFDCFID.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDCFID_CFRTR(value uint32) {
	volatile.StoreUint32(&o.CFDCFID.Reg, volatile.LoadUint32(&o.CFDCFID.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDCFID_CFRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDCFID.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDCFID_CFIDE(value uint32) {
	volatile.StoreUint32(&o.CFDCFID.Reg, volatile.LoadUint32(&o.CFDCFID.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDCFID_CFIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDCFID.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDCFPTR: Common FIFO Access Pointer Register
func (o *CANFD_B_Type) SetCFDCFPTR_CFTS(value uint32) {
	volatile.StoreUint32(&o.CFDCFPTR.Reg, volatile.LoadUint32(&o.CFDCFPTR.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDCFPTR_CFTS() uint32 {
	return volatile.LoadUint32(&o.CFDCFPTR.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDCFPTR_CFDLC(value uint32) {
	volatile.StoreUint32(&o.CFDCFPTR.Reg, volatile.LoadUint32(&o.CFDCFPTR.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDCFPTR_CFDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDCFPTR.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDCFFDCSTS: Common FIFO Access CANFD Control/Status Register
func (o *CANFD_B_Type) SetCFDCFFDCSTS_CFESI(value uint32) {
	volatile.StoreUint32(&o.CFDCFFDCSTS.Reg, volatile.LoadUint32(&o.CFDCFFDCSTS.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDCFFDCSTS_CFESI() uint32 {
	return volatile.LoadUint32(&o.CFDCFFDCSTS.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDCFFDCSTS_CFBRS(value uint32) {
	volatile.StoreUint32(&o.CFDCFFDCSTS.Reg, volatile.LoadUint32(&o.CFDCFFDCSTS.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDCFFDCSTS_CFBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDCFFDCSTS.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDCFFDCSTS_CFFDF(value uint32) {
	volatile.StoreUint32(&o.CFDCFFDCSTS.Reg, volatile.LoadUint32(&o.CFDCFFDCSTS.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDCFFDCSTS_CFFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDCFFDCSTS.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDCFFDCSTS_CFIFL(value uint32) {
	volatile.StoreUint32(&o.CFDCFFDCSTS.Reg, volatile.LoadUint32(&o.CFDCFFDCSTS.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFFDCSTS_CFIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFFDCSTS.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDCFFDCSTS_CFPTR(value uint32) {
	volatile.StoreUint32(&o.CFDCFFDCSTS.Reg, volatile.LoadUint32(&o.CFDCFFDCSTS.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFFDCSTS_CFPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDCFFDCSTS.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDCFDF0: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF0_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF0.Reg, volatile.LoadUint32(&o.CFDCFDF0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF0_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF0_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF0.Reg, volatile.LoadUint32(&o.CFDCFDF0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF0_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF0_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF0.Reg, volatile.LoadUint32(&o.CFDCFDF0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF0_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF0_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF0.Reg, volatile.LoadUint32(&o.CFDCFDF0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF0_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF1: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF1_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF1.Reg, volatile.LoadUint32(&o.CFDCFDF1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF1_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF1_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF1.Reg, volatile.LoadUint32(&o.CFDCFDF1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF1_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF1_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF1.Reg, volatile.LoadUint32(&o.CFDCFDF1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF1_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF1_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF1.Reg, volatile.LoadUint32(&o.CFDCFDF1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF1_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF2: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF2_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF2.Reg, volatile.LoadUint32(&o.CFDCFDF2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF2_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF2_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF2.Reg, volatile.LoadUint32(&o.CFDCFDF2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF2_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF2_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF2.Reg, volatile.LoadUint32(&o.CFDCFDF2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF2_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF2_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF2.Reg, volatile.LoadUint32(&o.CFDCFDF2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF2_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF3: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF3_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF3.Reg, volatile.LoadUint32(&o.CFDCFDF3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF3_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF3_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF3.Reg, volatile.LoadUint32(&o.CFDCFDF3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF3_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF3_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF3.Reg, volatile.LoadUint32(&o.CFDCFDF3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF3_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF3_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF3.Reg, volatile.LoadUint32(&o.CFDCFDF3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF3_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF4: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF4_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF4.Reg, volatile.LoadUint32(&o.CFDCFDF4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF4_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF4_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF4.Reg, volatile.LoadUint32(&o.CFDCFDF4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF4_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF4_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF4.Reg, volatile.LoadUint32(&o.CFDCFDF4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF4_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF4_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF4.Reg, volatile.LoadUint32(&o.CFDCFDF4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF4_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF5: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF5_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF5.Reg, volatile.LoadUint32(&o.CFDCFDF5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF5_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF5_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF5.Reg, volatile.LoadUint32(&o.CFDCFDF5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF5_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF5_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF5.Reg, volatile.LoadUint32(&o.CFDCFDF5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF5_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF5_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF5.Reg, volatile.LoadUint32(&o.CFDCFDF5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF5_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF6: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF6_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF6.Reg, volatile.LoadUint32(&o.CFDCFDF6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF6_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF6_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF6.Reg, volatile.LoadUint32(&o.CFDCFDF6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF6_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF6_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF6.Reg, volatile.LoadUint32(&o.CFDCFDF6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF6_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF6_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF6.Reg, volatile.LoadUint32(&o.CFDCFDF6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF6_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF7: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF7_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF7.Reg, volatile.LoadUint32(&o.CFDCFDF7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF7_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF7_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF7.Reg, volatile.LoadUint32(&o.CFDCFDF7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF7_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF7_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF7.Reg, volatile.LoadUint32(&o.CFDCFDF7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF7_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF7_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF7.Reg, volatile.LoadUint32(&o.CFDCFDF7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF7_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF8: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF8_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF8.Reg, volatile.LoadUint32(&o.CFDCFDF8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF8_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF8_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF8.Reg, volatile.LoadUint32(&o.CFDCFDF8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF8_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF8_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF8.Reg, volatile.LoadUint32(&o.CFDCFDF8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF8_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF8_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF8.Reg, volatile.LoadUint32(&o.CFDCFDF8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF8_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF9: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF9_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF9.Reg, volatile.LoadUint32(&o.CFDCFDF9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF9_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF9_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF9.Reg, volatile.LoadUint32(&o.CFDCFDF9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF9_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF9_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF9.Reg, volatile.LoadUint32(&o.CFDCFDF9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF9_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF9_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF9.Reg, volatile.LoadUint32(&o.CFDCFDF9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF9_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF10: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF10_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF10.Reg, volatile.LoadUint32(&o.CFDCFDF10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF10_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF10_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF10.Reg, volatile.LoadUint32(&o.CFDCFDF10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF10_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF10_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF10.Reg, volatile.LoadUint32(&o.CFDCFDF10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF10_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF10_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF10.Reg, volatile.LoadUint32(&o.CFDCFDF10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF10_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF11: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF11_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF11.Reg, volatile.LoadUint32(&o.CFDCFDF11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF11_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF11_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF11.Reg, volatile.LoadUint32(&o.CFDCFDF11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF11_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF11_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF11.Reg, volatile.LoadUint32(&o.CFDCFDF11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF11_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF11_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF11.Reg, volatile.LoadUint32(&o.CFDCFDF11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF11_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF12: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF12_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF12.Reg, volatile.LoadUint32(&o.CFDCFDF12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF12_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF12_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF12.Reg, volatile.LoadUint32(&o.CFDCFDF12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF12_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF12_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF12.Reg, volatile.LoadUint32(&o.CFDCFDF12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF12_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF12_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF12.Reg, volatile.LoadUint32(&o.CFDCFDF12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF12_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF13: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF13_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF13.Reg, volatile.LoadUint32(&o.CFDCFDF13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF13_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF13_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF13.Reg, volatile.LoadUint32(&o.CFDCFDF13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF13_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF13_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF13.Reg, volatile.LoadUint32(&o.CFDCFDF13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF13_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF13_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF13.Reg, volatile.LoadUint32(&o.CFDCFDF13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF13_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF14: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF14_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF14.Reg, volatile.LoadUint32(&o.CFDCFDF14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF14_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF14_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF14.Reg, volatile.LoadUint32(&o.CFDCFDF14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF14_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF14_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF14.Reg, volatile.LoadUint32(&o.CFDCFDF14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF14_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF14_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF14.Reg, volatile.LoadUint32(&o.CFDCFDF14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF14_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDCFDF15: Common FIFO Access Data Field %s Registers
func (o *CANFD_B_Type) SetCFDCFDF15_CFDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF15.Reg, volatile.LoadUint32(&o.CFDCFDF15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDCFDF15_CFDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDCFDF15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDCFDF15_CFDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF15.Reg, volatile.LoadUint32(&o.CFDCFDF15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDCFDF15_CFDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDCFDF15_CFDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF15.Reg, volatile.LoadUint32(&o.CFDCFDF15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDCFDF15_CFDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDCFDF15_CFDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDCFDF15.Reg, volatile.LoadUint32(&o.CFDCFDF15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDCFDF15_CFDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDCFDF15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMID0: TX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDTMID0_TMID(value uint32) {
	volatile.StoreUint32(&o.CFDTMID0.Reg, volatile.LoadUint32(&o.CFDTMID0.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDTMID0_TMID() uint32 {
	return volatile.LoadUint32(&o.CFDTMID0.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDTMID0_THLEN(value uint32) {
	volatile.StoreUint32(&o.CFDTMID0.Reg, volatile.LoadUint32(&o.CFDTMID0.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDTMID0_THLEN() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID0.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDTMID0_TMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMID0.Reg, volatile.LoadUint32(&o.CFDTMID0.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDTMID0_TMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID0.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDTMID0_TMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDTMID0.Reg, volatile.LoadUint32(&o.CFDTMID0.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDTMID0_TMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID0.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDTMPTR0: TX Message Buffer Pointer Register
func (o *CANFD_B_Type) SetCFDTMPTR0_TMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDTMPTR0.Reg, volatile.LoadUint32(&o.CFDTMPTR0.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDTMPTR0_TMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDTMPTR0.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDTMFDCTR0: TX Message Buffer CANFD Control Register
func (o *CANFD_B_Type) SetCFDTMFDCTR0_TMESI(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR0.Reg, volatile.LoadUint32(&o.CFDTMFDCTR0.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR0_TMESI() uint32 {
	return volatile.LoadUint32(&o.CFDTMFDCTR0.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR0_TMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR0.Reg, volatile.LoadUint32(&o.CFDTMFDCTR0.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR0_TMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR0.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR0_TMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR0.Reg, volatile.LoadUint32(&o.CFDTMFDCTR0.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR0_TMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR0.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDTMFDCTR0_TMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR0.Reg, volatile.LoadUint32(&o.CFDTMFDCTR0.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR0_TMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR0.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDTMFDCTR0_TMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR0.Reg, volatile.LoadUint32(&o.CFDTMFDCTR0.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR0_TMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR0.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDTMDF0_0: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_0_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_0.Reg, volatile.LoadUint32(&o.CFDTMDF0_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_0_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_0_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_0.Reg, volatile.LoadUint32(&o.CFDTMDF0_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_0_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_0_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_0.Reg, volatile.LoadUint32(&o.CFDTMDF0_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_0_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_0_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_0.Reg, volatile.LoadUint32(&o.CFDTMDF0_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_0_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_1: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_1_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_1.Reg, volatile.LoadUint32(&o.CFDTMDF0_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_1_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_1_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_1.Reg, volatile.LoadUint32(&o.CFDTMDF0_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_1_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_1_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_1.Reg, volatile.LoadUint32(&o.CFDTMDF0_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_1_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_1_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_1.Reg, volatile.LoadUint32(&o.CFDTMDF0_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_1_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_2: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_2_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_2.Reg, volatile.LoadUint32(&o.CFDTMDF0_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_2_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_2_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_2.Reg, volatile.LoadUint32(&o.CFDTMDF0_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_2_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_2_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_2.Reg, volatile.LoadUint32(&o.CFDTMDF0_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_2_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_2_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_2.Reg, volatile.LoadUint32(&o.CFDTMDF0_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_2_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_3: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_3_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_3.Reg, volatile.LoadUint32(&o.CFDTMDF0_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_3_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_3_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_3.Reg, volatile.LoadUint32(&o.CFDTMDF0_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_3_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_3_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_3.Reg, volatile.LoadUint32(&o.CFDTMDF0_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_3_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_3_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_3.Reg, volatile.LoadUint32(&o.CFDTMDF0_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_3_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_4: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_4_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_4.Reg, volatile.LoadUint32(&o.CFDTMDF0_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_4_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_4_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_4.Reg, volatile.LoadUint32(&o.CFDTMDF0_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_4_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_4_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_4.Reg, volatile.LoadUint32(&o.CFDTMDF0_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_4_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_4_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_4.Reg, volatile.LoadUint32(&o.CFDTMDF0_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_4_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_5: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_5_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_5.Reg, volatile.LoadUint32(&o.CFDTMDF0_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_5_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_5_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_5.Reg, volatile.LoadUint32(&o.CFDTMDF0_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_5_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_5_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_5.Reg, volatile.LoadUint32(&o.CFDTMDF0_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_5_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_5_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_5.Reg, volatile.LoadUint32(&o.CFDTMDF0_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_5_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_6: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_6_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_6.Reg, volatile.LoadUint32(&o.CFDTMDF0_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_6_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_6_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_6.Reg, volatile.LoadUint32(&o.CFDTMDF0_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_6_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_6_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_6.Reg, volatile.LoadUint32(&o.CFDTMDF0_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_6_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_6_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_6.Reg, volatile.LoadUint32(&o.CFDTMDF0_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_6_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_7: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_7_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_7.Reg, volatile.LoadUint32(&o.CFDTMDF0_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_7_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_7_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_7.Reg, volatile.LoadUint32(&o.CFDTMDF0_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_7_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_7_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_7.Reg, volatile.LoadUint32(&o.CFDTMDF0_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_7_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_7_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_7.Reg, volatile.LoadUint32(&o.CFDTMDF0_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_7_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_8: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_8_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_8.Reg, volatile.LoadUint32(&o.CFDTMDF0_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_8_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_8_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_8.Reg, volatile.LoadUint32(&o.CFDTMDF0_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_8_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_8_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_8.Reg, volatile.LoadUint32(&o.CFDTMDF0_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_8_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_8_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_8.Reg, volatile.LoadUint32(&o.CFDTMDF0_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_8_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_9: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_9_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_9.Reg, volatile.LoadUint32(&o.CFDTMDF0_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_9_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_9_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_9.Reg, volatile.LoadUint32(&o.CFDTMDF0_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_9_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_9_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_9.Reg, volatile.LoadUint32(&o.CFDTMDF0_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_9_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_9_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_9.Reg, volatile.LoadUint32(&o.CFDTMDF0_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_9_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_10: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_10_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_10.Reg, volatile.LoadUint32(&o.CFDTMDF0_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_10_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_10_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_10.Reg, volatile.LoadUint32(&o.CFDTMDF0_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_10_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_10_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_10.Reg, volatile.LoadUint32(&o.CFDTMDF0_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_10_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_10_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_10.Reg, volatile.LoadUint32(&o.CFDTMDF0_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_10_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_11: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_11_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_11.Reg, volatile.LoadUint32(&o.CFDTMDF0_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_11_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_11_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_11.Reg, volatile.LoadUint32(&o.CFDTMDF0_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_11_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_11_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_11.Reg, volatile.LoadUint32(&o.CFDTMDF0_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_11_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_11_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_11.Reg, volatile.LoadUint32(&o.CFDTMDF0_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_11_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_12: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_12_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_12.Reg, volatile.LoadUint32(&o.CFDTMDF0_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_12_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_12_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_12.Reg, volatile.LoadUint32(&o.CFDTMDF0_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_12_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_12_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_12.Reg, volatile.LoadUint32(&o.CFDTMDF0_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_12_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_12_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_12.Reg, volatile.LoadUint32(&o.CFDTMDF0_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_12_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_13: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_13_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_13.Reg, volatile.LoadUint32(&o.CFDTMDF0_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_13_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_13_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_13.Reg, volatile.LoadUint32(&o.CFDTMDF0_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_13_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_13_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_13.Reg, volatile.LoadUint32(&o.CFDTMDF0_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_13_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_13_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_13.Reg, volatile.LoadUint32(&o.CFDTMDF0_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_13_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_14: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_14_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_14.Reg, volatile.LoadUint32(&o.CFDTMDF0_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_14_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_14_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_14.Reg, volatile.LoadUint32(&o.CFDTMDF0_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_14_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_14_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_14.Reg, volatile.LoadUint32(&o.CFDTMDF0_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_14_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_14_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_14.Reg, volatile.LoadUint32(&o.CFDTMDF0_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_14_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF0_15: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF0_15_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_15.Reg, volatile.LoadUint32(&o.CFDTMDF0_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF0_15_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF0_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF0_15_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_15.Reg, volatile.LoadUint32(&o.CFDTMDF0_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF0_15_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF0_15_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_15.Reg, volatile.LoadUint32(&o.CFDTMDF0_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF0_15_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF0_15_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF0_15.Reg, volatile.LoadUint32(&o.CFDTMDF0_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF0_15_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF0_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMID1: TX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDTMID1_TMID(value uint32) {
	volatile.StoreUint32(&o.CFDTMID1.Reg, volatile.LoadUint32(&o.CFDTMID1.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDTMID1_TMID() uint32 {
	return volatile.LoadUint32(&o.CFDTMID1.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDTMID1_THLEN(value uint32) {
	volatile.StoreUint32(&o.CFDTMID1.Reg, volatile.LoadUint32(&o.CFDTMID1.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDTMID1_THLEN() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID1.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDTMID1_TMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMID1.Reg, volatile.LoadUint32(&o.CFDTMID1.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDTMID1_TMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID1.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDTMID1_TMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDTMID1.Reg, volatile.LoadUint32(&o.CFDTMID1.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDTMID1_TMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID1.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDTMPTR1: TX Message Buffer Pointer Register
func (o *CANFD_B_Type) SetCFDTMPTR1_TMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDTMPTR1.Reg, volatile.LoadUint32(&o.CFDTMPTR1.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDTMPTR1_TMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDTMPTR1.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDTMFDCTR1: TX Message Buffer CANFD Control Register
func (o *CANFD_B_Type) SetCFDTMFDCTR1_TMESI(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR1.Reg, volatile.LoadUint32(&o.CFDTMFDCTR1.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR1_TMESI() uint32 {
	return volatile.LoadUint32(&o.CFDTMFDCTR1.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR1_TMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR1.Reg, volatile.LoadUint32(&o.CFDTMFDCTR1.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR1_TMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR1.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR1_TMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR1.Reg, volatile.LoadUint32(&o.CFDTMFDCTR1.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR1_TMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR1.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDTMFDCTR1_TMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR1.Reg, volatile.LoadUint32(&o.CFDTMFDCTR1.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR1_TMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR1.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDTMFDCTR1_TMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR1.Reg, volatile.LoadUint32(&o.CFDTMFDCTR1.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR1_TMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR1.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDTMDF1_0: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_0_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_0.Reg, volatile.LoadUint32(&o.CFDTMDF1_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_0_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_0_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_0.Reg, volatile.LoadUint32(&o.CFDTMDF1_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_0_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_0_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_0.Reg, volatile.LoadUint32(&o.CFDTMDF1_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_0_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_0_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_0.Reg, volatile.LoadUint32(&o.CFDTMDF1_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_0_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_1: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_1_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_1.Reg, volatile.LoadUint32(&o.CFDTMDF1_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_1_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_1_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_1.Reg, volatile.LoadUint32(&o.CFDTMDF1_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_1_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_1_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_1.Reg, volatile.LoadUint32(&o.CFDTMDF1_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_1_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_1_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_1.Reg, volatile.LoadUint32(&o.CFDTMDF1_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_1_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_2: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_2_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_2.Reg, volatile.LoadUint32(&o.CFDTMDF1_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_2_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_2_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_2.Reg, volatile.LoadUint32(&o.CFDTMDF1_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_2_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_2_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_2.Reg, volatile.LoadUint32(&o.CFDTMDF1_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_2_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_2_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_2.Reg, volatile.LoadUint32(&o.CFDTMDF1_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_2_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_3: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_3_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_3.Reg, volatile.LoadUint32(&o.CFDTMDF1_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_3_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_3_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_3.Reg, volatile.LoadUint32(&o.CFDTMDF1_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_3_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_3_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_3.Reg, volatile.LoadUint32(&o.CFDTMDF1_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_3_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_3_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_3.Reg, volatile.LoadUint32(&o.CFDTMDF1_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_3_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_4: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_4_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_4.Reg, volatile.LoadUint32(&o.CFDTMDF1_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_4_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_4_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_4.Reg, volatile.LoadUint32(&o.CFDTMDF1_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_4_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_4_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_4.Reg, volatile.LoadUint32(&o.CFDTMDF1_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_4_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_4_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_4.Reg, volatile.LoadUint32(&o.CFDTMDF1_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_4_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_5: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_5_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_5.Reg, volatile.LoadUint32(&o.CFDTMDF1_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_5_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_5_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_5.Reg, volatile.LoadUint32(&o.CFDTMDF1_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_5_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_5_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_5.Reg, volatile.LoadUint32(&o.CFDTMDF1_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_5_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_5_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_5.Reg, volatile.LoadUint32(&o.CFDTMDF1_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_5_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_6: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_6_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_6.Reg, volatile.LoadUint32(&o.CFDTMDF1_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_6_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_6_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_6.Reg, volatile.LoadUint32(&o.CFDTMDF1_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_6_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_6_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_6.Reg, volatile.LoadUint32(&o.CFDTMDF1_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_6_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_6_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_6.Reg, volatile.LoadUint32(&o.CFDTMDF1_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_6_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_7: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_7_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_7.Reg, volatile.LoadUint32(&o.CFDTMDF1_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_7_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_7_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_7.Reg, volatile.LoadUint32(&o.CFDTMDF1_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_7_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_7_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_7.Reg, volatile.LoadUint32(&o.CFDTMDF1_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_7_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_7_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_7.Reg, volatile.LoadUint32(&o.CFDTMDF1_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_7_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_8: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_8_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_8.Reg, volatile.LoadUint32(&o.CFDTMDF1_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_8_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_8_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_8.Reg, volatile.LoadUint32(&o.CFDTMDF1_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_8_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_8_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_8.Reg, volatile.LoadUint32(&o.CFDTMDF1_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_8_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_8_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_8.Reg, volatile.LoadUint32(&o.CFDTMDF1_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_8_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_9: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_9_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_9.Reg, volatile.LoadUint32(&o.CFDTMDF1_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_9_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_9_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_9.Reg, volatile.LoadUint32(&o.CFDTMDF1_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_9_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_9_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_9.Reg, volatile.LoadUint32(&o.CFDTMDF1_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_9_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_9_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_9.Reg, volatile.LoadUint32(&o.CFDTMDF1_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_9_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_10: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_10_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_10.Reg, volatile.LoadUint32(&o.CFDTMDF1_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_10_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_10_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_10.Reg, volatile.LoadUint32(&o.CFDTMDF1_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_10_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_10_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_10.Reg, volatile.LoadUint32(&o.CFDTMDF1_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_10_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_10_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_10.Reg, volatile.LoadUint32(&o.CFDTMDF1_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_10_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_11: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_11_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_11.Reg, volatile.LoadUint32(&o.CFDTMDF1_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_11_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_11_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_11.Reg, volatile.LoadUint32(&o.CFDTMDF1_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_11_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_11_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_11.Reg, volatile.LoadUint32(&o.CFDTMDF1_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_11_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_11_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_11.Reg, volatile.LoadUint32(&o.CFDTMDF1_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_11_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_12: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_12_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_12.Reg, volatile.LoadUint32(&o.CFDTMDF1_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_12_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_12_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_12.Reg, volatile.LoadUint32(&o.CFDTMDF1_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_12_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_12_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_12.Reg, volatile.LoadUint32(&o.CFDTMDF1_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_12_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_12_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_12.Reg, volatile.LoadUint32(&o.CFDTMDF1_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_12_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_13: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_13_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_13.Reg, volatile.LoadUint32(&o.CFDTMDF1_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_13_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_13_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_13.Reg, volatile.LoadUint32(&o.CFDTMDF1_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_13_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_13_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_13.Reg, volatile.LoadUint32(&o.CFDTMDF1_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_13_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_13_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_13.Reg, volatile.LoadUint32(&o.CFDTMDF1_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_13_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_14: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_14_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_14.Reg, volatile.LoadUint32(&o.CFDTMDF1_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_14_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_14_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_14.Reg, volatile.LoadUint32(&o.CFDTMDF1_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_14_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_14_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_14.Reg, volatile.LoadUint32(&o.CFDTMDF1_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_14_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_14_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_14.Reg, volatile.LoadUint32(&o.CFDTMDF1_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_14_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF1_15: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF1_15_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_15.Reg, volatile.LoadUint32(&o.CFDTMDF1_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF1_15_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF1_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF1_15_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_15.Reg, volatile.LoadUint32(&o.CFDTMDF1_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF1_15_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF1_15_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_15.Reg, volatile.LoadUint32(&o.CFDTMDF1_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF1_15_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF1_15_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF1_15.Reg, volatile.LoadUint32(&o.CFDTMDF1_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF1_15_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF1_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMID2: TX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDTMID2_TMID(value uint32) {
	volatile.StoreUint32(&o.CFDTMID2.Reg, volatile.LoadUint32(&o.CFDTMID2.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDTMID2_TMID() uint32 {
	return volatile.LoadUint32(&o.CFDTMID2.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDTMID2_THLEN(value uint32) {
	volatile.StoreUint32(&o.CFDTMID2.Reg, volatile.LoadUint32(&o.CFDTMID2.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDTMID2_THLEN() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID2.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDTMID2_TMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMID2.Reg, volatile.LoadUint32(&o.CFDTMID2.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDTMID2_TMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID2.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDTMID2_TMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDTMID2.Reg, volatile.LoadUint32(&o.CFDTMID2.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDTMID2_TMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID2.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDTMPTR2: TX Message Buffer Pointer Register
func (o *CANFD_B_Type) SetCFDTMPTR2_TMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDTMPTR2.Reg, volatile.LoadUint32(&o.CFDTMPTR2.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDTMPTR2_TMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDTMPTR2.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDTMFDCTR2: TX Message Buffer CANFD Control Register
func (o *CANFD_B_Type) SetCFDTMFDCTR2_TMESI(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR2.Reg, volatile.LoadUint32(&o.CFDTMFDCTR2.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR2_TMESI() uint32 {
	return volatile.LoadUint32(&o.CFDTMFDCTR2.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR2_TMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR2.Reg, volatile.LoadUint32(&o.CFDTMFDCTR2.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR2_TMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR2.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR2_TMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR2.Reg, volatile.LoadUint32(&o.CFDTMFDCTR2.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR2_TMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR2.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDTMFDCTR2_TMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR2.Reg, volatile.LoadUint32(&o.CFDTMFDCTR2.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR2_TMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR2.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDTMFDCTR2_TMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR2.Reg, volatile.LoadUint32(&o.CFDTMFDCTR2.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR2_TMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR2.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDTMDF2_0: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_0_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_0.Reg, volatile.LoadUint32(&o.CFDTMDF2_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_0_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_0_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_0.Reg, volatile.LoadUint32(&o.CFDTMDF2_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_0_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_0_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_0.Reg, volatile.LoadUint32(&o.CFDTMDF2_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_0_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_0_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_0.Reg, volatile.LoadUint32(&o.CFDTMDF2_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_0_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_1: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_1_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_1.Reg, volatile.LoadUint32(&o.CFDTMDF2_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_1_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_1_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_1.Reg, volatile.LoadUint32(&o.CFDTMDF2_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_1_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_1_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_1.Reg, volatile.LoadUint32(&o.CFDTMDF2_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_1_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_1_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_1.Reg, volatile.LoadUint32(&o.CFDTMDF2_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_1_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_2: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_2_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_2.Reg, volatile.LoadUint32(&o.CFDTMDF2_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_2_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_2_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_2.Reg, volatile.LoadUint32(&o.CFDTMDF2_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_2_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_2_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_2.Reg, volatile.LoadUint32(&o.CFDTMDF2_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_2_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_2_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_2.Reg, volatile.LoadUint32(&o.CFDTMDF2_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_2_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_3: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_3_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_3.Reg, volatile.LoadUint32(&o.CFDTMDF2_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_3_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_3_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_3.Reg, volatile.LoadUint32(&o.CFDTMDF2_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_3_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_3_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_3.Reg, volatile.LoadUint32(&o.CFDTMDF2_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_3_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_3_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_3.Reg, volatile.LoadUint32(&o.CFDTMDF2_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_3_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_4: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_4_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_4.Reg, volatile.LoadUint32(&o.CFDTMDF2_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_4_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_4_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_4.Reg, volatile.LoadUint32(&o.CFDTMDF2_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_4_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_4_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_4.Reg, volatile.LoadUint32(&o.CFDTMDF2_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_4_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_4_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_4.Reg, volatile.LoadUint32(&o.CFDTMDF2_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_4_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_5: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_5_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_5.Reg, volatile.LoadUint32(&o.CFDTMDF2_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_5_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_5_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_5.Reg, volatile.LoadUint32(&o.CFDTMDF2_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_5_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_5_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_5.Reg, volatile.LoadUint32(&o.CFDTMDF2_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_5_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_5_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_5.Reg, volatile.LoadUint32(&o.CFDTMDF2_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_5_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_6: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_6_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_6.Reg, volatile.LoadUint32(&o.CFDTMDF2_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_6_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_6_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_6.Reg, volatile.LoadUint32(&o.CFDTMDF2_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_6_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_6_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_6.Reg, volatile.LoadUint32(&o.CFDTMDF2_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_6_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_6_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_6.Reg, volatile.LoadUint32(&o.CFDTMDF2_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_6_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_7: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_7_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_7.Reg, volatile.LoadUint32(&o.CFDTMDF2_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_7_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_7_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_7.Reg, volatile.LoadUint32(&o.CFDTMDF2_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_7_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_7_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_7.Reg, volatile.LoadUint32(&o.CFDTMDF2_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_7_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_7_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_7.Reg, volatile.LoadUint32(&o.CFDTMDF2_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_7_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_8: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_8_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_8.Reg, volatile.LoadUint32(&o.CFDTMDF2_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_8_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_8_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_8.Reg, volatile.LoadUint32(&o.CFDTMDF2_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_8_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_8_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_8.Reg, volatile.LoadUint32(&o.CFDTMDF2_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_8_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_8_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_8.Reg, volatile.LoadUint32(&o.CFDTMDF2_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_8_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_9: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_9_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_9.Reg, volatile.LoadUint32(&o.CFDTMDF2_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_9_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_9_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_9.Reg, volatile.LoadUint32(&o.CFDTMDF2_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_9_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_9_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_9.Reg, volatile.LoadUint32(&o.CFDTMDF2_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_9_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_9_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_9.Reg, volatile.LoadUint32(&o.CFDTMDF2_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_9_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_10: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_10_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_10.Reg, volatile.LoadUint32(&o.CFDTMDF2_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_10_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_10_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_10.Reg, volatile.LoadUint32(&o.CFDTMDF2_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_10_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_10_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_10.Reg, volatile.LoadUint32(&o.CFDTMDF2_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_10_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_10_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_10.Reg, volatile.LoadUint32(&o.CFDTMDF2_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_10_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_11: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_11_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_11.Reg, volatile.LoadUint32(&o.CFDTMDF2_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_11_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_11_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_11.Reg, volatile.LoadUint32(&o.CFDTMDF2_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_11_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_11_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_11.Reg, volatile.LoadUint32(&o.CFDTMDF2_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_11_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_11_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_11.Reg, volatile.LoadUint32(&o.CFDTMDF2_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_11_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_12: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_12_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_12.Reg, volatile.LoadUint32(&o.CFDTMDF2_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_12_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_12_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_12.Reg, volatile.LoadUint32(&o.CFDTMDF2_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_12_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_12_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_12.Reg, volatile.LoadUint32(&o.CFDTMDF2_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_12_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_12_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_12.Reg, volatile.LoadUint32(&o.CFDTMDF2_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_12_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_13: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_13_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_13.Reg, volatile.LoadUint32(&o.CFDTMDF2_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_13_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_13_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_13.Reg, volatile.LoadUint32(&o.CFDTMDF2_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_13_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_13_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_13.Reg, volatile.LoadUint32(&o.CFDTMDF2_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_13_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_13_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_13.Reg, volatile.LoadUint32(&o.CFDTMDF2_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_13_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_14: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_14_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_14.Reg, volatile.LoadUint32(&o.CFDTMDF2_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_14_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_14_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_14.Reg, volatile.LoadUint32(&o.CFDTMDF2_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_14_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_14_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_14.Reg, volatile.LoadUint32(&o.CFDTMDF2_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_14_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_14_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_14.Reg, volatile.LoadUint32(&o.CFDTMDF2_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_14_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF2_15: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF2_15_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_15.Reg, volatile.LoadUint32(&o.CFDTMDF2_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF2_15_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF2_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF2_15_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_15.Reg, volatile.LoadUint32(&o.CFDTMDF2_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF2_15_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF2_15_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_15.Reg, volatile.LoadUint32(&o.CFDTMDF2_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF2_15_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF2_15_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF2_15.Reg, volatile.LoadUint32(&o.CFDTMDF2_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF2_15_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF2_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMID3: TX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDTMID3_TMID(value uint32) {
	volatile.StoreUint32(&o.CFDTMID3.Reg, volatile.LoadUint32(&o.CFDTMID3.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDTMID3_TMID() uint32 {
	return volatile.LoadUint32(&o.CFDTMID3.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDTMID3_THLEN(value uint32) {
	volatile.StoreUint32(&o.CFDTMID3.Reg, volatile.LoadUint32(&o.CFDTMID3.Reg)&^(0x20000000)|value<<29)
}
func (o *CANFD_B_Type) GetCFDTMID3_THLEN() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID3.Reg) & 0x20000000) >> 29
}
func (o *CANFD_B_Type) SetCFDTMID3_TMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMID3.Reg, volatile.LoadUint32(&o.CFDTMID3.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDTMID3_TMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID3.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDTMID3_TMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDTMID3.Reg, volatile.LoadUint32(&o.CFDTMID3.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDTMID3_TMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDTMID3.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDTMPTR3: TX Message Buffer Pointer Register
func (o *CANFD_B_Type) SetCFDTMPTR3_TMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDTMPTR3.Reg, volatile.LoadUint32(&o.CFDTMPTR3.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDTMPTR3_TMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDTMPTR3.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDTMFDCTR3: TX Message Buffer CANFD Control Register
func (o *CANFD_B_Type) SetCFDTMFDCTR3_TMESI(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR3.Reg, volatile.LoadUint32(&o.CFDTMFDCTR3.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR3_TMESI() uint32 {
	return volatile.LoadUint32(&o.CFDTMFDCTR3.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR3_TMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR3.Reg, volatile.LoadUint32(&o.CFDTMFDCTR3.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR3_TMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR3.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDTMFDCTR3_TMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR3.Reg, volatile.LoadUint32(&o.CFDTMFDCTR3.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR3_TMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR3.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDTMFDCTR3_TMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR3.Reg, volatile.LoadUint32(&o.CFDTMFDCTR3.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR3_TMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR3.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDTMFDCTR3_TMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDTMFDCTR3.Reg, volatile.LoadUint32(&o.CFDTMFDCTR3.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMFDCTR3_TMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDTMFDCTR3.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDTMDF3_0: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_0_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_0.Reg, volatile.LoadUint32(&o.CFDTMDF3_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_0_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_0_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_0.Reg, volatile.LoadUint32(&o.CFDTMDF3_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_0_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_0_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_0.Reg, volatile.LoadUint32(&o.CFDTMDF3_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_0_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_0_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_0.Reg, volatile.LoadUint32(&o.CFDTMDF3_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_0_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_1: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_1_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_1.Reg, volatile.LoadUint32(&o.CFDTMDF3_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_1_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_1_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_1.Reg, volatile.LoadUint32(&o.CFDTMDF3_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_1_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_1_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_1.Reg, volatile.LoadUint32(&o.CFDTMDF3_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_1_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_1_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_1.Reg, volatile.LoadUint32(&o.CFDTMDF3_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_1_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_2: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_2_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_2.Reg, volatile.LoadUint32(&o.CFDTMDF3_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_2_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_2_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_2.Reg, volatile.LoadUint32(&o.CFDTMDF3_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_2_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_2_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_2.Reg, volatile.LoadUint32(&o.CFDTMDF3_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_2_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_2_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_2.Reg, volatile.LoadUint32(&o.CFDTMDF3_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_2_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_3: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_3_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_3.Reg, volatile.LoadUint32(&o.CFDTMDF3_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_3_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_3_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_3.Reg, volatile.LoadUint32(&o.CFDTMDF3_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_3_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_3_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_3.Reg, volatile.LoadUint32(&o.CFDTMDF3_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_3_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_3_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_3.Reg, volatile.LoadUint32(&o.CFDTMDF3_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_3_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_4: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_4_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_4.Reg, volatile.LoadUint32(&o.CFDTMDF3_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_4_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_4_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_4.Reg, volatile.LoadUint32(&o.CFDTMDF3_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_4_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_4_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_4.Reg, volatile.LoadUint32(&o.CFDTMDF3_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_4_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_4_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_4.Reg, volatile.LoadUint32(&o.CFDTMDF3_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_4_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_5: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_5_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_5.Reg, volatile.LoadUint32(&o.CFDTMDF3_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_5_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_5_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_5.Reg, volatile.LoadUint32(&o.CFDTMDF3_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_5_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_5_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_5.Reg, volatile.LoadUint32(&o.CFDTMDF3_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_5_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_5_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_5.Reg, volatile.LoadUint32(&o.CFDTMDF3_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_5_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_6: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_6_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_6.Reg, volatile.LoadUint32(&o.CFDTMDF3_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_6_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_6_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_6.Reg, volatile.LoadUint32(&o.CFDTMDF3_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_6_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_6_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_6.Reg, volatile.LoadUint32(&o.CFDTMDF3_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_6_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_6_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_6.Reg, volatile.LoadUint32(&o.CFDTMDF3_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_6_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_7: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_7_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_7.Reg, volatile.LoadUint32(&o.CFDTMDF3_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_7_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_7_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_7.Reg, volatile.LoadUint32(&o.CFDTMDF3_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_7_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_7_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_7.Reg, volatile.LoadUint32(&o.CFDTMDF3_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_7_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_7_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_7.Reg, volatile.LoadUint32(&o.CFDTMDF3_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_7_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_8: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_8_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_8.Reg, volatile.LoadUint32(&o.CFDTMDF3_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_8_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_8_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_8.Reg, volatile.LoadUint32(&o.CFDTMDF3_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_8_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_8_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_8.Reg, volatile.LoadUint32(&o.CFDTMDF3_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_8_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_8_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_8.Reg, volatile.LoadUint32(&o.CFDTMDF3_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_8_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_9: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_9_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_9.Reg, volatile.LoadUint32(&o.CFDTMDF3_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_9_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_9_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_9.Reg, volatile.LoadUint32(&o.CFDTMDF3_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_9_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_9_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_9.Reg, volatile.LoadUint32(&o.CFDTMDF3_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_9_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_9_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_9.Reg, volatile.LoadUint32(&o.CFDTMDF3_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_9_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_10: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_10_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_10.Reg, volatile.LoadUint32(&o.CFDTMDF3_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_10_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_10_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_10.Reg, volatile.LoadUint32(&o.CFDTMDF3_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_10_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_10_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_10.Reg, volatile.LoadUint32(&o.CFDTMDF3_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_10_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_10_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_10.Reg, volatile.LoadUint32(&o.CFDTMDF3_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_10_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_11: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_11_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_11.Reg, volatile.LoadUint32(&o.CFDTMDF3_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_11_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_11_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_11.Reg, volatile.LoadUint32(&o.CFDTMDF3_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_11_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_11_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_11.Reg, volatile.LoadUint32(&o.CFDTMDF3_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_11_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_11_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_11.Reg, volatile.LoadUint32(&o.CFDTMDF3_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_11_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_12: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_12_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_12.Reg, volatile.LoadUint32(&o.CFDTMDF3_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_12_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_12_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_12.Reg, volatile.LoadUint32(&o.CFDTMDF3_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_12_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_12_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_12.Reg, volatile.LoadUint32(&o.CFDTMDF3_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_12_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_12_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_12.Reg, volatile.LoadUint32(&o.CFDTMDF3_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_12_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_13: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_13_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_13.Reg, volatile.LoadUint32(&o.CFDTMDF3_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_13_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_13_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_13.Reg, volatile.LoadUint32(&o.CFDTMDF3_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_13_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_13_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_13.Reg, volatile.LoadUint32(&o.CFDTMDF3_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_13_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_13_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_13.Reg, volatile.LoadUint32(&o.CFDTMDF3_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_13_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_14: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_14_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_14.Reg, volatile.LoadUint32(&o.CFDTMDF3_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_14_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_14_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_14.Reg, volatile.LoadUint32(&o.CFDTMDF3_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_14_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_14_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_14.Reg, volatile.LoadUint32(&o.CFDTMDF3_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_14_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_14_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_14.Reg, volatile.LoadUint32(&o.CFDTMDF3_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_14_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTMDF3_15: TX Message Buffer Data Field Register
func (o *CANFD_B_Type) SetCFDTMDF3_15_TMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_15.Reg, volatile.LoadUint32(&o.CFDTMDF3_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDTMDF3_15_TMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDTMDF3_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDTMDF3_15_TMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_15.Reg, volatile.LoadUint32(&o.CFDTMDF3_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDTMDF3_15_TMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDTMDF3_15_TMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_15.Reg, volatile.LoadUint32(&o.CFDTMDF3_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTMDF3_15_TMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDTMDF3_15_TMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDTMDF3_15.Reg, volatile.LoadUint32(&o.CFDTMDF3_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDTMDF3_15_TMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDTMDF3_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDTHLACC0: TX History List Access Register 0
func (o *CANFD_B_Type) SetCFDTHLACC0_BT(value uint32) {
	volatile.StoreUint32(&o.CFDTHLACC0.Reg, volatile.LoadUint32(&o.CFDTHLACC0.Reg)&^(0x7)|value)
}
func (o *CANFD_B_Type) GetCFDTHLACC0_BT() uint32 {
	return volatile.LoadUint32(&o.CFDTHLACC0.Reg) & 0x7
}
func (o *CANFD_B_Type) SetCFDTHLACC0_BN(value uint32) {
	volatile.StoreUint32(&o.CFDTHLACC0.Reg, volatile.LoadUint32(&o.CFDTHLACC0.Reg)&^(0x18)|value<<3)
}
func (o *CANFD_B_Type) GetCFDTHLACC0_BN() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLACC0.Reg) & 0x18) >> 3
}
func (o *CANFD_B_Type) SetCFDTHLACC0_TMTS(value uint32) {
	volatile.StoreUint32(&o.CFDTHLACC0.Reg, volatile.LoadUint32(&o.CFDTHLACC0.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTHLACC0_TMTS() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLACC0.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDTHLACC1: TX History List Access Register 1
func (o *CANFD_B_Type) SetCFDTHLACC1_TID(value uint32) {
	volatile.StoreUint32(&o.CFDTHLACC1.Reg, volatile.LoadUint32(&o.CFDTHLACC1.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDTHLACC1_TID() uint32 {
	return volatile.LoadUint32(&o.CFDTHLACC1.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDTHLACC1_TIFL(value uint32) {
	volatile.StoreUint32(&o.CFDTHLACC1.Reg, volatile.LoadUint32(&o.CFDTHLACC1.Reg)&^(0x30000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDTHLACC1_TIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDTHLACC1.Reg) & 0x30000) >> 16
}

// CANFD_B.CFDRMID0: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID0_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID0.Reg, volatile.LoadUint32(&o.CFDRMID0.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID0_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID0.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID0_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID0.Reg, volatile.LoadUint32(&o.CFDRMID0.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID0_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID0.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID0_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID0.Reg, volatile.LoadUint32(&o.CFDRMID0.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID0_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID0.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR0: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR0_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR0.Reg, volatile.LoadUint32(&o.CFDRMPTR0.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR0_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR0.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR0_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR0.Reg, volatile.LoadUint32(&o.CFDRMPTR0.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR0_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR0.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS0: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS0_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS0.Reg, volatile.LoadUint32(&o.CFDRMFDSTS0.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS0_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS0.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS0_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS0.Reg, volatile.LoadUint32(&o.CFDRMFDSTS0.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS0_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS0.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS0_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS0.Reg, volatile.LoadUint32(&o.CFDRMFDSTS0.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS0_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS0.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS0_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS0.Reg, volatile.LoadUint32(&o.CFDRMFDSTS0.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS0_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS0.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS0_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS0.Reg, volatile.LoadUint32(&o.CFDRMFDSTS0.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS0_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS0.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF0_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_0.Reg, volatile.LoadUint32(&o.CFDRMDF0_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_0.Reg, volatile.LoadUint32(&o.CFDRMDF0_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_0.Reg, volatile.LoadUint32(&o.CFDRMDF0_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_0.Reg, volatile.LoadUint32(&o.CFDRMDF0_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_1.Reg, volatile.LoadUint32(&o.CFDRMDF0_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_1.Reg, volatile.LoadUint32(&o.CFDRMDF0_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_1.Reg, volatile.LoadUint32(&o.CFDRMDF0_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_1.Reg, volatile.LoadUint32(&o.CFDRMDF0_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_2.Reg, volatile.LoadUint32(&o.CFDRMDF0_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_2.Reg, volatile.LoadUint32(&o.CFDRMDF0_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_2.Reg, volatile.LoadUint32(&o.CFDRMDF0_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_2.Reg, volatile.LoadUint32(&o.CFDRMDF0_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_3.Reg, volatile.LoadUint32(&o.CFDRMDF0_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_3.Reg, volatile.LoadUint32(&o.CFDRMDF0_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_3.Reg, volatile.LoadUint32(&o.CFDRMDF0_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_3.Reg, volatile.LoadUint32(&o.CFDRMDF0_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_4.Reg, volatile.LoadUint32(&o.CFDRMDF0_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_4.Reg, volatile.LoadUint32(&o.CFDRMDF0_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_4.Reg, volatile.LoadUint32(&o.CFDRMDF0_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_4.Reg, volatile.LoadUint32(&o.CFDRMDF0_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_5.Reg, volatile.LoadUint32(&o.CFDRMDF0_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_5.Reg, volatile.LoadUint32(&o.CFDRMDF0_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_5.Reg, volatile.LoadUint32(&o.CFDRMDF0_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_5.Reg, volatile.LoadUint32(&o.CFDRMDF0_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_6.Reg, volatile.LoadUint32(&o.CFDRMDF0_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_6.Reg, volatile.LoadUint32(&o.CFDRMDF0_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_6.Reg, volatile.LoadUint32(&o.CFDRMDF0_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_6.Reg, volatile.LoadUint32(&o.CFDRMDF0_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_7.Reg, volatile.LoadUint32(&o.CFDRMDF0_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_7.Reg, volatile.LoadUint32(&o.CFDRMDF0_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_7.Reg, volatile.LoadUint32(&o.CFDRMDF0_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_7.Reg, volatile.LoadUint32(&o.CFDRMDF0_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_8.Reg, volatile.LoadUint32(&o.CFDRMDF0_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_8.Reg, volatile.LoadUint32(&o.CFDRMDF0_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_8.Reg, volatile.LoadUint32(&o.CFDRMDF0_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_8.Reg, volatile.LoadUint32(&o.CFDRMDF0_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_9.Reg, volatile.LoadUint32(&o.CFDRMDF0_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_9.Reg, volatile.LoadUint32(&o.CFDRMDF0_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_9.Reg, volatile.LoadUint32(&o.CFDRMDF0_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_9.Reg, volatile.LoadUint32(&o.CFDRMDF0_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_10.Reg, volatile.LoadUint32(&o.CFDRMDF0_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_10.Reg, volatile.LoadUint32(&o.CFDRMDF0_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_10.Reg, volatile.LoadUint32(&o.CFDRMDF0_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_10.Reg, volatile.LoadUint32(&o.CFDRMDF0_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_11.Reg, volatile.LoadUint32(&o.CFDRMDF0_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_11.Reg, volatile.LoadUint32(&o.CFDRMDF0_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_11.Reg, volatile.LoadUint32(&o.CFDRMDF0_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_11.Reg, volatile.LoadUint32(&o.CFDRMDF0_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_12.Reg, volatile.LoadUint32(&o.CFDRMDF0_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_12.Reg, volatile.LoadUint32(&o.CFDRMDF0_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_12.Reg, volatile.LoadUint32(&o.CFDRMDF0_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_12.Reg, volatile.LoadUint32(&o.CFDRMDF0_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_13.Reg, volatile.LoadUint32(&o.CFDRMDF0_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_13.Reg, volatile.LoadUint32(&o.CFDRMDF0_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_13.Reg, volatile.LoadUint32(&o.CFDRMDF0_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_13.Reg, volatile.LoadUint32(&o.CFDRMDF0_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_14.Reg, volatile.LoadUint32(&o.CFDRMDF0_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_14.Reg, volatile.LoadUint32(&o.CFDRMDF0_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_14.Reg, volatile.LoadUint32(&o.CFDRMDF0_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_14.Reg, volatile.LoadUint32(&o.CFDRMDF0_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF0_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF0_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_15.Reg, volatile.LoadUint32(&o.CFDRMDF0_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF0_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF0_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF0_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_15.Reg, volatile.LoadUint32(&o.CFDRMDF0_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF0_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF0_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_15.Reg, volatile.LoadUint32(&o.CFDRMDF0_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF0_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF0_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF0_15.Reg, volatile.LoadUint32(&o.CFDRMDF0_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF0_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF0_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID1: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID1_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID1.Reg, volatile.LoadUint32(&o.CFDRMID1.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID1_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID1.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID1_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID1.Reg, volatile.LoadUint32(&o.CFDRMID1.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID1_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID1.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID1_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID1.Reg, volatile.LoadUint32(&o.CFDRMID1.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID1_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID1.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR1: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR1_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR1.Reg, volatile.LoadUint32(&o.CFDRMPTR1.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR1_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR1.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR1_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR1.Reg, volatile.LoadUint32(&o.CFDRMPTR1.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR1_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR1.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS1: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS1_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS1.Reg, volatile.LoadUint32(&o.CFDRMFDSTS1.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS1_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS1.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS1_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS1.Reg, volatile.LoadUint32(&o.CFDRMFDSTS1.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS1_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS1.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS1_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS1.Reg, volatile.LoadUint32(&o.CFDRMFDSTS1.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS1_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS1.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS1_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS1.Reg, volatile.LoadUint32(&o.CFDRMFDSTS1.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS1_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS1.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS1_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS1.Reg, volatile.LoadUint32(&o.CFDRMFDSTS1.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS1_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS1.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF1_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_0.Reg, volatile.LoadUint32(&o.CFDRMDF1_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_0.Reg, volatile.LoadUint32(&o.CFDRMDF1_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_0.Reg, volatile.LoadUint32(&o.CFDRMDF1_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_0.Reg, volatile.LoadUint32(&o.CFDRMDF1_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_1.Reg, volatile.LoadUint32(&o.CFDRMDF1_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_1.Reg, volatile.LoadUint32(&o.CFDRMDF1_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_1.Reg, volatile.LoadUint32(&o.CFDRMDF1_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_1.Reg, volatile.LoadUint32(&o.CFDRMDF1_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_2.Reg, volatile.LoadUint32(&o.CFDRMDF1_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_2.Reg, volatile.LoadUint32(&o.CFDRMDF1_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_2.Reg, volatile.LoadUint32(&o.CFDRMDF1_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_2.Reg, volatile.LoadUint32(&o.CFDRMDF1_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_3.Reg, volatile.LoadUint32(&o.CFDRMDF1_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_3.Reg, volatile.LoadUint32(&o.CFDRMDF1_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_3.Reg, volatile.LoadUint32(&o.CFDRMDF1_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_3.Reg, volatile.LoadUint32(&o.CFDRMDF1_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_4.Reg, volatile.LoadUint32(&o.CFDRMDF1_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_4.Reg, volatile.LoadUint32(&o.CFDRMDF1_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_4.Reg, volatile.LoadUint32(&o.CFDRMDF1_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_4.Reg, volatile.LoadUint32(&o.CFDRMDF1_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_5.Reg, volatile.LoadUint32(&o.CFDRMDF1_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_5.Reg, volatile.LoadUint32(&o.CFDRMDF1_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_5.Reg, volatile.LoadUint32(&o.CFDRMDF1_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_5.Reg, volatile.LoadUint32(&o.CFDRMDF1_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_6.Reg, volatile.LoadUint32(&o.CFDRMDF1_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_6.Reg, volatile.LoadUint32(&o.CFDRMDF1_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_6.Reg, volatile.LoadUint32(&o.CFDRMDF1_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_6.Reg, volatile.LoadUint32(&o.CFDRMDF1_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_7.Reg, volatile.LoadUint32(&o.CFDRMDF1_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_7.Reg, volatile.LoadUint32(&o.CFDRMDF1_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_7.Reg, volatile.LoadUint32(&o.CFDRMDF1_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_7.Reg, volatile.LoadUint32(&o.CFDRMDF1_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_8.Reg, volatile.LoadUint32(&o.CFDRMDF1_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_8.Reg, volatile.LoadUint32(&o.CFDRMDF1_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_8.Reg, volatile.LoadUint32(&o.CFDRMDF1_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_8.Reg, volatile.LoadUint32(&o.CFDRMDF1_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_9.Reg, volatile.LoadUint32(&o.CFDRMDF1_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_9.Reg, volatile.LoadUint32(&o.CFDRMDF1_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_9.Reg, volatile.LoadUint32(&o.CFDRMDF1_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_9.Reg, volatile.LoadUint32(&o.CFDRMDF1_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_10.Reg, volatile.LoadUint32(&o.CFDRMDF1_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_10.Reg, volatile.LoadUint32(&o.CFDRMDF1_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_10.Reg, volatile.LoadUint32(&o.CFDRMDF1_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_10.Reg, volatile.LoadUint32(&o.CFDRMDF1_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_11.Reg, volatile.LoadUint32(&o.CFDRMDF1_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_11.Reg, volatile.LoadUint32(&o.CFDRMDF1_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_11.Reg, volatile.LoadUint32(&o.CFDRMDF1_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_11.Reg, volatile.LoadUint32(&o.CFDRMDF1_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_12.Reg, volatile.LoadUint32(&o.CFDRMDF1_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_12.Reg, volatile.LoadUint32(&o.CFDRMDF1_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_12.Reg, volatile.LoadUint32(&o.CFDRMDF1_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_12.Reg, volatile.LoadUint32(&o.CFDRMDF1_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_13.Reg, volatile.LoadUint32(&o.CFDRMDF1_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_13.Reg, volatile.LoadUint32(&o.CFDRMDF1_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_13.Reg, volatile.LoadUint32(&o.CFDRMDF1_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_13.Reg, volatile.LoadUint32(&o.CFDRMDF1_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_14.Reg, volatile.LoadUint32(&o.CFDRMDF1_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_14.Reg, volatile.LoadUint32(&o.CFDRMDF1_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_14.Reg, volatile.LoadUint32(&o.CFDRMDF1_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_14.Reg, volatile.LoadUint32(&o.CFDRMDF1_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF1_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF1_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_15.Reg, volatile.LoadUint32(&o.CFDRMDF1_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF1_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF1_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF1_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_15.Reg, volatile.LoadUint32(&o.CFDRMDF1_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF1_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF1_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_15.Reg, volatile.LoadUint32(&o.CFDRMDF1_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF1_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF1_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF1_15.Reg, volatile.LoadUint32(&o.CFDRMDF1_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF1_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF1_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID2: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID2_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID2.Reg, volatile.LoadUint32(&o.CFDRMID2.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID2_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID2.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID2_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID2.Reg, volatile.LoadUint32(&o.CFDRMID2.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID2_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID2.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID2_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID2.Reg, volatile.LoadUint32(&o.CFDRMID2.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID2_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID2.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR2: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR2_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR2.Reg, volatile.LoadUint32(&o.CFDRMPTR2.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR2_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR2.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR2_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR2.Reg, volatile.LoadUint32(&o.CFDRMPTR2.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR2_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR2.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS2: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS2_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS2.Reg, volatile.LoadUint32(&o.CFDRMFDSTS2.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS2_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS2.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS2_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS2.Reg, volatile.LoadUint32(&o.CFDRMFDSTS2.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS2_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS2.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS2_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS2.Reg, volatile.LoadUint32(&o.CFDRMFDSTS2.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS2_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS2.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS2_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS2.Reg, volatile.LoadUint32(&o.CFDRMFDSTS2.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS2_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS2.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS2_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS2.Reg, volatile.LoadUint32(&o.CFDRMFDSTS2.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS2_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS2.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF2_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_0.Reg, volatile.LoadUint32(&o.CFDRMDF2_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_0.Reg, volatile.LoadUint32(&o.CFDRMDF2_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_0.Reg, volatile.LoadUint32(&o.CFDRMDF2_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_0.Reg, volatile.LoadUint32(&o.CFDRMDF2_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_1.Reg, volatile.LoadUint32(&o.CFDRMDF2_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_1.Reg, volatile.LoadUint32(&o.CFDRMDF2_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_1.Reg, volatile.LoadUint32(&o.CFDRMDF2_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_1.Reg, volatile.LoadUint32(&o.CFDRMDF2_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_2.Reg, volatile.LoadUint32(&o.CFDRMDF2_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_2.Reg, volatile.LoadUint32(&o.CFDRMDF2_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_2.Reg, volatile.LoadUint32(&o.CFDRMDF2_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_2.Reg, volatile.LoadUint32(&o.CFDRMDF2_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_3.Reg, volatile.LoadUint32(&o.CFDRMDF2_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_3.Reg, volatile.LoadUint32(&o.CFDRMDF2_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_3.Reg, volatile.LoadUint32(&o.CFDRMDF2_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_3.Reg, volatile.LoadUint32(&o.CFDRMDF2_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_4.Reg, volatile.LoadUint32(&o.CFDRMDF2_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_4.Reg, volatile.LoadUint32(&o.CFDRMDF2_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_4.Reg, volatile.LoadUint32(&o.CFDRMDF2_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_4.Reg, volatile.LoadUint32(&o.CFDRMDF2_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_5.Reg, volatile.LoadUint32(&o.CFDRMDF2_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_5.Reg, volatile.LoadUint32(&o.CFDRMDF2_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_5.Reg, volatile.LoadUint32(&o.CFDRMDF2_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_5.Reg, volatile.LoadUint32(&o.CFDRMDF2_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_6.Reg, volatile.LoadUint32(&o.CFDRMDF2_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_6.Reg, volatile.LoadUint32(&o.CFDRMDF2_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_6.Reg, volatile.LoadUint32(&o.CFDRMDF2_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_6.Reg, volatile.LoadUint32(&o.CFDRMDF2_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_7.Reg, volatile.LoadUint32(&o.CFDRMDF2_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_7.Reg, volatile.LoadUint32(&o.CFDRMDF2_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_7.Reg, volatile.LoadUint32(&o.CFDRMDF2_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_7.Reg, volatile.LoadUint32(&o.CFDRMDF2_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_8.Reg, volatile.LoadUint32(&o.CFDRMDF2_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_8.Reg, volatile.LoadUint32(&o.CFDRMDF2_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_8.Reg, volatile.LoadUint32(&o.CFDRMDF2_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_8.Reg, volatile.LoadUint32(&o.CFDRMDF2_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_9.Reg, volatile.LoadUint32(&o.CFDRMDF2_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_9.Reg, volatile.LoadUint32(&o.CFDRMDF2_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_9.Reg, volatile.LoadUint32(&o.CFDRMDF2_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_9.Reg, volatile.LoadUint32(&o.CFDRMDF2_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_10.Reg, volatile.LoadUint32(&o.CFDRMDF2_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_10.Reg, volatile.LoadUint32(&o.CFDRMDF2_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_10.Reg, volatile.LoadUint32(&o.CFDRMDF2_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_10.Reg, volatile.LoadUint32(&o.CFDRMDF2_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_11.Reg, volatile.LoadUint32(&o.CFDRMDF2_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_11.Reg, volatile.LoadUint32(&o.CFDRMDF2_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_11.Reg, volatile.LoadUint32(&o.CFDRMDF2_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_11.Reg, volatile.LoadUint32(&o.CFDRMDF2_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_12.Reg, volatile.LoadUint32(&o.CFDRMDF2_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_12.Reg, volatile.LoadUint32(&o.CFDRMDF2_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_12.Reg, volatile.LoadUint32(&o.CFDRMDF2_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_12.Reg, volatile.LoadUint32(&o.CFDRMDF2_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_13.Reg, volatile.LoadUint32(&o.CFDRMDF2_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_13.Reg, volatile.LoadUint32(&o.CFDRMDF2_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_13.Reg, volatile.LoadUint32(&o.CFDRMDF2_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_13.Reg, volatile.LoadUint32(&o.CFDRMDF2_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_14.Reg, volatile.LoadUint32(&o.CFDRMDF2_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_14.Reg, volatile.LoadUint32(&o.CFDRMDF2_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_14.Reg, volatile.LoadUint32(&o.CFDRMDF2_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_14.Reg, volatile.LoadUint32(&o.CFDRMDF2_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF2_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF2_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_15.Reg, volatile.LoadUint32(&o.CFDRMDF2_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF2_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF2_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF2_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_15.Reg, volatile.LoadUint32(&o.CFDRMDF2_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF2_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF2_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_15.Reg, volatile.LoadUint32(&o.CFDRMDF2_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF2_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF2_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF2_15.Reg, volatile.LoadUint32(&o.CFDRMDF2_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF2_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF2_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID3: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID3_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID3.Reg, volatile.LoadUint32(&o.CFDRMID3.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID3_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID3.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID3_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID3.Reg, volatile.LoadUint32(&o.CFDRMID3.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID3_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID3.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID3_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID3.Reg, volatile.LoadUint32(&o.CFDRMID3.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID3_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID3.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR3: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR3_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR3.Reg, volatile.LoadUint32(&o.CFDRMPTR3.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR3_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR3.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR3_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR3.Reg, volatile.LoadUint32(&o.CFDRMPTR3.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR3_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR3.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS3: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS3_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS3.Reg, volatile.LoadUint32(&o.CFDRMFDSTS3.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS3_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS3.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS3_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS3.Reg, volatile.LoadUint32(&o.CFDRMFDSTS3.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS3_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS3.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS3_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS3.Reg, volatile.LoadUint32(&o.CFDRMFDSTS3.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS3_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS3.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS3_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS3.Reg, volatile.LoadUint32(&o.CFDRMFDSTS3.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS3_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS3.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS3_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS3.Reg, volatile.LoadUint32(&o.CFDRMFDSTS3.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS3_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS3.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF3_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_0.Reg, volatile.LoadUint32(&o.CFDRMDF3_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_0.Reg, volatile.LoadUint32(&o.CFDRMDF3_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_0.Reg, volatile.LoadUint32(&o.CFDRMDF3_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_0.Reg, volatile.LoadUint32(&o.CFDRMDF3_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_1.Reg, volatile.LoadUint32(&o.CFDRMDF3_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_1.Reg, volatile.LoadUint32(&o.CFDRMDF3_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_1.Reg, volatile.LoadUint32(&o.CFDRMDF3_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_1.Reg, volatile.LoadUint32(&o.CFDRMDF3_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_2.Reg, volatile.LoadUint32(&o.CFDRMDF3_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_2.Reg, volatile.LoadUint32(&o.CFDRMDF3_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_2.Reg, volatile.LoadUint32(&o.CFDRMDF3_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_2.Reg, volatile.LoadUint32(&o.CFDRMDF3_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_3.Reg, volatile.LoadUint32(&o.CFDRMDF3_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_3.Reg, volatile.LoadUint32(&o.CFDRMDF3_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_3.Reg, volatile.LoadUint32(&o.CFDRMDF3_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_3.Reg, volatile.LoadUint32(&o.CFDRMDF3_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_4.Reg, volatile.LoadUint32(&o.CFDRMDF3_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_4.Reg, volatile.LoadUint32(&o.CFDRMDF3_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_4.Reg, volatile.LoadUint32(&o.CFDRMDF3_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_4.Reg, volatile.LoadUint32(&o.CFDRMDF3_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_5.Reg, volatile.LoadUint32(&o.CFDRMDF3_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_5.Reg, volatile.LoadUint32(&o.CFDRMDF3_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_5.Reg, volatile.LoadUint32(&o.CFDRMDF3_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_5.Reg, volatile.LoadUint32(&o.CFDRMDF3_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_6.Reg, volatile.LoadUint32(&o.CFDRMDF3_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_6.Reg, volatile.LoadUint32(&o.CFDRMDF3_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_6.Reg, volatile.LoadUint32(&o.CFDRMDF3_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_6.Reg, volatile.LoadUint32(&o.CFDRMDF3_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_7.Reg, volatile.LoadUint32(&o.CFDRMDF3_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_7.Reg, volatile.LoadUint32(&o.CFDRMDF3_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_7.Reg, volatile.LoadUint32(&o.CFDRMDF3_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_7.Reg, volatile.LoadUint32(&o.CFDRMDF3_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_8.Reg, volatile.LoadUint32(&o.CFDRMDF3_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_8.Reg, volatile.LoadUint32(&o.CFDRMDF3_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_8.Reg, volatile.LoadUint32(&o.CFDRMDF3_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_8.Reg, volatile.LoadUint32(&o.CFDRMDF3_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_9.Reg, volatile.LoadUint32(&o.CFDRMDF3_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_9.Reg, volatile.LoadUint32(&o.CFDRMDF3_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_9.Reg, volatile.LoadUint32(&o.CFDRMDF3_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_9.Reg, volatile.LoadUint32(&o.CFDRMDF3_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_10.Reg, volatile.LoadUint32(&o.CFDRMDF3_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_10.Reg, volatile.LoadUint32(&o.CFDRMDF3_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_10.Reg, volatile.LoadUint32(&o.CFDRMDF3_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_10.Reg, volatile.LoadUint32(&o.CFDRMDF3_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_11.Reg, volatile.LoadUint32(&o.CFDRMDF3_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_11.Reg, volatile.LoadUint32(&o.CFDRMDF3_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_11.Reg, volatile.LoadUint32(&o.CFDRMDF3_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_11.Reg, volatile.LoadUint32(&o.CFDRMDF3_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_12.Reg, volatile.LoadUint32(&o.CFDRMDF3_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_12.Reg, volatile.LoadUint32(&o.CFDRMDF3_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_12.Reg, volatile.LoadUint32(&o.CFDRMDF3_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_12.Reg, volatile.LoadUint32(&o.CFDRMDF3_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_13.Reg, volatile.LoadUint32(&o.CFDRMDF3_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_13.Reg, volatile.LoadUint32(&o.CFDRMDF3_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_13.Reg, volatile.LoadUint32(&o.CFDRMDF3_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_13.Reg, volatile.LoadUint32(&o.CFDRMDF3_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_14.Reg, volatile.LoadUint32(&o.CFDRMDF3_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_14.Reg, volatile.LoadUint32(&o.CFDRMDF3_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_14.Reg, volatile.LoadUint32(&o.CFDRMDF3_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_14.Reg, volatile.LoadUint32(&o.CFDRMDF3_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF3_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF3_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_15.Reg, volatile.LoadUint32(&o.CFDRMDF3_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF3_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF3_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF3_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_15.Reg, volatile.LoadUint32(&o.CFDRMDF3_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF3_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF3_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_15.Reg, volatile.LoadUint32(&o.CFDRMDF3_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF3_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF3_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF3_15.Reg, volatile.LoadUint32(&o.CFDRMDF3_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF3_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF3_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID4: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID4_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID4.Reg, volatile.LoadUint32(&o.CFDRMID4.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID4_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID4.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID4_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID4.Reg, volatile.LoadUint32(&o.CFDRMID4.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID4_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID4.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID4_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID4.Reg, volatile.LoadUint32(&o.CFDRMID4.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID4_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID4.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR4: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR4_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR4.Reg, volatile.LoadUint32(&o.CFDRMPTR4.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR4_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR4.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR4_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR4.Reg, volatile.LoadUint32(&o.CFDRMPTR4.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR4_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR4.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS4: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS4_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS4.Reg, volatile.LoadUint32(&o.CFDRMFDSTS4.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS4_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS4.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS4_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS4.Reg, volatile.LoadUint32(&o.CFDRMFDSTS4.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS4_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS4.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS4_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS4.Reg, volatile.LoadUint32(&o.CFDRMFDSTS4.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS4_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS4.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS4_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS4.Reg, volatile.LoadUint32(&o.CFDRMFDSTS4.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS4_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS4.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS4_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS4.Reg, volatile.LoadUint32(&o.CFDRMFDSTS4.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS4_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS4.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF4_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_0.Reg, volatile.LoadUint32(&o.CFDRMDF4_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_0.Reg, volatile.LoadUint32(&o.CFDRMDF4_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_0.Reg, volatile.LoadUint32(&o.CFDRMDF4_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_0.Reg, volatile.LoadUint32(&o.CFDRMDF4_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_1.Reg, volatile.LoadUint32(&o.CFDRMDF4_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_1.Reg, volatile.LoadUint32(&o.CFDRMDF4_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_1.Reg, volatile.LoadUint32(&o.CFDRMDF4_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_1.Reg, volatile.LoadUint32(&o.CFDRMDF4_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_2.Reg, volatile.LoadUint32(&o.CFDRMDF4_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_2.Reg, volatile.LoadUint32(&o.CFDRMDF4_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_2.Reg, volatile.LoadUint32(&o.CFDRMDF4_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_2.Reg, volatile.LoadUint32(&o.CFDRMDF4_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_3.Reg, volatile.LoadUint32(&o.CFDRMDF4_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_3.Reg, volatile.LoadUint32(&o.CFDRMDF4_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_3.Reg, volatile.LoadUint32(&o.CFDRMDF4_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_3.Reg, volatile.LoadUint32(&o.CFDRMDF4_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_4.Reg, volatile.LoadUint32(&o.CFDRMDF4_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_4.Reg, volatile.LoadUint32(&o.CFDRMDF4_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_4.Reg, volatile.LoadUint32(&o.CFDRMDF4_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_4.Reg, volatile.LoadUint32(&o.CFDRMDF4_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_5.Reg, volatile.LoadUint32(&o.CFDRMDF4_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_5.Reg, volatile.LoadUint32(&o.CFDRMDF4_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_5.Reg, volatile.LoadUint32(&o.CFDRMDF4_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_5.Reg, volatile.LoadUint32(&o.CFDRMDF4_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_6.Reg, volatile.LoadUint32(&o.CFDRMDF4_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_6.Reg, volatile.LoadUint32(&o.CFDRMDF4_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_6.Reg, volatile.LoadUint32(&o.CFDRMDF4_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_6.Reg, volatile.LoadUint32(&o.CFDRMDF4_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_7.Reg, volatile.LoadUint32(&o.CFDRMDF4_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_7.Reg, volatile.LoadUint32(&o.CFDRMDF4_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_7.Reg, volatile.LoadUint32(&o.CFDRMDF4_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_7.Reg, volatile.LoadUint32(&o.CFDRMDF4_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_8.Reg, volatile.LoadUint32(&o.CFDRMDF4_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_8.Reg, volatile.LoadUint32(&o.CFDRMDF4_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_8.Reg, volatile.LoadUint32(&o.CFDRMDF4_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_8.Reg, volatile.LoadUint32(&o.CFDRMDF4_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_9.Reg, volatile.LoadUint32(&o.CFDRMDF4_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_9.Reg, volatile.LoadUint32(&o.CFDRMDF4_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_9.Reg, volatile.LoadUint32(&o.CFDRMDF4_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_9.Reg, volatile.LoadUint32(&o.CFDRMDF4_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_10.Reg, volatile.LoadUint32(&o.CFDRMDF4_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_10.Reg, volatile.LoadUint32(&o.CFDRMDF4_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_10.Reg, volatile.LoadUint32(&o.CFDRMDF4_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_10.Reg, volatile.LoadUint32(&o.CFDRMDF4_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_11.Reg, volatile.LoadUint32(&o.CFDRMDF4_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_11.Reg, volatile.LoadUint32(&o.CFDRMDF4_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_11.Reg, volatile.LoadUint32(&o.CFDRMDF4_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_11.Reg, volatile.LoadUint32(&o.CFDRMDF4_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_12.Reg, volatile.LoadUint32(&o.CFDRMDF4_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_12.Reg, volatile.LoadUint32(&o.CFDRMDF4_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_12.Reg, volatile.LoadUint32(&o.CFDRMDF4_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_12.Reg, volatile.LoadUint32(&o.CFDRMDF4_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_13.Reg, volatile.LoadUint32(&o.CFDRMDF4_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_13.Reg, volatile.LoadUint32(&o.CFDRMDF4_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_13.Reg, volatile.LoadUint32(&o.CFDRMDF4_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_13.Reg, volatile.LoadUint32(&o.CFDRMDF4_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_14.Reg, volatile.LoadUint32(&o.CFDRMDF4_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_14.Reg, volatile.LoadUint32(&o.CFDRMDF4_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_14.Reg, volatile.LoadUint32(&o.CFDRMDF4_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_14.Reg, volatile.LoadUint32(&o.CFDRMDF4_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF4_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF4_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_15.Reg, volatile.LoadUint32(&o.CFDRMDF4_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF4_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF4_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF4_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_15.Reg, volatile.LoadUint32(&o.CFDRMDF4_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF4_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF4_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_15.Reg, volatile.LoadUint32(&o.CFDRMDF4_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF4_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF4_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF4_15.Reg, volatile.LoadUint32(&o.CFDRMDF4_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF4_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF4_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID5: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID5_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID5.Reg, volatile.LoadUint32(&o.CFDRMID5.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID5_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID5.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID5_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID5.Reg, volatile.LoadUint32(&o.CFDRMID5.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID5_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID5.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID5_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID5.Reg, volatile.LoadUint32(&o.CFDRMID5.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID5_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID5.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR5: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR5_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR5.Reg, volatile.LoadUint32(&o.CFDRMPTR5.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR5_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR5.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR5_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR5.Reg, volatile.LoadUint32(&o.CFDRMPTR5.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR5_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR5.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS5: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS5_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS5.Reg, volatile.LoadUint32(&o.CFDRMFDSTS5.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS5_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS5.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS5_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS5.Reg, volatile.LoadUint32(&o.CFDRMFDSTS5.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS5_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS5.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS5_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS5.Reg, volatile.LoadUint32(&o.CFDRMFDSTS5.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS5_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS5.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS5_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS5.Reg, volatile.LoadUint32(&o.CFDRMFDSTS5.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS5_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS5.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS5_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS5.Reg, volatile.LoadUint32(&o.CFDRMFDSTS5.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS5_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS5.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF5_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_0.Reg, volatile.LoadUint32(&o.CFDRMDF5_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_0.Reg, volatile.LoadUint32(&o.CFDRMDF5_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_0.Reg, volatile.LoadUint32(&o.CFDRMDF5_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_0.Reg, volatile.LoadUint32(&o.CFDRMDF5_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_1.Reg, volatile.LoadUint32(&o.CFDRMDF5_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_1.Reg, volatile.LoadUint32(&o.CFDRMDF5_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_1.Reg, volatile.LoadUint32(&o.CFDRMDF5_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_1.Reg, volatile.LoadUint32(&o.CFDRMDF5_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_2.Reg, volatile.LoadUint32(&o.CFDRMDF5_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_2.Reg, volatile.LoadUint32(&o.CFDRMDF5_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_2.Reg, volatile.LoadUint32(&o.CFDRMDF5_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_2.Reg, volatile.LoadUint32(&o.CFDRMDF5_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_3.Reg, volatile.LoadUint32(&o.CFDRMDF5_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_3.Reg, volatile.LoadUint32(&o.CFDRMDF5_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_3.Reg, volatile.LoadUint32(&o.CFDRMDF5_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_3.Reg, volatile.LoadUint32(&o.CFDRMDF5_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_4.Reg, volatile.LoadUint32(&o.CFDRMDF5_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_4.Reg, volatile.LoadUint32(&o.CFDRMDF5_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_4.Reg, volatile.LoadUint32(&o.CFDRMDF5_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_4.Reg, volatile.LoadUint32(&o.CFDRMDF5_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_5.Reg, volatile.LoadUint32(&o.CFDRMDF5_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_5.Reg, volatile.LoadUint32(&o.CFDRMDF5_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_5.Reg, volatile.LoadUint32(&o.CFDRMDF5_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_5.Reg, volatile.LoadUint32(&o.CFDRMDF5_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_6.Reg, volatile.LoadUint32(&o.CFDRMDF5_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_6.Reg, volatile.LoadUint32(&o.CFDRMDF5_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_6.Reg, volatile.LoadUint32(&o.CFDRMDF5_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_6.Reg, volatile.LoadUint32(&o.CFDRMDF5_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_7.Reg, volatile.LoadUint32(&o.CFDRMDF5_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_7.Reg, volatile.LoadUint32(&o.CFDRMDF5_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_7.Reg, volatile.LoadUint32(&o.CFDRMDF5_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_7.Reg, volatile.LoadUint32(&o.CFDRMDF5_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_8.Reg, volatile.LoadUint32(&o.CFDRMDF5_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_8.Reg, volatile.LoadUint32(&o.CFDRMDF5_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_8.Reg, volatile.LoadUint32(&o.CFDRMDF5_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_8.Reg, volatile.LoadUint32(&o.CFDRMDF5_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_9.Reg, volatile.LoadUint32(&o.CFDRMDF5_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_9.Reg, volatile.LoadUint32(&o.CFDRMDF5_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_9.Reg, volatile.LoadUint32(&o.CFDRMDF5_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_9.Reg, volatile.LoadUint32(&o.CFDRMDF5_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_10.Reg, volatile.LoadUint32(&o.CFDRMDF5_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_10.Reg, volatile.LoadUint32(&o.CFDRMDF5_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_10.Reg, volatile.LoadUint32(&o.CFDRMDF5_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_10.Reg, volatile.LoadUint32(&o.CFDRMDF5_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_11.Reg, volatile.LoadUint32(&o.CFDRMDF5_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_11.Reg, volatile.LoadUint32(&o.CFDRMDF5_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_11.Reg, volatile.LoadUint32(&o.CFDRMDF5_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_11.Reg, volatile.LoadUint32(&o.CFDRMDF5_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_12.Reg, volatile.LoadUint32(&o.CFDRMDF5_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_12.Reg, volatile.LoadUint32(&o.CFDRMDF5_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_12.Reg, volatile.LoadUint32(&o.CFDRMDF5_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_12.Reg, volatile.LoadUint32(&o.CFDRMDF5_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_13.Reg, volatile.LoadUint32(&o.CFDRMDF5_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_13.Reg, volatile.LoadUint32(&o.CFDRMDF5_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_13.Reg, volatile.LoadUint32(&o.CFDRMDF5_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_13.Reg, volatile.LoadUint32(&o.CFDRMDF5_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_14.Reg, volatile.LoadUint32(&o.CFDRMDF5_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_14.Reg, volatile.LoadUint32(&o.CFDRMDF5_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_14.Reg, volatile.LoadUint32(&o.CFDRMDF5_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_14.Reg, volatile.LoadUint32(&o.CFDRMDF5_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF5_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF5_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_15.Reg, volatile.LoadUint32(&o.CFDRMDF5_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF5_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF5_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF5_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_15.Reg, volatile.LoadUint32(&o.CFDRMDF5_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF5_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF5_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_15.Reg, volatile.LoadUint32(&o.CFDRMDF5_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF5_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF5_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF5_15.Reg, volatile.LoadUint32(&o.CFDRMDF5_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF5_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF5_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID6: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID6_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID6.Reg, volatile.LoadUint32(&o.CFDRMID6.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID6_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID6.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID6_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID6.Reg, volatile.LoadUint32(&o.CFDRMID6.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID6_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID6.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID6_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID6.Reg, volatile.LoadUint32(&o.CFDRMID6.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID6_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID6.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR6: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR6_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR6.Reg, volatile.LoadUint32(&o.CFDRMPTR6.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR6_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR6.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR6_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR6.Reg, volatile.LoadUint32(&o.CFDRMPTR6.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR6_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR6.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS6: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS6_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS6.Reg, volatile.LoadUint32(&o.CFDRMFDSTS6.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS6_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS6.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS6_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS6.Reg, volatile.LoadUint32(&o.CFDRMFDSTS6.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS6_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS6.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS6_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS6.Reg, volatile.LoadUint32(&o.CFDRMFDSTS6.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS6_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS6.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS6_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS6.Reg, volatile.LoadUint32(&o.CFDRMFDSTS6.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS6_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS6.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS6_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS6.Reg, volatile.LoadUint32(&o.CFDRMFDSTS6.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS6_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS6.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF6_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_0.Reg, volatile.LoadUint32(&o.CFDRMDF6_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_0.Reg, volatile.LoadUint32(&o.CFDRMDF6_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_0.Reg, volatile.LoadUint32(&o.CFDRMDF6_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_0.Reg, volatile.LoadUint32(&o.CFDRMDF6_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_1.Reg, volatile.LoadUint32(&o.CFDRMDF6_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_1.Reg, volatile.LoadUint32(&o.CFDRMDF6_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_1.Reg, volatile.LoadUint32(&o.CFDRMDF6_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_1.Reg, volatile.LoadUint32(&o.CFDRMDF6_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_2.Reg, volatile.LoadUint32(&o.CFDRMDF6_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_2.Reg, volatile.LoadUint32(&o.CFDRMDF6_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_2.Reg, volatile.LoadUint32(&o.CFDRMDF6_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_2.Reg, volatile.LoadUint32(&o.CFDRMDF6_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_3.Reg, volatile.LoadUint32(&o.CFDRMDF6_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_3.Reg, volatile.LoadUint32(&o.CFDRMDF6_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_3.Reg, volatile.LoadUint32(&o.CFDRMDF6_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_3.Reg, volatile.LoadUint32(&o.CFDRMDF6_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_4.Reg, volatile.LoadUint32(&o.CFDRMDF6_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_4.Reg, volatile.LoadUint32(&o.CFDRMDF6_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_4.Reg, volatile.LoadUint32(&o.CFDRMDF6_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_4.Reg, volatile.LoadUint32(&o.CFDRMDF6_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_5.Reg, volatile.LoadUint32(&o.CFDRMDF6_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_5.Reg, volatile.LoadUint32(&o.CFDRMDF6_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_5.Reg, volatile.LoadUint32(&o.CFDRMDF6_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_5.Reg, volatile.LoadUint32(&o.CFDRMDF6_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_6.Reg, volatile.LoadUint32(&o.CFDRMDF6_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_6.Reg, volatile.LoadUint32(&o.CFDRMDF6_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_6.Reg, volatile.LoadUint32(&o.CFDRMDF6_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_6.Reg, volatile.LoadUint32(&o.CFDRMDF6_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_7.Reg, volatile.LoadUint32(&o.CFDRMDF6_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_7.Reg, volatile.LoadUint32(&o.CFDRMDF6_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_7.Reg, volatile.LoadUint32(&o.CFDRMDF6_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_7.Reg, volatile.LoadUint32(&o.CFDRMDF6_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_8.Reg, volatile.LoadUint32(&o.CFDRMDF6_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_8.Reg, volatile.LoadUint32(&o.CFDRMDF6_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_8.Reg, volatile.LoadUint32(&o.CFDRMDF6_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_8.Reg, volatile.LoadUint32(&o.CFDRMDF6_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_9.Reg, volatile.LoadUint32(&o.CFDRMDF6_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_9.Reg, volatile.LoadUint32(&o.CFDRMDF6_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_9.Reg, volatile.LoadUint32(&o.CFDRMDF6_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_9.Reg, volatile.LoadUint32(&o.CFDRMDF6_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_10.Reg, volatile.LoadUint32(&o.CFDRMDF6_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_10.Reg, volatile.LoadUint32(&o.CFDRMDF6_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_10.Reg, volatile.LoadUint32(&o.CFDRMDF6_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_10.Reg, volatile.LoadUint32(&o.CFDRMDF6_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_11.Reg, volatile.LoadUint32(&o.CFDRMDF6_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_11.Reg, volatile.LoadUint32(&o.CFDRMDF6_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_11.Reg, volatile.LoadUint32(&o.CFDRMDF6_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_11.Reg, volatile.LoadUint32(&o.CFDRMDF6_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_12.Reg, volatile.LoadUint32(&o.CFDRMDF6_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_12.Reg, volatile.LoadUint32(&o.CFDRMDF6_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_12.Reg, volatile.LoadUint32(&o.CFDRMDF6_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_12.Reg, volatile.LoadUint32(&o.CFDRMDF6_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_13.Reg, volatile.LoadUint32(&o.CFDRMDF6_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_13.Reg, volatile.LoadUint32(&o.CFDRMDF6_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_13.Reg, volatile.LoadUint32(&o.CFDRMDF6_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_13.Reg, volatile.LoadUint32(&o.CFDRMDF6_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_14.Reg, volatile.LoadUint32(&o.CFDRMDF6_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_14.Reg, volatile.LoadUint32(&o.CFDRMDF6_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_14.Reg, volatile.LoadUint32(&o.CFDRMDF6_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_14.Reg, volatile.LoadUint32(&o.CFDRMDF6_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF6_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF6_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_15.Reg, volatile.LoadUint32(&o.CFDRMDF6_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF6_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF6_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF6_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_15.Reg, volatile.LoadUint32(&o.CFDRMDF6_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF6_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF6_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_15.Reg, volatile.LoadUint32(&o.CFDRMDF6_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF6_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF6_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF6_15.Reg, volatile.LoadUint32(&o.CFDRMDF6_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF6_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF6_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID7: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID7_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID7.Reg, volatile.LoadUint32(&o.CFDRMID7.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID7_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID7.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID7_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID7.Reg, volatile.LoadUint32(&o.CFDRMID7.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID7_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID7.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID7_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID7.Reg, volatile.LoadUint32(&o.CFDRMID7.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID7_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID7.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR7: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR7_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR7.Reg, volatile.LoadUint32(&o.CFDRMPTR7.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR7_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR7.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR7_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR7.Reg, volatile.LoadUint32(&o.CFDRMPTR7.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR7_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR7.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS7: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS7_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS7.Reg, volatile.LoadUint32(&o.CFDRMFDSTS7.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS7_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS7.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS7_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS7.Reg, volatile.LoadUint32(&o.CFDRMFDSTS7.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS7_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS7.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS7_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS7.Reg, volatile.LoadUint32(&o.CFDRMFDSTS7.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS7_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS7.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS7_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS7.Reg, volatile.LoadUint32(&o.CFDRMFDSTS7.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS7_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS7.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS7_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS7.Reg, volatile.LoadUint32(&o.CFDRMFDSTS7.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS7_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS7.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF7_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_0.Reg, volatile.LoadUint32(&o.CFDRMDF7_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_0.Reg, volatile.LoadUint32(&o.CFDRMDF7_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_0.Reg, volatile.LoadUint32(&o.CFDRMDF7_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_0.Reg, volatile.LoadUint32(&o.CFDRMDF7_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_1.Reg, volatile.LoadUint32(&o.CFDRMDF7_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_1.Reg, volatile.LoadUint32(&o.CFDRMDF7_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_1.Reg, volatile.LoadUint32(&o.CFDRMDF7_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_1.Reg, volatile.LoadUint32(&o.CFDRMDF7_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_2.Reg, volatile.LoadUint32(&o.CFDRMDF7_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_2.Reg, volatile.LoadUint32(&o.CFDRMDF7_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_2.Reg, volatile.LoadUint32(&o.CFDRMDF7_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_2.Reg, volatile.LoadUint32(&o.CFDRMDF7_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_3.Reg, volatile.LoadUint32(&o.CFDRMDF7_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_3.Reg, volatile.LoadUint32(&o.CFDRMDF7_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_3.Reg, volatile.LoadUint32(&o.CFDRMDF7_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_3.Reg, volatile.LoadUint32(&o.CFDRMDF7_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_4.Reg, volatile.LoadUint32(&o.CFDRMDF7_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_4.Reg, volatile.LoadUint32(&o.CFDRMDF7_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_4.Reg, volatile.LoadUint32(&o.CFDRMDF7_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_4.Reg, volatile.LoadUint32(&o.CFDRMDF7_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_5.Reg, volatile.LoadUint32(&o.CFDRMDF7_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_5.Reg, volatile.LoadUint32(&o.CFDRMDF7_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_5.Reg, volatile.LoadUint32(&o.CFDRMDF7_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_5.Reg, volatile.LoadUint32(&o.CFDRMDF7_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_6.Reg, volatile.LoadUint32(&o.CFDRMDF7_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_6.Reg, volatile.LoadUint32(&o.CFDRMDF7_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_6.Reg, volatile.LoadUint32(&o.CFDRMDF7_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_6.Reg, volatile.LoadUint32(&o.CFDRMDF7_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_7.Reg, volatile.LoadUint32(&o.CFDRMDF7_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_7.Reg, volatile.LoadUint32(&o.CFDRMDF7_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_7.Reg, volatile.LoadUint32(&o.CFDRMDF7_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_7.Reg, volatile.LoadUint32(&o.CFDRMDF7_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_8.Reg, volatile.LoadUint32(&o.CFDRMDF7_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_8.Reg, volatile.LoadUint32(&o.CFDRMDF7_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_8.Reg, volatile.LoadUint32(&o.CFDRMDF7_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_8.Reg, volatile.LoadUint32(&o.CFDRMDF7_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_9.Reg, volatile.LoadUint32(&o.CFDRMDF7_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_9.Reg, volatile.LoadUint32(&o.CFDRMDF7_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_9.Reg, volatile.LoadUint32(&o.CFDRMDF7_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_9.Reg, volatile.LoadUint32(&o.CFDRMDF7_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_10.Reg, volatile.LoadUint32(&o.CFDRMDF7_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_10.Reg, volatile.LoadUint32(&o.CFDRMDF7_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_10.Reg, volatile.LoadUint32(&o.CFDRMDF7_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_10.Reg, volatile.LoadUint32(&o.CFDRMDF7_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_11.Reg, volatile.LoadUint32(&o.CFDRMDF7_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_11.Reg, volatile.LoadUint32(&o.CFDRMDF7_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_11.Reg, volatile.LoadUint32(&o.CFDRMDF7_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_11.Reg, volatile.LoadUint32(&o.CFDRMDF7_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_12.Reg, volatile.LoadUint32(&o.CFDRMDF7_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_12.Reg, volatile.LoadUint32(&o.CFDRMDF7_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_12.Reg, volatile.LoadUint32(&o.CFDRMDF7_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_12.Reg, volatile.LoadUint32(&o.CFDRMDF7_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_13.Reg, volatile.LoadUint32(&o.CFDRMDF7_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_13.Reg, volatile.LoadUint32(&o.CFDRMDF7_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_13.Reg, volatile.LoadUint32(&o.CFDRMDF7_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_13.Reg, volatile.LoadUint32(&o.CFDRMDF7_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_14.Reg, volatile.LoadUint32(&o.CFDRMDF7_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_14.Reg, volatile.LoadUint32(&o.CFDRMDF7_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_14.Reg, volatile.LoadUint32(&o.CFDRMDF7_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_14.Reg, volatile.LoadUint32(&o.CFDRMDF7_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF7_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF7_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_15.Reg, volatile.LoadUint32(&o.CFDRMDF7_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF7_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF7_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF7_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_15.Reg, volatile.LoadUint32(&o.CFDRMDF7_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF7_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF7_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_15.Reg, volatile.LoadUint32(&o.CFDRMDF7_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF7_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF7_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF7_15.Reg, volatile.LoadUint32(&o.CFDRMDF7_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF7_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF7_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID8: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID8_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID8.Reg, volatile.LoadUint32(&o.CFDRMID8.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID8_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID8.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID8_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID8.Reg, volatile.LoadUint32(&o.CFDRMID8.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID8_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID8.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID8_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID8.Reg, volatile.LoadUint32(&o.CFDRMID8.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID8_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID8.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR8: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR8_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR8.Reg, volatile.LoadUint32(&o.CFDRMPTR8.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR8_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR8.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR8_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR8.Reg, volatile.LoadUint32(&o.CFDRMPTR8.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR8_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR8.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS8: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS8_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS8.Reg, volatile.LoadUint32(&o.CFDRMFDSTS8.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS8_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS8.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS8_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS8.Reg, volatile.LoadUint32(&o.CFDRMFDSTS8.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS8_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS8.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS8_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS8.Reg, volatile.LoadUint32(&o.CFDRMFDSTS8.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS8_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS8.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS8_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS8.Reg, volatile.LoadUint32(&o.CFDRMFDSTS8.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS8_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS8.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS8_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS8.Reg, volatile.LoadUint32(&o.CFDRMFDSTS8.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS8_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS8.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF8_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_0.Reg, volatile.LoadUint32(&o.CFDRMDF8_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_0.Reg, volatile.LoadUint32(&o.CFDRMDF8_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_0.Reg, volatile.LoadUint32(&o.CFDRMDF8_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_0.Reg, volatile.LoadUint32(&o.CFDRMDF8_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_1.Reg, volatile.LoadUint32(&o.CFDRMDF8_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_1.Reg, volatile.LoadUint32(&o.CFDRMDF8_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_1.Reg, volatile.LoadUint32(&o.CFDRMDF8_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_1.Reg, volatile.LoadUint32(&o.CFDRMDF8_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_2.Reg, volatile.LoadUint32(&o.CFDRMDF8_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_2.Reg, volatile.LoadUint32(&o.CFDRMDF8_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_2.Reg, volatile.LoadUint32(&o.CFDRMDF8_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_2.Reg, volatile.LoadUint32(&o.CFDRMDF8_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_3.Reg, volatile.LoadUint32(&o.CFDRMDF8_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_3.Reg, volatile.LoadUint32(&o.CFDRMDF8_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_3.Reg, volatile.LoadUint32(&o.CFDRMDF8_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_3.Reg, volatile.LoadUint32(&o.CFDRMDF8_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_4.Reg, volatile.LoadUint32(&o.CFDRMDF8_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_4.Reg, volatile.LoadUint32(&o.CFDRMDF8_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_4.Reg, volatile.LoadUint32(&o.CFDRMDF8_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_4.Reg, volatile.LoadUint32(&o.CFDRMDF8_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_5.Reg, volatile.LoadUint32(&o.CFDRMDF8_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_5.Reg, volatile.LoadUint32(&o.CFDRMDF8_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_5.Reg, volatile.LoadUint32(&o.CFDRMDF8_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_5.Reg, volatile.LoadUint32(&o.CFDRMDF8_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_6.Reg, volatile.LoadUint32(&o.CFDRMDF8_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_6.Reg, volatile.LoadUint32(&o.CFDRMDF8_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_6.Reg, volatile.LoadUint32(&o.CFDRMDF8_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_6.Reg, volatile.LoadUint32(&o.CFDRMDF8_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_7.Reg, volatile.LoadUint32(&o.CFDRMDF8_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_7.Reg, volatile.LoadUint32(&o.CFDRMDF8_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_7.Reg, volatile.LoadUint32(&o.CFDRMDF8_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_7.Reg, volatile.LoadUint32(&o.CFDRMDF8_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_8.Reg, volatile.LoadUint32(&o.CFDRMDF8_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_8.Reg, volatile.LoadUint32(&o.CFDRMDF8_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_8.Reg, volatile.LoadUint32(&o.CFDRMDF8_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_8.Reg, volatile.LoadUint32(&o.CFDRMDF8_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_9.Reg, volatile.LoadUint32(&o.CFDRMDF8_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_9.Reg, volatile.LoadUint32(&o.CFDRMDF8_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_9.Reg, volatile.LoadUint32(&o.CFDRMDF8_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_9.Reg, volatile.LoadUint32(&o.CFDRMDF8_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_10.Reg, volatile.LoadUint32(&o.CFDRMDF8_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_10.Reg, volatile.LoadUint32(&o.CFDRMDF8_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_10.Reg, volatile.LoadUint32(&o.CFDRMDF8_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_10.Reg, volatile.LoadUint32(&o.CFDRMDF8_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_11.Reg, volatile.LoadUint32(&o.CFDRMDF8_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_11.Reg, volatile.LoadUint32(&o.CFDRMDF8_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_11.Reg, volatile.LoadUint32(&o.CFDRMDF8_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_11.Reg, volatile.LoadUint32(&o.CFDRMDF8_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_12.Reg, volatile.LoadUint32(&o.CFDRMDF8_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_12.Reg, volatile.LoadUint32(&o.CFDRMDF8_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_12.Reg, volatile.LoadUint32(&o.CFDRMDF8_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_12.Reg, volatile.LoadUint32(&o.CFDRMDF8_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_13.Reg, volatile.LoadUint32(&o.CFDRMDF8_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_13.Reg, volatile.LoadUint32(&o.CFDRMDF8_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_13.Reg, volatile.LoadUint32(&o.CFDRMDF8_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_13.Reg, volatile.LoadUint32(&o.CFDRMDF8_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_14.Reg, volatile.LoadUint32(&o.CFDRMDF8_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_14.Reg, volatile.LoadUint32(&o.CFDRMDF8_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_14.Reg, volatile.LoadUint32(&o.CFDRMDF8_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_14.Reg, volatile.LoadUint32(&o.CFDRMDF8_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF8_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF8_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_15.Reg, volatile.LoadUint32(&o.CFDRMDF8_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF8_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF8_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF8_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_15.Reg, volatile.LoadUint32(&o.CFDRMDF8_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF8_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF8_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_15.Reg, volatile.LoadUint32(&o.CFDRMDF8_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF8_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF8_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF8_15.Reg, volatile.LoadUint32(&o.CFDRMDF8_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF8_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF8_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID9: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID9_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID9.Reg, volatile.LoadUint32(&o.CFDRMID9.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID9_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID9.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID9_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID9.Reg, volatile.LoadUint32(&o.CFDRMID9.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID9_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID9.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID9_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID9.Reg, volatile.LoadUint32(&o.CFDRMID9.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID9_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID9.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR9: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR9_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR9.Reg, volatile.LoadUint32(&o.CFDRMPTR9.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR9_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR9.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR9_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR9.Reg, volatile.LoadUint32(&o.CFDRMPTR9.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR9_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR9.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS9: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS9_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS9.Reg, volatile.LoadUint32(&o.CFDRMFDSTS9.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS9_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS9.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS9_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS9.Reg, volatile.LoadUint32(&o.CFDRMFDSTS9.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS9_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS9.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS9_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS9.Reg, volatile.LoadUint32(&o.CFDRMFDSTS9.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS9_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS9.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS9_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS9.Reg, volatile.LoadUint32(&o.CFDRMFDSTS9.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS9_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS9.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS9_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS9.Reg, volatile.LoadUint32(&o.CFDRMFDSTS9.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS9_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS9.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF9_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_0.Reg, volatile.LoadUint32(&o.CFDRMDF9_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_0.Reg, volatile.LoadUint32(&o.CFDRMDF9_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_0.Reg, volatile.LoadUint32(&o.CFDRMDF9_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_0.Reg, volatile.LoadUint32(&o.CFDRMDF9_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_1.Reg, volatile.LoadUint32(&o.CFDRMDF9_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_1.Reg, volatile.LoadUint32(&o.CFDRMDF9_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_1.Reg, volatile.LoadUint32(&o.CFDRMDF9_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_1.Reg, volatile.LoadUint32(&o.CFDRMDF9_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_2.Reg, volatile.LoadUint32(&o.CFDRMDF9_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_2.Reg, volatile.LoadUint32(&o.CFDRMDF9_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_2.Reg, volatile.LoadUint32(&o.CFDRMDF9_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_2.Reg, volatile.LoadUint32(&o.CFDRMDF9_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_3.Reg, volatile.LoadUint32(&o.CFDRMDF9_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_3.Reg, volatile.LoadUint32(&o.CFDRMDF9_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_3.Reg, volatile.LoadUint32(&o.CFDRMDF9_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_3.Reg, volatile.LoadUint32(&o.CFDRMDF9_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_4.Reg, volatile.LoadUint32(&o.CFDRMDF9_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_4.Reg, volatile.LoadUint32(&o.CFDRMDF9_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_4.Reg, volatile.LoadUint32(&o.CFDRMDF9_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_4.Reg, volatile.LoadUint32(&o.CFDRMDF9_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_5.Reg, volatile.LoadUint32(&o.CFDRMDF9_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_5.Reg, volatile.LoadUint32(&o.CFDRMDF9_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_5.Reg, volatile.LoadUint32(&o.CFDRMDF9_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_5.Reg, volatile.LoadUint32(&o.CFDRMDF9_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_6.Reg, volatile.LoadUint32(&o.CFDRMDF9_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_6.Reg, volatile.LoadUint32(&o.CFDRMDF9_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_6.Reg, volatile.LoadUint32(&o.CFDRMDF9_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_6.Reg, volatile.LoadUint32(&o.CFDRMDF9_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_7.Reg, volatile.LoadUint32(&o.CFDRMDF9_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_7.Reg, volatile.LoadUint32(&o.CFDRMDF9_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_7.Reg, volatile.LoadUint32(&o.CFDRMDF9_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_7.Reg, volatile.LoadUint32(&o.CFDRMDF9_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_8.Reg, volatile.LoadUint32(&o.CFDRMDF9_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_8.Reg, volatile.LoadUint32(&o.CFDRMDF9_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_8.Reg, volatile.LoadUint32(&o.CFDRMDF9_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_8.Reg, volatile.LoadUint32(&o.CFDRMDF9_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_9.Reg, volatile.LoadUint32(&o.CFDRMDF9_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_9.Reg, volatile.LoadUint32(&o.CFDRMDF9_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_9.Reg, volatile.LoadUint32(&o.CFDRMDF9_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_9.Reg, volatile.LoadUint32(&o.CFDRMDF9_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_10.Reg, volatile.LoadUint32(&o.CFDRMDF9_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_10.Reg, volatile.LoadUint32(&o.CFDRMDF9_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_10.Reg, volatile.LoadUint32(&o.CFDRMDF9_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_10.Reg, volatile.LoadUint32(&o.CFDRMDF9_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_11.Reg, volatile.LoadUint32(&o.CFDRMDF9_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_11.Reg, volatile.LoadUint32(&o.CFDRMDF9_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_11.Reg, volatile.LoadUint32(&o.CFDRMDF9_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_11.Reg, volatile.LoadUint32(&o.CFDRMDF9_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_12.Reg, volatile.LoadUint32(&o.CFDRMDF9_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_12.Reg, volatile.LoadUint32(&o.CFDRMDF9_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_12.Reg, volatile.LoadUint32(&o.CFDRMDF9_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_12.Reg, volatile.LoadUint32(&o.CFDRMDF9_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_13.Reg, volatile.LoadUint32(&o.CFDRMDF9_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_13.Reg, volatile.LoadUint32(&o.CFDRMDF9_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_13.Reg, volatile.LoadUint32(&o.CFDRMDF9_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_13.Reg, volatile.LoadUint32(&o.CFDRMDF9_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_14.Reg, volatile.LoadUint32(&o.CFDRMDF9_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_14.Reg, volatile.LoadUint32(&o.CFDRMDF9_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_14.Reg, volatile.LoadUint32(&o.CFDRMDF9_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_14.Reg, volatile.LoadUint32(&o.CFDRMDF9_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF9_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF9_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_15.Reg, volatile.LoadUint32(&o.CFDRMDF9_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF9_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF9_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF9_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_15.Reg, volatile.LoadUint32(&o.CFDRMDF9_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF9_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF9_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_15.Reg, volatile.LoadUint32(&o.CFDRMDF9_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF9_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF9_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF9_15.Reg, volatile.LoadUint32(&o.CFDRMDF9_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF9_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF9_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID10: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID10_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID10.Reg, volatile.LoadUint32(&o.CFDRMID10.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID10_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID10.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID10_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID10.Reg, volatile.LoadUint32(&o.CFDRMID10.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID10_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID10.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID10_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID10.Reg, volatile.LoadUint32(&o.CFDRMID10.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID10_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID10.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR10: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR10_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR10.Reg, volatile.LoadUint32(&o.CFDRMPTR10.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR10_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR10.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR10_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR10.Reg, volatile.LoadUint32(&o.CFDRMPTR10.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR10_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR10.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS10: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS10_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS10.Reg, volatile.LoadUint32(&o.CFDRMFDSTS10.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS10_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS10.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS10_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS10.Reg, volatile.LoadUint32(&o.CFDRMFDSTS10.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS10_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS10.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS10_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS10.Reg, volatile.LoadUint32(&o.CFDRMFDSTS10.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS10_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS10.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS10_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS10.Reg, volatile.LoadUint32(&o.CFDRMFDSTS10.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS10_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS10.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS10_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS10.Reg, volatile.LoadUint32(&o.CFDRMFDSTS10.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS10_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS10.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF10_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_0.Reg, volatile.LoadUint32(&o.CFDRMDF10_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_0.Reg, volatile.LoadUint32(&o.CFDRMDF10_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_0.Reg, volatile.LoadUint32(&o.CFDRMDF10_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_0.Reg, volatile.LoadUint32(&o.CFDRMDF10_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_1.Reg, volatile.LoadUint32(&o.CFDRMDF10_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_1.Reg, volatile.LoadUint32(&o.CFDRMDF10_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_1.Reg, volatile.LoadUint32(&o.CFDRMDF10_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_1.Reg, volatile.LoadUint32(&o.CFDRMDF10_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_2.Reg, volatile.LoadUint32(&o.CFDRMDF10_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_2.Reg, volatile.LoadUint32(&o.CFDRMDF10_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_2.Reg, volatile.LoadUint32(&o.CFDRMDF10_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_2.Reg, volatile.LoadUint32(&o.CFDRMDF10_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_3.Reg, volatile.LoadUint32(&o.CFDRMDF10_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_3.Reg, volatile.LoadUint32(&o.CFDRMDF10_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_3.Reg, volatile.LoadUint32(&o.CFDRMDF10_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_3.Reg, volatile.LoadUint32(&o.CFDRMDF10_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_4.Reg, volatile.LoadUint32(&o.CFDRMDF10_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_4.Reg, volatile.LoadUint32(&o.CFDRMDF10_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_4.Reg, volatile.LoadUint32(&o.CFDRMDF10_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_4.Reg, volatile.LoadUint32(&o.CFDRMDF10_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_5.Reg, volatile.LoadUint32(&o.CFDRMDF10_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_5.Reg, volatile.LoadUint32(&o.CFDRMDF10_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_5.Reg, volatile.LoadUint32(&o.CFDRMDF10_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_5.Reg, volatile.LoadUint32(&o.CFDRMDF10_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_6.Reg, volatile.LoadUint32(&o.CFDRMDF10_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_6.Reg, volatile.LoadUint32(&o.CFDRMDF10_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_6.Reg, volatile.LoadUint32(&o.CFDRMDF10_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_6.Reg, volatile.LoadUint32(&o.CFDRMDF10_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_7.Reg, volatile.LoadUint32(&o.CFDRMDF10_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_7.Reg, volatile.LoadUint32(&o.CFDRMDF10_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_7.Reg, volatile.LoadUint32(&o.CFDRMDF10_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_7.Reg, volatile.LoadUint32(&o.CFDRMDF10_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_8.Reg, volatile.LoadUint32(&o.CFDRMDF10_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_8.Reg, volatile.LoadUint32(&o.CFDRMDF10_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_8.Reg, volatile.LoadUint32(&o.CFDRMDF10_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_8.Reg, volatile.LoadUint32(&o.CFDRMDF10_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_9.Reg, volatile.LoadUint32(&o.CFDRMDF10_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_9.Reg, volatile.LoadUint32(&o.CFDRMDF10_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_9.Reg, volatile.LoadUint32(&o.CFDRMDF10_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_9.Reg, volatile.LoadUint32(&o.CFDRMDF10_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_10.Reg, volatile.LoadUint32(&o.CFDRMDF10_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_10.Reg, volatile.LoadUint32(&o.CFDRMDF10_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_10.Reg, volatile.LoadUint32(&o.CFDRMDF10_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_10.Reg, volatile.LoadUint32(&o.CFDRMDF10_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_11.Reg, volatile.LoadUint32(&o.CFDRMDF10_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_11.Reg, volatile.LoadUint32(&o.CFDRMDF10_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_11.Reg, volatile.LoadUint32(&o.CFDRMDF10_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_11.Reg, volatile.LoadUint32(&o.CFDRMDF10_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_12.Reg, volatile.LoadUint32(&o.CFDRMDF10_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_12.Reg, volatile.LoadUint32(&o.CFDRMDF10_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_12.Reg, volatile.LoadUint32(&o.CFDRMDF10_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_12.Reg, volatile.LoadUint32(&o.CFDRMDF10_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_13.Reg, volatile.LoadUint32(&o.CFDRMDF10_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_13.Reg, volatile.LoadUint32(&o.CFDRMDF10_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_13.Reg, volatile.LoadUint32(&o.CFDRMDF10_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_13.Reg, volatile.LoadUint32(&o.CFDRMDF10_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_14.Reg, volatile.LoadUint32(&o.CFDRMDF10_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_14.Reg, volatile.LoadUint32(&o.CFDRMDF10_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_14.Reg, volatile.LoadUint32(&o.CFDRMDF10_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_14.Reg, volatile.LoadUint32(&o.CFDRMDF10_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF10_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF10_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_15.Reg, volatile.LoadUint32(&o.CFDRMDF10_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF10_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF10_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF10_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_15.Reg, volatile.LoadUint32(&o.CFDRMDF10_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF10_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF10_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_15.Reg, volatile.LoadUint32(&o.CFDRMDF10_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF10_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF10_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF10_15.Reg, volatile.LoadUint32(&o.CFDRMDF10_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF10_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF10_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID11: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID11_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID11.Reg, volatile.LoadUint32(&o.CFDRMID11.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID11_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID11.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID11_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID11.Reg, volatile.LoadUint32(&o.CFDRMID11.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID11_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID11.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID11_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID11.Reg, volatile.LoadUint32(&o.CFDRMID11.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID11_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID11.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR11: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR11_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR11.Reg, volatile.LoadUint32(&o.CFDRMPTR11.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR11_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR11.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR11_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR11.Reg, volatile.LoadUint32(&o.CFDRMPTR11.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR11_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR11.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS11: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS11_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS11.Reg, volatile.LoadUint32(&o.CFDRMFDSTS11.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS11_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS11.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS11_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS11.Reg, volatile.LoadUint32(&o.CFDRMFDSTS11.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS11_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS11.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS11_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS11.Reg, volatile.LoadUint32(&o.CFDRMFDSTS11.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS11_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS11.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS11_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS11.Reg, volatile.LoadUint32(&o.CFDRMFDSTS11.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS11_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS11.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS11_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS11.Reg, volatile.LoadUint32(&o.CFDRMFDSTS11.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS11_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS11.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF11_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_0.Reg, volatile.LoadUint32(&o.CFDRMDF11_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_0.Reg, volatile.LoadUint32(&o.CFDRMDF11_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_0.Reg, volatile.LoadUint32(&o.CFDRMDF11_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_0.Reg, volatile.LoadUint32(&o.CFDRMDF11_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_1.Reg, volatile.LoadUint32(&o.CFDRMDF11_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_1.Reg, volatile.LoadUint32(&o.CFDRMDF11_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_1.Reg, volatile.LoadUint32(&o.CFDRMDF11_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_1.Reg, volatile.LoadUint32(&o.CFDRMDF11_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_2.Reg, volatile.LoadUint32(&o.CFDRMDF11_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_2.Reg, volatile.LoadUint32(&o.CFDRMDF11_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_2.Reg, volatile.LoadUint32(&o.CFDRMDF11_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_2.Reg, volatile.LoadUint32(&o.CFDRMDF11_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_3.Reg, volatile.LoadUint32(&o.CFDRMDF11_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_3.Reg, volatile.LoadUint32(&o.CFDRMDF11_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_3.Reg, volatile.LoadUint32(&o.CFDRMDF11_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_3.Reg, volatile.LoadUint32(&o.CFDRMDF11_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_4.Reg, volatile.LoadUint32(&o.CFDRMDF11_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_4.Reg, volatile.LoadUint32(&o.CFDRMDF11_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_4.Reg, volatile.LoadUint32(&o.CFDRMDF11_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_4.Reg, volatile.LoadUint32(&o.CFDRMDF11_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_5.Reg, volatile.LoadUint32(&o.CFDRMDF11_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_5.Reg, volatile.LoadUint32(&o.CFDRMDF11_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_5.Reg, volatile.LoadUint32(&o.CFDRMDF11_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_5.Reg, volatile.LoadUint32(&o.CFDRMDF11_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_6.Reg, volatile.LoadUint32(&o.CFDRMDF11_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_6.Reg, volatile.LoadUint32(&o.CFDRMDF11_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_6.Reg, volatile.LoadUint32(&o.CFDRMDF11_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_6.Reg, volatile.LoadUint32(&o.CFDRMDF11_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_7.Reg, volatile.LoadUint32(&o.CFDRMDF11_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_7.Reg, volatile.LoadUint32(&o.CFDRMDF11_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_7.Reg, volatile.LoadUint32(&o.CFDRMDF11_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_7.Reg, volatile.LoadUint32(&o.CFDRMDF11_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_8.Reg, volatile.LoadUint32(&o.CFDRMDF11_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_8.Reg, volatile.LoadUint32(&o.CFDRMDF11_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_8.Reg, volatile.LoadUint32(&o.CFDRMDF11_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_8.Reg, volatile.LoadUint32(&o.CFDRMDF11_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_9.Reg, volatile.LoadUint32(&o.CFDRMDF11_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_9.Reg, volatile.LoadUint32(&o.CFDRMDF11_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_9.Reg, volatile.LoadUint32(&o.CFDRMDF11_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_9.Reg, volatile.LoadUint32(&o.CFDRMDF11_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_10.Reg, volatile.LoadUint32(&o.CFDRMDF11_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_10.Reg, volatile.LoadUint32(&o.CFDRMDF11_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_10.Reg, volatile.LoadUint32(&o.CFDRMDF11_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_10.Reg, volatile.LoadUint32(&o.CFDRMDF11_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_11.Reg, volatile.LoadUint32(&o.CFDRMDF11_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_11.Reg, volatile.LoadUint32(&o.CFDRMDF11_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_11.Reg, volatile.LoadUint32(&o.CFDRMDF11_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_11.Reg, volatile.LoadUint32(&o.CFDRMDF11_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_12.Reg, volatile.LoadUint32(&o.CFDRMDF11_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_12.Reg, volatile.LoadUint32(&o.CFDRMDF11_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_12.Reg, volatile.LoadUint32(&o.CFDRMDF11_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_12.Reg, volatile.LoadUint32(&o.CFDRMDF11_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_13.Reg, volatile.LoadUint32(&o.CFDRMDF11_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_13.Reg, volatile.LoadUint32(&o.CFDRMDF11_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_13.Reg, volatile.LoadUint32(&o.CFDRMDF11_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_13.Reg, volatile.LoadUint32(&o.CFDRMDF11_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_14.Reg, volatile.LoadUint32(&o.CFDRMDF11_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_14.Reg, volatile.LoadUint32(&o.CFDRMDF11_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_14.Reg, volatile.LoadUint32(&o.CFDRMDF11_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_14.Reg, volatile.LoadUint32(&o.CFDRMDF11_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF11_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF11_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_15.Reg, volatile.LoadUint32(&o.CFDRMDF11_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF11_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF11_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF11_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_15.Reg, volatile.LoadUint32(&o.CFDRMDF11_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF11_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF11_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_15.Reg, volatile.LoadUint32(&o.CFDRMDF11_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF11_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF11_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF11_15.Reg, volatile.LoadUint32(&o.CFDRMDF11_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF11_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF11_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID12: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID12_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID12.Reg, volatile.LoadUint32(&o.CFDRMID12.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID12_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID12.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID12_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID12.Reg, volatile.LoadUint32(&o.CFDRMID12.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID12_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID12.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID12_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID12.Reg, volatile.LoadUint32(&o.CFDRMID12.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID12_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID12.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR12: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR12_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR12.Reg, volatile.LoadUint32(&o.CFDRMPTR12.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR12_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR12.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR12_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR12.Reg, volatile.LoadUint32(&o.CFDRMPTR12.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR12_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR12.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS12: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS12_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS12.Reg, volatile.LoadUint32(&o.CFDRMFDSTS12.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS12_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS12.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS12_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS12.Reg, volatile.LoadUint32(&o.CFDRMFDSTS12.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS12_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS12.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS12_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS12.Reg, volatile.LoadUint32(&o.CFDRMFDSTS12.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS12_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS12.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS12_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS12.Reg, volatile.LoadUint32(&o.CFDRMFDSTS12.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS12_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS12.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS12_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS12.Reg, volatile.LoadUint32(&o.CFDRMFDSTS12.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS12_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS12.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF12_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_0.Reg, volatile.LoadUint32(&o.CFDRMDF12_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_0.Reg, volatile.LoadUint32(&o.CFDRMDF12_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_0.Reg, volatile.LoadUint32(&o.CFDRMDF12_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_0.Reg, volatile.LoadUint32(&o.CFDRMDF12_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_1.Reg, volatile.LoadUint32(&o.CFDRMDF12_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_1.Reg, volatile.LoadUint32(&o.CFDRMDF12_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_1.Reg, volatile.LoadUint32(&o.CFDRMDF12_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_1.Reg, volatile.LoadUint32(&o.CFDRMDF12_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_2.Reg, volatile.LoadUint32(&o.CFDRMDF12_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_2.Reg, volatile.LoadUint32(&o.CFDRMDF12_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_2.Reg, volatile.LoadUint32(&o.CFDRMDF12_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_2.Reg, volatile.LoadUint32(&o.CFDRMDF12_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_3.Reg, volatile.LoadUint32(&o.CFDRMDF12_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_3.Reg, volatile.LoadUint32(&o.CFDRMDF12_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_3.Reg, volatile.LoadUint32(&o.CFDRMDF12_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_3.Reg, volatile.LoadUint32(&o.CFDRMDF12_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_4.Reg, volatile.LoadUint32(&o.CFDRMDF12_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_4.Reg, volatile.LoadUint32(&o.CFDRMDF12_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_4.Reg, volatile.LoadUint32(&o.CFDRMDF12_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_4.Reg, volatile.LoadUint32(&o.CFDRMDF12_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_5.Reg, volatile.LoadUint32(&o.CFDRMDF12_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_5.Reg, volatile.LoadUint32(&o.CFDRMDF12_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_5.Reg, volatile.LoadUint32(&o.CFDRMDF12_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_5.Reg, volatile.LoadUint32(&o.CFDRMDF12_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_6.Reg, volatile.LoadUint32(&o.CFDRMDF12_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_6.Reg, volatile.LoadUint32(&o.CFDRMDF12_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_6.Reg, volatile.LoadUint32(&o.CFDRMDF12_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_6.Reg, volatile.LoadUint32(&o.CFDRMDF12_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_7.Reg, volatile.LoadUint32(&o.CFDRMDF12_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_7.Reg, volatile.LoadUint32(&o.CFDRMDF12_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_7.Reg, volatile.LoadUint32(&o.CFDRMDF12_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_7.Reg, volatile.LoadUint32(&o.CFDRMDF12_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_8.Reg, volatile.LoadUint32(&o.CFDRMDF12_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_8.Reg, volatile.LoadUint32(&o.CFDRMDF12_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_8.Reg, volatile.LoadUint32(&o.CFDRMDF12_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_8.Reg, volatile.LoadUint32(&o.CFDRMDF12_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_9.Reg, volatile.LoadUint32(&o.CFDRMDF12_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_9.Reg, volatile.LoadUint32(&o.CFDRMDF12_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_9.Reg, volatile.LoadUint32(&o.CFDRMDF12_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_9.Reg, volatile.LoadUint32(&o.CFDRMDF12_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_10.Reg, volatile.LoadUint32(&o.CFDRMDF12_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_10.Reg, volatile.LoadUint32(&o.CFDRMDF12_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_10.Reg, volatile.LoadUint32(&o.CFDRMDF12_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_10.Reg, volatile.LoadUint32(&o.CFDRMDF12_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_11.Reg, volatile.LoadUint32(&o.CFDRMDF12_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_11.Reg, volatile.LoadUint32(&o.CFDRMDF12_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_11.Reg, volatile.LoadUint32(&o.CFDRMDF12_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_11.Reg, volatile.LoadUint32(&o.CFDRMDF12_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_12.Reg, volatile.LoadUint32(&o.CFDRMDF12_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_12.Reg, volatile.LoadUint32(&o.CFDRMDF12_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_12.Reg, volatile.LoadUint32(&o.CFDRMDF12_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_12.Reg, volatile.LoadUint32(&o.CFDRMDF12_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_13.Reg, volatile.LoadUint32(&o.CFDRMDF12_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_13.Reg, volatile.LoadUint32(&o.CFDRMDF12_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_13.Reg, volatile.LoadUint32(&o.CFDRMDF12_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_13.Reg, volatile.LoadUint32(&o.CFDRMDF12_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_14.Reg, volatile.LoadUint32(&o.CFDRMDF12_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_14.Reg, volatile.LoadUint32(&o.CFDRMDF12_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_14.Reg, volatile.LoadUint32(&o.CFDRMDF12_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_14.Reg, volatile.LoadUint32(&o.CFDRMDF12_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF12_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF12_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_15.Reg, volatile.LoadUint32(&o.CFDRMDF12_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF12_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF12_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF12_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_15.Reg, volatile.LoadUint32(&o.CFDRMDF12_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF12_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF12_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_15.Reg, volatile.LoadUint32(&o.CFDRMDF12_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF12_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF12_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF12_15.Reg, volatile.LoadUint32(&o.CFDRMDF12_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF12_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF12_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID13: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID13_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID13.Reg, volatile.LoadUint32(&o.CFDRMID13.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID13_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID13.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID13_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID13.Reg, volatile.LoadUint32(&o.CFDRMID13.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID13_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID13.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID13_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID13.Reg, volatile.LoadUint32(&o.CFDRMID13.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID13_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID13.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR13: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR13_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR13.Reg, volatile.LoadUint32(&o.CFDRMPTR13.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR13_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR13.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR13_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR13.Reg, volatile.LoadUint32(&o.CFDRMPTR13.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR13_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR13.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS13: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS13_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS13.Reg, volatile.LoadUint32(&o.CFDRMFDSTS13.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS13_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS13.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS13_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS13.Reg, volatile.LoadUint32(&o.CFDRMFDSTS13.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS13_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS13.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS13_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS13.Reg, volatile.LoadUint32(&o.CFDRMFDSTS13.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS13_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS13.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS13_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS13.Reg, volatile.LoadUint32(&o.CFDRMFDSTS13.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS13_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS13.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS13_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS13.Reg, volatile.LoadUint32(&o.CFDRMFDSTS13.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS13_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS13.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF13_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_0.Reg, volatile.LoadUint32(&o.CFDRMDF13_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_0.Reg, volatile.LoadUint32(&o.CFDRMDF13_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_0.Reg, volatile.LoadUint32(&o.CFDRMDF13_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_0.Reg, volatile.LoadUint32(&o.CFDRMDF13_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_1.Reg, volatile.LoadUint32(&o.CFDRMDF13_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_1.Reg, volatile.LoadUint32(&o.CFDRMDF13_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_1.Reg, volatile.LoadUint32(&o.CFDRMDF13_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_1.Reg, volatile.LoadUint32(&o.CFDRMDF13_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_2.Reg, volatile.LoadUint32(&o.CFDRMDF13_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_2.Reg, volatile.LoadUint32(&o.CFDRMDF13_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_2.Reg, volatile.LoadUint32(&o.CFDRMDF13_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_2.Reg, volatile.LoadUint32(&o.CFDRMDF13_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_3.Reg, volatile.LoadUint32(&o.CFDRMDF13_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_3.Reg, volatile.LoadUint32(&o.CFDRMDF13_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_3.Reg, volatile.LoadUint32(&o.CFDRMDF13_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_3.Reg, volatile.LoadUint32(&o.CFDRMDF13_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_4.Reg, volatile.LoadUint32(&o.CFDRMDF13_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_4.Reg, volatile.LoadUint32(&o.CFDRMDF13_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_4.Reg, volatile.LoadUint32(&o.CFDRMDF13_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_4.Reg, volatile.LoadUint32(&o.CFDRMDF13_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_5.Reg, volatile.LoadUint32(&o.CFDRMDF13_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_5.Reg, volatile.LoadUint32(&o.CFDRMDF13_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_5.Reg, volatile.LoadUint32(&o.CFDRMDF13_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_5.Reg, volatile.LoadUint32(&o.CFDRMDF13_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_6.Reg, volatile.LoadUint32(&o.CFDRMDF13_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_6.Reg, volatile.LoadUint32(&o.CFDRMDF13_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_6.Reg, volatile.LoadUint32(&o.CFDRMDF13_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_6.Reg, volatile.LoadUint32(&o.CFDRMDF13_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_7.Reg, volatile.LoadUint32(&o.CFDRMDF13_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_7.Reg, volatile.LoadUint32(&o.CFDRMDF13_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_7.Reg, volatile.LoadUint32(&o.CFDRMDF13_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_7.Reg, volatile.LoadUint32(&o.CFDRMDF13_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_8.Reg, volatile.LoadUint32(&o.CFDRMDF13_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_8.Reg, volatile.LoadUint32(&o.CFDRMDF13_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_8.Reg, volatile.LoadUint32(&o.CFDRMDF13_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_8.Reg, volatile.LoadUint32(&o.CFDRMDF13_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_9.Reg, volatile.LoadUint32(&o.CFDRMDF13_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_9.Reg, volatile.LoadUint32(&o.CFDRMDF13_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_9.Reg, volatile.LoadUint32(&o.CFDRMDF13_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_9.Reg, volatile.LoadUint32(&o.CFDRMDF13_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_10.Reg, volatile.LoadUint32(&o.CFDRMDF13_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_10.Reg, volatile.LoadUint32(&o.CFDRMDF13_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_10.Reg, volatile.LoadUint32(&o.CFDRMDF13_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_10.Reg, volatile.LoadUint32(&o.CFDRMDF13_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_11.Reg, volatile.LoadUint32(&o.CFDRMDF13_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_11.Reg, volatile.LoadUint32(&o.CFDRMDF13_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_11.Reg, volatile.LoadUint32(&o.CFDRMDF13_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_11.Reg, volatile.LoadUint32(&o.CFDRMDF13_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_12.Reg, volatile.LoadUint32(&o.CFDRMDF13_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_12.Reg, volatile.LoadUint32(&o.CFDRMDF13_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_12.Reg, volatile.LoadUint32(&o.CFDRMDF13_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_12.Reg, volatile.LoadUint32(&o.CFDRMDF13_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_13.Reg, volatile.LoadUint32(&o.CFDRMDF13_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_13.Reg, volatile.LoadUint32(&o.CFDRMDF13_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_13.Reg, volatile.LoadUint32(&o.CFDRMDF13_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_13.Reg, volatile.LoadUint32(&o.CFDRMDF13_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_14.Reg, volatile.LoadUint32(&o.CFDRMDF13_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_14.Reg, volatile.LoadUint32(&o.CFDRMDF13_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_14.Reg, volatile.LoadUint32(&o.CFDRMDF13_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_14.Reg, volatile.LoadUint32(&o.CFDRMDF13_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF13_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF13_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_15.Reg, volatile.LoadUint32(&o.CFDRMDF13_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF13_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF13_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF13_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_15.Reg, volatile.LoadUint32(&o.CFDRMDF13_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF13_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF13_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_15.Reg, volatile.LoadUint32(&o.CFDRMDF13_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF13_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF13_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF13_15.Reg, volatile.LoadUint32(&o.CFDRMDF13_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF13_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF13_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID14: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID14_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID14.Reg, volatile.LoadUint32(&o.CFDRMID14.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID14_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID14.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID14_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID14.Reg, volatile.LoadUint32(&o.CFDRMID14.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID14_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID14.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID14_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID14.Reg, volatile.LoadUint32(&o.CFDRMID14.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID14_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID14.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR14: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR14_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR14.Reg, volatile.LoadUint32(&o.CFDRMPTR14.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR14_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR14.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR14_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR14.Reg, volatile.LoadUint32(&o.CFDRMPTR14.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR14_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR14.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS14: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS14_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS14.Reg, volatile.LoadUint32(&o.CFDRMFDSTS14.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS14_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS14.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS14_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS14.Reg, volatile.LoadUint32(&o.CFDRMFDSTS14.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS14_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS14.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS14_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS14.Reg, volatile.LoadUint32(&o.CFDRMFDSTS14.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS14_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS14.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS14_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS14.Reg, volatile.LoadUint32(&o.CFDRMFDSTS14.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS14_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS14.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS14_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS14.Reg, volatile.LoadUint32(&o.CFDRMFDSTS14.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS14_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS14.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF14_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_0.Reg, volatile.LoadUint32(&o.CFDRMDF14_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_0.Reg, volatile.LoadUint32(&o.CFDRMDF14_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_0.Reg, volatile.LoadUint32(&o.CFDRMDF14_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_0.Reg, volatile.LoadUint32(&o.CFDRMDF14_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_1.Reg, volatile.LoadUint32(&o.CFDRMDF14_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_1.Reg, volatile.LoadUint32(&o.CFDRMDF14_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_1.Reg, volatile.LoadUint32(&o.CFDRMDF14_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_1.Reg, volatile.LoadUint32(&o.CFDRMDF14_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_2.Reg, volatile.LoadUint32(&o.CFDRMDF14_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_2.Reg, volatile.LoadUint32(&o.CFDRMDF14_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_2.Reg, volatile.LoadUint32(&o.CFDRMDF14_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_2.Reg, volatile.LoadUint32(&o.CFDRMDF14_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_3.Reg, volatile.LoadUint32(&o.CFDRMDF14_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_3.Reg, volatile.LoadUint32(&o.CFDRMDF14_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_3.Reg, volatile.LoadUint32(&o.CFDRMDF14_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_3.Reg, volatile.LoadUint32(&o.CFDRMDF14_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_4.Reg, volatile.LoadUint32(&o.CFDRMDF14_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_4.Reg, volatile.LoadUint32(&o.CFDRMDF14_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_4.Reg, volatile.LoadUint32(&o.CFDRMDF14_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_4.Reg, volatile.LoadUint32(&o.CFDRMDF14_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_5.Reg, volatile.LoadUint32(&o.CFDRMDF14_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_5.Reg, volatile.LoadUint32(&o.CFDRMDF14_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_5.Reg, volatile.LoadUint32(&o.CFDRMDF14_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_5.Reg, volatile.LoadUint32(&o.CFDRMDF14_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_6.Reg, volatile.LoadUint32(&o.CFDRMDF14_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_6.Reg, volatile.LoadUint32(&o.CFDRMDF14_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_6.Reg, volatile.LoadUint32(&o.CFDRMDF14_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_6.Reg, volatile.LoadUint32(&o.CFDRMDF14_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_7.Reg, volatile.LoadUint32(&o.CFDRMDF14_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_7.Reg, volatile.LoadUint32(&o.CFDRMDF14_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_7.Reg, volatile.LoadUint32(&o.CFDRMDF14_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_7.Reg, volatile.LoadUint32(&o.CFDRMDF14_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_8.Reg, volatile.LoadUint32(&o.CFDRMDF14_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_8.Reg, volatile.LoadUint32(&o.CFDRMDF14_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_8.Reg, volatile.LoadUint32(&o.CFDRMDF14_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_8.Reg, volatile.LoadUint32(&o.CFDRMDF14_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_9.Reg, volatile.LoadUint32(&o.CFDRMDF14_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_9.Reg, volatile.LoadUint32(&o.CFDRMDF14_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_9.Reg, volatile.LoadUint32(&o.CFDRMDF14_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_9.Reg, volatile.LoadUint32(&o.CFDRMDF14_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_10.Reg, volatile.LoadUint32(&o.CFDRMDF14_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_10.Reg, volatile.LoadUint32(&o.CFDRMDF14_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_10.Reg, volatile.LoadUint32(&o.CFDRMDF14_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_10.Reg, volatile.LoadUint32(&o.CFDRMDF14_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_11.Reg, volatile.LoadUint32(&o.CFDRMDF14_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_11.Reg, volatile.LoadUint32(&o.CFDRMDF14_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_11.Reg, volatile.LoadUint32(&o.CFDRMDF14_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_11.Reg, volatile.LoadUint32(&o.CFDRMDF14_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_12.Reg, volatile.LoadUint32(&o.CFDRMDF14_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_12.Reg, volatile.LoadUint32(&o.CFDRMDF14_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_12.Reg, volatile.LoadUint32(&o.CFDRMDF14_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_12.Reg, volatile.LoadUint32(&o.CFDRMDF14_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_13.Reg, volatile.LoadUint32(&o.CFDRMDF14_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_13.Reg, volatile.LoadUint32(&o.CFDRMDF14_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_13.Reg, volatile.LoadUint32(&o.CFDRMDF14_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_13.Reg, volatile.LoadUint32(&o.CFDRMDF14_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_14.Reg, volatile.LoadUint32(&o.CFDRMDF14_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_14.Reg, volatile.LoadUint32(&o.CFDRMDF14_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_14.Reg, volatile.LoadUint32(&o.CFDRMDF14_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_14.Reg, volatile.LoadUint32(&o.CFDRMDF14_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF14_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF14_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_15.Reg, volatile.LoadUint32(&o.CFDRMDF14_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF14_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF14_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF14_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_15.Reg, volatile.LoadUint32(&o.CFDRMDF14_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF14_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF14_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_15.Reg, volatile.LoadUint32(&o.CFDRMDF14_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF14_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF14_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF14_15.Reg, volatile.LoadUint32(&o.CFDRMDF14_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF14_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF14_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID15: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID15_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID15.Reg, volatile.LoadUint32(&o.CFDRMID15.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID15_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID15.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID15_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID15.Reg, volatile.LoadUint32(&o.CFDRMID15.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID15_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID15.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID15_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID15.Reg, volatile.LoadUint32(&o.CFDRMID15.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID15_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID15.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR15: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR15_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR15.Reg, volatile.LoadUint32(&o.CFDRMPTR15.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR15_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR15.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR15_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR15.Reg, volatile.LoadUint32(&o.CFDRMPTR15.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR15_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR15.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS15: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS15_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS15.Reg, volatile.LoadUint32(&o.CFDRMFDSTS15.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS15_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS15.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS15_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS15.Reg, volatile.LoadUint32(&o.CFDRMFDSTS15.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS15_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS15.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS15_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS15.Reg, volatile.LoadUint32(&o.CFDRMFDSTS15.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS15_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS15.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS15_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS15.Reg, volatile.LoadUint32(&o.CFDRMFDSTS15.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS15_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS15.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS15_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS15.Reg, volatile.LoadUint32(&o.CFDRMFDSTS15.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS15_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS15.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF15_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_0.Reg, volatile.LoadUint32(&o.CFDRMDF15_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_0.Reg, volatile.LoadUint32(&o.CFDRMDF15_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_0.Reg, volatile.LoadUint32(&o.CFDRMDF15_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_0.Reg, volatile.LoadUint32(&o.CFDRMDF15_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_1.Reg, volatile.LoadUint32(&o.CFDRMDF15_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_1.Reg, volatile.LoadUint32(&o.CFDRMDF15_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_1.Reg, volatile.LoadUint32(&o.CFDRMDF15_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_1.Reg, volatile.LoadUint32(&o.CFDRMDF15_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_2.Reg, volatile.LoadUint32(&o.CFDRMDF15_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_2.Reg, volatile.LoadUint32(&o.CFDRMDF15_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_2.Reg, volatile.LoadUint32(&o.CFDRMDF15_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_2.Reg, volatile.LoadUint32(&o.CFDRMDF15_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_3.Reg, volatile.LoadUint32(&o.CFDRMDF15_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_3.Reg, volatile.LoadUint32(&o.CFDRMDF15_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_3.Reg, volatile.LoadUint32(&o.CFDRMDF15_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_3.Reg, volatile.LoadUint32(&o.CFDRMDF15_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_4.Reg, volatile.LoadUint32(&o.CFDRMDF15_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_4.Reg, volatile.LoadUint32(&o.CFDRMDF15_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_4.Reg, volatile.LoadUint32(&o.CFDRMDF15_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_4.Reg, volatile.LoadUint32(&o.CFDRMDF15_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_5.Reg, volatile.LoadUint32(&o.CFDRMDF15_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_5.Reg, volatile.LoadUint32(&o.CFDRMDF15_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_5.Reg, volatile.LoadUint32(&o.CFDRMDF15_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_5.Reg, volatile.LoadUint32(&o.CFDRMDF15_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_6.Reg, volatile.LoadUint32(&o.CFDRMDF15_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_6.Reg, volatile.LoadUint32(&o.CFDRMDF15_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_6.Reg, volatile.LoadUint32(&o.CFDRMDF15_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_6.Reg, volatile.LoadUint32(&o.CFDRMDF15_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_7.Reg, volatile.LoadUint32(&o.CFDRMDF15_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_7.Reg, volatile.LoadUint32(&o.CFDRMDF15_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_7.Reg, volatile.LoadUint32(&o.CFDRMDF15_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_7.Reg, volatile.LoadUint32(&o.CFDRMDF15_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_8.Reg, volatile.LoadUint32(&o.CFDRMDF15_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_8.Reg, volatile.LoadUint32(&o.CFDRMDF15_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_8.Reg, volatile.LoadUint32(&o.CFDRMDF15_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_8.Reg, volatile.LoadUint32(&o.CFDRMDF15_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_9.Reg, volatile.LoadUint32(&o.CFDRMDF15_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_9.Reg, volatile.LoadUint32(&o.CFDRMDF15_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_9.Reg, volatile.LoadUint32(&o.CFDRMDF15_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_9.Reg, volatile.LoadUint32(&o.CFDRMDF15_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_10.Reg, volatile.LoadUint32(&o.CFDRMDF15_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_10.Reg, volatile.LoadUint32(&o.CFDRMDF15_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_10.Reg, volatile.LoadUint32(&o.CFDRMDF15_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_10.Reg, volatile.LoadUint32(&o.CFDRMDF15_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_11.Reg, volatile.LoadUint32(&o.CFDRMDF15_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_11.Reg, volatile.LoadUint32(&o.CFDRMDF15_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_11.Reg, volatile.LoadUint32(&o.CFDRMDF15_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_11.Reg, volatile.LoadUint32(&o.CFDRMDF15_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_12.Reg, volatile.LoadUint32(&o.CFDRMDF15_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_12.Reg, volatile.LoadUint32(&o.CFDRMDF15_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_12.Reg, volatile.LoadUint32(&o.CFDRMDF15_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_12.Reg, volatile.LoadUint32(&o.CFDRMDF15_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_13.Reg, volatile.LoadUint32(&o.CFDRMDF15_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_13.Reg, volatile.LoadUint32(&o.CFDRMDF15_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_13.Reg, volatile.LoadUint32(&o.CFDRMDF15_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_13.Reg, volatile.LoadUint32(&o.CFDRMDF15_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_14.Reg, volatile.LoadUint32(&o.CFDRMDF15_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_14.Reg, volatile.LoadUint32(&o.CFDRMDF15_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_14.Reg, volatile.LoadUint32(&o.CFDRMDF15_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_14.Reg, volatile.LoadUint32(&o.CFDRMDF15_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF15_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF15_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_15.Reg, volatile.LoadUint32(&o.CFDRMDF15_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF15_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF15_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF15_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_15.Reg, volatile.LoadUint32(&o.CFDRMDF15_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF15_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF15_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_15.Reg, volatile.LoadUint32(&o.CFDRMDF15_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF15_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF15_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF15_15.Reg, volatile.LoadUint32(&o.CFDRMDF15_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF15_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF15_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID16: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID16_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID16.Reg, volatile.LoadUint32(&o.CFDRMID16.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID16_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID16.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID16_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID16.Reg, volatile.LoadUint32(&o.CFDRMID16.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID16_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID16.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID16_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID16.Reg, volatile.LoadUint32(&o.CFDRMID16.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID16_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID16.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR16: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR16_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR16.Reg, volatile.LoadUint32(&o.CFDRMPTR16.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR16_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR16.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR16_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR16.Reg, volatile.LoadUint32(&o.CFDRMPTR16.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR16_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR16.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS16: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS16_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS16.Reg, volatile.LoadUint32(&o.CFDRMFDSTS16.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS16_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS16.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS16_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS16.Reg, volatile.LoadUint32(&o.CFDRMFDSTS16.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS16_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS16.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS16_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS16.Reg, volatile.LoadUint32(&o.CFDRMFDSTS16.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS16_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS16.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS16_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS16.Reg, volatile.LoadUint32(&o.CFDRMFDSTS16.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS16_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS16.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS16_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS16.Reg, volatile.LoadUint32(&o.CFDRMFDSTS16.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS16_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS16.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF16_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_0.Reg, volatile.LoadUint32(&o.CFDRMDF16_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_0.Reg, volatile.LoadUint32(&o.CFDRMDF16_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_0.Reg, volatile.LoadUint32(&o.CFDRMDF16_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_0.Reg, volatile.LoadUint32(&o.CFDRMDF16_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_1.Reg, volatile.LoadUint32(&o.CFDRMDF16_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_1.Reg, volatile.LoadUint32(&o.CFDRMDF16_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_1.Reg, volatile.LoadUint32(&o.CFDRMDF16_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_1.Reg, volatile.LoadUint32(&o.CFDRMDF16_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_2.Reg, volatile.LoadUint32(&o.CFDRMDF16_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_2.Reg, volatile.LoadUint32(&o.CFDRMDF16_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_2.Reg, volatile.LoadUint32(&o.CFDRMDF16_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_2.Reg, volatile.LoadUint32(&o.CFDRMDF16_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_3.Reg, volatile.LoadUint32(&o.CFDRMDF16_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_3.Reg, volatile.LoadUint32(&o.CFDRMDF16_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_3.Reg, volatile.LoadUint32(&o.CFDRMDF16_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_3.Reg, volatile.LoadUint32(&o.CFDRMDF16_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_4.Reg, volatile.LoadUint32(&o.CFDRMDF16_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_4.Reg, volatile.LoadUint32(&o.CFDRMDF16_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_4.Reg, volatile.LoadUint32(&o.CFDRMDF16_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_4.Reg, volatile.LoadUint32(&o.CFDRMDF16_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_5.Reg, volatile.LoadUint32(&o.CFDRMDF16_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_5.Reg, volatile.LoadUint32(&o.CFDRMDF16_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_5.Reg, volatile.LoadUint32(&o.CFDRMDF16_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_5.Reg, volatile.LoadUint32(&o.CFDRMDF16_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_6.Reg, volatile.LoadUint32(&o.CFDRMDF16_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_6.Reg, volatile.LoadUint32(&o.CFDRMDF16_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_6.Reg, volatile.LoadUint32(&o.CFDRMDF16_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_6.Reg, volatile.LoadUint32(&o.CFDRMDF16_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_7.Reg, volatile.LoadUint32(&o.CFDRMDF16_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_7.Reg, volatile.LoadUint32(&o.CFDRMDF16_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_7.Reg, volatile.LoadUint32(&o.CFDRMDF16_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_7.Reg, volatile.LoadUint32(&o.CFDRMDF16_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_8.Reg, volatile.LoadUint32(&o.CFDRMDF16_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_8.Reg, volatile.LoadUint32(&o.CFDRMDF16_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_8.Reg, volatile.LoadUint32(&o.CFDRMDF16_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_8.Reg, volatile.LoadUint32(&o.CFDRMDF16_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_9.Reg, volatile.LoadUint32(&o.CFDRMDF16_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_9.Reg, volatile.LoadUint32(&o.CFDRMDF16_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_9.Reg, volatile.LoadUint32(&o.CFDRMDF16_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_9.Reg, volatile.LoadUint32(&o.CFDRMDF16_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_10.Reg, volatile.LoadUint32(&o.CFDRMDF16_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_10.Reg, volatile.LoadUint32(&o.CFDRMDF16_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_10.Reg, volatile.LoadUint32(&o.CFDRMDF16_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_10.Reg, volatile.LoadUint32(&o.CFDRMDF16_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_11.Reg, volatile.LoadUint32(&o.CFDRMDF16_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_11.Reg, volatile.LoadUint32(&o.CFDRMDF16_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_11.Reg, volatile.LoadUint32(&o.CFDRMDF16_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_11.Reg, volatile.LoadUint32(&o.CFDRMDF16_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_12.Reg, volatile.LoadUint32(&o.CFDRMDF16_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_12.Reg, volatile.LoadUint32(&o.CFDRMDF16_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_12.Reg, volatile.LoadUint32(&o.CFDRMDF16_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_12.Reg, volatile.LoadUint32(&o.CFDRMDF16_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_13.Reg, volatile.LoadUint32(&o.CFDRMDF16_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_13.Reg, volatile.LoadUint32(&o.CFDRMDF16_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_13.Reg, volatile.LoadUint32(&o.CFDRMDF16_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_13.Reg, volatile.LoadUint32(&o.CFDRMDF16_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_14.Reg, volatile.LoadUint32(&o.CFDRMDF16_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_14.Reg, volatile.LoadUint32(&o.CFDRMDF16_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_14.Reg, volatile.LoadUint32(&o.CFDRMDF16_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_14.Reg, volatile.LoadUint32(&o.CFDRMDF16_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF16_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF16_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_15.Reg, volatile.LoadUint32(&o.CFDRMDF16_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF16_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF16_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF16_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_15.Reg, volatile.LoadUint32(&o.CFDRMDF16_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF16_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF16_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_15.Reg, volatile.LoadUint32(&o.CFDRMDF16_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF16_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF16_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF16_15.Reg, volatile.LoadUint32(&o.CFDRMDF16_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF16_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF16_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID17: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID17_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID17.Reg, volatile.LoadUint32(&o.CFDRMID17.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID17_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID17.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID17_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID17.Reg, volatile.LoadUint32(&o.CFDRMID17.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID17_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID17.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID17_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID17.Reg, volatile.LoadUint32(&o.CFDRMID17.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID17_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID17.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR17: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR17_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR17.Reg, volatile.LoadUint32(&o.CFDRMPTR17.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR17_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR17.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR17_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR17.Reg, volatile.LoadUint32(&o.CFDRMPTR17.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR17_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR17.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS17: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS17_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS17.Reg, volatile.LoadUint32(&o.CFDRMFDSTS17.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS17_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS17.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS17_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS17.Reg, volatile.LoadUint32(&o.CFDRMFDSTS17.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS17_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS17.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS17_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS17.Reg, volatile.LoadUint32(&o.CFDRMFDSTS17.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS17_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS17.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS17_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS17.Reg, volatile.LoadUint32(&o.CFDRMFDSTS17.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS17_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS17.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS17_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS17.Reg, volatile.LoadUint32(&o.CFDRMFDSTS17.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS17_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS17.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF17_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_0.Reg, volatile.LoadUint32(&o.CFDRMDF17_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_0.Reg, volatile.LoadUint32(&o.CFDRMDF17_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_0.Reg, volatile.LoadUint32(&o.CFDRMDF17_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_0.Reg, volatile.LoadUint32(&o.CFDRMDF17_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_1.Reg, volatile.LoadUint32(&o.CFDRMDF17_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_1.Reg, volatile.LoadUint32(&o.CFDRMDF17_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_1.Reg, volatile.LoadUint32(&o.CFDRMDF17_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_1.Reg, volatile.LoadUint32(&o.CFDRMDF17_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_2.Reg, volatile.LoadUint32(&o.CFDRMDF17_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_2.Reg, volatile.LoadUint32(&o.CFDRMDF17_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_2.Reg, volatile.LoadUint32(&o.CFDRMDF17_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_2.Reg, volatile.LoadUint32(&o.CFDRMDF17_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_3.Reg, volatile.LoadUint32(&o.CFDRMDF17_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_3.Reg, volatile.LoadUint32(&o.CFDRMDF17_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_3.Reg, volatile.LoadUint32(&o.CFDRMDF17_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_3.Reg, volatile.LoadUint32(&o.CFDRMDF17_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_4.Reg, volatile.LoadUint32(&o.CFDRMDF17_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_4.Reg, volatile.LoadUint32(&o.CFDRMDF17_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_4.Reg, volatile.LoadUint32(&o.CFDRMDF17_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_4.Reg, volatile.LoadUint32(&o.CFDRMDF17_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_5.Reg, volatile.LoadUint32(&o.CFDRMDF17_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_5.Reg, volatile.LoadUint32(&o.CFDRMDF17_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_5.Reg, volatile.LoadUint32(&o.CFDRMDF17_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_5.Reg, volatile.LoadUint32(&o.CFDRMDF17_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_6.Reg, volatile.LoadUint32(&o.CFDRMDF17_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_6.Reg, volatile.LoadUint32(&o.CFDRMDF17_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_6.Reg, volatile.LoadUint32(&o.CFDRMDF17_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_6.Reg, volatile.LoadUint32(&o.CFDRMDF17_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_7.Reg, volatile.LoadUint32(&o.CFDRMDF17_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_7.Reg, volatile.LoadUint32(&o.CFDRMDF17_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_7.Reg, volatile.LoadUint32(&o.CFDRMDF17_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_7.Reg, volatile.LoadUint32(&o.CFDRMDF17_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_8.Reg, volatile.LoadUint32(&o.CFDRMDF17_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_8.Reg, volatile.LoadUint32(&o.CFDRMDF17_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_8.Reg, volatile.LoadUint32(&o.CFDRMDF17_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_8.Reg, volatile.LoadUint32(&o.CFDRMDF17_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_9.Reg, volatile.LoadUint32(&o.CFDRMDF17_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_9.Reg, volatile.LoadUint32(&o.CFDRMDF17_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_9.Reg, volatile.LoadUint32(&o.CFDRMDF17_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_9.Reg, volatile.LoadUint32(&o.CFDRMDF17_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_10.Reg, volatile.LoadUint32(&o.CFDRMDF17_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_10.Reg, volatile.LoadUint32(&o.CFDRMDF17_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_10.Reg, volatile.LoadUint32(&o.CFDRMDF17_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_10.Reg, volatile.LoadUint32(&o.CFDRMDF17_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_11.Reg, volatile.LoadUint32(&o.CFDRMDF17_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_11.Reg, volatile.LoadUint32(&o.CFDRMDF17_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_11.Reg, volatile.LoadUint32(&o.CFDRMDF17_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_11.Reg, volatile.LoadUint32(&o.CFDRMDF17_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_12.Reg, volatile.LoadUint32(&o.CFDRMDF17_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_12.Reg, volatile.LoadUint32(&o.CFDRMDF17_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_12.Reg, volatile.LoadUint32(&o.CFDRMDF17_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_12.Reg, volatile.LoadUint32(&o.CFDRMDF17_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_13.Reg, volatile.LoadUint32(&o.CFDRMDF17_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_13.Reg, volatile.LoadUint32(&o.CFDRMDF17_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_13.Reg, volatile.LoadUint32(&o.CFDRMDF17_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_13.Reg, volatile.LoadUint32(&o.CFDRMDF17_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_14.Reg, volatile.LoadUint32(&o.CFDRMDF17_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_14.Reg, volatile.LoadUint32(&o.CFDRMDF17_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_14.Reg, volatile.LoadUint32(&o.CFDRMDF17_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_14.Reg, volatile.LoadUint32(&o.CFDRMDF17_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF17_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF17_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_15.Reg, volatile.LoadUint32(&o.CFDRMDF17_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF17_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF17_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF17_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_15.Reg, volatile.LoadUint32(&o.CFDRMDF17_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF17_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF17_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_15.Reg, volatile.LoadUint32(&o.CFDRMDF17_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF17_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF17_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF17_15.Reg, volatile.LoadUint32(&o.CFDRMDF17_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF17_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF17_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID18: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID18_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID18.Reg, volatile.LoadUint32(&o.CFDRMID18.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID18_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID18.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID18_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID18.Reg, volatile.LoadUint32(&o.CFDRMID18.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID18_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID18.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID18_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID18.Reg, volatile.LoadUint32(&o.CFDRMID18.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID18_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID18.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR18: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR18_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR18.Reg, volatile.LoadUint32(&o.CFDRMPTR18.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR18_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR18.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR18_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR18.Reg, volatile.LoadUint32(&o.CFDRMPTR18.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR18_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR18.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS18: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS18_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS18.Reg, volatile.LoadUint32(&o.CFDRMFDSTS18.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS18_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS18.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS18_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS18.Reg, volatile.LoadUint32(&o.CFDRMFDSTS18.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS18_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS18.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS18_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS18.Reg, volatile.LoadUint32(&o.CFDRMFDSTS18.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS18_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS18.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS18_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS18.Reg, volatile.LoadUint32(&o.CFDRMFDSTS18.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS18_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS18.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS18_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS18.Reg, volatile.LoadUint32(&o.CFDRMFDSTS18.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS18_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS18.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF18_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_0.Reg, volatile.LoadUint32(&o.CFDRMDF18_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_0.Reg, volatile.LoadUint32(&o.CFDRMDF18_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_0.Reg, volatile.LoadUint32(&o.CFDRMDF18_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_0.Reg, volatile.LoadUint32(&o.CFDRMDF18_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_1.Reg, volatile.LoadUint32(&o.CFDRMDF18_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_1.Reg, volatile.LoadUint32(&o.CFDRMDF18_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_1.Reg, volatile.LoadUint32(&o.CFDRMDF18_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_1.Reg, volatile.LoadUint32(&o.CFDRMDF18_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_2.Reg, volatile.LoadUint32(&o.CFDRMDF18_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_2.Reg, volatile.LoadUint32(&o.CFDRMDF18_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_2.Reg, volatile.LoadUint32(&o.CFDRMDF18_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_2.Reg, volatile.LoadUint32(&o.CFDRMDF18_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_3.Reg, volatile.LoadUint32(&o.CFDRMDF18_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_3.Reg, volatile.LoadUint32(&o.CFDRMDF18_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_3.Reg, volatile.LoadUint32(&o.CFDRMDF18_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_3.Reg, volatile.LoadUint32(&o.CFDRMDF18_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_4.Reg, volatile.LoadUint32(&o.CFDRMDF18_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_4.Reg, volatile.LoadUint32(&o.CFDRMDF18_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_4.Reg, volatile.LoadUint32(&o.CFDRMDF18_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_4.Reg, volatile.LoadUint32(&o.CFDRMDF18_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_5.Reg, volatile.LoadUint32(&o.CFDRMDF18_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_5.Reg, volatile.LoadUint32(&o.CFDRMDF18_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_5.Reg, volatile.LoadUint32(&o.CFDRMDF18_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_5.Reg, volatile.LoadUint32(&o.CFDRMDF18_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_6.Reg, volatile.LoadUint32(&o.CFDRMDF18_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_6.Reg, volatile.LoadUint32(&o.CFDRMDF18_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_6.Reg, volatile.LoadUint32(&o.CFDRMDF18_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_6.Reg, volatile.LoadUint32(&o.CFDRMDF18_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_7.Reg, volatile.LoadUint32(&o.CFDRMDF18_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_7.Reg, volatile.LoadUint32(&o.CFDRMDF18_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_7.Reg, volatile.LoadUint32(&o.CFDRMDF18_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_7.Reg, volatile.LoadUint32(&o.CFDRMDF18_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_8.Reg, volatile.LoadUint32(&o.CFDRMDF18_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_8.Reg, volatile.LoadUint32(&o.CFDRMDF18_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_8.Reg, volatile.LoadUint32(&o.CFDRMDF18_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_8.Reg, volatile.LoadUint32(&o.CFDRMDF18_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_9.Reg, volatile.LoadUint32(&o.CFDRMDF18_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_9.Reg, volatile.LoadUint32(&o.CFDRMDF18_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_9.Reg, volatile.LoadUint32(&o.CFDRMDF18_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_9.Reg, volatile.LoadUint32(&o.CFDRMDF18_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_10.Reg, volatile.LoadUint32(&o.CFDRMDF18_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_10.Reg, volatile.LoadUint32(&o.CFDRMDF18_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_10.Reg, volatile.LoadUint32(&o.CFDRMDF18_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_10.Reg, volatile.LoadUint32(&o.CFDRMDF18_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_11.Reg, volatile.LoadUint32(&o.CFDRMDF18_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_11.Reg, volatile.LoadUint32(&o.CFDRMDF18_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_11.Reg, volatile.LoadUint32(&o.CFDRMDF18_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_11.Reg, volatile.LoadUint32(&o.CFDRMDF18_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_12.Reg, volatile.LoadUint32(&o.CFDRMDF18_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_12.Reg, volatile.LoadUint32(&o.CFDRMDF18_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_12.Reg, volatile.LoadUint32(&o.CFDRMDF18_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_12.Reg, volatile.LoadUint32(&o.CFDRMDF18_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_13.Reg, volatile.LoadUint32(&o.CFDRMDF18_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_13.Reg, volatile.LoadUint32(&o.CFDRMDF18_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_13.Reg, volatile.LoadUint32(&o.CFDRMDF18_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_13.Reg, volatile.LoadUint32(&o.CFDRMDF18_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_14.Reg, volatile.LoadUint32(&o.CFDRMDF18_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_14.Reg, volatile.LoadUint32(&o.CFDRMDF18_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_14.Reg, volatile.LoadUint32(&o.CFDRMDF18_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_14.Reg, volatile.LoadUint32(&o.CFDRMDF18_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF18_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF18_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_15.Reg, volatile.LoadUint32(&o.CFDRMDF18_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF18_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF18_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF18_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_15.Reg, volatile.LoadUint32(&o.CFDRMDF18_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF18_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF18_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_15.Reg, volatile.LoadUint32(&o.CFDRMDF18_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF18_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF18_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF18_15.Reg, volatile.LoadUint32(&o.CFDRMDF18_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF18_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF18_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID19: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID19_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID19.Reg, volatile.LoadUint32(&o.CFDRMID19.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID19_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID19.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID19_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID19.Reg, volatile.LoadUint32(&o.CFDRMID19.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID19_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID19.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID19_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID19.Reg, volatile.LoadUint32(&o.CFDRMID19.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID19_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID19.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR19: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR19_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR19.Reg, volatile.LoadUint32(&o.CFDRMPTR19.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR19_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR19.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR19_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR19.Reg, volatile.LoadUint32(&o.CFDRMPTR19.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR19_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR19.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS19: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS19_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS19.Reg, volatile.LoadUint32(&o.CFDRMFDSTS19.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS19_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS19.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS19_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS19.Reg, volatile.LoadUint32(&o.CFDRMFDSTS19.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS19_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS19.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS19_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS19.Reg, volatile.LoadUint32(&o.CFDRMFDSTS19.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS19_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS19.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS19_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS19.Reg, volatile.LoadUint32(&o.CFDRMFDSTS19.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS19_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS19.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS19_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS19.Reg, volatile.LoadUint32(&o.CFDRMFDSTS19.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS19_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS19.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF19_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_0.Reg, volatile.LoadUint32(&o.CFDRMDF19_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_0.Reg, volatile.LoadUint32(&o.CFDRMDF19_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_0.Reg, volatile.LoadUint32(&o.CFDRMDF19_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_0.Reg, volatile.LoadUint32(&o.CFDRMDF19_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_1.Reg, volatile.LoadUint32(&o.CFDRMDF19_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_1.Reg, volatile.LoadUint32(&o.CFDRMDF19_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_1.Reg, volatile.LoadUint32(&o.CFDRMDF19_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_1.Reg, volatile.LoadUint32(&o.CFDRMDF19_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_2.Reg, volatile.LoadUint32(&o.CFDRMDF19_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_2.Reg, volatile.LoadUint32(&o.CFDRMDF19_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_2.Reg, volatile.LoadUint32(&o.CFDRMDF19_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_2.Reg, volatile.LoadUint32(&o.CFDRMDF19_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_3.Reg, volatile.LoadUint32(&o.CFDRMDF19_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_3.Reg, volatile.LoadUint32(&o.CFDRMDF19_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_3.Reg, volatile.LoadUint32(&o.CFDRMDF19_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_3.Reg, volatile.LoadUint32(&o.CFDRMDF19_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_4.Reg, volatile.LoadUint32(&o.CFDRMDF19_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_4.Reg, volatile.LoadUint32(&o.CFDRMDF19_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_4.Reg, volatile.LoadUint32(&o.CFDRMDF19_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_4.Reg, volatile.LoadUint32(&o.CFDRMDF19_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_5.Reg, volatile.LoadUint32(&o.CFDRMDF19_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_5.Reg, volatile.LoadUint32(&o.CFDRMDF19_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_5.Reg, volatile.LoadUint32(&o.CFDRMDF19_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_5.Reg, volatile.LoadUint32(&o.CFDRMDF19_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_6.Reg, volatile.LoadUint32(&o.CFDRMDF19_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_6.Reg, volatile.LoadUint32(&o.CFDRMDF19_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_6.Reg, volatile.LoadUint32(&o.CFDRMDF19_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_6.Reg, volatile.LoadUint32(&o.CFDRMDF19_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_7.Reg, volatile.LoadUint32(&o.CFDRMDF19_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_7.Reg, volatile.LoadUint32(&o.CFDRMDF19_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_7.Reg, volatile.LoadUint32(&o.CFDRMDF19_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_7.Reg, volatile.LoadUint32(&o.CFDRMDF19_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_8.Reg, volatile.LoadUint32(&o.CFDRMDF19_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_8.Reg, volatile.LoadUint32(&o.CFDRMDF19_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_8.Reg, volatile.LoadUint32(&o.CFDRMDF19_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_8.Reg, volatile.LoadUint32(&o.CFDRMDF19_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_9.Reg, volatile.LoadUint32(&o.CFDRMDF19_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_9.Reg, volatile.LoadUint32(&o.CFDRMDF19_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_9.Reg, volatile.LoadUint32(&o.CFDRMDF19_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_9.Reg, volatile.LoadUint32(&o.CFDRMDF19_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_10.Reg, volatile.LoadUint32(&o.CFDRMDF19_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_10.Reg, volatile.LoadUint32(&o.CFDRMDF19_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_10.Reg, volatile.LoadUint32(&o.CFDRMDF19_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_10.Reg, volatile.LoadUint32(&o.CFDRMDF19_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_11.Reg, volatile.LoadUint32(&o.CFDRMDF19_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_11.Reg, volatile.LoadUint32(&o.CFDRMDF19_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_11.Reg, volatile.LoadUint32(&o.CFDRMDF19_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_11.Reg, volatile.LoadUint32(&o.CFDRMDF19_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_12.Reg, volatile.LoadUint32(&o.CFDRMDF19_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_12.Reg, volatile.LoadUint32(&o.CFDRMDF19_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_12.Reg, volatile.LoadUint32(&o.CFDRMDF19_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_12.Reg, volatile.LoadUint32(&o.CFDRMDF19_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_13.Reg, volatile.LoadUint32(&o.CFDRMDF19_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_13.Reg, volatile.LoadUint32(&o.CFDRMDF19_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_13.Reg, volatile.LoadUint32(&o.CFDRMDF19_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_13.Reg, volatile.LoadUint32(&o.CFDRMDF19_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_14.Reg, volatile.LoadUint32(&o.CFDRMDF19_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_14.Reg, volatile.LoadUint32(&o.CFDRMDF19_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_14.Reg, volatile.LoadUint32(&o.CFDRMDF19_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_14.Reg, volatile.LoadUint32(&o.CFDRMDF19_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF19_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF19_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_15.Reg, volatile.LoadUint32(&o.CFDRMDF19_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF19_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF19_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF19_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_15.Reg, volatile.LoadUint32(&o.CFDRMDF19_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF19_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF19_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_15.Reg, volatile.LoadUint32(&o.CFDRMDF19_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF19_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF19_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF19_15.Reg, volatile.LoadUint32(&o.CFDRMDF19_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF19_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF19_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID20: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID20_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID20.Reg, volatile.LoadUint32(&o.CFDRMID20.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID20_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID20.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID20_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID20.Reg, volatile.LoadUint32(&o.CFDRMID20.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID20_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID20.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID20_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID20.Reg, volatile.LoadUint32(&o.CFDRMID20.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID20_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID20.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR20: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR20_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR20.Reg, volatile.LoadUint32(&o.CFDRMPTR20.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR20_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR20.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR20_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR20.Reg, volatile.LoadUint32(&o.CFDRMPTR20.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR20_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR20.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS20: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS20_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS20.Reg, volatile.LoadUint32(&o.CFDRMFDSTS20.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS20_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS20.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS20_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS20.Reg, volatile.LoadUint32(&o.CFDRMFDSTS20.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS20_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS20.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS20_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS20.Reg, volatile.LoadUint32(&o.CFDRMFDSTS20.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS20_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS20.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS20_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS20.Reg, volatile.LoadUint32(&o.CFDRMFDSTS20.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS20_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS20.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS20_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS20.Reg, volatile.LoadUint32(&o.CFDRMFDSTS20.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS20_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS20.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF20_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_0.Reg, volatile.LoadUint32(&o.CFDRMDF20_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_0.Reg, volatile.LoadUint32(&o.CFDRMDF20_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_0.Reg, volatile.LoadUint32(&o.CFDRMDF20_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_0.Reg, volatile.LoadUint32(&o.CFDRMDF20_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_1.Reg, volatile.LoadUint32(&o.CFDRMDF20_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_1.Reg, volatile.LoadUint32(&o.CFDRMDF20_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_1.Reg, volatile.LoadUint32(&o.CFDRMDF20_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_1.Reg, volatile.LoadUint32(&o.CFDRMDF20_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_2.Reg, volatile.LoadUint32(&o.CFDRMDF20_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_2.Reg, volatile.LoadUint32(&o.CFDRMDF20_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_2.Reg, volatile.LoadUint32(&o.CFDRMDF20_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_2.Reg, volatile.LoadUint32(&o.CFDRMDF20_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_3.Reg, volatile.LoadUint32(&o.CFDRMDF20_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_3.Reg, volatile.LoadUint32(&o.CFDRMDF20_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_3.Reg, volatile.LoadUint32(&o.CFDRMDF20_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_3.Reg, volatile.LoadUint32(&o.CFDRMDF20_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_4.Reg, volatile.LoadUint32(&o.CFDRMDF20_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_4.Reg, volatile.LoadUint32(&o.CFDRMDF20_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_4.Reg, volatile.LoadUint32(&o.CFDRMDF20_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_4.Reg, volatile.LoadUint32(&o.CFDRMDF20_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_5.Reg, volatile.LoadUint32(&o.CFDRMDF20_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_5.Reg, volatile.LoadUint32(&o.CFDRMDF20_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_5.Reg, volatile.LoadUint32(&o.CFDRMDF20_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_5.Reg, volatile.LoadUint32(&o.CFDRMDF20_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_6.Reg, volatile.LoadUint32(&o.CFDRMDF20_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_6.Reg, volatile.LoadUint32(&o.CFDRMDF20_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_6.Reg, volatile.LoadUint32(&o.CFDRMDF20_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_6.Reg, volatile.LoadUint32(&o.CFDRMDF20_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_7.Reg, volatile.LoadUint32(&o.CFDRMDF20_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_7.Reg, volatile.LoadUint32(&o.CFDRMDF20_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_7.Reg, volatile.LoadUint32(&o.CFDRMDF20_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_7.Reg, volatile.LoadUint32(&o.CFDRMDF20_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_8.Reg, volatile.LoadUint32(&o.CFDRMDF20_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_8.Reg, volatile.LoadUint32(&o.CFDRMDF20_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_8.Reg, volatile.LoadUint32(&o.CFDRMDF20_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_8.Reg, volatile.LoadUint32(&o.CFDRMDF20_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_9.Reg, volatile.LoadUint32(&o.CFDRMDF20_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_9.Reg, volatile.LoadUint32(&o.CFDRMDF20_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_9.Reg, volatile.LoadUint32(&o.CFDRMDF20_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_9.Reg, volatile.LoadUint32(&o.CFDRMDF20_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_10.Reg, volatile.LoadUint32(&o.CFDRMDF20_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_10.Reg, volatile.LoadUint32(&o.CFDRMDF20_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_10.Reg, volatile.LoadUint32(&o.CFDRMDF20_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_10.Reg, volatile.LoadUint32(&o.CFDRMDF20_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_11.Reg, volatile.LoadUint32(&o.CFDRMDF20_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_11.Reg, volatile.LoadUint32(&o.CFDRMDF20_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_11.Reg, volatile.LoadUint32(&o.CFDRMDF20_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_11.Reg, volatile.LoadUint32(&o.CFDRMDF20_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_12.Reg, volatile.LoadUint32(&o.CFDRMDF20_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_12.Reg, volatile.LoadUint32(&o.CFDRMDF20_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_12.Reg, volatile.LoadUint32(&o.CFDRMDF20_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_12.Reg, volatile.LoadUint32(&o.CFDRMDF20_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_13.Reg, volatile.LoadUint32(&o.CFDRMDF20_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_13.Reg, volatile.LoadUint32(&o.CFDRMDF20_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_13.Reg, volatile.LoadUint32(&o.CFDRMDF20_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_13.Reg, volatile.LoadUint32(&o.CFDRMDF20_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_14.Reg, volatile.LoadUint32(&o.CFDRMDF20_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_14.Reg, volatile.LoadUint32(&o.CFDRMDF20_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_14.Reg, volatile.LoadUint32(&o.CFDRMDF20_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_14.Reg, volatile.LoadUint32(&o.CFDRMDF20_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF20_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF20_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_15.Reg, volatile.LoadUint32(&o.CFDRMDF20_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF20_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF20_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF20_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_15.Reg, volatile.LoadUint32(&o.CFDRMDF20_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF20_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF20_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_15.Reg, volatile.LoadUint32(&o.CFDRMDF20_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF20_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF20_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF20_15.Reg, volatile.LoadUint32(&o.CFDRMDF20_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF20_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF20_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID21: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID21_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID21.Reg, volatile.LoadUint32(&o.CFDRMID21.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID21_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID21.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID21_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID21.Reg, volatile.LoadUint32(&o.CFDRMID21.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID21_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID21.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID21_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID21.Reg, volatile.LoadUint32(&o.CFDRMID21.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID21_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID21.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR21: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR21_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR21.Reg, volatile.LoadUint32(&o.CFDRMPTR21.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR21_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR21.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR21_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR21.Reg, volatile.LoadUint32(&o.CFDRMPTR21.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR21_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR21.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS21: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS21_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS21.Reg, volatile.LoadUint32(&o.CFDRMFDSTS21.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS21_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS21.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS21_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS21.Reg, volatile.LoadUint32(&o.CFDRMFDSTS21.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS21_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS21.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS21_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS21.Reg, volatile.LoadUint32(&o.CFDRMFDSTS21.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS21_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS21.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS21_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS21.Reg, volatile.LoadUint32(&o.CFDRMFDSTS21.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS21_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS21.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS21_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS21.Reg, volatile.LoadUint32(&o.CFDRMFDSTS21.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS21_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS21.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF21_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_0.Reg, volatile.LoadUint32(&o.CFDRMDF21_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_0.Reg, volatile.LoadUint32(&o.CFDRMDF21_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_0.Reg, volatile.LoadUint32(&o.CFDRMDF21_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_0.Reg, volatile.LoadUint32(&o.CFDRMDF21_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_1.Reg, volatile.LoadUint32(&o.CFDRMDF21_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_1.Reg, volatile.LoadUint32(&o.CFDRMDF21_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_1.Reg, volatile.LoadUint32(&o.CFDRMDF21_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_1.Reg, volatile.LoadUint32(&o.CFDRMDF21_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_2.Reg, volatile.LoadUint32(&o.CFDRMDF21_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_2.Reg, volatile.LoadUint32(&o.CFDRMDF21_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_2.Reg, volatile.LoadUint32(&o.CFDRMDF21_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_2.Reg, volatile.LoadUint32(&o.CFDRMDF21_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_3.Reg, volatile.LoadUint32(&o.CFDRMDF21_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_3.Reg, volatile.LoadUint32(&o.CFDRMDF21_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_3.Reg, volatile.LoadUint32(&o.CFDRMDF21_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_3.Reg, volatile.LoadUint32(&o.CFDRMDF21_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_4.Reg, volatile.LoadUint32(&o.CFDRMDF21_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_4.Reg, volatile.LoadUint32(&o.CFDRMDF21_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_4.Reg, volatile.LoadUint32(&o.CFDRMDF21_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_4.Reg, volatile.LoadUint32(&o.CFDRMDF21_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_5.Reg, volatile.LoadUint32(&o.CFDRMDF21_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_5.Reg, volatile.LoadUint32(&o.CFDRMDF21_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_5.Reg, volatile.LoadUint32(&o.CFDRMDF21_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_5.Reg, volatile.LoadUint32(&o.CFDRMDF21_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_6.Reg, volatile.LoadUint32(&o.CFDRMDF21_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_6.Reg, volatile.LoadUint32(&o.CFDRMDF21_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_6.Reg, volatile.LoadUint32(&o.CFDRMDF21_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_6.Reg, volatile.LoadUint32(&o.CFDRMDF21_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_7.Reg, volatile.LoadUint32(&o.CFDRMDF21_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_7.Reg, volatile.LoadUint32(&o.CFDRMDF21_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_7.Reg, volatile.LoadUint32(&o.CFDRMDF21_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_7.Reg, volatile.LoadUint32(&o.CFDRMDF21_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_8.Reg, volatile.LoadUint32(&o.CFDRMDF21_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_8.Reg, volatile.LoadUint32(&o.CFDRMDF21_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_8.Reg, volatile.LoadUint32(&o.CFDRMDF21_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_8.Reg, volatile.LoadUint32(&o.CFDRMDF21_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_9.Reg, volatile.LoadUint32(&o.CFDRMDF21_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_9.Reg, volatile.LoadUint32(&o.CFDRMDF21_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_9.Reg, volatile.LoadUint32(&o.CFDRMDF21_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_9.Reg, volatile.LoadUint32(&o.CFDRMDF21_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_10.Reg, volatile.LoadUint32(&o.CFDRMDF21_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_10.Reg, volatile.LoadUint32(&o.CFDRMDF21_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_10.Reg, volatile.LoadUint32(&o.CFDRMDF21_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_10.Reg, volatile.LoadUint32(&o.CFDRMDF21_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_11.Reg, volatile.LoadUint32(&o.CFDRMDF21_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_11.Reg, volatile.LoadUint32(&o.CFDRMDF21_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_11.Reg, volatile.LoadUint32(&o.CFDRMDF21_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_11.Reg, volatile.LoadUint32(&o.CFDRMDF21_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_12.Reg, volatile.LoadUint32(&o.CFDRMDF21_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_12.Reg, volatile.LoadUint32(&o.CFDRMDF21_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_12.Reg, volatile.LoadUint32(&o.CFDRMDF21_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_12.Reg, volatile.LoadUint32(&o.CFDRMDF21_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_13.Reg, volatile.LoadUint32(&o.CFDRMDF21_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_13.Reg, volatile.LoadUint32(&o.CFDRMDF21_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_13.Reg, volatile.LoadUint32(&o.CFDRMDF21_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_13.Reg, volatile.LoadUint32(&o.CFDRMDF21_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_14.Reg, volatile.LoadUint32(&o.CFDRMDF21_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_14.Reg, volatile.LoadUint32(&o.CFDRMDF21_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_14.Reg, volatile.LoadUint32(&o.CFDRMDF21_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_14.Reg, volatile.LoadUint32(&o.CFDRMDF21_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF21_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF21_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_15.Reg, volatile.LoadUint32(&o.CFDRMDF21_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF21_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF21_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF21_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_15.Reg, volatile.LoadUint32(&o.CFDRMDF21_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF21_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF21_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_15.Reg, volatile.LoadUint32(&o.CFDRMDF21_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF21_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF21_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF21_15.Reg, volatile.LoadUint32(&o.CFDRMDF21_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF21_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF21_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID22: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID22_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID22.Reg, volatile.LoadUint32(&o.CFDRMID22.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID22_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID22.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID22_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID22.Reg, volatile.LoadUint32(&o.CFDRMID22.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID22_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID22.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID22_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID22.Reg, volatile.LoadUint32(&o.CFDRMID22.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID22_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID22.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR22: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR22_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR22.Reg, volatile.LoadUint32(&o.CFDRMPTR22.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR22_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR22.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR22_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR22.Reg, volatile.LoadUint32(&o.CFDRMPTR22.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR22_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR22.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS22: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS22_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS22.Reg, volatile.LoadUint32(&o.CFDRMFDSTS22.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS22_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS22.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS22_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS22.Reg, volatile.LoadUint32(&o.CFDRMFDSTS22.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS22_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS22.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS22_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS22.Reg, volatile.LoadUint32(&o.CFDRMFDSTS22.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS22_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS22.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS22_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS22.Reg, volatile.LoadUint32(&o.CFDRMFDSTS22.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS22_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS22.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS22_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS22.Reg, volatile.LoadUint32(&o.CFDRMFDSTS22.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS22_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS22.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF22_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_0.Reg, volatile.LoadUint32(&o.CFDRMDF22_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_0.Reg, volatile.LoadUint32(&o.CFDRMDF22_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_0.Reg, volatile.LoadUint32(&o.CFDRMDF22_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_0.Reg, volatile.LoadUint32(&o.CFDRMDF22_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_1.Reg, volatile.LoadUint32(&o.CFDRMDF22_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_1.Reg, volatile.LoadUint32(&o.CFDRMDF22_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_1.Reg, volatile.LoadUint32(&o.CFDRMDF22_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_1.Reg, volatile.LoadUint32(&o.CFDRMDF22_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_2.Reg, volatile.LoadUint32(&o.CFDRMDF22_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_2.Reg, volatile.LoadUint32(&o.CFDRMDF22_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_2.Reg, volatile.LoadUint32(&o.CFDRMDF22_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_2.Reg, volatile.LoadUint32(&o.CFDRMDF22_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_3.Reg, volatile.LoadUint32(&o.CFDRMDF22_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_3.Reg, volatile.LoadUint32(&o.CFDRMDF22_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_3.Reg, volatile.LoadUint32(&o.CFDRMDF22_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_3.Reg, volatile.LoadUint32(&o.CFDRMDF22_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_4.Reg, volatile.LoadUint32(&o.CFDRMDF22_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_4.Reg, volatile.LoadUint32(&o.CFDRMDF22_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_4.Reg, volatile.LoadUint32(&o.CFDRMDF22_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_4.Reg, volatile.LoadUint32(&o.CFDRMDF22_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_5.Reg, volatile.LoadUint32(&o.CFDRMDF22_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_5.Reg, volatile.LoadUint32(&o.CFDRMDF22_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_5.Reg, volatile.LoadUint32(&o.CFDRMDF22_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_5.Reg, volatile.LoadUint32(&o.CFDRMDF22_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_6.Reg, volatile.LoadUint32(&o.CFDRMDF22_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_6.Reg, volatile.LoadUint32(&o.CFDRMDF22_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_6.Reg, volatile.LoadUint32(&o.CFDRMDF22_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_6.Reg, volatile.LoadUint32(&o.CFDRMDF22_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_7.Reg, volatile.LoadUint32(&o.CFDRMDF22_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_7.Reg, volatile.LoadUint32(&o.CFDRMDF22_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_7.Reg, volatile.LoadUint32(&o.CFDRMDF22_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_7.Reg, volatile.LoadUint32(&o.CFDRMDF22_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_8.Reg, volatile.LoadUint32(&o.CFDRMDF22_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_8.Reg, volatile.LoadUint32(&o.CFDRMDF22_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_8.Reg, volatile.LoadUint32(&o.CFDRMDF22_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_8.Reg, volatile.LoadUint32(&o.CFDRMDF22_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_9.Reg, volatile.LoadUint32(&o.CFDRMDF22_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_9.Reg, volatile.LoadUint32(&o.CFDRMDF22_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_9.Reg, volatile.LoadUint32(&o.CFDRMDF22_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_9.Reg, volatile.LoadUint32(&o.CFDRMDF22_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_10.Reg, volatile.LoadUint32(&o.CFDRMDF22_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_10.Reg, volatile.LoadUint32(&o.CFDRMDF22_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_10.Reg, volatile.LoadUint32(&o.CFDRMDF22_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_10.Reg, volatile.LoadUint32(&o.CFDRMDF22_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_11.Reg, volatile.LoadUint32(&o.CFDRMDF22_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_11.Reg, volatile.LoadUint32(&o.CFDRMDF22_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_11.Reg, volatile.LoadUint32(&o.CFDRMDF22_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_11.Reg, volatile.LoadUint32(&o.CFDRMDF22_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_12.Reg, volatile.LoadUint32(&o.CFDRMDF22_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_12.Reg, volatile.LoadUint32(&o.CFDRMDF22_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_12.Reg, volatile.LoadUint32(&o.CFDRMDF22_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_12.Reg, volatile.LoadUint32(&o.CFDRMDF22_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_13.Reg, volatile.LoadUint32(&o.CFDRMDF22_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_13.Reg, volatile.LoadUint32(&o.CFDRMDF22_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_13.Reg, volatile.LoadUint32(&o.CFDRMDF22_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_13.Reg, volatile.LoadUint32(&o.CFDRMDF22_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_14.Reg, volatile.LoadUint32(&o.CFDRMDF22_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_14.Reg, volatile.LoadUint32(&o.CFDRMDF22_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_14.Reg, volatile.LoadUint32(&o.CFDRMDF22_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_14.Reg, volatile.LoadUint32(&o.CFDRMDF22_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF22_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF22_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_15.Reg, volatile.LoadUint32(&o.CFDRMDF22_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF22_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF22_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF22_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_15.Reg, volatile.LoadUint32(&o.CFDRMDF22_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF22_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF22_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_15.Reg, volatile.LoadUint32(&o.CFDRMDF22_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF22_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF22_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF22_15.Reg, volatile.LoadUint32(&o.CFDRMDF22_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF22_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF22_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID23: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID23_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID23.Reg, volatile.LoadUint32(&o.CFDRMID23.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID23_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID23.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID23_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID23.Reg, volatile.LoadUint32(&o.CFDRMID23.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID23_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID23.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID23_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID23.Reg, volatile.LoadUint32(&o.CFDRMID23.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID23_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID23.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR23: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR23_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR23.Reg, volatile.LoadUint32(&o.CFDRMPTR23.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR23_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR23.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR23_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR23.Reg, volatile.LoadUint32(&o.CFDRMPTR23.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR23_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR23.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS23: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS23_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS23.Reg, volatile.LoadUint32(&o.CFDRMFDSTS23.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS23_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS23.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS23_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS23.Reg, volatile.LoadUint32(&o.CFDRMFDSTS23.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS23_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS23.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS23_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS23.Reg, volatile.LoadUint32(&o.CFDRMFDSTS23.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS23_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS23.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS23_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS23.Reg, volatile.LoadUint32(&o.CFDRMFDSTS23.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS23_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS23.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS23_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS23.Reg, volatile.LoadUint32(&o.CFDRMFDSTS23.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS23_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS23.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF23_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_0.Reg, volatile.LoadUint32(&o.CFDRMDF23_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_0.Reg, volatile.LoadUint32(&o.CFDRMDF23_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_0.Reg, volatile.LoadUint32(&o.CFDRMDF23_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_0.Reg, volatile.LoadUint32(&o.CFDRMDF23_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_1.Reg, volatile.LoadUint32(&o.CFDRMDF23_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_1.Reg, volatile.LoadUint32(&o.CFDRMDF23_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_1.Reg, volatile.LoadUint32(&o.CFDRMDF23_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_1.Reg, volatile.LoadUint32(&o.CFDRMDF23_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_2.Reg, volatile.LoadUint32(&o.CFDRMDF23_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_2.Reg, volatile.LoadUint32(&o.CFDRMDF23_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_2.Reg, volatile.LoadUint32(&o.CFDRMDF23_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_2.Reg, volatile.LoadUint32(&o.CFDRMDF23_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_3.Reg, volatile.LoadUint32(&o.CFDRMDF23_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_3.Reg, volatile.LoadUint32(&o.CFDRMDF23_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_3.Reg, volatile.LoadUint32(&o.CFDRMDF23_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_3.Reg, volatile.LoadUint32(&o.CFDRMDF23_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_4.Reg, volatile.LoadUint32(&o.CFDRMDF23_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_4.Reg, volatile.LoadUint32(&o.CFDRMDF23_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_4.Reg, volatile.LoadUint32(&o.CFDRMDF23_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_4.Reg, volatile.LoadUint32(&o.CFDRMDF23_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_5.Reg, volatile.LoadUint32(&o.CFDRMDF23_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_5.Reg, volatile.LoadUint32(&o.CFDRMDF23_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_5.Reg, volatile.LoadUint32(&o.CFDRMDF23_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_5.Reg, volatile.LoadUint32(&o.CFDRMDF23_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_6.Reg, volatile.LoadUint32(&o.CFDRMDF23_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_6.Reg, volatile.LoadUint32(&o.CFDRMDF23_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_6.Reg, volatile.LoadUint32(&o.CFDRMDF23_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_6.Reg, volatile.LoadUint32(&o.CFDRMDF23_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_7.Reg, volatile.LoadUint32(&o.CFDRMDF23_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_7.Reg, volatile.LoadUint32(&o.CFDRMDF23_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_7.Reg, volatile.LoadUint32(&o.CFDRMDF23_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_7.Reg, volatile.LoadUint32(&o.CFDRMDF23_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_8.Reg, volatile.LoadUint32(&o.CFDRMDF23_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_8.Reg, volatile.LoadUint32(&o.CFDRMDF23_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_8.Reg, volatile.LoadUint32(&o.CFDRMDF23_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_8.Reg, volatile.LoadUint32(&o.CFDRMDF23_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_9.Reg, volatile.LoadUint32(&o.CFDRMDF23_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_9.Reg, volatile.LoadUint32(&o.CFDRMDF23_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_9.Reg, volatile.LoadUint32(&o.CFDRMDF23_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_9.Reg, volatile.LoadUint32(&o.CFDRMDF23_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_10.Reg, volatile.LoadUint32(&o.CFDRMDF23_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_10.Reg, volatile.LoadUint32(&o.CFDRMDF23_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_10.Reg, volatile.LoadUint32(&o.CFDRMDF23_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_10.Reg, volatile.LoadUint32(&o.CFDRMDF23_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_11.Reg, volatile.LoadUint32(&o.CFDRMDF23_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_11.Reg, volatile.LoadUint32(&o.CFDRMDF23_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_11.Reg, volatile.LoadUint32(&o.CFDRMDF23_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_11.Reg, volatile.LoadUint32(&o.CFDRMDF23_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_12.Reg, volatile.LoadUint32(&o.CFDRMDF23_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_12.Reg, volatile.LoadUint32(&o.CFDRMDF23_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_12.Reg, volatile.LoadUint32(&o.CFDRMDF23_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_12.Reg, volatile.LoadUint32(&o.CFDRMDF23_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_13.Reg, volatile.LoadUint32(&o.CFDRMDF23_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_13.Reg, volatile.LoadUint32(&o.CFDRMDF23_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_13.Reg, volatile.LoadUint32(&o.CFDRMDF23_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_13.Reg, volatile.LoadUint32(&o.CFDRMDF23_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_14.Reg, volatile.LoadUint32(&o.CFDRMDF23_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_14.Reg, volatile.LoadUint32(&o.CFDRMDF23_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_14.Reg, volatile.LoadUint32(&o.CFDRMDF23_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_14.Reg, volatile.LoadUint32(&o.CFDRMDF23_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF23_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF23_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_15.Reg, volatile.LoadUint32(&o.CFDRMDF23_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF23_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF23_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF23_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_15.Reg, volatile.LoadUint32(&o.CFDRMDF23_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF23_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF23_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_15.Reg, volatile.LoadUint32(&o.CFDRMDF23_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF23_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF23_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF23_15.Reg, volatile.LoadUint32(&o.CFDRMDF23_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF23_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF23_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID24: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID24_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID24.Reg, volatile.LoadUint32(&o.CFDRMID24.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID24_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID24.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID24_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID24.Reg, volatile.LoadUint32(&o.CFDRMID24.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID24_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID24.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID24_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID24.Reg, volatile.LoadUint32(&o.CFDRMID24.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID24_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID24.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR24: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR24_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR24.Reg, volatile.LoadUint32(&o.CFDRMPTR24.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR24_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR24.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR24_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR24.Reg, volatile.LoadUint32(&o.CFDRMPTR24.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR24_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR24.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS24: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS24_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS24.Reg, volatile.LoadUint32(&o.CFDRMFDSTS24.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS24_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS24.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS24_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS24.Reg, volatile.LoadUint32(&o.CFDRMFDSTS24.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS24_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS24.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS24_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS24.Reg, volatile.LoadUint32(&o.CFDRMFDSTS24.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS24_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS24.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS24_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS24.Reg, volatile.LoadUint32(&o.CFDRMFDSTS24.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS24_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS24.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS24_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS24.Reg, volatile.LoadUint32(&o.CFDRMFDSTS24.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS24_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS24.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF24_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_0.Reg, volatile.LoadUint32(&o.CFDRMDF24_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_0.Reg, volatile.LoadUint32(&o.CFDRMDF24_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_0.Reg, volatile.LoadUint32(&o.CFDRMDF24_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_0.Reg, volatile.LoadUint32(&o.CFDRMDF24_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_1.Reg, volatile.LoadUint32(&o.CFDRMDF24_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_1.Reg, volatile.LoadUint32(&o.CFDRMDF24_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_1.Reg, volatile.LoadUint32(&o.CFDRMDF24_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_1.Reg, volatile.LoadUint32(&o.CFDRMDF24_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_2.Reg, volatile.LoadUint32(&o.CFDRMDF24_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_2.Reg, volatile.LoadUint32(&o.CFDRMDF24_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_2.Reg, volatile.LoadUint32(&o.CFDRMDF24_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_2.Reg, volatile.LoadUint32(&o.CFDRMDF24_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_3.Reg, volatile.LoadUint32(&o.CFDRMDF24_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_3.Reg, volatile.LoadUint32(&o.CFDRMDF24_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_3.Reg, volatile.LoadUint32(&o.CFDRMDF24_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_3.Reg, volatile.LoadUint32(&o.CFDRMDF24_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_4.Reg, volatile.LoadUint32(&o.CFDRMDF24_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_4.Reg, volatile.LoadUint32(&o.CFDRMDF24_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_4.Reg, volatile.LoadUint32(&o.CFDRMDF24_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_4.Reg, volatile.LoadUint32(&o.CFDRMDF24_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_5.Reg, volatile.LoadUint32(&o.CFDRMDF24_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_5.Reg, volatile.LoadUint32(&o.CFDRMDF24_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_5.Reg, volatile.LoadUint32(&o.CFDRMDF24_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_5.Reg, volatile.LoadUint32(&o.CFDRMDF24_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_6.Reg, volatile.LoadUint32(&o.CFDRMDF24_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_6.Reg, volatile.LoadUint32(&o.CFDRMDF24_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_6.Reg, volatile.LoadUint32(&o.CFDRMDF24_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_6.Reg, volatile.LoadUint32(&o.CFDRMDF24_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_7.Reg, volatile.LoadUint32(&o.CFDRMDF24_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_7.Reg, volatile.LoadUint32(&o.CFDRMDF24_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_7.Reg, volatile.LoadUint32(&o.CFDRMDF24_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_7.Reg, volatile.LoadUint32(&o.CFDRMDF24_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_8.Reg, volatile.LoadUint32(&o.CFDRMDF24_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_8.Reg, volatile.LoadUint32(&o.CFDRMDF24_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_8.Reg, volatile.LoadUint32(&o.CFDRMDF24_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_8.Reg, volatile.LoadUint32(&o.CFDRMDF24_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_9.Reg, volatile.LoadUint32(&o.CFDRMDF24_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_9.Reg, volatile.LoadUint32(&o.CFDRMDF24_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_9.Reg, volatile.LoadUint32(&o.CFDRMDF24_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_9.Reg, volatile.LoadUint32(&o.CFDRMDF24_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_10.Reg, volatile.LoadUint32(&o.CFDRMDF24_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_10.Reg, volatile.LoadUint32(&o.CFDRMDF24_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_10.Reg, volatile.LoadUint32(&o.CFDRMDF24_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_10.Reg, volatile.LoadUint32(&o.CFDRMDF24_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_11.Reg, volatile.LoadUint32(&o.CFDRMDF24_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_11.Reg, volatile.LoadUint32(&o.CFDRMDF24_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_11.Reg, volatile.LoadUint32(&o.CFDRMDF24_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_11.Reg, volatile.LoadUint32(&o.CFDRMDF24_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_12.Reg, volatile.LoadUint32(&o.CFDRMDF24_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_12.Reg, volatile.LoadUint32(&o.CFDRMDF24_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_12.Reg, volatile.LoadUint32(&o.CFDRMDF24_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_12.Reg, volatile.LoadUint32(&o.CFDRMDF24_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_13.Reg, volatile.LoadUint32(&o.CFDRMDF24_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_13.Reg, volatile.LoadUint32(&o.CFDRMDF24_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_13.Reg, volatile.LoadUint32(&o.CFDRMDF24_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_13.Reg, volatile.LoadUint32(&o.CFDRMDF24_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_14.Reg, volatile.LoadUint32(&o.CFDRMDF24_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_14.Reg, volatile.LoadUint32(&o.CFDRMDF24_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_14.Reg, volatile.LoadUint32(&o.CFDRMDF24_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_14.Reg, volatile.LoadUint32(&o.CFDRMDF24_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF24_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF24_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_15.Reg, volatile.LoadUint32(&o.CFDRMDF24_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF24_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF24_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF24_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_15.Reg, volatile.LoadUint32(&o.CFDRMDF24_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF24_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF24_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_15.Reg, volatile.LoadUint32(&o.CFDRMDF24_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF24_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF24_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF24_15.Reg, volatile.LoadUint32(&o.CFDRMDF24_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF24_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF24_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID25: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID25_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID25.Reg, volatile.LoadUint32(&o.CFDRMID25.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID25_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID25.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID25_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID25.Reg, volatile.LoadUint32(&o.CFDRMID25.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID25_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID25.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID25_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID25.Reg, volatile.LoadUint32(&o.CFDRMID25.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID25_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID25.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR25: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR25_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR25.Reg, volatile.LoadUint32(&o.CFDRMPTR25.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR25_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR25.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR25_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR25.Reg, volatile.LoadUint32(&o.CFDRMPTR25.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR25_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR25.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS25: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS25_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS25.Reg, volatile.LoadUint32(&o.CFDRMFDSTS25.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS25_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS25.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS25_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS25.Reg, volatile.LoadUint32(&o.CFDRMFDSTS25.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS25_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS25.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS25_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS25.Reg, volatile.LoadUint32(&o.CFDRMFDSTS25.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS25_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS25.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS25_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS25.Reg, volatile.LoadUint32(&o.CFDRMFDSTS25.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS25_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS25.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS25_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS25.Reg, volatile.LoadUint32(&o.CFDRMFDSTS25.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS25_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS25.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF25_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_0.Reg, volatile.LoadUint32(&o.CFDRMDF25_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_0.Reg, volatile.LoadUint32(&o.CFDRMDF25_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_0.Reg, volatile.LoadUint32(&o.CFDRMDF25_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_0.Reg, volatile.LoadUint32(&o.CFDRMDF25_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_1.Reg, volatile.LoadUint32(&o.CFDRMDF25_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_1.Reg, volatile.LoadUint32(&o.CFDRMDF25_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_1.Reg, volatile.LoadUint32(&o.CFDRMDF25_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_1.Reg, volatile.LoadUint32(&o.CFDRMDF25_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_2.Reg, volatile.LoadUint32(&o.CFDRMDF25_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_2.Reg, volatile.LoadUint32(&o.CFDRMDF25_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_2.Reg, volatile.LoadUint32(&o.CFDRMDF25_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_2.Reg, volatile.LoadUint32(&o.CFDRMDF25_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_3.Reg, volatile.LoadUint32(&o.CFDRMDF25_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_3.Reg, volatile.LoadUint32(&o.CFDRMDF25_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_3.Reg, volatile.LoadUint32(&o.CFDRMDF25_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_3.Reg, volatile.LoadUint32(&o.CFDRMDF25_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_4.Reg, volatile.LoadUint32(&o.CFDRMDF25_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_4.Reg, volatile.LoadUint32(&o.CFDRMDF25_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_4.Reg, volatile.LoadUint32(&o.CFDRMDF25_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_4.Reg, volatile.LoadUint32(&o.CFDRMDF25_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_5.Reg, volatile.LoadUint32(&o.CFDRMDF25_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_5.Reg, volatile.LoadUint32(&o.CFDRMDF25_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_5.Reg, volatile.LoadUint32(&o.CFDRMDF25_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_5.Reg, volatile.LoadUint32(&o.CFDRMDF25_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_6.Reg, volatile.LoadUint32(&o.CFDRMDF25_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_6.Reg, volatile.LoadUint32(&o.CFDRMDF25_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_6.Reg, volatile.LoadUint32(&o.CFDRMDF25_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_6.Reg, volatile.LoadUint32(&o.CFDRMDF25_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_7.Reg, volatile.LoadUint32(&o.CFDRMDF25_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_7.Reg, volatile.LoadUint32(&o.CFDRMDF25_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_7.Reg, volatile.LoadUint32(&o.CFDRMDF25_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_7.Reg, volatile.LoadUint32(&o.CFDRMDF25_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_8.Reg, volatile.LoadUint32(&o.CFDRMDF25_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_8.Reg, volatile.LoadUint32(&o.CFDRMDF25_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_8.Reg, volatile.LoadUint32(&o.CFDRMDF25_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_8.Reg, volatile.LoadUint32(&o.CFDRMDF25_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_9.Reg, volatile.LoadUint32(&o.CFDRMDF25_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_9.Reg, volatile.LoadUint32(&o.CFDRMDF25_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_9.Reg, volatile.LoadUint32(&o.CFDRMDF25_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_9.Reg, volatile.LoadUint32(&o.CFDRMDF25_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_10.Reg, volatile.LoadUint32(&o.CFDRMDF25_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_10.Reg, volatile.LoadUint32(&o.CFDRMDF25_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_10.Reg, volatile.LoadUint32(&o.CFDRMDF25_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_10.Reg, volatile.LoadUint32(&o.CFDRMDF25_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_11.Reg, volatile.LoadUint32(&o.CFDRMDF25_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_11.Reg, volatile.LoadUint32(&o.CFDRMDF25_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_11.Reg, volatile.LoadUint32(&o.CFDRMDF25_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_11.Reg, volatile.LoadUint32(&o.CFDRMDF25_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_12.Reg, volatile.LoadUint32(&o.CFDRMDF25_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_12.Reg, volatile.LoadUint32(&o.CFDRMDF25_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_12.Reg, volatile.LoadUint32(&o.CFDRMDF25_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_12.Reg, volatile.LoadUint32(&o.CFDRMDF25_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_13.Reg, volatile.LoadUint32(&o.CFDRMDF25_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_13.Reg, volatile.LoadUint32(&o.CFDRMDF25_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_13.Reg, volatile.LoadUint32(&o.CFDRMDF25_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_13.Reg, volatile.LoadUint32(&o.CFDRMDF25_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_14.Reg, volatile.LoadUint32(&o.CFDRMDF25_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_14.Reg, volatile.LoadUint32(&o.CFDRMDF25_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_14.Reg, volatile.LoadUint32(&o.CFDRMDF25_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_14.Reg, volatile.LoadUint32(&o.CFDRMDF25_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF25_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF25_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_15.Reg, volatile.LoadUint32(&o.CFDRMDF25_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF25_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF25_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF25_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_15.Reg, volatile.LoadUint32(&o.CFDRMDF25_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF25_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF25_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_15.Reg, volatile.LoadUint32(&o.CFDRMDF25_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF25_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF25_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF25_15.Reg, volatile.LoadUint32(&o.CFDRMDF25_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF25_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF25_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID26: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID26_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID26.Reg, volatile.LoadUint32(&o.CFDRMID26.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID26_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID26.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID26_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID26.Reg, volatile.LoadUint32(&o.CFDRMID26.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID26_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID26.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID26_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID26.Reg, volatile.LoadUint32(&o.CFDRMID26.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID26_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID26.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR26: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR26_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR26.Reg, volatile.LoadUint32(&o.CFDRMPTR26.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR26_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR26.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR26_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR26.Reg, volatile.LoadUint32(&o.CFDRMPTR26.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR26_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR26.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS26: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS26_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS26.Reg, volatile.LoadUint32(&o.CFDRMFDSTS26.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS26_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS26.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS26_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS26.Reg, volatile.LoadUint32(&o.CFDRMFDSTS26.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS26_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS26.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS26_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS26.Reg, volatile.LoadUint32(&o.CFDRMFDSTS26.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS26_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS26.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS26_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS26.Reg, volatile.LoadUint32(&o.CFDRMFDSTS26.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS26_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS26.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS26_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS26.Reg, volatile.LoadUint32(&o.CFDRMFDSTS26.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS26_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS26.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF26_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_0.Reg, volatile.LoadUint32(&o.CFDRMDF26_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_0.Reg, volatile.LoadUint32(&o.CFDRMDF26_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_0.Reg, volatile.LoadUint32(&o.CFDRMDF26_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_0.Reg, volatile.LoadUint32(&o.CFDRMDF26_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_1.Reg, volatile.LoadUint32(&o.CFDRMDF26_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_1.Reg, volatile.LoadUint32(&o.CFDRMDF26_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_1.Reg, volatile.LoadUint32(&o.CFDRMDF26_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_1.Reg, volatile.LoadUint32(&o.CFDRMDF26_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_2.Reg, volatile.LoadUint32(&o.CFDRMDF26_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_2.Reg, volatile.LoadUint32(&o.CFDRMDF26_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_2.Reg, volatile.LoadUint32(&o.CFDRMDF26_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_2.Reg, volatile.LoadUint32(&o.CFDRMDF26_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_3.Reg, volatile.LoadUint32(&o.CFDRMDF26_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_3.Reg, volatile.LoadUint32(&o.CFDRMDF26_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_3.Reg, volatile.LoadUint32(&o.CFDRMDF26_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_3.Reg, volatile.LoadUint32(&o.CFDRMDF26_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_4.Reg, volatile.LoadUint32(&o.CFDRMDF26_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_4.Reg, volatile.LoadUint32(&o.CFDRMDF26_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_4.Reg, volatile.LoadUint32(&o.CFDRMDF26_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_4.Reg, volatile.LoadUint32(&o.CFDRMDF26_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_5.Reg, volatile.LoadUint32(&o.CFDRMDF26_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_5.Reg, volatile.LoadUint32(&o.CFDRMDF26_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_5.Reg, volatile.LoadUint32(&o.CFDRMDF26_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_5.Reg, volatile.LoadUint32(&o.CFDRMDF26_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_6.Reg, volatile.LoadUint32(&o.CFDRMDF26_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_6.Reg, volatile.LoadUint32(&o.CFDRMDF26_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_6.Reg, volatile.LoadUint32(&o.CFDRMDF26_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_6.Reg, volatile.LoadUint32(&o.CFDRMDF26_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_7.Reg, volatile.LoadUint32(&o.CFDRMDF26_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_7.Reg, volatile.LoadUint32(&o.CFDRMDF26_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_7.Reg, volatile.LoadUint32(&o.CFDRMDF26_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_7.Reg, volatile.LoadUint32(&o.CFDRMDF26_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_8.Reg, volatile.LoadUint32(&o.CFDRMDF26_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_8.Reg, volatile.LoadUint32(&o.CFDRMDF26_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_8.Reg, volatile.LoadUint32(&o.CFDRMDF26_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_8.Reg, volatile.LoadUint32(&o.CFDRMDF26_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_9.Reg, volatile.LoadUint32(&o.CFDRMDF26_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_9.Reg, volatile.LoadUint32(&o.CFDRMDF26_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_9.Reg, volatile.LoadUint32(&o.CFDRMDF26_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_9.Reg, volatile.LoadUint32(&o.CFDRMDF26_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_10.Reg, volatile.LoadUint32(&o.CFDRMDF26_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_10.Reg, volatile.LoadUint32(&o.CFDRMDF26_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_10.Reg, volatile.LoadUint32(&o.CFDRMDF26_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_10.Reg, volatile.LoadUint32(&o.CFDRMDF26_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_11.Reg, volatile.LoadUint32(&o.CFDRMDF26_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_11.Reg, volatile.LoadUint32(&o.CFDRMDF26_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_11.Reg, volatile.LoadUint32(&o.CFDRMDF26_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_11.Reg, volatile.LoadUint32(&o.CFDRMDF26_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_12.Reg, volatile.LoadUint32(&o.CFDRMDF26_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_12.Reg, volatile.LoadUint32(&o.CFDRMDF26_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_12.Reg, volatile.LoadUint32(&o.CFDRMDF26_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_12.Reg, volatile.LoadUint32(&o.CFDRMDF26_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_13.Reg, volatile.LoadUint32(&o.CFDRMDF26_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_13.Reg, volatile.LoadUint32(&o.CFDRMDF26_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_13.Reg, volatile.LoadUint32(&o.CFDRMDF26_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_13.Reg, volatile.LoadUint32(&o.CFDRMDF26_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_14.Reg, volatile.LoadUint32(&o.CFDRMDF26_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_14.Reg, volatile.LoadUint32(&o.CFDRMDF26_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_14.Reg, volatile.LoadUint32(&o.CFDRMDF26_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_14.Reg, volatile.LoadUint32(&o.CFDRMDF26_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF26_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF26_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_15.Reg, volatile.LoadUint32(&o.CFDRMDF26_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF26_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF26_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF26_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_15.Reg, volatile.LoadUint32(&o.CFDRMDF26_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF26_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF26_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_15.Reg, volatile.LoadUint32(&o.CFDRMDF26_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF26_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF26_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF26_15.Reg, volatile.LoadUint32(&o.CFDRMDF26_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF26_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF26_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID27: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID27_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID27.Reg, volatile.LoadUint32(&o.CFDRMID27.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID27_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID27.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID27_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID27.Reg, volatile.LoadUint32(&o.CFDRMID27.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID27_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID27.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID27_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID27.Reg, volatile.LoadUint32(&o.CFDRMID27.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID27_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID27.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR27: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR27_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR27.Reg, volatile.LoadUint32(&o.CFDRMPTR27.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR27_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR27.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR27_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR27.Reg, volatile.LoadUint32(&o.CFDRMPTR27.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR27_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR27.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS27: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS27_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS27.Reg, volatile.LoadUint32(&o.CFDRMFDSTS27.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS27_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS27.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS27_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS27.Reg, volatile.LoadUint32(&o.CFDRMFDSTS27.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS27_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS27.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS27_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS27.Reg, volatile.LoadUint32(&o.CFDRMFDSTS27.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS27_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS27.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS27_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS27.Reg, volatile.LoadUint32(&o.CFDRMFDSTS27.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS27_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS27.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS27_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS27.Reg, volatile.LoadUint32(&o.CFDRMFDSTS27.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS27_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS27.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF27_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_0.Reg, volatile.LoadUint32(&o.CFDRMDF27_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_0.Reg, volatile.LoadUint32(&o.CFDRMDF27_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_0.Reg, volatile.LoadUint32(&o.CFDRMDF27_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_0.Reg, volatile.LoadUint32(&o.CFDRMDF27_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_1.Reg, volatile.LoadUint32(&o.CFDRMDF27_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_1.Reg, volatile.LoadUint32(&o.CFDRMDF27_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_1.Reg, volatile.LoadUint32(&o.CFDRMDF27_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_1.Reg, volatile.LoadUint32(&o.CFDRMDF27_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_2.Reg, volatile.LoadUint32(&o.CFDRMDF27_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_2.Reg, volatile.LoadUint32(&o.CFDRMDF27_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_2.Reg, volatile.LoadUint32(&o.CFDRMDF27_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_2.Reg, volatile.LoadUint32(&o.CFDRMDF27_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_3.Reg, volatile.LoadUint32(&o.CFDRMDF27_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_3.Reg, volatile.LoadUint32(&o.CFDRMDF27_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_3.Reg, volatile.LoadUint32(&o.CFDRMDF27_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_3.Reg, volatile.LoadUint32(&o.CFDRMDF27_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_4.Reg, volatile.LoadUint32(&o.CFDRMDF27_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_4.Reg, volatile.LoadUint32(&o.CFDRMDF27_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_4.Reg, volatile.LoadUint32(&o.CFDRMDF27_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_4.Reg, volatile.LoadUint32(&o.CFDRMDF27_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_5.Reg, volatile.LoadUint32(&o.CFDRMDF27_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_5.Reg, volatile.LoadUint32(&o.CFDRMDF27_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_5.Reg, volatile.LoadUint32(&o.CFDRMDF27_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_5.Reg, volatile.LoadUint32(&o.CFDRMDF27_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_6.Reg, volatile.LoadUint32(&o.CFDRMDF27_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_6.Reg, volatile.LoadUint32(&o.CFDRMDF27_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_6.Reg, volatile.LoadUint32(&o.CFDRMDF27_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_6.Reg, volatile.LoadUint32(&o.CFDRMDF27_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_7.Reg, volatile.LoadUint32(&o.CFDRMDF27_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_7.Reg, volatile.LoadUint32(&o.CFDRMDF27_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_7.Reg, volatile.LoadUint32(&o.CFDRMDF27_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_7.Reg, volatile.LoadUint32(&o.CFDRMDF27_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_8.Reg, volatile.LoadUint32(&o.CFDRMDF27_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_8.Reg, volatile.LoadUint32(&o.CFDRMDF27_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_8.Reg, volatile.LoadUint32(&o.CFDRMDF27_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_8.Reg, volatile.LoadUint32(&o.CFDRMDF27_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_9.Reg, volatile.LoadUint32(&o.CFDRMDF27_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_9.Reg, volatile.LoadUint32(&o.CFDRMDF27_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_9.Reg, volatile.LoadUint32(&o.CFDRMDF27_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_9.Reg, volatile.LoadUint32(&o.CFDRMDF27_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_10.Reg, volatile.LoadUint32(&o.CFDRMDF27_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_10.Reg, volatile.LoadUint32(&o.CFDRMDF27_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_10.Reg, volatile.LoadUint32(&o.CFDRMDF27_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_10.Reg, volatile.LoadUint32(&o.CFDRMDF27_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_11.Reg, volatile.LoadUint32(&o.CFDRMDF27_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_11.Reg, volatile.LoadUint32(&o.CFDRMDF27_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_11.Reg, volatile.LoadUint32(&o.CFDRMDF27_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_11.Reg, volatile.LoadUint32(&o.CFDRMDF27_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_12.Reg, volatile.LoadUint32(&o.CFDRMDF27_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_12.Reg, volatile.LoadUint32(&o.CFDRMDF27_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_12.Reg, volatile.LoadUint32(&o.CFDRMDF27_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_12.Reg, volatile.LoadUint32(&o.CFDRMDF27_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_13.Reg, volatile.LoadUint32(&o.CFDRMDF27_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_13.Reg, volatile.LoadUint32(&o.CFDRMDF27_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_13.Reg, volatile.LoadUint32(&o.CFDRMDF27_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_13.Reg, volatile.LoadUint32(&o.CFDRMDF27_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_14.Reg, volatile.LoadUint32(&o.CFDRMDF27_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_14.Reg, volatile.LoadUint32(&o.CFDRMDF27_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_14.Reg, volatile.LoadUint32(&o.CFDRMDF27_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_14.Reg, volatile.LoadUint32(&o.CFDRMDF27_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF27_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF27_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_15.Reg, volatile.LoadUint32(&o.CFDRMDF27_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF27_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF27_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF27_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_15.Reg, volatile.LoadUint32(&o.CFDRMDF27_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF27_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF27_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_15.Reg, volatile.LoadUint32(&o.CFDRMDF27_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF27_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF27_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF27_15.Reg, volatile.LoadUint32(&o.CFDRMDF27_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF27_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF27_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID28: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID28_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID28.Reg, volatile.LoadUint32(&o.CFDRMID28.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID28_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID28.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID28_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID28.Reg, volatile.LoadUint32(&o.CFDRMID28.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID28_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID28.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID28_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID28.Reg, volatile.LoadUint32(&o.CFDRMID28.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID28_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID28.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR28: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR28_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR28.Reg, volatile.LoadUint32(&o.CFDRMPTR28.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR28_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR28.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR28_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR28.Reg, volatile.LoadUint32(&o.CFDRMPTR28.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR28_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR28.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS28: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS28_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS28.Reg, volatile.LoadUint32(&o.CFDRMFDSTS28.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS28_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS28.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS28_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS28.Reg, volatile.LoadUint32(&o.CFDRMFDSTS28.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS28_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS28.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS28_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS28.Reg, volatile.LoadUint32(&o.CFDRMFDSTS28.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS28_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS28.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS28_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS28.Reg, volatile.LoadUint32(&o.CFDRMFDSTS28.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS28_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS28.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS28_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS28.Reg, volatile.LoadUint32(&o.CFDRMFDSTS28.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS28_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS28.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF28_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_0.Reg, volatile.LoadUint32(&o.CFDRMDF28_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_0.Reg, volatile.LoadUint32(&o.CFDRMDF28_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_0.Reg, volatile.LoadUint32(&o.CFDRMDF28_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_0.Reg, volatile.LoadUint32(&o.CFDRMDF28_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_1.Reg, volatile.LoadUint32(&o.CFDRMDF28_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_1.Reg, volatile.LoadUint32(&o.CFDRMDF28_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_1.Reg, volatile.LoadUint32(&o.CFDRMDF28_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_1.Reg, volatile.LoadUint32(&o.CFDRMDF28_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_2.Reg, volatile.LoadUint32(&o.CFDRMDF28_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_2.Reg, volatile.LoadUint32(&o.CFDRMDF28_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_2.Reg, volatile.LoadUint32(&o.CFDRMDF28_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_2.Reg, volatile.LoadUint32(&o.CFDRMDF28_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_3.Reg, volatile.LoadUint32(&o.CFDRMDF28_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_3.Reg, volatile.LoadUint32(&o.CFDRMDF28_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_3.Reg, volatile.LoadUint32(&o.CFDRMDF28_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_3.Reg, volatile.LoadUint32(&o.CFDRMDF28_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_4.Reg, volatile.LoadUint32(&o.CFDRMDF28_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_4.Reg, volatile.LoadUint32(&o.CFDRMDF28_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_4.Reg, volatile.LoadUint32(&o.CFDRMDF28_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_4.Reg, volatile.LoadUint32(&o.CFDRMDF28_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_5.Reg, volatile.LoadUint32(&o.CFDRMDF28_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_5.Reg, volatile.LoadUint32(&o.CFDRMDF28_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_5.Reg, volatile.LoadUint32(&o.CFDRMDF28_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_5.Reg, volatile.LoadUint32(&o.CFDRMDF28_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_6.Reg, volatile.LoadUint32(&o.CFDRMDF28_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_6.Reg, volatile.LoadUint32(&o.CFDRMDF28_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_6.Reg, volatile.LoadUint32(&o.CFDRMDF28_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_6.Reg, volatile.LoadUint32(&o.CFDRMDF28_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_7.Reg, volatile.LoadUint32(&o.CFDRMDF28_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_7.Reg, volatile.LoadUint32(&o.CFDRMDF28_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_7.Reg, volatile.LoadUint32(&o.CFDRMDF28_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_7.Reg, volatile.LoadUint32(&o.CFDRMDF28_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_8.Reg, volatile.LoadUint32(&o.CFDRMDF28_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_8.Reg, volatile.LoadUint32(&o.CFDRMDF28_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_8.Reg, volatile.LoadUint32(&o.CFDRMDF28_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_8.Reg, volatile.LoadUint32(&o.CFDRMDF28_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_9.Reg, volatile.LoadUint32(&o.CFDRMDF28_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_9.Reg, volatile.LoadUint32(&o.CFDRMDF28_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_9.Reg, volatile.LoadUint32(&o.CFDRMDF28_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_9.Reg, volatile.LoadUint32(&o.CFDRMDF28_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_10.Reg, volatile.LoadUint32(&o.CFDRMDF28_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_10.Reg, volatile.LoadUint32(&o.CFDRMDF28_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_10.Reg, volatile.LoadUint32(&o.CFDRMDF28_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_10.Reg, volatile.LoadUint32(&o.CFDRMDF28_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_11.Reg, volatile.LoadUint32(&o.CFDRMDF28_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_11.Reg, volatile.LoadUint32(&o.CFDRMDF28_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_11.Reg, volatile.LoadUint32(&o.CFDRMDF28_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_11.Reg, volatile.LoadUint32(&o.CFDRMDF28_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_12.Reg, volatile.LoadUint32(&o.CFDRMDF28_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_12.Reg, volatile.LoadUint32(&o.CFDRMDF28_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_12.Reg, volatile.LoadUint32(&o.CFDRMDF28_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_12.Reg, volatile.LoadUint32(&o.CFDRMDF28_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_13.Reg, volatile.LoadUint32(&o.CFDRMDF28_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_13.Reg, volatile.LoadUint32(&o.CFDRMDF28_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_13.Reg, volatile.LoadUint32(&o.CFDRMDF28_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_13.Reg, volatile.LoadUint32(&o.CFDRMDF28_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_14.Reg, volatile.LoadUint32(&o.CFDRMDF28_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_14.Reg, volatile.LoadUint32(&o.CFDRMDF28_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_14.Reg, volatile.LoadUint32(&o.CFDRMDF28_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_14.Reg, volatile.LoadUint32(&o.CFDRMDF28_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF28_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF28_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_15.Reg, volatile.LoadUint32(&o.CFDRMDF28_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF28_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF28_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF28_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_15.Reg, volatile.LoadUint32(&o.CFDRMDF28_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF28_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF28_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_15.Reg, volatile.LoadUint32(&o.CFDRMDF28_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF28_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF28_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF28_15.Reg, volatile.LoadUint32(&o.CFDRMDF28_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF28_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF28_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID29: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID29_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID29.Reg, volatile.LoadUint32(&o.CFDRMID29.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID29_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID29.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID29_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID29.Reg, volatile.LoadUint32(&o.CFDRMID29.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID29_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID29.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID29_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID29.Reg, volatile.LoadUint32(&o.CFDRMID29.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID29_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID29.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR29: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR29_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR29.Reg, volatile.LoadUint32(&o.CFDRMPTR29.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR29_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR29.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR29_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR29.Reg, volatile.LoadUint32(&o.CFDRMPTR29.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR29_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR29.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS29: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS29_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS29.Reg, volatile.LoadUint32(&o.CFDRMFDSTS29.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS29_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS29.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS29_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS29.Reg, volatile.LoadUint32(&o.CFDRMFDSTS29.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS29_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS29.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS29_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS29.Reg, volatile.LoadUint32(&o.CFDRMFDSTS29.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS29_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS29.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS29_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS29.Reg, volatile.LoadUint32(&o.CFDRMFDSTS29.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS29_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS29.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS29_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS29.Reg, volatile.LoadUint32(&o.CFDRMFDSTS29.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS29_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS29.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF29_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_0.Reg, volatile.LoadUint32(&o.CFDRMDF29_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_0.Reg, volatile.LoadUint32(&o.CFDRMDF29_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_0.Reg, volatile.LoadUint32(&o.CFDRMDF29_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_0.Reg, volatile.LoadUint32(&o.CFDRMDF29_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_1.Reg, volatile.LoadUint32(&o.CFDRMDF29_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_1.Reg, volatile.LoadUint32(&o.CFDRMDF29_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_1.Reg, volatile.LoadUint32(&o.CFDRMDF29_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_1.Reg, volatile.LoadUint32(&o.CFDRMDF29_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_2.Reg, volatile.LoadUint32(&o.CFDRMDF29_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_2.Reg, volatile.LoadUint32(&o.CFDRMDF29_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_2.Reg, volatile.LoadUint32(&o.CFDRMDF29_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_2.Reg, volatile.LoadUint32(&o.CFDRMDF29_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_3.Reg, volatile.LoadUint32(&o.CFDRMDF29_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_3.Reg, volatile.LoadUint32(&o.CFDRMDF29_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_3.Reg, volatile.LoadUint32(&o.CFDRMDF29_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_3.Reg, volatile.LoadUint32(&o.CFDRMDF29_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_4.Reg, volatile.LoadUint32(&o.CFDRMDF29_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_4.Reg, volatile.LoadUint32(&o.CFDRMDF29_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_4.Reg, volatile.LoadUint32(&o.CFDRMDF29_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_4.Reg, volatile.LoadUint32(&o.CFDRMDF29_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_5.Reg, volatile.LoadUint32(&o.CFDRMDF29_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_5.Reg, volatile.LoadUint32(&o.CFDRMDF29_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_5.Reg, volatile.LoadUint32(&o.CFDRMDF29_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_5.Reg, volatile.LoadUint32(&o.CFDRMDF29_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_6.Reg, volatile.LoadUint32(&o.CFDRMDF29_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_6.Reg, volatile.LoadUint32(&o.CFDRMDF29_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_6.Reg, volatile.LoadUint32(&o.CFDRMDF29_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_6.Reg, volatile.LoadUint32(&o.CFDRMDF29_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_7.Reg, volatile.LoadUint32(&o.CFDRMDF29_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_7.Reg, volatile.LoadUint32(&o.CFDRMDF29_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_7.Reg, volatile.LoadUint32(&o.CFDRMDF29_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_7.Reg, volatile.LoadUint32(&o.CFDRMDF29_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_8.Reg, volatile.LoadUint32(&o.CFDRMDF29_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_8.Reg, volatile.LoadUint32(&o.CFDRMDF29_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_8.Reg, volatile.LoadUint32(&o.CFDRMDF29_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_8.Reg, volatile.LoadUint32(&o.CFDRMDF29_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_9.Reg, volatile.LoadUint32(&o.CFDRMDF29_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_9.Reg, volatile.LoadUint32(&o.CFDRMDF29_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_9.Reg, volatile.LoadUint32(&o.CFDRMDF29_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_9.Reg, volatile.LoadUint32(&o.CFDRMDF29_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_10.Reg, volatile.LoadUint32(&o.CFDRMDF29_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_10.Reg, volatile.LoadUint32(&o.CFDRMDF29_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_10.Reg, volatile.LoadUint32(&o.CFDRMDF29_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_10.Reg, volatile.LoadUint32(&o.CFDRMDF29_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_11.Reg, volatile.LoadUint32(&o.CFDRMDF29_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_11.Reg, volatile.LoadUint32(&o.CFDRMDF29_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_11.Reg, volatile.LoadUint32(&o.CFDRMDF29_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_11.Reg, volatile.LoadUint32(&o.CFDRMDF29_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_12.Reg, volatile.LoadUint32(&o.CFDRMDF29_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_12.Reg, volatile.LoadUint32(&o.CFDRMDF29_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_12.Reg, volatile.LoadUint32(&o.CFDRMDF29_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_12.Reg, volatile.LoadUint32(&o.CFDRMDF29_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_13.Reg, volatile.LoadUint32(&o.CFDRMDF29_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_13.Reg, volatile.LoadUint32(&o.CFDRMDF29_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_13.Reg, volatile.LoadUint32(&o.CFDRMDF29_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_13.Reg, volatile.LoadUint32(&o.CFDRMDF29_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_14.Reg, volatile.LoadUint32(&o.CFDRMDF29_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_14.Reg, volatile.LoadUint32(&o.CFDRMDF29_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_14.Reg, volatile.LoadUint32(&o.CFDRMDF29_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_14.Reg, volatile.LoadUint32(&o.CFDRMDF29_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF29_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF29_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_15.Reg, volatile.LoadUint32(&o.CFDRMDF29_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF29_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF29_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF29_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_15.Reg, volatile.LoadUint32(&o.CFDRMDF29_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF29_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF29_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_15.Reg, volatile.LoadUint32(&o.CFDRMDF29_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF29_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF29_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF29_15.Reg, volatile.LoadUint32(&o.CFDRMDF29_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF29_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF29_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID30: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID30_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID30.Reg, volatile.LoadUint32(&o.CFDRMID30.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID30_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID30.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID30_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID30.Reg, volatile.LoadUint32(&o.CFDRMID30.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID30_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID30.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID30_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID30.Reg, volatile.LoadUint32(&o.CFDRMID30.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID30_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID30.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR30: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR30_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR30.Reg, volatile.LoadUint32(&o.CFDRMPTR30.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR30_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR30.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR30_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR30.Reg, volatile.LoadUint32(&o.CFDRMPTR30.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR30_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR30.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS30: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS30_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS30.Reg, volatile.LoadUint32(&o.CFDRMFDSTS30.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS30_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS30.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS30_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS30.Reg, volatile.LoadUint32(&o.CFDRMFDSTS30.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS30_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS30.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS30_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS30.Reg, volatile.LoadUint32(&o.CFDRMFDSTS30.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS30_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS30.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS30_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS30.Reg, volatile.LoadUint32(&o.CFDRMFDSTS30.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS30_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS30.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS30_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS30.Reg, volatile.LoadUint32(&o.CFDRMFDSTS30.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS30_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS30.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF30_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_0.Reg, volatile.LoadUint32(&o.CFDRMDF30_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_0.Reg, volatile.LoadUint32(&o.CFDRMDF30_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_0.Reg, volatile.LoadUint32(&o.CFDRMDF30_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_0.Reg, volatile.LoadUint32(&o.CFDRMDF30_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_1.Reg, volatile.LoadUint32(&o.CFDRMDF30_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_1.Reg, volatile.LoadUint32(&o.CFDRMDF30_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_1.Reg, volatile.LoadUint32(&o.CFDRMDF30_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_1.Reg, volatile.LoadUint32(&o.CFDRMDF30_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_2.Reg, volatile.LoadUint32(&o.CFDRMDF30_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_2.Reg, volatile.LoadUint32(&o.CFDRMDF30_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_2.Reg, volatile.LoadUint32(&o.CFDRMDF30_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_2.Reg, volatile.LoadUint32(&o.CFDRMDF30_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_3.Reg, volatile.LoadUint32(&o.CFDRMDF30_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_3.Reg, volatile.LoadUint32(&o.CFDRMDF30_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_3.Reg, volatile.LoadUint32(&o.CFDRMDF30_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_3.Reg, volatile.LoadUint32(&o.CFDRMDF30_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_4.Reg, volatile.LoadUint32(&o.CFDRMDF30_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_4.Reg, volatile.LoadUint32(&o.CFDRMDF30_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_4.Reg, volatile.LoadUint32(&o.CFDRMDF30_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_4.Reg, volatile.LoadUint32(&o.CFDRMDF30_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_5.Reg, volatile.LoadUint32(&o.CFDRMDF30_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_5.Reg, volatile.LoadUint32(&o.CFDRMDF30_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_5.Reg, volatile.LoadUint32(&o.CFDRMDF30_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_5.Reg, volatile.LoadUint32(&o.CFDRMDF30_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_6.Reg, volatile.LoadUint32(&o.CFDRMDF30_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_6.Reg, volatile.LoadUint32(&o.CFDRMDF30_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_6.Reg, volatile.LoadUint32(&o.CFDRMDF30_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_6.Reg, volatile.LoadUint32(&o.CFDRMDF30_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_7.Reg, volatile.LoadUint32(&o.CFDRMDF30_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_7.Reg, volatile.LoadUint32(&o.CFDRMDF30_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_7.Reg, volatile.LoadUint32(&o.CFDRMDF30_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_7.Reg, volatile.LoadUint32(&o.CFDRMDF30_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_8.Reg, volatile.LoadUint32(&o.CFDRMDF30_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_8.Reg, volatile.LoadUint32(&o.CFDRMDF30_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_8.Reg, volatile.LoadUint32(&o.CFDRMDF30_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_8.Reg, volatile.LoadUint32(&o.CFDRMDF30_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_9.Reg, volatile.LoadUint32(&o.CFDRMDF30_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_9.Reg, volatile.LoadUint32(&o.CFDRMDF30_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_9.Reg, volatile.LoadUint32(&o.CFDRMDF30_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_9.Reg, volatile.LoadUint32(&o.CFDRMDF30_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_10.Reg, volatile.LoadUint32(&o.CFDRMDF30_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_10.Reg, volatile.LoadUint32(&o.CFDRMDF30_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_10.Reg, volatile.LoadUint32(&o.CFDRMDF30_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_10.Reg, volatile.LoadUint32(&o.CFDRMDF30_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_11.Reg, volatile.LoadUint32(&o.CFDRMDF30_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_11.Reg, volatile.LoadUint32(&o.CFDRMDF30_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_11.Reg, volatile.LoadUint32(&o.CFDRMDF30_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_11.Reg, volatile.LoadUint32(&o.CFDRMDF30_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_12.Reg, volatile.LoadUint32(&o.CFDRMDF30_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_12.Reg, volatile.LoadUint32(&o.CFDRMDF30_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_12.Reg, volatile.LoadUint32(&o.CFDRMDF30_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_12.Reg, volatile.LoadUint32(&o.CFDRMDF30_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_13.Reg, volatile.LoadUint32(&o.CFDRMDF30_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_13.Reg, volatile.LoadUint32(&o.CFDRMDF30_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_13.Reg, volatile.LoadUint32(&o.CFDRMDF30_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_13.Reg, volatile.LoadUint32(&o.CFDRMDF30_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_14.Reg, volatile.LoadUint32(&o.CFDRMDF30_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_14.Reg, volatile.LoadUint32(&o.CFDRMDF30_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_14.Reg, volatile.LoadUint32(&o.CFDRMDF30_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_14.Reg, volatile.LoadUint32(&o.CFDRMDF30_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF30_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF30_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_15.Reg, volatile.LoadUint32(&o.CFDRMDF30_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF30_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF30_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF30_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_15.Reg, volatile.LoadUint32(&o.CFDRMDF30_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF30_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF30_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_15.Reg, volatile.LoadUint32(&o.CFDRMDF30_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF30_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF30_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF30_15.Reg, volatile.LoadUint32(&o.CFDRMDF30_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF30_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF30_15.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMID31: RX Message Buffer ID Registers
func (o *CANFD_B_Type) SetCFDRMID31_RMID(value uint32) {
	volatile.StoreUint32(&o.CFDRMID31.Reg, volatile.LoadUint32(&o.CFDRMID31.Reg)&^(0x1fffffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMID31_RMID() uint32 {
	return volatile.LoadUint32(&o.CFDRMID31.Reg) & 0x1fffffff
}
func (o *CANFD_B_Type) SetCFDRMID31_RMRTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMID31.Reg, volatile.LoadUint32(&o.CFDRMID31.Reg)&^(0x40000000)|value<<30)
}
func (o *CANFD_B_Type) GetCFDRMID31_RMRTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID31.Reg) & 0x40000000) >> 30
}
func (o *CANFD_B_Type) SetCFDRMID31_RMIDE(value uint32) {
	volatile.StoreUint32(&o.CFDRMID31.Reg, volatile.LoadUint32(&o.CFDRMID31.Reg)&^(0x80000000)|value<<31)
}
func (o *CANFD_B_Type) GetCFDRMID31_RMIDE() uint32 {
	return (volatile.LoadUint32(&o.CFDRMID31.Reg) & 0x80000000) >> 31
}

// CANFD_B.CFDRMPTR31: RX Message Buffer Pointer Registers
func (o *CANFD_B_Type) SetCFDRMPTR31_RMTS(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR31.Reg, volatile.LoadUint32(&o.CFDRMPTR31.Reg)&^(0xffff)|value)
}
func (o *CANFD_B_Type) GetCFDRMPTR31_RMTS() uint32 {
	return volatile.LoadUint32(&o.CFDRMPTR31.Reg) & 0xffff
}
func (o *CANFD_B_Type) SetCFDRMPTR31_RMDLC(value uint32) {
	volatile.StoreUint32(&o.CFDRMPTR31.Reg, volatile.LoadUint32(&o.CFDRMPTR31.Reg)&^(0xf0000000)|value<<28)
}
func (o *CANFD_B_Type) GetCFDRMPTR31_RMDLC() uint32 {
	return (volatile.LoadUint32(&o.CFDRMPTR31.Reg) & 0xf0000000) >> 28
}

// CANFD_B.CFDRMFDSTS31: RX Message Buffer CANFD Status Registers
func (o *CANFD_B_Type) SetCFDRMFDSTS31_RMESI(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS31.Reg, volatile.LoadUint32(&o.CFDRMFDSTS31.Reg)&^(0x1)|value)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS31_RMESI() uint32 {
	return volatile.LoadUint32(&o.CFDRMFDSTS31.Reg) & 0x1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS31_RMBRS(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS31.Reg, volatile.LoadUint32(&o.CFDRMFDSTS31.Reg)&^(0x2)|value<<1)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS31_RMBRS() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS31.Reg) & 0x2) >> 1
}
func (o *CANFD_B_Type) SetCFDRMFDSTS31_RMFDF(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS31.Reg, volatile.LoadUint32(&o.CFDRMFDSTS31.Reg)&^(0x4)|value<<2)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS31_RMFDF() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS31.Reg) & 0x4) >> 2
}
func (o *CANFD_B_Type) SetCFDRMFDSTS31_RMIFL(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS31.Reg, volatile.LoadUint32(&o.CFDRMFDSTS31.Reg)&^(0x300)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS31_RMIFL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS31.Reg) & 0x300) >> 8
}
func (o *CANFD_B_Type) SetCFDRMFDSTS31_RMPTR(value uint32) {
	volatile.StoreUint32(&o.CFDRMFDSTS31.Reg, volatile.LoadUint32(&o.CFDRMFDSTS31.Reg)&^(0xffff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMFDSTS31_RMPTR() uint32 {
	return (volatile.LoadUint32(&o.CFDRMFDSTS31.Reg) & 0xffff0000) >> 16
}

// CANFD_B.CFDRMDF31_0: RX Message Buffer Data Field 0 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_0_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_0.Reg, volatile.LoadUint32(&o.CFDRMDF31_0.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_0_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_0.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_0_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_0.Reg, volatile.LoadUint32(&o.CFDRMDF31_0.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_0_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_0.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_0_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_0.Reg, volatile.LoadUint32(&o.CFDRMDF31_0.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_0_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_0.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_0_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_0.Reg, volatile.LoadUint32(&o.CFDRMDF31_0.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_0_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_0.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_1: RX Message Buffer Data Field 1 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_1_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_1.Reg, volatile.LoadUint32(&o.CFDRMDF31_1.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_1_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_1.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_1_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_1.Reg, volatile.LoadUint32(&o.CFDRMDF31_1.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_1_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_1.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_1_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_1.Reg, volatile.LoadUint32(&o.CFDRMDF31_1.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_1_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_1.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_1_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_1.Reg, volatile.LoadUint32(&o.CFDRMDF31_1.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_1_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_1.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_2: RX Message Buffer Data Field 2 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_2_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_2.Reg, volatile.LoadUint32(&o.CFDRMDF31_2.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_2_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_2.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_2_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_2.Reg, volatile.LoadUint32(&o.CFDRMDF31_2.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_2_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_2.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_2_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_2.Reg, volatile.LoadUint32(&o.CFDRMDF31_2.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_2_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_2.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_2_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_2.Reg, volatile.LoadUint32(&o.CFDRMDF31_2.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_2_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_2.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_3: RX Message Buffer Data Field 3 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_3_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_3.Reg, volatile.LoadUint32(&o.CFDRMDF31_3.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_3_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_3.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_3_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_3.Reg, volatile.LoadUint32(&o.CFDRMDF31_3.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_3_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_3.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_3_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_3.Reg, volatile.LoadUint32(&o.CFDRMDF31_3.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_3_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_3.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_3_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_3.Reg, volatile.LoadUint32(&o.CFDRMDF31_3.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_3_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_3.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_4: RX Message Buffer Data Field 4 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_4_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_4.Reg, volatile.LoadUint32(&o.CFDRMDF31_4.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_4_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_4.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_4_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_4.Reg, volatile.LoadUint32(&o.CFDRMDF31_4.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_4_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_4.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_4_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_4.Reg, volatile.LoadUint32(&o.CFDRMDF31_4.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_4_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_4.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_4_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_4.Reg, volatile.LoadUint32(&o.CFDRMDF31_4.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_4_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_4.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_5: RX Message Buffer Data Field 5 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_5_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_5.Reg, volatile.LoadUint32(&o.CFDRMDF31_5.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_5_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_5.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_5_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_5.Reg, volatile.LoadUint32(&o.CFDRMDF31_5.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_5_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_5.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_5_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_5.Reg, volatile.LoadUint32(&o.CFDRMDF31_5.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_5_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_5.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_5_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_5.Reg, volatile.LoadUint32(&o.CFDRMDF31_5.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_5_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_5.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_6: RX Message Buffer Data Field 6 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_6_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_6.Reg, volatile.LoadUint32(&o.CFDRMDF31_6.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_6_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_6.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_6_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_6.Reg, volatile.LoadUint32(&o.CFDRMDF31_6.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_6_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_6.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_6_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_6.Reg, volatile.LoadUint32(&o.CFDRMDF31_6.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_6_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_6.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_6_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_6.Reg, volatile.LoadUint32(&o.CFDRMDF31_6.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_6_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_6.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_7: RX Message Buffer Data Field 7 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_7_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_7.Reg, volatile.LoadUint32(&o.CFDRMDF31_7.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_7_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_7.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_7_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_7.Reg, volatile.LoadUint32(&o.CFDRMDF31_7.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_7_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_7.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_7_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_7.Reg, volatile.LoadUint32(&o.CFDRMDF31_7.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_7_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_7.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_7_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_7.Reg, volatile.LoadUint32(&o.CFDRMDF31_7.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_7_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_7.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_8: RX Message Buffer Data Field 8 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_8_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_8.Reg, volatile.LoadUint32(&o.CFDRMDF31_8.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_8_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_8.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_8_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_8.Reg, volatile.LoadUint32(&o.CFDRMDF31_8.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_8_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_8.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_8_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_8.Reg, volatile.LoadUint32(&o.CFDRMDF31_8.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_8_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_8.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_8_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_8.Reg, volatile.LoadUint32(&o.CFDRMDF31_8.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_8_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_8.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_9: RX Message Buffer Data Field 9 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_9_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_9.Reg, volatile.LoadUint32(&o.CFDRMDF31_9.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_9_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_9.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_9_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_9.Reg, volatile.LoadUint32(&o.CFDRMDF31_9.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_9_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_9.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_9_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_9.Reg, volatile.LoadUint32(&o.CFDRMDF31_9.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_9_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_9.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_9_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_9.Reg, volatile.LoadUint32(&o.CFDRMDF31_9.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_9_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_9.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_10: RX Message Buffer Data Field 10 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_10_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_10.Reg, volatile.LoadUint32(&o.CFDRMDF31_10.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_10_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_10.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_10_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_10.Reg, volatile.LoadUint32(&o.CFDRMDF31_10.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_10_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_10.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_10_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_10.Reg, volatile.LoadUint32(&o.CFDRMDF31_10.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_10_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_10.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_10_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_10.Reg, volatile.LoadUint32(&o.CFDRMDF31_10.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_10_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_10.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_11: RX Message Buffer Data Field 11 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_11_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_11.Reg, volatile.LoadUint32(&o.CFDRMDF31_11.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_11_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_11.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_11_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_11.Reg, volatile.LoadUint32(&o.CFDRMDF31_11.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_11_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_11.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_11_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_11.Reg, volatile.LoadUint32(&o.CFDRMDF31_11.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_11_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_11.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_11_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_11.Reg, volatile.LoadUint32(&o.CFDRMDF31_11.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_11_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_11.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_12: RX Message Buffer Data Field 12 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_12_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_12.Reg, volatile.LoadUint32(&o.CFDRMDF31_12.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_12_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_12.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_12_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_12.Reg, volatile.LoadUint32(&o.CFDRMDF31_12.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_12_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_12.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_12_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_12.Reg, volatile.LoadUint32(&o.CFDRMDF31_12.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_12_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_12.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_12_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_12.Reg, volatile.LoadUint32(&o.CFDRMDF31_12.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_12_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_12.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_13: RX Message Buffer Data Field 13 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_13_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_13.Reg, volatile.LoadUint32(&o.CFDRMDF31_13.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_13_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_13.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_13_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_13.Reg, volatile.LoadUint32(&o.CFDRMDF31_13.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_13_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_13.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_13_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_13.Reg, volatile.LoadUint32(&o.CFDRMDF31_13.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_13_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_13.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_13_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_13.Reg, volatile.LoadUint32(&o.CFDRMDF31_13.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_13_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_13.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_14: RX Message Buffer Data Field 14 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_14_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_14.Reg, volatile.LoadUint32(&o.CFDRMDF31_14.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_14_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_14.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_14_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_14.Reg, volatile.LoadUint32(&o.CFDRMDF31_14.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_14_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_14.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_14_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_14.Reg, volatile.LoadUint32(&o.CFDRMDF31_14.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_14_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_14.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_14_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_14.Reg, volatile.LoadUint32(&o.CFDRMDF31_14.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_14_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_14.Reg) & 0xff000000) >> 24
}

// CANFD_B.CFDRMDF31_15: RX Message Buffer Data Field 15 Registers
func (o *CANFD_B_Type) SetCFDRMDF31_15_RMDB_LL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_15.Reg, volatile.LoadUint32(&o.CFDRMDF31_15.Reg)&^(0xff)|value)
}
func (o *CANFD_B_Type) GetCFDRMDF31_15_RMDB_LL() uint32 {
	return volatile.LoadUint32(&o.CFDRMDF31_15.Reg) & 0xff
}
func (o *CANFD_B_Type) SetCFDRMDF31_15_RMDB_LH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_15.Reg, volatile.LoadUint32(&o.CFDRMDF31_15.Reg)&^(0xff00)|value<<8)
}
func (o *CANFD_B_Type) GetCFDRMDF31_15_RMDB_LH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_15.Reg) & 0xff00) >> 8
}
func (o *CANFD_B_Type) SetCFDRMDF31_15_RMDB_HL(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_15.Reg, volatile.LoadUint32(&o.CFDRMDF31_15.Reg)&^(0xff0000)|value<<16)
}
func (o *CANFD_B_Type) GetCFDRMDF31_15_RMDB_HL() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_15.Reg) & 0xff0000) >> 16
}
func (o *CANFD_B_Type) SetCFDRMDF31_15_RMDB_HH(value uint32) {
	volatile.StoreUint32(&o.CFDRMDF31_15.Reg, volatile.LoadUint32(&o.CFDRMDF31_15.Reg)&^(0xff000000)|value<<24)
}
func (o *CANFD_B_Type) GetCFDRMDF31_15_RMDB_HH() uint32 {
	return (volatile.LoadUint32(&o.CFDRMDF31_15.Reg) & 0xff000000) >> 24
}

// Peripheral Security Control Unit
type PSCU_Type struct {
	_        [4]byte
	PSARB    volatile.Register32 // 0x4
	PSARC    volatile.Register32 // 0x8
	PSARD    volatile.Register32 // 0xC
	PSARE    volatile.Register32 // 0x10
	MSSAR    volatile.Register32 // 0x14
	CFSAMONA volatile.Register32 // 0x18
	CFSAMONB volatile.Register32 // 0x1C
	DFSAMON  volatile.Register32 // 0x20
	SSAMONA  volatile.Register32 // 0x24
	SSAMONB  volatile.Register32 // 0x28
}

// PSCU.PSARB: Peripheral Security Attribution Register B
func (o *PSCU_Type) SetPSARB_PSARB3(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x8)|value<<3)
}
func (o *PSCU_Type) GetPSARB_PSARB3() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x8) >> 3
}
func (o *PSCU_Type) SetPSARB_PSARB4(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x10)|value<<4)
}
func (o *PSCU_Type) GetPSARB_PSARB4() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x10) >> 4
}
func (o *PSCU_Type) SetPSARB_PSARB6(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x40)|value<<6)
}
func (o *PSCU_Type) GetPSARB_PSARB6() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x40) >> 6
}
func (o *PSCU_Type) SetPSARB_PSARB11(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x800)|value<<11)
}
func (o *PSCU_Type) GetPSARB_PSARB11() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x800) >> 11
}
func (o *PSCU_Type) SetPSARB_PSARB18(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x40000)|value<<18)
}
func (o *PSCU_Type) GetPSARB_PSARB18() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x40000) >> 18
}
func (o *PSCU_Type) SetPSARB_PSARB19(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x80000)|value<<19)
}
func (o *PSCU_Type) GetPSARB_PSARB19() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x80000) >> 19
}
func (o *PSCU_Type) SetPSARB_PSARB22(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x400000)|value<<22)
}
func (o *PSCU_Type) GetPSARB_PSARB22() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x400000) >> 22
}
func (o *PSCU_Type) SetPSARB_PSARB31(value uint32) {
	volatile.StoreUint32(&o.PSARB.Reg, volatile.LoadUint32(&o.PSARB.Reg)&^(0x80000000)|value<<31)
}
func (o *PSCU_Type) GetPSARB_PSARB31() uint32 {
	return (volatile.LoadUint32(&o.PSARB.Reg) & 0x80000000) >> 31
}

// PSCU.PSARC: Peripheral Security Attribution Register C
func (o *PSCU_Type) SetPSARC_PSARC0(value uint32) {
	volatile.StoreUint32(&o.PSARC.Reg, volatile.LoadUint32(&o.PSARC.Reg)&^(0x1)|value)
}
func (o *PSCU_Type) GetPSARC_PSARC0() uint32 {
	return volatile.LoadUint32(&o.PSARC.Reg) & 0x1
}
func (o *PSCU_Type) SetPSARC_PSARC1(value uint32) {
	volatile.StoreUint32(&o.PSARC.Reg, volatile.LoadUint32(&o.PSARC.Reg)&^(0x2)|value<<1)
}
func (o *PSCU_Type) GetPSARC_PSARC1() uint32 {
	return (volatile.LoadUint32(&o.PSARC.Reg) & 0x2) >> 1
}
func (o *PSCU_Type) SetPSARC_PSARC8(value uint32) {
	volatile.StoreUint32(&o.PSARC.Reg, volatile.LoadUint32(&o.PSARC.Reg)&^(0x100)|value<<8)
}
func (o *PSCU_Type) GetPSARC_PSARC8() uint32 {
	return (volatile.LoadUint32(&o.PSARC.Reg) & 0x100) >> 8
}
func (o *PSCU_Type) SetPSARC_PSARC13(value uint32) {
	volatile.StoreUint32(&o.PSARC.Reg, volatile.LoadUint32(&o.PSARC.Reg)&^(0x2000)|value<<13)
}
func (o *PSCU_Type) GetPSARC_PSARC13() uint32 {
	return (volatile.LoadUint32(&o.PSARC.Reg) & 0x2000) >> 13
}
func (o *PSCU_Type) SetPSARC_PSARC27(value uint32) {
	volatile.StoreUint32(&o.PSARC.Reg, volatile.LoadUint32(&o.PSARC.Reg)&^(0x8000000)|value<<27)
}
func (o *PSCU_Type) GetPSARC_PSARC27() uint32 {
	return (volatile.LoadUint32(&o.PSARC.Reg) & 0x8000000) >> 27
}
func (o *PSCU_Type) SetPSARC_PSARC28(value uint32) {
	volatile.StoreUint32(&o.PSARC.Reg, volatile.LoadUint32(&o.PSARC.Reg)&^(0x10000000)|value<<28)
}
func (o *PSCU_Type) GetPSARC_PSARC28() uint32 {
	return (volatile.LoadUint32(&o.PSARC.Reg) & 0x10000000) >> 28
}

// PSCU.PSARD: Peripheral Security Attribution Register D
func (o *PSCU_Type) SetPSARD_PSARD2(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x4)|value<<2)
}
func (o *PSCU_Type) GetPSARD_PSARD2() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x4) >> 2
}
func (o *PSCU_Type) SetPSARD_PSARD3(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x8)|value<<3)
}
func (o *PSCU_Type) GetPSARD_PSARD3() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x8) >> 3
}
func (o *PSCU_Type) SetPSARD_PSARD11(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x800)|value<<11)
}
func (o *PSCU_Type) GetPSARD_PSARD11() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x800) >> 11
}
func (o *PSCU_Type) SetPSARD_PSARD12(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x1000)|value<<12)
}
func (o *PSCU_Type) GetPSARD_PSARD12() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x1000) >> 12
}
func (o *PSCU_Type) SetPSARD_PSARD13(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x2000)|value<<13)
}
func (o *PSCU_Type) GetPSARD_PSARD13() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x2000) >> 13
}
func (o *PSCU_Type) SetPSARD_PSARD14(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x4000)|value<<14)
}
func (o *PSCU_Type) GetPSARD_PSARD14() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x4000) >> 14
}
func (o *PSCU_Type) SetPSARD_PSARD16(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x10000)|value<<16)
}
func (o *PSCU_Type) GetPSARD_PSARD16() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x10000) >> 16
}
func (o *PSCU_Type) SetPSARD_PSARD20(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x100000)|value<<20)
}
func (o *PSCU_Type) GetPSARD_PSARD20() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x100000) >> 20
}
func (o *PSCU_Type) SetPSARD_PSARD22(value uint32) {
	volatile.StoreUint32(&o.PSARD.Reg, volatile.LoadUint32(&o.PSARD.Reg)&^(0x400000)|value<<22)
}
func (o *PSCU_Type) GetPSARD_PSARD22() uint32 {
	return (volatile.LoadUint32(&o.PSARD.Reg) & 0x400000) >> 22
}

// PSCU.PSARE: Peripheral Security Attribution Register E
func (o *PSCU_Type) SetPSARE_PSARE0(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x1)|value)
}
func (o *PSCU_Type) GetPSARE_PSARE0() uint32 {
	return volatile.LoadUint32(&o.PSARE.Reg) & 0x1
}
func (o *PSCU_Type) SetPSARE_PSARE1(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x2)|value<<1)
}
func (o *PSCU_Type) GetPSARE_PSARE1() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x2) >> 1
}
func (o *PSCU_Type) SetPSARE_PSARE2(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x4)|value<<2)
}
func (o *PSCU_Type) GetPSARE_PSARE2() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x4) >> 2
}
func (o *PSCU_Type) SetPSARE_PSARE26(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x4000000)|value<<26)
}
func (o *PSCU_Type) GetPSARE_PSARE26() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x4000000) >> 26
}
func (o *PSCU_Type) SetPSARE_PSARE27(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x8000000)|value<<27)
}
func (o *PSCU_Type) GetPSARE_PSARE27() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x8000000) >> 27
}
func (o *PSCU_Type) SetPSARE_PSARE28(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x10000000)|value<<28)
}
func (o *PSCU_Type) GetPSARE_PSARE28() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x10000000) >> 28
}
func (o *PSCU_Type) SetPSARE_PSARE29(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x20000000)|value<<29)
}
func (o *PSCU_Type) GetPSARE_PSARE29() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x20000000) >> 29
}
func (o *PSCU_Type) SetPSARE_PSARE30(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x40000000)|value<<30)
}
func (o *PSCU_Type) GetPSARE_PSARE30() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x40000000) >> 30
}
func (o *PSCU_Type) SetPSARE_PSARE31(value uint32) {
	volatile.StoreUint32(&o.PSARE.Reg, volatile.LoadUint32(&o.PSARE.Reg)&^(0x80000000)|value<<31)
}
func (o *PSCU_Type) GetPSARE_PSARE31() uint32 {
	return (volatile.LoadUint32(&o.PSARE.Reg) & 0x80000000) >> 31
}

// PSCU.MSSAR: Module Stop Security Attribution Register
func (o *PSCU_Type) SetMSSAR_MSSAR0(value uint32) {
	volatile.StoreUint32(&o.MSSAR.Reg, volatile.LoadUint32(&o.MSSAR.Reg)&^(0x1)|value)
}
func (o *PSCU_Type) GetMSSAR_MSSAR0() uint32 {
	return volatile.LoadUint32(&o.MSSAR.Reg) & 0x1
}
func (o *PSCU_Type) SetMSSAR_MSSAR1(value uint32) {
	volatile.StoreUint32(&o.MSSAR.Reg, volatile.LoadUint32(&o.MSSAR.Reg)&^(0x2)|value<<1)
}
func (o *PSCU_Type) GetMSSAR_MSSAR1() uint32 {
	return (volatile.LoadUint32(&o.MSSAR.Reg) & 0x2) >> 1
}
func (o *PSCU_Type) SetMSSAR_MSSAR2(value uint32) {
	volatile.StoreUint32(&o.MSSAR.Reg, volatile.LoadUint32(&o.MSSAR.Reg)&^(0x4)|value<<2)
}
func (o *PSCU_Type) GetMSSAR_MSSAR2() uint32 {
	return (volatile.LoadUint32(&o.MSSAR.Reg) & 0x4) >> 2
}
func (o *PSCU_Type) SetMSSAR_MSSAR3(value uint32) {
	volatile.StoreUint32(&o.MSSAR.Reg, volatile.LoadUint32(&o.MSSAR.Reg)&^(0x8)|value<<3)
}
func (o *PSCU_Type) GetMSSAR_MSSAR3() uint32 {
	return (volatile.LoadUint32(&o.MSSAR.Reg) & 0x8) >> 3
}

// PSCU.CFSAMONA: Code Flash Security Attribution Register A
func (o *PSCU_Type) SetCFSAMONA_CFS2(value uint32) {
	volatile.StoreUint32(&o.CFSAMONA.Reg, volatile.LoadUint32(&o.CFSAMONA.Reg)&^(0xff8000)|value<<15)
}
func (o *PSCU_Type) GetCFSAMONA_CFS2() uint32 {
	return (volatile.LoadUint32(&o.CFSAMONA.Reg) & 0xff8000) >> 15
}

// PSCU.CFSAMONB: Code Flash Security Attribution Register B
func (o *PSCU_Type) SetCFSAMONB_CFS1(value uint32) {
	volatile.StoreUint32(&o.CFSAMONB.Reg, volatile.LoadUint32(&o.CFSAMONB.Reg)&^(0xfffc00)|value<<10)
}
func (o *PSCU_Type) GetCFSAMONB_CFS1() uint32 {
	return (volatile.LoadUint32(&o.CFSAMONB.Reg) & 0xfffc00) >> 10
}

// PSCU.DFSAMON: Data Flash Security Attribution Register
func (o *PSCU_Type) SetDFSAMON_DFS(value uint32) {
	volatile.StoreUint32(&o.DFSAMON.Reg, volatile.LoadUint32(&o.DFSAMON.Reg)&^(0xfc00)|value<<10)
}
func (o *PSCU_Type) GetDFSAMON_DFS() uint32 {
	return (volatile.LoadUint32(&o.DFSAMON.Reg) & 0xfc00) >> 10
}

// PSCU.SSAMONA: SRAM Security Attribution Register A
func (o *PSCU_Type) SetSSAMONA_SS2(value uint32) {
	volatile.StoreUint32(&o.SSAMONA.Reg, volatile.LoadUint32(&o.SSAMONA.Reg)&^(0x1fe000)|value<<13)
}
func (o *PSCU_Type) GetSSAMONA_SS2() uint32 {
	return (volatile.LoadUint32(&o.SSAMONA.Reg) & 0x1fe000) >> 13
}

// PSCU.SSAMONB: SRAM Security Attribution Register B
func (o *PSCU_Type) SetSSAMONB_SS1(value uint32) {
	volatile.StoreUint32(&o.SSAMONB.Reg, volatile.LoadUint32(&o.SSAMONB.Reg)&^(0x1ffc00)|value<<10)
}
func (o *PSCU_Type) GetSSAMONB_SS1() uint32 {
	return (volatile.LoadUint32(&o.SSAMONB.Reg) & 0x1ffc00) >> 10
}

// Low Power Asynchronous General Purpose Timer 0
type AGTW0_Type struct {
	AGT      volatile.Register32 // 0x0
	AGTCMA   volatile.Register32 // 0x4
	AGTCMB   volatile.Register32 // 0x8
	AGTCR    volatile.Register8  // 0xC
	AGTMR1   volatile.Register8  // 0xD
	AGTMR2   volatile.Register8  // 0xE
	_        byte
	AGTIOC   volatile.Register8 // 0x10
	AGTISR   volatile.Register8 // 0x11
	AGTCMSR  volatile.Register8 // 0x12
	AGTIOSEL volatile.Register8 // 0x13
}

// AGTW0.AGTCR: AGT Control Register
func (o *AGTW0_Type) SetAGTCR_TSTART(value uint8) {
	volatile.StoreUint8(&o.AGTCR.Reg, volatile.LoadUint8(&o.AGTCR.Reg)&^(0x1)|value)
}
func (o *AGTW0_Type) GetAGTCR_TSTART() uint8 {
	return volatile.LoadUint8(&o.AGTCR.Reg) & 0x1
}
func (o *AGTW0_Type) SetAGTCR_TCSTF(value uint8) {
	volatile.StoreUint8(&o.AGTCR.Reg, volatile.LoadUint8(&o.AGTCR.Reg)&^(0x2)|value<<1)
}
func (o *AGTW0_Type) GetAGTCR_TCSTF() uint8 {
	return (volatile.LoadUint8(&o.AGTCR.Reg) & 0x2) >> 1
}
func (o *AGTW0_Type) SetAGTCR_TSTOP(value uint8) {
	volatile.StoreUint8(&o.AGTCR.Reg, volatile.LoadUint8(&o.AGTCR.Reg)&^(0x4)|value<<2)
}
func (o *AGTW0_Type) GetAGTCR_TSTOP() uint8 {
	return (volatile.LoadUint8(&o.AGTCR.Reg) & 0x4) >> 2
}
func (o *AGTW0_Type) SetAGTCR_TEDGF(value uint8) {
	volatile.StoreUint8(&o.AGTCR.Reg, volatile.LoadUint8(&o.AGTCR.Reg)&^(0x10)|value<<4)
}
func (o *AGTW0_Type) GetAGTCR_TEDGF() uint8 {
	return (volatile.LoadUint8(&o.AGTCR.Reg) & 0x10) >> 4
}
func (o *AGTW0_Type) SetAGTCR_TUNDF(value uint8) {
	volatile.StoreUint8(&o.AGTCR.Reg, volatile.LoadUint8(&o.AGTCR.Reg)&^(0x20)|value<<5)
}
func (o *AGTW0_Type) GetAGTCR_TUNDF() uint8 {
	return (volatile.LoadUint8(&o.AGTCR.Reg) & 0x20) >> 5
}
func (o *AGTW0_Type) SetAGTCR_TCMAF(value uint8) {
	volatile.StoreUint8(&o.AGTCR.Reg, volatile.LoadUint8(&o.AGTCR.Reg)&^(0x40)|value<<6)
}
func (o *AGTW0_Type) GetAGTCR_TCMAF() uint8 {
	return (volatile.LoadUint8(&o.AGTCR.Reg) & 0x40) >> 6
}
func (o *AGTW0_Type) SetAGTCR_TCMBF(value uint8) {
	volatile.StoreUint8(&o.AGTCR.Reg, volatile.LoadUint8(&o.AGTCR.Reg)&^(0x80)|value<<7)
}
func (o *AGTW0_Type) GetAGTCR_TCMBF() uint8 {
	return (volatile.LoadUint8(&o.AGTCR.Reg) & 0x80) >> 7
}

// AGTW0.AGTMR1: AGT Mode Register 1
func (o *AGTW0_Type) SetAGTMR1_TMOD(value uint8) {
	volatile.StoreUint8(&o.AGTMR1.Reg, volatile.LoadUint8(&o.AGTMR1.Reg)&^(0x7)|value)
}
func (o *AGTW0_Type) GetAGTMR1_TMOD() uint8 {
	return volatile.LoadUint8(&o.AGTMR1.Reg) & 0x7
}
func (o *AGTW0_Type) SetAGTMR1_TEDGPL(value uint8) {
	volatile.StoreUint8(&o.AGTMR1.Reg, volatile.LoadUint8(&o.AGTMR1.Reg)&^(0x8)|value<<3)
}
func (o *AGTW0_Type) GetAGTMR1_TEDGPL() uint8 {
	return (volatile.LoadUint8(&o.AGTMR1.Reg) & 0x8) >> 3
}
func (o *AGTW0_Type) SetAGTMR1_TCK(value uint8) {
	volatile.StoreUint8(&o.AGTMR1.Reg, volatile.LoadUint8(&o.AGTMR1.Reg)&^(0x70)|value<<4)
}
func (o *AGTW0_Type) GetAGTMR1_TCK() uint8 {
	return (volatile.LoadUint8(&o.AGTMR1.Reg) & 0x70) >> 4
}

// AGTW0.AGTMR2: AGT Mode Register 2
func (o *AGTW0_Type) SetAGTMR2_CKS(value uint8) {
	volatile.StoreUint8(&o.AGTMR2.Reg, volatile.LoadUint8(&o.AGTMR2.Reg)&^(0x7)|value)
}
func (o *AGTW0_Type) GetAGTMR2_CKS() uint8 {
	return volatile.LoadUint8(&o.AGTMR2.Reg) & 0x7
}
func (o *AGTW0_Type) SetAGTMR2_LPM(value uint8) {
	volatile.StoreUint8(&o.AGTMR2.Reg, volatile.LoadUint8(&o.AGTMR2.Reg)&^(0x80)|value<<7)
}
func (o *AGTW0_Type) GetAGTMR2_LPM() uint8 {
	return (volatile.LoadUint8(&o.AGTMR2.Reg) & 0x80) >> 7
}

// AGTW0.AGTIOC: AGT I/O Control Register
func (o *AGTW0_Type) SetAGTIOC_TEDGSEL(value uint8) {
	volatile.StoreUint8(&o.AGTIOC.Reg, volatile.LoadUint8(&o.AGTIOC.Reg)&^(0x1)|value)
}
func (o *AGTW0_Type) GetAGTIOC_TEDGSEL() uint8 {
	return volatile.LoadUint8(&o.AGTIOC.Reg) & 0x1
}
func (o *AGTW0_Type) SetAGTIOC_TOE(value uint8) {
	volatile.StoreUint8(&o.AGTIOC.Reg, volatile.LoadUint8(&o.AGTIOC.Reg)&^(0x4)|value<<2)
}
func (o *AGTW0_Type) GetAGTIOC_TOE() uint8 {
	return (volatile.LoadUint8(&o.AGTIOC.Reg) & 0x4) >> 2
}
func (o *AGTW0_Type) SetAGTIOC_TIPF(value uint8) {
	volatile.StoreUint8(&o.AGTIOC.Reg, volatile.LoadUint8(&o.AGTIOC.Reg)&^(0x30)|value<<4)
}
func (o *AGTW0_Type) GetAGTIOC_TIPF() uint8 {
	return (volatile.LoadUint8(&o.AGTIOC.Reg) & 0x30) >> 4
}
func (o *AGTW0_Type) SetAGTIOC_TIOGT(value uint8) {
	volatile.StoreUint8(&o.AGTIOC.Reg, volatile.LoadUint8(&o.AGTIOC.Reg)&^(0xc0)|value<<6)
}
func (o *AGTW0_Type) GetAGTIOC_TIOGT() uint8 {
	return (volatile.LoadUint8(&o.AGTIOC.Reg) & 0xc0) >> 6
}

// AGTW0.AGTISR: AGT Event Pin Select Register
func (o *AGTW0_Type) SetAGTISR_EEPS(value uint8) {
	volatile.StoreUint8(&o.AGTISR.Reg, volatile.LoadUint8(&o.AGTISR.Reg)&^(0x4)|value<<2)
}
func (o *AGTW0_Type) GetAGTISR_EEPS() uint8 {
	return (volatile.LoadUint8(&o.AGTISR.Reg) & 0x4) >> 2
}

// AGTW0.AGTCMSR: AGT Compare Match Function Select Register
func (o *AGTW0_Type) SetAGTCMSR_TCMEA(value uint8) {
	volatile.StoreUint8(&o.AGTCMSR.Reg, volatile.LoadUint8(&o.AGTCMSR.Reg)&^(0x1)|value)
}
func (o *AGTW0_Type) GetAGTCMSR_TCMEA() uint8 {
	return volatile.LoadUint8(&o.AGTCMSR.Reg) & 0x1
}
func (o *AGTW0_Type) SetAGTCMSR_TOEA(value uint8) {
	volatile.StoreUint8(&o.AGTCMSR.Reg, volatile.LoadUint8(&o.AGTCMSR.Reg)&^(0x2)|value<<1)
}
func (o *AGTW0_Type) GetAGTCMSR_TOEA() uint8 {
	return (volatile.LoadUint8(&o.AGTCMSR.Reg) & 0x2) >> 1
}
func (o *AGTW0_Type) SetAGTCMSR_TOPOLA(value uint8) {
	volatile.StoreUint8(&o.AGTCMSR.Reg, volatile.LoadUint8(&o.AGTCMSR.Reg)&^(0x4)|value<<2)
}
func (o *AGTW0_Type) GetAGTCMSR_TOPOLA() uint8 {
	return (volatile.LoadUint8(&o.AGTCMSR.Reg) & 0x4) >> 2
}
func (o *AGTW0_Type) SetAGTCMSR_TCMEB(value uint8) {
	volatile.StoreUint8(&o.AGTCMSR.Reg, volatile.LoadUint8(&o.AGTCMSR.Reg)&^(0x10)|value<<4)
}
func (o *AGTW0_Type) GetAGTCMSR_TCMEB() uint8 {
	return (volatile.LoadUint8(&o.AGTCMSR.Reg) & 0x10) >> 4
}
func (o *AGTW0_Type) SetAGTCMSR_TOEB(value uint8) {
	volatile.StoreUint8(&o.AGTCMSR.Reg, volatile.LoadUint8(&o.AGTCMSR.Reg)&^(0x20)|value<<5)
}
func (o *AGTW0_Type) GetAGTCMSR_TOEB() uint8 {
	return (volatile.LoadUint8(&o.AGTCMSR.Reg) & 0x20) >> 5
}
func (o *AGTW0_Type) SetAGTCMSR_TOPOLB(value uint8) {
	volatile.StoreUint8(&o.AGTCMSR.Reg, volatile.LoadUint8(&o.AGTCMSR.Reg)&^(0x40)|value<<6)
}
func (o *AGTW0_Type) GetAGTCMSR_TOPOLB() uint8 {
	return (volatile.LoadUint8(&o.AGTCMSR.Reg) & 0x40) >> 6
}

// AGTW0.AGTIOSEL: AGT Pin Select Register
func (o *AGTW0_Type) SetAGTIOSEL_SEL(value uint8) {
	volatile.StoreUint8(&o.AGTIOSEL.Reg, volatile.LoadUint8(&o.AGTIOSEL.Reg)&^(0x3)|value)
}
func (o *AGTW0_Type) GetAGTIOSEL_SEL() uint8 {
	return volatile.LoadUint8(&o.AGTIOSEL.Reg) & 0x3
}
func (o *AGTW0_Type) SetAGTIOSEL_TIES(value uint8) {
	volatile.StoreUint8(&o.AGTIOSEL.Reg, volatile.LoadUint8(&o.AGTIOSEL.Reg)&^(0x10)|value<<4)
}
func (o *AGTW0_Type) GetAGTIOSEL_TIES() uint8 {
	return (volatile.LoadUint8(&o.AGTIOSEL.Reg) & 0x10) >> 4
}

// Temperature Sensor
type TSN_Type struct {
	TSCR volatile.Register8 // 0x0
}

// TSN.TSCR: Temperature Sensor Control Register
func (o *TSN_Type) SetTSCR_TSOE(value uint8) {
	volatile.StoreUint8(&o.TSCR.Reg, volatile.LoadUint8(&o.TSCR.Reg)&^(0x10)|value<<4)
}
func (o *TSN_Type) GetTSCR_TSOE() uint8 {
	return (volatile.LoadUint8(&o.TSCR.Reg) & 0x10) >> 4
}
func (o *TSN_Type) SetTSCR_TSEN(value uint8) {
	volatile.StoreUint8(&o.TSCR.Reg, volatile.LoadUint8(&o.TSCR.Reg)&^(0x80)|value<<7)
}
func (o *TSN_Type) GetTSCR_TSEN() uint8 {
	return (volatile.LoadUint8(&o.TSCR.Reg) & 0x80) >> 7
}

// Cyclic Redundancy Check Calculator
type CRC_Type struct {
	CRCCR0 volatile.Register8 // 0x0
	_      [3]byte
	CRCDIR volatile.Register32 // 0x4
	CRCDOR volatile.Register32 // 0x8
}

// CRC.CRCCR0: CRC Control Register 0
func (o *CRC_Type) SetCRCCR0_GPS(value uint8) {
	volatile.StoreUint8(&o.CRCCR0.Reg, volatile.LoadUint8(&o.CRCCR0.Reg)&^(0x7)|value)
}
func (o *CRC_Type) GetCRCCR0_GPS() uint8 {
	return volatile.LoadUint8(&o.CRCCR0.Reg) & 0x7
}
func (o *CRC_Type) SetCRCCR0_LMS(value uint8) {
	volatile.StoreUint8(&o.CRCCR0.Reg, volatile.LoadUint8(&o.CRCCR0.Reg)&^(0x40)|value<<6)
}
func (o *CRC_Type) GetCRCCR0_LMS() uint8 {
	return (volatile.LoadUint8(&o.CRCCR0.Reg) & 0x40) >> 6
}
func (o *CRC_Type) SetCRCCR0_DORCLR(value uint8) {
	volatile.StoreUint8(&o.CRCCR0.Reg, volatile.LoadUint8(&o.CRCCR0.Reg)&^(0x80)|value<<7)
}
func (o *CRC_Type) GetCRCCR0_DORCLR() uint8 {
	return (volatile.LoadUint8(&o.CRCCR0.Reg) & 0x80) >> 7
}

// Data Operation Circuit
type DOC_Type struct {
	DOCR  volatile.Register8 // 0x0
	_     byte
	DODIR volatile.Register16 // 0x2
	DODSR volatile.Register16 // 0x4
}

// DOC.DOCR: DOC Control Register
func (o *DOC_Type) SetDOCR_OMS(value uint8) {
	volatile.StoreUint8(&o.DOCR.Reg, volatile.LoadUint8(&o.DOCR.Reg)&^(0x3)|value)
}
func (o *DOC_Type) GetDOCR_OMS() uint8 {
	return volatile.LoadUint8(&o.DOCR.Reg) & 0x3
}
func (o *DOC_Type) SetDOCR_DCSEL(value uint8) {
	volatile.StoreUint8(&o.DOCR.Reg, volatile.LoadUint8(&o.DOCR.Reg)&^(0x4)|value<<2)
}
func (o *DOC_Type) GetDOCR_DCSEL() uint8 {
	return (volatile.LoadUint8(&o.DOCR.Reg) & 0x4) >> 2
}
func (o *DOC_Type) SetDOCR_DOPCF(value uint8) {
	volatile.StoreUint8(&o.DOCR.Reg, volatile.LoadUint8(&o.DOCR.Reg)&^(0x20)|value<<5)
}
func (o *DOC_Type) GetDOCR_DOPCF() uint8 {
	return (volatile.LoadUint8(&o.DOCR.Reg) & 0x20) >> 5
}
func (o *DOC_Type) SetDOCR_DOPCFCL(value uint8) {
	volatile.StoreUint8(&o.DOCR.Reg, volatile.LoadUint8(&o.DOCR.Reg)&^(0x40)|value<<6)
}
func (o *DOC_Type) GetDOCR_DOPCFCL() uint8 {
	return (volatile.LoadUint8(&o.DOCR.Reg) & 0x40) >> 6
}

// Serial Communication Interface
type SCI0_Type struct {
	SMR    volatile.Register8  // 0x0
	BRR    volatile.Register8  // 0x1
	SCR    volatile.Register8  // 0x2
	TDR    volatile.Register8  // 0x3
	SSR    volatile.Register8  // 0x4
	RDR    volatile.Register8  // 0x5
	SCMR   volatile.Register8  // 0x6
	SEMR   volatile.Register8  // 0x7
	SNFR   volatile.Register8  // 0x8
	SIMR1  volatile.Register8  // 0x9
	SIMR2  volatile.Register8  // 0xA
	SIMR3  volatile.Register8  // 0xB
	SISR   volatile.Register8  // 0xC
	SPMR   volatile.Register8  // 0xD
	FTDRHL volatile.Register16 // 0xE
	FRDRHL volatile.Register16 // 0x10
	MDDR   volatile.Register8  // 0x12
	DCCR   volatile.Register8  // 0x13
	FCR    volatile.Register16 // 0x14
	FDR    volatile.Register16 // 0x16
	LSR    volatile.Register16 // 0x18
	CDR    volatile.Register16 // 0x1A
	SPTR   volatile.Register8  // 0x1C
	ACTR   volatile.Register8  // 0x1D
	_      [2]byte
	MMR    volatile.Register8 // 0x20
	_      byte
	TMPR   volatile.Register8 // 0x22
	RMPR   volatile.Register8 // 0x23
	MESR   volatile.Register8 // 0x24
	MECR   volatile.Register8 // 0x25
}

// SCI0.SMR: Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
func (o *SCI0_Type) SetSMR_CKS(value uint8) {
	volatile.StoreUint8(&o.SMR.Reg, volatile.LoadUint8(&o.SMR.Reg)&^(0x3)|value)
}
func (o *SCI0_Type) GetSMR_CKS() uint8 {
	return volatile.LoadUint8(&o.SMR.Reg) & 0x3
}
func (o *SCI0_Type) SetSMR_MP(value uint8) {
	volatile.StoreUint8(&o.SMR.Reg, volatile.LoadUint8(&o.SMR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSMR_MP() uint8 {
	return (volatile.LoadUint8(&o.SMR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSMR_STOP(value uint8) {
	volatile.StoreUint8(&o.SMR.Reg, volatile.LoadUint8(&o.SMR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetSMR_STOP() uint8 {
	return (volatile.LoadUint8(&o.SMR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetSMR_PM(value uint8) {
	volatile.StoreUint8(&o.SMR.Reg, volatile.LoadUint8(&o.SMR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetSMR_PM() uint8 {
	return (volatile.LoadUint8(&o.SMR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetSMR_PE(value uint8) {
	volatile.StoreUint8(&o.SMR.Reg, volatile.LoadUint8(&o.SMR.Reg)&^(0x20)|value<<5)
}
func (o *SCI0_Type) GetSMR_PE() uint8 {
	return (volatile.LoadUint8(&o.SMR.Reg) & 0x20) >> 5
}
func (o *SCI0_Type) SetSMR_CHR(value uint8) {
	volatile.StoreUint8(&o.SMR.Reg, volatile.LoadUint8(&o.SMR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetSMR_CHR() uint8 {
	return (volatile.LoadUint8(&o.SMR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetSMR_CM(value uint8) {
	volatile.StoreUint8(&o.SMR.Reg, volatile.LoadUint8(&o.SMR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetSMR_CM() uint8 {
	return (volatile.LoadUint8(&o.SMR.Reg) & 0x80) >> 7
}

// SCI0.SCR: Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
func (o *SCI0_Type) SetSCR_CKE(value uint8) {
	volatile.StoreUint8(&o.SCR.Reg, volatile.LoadUint8(&o.SCR.Reg)&^(0x3)|value)
}
func (o *SCI0_Type) GetSCR_CKE() uint8 {
	return volatile.LoadUint8(&o.SCR.Reg) & 0x3
}
func (o *SCI0_Type) SetSCR_TEIE(value uint8) {
	volatile.StoreUint8(&o.SCR.Reg, volatile.LoadUint8(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSCR_TEIE() uint8 {
	return (volatile.LoadUint8(&o.SCR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSCR_MPIE(value uint8) {
	volatile.StoreUint8(&o.SCR.Reg, volatile.LoadUint8(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetSCR_MPIE() uint8 {
	return (volatile.LoadUint8(&o.SCR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetSCR_RE(value uint8) {
	volatile.StoreUint8(&o.SCR.Reg, volatile.LoadUint8(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetSCR_RE() uint8 {
	return (volatile.LoadUint8(&o.SCR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetSCR_TE(value uint8) {
	volatile.StoreUint8(&o.SCR.Reg, volatile.LoadUint8(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *SCI0_Type) GetSCR_TE() uint8 {
	return (volatile.LoadUint8(&o.SCR.Reg) & 0x20) >> 5
}
func (o *SCI0_Type) SetSCR_RIE(value uint8) {
	volatile.StoreUint8(&o.SCR.Reg, volatile.LoadUint8(&o.SCR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetSCR_RIE() uint8 {
	return (volatile.LoadUint8(&o.SCR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetSCR_TIE(value uint8) {
	volatile.StoreUint8(&o.SCR.Reg, volatile.LoadUint8(&o.SCR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetSCR_TIE() uint8 {
	return (volatile.LoadUint8(&o.SCR.Reg) & 0x80) >> 7
}

// SCI0.SSR: Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0)
func (o *SCI0_Type) SetSSR_MPBT(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSSR_MPBT() uint8 {
	return volatile.LoadUint8(&o.SSR.Reg) & 0x1
}
func (o *SCI0_Type) SetSSR_MPB(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetSSR_MPB() uint8 {
	return (volatile.LoadUint8(&o.SSR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetSSR_TEND(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSSR_TEND() uint8 {
	return (volatile.LoadUint8(&o.SSR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSSR_PER(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetSSR_PER() uint8 {
	return (volatile.LoadUint8(&o.SSR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetSSR_FER(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetSSR_FER() uint8 {
	return (volatile.LoadUint8(&o.SSR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetSSR_ORER(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x20)|value<<5)
}
func (o *SCI0_Type) GetSSR_ORER() uint8 {
	return (volatile.LoadUint8(&o.SSR.Reg) & 0x20) >> 5
}
func (o *SCI0_Type) SetSSR_RDRF(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetSSR_RDRF() uint8 {
	return (volatile.LoadUint8(&o.SSR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetSSR_TDRE(value uint8) {
	volatile.StoreUint8(&o.SSR.Reg, volatile.LoadUint8(&o.SSR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetSSR_TDRE() uint8 {
	return (volatile.LoadUint8(&o.SSR.Reg) & 0x80) >> 7
}

// SCI0.SCMR: Smart Card Mode Register
func (o *SCI0_Type) SetSCMR_SMIF(value uint8) {
	volatile.StoreUint8(&o.SCMR.Reg, volatile.LoadUint8(&o.SCMR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSCMR_SMIF() uint8 {
	return volatile.LoadUint8(&o.SCMR.Reg) & 0x1
}
func (o *SCI0_Type) SetSCMR_SINV(value uint8) {
	volatile.StoreUint8(&o.SCMR.Reg, volatile.LoadUint8(&o.SCMR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSCMR_SINV() uint8 {
	return (volatile.LoadUint8(&o.SCMR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSCMR_SDIR(value uint8) {
	volatile.StoreUint8(&o.SCMR.Reg, volatile.LoadUint8(&o.SCMR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetSCMR_SDIR() uint8 {
	return (volatile.LoadUint8(&o.SCMR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetSCMR_CHR1(value uint8) {
	volatile.StoreUint8(&o.SCMR.Reg, volatile.LoadUint8(&o.SCMR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetSCMR_CHR1() uint8 {
	return (volatile.LoadUint8(&o.SCMR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetSCMR_BCP2(value uint8) {
	volatile.StoreUint8(&o.SCMR.Reg, volatile.LoadUint8(&o.SCMR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetSCMR_BCP2() uint8 {
	return (volatile.LoadUint8(&o.SCMR.Reg) & 0x80) >> 7
}

// SCI0.SEMR: Serial Extended Mode Register
func (o *SCI0_Type) SetSEMR_PADIS(value uint8) {
	volatile.StoreUint8(&o.SEMR.Reg, volatile.LoadUint8(&o.SEMR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetSEMR_PADIS() uint8 {
	return (volatile.LoadUint8(&o.SEMR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetSEMR_BRME(value uint8) {
	volatile.StoreUint8(&o.SEMR.Reg, volatile.LoadUint8(&o.SEMR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSEMR_BRME() uint8 {
	return (volatile.LoadUint8(&o.SEMR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSEMR_ABCSE(value uint8) {
	volatile.StoreUint8(&o.SEMR.Reg, volatile.LoadUint8(&o.SEMR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetSEMR_ABCSE() uint8 {
	return (volatile.LoadUint8(&o.SEMR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetSEMR_ABCS(value uint8) {
	volatile.StoreUint8(&o.SEMR.Reg, volatile.LoadUint8(&o.SEMR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetSEMR_ABCS() uint8 {
	return (volatile.LoadUint8(&o.SEMR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetSEMR_NFEN(value uint8) {
	volatile.StoreUint8(&o.SEMR.Reg, volatile.LoadUint8(&o.SEMR.Reg)&^(0x20)|value<<5)
}
func (o *SCI0_Type) GetSEMR_NFEN() uint8 {
	return (volatile.LoadUint8(&o.SEMR.Reg) & 0x20) >> 5
}
func (o *SCI0_Type) SetSEMR_BGDM(value uint8) {
	volatile.StoreUint8(&o.SEMR.Reg, volatile.LoadUint8(&o.SEMR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetSEMR_BGDM() uint8 {
	return (volatile.LoadUint8(&o.SEMR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetSEMR_RXDESEL(value uint8) {
	volatile.StoreUint8(&o.SEMR.Reg, volatile.LoadUint8(&o.SEMR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetSEMR_RXDESEL() uint8 {
	return (volatile.LoadUint8(&o.SEMR.Reg) & 0x80) >> 7
}

// SCI0.SNFR: Noise Filter Setting Register
func (o *SCI0_Type) SetSNFR_NFCS(value uint8) {
	volatile.StoreUint8(&o.SNFR.Reg, volatile.LoadUint8(&o.SNFR.Reg)&^(0x7)|value)
}
func (o *SCI0_Type) GetSNFR_NFCS() uint8 {
	return volatile.LoadUint8(&o.SNFR.Reg) & 0x7
}

// SCI0.SIMR1: IIC Mode Register 1
func (o *SCI0_Type) SetSIMR1_IICM(value uint8) {
	volatile.StoreUint8(&o.SIMR1.Reg, volatile.LoadUint8(&o.SIMR1.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSIMR1_IICM() uint8 {
	return volatile.LoadUint8(&o.SIMR1.Reg) & 0x1
}
func (o *SCI0_Type) SetSIMR1_IICDL(value uint8) {
	volatile.StoreUint8(&o.SIMR1.Reg, volatile.LoadUint8(&o.SIMR1.Reg)&^(0xf8)|value<<3)
}
func (o *SCI0_Type) GetSIMR1_IICDL() uint8 {
	return (volatile.LoadUint8(&o.SIMR1.Reg) & 0xf8) >> 3
}

// SCI0.SIMR2: IIC Mode Register 2
func (o *SCI0_Type) SetSIMR2_IICINTM(value uint8) {
	volatile.StoreUint8(&o.SIMR2.Reg, volatile.LoadUint8(&o.SIMR2.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSIMR2_IICINTM() uint8 {
	return volatile.LoadUint8(&o.SIMR2.Reg) & 0x1
}
func (o *SCI0_Type) SetSIMR2_IICCSC(value uint8) {
	volatile.StoreUint8(&o.SIMR2.Reg, volatile.LoadUint8(&o.SIMR2.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetSIMR2_IICCSC() uint8 {
	return (volatile.LoadUint8(&o.SIMR2.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetSIMR2_IICACKT(value uint8) {
	volatile.StoreUint8(&o.SIMR2.Reg, volatile.LoadUint8(&o.SIMR2.Reg)&^(0x20)|value<<5)
}
func (o *SCI0_Type) GetSIMR2_IICACKT() uint8 {
	return (volatile.LoadUint8(&o.SIMR2.Reg) & 0x20) >> 5
}

// SCI0.SIMR3: IIC Mode Register 3
func (o *SCI0_Type) SetSIMR3_IICSTAREQ(value uint8) {
	volatile.StoreUint8(&o.SIMR3.Reg, volatile.LoadUint8(&o.SIMR3.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSIMR3_IICSTAREQ() uint8 {
	return volatile.LoadUint8(&o.SIMR3.Reg) & 0x1
}
func (o *SCI0_Type) SetSIMR3_IICRSTAREQ(value uint8) {
	volatile.StoreUint8(&o.SIMR3.Reg, volatile.LoadUint8(&o.SIMR3.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetSIMR3_IICRSTAREQ() uint8 {
	return (volatile.LoadUint8(&o.SIMR3.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetSIMR3_IICSTPREQ(value uint8) {
	volatile.StoreUint8(&o.SIMR3.Reg, volatile.LoadUint8(&o.SIMR3.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSIMR3_IICSTPREQ() uint8 {
	return (volatile.LoadUint8(&o.SIMR3.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSIMR3_IICSTIF(value uint8) {
	volatile.StoreUint8(&o.SIMR3.Reg, volatile.LoadUint8(&o.SIMR3.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetSIMR3_IICSTIF() uint8 {
	return (volatile.LoadUint8(&o.SIMR3.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetSIMR3_IICSDAS(value uint8) {
	volatile.StoreUint8(&o.SIMR3.Reg, volatile.LoadUint8(&o.SIMR3.Reg)&^(0x30)|value<<4)
}
func (o *SCI0_Type) GetSIMR3_IICSDAS() uint8 {
	return (volatile.LoadUint8(&o.SIMR3.Reg) & 0x30) >> 4
}
func (o *SCI0_Type) SetSIMR3_IICSCLS(value uint8) {
	volatile.StoreUint8(&o.SIMR3.Reg, volatile.LoadUint8(&o.SIMR3.Reg)&^(0xc0)|value<<6)
}
func (o *SCI0_Type) GetSIMR3_IICSCLS() uint8 {
	return (volatile.LoadUint8(&o.SIMR3.Reg) & 0xc0) >> 6
}

// SCI0.SISR: IIC Status Register
func (o *SCI0_Type) SetSISR_IICACKR(value uint8) {
	volatile.StoreUint8(&o.SISR.Reg, volatile.LoadUint8(&o.SISR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSISR_IICACKR() uint8 {
	return volatile.LoadUint8(&o.SISR.Reg) & 0x1
}

// SCI0.SPMR: SPI Mode Register
func (o *SCI0_Type) SetSPMR_SSE(value uint8) {
	volatile.StoreUint8(&o.SPMR.Reg, volatile.LoadUint8(&o.SPMR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSPMR_SSE() uint8 {
	return volatile.LoadUint8(&o.SPMR.Reg) & 0x1
}
func (o *SCI0_Type) SetSPMR_CTSE(value uint8) {
	volatile.StoreUint8(&o.SPMR.Reg, volatile.LoadUint8(&o.SPMR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetSPMR_CTSE() uint8 {
	return (volatile.LoadUint8(&o.SPMR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetSPMR_MSS(value uint8) {
	volatile.StoreUint8(&o.SPMR.Reg, volatile.LoadUint8(&o.SPMR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSPMR_MSS() uint8 {
	return (volatile.LoadUint8(&o.SPMR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSPMR_CTSPEN(value uint8) {
	volatile.StoreUint8(&o.SPMR.Reg, volatile.LoadUint8(&o.SPMR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetSPMR_CTSPEN() uint8 {
	return (volatile.LoadUint8(&o.SPMR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetSPMR_MFF(value uint8) {
	volatile.StoreUint8(&o.SPMR.Reg, volatile.LoadUint8(&o.SPMR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetSPMR_MFF() uint8 {
	return (volatile.LoadUint8(&o.SPMR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetSPMR_CKPOL(value uint8) {
	volatile.StoreUint8(&o.SPMR.Reg, volatile.LoadUint8(&o.SPMR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetSPMR_CKPOL() uint8 {
	return (volatile.LoadUint8(&o.SPMR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetSPMR_CKPH(value uint8) {
	volatile.StoreUint8(&o.SPMR.Reg, volatile.LoadUint8(&o.SPMR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetSPMR_CKPH() uint8 {
	return (volatile.LoadUint8(&o.SPMR.Reg) & 0x80) >> 7
}

// SCI0.FTDRHL: Transmit FIFO Data Register
func (o *SCI0_Type) SetFTDRHL_TDAT(value uint16) {
	volatile.StoreUint16(&o.FTDRHL.Reg, volatile.LoadUint16(&o.FTDRHL.Reg)&^(0x1ff)|value)
}
func (o *SCI0_Type) GetFTDRHL_TDAT() uint16 {
	return volatile.LoadUint16(&o.FTDRHL.Reg) & 0x1ff
}
func (o *SCI0_Type) SetFTDRHL_MPBT(value uint16) {
	volatile.StoreUint16(&o.FTDRHL.Reg, volatile.LoadUint16(&o.FTDRHL.Reg)&^(0x200)|value<<9)
}
func (o *SCI0_Type) GetFTDRHL_MPBT() uint16 {
	return (volatile.LoadUint16(&o.FTDRHL.Reg) & 0x200) >> 9
}

// SCI0.FRDRHL: Receive FIFO Data Register
func (o *SCI0_Type) SetFRDRHL_RDAT(value uint16) {
	volatile.StoreUint16(&o.FRDRHL.Reg, volatile.LoadUint16(&o.FRDRHL.Reg)&^(0x1ff)|value)
}
func (o *SCI0_Type) GetFRDRHL_RDAT() uint16 {
	return volatile.LoadUint16(&o.FRDRHL.Reg) & 0x1ff
}
func (o *SCI0_Type) SetFRDRHL_MPB(value uint16) {
	volatile.StoreUint16(&o.FRDRHL.Reg, volatile.LoadUint16(&o.FRDRHL.Reg)&^(0x200)|value<<9)
}
func (o *SCI0_Type) GetFRDRHL_MPB() uint16 {
	return (volatile.LoadUint16(&o.FRDRHL.Reg) & 0x200) >> 9
}
func (o *SCI0_Type) SetFRDRHL_DR(value uint16) {
	volatile.StoreUint16(&o.FRDRHL.Reg, volatile.LoadUint16(&o.FRDRHL.Reg)&^(0x400)|value<<10)
}
func (o *SCI0_Type) GetFRDRHL_DR() uint16 {
	return (volatile.LoadUint16(&o.FRDRHL.Reg) & 0x400) >> 10
}
func (o *SCI0_Type) SetFRDRHL_PER(value uint16) {
	volatile.StoreUint16(&o.FRDRHL.Reg, volatile.LoadUint16(&o.FRDRHL.Reg)&^(0x800)|value<<11)
}
func (o *SCI0_Type) GetFRDRHL_PER() uint16 {
	return (volatile.LoadUint16(&o.FRDRHL.Reg) & 0x800) >> 11
}
func (o *SCI0_Type) SetFRDRHL_FER(value uint16) {
	volatile.StoreUint16(&o.FRDRHL.Reg, volatile.LoadUint16(&o.FRDRHL.Reg)&^(0x1000)|value<<12)
}
func (o *SCI0_Type) GetFRDRHL_FER() uint16 {
	return (volatile.LoadUint16(&o.FRDRHL.Reg) & 0x1000) >> 12
}
func (o *SCI0_Type) SetFRDRHL_ORER(value uint16) {
	volatile.StoreUint16(&o.FRDRHL.Reg, volatile.LoadUint16(&o.FRDRHL.Reg)&^(0x2000)|value<<13)
}
func (o *SCI0_Type) GetFRDRHL_ORER() uint16 {
	return (volatile.LoadUint16(&o.FRDRHL.Reg) & 0x2000) >> 13
}
func (o *SCI0_Type) SetFRDRHL_RDF(value uint16) {
	volatile.StoreUint16(&o.FRDRHL.Reg, volatile.LoadUint16(&o.FRDRHL.Reg)&^(0x4000)|value<<14)
}
func (o *SCI0_Type) GetFRDRHL_RDF() uint16 {
	return (volatile.LoadUint16(&o.FRDRHL.Reg) & 0x4000) >> 14
}

// SCI0.DCCR: Data Compare Match Control Register
func (o *SCI0_Type) SetDCCR_DCMF(value uint8) {
	volatile.StoreUint8(&o.DCCR.Reg, volatile.LoadUint8(&o.DCCR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetDCCR_DCMF() uint8 {
	return volatile.LoadUint8(&o.DCCR.Reg) & 0x1
}
func (o *SCI0_Type) SetDCCR_DPER(value uint8) {
	volatile.StoreUint8(&o.DCCR.Reg, volatile.LoadUint8(&o.DCCR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetDCCR_DPER() uint8 {
	return (volatile.LoadUint8(&o.DCCR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetDCCR_DFER(value uint8) {
	volatile.StoreUint8(&o.DCCR.Reg, volatile.LoadUint8(&o.DCCR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetDCCR_DFER() uint8 {
	return (volatile.LoadUint8(&o.DCCR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetDCCR_IDSEL(value uint8) {
	volatile.StoreUint8(&o.DCCR.Reg, volatile.LoadUint8(&o.DCCR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetDCCR_IDSEL() uint8 {
	return (volatile.LoadUint8(&o.DCCR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetDCCR_DCME(value uint8) {
	volatile.StoreUint8(&o.DCCR.Reg, volatile.LoadUint8(&o.DCCR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetDCCR_DCME() uint8 {
	return (volatile.LoadUint8(&o.DCCR.Reg) & 0x80) >> 7
}

// SCI0.FCR: FIFO Control Register
func (o *SCI0_Type) SetFCR_FM(value uint16) {
	volatile.StoreUint16(&o.FCR.Reg, volatile.LoadUint16(&o.FCR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetFCR_FM() uint16 {
	return volatile.LoadUint16(&o.FCR.Reg) & 0x1
}
func (o *SCI0_Type) SetFCR_RFRST(value uint16) {
	volatile.StoreUint16(&o.FCR.Reg, volatile.LoadUint16(&o.FCR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetFCR_RFRST() uint16 {
	return (volatile.LoadUint16(&o.FCR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetFCR_TFRST(value uint16) {
	volatile.StoreUint16(&o.FCR.Reg, volatile.LoadUint16(&o.FCR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetFCR_TFRST() uint16 {
	return (volatile.LoadUint16(&o.FCR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetFCR_DRES(value uint16) {
	volatile.StoreUint16(&o.FCR.Reg, volatile.LoadUint16(&o.FCR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetFCR_DRES() uint16 {
	return (volatile.LoadUint16(&o.FCR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetFCR_TTRG(value uint16) {
	volatile.StoreUint16(&o.FCR.Reg, volatile.LoadUint16(&o.FCR.Reg)&^(0xf0)|value<<4)
}
func (o *SCI0_Type) GetFCR_TTRG() uint16 {
	return (volatile.LoadUint16(&o.FCR.Reg) & 0xf0) >> 4
}
func (o *SCI0_Type) SetFCR_RTRG(value uint16) {
	volatile.StoreUint16(&o.FCR.Reg, volatile.LoadUint16(&o.FCR.Reg)&^(0xf00)|value<<8)
}
func (o *SCI0_Type) GetFCR_RTRG() uint16 {
	return (volatile.LoadUint16(&o.FCR.Reg) & 0xf00) >> 8
}
func (o *SCI0_Type) SetFCR_RSTRG(value uint16) {
	volatile.StoreUint16(&o.FCR.Reg, volatile.LoadUint16(&o.FCR.Reg)&^(0xf000)|value<<12)
}
func (o *SCI0_Type) GetFCR_RSTRG() uint16 {
	return (volatile.LoadUint16(&o.FCR.Reg) & 0xf000) >> 12
}

// SCI0.FDR: FIFO Data Count Register
func (o *SCI0_Type) SetFDR_R(value uint16) {
	volatile.StoreUint16(&o.FDR.Reg, volatile.LoadUint16(&o.FDR.Reg)&^(0x1f)|value)
}
func (o *SCI0_Type) GetFDR_R() uint16 {
	return volatile.LoadUint16(&o.FDR.Reg) & 0x1f
}
func (o *SCI0_Type) SetFDR_T(value uint16) {
	volatile.StoreUint16(&o.FDR.Reg, volatile.LoadUint16(&o.FDR.Reg)&^(0x1f00)|value<<8)
}
func (o *SCI0_Type) GetFDR_T() uint16 {
	return (volatile.LoadUint16(&o.FDR.Reg) & 0x1f00) >> 8
}

// SCI0.LSR: Line Status Register
func (o *SCI0_Type) SetLSR_ORER(value uint16) {
	volatile.StoreUint16(&o.LSR.Reg, volatile.LoadUint16(&o.LSR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetLSR_ORER() uint16 {
	return volatile.LoadUint16(&o.LSR.Reg) & 0x1
}
func (o *SCI0_Type) SetLSR_FNUM(value uint16) {
	volatile.StoreUint16(&o.LSR.Reg, volatile.LoadUint16(&o.LSR.Reg)&^(0x7c)|value<<2)
}
func (o *SCI0_Type) GetLSR_FNUM() uint16 {
	return (volatile.LoadUint16(&o.LSR.Reg) & 0x7c) >> 2
}
func (o *SCI0_Type) SetLSR_PNUM(value uint16) {
	volatile.StoreUint16(&o.LSR.Reg, volatile.LoadUint16(&o.LSR.Reg)&^(0x1f00)|value<<8)
}
func (o *SCI0_Type) GetLSR_PNUM() uint16 {
	return (volatile.LoadUint16(&o.LSR.Reg) & 0x1f00) >> 8
}

// SCI0.CDR: Compare Match Data Register
func (o *SCI0_Type) SetCDR_CMPD(value uint16) {
	volatile.StoreUint16(&o.CDR.Reg, volatile.LoadUint16(&o.CDR.Reg)&^(0x1ff)|value)
}
func (o *SCI0_Type) GetCDR_CMPD() uint16 {
	return volatile.LoadUint16(&o.CDR.Reg) & 0x1ff
}

// SCI0.SPTR: Serial Port Register
func (o *SCI0_Type) SetSPTR_RXDMON(value uint8) {
	volatile.StoreUint8(&o.SPTR.Reg, volatile.LoadUint8(&o.SPTR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetSPTR_RXDMON() uint8 {
	return volatile.LoadUint8(&o.SPTR.Reg) & 0x1
}
func (o *SCI0_Type) SetSPTR_SPB2DT(value uint8) {
	volatile.StoreUint8(&o.SPTR.Reg, volatile.LoadUint8(&o.SPTR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetSPTR_SPB2DT() uint8 {
	return (volatile.LoadUint8(&o.SPTR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetSPTR_SPB2IO(value uint8) {
	volatile.StoreUint8(&o.SPTR.Reg, volatile.LoadUint8(&o.SPTR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetSPTR_SPB2IO() uint8 {
	return (volatile.LoadUint8(&o.SPTR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetSPTR_RINV(value uint8) {
	volatile.StoreUint8(&o.SPTR.Reg, volatile.LoadUint8(&o.SPTR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetSPTR_RINV() uint8 {
	return (volatile.LoadUint8(&o.SPTR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetSPTR_TINV(value uint8) {
	volatile.StoreUint8(&o.SPTR.Reg, volatile.LoadUint8(&o.SPTR.Reg)&^(0x20)|value<<5)
}
func (o *SCI0_Type) GetSPTR_TINV() uint8 {
	return (volatile.LoadUint8(&o.SPTR.Reg) & 0x20) >> 5
}
func (o *SCI0_Type) SetSPTR_ASEN(value uint8) {
	volatile.StoreUint8(&o.SPTR.Reg, volatile.LoadUint8(&o.SPTR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetSPTR_ASEN() uint8 {
	return (volatile.LoadUint8(&o.SPTR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetSPTR_ATEN(value uint8) {
	volatile.StoreUint8(&o.SPTR.Reg, volatile.LoadUint8(&o.SPTR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetSPTR_ATEN() uint8 {
	return (volatile.LoadUint8(&o.SPTR.Reg) & 0x80) >> 7
}

// SCI0.ACTR: Adjustment Communication Timing Register
func (o *SCI0_Type) SetACTR_AST(value uint8) {
	volatile.StoreUint8(&o.ACTR.Reg, volatile.LoadUint8(&o.ACTR.Reg)&^(0x7)|value)
}
func (o *SCI0_Type) GetACTR_AST() uint8 {
	return volatile.LoadUint8(&o.ACTR.Reg) & 0x7
}
func (o *SCI0_Type) SetACTR_AJD(value uint8) {
	volatile.StoreUint8(&o.ACTR.Reg, volatile.LoadUint8(&o.ACTR.Reg)&^(0x8)|value<<3)
}
func (o *SCI0_Type) GetACTR_AJD() uint8 {
	return (volatile.LoadUint8(&o.ACTR.Reg) & 0x8) >> 3
}
func (o *SCI0_Type) SetACTR_ATT(value uint8) {
	volatile.StoreUint8(&o.ACTR.Reg, volatile.LoadUint8(&o.ACTR.Reg)&^(0x70)|value<<4)
}
func (o *SCI0_Type) GetACTR_ATT() uint8 {
	return (volatile.LoadUint8(&o.ACTR.Reg) & 0x70) >> 4
}
func (o *SCI0_Type) SetACTR_AET(value uint8) {
	volatile.StoreUint8(&o.ACTR.Reg, volatile.LoadUint8(&o.ACTR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetACTR_AET() uint8 {
	return (volatile.LoadUint8(&o.ACTR.Reg) & 0x80) >> 7
}

// SCI0.MMR: Manchester Mode Register
func (o *SCI0_Type) SetMMR_RMPOL(value uint8) {
	volatile.StoreUint8(&o.MMR.Reg, volatile.LoadUint8(&o.MMR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetMMR_RMPOL() uint8 {
	return volatile.LoadUint8(&o.MMR.Reg) & 0x1
}
func (o *SCI0_Type) SetMMR_TMPOL(value uint8) {
	volatile.StoreUint8(&o.MMR.Reg, volatile.LoadUint8(&o.MMR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetMMR_TMPOL() uint8 {
	return (volatile.LoadUint8(&o.MMR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetMMR_ERTEN(value uint8) {
	volatile.StoreUint8(&o.MMR.Reg, volatile.LoadUint8(&o.MMR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetMMR_ERTEN() uint8 {
	return (volatile.LoadUint8(&o.MMR.Reg) & 0x4) >> 2
}
func (o *SCI0_Type) SetMMR_SYNVAL(value uint8) {
	volatile.StoreUint8(&o.MMR.Reg, volatile.LoadUint8(&o.MMR.Reg)&^(0x10)|value<<4)
}
func (o *SCI0_Type) GetMMR_SYNVAL() uint8 {
	return (volatile.LoadUint8(&o.MMR.Reg) & 0x10) >> 4
}
func (o *SCI0_Type) SetMMR_SYNSEL(value uint8) {
	volatile.StoreUint8(&o.MMR.Reg, volatile.LoadUint8(&o.MMR.Reg)&^(0x20)|value<<5)
}
func (o *SCI0_Type) GetMMR_SYNSEL() uint8 {
	return (volatile.LoadUint8(&o.MMR.Reg) & 0x20) >> 5
}
func (o *SCI0_Type) SetMMR_SBSEL(value uint8) {
	volatile.StoreUint8(&o.MMR.Reg, volatile.LoadUint8(&o.MMR.Reg)&^(0x40)|value<<6)
}
func (o *SCI0_Type) GetMMR_SBSEL() uint8 {
	return (volatile.LoadUint8(&o.MMR.Reg) & 0x40) >> 6
}
func (o *SCI0_Type) SetMMR_MANEN(value uint8) {
	volatile.StoreUint8(&o.MMR.Reg, volatile.LoadUint8(&o.MMR.Reg)&^(0x80)|value<<7)
}
func (o *SCI0_Type) GetMMR_MANEN() uint8 {
	return (volatile.LoadUint8(&o.MMR.Reg) & 0x80) >> 7
}

// SCI0.TMPR: Transmit Manchester Preface Setting Register
func (o *SCI0_Type) SetTMPR_TPLEN(value uint8) {
	volatile.StoreUint8(&o.TMPR.Reg, volatile.LoadUint8(&o.TMPR.Reg)&^(0xf)|value)
}
func (o *SCI0_Type) GetTMPR_TPLEN() uint8 {
	return volatile.LoadUint8(&o.TMPR.Reg) & 0xf
}
func (o *SCI0_Type) SetTMPR_TPPAT(value uint8) {
	volatile.StoreUint8(&o.TMPR.Reg, volatile.LoadUint8(&o.TMPR.Reg)&^(0x30)|value<<4)
}
func (o *SCI0_Type) GetTMPR_TPPAT() uint8 {
	return (volatile.LoadUint8(&o.TMPR.Reg) & 0x30) >> 4
}

// SCI0.RMPR: Receive Manchester Preface Setting Register
func (o *SCI0_Type) SetRMPR_RPLEN(value uint8) {
	volatile.StoreUint8(&o.RMPR.Reg, volatile.LoadUint8(&o.RMPR.Reg)&^(0xf)|value)
}
func (o *SCI0_Type) GetRMPR_RPLEN() uint8 {
	return volatile.LoadUint8(&o.RMPR.Reg) & 0xf
}
func (o *SCI0_Type) SetRMPR_RPPAT(value uint8) {
	volatile.StoreUint8(&o.RMPR.Reg, volatile.LoadUint8(&o.RMPR.Reg)&^(0x30)|value<<4)
}
func (o *SCI0_Type) GetRMPR_RPPAT() uint8 {
	return (volatile.LoadUint8(&o.RMPR.Reg) & 0x30) >> 4
}

// SCI0.MESR: Manchester Extended Error Status Register
func (o *SCI0_Type) SetMESR_PFER(value uint8) {
	volatile.StoreUint8(&o.MESR.Reg, volatile.LoadUint8(&o.MESR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetMESR_PFER() uint8 {
	return volatile.LoadUint8(&o.MESR.Reg) & 0x1
}
func (o *SCI0_Type) SetMESR_SYER(value uint8) {
	volatile.StoreUint8(&o.MESR.Reg, volatile.LoadUint8(&o.MESR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetMESR_SYER() uint8 {
	return (volatile.LoadUint8(&o.MESR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetMESR_SBER(value uint8) {
	volatile.StoreUint8(&o.MESR.Reg, volatile.LoadUint8(&o.MESR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetMESR_SBER() uint8 {
	return (volatile.LoadUint8(&o.MESR.Reg) & 0x4) >> 2
}

// SCI0.MECR: Manchester Extended Error Control Register
func (o *SCI0_Type) SetMECR_PFEREN(value uint8) {
	volatile.StoreUint8(&o.MECR.Reg, volatile.LoadUint8(&o.MECR.Reg)&^(0x1)|value)
}
func (o *SCI0_Type) GetMECR_PFEREN() uint8 {
	return volatile.LoadUint8(&o.MECR.Reg) & 0x1
}
func (o *SCI0_Type) SetMECR_SYEREN(value uint8) {
	volatile.StoreUint8(&o.MECR.Reg, volatile.LoadUint8(&o.MECR.Reg)&^(0x2)|value<<1)
}
func (o *SCI0_Type) GetMECR_SYEREN() uint8 {
	return (volatile.LoadUint8(&o.MECR.Reg) & 0x2) >> 1
}
func (o *SCI0_Type) SetMECR_SBEREN(value uint8) {
	volatile.StoreUint8(&o.MECR.Reg, volatile.LoadUint8(&o.MECR.Reg)&^(0x4)|value<<2)
}
func (o *SCI0_Type) GetMECR_SBEREN() uint8 {
	return (volatile.LoadUint8(&o.MECR.Reg) & 0x4) >> 2
}

// Serial Peripheral Interface 0
type SPI0_Type struct {
	SPCR   volatile.Register8  // 0x0
	SSLP   volatile.Register8  // 0x1
	SPPCR  volatile.Register8  // 0x2
	SPSR   volatile.Register8  // 0x3
	SPDR   volatile.Register32 // 0x4
	SPSCR  volatile.Register8  // 0x8
	SPSSR  volatile.Register8  // 0x9
	SPBR   volatile.Register8  // 0xA
	SPDCR  volatile.Register8  // 0xB
	SPCKD  volatile.Register8  // 0xC
	SSLND  volatile.Register8  // 0xD
	SPND   volatile.Register8  // 0xE
	SPCR2  volatile.Register8  // 0xF
	SPCMD0 volatile.Register16 // 0x10
	SPCMD1 volatile.Register16 // 0x12
	SPCMD2 volatile.Register16 // 0x14
	SPCMD3 volatile.Register16 // 0x16
	SPCMD4 volatile.Register16 // 0x18
	SPCMD5 volatile.Register16 // 0x1A
	SPCMD6 volatile.Register16 // 0x1C
	SPCMD7 volatile.Register16 // 0x1E
	SPDCR2 volatile.Register8  // 0x20
	SPCR3  volatile.Register8  // 0x21
}

// SPI0.SPCR: SPI Control Register
func (o *SPI0_Type) SetSPCR_SPMS(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCR_SPMS() uint8 {
	return volatile.LoadUint8(&o.SPCR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCR_TXMD(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCR_TXMD() uint8 {
	return (volatile.LoadUint8(&o.SPCR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCR_MODFEN(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPCR_MODFEN() uint8 {
	return (volatile.LoadUint8(&o.SPCR.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPCR_MSTR(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPCR_MSTR() uint8 {
	return (volatile.LoadUint8(&o.SPCR.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPCR_SPEIE(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPCR_SPEIE() uint8 {
	return (volatile.LoadUint8(&o.SPCR.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPCR_SPTIE(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPCR_SPTIE() uint8 {
	return (volatile.LoadUint8(&o.SPCR.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPCR_SPE(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPCR_SPE() uint8 {
	return (volatile.LoadUint8(&o.SPCR.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPCR_SPRIE(value uint8) {
	volatile.StoreUint8(&o.SPCR.Reg, volatile.LoadUint8(&o.SPCR.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCR_SPRIE() uint8 {
	return (volatile.LoadUint8(&o.SPCR.Reg) & 0x80) >> 7
}

// SPI0.SSLP: SPI Slave Select Polarity Register
func (o *SPI0_Type) SetSSLP_SSL0P(value uint8) {
	volatile.StoreUint8(&o.SSLP.Reg, volatile.LoadUint8(&o.SSLP.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSSLP_SSL0P() uint8 {
	return volatile.LoadUint8(&o.SSLP.Reg) & 0x1
}
func (o *SPI0_Type) SetSSLP_SSL1P(value uint8) {
	volatile.StoreUint8(&o.SSLP.Reg, volatile.LoadUint8(&o.SSLP.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSSLP_SSL1P() uint8 {
	return (volatile.LoadUint8(&o.SSLP.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSSLP_SSL2P(value uint8) {
	volatile.StoreUint8(&o.SSLP.Reg, volatile.LoadUint8(&o.SSLP.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSSLP_SSL2P() uint8 {
	return (volatile.LoadUint8(&o.SSLP.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSSLP_SSL3P(value uint8) {
	volatile.StoreUint8(&o.SSLP.Reg, volatile.LoadUint8(&o.SSLP.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSSLP_SSL3P() uint8 {
	return (volatile.LoadUint8(&o.SSLP.Reg) & 0x8) >> 3
}

// SPI0.SPPCR: SPI Pin Control Register
func (o *SPI0_Type) SetSPPCR_SPLP(value uint8) {
	volatile.StoreUint8(&o.SPPCR.Reg, volatile.LoadUint8(&o.SPPCR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPPCR_SPLP() uint8 {
	return volatile.LoadUint8(&o.SPPCR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPPCR_SPLP2(value uint8) {
	volatile.StoreUint8(&o.SPPCR.Reg, volatile.LoadUint8(&o.SPPCR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPPCR_SPLP2() uint8 {
	return (volatile.LoadUint8(&o.SPPCR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPPCR_MOIFV(value uint8) {
	volatile.StoreUint8(&o.SPPCR.Reg, volatile.LoadUint8(&o.SPPCR.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPPCR_MOIFV() uint8 {
	return (volatile.LoadUint8(&o.SPPCR.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPPCR_MOIFE(value uint8) {
	volatile.StoreUint8(&o.SPPCR.Reg, volatile.LoadUint8(&o.SPPCR.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPPCR_MOIFE() uint8 {
	return (volatile.LoadUint8(&o.SPPCR.Reg) & 0x20) >> 5
}

// SPI0.SPSR: SPI Status Register
func (o *SPI0_Type) SetSPSR_OVRF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPSR_OVRF() uint8 {
	return volatile.LoadUint8(&o.SPSR.Reg) & 0x1
}
func (o *SPI0_Type) SetSPSR_IDLNF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPSR_IDLNF() uint8 {
	return (volatile.LoadUint8(&o.SPSR.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPSR_MODF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPSR_MODF() uint8 {
	return (volatile.LoadUint8(&o.SPSR.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPSR_PERF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPSR_PERF() uint8 {
	return (volatile.LoadUint8(&o.SPSR.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPSR_UDRF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPSR_UDRF() uint8 {
	return (volatile.LoadUint8(&o.SPSR.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPSR_SPTEF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPSR_SPTEF() uint8 {
	return (volatile.LoadUint8(&o.SPSR.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPSR_CENDF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPSR_CENDF() uint8 {
	return (volatile.LoadUint8(&o.SPSR.Reg) & 0x40) >> 6
}
func (o *SPI0_Type) SetSPSR_SPRF(value uint8) {
	volatile.StoreUint8(&o.SPSR.Reg, volatile.LoadUint8(&o.SPSR.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPSR_SPRF() uint8 {
	return (volatile.LoadUint8(&o.SPSR.Reg) & 0x80) >> 7
}

// SPI0.SPSCR: SPI Sequence Control Register
func (o *SPI0_Type) SetSPSCR_SPSLN(value uint8) {
	volatile.StoreUint8(&o.SPSCR.Reg, volatile.LoadUint8(&o.SPSCR.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPSCR_SPSLN() uint8 {
	return volatile.LoadUint8(&o.SPSCR.Reg) & 0x7
}

// SPI0.SPSSR: SPI Sequence Status Register
func (o *SPI0_Type) SetSPSSR_SPCP(value uint8) {
	volatile.StoreUint8(&o.SPSSR.Reg, volatile.LoadUint8(&o.SPSSR.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPSSR_SPCP() uint8 {
	return volatile.LoadUint8(&o.SPSSR.Reg) & 0x7
}
func (o *SPI0_Type) SetSPSSR_SPECM(value uint8) {
	volatile.StoreUint8(&o.SPSSR.Reg, volatile.LoadUint8(&o.SPSSR.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPSSR_SPECM() uint8 {
	return (volatile.LoadUint8(&o.SPSSR.Reg) & 0x70) >> 4
}

// SPI0.SPDCR: SPI Data Control Register
func (o *SPI0_Type) SetSPDCR_SPFC(value uint8) {
	volatile.StoreUint8(&o.SPDCR.Reg, volatile.LoadUint8(&o.SPDCR.Reg)&^(0x3)|value)
}
func (o *SPI0_Type) GetSPDCR_SPFC() uint8 {
	return volatile.LoadUint8(&o.SPDCR.Reg) & 0x3
}
func (o *SPI0_Type) SetSPDCR_SPRDTD(value uint8) {
	volatile.StoreUint8(&o.SPDCR.Reg, volatile.LoadUint8(&o.SPDCR.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPDCR_SPRDTD() uint8 {
	return (volatile.LoadUint8(&o.SPDCR.Reg) & 0x10) >> 4
}
func (o *SPI0_Type) SetSPDCR_SPLW(value uint8) {
	volatile.StoreUint8(&o.SPDCR.Reg, volatile.LoadUint8(&o.SPDCR.Reg)&^(0x20)|value<<5)
}
func (o *SPI0_Type) GetSPDCR_SPLW() uint8 {
	return (volatile.LoadUint8(&o.SPDCR.Reg) & 0x20) >> 5
}
func (o *SPI0_Type) SetSPDCR_SPBYT(value uint8) {
	volatile.StoreUint8(&o.SPDCR.Reg, volatile.LoadUint8(&o.SPDCR.Reg)&^(0x40)|value<<6)
}
func (o *SPI0_Type) GetSPDCR_SPBYT() uint8 {
	return (volatile.LoadUint8(&o.SPDCR.Reg) & 0x40) >> 6
}

// SPI0.SPCKD: SPI Clock Delay Register
func (o *SPI0_Type) SetSPCKD_SCKDL(value uint8) {
	volatile.StoreUint8(&o.SPCKD.Reg, volatile.LoadUint8(&o.SPCKD.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPCKD_SCKDL() uint8 {
	return volatile.LoadUint8(&o.SPCKD.Reg) & 0x7
}

// SPI0.SSLND: SPI Slave Select Negation Delay Register
func (o *SPI0_Type) SetSSLND_SLNDL(value uint8) {
	volatile.StoreUint8(&o.SSLND.Reg, volatile.LoadUint8(&o.SSLND.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSSLND_SLNDL() uint8 {
	return volatile.LoadUint8(&o.SSLND.Reg) & 0x7
}

// SPI0.SPND: SPI Next-Access Delay Register
func (o *SPI0_Type) SetSPND_SPNDL(value uint8) {
	volatile.StoreUint8(&o.SPND.Reg, volatile.LoadUint8(&o.SPND.Reg)&^(0x7)|value)
}
func (o *SPI0_Type) GetSPND_SPNDL() uint8 {
	return volatile.LoadUint8(&o.SPND.Reg) & 0x7
}

// SPI0.SPCR2: SPI Control Register 2
func (o *SPI0_Type) SetSPCR2_SPPE(value uint8) {
	volatile.StoreUint8(&o.SPCR2.Reg, volatile.LoadUint8(&o.SPCR2.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCR2_SPPE() uint8 {
	return volatile.LoadUint8(&o.SPCR2.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCR2_SPOE(value uint8) {
	volatile.StoreUint8(&o.SPCR2.Reg, volatile.LoadUint8(&o.SPCR2.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCR2_SPOE() uint8 {
	return (volatile.LoadUint8(&o.SPCR2.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCR2_SPIIE(value uint8) {
	volatile.StoreUint8(&o.SPCR2.Reg, volatile.LoadUint8(&o.SPCR2.Reg)&^(0x4)|value<<2)
}
func (o *SPI0_Type) GetSPCR2_SPIIE() uint8 {
	return (volatile.LoadUint8(&o.SPCR2.Reg) & 0x4) >> 2
}
func (o *SPI0_Type) SetSPCR2_PTE(value uint8) {
	volatile.StoreUint8(&o.SPCR2.Reg, volatile.LoadUint8(&o.SPCR2.Reg)&^(0x8)|value<<3)
}
func (o *SPI0_Type) GetSPCR2_PTE() uint8 {
	return (volatile.LoadUint8(&o.SPCR2.Reg) & 0x8) >> 3
}
func (o *SPI0_Type) SetSPCR2_SCKASE(value uint8) {
	volatile.StoreUint8(&o.SPCR2.Reg, volatile.LoadUint8(&o.SPCR2.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPCR2_SCKASE() uint8 {
	return (volatile.LoadUint8(&o.SPCR2.Reg) & 0x10) >> 4
}

// SPI0.SPCMD0: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD0_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD0_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD0.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD0_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD0_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD0_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD0_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD0_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD0_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD0_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD0_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD0_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD0_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD0_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD0_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD0_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD0_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD0_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD0_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD0_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD0.Reg, volatile.LoadUint16(&o.SPCMD0.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD0_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD0.Reg) & 0x8000) >> 15
}

// SPI0.SPCMD1: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD1_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD1_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD1.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD1_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD1_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD1_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD1_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD1_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD1_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD1_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD1_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD1_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD1_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD1_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD1_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD1_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD1_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD1_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD1_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD1_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD1.Reg, volatile.LoadUint16(&o.SPCMD1.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD1_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD1.Reg) & 0x8000) >> 15
}

// SPI0.SPCMD2: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD2_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD2_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD2.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD2_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD2_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD2_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD2_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD2_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD2_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD2_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD2_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD2_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD2_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD2_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD2_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD2_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD2_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD2_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD2_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD2_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD2.Reg, volatile.LoadUint16(&o.SPCMD2.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD2_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD2.Reg) & 0x8000) >> 15
}

// SPI0.SPCMD3: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD3_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD3_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD3.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD3_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD3_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD3_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD3_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD3_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD3_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD3_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD3_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD3_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD3_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD3_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD3_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD3_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD3_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD3_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD3_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD3_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD3.Reg, volatile.LoadUint16(&o.SPCMD3.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD3_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD3.Reg) & 0x8000) >> 15
}

// SPI0.SPCMD4: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD4_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD4_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD4.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD4_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD4_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD4_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD4_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD4_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD4_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD4_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD4_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD4_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD4_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD4_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD4_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD4_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD4_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD4_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD4_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD4_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD4.Reg, volatile.LoadUint16(&o.SPCMD4.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD4_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD4.Reg) & 0x8000) >> 15
}

// SPI0.SPCMD5: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD5_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD5_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD5.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD5_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD5_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD5_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD5_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD5_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD5_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD5_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD5_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD5_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD5_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD5_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD5_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD5_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD5_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD5_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD5_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD5_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD5.Reg, volatile.LoadUint16(&o.SPCMD5.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD5_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD5.Reg) & 0x8000) >> 15
}

// SPI0.SPCMD6: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD6_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD6_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD6.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD6_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD6_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD6_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD6_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD6_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD6_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD6_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD6_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD6_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD6_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD6_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD6_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD6_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD6_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD6_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD6_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD6_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD6.Reg, volatile.LoadUint16(&o.SPCMD6.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD6_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD6.Reg) & 0x8000) >> 15
}

// SPI0.SPCMD7: SPI Command Register %s
func (o *SPI0_Type) SetSPCMD7_CPHA(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCMD7_CPHA() uint16 {
	return volatile.LoadUint16(&o.SPCMD7.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCMD7_CPOL(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCMD7_CPOL() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCMD7_BRDV(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0xc)|value<<2)
}
func (o *SPI0_Type) GetSPCMD7_BRDV() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0xc) >> 2
}
func (o *SPI0_Type) SetSPCMD7_SSLA(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x70)|value<<4)
}
func (o *SPI0_Type) GetSPCMD7_SSLA() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0x70) >> 4
}
func (o *SPI0_Type) SetSPCMD7_SSLKP(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x80)|value<<7)
}
func (o *SPI0_Type) GetSPCMD7_SSLKP() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0x80) >> 7
}
func (o *SPI0_Type) SetSPCMD7_SPB(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0xf00)|value<<8)
}
func (o *SPI0_Type) GetSPCMD7_SPB() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0xf00) >> 8
}
func (o *SPI0_Type) SetSPCMD7_LSBF(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x1000)|value<<12)
}
func (o *SPI0_Type) GetSPCMD7_LSBF() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0x1000) >> 12
}
func (o *SPI0_Type) SetSPCMD7_SPNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x2000)|value<<13)
}
func (o *SPI0_Type) GetSPCMD7_SPNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0x2000) >> 13
}
func (o *SPI0_Type) SetSPCMD7_SLNDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x4000)|value<<14)
}
func (o *SPI0_Type) GetSPCMD7_SLNDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0x4000) >> 14
}
func (o *SPI0_Type) SetSPCMD7_SCKDEN(value uint16) {
	volatile.StoreUint16(&o.SPCMD7.Reg, volatile.LoadUint16(&o.SPCMD7.Reg)&^(0x8000)|value<<15)
}
func (o *SPI0_Type) GetSPCMD7_SCKDEN() uint16 {
	return (volatile.LoadUint16(&o.SPCMD7.Reg) & 0x8000) >> 15
}

// SPI0.SPDCR2: SPI Data Control Register 2
func (o *SPI0_Type) SetSPDCR2_BYSW(value uint8) {
	volatile.StoreUint8(&o.SPDCR2.Reg, volatile.LoadUint8(&o.SPDCR2.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPDCR2_BYSW() uint8 {
	return volatile.LoadUint8(&o.SPDCR2.Reg) & 0x1
}
func (o *SPI0_Type) SetSPDCR2_SINV(value uint8) {
	volatile.StoreUint8(&o.SPDCR2.Reg, volatile.LoadUint8(&o.SPDCR2.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPDCR2_SINV() uint8 {
	return (volatile.LoadUint8(&o.SPDCR2.Reg) & 0x2) >> 1
}

// SPI0.SPCR3: SPI Control Register 3
func (o *SPI0_Type) SetSPCR3_ETXMD(value uint8) {
	volatile.StoreUint8(&o.SPCR3.Reg, volatile.LoadUint8(&o.SPCR3.Reg)&^(0x1)|value)
}
func (o *SPI0_Type) GetSPCR3_ETXMD() uint8 {
	return volatile.LoadUint8(&o.SPCR3.Reg) & 0x1
}
func (o *SPI0_Type) SetSPCR3_BFDS(value uint8) {
	volatile.StoreUint8(&o.SPCR3.Reg, volatile.LoadUint8(&o.SPCR3.Reg)&^(0x2)|value<<1)
}
func (o *SPI0_Type) GetSPCR3_BFDS() uint8 {
	return (volatile.LoadUint8(&o.SPCR3.Reg) & 0x2) >> 1
}
func (o *SPI0_Type) SetSPCR3_CENDIE(value uint8) {
	volatile.StoreUint8(&o.SPCR3.Reg, volatile.LoadUint8(&o.SPCR3.Reg)&^(0x10)|value<<4)
}
func (o *SPI0_Type) GetSPCR3_CENDIE() uint8 {
	return (volatile.LoadUint8(&o.SPCR3.Reg) & 0x10) >> 4
}

// I3C Bus Interface
type I3C_Type struct {
	PRTS      volatile.Register32 // 0x0
	_         [12]byte
	CECTL     volatile.Register32 // 0x10
	BCTL      volatile.Register32 // 0x14
	MSDVAD    volatile.Register32 // 0x18
	_         [4]byte
	RSTCTL    volatile.Register32 // 0x20
	PRSST     volatile.Register32 // 0x24
	_         [8]byte
	INST      volatile.Register32 // 0x30
	INSTE     volatile.Register32 // 0x34
	INIE      volatile.Register32 // 0x38
	INSTFC    volatile.Register32 // 0x3C
	_         [4]byte
	DVCT      volatile.Register32 // 0x44
	_         [16]byte
	IBINCTL   volatile.Register32 // 0x58
	_         [4]byte
	BFCTL     volatile.Register32 // 0x60
	SVCTL     volatile.Register32 // 0x64
	_         [8]byte
	REFCKCTL  volatile.Register32 // 0x70
	STDBR     volatile.Register32 // 0x74
	EXTBR     volatile.Register32 // 0x78
	BFRECDT   volatile.Register32 // 0x7C
	BAVLCDT   volatile.Register32 // 0x80
	BIDLCDT   volatile.Register32 // 0x84
	OUTCTL    volatile.Register32 // 0x88
	INCTL     volatile.Register32 // 0x8C
	TMOCTL    volatile.Register32 // 0x90
	_         [4]byte
	WUCTL     volatile.Register32 // 0x98
	_         [4]byte
	ACKCTL    volatile.Register32 // 0xA0
	SCSTRCTL  volatile.Register32 // 0xA4
	_         [8]byte
	SCSTLCTL  volatile.Register32 // 0xB0
	_         [12]byte
	SVTDLG0   volatile.Register32 // 0xC0
	_         [92]byte
	STCTL     volatile.Register32 // 0x120
	ATCTL     volatile.Register32 // 0x124
	ATTRG     volatile.Register32 // 0x128
	ATCCNTE   volatile.Register32 // 0x12C
	_         [16]byte
	CNDCTL    volatile.Register32 // 0x140
	_         [12]byte
	NCMDQP    volatile.Register32 // 0x150
	NRSPQP    volatile.Register32 // 0x154
	NTDTBP0   volatile.Register32 // 0x158
	_         [32]byte
	NIBIQP    volatile.Register32 // 0x17C
	NRSQP     volatile.Register32 // 0x180
	HCMDQP    volatile.Register32 // 0x184
	HRSPQP    volatile.Register32 // 0x188
	HTDTBP    volatile.Register32 // 0x18C
	NQTHCTL   volatile.Register32 // 0x190
	NTBTHCTL0 volatile.Register32 // 0x194
	_         [40]byte
	NRQTHCTL  volatile.Register32 // 0x1C0
	HQTHCTL   volatile.Register32 // 0x1C4
	HTBTHCTL  volatile.Register32 // 0x1C8
	_         [4]byte
	BST       volatile.Register32 // 0x1D0
	BSTE      volatile.Register32 // 0x1D4
	BIE       volatile.Register32 // 0x1D8
	BSTFC     volatile.Register32 // 0x1DC
	NTST      volatile.Register32 // 0x1E0
	NTSTE     volatile.Register32 // 0x1E4
	NTIE      volatile.Register32 // 0x1E8
	NTSTFC    volatile.Register32 // 0x1EC
	_         [16]byte
	HTST      volatile.Register32 // 0x200
	HTSTE     volatile.Register32 // 0x204
	HTIE      volatile.Register32 // 0x208
	HTSTFC    volatile.Register32 // 0x20C
	BCST      volatile.Register32 // 0x210
	SVST      volatile.Register32 // 0x214
	WUST      volatile.Register32 // 0x218
	MRCCPT    volatile.Register32 // 0x21C
	_         [4]byte
	DATBAS0   volatile.Register32 // 0x224
	_         [4]byte
	DATBAS1   volatile.Register32 // 0x22C
	_         [4]byte
	DATBAS2   volatile.Register32 // 0x234
	_         [4]byte
	DATBAS3   volatile.Register32 // 0x23C
	_         [4]byte
	DATBAS4   volatile.Register32 // 0x244
	_         [4]byte
	DATBAS5   volatile.Register32 // 0x24C
	_         [4]byte
	DATBAS6   volatile.Register32 // 0x254
	_         [4]byte
	DATBAS7   volatile.Register32 // 0x25C
	_         [64]byte
	EXDATBAS  volatile.Register32 // 0x2A0
	_         [12]byte
	SDATBAS0  volatile.Register32 // 0x2B0
	_         [28]byte
	MSDCT0    volatile.Register32 // 0x2D0
	MSDCT1    volatile.Register32 // 0x2D4
	MSDCT2    volatile.Register32 // 0x2D8
	MSDCT3    volatile.Register32 // 0x2DC
	MSDCT4    volatile.Register32 // 0x2E0
	MSDCT5    volatile.Register32 // 0x2E4
	MSDCT6    volatile.Register32 // 0x2E8
	MSDCT7    volatile.Register32 // 0x2EC
	_         [48]byte
	SVDCT     volatile.Register32 // 0x320
	SDCTPIDL  volatile.Register32 // 0x324
	SDCTPIDH  volatile.Register32 // 0x328
	_         [4]byte
	SVDVAD0   volatile.Register32 // 0x330
	SVDVAD1   volatile.Register32 // 0x334
	SVDVAD2   volatile.Register32 // 0x338
	_         [20]byte
	CSECMD    volatile.Register32 // 0x350
	CEACTST   volatile.Register32 // 0x354
	CMWLG     volatile.Register32 // 0x358
	CMRLG     volatile.Register32 // 0x35C
	CETSTMD   volatile.Register32 // 0x360
	CGDVST    volatile.Register32 // 0x364
	CMDSPW    volatile.Register32 // 0x368
	CMDSPR    volatile.Register32 // 0x36C
	CMDSPT    volatile.Register32 // 0x370
	CETSM     volatile.Register32 // 0x374
	CETSS     volatile.Register32 // 0x378
	_         [4]byte
	BITCNT    volatile.Register32 // 0x380
	_         [16]byte
	NQSTLV    volatile.Register32 // 0x394
	NDBSTLV0  volatile.Register32 // 0x398
	_         [36]byte
	NRSQSTLV  volatile.Register32 // 0x3C0
	HQSTLV    volatile.Register32 // 0x3C4
	HDBSTLV   volatile.Register32 // 0x3C8
	PRSTDBG   volatile.Register32 // 0x3CC
	MSERRCNT  volatile.Register32 // 0x3D0
	_         [12]byte
	SC1CPT    volatile.Register32 // 0x3E0
	SC2CPT    volatile.Register32 // 0x3E4
}

// I3C.PRTS: Protocol Selection Register
func (o *I3C_Type) SetPRTS_PRTMD(value uint32) {
	volatile.StoreUint32(&o.PRTS.Reg, volatile.LoadUint32(&o.PRTS.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetPRTS_PRTMD() uint32 {
	return volatile.LoadUint32(&o.PRTS.Reg) & 0x1
}

// I3C.CECTL: Clock Enable Control Resisters
func (o *I3C_Type) SetCECTL_CLKE(value uint32) {
	volatile.StoreUint32(&o.CECTL.Reg, volatile.LoadUint32(&o.CECTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetCECTL_CLKE() uint32 {
	return volatile.LoadUint32(&o.CECTL.Reg) & 0x1
}

// I3C.BCTL: Bus Control Register
func (o *I3C_Type) SetBCTL_INCBA(value uint32) {
	volatile.StoreUint32(&o.BCTL.Reg, volatile.LoadUint32(&o.BCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetBCTL_INCBA() uint32 {
	return volatile.LoadUint32(&o.BCTL.Reg) & 0x1
}
func (o *I3C_Type) SetBCTL_ABT(value uint32) {
	volatile.StoreUint32(&o.BCTL.Reg, volatile.LoadUint32(&o.BCTL.Reg)&^(0x20000000)|value<<29)
}
func (o *I3C_Type) GetBCTL_ABT() uint32 {
	return (volatile.LoadUint32(&o.BCTL.Reg) & 0x20000000) >> 29
}
func (o *I3C_Type) SetBCTL_RSM(value uint32) {
	volatile.StoreUint32(&o.BCTL.Reg, volatile.LoadUint32(&o.BCTL.Reg)&^(0x40000000)|value<<30)
}
func (o *I3C_Type) GetBCTL_RSM() uint32 {
	return (volatile.LoadUint32(&o.BCTL.Reg) & 0x40000000) >> 30
}
func (o *I3C_Type) SetBCTL_BUSE(value uint32) {
	volatile.StoreUint32(&o.BCTL.Reg, volatile.LoadUint32(&o.BCTL.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetBCTL_BUSE() uint32 {
	return (volatile.LoadUint32(&o.BCTL.Reg) & 0x80000000) >> 31
}

// I3C.MSDVAD: Master Device Address Register
func (o *I3C_Type) SetMSDVAD_MDYAD(value uint32) {
	volatile.StoreUint32(&o.MSDVAD.Reg, volatile.LoadUint32(&o.MSDVAD.Reg)&^(0x7f0000)|value<<16)
}
func (o *I3C_Type) GetMSDVAD_MDYAD() uint32 {
	return (volatile.LoadUint32(&o.MSDVAD.Reg) & 0x7f0000) >> 16
}
func (o *I3C_Type) SetMSDVAD_MDYADV(value uint32) {
	volatile.StoreUint32(&o.MSDVAD.Reg, volatile.LoadUint32(&o.MSDVAD.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetMSDVAD_MDYADV() uint32 {
	return (volatile.LoadUint32(&o.MSDVAD.Reg) & 0x80000000) >> 31
}

// I3C.RSTCTL: Reset Control Register
func (o *I3C_Type) SetRSTCTL_RI3CRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetRSTCTL_RI3CRST() uint32 {
	return volatile.LoadUint32(&o.RSTCTL.Reg) & 0x1
}
func (o *I3C_Type) SetRSTCTL_CMDQRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetRSTCTL_CMDQRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetRSTCTL_RSPQRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetRSTCTL_RSPQRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetRSTCTL_TDBRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetRSTCTL_TDBRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetRSTCTL_RDBRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetRSTCTL_RDBRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetRSTCTL_IBIQRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetRSTCTL_IBIQRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetRSTCTL_RSQRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x40)|value<<6)
}
func (o *I3C_Type) GetRSTCTL_RSQRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x40) >> 6
}
func (o *I3C_Type) SetRSTCTL_HCMDQRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetRSTCTL_HCMDQRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetRSTCTL_HRSPQRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetRSTCTL_HRSPQRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetRSTCTL_HTDBRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetRSTCTL_HTDBRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetRSTCTL_HRDBRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetRSTCTL_HRDBRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetRSTCTL_INTLRST(value uint32) {
	volatile.StoreUint32(&o.RSTCTL.Reg, volatile.LoadUint32(&o.RSTCTL.Reg)&^(0x10000)|value<<16)
}
func (o *I3C_Type) GetRSTCTL_INTLRST() uint32 {
	return (volatile.LoadUint32(&o.RSTCTL.Reg) & 0x10000) >> 16
}

// I3C.PRSST: Present State Register
func (o *I3C_Type) SetPRSST_CRMS(value uint32) {
	volatile.StoreUint32(&o.PRSST.Reg, volatile.LoadUint32(&o.PRSST.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetPRSST_CRMS() uint32 {
	return (volatile.LoadUint32(&o.PRSST.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetPRSST_TRMD(value uint32) {
	volatile.StoreUint32(&o.PRSST.Reg, volatile.LoadUint32(&o.PRSST.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetPRSST_TRMD() uint32 {
	return (volatile.LoadUint32(&o.PRSST.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetPRSST_PRSSTWP(value uint32) {
	volatile.StoreUint32(&o.PRSST.Reg, volatile.LoadUint32(&o.PRSST.Reg)&^(0x80)|value<<7)
}
func (o *I3C_Type) GetPRSST_PRSSTWP() uint32 {
	return (volatile.LoadUint32(&o.PRSST.Reg) & 0x80) >> 7
}

// I3C.INST: Internal Status Register
func (o *I3C_Type) SetINST_INEF(value uint32) {
	volatile.StoreUint32(&o.INST.Reg, volatile.LoadUint32(&o.INST.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetINST_INEF() uint32 {
	return (volatile.LoadUint32(&o.INST.Reg) & 0x400) >> 10
}

// I3C.INSTE: Internal Status Enable Register
func (o *I3C_Type) SetINSTE_INEE(value uint32) {
	volatile.StoreUint32(&o.INSTE.Reg, volatile.LoadUint32(&o.INSTE.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetINSTE_INEE() uint32 {
	return (volatile.LoadUint32(&o.INSTE.Reg) & 0x400) >> 10
}

// I3C.INIE: Internal Interrupt Enable Register
func (o *I3C_Type) SetINIE_INEIE(value uint32) {
	volatile.StoreUint32(&o.INIE.Reg, volatile.LoadUint32(&o.INIE.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetINIE_INEIE() uint32 {
	return (volatile.LoadUint32(&o.INIE.Reg) & 0x400) >> 10
}

// I3C.INSTFC: Internal Status Force Register
func (o *I3C_Type) SetINSTFC_INEFC(value uint32) {
	volatile.StoreUint32(&o.INSTFC.Reg, volatile.LoadUint32(&o.INSTFC.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetINSTFC_INEFC() uint32 {
	return (volatile.LoadUint32(&o.INSTFC.Reg) & 0x400) >> 10
}

// I3C.DVCT: Device Characteristic Table Register
func (o *I3C_Type) SetDVCT_IDX(value uint32) {
	volatile.StoreUint32(&o.DVCT.Reg, volatile.LoadUint32(&o.DVCT.Reg)&^(0xf80000)|value<<19)
}
func (o *I3C_Type) GetDVCT_IDX() uint32 {
	return (volatile.LoadUint32(&o.DVCT.Reg) & 0xf80000) >> 19
}

// I3C.IBINCTL: IBI Notify Control Register
func (o *I3C_Type) SetIBINCTL_NRMRCTL(value uint32) {
	volatile.StoreUint32(&o.IBINCTL.Reg, volatile.LoadUint32(&o.IBINCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetIBINCTL_NRMRCTL() uint32 {
	return (volatile.LoadUint32(&o.IBINCTL.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetIBINCTL_NRSIRCTL(value uint32) {
	volatile.StoreUint32(&o.IBINCTL.Reg, volatile.LoadUint32(&o.IBINCTL.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetIBINCTL_NRSIRCTL() uint32 {
	return (volatile.LoadUint32(&o.IBINCTL.Reg) & 0x8) >> 3
}

// I3C.BFCTL: Bus Function Control Register
func (o *I3C_Type) SetBFCTL_MALE(value uint32) {
	volatile.StoreUint32(&o.BFCTL.Reg, volatile.LoadUint32(&o.BFCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetBFCTL_MALE() uint32 {
	return volatile.LoadUint32(&o.BFCTL.Reg) & 0x1
}
func (o *I3C_Type) SetBFCTL_NALE(value uint32) {
	volatile.StoreUint32(&o.BFCTL.Reg, volatile.LoadUint32(&o.BFCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetBFCTL_NALE() uint32 {
	return (volatile.LoadUint32(&o.BFCTL.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetBFCTL_SALE(value uint32) {
	volatile.StoreUint32(&o.BFCTL.Reg, volatile.LoadUint32(&o.BFCTL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetBFCTL_SALE() uint32 {
	return (volatile.LoadUint32(&o.BFCTL.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetBFCTL_SCSYNE(value uint32) {
	volatile.StoreUint32(&o.BFCTL.Reg, volatile.LoadUint32(&o.BFCTL.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetBFCTL_SCSYNE() uint32 {
	return (volatile.LoadUint32(&o.BFCTL.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetBFCTL_SMBS(value uint32) {
	volatile.StoreUint32(&o.BFCTL.Reg, volatile.LoadUint32(&o.BFCTL.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetBFCTL_SMBS() uint32 {
	return (volatile.LoadUint32(&o.BFCTL.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetBFCTL_FMPE(value uint32) {
	volatile.StoreUint32(&o.BFCTL.Reg, volatile.LoadUint32(&o.BFCTL.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetBFCTL_FMPE() uint32 {
	return (volatile.LoadUint32(&o.BFCTL.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetBFCTL_HSME(value uint32) {
	volatile.StoreUint32(&o.BFCTL.Reg, volatile.LoadUint32(&o.BFCTL.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetBFCTL_HSME() uint32 {
	return (volatile.LoadUint32(&o.BFCTL.Reg) & 0x8000) >> 15
}

// I3C.SVCTL: Slave Control Register
func (o *I3C_Type) SetSVCTL_GCAE(value uint32) {
	volatile.StoreUint32(&o.SVCTL.Reg, volatile.LoadUint32(&o.SVCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetSVCTL_GCAE() uint32 {
	return volatile.LoadUint32(&o.SVCTL.Reg) & 0x1
}
func (o *I3C_Type) SetSVCTL_HSMCE(value uint32) {
	volatile.StoreUint32(&o.SVCTL.Reg, volatile.LoadUint32(&o.SVCTL.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetSVCTL_HSMCE() uint32 {
	return (volatile.LoadUint32(&o.SVCTL.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetSVCTL_DVIDE(value uint32) {
	volatile.StoreUint32(&o.SVCTL.Reg, volatile.LoadUint32(&o.SVCTL.Reg)&^(0x40)|value<<6)
}
func (o *I3C_Type) GetSVCTL_DVIDE() uint32 {
	return (volatile.LoadUint32(&o.SVCTL.Reg) & 0x40) >> 6
}
func (o *I3C_Type) SetSVCTL_HOAE(value uint32) {
	volatile.StoreUint32(&o.SVCTL.Reg, volatile.LoadUint32(&o.SVCTL.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetSVCTL_HOAE() uint32 {
	return (volatile.LoadUint32(&o.SVCTL.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetSVCTL_SVAE(value uint32) {
	volatile.StoreUint32(&o.SVCTL.Reg, volatile.LoadUint32(&o.SVCTL.Reg)&^(0x70000)|value<<16)
}
func (o *I3C_Type) GetSVCTL_SVAE() uint32 {
	return (volatile.LoadUint32(&o.SVCTL.Reg) & 0x70000) >> 16
}

// I3C.REFCKCTL: Reference Clock Control Register
func (o *I3C_Type) SetREFCKCTL_IREFCKS(value uint32) {
	volatile.StoreUint32(&o.REFCKCTL.Reg, volatile.LoadUint32(&o.REFCKCTL.Reg)&^(0x7)|value)
}
func (o *I3C_Type) GetREFCKCTL_IREFCKS() uint32 {
	return volatile.LoadUint32(&o.REFCKCTL.Reg) & 0x7
}

// I3C.STDBR: Standard Bit Rate Register
func (o *I3C_Type) SetSTDBR_SBRLO(value uint32) {
	volatile.StoreUint32(&o.STDBR.Reg, volatile.LoadUint32(&o.STDBR.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetSTDBR_SBRLO() uint32 {
	return volatile.LoadUint32(&o.STDBR.Reg) & 0xff
}
func (o *I3C_Type) SetSTDBR_SBRHO(value uint32) {
	volatile.StoreUint32(&o.STDBR.Reg, volatile.LoadUint32(&o.STDBR.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetSTDBR_SBRHO() uint32 {
	return (volatile.LoadUint32(&o.STDBR.Reg) & 0xff00) >> 8
}
func (o *I3C_Type) SetSTDBR_SBRLP(value uint32) {
	volatile.StoreUint32(&o.STDBR.Reg, volatile.LoadUint32(&o.STDBR.Reg)&^(0x3f0000)|value<<16)
}
func (o *I3C_Type) GetSTDBR_SBRLP() uint32 {
	return (volatile.LoadUint32(&o.STDBR.Reg) & 0x3f0000) >> 16
}
func (o *I3C_Type) SetSTDBR_SBRHP(value uint32) {
	volatile.StoreUint32(&o.STDBR.Reg, volatile.LoadUint32(&o.STDBR.Reg)&^(0x3f000000)|value<<24)
}
func (o *I3C_Type) GetSTDBR_SBRHP() uint32 {
	return (volatile.LoadUint32(&o.STDBR.Reg) & 0x3f000000) >> 24
}
func (o *I3C_Type) SetSTDBR_DSBRPO(value uint32) {
	volatile.StoreUint32(&o.STDBR.Reg, volatile.LoadUint32(&o.STDBR.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetSTDBR_DSBRPO() uint32 {
	return (volatile.LoadUint32(&o.STDBR.Reg) & 0x80000000) >> 31
}

// I3C.EXTBR: Extended Bit Rate Register
func (o *I3C_Type) SetEXTBR_EBRLO(value uint32) {
	volatile.StoreUint32(&o.EXTBR.Reg, volatile.LoadUint32(&o.EXTBR.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetEXTBR_EBRLO() uint32 {
	return volatile.LoadUint32(&o.EXTBR.Reg) & 0xff
}
func (o *I3C_Type) SetEXTBR_EBRHO(value uint32) {
	volatile.StoreUint32(&o.EXTBR.Reg, volatile.LoadUint32(&o.EXTBR.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetEXTBR_EBRHO() uint32 {
	return (volatile.LoadUint32(&o.EXTBR.Reg) & 0xff00) >> 8
}
func (o *I3C_Type) SetEXTBR_EBRLP(value uint32) {
	volatile.StoreUint32(&o.EXTBR.Reg, volatile.LoadUint32(&o.EXTBR.Reg)&^(0x3f0000)|value<<16)
}
func (o *I3C_Type) GetEXTBR_EBRLP() uint32 {
	return (volatile.LoadUint32(&o.EXTBR.Reg) & 0x3f0000) >> 16
}
func (o *I3C_Type) SetEXTBR_EBRHP(value uint32) {
	volatile.StoreUint32(&o.EXTBR.Reg, volatile.LoadUint32(&o.EXTBR.Reg)&^(0x3f000000)|value<<24)
}
func (o *I3C_Type) GetEXTBR_EBRHP() uint32 {
	return (volatile.LoadUint32(&o.EXTBR.Reg) & 0x3f000000) >> 24
}

// I3C.BFRECDT: Bus Free Condition Detection Time Register
func (o *I3C_Type) SetBFRECDT_FRECYC(value uint32) {
	volatile.StoreUint32(&o.BFRECDT.Reg, volatile.LoadUint32(&o.BFRECDT.Reg)&^(0x1ff)|value)
}
func (o *I3C_Type) GetBFRECDT_FRECYC() uint32 {
	return volatile.LoadUint32(&o.BFRECDT.Reg) & 0x1ff
}

// I3C.BAVLCDT: Bus Available Condition Detection Time Register
func (o *I3C_Type) SetBAVLCDT_AVLCYC(value uint32) {
	volatile.StoreUint32(&o.BAVLCDT.Reg, volatile.LoadUint32(&o.BAVLCDT.Reg)&^(0x1ff)|value)
}
func (o *I3C_Type) GetBAVLCDT_AVLCYC() uint32 {
	return volatile.LoadUint32(&o.BAVLCDT.Reg) & 0x1ff
}

// I3C.BIDLCDT: Bus Idle Condition Detection Time Register
func (o *I3C_Type) SetBIDLCDT_IDLCYC(value uint32) {
	volatile.StoreUint32(&o.BIDLCDT.Reg, volatile.LoadUint32(&o.BIDLCDT.Reg)&^(0x3ffff)|value)
}
func (o *I3C_Type) GetBIDLCDT_IDLCYC() uint32 {
	return volatile.LoadUint32(&o.BIDLCDT.Reg) & 0x3ffff
}

// I3C.OUTCTL: Output Control Register
func (o *I3C_Type) SetOUTCTL_SDOC(value uint32) {
	volatile.StoreUint32(&o.OUTCTL.Reg, volatile.LoadUint32(&o.OUTCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetOUTCTL_SDOC() uint32 {
	return volatile.LoadUint32(&o.OUTCTL.Reg) & 0x1
}
func (o *I3C_Type) SetOUTCTL_SCOC(value uint32) {
	volatile.StoreUint32(&o.OUTCTL.Reg, volatile.LoadUint32(&o.OUTCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetOUTCTL_SCOC() uint32 {
	return (volatile.LoadUint32(&o.OUTCTL.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetOUTCTL_SOCWP(value uint32) {
	volatile.StoreUint32(&o.OUTCTL.Reg, volatile.LoadUint32(&o.OUTCTL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetOUTCTL_SOCWP() uint32 {
	return (volatile.LoadUint32(&o.OUTCTL.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetOUTCTL_EXCYC(value uint32) {
	volatile.StoreUint32(&o.OUTCTL.Reg, volatile.LoadUint32(&o.OUTCTL.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetOUTCTL_EXCYC() uint32 {
	return (volatile.LoadUint32(&o.OUTCTL.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetOUTCTL_SDOD(value uint32) {
	volatile.StoreUint32(&o.OUTCTL.Reg, volatile.LoadUint32(&o.OUTCTL.Reg)&^(0x700)|value<<8)
}
func (o *I3C_Type) GetOUTCTL_SDOD() uint32 {
	return (volatile.LoadUint32(&o.OUTCTL.Reg) & 0x700) >> 8
}
func (o *I3C_Type) SetOUTCTL_SDODCS(value uint32) {
	volatile.StoreUint32(&o.OUTCTL.Reg, volatile.LoadUint32(&o.OUTCTL.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetOUTCTL_SDODCS() uint32 {
	return (volatile.LoadUint32(&o.OUTCTL.Reg) & 0x8000) >> 15
}

// I3C.INCTL: Input Control Register
func (o *I3C_Type) SetINCTL_DNFS(value uint32) {
	volatile.StoreUint32(&o.INCTL.Reg, volatile.LoadUint32(&o.INCTL.Reg)&^(0xf)|value)
}
func (o *I3C_Type) GetINCTL_DNFS() uint32 {
	return volatile.LoadUint32(&o.INCTL.Reg) & 0xf
}
func (o *I3C_Type) SetINCTL_DNFE(value uint32) {
	volatile.StoreUint32(&o.INCTL.Reg, volatile.LoadUint32(&o.INCTL.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetINCTL_DNFE() uint32 {
	return (volatile.LoadUint32(&o.INCTL.Reg) & 0x10) >> 4
}

// I3C.TMOCTL: Timeout Control Register
func (o *I3C_Type) SetTMOCTL_TODTS(value uint32) {
	volatile.StoreUint32(&o.TMOCTL.Reg, volatile.LoadUint32(&o.TMOCTL.Reg)&^(0x3)|value)
}
func (o *I3C_Type) GetTMOCTL_TODTS() uint32 {
	return volatile.LoadUint32(&o.TMOCTL.Reg) & 0x3
}
func (o *I3C_Type) SetTMOCTL_TOLCTL(value uint32) {
	volatile.StoreUint32(&o.TMOCTL.Reg, volatile.LoadUint32(&o.TMOCTL.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetTMOCTL_TOLCTL() uint32 {
	return (volatile.LoadUint32(&o.TMOCTL.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetTMOCTL_TOHCTL(value uint32) {
	volatile.StoreUint32(&o.TMOCTL.Reg, volatile.LoadUint32(&o.TMOCTL.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetTMOCTL_TOHCTL() uint32 {
	return (volatile.LoadUint32(&o.TMOCTL.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetTMOCTL_TOMDS(value uint32) {
	volatile.StoreUint32(&o.TMOCTL.Reg, volatile.LoadUint32(&o.TMOCTL.Reg)&^(0xc0)|value<<6)
}
func (o *I3C_Type) GetTMOCTL_TOMDS() uint32 {
	return (volatile.LoadUint32(&o.TMOCTL.Reg) & 0xc0) >> 6
}

// I3C.WUCTL: Wake Up Unit Control Register
func (o *I3C_Type) SetWUCTL_WUACKS(value uint32) {
	volatile.StoreUint32(&o.WUCTL.Reg, volatile.LoadUint32(&o.WUCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetWUCTL_WUACKS() uint32 {
	return volatile.LoadUint32(&o.WUCTL.Reg) & 0x1
}
func (o *I3C_Type) SetWUCTL_WUANFS(value uint32) {
	volatile.StoreUint32(&o.WUCTL.Reg, volatile.LoadUint32(&o.WUCTL.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetWUCTL_WUANFS() uint32 {
	return (volatile.LoadUint32(&o.WUCTL.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetWUCTL_WUFSYNE(value uint32) {
	volatile.StoreUint32(&o.WUCTL.Reg, volatile.LoadUint32(&o.WUCTL.Reg)&^(0x40)|value<<6)
}
func (o *I3C_Type) GetWUCTL_WUFSYNE() uint32 {
	return (volatile.LoadUint32(&o.WUCTL.Reg) & 0x40) >> 6
}
func (o *I3C_Type) SetWUCTL_WUFE(value uint32) {
	volatile.StoreUint32(&o.WUCTL.Reg, volatile.LoadUint32(&o.WUCTL.Reg)&^(0x80)|value<<7)
}
func (o *I3C_Type) GetWUCTL_WUFE() uint32 {
	return (volatile.LoadUint32(&o.WUCTL.Reg) & 0x80) >> 7
}

// I3C.ACKCTL: Acknowledge Control Register
func (o *I3C_Type) SetACKCTL_ACKR(value uint32) {
	volatile.StoreUint32(&o.ACKCTL.Reg, volatile.LoadUint32(&o.ACKCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetACKCTL_ACKR() uint32 {
	return volatile.LoadUint32(&o.ACKCTL.Reg) & 0x1
}
func (o *I3C_Type) SetACKCTL_ACKT(value uint32) {
	volatile.StoreUint32(&o.ACKCTL.Reg, volatile.LoadUint32(&o.ACKCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetACKCTL_ACKT() uint32 {
	return (volatile.LoadUint32(&o.ACKCTL.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetACKCTL_ACKTWP(value uint32) {
	volatile.StoreUint32(&o.ACKCTL.Reg, volatile.LoadUint32(&o.ACKCTL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetACKCTL_ACKTWP() uint32 {
	return (volatile.LoadUint32(&o.ACKCTL.Reg) & 0x4) >> 2
}

// I3C.SCSTRCTL: SCL Stretch Control Register
func (o *I3C_Type) SetSCSTRCTL_ACKTWE(value uint32) {
	volatile.StoreUint32(&o.SCSTRCTL.Reg, volatile.LoadUint32(&o.SCSTRCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetSCSTRCTL_ACKTWE() uint32 {
	return volatile.LoadUint32(&o.SCSTRCTL.Reg) & 0x1
}
func (o *I3C_Type) SetSCSTRCTL_RWE(value uint32) {
	volatile.StoreUint32(&o.SCSTRCTL.Reg, volatile.LoadUint32(&o.SCSTRCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetSCSTRCTL_RWE() uint32 {
	return (volatile.LoadUint32(&o.SCSTRCTL.Reg) & 0x2) >> 1
}

// I3C.SCSTLCTL: SCL Stalling Control Register
func (o *I3C_Type) SetSCSTLCTL_STLCYC(value uint32) {
	volatile.StoreUint32(&o.SCSTLCTL.Reg, volatile.LoadUint32(&o.SCSTLCTL.Reg)&^(0xffff)|value)
}
func (o *I3C_Type) GetSCSTLCTL_STLCYC() uint32 {
	return volatile.LoadUint32(&o.SCSTLCTL.Reg) & 0xffff
}
func (o *I3C_Type) SetSCSTLCTL_AAPE(value uint32) {
	volatile.StoreUint32(&o.SCSTLCTL.Reg, volatile.LoadUint32(&o.SCSTLCTL.Reg)&^(0x10000000)|value<<28)
}
func (o *I3C_Type) GetSCSTLCTL_AAPE() uint32 {
	return (volatile.LoadUint32(&o.SCSTLCTL.Reg) & 0x10000000) >> 28
}
func (o *I3C_Type) SetSCSTLCTL_PARPE(value uint32) {
	volatile.StoreUint32(&o.SCSTLCTL.Reg, volatile.LoadUint32(&o.SCSTLCTL.Reg)&^(0x40000000)|value<<30)
}
func (o *I3C_Type) GetSCSTLCTL_PARPE() uint32 {
	return (volatile.LoadUint32(&o.SCSTLCTL.Reg) & 0x40000000) >> 30
}
func (o *I3C_Type) SetSCSTLCTL_ACKPE(value uint32) {
	volatile.StoreUint32(&o.SCSTLCTL.Reg, volatile.LoadUint32(&o.SCSTLCTL.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetSCSTLCTL_ACKPE() uint32 {
	return (volatile.LoadUint32(&o.SCSTLCTL.Reg) & 0x80000000) >> 31
}

// I3C.SVTDLG0: Slave Transfer Data Length Register 0
func (o *I3C_Type) SetSVTDLG0_STDLG(value uint32) {
	volatile.StoreUint32(&o.SVTDLG0.Reg, volatile.LoadUint32(&o.SVTDLG0.Reg)&^(0xffff0000)|value<<16)
}
func (o *I3C_Type) GetSVTDLG0_STDLG() uint32 {
	return (volatile.LoadUint32(&o.SVTDLG0.Reg) & 0xffff0000) >> 16
}

// I3C.STCTL: Synchronous Timing Control Register
func (o *I3C_Type) SetSTCTL_STOE(value uint32) {
	volatile.StoreUint32(&o.STCTL.Reg, volatile.LoadUint32(&o.STCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetSTCTL_STOE() uint32 {
	return volatile.LoadUint32(&o.STCTL.Reg) & 0x1
}

// I3C.ATCTL: Asynchronous Timing Control Register
func (o *I3C_Type) SetATCTL_ATTRGS(value uint32) {
	volatile.StoreUint32(&o.ATCTL.Reg, volatile.LoadUint32(&o.ATCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetATCTL_ATTRGS() uint32 {
	return volatile.LoadUint32(&o.ATCTL.Reg) & 0x1
}
func (o *I3C_Type) SetATCTL_MREFOE(value uint32) {
	volatile.StoreUint32(&o.ATCTL.Reg, volatile.LoadUint32(&o.ATCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetATCTL_MREFOE() uint32 {
	return (volatile.LoadUint32(&o.ATCTL.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetATCTL_AMEOE(value uint32) {
	volatile.StoreUint32(&o.ATCTL.Reg, volatile.LoadUint32(&o.ATCTL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetATCTL_AMEOE() uint32 {
	return (volatile.LoadUint32(&o.ATCTL.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetATCTL_CDIV(value uint32) {
	volatile.StoreUint32(&o.ATCTL.Reg, volatile.LoadUint32(&o.ATCTL.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetATCTL_CDIV() uint32 {
	return (volatile.LoadUint32(&o.ATCTL.Reg) & 0xff00) >> 8
}

// I3C.ATTRG: Asynchronous Timing Trigger Register
func (o *I3C_Type) SetATTRG_ATSTRG(value uint32) {
	volatile.StoreUint32(&o.ATTRG.Reg, volatile.LoadUint32(&o.ATTRG.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetATTRG_ATSTRG() uint32 {
	return volatile.LoadUint32(&o.ATTRG.Reg) & 0x1
}

// I3C.ATCCNTE: Asynchronous Timing Contorol Counter enable Register
func (o *I3C_Type) SetATCCNTE_ATCE(value uint32) {
	volatile.StoreUint32(&o.ATCCNTE.Reg, volatile.LoadUint32(&o.ATCCNTE.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetATCCNTE_ATCE() uint32 {
	return volatile.LoadUint32(&o.ATCCNTE.Reg) & 0x1
}

// I3C.CNDCTL: Condition Control Register
func (o *I3C_Type) SetCNDCTL_STCND(value uint32) {
	volatile.StoreUint32(&o.CNDCTL.Reg, volatile.LoadUint32(&o.CNDCTL.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetCNDCTL_STCND() uint32 {
	return volatile.LoadUint32(&o.CNDCTL.Reg) & 0x1
}
func (o *I3C_Type) SetCNDCTL_SRCND(value uint32) {
	volatile.StoreUint32(&o.CNDCTL.Reg, volatile.LoadUint32(&o.CNDCTL.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetCNDCTL_SRCND() uint32 {
	return (volatile.LoadUint32(&o.CNDCTL.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetCNDCTL_SPCND(value uint32) {
	volatile.StoreUint32(&o.CNDCTL.Reg, volatile.LoadUint32(&o.CNDCTL.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetCNDCTL_SPCND() uint32 {
	return (volatile.LoadUint32(&o.CNDCTL.Reg) & 0x4) >> 2
}

// I3C.NQTHCTL: Normal Queue Threshold Control Register
func (o *I3C_Type) SetNQTHCTL_CMDQTH(value uint32) {
	volatile.StoreUint32(&o.NQTHCTL.Reg, volatile.LoadUint32(&o.NQTHCTL.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetNQTHCTL_CMDQTH() uint32 {
	return volatile.LoadUint32(&o.NQTHCTL.Reg) & 0xff
}
func (o *I3C_Type) SetNQTHCTL_RSPQTH(value uint32) {
	volatile.StoreUint32(&o.NQTHCTL.Reg, volatile.LoadUint32(&o.NQTHCTL.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetNQTHCTL_RSPQTH() uint32 {
	return (volatile.LoadUint32(&o.NQTHCTL.Reg) & 0xff00) >> 8
}
func (o *I3C_Type) SetNQTHCTL_IBIDSSZ(value uint32) {
	volatile.StoreUint32(&o.NQTHCTL.Reg, volatile.LoadUint32(&o.NQTHCTL.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetNQTHCTL_IBIDSSZ() uint32 {
	return (volatile.LoadUint32(&o.NQTHCTL.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetNQTHCTL_IBIQTH(value uint32) {
	volatile.StoreUint32(&o.NQTHCTL.Reg, volatile.LoadUint32(&o.NQTHCTL.Reg)&^(0xff000000)|value<<24)
}
func (o *I3C_Type) GetNQTHCTL_IBIQTH() uint32 {
	return (volatile.LoadUint32(&o.NQTHCTL.Reg) & 0xff000000) >> 24
}

// I3C.NTBTHCTL0: Normal Transfer Data Buffer Threshold Control Register 0
func (o *I3C_Type) SetNTBTHCTL0_TXDBTH(value uint32) {
	volatile.StoreUint32(&o.NTBTHCTL0.Reg, volatile.LoadUint32(&o.NTBTHCTL0.Reg)&^(0x7)|value)
}
func (o *I3C_Type) GetNTBTHCTL0_TXDBTH() uint32 {
	return volatile.LoadUint32(&o.NTBTHCTL0.Reg) & 0x7
}
func (o *I3C_Type) SetNTBTHCTL0_RXDBTH(value uint32) {
	volatile.StoreUint32(&o.NTBTHCTL0.Reg, volatile.LoadUint32(&o.NTBTHCTL0.Reg)&^(0x700)|value<<8)
}
func (o *I3C_Type) GetNTBTHCTL0_RXDBTH() uint32 {
	return (volatile.LoadUint32(&o.NTBTHCTL0.Reg) & 0x700) >> 8
}
func (o *I3C_Type) SetNTBTHCTL0_TXSTTH(value uint32) {
	volatile.StoreUint32(&o.NTBTHCTL0.Reg, volatile.LoadUint32(&o.NTBTHCTL0.Reg)&^(0x70000)|value<<16)
}
func (o *I3C_Type) GetNTBTHCTL0_TXSTTH() uint32 {
	return (volatile.LoadUint32(&o.NTBTHCTL0.Reg) & 0x70000) >> 16
}
func (o *I3C_Type) SetNTBTHCTL0_RXSTTH(value uint32) {
	volatile.StoreUint32(&o.NTBTHCTL0.Reg, volatile.LoadUint32(&o.NTBTHCTL0.Reg)&^(0x7000000)|value<<24)
}
func (o *I3C_Type) GetNTBTHCTL0_RXSTTH() uint32 {
	return (volatile.LoadUint32(&o.NTBTHCTL0.Reg) & 0x7000000) >> 24
}

// I3C.NRQTHCTL: Normal Receive Status Queue Threshold Control Register
func (o *I3C_Type) SetNRQTHCTL_RSQTH(value uint32) {
	volatile.StoreUint32(&o.NRQTHCTL.Reg, volatile.LoadUint32(&o.NRQTHCTL.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetNRQTHCTL_RSQTH() uint32 {
	return volatile.LoadUint32(&o.NRQTHCTL.Reg) & 0xff
}

// I3C.HQTHCTL: High Priority Queue Threshold Control Register
func (o *I3C_Type) SetHQTHCTL_CMDQTH(value uint32) {
	volatile.StoreUint32(&o.HQTHCTL.Reg, volatile.LoadUint32(&o.HQTHCTL.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetHQTHCTL_CMDQTH() uint32 {
	return volatile.LoadUint32(&o.HQTHCTL.Reg) & 0xff
}
func (o *I3C_Type) SetHQTHCTL_RSPQTH(value uint32) {
	volatile.StoreUint32(&o.HQTHCTL.Reg, volatile.LoadUint32(&o.HQTHCTL.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetHQTHCTL_RSPQTH() uint32 {
	return (volatile.LoadUint32(&o.HQTHCTL.Reg) & 0xff00) >> 8
}

// I3C.HTBTHCTL: High Priority Transfer Data Buffer Threshold Control Register
func (o *I3C_Type) SetHTBTHCTL_TXDBTH(value uint32) {
	volatile.StoreUint32(&o.HTBTHCTL.Reg, volatile.LoadUint32(&o.HTBTHCTL.Reg)&^(0x7)|value)
}
func (o *I3C_Type) GetHTBTHCTL_TXDBTH() uint32 {
	return volatile.LoadUint32(&o.HTBTHCTL.Reg) & 0x7
}
func (o *I3C_Type) SetHTBTHCTL_RXDBTH(value uint32) {
	volatile.StoreUint32(&o.HTBTHCTL.Reg, volatile.LoadUint32(&o.HTBTHCTL.Reg)&^(0x700)|value<<8)
}
func (o *I3C_Type) GetHTBTHCTL_RXDBTH() uint32 {
	return (volatile.LoadUint32(&o.HTBTHCTL.Reg) & 0x700) >> 8
}
func (o *I3C_Type) SetHTBTHCTL_TXSTTH(value uint32) {
	volatile.StoreUint32(&o.HTBTHCTL.Reg, volatile.LoadUint32(&o.HTBTHCTL.Reg)&^(0x70000)|value<<16)
}
func (o *I3C_Type) GetHTBTHCTL_TXSTTH() uint32 {
	return (volatile.LoadUint32(&o.HTBTHCTL.Reg) & 0x70000) >> 16
}
func (o *I3C_Type) SetHTBTHCTL_RXSTTH(value uint32) {
	volatile.StoreUint32(&o.HTBTHCTL.Reg, volatile.LoadUint32(&o.HTBTHCTL.Reg)&^(0x7000000)|value<<24)
}
func (o *I3C_Type) GetHTBTHCTL_RXSTTH() uint32 {
	return (volatile.LoadUint32(&o.HTBTHCTL.Reg) & 0x7000000) >> 24
}

// I3C.BST: Bus Status Register
func (o *I3C_Type) SetBST_STCNDDF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetBST_STCNDDF() uint32 {
	return volatile.LoadUint32(&o.BST.Reg) & 0x1
}
func (o *I3C_Type) SetBST_SPCNDDF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetBST_SPCNDDF() uint32 {
	return (volatile.LoadUint32(&o.BST.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetBST_HDREXDF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetBST_HDREXDF() uint32 {
	return (volatile.LoadUint32(&o.BST.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetBST_NACKDF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetBST_NACKDF() uint32 {
	return (volatile.LoadUint32(&o.BST.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetBST_TENDF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetBST_TENDF() uint32 {
	return (volatile.LoadUint32(&o.BST.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetBST_ALF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x10000)|value<<16)
}
func (o *I3C_Type) GetBST_ALF() uint32 {
	return (volatile.LoadUint32(&o.BST.Reg) & 0x10000) >> 16
}
func (o *I3C_Type) SetBST_TODF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetBST_TODF() uint32 {
	return (volatile.LoadUint32(&o.BST.Reg) & 0x100000) >> 20
}
func (o *I3C_Type) SetBST_WUCNDDF(value uint32) {
	volatile.StoreUint32(&o.BST.Reg, volatile.LoadUint32(&o.BST.Reg)&^(0x1000000)|value<<24)
}
func (o *I3C_Type) GetBST_WUCNDDF() uint32 {
	return (volatile.LoadUint32(&o.BST.Reg) & 0x1000000) >> 24
}

// I3C.BSTE: Bus Status Enable Register
func (o *I3C_Type) SetBSTE_STCNDDE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetBSTE_STCNDDE() uint32 {
	return volatile.LoadUint32(&o.BSTE.Reg) & 0x1
}
func (o *I3C_Type) SetBSTE_SPCNDDE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetBSTE_SPCNDDE() uint32 {
	return (volatile.LoadUint32(&o.BSTE.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetBSTE_HDREXDE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetBSTE_HDREXDE() uint32 {
	return (volatile.LoadUint32(&o.BSTE.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetBSTE_NACKDE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetBSTE_NACKDE() uint32 {
	return (volatile.LoadUint32(&o.BSTE.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetBSTE_TENDE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetBSTE_TENDE() uint32 {
	return (volatile.LoadUint32(&o.BSTE.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetBSTE_ALE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x10000)|value<<16)
}
func (o *I3C_Type) GetBSTE_ALE() uint32 {
	return (volatile.LoadUint32(&o.BSTE.Reg) & 0x10000) >> 16
}
func (o *I3C_Type) SetBSTE_TODE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetBSTE_TODE() uint32 {
	return (volatile.LoadUint32(&o.BSTE.Reg) & 0x100000) >> 20
}
func (o *I3C_Type) SetBSTE_WUCNDDE(value uint32) {
	volatile.StoreUint32(&o.BSTE.Reg, volatile.LoadUint32(&o.BSTE.Reg)&^(0x1000000)|value<<24)
}
func (o *I3C_Type) GetBSTE_WUCNDDE() uint32 {
	return (volatile.LoadUint32(&o.BSTE.Reg) & 0x1000000) >> 24
}

// I3C.BIE: Bus Interrupt Enable Register
func (o *I3C_Type) SetBIE_STCNDDIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetBIE_STCNDDIE() uint32 {
	return volatile.LoadUint32(&o.BIE.Reg) & 0x1
}
func (o *I3C_Type) SetBIE_SPCNDDIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetBIE_SPCNDDIE() uint32 {
	return (volatile.LoadUint32(&o.BIE.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetBIE_HDREXDIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetBIE_HDREXDIE() uint32 {
	return (volatile.LoadUint32(&o.BIE.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetBIE_NACKDIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetBIE_NACKDIE() uint32 {
	return (volatile.LoadUint32(&o.BIE.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetBIE_TENDIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetBIE_TENDIE() uint32 {
	return (volatile.LoadUint32(&o.BIE.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetBIE_ALIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x10000)|value<<16)
}
func (o *I3C_Type) GetBIE_ALIE() uint32 {
	return (volatile.LoadUint32(&o.BIE.Reg) & 0x10000) >> 16
}
func (o *I3C_Type) SetBIE_TODIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetBIE_TODIE() uint32 {
	return (volatile.LoadUint32(&o.BIE.Reg) & 0x100000) >> 20
}
func (o *I3C_Type) SetBIE_WUCNDDIE(value uint32) {
	volatile.StoreUint32(&o.BIE.Reg, volatile.LoadUint32(&o.BIE.Reg)&^(0x1000000)|value<<24)
}
func (o *I3C_Type) GetBIE_WUCNDDIE() uint32 {
	return (volatile.LoadUint32(&o.BIE.Reg) & 0x1000000) >> 24
}

// I3C.BSTFC: Bus Status Force Register
func (o *I3C_Type) SetBSTFC_STCNDDFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetBSTFC_STCNDDFC() uint32 {
	return volatile.LoadUint32(&o.BSTFC.Reg) & 0x1
}
func (o *I3C_Type) SetBSTFC_SPCNDDFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetBSTFC_SPCNDDFC() uint32 {
	return (volatile.LoadUint32(&o.BSTFC.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetBSTFC_HDREXDFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetBSTFC_HDREXDFC() uint32 {
	return (volatile.LoadUint32(&o.BSTFC.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetBSTFC_NACKDFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetBSTFC_NACKDFC() uint32 {
	return (volatile.LoadUint32(&o.BSTFC.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetBSTFC_TENDFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetBSTFC_TENDFC() uint32 {
	return (volatile.LoadUint32(&o.BSTFC.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetBSTFC_ALFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x10000)|value<<16)
}
func (o *I3C_Type) GetBSTFC_ALFC() uint32 {
	return (volatile.LoadUint32(&o.BSTFC.Reg) & 0x10000) >> 16
}
func (o *I3C_Type) SetBSTFC_TODFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetBSTFC_TODFC() uint32 {
	return (volatile.LoadUint32(&o.BSTFC.Reg) & 0x100000) >> 20
}
func (o *I3C_Type) SetBSTFC_WUCNDDFC(value uint32) {
	volatile.StoreUint32(&o.BSTFC.Reg, volatile.LoadUint32(&o.BSTFC.Reg)&^(0x1000000)|value<<24)
}
func (o *I3C_Type) GetBSTFC_WUCNDDFC() uint32 {
	return (volatile.LoadUint32(&o.BSTFC.Reg) & 0x1000000) >> 24
}

// I3C.NTST: Normal Transfer Status Register
func (o *I3C_Type) SetNTST_TDBEF0(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetNTST_TDBEF0() uint32 {
	return volatile.LoadUint32(&o.NTST.Reg) & 0x1
}
func (o *I3C_Type) SetNTST_RDBFF0(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetNTST_RDBFF0() uint32 {
	return (volatile.LoadUint32(&o.NTST.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetNTST_IBIQEFF(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetNTST_IBIQEFF() uint32 {
	return (volatile.LoadUint32(&o.NTST.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetNTST_CMDQEF(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetNTST_CMDQEF() uint32 {
	return (volatile.LoadUint32(&o.NTST.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetNTST_RSPQFF(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetNTST_RSPQFF() uint32 {
	return (volatile.LoadUint32(&o.NTST.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetNTST_TABTF(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetNTST_TABTF() uint32 {
	return (volatile.LoadUint32(&o.NTST.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetNTST_TEF(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetNTST_TEF() uint32 {
	return (volatile.LoadUint32(&o.NTST.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetNTST_RSQFF(value uint32) {
	volatile.StoreUint32(&o.NTST.Reg, volatile.LoadUint32(&o.NTST.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetNTST_RSQFF() uint32 {
	return (volatile.LoadUint32(&o.NTST.Reg) & 0x100000) >> 20
}

// I3C.NTSTE: Normal Transfer Status Enable Register
func (o *I3C_Type) SetNTSTE_TDBEE0(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetNTSTE_TDBEE0() uint32 {
	return volatile.LoadUint32(&o.NTSTE.Reg) & 0x1
}
func (o *I3C_Type) SetNTSTE_RDBFE0(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetNTSTE_RDBFE0() uint32 {
	return (volatile.LoadUint32(&o.NTSTE.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetNTSTE_IBIQEFE(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetNTSTE_IBIQEFE() uint32 {
	return (volatile.LoadUint32(&o.NTSTE.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetNTSTE_CMDQEE(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetNTSTE_CMDQEE() uint32 {
	return (volatile.LoadUint32(&o.NTSTE.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetNTSTE_RSPQFE(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetNTSTE_RSPQFE() uint32 {
	return (volatile.LoadUint32(&o.NTSTE.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetNTSTE_TABTE(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetNTSTE_TABTE() uint32 {
	return (volatile.LoadUint32(&o.NTSTE.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetNTSTE_TEE(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetNTSTE_TEE() uint32 {
	return (volatile.LoadUint32(&o.NTSTE.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetNTSTE_RSQFE(value uint32) {
	volatile.StoreUint32(&o.NTSTE.Reg, volatile.LoadUint32(&o.NTSTE.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetNTSTE_RSQFE() uint32 {
	return (volatile.LoadUint32(&o.NTSTE.Reg) & 0x100000) >> 20
}

// I3C.NTIE: Normal Transfer Interrupt Enable Register
func (o *I3C_Type) SetNTIE_TDBEIE0(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetNTIE_TDBEIE0() uint32 {
	return volatile.LoadUint32(&o.NTIE.Reg) & 0x1
}
func (o *I3C_Type) SetNTIE_RDBFIE0(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetNTIE_RDBFIE0() uint32 {
	return (volatile.LoadUint32(&o.NTIE.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetNTIE_IBIQEFIE(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetNTIE_IBIQEFIE() uint32 {
	return (volatile.LoadUint32(&o.NTIE.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetNTIE_CMDQEIE(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetNTIE_CMDQEIE() uint32 {
	return (volatile.LoadUint32(&o.NTIE.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetNTIE_RSPQFIE(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetNTIE_RSPQFIE() uint32 {
	return (volatile.LoadUint32(&o.NTIE.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetNTIE_TABTIE(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetNTIE_TABTIE() uint32 {
	return (volatile.LoadUint32(&o.NTIE.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetNTIE_TEIE(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetNTIE_TEIE() uint32 {
	return (volatile.LoadUint32(&o.NTIE.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetNTIE_RSQFIE(value uint32) {
	volatile.StoreUint32(&o.NTIE.Reg, volatile.LoadUint32(&o.NTIE.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetNTIE_RSQFIE() uint32 {
	return (volatile.LoadUint32(&o.NTIE.Reg) & 0x100000) >> 20
}

// I3C.NTSTFC: Normal Transfer Status Force Register
func (o *I3C_Type) SetNTSTFC_TDBEFC0(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetNTSTFC_TDBEFC0() uint32 {
	return volatile.LoadUint32(&o.NTSTFC.Reg) & 0x1
}
func (o *I3C_Type) SetNTSTFC_RDBFFC0(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetNTSTFC_RDBFFC0() uint32 {
	return (volatile.LoadUint32(&o.NTSTFC.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetNTSTFC_IBIQEFFC(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetNTSTFC_IBIQEFFC() uint32 {
	return (volatile.LoadUint32(&o.NTSTFC.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetNTSTFC_CMDQEFC(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetNTSTFC_CMDQEFC() uint32 {
	return (volatile.LoadUint32(&o.NTSTFC.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetNTSTFC_RSPQFFC(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetNTSTFC_RSPQFFC() uint32 {
	return (volatile.LoadUint32(&o.NTSTFC.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetNTSTFC_TABTFC(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetNTSTFC_TABTFC() uint32 {
	return (volatile.LoadUint32(&o.NTSTFC.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetNTSTFC_TEFC(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetNTSTFC_TEFC() uint32 {
	return (volatile.LoadUint32(&o.NTSTFC.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetNTSTFC_RSQFFC(value uint32) {
	volatile.StoreUint32(&o.NTSTFC.Reg, volatile.LoadUint32(&o.NTSTFC.Reg)&^(0x100000)|value<<20)
}
func (o *I3C_Type) GetNTSTFC_RSQFFC() uint32 {
	return (volatile.LoadUint32(&o.NTSTFC.Reg) & 0x100000) >> 20
}

// I3C.HTST: High Priority Transfer Status Register
func (o *I3C_Type) SetHTST_TDBEF(value uint32) {
	volatile.StoreUint32(&o.HTST.Reg, volatile.LoadUint32(&o.HTST.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetHTST_TDBEF() uint32 {
	return volatile.LoadUint32(&o.HTST.Reg) & 0x1
}
func (o *I3C_Type) SetHTST_RDBFF(value uint32) {
	volatile.StoreUint32(&o.HTST.Reg, volatile.LoadUint32(&o.HTST.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetHTST_RDBFF() uint32 {
	return (volatile.LoadUint32(&o.HTST.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetHTST_CMDQEF(value uint32) {
	volatile.StoreUint32(&o.HTST.Reg, volatile.LoadUint32(&o.HTST.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetHTST_CMDQEF() uint32 {
	return (volatile.LoadUint32(&o.HTST.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetHTST_RSPQFF(value uint32) {
	volatile.StoreUint32(&o.HTST.Reg, volatile.LoadUint32(&o.HTST.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetHTST_RSPQFF() uint32 {
	return (volatile.LoadUint32(&o.HTST.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetHTST_TABTF(value uint32) {
	volatile.StoreUint32(&o.HTST.Reg, volatile.LoadUint32(&o.HTST.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetHTST_TABTF() uint32 {
	return (volatile.LoadUint32(&o.HTST.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetHTST_TEF(value uint32) {
	volatile.StoreUint32(&o.HTST.Reg, volatile.LoadUint32(&o.HTST.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetHTST_TEF() uint32 {
	return (volatile.LoadUint32(&o.HTST.Reg) & 0x200) >> 9
}

// I3C.HTSTE: High Priority Transfer Status Enable Register
func (o *I3C_Type) SetHTSTE_TDBEE(value uint32) {
	volatile.StoreUint32(&o.HTSTE.Reg, volatile.LoadUint32(&o.HTSTE.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetHTSTE_TDBEE() uint32 {
	return volatile.LoadUint32(&o.HTSTE.Reg) & 0x1
}
func (o *I3C_Type) SetHTSTE_RDBFE(value uint32) {
	volatile.StoreUint32(&o.HTSTE.Reg, volatile.LoadUint32(&o.HTSTE.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetHTSTE_RDBFE() uint32 {
	return (volatile.LoadUint32(&o.HTSTE.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetHTSTE_CMDQEE(value uint32) {
	volatile.StoreUint32(&o.HTSTE.Reg, volatile.LoadUint32(&o.HTSTE.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetHTSTE_CMDQEE() uint32 {
	return (volatile.LoadUint32(&o.HTSTE.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetHTSTE_RSPQFE(value uint32) {
	volatile.StoreUint32(&o.HTSTE.Reg, volatile.LoadUint32(&o.HTSTE.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetHTSTE_RSPQFE() uint32 {
	return (volatile.LoadUint32(&o.HTSTE.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetHTSTE_TABTE(value uint32) {
	volatile.StoreUint32(&o.HTSTE.Reg, volatile.LoadUint32(&o.HTSTE.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetHTSTE_TABTE() uint32 {
	return (volatile.LoadUint32(&o.HTSTE.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetHTSTE_TEE(value uint32) {
	volatile.StoreUint32(&o.HTSTE.Reg, volatile.LoadUint32(&o.HTSTE.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetHTSTE_TEE() uint32 {
	return (volatile.LoadUint32(&o.HTSTE.Reg) & 0x200) >> 9
}

// I3C.HTIE: High Priority Transfer Interrupt Enable Register
func (o *I3C_Type) SetHTIE_TDBEIE(value uint32) {
	volatile.StoreUint32(&o.HTIE.Reg, volatile.LoadUint32(&o.HTIE.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetHTIE_TDBEIE() uint32 {
	return volatile.LoadUint32(&o.HTIE.Reg) & 0x1
}
func (o *I3C_Type) SetHTIE_RDBFIE(value uint32) {
	volatile.StoreUint32(&o.HTIE.Reg, volatile.LoadUint32(&o.HTIE.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetHTIE_RDBFIE() uint32 {
	return (volatile.LoadUint32(&o.HTIE.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetHTIE_CMDQEIE(value uint32) {
	volatile.StoreUint32(&o.HTIE.Reg, volatile.LoadUint32(&o.HTIE.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetHTIE_CMDQEIE() uint32 {
	return (volatile.LoadUint32(&o.HTIE.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetHTIE_RSPQFIE(value uint32) {
	volatile.StoreUint32(&o.HTIE.Reg, volatile.LoadUint32(&o.HTIE.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetHTIE_RSPQFIE() uint32 {
	return (volatile.LoadUint32(&o.HTIE.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetHTIE_TABTIE(value uint32) {
	volatile.StoreUint32(&o.HTIE.Reg, volatile.LoadUint32(&o.HTIE.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetHTIE_TABTIE() uint32 {
	return (volatile.LoadUint32(&o.HTIE.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetHTIE_TEIE(value uint32) {
	volatile.StoreUint32(&o.HTIE.Reg, volatile.LoadUint32(&o.HTIE.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetHTIE_TEIE() uint32 {
	return (volatile.LoadUint32(&o.HTIE.Reg) & 0x200) >> 9
}

// I3C.HTSTFC: High Priority Transfer Status Force Register
func (o *I3C_Type) SetHTSTFC_TDBEFC(value uint32) {
	volatile.StoreUint32(&o.HTSTFC.Reg, volatile.LoadUint32(&o.HTSTFC.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetHTSTFC_TDBEFC() uint32 {
	return volatile.LoadUint32(&o.HTSTFC.Reg) & 0x1
}
func (o *I3C_Type) SetHTSTFC_RDBFFC(value uint32) {
	volatile.StoreUint32(&o.HTSTFC.Reg, volatile.LoadUint32(&o.HTSTFC.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetHTSTFC_RDBFFC() uint32 {
	return (volatile.LoadUint32(&o.HTSTFC.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetHTSTFC_CMDQEFC(value uint32) {
	volatile.StoreUint32(&o.HTSTFC.Reg, volatile.LoadUint32(&o.HTSTFC.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetHTSTFC_CMDQEFC() uint32 {
	return (volatile.LoadUint32(&o.HTSTFC.Reg) & 0x8) >> 3
}
func (o *I3C_Type) SetHTSTFC_RSPQFFC(value uint32) {
	volatile.StoreUint32(&o.HTSTFC.Reg, volatile.LoadUint32(&o.HTSTFC.Reg)&^(0x10)|value<<4)
}
func (o *I3C_Type) GetHTSTFC_RSPQFFC() uint32 {
	return (volatile.LoadUint32(&o.HTSTFC.Reg) & 0x10) >> 4
}
func (o *I3C_Type) SetHTSTFC_TABTFC(value uint32) {
	volatile.StoreUint32(&o.HTSTFC.Reg, volatile.LoadUint32(&o.HTSTFC.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetHTSTFC_TABTFC() uint32 {
	return (volatile.LoadUint32(&o.HTSTFC.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetHTSTFC_TEFC(value uint32) {
	volatile.StoreUint32(&o.HTSTFC.Reg, volatile.LoadUint32(&o.HTSTFC.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetHTSTFC_TEFC() uint32 {
	return (volatile.LoadUint32(&o.HTSTFC.Reg) & 0x200) >> 9
}

// I3C.BCST: Bus Condition Status Register
func (o *I3C_Type) SetBCST_BFREF(value uint32) {
	volatile.StoreUint32(&o.BCST.Reg, volatile.LoadUint32(&o.BCST.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetBCST_BFREF() uint32 {
	return volatile.LoadUint32(&o.BCST.Reg) & 0x1
}
func (o *I3C_Type) SetBCST_BAVLF(value uint32) {
	volatile.StoreUint32(&o.BCST.Reg, volatile.LoadUint32(&o.BCST.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetBCST_BAVLF() uint32 {
	return (volatile.LoadUint32(&o.BCST.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetBCST_BIDLF(value uint32) {
	volatile.StoreUint32(&o.BCST.Reg, volatile.LoadUint32(&o.BCST.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetBCST_BIDLF() uint32 {
	return (volatile.LoadUint32(&o.BCST.Reg) & 0x4) >> 2
}

// I3C.SVST: Slave Status Register
func (o *I3C_Type) SetSVST_GCAF(value uint32) {
	volatile.StoreUint32(&o.SVST.Reg, volatile.LoadUint32(&o.SVST.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetSVST_GCAF() uint32 {
	return volatile.LoadUint32(&o.SVST.Reg) & 0x1
}
func (o *I3C_Type) SetSVST_HSMCF(value uint32) {
	volatile.StoreUint32(&o.SVST.Reg, volatile.LoadUint32(&o.SVST.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetSVST_HSMCF() uint32 {
	return (volatile.LoadUint32(&o.SVST.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetSVST_DVIDF(value uint32) {
	volatile.StoreUint32(&o.SVST.Reg, volatile.LoadUint32(&o.SVST.Reg)&^(0x40)|value<<6)
}
func (o *I3C_Type) GetSVST_DVIDF() uint32 {
	return (volatile.LoadUint32(&o.SVST.Reg) & 0x40) >> 6
}
func (o *I3C_Type) SetSVST_HOAF(value uint32) {
	volatile.StoreUint32(&o.SVST.Reg, volatile.LoadUint32(&o.SVST.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetSVST_HOAF() uint32 {
	return (volatile.LoadUint32(&o.SVST.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetSVST_SVAF(value uint32) {
	volatile.StoreUint32(&o.SVST.Reg, volatile.LoadUint32(&o.SVST.Reg)&^(0x70000)|value<<16)
}
func (o *I3C_Type) GetSVST_SVAF() uint32 {
	return (volatile.LoadUint32(&o.SVST.Reg) & 0x70000) >> 16
}

// I3C.WUST: Wake Up Unit Operating Status Register
func (o *I3C_Type) SetWUST_WUASYNF(value uint32) {
	volatile.StoreUint32(&o.WUST.Reg, volatile.LoadUint32(&o.WUST.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetWUST_WUASYNF() uint32 {
	return volatile.LoadUint32(&o.WUST.Reg) & 0x1
}

// I3C.DATBAS0: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS0_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS0_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS0.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS0_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS0_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS0.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS0_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS0_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS0.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS0_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS0_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS0.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS0_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS0_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS0.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS0_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS0_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS0.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS0_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS0_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS0.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS0_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS0.Reg, volatile.LoadUint32(&o.DATBAS0.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS0_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS0.Reg) & 0x80000000) >> 31
}

// I3C.DATBAS1: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS1_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS1_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS1.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS1_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS1_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS1.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS1_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS1_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS1.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS1_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS1_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS1.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS1_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS1_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS1.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS1_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS1_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS1.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS1_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS1_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS1.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS1_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS1.Reg, volatile.LoadUint32(&o.DATBAS1.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS1_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS1.Reg) & 0x80000000) >> 31
}

// I3C.DATBAS2: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS2_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS2_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS2.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS2_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS2_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS2.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS2_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS2_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS2.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS2_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS2_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS2.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS2_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS2_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS2.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS2_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS2_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS2.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS2_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS2_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS2.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS2_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS2.Reg, volatile.LoadUint32(&o.DATBAS2.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS2_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS2.Reg) & 0x80000000) >> 31
}

// I3C.DATBAS3: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS3_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS3_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS3.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS3_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS3_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS3.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS3_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS3_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS3.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS3_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS3_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS3.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS3_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS3_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS3.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS3_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS3_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS3.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS3_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS3_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS3.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS3_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS3.Reg, volatile.LoadUint32(&o.DATBAS3.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS3_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS3.Reg) & 0x80000000) >> 31
}

// I3C.DATBAS4: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS4_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS4_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS4.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS4_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS4_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS4.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS4_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS4_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS4.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS4_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS4_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS4.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS4_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS4_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS4.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS4_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS4_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS4.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS4_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS4_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS4.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS4_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS4.Reg, volatile.LoadUint32(&o.DATBAS4.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS4_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS4.Reg) & 0x80000000) >> 31
}

// I3C.DATBAS5: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS5_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS5_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS5.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS5_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS5_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS5.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS5_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS5_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS5.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS5_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS5_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS5.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS5_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS5_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS5.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS5_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS5_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS5.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS5_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS5_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS5.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS5_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS5.Reg, volatile.LoadUint32(&o.DATBAS5.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS5_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS5.Reg) & 0x80000000) >> 31
}

// I3C.DATBAS6: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS6_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS6_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS6.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS6_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS6_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS6.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS6_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS6_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS6.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS6_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS6_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS6.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS6_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS6_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS6.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS6_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS6_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS6.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS6_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS6_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS6.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS6_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS6.Reg, volatile.LoadUint32(&o.DATBAS6.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS6_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS6.Reg) & 0x80000000) >> 31
}

// I3C.DATBAS7: Device Address Table Basic Register %s
func (o *I3C_Type) SetDATBAS7_DVSTAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetDATBAS7_DVSTAD() uint32 {
	return volatile.LoadUint32(&o.DATBAS7.Reg) & 0x7f
}
func (o *I3C_Type) SetDATBAS7_DVIBIPL(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetDATBAS7_DVIBIPL() uint32 {
	return (volatile.LoadUint32(&o.DATBAS7.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetDATBAS7_DVSIRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0x2000)|value<<13)
}
func (o *I3C_Type) GetDATBAS7_DVSIRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS7.Reg) & 0x2000) >> 13
}
func (o *I3C_Type) SetDATBAS7_DVMRRJ(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0x4000)|value<<14)
}
func (o *I3C_Type) GetDATBAS7_DVMRRJ() uint32 {
	return (volatile.LoadUint32(&o.DATBAS7.Reg) & 0x4000) >> 14
}
func (o *I3C_Type) SetDATBAS7_DVIBITS(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0x8000)|value<<15)
}
func (o *I3C_Type) GetDATBAS7_DVIBITS() uint32 {
	return (volatile.LoadUint32(&o.DATBAS7.Reg) & 0x8000) >> 15
}
func (o *I3C_Type) SetDATBAS7_DVDYAD(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetDATBAS7_DVDYAD() uint32 {
	return (volatile.LoadUint32(&o.DATBAS7.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetDATBAS7_DVNACK(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetDATBAS7_DVNACK() uint32 {
	return (volatile.LoadUint32(&o.DATBAS7.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetDATBAS7_DVTYP(value uint32) {
	volatile.StoreUint32(&o.DATBAS7.Reg, volatile.LoadUint32(&o.DATBAS7.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetDATBAS7_DVTYP() uint32 {
	return (volatile.LoadUint32(&o.DATBAS7.Reg) & 0x80000000) >> 31
}

// I3C.EXDATBAS: Extended Device Address Table Basic Register
func (o *I3C_Type) SetEXDATBAS_EDSTAD(value uint32) {
	volatile.StoreUint32(&o.EXDATBAS.Reg, volatile.LoadUint32(&o.EXDATBAS.Reg)&^(0x7f)|value)
}
func (o *I3C_Type) GetEXDATBAS_EDSTAD() uint32 {
	return volatile.LoadUint32(&o.EXDATBAS.Reg) & 0x7f
}
func (o *I3C_Type) SetEXDATBAS_EDDYAD(value uint32) {
	volatile.StoreUint32(&o.EXDATBAS.Reg, volatile.LoadUint32(&o.EXDATBAS.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetEXDATBAS_EDDYAD() uint32 {
	return (volatile.LoadUint32(&o.EXDATBAS.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetEXDATBAS_EDNACK(value uint32) {
	volatile.StoreUint32(&o.EXDATBAS.Reg, volatile.LoadUint32(&o.EXDATBAS.Reg)&^(0x60000000)|value<<29)
}
func (o *I3C_Type) GetEXDATBAS_EDNACK() uint32 {
	return (volatile.LoadUint32(&o.EXDATBAS.Reg) & 0x60000000) >> 29
}
func (o *I3C_Type) SetEXDATBAS_EDTYP(value uint32) {
	volatile.StoreUint32(&o.EXDATBAS.Reg, volatile.LoadUint32(&o.EXDATBAS.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetEXDATBAS_EDTYP() uint32 {
	return (volatile.LoadUint32(&o.EXDATBAS.Reg) & 0x80000000) >> 31
}

// I3C.SDATBAS0: Slave Device Address Table Basic Register 0
func (o *I3C_Type) SetSDATBAS0_SDSTAD(value uint32) {
	volatile.StoreUint32(&o.SDATBAS0.Reg, volatile.LoadUint32(&o.SDATBAS0.Reg)&^(0x3ff)|value)
}
func (o *I3C_Type) GetSDATBAS0_SDSTAD() uint32 {
	return volatile.LoadUint32(&o.SDATBAS0.Reg) & 0x3ff
}
func (o *I3C_Type) SetSDATBAS0_SDADLS(value uint32) {
	volatile.StoreUint32(&o.SDATBAS0.Reg, volatile.LoadUint32(&o.SDATBAS0.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetSDATBAS0_SDADLS() uint32 {
	return (volatile.LoadUint32(&o.SDATBAS0.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetSDATBAS0_SDIBIPL(value uint32) {
	volatile.StoreUint32(&o.SDATBAS0.Reg, volatile.LoadUint32(&o.SDATBAS0.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetSDATBAS0_SDIBIPL() uint32 {
	return (volatile.LoadUint32(&o.SDATBAS0.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetSDATBAS0_SDDYAD(value uint32) {
	volatile.StoreUint32(&o.SDATBAS0.Reg, volatile.LoadUint32(&o.SDATBAS0.Reg)&^(0x7f0000)|value<<16)
}
func (o *I3C_Type) GetSDATBAS0_SDDYAD() uint32 {
	return (volatile.LoadUint32(&o.SDATBAS0.Reg) & 0x7f0000) >> 16
}

// I3C.MSDCT0: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT0_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT0.Reg, volatile.LoadUint32(&o.MSDCT0.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT0_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT0.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT0_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT0.Reg, volatile.LoadUint32(&o.MSDCT0.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT0_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT0.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT0_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT0.Reg, volatile.LoadUint32(&o.MSDCT0.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT0_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT0.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT0_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT0.Reg, volatile.LoadUint32(&o.MSDCT0.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT0_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT0.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT0_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT0.Reg, volatile.LoadUint32(&o.MSDCT0.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT0_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT0.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT0_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT0.Reg, volatile.LoadUint32(&o.MSDCT0.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT0_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT0.Reg) & 0xc000) >> 14
}

// I3C.MSDCT1: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT1_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT1.Reg, volatile.LoadUint32(&o.MSDCT1.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT1_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT1.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT1_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT1.Reg, volatile.LoadUint32(&o.MSDCT1.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT1_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT1.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT1_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT1.Reg, volatile.LoadUint32(&o.MSDCT1.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT1_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT1.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT1_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT1.Reg, volatile.LoadUint32(&o.MSDCT1.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT1_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT1.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT1_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT1.Reg, volatile.LoadUint32(&o.MSDCT1.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT1_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT1.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT1_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT1.Reg, volatile.LoadUint32(&o.MSDCT1.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT1_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT1.Reg) & 0xc000) >> 14
}

// I3C.MSDCT2: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT2_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT2.Reg, volatile.LoadUint32(&o.MSDCT2.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT2_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT2.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT2_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT2.Reg, volatile.LoadUint32(&o.MSDCT2.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT2_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT2.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT2_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT2.Reg, volatile.LoadUint32(&o.MSDCT2.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT2_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT2.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT2_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT2.Reg, volatile.LoadUint32(&o.MSDCT2.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT2_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT2.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT2_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT2.Reg, volatile.LoadUint32(&o.MSDCT2.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT2_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT2.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT2_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT2.Reg, volatile.LoadUint32(&o.MSDCT2.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT2_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT2.Reg) & 0xc000) >> 14
}

// I3C.MSDCT3: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT3_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT3.Reg, volatile.LoadUint32(&o.MSDCT3.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT3_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT3.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT3_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT3.Reg, volatile.LoadUint32(&o.MSDCT3.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT3_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT3.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT3_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT3.Reg, volatile.LoadUint32(&o.MSDCT3.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT3_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT3.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT3_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT3.Reg, volatile.LoadUint32(&o.MSDCT3.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT3_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT3.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT3_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT3.Reg, volatile.LoadUint32(&o.MSDCT3.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT3_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT3.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT3_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT3.Reg, volatile.LoadUint32(&o.MSDCT3.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT3_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT3.Reg) & 0xc000) >> 14
}

// I3C.MSDCT4: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT4_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT4.Reg, volatile.LoadUint32(&o.MSDCT4.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT4_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT4.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT4_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT4.Reg, volatile.LoadUint32(&o.MSDCT4.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT4_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT4.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT4_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT4.Reg, volatile.LoadUint32(&o.MSDCT4.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT4_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT4.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT4_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT4.Reg, volatile.LoadUint32(&o.MSDCT4.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT4_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT4.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT4_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT4.Reg, volatile.LoadUint32(&o.MSDCT4.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT4_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT4.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT4_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT4.Reg, volatile.LoadUint32(&o.MSDCT4.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT4_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT4.Reg) & 0xc000) >> 14
}

// I3C.MSDCT5: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT5_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT5.Reg, volatile.LoadUint32(&o.MSDCT5.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT5_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT5.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT5_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT5.Reg, volatile.LoadUint32(&o.MSDCT5.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT5_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT5.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT5_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT5.Reg, volatile.LoadUint32(&o.MSDCT5.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT5_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT5.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT5_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT5.Reg, volatile.LoadUint32(&o.MSDCT5.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT5_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT5.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT5_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT5.Reg, volatile.LoadUint32(&o.MSDCT5.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT5_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT5.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT5_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT5.Reg, volatile.LoadUint32(&o.MSDCT5.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT5_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT5.Reg) & 0xc000) >> 14
}

// I3C.MSDCT6: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT6_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT6.Reg, volatile.LoadUint32(&o.MSDCT6.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT6_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT6.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT6_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT6.Reg, volatile.LoadUint32(&o.MSDCT6.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT6_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT6.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT6_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT6.Reg, volatile.LoadUint32(&o.MSDCT6.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT6_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT6.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT6_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT6.Reg, volatile.LoadUint32(&o.MSDCT6.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT6_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT6.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT6_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT6.Reg, volatile.LoadUint32(&o.MSDCT6.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT6_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT6.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT6_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT6.Reg, volatile.LoadUint32(&o.MSDCT6.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT6_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT6.Reg) & 0xc000) >> 14
}

// I3C.MSDCT7: Master Device Characteristic Table Register %s
func (o *I3C_Type) SetMSDCT7_RBCR0(value uint32) {
	volatile.StoreUint32(&o.MSDCT7.Reg, volatile.LoadUint32(&o.MSDCT7.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetMSDCT7_RBCR0() uint32 {
	return (volatile.LoadUint32(&o.MSDCT7.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetMSDCT7_RBCR1(value uint32) {
	volatile.StoreUint32(&o.MSDCT7.Reg, volatile.LoadUint32(&o.MSDCT7.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetMSDCT7_RBCR1() uint32 {
	return (volatile.LoadUint32(&o.MSDCT7.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetMSDCT7_RBCR2(value uint32) {
	volatile.StoreUint32(&o.MSDCT7.Reg, volatile.LoadUint32(&o.MSDCT7.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetMSDCT7_RBCR2() uint32 {
	return (volatile.LoadUint32(&o.MSDCT7.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetMSDCT7_RBCR3(value uint32) {
	volatile.StoreUint32(&o.MSDCT7.Reg, volatile.LoadUint32(&o.MSDCT7.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetMSDCT7_RBCR3() uint32 {
	return (volatile.LoadUint32(&o.MSDCT7.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetMSDCT7_RBCR4(value uint32) {
	volatile.StoreUint32(&o.MSDCT7.Reg, volatile.LoadUint32(&o.MSDCT7.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetMSDCT7_RBCR4() uint32 {
	return (volatile.LoadUint32(&o.MSDCT7.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetMSDCT7_RBCR76(value uint32) {
	volatile.StoreUint32(&o.MSDCT7.Reg, volatile.LoadUint32(&o.MSDCT7.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetMSDCT7_RBCR76() uint32 {
	return (volatile.LoadUint32(&o.MSDCT7.Reg) & 0xc000) >> 14
}

// I3C.SVDCT: Slave Device Characteristic Table Register
func (o *I3C_Type) SetSVDCT_TDCR(value uint32) {
	volatile.StoreUint32(&o.SVDCT.Reg, volatile.LoadUint32(&o.SVDCT.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetSVDCT_TDCR() uint32 {
	return volatile.LoadUint32(&o.SVDCT.Reg) & 0xff
}
func (o *I3C_Type) SetSVDCT_TBCR0(value uint32) {
	volatile.StoreUint32(&o.SVDCT.Reg, volatile.LoadUint32(&o.SVDCT.Reg)&^(0x100)|value<<8)
}
func (o *I3C_Type) GetSVDCT_TBCR0() uint32 {
	return (volatile.LoadUint32(&o.SVDCT.Reg) & 0x100) >> 8
}
func (o *I3C_Type) SetSVDCT_TBCR1(value uint32) {
	volatile.StoreUint32(&o.SVDCT.Reg, volatile.LoadUint32(&o.SVDCT.Reg)&^(0x200)|value<<9)
}
func (o *I3C_Type) GetSVDCT_TBCR1() uint32 {
	return (volatile.LoadUint32(&o.SVDCT.Reg) & 0x200) >> 9
}
func (o *I3C_Type) SetSVDCT_TBCR2(value uint32) {
	volatile.StoreUint32(&o.SVDCT.Reg, volatile.LoadUint32(&o.SVDCT.Reg)&^(0x400)|value<<10)
}
func (o *I3C_Type) GetSVDCT_TBCR2() uint32 {
	return (volatile.LoadUint32(&o.SVDCT.Reg) & 0x400) >> 10
}
func (o *I3C_Type) SetSVDCT_TBCR3(value uint32) {
	volatile.StoreUint32(&o.SVDCT.Reg, volatile.LoadUint32(&o.SVDCT.Reg)&^(0x800)|value<<11)
}
func (o *I3C_Type) GetSVDCT_TBCR3() uint32 {
	return (volatile.LoadUint32(&o.SVDCT.Reg) & 0x800) >> 11
}
func (o *I3C_Type) SetSVDCT_TBCR4(value uint32) {
	volatile.StoreUint32(&o.SVDCT.Reg, volatile.LoadUint32(&o.SVDCT.Reg)&^(0x1000)|value<<12)
}
func (o *I3C_Type) GetSVDCT_TBCR4() uint32 {
	return (volatile.LoadUint32(&o.SVDCT.Reg) & 0x1000) >> 12
}
func (o *I3C_Type) SetSVDCT_TBCR76(value uint32) {
	volatile.StoreUint32(&o.SVDCT.Reg, volatile.LoadUint32(&o.SVDCT.Reg)&^(0xc000)|value<<14)
}
func (o *I3C_Type) GetSVDCT_TBCR76() uint32 {
	return (volatile.LoadUint32(&o.SVDCT.Reg) & 0xc000) >> 14
}

// I3C.SVDVAD0: Slave Device Address Register %s
func (o *I3C_Type) SetSVDVAD0_SVAD(value uint32) {
	volatile.StoreUint32(&o.SVDVAD0.Reg, volatile.LoadUint32(&o.SVDVAD0.Reg)&^(0x3ff0000)|value<<16)
}
func (o *I3C_Type) GetSVDVAD0_SVAD() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD0.Reg) & 0x3ff0000) >> 16
}
func (o *I3C_Type) SetSVDVAD0_SADLG(value uint32) {
	volatile.StoreUint32(&o.SVDVAD0.Reg, volatile.LoadUint32(&o.SVDVAD0.Reg)&^(0x8000000)|value<<27)
}
func (o *I3C_Type) GetSVDVAD0_SADLG() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD0.Reg) & 0x8000000) >> 27
}
func (o *I3C_Type) SetSVDVAD0_SSTADV(value uint32) {
	volatile.StoreUint32(&o.SVDVAD0.Reg, volatile.LoadUint32(&o.SVDVAD0.Reg)&^(0x40000000)|value<<30)
}
func (o *I3C_Type) GetSVDVAD0_SSTADV() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD0.Reg) & 0x40000000) >> 30
}
func (o *I3C_Type) SetSVDVAD0_SDYADV(value uint32) {
	volatile.StoreUint32(&o.SVDVAD0.Reg, volatile.LoadUint32(&o.SVDVAD0.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetSVDVAD0_SDYADV() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD0.Reg) & 0x80000000) >> 31
}

// I3C.SVDVAD1: Slave Device Address Register %s
func (o *I3C_Type) SetSVDVAD1_SVAD(value uint32) {
	volatile.StoreUint32(&o.SVDVAD1.Reg, volatile.LoadUint32(&o.SVDVAD1.Reg)&^(0x3ff0000)|value<<16)
}
func (o *I3C_Type) GetSVDVAD1_SVAD() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD1.Reg) & 0x3ff0000) >> 16
}
func (o *I3C_Type) SetSVDVAD1_SADLG(value uint32) {
	volatile.StoreUint32(&o.SVDVAD1.Reg, volatile.LoadUint32(&o.SVDVAD1.Reg)&^(0x8000000)|value<<27)
}
func (o *I3C_Type) GetSVDVAD1_SADLG() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD1.Reg) & 0x8000000) >> 27
}
func (o *I3C_Type) SetSVDVAD1_SSTADV(value uint32) {
	volatile.StoreUint32(&o.SVDVAD1.Reg, volatile.LoadUint32(&o.SVDVAD1.Reg)&^(0x40000000)|value<<30)
}
func (o *I3C_Type) GetSVDVAD1_SSTADV() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD1.Reg) & 0x40000000) >> 30
}
func (o *I3C_Type) SetSVDVAD1_SDYADV(value uint32) {
	volatile.StoreUint32(&o.SVDVAD1.Reg, volatile.LoadUint32(&o.SVDVAD1.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetSVDVAD1_SDYADV() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD1.Reg) & 0x80000000) >> 31
}

// I3C.SVDVAD2: Slave Device Address Register %s
func (o *I3C_Type) SetSVDVAD2_SVAD(value uint32) {
	volatile.StoreUint32(&o.SVDVAD2.Reg, volatile.LoadUint32(&o.SVDVAD2.Reg)&^(0x3ff0000)|value<<16)
}
func (o *I3C_Type) GetSVDVAD2_SVAD() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD2.Reg) & 0x3ff0000) >> 16
}
func (o *I3C_Type) SetSVDVAD2_SADLG(value uint32) {
	volatile.StoreUint32(&o.SVDVAD2.Reg, volatile.LoadUint32(&o.SVDVAD2.Reg)&^(0x8000000)|value<<27)
}
func (o *I3C_Type) GetSVDVAD2_SADLG() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD2.Reg) & 0x8000000) >> 27
}
func (o *I3C_Type) SetSVDVAD2_SSTADV(value uint32) {
	volatile.StoreUint32(&o.SVDVAD2.Reg, volatile.LoadUint32(&o.SVDVAD2.Reg)&^(0x40000000)|value<<30)
}
func (o *I3C_Type) GetSVDVAD2_SSTADV() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD2.Reg) & 0x40000000) >> 30
}
func (o *I3C_Type) SetSVDVAD2_SDYADV(value uint32) {
	volatile.StoreUint32(&o.SVDVAD2.Reg, volatile.LoadUint32(&o.SVDVAD2.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetSVDVAD2_SDYADV() uint32 {
	return (volatile.LoadUint32(&o.SVDVAD2.Reg) & 0x80000000) >> 31
}

// I3C.CSECMD: CCC Slave Events Command Register
func (o *I3C_Type) SetCSECMD_SVIRQE(value uint32) {
	volatile.StoreUint32(&o.CSECMD.Reg, volatile.LoadUint32(&o.CSECMD.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetCSECMD_SVIRQE() uint32 {
	return volatile.LoadUint32(&o.CSECMD.Reg) & 0x1
}
func (o *I3C_Type) SetCSECMD_MSRQE(value uint32) {
	volatile.StoreUint32(&o.CSECMD.Reg, volatile.LoadUint32(&o.CSECMD.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetCSECMD_MSRQE() uint32 {
	return (volatile.LoadUint32(&o.CSECMD.Reg) & 0x2) >> 1
}

// I3C.CEACTST: CCC Enter Activity State Register
func (o *I3C_Type) SetCEACTST_ACTST(value uint32) {
	volatile.StoreUint32(&o.CEACTST.Reg, volatile.LoadUint32(&o.CEACTST.Reg)&^(0xf)|value)
}
func (o *I3C_Type) GetCEACTST_ACTST() uint32 {
	return volatile.LoadUint32(&o.CEACTST.Reg) & 0xf
}

// I3C.CMWLG: CCC Max Write Length Register
func (o *I3C_Type) SetCMWLG_MWLG(value uint32) {
	volatile.StoreUint32(&o.CMWLG.Reg, volatile.LoadUint32(&o.CMWLG.Reg)&^(0xffff)|value)
}
func (o *I3C_Type) GetCMWLG_MWLG() uint32 {
	return volatile.LoadUint32(&o.CMWLG.Reg) & 0xffff
}

// I3C.CMRLG: CCC Max Read Length Register
func (o *I3C_Type) SetCMRLG_MRLG(value uint32) {
	volatile.StoreUint32(&o.CMRLG.Reg, volatile.LoadUint32(&o.CMRLG.Reg)&^(0xffff)|value)
}
func (o *I3C_Type) GetCMRLG_MRLG() uint32 {
	return volatile.LoadUint32(&o.CMRLG.Reg) & 0xffff
}
func (o *I3C_Type) SetCMRLG_IBIPSZ(value uint32) {
	volatile.StoreUint32(&o.CMRLG.Reg, volatile.LoadUint32(&o.CMRLG.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetCMRLG_IBIPSZ() uint32 {
	return (volatile.LoadUint32(&o.CMRLG.Reg) & 0xff0000) >> 16
}

// I3C.CETSTMD: CCC Enter Test Mode Register
func (o *I3C_Type) SetCETSTMD_TSTMD(value uint32) {
	volatile.StoreUint32(&o.CETSTMD.Reg, volatile.LoadUint32(&o.CETSTMD.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetCETSTMD_TSTMD() uint32 {
	return volatile.LoadUint32(&o.CETSTMD.Reg) & 0xff
}

// I3C.CGDVST: CCC Get Device Status Register
func (o *I3C_Type) SetCGDVST_PNDINT(value uint32) {
	volatile.StoreUint32(&o.CGDVST.Reg, volatile.LoadUint32(&o.CGDVST.Reg)&^(0xf)|value)
}
func (o *I3C_Type) GetCGDVST_PNDINT() uint32 {
	return volatile.LoadUint32(&o.CGDVST.Reg) & 0xf
}
func (o *I3C_Type) SetCGDVST_PRTE(value uint32) {
	volatile.StoreUint32(&o.CGDVST.Reg, volatile.LoadUint32(&o.CGDVST.Reg)&^(0x20)|value<<5)
}
func (o *I3C_Type) GetCGDVST_PRTE() uint32 {
	return (volatile.LoadUint32(&o.CGDVST.Reg) & 0x20) >> 5
}
func (o *I3C_Type) SetCGDVST_ACTMD(value uint32) {
	volatile.StoreUint32(&o.CGDVST.Reg, volatile.LoadUint32(&o.CGDVST.Reg)&^(0xc0)|value<<6)
}
func (o *I3C_Type) GetCGDVST_ACTMD() uint32 {
	return (volatile.LoadUint32(&o.CGDVST.Reg) & 0xc0) >> 6
}
func (o *I3C_Type) SetCGDVST_VDRSV(value uint32) {
	volatile.StoreUint32(&o.CGDVST.Reg, volatile.LoadUint32(&o.CGDVST.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetCGDVST_VDRSV() uint32 {
	return (volatile.LoadUint32(&o.CGDVST.Reg) & 0xff00) >> 8
}

// I3C.CMDSPW: CCC Max Data Speed W (Write) Register
func (o *I3C_Type) SetCMDSPW_MSWDR(value uint32) {
	volatile.StoreUint32(&o.CMDSPW.Reg, volatile.LoadUint32(&o.CMDSPW.Reg)&^(0x7)|value)
}
func (o *I3C_Type) GetCMDSPW_MSWDR() uint32 {
	return volatile.LoadUint32(&o.CMDSPW.Reg) & 0x7
}

// I3C.CMDSPR: CCC Max Data Speed R (Read) Register
func (o *I3C_Type) SetCMDSPR_MSRDR(value uint32) {
	volatile.StoreUint32(&o.CMDSPR.Reg, volatile.LoadUint32(&o.CMDSPR.Reg)&^(0x7)|value)
}
func (o *I3C_Type) GetCMDSPR_MSRDR() uint32 {
	return volatile.LoadUint32(&o.CMDSPR.Reg) & 0x7
}
func (o *I3C_Type) SetCMDSPR_CDTTIM(value uint32) {
	volatile.StoreUint32(&o.CMDSPR.Reg, volatile.LoadUint32(&o.CMDSPR.Reg)&^(0x38)|value<<3)
}
func (o *I3C_Type) GetCMDSPR_CDTTIM() uint32 {
	return (volatile.LoadUint32(&o.CMDSPR.Reg) & 0x38) >> 3
}

// I3C.CMDSPT: CCC Max Data Speed T (Turnaround) Register
func (o *I3C_Type) SetCMDSPT_MRTTIM(value uint32) {
	volatile.StoreUint32(&o.CMDSPT.Reg, volatile.LoadUint32(&o.CMDSPT.Reg)&^(0xffffff)|value)
}
func (o *I3C_Type) GetCMDSPT_MRTTIM() uint32 {
	return volatile.LoadUint32(&o.CMDSPT.Reg) & 0xffffff
}
func (o *I3C_Type) SetCMDSPT_MRTE(value uint32) {
	volatile.StoreUint32(&o.CMDSPT.Reg, volatile.LoadUint32(&o.CMDSPT.Reg)&^(0x80000000)|value<<31)
}
func (o *I3C_Type) GetCMDSPT_MRTE() uint32 {
	return (volatile.LoadUint32(&o.CMDSPT.Reg) & 0x80000000) >> 31
}

// I3C.CETSM: CCC Exchange Timing Support Information M (Mode) Register
func (o *I3C_Type) SetCETSM_SPTSYN(value uint32) {
	volatile.StoreUint32(&o.CETSM.Reg, volatile.LoadUint32(&o.CETSM.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetCETSM_SPTSYN() uint32 {
	return volatile.LoadUint32(&o.CETSM.Reg) & 0x1
}
func (o *I3C_Type) SetCETSM_SPTASYN0(value uint32) {
	volatile.StoreUint32(&o.CETSM.Reg, volatile.LoadUint32(&o.CETSM.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetCETSM_SPTASYN0() uint32 {
	return (volatile.LoadUint32(&o.CETSM.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetCETSM_SPTASYN1(value uint32) {
	volatile.StoreUint32(&o.CETSM.Reg, volatile.LoadUint32(&o.CETSM.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetCETSM_SPTASYN1() uint32 {
	return (volatile.LoadUint32(&o.CETSM.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetCETSM_FREQ(value uint32) {
	volatile.StoreUint32(&o.CETSM.Reg, volatile.LoadUint32(&o.CETSM.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetCETSM_FREQ() uint32 {
	return (volatile.LoadUint32(&o.CETSM.Reg) & 0xff00) >> 8
}
func (o *I3C_Type) SetCETSM_INAC(value uint32) {
	volatile.StoreUint32(&o.CETSM.Reg, volatile.LoadUint32(&o.CETSM.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetCETSM_INAC() uint32 {
	return (volatile.LoadUint32(&o.CETSM.Reg) & 0xff0000) >> 16
}

// I3C.CETSS: CCC Exchange Timing Support Information S (State) Register
func (o *I3C_Type) SetCETSS_SYNE(value uint32) {
	volatile.StoreUint32(&o.CETSS.Reg, volatile.LoadUint32(&o.CETSS.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetCETSS_SYNE() uint32 {
	return volatile.LoadUint32(&o.CETSS.Reg) & 0x1
}
func (o *I3C_Type) SetCETSS_ASYNE(value uint32) {
	volatile.StoreUint32(&o.CETSS.Reg, volatile.LoadUint32(&o.CETSS.Reg)&^(0x6)|value<<1)
}
func (o *I3C_Type) GetCETSS_ASYNE() uint32 {
	return (volatile.LoadUint32(&o.CETSS.Reg) & 0x6) >> 1
}
func (o *I3C_Type) SetCETSS_ICOVF(value uint32) {
	volatile.StoreUint32(&o.CETSS.Reg, volatile.LoadUint32(&o.CETSS.Reg)&^(0x80)|value<<7)
}
func (o *I3C_Type) GetCETSS_ICOVF() uint32 {
	return (volatile.LoadUint32(&o.CETSS.Reg) & 0x80) >> 7
}

// I3C.BITCNT: Bit Count Register
func (o *I3C_Type) SetBITCNT_BCNT(value uint32) {
	volatile.StoreUint32(&o.BITCNT.Reg, volatile.LoadUint32(&o.BITCNT.Reg)&^(0x1f)|value)
}
func (o *I3C_Type) GetBITCNT_BCNT() uint32 {
	return volatile.LoadUint32(&o.BITCNT.Reg) & 0x1f
}

// I3C.NQSTLV: Normal Queue Status Level Register
func (o *I3C_Type) SetNQSTLV_CMDQFLV(value uint32) {
	volatile.StoreUint32(&o.NQSTLV.Reg, volatile.LoadUint32(&o.NQSTLV.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetNQSTLV_CMDQFLV() uint32 {
	return volatile.LoadUint32(&o.NQSTLV.Reg) & 0xff
}
func (o *I3C_Type) SetNQSTLV_RSPQLV(value uint32) {
	volatile.StoreUint32(&o.NQSTLV.Reg, volatile.LoadUint32(&o.NQSTLV.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetNQSTLV_RSPQLV() uint32 {
	return (volatile.LoadUint32(&o.NQSTLV.Reg) & 0xff00) >> 8
}
func (o *I3C_Type) SetNQSTLV_IBIQLV(value uint32) {
	volatile.StoreUint32(&o.NQSTLV.Reg, volatile.LoadUint32(&o.NQSTLV.Reg)&^(0xff0000)|value<<16)
}
func (o *I3C_Type) GetNQSTLV_IBIQLV() uint32 {
	return (volatile.LoadUint32(&o.NQSTLV.Reg) & 0xff0000) >> 16
}
func (o *I3C_Type) SetNQSTLV_IBISCNT(value uint32) {
	volatile.StoreUint32(&o.NQSTLV.Reg, volatile.LoadUint32(&o.NQSTLV.Reg)&^(0x1f000000)|value<<24)
}
func (o *I3C_Type) GetNQSTLV_IBISCNT() uint32 {
	return (volatile.LoadUint32(&o.NQSTLV.Reg) & 0x1f000000) >> 24
}

// I3C.NDBSTLV0: Normal Data Buffer Status Level Register 0
func (o *I3C_Type) SetNDBSTLV0_TDBFLV(value uint32) {
	volatile.StoreUint32(&o.NDBSTLV0.Reg, volatile.LoadUint32(&o.NDBSTLV0.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetNDBSTLV0_TDBFLV() uint32 {
	return volatile.LoadUint32(&o.NDBSTLV0.Reg) & 0xff
}
func (o *I3C_Type) SetNDBSTLV0_RDBLV(value uint32) {
	volatile.StoreUint32(&o.NDBSTLV0.Reg, volatile.LoadUint32(&o.NDBSTLV0.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetNDBSTLV0_RDBLV() uint32 {
	return (volatile.LoadUint32(&o.NDBSTLV0.Reg) & 0xff00) >> 8
}

// I3C.NRSQSTLV: Normal Receive Status Queue Status Level Register
func (o *I3C_Type) SetNRSQSTLV_RSQLV(value uint32) {
	volatile.StoreUint32(&o.NRSQSTLV.Reg, volatile.LoadUint32(&o.NRSQSTLV.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetNRSQSTLV_RSQLV() uint32 {
	return volatile.LoadUint32(&o.NRSQSTLV.Reg) & 0xff
}

// I3C.HQSTLV: High Priority Queue Status Level Register
func (o *I3C_Type) SetHQSTLV_CMDQLV(value uint32) {
	volatile.StoreUint32(&o.HQSTLV.Reg, volatile.LoadUint32(&o.HQSTLV.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetHQSTLV_CMDQLV() uint32 {
	return volatile.LoadUint32(&o.HQSTLV.Reg) & 0xff
}
func (o *I3C_Type) SetHQSTLV_RSPQLV(value uint32) {
	volatile.StoreUint32(&o.HQSTLV.Reg, volatile.LoadUint32(&o.HQSTLV.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetHQSTLV_RSPQLV() uint32 {
	return (volatile.LoadUint32(&o.HQSTLV.Reg) & 0xff00) >> 8
}

// I3C.HDBSTLV: High Priority Data Buffer Status Level Register
func (o *I3C_Type) SetHDBSTLV_TDBFLV(value uint32) {
	volatile.StoreUint32(&o.HDBSTLV.Reg, volatile.LoadUint32(&o.HDBSTLV.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetHDBSTLV_TDBFLV() uint32 {
	return volatile.LoadUint32(&o.HDBSTLV.Reg) & 0xff
}
func (o *I3C_Type) SetHDBSTLV_RDBLV(value uint32) {
	volatile.StoreUint32(&o.HDBSTLV.Reg, volatile.LoadUint32(&o.HDBSTLV.Reg)&^(0xff00)|value<<8)
}
func (o *I3C_Type) GetHDBSTLV_RDBLV() uint32 {
	return (volatile.LoadUint32(&o.HDBSTLV.Reg) & 0xff00) >> 8
}

// I3C.PRSTDBG: Present State Debug Register
func (o *I3C_Type) SetPRSTDBG_SCILV(value uint32) {
	volatile.StoreUint32(&o.PRSTDBG.Reg, volatile.LoadUint32(&o.PRSTDBG.Reg)&^(0x1)|value)
}
func (o *I3C_Type) GetPRSTDBG_SCILV() uint32 {
	return volatile.LoadUint32(&o.PRSTDBG.Reg) & 0x1
}
func (o *I3C_Type) SetPRSTDBG_SDILV(value uint32) {
	volatile.StoreUint32(&o.PRSTDBG.Reg, volatile.LoadUint32(&o.PRSTDBG.Reg)&^(0x2)|value<<1)
}
func (o *I3C_Type) GetPRSTDBG_SDILV() uint32 {
	return (volatile.LoadUint32(&o.PRSTDBG.Reg) & 0x2) >> 1
}
func (o *I3C_Type) SetPRSTDBG_SCOLV(value uint32) {
	volatile.StoreUint32(&o.PRSTDBG.Reg, volatile.LoadUint32(&o.PRSTDBG.Reg)&^(0x4)|value<<2)
}
func (o *I3C_Type) GetPRSTDBG_SCOLV() uint32 {
	return (volatile.LoadUint32(&o.PRSTDBG.Reg) & 0x4) >> 2
}
func (o *I3C_Type) SetPRSTDBG_SDOLV(value uint32) {
	volatile.StoreUint32(&o.PRSTDBG.Reg, volatile.LoadUint32(&o.PRSTDBG.Reg)&^(0x8)|value<<3)
}
func (o *I3C_Type) GetPRSTDBG_SDOLV() uint32 {
	return (volatile.LoadUint32(&o.PRSTDBG.Reg) & 0x8) >> 3
}

// I3C.MSERRCNT: Master Error Counters Register
func (o *I3C_Type) SetMSERRCNT_M2ECNT(value uint32) {
	volatile.StoreUint32(&o.MSERRCNT.Reg, volatile.LoadUint32(&o.MSERRCNT.Reg)&^(0xff)|value)
}
func (o *I3C_Type) GetMSERRCNT_M2ECNT() uint32 {
	return volatile.LoadUint32(&o.MSERRCNT.Reg) & 0xff
}

// I3C.SC1CPT: SC1 Capture monitor Register
func (o *I3C_Type) SetSC1CPT_SC1C(value uint32) {
	volatile.StoreUint32(&o.SC1CPT.Reg, volatile.LoadUint32(&o.SC1CPT.Reg)&^(0xffff)|value)
}
func (o *I3C_Type) GetSC1CPT_SC1C() uint32 {
	return volatile.LoadUint32(&o.SC1CPT.Reg) & 0xffff
}

// I3C.SC2CPT: SC2 Capture monitor Register
func (o *I3C_Type) SetSC2CPT_SC2C(value uint32) {
	volatile.StoreUint32(&o.SC2CPT.Reg, volatile.LoadUint32(&o.SC2CPT.Reg)&^(0xffff)|value)
}
func (o *I3C_Type) GetSC2CPT_SC2C() uint32 {
	return volatile.LoadUint32(&o.SC2CPT.Reg) & 0xffff
}

// ECCMB
type ECCMB_Type struct {
	EC710CTL  volatile.Register32 // 0x0
	EC710TMC  volatile.Register16 // 0x4
	_         [6]byte
	EC710TED  volatile.Register32 // 0xC
	EC710EAD0 volatile.Register32 // 0x10
}

// ECCMB.EC710CTL: ECC Control Register
func (o *ECCMB_Type) SetEC710CTL_ECEMF(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x1)|value)
}
func (o *ECCMB_Type) GetEC710CTL_ECEMF() uint32 {
	return volatile.LoadUint32(&o.EC710CTL.Reg) & 0x1
}
func (o *ECCMB_Type) SetEC710CTL_ECER1F(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x2)|value<<1)
}
func (o *ECCMB_Type) GetEC710CTL_ECER1F() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x2) >> 1
}
func (o *ECCMB_Type) SetEC710CTL_ECER2F(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x4)|value<<2)
}
func (o *ECCMB_Type) GetEC710CTL_ECER2F() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x4) >> 2
}
func (o *ECCMB_Type) SetEC710CTL_EC1EDIC(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x8)|value<<3)
}
func (o *ECCMB_Type) GetEC710CTL_EC1EDIC() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x8) >> 3
}
func (o *ECCMB_Type) SetEC710CTL_EC2EDIC(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x10)|value<<4)
}
func (o *ECCMB_Type) GetEC710CTL_EC2EDIC() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x10) >> 4
}
func (o *ECCMB_Type) SetEC710CTL_EC1ECP(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x20)|value<<5)
}
func (o *ECCMB_Type) GetEC710CTL_EC1ECP() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x20) >> 5
}
func (o *ECCMB_Type) SetEC710CTL_ECERVF(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x40)|value<<6)
}
func (o *ECCMB_Type) GetEC710CTL_ECERVF() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x40) >> 6
}
func (o *ECCMB_Type) SetEC710CTL_ECER1C(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x200)|value<<9)
}
func (o *ECCMB_Type) GetEC710CTL_ECER1C() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x200) >> 9
}
func (o *ECCMB_Type) SetEC710CTL_ECER2C(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x400)|value<<10)
}
func (o *ECCMB_Type) GetEC710CTL_ECER2C() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x400) >> 10
}
func (o *ECCMB_Type) SetEC710CTL_ECOVFF(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x800)|value<<11)
}
func (o *ECCMB_Type) GetEC710CTL_ECOVFF() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x800) >> 11
}
func (o *ECCMB_Type) SetEC710CTL_EMCA(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0xc000)|value<<14)
}
func (o *ECCMB_Type) GetEC710CTL_EMCA() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0xc000) >> 14
}
func (o *ECCMB_Type) SetEC710CTL_ECSEDF0(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x10000)|value<<16)
}
func (o *ECCMB_Type) GetEC710CTL_ECSEDF0() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x10000) >> 16
}
func (o *ECCMB_Type) SetEC710CTL_ECDEDF0(value uint32) {
	volatile.StoreUint32(&o.EC710CTL.Reg, volatile.LoadUint32(&o.EC710CTL.Reg)&^(0x20000)|value<<17)
}
func (o *ECCMB_Type) GetEC710CTL_ECDEDF0() uint32 {
	return (volatile.LoadUint32(&o.EC710CTL.Reg) & 0x20000) >> 17
}

// ECCMB.EC710TMC: ECC Test Mode Control Register
func (o *ECCMB_Type) SetEC710TMC_ECDCS(value uint16) {
	volatile.StoreUint16(&o.EC710TMC.Reg, volatile.LoadUint16(&o.EC710TMC.Reg)&^(0x2)|value<<1)
}
func (o *ECCMB_Type) GetEC710TMC_ECDCS() uint16 {
	return (volatile.LoadUint16(&o.EC710TMC.Reg) & 0x2) >> 1
}
func (o *ECCMB_Type) SetEC710TMC_ECTMCE(value uint16) {
	volatile.StoreUint16(&o.EC710TMC.Reg, volatile.LoadUint16(&o.EC710TMC.Reg)&^(0x80)|value<<7)
}
func (o *ECCMB_Type) GetEC710TMC_ECTMCE() uint16 {
	return (volatile.LoadUint16(&o.EC710TMC.Reg) & 0x80) >> 7
}
func (o *ECCMB_Type) SetEC710TMC_ETMA(value uint16) {
	volatile.StoreUint16(&o.EC710TMC.Reg, volatile.LoadUint16(&o.EC710TMC.Reg)&^(0xc000)|value<<14)
}
func (o *ECCMB_Type) GetEC710TMC_ETMA() uint16 {
	return (volatile.LoadUint16(&o.EC710TMC.Reg) & 0xc000) >> 14
}

// ECCMB.EC710TED: ECC Test Substitute Data Register
func (o *ECCMB_Type) SetEC710TED(value uint32) {
	volatile.StoreUint32(&o.EC710TED.Reg, value)
}
func (o *ECCMB_Type) GetEC710TED() uint32 {
	return volatile.LoadUint32(&o.EC710TED.Reg)
}

// ECCMB.EC710EAD0: ECC Error Address Register
func (o *ECCMB_Type) SetEC710EAD0_ECEAD(value uint32) {
	volatile.StoreUint32(&o.EC710EAD0.Reg, volatile.LoadUint32(&o.EC710EAD0.Reg)&^(0x7ff)|value)
}
func (o *ECCMB_Type) GetEC710EAD0_ECEAD() uint32 {
	return volatile.LoadUint32(&o.EC710EAD0.Reg) & 0x7ff
}

// General PWM 16-bit Timer 0
type GPT16E0_Type struct {
	GTWP      volatile.Register32 // 0x0
	GTSTR     volatile.Register32 // 0x4
	GTSTP     volatile.Register32 // 0x8
	GTCLR     volatile.Register32 // 0xC
	GTSSR     volatile.Register32 // 0x10
	GTPSR     volatile.Register32 // 0x14
	GTCSR     volatile.Register32 // 0x18
	GTUPSR    volatile.Register32 // 0x1C
	GTDNSR    volatile.Register32 // 0x20
	GTICASR   volatile.Register32 // 0x24
	GTICBSR   volatile.Register32 // 0x28
	GTCR      volatile.Register32 // 0x2C
	GTUDDTYC  volatile.Register32 // 0x30
	GTIOR     volatile.Register32 // 0x34
	GTINTAD   volatile.Register32 // 0x38
	GTST      volatile.Register32 // 0x3C
	GTBER     volatile.Register32 // 0x40
	GTITC     volatile.Register32 // 0x44
	GTCNT     volatile.Register32 // 0x48
	GTCCRA    volatile.Register32 // 0x4C
	GTCCRB    volatile.Register32 // 0x50
	GTCCRC    volatile.Register32 // 0x54
	GTCCRE    volatile.Register32 // 0x58
	GTCCRD    volatile.Register32 // 0x5C
	GTCCRF    volatile.Register32 // 0x60
	GTPR      volatile.Register32 // 0x64
	GTPBR     volatile.Register32 // 0x68
	GTPDBR    volatile.Register32 // 0x6C
	GTADTRA   volatile.Register32 // 0x70
	GTADTBRA  volatile.Register32 // 0x74
	GTADTDBRA volatile.Register32 // 0x78
	GTADTRB   volatile.Register32 // 0x7C
	GTADTBRB  volatile.Register32 // 0x80
	GTADTDBRB volatile.Register32 // 0x84
	GTDTCR    volatile.Register32 // 0x88
	GTDVU     volatile.Register32 // 0x8C
	GTDVD     volatile.Register32 // 0x90
	GTDBU     volatile.Register32 // 0x94
	GTDBD     volatile.Register32 // 0x98
	GTSOS     volatile.Register32 // 0x9C
	GTSOTR    volatile.Register32 // 0xA0
	GTADSMR   volatile.Register32 // 0xA4
	_         [16]byte
	GTICLF    volatile.Register32 // 0xB8
	GTPC      volatile.Register32 // 0xBC
	_         [16]byte
	GTSECSR   volatile.Register32 // 0xD0
	GTSECR    volatile.Register32 // 0xD4
}

// GPT16E0.GTWP: General PWM Timer Write-Protection Register
func (o *GPT16E0_Type) SetGTWP_WP(value uint32) {
	volatile.StoreUint32(&o.GTWP.Reg, volatile.LoadUint32(&o.GTWP.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTWP_WP() uint32 {
	return volatile.LoadUint32(&o.GTWP.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTWP_STRWP(value uint32) {
	volatile.StoreUint32(&o.GTWP.Reg, volatile.LoadUint32(&o.GTWP.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTWP_STRWP() uint32 {
	return (volatile.LoadUint32(&o.GTWP.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTWP_STPWP(value uint32) {
	volatile.StoreUint32(&o.GTWP.Reg, volatile.LoadUint32(&o.GTWP.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTWP_STPWP() uint32 {
	return (volatile.LoadUint32(&o.GTWP.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTWP_CLRWP(value uint32) {
	volatile.StoreUint32(&o.GTWP.Reg, volatile.LoadUint32(&o.GTWP.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTWP_CLRWP() uint32 {
	return (volatile.LoadUint32(&o.GTWP.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTWP_CMNWP(value uint32) {
	volatile.StoreUint32(&o.GTWP.Reg, volatile.LoadUint32(&o.GTWP.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTWP_CMNWP() uint32 {
	return (volatile.LoadUint32(&o.GTWP.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTWP_PRKEY(value uint32) {
	volatile.StoreUint32(&o.GTWP.Reg, volatile.LoadUint32(&o.GTWP.Reg)&^(0xff00)|value<<8)
}
func (o *GPT16E0_Type) GetGTWP_PRKEY() uint32 {
	return (volatile.LoadUint32(&o.GTWP.Reg) & 0xff00) >> 8
}

// GPT16E0.GTSTR: General PWM Timer Software Start Register
func (o *GPT16E0_Type) SetGTSTR_CSTRT0(value uint32) {
	volatile.StoreUint32(&o.GTSTR.Reg, volatile.LoadUint32(&o.GTSTR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTSTR_CSTRT0() uint32 {
	return volatile.LoadUint32(&o.GTSTR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTSTR_CSTRT1(value uint32) {
	volatile.StoreUint32(&o.GTSTR.Reg, volatile.LoadUint32(&o.GTSTR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTSTR_CSTRT1() uint32 {
	return (volatile.LoadUint32(&o.GTSTR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTSTR_CSTRT2(value uint32) {
	volatile.StoreUint32(&o.GTSTR.Reg, volatile.LoadUint32(&o.GTSTR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTSTR_CSTRT2() uint32 {
	return (volatile.LoadUint32(&o.GTSTR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTSTR_CSTRT3(value uint32) {
	volatile.StoreUint32(&o.GTSTR.Reg, volatile.LoadUint32(&o.GTSTR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTSTR_CSTRT3() uint32 {
	return (volatile.LoadUint32(&o.GTSTR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTSTR_CSTRT4(value uint32) {
	volatile.StoreUint32(&o.GTSTR.Reg, volatile.LoadUint32(&o.GTSTR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTSTR_CSTRT4() uint32 {
	return (volatile.LoadUint32(&o.GTSTR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTSTR_CSTRT5(value uint32) {
	volatile.StoreUint32(&o.GTSTR.Reg, volatile.LoadUint32(&o.GTSTR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTSTR_CSTRT5() uint32 {
	return (volatile.LoadUint32(&o.GTSTR.Reg) & 0x20) >> 5
}

// GPT16E0.GTSTP: General PWM Timer Software Stop Register
func (o *GPT16E0_Type) SetGTSTP_CSTOP0(value uint32) {
	volatile.StoreUint32(&o.GTSTP.Reg, volatile.LoadUint32(&o.GTSTP.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTSTP_CSTOP0() uint32 {
	return volatile.LoadUint32(&o.GTSTP.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTSTP_CSTOP1(value uint32) {
	volatile.StoreUint32(&o.GTSTP.Reg, volatile.LoadUint32(&o.GTSTP.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTSTP_CSTOP1() uint32 {
	return (volatile.LoadUint32(&o.GTSTP.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTSTP_CSTOP2(value uint32) {
	volatile.StoreUint32(&o.GTSTP.Reg, volatile.LoadUint32(&o.GTSTP.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTSTP_CSTOP2() uint32 {
	return (volatile.LoadUint32(&o.GTSTP.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTSTP_CSTOP3(value uint32) {
	volatile.StoreUint32(&o.GTSTP.Reg, volatile.LoadUint32(&o.GTSTP.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTSTP_CSTOP3() uint32 {
	return (volatile.LoadUint32(&o.GTSTP.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTSTP_CSTOP4(value uint32) {
	volatile.StoreUint32(&o.GTSTP.Reg, volatile.LoadUint32(&o.GTSTP.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTSTP_CSTOP4() uint32 {
	return (volatile.LoadUint32(&o.GTSTP.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTSTP_CSTOP5(value uint32) {
	volatile.StoreUint32(&o.GTSTP.Reg, volatile.LoadUint32(&o.GTSTP.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTSTP_CSTOP5() uint32 {
	return (volatile.LoadUint32(&o.GTSTP.Reg) & 0x20) >> 5
}

// GPT16E0.GTCLR: General PWM Timer Software Clear Register
func (o *GPT16E0_Type) SetGTCLR_CCLR0(value uint32) {
	volatile.StoreUint32(&o.GTCLR.Reg, volatile.LoadUint32(&o.GTCLR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTCLR_CCLR0() uint32 {
	return volatile.LoadUint32(&o.GTCLR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTCLR_CCLR1(value uint32) {
	volatile.StoreUint32(&o.GTCLR.Reg, volatile.LoadUint32(&o.GTCLR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTCLR_CCLR1() uint32 {
	return (volatile.LoadUint32(&o.GTCLR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTCLR_CCLR2(value uint32) {
	volatile.StoreUint32(&o.GTCLR.Reg, volatile.LoadUint32(&o.GTCLR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTCLR_CCLR2() uint32 {
	return (volatile.LoadUint32(&o.GTCLR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTCLR_CCLR3(value uint32) {
	volatile.StoreUint32(&o.GTCLR.Reg, volatile.LoadUint32(&o.GTCLR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTCLR_CCLR3() uint32 {
	return (volatile.LoadUint32(&o.GTCLR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTCLR_CCLR4(value uint32) {
	volatile.StoreUint32(&o.GTCLR.Reg, volatile.LoadUint32(&o.GTCLR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTCLR_CCLR4() uint32 {
	return (volatile.LoadUint32(&o.GTCLR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTCLR_CCLR5(value uint32) {
	volatile.StoreUint32(&o.GTCLR.Reg, volatile.LoadUint32(&o.GTCLR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTCLR_CCLR5() uint32 {
	return (volatile.LoadUint32(&o.GTCLR.Reg) & 0x20) >> 5
}

// GPT16E0.GTSSR: General PWM Timer Start Source Select Register
func (o *GPT16E0_Type) SetGTSSR_SSGTRGAR(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGAR() uint32 {
	return volatile.LoadUint32(&o.GTSSR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTSSR_SSGTRGAF(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGAF() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTSSR_SSGTRGBR(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGBR() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTSSR_SSGTRGBF(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGBF() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTSSR_SSGTRGCR(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGCR() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTSSR_SSGTRGCF(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGCF() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTSSR_SSGTRGDR(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGDR() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTSSR_SSGTRGDF(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTSSR_SSGTRGDF() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTSSR_SSCARBL(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTSSR_SSCARBL() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTSSR_SSCARBH(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTSSR_SSCARBH() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTSSR_SSCAFBL(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTSSR_SSCAFBL() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTSSR_SSCAFBH(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTSSR_SSCAFBH() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTSSR_SSCBRAL(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTSSR_SSCBRAL() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTSSR_SSCBRAH(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTSSR_SSCBRAH() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTSSR_SSCBFAL(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTSSR_SSCBFAL() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x4000) >> 14
}
func (o *GPT16E0_Type) SetGTSSR_SSCBFAH(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTSSR_SSCBFAH() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTSSR_SSELCA(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCA() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTSSR_SSELCB(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCB() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTSSR_SSELCC(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCC() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTSSR_SSELCD(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCD() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTSSR_SSELCE(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCE() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x100000) >> 20
}
func (o *GPT16E0_Type) SetGTSSR_SSELCF(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCF() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x200000) >> 21
}
func (o *GPT16E0_Type) SetGTSSR_SSELCG(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCG() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTSSR_SSELCH(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTSSR_SSELCH() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x800000) >> 23
}
func (o *GPT16E0_Type) SetGTSSR_CSTRT(value uint32) {
	volatile.StoreUint32(&o.GTSSR.Reg, volatile.LoadUint32(&o.GTSSR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPT16E0_Type) GetGTSSR_CSTRT() uint32 {
	return (volatile.LoadUint32(&o.GTSSR.Reg) & 0x80000000) >> 31
}

// GPT16E0.GTPSR: General PWM Timer Stop Source Select Register
func (o *GPT16E0_Type) SetGTPSR_PSGTRGAR(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGAR() uint32 {
	return volatile.LoadUint32(&o.GTPSR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTPSR_PSGTRGAF(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGAF() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTPSR_PSGTRGBR(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGBR() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTPSR_PSGTRGBF(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGBF() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTPSR_PSGTRGCR(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGCR() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTPSR_PSGTRGCF(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGCF() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTPSR_PSGTRGDR(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGDR() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTPSR_PSGTRGDF(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTPSR_PSGTRGDF() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTPSR_PSCARBL(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTPSR_PSCARBL() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTPSR_PSCARBH(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTPSR_PSCARBH() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTPSR_PSCAFBL(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTPSR_PSCAFBL() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTPSR_PSCAFBH(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTPSR_PSCAFBH() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTPSR_PSCBRAL(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTPSR_PSCBRAL() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTPSR_PSCBRAH(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTPSR_PSCBRAH() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTPSR_PSCBFAL(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTPSR_PSCBFAL() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x4000) >> 14
}
func (o *GPT16E0_Type) SetGTPSR_PSCBFAH(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTPSR_PSCBFAH() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTPSR_PSELCA(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCA() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTPSR_PSELCB(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCB() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTPSR_PSELCC(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCC() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTPSR_PSELCD(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCD() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTPSR_PSELCE(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCE() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x100000) >> 20
}
func (o *GPT16E0_Type) SetGTPSR_PSELCF(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCF() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x200000) >> 21
}
func (o *GPT16E0_Type) SetGTPSR_PSELCG(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCG() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTPSR_PSELCH(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTPSR_PSELCH() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x800000) >> 23
}
func (o *GPT16E0_Type) SetGTPSR_CSTOP(value uint32) {
	volatile.StoreUint32(&o.GTPSR.Reg, volatile.LoadUint32(&o.GTPSR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPT16E0_Type) GetGTPSR_CSTOP() uint32 {
	return (volatile.LoadUint32(&o.GTPSR.Reg) & 0x80000000) >> 31
}

// GPT16E0.GTCSR: General PWM Timer Clear Source Select Register
func (o *GPT16E0_Type) SetGTCSR_CSGTRGAR(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGAR() uint32 {
	return volatile.LoadUint32(&o.GTCSR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTCSR_CSGTRGAF(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGAF() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTCSR_CSGTRGBR(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGBR() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTCSR_CSGTRGBF(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGBF() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTCSR_CSGTRGCR(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGCR() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTCSR_CSGTRGCF(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGCF() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTCSR_CSGTRGDR(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGDR() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTCSR_CSGTRGDF(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTCSR_CSGTRGDF() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTCSR_CSCARBL(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTCSR_CSCARBL() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTCSR_CSCARBH(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTCSR_CSCARBH() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTCSR_CSCAFBL(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTCSR_CSCAFBL() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTCSR_CSCAFBH(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTCSR_CSCAFBH() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTCSR_CSCBRAL(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTCSR_CSCBRAL() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTCSR_CSCBRAH(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTCSR_CSCBRAH() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTCSR_CSCBFAL(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTCSR_CSCBFAL() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x4000) >> 14
}
func (o *GPT16E0_Type) SetGTCSR_CSCBFAH(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTCSR_CSCBFAH() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTCSR_CSELCA(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCA() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTCSR_CSELCB(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCB() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTCSR_CSELCC(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCC() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTCSR_CSELCD(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCD() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTCSR_CSELCE(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCE() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x100000) >> 20
}
func (o *GPT16E0_Type) SetGTCSR_CSELCF(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCF() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x200000) >> 21
}
func (o *GPT16E0_Type) SetGTCSR_CSELCG(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCG() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTCSR_CSELCH(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTCSR_CSELCH() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x800000) >> 23
}
func (o *GPT16E0_Type) SetGTCSR_CCLR(value uint32) {
	volatile.StoreUint32(&o.GTCSR.Reg, volatile.LoadUint32(&o.GTCSR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPT16E0_Type) GetGTCSR_CCLR() uint32 {
	return (volatile.LoadUint32(&o.GTCSR.Reg) & 0x80000000) >> 31
}

// GPT16E0.GTUPSR: General PWM Timer Up Count Source Select Register
func (o *GPT16E0_Type) SetGTUPSR_USGTRGAR(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGAR() uint32 {
	return volatile.LoadUint32(&o.GTUPSR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTUPSR_USGTRGAF(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGAF() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTUPSR_USGTRGBR(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGBR() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTUPSR_USGTRGBF(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGBF() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTUPSR_USGTRGCR(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGCR() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTUPSR_USGTRGCF(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGCF() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTUPSR_USGTRGDR(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGDR() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTUPSR_USGTRGDF(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTUPSR_USGTRGDF() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTUPSR_USCARBL(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTUPSR_USCARBL() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTUPSR_USCARBH(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTUPSR_USCARBH() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTUPSR_USCAFBL(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTUPSR_USCAFBL() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTUPSR_USCAFBH(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTUPSR_USCAFBH() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTUPSR_USCBRAL(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTUPSR_USCBRAL() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTUPSR_USCBRAH(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTUPSR_USCBRAH() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTUPSR_USCBFAL(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTUPSR_USCBFAL() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x4000) >> 14
}
func (o *GPT16E0_Type) SetGTUPSR_USCBFAH(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTUPSR_USCBFAH() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTUPSR_USELCA(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCA() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTUPSR_USELCB(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCB() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTUPSR_USELCC(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCC() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTUPSR_USELCD(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCD() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTUPSR_USELCE(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCE() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x100000) >> 20
}
func (o *GPT16E0_Type) SetGTUPSR_USELCF(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCF() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x200000) >> 21
}
func (o *GPT16E0_Type) SetGTUPSR_USELCG(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCG() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTUPSR_USELCH(value uint32) {
	volatile.StoreUint32(&o.GTUPSR.Reg, volatile.LoadUint32(&o.GTUPSR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTUPSR_USELCH() uint32 {
	return (volatile.LoadUint32(&o.GTUPSR.Reg) & 0x800000) >> 23
}

// GPT16E0.GTDNSR: General PWM Timer Down Count Source Select Register
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGAR(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGAR() uint32 {
	return volatile.LoadUint32(&o.GTDNSR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGAF(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGAF() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGBR(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGBR() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGBF(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGBF() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGCR(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGCR() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGCF(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGCF() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGDR(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGDR() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTDNSR_DSGTRGDF(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTDNSR_DSGTRGDF() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTDNSR_DSCARBL(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCARBL() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTDNSR_DSCARBH(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCARBH() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTDNSR_DSCAFBL(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCAFBL() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTDNSR_DSCAFBH(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCAFBH() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTDNSR_DSCBRAL(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCBRAL() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTDNSR_DSCBRAH(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCBRAH() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTDNSR_DSCBFAL(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCBFAL() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x4000) >> 14
}
func (o *GPT16E0_Type) SetGTDNSR_DSCBFAH(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTDNSR_DSCBFAH() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCA(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCA() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCB(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCB() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCC(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCC() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCD(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCD() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCE(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCE() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x100000) >> 20
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCF(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCF() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x200000) >> 21
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCG(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCG() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTDNSR_DSELCH(value uint32) {
	volatile.StoreUint32(&o.GTDNSR.Reg, volatile.LoadUint32(&o.GTDNSR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTDNSR_DSELCH() uint32 {
	return (volatile.LoadUint32(&o.GTDNSR.Reg) & 0x800000) >> 23
}

// GPT16E0.GTICASR: General PWM Timer Input Capture Source Select Register A
func (o *GPT16E0_Type) SetGTICASR_ASGTRGAR(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGAR() uint32 {
	return volatile.LoadUint32(&o.GTICASR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTICASR_ASGTRGAF(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGAF() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTICASR_ASGTRGBR(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGBR() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTICASR_ASGTRGBF(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGBF() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTICASR_ASGTRGCR(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGCR() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTICASR_ASGTRGCF(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGCF() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTICASR_ASGTRGDR(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGDR() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTICASR_ASGTRGDF(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTICASR_ASGTRGDF() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTICASR_ASCARBL(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTICASR_ASCARBL() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTICASR_ASCARBH(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTICASR_ASCARBH() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTICASR_ASCAFBL(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTICASR_ASCAFBL() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTICASR_ASCAFBH(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTICASR_ASCAFBH() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTICASR_ASCBRAL(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTICASR_ASCBRAL() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTICASR_ASCBRAH(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTICASR_ASCBRAH() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTICASR_ASCBFAL(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTICASR_ASCBFAL() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x4000) >> 14
}
func (o *GPT16E0_Type) SetGTICASR_ASCBFAH(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTICASR_ASCBFAH() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTICASR_ASELCA(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCA() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTICASR_ASELCB(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCB() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTICASR_ASELCC(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCC() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTICASR_ASELCD(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCD() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTICASR_ASELCE(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCE() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x100000) >> 20
}
func (o *GPT16E0_Type) SetGTICASR_ASELCF(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCF() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x200000) >> 21
}
func (o *GPT16E0_Type) SetGTICASR_ASELCG(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCG() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTICASR_ASELCH(value uint32) {
	volatile.StoreUint32(&o.GTICASR.Reg, volatile.LoadUint32(&o.GTICASR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTICASR_ASELCH() uint32 {
	return (volatile.LoadUint32(&o.GTICASR.Reg) & 0x800000) >> 23
}

// GPT16E0.GTICBSR: General PWM Timer Input Capture Source Select Register B
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGAR(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGAR() uint32 {
	return volatile.LoadUint32(&o.GTICBSR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGAF(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGAF() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGBR(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGBR() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGBF(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGBF() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGCR(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGCR() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGCF(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGCF() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGDR(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGDR() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTICBSR_BSGTRGDF(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTICBSR_BSGTRGDF() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTICBSR_BSCARBL(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCARBL() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTICBSR_BSCARBH(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCARBH() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTICBSR_BSCAFBL(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCAFBL() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTICBSR_BSCAFBH(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCAFBH() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTICBSR_BSCBRAL(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCBRAL() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTICBSR_BSCBRAH(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCBRAH() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTICBSR_BSCBFAL(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCBFAL() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x4000) >> 14
}
func (o *GPT16E0_Type) SetGTICBSR_BSCBFAH(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTICBSR_BSCBFAH() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCA(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCA() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCB(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCB() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCC(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCC() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCD(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCD() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCE(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCE() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x100000) >> 20
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCF(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCF() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x200000) >> 21
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCG(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCG() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTICBSR_BSELCH(value uint32) {
	volatile.StoreUint32(&o.GTICBSR.Reg, volatile.LoadUint32(&o.GTICBSR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTICBSR_BSELCH() uint32 {
	return (volatile.LoadUint32(&o.GTICBSR.Reg) & 0x800000) >> 23
}

// GPT16E0.GTCR: General PWM Timer Control Register
func (o *GPT16E0_Type) SetGTCR_CST(value uint32) {
	volatile.StoreUint32(&o.GTCR.Reg, volatile.LoadUint32(&o.GTCR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTCR_CST() uint32 {
	return volatile.LoadUint32(&o.GTCR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTCR_MD(value uint32) {
	volatile.StoreUint32(&o.GTCR.Reg, volatile.LoadUint32(&o.GTCR.Reg)&^(0x70000)|value<<16)
}
func (o *GPT16E0_Type) GetGTCR_MD() uint32 {
	return (volatile.LoadUint32(&o.GTCR.Reg) & 0x70000) >> 16
}
func (o *GPT16E0_Type) SetGTCR_TPCS(value uint32) {
	volatile.StoreUint32(&o.GTCR.Reg, volatile.LoadUint32(&o.GTCR.Reg)&^(0x7800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTCR_TPCS() uint32 {
	return (volatile.LoadUint32(&o.GTCR.Reg) & 0x7800000) >> 23
}

// GPT16E0.GTUDDTYC: General PWM Timer Count Direction and Duty Setting Register
func (o *GPT16E0_Type) SetGTUDDTYC_UD(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTUDDTYC_UD() uint32 {
	return volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTUDDTYC_UDF(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTUDDTYC_UDF() uint32 {
	return (volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTUDDTYC_OADTY(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x30000)|value<<16)
}
func (o *GPT16E0_Type) GetGTUDDTYC_OADTY() uint32 {
	return (volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x30000) >> 16
}
func (o *GPT16E0_Type) SetGTUDDTYC_OADTYF(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTUDDTYC_OADTYF() uint32 {
	return (volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTUDDTYC_OADTYR(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTUDDTYC_OADTYR() uint32 {
	return (volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTUDDTYC_OBDTY(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x3000000)|value<<24)
}
func (o *GPT16E0_Type) GetGTUDDTYC_OBDTY() uint32 {
	return (volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x3000000) >> 24
}
func (o *GPT16E0_Type) SetGTUDDTYC_OBDTYF(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x4000000)|value<<26)
}
func (o *GPT16E0_Type) GetGTUDDTYC_OBDTYF() uint32 {
	return (volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x4000000) >> 26
}
func (o *GPT16E0_Type) SetGTUDDTYC_OBDTYR(value uint32) {
	volatile.StoreUint32(&o.GTUDDTYC.Reg, volatile.LoadUint32(&o.GTUDDTYC.Reg)&^(0x8000000)|value<<27)
}
func (o *GPT16E0_Type) GetGTUDDTYC_OBDTYR() uint32 {
	return (volatile.LoadUint32(&o.GTUDDTYC.Reg) & 0x8000000) >> 27
}

// GPT16E0.GTIOR: General PWM Timer I/O Control Register
func (o *GPT16E0_Type) SetGTIOR_GTIOA(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x1f)|value)
}
func (o *GPT16E0_Type) GetGTIOR_GTIOA() uint32 {
	return volatile.LoadUint32(&o.GTIOR.Reg) & 0x1f
}
func (o *GPT16E0_Type) SetGTIOR_OADFLT(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTIOR_OADFLT() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTIOR_OAHLD(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTIOR_OAHLD() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTIOR_OAE(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTIOR_OAE() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTIOR_OADF(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x600)|value<<9)
}
func (o *GPT16E0_Type) GetGTIOR_OADF() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x600) >> 9
}
func (o *GPT16E0_Type) SetGTIOR_NFAEN(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x2000)|value<<13)
}
func (o *GPT16E0_Type) GetGTIOR_NFAEN() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x2000) >> 13
}
func (o *GPT16E0_Type) SetGTIOR_NFCSA(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0xc000)|value<<14)
}
func (o *GPT16E0_Type) GetGTIOR_NFCSA() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0xc000) >> 14
}
func (o *GPT16E0_Type) SetGTIOR_GTIOB(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x1f0000)|value<<16)
}
func (o *GPT16E0_Type) GetGTIOR_GTIOB() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x1f0000) >> 16
}
func (o *GPT16E0_Type) SetGTIOR_OBDFLT(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTIOR_OBDFLT() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTIOR_OBHLD(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x800000)|value<<23)
}
func (o *GPT16E0_Type) GetGTIOR_OBHLD() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x800000) >> 23
}
func (o *GPT16E0_Type) SetGTIOR_OBE(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x1000000)|value<<24)
}
func (o *GPT16E0_Type) GetGTIOR_OBE() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x1000000) >> 24
}
func (o *GPT16E0_Type) SetGTIOR_OBDF(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x6000000)|value<<25)
}
func (o *GPT16E0_Type) GetGTIOR_OBDF() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x6000000) >> 25
}
func (o *GPT16E0_Type) SetGTIOR_NFBEN(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0x20000000)|value<<29)
}
func (o *GPT16E0_Type) GetGTIOR_NFBEN() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0x20000000) >> 29
}
func (o *GPT16E0_Type) SetGTIOR_NFCSB(value uint32) {
	volatile.StoreUint32(&o.GTIOR.Reg, volatile.LoadUint32(&o.GTIOR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPT16E0_Type) GetGTIOR_NFCSB() uint32 {
	return (volatile.LoadUint32(&o.GTIOR.Reg) & 0xc0000000) >> 30
}

// GPT16E0.GTINTAD: General PWM Timer Interrupt Output Setting Register
func (o *GPT16E0_Type) SetGTINTAD_GRP(value uint32) {
	volatile.StoreUint32(&o.GTINTAD.Reg, volatile.LoadUint32(&o.GTINTAD.Reg)&^(0x3000000)|value<<24)
}
func (o *GPT16E0_Type) GetGTINTAD_GRP() uint32 {
	return (volatile.LoadUint32(&o.GTINTAD.Reg) & 0x3000000) >> 24
}
func (o *GPT16E0_Type) SetGTINTAD_GRPABH(value uint32) {
	volatile.StoreUint32(&o.GTINTAD.Reg, volatile.LoadUint32(&o.GTINTAD.Reg)&^(0x20000000)|value<<29)
}
func (o *GPT16E0_Type) GetGTINTAD_GRPABH() uint32 {
	return (volatile.LoadUint32(&o.GTINTAD.Reg) & 0x20000000) >> 29
}
func (o *GPT16E0_Type) SetGTINTAD_GRPABL(value uint32) {
	volatile.StoreUint32(&o.GTINTAD.Reg, volatile.LoadUint32(&o.GTINTAD.Reg)&^(0x40000000)|value<<30)
}
func (o *GPT16E0_Type) GetGTINTAD_GRPABL() uint32 {
	return (volatile.LoadUint32(&o.GTINTAD.Reg) & 0x40000000) >> 30
}

// GPT16E0.GTST: General PWM Timer Status Register
func (o *GPT16E0_Type) SetGTST_TCFA(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTST_TCFA() uint32 {
	return volatile.LoadUint32(&o.GTST.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTST_TCFB(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTST_TCFB() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTST_TCFC(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTST_TCFC() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTST_TCFD(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTST_TCFD() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTST_TCFE(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTST_TCFE() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTST_TCFF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTST_TCFF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTST_TCFPO(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x40)|value<<6)
}
func (o *GPT16E0_Type) GetGTST_TCFPO() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x40) >> 6
}
func (o *GPT16E0_Type) SetGTST_TCFPU(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x80)|value<<7)
}
func (o *GPT16E0_Type) GetGTST_TCFPU() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x80) >> 7
}
func (o *GPT16E0_Type) SetGTST_ITCNT(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x700)|value<<8)
}
func (o *GPT16E0_Type) GetGTST_ITCNT() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x700) >> 8
}
func (o *GPT16E0_Type) SetGTST_TUCF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x8000)|value<<15)
}
func (o *GPT16E0_Type) GetGTST_TUCF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x8000) >> 15
}
func (o *GPT16E0_Type) SetGTST_ADTRAUF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTST_ADTRAUF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTST_ADTRADF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x20000)|value<<17)
}
func (o *GPT16E0_Type) GetGTST_ADTRADF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x20000) >> 17
}
func (o *GPT16E0_Type) SetGTST_ADTRBUF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x40000)|value<<18)
}
func (o *GPT16E0_Type) GetGTST_ADTRBUF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x40000) >> 18
}
func (o *GPT16E0_Type) SetGTST_ADTRBDF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x80000)|value<<19)
}
func (o *GPT16E0_Type) GetGTST_ADTRBDF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x80000) >> 19
}
func (o *GPT16E0_Type) SetGTST_ODF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x1000000)|value<<24)
}
func (o *GPT16E0_Type) GetGTST_ODF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x1000000) >> 24
}
func (o *GPT16E0_Type) SetGTST_DTEF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x10000000)|value<<28)
}
func (o *GPT16E0_Type) GetGTST_DTEF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x10000000) >> 28
}
func (o *GPT16E0_Type) SetGTST_OABHF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x20000000)|value<<29)
}
func (o *GPT16E0_Type) GetGTST_OABHF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x20000000) >> 29
}
func (o *GPT16E0_Type) SetGTST_OABLF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x40000000)|value<<30)
}
func (o *GPT16E0_Type) GetGTST_OABLF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x40000000) >> 30
}
func (o *GPT16E0_Type) SetGTST_PCF(value uint32) {
	volatile.StoreUint32(&o.GTST.Reg, volatile.LoadUint32(&o.GTST.Reg)&^(0x80000000)|value<<31)
}
func (o *GPT16E0_Type) GetGTST_PCF() uint32 {
	return (volatile.LoadUint32(&o.GTST.Reg) & 0x80000000) >> 31
}

// GPT16E0.GTBER: General PWM Timer Buffer Enable Register
func (o *GPT16E0_Type) SetGTBER_BD0(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTBER_BD0() uint32 {
	return volatile.LoadUint32(&o.GTBER.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTBER_BD1(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTBER_BD1() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTBER_BD2(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTBER_BD2() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTBER_BD3(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTBER_BD3() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTBER_CCRA(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x30000)|value<<16)
}
func (o *GPT16E0_Type) GetGTBER_CCRA() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x30000) >> 16
}
func (o *GPT16E0_Type) SetGTBER_CCRB(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0xc0000)|value<<18)
}
func (o *GPT16E0_Type) GetGTBER_CCRB() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0xc0000) >> 18
}
func (o *GPT16E0_Type) SetGTBER_PR(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x300000)|value<<20)
}
func (o *GPT16E0_Type) GetGTBER_PR() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x300000) >> 20
}
func (o *GPT16E0_Type) SetGTBER_CCRSWT(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x400000)|value<<22)
}
func (o *GPT16E0_Type) GetGTBER_CCRSWT() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x400000) >> 22
}
func (o *GPT16E0_Type) SetGTBER_ADTTA(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x3000000)|value<<24)
}
func (o *GPT16E0_Type) GetGTBER_ADTTA() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x3000000) >> 24
}
func (o *GPT16E0_Type) SetGTBER_ADTDA(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x4000000)|value<<26)
}
func (o *GPT16E0_Type) GetGTBER_ADTDA() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x4000000) >> 26
}
func (o *GPT16E0_Type) SetGTBER_ADTTB(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x30000000)|value<<28)
}
func (o *GPT16E0_Type) GetGTBER_ADTTB() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x30000000) >> 28
}
func (o *GPT16E0_Type) SetGTBER_ADTDB(value uint32) {
	volatile.StoreUint32(&o.GTBER.Reg, volatile.LoadUint32(&o.GTBER.Reg)&^(0x40000000)|value<<30)
}
func (o *GPT16E0_Type) GetGTBER_ADTDB() uint32 {
	return (volatile.LoadUint32(&o.GTBER.Reg) & 0x40000000) >> 30
}

// GPT16E0.GTITC: General PWM Timer Interrupt and A/D Conversion Start Request Skipping Setting Register
func (o *GPT16E0_Type) SetGTITC_ITLA(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTITC_ITLA() uint32 {
	return volatile.LoadUint32(&o.GTITC.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTITC_ITLB(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTITC_ITLB() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTITC_ITLC(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTITC_ITLC() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTITC_ITLD(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTITC_ITLD() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTITC_ITLE(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTITC_ITLE() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTITC_ITLF(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTITC_ITLF() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTITC_IVTC(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0xc0)|value<<6)
}
func (o *GPT16E0_Type) GetGTITC_IVTC() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0xc0) >> 6
}
func (o *GPT16E0_Type) SetGTITC_IVTT(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x700)|value<<8)
}
func (o *GPT16E0_Type) GetGTITC_IVTT() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x700) >> 8
}
func (o *GPT16E0_Type) SetGTITC_ADTAL(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x1000)|value<<12)
}
func (o *GPT16E0_Type) GetGTITC_ADTAL() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x1000) >> 12
}
func (o *GPT16E0_Type) SetGTITC_ADTBL(value uint32) {
	volatile.StoreUint32(&o.GTITC.Reg, volatile.LoadUint32(&o.GTITC.Reg)&^(0x4000)|value<<14)
}
func (o *GPT16E0_Type) GetGTITC_ADTBL() uint32 {
	return (volatile.LoadUint32(&o.GTITC.Reg) & 0x4000) >> 14
}

// GPT16E0.GTDTCR: General PWM Timer Dead Time Control Register
func (o *GPT16E0_Type) SetGTDTCR_TDE(value uint32) {
	volatile.StoreUint32(&o.GTDTCR.Reg, volatile.LoadUint32(&o.GTDTCR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTDTCR_TDE() uint32 {
	return volatile.LoadUint32(&o.GTDTCR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTDTCR_TDBUE(value uint32) {
	volatile.StoreUint32(&o.GTDTCR.Reg, volatile.LoadUint32(&o.GTDTCR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTDTCR_TDBUE() uint32 {
	return (volatile.LoadUint32(&o.GTDTCR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTDTCR_TDBDE(value uint32) {
	volatile.StoreUint32(&o.GTDTCR.Reg, volatile.LoadUint32(&o.GTDTCR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTDTCR_TDBDE() uint32 {
	return (volatile.LoadUint32(&o.GTDTCR.Reg) & 0x20) >> 5
}
func (o *GPT16E0_Type) SetGTDTCR_TDFER(value uint32) {
	volatile.StoreUint32(&o.GTDTCR.Reg, volatile.LoadUint32(&o.GTDTCR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTDTCR_TDFER() uint32 {
	return (volatile.LoadUint32(&o.GTDTCR.Reg) & 0x100) >> 8
}

// GPT16E0.GTSOS: General PWM Timer Output Protection Function Status Register
func (o *GPT16E0_Type) SetGTSOS_SOS(value uint32) {
	volatile.StoreUint32(&o.GTSOS.Reg, volatile.LoadUint32(&o.GTSOS.Reg)&^(0x3)|value)
}
func (o *GPT16E0_Type) GetGTSOS_SOS() uint32 {
	return volatile.LoadUint32(&o.GTSOS.Reg) & 0x3
}

// GPT16E0.GTSOTR: General PWM Timer Output Protection Function Temporary Release Register
func (o *GPT16E0_Type) SetGTSOTR_SOTR(value uint32) {
	volatile.StoreUint32(&o.GTSOTR.Reg, volatile.LoadUint32(&o.GTSOTR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTSOTR_SOTR() uint32 {
	return volatile.LoadUint32(&o.GTSOTR.Reg) & 0x1
}

// GPT16E0.GTADSMR: General PWM Timer A/D Conversion Start Request Signal Monitoring Register
func (o *GPT16E0_Type) SetGTADSMR_ADSMS0(value uint32) {
	volatile.StoreUint32(&o.GTADSMR.Reg, volatile.LoadUint32(&o.GTADSMR.Reg)&^(0x3)|value)
}
func (o *GPT16E0_Type) GetGTADSMR_ADSMS0() uint32 {
	return volatile.LoadUint32(&o.GTADSMR.Reg) & 0x3
}
func (o *GPT16E0_Type) SetGTADSMR_ADSMEN0(value uint32) {
	volatile.StoreUint32(&o.GTADSMR.Reg, volatile.LoadUint32(&o.GTADSMR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTADSMR_ADSMEN0() uint32 {
	return (volatile.LoadUint32(&o.GTADSMR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTADSMR_ADSMS1(value uint32) {
	volatile.StoreUint32(&o.GTADSMR.Reg, volatile.LoadUint32(&o.GTADSMR.Reg)&^(0x30000)|value<<16)
}
func (o *GPT16E0_Type) GetGTADSMR_ADSMS1() uint32 {
	return (volatile.LoadUint32(&o.GTADSMR.Reg) & 0x30000) >> 16
}
func (o *GPT16E0_Type) SetGTADSMR_ADSMEN1(value uint32) {
	volatile.StoreUint32(&o.GTADSMR.Reg, volatile.LoadUint32(&o.GTADSMR.Reg)&^(0x1000000)|value<<24)
}
func (o *GPT16E0_Type) GetGTADSMR_ADSMEN1() uint32 {
	return (volatile.LoadUint32(&o.GTADSMR.Reg) & 0x1000000) >> 24
}

// GPT16E0.GTICLF: General PWM Timer Inter Channel Logical Operation Function Setting Register
func (o *GPT16E0_Type) SetGTICLF_ICLFA(value uint32) {
	volatile.StoreUint32(&o.GTICLF.Reg, volatile.LoadUint32(&o.GTICLF.Reg)&^(0x7)|value)
}
func (o *GPT16E0_Type) GetGTICLF_ICLFA() uint32 {
	return volatile.LoadUint32(&o.GTICLF.Reg) & 0x7
}
func (o *GPT16E0_Type) SetGTICLF_ICLFSELC(value uint32) {
	volatile.StoreUint32(&o.GTICLF.Reg, volatile.LoadUint32(&o.GTICLF.Reg)&^(0x3f0)|value<<4)
}
func (o *GPT16E0_Type) GetGTICLF_ICLFSELC() uint32 {
	return (volatile.LoadUint32(&o.GTICLF.Reg) & 0x3f0) >> 4
}
func (o *GPT16E0_Type) SetGTICLF_ICLFB(value uint32) {
	volatile.StoreUint32(&o.GTICLF.Reg, volatile.LoadUint32(&o.GTICLF.Reg)&^(0x70000)|value<<16)
}
func (o *GPT16E0_Type) GetGTICLF_ICLFB() uint32 {
	return (volatile.LoadUint32(&o.GTICLF.Reg) & 0x70000) >> 16
}
func (o *GPT16E0_Type) SetGTICLF_ICLFSELD(value uint32) {
	volatile.StoreUint32(&o.GTICLF.Reg, volatile.LoadUint32(&o.GTICLF.Reg)&^(0x3f00000)|value<<20)
}
func (o *GPT16E0_Type) GetGTICLF_ICLFSELD() uint32 {
	return (volatile.LoadUint32(&o.GTICLF.Reg) & 0x3f00000) >> 20
}

// GPT16E0.GTPC: General PWM Timer Period Count Register
func (o *GPT16E0_Type) SetGTPC_PCEN(value uint32) {
	volatile.StoreUint32(&o.GTPC.Reg, volatile.LoadUint32(&o.GTPC.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTPC_PCEN() uint32 {
	return volatile.LoadUint32(&o.GTPC.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTPC_ASTP(value uint32) {
	volatile.StoreUint32(&o.GTPC.Reg, volatile.LoadUint32(&o.GTPC.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTPC_ASTP() uint32 {
	return (volatile.LoadUint32(&o.GTPC.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTPC_PCNT(value uint32) {
	volatile.StoreUint32(&o.GTPC.Reg, volatile.LoadUint32(&o.GTPC.Reg)&^(0xfff0000)|value<<16)
}
func (o *GPT16E0_Type) GetGTPC_PCNT() uint32 {
	return (volatile.LoadUint32(&o.GTPC.Reg) & 0xfff0000) >> 16
}

// GPT16E0.GTSECSR: General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register
func (o *GPT16E0_Type) SetGTSECSR_SECSEL0(value uint32) {
	volatile.StoreUint32(&o.GTSECSR.Reg, volatile.LoadUint32(&o.GTSECSR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTSECSR_SECSEL0() uint32 {
	return volatile.LoadUint32(&o.GTSECSR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTSECSR_SECSEL1(value uint32) {
	volatile.StoreUint32(&o.GTSECSR.Reg, volatile.LoadUint32(&o.GTSECSR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTSECSR_SECSEL1() uint32 {
	return (volatile.LoadUint32(&o.GTSECSR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTSECSR_SECSEL2(value uint32) {
	volatile.StoreUint32(&o.GTSECSR.Reg, volatile.LoadUint32(&o.GTSECSR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTSECSR_SECSEL2() uint32 {
	return (volatile.LoadUint32(&o.GTSECSR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTSECSR_SECSEL3(value uint32) {
	volatile.StoreUint32(&o.GTSECSR.Reg, volatile.LoadUint32(&o.GTSECSR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTSECSR_SECSEL3() uint32 {
	return (volatile.LoadUint32(&o.GTSECSR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTSECSR_SECSEL4(value uint32) {
	volatile.StoreUint32(&o.GTSECSR.Reg, volatile.LoadUint32(&o.GTSECSR.Reg)&^(0x10)|value<<4)
}
func (o *GPT16E0_Type) GetGTSECSR_SECSEL4() uint32 {
	return (volatile.LoadUint32(&o.GTSECSR.Reg) & 0x10) >> 4
}
func (o *GPT16E0_Type) SetGTSECSR_SECSEL5(value uint32) {
	volatile.StoreUint32(&o.GTSECSR.Reg, volatile.LoadUint32(&o.GTSECSR.Reg)&^(0x20)|value<<5)
}
func (o *GPT16E0_Type) GetGTSECSR_SECSEL5() uint32 {
	return (volatile.LoadUint32(&o.GTSECSR.Reg) & 0x20) >> 5
}

// GPT16E0.GTSECR: General PWM Timer Operation Enable Bit Simultaneous Control Register
func (o *GPT16E0_Type) SetGTSECR_SBDCE(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x1)|value)
}
func (o *GPT16E0_Type) GetGTSECR_SBDCE() uint32 {
	return volatile.LoadUint32(&o.GTSECR.Reg) & 0x1
}
func (o *GPT16E0_Type) SetGTSECR_SBDPE(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x2)|value<<1)
}
func (o *GPT16E0_Type) GetGTSECR_SBDPE() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x2) >> 1
}
func (o *GPT16E0_Type) SetGTSECR_SBDAE(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x4)|value<<2)
}
func (o *GPT16E0_Type) GetGTSECR_SBDAE() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x4) >> 2
}
func (o *GPT16E0_Type) SetGTSECR_SBDDE(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x8)|value<<3)
}
func (o *GPT16E0_Type) GetGTSECR_SBDDE() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x8) >> 3
}
func (o *GPT16E0_Type) SetGTSECR_SBDCD(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x100)|value<<8)
}
func (o *GPT16E0_Type) GetGTSECR_SBDCD() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x100) >> 8
}
func (o *GPT16E0_Type) SetGTSECR_SBDPD(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x200)|value<<9)
}
func (o *GPT16E0_Type) GetGTSECR_SBDPD() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x200) >> 9
}
func (o *GPT16E0_Type) SetGTSECR_SBDAD(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x400)|value<<10)
}
func (o *GPT16E0_Type) GetGTSECR_SBDAD() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x400) >> 10
}
func (o *GPT16E0_Type) SetGTSECR_SBDDD(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x800)|value<<11)
}
func (o *GPT16E0_Type) GetGTSECR_SBDDD() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x800) >> 11
}
func (o *GPT16E0_Type) SetGTSECR_SPCE(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT16E0_Type) GetGTSECR_SPCE() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x10000) >> 16
}
func (o *GPT16E0_Type) SetGTSECR_SPCD(value uint32) {
	volatile.StoreUint32(&o.GTSECR.Reg, volatile.LoadUint32(&o.GTSECR.Reg)&^(0x1000000)|value<<24)
}
func (o *GPT16E0_Type) GetGTSECR_SPCD() uint32 {
	return (volatile.LoadUint32(&o.GTSECR.Reg) & 0x1000000) >> 24
}

// Output Phase Switching Controller
type GPT_OPS_Type struct {
	OPSCR volatile.Register32 // 0x0
}

// GPT_OPS.OPSCR: Output Phase Switching Control Register
func (o *GPT_OPS_Type) SetOPSCR_UF(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x1)|value)
}
func (o *GPT_OPS_Type) GetOPSCR_UF() uint32 {
	return volatile.LoadUint32(&o.OPSCR.Reg) & 0x1
}
func (o *GPT_OPS_Type) SetOPSCR_VF(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x2)|value<<1)
}
func (o *GPT_OPS_Type) GetOPSCR_VF() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x2) >> 1
}
func (o *GPT_OPS_Type) SetOPSCR_WF(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x4)|value<<2)
}
func (o *GPT_OPS_Type) GetOPSCR_WF() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x4) >> 2
}
func (o *GPT_OPS_Type) SetOPSCR_U(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x10)|value<<4)
}
func (o *GPT_OPS_Type) GetOPSCR_U() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x10) >> 4
}
func (o *GPT_OPS_Type) SetOPSCR_V(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x20)|value<<5)
}
func (o *GPT_OPS_Type) GetOPSCR_V() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x20) >> 5
}
func (o *GPT_OPS_Type) SetOPSCR_W(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x40)|value<<6)
}
func (o *GPT_OPS_Type) GetOPSCR_W() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x40) >> 6
}
func (o *GPT_OPS_Type) SetOPSCR_EN(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x100)|value<<8)
}
func (o *GPT_OPS_Type) GetOPSCR_EN() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x100) >> 8
}
func (o *GPT_OPS_Type) SetOPSCR_FB(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x10000)|value<<16)
}
func (o *GPT_OPS_Type) GetOPSCR_FB() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x10000) >> 16
}
func (o *GPT_OPS_Type) SetOPSCR_P(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x20000)|value<<17)
}
func (o *GPT_OPS_Type) GetOPSCR_P() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x20000) >> 17
}
func (o *GPT_OPS_Type) SetOPSCR_N(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x40000)|value<<18)
}
func (o *GPT_OPS_Type) GetOPSCR_N() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x40000) >> 18
}
func (o *GPT_OPS_Type) SetOPSCR_INV(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x80000)|value<<19)
}
func (o *GPT_OPS_Type) GetOPSCR_INV() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x80000) >> 19
}
func (o *GPT_OPS_Type) SetOPSCR_RV(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x100000)|value<<20)
}
func (o *GPT_OPS_Type) GetOPSCR_RV() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x100000) >> 20
}
func (o *GPT_OPS_Type) SetOPSCR_ALIGN(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x200000)|value<<21)
}
func (o *GPT_OPS_Type) GetOPSCR_ALIGN() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x200000) >> 21
}
func (o *GPT_OPS_Type) SetOPSCR_GRP(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPT_OPS_Type) GetOPSCR_GRP() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x3000000) >> 24
}
func (o *GPT_OPS_Type) SetOPSCR_GODF(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x4000000)|value<<26)
}
func (o *GPT_OPS_Type) GetOPSCR_GODF() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x4000000) >> 26
}
func (o *GPT_OPS_Type) SetOPSCR_NFEN(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0x20000000)|value<<29)
}
func (o *GPT_OPS_Type) GetOPSCR_NFEN() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0x20000000) >> 29
}
func (o *GPT_OPS_Type) SetOPSCR_NFCS(value uint32) {
	volatile.StoreUint32(&o.OPSCR.Reg, volatile.LoadUint32(&o.OPSCR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPT_OPS_Type) GetOPSCR_NFCS() uint32 {
	return (volatile.LoadUint32(&o.OPSCR.Reg) & 0xc0000000) >> 30
}

// 12-bit A/D Converter
type ADC120_Type struct {
	ADCSR      volatile.Register16 // 0x0
	_          [2]byte
	ADANSA0    volatile.Register16 // 0x4
	ADANSA1    volatile.Register16 // 0x6
	ADADS0     volatile.Register16 // 0x8
	ADADS1     volatile.Register16 // 0xA
	ADADC      volatile.Register8  // 0xC
	_          byte
	ADCER      volatile.Register16 // 0xE
	ADSTRGR    volatile.Register16 // 0x10
	ADEXICR    volatile.Register16 // 0x12
	ADANSB0    volatile.Register16 // 0x14
	ADANSB1    volatile.Register16 // 0x16
	ADDBLDR    volatile.Register16 // 0x18
	ADTSDR     volatile.Register16 // 0x1A
	ADOCDR     volatile.Register16 // 0x1C
	ADRD       volatile.Register16 // 0x1E
	ADDR0      volatile.Register16 // 0x20
	ADDR1      volatile.Register16 // 0x22
	ADDR2      volatile.Register16 // 0x24
	_          [2]byte
	ADDR4      volatile.Register16 // 0x28
	ADDR5      volatile.Register16 // 0x2A
	ADDR6      volatile.Register16 // 0x2C
	ADDR7      volatile.Register16 // 0x2E
	ADDR8      volatile.Register16 // 0x30
	_          [4]byte
	ADDR11     volatile.Register16 // 0x36
	ADDR12     volatile.Register16 // 0x38
	ADDR13     volatile.Register16 // 0x3A
	_          [4]byte
	ADDR16     volatile.Register16 // 0x40
	_          [56]byte
	ADDISCR    volatile.Register8 // 0x7A
	_          [5]byte
	ADGSPCR    volatile.Register16 // 0x80
	_          [2]byte
	ADDBLDRA   volatile.Register16 // 0x84
	ADDBLDRB   volatile.Register16 // 0x86
	_          [4]byte
	ADWINMON   volatile.Register8 // 0x8C
	_          [3]byte
	ADCMPCR    volatile.Register16 // 0x90
	ADCMPANSER volatile.Register8  // 0x92
	ADCMPLER   volatile.Register8  // 0x93
	ADCMPANSR0 volatile.Register16 // 0x94
	ADCMPANSR1 volatile.Register16 // 0x96
	ADCMPLR0   volatile.Register16 // 0x98
	ADCMPLR1   volatile.Register16 // 0x9A
	ADCMPDR0   volatile.Register16 // 0x9C
	ADCMPDR1   volatile.Register16 // 0x9E
	ADCMPSR0   volatile.Register16 // 0xA0
	ADCMPSR1   volatile.Register16 // 0xA2
	ADCMPSER   volatile.Register8  // 0xA4
	_          byte
	ADCMPBNSR  volatile.Register8 // 0xA6
	_          byte
	ADWINLLB   volatile.Register16 // 0xA8
	ADWINULB   volatile.Register16 // 0xAA
	ADCMPBSR   volatile.Register8  // 0xAC
	_          [3]byte
	ADBUF0     volatile.Register16 // 0xB0
	ADBUF1     volatile.Register16 // 0xB2
	ADBUF2     volatile.Register16 // 0xB4
	ADBUF3     volatile.Register16 // 0xB6
	ADBUF4     volatile.Register16 // 0xB8
	ADBUF5     volatile.Register16 // 0xBA
	ADBUF6     volatile.Register16 // 0xBC
	ADBUF7     volatile.Register16 // 0xBE
	ADBUF8     volatile.Register16 // 0xC0
	ADBUF9     volatile.Register16 // 0xC2
	ADBUF10    volatile.Register16 // 0xC4
	ADBUF11    volatile.Register16 // 0xC6
	ADBUF12    volatile.Register16 // 0xC8
	ADBUF13    volatile.Register16 // 0xCA
	ADBUF14    volatile.Register16 // 0xCC
	ADBUF15    volatile.Register16 // 0xCE
	ADBUFEN    volatile.Register8  // 0xD0
	_          byte
	ADBUFPTR   volatile.Register8 // 0xD2
	_          [10]byte
	ADSSTRL    volatile.Register8 // 0xDD
	ADSSTRT    volatile.Register8 // 0xDE
	ADSSTRO    volatile.Register8 // 0xDF
	ADSSTR0    volatile.Register8 // 0xE0
	ADSSTR1    volatile.Register8 // 0xE1
	ADSSTR2    volatile.Register8 // 0xE2
	_          byte
	ADSSTR4    volatile.Register8 // 0xE4
	ADSSTR5    volatile.Register8 // 0xE5
	ADSSTR6    volatile.Register8 // 0xE6
	ADSSTR7    volatile.Register8 // 0xE7
	ADSSTR8    volatile.Register8 // 0xE8
	_          [2]byte
	ADSSTR11   volatile.Register8 // 0xEB
	ADSSTR12   volatile.Register8 // 0xEC
	ADSSTR13   volatile.Register8 // 0xED
}

// ADC120.ADCSR: A/D Control Register
func (o *ADC120_Type) SetADCSR_DBLANS(value uint16) {
	volatile.StoreUint16(&o.ADCSR.Reg, volatile.LoadUint16(&o.ADCSR.Reg)&^(0x1f)|value)
}
func (o *ADC120_Type) GetADCSR_DBLANS() uint16 {
	return volatile.LoadUint16(&o.ADCSR.Reg) & 0x1f
}
func (o *ADC120_Type) SetADCSR_GBADIE(value uint16) {
	volatile.StoreUint16(&o.ADCSR.Reg, volatile.LoadUint16(&o.ADCSR.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADCSR_GBADIE() uint16 {
	return (volatile.LoadUint16(&o.ADCSR.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADCSR_DBLE(value uint16) {
	volatile.StoreUint16(&o.ADCSR.Reg, volatile.LoadUint16(&o.ADCSR.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCSR_DBLE() uint16 {
	return (volatile.LoadUint16(&o.ADCSR.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADCSR_EXTRG(value uint16) {
	volatile.StoreUint16(&o.ADCSR.Reg, volatile.LoadUint16(&o.ADCSR.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADCSR_EXTRG() uint16 {
	return (volatile.LoadUint16(&o.ADCSR.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADCSR_TRGE(value uint16) {
	volatile.StoreUint16(&o.ADCSR.Reg, volatile.LoadUint16(&o.ADCSR.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCSR_TRGE() uint16 {
	return (volatile.LoadUint16(&o.ADCSR.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCSR_ADCS(value uint16) {
	volatile.StoreUint16(&o.ADCSR.Reg, volatile.LoadUint16(&o.ADCSR.Reg)&^(0x6000)|value<<13)
}
func (o *ADC120_Type) GetADCSR_ADCS() uint16 {
	return (volatile.LoadUint16(&o.ADCSR.Reg) & 0x6000) >> 13
}
func (o *ADC120_Type) SetADCSR_ADST(value uint16) {
	volatile.StoreUint16(&o.ADCSR.Reg, volatile.LoadUint16(&o.ADCSR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCSR_ADST() uint16 {
	return (volatile.LoadUint16(&o.ADCSR.Reg) & 0x8000) >> 15
}

// ADC120.ADANSA0: A/D Channel Select Register A0
func (o *ADC120_Type) SetADANSA0_ANSA00(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADANSA0_ANSA00() uint16 {
	return volatile.LoadUint16(&o.ADANSA0.Reg) & 0x1
}
func (o *ADC120_Type) SetADANSA0_ANSA01(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADANSA0_ANSA01() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADANSA0_ANSA02(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADANSA0_ANSA02() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADANSA0_ANSA03(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADANSA0_ANSA03() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADANSA0_ANSA04(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADANSA0_ANSA04() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADANSA0_ANSA05(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADANSA0_ANSA05() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADANSA0_ANSA06(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADANSA0_ANSA06() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADANSA0_ANSA07(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADANSA0_ANSA07() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADANSA0_ANSA08(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADANSA0_ANSA08() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADANSA0_ANSA09(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADANSA0_ANSA09() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADANSA0_ANSA10(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADANSA0_ANSA10() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADANSA0_ANSA11(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADANSA0_ANSA11() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADANSA0_ANSA12(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADANSA0_ANSA12() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADANSA0_ANSA13(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADANSA0_ANSA13() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADANSA0_ANSA14(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADANSA0_ANSA14() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADANSA0_ANSA15(value uint16) {
	volatile.StoreUint16(&o.ADANSA0.Reg, volatile.LoadUint16(&o.ADANSA0.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADANSA0_ANSA15() uint16 {
	return (volatile.LoadUint16(&o.ADANSA0.Reg) & 0x8000) >> 15
}

// ADC120.ADANSA1: A/D Channel Select Register A1
func (o *ADC120_Type) SetADANSA1_ANSA16(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADANSA1_ANSA16() uint16 {
	return volatile.LoadUint16(&o.ADANSA1.Reg) & 0x1
}
func (o *ADC120_Type) SetADANSA1_ANSA17(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADANSA1_ANSA17() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADANSA1_ANSA18(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADANSA1_ANSA18() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADANSA1_ANSA19(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADANSA1_ANSA19() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADANSA1_ANSA20(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADANSA1_ANSA20() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADANSA1_ANSA21(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADANSA1_ANSA21() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADANSA1_ANSA22(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADANSA1_ANSA22() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADANSA1_ANSA23(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADANSA1_ANSA23() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADANSA1_ANSA24(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADANSA1_ANSA24() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADANSA1_ANSA25(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADANSA1_ANSA25() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADANSA1_ANSA26(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADANSA1_ANSA26() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADANSA1_ANSA27(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADANSA1_ANSA27() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADANSA1_ANSA28(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADANSA1_ANSA28() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADANSA1_ANSA29(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADANSA1_ANSA29() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADANSA1_ANSA30(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADANSA1_ANSA30() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADANSA1_ANSA31(value uint16) {
	volatile.StoreUint16(&o.ADANSA1.Reg, volatile.LoadUint16(&o.ADANSA1.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADANSA1_ANSA31() uint16 {
	return (volatile.LoadUint16(&o.ADANSA1.Reg) & 0x8000) >> 15
}

// ADC120.ADADS0: A/D-Converted Value Addition/Average Channel Select Register 0
func (o *ADC120_Type) SetADADS0_ADS00(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADADS0_ADS00() uint16 {
	return volatile.LoadUint16(&o.ADADS0.Reg) & 0x1
}
func (o *ADC120_Type) SetADADS0_ADS01(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADADS0_ADS01() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADADS0_ADS02(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADADS0_ADS02() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADADS0_ADS03(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADADS0_ADS03() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADADS0_ADS04(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADADS0_ADS04() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADADS0_ADS05(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADADS0_ADS05() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADADS0_ADS06(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADADS0_ADS06() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADADS0_ADS07(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADADS0_ADS07() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADADS0_ADS08(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADADS0_ADS08() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADADS0_ADS09(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADADS0_ADS09() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADADS0_ADS10(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADADS0_ADS10() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADADS0_ADS11(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADADS0_ADS11() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADADS0_ADS12(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADADS0_ADS12() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADADS0_ADS13(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADADS0_ADS13() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADADS0_ADS14(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADADS0_ADS14() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADADS0_ADS15(value uint16) {
	volatile.StoreUint16(&o.ADADS0.Reg, volatile.LoadUint16(&o.ADADS0.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADADS0_ADS15() uint16 {
	return (volatile.LoadUint16(&o.ADADS0.Reg) & 0x8000) >> 15
}

// ADC120.ADADS1: A/D-Converted Value Addition/Average Channel Select Register 1
func (o *ADC120_Type) SetADADS1_ADS16(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADADS1_ADS16() uint16 {
	return volatile.LoadUint16(&o.ADADS1.Reg) & 0x1
}
func (o *ADC120_Type) SetADADS1_ADS17(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADADS1_ADS17() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADADS1_ADS18(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADADS1_ADS18() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADADS1_ADS19(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADADS1_ADS19() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADADS1_ADS20(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADADS1_ADS20() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADADS1_ADS21(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADADS1_ADS21() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADADS1_ADS22(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADADS1_ADS22() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADADS1_ADS23(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADADS1_ADS23() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADADS1_ADS24(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADADS1_ADS24() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADADS1_ADS25(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADADS1_ADS25() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADADS1_ADS26(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADADS1_ADS26() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADADS1_ADS27(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADADS1_ADS27() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADADS1_ADS28(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADADS1_ADS28() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADADS1_ADS29(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADADS1_ADS29() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADADS1_ADS30(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADADS1_ADS30() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADADS1_ADS31(value uint16) {
	volatile.StoreUint16(&o.ADADS1.Reg, volatile.LoadUint16(&o.ADADS1.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADADS1_ADS31() uint16 {
	return (volatile.LoadUint16(&o.ADADS1.Reg) & 0x8000) >> 15
}

// ADC120.ADADC: A/D-Converted Value Addition/Average Count Select Register
func (o *ADC120_Type) SetADADC_ADC(value uint8) {
	volatile.StoreUint8(&o.ADADC.Reg, volatile.LoadUint8(&o.ADADC.Reg)&^(0x7)|value)
}
func (o *ADC120_Type) GetADADC_ADC() uint8 {
	return volatile.LoadUint8(&o.ADADC.Reg) & 0x7
}
func (o *ADC120_Type) SetADADC_AVEE(value uint8) {
	volatile.StoreUint8(&o.ADADC.Reg, volatile.LoadUint8(&o.ADADC.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADADC_AVEE() uint8 {
	return (volatile.LoadUint8(&o.ADADC.Reg) & 0x80) >> 7
}

// ADC120.ADCER: A/D Control Extended Register
func (o *ADC120_Type) SetADCER_ADPRC(value uint16) {
	volatile.StoreUint16(&o.ADCER.Reg, volatile.LoadUint16(&o.ADCER.Reg)&^(0x6)|value<<1)
}
func (o *ADC120_Type) GetADCER_ADPRC() uint16 {
	return (volatile.LoadUint16(&o.ADCER.Reg) & 0x6) >> 1
}
func (o *ADC120_Type) SetADCER_ACE(value uint16) {
	volatile.StoreUint16(&o.ADCER.Reg, volatile.LoadUint16(&o.ADCER.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADCER_ACE() uint16 {
	return (volatile.LoadUint16(&o.ADCER.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADCER_DIAGVAL(value uint16) {
	volatile.StoreUint16(&o.ADCER.Reg, volatile.LoadUint16(&o.ADCER.Reg)&^(0x300)|value<<8)
}
func (o *ADC120_Type) GetADCER_DIAGVAL() uint16 {
	return (volatile.LoadUint16(&o.ADCER.Reg) & 0x300) >> 8
}
func (o *ADC120_Type) SetADCER_DIAGLD(value uint16) {
	volatile.StoreUint16(&o.ADCER.Reg, volatile.LoadUint16(&o.ADCER.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADCER_DIAGLD() uint16 {
	return (volatile.LoadUint16(&o.ADCER.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADCER_DIAGM(value uint16) {
	volatile.StoreUint16(&o.ADCER.Reg, volatile.LoadUint16(&o.ADCER.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCER_DIAGM() uint16 {
	return (volatile.LoadUint16(&o.ADCER.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCER_ADRFMT(value uint16) {
	volatile.StoreUint16(&o.ADCER.Reg, volatile.LoadUint16(&o.ADCER.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCER_ADRFMT() uint16 {
	return (volatile.LoadUint16(&o.ADCER.Reg) & 0x8000) >> 15
}

// ADC120.ADSTRGR: A/D Conversion Start Trigger Select Register
func (o *ADC120_Type) SetADSTRGR_TRSB(value uint16) {
	volatile.StoreUint16(&o.ADSTRGR.Reg, volatile.LoadUint16(&o.ADSTRGR.Reg)&^(0x3f)|value)
}
func (o *ADC120_Type) GetADSTRGR_TRSB() uint16 {
	return volatile.LoadUint16(&o.ADSTRGR.Reg) & 0x3f
}
func (o *ADC120_Type) SetADSTRGR_TRSA(value uint16) {
	volatile.StoreUint16(&o.ADSTRGR.Reg, volatile.LoadUint16(&o.ADSTRGR.Reg)&^(0x3f00)|value<<8)
}
func (o *ADC120_Type) GetADSTRGR_TRSA() uint16 {
	return (volatile.LoadUint16(&o.ADSTRGR.Reg) & 0x3f00) >> 8
}

// ADC120.ADEXICR: A/D Conversion Extended Input Control Registers
func (o *ADC120_Type) SetADEXICR_TSSAD(value uint16) {
	volatile.StoreUint16(&o.ADEXICR.Reg, volatile.LoadUint16(&o.ADEXICR.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADEXICR_TSSAD() uint16 {
	return volatile.LoadUint16(&o.ADEXICR.Reg) & 0x1
}
func (o *ADC120_Type) SetADEXICR_OCSAD(value uint16) {
	volatile.StoreUint16(&o.ADEXICR.Reg, volatile.LoadUint16(&o.ADEXICR.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADEXICR_OCSAD() uint16 {
	return (volatile.LoadUint16(&o.ADEXICR.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADEXICR_TSSA(value uint16) {
	volatile.StoreUint16(&o.ADEXICR.Reg, volatile.LoadUint16(&o.ADEXICR.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADEXICR_TSSA() uint16 {
	return (volatile.LoadUint16(&o.ADEXICR.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADEXICR_OCSA(value uint16) {
	volatile.StoreUint16(&o.ADEXICR.Reg, volatile.LoadUint16(&o.ADEXICR.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADEXICR_OCSA() uint16 {
	return (volatile.LoadUint16(&o.ADEXICR.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADEXICR_TSSB(value uint16) {
	volatile.StoreUint16(&o.ADEXICR.Reg, volatile.LoadUint16(&o.ADEXICR.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADEXICR_TSSB() uint16 {
	return (volatile.LoadUint16(&o.ADEXICR.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADEXICR_OCSB(value uint16) {
	volatile.StoreUint16(&o.ADEXICR.Reg, volatile.LoadUint16(&o.ADEXICR.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADEXICR_OCSB() uint16 {
	return (volatile.LoadUint16(&o.ADEXICR.Reg) & 0x800) >> 11
}

// ADC120.ADANSB0: A/D Channel Select Register B0
func (o *ADC120_Type) SetADANSB0_ANSB00(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADANSB0_ANSB00() uint16 {
	return volatile.LoadUint16(&o.ADANSB0.Reg) & 0x1
}
func (o *ADC120_Type) SetADANSB0_ANSB01(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADANSB0_ANSB01() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADANSB0_ANSB02(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADANSB0_ANSB02() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADANSB0_ANSB03(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADANSB0_ANSB03() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADANSB0_ANSB04(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADANSB0_ANSB04() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADANSB0_ANSB05(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADANSB0_ANSB05() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADANSB0_ANSB06(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADANSB0_ANSB06() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADANSB0_ANSB07(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADANSB0_ANSB07() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADANSB0_ANSB08(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADANSB0_ANSB08() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADANSB0_ANSB09(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADANSB0_ANSB09() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADANSB0_ANSB10(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADANSB0_ANSB10() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADANSB0_ANSB11(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADANSB0_ANSB11() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADANSB0_ANSB12(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADANSB0_ANSB12() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADANSB0_ANSB13(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADANSB0_ANSB13() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADANSB0_ANSB14(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADANSB0_ANSB14() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADANSB0_ANSB15(value uint16) {
	volatile.StoreUint16(&o.ADANSB0.Reg, volatile.LoadUint16(&o.ADANSB0.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADANSB0_ANSB15() uint16 {
	return (volatile.LoadUint16(&o.ADANSB0.Reg) & 0x8000) >> 15
}

// ADC120.ADANSB1: A/D Channel Select Register B1
func (o *ADC120_Type) SetADANSB1_ANSB16(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADANSB1_ANSB16() uint16 {
	return volatile.LoadUint16(&o.ADANSB1.Reg) & 0x1
}
func (o *ADC120_Type) SetADANSB1_ANSB17(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADANSB1_ANSB17() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADANSB1_ANSB18(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADANSB1_ANSB18() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADANSB1_ANSB19(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADANSB1_ANSB19() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADANSB1_ANSB20(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADANSB1_ANSB20() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADANSB1_ANSB21(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADANSB1_ANSB21() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADANSB1_ANSB22(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADANSB1_ANSB22() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADANSB1_ANSB23(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADANSB1_ANSB23() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADANSB1_ANSB24(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADANSB1_ANSB24() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADANSB1_ANSB25(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADANSB1_ANSB25() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADANSB1_ANSB26(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADANSB1_ANSB26() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADANSB1_ANSB27(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADANSB1_ANSB27() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADANSB1_ANSB28(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADANSB1_ANSB28() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADANSB1_ANSB29(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADANSB1_ANSB29() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADANSB1_ANSB30(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADANSB1_ANSB30() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADANSB1_ANSB31(value uint16) {
	volatile.StoreUint16(&o.ADANSB1.Reg, volatile.LoadUint16(&o.ADANSB1.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADANSB1_ANSB31() uint16 {
	return (volatile.LoadUint16(&o.ADANSB1.Reg) & 0x8000) >> 15
}

// ADC120.ADDBLDR: A/D Data Duplexing Register
func (o *ADC120_Type) SetADDBLDR(value uint16) {
	volatile.StoreUint16(&o.ADDBLDR.Reg, value)
}
func (o *ADC120_Type) GetADDBLDR() uint16 {
	return volatile.LoadUint16(&o.ADDBLDR.Reg)
}

// ADC120.ADTSDR: A/D Temperature Sensor Data Register
func (o *ADC120_Type) SetADTSDR(value uint16) {
	volatile.StoreUint16(&o.ADTSDR.Reg, value)
}
func (o *ADC120_Type) GetADTSDR() uint16 {
	return volatile.LoadUint16(&o.ADTSDR.Reg)
}

// ADC120.ADOCDR: A/D Internal Reference Voltage Data Register
func (o *ADC120_Type) SetADOCDR(value uint16) {
	volatile.StoreUint16(&o.ADOCDR.Reg, value)
}
func (o *ADC120_Type) GetADOCDR() uint16 {
	return volatile.LoadUint16(&o.ADOCDR.Reg)
}

// ADC120.ADRD: A/D Self-Diagnosis Data Register
func (o *ADC120_Type) SetADRD_AD(value uint16) {
	volatile.StoreUint16(&o.ADRD.Reg, volatile.LoadUint16(&o.ADRD.Reg)&^(0xfff)|value)
}
func (o *ADC120_Type) GetADRD_AD() uint16 {
	return volatile.LoadUint16(&o.ADRD.Reg) & 0xfff
}
func (o *ADC120_Type) SetADRD_DIAGST(value uint16) {
	volatile.StoreUint16(&o.ADRD.Reg, volatile.LoadUint16(&o.ADRD.Reg)&^(0xc000)|value<<14)
}
func (o *ADC120_Type) GetADRD_DIAGST() uint16 {
	return (volatile.LoadUint16(&o.ADRD.Reg) & 0xc000) >> 14
}

// ADC120.ADDR0: A/D Data Registers %s
func (o *ADC120_Type) SetADDR0(value uint16) {
	volatile.StoreUint16(&o.ADDR0.Reg, value)
}
func (o *ADC120_Type) GetADDR0() uint16 {
	return volatile.LoadUint16(&o.ADDR0.Reg)
}

// ADC120.ADDR1: A/D Data Registers %s
func (o *ADC120_Type) SetADDR1(value uint16) {
	volatile.StoreUint16(&o.ADDR1.Reg, value)
}
func (o *ADC120_Type) GetADDR1() uint16 {
	return volatile.LoadUint16(&o.ADDR1.Reg)
}

// ADC120.ADDR2: A/D Data Registers %s
func (o *ADC120_Type) SetADDR2(value uint16) {
	volatile.StoreUint16(&o.ADDR2.Reg, value)
}
func (o *ADC120_Type) GetADDR2() uint16 {
	return volatile.LoadUint16(&o.ADDR2.Reg)
}

// ADC120.ADDR4: A/D Data Registers %s
func (o *ADC120_Type) SetADDR4(value uint16) {
	volatile.StoreUint16(&o.ADDR4.Reg, value)
}
func (o *ADC120_Type) GetADDR4() uint16 {
	return volatile.LoadUint16(&o.ADDR4.Reg)
}

// ADC120.ADDR5: A/D Data Registers %s
func (o *ADC120_Type) SetADDR5(value uint16) {
	volatile.StoreUint16(&o.ADDR5.Reg, value)
}
func (o *ADC120_Type) GetADDR5() uint16 {
	return volatile.LoadUint16(&o.ADDR5.Reg)
}

// ADC120.ADDR6: A/D Data Registers %s
func (o *ADC120_Type) SetADDR6(value uint16) {
	volatile.StoreUint16(&o.ADDR6.Reg, value)
}
func (o *ADC120_Type) GetADDR6() uint16 {
	return volatile.LoadUint16(&o.ADDR6.Reg)
}

// ADC120.ADDR7: A/D Data Registers %s
func (o *ADC120_Type) SetADDR7(value uint16) {
	volatile.StoreUint16(&o.ADDR7.Reg, value)
}
func (o *ADC120_Type) GetADDR7() uint16 {
	return volatile.LoadUint16(&o.ADDR7.Reg)
}

// ADC120.ADDR8: A/D Data Registers %s
func (o *ADC120_Type) SetADDR8(value uint16) {
	volatile.StoreUint16(&o.ADDR8.Reg, value)
}
func (o *ADC120_Type) GetADDR8() uint16 {
	return volatile.LoadUint16(&o.ADDR8.Reg)
}

// ADC120.ADDR11: A/D Data Registers %s
func (o *ADC120_Type) SetADDR11(value uint16) {
	volatile.StoreUint16(&o.ADDR11.Reg, value)
}
func (o *ADC120_Type) GetADDR11() uint16 {
	return volatile.LoadUint16(&o.ADDR11.Reg)
}

// ADC120.ADDR12: A/D Data Registers %s
func (o *ADC120_Type) SetADDR12(value uint16) {
	volatile.StoreUint16(&o.ADDR12.Reg, value)
}
func (o *ADC120_Type) GetADDR12() uint16 {
	return volatile.LoadUint16(&o.ADDR12.Reg)
}

// ADC120.ADDR13: A/D Data Registers %s
func (o *ADC120_Type) SetADDR13(value uint16) {
	volatile.StoreUint16(&o.ADDR13.Reg, value)
}
func (o *ADC120_Type) GetADDR13() uint16 {
	return volatile.LoadUint16(&o.ADDR13.Reg)
}

// ADC120.ADDR16: A/D Data Registers 16
func (o *ADC120_Type) SetADDR16(value uint16) {
	volatile.StoreUint16(&o.ADDR16.Reg, value)
}
func (o *ADC120_Type) GetADDR16() uint16 {
	return volatile.LoadUint16(&o.ADDR16.Reg)
}

// ADC120.ADDISCR: A/D Disconnection Detection Control Register
func (o *ADC120_Type) SetADDISCR_ADNDIS(value uint8) {
	volatile.StoreUint8(&o.ADDISCR.Reg, volatile.LoadUint8(&o.ADDISCR.Reg)&^(0xf)|value)
}
func (o *ADC120_Type) GetADDISCR_ADNDIS() uint8 {
	return volatile.LoadUint8(&o.ADDISCR.Reg) & 0xf
}
func (o *ADC120_Type) SetADDISCR_PCHG(value uint8) {
	volatile.StoreUint8(&o.ADDISCR.Reg, volatile.LoadUint8(&o.ADDISCR.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADDISCR_PCHG() uint8 {
	return (volatile.LoadUint8(&o.ADDISCR.Reg) & 0x10) >> 4
}

// ADC120.ADGSPCR: A/D Group Scan Priority Control Register
func (o *ADC120_Type) SetADGSPCR_PGS(value uint16) {
	volatile.StoreUint16(&o.ADGSPCR.Reg, volatile.LoadUint16(&o.ADGSPCR.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADGSPCR_PGS() uint16 {
	return volatile.LoadUint16(&o.ADGSPCR.Reg) & 0x1
}
func (o *ADC120_Type) SetADGSPCR_GBRSCN(value uint16) {
	volatile.StoreUint16(&o.ADGSPCR.Reg, volatile.LoadUint16(&o.ADGSPCR.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADGSPCR_GBRSCN() uint16 {
	return (volatile.LoadUint16(&o.ADGSPCR.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADGSPCR_LGRRS(value uint16) {
	volatile.StoreUint16(&o.ADGSPCR.Reg, volatile.LoadUint16(&o.ADGSPCR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADGSPCR_LGRRS() uint16 {
	return (volatile.LoadUint16(&o.ADGSPCR.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADGSPCR_GBRP(value uint16) {
	volatile.StoreUint16(&o.ADGSPCR.Reg, volatile.LoadUint16(&o.ADGSPCR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADGSPCR_GBRP() uint16 {
	return (volatile.LoadUint16(&o.ADGSPCR.Reg) & 0x8000) >> 15
}

// ADC120.ADDBLDRA: A/D Data Duplexing Register A
func (o *ADC120_Type) SetADDBLDRA(value uint16) {
	volatile.StoreUint16(&o.ADDBLDRA.Reg, value)
}
func (o *ADC120_Type) GetADDBLDRA() uint16 {
	return volatile.LoadUint16(&o.ADDBLDRA.Reg)
}

// ADC120.ADDBLDRB: A/D Data Duplexing Register B
func (o *ADC120_Type) SetADDBLDRB(value uint16) {
	volatile.StoreUint16(&o.ADDBLDRB.Reg, value)
}
func (o *ADC120_Type) GetADDBLDRB() uint16 {
	return volatile.LoadUint16(&o.ADDBLDRB.Reg)
}

// ADC120.ADWINMON: A/D Compare Function Window A/B Status Monitor Register
func (o *ADC120_Type) SetADWINMON_MONCOMB(value uint8) {
	volatile.StoreUint8(&o.ADWINMON.Reg, volatile.LoadUint8(&o.ADWINMON.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADWINMON_MONCOMB() uint8 {
	return volatile.LoadUint8(&o.ADWINMON.Reg) & 0x1
}
func (o *ADC120_Type) SetADWINMON_MONCMPA(value uint8) {
	volatile.StoreUint8(&o.ADWINMON.Reg, volatile.LoadUint8(&o.ADWINMON.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADWINMON_MONCMPA() uint8 {
	return (volatile.LoadUint8(&o.ADWINMON.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADWINMON_MONCMPB(value uint8) {
	volatile.StoreUint8(&o.ADWINMON.Reg, volatile.LoadUint8(&o.ADWINMON.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADWINMON_MONCMPB() uint8 {
	return (volatile.LoadUint8(&o.ADWINMON.Reg) & 0x20) >> 5
}

// ADC120.ADCMPCR: A/D Compare Function Control Register
func (o *ADC120_Type) SetADCMPCR_CMPAB(value uint16) {
	volatile.StoreUint16(&o.ADCMPCR.Reg, volatile.LoadUint16(&o.ADCMPCR.Reg)&^(0x3)|value)
}
func (o *ADC120_Type) GetADCMPCR_CMPAB() uint16 {
	return volatile.LoadUint16(&o.ADCMPCR.Reg) & 0x3
}
func (o *ADC120_Type) SetADCMPCR_CMPBE(value uint16) {
	volatile.StoreUint16(&o.ADCMPCR.Reg, volatile.LoadUint16(&o.ADCMPCR.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCMPCR_CMPBE() uint16 {
	return (volatile.LoadUint16(&o.ADCMPCR.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCMPCR_CMPAE(value uint16) {
	volatile.StoreUint16(&o.ADCMPCR.Reg, volatile.LoadUint16(&o.ADCMPCR.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCMPCR_CMPAE() uint16 {
	return (volatile.LoadUint16(&o.ADCMPCR.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCMPCR_CMPBIE(value uint16) {
	volatile.StoreUint16(&o.ADCMPCR.Reg, volatile.LoadUint16(&o.ADCMPCR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADCMPCR_CMPBIE() uint16 {
	return (volatile.LoadUint16(&o.ADCMPCR.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADCMPCR_WCMPE(value uint16) {
	volatile.StoreUint16(&o.ADCMPCR.Reg, volatile.LoadUint16(&o.ADCMPCR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADCMPCR_WCMPE() uint16 {
	return (volatile.LoadUint16(&o.ADCMPCR.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADCMPCR_CMPAIE(value uint16) {
	volatile.StoreUint16(&o.ADCMPCR.Reg, volatile.LoadUint16(&o.ADCMPCR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCMPCR_CMPAIE() uint16 {
	return (volatile.LoadUint16(&o.ADCMPCR.Reg) & 0x8000) >> 15
}

// ADC120.ADCMPANSER: A/D Compare Function Window A Extended Input Select Register
func (o *ADC120_Type) SetADCMPANSER_CMPTSA(value uint8) {
	volatile.StoreUint8(&o.ADCMPANSER.Reg, volatile.LoadUint8(&o.ADCMPANSER.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPANSER_CMPTSA() uint8 {
	return volatile.LoadUint8(&o.ADCMPANSER.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPANSER_CMPOCA(value uint8) {
	volatile.StoreUint8(&o.ADCMPANSER.Reg, volatile.LoadUint8(&o.ADCMPANSER.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPANSER_CMPOCA() uint8 {
	return (volatile.LoadUint8(&o.ADCMPANSER.Reg) & 0x2) >> 1
}

// ADC120.ADCMPLER: A/D Compare Function Window A Extended Input Comparison Condition Setting Register
func (o *ADC120_Type) SetADCMPLER_CMPLTSA(value uint8) {
	volatile.StoreUint8(&o.ADCMPLER.Reg, volatile.LoadUint8(&o.ADCMPLER.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPLER_CMPLTSA() uint8 {
	return volatile.LoadUint8(&o.ADCMPLER.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPLER_CMPLOCA(value uint8) {
	volatile.StoreUint8(&o.ADCMPLER.Reg, volatile.LoadUint8(&o.ADCMPLER.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPLER_CMPLOCA() uint8 {
	return (volatile.LoadUint8(&o.ADCMPLER.Reg) & 0x2) >> 1
}

// ADC120.ADCMPANSR0: A/D Compare Function Window A Channel Select Register 0
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA00(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA00() uint16 {
	return volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA01(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA01() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA02(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA02() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA03(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA03() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA04(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA04() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA05(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA05() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA06(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA06() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA07(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA07() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA08(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA08() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA09(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA09() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA10(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA10() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA11(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA11() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA12(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA12() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA13(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA13() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA14(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA14() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADCMPANSR0_CMPCHA15(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR0.Reg, volatile.LoadUint16(&o.ADCMPANSR0.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCMPANSR0_CMPCHA15() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR0.Reg) & 0x8000) >> 15
}

// ADC120.ADCMPANSR1: A/D Compare Function Window A Channel Select Register 1
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA16(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA16() uint16 {
	return volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA17(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA17() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA18(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA18() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA19(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA19() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA20(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA20() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA21(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA21() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA22(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA22() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA23(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA23() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA24(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA24() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA25(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA25() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA26(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA26() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA27(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA27() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA28(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA28() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA29(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA29() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA30(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA30() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADCMPANSR1_CMPCHA31(value uint16) {
	volatile.StoreUint16(&o.ADCMPANSR1.Reg, volatile.LoadUint16(&o.ADCMPANSR1.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCMPANSR1_CMPCHA31() uint16 {
	return (volatile.LoadUint16(&o.ADCMPANSR1.Reg) & 0x8000) >> 15
}

// ADC120.ADCMPLR0: A/D Compare Function Window A Comparison Condition Setting Register 0
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA00(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA00() uint16 {
	return volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA01(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA01() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA02(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA02() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA03(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA03() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA04(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA04() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA05(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA05() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA06(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA06() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA07(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA07() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA08(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA08() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA09(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA09() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA10(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA10() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA11(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA11() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA12(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA12() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA13(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA13() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA14(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA14() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADCMPLR0_CMPLCHA15(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR0.Reg, volatile.LoadUint16(&o.ADCMPLR0.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCMPLR0_CMPLCHA15() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR0.Reg) & 0x8000) >> 15
}

// ADC120.ADCMPLR1: A/D Compare Function Window A Comparison Condition Setting Register 1
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA16(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA16() uint16 {
	return volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA17(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA17() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA18(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA18() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA19(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA19() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA20(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA20() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA21(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA21() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA22(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA22() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA23(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA23() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA24(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA24() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA25(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA25() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA26(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA26() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA27(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA27() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA28(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA28() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA29(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA29() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA30(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA30() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADCMPLR1_CMPLCHA31(value uint16) {
	volatile.StoreUint16(&o.ADCMPLR1.Reg, volatile.LoadUint16(&o.ADCMPLR1.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCMPLR1_CMPLCHA31() uint16 {
	return (volatile.LoadUint16(&o.ADCMPLR1.Reg) & 0x8000) >> 15
}

// ADC120.ADCMPSR0: A/D Compare Function Window A Channel Status Register 0
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA00(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA00() uint16 {
	return volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA01(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA01() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA02(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA02() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA03(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA03() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA04(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA04() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA05(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA05() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA06(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA06() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA07(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA07() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA08(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA08() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA09(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA09() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA10(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA10() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA11(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA11() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA12(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA12() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA13(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA13() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA14(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA14() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADCMPSR0_CMPSTCHA15(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR0.Reg, volatile.LoadUint16(&o.ADCMPSR0.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCMPSR0_CMPSTCHA15() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR0.Reg) & 0x8000) >> 15
}

// ADC120.ADCMPSR1: A/D Compare Function Window A Channel Status Register1
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA16(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA16() uint16 {
	return volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA17(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA17() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x2) >> 1
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA18(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x4)|value<<2)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA18() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x4) >> 2
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA19(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x8)|value<<3)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA19() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x8) >> 3
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA20(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA20() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x10) >> 4
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA21(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x20)|value<<5)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA21() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x20) >> 5
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA22(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x40)|value<<6)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA22() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x40) >> 6
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA23(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA23() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x80) >> 7
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA24(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x100)|value<<8)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA24() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x100) >> 8
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA25(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x200)|value<<9)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA25() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x200) >> 9
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA26(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x400)|value<<10)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA26() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x400) >> 10
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA27(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x800)|value<<11)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA27() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x800) >> 11
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA28(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x1000)|value<<12)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA28() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x1000) >> 12
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA29(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x2000)|value<<13)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA29() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x2000) >> 13
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA30(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x4000)|value<<14)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA30() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x4000) >> 14
}
func (o *ADC120_Type) SetADCMPSR1_CMPSTCHA31(value uint16) {
	volatile.StoreUint16(&o.ADCMPSR1.Reg, volatile.LoadUint16(&o.ADCMPSR1.Reg)&^(0x8000)|value<<15)
}
func (o *ADC120_Type) GetADCMPSR1_CMPSTCHA31() uint16 {
	return (volatile.LoadUint16(&o.ADCMPSR1.Reg) & 0x8000) >> 15
}

// ADC120.ADCMPSER: A/D Compare Function Window A Extended Input Channel Status Register
func (o *ADC120_Type) SetADCMPSER_CMPSTTSA(value uint8) {
	volatile.StoreUint8(&o.ADCMPSER.Reg, volatile.LoadUint8(&o.ADCMPSER.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPSER_CMPSTTSA() uint8 {
	return volatile.LoadUint8(&o.ADCMPSER.Reg) & 0x1
}
func (o *ADC120_Type) SetADCMPSER_CMPSTOCA(value uint8) {
	volatile.StoreUint8(&o.ADCMPSER.Reg, volatile.LoadUint8(&o.ADCMPSER.Reg)&^(0x2)|value<<1)
}
func (o *ADC120_Type) GetADCMPSER_CMPSTOCA() uint8 {
	return (volatile.LoadUint8(&o.ADCMPSER.Reg) & 0x2) >> 1
}

// ADC120.ADCMPBNSR: A/D Compare Function Window B Channel Select Register
func (o *ADC120_Type) SetADCMPBNSR_CMPCHB(value uint8) {
	volatile.StoreUint8(&o.ADCMPBNSR.Reg, volatile.LoadUint8(&o.ADCMPBNSR.Reg)&^(0x3f)|value)
}
func (o *ADC120_Type) GetADCMPBNSR_CMPCHB() uint8 {
	return volatile.LoadUint8(&o.ADCMPBNSR.Reg) & 0x3f
}
func (o *ADC120_Type) SetADCMPBNSR_CMPLB(value uint8) {
	volatile.StoreUint8(&o.ADCMPBNSR.Reg, volatile.LoadUint8(&o.ADCMPBNSR.Reg)&^(0x80)|value<<7)
}
func (o *ADC120_Type) GetADCMPBNSR_CMPLB() uint8 {
	return (volatile.LoadUint8(&o.ADCMPBNSR.Reg) & 0x80) >> 7
}

// ADC120.ADCMPBSR: A/D Compare Function Window B Status Register
func (o *ADC120_Type) SetADCMPBSR_CMPSTB(value uint8) {
	volatile.StoreUint8(&o.ADCMPBSR.Reg, volatile.LoadUint8(&o.ADCMPBSR.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADCMPBSR_CMPSTB() uint8 {
	return volatile.LoadUint8(&o.ADCMPBSR.Reg) & 0x1
}

// ADC120.ADBUF0: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF0(value uint16) {
	volatile.StoreUint16(&o.ADBUF0.Reg, value)
}
func (o *ADC120_Type) GetADBUF0() uint16 {
	return volatile.LoadUint16(&o.ADBUF0.Reg)
}

// ADC120.ADBUF1: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF1(value uint16) {
	volatile.StoreUint16(&o.ADBUF1.Reg, value)
}
func (o *ADC120_Type) GetADBUF1() uint16 {
	return volatile.LoadUint16(&o.ADBUF1.Reg)
}

// ADC120.ADBUF2: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF2(value uint16) {
	volatile.StoreUint16(&o.ADBUF2.Reg, value)
}
func (o *ADC120_Type) GetADBUF2() uint16 {
	return volatile.LoadUint16(&o.ADBUF2.Reg)
}

// ADC120.ADBUF3: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF3(value uint16) {
	volatile.StoreUint16(&o.ADBUF3.Reg, value)
}
func (o *ADC120_Type) GetADBUF3() uint16 {
	return volatile.LoadUint16(&o.ADBUF3.Reg)
}

// ADC120.ADBUF4: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF4(value uint16) {
	volatile.StoreUint16(&o.ADBUF4.Reg, value)
}
func (o *ADC120_Type) GetADBUF4() uint16 {
	return volatile.LoadUint16(&o.ADBUF4.Reg)
}

// ADC120.ADBUF5: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF5(value uint16) {
	volatile.StoreUint16(&o.ADBUF5.Reg, value)
}
func (o *ADC120_Type) GetADBUF5() uint16 {
	return volatile.LoadUint16(&o.ADBUF5.Reg)
}

// ADC120.ADBUF6: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF6(value uint16) {
	volatile.StoreUint16(&o.ADBUF6.Reg, value)
}
func (o *ADC120_Type) GetADBUF6() uint16 {
	return volatile.LoadUint16(&o.ADBUF6.Reg)
}

// ADC120.ADBUF7: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF7(value uint16) {
	volatile.StoreUint16(&o.ADBUF7.Reg, value)
}
func (o *ADC120_Type) GetADBUF7() uint16 {
	return volatile.LoadUint16(&o.ADBUF7.Reg)
}

// ADC120.ADBUF8: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF8(value uint16) {
	volatile.StoreUint16(&o.ADBUF8.Reg, value)
}
func (o *ADC120_Type) GetADBUF8() uint16 {
	return volatile.LoadUint16(&o.ADBUF8.Reg)
}

// ADC120.ADBUF9: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF9(value uint16) {
	volatile.StoreUint16(&o.ADBUF9.Reg, value)
}
func (o *ADC120_Type) GetADBUF9() uint16 {
	return volatile.LoadUint16(&o.ADBUF9.Reg)
}

// ADC120.ADBUF10: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF10(value uint16) {
	volatile.StoreUint16(&o.ADBUF10.Reg, value)
}
func (o *ADC120_Type) GetADBUF10() uint16 {
	return volatile.LoadUint16(&o.ADBUF10.Reg)
}

// ADC120.ADBUF11: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF11(value uint16) {
	volatile.StoreUint16(&o.ADBUF11.Reg, value)
}
func (o *ADC120_Type) GetADBUF11() uint16 {
	return volatile.LoadUint16(&o.ADBUF11.Reg)
}

// ADC120.ADBUF12: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF12(value uint16) {
	volatile.StoreUint16(&o.ADBUF12.Reg, value)
}
func (o *ADC120_Type) GetADBUF12() uint16 {
	return volatile.LoadUint16(&o.ADBUF12.Reg)
}

// ADC120.ADBUF13: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF13(value uint16) {
	volatile.StoreUint16(&o.ADBUF13.Reg, value)
}
func (o *ADC120_Type) GetADBUF13() uint16 {
	return volatile.LoadUint16(&o.ADBUF13.Reg)
}

// ADC120.ADBUF14: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF14(value uint16) {
	volatile.StoreUint16(&o.ADBUF14.Reg, value)
}
func (o *ADC120_Type) GetADBUF14() uint16 {
	return volatile.LoadUint16(&o.ADBUF14.Reg)
}

// ADC120.ADBUF15: A/D Data Buffer Registers %s
func (o *ADC120_Type) SetADBUF15(value uint16) {
	volatile.StoreUint16(&o.ADBUF15.Reg, value)
}
func (o *ADC120_Type) GetADBUF15() uint16 {
	return volatile.LoadUint16(&o.ADBUF15.Reg)
}

// ADC120.ADBUFEN: A/D Data Buffer Enable Register
func (o *ADC120_Type) SetADBUFEN_BUFEN(value uint8) {
	volatile.StoreUint8(&o.ADBUFEN.Reg, volatile.LoadUint8(&o.ADBUFEN.Reg)&^(0x1)|value)
}
func (o *ADC120_Type) GetADBUFEN_BUFEN() uint8 {
	return volatile.LoadUint8(&o.ADBUFEN.Reg) & 0x1
}

// ADC120.ADBUFPTR: A/D Data Buffer Pointer Register
func (o *ADC120_Type) SetADBUFPTR_BUFPTR(value uint8) {
	volatile.StoreUint8(&o.ADBUFPTR.Reg, volatile.LoadUint8(&o.ADBUFPTR.Reg)&^(0xf)|value)
}
func (o *ADC120_Type) GetADBUFPTR_BUFPTR() uint8 {
	return volatile.LoadUint8(&o.ADBUFPTR.Reg) & 0xf
}
func (o *ADC120_Type) SetADBUFPTR_PTROVF(value uint8) {
	volatile.StoreUint8(&o.ADBUFPTR.Reg, volatile.LoadUint8(&o.ADBUFPTR.Reg)&^(0x10)|value<<4)
}
func (o *ADC120_Type) GetADBUFPTR_PTROVF() uint8 {
	return (volatile.LoadUint8(&o.ADBUFPTR.Reg) & 0x10) >> 4
}

// ADC120.ADSSTRL: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTRL(value uint8) {
	volatile.StoreUint8(&o.ADSSTRL.Reg, value)
}
func (o *ADC120_Type) GetADSSTRL() uint8 {
	return volatile.LoadUint8(&o.ADSSTRL.Reg)
}

// ADC120.ADSSTRT: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTRT(value uint8) {
	volatile.StoreUint8(&o.ADSSTRT.Reg, value)
}
func (o *ADC120_Type) GetADSSTRT() uint8 {
	return volatile.LoadUint8(&o.ADSSTRT.Reg)
}

// ADC120.ADSSTRO: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTRO(value uint8) {
	volatile.StoreUint8(&o.ADSSTRO.Reg, value)
}
func (o *ADC120_Type) GetADSSTRO() uint8 {
	return volatile.LoadUint8(&o.ADSSTRO.Reg)
}

// ADC120.ADSSTR0: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR0(value uint8) {
	volatile.StoreUint8(&o.ADSSTR0.Reg, value)
}
func (o *ADC120_Type) GetADSSTR0() uint8 {
	return volatile.LoadUint8(&o.ADSSTR0.Reg)
}

// ADC120.ADSSTR1: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR1(value uint8) {
	volatile.StoreUint8(&o.ADSSTR1.Reg, value)
}
func (o *ADC120_Type) GetADSSTR1() uint8 {
	return volatile.LoadUint8(&o.ADSSTR1.Reg)
}

// ADC120.ADSSTR2: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR2(value uint8) {
	volatile.StoreUint8(&o.ADSSTR2.Reg, value)
}
func (o *ADC120_Type) GetADSSTR2() uint8 {
	return volatile.LoadUint8(&o.ADSSTR2.Reg)
}

// ADC120.ADSSTR4: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR4(value uint8) {
	volatile.StoreUint8(&o.ADSSTR4.Reg, value)
}
func (o *ADC120_Type) GetADSSTR4() uint8 {
	return volatile.LoadUint8(&o.ADSSTR4.Reg)
}

// ADC120.ADSSTR5: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR5(value uint8) {
	volatile.StoreUint8(&o.ADSSTR5.Reg, value)
}
func (o *ADC120_Type) GetADSSTR5() uint8 {
	return volatile.LoadUint8(&o.ADSSTR5.Reg)
}

// ADC120.ADSSTR6: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR6(value uint8) {
	volatile.StoreUint8(&o.ADSSTR6.Reg, value)
}
func (o *ADC120_Type) GetADSSTR6() uint8 {
	return volatile.LoadUint8(&o.ADSSTR6.Reg)
}

// ADC120.ADSSTR7: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR7(value uint8) {
	volatile.StoreUint8(&o.ADSSTR7.Reg, value)
}
func (o *ADC120_Type) GetADSSTR7() uint8 {
	return volatile.LoadUint8(&o.ADSSTR7.Reg)
}

// ADC120.ADSSTR8: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR8(value uint8) {
	volatile.StoreUint8(&o.ADSSTR8.Reg, value)
}
func (o *ADC120_Type) GetADSSTR8() uint8 {
	return volatile.LoadUint8(&o.ADSSTR8.Reg)
}

// ADC120.ADSSTR11: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR11(value uint8) {
	volatile.StoreUint8(&o.ADSSTR11.Reg, value)
}
func (o *ADC120_Type) GetADSSTR11() uint8 {
	return volatile.LoadUint8(&o.ADSSTR11.Reg)
}

// ADC120.ADSSTR12: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR12(value uint8) {
	volatile.StoreUint8(&o.ADSSTR12.Reg, value)
}
func (o *ADC120_Type) GetADSSTR12() uint8 {
	return volatile.LoadUint8(&o.ADSSTR12.Reg)
}

// ADC120.ADSSTR13: A/D Sampling State Register
func (o *ADC120_Type) SetADSSTR13(value uint8) {
	volatile.StoreUint8(&o.ADSSTR13.Reg, value)
}
func (o *ADC120_Type) GetADSSTR13() uint8 {
	return volatile.LoadUint8(&o.ADSSTR13.Reg)
}

// 12-bit D/A converter
type DAC12_Type struct {
	DADR0   volatile.Register16 // 0x0
	DADR1   volatile.Register16 // 0x2
	DACR    volatile.Register8  // 0x4
	DADPR   volatile.Register8  // 0x5
	DAADSCR volatile.Register8  // 0x6
	_       byte
	DAAMPCR volatile.Register8 // 0x8
	_       [19]byte
	DAASWCR volatile.Register8 // 0x1C
	_       [4259]byte
	DAADUSR volatile.Register8 // 0x10C0
}

// DAC12.DACR: D/A Control Register
func (o *DAC12_Type) SetDACR_DAE(value uint8) {
	volatile.StoreUint8(&o.DACR.Reg, volatile.LoadUint8(&o.DACR.Reg)&^(0x20)|value<<5)
}
func (o *DAC12_Type) GetDACR_DAE() uint8 {
	return (volatile.LoadUint8(&o.DACR.Reg) & 0x20) >> 5
}
func (o *DAC12_Type) SetDACR_DAOE0(value uint8) {
	volatile.StoreUint8(&o.DACR.Reg, volatile.LoadUint8(&o.DACR.Reg)&^(0x40)|value<<6)
}
func (o *DAC12_Type) GetDACR_DAOE0() uint8 {
	return (volatile.LoadUint8(&o.DACR.Reg) & 0x40) >> 6
}
func (o *DAC12_Type) SetDACR_DAOE1(value uint8) {
	volatile.StoreUint8(&o.DACR.Reg, volatile.LoadUint8(&o.DACR.Reg)&^(0x80)|value<<7)
}
func (o *DAC12_Type) GetDACR_DAOE1() uint8 {
	return (volatile.LoadUint8(&o.DACR.Reg) & 0x80) >> 7
}

// DAC12.DADPR: DADRn Format Select Register
func (o *DAC12_Type) SetDADPR_DPSEL(value uint8) {
	volatile.StoreUint8(&o.DADPR.Reg, volatile.LoadUint8(&o.DADPR.Reg)&^(0x80)|value<<7)
}
func (o *DAC12_Type) GetDADPR_DPSEL() uint8 {
	return (volatile.LoadUint8(&o.DADPR.Reg) & 0x80) >> 7
}

// DAC12.DAADSCR: D/A A/D Synchronous Start Control Register
func (o *DAC12_Type) SetDAADSCR_DAADST(value uint8) {
	volatile.StoreUint8(&o.DAADSCR.Reg, volatile.LoadUint8(&o.DAADSCR.Reg)&^(0x80)|value<<7)
}
func (o *DAC12_Type) GetDAADSCR_DAADST() uint8 {
	return (volatile.LoadUint8(&o.DAADSCR.Reg) & 0x80) >> 7
}

// DAC12.DAAMPCR: D/A Output Amplifier Control Register
func (o *DAC12_Type) SetDAAMPCR_DAAMP0(value uint8) {
	volatile.StoreUint8(&o.DAAMPCR.Reg, volatile.LoadUint8(&o.DAAMPCR.Reg)&^(0x40)|value<<6)
}
func (o *DAC12_Type) GetDAAMPCR_DAAMP0() uint8 {
	return (volatile.LoadUint8(&o.DAAMPCR.Reg) & 0x40) >> 6
}
func (o *DAC12_Type) SetDAAMPCR_DAAMP1(value uint8) {
	volatile.StoreUint8(&o.DAAMPCR.Reg, volatile.LoadUint8(&o.DAAMPCR.Reg)&^(0x80)|value<<7)
}
func (o *DAC12_Type) GetDAAMPCR_DAAMP1() uint8 {
	return (volatile.LoadUint8(&o.DAAMPCR.Reg) & 0x80) >> 7
}

// DAC12.DAASWCR: D/A Amplifier Stabilization Wait Control Register
func (o *DAC12_Type) SetDAASWCR_DAASW0(value uint8) {
	volatile.StoreUint8(&o.DAASWCR.Reg, volatile.LoadUint8(&o.DAASWCR.Reg)&^(0x40)|value<<6)
}
func (o *DAC12_Type) GetDAASWCR_DAASW0() uint8 {
	return (volatile.LoadUint8(&o.DAASWCR.Reg) & 0x40) >> 6
}
func (o *DAC12_Type) SetDAASWCR_DAASW1(value uint8) {
	volatile.StoreUint8(&o.DAASWCR.Reg, volatile.LoadUint8(&o.DAASWCR.Reg)&^(0x80)|value<<7)
}
func (o *DAC12_Type) GetDAASWCR_DAASW1() uint8 {
	return (volatile.LoadUint8(&o.DAASWCR.Reg) & 0x80) >> 7
}

// DAC12.DAADUSR: D/A A/D Synchronous Unit Select Register
func (o *DAC12_Type) SetDAADUSR_AMADSEL0(value uint8) {
	volatile.StoreUint8(&o.DAADUSR.Reg, volatile.LoadUint8(&o.DAADUSR.Reg)&^(0x1)|value)
}
func (o *DAC12_Type) GetDAADUSR_AMADSEL0() uint8 {
	return volatile.LoadUint8(&o.DAADUSR.Reg) & 0x1
}

// Temperature Sensor Calibration Data
type TSD_Type struct {
	_     [380]byte
	TSCDR volatile.Register32 // 0x17C
}

// TSD.TSCDR: Temperature Sensor Calibration Data Register
func (o *TSD_Type) SetTSCDR(value uint32) {
	volatile.StoreUint32(&o.TSCDR.Reg, volatile.LoadUint32(&o.TSCDR.Reg)&^(0xffff)|value)
}
func (o *TSD_Type) GetTSCDR() uint32 {
	return volatile.LoadUint32(&o.TSCDR.Reg) & 0xffff
}

// Data Flash
type FLAD_Type struct {
	_      [64]byte
	FCKMHZ volatile.Register8 // 0x40
}

// FLAD.FCKMHZ: Data Flash Access Frequency Register
func (o *FLAD_Type) SetFCKMHZ(value uint8) {
	volatile.StoreUint8(&o.FCKMHZ.Reg, value)
}
func (o *FLAD_Type) GetFCKMHZ() uint8 {
	return volatile.LoadUint8(&o.FCKMHZ.Reg)
}

// Flash/CPU Interface
type FACI_Type struct {
	_        [16]byte
	FASTAT   volatile.Register8 // 0x10
	_        [3]byte
	FAEINT   volatile.Register8 // 0x14
	_        [3]byte
	FRDYIE   volatile.Register8 // 0x18
	_        [23]byte
	FSADDR   volatile.Register32 // 0x30
	FEADDR   volatile.Register32 // 0x34
	_        [12]byte
	FMEPROT  volatile.Register16 // 0x44
	_        [54]byte
	FBPROT1  volatile.Register16 // 0x7C
	_        [2]byte
	FSTATR   volatile.Register32 // 0x80
	FENTRYR  volatile.Register16 // 0x84
	_        [6]byte
	FSUINITR volatile.Register16 // 0x8C
	_        [18]byte
	FCMDR    volatile.Register16 // 0xA0
	_        [46]byte
	FBCCNT   volatile.Register8 // 0xD0
	_        [3]byte
	FBCSTAT  volatile.Register8 // 0xD4
	_        [3]byte
	FPSADDR  volatile.Register32 // 0xD8
	FSUASMON volatile.Register32 // 0xDC
	FCPSR    volatile.Register16 // 0xE0
	_        [2]byte
	FPCKAR   volatile.Register16 // 0xE4
	_        [2]byte
	FSUACR   volatile.Register16 // 0xE8
}

// FACI.FASTAT: Flash Access Status Register
func (o *FACI_Type) SetFASTAT_DFAE(value uint8) {
	volatile.StoreUint8(&o.FASTAT.Reg, volatile.LoadUint8(&o.FASTAT.Reg)&^(0x8)|value<<3)
}
func (o *FACI_Type) GetFASTAT_DFAE() uint8 {
	return (volatile.LoadUint8(&o.FASTAT.Reg) & 0x8) >> 3
}
func (o *FACI_Type) SetFASTAT_CMDLK(value uint8) {
	volatile.StoreUint8(&o.FASTAT.Reg, volatile.LoadUint8(&o.FASTAT.Reg)&^(0x10)|value<<4)
}
func (o *FACI_Type) GetFASTAT_CMDLK() uint8 {
	return (volatile.LoadUint8(&o.FASTAT.Reg) & 0x10) >> 4
}
func (o *FACI_Type) SetFASTAT_CFAE(value uint8) {
	volatile.StoreUint8(&o.FASTAT.Reg, volatile.LoadUint8(&o.FASTAT.Reg)&^(0x80)|value<<7)
}
func (o *FACI_Type) GetFASTAT_CFAE() uint8 {
	return (volatile.LoadUint8(&o.FASTAT.Reg) & 0x80) >> 7
}

// FACI.FAEINT: Flash Access Error Interrupt Enable Register
func (o *FACI_Type) SetFAEINT_DFAEIE(value uint8) {
	volatile.StoreUint8(&o.FAEINT.Reg, volatile.LoadUint8(&o.FAEINT.Reg)&^(0x8)|value<<3)
}
func (o *FACI_Type) GetFAEINT_DFAEIE() uint8 {
	return (volatile.LoadUint8(&o.FAEINT.Reg) & 0x8) >> 3
}
func (o *FACI_Type) SetFAEINT_CMDLKIE(value uint8) {
	volatile.StoreUint8(&o.FAEINT.Reg, volatile.LoadUint8(&o.FAEINT.Reg)&^(0x10)|value<<4)
}
func (o *FACI_Type) GetFAEINT_CMDLKIE() uint8 {
	return (volatile.LoadUint8(&o.FAEINT.Reg) & 0x10) >> 4
}
func (o *FACI_Type) SetFAEINT_CFAEIE(value uint8) {
	volatile.StoreUint8(&o.FAEINT.Reg, volatile.LoadUint8(&o.FAEINT.Reg)&^(0x80)|value<<7)
}
func (o *FACI_Type) GetFAEINT_CFAEIE() uint8 {
	return (volatile.LoadUint8(&o.FAEINT.Reg) & 0x80) >> 7
}

// FACI.FRDYIE: Flash Ready Interrupt Enable Register
func (o *FACI_Type) SetFRDYIE(value uint8) {
	volatile.StoreUint8(&o.FRDYIE.Reg, volatile.LoadUint8(&o.FRDYIE.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFRDYIE() uint8 {
	return volatile.LoadUint8(&o.FRDYIE.Reg) & 0x1
}

// FACI.FEADDR: FACI Command End Address Register
func (o *FACI_Type) SetFEADDR(value uint32) {
	volatile.StoreUint32(&o.FEADDR.Reg, value)
}
func (o *FACI_Type) GetFEADDR() uint32 {
	return volatile.LoadUint32(&o.FEADDR.Reg)
}

// FACI.FMEPROT: Flash P/E Mode Entry Protection Register
func (o *FACI_Type) SetFMEPROT_CEPROT(value uint16) {
	volatile.StoreUint16(&o.FMEPROT.Reg, volatile.LoadUint16(&o.FMEPROT.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFMEPROT_CEPROT() uint16 {
	return volatile.LoadUint16(&o.FMEPROT.Reg) & 0x1
}
func (o *FACI_Type) SetFMEPROT_KEY(value uint16) {
	volatile.StoreUint16(&o.FMEPROT.Reg, volatile.LoadUint16(&o.FMEPROT.Reg)&^(0xff00)|value<<8)
}
func (o *FACI_Type) GetFMEPROT_KEY() uint16 {
	return (volatile.LoadUint16(&o.FMEPROT.Reg) & 0xff00) >> 8
}

// FACI.FBPROT1: Flash Block Protection for Secure Register
func (o *FACI_Type) SetFBPROT1_BPCN1(value uint16) {
	volatile.StoreUint16(&o.FBPROT1.Reg, volatile.LoadUint16(&o.FBPROT1.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFBPROT1_BPCN1() uint16 {
	return volatile.LoadUint16(&o.FBPROT1.Reg) & 0x1
}
func (o *FACI_Type) SetFBPROT1_KEY(value uint16) {
	volatile.StoreUint16(&o.FBPROT1.Reg, volatile.LoadUint16(&o.FBPROT1.Reg)&^(0xff00)|value<<8)
}
func (o *FACI_Type) GetFBPROT1_KEY() uint16 {
	return (volatile.LoadUint16(&o.FBPROT1.Reg) & 0xff00) >> 8
}

// FACI.FSTATR: Flash Status Register
func (o *FACI_Type) SetFSTATR_FLWEERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x40)|value<<6)
}
func (o *FACI_Type) GetFSTATR_FLWEERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x40) >> 6
}
func (o *FACI_Type) SetFSTATR_PRGSPD(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x100)|value<<8)
}
func (o *FACI_Type) GetFSTATR_PRGSPD() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x100) >> 8
}
func (o *FACI_Type) SetFSTATR_ERSSPD(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x200)|value<<9)
}
func (o *FACI_Type) GetFSTATR_ERSSPD() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x200) >> 9
}
func (o *FACI_Type) SetFSTATR_DBFULL(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x400)|value<<10)
}
func (o *FACI_Type) GetFSTATR_DBFULL() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x400) >> 10
}
func (o *FACI_Type) SetFSTATR_SUSRDY(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x800)|value<<11)
}
func (o *FACI_Type) GetFSTATR_SUSRDY() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x800) >> 11
}
func (o *FACI_Type) SetFSTATR_PRGERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x1000)|value<<12)
}
func (o *FACI_Type) GetFSTATR_PRGERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x1000) >> 12
}
func (o *FACI_Type) SetFSTATR_ERSERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x2000)|value<<13)
}
func (o *FACI_Type) GetFSTATR_ERSERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x2000) >> 13
}
func (o *FACI_Type) SetFSTATR_ILGLERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x4000)|value<<14)
}
func (o *FACI_Type) GetFSTATR_ILGLERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x4000) >> 14
}
func (o *FACI_Type) SetFSTATR_FRDY(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x8000)|value<<15)
}
func (o *FACI_Type) GetFSTATR_FRDY() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x8000) >> 15
}
func (o *FACI_Type) SetFSTATR_OTERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x100000)|value<<20)
}
func (o *FACI_Type) GetFSTATR_OTERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x100000) >> 20
}
func (o *FACI_Type) SetFSTATR_SECERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x200000)|value<<21)
}
func (o *FACI_Type) GetFSTATR_SECERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x200000) >> 21
}
func (o *FACI_Type) SetFSTATR_FESETERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x400000)|value<<22)
}
func (o *FACI_Type) GetFSTATR_FESETERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x400000) >> 22
}
func (o *FACI_Type) SetFSTATR_ILGCOMERR(value uint32) {
	volatile.StoreUint32(&o.FSTATR.Reg, volatile.LoadUint32(&o.FSTATR.Reg)&^(0x800000)|value<<23)
}
func (o *FACI_Type) GetFSTATR_ILGCOMERR() uint32 {
	return (volatile.LoadUint32(&o.FSTATR.Reg) & 0x800000) >> 23
}

// FACI.FENTRYR: Flash P/E Mode Entry Register
func (o *FACI_Type) SetFENTRYR_FENTRYC(value uint16) {
	volatile.StoreUint16(&o.FENTRYR.Reg, volatile.LoadUint16(&o.FENTRYR.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFENTRYR_FENTRYC() uint16 {
	return volatile.LoadUint16(&o.FENTRYR.Reg) & 0x1
}
func (o *FACI_Type) SetFENTRYR_FENTRYD(value uint16) {
	volatile.StoreUint16(&o.FENTRYR.Reg, volatile.LoadUint16(&o.FENTRYR.Reg)&^(0x80)|value<<7)
}
func (o *FACI_Type) GetFENTRYR_FENTRYD() uint16 {
	return (volatile.LoadUint16(&o.FENTRYR.Reg) & 0x80) >> 7
}
func (o *FACI_Type) SetFENTRYR_KEY(value uint16) {
	volatile.StoreUint16(&o.FENTRYR.Reg, volatile.LoadUint16(&o.FENTRYR.Reg)&^(0xff00)|value<<8)
}
func (o *FACI_Type) GetFENTRYR_KEY() uint16 {
	return (volatile.LoadUint16(&o.FENTRYR.Reg) & 0xff00) >> 8
}

// FACI.FSUINITR: Flash Sequencer Setup Initialization Register
func (o *FACI_Type) SetFSUINITR_SUINIT(value uint16) {
	volatile.StoreUint16(&o.FSUINITR.Reg, volatile.LoadUint16(&o.FSUINITR.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFSUINITR_SUINIT() uint16 {
	return volatile.LoadUint16(&o.FSUINITR.Reg) & 0x1
}
func (o *FACI_Type) SetFSUINITR_KEY(value uint16) {
	volatile.StoreUint16(&o.FSUINITR.Reg, volatile.LoadUint16(&o.FSUINITR.Reg)&^(0xff00)|value<<8)
}
func (o *FACI_Type) GetFSUINITR_KEY() uint16 {
	return (volatile.LoadUint16(&o.FSUINITR.Reg) & 0xff00) >> 8
}

// FACI.FCMDR: FACI Command Register
func (o *FACI_Type) SetFCMDR_PCMDR(value uint16) {
	volatile.StoreUint16(&o.FCMDR.Reg, volatile.LoadUint16(&o.FCMDR.Reg)&^(0xff)|value)
}
func (o *FACI_Type) GetFCMDR_PCMDR() uint16 {
	return volatile.LoadUint16(&o.FCMDR.Reg) & 0xff
}
func (o *FACI_Type) SetFCMDR_CMDR(value uint16) {
	volatile.StoreUint16(&o.FCMDR.Reg, volatile.LoadUint16(&o.FCMDR.Reg)&^(0xff00)|value<<8)
}
func (o *FACI_Type) GetFCMDR_CMDR() uint16 {
	return (volatile.LoadUint16(&o.FCMDR.Reg) & 0xff00) >> 8
}

// FACI.FBCCNT: Blank Check Control Register
func (o *FACI_Type) SetFBCCNT_BCDIR(value uint8) {
	volatile.StoreUint8(&o.FBCCNT.Reg, volatile.LoadUint8(&o.FBCCNT.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFBCCNT_BCDIR() uint8 {
	return volatile.LoadUint8(&o.FBCCNT.Reg) & 0x1
}

// FACI.FBCSTAT: Blank Check Status Register
func (o *FACI_Type) SetFBCSTAT_BCST(value uint8) {
	volatile.StoreUint8(&o.FBCSTAT.Reg, volatile.LoadUint8(&o.FBCSTAT.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFBCSTAT_BCST() uint8 {
	return volatile.LoadUint8(&o.FBCSTAT.Reg) & 0x1
}

// FACI.FPSADDR: Data Flash Programming Start Address Register
func (o *FACI_Type) SetFPSADDR_PSADR(value uint32) {
	volatile.StoreUint32(&o.FPSADDR.Reg, volatile.LoadUint32(&o.FPSADDR.Reg)&^(0x1ffff)|value)
}
func (o *FACI_Type) GetFPSADDR_PSADR() uint32 {
	return volatile.LoadUint32(&o.FPSADDR.Reg) & 0x1ffff
}

// FACI.FSUASMON: Flash Startup Area Select Monitor Register
func (o *FACI_Type) SetFSUASMON_FSPR(value uint32) {
	volatile.StoreUint32(&o.FSUASMON.Reg, volatile.LoadUint32(&o.FSUASMON.Reg)&^(0x8000)|value<<15)
}
func (o *FACI_Type) GetFSUASMON_FSPR() uint32 {
	return (volatile.LoadUint32(&o.FSUASMON.Reg) & 0x8000) >> 15
}
func (o *FACI_Type) SetFSUASMON_BTFLG(value uint32) {
	volatile.StoreUint32(&o.FSUASMON.Reg, volatile.LoadUint32(&o.FSUASMON.Reg)&^(0x80000000)|value<<31)
}
func (o *FACI_Type) GetFSUASMON_BTFLG() uint32 {
	return (volatile.LoadUint32(&o.FSUASMON.Reg) & 0x80000000) >> 31
}

// FACI.FCPSR: Flash Sequencer Processing Switching Register
func (o *FACI_Type) SetFCPSR_ESUSPMD(value uint16) {
	volatile.StoreUint16(&o.FCPSR.Reg, volatile.LoadUint16(&o.FCPSR.Reg)&^(0x1)|value)
}
func (o *FACI_Type) GetFCPSR_ESUSPMD() uint16 {
	return volatile.LoadUint16(&o.FCPSR.Reg) & 0x1
}

// FACI.FPCKAR: Flash Sequencer Processing Clock Notification Register
func (o *FACI_Type) SetFPCKAR_PCKA(value uint16) {
	volatile.StoreUint16(&o.FPCKAR.Reg, volatile.LoadUint16(&o.FPCKAR.Reg)&^(0xff)|value)
}
func (o *FACI_Type) GetFPCKAR_PCKA() uint16 {
	return volatile.LoadUint16(&o.FPCKAR.Reg) & 0xff
}
func (o *FACI_Type) SetFPCKAR_KEY(value uint16) {
	volatile.StoreUint16(&o.FPCKAR.Reg, volatile.LoadUint16(&o.FPCKAR.Reg)&^(0xff00)|value<<8)
}
func (o *FACI_Type) GetFPCKAR_KEY() uint16 {
	return (volatile.LoadUint16(&o.FPCKAR.Reg) & 0xff00) >> 8
}

// FACI.FSUACR: Flash Startup Area Control Register
func (o *FACI_Type) SetFSUACR_SAS(value uint16) {
	volatile.StoreUint16(&o.FSUACR.Reg, volatile.LoadUint16(&o.FSUACR.Reg)&^(0x3)|value)
}
func (o *FACI_Type) GetFSUACR_SAS() uint16 {
	return volatile.LoadUint16(&o.FSUACR.Reg) & 0x3
}
func (o *FACI_Type) SetFSUACR_KEY(value uint16) {
	volatile.StoreUint16(&o.FSUACR.Reg, volatile.LoadUint16(&o.FSUACR.Reg)&^(0xff00)|value<<8)
}
func (o *FACI_Type) GetFSUACR_KEY() uint16 {
	return (volatile.LoadUint16(&o.FSUACR.Reg) & 0xff00) >> 8
}

// Quad Serial Peripheral Interface
type QSPI_Type struct {
	SFMSMD  volatile.Register32 // 0x0
	SFMSSC  volatile.Register32 // 0x4
	SFMSKC  volatile.Register32 // 0x8
	SFMSST  volatile.Register32 // 0xC
	SFMCOM  volatile.Register32 // 0x10
	SFMCMD  volatile.Register32 // 0x14
	SFMCST  volatile.Register32 // 0x18
	_       [4]byte
	SFMSIC  volatile.Register32 // 0x20
	SFMSAC  volatile.Register32 // 0x24
	SFMSDC  volatile.Register32 // 0x28
	_       [4]byte
	SFMSPC  volatile.Register32 // 0x30
	SFMPMD  volatile.Register32 // 0x34
	_       [1996]byte
	SFMCNT1 volatile.Register32 // 0x804
}

// QSPI.SFMSMD: Transfer Mode Control Register
func (o *QSPI_Type) SetSFMSMD_SFMRM(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x7)|value)
}
func (o *QSPI_Type) GetSFMSMD_SFMRM() uint32 {
	return volatile.LoadUint32(&o.SFMSMD.Reg) & 0x7
}
func (o *QSPI_Type) SetSFMSMD_SFMSE(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x30)|value<<4)
}
func (o *QSPI_Type) GetSFMSMD_SFMSE() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x30) >> 4
}
func (o *QSPI_Type) SetSFMSMD_SFMPFE(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x40)|value<<6)
}
func (o *QSPI_Type) GetSFMSMD_SFMPFE() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x40) >> 6
}
func (o *QSPI_Type) SetSFMSMD_SFMPAE(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x80)|value<<7)
}
func (o *QSPI_Type) GetSFMSMD_SFMPAE() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x80) >> 7
}
func (o *QSPI_Type) SetSFMSMD_SFMMD3(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x100)|value<<8)
}
func (o *QSPI_Type) GetSFMSMD_SFMMD3() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x100) >> 8
}
func (o *QSPI_Type) SetSFMSMD_SFMOEX(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x200)|value<<9)
}
func (o *QSPI_Type) GetSFMSMD_SFMOEX() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x200) >> 9
}
func (o *QSPI_Type) SetSFMSMD_SFMOHW(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x400)|value<<10)
}
func (o *QSPI_Type) GetSFMSMD_SFMOHW() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x400) >> 10
}
func (o *QSPI_Type) SetSFMSMD_SFMOSW(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x800)|value<<11)
}
func (o *QSPI_Type) GetSFMSMD_SFMOSW() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x800) >> 11
}
func (o *QSPI_Type) SetSFMSMD_SFMCCE(value uint32) {
	volatile.StoreUint32(&o.SFMSMD.Reg, volatile.LoadUint32(&o.SFMSMD.Reg)&^(0x8000)|value<<15)
}
func (o *QSPI_Type) GetSFMSMD_SFMCCE() uint32 {
	return (volatile.LoadUint32(&o.SFMSMD.Reg) & 0x8000) >> 15
}

// QSPI.SFMSSC: Chip Selection Control Register
func (o *QSPI_Type) SetSFMSSC_SFMSW(value uint32) {
	volatile.StoreUint32(&o.SFMSSC.Reg, volatile.LoadUint32(&o.SFMSSC.Reg)&^(0xf)|value)
}
func (o *QSPI_Type) GetSFMSSC_SFMSW() uint32 {
	return volatile.LoadUint32(&o.SFMSSC.Reg) & 0xf
}
func (o *QSPI_Type) SetSFMSSC_SFMSHD(value uint32) {
	volatile.StoreUint32(&o.SFMSSC.Reg, volatile.LoadUint32(&o.SFMSSC.Reg)&^(0x10)|value<<4)
}
func (o *QSPI_Type) GetSFMSSC_SFMSHD() uint32 {
	return (volatile.LoadUint32(&o.SFMSSC.Reg) & 0x10) >> 4
}
func (o *QSPI_Type) SetSFMSSC_SFMSLD(value uint32) {
	volatile.StoreUint32(&o.SFMSSC.Reg, volatile.LoadUint32(&o.SFMSSC.Reg)&^(0x20)|value<<5)
}
func (o *QSPI_Type) GetSFMSSC_SFMSLD() uint32 {
	return (volatile.LoadUint32(&o.SFMSSC.Reg) & 0x20) >> 5
}

// QSPI.SFMSKC: Clock Control Register
func (o *QSPI_Type) SetSFMSKC_SFMDV(value uint32) {
	volatile.StoreUint32(&o.SFMSKC.Reg, volatile.LoadUint32(&o.SFMSKC.Reg)&^(0x1f)|value)
}
func (o *QSPI_Type) GetSFMSKC_SFMDV() uint32 {
	return volatile.LoadUint32(&o.SFMSKC.Reg) & 0x1f
}
func (o *QSPI_Type) SetSFMSKC_SFMDTY(value uint32) {
	volatile.StoreUint32(&o.SFMSKC.Reg, volatile.LoadUint32(&o.SFMSKC.Reg)&^(0x20)|value<<5)
}
func (o *QSPI_Type) GetSFMSKC_SFMDTY() uint32 {
	return (volatile.LoadUint32(&o.SFMSKC.Reg) & 0x20) >> 5
}

// QSPI.SFMSST: Status Register
func (o *QSPI_Type) SetSFMSST_PFCNT(value uint32) {
	volatile.StoreUint32(&o.SFMSST.Reg, volatile.LoadUint32(&o.SFMSST.Reg)&^(0x1f)|value)
}
func (o *QSPI_Type) GetSFMSST_PFCNT() uint32 {
	return volatile.LoadUint32(&o.SFMSST.Reg) & 0x1f
}
func (o *QSPI_Type) SetSFMSST_PFFUL(value uint32) {
	volatile.StoreUint32(&o.SFMSST.Reg, volatile.LoadUint32(&o.SFMSST.Reg)&^(0x40)|value<<6)
}
func (o *QSPI_Type) GetSFMSST_PFFUL() uint32 {
	return (volatile.LoadUint32(&o.SFMSST.Reg) & 0x40) >> 6
}
func (o *QSPI_Type) SetSFMSST_PFOFF(value uint32) {
	volatile.StoreUint32(&o.SFMSST.Reg, volatile.LoadUint32(&o.SFMSST.Reg)&^(0x80)|value<<7)
}
func (o *QSPI_Type) GetSFMSST_PFOFF() uint32 {
	return (volatile.LoadUint32(&o.SFMSST.Reg) & 0x80) >> 7
}

// QSPI.SFMCOM: Communication Port Register
func (o *QSPI_Type) SetSFMCOM_SFMD(value uint32) {
	volatile.StoreUint32(&o.SFMCOM.Reg, volatile.LoadUint32(&o.SFMCOM.Reg)&^(0xff)|value)
}
func (o *QSPI_Type) GetSFMCOM_SFMD() uint32 {
	return volatile.LoadUint32(&o.SFMCOM.Reg) & 0xff
}

// QSPI.SFMCMD: Communication Mode Control Register
func (o *QSPI_Type) SetSFMCMD_DCOM(value uint32) {
	volatile.StoreUint32(&o.SFMCMD.Reg, volatile.LoadUint32(&o.SFMCMD.Reg)&^(0x1)|value)
}
func (o *QSPI_Type) GetSFMCMD_DCOM() uint32 {
	return volatile.LoadUint32(&o.SFMCMD.Reg) & 0x1
}

// QSPI.SFMCST: Communication Status Register
func (o *QSPI_Type) SetSFMCST_COMBSY(value uint32) {
	volatile.StoreUint32(&o.SFMCST.Reg, volatile.LoadUint32(&o.SFMCST.Reg)&^(0x1)|value)
}
func (o *QSPI_Type) GetSFMCST_COMBSY() uint32 {
	return volatile.LoadUint32(&o.SFMCST.Reg) & 0x1
}
func (o *QSPI_Type) SetSFMCST_EROMR(value uint32) {
	volatile.StoreUint32(&o.SFMCST.Reg, volatile.LoadUint32(&o.SFMCST.Reg)&^(0x80)|value<<7)
}
func (o *QSPI_Type) GetSFMCST_EROMR() uint32 {
	return (volatile.LoadUint32(&o.SFMCST.Reg) & 0x80) >> 7
}

// QSPI.SFMSIC: Instruction Code Register
func (o *QSPI_Type) SetSFMSIC_SFMCIC(value uint32) {
	volatile.StoreUint32(&o.SFMSIC.Reg, volatile.LoadUint32(&o.SFMSIC.Reg)&^(0xff)|value)
}
func (o *QSPI_Type) GetSFMSIC_SFMCIC() uint32 {
	return volatile.LoadUint32(&o.SFMSIC.Reg) & 0xff
}

// QSPI.SFMSAC: Address Mode Control Register
func (o *QSPI_Type) SetSFMSAC_SFMAS(value uint32) {
	volatile.StoreUint32(&o.SFMSAC.Reg, volatile.LoadUint32(&o.SFMSAC.Reg)&^(0x3)|value)
}
func (o *QSPI_Type) GetSFMSAC_SFMAS() uint32 {
	return volatile.LoadUint32(&o.SFMSAC.Reg) & 0x3
}
func (o *QSPI_Type) SetSFMSAC_SFM4BC(value uint32) {
	volatile.StoreUint32(&o.SFMSAC.Reg, volatile.LoadUint32(&o.SFMSAC.Reg)&^(0x10)|value<<4)
}
func (o *QSPI_Type) GetSFMSAC_SFM4BC() uint32 {
	return (volatile.LoadUint32(&o.SFMSAC.Reg) & 0x10) >> 4
}

// QSPI.SFMSDC: Dummy Cycle Control Register
func (o *QSPI_Type) SetSFMSDC_SFMDN(value uint32) {
	volatile.StoreUint32(&o.SFMSDC.Reg, volatile.LoadUint32(&o.SFMSDC.Reg)&^(0xf)|value)
}
func (o *QSPI_Type) GetSFMSDC_SFMDN() uint32 {
	return volatile.LoadUint32(&o.SFMSDC.Reg) & 0xf
}
func (o *QSPI_Type) SetSFMSDC_SFMXST(value uint32) {
	volatile.StoreUint32(&o.SFMSDC.Reg, volatile.LoadUint32(&o.SFMSDC.Reg)&^(0x40)|value<<6)
}
func (o *QSPI_Type) GetSFMSDC_SFMXST() uint32 {
	return (volatile.LoadUint32(&o.SFMSDC.Reg) & 0x40) >> 6
}
func (o *QSPI_Type) SetSFMSDC_SFMXEN(value uint32) {
	volatile.StoreUint32(&o.SFMSDC.Reg, volatile.LoadUint32(&o.SFMSDC.Reg)&^(0x80)|value<<7)
}
func (o *QSPI_Type) GetSFMSDC_SFMXEN() uint32 {
	return (volatile.LoadUint32(&o.SFMSDC.Reg) & 0x80) >> 7
}
func (o *QSPI_Type) SetSFMSDC_SFMXD(value uint32) {
	volatile.StoreUint32(&o.SFMSDC.Reg, volatile.LoadUint32(&o.SFMSDC.Reg)&^(0xff00)|value<<8)
}
func (o *QSPI_Type) GetSFMSDC_SFMXD() uint32 {
	return (volatile.LoadUint32(&o.SFMSDC.Reg) & 0xff00) >> 8
}

// QSPI.SFMSPC: SPI Protocol Control Register
func (o *QSPI_Type) SetSFMSPC_SFMSPI(value uint32) {
	volatile.StoreUint32(&o.SFMSPC.Reg, volatile.LoadUint32(&o.SFMSPC.Reg)&^(0x3)|value)
}
func (o *QSPI_Type) GetSFMSPC_SFMSPI() uint32 {
	return volatile.LoadUint32(&o.SFMSPC.Reg) & 0x3
}
func (o *QSPI_Type) SetSFMSPC_SFMSDE(value uint32) {
	volatile.StoreUint32(&o.SFMSPC.Reg, volatile.LoadUint32(&o.SFMSPC.Reg)&^(0x10)|value<<4)
}
func (o *QSPI_Type) GetSFMSPC_SFMSDE() uint32 {
	return (volatile.LoadUint32(&o.SFMSPC.Reg) & 0x10) >> 4
}

// QSPI.SFMPMD: Port Control Register
func (o *QSPI_Type) SetSFMPMD_SFMWPL(value uint32) {
	volatile.StoreUint32(&o.SFMPMD.Reg, volatile.LoadUint32(&o.SFMPMD.Reg)&^(0x4)|value<<2)
}
func (o *QSPI_Type) GetSFMPMD_SFMWPL() uint32 {
	return (volatile.LoadUint32(&o.SFMPMD.Reg) & 0x4) >> 2
}

// QSPI.SFMCNT1: External QSPI Address Register
func (o *QSPI_Type) SetSFMCNT1_QSPI_EXT(value uint32) {
	volatile.StoreUint32(&o.SFMCNT1.Reg, volatile.LoadUint32(&o.SFMCNT1.Reg)&^(0xfc000000)|value<<26)
}
func (o *QSPI_Type) GetSFMCNT1_QSPI_EXT() uint32 {
	return (volatile.LoadUint32(&o.SFMCNT1.Reg) & 0xfc000000) >> 26
}

// Constants for RMPU: Renesas Memory Protection Unit
const (
	// MMPUOAD: MMPU Operation After Detection Register
	// Position of OAD field.
	RMPU_MMPUOAD_OAD_Pos = 0x0
	// Bit mask of OAD field.
	RMPU_MMPUOAD_OAD_Msk = 0x1
	// Bit OAD.
	RMPU_MMPUOAD_OAD = 0x1
	// Non-maskable interrupt
	RMPU_MMPUOAD_OAD_0 = 0x0
	// Reset
	RMPU_MMPUOAD_OAD_1 = 0x1
	// Position of KEY field.
	RMPU_MMPUOAD_KEY_Pos = 0x8
	// Bit mask of KEY field.
	RMPU_MMPUOAD_KEY_Msk = 0xff00

	// MMPUOADPT: MMPU Operation After Detection Protect Register
	// Position of PROTECT field.
	RMPU_MMPUOADPT_PROTECT_Pos = 0x0
	// Bit mask of PROTECT field.
	RMPU_MMPUOADPT_PROTECT_Msk = 0x1
	// Bit PROTECT.
	RMPU_MMPUOADPT_PROTECT = 0x1
	// MMPUOAD register writes are possible.
	RMPU_MMPUOADPT_PROTECT_0 = 0x0
	// MMPUOAD register writes are protected. Read is possible.
	RMPU_MMPUOADPT_PROTECT_1 = 0x1
	// Position of KEY field.
	RMPU_MMPUOADPT_KEY_Pos = 0x8
	// Bit mask of KEY field.
	RMPU_MMPUOADPT_KEY_Msk = 0xff00

	// MMPUENDMAC: MMPU Enable Register for DMAC
	// Position of ENABLE field.
	RMPU_MMPUENDMAC_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	RMPU_MMPUENDMAC_ENABLE_Msk = 0x1
	// Bit ENABLE.
	RMPU_MMPUENDMAC_ENABLE = 0x1
	// Bus Master MPU of DMAC is disabled.
	RMPU_MMPUENDMAC_ENABLE_0 = 0x0
	// Bus Master MPU of DMAC is enabled.
	RMPU_MMPUENDMAC_ENABLE_1 = 0x1
	// Position of KEY field.
	RMPU_MMPUENDMAC_KEY_Pos = 0x8
	// Bit mask of KEY field.
	RMPU_MMPUENDMAC_KEY_Msk = 0xff00

	// MMPUENPTDMAC: MMPU Enable Protect Register for DMAC
	// Position of PROTECT field.
	RMPU_MMPUENPTDMAC_PROTECT_Pos = 0x0
	// Bit mask of PROTECT field.
	RMPU_MMPUENPTDMAC_PROTECT_Msk = 0x1
	// Bit PROTECT.
	RMPU_MMPUENPTDMAC_PROTECT = 0x1
	// MMPUENDMAC register writes are possible.
	RMPU_MMPUENPTDMAC_PROTECT_0 = 0x0
	// MMPUENDMAC register writes are protected. Read is possible.
	RMPU_MMPUENPTDMAC_PROTECT_1 = 0x1
	// Position of KEY field.
	RMPU_MMPUENPTDMAC_KEY_Pos = 0x8
	// Bit mask of KEY field.
	RMPU_MMPUENPTDMAC_KEY_Msk = 0xff00

	// MMPURPTDMAC: MMPU Regions Protect Register for DMAC
	// Position of PROTECT field.
	RMPU_MMPURPTDMAC_PROTECT_Pos = 0x0
	// Bit mask of PROTECT field.
	RMPU_MMPURPTDMAC_PROTECT_Msk = 0x1
	// Bit PROTECT.
	RMPU_MMPURPTDMAC_PROTECT = 0x1
	// Bus Master MPU register for DMAC writing is possible.
	RMPU_MMPURPTDMAC_PROTECT_0 = 0x0
	// Bus Master MPU register for DMAC writing is protected. Read is possible.
	RMPU_MMPURPTDMAC_PROTECT_1 = 0x1
	// Position of KEY field.
	RMPU_MMPURPTDMAC_KEY_Pos = 0x8
	// Bit mask of KEY field.
	RMPU_MMPURPTDMAC_KEY_Msk = 0xff00

	// MMPURPTDMAC_SEC: MMPU Regions Protect register for DMAC Secure
	// Position of PROTECT field.
	RMPU_MMPURPTDMAC_SEC_PROTECT_Pos = 0x0
	// Bit mask of PROTECT field.
	RMPU_MMPURPTDMAC_SEC_PROTECT_Msk = 0x1
	// Bit PROTECT.
	RMPU_MMPURPTDMAC_SEC_PROTECT = 0x1
	// Bus master MPU register for DMAC secure writes are possible.
	RMPU_MMPURPTDMAC_SEC_PROTECT_0 = 0x0
	// Bus master MPU register for DMAC secure writes are protected. Read is possible.
	RMPU_MMPURPTDMAC_SEC_PROTECT_1 = 0x1
	// Position of KEY field.
	RMPU_MMPURPTDMAC_SEC_KEY_Pos = 0x8
	// Bit mask of KEY field.
	RMPU_MMPURPTDMAC_SEC_KEY_Msk = 0xff00

	// MMPUACDMAC0: MMPU Access Control Register for DMAC
	// Position of ENABLE field.
	RMPU_MMPUACDMAC_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	RMPU_MMPUACDMAC_ENABLE_Msk = 0x1
	// Bit ENABLE.
	RMPU_MMPUACDMAC_ENABLE = 0x1
	// DMAC Region n unit is disabled
	RMPU_MMPUACDMAC_ENABLE_0 = 0x0
	// DMAC Region n unit is enabled
	RMPU_MMPUACDMAC_ENABLE_1 = 0x1
	// Position of RP field.
	RMPU_MMPUACDMAC_RP_Pos = 0x1
	// Bit mask of RP field.
	RMPU_MMPUACDMAC_RP_Msk = 0x2
	// Bit RP.
	RMPU_MMPUACDMAC_RP = 0x2
	// Read permission
	RMPU_MMPUACDMAC_RP_0 = 0x0
	// Read protection
	RMPU_MMPUACDMAC_RP_1 = 0x1
	// Position of WP field.
	RMPU_MMPUACDMAC_WP_Pos = 0x2
	// Bit mask of WP field.
	RMPU_MMPUACDMAC_WP_Msk = 0x4
	// Bit WP.
	RMPU_MMPUACDMAC_WP = 0x4
	// Write permission
	RMPU_MMPUACDMAC_WP_0 = 0x0
	// Write protection
	RMPU_MMPUACDMAC_WP_1 = 0x1

	// MMPUSDMAC0: MMPU Start Address Register for DMAC
	// Position of MMPUS field.
	RMPU_MMPUSDMAC_MMPUS_Pos = 0x5
	// Bit mask of MMPUS field.
	RMPU_MMPUSDMAC_MMPUS_Msk = 0xffffffe0

	// MMPUEDMAC0: MMPU End Address Register for DMAC
	// Position of MMPUE field.
	RMPU_MMPUEDMAC_MMPUE_Pos = 0x5
	// Bit mask of MMPUE field.
	RMPU_MMPUEDMAC_MMPUE_Msk = 0xffffffe0
)

// Constants for TZF: TrustZone Filter
const (
	// TZFOAD: TrustZone Filter Operation After Detection Register
	// Position of OAD field.
	TZF_TZFOAD_OAD_Pos = 0x0
	// Bit mask of OAD field.
	TZF_TZFOAD_OAD_Msk = 0x1
	// Bit OAD.
	TZF_TZFOAD_OAD = 0x1
	// Non-maskable interrupt
	TZF_TZFOAD_OAD_0 = 0x0
	// Reset
	TZF_TZFOAD_OAD_1 = 0x1
	// Position of KEY field.
	TZF_TZFOAD_KEY_Pos = 0x8
	// Bit mask of KEY field.
	TZF_TZFOAD_KEY_Msk = 0xff00

	// TZFPT: TrustZone Filter Protect Register
	// Position of PROTECT field.
	TZF_TZFPT_PROTECT_Pos = 0x0
	// Bit mask of PROTECT field.
	TZF_TZFPT_PROTECT_Msk = 0x1
	// Bit PROTECT.
	TZF_TZFPT_PROTECT = 0x1
	// All Bus TrustZone Filter register writing is protected. Read is possible.
	TZF_TZFPT_PROTECT_0 = 0x0
	// All Bus TrustZone Filter register writing is possible.
	TZF_TZFPT_PROTECT_1 = 0x1
	// Position of KEY field.
	TZF_TZFPT_KEY_Pos = 0x8
	// Bit mask of KEY field.
	TZF_TZFPT_KEY_Msk = 0xff00
)

// Constants for SRAM: SRAM Control
const (
	// PARIOAD: SRAM Parity Error Operation After Detection Register
	// Position of OAD field.
	SRAM_PARIOAD_OAD_Pos = 0x0
	// Bit mask of OAD field.
	SRAM_PARIOAD_OAD_Msk = 0x1
	// Bit OAD.
	SRAM_PARIOAD_OAD = 0x1
	// Non-maskable interrupt
	SRAM_PARIOAD_OAD_0 = 0x0
	// Reset
	SRAM_PARIOAD_OAD_1 = 0x1

	// SRAMPRCR: SRAM Protection Register
	// Position of SRAMPRCR field.
	SRAM_SRAMPRCR_SRAMPRCR_Pos = 0x0
	// Bit mask of SRAMPRCR field.
	SRAM_SRAMPRCR_SRAMPRCR_Msk = 0x1
	// Bit SRAMPRCR.
	SRAM_SRAMPRCR_SRAMPRCR = 0x1
	// Disable writes to protected registers
	SRAM_SRAMPRCR_SRAMPRCR_0 = 0x0
	// Enable writes to protected registers
	SRAM_SRAMPRCR_SRAMPRCR_1 = 0x1
	// Position of KW field.
	SRAM_SRAMPRCR_KW_Pos = 0x1
	// Bit mask of KW field.
	SRAM_SRAMPRCR_KW_Msk = 0xfe

	// SRAMWTSC: SRAM Wait State Control Register
	// Position of SRAM0WTEN field.
	SRAM_SRAMWTSC_SRAM0WTEN_Pos = 0x0
	// Bit mask of SRAM0WTEN field.
	SRAM_SRAMWTSC_SRAM0WTEN_Msk = 0x1
	// Bit SRAM0WTEN.
	SRAM_SRAMWTSC_SRAM0WTEN = 0x1
	// No wait
	SRAM_SRAMWTSC_SRAM0WTEN_0 = 0x0
	// Add wait state in read access cycle to SRAM0
	SRAM_SRAMWTSC_SRAM0WTEN_1 = 0x1

	// SRAMPRCR2: SRAM Protection Register 2
	// Position of SRAMPRCR2 field.
	SRAM_SRAMPRCR2_SRAMPRCR2_Pos = 0x0
	// Bit mask of SRAMPRCR2 field.
	SRAM_SRAMPRCR2_SRAMPRCR2_Msk = 0x1
	// Bit SRAMPRCR2.
	SRAM_SRAMPRCR2_SRAMPRCR2 = 0x1
	// Disable writes to the protectedregisters
	SRAM_SRAMPRCR2_SRAMPRCR2_0 = 0x0
	// Enable writes to the protected registers
	SRAM_SRAMPRCR2_SRAMPRCR2_1 = 0x1
	// Position of KW field.
	SRAM_SRAMPRCR2_KW_Pos = 0x1
	// Bit mask of KW field.
	SRAM_SRAMPRCR2_KW_Msk = 0xfe

	// ECCMODE: ECC Operating Mode Control Register
	// Position of ECCMOD field.
	SRAM_ECCMODE_ECCMOD_Pos = 0x0
	// Bit mask of ECCMOD field.
	SRAM_ECCMODE_ECCMOD_Msk = 0x3
	// Disable ECC function
	SRAM_ECCMODE_ECCMOD_00 = 0x0
	// Setting prohibited
	SRAM_ECCMODE_ECCMOD_01 = 0x1
	// Enable ECC function without error checking
	SRAM_ECCMODE_ECCMOD_10 = 0x2
	// Enable ECC function with error checking
	SRAM_ECCMODE_ECCMOD_11 = 0x3

	// ECC2STS: ECC 2-Bit Error Status Register
	// Position of ECC2ERR field.
	SRAM_ECC2STS_ECC2ERR_Pos = 0x0
	// Bit mask of ECC2ERR field.
	SRAM_ECC2STS_ECC2ERR_Msk = 0x1
	// Bit ECC2ERR.
	SRAM_ECC2STS_ECC2ERR = 0x1
	// No 2-bit ECC error occurred
	SRAM_ECC2STS_ECC2ERR_0 = 0x0
	// 2-bit ECC error occurred
	SRAM_ECC2STS_ECC2ERR_1 = 0x1

	// ECC1STSEN: ECC 1-Bit Error Information Update Enable Register
	// Position of E1STSEN field.
	SRAM_ECC1STSEN_E1STSEN_Pos = 0x0
	// Bit mask of E1STSEN field.
	SRAM_ECC1STSEN_E1STSEN_Msk = 0x1
	// Bit E1STSEN.
	SRAM_ECC1STSEN_E1STSEN = 0x1
	// Disable updating of 1-bit ECC error information
	SRAM_ECC1STSEN_E1STSEN_0 = 0x0
	// Enable updating of 1-bit ECC error information
	SRAM_ECC1STSEN_E1STSEN_1 = 0x1

	// ECC1STS: ECC 1-Bit Error Status Register
	// Position of ECC1ERR field.
	SRAM_ECC1STS_ECC1ERR_Pos = 0x0
	// Bit mask of ECC1ERR field.
	SRAM_ECC1STS_ECC1ERR_Msk = 0x1
	// Bit ECC1ERR.
	SRAM_ECC1STS_ECC1ERR = 0x1
	// No 1-bit ECC error occurred
	SRAM_ECC1STS_ECC1ERR_0 = 0x0
	// 1-bit ECC error occurred
	SRAM_ECC1STS_ECC1ERR_1 = 0x1

	// ECCPRCR: ECC Protection Register
	// Position of ECCPRCR field.
	SRAM_ECCPRCR_ECCPRCR_Pos = 0x0
	// Bit mask of ECCPRCR field.
	SRAM_ECCPRCR_ECCPRCR_Msk = 0x1
	// Bit ECCPRCR.
	SRAM_ECCPRCR_ECCPRCR = 0x1
	// Disable writes to the protected registers
	SRAM_ECCPRCR_ECCPRCR_0 = 0x0
	// Enable writes to the protected registers
	SRAM_ECCPRCR_ECCPRCR_1 = 0x1
	// Position of KW field.
	SRAM_ECCPRCR_KW_Pos = 0x1
	// Bit mask of KW field.
	SRAM_ECCPRCR_KW_Msk = 0xfe
	// Disable write to the ECCPRCR bit
	SRAM_ECCPRCR_KW_Others = 0x0
	// Enable write to the ECCPRCR bit
	SRAM_ECCPRCR_KW_0x78 = 0x78

	// ECCPRCR2: ECC Protection Register 2
	// Position of ECCPRCR2 field.
	SRAM_ECCPRCR2_ECCPRCR2_Pos = 0x0
	// Bit mask of ECCPRCR2 field.
	SRAM_ECCPRCR2_ECCPRCR2_Msk = 0x1
	// Bit ECCPRCR2.
	SRAM_ECCPRCR2_ECCPRCR2 = 0x1
	// Disable writes to the protected registers
	SRAM_ECCPRCR2_ECCPRCR2_0 = 0x0
	// Enable writes to the protected registers
	SRAM_ECCPRCR2_ECCPRCR2_1 = 0x1
	// Position of KW2 field.
	SRAM_ECCPRCR2_KW2_Pos = 0x1
	// Bit mask of KW2 field.
	SRAM_ECCPRCR2_KW2_Msk = 0xfe
	// Disable write to the ECCPRCR2 bit
	SRAM_ECCPRCR2_KW2_Others = 0x0
	// Enable write to the ECCPRCR2 bit
	SRAM_ECCPRCR2_KW2_0x78 = 0x78

	// ECCETST: ECC Test Control Register
	// Position of TSTBYP field.
	SRAM_ECCETST_TSTBYP_Pos = 0x0
	// Bit mask of TSTBYP field.
	SRAM_ECCETST_TSTBYP_Msk = 0x1
	// Bit TSTBYP.
	SRAM_ECCETST_TSTBYP = 0x1
	// Disable ECC bypass
	SRAM_ECCETST_TSTBYP_0 = 0x0
	// Enable ECC bypass
	SRAM_ECCETST_TSTBYP_1 = 0x1

	// ECCOAD: SRAM ECC Error Operation After Detection Register
	// Position of OAD field.
	SRAM_ECCOAD_OAD_Pos = 0x0
	// Bit mask of OAD field.
	SRAM_ECCOAD_OAD_Msk = 0x1
	// Bit OAD.
	SRAM_ECCOAD_OAD = 0x1
	// Non-maskable interrupt
	SRAM_ECCOAD_OAD_0 = 0x0
	// Reset
	SRAM_ECCOAD_OAD_1 = 0x1
)

// Constants for BUS: Bus Control
const (
	// BUSSCNTFHBIU: Slave Bus Control Register
	// Position of ARBS field.
	BUS_BUSSCNTFHBIU_ARBS_Pos = 0x0
	// Bit mask of ARBS field.
	BUS_BUSSCNTFHBIU_ARBS_Msk = 0x3
	// DMAC/DTC > CPU
	BUS_BUSSCNTFHBIU_ARBS_00 = 0x0
	// DMAC/DTC ↔ CPU
	BUS_BUSSCNTFHBIU_ARBS_01 = 0x1
	// Setting prohibited
	BUS_BUSSCNTFHBIU_ARBS_Others = 0x2

	// BUSSCNTFLBIU: Slave Bus Control Register
	// Position of ARBS field.
	BUS_BUSSCNTFLBIU_ARBS_Pos = 0x0
	// Bit mask of ARBS field.
	BUS_BUSSCNTFLBIU_ARBS_Msk = 0x3
	// DMAC/DTC > CPU
	BUS_BUSSCNTFLBIU_ARBS_00 = 0x0
	// DMAC/DTC ↔ CPU
	BUS_BUSSCNTFLBIU_ARBS_01 = 0x1
	// Setting prohibited
	BUS_BUSSCNTFLBIU_ARBS_Others = 0x2

	// BUSSCNTS0BIU: Slave Bus Control Register
	// Position of ARBS field.
	BUS_BUSSCNTS0BIU_ARBS_Pos = 0x0
	// Bit mask of ARBS field.
	BUS_BUSSCNTS0BIU_ARBS_Msk = 0x3
	// DMAC/DTC > CPU
	BUS_BUSSCNTS0BIU_ARBS_00 = 0x0
	// DMAC/DTC ↔ CPU
	BUS_BUSSCNTS0BIU_ARBS_01 = 0x1
	// Setting prohibited
	BUS_BUSSCNTS0BIU_ARBS_Others = 0x2

	// BUSSCNTPSBIU: Slave Bus Control Register
	// Position of ARBS field.
	BUS_BUSSCNTPSBIU_ARBS_Pos = 0x0
	// Bit mask of ARBS field.
	BUS_BUSSCNTPSBIU_ARBS_Msk = 0x1
	// Bit ARBS.
	BUS_BUSSCNTPSBIU_ARBS = 0x1
	// DMAC/DTC > CPU
	BUS_BUSSCNTPSBIU_ARBS_0 = 0x0
	// DMAC/DTC ↔ CPU
	BUS_BUSSCNTPSBIU_ARBS_1 = 0x1

	// BUSSCNTPLBIU: Slave Bus Control Register
	// Position of ARBS field.
	BUS_BUSSCNTPLBIU_ARBS_Pos = 0x0
	// Bit mask of ARBS field.
	BUS_BUSSCNTPLBIU_ARBS_Msk = 0x1
	// Bit ARBS.
	BUS_BUSSCNTPLBIU_ARBS = 0x1
	// DMAC/DTC > CPU
	BUS_BUSSCNTPLBIU_ARBS_0 = 0x0
	// DMAC/DTC ↔ CPU
	BUS_BUSSCNTPLBIU_ARBS_1 = 0x1

	// BUSSCNTPHBIU: Slave Bus Control Register
	// Position of ARBS field.
	BUS_BUSSCNTPHBIU_ARBS_Pos = 0x0
	// Bit mask of ARBS field.
	BUS_BUSSCNTPHBIU_ARBS_Msk = 0x1
	// Bit ARBS.
	BUS_BUSSCNTPHBIU_ARBS = 0x1
	// DMAC/DTC > CPU
	BUS_BUSSCNTPHBIU_ARBS_0 = 0x0
	// DMAC/DTC ↔ CPU
	BUS_BUSSCNTPHBIU_ARBS_1 = 0x1

	// BUSSCNTEQBIU: Slave Bus Control Register
	// Position of ARBS field.
	BUS_BUSSCNTEQBIU_ARBS_Pos = 0x0
	// Bit mask of ARBS field.
	BUS_BUSSCNTEQBIU_ARBS_Msk = 0x3
	// DMAC/DTC > CPU
	BUS_BUSSCNTEQBIU_ARBS_00 = 0x0
	// DMAC/DTC ↔ CPU
	BUS_BUSSCNTEQBIU_ARBS_01 = 0x1
	// Setting prohibited
	BUS_BUSSCNTEQBIU_ARBS_Others = 0x2

	// BUS1ERRADD: BUS Error Address Register
	// Position of BERAD field.
	BUS_BUSERRADD_BERAD_Pos = 0x0
	// Bit mask of BERAD field.
	BUS_BUSERRADD_BERAD_Msk = 0xffffffff

	// BUS1ERRRW: BUS Error Read Write Register
	// Position of RWSTAT field.
	BUS_BUSERRRW_RWSTAT_Pos = 0x0
	// Bit mask of RWSTAT field.
	BUS_BUSERRRW_RWSTAT_Msk = 0x1
	// Bit RWSTAT.
	BUS_BUSERRRW_RWSTAT = 0x1
	// Read access
	BUS_BUSERRRW_RWSTAT_0 = 0x0
	// Write access
	BUS_BUSERRRW_RWSTAT_1 = 0x1

	// BTZF1ERRADD: BUS TZF Error Address Register
	// Position of BTZFERAD field.
	BUS_BTZFERRADD_BTZFERAD_Pos = 0x0
	// Bit mask of BTZFERAD field.
	BUS_BTZFERRADD_BTZFERAD_Msk = 0xffffffff

	// BTZF1ERRRW: BUS TZF Error Read Write Register
	// Position of TRWSTAT field.
	BUS_BTZFERRRW_TRWSTAT_Pos = 0x0
	// Bit mask of TRWSTAT field.
	BUS_BTZFERRRW_TRWSTAT_Msk = 0x1
	// Bit TRWSTAT.
	BUS_BTZFERRRW_TRWSTAT = 0x1
	// Read access
	BUS_BTZFERRRW_TRWSTAT_0 = 0x0
	// Write access
	BUS_BTZFERRRW_TRWSTAT_1 = 0x1

	// BUS1ERRSTAT: BUS Error Status Register %s
	// Position of SLERRSTAT field.
	BUS_BUSERRSTAT_SLERRSTAT_Pos = 0x0
	// Bit mask of SLERRSTAT field.
	BUS_BUSERRSTAT_SLERRSTAT_Msk = 0x1
	// Bit SLERRSTAT.
	BUS_BUSERRSTAT_SLERRSTAT = 0x1
	// No error occurred
	BUS_BUSERRSTAT_SLERRSTAT_0 = 0x0
	// Error occurred
	BUS_BUSERRSTAT_SLERRSTAT_1 = 0x1
	// Position of STERRSTAT field.
	BUS_BUSERRSTAT_STERRSTAT_Pos = 0x1
	// Bit mask of STERRSTAT field.
	BUS_BUSERRSTAT_STERRSTAT_Msk = 0x2
	// Bit STERRSTAT.
	BUS_BUSERRSTAT_STERRSTAT = 0x2
	// No error occurred
	BUS_BUSERRSTAT_STERRSTAT_0 = 0x0
	// Error occurred
	BUS_BUSERRSTAT_STERRSTAT_1 = 0x1
	// Position of MMERRSTAT field.
	BUS_BUSERRSTAT_MMERRSTAT_Pos = 0x3
	// Bit mask of MMERRSTAT field.
	BUS_BUSERRSTAT_MMERRSTAT_Msk = 0x8
	// Bit MMERRSTAT.
	BUS_BUSERRSTAT_MMERRSTAT = 0x8
	// No error occurred
	BUS_BUSERRSTAT_MMERRSTAT_0 = 0x0
	// Error occurred
	BUS_BUSERRSTAT_MMERRSTAT_1 = 0x1
	// Position of ILERRSTAT field.
	BUS_BUSERRSTAT_ILERRSTAT_Pos = 0x4
	// Bit mask of ILERRSTAT field.
	BUS_BUSERRSTAT_ILERRSTAT_Msk = 0x10
	// Bit ILERRSTAT.
	BUS_BUSERRSTAT_ILERRSTAT = 0x10
	// No error occurred
	BUS_BUSERRSTAT_ILERRSTAT_0 = 0x0
	// Error occurred
	BUS_BUSERRSTAT_ILERRSTAT_1 = 0x1

	// BUS1ERRCLR: BUS Error Clear Register %s
	// Position of SLERRCLR field.
	BUS_BUSERRCLR_SLERRCLR_Pos = 0x0
	// Bit mask of SLERRCLR field.
	BUS_BUSERRCLR_SLERRCLR_Msk = 0x1
	// Bit SLERRCLR.
	BUS_BUSERRCLR_SLERRCLR = 0x1
	// Position of STERRCLR field.
	BUS_BUSERRCLR_STERRCLR_Pos = 0x1
	// Bit mask of STERRCLR field.
	BUS_BUSERRCLR_STERRCLR_Msk = 0x2
	// Bit STERRCLR.
	BUS_BUSERRCLR_STERRCLR = 0x2
	// Position of MMERRCLR field.
	BUS_BUSERRCLR_MMERRCLR_Pos = 0x3
	// Bit mask of MMERRCLR field.
	BUS_BUSERRCLR_MMERRCLR_Msk = 0x8
	// Bit MMERRCLR.
	BUS_BUSERRCLR_MMERRCLR = 0x8
	// Position of ILERRCLR field.
	BUS_BUSERRCLR_ILERRCLR_Pos = 0x4
	// Bit mask of ILERRCLR field.
	BUS_BUSERRCLR_ILERRCLR_Msk = 0x10
	// Bit ILERRCLR.
	BUS_BUSERRCLR_ILERRCLR = 0x10

	// DMACDTCERRSTAT: DMAC/DTC Error Status Register
	// Position of MTERRSTAT field.
	BUS_DMACDTCERRSTAT_MTERRSTAT_Pos = 0x0
	// Bit mask of MTERRSTAT field.
	BUS_DMACDTCERRSTAT_MTERRSTAT_Msk = 0x1
	// Bit MTERRSTAT.
	BUS_DMACDTCERRSTAT_MTERRSTAT = 0x1
	// No error occurred
	BUS_DMACDTCERRSTAT_MTERRSTAT_0 = 0x0
	// Error occurred
	BUS_DMACDTCERRSTAT_MTERRSTAT_1 = 0x1

	// DMACDTCERRCLR: DMAC/DTC Error Clear Register
	// Position of MTERRCLR field.
	BUS_DMACDTCERRCLR_MTERRCLR_Pos = 0x0
	// Bit mask of MTERRCLR field.
	BUS_DMACDTCERRCLR_MTERRCLR_Msk = 0x1
	// Bit MTERRCLR.
	BUS_DMACDTCERRCLR_MTERRCLR = 0x1
)

// Constants for DMAC0: Direct memory access controller 0
const (
	// DMCRA: DMA Transfer Count Register
	// Position of DMCRAL field.
	DMAC0_DMCRA_DMCRAL_Pos = 0x0
	// Bit mask of DMCRAL field.
	DMAC0_DMCRA_DMCRAL_Msk = 0xffff
	// Position of DMCRAH field.
	DMAC0_DMCRA_DMCRAH_Pos = 0x10
	// Bit mask of DMCRAH field.
	DMAC0_DMCRA_DMCRAH_Msk = 0x3ff0000

	// DMCRB: DMA Block Transfer Count Register
	// Position of DMCRBL field.
	DMAC0_DMCRB_DMCRBL_Pos = 0x0
	// Bit mask of DMCRBL field.
	DMAC0_DMCRB_DMCRBL_Msk = 0xffff
	// Position of DMCRBH field.
	DMAC0_DMCRB_DMCRBH_Pos = 0x10
	// Bit mask of DMCRBH field.
	DMAC0_DMCRB_DMCRBH_Msk = 0xffff0000

	// DMTMD: DMA Transfer Mode Register
	// Position of DCTG field.
	DMAC0_DMTMD_DCTG_Pos = 0x0
	// Bit mask of DCTG field.
	DMAC0_DMTMD_DCTG_Msk = 0x3
	// Software request
	DMAC0_DMTMD_DCTG_00 = 0x0
	// Hardware request
	DMAC0_DMTMD_DCTG_01 = 0x1
	// Setting prohibited
	DMAC0_DMTMD_DCTG_10 = 0x2
	// Setting prohibited
	DMAC0_DMTMD_DCTG_11 = 0x3
	// Position of SZ field.
	DMAC0_DMTMD_SZ_Pos = 0x8
	// Bit mask of SZ field.
	DMAC0_DMTMD_SZ_Msk = 0x300
	// 8 bits
	DMAC0_DMTMD_SZ_00 = 0x0
	// 16 bits
	DMAC0_DMTMD_SZ_01 = 0x1
	// 32 bits
	DMAC0_DMTMD_SZ_10 = 0x2
	// Setting prohibited
	DMAC0_DMTMD_SZ_11 = 0x3
	// Position of TKP field.
	DMAC0_DMTMD_TKP_Pos = 0xa
	// Bit mask of TKP field.
	DMAC0_DMTMD_TKP_Msk = 0x400
	// Bit TKP.
	DMAC0_DMTMD_TKP = 0x400
	// Transfer is stopped by completion of specified total number of transfer operations.
	DMAC0_DMTMD_TKP_0 = 0x0
	// Transfer is not stopped by completion of specified total number of transfer operations (free-running).
	DMAC0_DMTMD_TKP_1 = 0x1
	// Position of DTS field.
	DMAC0_DMTMD_DTS_Pos = 0xc
	// Bit mask of DTS field.
	DMAC0_DMTMD_DTS_Msk = 0x3000
	// The destination is specified as the repeat area or block area.
	DMAC0_DMTMD_DTS_00 = 0x0
	// The source is specified as the repeat area or block area.
	DMAC0_DMTMD_DTS_01 = 0x1
	// The repeat area or block area is not specified.
	DMAC0_DMTMD_DTS_10 = 0x2
	// Setting prohibited.
	DMAC0_DMTMD_DTS_11 = 0x3
	// Position of MD field.
	DMAC0_DMTMD_MD_Pos = 0xe
	// Bit mask of MD field.
	DMAC0_DMTMD_MD_Msk = 0xc000
	// Normal transfer
	DMAC0_DMTMD_MD_00 = 0x0
	// Repeat transfer
	DMAC0_DMTMD_MD_01 = 0x1
	// Block transfer
	DMAC0_DMTMD_MD_10 = 0x2
	// Repeat-block transfer
	DMAC0_DMTMD_MD_11 = 0x3

	// DMINT: DMA Interrupt Setting Register
	// Position of DARIE field.
	DMAC0_DMINT_DARIE_Pos = 0x0
	// Bit mask of DARIE field.
	DMAC0_DMINT_DARIE_Msk = 0x1
	// Bit DARIE.
	DMAC0_DMINT_DARIE = 0x1
	// Disables an interrupt request for an extended repeat area overflow on the destination address.
	DMAC0_DMINT_DARIE_0 = 0x0
	// Enables an interrupt request for an extended repeat area overflow on the destination address.
	DMAC0_DMINT_DARIE_1 = 0x1
	// Position of SARIE field.
	DMAC0_DMINT_SARIE_Pos = 0x1
	// Bit mask of SARIE field.
	DMAC0_DMINT_SARIE_Msk = 0x2
	// Bit SARIE.
	DMAC0_DMINT_SARIE = 0x2
	// Disables an interrupt request for an extended repeat area overflow on the source address.
	DMAC0_DMINT_SARIE_0 = 0x0
	// Enables an interrupt request for an extended repeat area overflow on the source address.
	DMAC0_DMINT_SARIE_1 = 0x1
	// Position of RPTIE field.
	DMAC0_DMINT_RPTIE_Pos = 0x2
	// Bit mask of RPTIE field.
	DMAC0_DMINT_RPTIE_Msk = 0x4
	// Bit RPTIE.
	DMAC0_DMINT_RPTIE = 0x4
	// Disables the repeat size end interrupt request.
	DMAC0_DMINT_RPTIE_0 = 0x0
	// Enables the repeat size end interrupt request.
	DMAC0_DMINT_RPTIE_1 = 0x1
	// Position of ESIE field.
	DMAC0_DMINT_ESIE_Pos = 0x3
	// Bit mask of ESIE field.
	DMAC0_DMINT_ESIE_Msk = 0x8
	// Bit ESIE.
	DMAC0_DMINT_ESIE = 0x8
	// Disables the transfer escape end interrupt request.
	DMAC0_DMINT_ESIE_0 = 0x0
	// Enables the transfer escape end interrupt request.
	DMAC0_DMINT_ESIE_1 = 0x1
	// Position of DTIE field.
	DMAC0_DMINT_DTIE_Pos = 0x4
	// Bit mask of DTIE field.
	DMAC0_DMINT_DTIE_Msk = 0x10
	// Bit DTIE.
	DMAC0_DMINT_DTIE = 0x10
	// Disables the transfer end interrupt request.
	DMAC0_DMINT_DTIE_0 = 0x0
	// Enables the transfer end interrupt request.
	DMAC0_DMINT_DTIE_1 = 0x1

	// DMAMD: DMA Address Mode Register
	// Position of DARA field.
	DMAC0_DMAMD_DARA_Pos = 0x0
	// Bit mask of DARA field.
	DMAC0_DMAMD_DARA_Msk = 0x1f
	// Position of DADR field.
	DMAC0_DMAMD_DADR_Pos = 0x5
	// Bit mask of DADR field.
	DMAC0_DMAMD_DADR_Msk = 0x20
	// Bit DADR.
	DMAC0_DMAMD_DADR = 0x20
	// Only reloading.
	DMAC0_DMAMD_DADR_0 = 0x0
	// Add index after reloading.
	DMAC0_DMAMD_DADR_1 = 0x1
	// Position of DM field.
	DMAC0_DMAMD_DM_Pos = 0x6
	// Bit mask of DM field.
	DMAC0_DMAMD_DM_Msk = 0xc0
	// Destination address is fixed.
	DMAC0_DMAMD_DM_00 = 0x0
	// Offset addition.
	DMAC0_DMAMD_DM_01 = 0x1
	// Destination address is incremented.
	DMAC0_DMAMD_DM_10 = 0x2
	// Destination address is decremented.
	DMAC0_DMAMD_DM_11 = 0x3
	// Position of SARA field.
	DMAC0_DMAMD_SARA_Pos = 0x8
	// Bit mask of SARA field.
	DMAC0_DMAMD_SARA_Msk = 0x1f00
	// Position of SADR field.
	DMAC0_DMAMD_SADR_Pos = 0xd
	// Bit mask of SADR field.
	DMAC0_DMAMD_SADR_Msk = 0x2000
	// Bit SADR.
	DMAC0_DMAMD_SADR = 0x2000
	// Only reloading.
	DMAC0_DMAMD_SADR_0 = 0x0
	// Add index after reloading.
	DMAC0_DMAMD_SADR_1 = 0x1
	// Position of SM field.
	DMAC0_DMAMD_SM_Pos = 0xe
	// Bit mask of SM field.
	DMAC0_DMAMD_SM_Msk = 0xc000
	// Source address is fixed.
	DMAC0_DMAMD_SM_00 = 0x0
	// Offset addition.
	DMAC0_DMAMD_SM_01 = 0x1
	// Source address is incremented.
	DMAC0_DMAMD_SM_10 = 0x2
	// Source address is decremented.
	DMAC0_DMAMD_SM_11 = 0x3

	// DMCNT: DMA Transfer Enable Register
	// Position of DTE field.
	DMAC0_DMCNT_DTE_Pos = 0x0
	// Bit mask of DTE field.
	DMAC0_DMCNT_DTE_Msk = 0x1
	// Bit DTE.
	DMAC0_DMCNT_DTE = 0x1
	// Disables DMA transfer.
	DMAC0_DMCNT_DTE_0 = 0x0
	// Enables DMA transfer.
	DMAC0_DMCNT_DTE_1 = 0x1

	// DMREQ: DMA Software Start Register
	// Position of SWREQ field.
	DMAC0_DMREQ_SWREQ_Pos = 0x0
	// Bit mask of SWREQ field.
	DMAC0_DMREQ_SWREQ_Msk = 0x1
	// Bit SWREQ.
	DMAC0_DMREQ_SWREQ = 0x1
	// DMA transfer is not requested.
	DMAC0_DMREQ_SWREQ_0 = 0x0
	// DMA transfer is requested.
	DMAC0_DMREQ_SWREQ_1 = 0x1
	// Position of CLRS field.
	DMAC0_DMREQ_CLRS_Pos = 0x4
	// Bit mask of CLRS field.
	DMAC0_DMREQ_CLRS_Msk = 0x10
	// Bit CLRS.
	DMAC0_DMREQ_CLRS = 0x10
	// SWREQ bit is cleared after DMA transfer is started by software.
	DMAC0_DMREQ_CLRS_0 = 0x0
	// SWREQ bit is not cleared after DMA transfer is started by software.
	DMAC0_DMREQ_CLRS_1 = 0x1

	// DMSTS: DMA Status Register
	// Position of ESIF field.
	DMAC0_DMSTS_ESIF_Pos = 0x0
	// Bit mask of ESIF field.
	DMAC0_DMSTS_ESIF_Msk = 0x1
	// Bit ESIF.
	DMAC0_DMSTS_ESIF = 0x1
	// A transfer escape end interrupt has not been generated.
	DMAC0_DMSTS_ESIF_0 = 0x0
	// A transfer escape end interrupt has been generated.
	DMAC0_DMSTS_ESIF_1 = 0x1
	// Position of DTIF field.
	DMAC0_DMSTS_DTIF_Pos = 0x4
	// Bit mask of DTIF field.
	DMAC0_DMSTS_DTIF_Msk = 0x10
	// Bit DTIF.
	DMAC0_DMSTS_DTIF = 0x10
	// A transfer end interrupt has not been generated.
	DMAC0_DMSTS_DTIF_0 = 0x0
	// A transfer end interrupt has been generated.
	DMAC0_DMSTS_DTIF_1 = 0x1
	// Position of ACT field.
	DMAC0_DMSTS_ACT_Pos = 0x7
	// Bit mask of ACT field.
	DMAC0_DMSTS_ACT_Msk = 0x80
	// Bit ACT.
	DMAC0_DMSTS_ACT = 0x80
	// DMAC is in the idle state.
	DMAC0_DMSTS_ACT_0 = 0x0
	// DMAC is operating.
	DMAC0_DMSTS_ACT_1 = 0x1

	// DMSBS: DMA Source Buffer Size Register
	// Position of DMSBSL field.
	DMAC0_DMSBS_DMSBSL_Pos = 0x0
	// Bit mask of DMSBSL field.
	DMAC0_DMSBS_DMSBSL_Msk = 0xffff
	// Position of DMSBSH field.
	DMAC0_DMSBS_DMSBSH_Pos = 0x10
	// Bit mask of DMSBSH field.
	DMAC0_DMSBS_DMSBSH_Msk = 0xffff0000

	// DMDBS: DMA Destination Buffer Size Register
	// Position of DMDBSL field.
	DMAC0_DMDBS_DMDBSL_Pos = 0x0
	// Bit mask of DMDBSL field.
	DMAC0_DMDBS_DMDBSL_Msk = 0xffff
	// Position of DMDBSH field.
	DMAC0_DMDBS_DMDBSH_Pos = 0x10
	// Bit mask of DMDBSH field.
	DMAC0_DMDBS_DMDBSH_Msk = 0xffff0000
)

// Constants for DMA: DMAC Module Activation
const (
	// DMAST: DMA Module Activation Register
	// Position of DMST field.
	DMA_DMAST_DMST_Pos = 0x0
	// Bit mask of DMST field.
	DMA_DMAST_DMST_Msk = 0x1
	// Bit DMST.
	DMA_DMAST_DMST = 0x1
	// DMAC activation is disabled.
	DMA_DMAST_DMST_0 = 0x0
	// DMAC activation is enabled.
	DMA_DMAST_DMST_1 = 0x1

	// DMECHR: DMAC Error Channel Register
	// Position of DMECH field.
	DMA_DMECHR_DMECH_Pos = 0x0
	// Bit mask of DMECH field.
	DMA_DMECHR_DMECH_Msk = 0x7
	// Position of DMECHSAM field.
	DMA_DMECHR_DMECHSAM_Pos = 0x8
	// Bit mask of DMECHSAM field.
	DMA_DMECHR_DMECHSAM_Msk = 0x100
	// Bit DMECHSAM.
	DMA_DMECHR_DMECHSAM = 0x100
	// secure channel
	DMA_DMECHR_DMECHSAM_0 = 0x0
	// non-secure channel
	DMA_DMECHR_DMECHSAM_1 = 0x1
	// Position of DMESTA field.
	DMA_DMECHR_DMESTA_Pos = 0x10
	// Bit mask of DMESTA field.
	DMA_DMECHR_DMESTA_Msk = 0x10000
	// Bit DMESTA.
	DMA_DMECHR_DMESTA = 0x10000
	// No DMA transfer error occurred
	DMA_DMECHR_DMESTA_0 = 0x0
	// DMA transfer error occurred
	DMA_DMECHR_DMESTA_1 = 0x1
)

// Constants for DTC: Data Transfer Controller
const (
	// DTCCR: DTC Control Register
	// Position of RRS field.
	DTC_DTCCR_RRS_Pos = 0x4
	// Bit mask of RRS field.
	DTC_DTCCR_RRS_Msk = 0x10
	// Bit RRS.
	DTC_DTCCR_RRS = 0x10
	// Transfer information read is not skipped
	DTC_DTCCR_RRS_0 = 0x0
	// Transfer information read is skipped when vector numbers match
	DTC_DTCCR_RRS_1 = 0x1

	// DTCST: DTC Module Start Register
	// Position of DTCST field.
	DTC_DTCST_DTCST_Pos = 0x0
	// Bit mask of DTCST field.
	DTC_DTCST_DTCST_Msk = 0x1
	// Bit DTCST.
	DTC_DTCST_DTCST = 0x1
	// DTC module stopped.
	DTC_DTCST_DTCST_0 = 0x0
	// DTC module started.
	DTC_DTCST_DTCST_1 = 0x1

	// DTCSTS: DTC Status Register
	// Position of VECN field.
	DTC_DTCSTS_VECN_Pos = 0x0
	// Bit mask of VECN field.
	DTC_DTCSTS_VECN_Msk = 0xff
	// Position of ACT field.
	DTC_DTCSTS_ACT_Pos = 0xf
	// Bit mask of ACT field.
	DTC_DTCSTS_ACT_Msk = 0x8000
	// Bit ACT.
	DTC_DTCSTS_ACT = 0x8000
	// DTC transfer operation is not in progress.
	DTC_DTCSTS_ACT_0 = 0x0
	// DTC transfer operation is in progress.
	DTC_DTCSTS_ACT_1 = 0x1

	// DTCCR_SEC: DTC Control Register for secure Region
	// Position of RRS field.
	DTC_DTCCR_SEC_RRS_Pos = 0x4
	// Bit mask of RRS field.
	DTC_DTCCR_SEC_RRS_Msk = 0x10
	// Bit RRS.
	DTC_DTCCR_SEC_RRS = 0x10
	// Transfer information read is not skipped.
	DTC_DTCCR_SEC_RRS_0 = 0x0
	// Transfer information read is skipped when vector numbers match.
	DTC_DTCCR_SEC_RRS_1 = 0x1

	// DTEVR: DTC Error Vector Register
	// Position of DTEV field.
	DTC_DTEVR_DTEV_Pos = 0x0
	// Bit mask of DTEV field.
	DTC_DTEVR_DTEV_Msk = 0xff
	// Position of DTEVSAM field.
	DTC_DTEVR_DTEVSAM_Pos = 0x8
	// Bit mask of DTEVSAM field.
	DTC_DTEVR_DTEVSAM_Msk = 0x100
	// Bit DTEVSAM.
	DTC_DTEVR_DTEVSAM = 0x100
	// Secure vector number
	DTC_DTEVR_DTEVSAM_0 = 0x0
	// Non-Secure vector number
	DTC_DTEVR_DTEVSAM_1 = 0x1
	// Position of DTESTA field.
	DTC_DTEVR_DTESTA_Pos = 0x10
	// Bit mask of DTESTA field.
	DTC_DTEVR_DTESTA_Msk = 0x10000
	// Bit DTESTA.
	DTC_DTEVR_DTESTA = 0x10000
	// No DTC transfer error occurred
	DTC_DTEVR_DTESTA_0 = 0x0
	// DTC transfer error occurred
	DTC_DTEVR_DTESTA_1 = 0x1
)

// Constants for ICU: Interrupt Controller
const (
	// IRQCR0: IRQ Control Register %s
	// Position of IRQMD field.
	ICU_IRQCR_IRQMD_Pos = 0x0
	// Bit mask of IRQMD field.
	ICU_IRQCR_IRQMD_Msk = 0x3
	// Falling edge
	ICU_IRQCR_IRQMD_00 = 0x0
	// Rising edge
	ICU_IRQCR_IRQMD_01 = 0x1
	// Rising and falling edges
	ICU_IRQCR_IRQMD_10 = 0x2
	// Low level
	ICU_IRQCR_IRQMD_11 = 0x3
	// Position of FCLKSEL field.
	ICU_IRQCR_FCLKSEL_Pos = 0x4
	// Bit mask of FCLKSEL field.
	ICU_IRQCR_FCLKSEL_Msk = 0x30
	// PCLKB
	ICU_IRQCR_FCLKSEL_00 = 0x0
	// PCLKB/8
	ICU_IRQCR_FCLKSEL_01 = 0x1
	// PCLKB/32
	ICU_IRQCR_FCLKSEL_10 = 0x2
	// PCLKB/64
	ICU_IRQCR_FCLKSEL_11 = 0x3
	// Position of FLTEN field.
	ICU_IRQCR_FLTEN_Pos = 0x7
	// Bit mask of FLTEN field.
	ICU_IRQCR_FLTEN_Msk = 0x80
	// Bit FLTEN.
	ICU_IRQCR_FLTEN = 0x80
	// Digital filter is disabled
	ICU_IRQCR_FLTEN_0 = 0x0
	// Digital filter is enabled.
	ICU_IRQCR_FLTEN_1 = 0x1

	// NMICR: NMI Pin Interrupt Control Register
	// Position of NMIMD field.
	ICU_NMICR_NMIMD_Pos = 0x0
	// Bit mask of NMIMD field.
	ICU_NMICR_NMIMD_Msk = 0x1
	// Bit NMIMD.
	ICU_NMICR_NMIMD = 0x1
	// Falling edge
	ICU_NMICR_NMIMD_0 = 0x0
	// Rising edge
	ICU_NMICR_NMIMD_1 = 0x1
	// Position of NFCLKSEL field.
	ICU_NMICR_NFCLKSEL_Pos = 0x4
	// Bit mask of NFCLKSEL field.
	ICU_NMICR_NFCLKSEL_Msk = 0x30
	// PCLKB
	ICU_NMICR_NFCLKSEL_00 = 0x0
	// PCLKB/8
	ICU_NMICR_NFCLKSEL_01 = 0x1
	// PCLKB/32
	ICU_NMICR_NFCLKSEL_10 = 0x2
	// PCLKB/64
	ICU_NMICR_NFCLKSEL_11 = 0x3
	// Position of NFLTEN field.
	ICU_NMICR_NFLTEN_Pos = 0x7
	// Bit mask of NFLTEN field.
	ICU_NMICR_NFLTEN_Msk = 0x80
	// Bit NFLTEN.
	ICU_NMICR_NFLTEN = 0x80
	// Disabled.
	ICU_NMICR_NFLTEN_0 = 0x0
	// Enabled.
	ICU_NMICR_NFLTEN_1 = 0x1

	// NMIER: Non-Maskable Interrupt Enable Register
	// Position of IWDTEN field.
	ICU_NMIER_IWDTEN_Pos = 0x0
	// Bit mask of IWDTEN field.
	ICU_NMIER_IWDTEN_Msk = 0x1
	// Bit IWDTEN.
	ICU_NMIER_IWDTEN = 0x1
	// Disabled
	ICU_NMIER_IWDTEN_0 = 0x0
	// Enabled.
	ICU_NMIER_IWDTEN_1 = 0x1
	// Position of WDTEN field.
	ICU_NMIER_WDTEN_Pos = 0x1
	// Bit mask of WDTEN field.
	ICU_NMIER_WDTEN_Msk = 0x2
	// Bit WDTEN.
	ICU_NMIER_WDTEN = 0x2
	// Disabled
	ICU_NMIER_WDTEN_0 = 0x0
	// Enabled
	ICU_NMIER_WDTEN_1 = 0x1
	// Position of LVD1EN field.
	ICU_NMIER_LVD1EN_Pos = 0x2
	// Bit mask of LVD1EN field.
	ICU_NMIER_LVD1EN_Msk = 0x4
	// Bit LVD1EN.
	ICU_NMIER_LVD1EN = 0x4
	// Disabled
	ICU_NMIER_LVD1EN_0 = 0x0
	// Enabled
	ICU_NMIER_LVD1EN_1 = 0x1
	// Position of LVD2EN field.
	ICU_NMIER_LVD2EN_Pos = 0x3
	// Bit mask of LVD2EN field.
	ICU_NMIER_LVD2EN_Msk = 0x8
	// Bit LVD2EN.
	ICU_NMIER_LVD2EN = 0x8
	// Disabled
	ICU_NMIER_LVD2EN_0 = 0x0
	// Enabled
	ICU_NMIER_LVD2EN_1 = 0x1
	// Position of OSTEN field.
	ICU_NMIER_OSTEN_Pos = 0x6
	// Bit mask of OSTEN field.
	ICU_NMIER_OSTEN_Msk = 0x40
	// Bit OSTEN.
	ICU_NMIER_OSTEN = 0x40
	// Disabled
	ICU_NMIER_OSTEN_0 = 0x0
	// Enabled
	ICU_NMIER_OSTEN_1 = 0x1
	// Position of NMIEN field.
	ICU_NMIER_NMIEN_Pos = 0x7
	// Bit mask of NMIEN field.
	ICU_NMIER_NMIEN_Msk = 0x80
	// Bit NMIEN.
	ICU_NMIER_NMIEN = 0x80
	// Disabled
	ICU_NMIER_NMIEN_0 = 0x0
	// Enabled
	ICU_NMIER_NMIEN_1 = 0x1
	// Position of RPEEN field.
	ICU_NMIER_RPEEN_Pos = 0x8
	// Bit mask of RPEEN field.
	ICU_NMIER_RPEEN_Msk = 0x100
	// Bit RPEEN.
	ICU_NMIER_RPEEN = 0x100
	// Disabled
	ICU_NMIER_RPEEN_0 = 0x0
	// Enabled
	ICU_NMIER_RPEEN_1 = 0x1
	// Position of RECCEN field.
	ICU_NMIER_RECCEN_Pos = 0x9
	// Bit mask of RECCEN field.
	ICU_NMIER_RECCEN_Msk = 0x200
	// Bit RECCEN.
	ICU_NMIER_RECCEN = 0x200
	// Disabled
	ICU_NMIER_RECCEN_0 = 0x0
	// Enabled
	ICU_NMIER_RECCEN_1 = 0x1
	// Position of BUSMEN field.
	ICU_NMIER_BUSMEN_Pos = 0xb
	// Bit mask of BUSMEN field.
	ICU_NMIER_BUSMEN_Msk = 0x800
	// Bit BUSMEN.
	ICU_NMIER_BUSMEN = 0x800
	// Disabled
	ICU_NMIER_BUSMEN_0 = 0x0
	// Enabled
	ICU_NMIER_BUSMEN_1 = 0x1
	// Position of TZFEN field.
	ICU_NMIER_TZFEN_Pos = 0xd
	// Bit mask of TZFEN field.
	ICU_NMIER_TZFEN_Msk = 0x2000
	// Bit TZFEN.
	ICU_NMIER_TZFEN = 0x2000
	// Disabled
	ICU_NMIER_TZFEN_0 = 0x0
	// Enabled
	ICU_NMIER_TZFEN_1 = 0x1
	// Position of CPEEN field.
	ICU_NMIER_CPEEN_Pos = 0xf
	// Bit mask of CPEEN field.
	ICU_NMIER_CPEEN_Msk = 0x8000
	// Bit CPEEN.
	ICU_NMIER_CPEEN = 0x8000
	// Disabled
	ICU_NMIER_CPEEN_0 = 0x0
	// Enabled
	ICU_NMIER_CPEEN_1 = 0x1

	// NMICLR: Non-Maskable Interrupt Status Clear Register
	// Position of IWDTCLR field.
	ICU_NMICLR_IWDTCLR_Pos = 0x0
	// Bit mask of IWDTCLR field.
	ICU_NMICLR_IWDTCLR_Msk = 0x1
	// Bit IWDTCLR.
	ICU_NMICLR_IWDTCLR = 0x1
	// No effect
	ICU_NMICLR_IWDTCLR_0 = 0x0
	// Clear the NMISR.IWDTST flag
	ICU_NMICLR_IWDTCLR_1 = 0x1
	// Position of WDTCLR field.
	ICU_NMICLR_WDTCLR_Pos = 0x1
	// Bit mask of WDTCLR field.
	ICU_NMICLR_WDTCLR_Msk = 0x2
	// Bit WDTCLR.
	ICU_NMICLR_WDTCLR = 0x2
	// No effect
	ICU_NMICLR_WDTCLR_0 = 0x0
	// Clear the NMISR.WDTST flag
	ICU_NMICLR_WDTCLR_1 = 0x1
	// Position of LVD1CLR field.
	ICU_NMICLR_LVD1CLR_Pos = 0x2
	// Bit mask of LVD1CLR field.
	ICU_NMICLR_LVD1CLR_Msk = 0x4
	// Bit LVD1CLR.
	ICU_NMICLR_LVD1CLR = 0x4
	// No effect
	ICU_NMICLR_LVD1CLR_0 = 0x0
	// Clear the NMISR.LVD1ST flag
	ICU_NMICLR_LVD1CLR_1 = 0x1
	// Position of LVD2CLR field.
	ICU_NMICLR_LVD2CLR_Pos = 0x3
	// Bit mask of LVD2CLR field.
	ICU_NMICLR_LVD2CLR_Msk = 0x8
	// Bit LVD2CLR.
	ICU_NMICLR_LVD2CLR = 0x8
	// No effect
	ICU_NMICLR_LVD2CLR_0 = 0x0
	// Clear the NMISR.LVD2ST flag.
	ICU_NMICLR_LVD2CLR_1 = 0x1
	// Position of OSTCLR field.
	ICU_NMICLR_OSTCLR_Pos = 0x6
	// Bit mask of OSTCLR field.
	ICU_NMICLR_OSTCLR_Msk = 0x40
	// Bit OSTCLR.
	ICU_NMICLR_OSTCLR = 0x40
	// No effect
	ICU_NMICLR_OSTCLR_0 = 0x0
	// Clear the NMISR.OSTST flag
	ICU_NMICLR_OSTCLR_1 = 0x1
	// Position of NMICLR field.
	ICU_NMICLR_NMICLR_Pos = 0x7
	// Bit mask of NMICLR field.
	ICU_NMICLR_NMICLR_Msk = 0x80
	// Bit NMICLR.
	ICU_NMICLR_NMICLR = 0x80
	// No effect
	ICU_NMICLR_NMICLR_0 = 0x0
	// Clear the NMISR.NMIST flag
	ICU_NMICLR_NMICLR_1 = 0x1
	// Position of RPECLR field.
	ICU_NMICLR_RPECLR_Pos = 0x8
	// Bit mask of RPECLR field.
	ICU_NMICLR_RPECLR_Msk = 0x100
	// Bit RPECLR.
	ICU_NMICLR_RPECLR = 0x100
	// No effect
	ICU_NMICLR_RPECLR_0 = 0x0
	// Clear the NMISR.RPEST flag
	ICU_NMICLR_RPECLR_1 = 0x1
	// Position of RECCCLR field.
	ICU_NMICLR_RECCCLR_Pos = 0x9
	// Bit mask of RECCCLR field.
	ICU_NMICLR_RECCCLR_Msk = 0x200
	// Bit RECCCLR.
	ICU_NMICLR_RECCCLR = 0x200
	// No effect
	ICU_NMICLR_RECCCLR_0 = 0x0
	// Clear the NMISR.RECCST flag
	ICU_NMICLR_RECCCLR_1 = 0x1
	// Position of BUSMCLR field.
	ICU_NMICLR_BUSMCLR_Pos = 0xb
	// Bit mask of BUSMCLR field.
	ICU_NMICLR_BUSMCLR_Msk = 0x800
	// Bit BUSMCLR.
	ICU_NMICLR_BUSMCLR = 0x800
	// No effect
	ICU_NMICLR_BUSMCLR_0 = 0x0
	// Clear the NMISR.BUSMST flag
	ICU_NMICLR_BUSMCLR_1 = 0x1
	// Position of TZFCLR field.
	ICU_NMICLR_TZFCLR_Pos = 0xd
	// Bit mask of TZFCLR field.
	ICU_NMICLR_TZFCLR_Msk = 0x2000
	// Bit TZFCLR.
	ICU_NMICLR_TZFCLR = 0x2000
	// No effect
	ICU_NMICLR_TZFCLR_0 = 0x0
	// Clear the NMISR.TZFCLR flag
	ICU_NMICLR_TZFCLR_1 = 0x1
	// Position of CPECLR field.
	ICU_NMICLR_CPECLR_Pos = 0xf
	// Bit mask of CPECLR field.
	ICU_NMICLR_CPECLR_Msk = 0x8000
	// Bit CPECLR.
	ICU_NMICLR_CPECLR = 0x8000
	// No effect
	ICU_NMICLR_CPECLR_0 = 0x0
	// Clear the NMISR.CPECLR flag
	ICU_NMICLR_CPECLR_1 = 0x1

	// NMISR: Non-Maskable Interrupt Status Register
	// Position of IWDTST field.
	ICU_NMISR_IWDTST_Pos = 0x0
	// Bit mask of IWDTST field.
	ICU_NMISR_IWDTST_Msk = 0x1
	// Bit IWDTST.
	ICU_NMISR_IWDTST = 0x1
	// Interrupt not requested
	ICU_NMISR_IWDTST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_IWDTST_1 = 0x1
	// Position of WDTST field.
	ICU_NMISR_WDTST_Pos = 0x1
	// Bit mask of WDTST field.
	ICU_NMISR_WDTST_Msk = 0x2
	// Bit WDTST.
	ICU_NMISR_WDTST = 0x2
	// Interrupt not requested
	ICU_NMISR_WDTST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_WDTST_1 = 0x1
	// Position of LVD1ST field.
	ICU_NMISR_LVD1ST_Pos = 0x2
	// Bit mask of LVD1ST field.
	ICU_NMISR_LVD1ST_Msk = 0x4
	// Bit LVD1ST.
	ICU_NMISR_LVD1ST = 0x4
	// Interrupt not requested
	ICU_NMISR_LVD1ST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_LVD1ST_1 = 0x1
	// Position of LVD2ST field.
	ICU_NMISR_LVD2ST_Pos = 0x3
	// Bit mask of LVD2ST field.
	ICU_NMISR_LVD2ST_Msk = 0x8
	// Bit LVD2ST.
	ICU_NMISR_LVD2ST = 0x8
	// Interrupt not requested
	ICU_NMISR_LVD2ST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_LVD2ST_1 = 0x1
	// Position of OSTST field.
	ICU_NMISR_OSTST_Pos = 0x6
	// Bit mask of OSTST field.
	ICU_NMISR_OSTST_Msk = 0x40
	// Bit OSTST.
	ICU_NMISR_OSTST = 0x40
	// Interrupt not requested for main clock oscillation stop
	ICU_NMISR_OSTST_0 = 0x0
	// Interrupt requested for main clock oscillation stop
	ICU_NMISR_OSTST_1 = 0x1
	// Position of NMIST field.
	ICU_NMISR_NMIST_Pos = 0x7
	// Bit mask of NMIST field.
	ICU_NMISR_NMIST_Msk = 0x80
	// Bit NMIST.
	ICU_NMISR_NMIST = 0x80
	// Interrupt not requested
	ICU_NMISR_NMIST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_NMIST_1 = 0x1
	// Position of RPEST field.
	ICU_NMISR_RPEST_Pos = 0x8
	// Bit mask of RPEST field.
	ICU_NMISR_RPEST_Msk = 0x100
	// Bit RPEST.
	ICU_NMISR_RPEST = 0x100
	// Interrupt not requested
	ICU_NMISR_RPEST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_RPEST_1 = 0x1
	// Position of RECCST field.
	ICU_NMISR_RECCST_Pos = 0x9
	// Bit mask of RECCST field.
	ICU_NMISR_RECCST_Msk = 0x200
	// Bit RECCST.
	ICU_NMISR_RECCST = 0x200
	// Interrupt not requested
	ICU_NMISR_RECCST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_RECCST_1 = 0x1
	// Position of BUSMST field.
	ICU_NMISR_BUSMST_Pos = 0xb
	// Bit mask of BUSMST field.
	ICU_NMISR_BUSMST_Msk = 0x800
	// Bit BUSMST.
	ICU_NMISR_BUSMST = 0x800
	// Interrupt not requested
	ICU_NMISR_BUSMST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_BUSMST_1 = 0x1
	// Position of TZFST field.
	ICU_NMISR_TZFST_Pos = 0xd
	// Bit mask of TZFST field.
	ICU_NMISR_TZFST_Msk = 0x2000
	// Bit TZFST.
	ICU_NMISR_TZFST = 0x2000
	// Interrupt not requested
	ICU_NMISR_TZFST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_TZFST_1 = 0x1
	// Position of CPEST field.
	ICU_NMISR_CPEST_Pos = 0xf
	// Bit mask of CPEST field.
	ICU_NMISR_CPEST_Msk = 0x8000
	// Bit CPEST.
	ICU_NMISR_CPEST = 0x8000
	// Interrupt not requested
	ICU_NMISR_CPEST_0 = 0x0
	// Interrupt requested
	ICU_NMISR_CPEST_1 = 0x1

	// WUPEN0: Wake Up Interrupt Enable Register 0
	// Position of IRQWUPEN field.
	ICU_WUPEN0_IRQWUPEN_Pos = 0x0
	// Bit mask of IRQWUPEN field.
	ICU_WUPEN0_IRQWUPEN_Msk = 0x7fff
	// Software Standby/Snooze Mode returns by IRQn interrupt is disabled
	ICU_WUPEN0_IRQWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by IRQn interrupt is enabled
	ICU_WUPEN0_IRQWUPEN_1 = 0x1
	// Position of IWDTWUPEN field.
	ICU_WUPEN0_IWDTWUPEN_Pos = 0x10
	// Bit mask of IWDTWUPEN field.
	ICU_WUPEN0_IWDTWUPEN_Msk = 0x10000
	// Bit IWDTWUPEN.
	ICU_WUPEN0_IWDTWUPEN = 0x10000
	// Software Standby/Snooze Mode returns by IWDT interrupt is disabled
	ICU_WUPEN0_IWDTWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by IWDT interrupt is enabled
	ICU_WUPEN0_IWDTWUPEN_1 = 0x1
	// Position of LVD1WUPEN field.
	ICU_WUPEN0_LVD1WUPEN_Pos = 0x12
	// Bit mask of LVD1WUPEN field.
	ICU_WUPEN0_LVD1WUPEN_Msk = 0x40000
	// Bit LVD1WUPEN.
	ICU_WUPEN0_LVD1WUPEN = 0x40000
	// Software Standby/Snooze Mode returns by LVD1 interrupt is disabled
	ICU_WUPEN0_LVD1WUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by LVD1 interrupt is enabled
	ICU_WUPEN0_LVD1WUPEN_1 = 0x1
	// Position of LVD2WUPEN field.
	ICU_WUPEN0_LVD2WUPEN_Pos = 0x13
	// Bit mask of LVD2WUPEN field.
	ICU_WUPEN0_LVD2WUPEN_Msk = 0x80000
	// Bit LVD2WUPEN.
	ICU_WUPEN0_LVD2WUPEN = 0x80000
	// Software Standby/Snooze Mode returns by LVD2 interrupt is disabled
	ICU_WUPEN0_LVD2WUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by LVD2 interrupt is enabled
	ICU_WUPEN0_LVD2WUPEN_1 = 0x1
	// Position of RTCALMWUPEN field.
	ICU_WUPEN0_RTCALMWUPEN_Pos = 0x18
	// Bit mask of RTCALMWUPEN field.
	ICU_WUPEN0_RTCALMWUPEN_Msk = 0x1000000
	// Bit RTCALMWUPEN.
	ICU_WUPEN0_RTCALMWUPEN = 0x1000000
	// Software Standby/Snooze Mode returns by RTC alarm interrupt is disabled
	ICU_WUPEN0_RTCALMWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by RTC alarm interrupt is enabled
	ICU_WUPEN0_RTCALMWUPEN_1 = 0x1
	// Position of RTCPRDWUPEN field.
	ICU_WUPEN0_RTCPRDWUPEN_Pos = 0x19
	// Bit mask of RTCPRDWUPEN field.
	ICU_WUPEN0_RTCPRDWUPEN_Msk = 0x2000000
	// Bit RTCPRDWUPEN.
	ICU_WUPEN0_RTCPRDWUPEN = 0x2000000
	// Software Standby/Snooze Mode returns by RTC period interrupt is disabled
	ICU_WUPEN0_RTCPRDWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by RTC period interrupt is enabled
	ICU_WUPEN0_RTCPRDWUPEN_1 = 0x1
	// Position of USBFS0WUPEN field.
	ICU_WUPEN0_USBFS0WUPEN_Pos = 0x1b
	// Bit mask of USBFS0WUPEN field.
	ICU_WUPEN0_USBFS0WUPEN_Msk = 0x8000000
	// Bit USBFS0WUPEN.
	ICU_WUPEN0_USBFS0WUPEN = 0x8000000
	// Software Standby/Snooze Mode returns by USBFS0 interrupt is disabled
	ICU_WUPEN0_USBFS0WUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by USBFS0 interrupt is enabled
	ICU_WUPEN0_USBFS0WUPEN_1 = 0x1
	// Position of AGT1UDWUPEN field.
	ICU_WUPEN0_AGT1UDWUPEN_Pos = 0x1c
	// Bit mask of AGT1UDWUPEN field.
	ICU_WUPEN0_AGT1UDWUPEN_Msk = 0x10000000
	// Bit AGT1UDWUPEN.
	ICU_WUPEN0_AGT1UDWUPEN = 0x10000000
	// Software Standby/Snooze Mode returns by AGT1 underflow interrupt is disabled
	ICU_WUPEN0_AGT1UDWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by AGT1 underflow interrupt is enabled
	ICU_WUPEN0_AGT1UDWUPEN_1 = 0x1
	// Position of AGT1CAWUPEN field.
	ICU_WUPEN0_AGT1CAWUPEN_Pos = 0x1d
	// Bit mask of AGT1CAWUPEN field.
	ICU_WUPEN0_AGT1CAWUPEN_Msk = 0x20000000
	// Bit AGT1CAWUPEN.
	ICU_WUPEN0_AGT1CAWUPEN = 0x20000000
	// Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is disabled
	ICU_WUPEN0_AGT1CAWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is enabled
	ICU_WUPEN0_AGT1CAWUPEN_1 = 0x1
	// Position of AGT1CBWUPEN field.
	ICU_WUPEN0_AGT1CBWUPEN_Pos = 0x1e
	// Bit mask of AGT1CBWUPEN field.
	ICU_WUPEN0_AGT1CBWUPEN_Msk = 0x40000000
	// Bit AGT1CBWUPEN.
	ICU_WUPEN0_AGT1CBWUPEN = 0x40000000
	// Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is disabled
	ICU_WUPEN0_AGT1CBWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is enabled
	ICU_WUPEN0_AGT1CBWUPEN_1 = 0x1

	// WUPEN1: Wake Up Interrupt Enable Register 1
	// Position of I3CWUPEN field.
	ICU_WUPEN1_I3CWUPEN_Pos = 0xb
	// Bit mask of I3CWUPEN field.
	ICU_WUPEN1_I3CWUPEN_Msk = 0x800
	// Bit I3CWUPEN.
	ICU_WUPEN1_I3CWUPEN = 0x800
	// Software Standby/Snooze Mode returns by I3C address match interrupt is disabled
	ICU_WUPEN1_I3CWUPEN_0 = 0x0
	// Software Standby/Snooze Mode returns by I3C address match interrupt is enabled
	ICU_WUPEN1_I3CWUPEN_1 = 0x1

	// DELSR0: DMAC Event Link Setting Register %s
	// Position of DELS field.
	ICU_DELSR_DELS_Pos = 0x0
	// Bit mask of DELS field.
	ICU_DELSR_DELS_Msk = 0x1ff
	// Disable interrupts to the associated DMAC module.
	ICU_DELSR_DELS_0x00 = 0x0
	// Event signal number to be linked. For details, see .
	ICU_DELSR_DELS_Others = 0x1
	// Position of IR field.
	ICU_DELSR_IR_Pos = 0x10
	// Bit mask of IR field.
	ICU_DELSR_IR_Msk = 0x10000
	// Bit IR.
	ICU_DELSR_IR = 0x10000
	// No DMAC activation request occurred.
	ICU_DELSR_IR_0 = 0x0
	// DMAC activation request occurred.
	ICU_DELSR_IR_1 = 0x1
)

// Constants for CACHE: CACHE
const (
	// CCACTL: C-Cache Control Register
	// Position of ENC field.
	CACHE_CCACTL_ENC_Pos = 0x0
	// Bit mask of ENC field.
	CACHE_CCACTL_ENC_Msk = 0x1
	// Bit ENC.
	CACHE_CCACTL_ENC = 0x1
	// Disable C-cache
	CACHE_CCACTL_ENC_0 = 0x0
	// Enable C-cache
	CACHE_CCACTL_ENC_1 = 0x1

	// CCAFCT: C-Cache Flush Control Register
	// Position of FC field.
	CACHE_CCAFCT_FC_Pos = 0x0
	// Bit mask of FC field.
	CACHE_CCAFCT_FC_Msk = 0x1
	// Bit FC.
	CACHE_CCAFCT_FC = 0x1
	// No action
	CACHE_CCAFCT_FC_0 = 0x0
	// C-cache line flush (all lines invalidated)
	CACHE_CCAFCT_FC_1 = 0x1

	// CCALCF: C-Cache Line Configuration Register
	// Position of CC field.
	CACHE_CCALCF_CC_Pos = 0x0
	// Bit mask of CC field.
	CACHE_CCALCF_CC_Msk = 0x3
	// Prohibited
	CACHE_CCALCF_CC_00 = 0x0
	// Cache line size 32 bytes
	CACHE_CCALCF_CC_01 = 0x1
	// Cache line size 64 bytes
	CACHE_CCALCF_CC_10 = 0x2
	// Prohibited
	CACHE_CCALCF_CC_11 = 0x3

	// SCACTL: S-Cache Control Register
	// Position of ENS field.
	CACHE_SCACTL_ENS_Pos = 0x0
	// Bit mask of ENS field.
	CACHE_SCACTL_ENS_Msk = 0x1
	// Bit ENS.
	CACHE_SCACTL_ENS = 0x1
	// Disable S-cache
	CACHE_SCACTL_ENS_0 = 0x0
	// Enable S-cache
	CACHE_SCACTL_ENS_1 = 0x1

	// SCAFCT: S-Cache Flush Control Register
	// Position of FS field.
	CACHE_SCAFCT_FS_Pos = 0x0
	// Bit mask of FS field.
	CACHE_SCAFCT_FS_Msk = 0x1
	// Bit FS.
	CACHE_SCAFCT_FS = 0x1
	// No action
	CACHE_SCAFCT_FS_0 = 0x0
	// S-cache line flush (all lines invalidated)
	CACHE_SCAFCT_FS_1 = 0x1

	// SCALCF: S-Cache Line Configuration Register
	// Position of CS field.
	CACHE_SCALCF_CS_Pos = 0x0
	// Bit mask of CS field.
	CACHE_SCALCF_CS_Msk = 0x3
	// Prohibited
	CACHE_SCALCF_CS_00 = 0x0
	// Cache line size 32 bytes
	CACHE_SCALCF_CS_01 = 0x1
	// Cache line size 64 bytes
	CACHE_SCALCF_CS_10 = 0x2
	// Prohibited
	CACHE_SCALCF_CS_11 = 0x3

	// CAPOAD: Cache Parity Error Operation After Detection Register
	// Position of OAD field.
	CACHE_CAPOAD_OAD_Pos = 0x0
	// Bit mask of OAD field.
	CACHE_CAPOAD_OAD_Msk = 0x1
	// Bit OAD.
	CACHE_CAPOAD_OAD = 0x1
	// Non-maskable interrupt
	CACHE_CAPOAD_OAD_0 = 0x0
	// Reset
	CACHE_CAPOAD_OAD_1 = 0x1

	// CAPRCR: Cache Protection Register
	// Position of PRCR field.
	CACHE_CAPRCR_PRCR_Pos = 0x0
	// Bit mask of PRCR field.
	CACHE_CAPRCR_PRCR_Msk = 0x1
	// Bit PRCR.
	CACHE_CAPRCR_PRCR = 0x1
	// Disable writes to protected registers
	CACHE_CAPRCR_PRCR_0 = 0x0
	// Enable writes to protected registers
	CACHE_CAPRCR_PRCR_1 = 0x1
	// Position of KW field.
	CACHE_CAPRCR_KW_Pos = 0x1
	// Bit mask of KW field.
	CACHE_CAPRCR_KW_Msk = 0xfe
)

// Constants for CPSCU: CPU System Security Control Unit
const (
	// CSAR: Cache Security Attribution Register
	// Position of CACHESA field.
	CPSCU_CSAR_CACHESA_Pos = 0x0
	// Bit mask of CACHESA field.
	CPSCU_CSAR_CACHESA_Msk = 0x1
	// Bit CACHESA.
	CPSCU_CSAR_CACHESA = 0x1
	// Secure
	CPSCU_CSAR_CACHESA_0 = 0x0
	// Non-secure
	CPSCU_CSAR_CACHESA_1 = 0x1
	// Position of CACHELSA field.
	CPSCU_CSAR_CACHELSA_Pos = 0x1
	// Bit mask of CACHELSA field.
	CPSCU_CSAR_CACHELSA_Msk = 0x2
	// Bit CACHELSA.
	CPSCU_CSAR_CACHELSA = 0x2
	// Secure
	CPSCU_CSAR_CACHELSA_0 = 0x0
	// Non-secure
	CPSCU_CSAR_CACHELSA_1 = 0x1
	// Position of CACHEESA field.
	CPSCU_CSAR_CACHEESA_Pos = 0x2
	// Bit mask of CACHEESA field.
	CPSCU_CSAR_CACHEESA_Msk = 0x4
	// Bit CACHEESA.
	CPSCU_CSAR_CACHEESA = 0x4
	// Secure
	CPSCU_CSAR_CACHEESA_0 = 0x0
	// Non-secure
	CPSCU_CSAR_CACHEESA_1 = 0x1

	// SRAMSAR: SRAM Security Attribution Register
	// Position of SRAMSA0 field.
	CPSCU_SRAMSAR_SRAMSA0_Pos = 0x0
	// Bit mask of SRAMSA0 field.
	CPSCU_SRAMSAR_SRAMSA0_Msk = 0x1
	// Bit SRAMSA0.
	CPSCU_SRAMSAR_SRAMSA0 = 0x1
	// Secure
	CPSCU_SRAMSAR_SRAMSA0_0 = 0x0
	// Non-Secure
	CPSCU_SRAMSAR_SRAMSA0_1 = 0x1
	// Position of SRAMSA1 field.
	CPSCU_SRAMSAR_SRAMSA1_Pos = 0x1
	// Bit mask of SRAMSA1 field.
	CPSCU_SRAMSAR_SRAMSA1_Msk = 0x2
	// Bit SRAMSA1.
	CPSCU_SRAMSAR_SRAMSA1 = 0x2
	// Secure
	CPSCU_SRAMSAR_SRAMSA1_0 = 0x0
	// Non-Secure
	CPSCU_SRAMSAR_SRAMSA1_1 = 0x1
	// Position of SRAMSA2 field.
	CPSCU_SRAMSAR_SRAMSA2_Pos = 0x2
	// Bit mask of SRAMSA2 field.
	CPSCU_SRAMSAR_SRAMSA2_Msk = 0x4
	// Bit SRAMSA2.
	CPSCU_SRAMSAR_SRAMSA2 = 0x4
	// Secure
	CPSCU_SRAMSAR_SRAMSA2_0 = 0x0
	// Non-Secure
	CPSCU_SRAMSAR_SRAMSA2_1 = 0x1

	// STBRAMSAR: Standby RAM memory Security Attribution Register
	// Position of NSBSTBR field.
	CPSCU_STBRAMSAR_NSBSTBR_Pos = 0x0
	// Bit mask of NSBSTBR field.
	CPSCU_STBRAMSAR_NSBSTBR_Msk = 0xf
	// Region7-0 are all Secure.
	CPSCU_STBRAMSAR_NSBSTBR_0x0 = 0x0
	// Region7 is Non-secure. Region6-0 are Secure
	CPSCU_STBRAMSAR_NSBSTBR_0x1 = 0x1
	// Region7-6 are Non-secure. Region5-0 are Secure.
	CPSCU_STBRAMSAR_NSBSTBR_0x2 = 0x2
	// Region7-5 are Non-secure. Region4-0 are Secure.
	CPSCU_STBRAMSAR_NSBSTBR_0x3 = 0x3
	// Region7-4 are Non-secure. Region 3-0 are Secure.
	CPSCU_STBRAMSAR_NSBSTBR_0x4 = 0x4
	// Region7-3 are Non-secure. Region 2-0 are Secure.
	CPSCU_STBRAMSAR_NSBSTBR_0x5 = 0x5
	// Region7-2 are Non-secure. Region 1-0 are Secure.
	CPSCU_STBRAMSAR_NSBSTBR_0x6 = 0x6
	// Region7-1 are Non-Secure. Region0 is Secure.
	CPSCU_STBRAMSAR_NSBSTBR_0x7 = 0x7
	// Region7-0 are all Non-Secure.
	CPSCU_STBRAMSAR_NSBSTBR_Others = 0x8

	// DTCSAR: DTC Controller Security Attribution Register
	// Position of DTCSTSA field.
	CPSCU_DTCSAR_DTCSTSA_Pos = 0x0
	// Bit mask of DTCSTSA field.
	CPSCU_DTCSAR_DTCSTSA_Msk = 0x1
	// Bit DTCSTSA.
	CPSCU_DTCSAR_DTCSTSA = 0x1
	// Secure.
	CPSCU_DTCSAR_DTCSTSA_0 = 0x0
	// Non-Secure.
	CPSCU_DTCSAR_DTCSTSA_1 = 0x1

	// DMACSAR: DMAC Controller Security Attribution Register
	// Position of DMASTSA field.
	CPSCU_DMACSAR_DMASTSA_Pos = 0x0
	// Bit mask of DMASTSA field.
	CPSCU_DMACSAR_DMASTSA_Msk = 0x1
	// Bit DMASTSA.
	CPSCU_DMACSAR_DMASTSA = 0x1
	// Secure
	CPSCU_DMACSAR_DMASTSA_0 = 0x0
	// Non-secure
	CPSCU_DMACSAR_DMASTSA_1 = 0x1

	// ICUSARA: Interrupt Controller Unit Security Attribution Register A
	// Position of SAIRQCR00 field.
	CPSCU_ICUSARA_SAIRQCR00_Pos = 0x0
	// Bit mask of SAIRQCR00 field.
	CPSCU_ICUSARA_SAIRQCR00_Msk = 0x1
	// Bit SAIRQCR00.
	CPSCU_ICUSARA_SAIRQCR00 = 0x1
	// Secure
	CPSCU_ICUSARA_SAIRQCR00_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR00_1 = 0x1
	// Position of SAIRQCR01 field.
	CPSCU_ICUSARA_SAIRQCR01_Pos = 0x1
	// Bit mask of SAIRQCR01 field.
	CPSCU_ICUSARA_SAIRQCR01_Msk = 0x2
	// Bit SAIRQCR01.
	CPSCU_ICUSARA_SAIRQCR01 = 0x2
	// Secure
	CPSCU_ICUSARA_SAIRQCR01_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR01_1 = 0x1
	// Position of SAIRQCR02 field.
	CPSCU_ICUSARA_SAIRQCR02_Pos = 0x2
	// Bit mask of SAIRQCR02 field.
	CPSCU_ICUSARA_SAIRQCR02_Msk = 0x4
	// Bit SAIRQCR02.
	CPSCU_ICUSARA_SAIRQCR02 = 0x4
	// Secure
	CPSCU_ICUSARA_SAIRQCR02_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR02_1 = 0x1
	// Position of SAIRQCR03 field.
	CPSCU_ICUSARA_SAIRQCR03_Pos = 0x3
	// Bit mask of SAIRQCR03 field.
	CPSCU_ICUSARA_SAIRQCR03_Msk = 0x8
	// Bit SAIRQCR03.
	CPSCU_ICUSARA_SAIRQCR03 = 0x8
	// Secure
	CPSCU_ICUSARA_SAIRQCR03_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR03_1 = 0x1
	// Position of SAIRQCR04 field.
	CPSCU_ICUSARA_SAIRQCR04_Pos = 0x4
	// Bit mask of SAIRQCR04 field.
	CPSCU_ICUSARA_SAIRQCR04_Msk = 0x10
	// Bit SAIRQCR04.
	CPSCU_ICUSARA_SAIRQCR04 = 0x10
	// Secure
	CPSCU_ICUSARA_SAIRQCR04_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR04_1 = 0x1
	// Position of SAIRQCR05 field.
	CPSCU_ICUSARA_SAIRQCR05_Pos = 0x5
	// Bit mask of SAIRQCR05 field.
	CPSCU_ICUSARA_SAIRQCR05_Msk = 0x20
	// Bit SAIRQCR05.
	CPSCU_ICUSARA_SAIRQCR05 = 0x20
	// Secure
	CPSCU_ICUSARA_SAIRQCR05_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR05_1 = 0x1
	// Position of SAIRQCR06 field.
	CPSCU_ICUSARA_SAIRQCR06_Pos = 0x6
	// Bit mask of SAIRQCR06 field.
	CPSCU_ICUSARA_SAIRQCR06_Msk = 0x40
	// Bit SAIRQCR06.
	CPSCU_ICUSARA_SAIRQCR06 = 0x40
	// Secure
	CPSCU_ICUSARA_SAIRQCR06_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR06_1 = 0x1
	// Position of SAIRQCR07 field.
	CPSCU_ICUSARA_SAIRQCR07_Pos = 0x7
	// Bit mask of SAIRQCR07 field.
	CPSCU_ICUSARA_SAIRQCR07_Msk = 0x80
	// Bit SAIRQCR07.
	CPSCU_ICUSARA_SAIRQCR07 = 0x80
	// Secure
	CPSCU_ICUSARA_SAIRQCR07_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR07_1 = 0x1
	// Position of SAIRQCR08 field.
	CPSCU_ICUSARA_SAIRQCR08_Pos = 0x8
	// Bit mask of SAIRQCR08 field.
	CPSCU_ICUSARA_SAIRQCR08_Msk = 0x100
	// Bit SAIRQCR08.
	CPSCU_ICUSARA_SAIRQCR08 = 0x100
	// Secure
	CPSCU_ICUSARA_SAIRQCR08_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR08_1 = 0x1
	// Position of SAIRQCR09 field.
	CPSCU_ICUSARA_SAIRQCR09_Pos = 0x9
	// Bit mask of SAIRQCR09 field.
	CPSCU_ICUSARA_SAIRQCR09_Msk = 0x200
	// Bit SAIRQCR09.
	CPSCU_ICUSARA_SAIRQCR09 = 0x200
	// Secure
	CPSCU_ICUSARA_SAIRQCR09_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR09_1 = 0x1
	// Position of SAIRQCR10 field.
	CPSCU_ICUSARA_SAIRQCR10_Pos = 0xa
	// Bit mask of SAIRQCR10 field.
	CPSCU_ICUSARA_SAIRQCR10_Msk = 0x400
	// Bit SAIRQCR10.
	CPSCU_ICUSARA_SAIRQCR10 = 0x400
	// Secure
	CPSCU_ICUSARA_SAIRQCR10_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR10_1 = 0x1
	// Position of SAIRQCR11 field.
	CPSCU_ICUSARA_SAIRQCR11_Pos = 0xb
	// Bit mask of SAIRQCR11 field.
	CPSCU_ICUSARA_SAIRQCR11_Msk = 0x800
	// Bit SAIRQCR11.
	CPSCU_ICUSARA_SAIRQCR11 = 0x800
	// Secure
	CPSCU_ICUSARA_SAIRQCR11_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR11_1 = 0x1
	// Position of SAIRQCR12 field.
	CPSCU_ICUSARA_SAIRQCR12_Pos = 0xc
	// Bit mask of SAIRQCR12 field.
	CPSCU_ICUSARA_SAIRQCR12_Msk = 0x1000
	// Bit SAIRQCR12.
	CPSCU_ICUSARA_SAIRQCR12 = 0x1000
	// Secure
	CPSCU_ICUSARA_SAIRQCR12_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR12_1 = 0x1
	// Position of SAIRQCR13 field.
	CPSCU_ICUSARA_SAIRQCR13_Pos = 0xd
	// Bit mask of SAIRQCR13 field.
	CPSCU_ICUSARA_SAIRQCR13_Msk = 0x2000
	// Bit SAIRQCR13.
	CPSCU_ICUSARA_SAIRQCR13 = 0x2000
	// Secure
	CPSCU_ICUSARA_SAIRQCR13_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR13_1 = 0x1
	// Position of SAIRQCR14 field.
	CPSCU_ICUSARA_SAIRQCR14_Pos = 0xe
	// Bit mask of SAIRQCR14 field.
	CPSCU_ICUSARA_SAIRQCR14_Msk = 0x4000
	// Bit SAIRQCR14.
	CPSCU_ICUSARA_SAIRQCR14 = 0x4000
	// Secure
	CPSCU_ICUSARA_SAIRQCR14_0 = 0x0
	// Non-secure
	CPSCU_ICUSARA_SAIRQCR14_1 = 0x1

	// ICUSARB: Interrupt Controller Unit Security Attribution Register B
	// Position of SANMI field.
	CPSCU_ICUSARB_SANMI_Pos = 0x0
	// Bit mask of SANMI field.
	CPSCU_ICUSARB_SANMI_Msk = 0x1
	// Bit SANMI.
	CPSCU_ICUSARB_SANMI = 0x1
	// Secure
	CPSCU_ICUSARB_SANMI_0 = 0x0
	// Non-secure
	CPSCU_ICUSARB_SANMI_1 = 0x1

	// ICUSARC: Interrupt Controller Unit Security Attribution Register C
	// Position of SADMAC0 field.
	CPSCU_ICUSARC_SADMAC0_Pos = 0x0
	// Bit mask of SADMAC0 field.
	CPSCU_ICUSARC_SADMAC0_Msk = 0x1
	// Bit SADMAC0.
	CPSCU_ICUSARC_SADMAC0 = 0x1
	// Secure
	CPSCU_ICUSARC_SADMAC0_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC0_1 = 0x1
	// Position of SADMAC1 field.
	CPSCU_ICUSARC_SADMAC1_Pos = 0x1
	// Bit mask of SADMAC1 field.
	CPSCU_ICUSARC_SADMAC1_Msk = 0x2
	// Bit SADMAC1.
	CPSCU_ICUSARC_SADMAC1 = 0x2
	// Secure
	CPSCU_ICUSARC_SADMAC1_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC1_1 = 0x1
	// Position of SADMAC2 field.
	CPSCU_ICUSARC_SADMAC2_Pos = 0x2
	// Bit mask of SADMAC2 field.
	CPSCU_ICUSARC_SADMAC2_Msk = 0x4
	// Bit SADMAC2.
	CPSCU_ICUSARC_SADMAC2 = 0x4
	// Secure
	CPSCU_ICUSARC_SADMAC2_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC2_1 = 0x1
	// Position of SADMAC3 field.
	CPSCU_ICUSARC_SADMAC3_Pos = 0x3
	// Bit mask of SADMAC3 field.
	CPSCU_ICUSARC_SADMAC3_Msk = 0x8
	// Bit SADMAC3.
	CPSCU_ICUSARC_SADMAC3 = 0x8
	// Secure
	CPSCU_ICUSARC_SADMAC3_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC3_1 = 0x1
	// Position of SADMAC4 field.
	CPSCU_ICUSARC_SADMAC4_Pos = 0x4
	// Bit mask of SADMAC4 field.
	CPSCU_ICUSARC_SADMAC4_Msk = 0x10
	// Bit SADMAC4.
	CPSCU_ICUSARC_SADMAC4 = 0x10
	// Secure
	CPSCU_ICUSARC_SADMAC4_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC4_1 = 0x1
	// Position of SADMAC5 field.
	CPSCU_ICUSARC_SADMAC5_Pos = 0x5
	// Bit mask of SADMAC5 field.
	CPSCU_ICUSARC_SADMAC5_Msk = 0x20
	// Bit SADMAC5.
	CPSCU_ICUSARC_SADMAC5 = 0x20
	// Secure
	CPSCU_ICUSARC_SADMAC5_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC5_1 = 0x1
	// Position of SADMAC6 field.
	CPSCU_ICUSARC_SADMAC6_Pos = 0x6
	// Bit mask of SADMAC6 field.
	CPSCU_ICUSARC_SADMAC6_Msk = 0x40
	// Bit SADMAC6.
	CPSCU_ICUSARC_SADMAC6 = 0x40
	// Secure
	CPSCU_ICUSARC_SADMAC6_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC6_1 = 0x1
	// Position of SADMAC7 field.
	CPSCU_ICUSARC_SADMAC7_Pos = 0x7
	// Bit mask of SADMAC7 field.
	CPSCU_ICUSARC_SADMAC7_Msk = 0x80
	// Bit SADMAC7.
	CPSCU_ICUSARC_SADMAC7 = 0x80
	// Secure
	CPSCU_ICUSARC_SADMAC7_0 = 0x0
	// Non-secure
	CPSCU_ICUSARC_SADMAC7_1 = 0x1

	// ICUSARD: Interrupt Controller Unit Security Attribution Register D
	// Position of SASELSR0 field.
	CPSCU_ICUSARD_SASELSR0_Pos = 0x0
	// Bit mask of SASELSR0 field.
	CPSCU_ICUSARD_SASELSR0_Msk = 0x1
	// Bit SASELSR0.
	CPSCU_ICUSARD_SASELSR0 = 0x1
	// Secure
	CPSCU_ICUSARD_SASELSR0_0 = 0x0
	// Non-secure
	CPSCU_ICUSARD_SASELSR0_1 = 0x1

	// ICUSARF: Interrupt Controller Unit Security Attribution Register F
	// Position of SAI3CWUP field.
	CPSCU_ICUSARF_SAI3CWUP_Pos = 0xb
	// Bit mask of SAI3CWUP field.
	CPSCU_ICUSARF_SAI3CWUP_Msk = 0x800
	// Bit SAI3CWUP.
	CPSCU_ICUSARF_SAI3CWUP = 0x800
	// Secure
	CPSCU_ICUSARF_SAI3CWUP_0 = 0x0
	// Non-secure
	CPSCU_ICUSARF_SAI3CWUP_1 = 0x1

	// ICUSARG: Interrupt Controller Unit Security Attribution Register G
	// Position of SAIELSR00 field.
	CPSCU_ICUSARG_SAIELSR00_Pos = 0x0
	// Bit mask of SAIELSR00 field.
	CPSCU_ICUSARG_SAIELSR00_Msk = 0x1
	// Bit SAIELSR00.
	CPSCU_ICUSARG_SAIELSR00 = 0x1
	// Secure
	CPSCU_ICUSARG_SAIELSR00_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR00_1 = 0x1
	// Position of SAIELSR01 field.
	CPSCU_ICUSARG_SAIELSR01_Pos = 0x1
	// Bit mask of SAIELSR01 field.
	CPSCU_ICUSARG_SAIELSR01_Msk = 0x2
	// Bit SAIELSR01.
	CPSCU_ICUSARG_SAIELSR01 = 0x2
	// Secure
	CPSCU_ICUSARG_SAIELSR01_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR01_1 = 0x1
	// Position of SAIELSR02 field.
	CPSCU_ICUSARG_SAIELSR02_Pos = 0x2
	// Bit mask of SAIELSR02 field.
	CPSCU_ICUSARG_SAIELSR02_Msk = 0x4
	// Bit SAIELSR02.
	CPSCU_ICUSARG_SAIELSR02 = 0x4
	// Secure
	CPSCU_ICUSARG_SAIELSR02_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR02_1 = 0x1
	// Position of SAIELSR03 field.
	CPSCU_ICUSARG_SAIELSR03_Pos = 0x3
	// Bit mask of SAIELSR03 field.
	CPSCU_ICUSARG_SAIELSR03_Msk = 0x8
	// Bit SAIELSR03.
	CPSCU_ICUSARG_SAIELSR03 = 0x8
	// Secure
	CPSCU_ICUSARG_SAIELSR03_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR03_1 = 0x1
	// Position of SAIELSR04 field.
	CPSCU_ICUSARG_SAIELSR04_Pos = 0x4
	// Bit mask of SAIELSR04 field.
	CPSCU_ICUSARG_SAIELSR04_Msk = 0x10
	// Bit SAIELSR04.
	CPSCU_ICUSARG_SAIELSR04 = 0x10
	// Secure
	CPSCU_ICUSARG_SAIELSR04_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR04_1 = 0x1
	// Position of SAIELSR05 field.
	CPSCU_ICUSARG_SAIELSR05_Pos = 0x5
	// Bit mask of SAIELSR05 field.
	CPSCU_ICUSARG_SAIELSR05_Msk = 0x20
	// Bit SAIELSR05.
	CPSCU_ICUSARG_SAIELSR05 = 0x20
	// Secure
	CPSCU_ICUSARG_SAIELSR05_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR05_1 = 0x1
	// Position of SAIELSR06 field.
	CPSCU_ICUSARG_SAIELSR06_Pos = 0x6
	// Bit mask of SAIELSR06 field.
	CPSCU_ICUSARG_SAIELSR06_Msk = 0x40
	// Bit SAIELSR06.
	CPSCU_ICUSARG_SAIELSR06 = 0x40
	// Secure
	CPSCU_ICUSARG_SAIELSR06_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR06_1 = 0x1
	// Position of SAIELSR07 field.
	CPSCU_ICUSARG_SAIELSR07_Pos = 0x7
	// Bit mask of SAIELSR07 field.
	CPSCU_ICUSARG_SAIELSR07_Msk = 0x80
	// Bit SAIELSR07.
	CPSCU_ICUSARG_SAIELSR07 = 0x80
	// Secure
	CPSCU_ICUSARG_SAIELSR07_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR07_1 = 0x1
	// Position of SAIELSR08 field.
	CPSCU_ICUSARG_SAIELSR08_Pos = 0x8
	// Bit mask of SAIELSR08 field.
	CPSCU_ICUSARG_SAIELSR08_Msk = 0x100
	// Bit SAIELSR08.
	CPSCU_ICUSARG_SAIELSR08 = 0x100
	// Secure
	CPSCU_ICUSARG_SAIELSR08_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR08_1 = 0x1
	// Position of SAIELSR09 field.
	CPSCU_ICUSARG_SAIELSR09_Pos = 0x9
	// Bit mask of SAIELSR09 field.
	CPSCU_ICUSARG_SAIELSR09_Msk = 0x200
	// Bit SAIELSR09.
	CPSCU_ICUSARG_SAIELSR09 = 0x200
	// Secure
	CPSCU_ICUSARG_SAIELSR09_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR09_1 = 0x1
	// Position of SAIELSR10 field.
	CPSCU_ICUSARG_SAIELSR10_Pos = 0xa
	// Bit mask of SAIELSR10 field.
	CPSCU_ICUSARG_SAIELSR10_Msk = 0x400
	// Bit SAIELSR10.
	CPSCU_ICUSARG_SAIELSR10 = 0x400
	// Secure
	CPSCU_ICUSARG_SAIELSR10_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR10_1 = 0x1
	// Position of SAIELSR11 field.
	CPSCU_ICUSARG_SAIELSR11_Pos = 0xb
	// Bit mask of SAIELSR11 field.
	CPSCU_ICUSARG_SAIELSR11_Msk = 0x800
	// Bit SAIELSR11.
	CPSCU_ICUSARG_SAIELSR11 = 0x800
	// Secure
	CPSCU_ICUSARG_SAIELSR11_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR11_1 = 0x1
	// Position of SAIELSR12 field.
	CPSCU_ICUSARG_SAIELSR12_Pos = 0xc
	// Bit mask of SAIELSR12 field.
	CPSCU_ICUSARG_SAIELSR12_Msk = 0x1000
	// Bit SAIELSR12.
	CPSCU_ICUSARG_SAIELSR12 = 0x1000
	// Secure
	CPSCU_ICUSARG_SAIELSR12_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR12_1 = 0x1
	// Position of SAIELSR13 field.
	CPSCU_ICUSARG_SAIELSR13_Pos = 0xd
	// Bit mask of SAIELSR13 field.
	CPSCU_ICUSARG_SAIELSR13_Msk = 0x2000
	// Bit SAIELSR13.
	CPSCU_ICUSARG_SAIELSR13 = 0x2000
	// Secure
	CPSCU_ICUSARG_SAIELSR13_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR13_1 = 0x1
	// Position of SAIELSR14 field.
	CPSCU_ICUSARG_SAIELSR14_Pos = 0xe
	// Bit mask of SAIELSR14 field.
	CPSCU_ICUSARG_SAIELSR14_Msk = 0x4000
	// Bit SAIELSR14.
	CPSCU_ICUSARG_SAIELSR14 = 0x4000
	// Secure
	CPSCU_ICUSARG_SAIELSR14_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR14_1 = 0x1
	// Position of SAIELSR15 field.
	CPSCU_ICUSARG_SAIELSR15_Pos = 0xf
	// Bit mask of SAIELSR15 field.
	CPSCU_ICUSARG_SAIELSR15_Msk = 0x8000
	// Bit SAIELSR15.
	CPSCU_ICUSARG_SAIELSR15 = 0x8000
	// Secure
	CPSCU_ICUSARG_SAIELSR15_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR15_1 = 0x1
	// Position of SAIELSR16 field.
	CPSCU_ICUSARG_SAIELSR16_Pos = 0x10
	// Bit mask of SAIELSR16 field.
	CPSCU_ICUSARG_SAIELSR16_Msk = 0x10000
	// Bit SAIELSR16.
	CPSCU_ICUSARG_SAIELSR16 = 0x10000
	// Secure
	CPSCU_ICUSARG_SAIELSR16_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR16_1 = 0x1
	// Position of SAIELSR17 field.
	CPSCU_ICUSARG_SAIELSR17_Pos = 0x11
	// Bit mask of SAIELSR17 field.
	CPSCU_ICUSARG_SAIELSR17_Msk = 0x20000
	// Bit SAIELSR17.
	CPSCU_ICUSARG_SAIELSR17 = 0x20000
	// Secure
	CPSCU_ICUSARG_SAIELSR17_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR17_1 = 0x1
	// Position of SAIELSR18 field.
	CPSCU_ICUSARG_SAIELSR18_Pos = 0x12
	// Bit mask of SAIELSR18 field.
	CPSCU_ICUSARG_SAIELSR18_Msk = 0x40000
	// Bit SAIELSR18.
	CPSCU_ICUSARG_SAIELSR18 = 0x40000
	// Secure
	CPSCU_ICUSARG_SAIELSR18_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR18_1 = 0x1
	// Position of SAIELSR19 field.
	CPSCU_ICUSARG_SAIELSR19_Pos = 0x13
	// Bit mask of SAIELSR19 field.
	CPSCU_ICUSARG_SAIELSR19_Msk = 0x80000
	// Bit SAIELSR19.
	CPSCU_ICUSARG_SAIELSR19 = 0x80000
	// Secure
	CPSCU_ICUSARG_SAIELSR19_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR19_1 = 0x1
	// Position of SAIELSR20 field.
	CPSCU_ICUSARG_SAIELSR20_Pos = 0x14
	// Bit mask of SAIELSR20 field.
	CPSCU_ICUSARG_SAIELSR20_Msk = 0x100000
	// Bit SAIELSR20.
	CPSCU_ICUSARG_SAIELSR20 = 0x100000
	// Secure
	CPSCU_ICUSARG_SAIELSR20_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR20_1 = 0x1
	// Position of SAIELSR21 field.
	CPSCU_ICUSARG_SAIELSR21_Pos = 0x15
	// Bit mask of SAIELSR21 field.
	CPSCU_ICUSARG_SAIELSR21_Msk = 0x200000
	// Bit SAIELSR21.
	CPSCU_ICUSARG_SAIELSR21 = 0x200000
	// Secure
	CPSCU_ICUSARG_SAIELSR21_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR21_1 = 0x1
	// Position of SAIELSR22 field.
	CPSCU_ICUSARG_SAIELSR22_Pos = 0x16
	// Bit mask of SAIELSR22 field.
	CPSCU_ICUSARG_SAIELSR22_Msk = 0x400000
	// Bit SAIELSR22.
	CPSCU_ICUSARG_SAIELSR22 = 0x400000
	// Secure
	CPSCU_ICUSARG_SAIELSR22_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR22_1 = 0x1
	// Position of SAIELSR23 field.
	CPSCU_ICUSARG_SAIELSR23_Pos = 0x17
	// Bit mask of SAIELSR23 field.
	CPSCU_ICUSARG_SAIELSR23_Msk = 0x800000
	// Bit SAIELSR23.
	CPSCU_ICUSARG_SAIELSR23 = 0x800000
	// Secure
	CPSCU_ICUSARG_SAIELSR23_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR23_1 = 0x1
	// Position of SAIELSR24 field.
	CPSCU_ICUSARG_SAIELSR24_Pos = 0x18
	// Bit mask of SAIELSR24 field.
	CPSCU_ICUSARG_SAIELSR24_Msk = 0x1000000
	// Bit SAIELSR24.
	CPSCU_ICUSARG_SAIELSR24 = 0x1000000
	// Secure
	CPSCU_ICUSARG_SAIELSR24_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR24_1 = 0x1
	// Position of SAIELSR25 field.
	CPSCU_ICUSARG_SAIELSR25_Pos = 0x19
	// Bit mask of SAIELSR25 field.
	CPSCU_ICUSARG_SAIELSR25_Msk = 0x2000000
	// Bit SAIELSR25.
	CPSCU_ICUSARG_SAIELSR25 = 0x2000000
	// Secure
	CPSCU_ICUSARG_SAIELSR25_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR25_1 = 0x1
	// Position of SAIELSR26 field.
	CPSCU_ICUSARG_SAIELSR26_Pos = 0x1a
	// Bit mask of SAIELSR26 field.
	CPSCU_ICUSARG_SAIELSR26_Msk = 0x4000000
	// Bit SAIELSR26.
	CPSCU_ICUSARG_SAIELSR26 = 0x4000000
	// Secure
	CPSCU_ICUSARG_SAIELSR26_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR26_1 = 0x1
	// Position of SAIELSR27 field.
	CPSCU_ICUSARG_SAIELSR27_Pos = 0x1b
	// Bit mask of SAIELSR27 field.
	CPSCU_ICUSARG_SAIELSR27_Msk = 0x8000000
	// Bit SAIELSR27.
	CPSCU_ICUSARG_SAIELSR27 = 0x8000000
	// Secure
	CPSCU_ICUSARG_SAIELSR27_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR27_1 = 0x1
	// Position of SAIELSR28 field.
	CPSCU_ICUSARG_SAIELSR28_Pos = 0x1c
	// Bit mask of SAIELSR28 field.
	CPSCU_ICUSARG_SAIELSR28_Msk = 0x10000000
	// Bit SAIELSR28.
	CPSCU_ICUSARG_SAIELSR28 = 0x10000000
	// Secure
	CPSCU_ICUSARG_SAIELSR28_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR28_1 = 0x1
	// Position of SAIELSR29 field.
	CPSCU_ICUSARG_SAIELSR29_Pos = 0x1d
	// Bit mask of SAIELSR29 field.
	CPSCU_ICUSARG_SAIELSR29_Msk = 0x20000000
	// Bit SAIELSR29.
	CPSCU_ICUSARG_SAIELSR29 = 0x20000000
	// Secure
	CPSCU_ICUSARG_SAIELSR29_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR29_1 = 0x1
	// Position of SAIELSR30 field.
	CPSCU_ICUSARG_SAIELSR30_Pos = 0x1e
	// Bit mask of SAIELSR30 field.
	CPSCU_ICUSARG_SAIELSR30_Msk = 0x40000000
	// Bit SAIELSR30.
	CPSCU_ICUSARG_SAIELSR30 = 0x40000000
	// Secure
	CPSCU_ICUSARG_SAIELSR30_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR30_1 = 0x1
	// Position of SAIELSR31 field.
	CPSCU_ICUSARG_SAIELSR31_Pos = 0x1f
	// Bit mask of SAIELSR31 field.
	CPSCU_ICUSARG_SAIELSR31_Msk = 0x80000000
	// Bit SAIELSR31.
	CPSCU_ICUSARG_SAIELSR31 = 0x80000000
	// Secure
	CPSCU_ICUSARG_SAIELSR31_0 = 0x0
	// Non-secure
	CPSCU_ICUSARG_SAIELSR31_1 = 0x1

	// ICUSARH: Interrupt Controller Unit Security Attribution Register H
	// Position of SAIELSR32 field.
	CPSCU_ICUSARH_SAIELSR32_Pos = 0x0
	// Bit mask of SAIELSR32 field.
	CPSCU_ICUSARH_SAIELSR32_Msk = 0x1
	// Bit SAIELSR32.
	CPSCU_ICUSARH_SAIELSR32 = 0x1
	// Secure
	CPSCU_ICUSARH_SAIELSR32_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR32_1 = 0x1
	// Position of SAIELSR33 field.
	CPSCU_ICUSARH_SAIELSR33_Pos = 0x1
	// Bit mask of SAIELSR33 field.
	CPSCU_ICUSARH_SAIELSR33_Msk = 0x2
	// Bit SAIELSR33.
	CPSCU_ICUSARH_SAIELSR33 = 0x2
	// Secure
	CPSCU_ICUSARH_SAIELSR33_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR33_1 = 0x1
	// Position of SAIELSR34 field.
	CPSCU_ICUSARH_SAIELSR34_Pos = 0x2
	// Bit mask of SAIELSR34 field.
	CPSCU_ICUSARH_SAIELSR34_Msk = 0x4
	// Bit SAIELSR34.
	CPSCU_ICUSARH_SAIELSR34 = 0x4
	// Secure
	CPSCU_ICUSARH_SAIELSR34_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR34_1 = 0x1
	// Position of SAIELSR35 field.
	CPSCU_ICUSARH_SAIELSR35_Pos = 0x3
	// Bit mask of SAIELSR35 field.
	CPSCU_ICUSARH_SAIELSR35_Msk = 0x8
	// Bit SAIELSR35.
	CPSCU_ICUSARH_SAIELSR35 = 0x8
	// Secure
	CPSCU_ICUSARH_SAIELSR35_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR35_1 = 0x1
	// Position of SAIELSR36 field.
	CPSCU_ICUSARH_SAIELSR36_Pos = 0x4
	// Bit mask of SAIELSR36 field.
	CPSCU_ICUSARH_SAIELSR36_Msk = 0x10
	// Bit SAIELSR36.
	CPSCU_ICUSARH_SAIELSR36 = 0x10
	// Secure
	CPSCU_ICUSARH_SAIELSR36_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR36_1 = 0x1
	// Position of SAIELSR37 field.
	CPSCU_ICUSARH_SAIELSR37_Pos = 0x5
	// Bit mask of SAIELSR37 field.
	CPSCU_ICUSARH_SAIELSR37_Msk = 0x20
	// Bit SAIELSR37.
	CPSCU_ICUSARH_SAIELSR37 = 0x20
	// Secure
	CPSCU_ICUSARH_SAIELSR37_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR37_1 = 0x1
	// Position of SAIELSR38 field.
	CPSCU_ICUSARH_SAIELSR38_Pos = 0x6
	// Bit mask of SAIELSR38 field.
	CPSCU_ICUSARH_SAIELSR38_Msk = 0x40
	// Bit SAIELSR38.
	CPSCU_ICUSARH_SAIELSR38 = 0x40
	// Secure
	CPSCU_ICUSARH_SAIELSR38_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR38_1 = 0x1
	// Position of SAIELSR39 field.
	CPSCU_ICUSARH_SAIELSR39_Pos = 0x7
	// Bit mask of SAIELSR39 field.
	CPSCU_ICUSARH_SAIELSR39_Msk = 0x80
	// Bit SAIELSR39.
	CPSCU_ICUSARH_SAIELSR39 = 0x80
	// Secure
	CPSCU_ICUSARH_SAIELSR39_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR39_1 = 0x1
	// Position of SAIELSR40 field.
	CPSCU_ICUSARH_SAIELSR40_Pos = 0x8
	// Bit mask of SAIELSR40 field.
	CPSCU_ICUSARH_SAIELSR40_Msk = 0x100
	// Bit SAIELSR40.
	CPSCU_ICUSARH_SAIELSR40 = 0x100
	// Secure
	CPSCU_ICUSARH_SAIELSR40_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR40_1 = 0x1
	// Position of SAIELSR41 field.
	CPSCU_ICUSARH_SAIELSR41_Pos = 0x9
	// Bit mask of SAIELSR41 field.
	CPSCU_ICUSARH_SAIELSR41_Msk = 0x200
	// Bit SAIELSR41.
	CPSCU_ICUSARH_SAIELSR41 = 0x200
	// Secure
	CPSCU_ICUSARH_SAIELSR41_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR41_1 = 0x1
	// Position of SAIELSR42 field.
	CPSCU_ICUSARH_SAIELSR42_Pos = 0xa
	// Bit mask of SAIELSR42 field.
	CPSCU_ICUSARH_SAIELSR42_Msk = 0x400
	// Bit SAIELSR42.
	CPSCU_ICUSARH_SAIELSR42 = 0x400
	// Secure
	CPSCU_ICUSARH_SAIELSR42_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR42_1 = 0x1
	// Position of SAIELSR43 field.
	CPSCU_ICUSARH_SAIELSR43_Pos = 0xb
	// Bit mask of SAIELSR43 field.
	CPSCU_ICUSARH_SAIELSR43_Msk = 0x800
	// Bit SAIELSR43.
	CPSCU_ICUSARH_SAIELSR43 = 0x800
	// Secure
	CPSCU_ICUSARH_SAIELSR43_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR43_1 = 0x1
	// Position of SAIELSR44 field.
	CPSCU_ICUSARH_SAIELSR44_Pos = 0xc
	// Bit mask of SAIELSR44 field.
	CPSCU_ICUSARH_SAIELSR44_Msk = 0x1000
	// Bit SAIELSR44.
	CPSCU_ICUSARH_SAIELSR44 = 0x1000
	// Secure
	CPSCU_ICUSARH_SAIELSR44_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR44_1 = 0x1
	// Position of SAIELSR45 field.
	CPSCU_ICUSARH_SAIELSR45_Pos = 0xd
	// Bit mask of SAIELSR45 field.
	CPSCU_ICUSARH_SAIELSR45_Msk = 0x2000
	// Bit SAIELSR45.
	CPSCU_ICUSARH_SAIELSR45 = 0x2000
	// Secure
	CPSCU_ICUSARH_SAIELSR45_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR45_1 = 0x1
	// Position of SAIELSR46 field.
	CPSCU_ICUSARH_SAIELSR46_Pos = 0xe
	// Bit mask of SAIELSR46 field.
	CPSCU_ICUSARH_SAIELSR46_Msk = 0x4000
	// Bit SAIELSR46.
	CPSCU_ICUSARH_SAIELSR46 = 0x4000
	// Secure
	CPSCU_ICUSARH_SAIELSR46_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR46_1 = 0x1
	// Position of SAIELSR47 field.
	CPSCU_ICUSARH_SAIELSR47_Pos = 0xf
	// Bit mask of SAIELSR47 field.
	CPSCU_ICUSARH_SAIELSR47_Msk = 0x8000
	// Bit SAIELSR47.
	CPSCU_ICUSARH_SAIELSR47 = 0x8000
	// Secure
	CPSCU_ICUSARH_SAIELSR47_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR47_1 = 0x1
	// Position of SAIELSR48 field.
	CPSCU_ICUSARH_SAIELSR48_Pos = 0x10
	// Bit mask of SAIELSR48 field.
	CPSCU_ICUSARH_SAIELSR48_Msk = 0x10000
	// Bit SAIELSR48.
	CPSCU_ICUSARH_SAIELSR48 = 0x10000
	// Secure
	CPSCU_ICUSARH_SAIELSR48_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR48_1 = 0x1
	// Position of SAIELSR49 field.
	CPSCU_ICUSARH_SAIELSR49_Pos = 0x11
	// Bit mask of SAIELSR49 field.
	CPSCU_ICUSARH_SAIELSR49_Msk = 0x20000
	// Bit SAIELSR49.
	CPSCU_ICUSARH_SAIELSR49 = 0x20000
	// Secure
	CPSCU_ICUSARH_SAIELSR49_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR49_1 = 0x1
	// Position of SAIELSR50 field.
	CPSCU_ICUSARH_SAIELSR50_Pos = 0x12
	// Bit mask of SAIELSR50 field.
	CPSCU_ICUSARH_SAIELSR50_Msk = 0x40000
	// Bit SAIELSR50.
	CPSCU_ICUSARH_SAIELSR50 = 0x40000
	// Secure
	CPSCU_ICUSARH_SAIELSR50_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR50_1 = 0x1
	// Position of SAIELSR51 field.
	CPSCU_ICUSARH_SAIELSR51_Pos = 0x13
	// Bit mask of SAIELSR51 field.
	CPSCU_ICUSARH_SAIELSR51_Msk = 0x80000
	// Bit SAIELSR51.
	CPSCU_ICUSARH_SAIELSR51 = 0x80000
	// Secure
	CPSCU_ICUSARH_SAIELSR51_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR51_1 = 0x1
	// Position of SAIELSR52 field.
	CPSCU_ICUSARH_SAIELSR52_Pos = 0x14
	// Bit mask of SAIELSR52 field.
	CPSCU_ICUSARH_SAIELSR52_Msk = 0x100000
	// Bit SAIELSR52.
	CPSCU_ICUSARH_SAIELSR52 = 0x100000
	// Secure
	CPSCU_ICUSARH_SAIELSR52_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR52_1 = 0x1
	// Position of SAIELSR53 field.
	CPSCU_ICUSARH_SAIELSR53_Pos = 0x15
	// Bit mask of SAIELSR53 field.
	CPSCU_ICUSARH_SAIELSR53_Msk = 0x200000
	// Bit SAIELSR53.
	CPSCU_ICUSARH_SAIELSR53 = 0x200000
	// Secure
	CPSCU_ICUSARH_SAIELSR53_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR53_1 = 0x1
	// Position of SAIELSR54 field.
	CPSCU_ICUSARH_SAIELSR54_Pos = 0x16
	// Bit mask of SAIELSR54 field.
	CPSCU_ICUSARH_SAIELSR54_Msk = 0x400000
	// Bit SAIELSR54.
	CPSCU_ICUSARH_SAIELSR54 = 0x400000
	// Secure
	CPSCU_ICUSARH_SAIELSR54_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR54_1 = 0x1
	// Position of SAIELSR55 field.
	CPSCU_ICUSARH_SAIELSR55_Pos = 0x17
	// Bit mask of SAIELSR55 field.
	CPSCU_ICUSARH_SAIELSR55_Msk = 0x800000
	// Bit SAIELSR55.
	CPSCU_ICUSARH_SAIELSR55 = 0x800000
	// Secure
	CPSCU_ICUSARH_SAIELSR55_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR55_1 = 0x1
	// Position of SAIELSR56 field.
	CPSCU_ICUSARH_SAIELSR56_Pos = 0x18
	// Bit mask of SAIELSR56 field.
	CPSCU_ICUSARH_SAIELSR56_Msk = 0x1000000
	// Bit SAIELSR56.
	CPSCU_ICUSARH_SAIELSR56 = 0x1000000
	// Secure
	CPSCU_ICUSARH_SAIELSR56_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR56_1 = 0x1
	// Position of SAIELSR57 field.
	CPSCU_ICUSARH_SAIELSR57_Pos = 0x19
	// Bit mask of SAIELSR57 field.
	CPSCU_ICUSARH_SAIELSR57_Msk = 0x2000000
	// Bit SAIELSR57.
	CPSCU_ICUSARH_SAIELSR57 = 0x2000000
	// Secure
	CPSCU_ICUSARH_SAIELSR57_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR57_1 = 0x1
	// Position of SAIELSR58 field.
	CPSCU_ICUSARH_SAIELSR58_Pos = 0x1a
	// Bit mask of SAIELSR58 field.
	CPSCU_ICUSARH_SAIELSR58_Msk = 0x4000000
	// Bit SAIELSR58.
	CPSCU_ICUSARH_SAIELSR58 = 0x4000000
	// Secure
	CPSCU_ICUSARH_SAIELSR58_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR58_1 = 0x1
	// Position of SAIELSR59 field.
	CPSCU_ICUSARH_SAIELSR59_Pos = 0x1b
	// Bit mask of SAIELSR59 field.
	CPSCU_ICUSARH_SAIELSR59_Msk = 0x8000000
	// Bit SAIELSR59.
	CPSCU_ICUSARH_SAIELSR59 = 0x8000000
	// Secure
	CPSCU_ICUSARH_SAIELSR59_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR59_1 = 0x1
	// Position of SAIELSR60 field.
	CPSCU_ICUSARH_SAIELSR60_Pos = 0x1c
	// Bit mask of SAIELSR60 field.
	CPSCU_ICUSARH_SAIELSR60_Msk = 0x10000000
	// Bit SAIELSR60.
	CPSCU_ICUSARH_SAIELSR60 = 0x10000000
	// Secure
	CPSCU_ICUSARH_SAIELSR60_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR60_1 = 0x1
	// Position of SAIELSR61 field.
	CPSCU_ICUSARH_SAIELSR61_Pos = 0x1d
	// Bit mask of SAIELSR61 field.
	CPSCU_ICUSARH_SAIELSR61_Msk = 0x20000000
	// Bit SAIELSR61.
	CPSCU_ICUSARH_SAIELSR61 = 0x20000000
	// Secure
	CPSCU_ICUSARH_SAIELSR61_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR61_1 = 0x1
	// Position of SAIELSR62 field.
	CPSCU_ICUSARH_SAIELSR62_Pos = 0x1e
	// Bit mask of SAIELSR62 field.
	CPSCU_ICUSARH_SAIELSR62_Msk = 0x40000000
	// Bit SAIELSR62.
	CPSCU_ICUSARH_SAIELSR62 = 0x40000000
	// Secure
	CPSCU_ICUSARH_SAIELSR62_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR62_1 = 0x1
	// Position of SAIELSR63 field.
	CPSCU_ICUSARH_SAIELSR63_Pos = 0x1f
	// Bit mask of SAIELSR63 field.
	CPSCU_ICUSARH_SAIELSR63_Msk = 0x80000000
	// Bit SAIELSR63.
	CPSCU_ICUSARH_SAIELSR63 = 0x80000000
	// Secure
	CPSCU_ICUSARH_SAIELSR63_0 = 0x0
	// Non-secure
	CPSCU_ICUSARH_SAIELSR63_1 = 0x1

	// ICUSARI: Interrupt Controller Unit Security Attribution Register I
	// Position of SAIELSR64 field.
	CPSCU_ICUSARI_SAIELSR64_Pos = 0x0
	// Bit mask of SAIELSR64 field.
	CPSCU_ICUSARI_SAIELSR64_Msk = 0x1
	// Bit SAIELSR64.
	CPSCU_ICUSARI_SAIELSR64 = 0x1
	// Secure
	CPSCU_ICUSARI_SAIELSR64_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR64_1 = 0x1
	// Position of SAIELSR65 field.
	CPSCU_ICUSARI_SAIELSR65_Pos = 0x1
	// Bit mask of SAIELSR65 field.
	CPSCU_ICUSARI_SAIELSR65_Msk = 0x2
	// Bit SAIELSR65.
	CPSCU_ICUSARI_SAIELSR65 = 0x2
	// Secure
	CPSCU_ICUSARI_SAIELSR65_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR65_1 = 0x1
	// Position of SAIELSR66 field.
	CPSCU_ICUSARI_SAIELSR66_Pos = 0x2
	// Bit mask of SAIELSR66 field.
	CPSCU_ICUSARI_SAIELSR66_Msk = 0x4
	// Bit SAIELSR66.
	CPSCU_ICUSARI_SAIELSR66 = 0x4
	// Secure
	CPSCU_ICUSARI_SAIELSR66_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR66_1 = 0x1
	// Position of SAIELSR67 field.
	CPSCU_ICUSARI_SAIELSR67_Pos = 0x3
	// Bit mask of SAIELSR67 field.
	CPSCU_ICUSARI_SAIELSR67_Msk = 0x8
	// Bit SAIELSR67.
	CPSCU_ICUSARI_SAIELSR67 = 0x8
	// Secure
	CPSCU_ICUSARI_SAIELSR67_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR67_1 = 0x1
	// Position of SAIELSR68 field.
	CPSCU_ICUSARI_SAIELSR68_Pos = 0x4
	// Bit mask of SAIELSR68 field.
	CPSCU_ICUSARI_SAIELSR68_Msk = 0x10
	// Bit SAIELSR68.
	CPSCU_ICUSARI_SAIELSR68 = 0x10
	// Secure
	CPSCU_ICUSARI_SAIELSR68_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR68_1 = 0x1
	// Position of SAIELSR69 field.
	CPSCU_ICUSARI_SAIELSR69_Pos = 0x5
	// Bit mask of SAIELSR69 field.
	CPSCU_ICUSARI_SAIELSR69_Msk = 0x20
	// Bit SAIELSR69.
	CPSCU_ICUSARI_SAIELSR69 = 0x20
	// Secure
	CPSCU_ICUSARI_SAIELSR69_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR69_1 = 0x1
	// Position of SAIELSR70 field.
	CPSCU_ICUSARI_SAIELSR70_Pos = 0x6
	// Bit mask of SAIELSR70 field.
	CPSCU_ICUSARI_SAIELSR70_Msk = 0x40
	// Bit SAIELSR70.
	CPSCU_ICUSARI_SAIELSR70 = 0x40
	// Secure
	CPSCU_ICUSARI_SAIELSR70_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR70_1 = 0x1
	// Position of SAIELSR71 field.
	CPSCU_ICUSARI_SAIELSR71_Pos = 0x7
	// Bit mask of SAIELSR71 field.
	CPSCU_ICUSARI_SAIELSR71_Msk = 0x80
	// Bit SAIELSR71.
	CPSCU_ICUSARI_SAIELSR71 = 0x80
	// Secure
	CPSCU_ICUSARI_SAIELSR71_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR71_1 = 0x1
	// Position of SAIELSR72 field.
	CPSCU_ICUSARI_SAIELSR72_Pos = 0x8
	// Bit mask of SAIELSR72 field.
	CPSCU_ICUSARI_SAIELSR72_Msk = 0x100
	// Bit SAIELSR72.
	CPSCU_ICUSARI_SAIELSR72 = 0x100
	// Secure
	CPSCU_ICUSARI_SAIELSR72_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR72_1 = 0x1
	// Position of SAIELSR73 field.
	CPSCU_ICUSARI_SAIELSR73_Pos = 0x9
	// Bit mask of SAIELSR73 field.
	CPSCU_ICUSARI_SAIELSR73_Msk = 0x200
	// Bit SAIELSR73.
	CPSCU_ICUSARI_SAIELSR73 = 0x200
	// Secure
	CPSCU_ICUSARI_SAIELSR73_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR73_1 = 0x1
	// Position of SAIELSR74 field.
	CPSCU_ICUSARI_SAIELSR74_Pos = 0xa
	// Bit mask of SAIELSR74 field.
	CPSCU_ICUSARI_SAIELSR74_Msk = 0x400
	// Bit SAIELSR74.
	CPSCU_ICUSARI_SAIELSR74 = 0x400
	// Secure
	CPSCU_ICUSARI_SAIELSR74_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR74_1 = 0x1
	// Position of SAIELSR75 field.
	CPSCU_ICUSARI_SAIELSR75_Pos = 0xb
	// Bit mask of SAIELSR75 field.
	CPSCU_ICUSARI_SAIELSR75_Msk = 0x800
	// Bit SAIELSR75.
	CPSCU_ICUSARI_SAIELSR75 = 0x800
	// Secure
	CPSCU_ICUSARI_SAIELSR75_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR75_1 = 0x1
	// Position of SAIELSR76 field.
	CPSCU_ICUSARI_SAIELSR76_Pos = 0xc
	// Bit mask of SAIELSR76 field.
	CPSCU_ICUSARI_SAIELSR76_Msk = 0x1000
	// Bit SAIELSR76.
	CPSCU_ICUSARI_SAIELSR76 = 0x1000
	// Secure
	CPSCU_ICUSARI_SAIELSR76_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR76_1 = 0x1
	// Position of SAIELSR77 field.
	CPSCU_ICUSARI_SAIELSR77_Pos = 0xd
	// Bit mask of SAIELSR77 field.
	CPSCU_ICUSARI_SAIELSR77_Msk = 0x2000
	// Bit SAIELSR77.
	CPSCU_ICUSARI_SAIELSR77 = 0x2000
	// Secure
	CPSCU_ICUSARI_SAIELSR77_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR77_1 = 0x1
	// Position of SAIELSR78 field.
	CPSCU_ICUSARI_SAIELSR78_Pos = 0xe
	// Bit mask of SAIELSR78 field.
	CPSCU_ICUSARI_SAIELSR78_Msk = 0x4000
	// Bit SAIELSR78.
	CPSCU_ICUSARI_SAIELSR78 = 0x4000
	// Secure
	CPSCU_ICUSARI_SAIELSR78_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR78_1 = 0x1
	// Position of SAIELSR79 field.
	CPSCU_ICUSARI_SAIELSR79_Pos = 0xf
	// Bit mask of SAIELSR79 field.
	CPSCU_ICUSARI_SAIELSR79_Msk = 0x8000
	// Bit SAIELSR79.
	CPSCU_ICUSARI_SAIELSR79 = 0x8000
	// Secure
	CPSCU_ICUSARI_SAIELSR79_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR79_1 = 0x1
	// Position of SAIELSR80 field.
	CPSCU_ICUSARI_SAIELSR80_Pos = 0x10
	// Bit mask of SAIELSR80 field.
	CPSCU_ICUSARI_SAIELSR80_Msk = 0x10000
	// Bit SAIELSR80.
	CPSCU_ICUSARI_SAIELSR80 = 0x10000
	// Secure
	CPSCU_ICUSARI_SAIELSR80_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR80_1 = 0x1
	// Position of SAIELSR81 field.
	CPSCU_ICUSARI_SAIELSR81_Pos = 0x11
	// Bit mask of SAIELSR81 field.
	CPSCU_ICUSARI_SAIELSR81_Msk = 0x20000
	// Bit SAIELSR81.
	CPSCU_ICUSARI_SAIELSR81 = 0x20000
	// Secure
	CPSCU_ICUSARI_SAIELSR81_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR81_1 = 0x1
	// Position of SAIELSR82 field.
	CPSCU_ICUSARI_SAIELSR82_Pos = 0x12
	// Bit mask of SAIELSR82 field.
	CPSCU_ICUSARI_SAIELSR82_Msk = 0x40000
	// Bit SAIELSR82.
	CPSCU_ICUSARI_SAIELSR82 = 0x40000
	// Secure
	CPSCU_ICUSARI_SAIELSR82_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR82_1 = 0x1
	// Position of SAIELSR83 field.
	CPSCU_ICUSARI_SAIELSR83_Pos = 0x13
	// Bit mask of SAIELSR83 field.
	CPSCU_ICUSARI_SAIELSR83_Msk = 0x80000
	// Bit SAIELSR83.
	CPSCU_ICUSARI_SAIELSR83 = 0x80000
	// Secure
	CPSCU_ICUSARI_SAIELSR83_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR83_1 = 0x1
	// Position of SAIELSR84 field.
	CPSCU_ICUSARI_SAIELSR84_Pos = 0x14
	// Bit mask of SAIELSR84 field.
	CPSCU_ICUSARI_SAIELSR84_Msk = 0x100000
	// Bit SAIELSR84.
	CPSCU_ICUSARI_SAIELSR84 = 0x100000
	// Secure
	CPSCU_ICUSARI_SAIELSR84_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR84_1 = 0x1
	// Position of SAIELSR85 field.
	CPSCU_ICUSARI_SAIELSR85_Pos = 0x15
	// Bit mask of SAIELSR85 field.
	CPSCU_ICUSARI_SAIELSR85_Msk = 0x200000
	// Bit SAIELSR85.
	CPSCU_ICUSARI_SAIELSR85 = 0x200000
	// Secure
	CPSCU_ICUSARI_SAIELSR85_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR85_1 = 0x1
	// Position of SAIELSR86 field.
	CPSCU_ICUSARI_SAIELSR86_Pos = 0x16
	// Bit mask of SAIELSR86 field.
	CPSCU_ICUSARI_SAIELSR86_Msk = 0x400000
	// Bit SAIELSR86.
	CPSCU_ICUSARI_SAIELSR86 = 0x400000
	// Secure
	CPSCU_ICUSARI_SAIELSR86_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR86_1 = 0x1
	// Position of SAIELSR87 field.
	CPSCU_ICUSARI_SAIELSR87_Pos = 0x17
	// Bit mask of SAIELSR87 field.
	CPSCU_ICUSARI_SAIELSR87_Msk = 0x800000
	// Bit SAIELSR87.
	CPSCU_ICUSARI_SAIELSR87 = 0x800000
	// Secure
	CPSCU_ICUSARI_SAIELSR87_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR87_1 = 0x1
	// Position of SAIELSR88 field.
	CPSCU_ICUSARI_SAIELSR88_Pos = 0x18
	// Bit mask of SAIELSR88 field.
	CPSCU_ICUSARI_SAIELSR88_Msk = 0x1000000
	// Bit SAIELSR88.
	CPSCU_ICUSARI_SAIELSR88 = 0x1000000
	// Secure
	CPSCU_ICUSARI_SAIELSR88_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR88_1 = 0x1
	// Position of SAIELSR89 field.
	CPSCU_ICUSARI_SAIELSR89_Pos = 0x19
	// Bit mask of SAIELSR89 field.
	CPSCU_ICUSARI_SAIELSR89_Msk = 0x2000000
	// Bit SAIELSR89.
	CPSCU_ICUSARI_SAIELSR89 = 0x2000000
	// Secure
	CPSCU_ICUSARI_SAIELSR89_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR89_1 = 0x1
	// Position of SAIELSR90 field.
	CPSCU_ICUSARI_SAIELSR90_Pos = 0x1a
	// Bit mask of SAIELSR90 field.
	CPSCU_ICUSARI_SAIELSR90_Msk = 0x4000000
	// Bit SAIELSR90.
	CPSCU_ICUSARI_SAIELSR90 = 0x4000000
	// Secure
	CPSCU_ICUSARI_SAIELSR90_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR90_1 = 0x1
	// Position of SAIELSR91 field.
	CPSCU_ICUSARI_SAIELSR91_Pos = 0x1b
	// Bit mask of SAIELSR91 field.
	CPSCU_ICUSARI_SAIELSR91_Msk = 0x8000000
	// Bit SAIELSR91.
	CPSCU_ICUSARI_SAIELSR91 = 0x8000000
	// Secure
	CPSCU_ICUSARI_SAIELSR91_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR91_1 = 0x1
	// Position of SAIELSR92 field.
	CPSCU_ICUSARI_SAIELSR92_Pos = 0x1c
	// Bit mask of SAIELSR92 field.
	CPSCU_ICUSARI_SAIELSR92_Msk = 0x10000000
	// Bit SAIELSR92.
	CPSCU_ICUSARI_SAIELSR92 = 0x10000000
	// Secure
	CPSCU_ICUSARI_SAIELSR92_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR92_1 = 0x1
	// Position of SAIELSR93 field.
	CPSCU_ICUSARI_SAIELSR93_Pos = 0x1d
	// Bit mask of SAIELSR93 field.
	CPSCU_ICUSARI_SAIELSR93_Msk = 0x20000000
	// Bit SAIELSR93.
	CPSCU_ICUSARI_SAIELSR93 = 0x20000000
	// Secure
	CPSCU_ICUSARI_SAIELSR93_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR93_1 = 0x1
	// Position of SAIELSR94 field.
	CPSCU_ICUSARI_SAIELSR94_Pos = 0x1e
	// Bit mask of SAIELSR94 field.
	CPSCU_ICUSARI_SAIELSR94_Msk = 0x40000000
	// Bit SAIELSR94.
	CPSCU_ICUSARI_SAIELSR94 = 0x40000000
	// Secure
	CPSCU_ICUSARI_SAIELSR94_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR94_1 = 0x1
	// Position of SAIELSR95 field.
	CPSCU_ICUSARI_SAIELSR95_Pos = 0x1f
	// Bit mask of SAIELSR95 field.
	CPSCU_ICUSARI_SAIELSR95_Msk = 0x80000000
	// Bit SAIELSR95.
	CPSCU_ICUSARI_SAIELSR95 = 0x80000000
	// Secure
	CPSCU_ICUSARI_SAIELSR95_0 = 0x0
	// Non-secure
	CPSCU_ICUSARI_SAIELSR95_1 = 0x1

	// BUSSARA: BUS Security Attribution Register A
	// Position of BUSSA0 field.
	CPSCU_BUSSARA_BUSSA0_Pos = 0x0
	// Bit mask of BUSSA0 field.
	CPSCU_BUSSARA_BUSSA0_Msk = 0x1
	// Bit BUSSA0.
	CPSCU_BUSSARA_BUSSA0 = 0x1
	// Secure
	CPSCU_BUSSARA_BUSSA0_0 = 0x0
	// Non-Secure
	CPSCU_BUSSARA_BUSSA0_1 = 0x1

	// BUSSARB: BUS Security Attribution Register B
	// Position of BUSSB0 field.
	CPSCU_BUSSARB_BUSSB0_Pos = 0x0
	// Bit mask of BUSSB0 field.
	CPSCU_BUSSARB_BUSSB0_Msk = 0x1
	// Bit BUSSB0.
	CPSCU_BUSSARB_BUSSB0 = 0x1
	// Secure
	CPSCU_BUSSARB_BUSSB0_0 = 0x0
	// Non-Secure
	CPSCU_BUSSARB_BUSSB0_1 = 0x1

	// MMPUSARA: Master Memory Protection Unit Security Attribution Register A
	// Position of MMPUASAn field.
	CPSCU_MMPUSARA_MMPUASAn_Pos = 0x0
	// Bit mask of MMPUASAn field.
	CPSCU_MMPUSARA_MMPUASAn_Msk = 0xff
	// Secure
	CPSCU_MMPUSARA_MMPUASAn_0 = 0x0
	// Non-Secure
	CPSCU_MMPUSARA_MMPUASAn_1 = 0x1

	// MMPUSARB: Master Memory Protection Unit Security Attribution Register B
	// Position of MMPUBSA0 field.
	CPSCU_MMPUSARB_MMPUBSA0_Pos = 0x0
	// Bit mask of MMPUBSA0 field.
	CPSCU_MMPUSARB_MMPUBSA0_Msk = 0x1
	// Bit MMPUBSA0.
	CPSCU_MMPUSARB_MMPUBSA0 = 0x1
	// Secure
	CPSCU_MMPUSARB_MMPUBSA0_0 = 0x0
	// Non-Secure
	CPSCU_MMPUSARB_MMPUBSA0_1 = 0x1

	// TZFSAR: TrustZone Filter Security Attribution Register
	// Position of TZFSA0 field.
	CPSCU_TZFSAR_TZFSA0_Pos = 0x0
	// Bit mask of TZFSA0 field.
	CPSCU_TZFSAR_TZFSA0_Msk = 0x1
	// Bit TZFSA0.
	CPSCU_TZFSAR_TZFSA0 = 0x1
	// Secure
	CPSCU_TZFSAR_TZFSA0_0 = 0x0
	// Non-secure
	CPSCU_TZFSAR_TZFSA0_1 = 0x1

	// CPUDSAR: CPU Debug Security Attribution Register
	// Position of CPUDSA0 field.
	CPSCU_CPUDSAR_CPUDSA0_Pos = 0x0
	// Bit mask of CPUDSA0 field.
	CPSCU_CPUDSAR_CPUDSA0_Msk = 0x1
	// Bit CPUDSA0.
	CPSCU_CPUDSAR_CPUDSA0 = 0x1
	// Secure
	CPSCU_CPUDSAR_CPUDSA0_0 = 0x0
	// Non-secure
	CPSCU_CPUDSAR_CPUDSA0_1 = 0x1
)

// Constants for DBG: Debug Function
const (
	// DBGSTR: Debug Status Register
	// Position of CDBGPWRUPREQ field.
	DBG_DBGSTR_CDBGPWRUPREQ_Pos = 0x1c
	// Bit mask of CDBGPWRUPREQ field.
	DBG_DBGSTR_CDBGPWRUPREQ_Msk = 0x10000000
	// Bit CDBGPWRUPREQ.
	DBG_DBGSTR_CDBGPWRUPREQ = 0x10000000
	// OCD is not requesting debug power up
	DBG_DBGSTR_CDBGPWRUPREQ_0 = 0x0
	// OCD is requesting debug power up
	DBG_DBGSTR_CDBGPWRUPREQ_1 = 0x1
	// Position of CDBGPWRUPACK field.
	DBG_DBGSTR_CDBGPWRUPACK_Pos = 0x1d
	// Bit mask of CDBGPWRUPACK field.
	DBG_DBGSTR_CDBGPWRUPACK_Msk = 0x20000000
	// Bit CDBGPWRUPACK.
	DBG_DBGSTR_CDBGPWRUPACK = 0x20000000
	// Debug power-up request is not acknowledged
	DBG_DBGSTR_CDBGPWRUPACK_0 = 0x0
	// Debug power-up request is acknowledged
	DBG_DBGSTR_CDBGPWRUPACK_1 = 0x1

	// DBGSTOPCR: Debug Stop Control Register
	// Position of DBGSTOP_IWDT field.
	DBG_DBGSTOPCR_DBGSTOP_IWDT_Pos = 0x0
	// Bit mask of DBGSTOP_IWDT field.
	DBG_DBGSTOPCR_DBGSTOP_IWDT_Msk = 0x1
	// Bit DBGSTOP_IWDT.
	DBG_DBGSTOPCR_DBGSTOP_IWDT = 0x1
	// Enable IWDT reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_IWDT_0 = 0x0
	// Mask IWDT reset/interrupt and stop IWDT counter
	DBG_DBGSTOPCR_DBGSTOP_IWDT_1 = 0x1
	// Position of DBGSTOP_WDT field.
	DBG_DBGSTOPCR_DBGSTOP_WDT_Pos = 0x1
	// Bit mask of DBGSTOP_WDT field.
	DBG_DBGSTOPCR_DBGSTOP_WDT_Msk = 0x2
	// Bit DBGSTOP_WDT.
	DBG_DBGSTOPCR_DBGSTOP_WDT = 0x2
	// Enable WDT reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_WDT_0 = 0x0
	// Mask WDT reset/interrupt and stop WDT counter
	DBG_DBGSTOPCR_DBGSTOP_WDT_1 = 0x1
	// Position of DBGSTOP_LVD0 field.
	DBG_DBGSTOPCR_DBGSTOP_LVD0_Pos = 0x10
	// Bit mask of DBGSTOP_LVD0 field.
	DBG_DBGSTOPCR_DBGSTOP_LVD0_Msk = 0x10000
	// Bit DBGSTOP_LVD0.
	DBG_DBGSTOPCR_DBGSTOP_LVD0 = 0x10000
	// Enable LVD0 reset
	DBG_DBGSTOPCR_DBGSTOP_LVD0_0 = 0x0
	// Mask LVD0 reset
	DBG_DBGSTOPCR_DBGSTOP_LVD0_1 = 0x1
	// Position of DBGSTOP_LVD1 field.
	DBG_DBGSTOPCR_DBGSTOP_LVD1_Pos = 0x11
	// Bit mask of DBGSTOP_LVD1 field.
	DBG_DBGSTOPCR_DBGSTOP_LVD1_Msk = 0x20000
	// Bit DBGSTOP_LVD1.
	DBG_DBGSTOPCR_DBGSTOP_LVD1 = 0x20000
	// Enable LVD1 reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_LVD1_0 = 0x0
	// Mask LVD1 reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_LVD1_1 = 0x1
	// Position of DBGSTOP_LVD2 field.
	DBG_DBGSTOPCR_DBGSTOP_LVD2_Pos = 0x12
	// Bit mask of DBGSTOP_LVD2 field.
	DBG_DBGSTOPCR_DBGSTOP_LVD2_Msk = 0x40000
	// Bit DBGSTOP_LVD2.
	DBG_DBGSTOPCR_DBGSTOP_LVD2 = 0x40000
	// Enable LVD2 reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_LVD2_0 = 0x0
	// Mask LVD2 reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_LVD2_1 = 0x1
	// Position of DBGSTOP_RPER field.
	DBG_DBGSTOPCR_DBGSTOP_RPER_Pos = 0x18
	// Bit mask of DBGSTOP_RPER field.
	DBG_DBGSTOPCR_DBGSTOP_RPER_Msk = 0x1000000
	// Bit DBGSTOP_RPER.
	DBG_DBGSTOPCR_DBGSTOP_RPER = 0x1000000
	// Enable SRAM parity error reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_RPER_0 = 0x0
	// Mask SRAM parity error reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_RPER_1 = 0x1
	// Position of DBGSTOP_RECCR field.
	DBG_DBGSTOPCR_DBGSTOP_RECCR_Pos = 0x19
	// Bit mask of DBGSTOP_RECCR field.
	DBG_DBGSTOPCR_DBGSTOP_RECCR_Msk = 0x2000000
	// Bit DBGSTOP_RECCR.
	DBG_DBGSTOPCR_DBGSTOP_RECCR = 0x2000000
	// Enable SRAM ECC error reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_RECCR_0 = 0x0
	// Mask SRAM ECC error reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_RECCR_1 = 0x1
	// Position of DBGSTOP_CPER field.
	DBG_DBGSTOPCR_DBGSTOP_CPER_Pos = 0x1f
	// Bit mask of DBGSTOP_CPER field.
	DBG_DBGSTOPCR_DBGSTOP_CPER_Msk = 0x80000000
	// Bit DBGSTOP_CPER.
	DBG_DBGSTOPCR_DBGSTOP_CPER = 0x80000000
	// Enable Cache SRAM parity error reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_CPER_0 = 0x0
	// Mask Cache SRAM parity error reset/interrupt
	DBG_DBGSTOPCR_DBGSTOP_CPER_1 = 0x1
)

// Constants for FCACHE: SYSTEM/FLASH
const (
	// FCACHEE: Flash Cache Enable Register
	// Position of FCACHEEN field.
	FCACHE_FCACHEE_FCACHEEN_Pos = 0x0
	// Bit mask of FCACHEEN field.
	FCACHE_FCACHEE_FCACHEEN_Msk = 0x1
	// Bit FCACHEEN.
	FCACHE_FCACHEE_FCACHEEN = 0x1
	// FCACHE is disabled
	FCACHE_FCACHEE_FCACHEEN_0 = 0x0
	// FCACHE is enabled
	FCACHE_FCACHEE_FCACHEEN_1 = 0x1

	// FCACHEIV: Flash Cache Invalidate Register
	// Position of FCACHEIV field.
	FCACHE_FCACHEIV_FCACHEIV_Pos = 0x0
	// Bit mask of FCACHEIV field.
	FCACHE_FCACHEIV_FCACHEIV_Msk = 0x1
	// Bit FCACHEIV.
	FCACHE_FCACHEIV_FCACHEIV = 0x1
	// Read: Do not invalidate. Write: The setting is ignored.
	FCACHE_FCACHEIV_FCACHEIV_0 = 0x0
	// Invalidate FCACHE is invalidated.
	FCACHE_FCACHEIV_FCACHEIV_1 = 0x1

	// FLWT: Flash Wait Cycle Register
	// Position of FLWT field.
	FCACHE_FLWT_FLWT_Pos = 0x0
	// Bit mask of FLWT field.
	FCACHE_FLWT_FLWT_Msk = 0x7
	// 0 wait (ICLK ≤ 50 MHz)
	FCACHE_FLWT_FLWT_000 = 0x0
	// 1 wait (50 MHz < ICLK ≤ 100 MHz)
	FCACHE_FLWT_FLWT_001 = 0x1
	// 2 wait (100 MHz < ICLK ≤ 150 MHz)
	FCACHE_FLWT_FLWT_010 = 0x2
	// 3 wait (ICLK > 150 MHz)
	FCACHE_FLWT_FLWT_011 = 0x3
	// Setting prohibited
	FCACHE_FLWT_FLWT_Others = 0x4

	// FSAR: Flash Security Attribution Register
	// Position of FLWTSA field.
	FCACHE_FSAR_FLWTSA_Pos = 0x0
	// Bit mask of FLWTSA field.
	FCACHE_FSAR_FLWTSA_Msk = 0x1
	// Bit FLWTSA.
	FCACHE_FSAR_FLWTSA = 0x1
	// Secure
	FCACHE_FSAR_FLWTSA_0 = 0x0
	// Non-Secure
	FCACHE_FSAR_FLWTSA_1 = 0x1
	// Position of FCKMHZSA field.
	FCACHE_FSAR_FCKMHZSA_Pos = 0x8
	// Bit mask of FCKMHZSA field.
	FCACHE_FSAR_FCKMHZSA_Msk = 0x100
	// Bit FCKMHZSA.
	FCACHE_FSAR_FCKMHZSA = 0x100
	// Secure
	FCACHE_FSAR_FCKMHZSA_0 = 0x0
	// Non-Secure
	FCACHE_FSAR_FCKMHZSA_1 = 0x1
)

// Constants for SYSC: System Control
const (
	// SBYCR: Standby Control Register
	// Position of SSBY field.
	SYSC_SBYCR_SSBY_Pos = 0xf
	// Bit mask of SSBY field.
	SYSC_SBYCR_SSBY_Msk = 0x8000
	// Bit SSBY.
	SYSC_SBYCR_SSBY = 0x8000
	// Sleep mode
	SYSC_SBYCR_SSBY_0 = 0x0
	// Software Standby mode.
	SYSC_SBYCR_SSBY_1 = 0x1

	// SCKDIVCR: System Clock Division Control Register
	// Position of PCKD field.
	SYSC_SCKDIVCR_PCKD_Pos = 0x0
	// Bit mask of PCKD field.
	SYSC_SCKDIVCR_PCKD_Msk = 0x7
	// x 1/1
	SYSC_SCKDIVCR_PCKD_000 = 0x0
	// x 1/2
	SYSC_SCKDIVCR_PCKD_001 = 0x1
	// x 1/4
	SYSC_SCKDIVCR_PCKD_010 = 0x2
	// x 1/8
	SYSC_SCKDIVCR_PCKD_011 = 0x3
	// x 1/16
	SYSC_SCKDIVCR_PCKD_100 = 0x4
	// x 1/32
	SYSC_SCKDIVCR_PCKD_101 = 0x5
	// x 1/64
	SYSC_SCKDIVCR_PCKD_110 = 0x6
	// Setting prohibited.
	SYSC_SCKDIVCR_PCKD_Others = 0x7
	// Position of PCKC field.
	SYSC_SCKDIVCR_PCKC_Pos = 0x4
	// Bit mask of PCKC field.
	SYSC_SCKDIVCR_PCKC_Msk = 0x70
	// x 1/1
	SYSC_SCKDIVCR_PCKC_000 = 0x0
	// x 1/2
	SYSC_SCKDIVCR_PCKC_001 = 0x1
	// x 1/4
	SYSC_SCKDIVCR_PCKC_010 = 0x2
	// x 1/8
	SYSC_SCKDIVCR_PCKC_011 = 0x3
	// x 1/16
	SYSC_SCKDIVCR_PCKC_100 = 0x4
	// x 1/32
	SYSC_SCKDIVCR_PCKC_101 = 0x5
	// x 1/64
	SYSC_SCKDIVCR_PCKC_110 = 0x6
	// Setting prohibited.
	SYSC_SCKDIVCR_PCKC_Others = 0x7
	// Position of PCKB field.
	SYSC_SCKDIVCR_PCKB_Pos = 0x8
	// Bit mask of PCKB field.
	SYSC_SCKDIVCR_PCKB_Msk = 0x700
	// x 1/1
	SYSC_SCKDIVCR_PCKB_000 = 0x0
	// x 1/2
	SYSC_SCKDIVCR_PCKB_001 = 0x1
	// x 1/4
	SYSC_SCKDIVCR_PCKB_010 = 0x2
	// x 1/8
	SYSC_SCKDIVCR_PCKB_011 = 0x3
	// x 1/16
	SYSC_SCKDIVCR_PCKB_100 = 0x4
	// x 1/32
	SYSC_SCKDIVCR_PCKB_101 = 0x5
	// x 1/64
	SYSC_SCKDIVCR_PCKB_110 = 0x6
	// Setting prohibited.
	SYSC_SCKDIVCR_PCKB_Others = 0x7
	// Position of PCKA field.
	SYSC_SCKDIVCR_PCKA_Pos = 0xc
	// Bit mask of PCKA field.
	SYSC_SCKDIVCR_PCKA_Msk = 0x7000
	// x 1/1
	SYSC_SCKDIVCR_PCKA_000 = 0x0
	// x 1/2
	SYSC_SCKDIVCR_PCKA_001 = 0x1
	// x 1/4
	SYSC_SCKDIVCR_PCKA_010 = 0x2
	// x 1/8
	SYSC_SCKDIVCR_PCKA_011 = 0x3
	// x 1/16
	SYSC_SCKDIVCR_PCKA_100 = 0x4
	// x 1/32
	SYSC_SCKDIVCR_PCKA_101 = 0x5
	// x 1/64
	SYSC_SCKDIVCR_PCKA_110 = 0x6
	// Setting prohibited.
	SYSC_SCKDIVCR_PCKA_Others = 0x7
	// Position of ICK field.
	SYSC_SCKDIVCR_ICK_Pos = 0x18
	// Bit mask of ICK field.
	SYSC_SCKDIVCR_ICK_Msk = 0x7000000
	// x 1/1
	SYSC_SCKDIVCR_ICK_000 = 0x0
	// x 1/2
	SYSC_SCKDIVCR_ICK_001 = 0x1
	// x 1/4
	SYSC_SCKDIVCR_ICK_010 = 0x2
	// x 1/8
	SYSC_SCKDIVCR_ICK_011 = 0x3
	// x 1/16
	SYSC_SCKDIVCR_ICK_100 = 0x4
	// x 1/32
	SYSC_SCKDIVCR_ICK_101 = 0x5
	// x 1/64
	SYSC_SCKDIVCR_ICK_110 = 0x6
	// Setting prohibited.
	SYSC_SCKDIVCR_ICK_Others = 0x7
	// Position of FCK field.
	SYSC_SCKDIVCR_FCK_Pos = 0x1c
	// Bit mask of FCK field.
	SYSC_SCKDIVCR_FCK_Msk = 0x70000000
	// x 1/1
	SYSC_SCKDIVCR_FCK_000 = 0x0
	// x 1/2
	SYSC_SCKDIVCR_FCK_001 = 0x1
	// x 1/4
	SYSC_SCKDIVCR_FCK_010 = 0x2
	// x 1/8
	SYSC_SCKDIVCR_FCK_011 = 0x3
	// x 1/16
	SYSC_SCKDIVCR_FCK_100 = 0x4
	// x 1/32
	SYSC_SCKDIVCR_FCK_101 = 0x5
	// x 1/64
	SYSC_SCKDIVCR_FCK_110 = 0x6
	// Setting prohibited.
	SYSC_SCKDIVCR_FCK_Others = 0x7

	// SCKSCR: System Clock Source Control Register
	// Position of CKSEL field.
	SYSC_SCKSCR_CKSEL_Pos = 0x0
	// Bit mask of CKSEL field.
	SYSC_SCKSCR_CKSEL_Msk = 0x7
	// HOCO
	SYSC_SCKSCR_CKSEL_000 = 0x0
	// MOCO
	SYSC_SCKSCR_CKSEL_001 = 0x1
	// LOCO
	SYSC_SCKSCR_CKSEL_010 = 0x2
	// Main clock oscillator (MOSC)
	SYSC_SCKSCR_CKSEL_011 = 0x3
	// Sub-clock oscillator (SOSC)
	SYSC_SCKSCR_CKSEL_100 = 0x4
	// PLL
	SYSC_SCKSCR_CKSEL_101 = 0x5
	// Setting prohibited
	SYSC_SCKSCR_CKSEL_110 = 0x6
	// Setting prohibited
	SYSC_SCKSCR_CKSEL_111 = 0x7

	// PLLCCR: PLL Clock Control Register
	// Position of PLIDIV field.
	SYSC_PLLCCR_PLIDIV_Pos = 0x0
	// Bit mask of PLIDIV field.
	SYSC_PLLCCR_PLIDIV_Msk = 0x3
	// /1
	SYSC_PLLCCR_PLIDIV_00 = 0x0
	// /2
	SYSC_PLLCCR_PLIDIV_01 = 0x1
	// /3
	SYSC_PLLCCR_PLIDIV_10 = 0x2
	// Setting prohibited.
	SYSC_PLLCCR_PLIDIV_Others = 0x3
	// Position of PLSRCSEL field.
	SYSC_PLLCCR_PLSRCSEL_Pos = 0x4
	// Bit mask of PLSRCSEL field.
	SYSC_PLLCCR_PLSRCSEL_Msk = 0x10
	// Bit PLSRCSEL.
	SYSC_PLLCCR_PLSRCSEL = 0x10
	// Main clock oscillator
	SYSC_PLLCCR_PLSRCSEL_0 = 0x0
	// HOCO
	SYSC_PLLCCR_PLSRCSEL_1 = 0x1
	// Position of PLLMUL field.
	SYSC_PLLCCR_PLLMUL_Pos = 0x8
	// Bit mask of PLLMUL field.
	SYSC_PLLCCR_PLLMUL_Msk = 0x3f00

	// PLLCR: PLL Control Register
	// Position of PLLSTP field.
	SYSC_PLLCR_PLLSTP_Pos = 0x0
	// Bit mask of PLLSTP field.
	SYSC_PLLCR_PLLSTP_Msk = 0x1
	// Bit PLLSTP.
	SYSC_PLLCR_PLLSTP = 0x1
	// PLL is operating
	SYSC_PLLCR_PLLSTP_0 = 0x0
	// PLL is stopped.
	SYSC_PLLCR_PLLSTP_1 = 0x1

	// MOSCCR: Main Clock Oscillator Control Register
	// Position of MOSTP field.
	SYSC_MOSCCR_MOSTP_Pos = 0x0
	// Bit mask of MOSTP field.
	SYSC_MOSCCR_MOSTP_Msk = 0x1
	// Bit MOSTP.
	SYSC_MOSCCR_MOSTP = 0x1
	// Operate the main clock oscillator
	SYSC_MOSCCR_MOSTP_0 = 0x0
	// Stop the main clock oscillator
	SYSC_MOSCCR_MOSTP_1 = 0x1

	// HOCOCR: High-Speed On-Chip Oscillator Control Register
	// Position of HCSTP field.
	SYSC_HOCOCR_HCSTP_Pos = 0x0
	// Bit mask of HCSTP field.
	SYSC_HOCOCR_HCSTP_Msk = 0x1
	// Bit HCSTP.
	SYSC_HOCOCR_HCSTP = 0x1
	// Operate the HOCO clock
	SYSC_HOCOCR_HCSTP_0 = 0x0
	// Stop the HOCO clock
	SYSC_HOCOCR_HCSTP_1 = 0x1

	// MOCOCR: Middle-Speed On-Chip Oscillator Control Register
	// Position of MCSTP field.
	SYSC_MOCOCR_MCSTP_Pos = 0x0
	// Bit mask of MCSTP field.
	SYSC_MOCOCR_MCSTP_Msk = 0x1
	// Bit MCSTP.
	SYSC_MOCOCR_MCSTP = 0x1
	// MOCO clock is operating
	SYSC_MOCOCR_MCSTP_0 = 0x0
	// MOCO clock is stopped
	SYSC_MOCOCR_MCSTP_1 = 0x1

	// FLLCR1: FLL Control Register1
	// Position of FLLEN field.
	SYSC_FLLCR1_FLLEN_Pos = 0x0
	// Bit mask of FLLEN field.
	SYSC_FLLCR1_FLLEN_Msk = 0x1
	// Bit FLLEN.
	SYSC_FLLCR1_FLLEN = 0x1
	// FLL function is disabled
	SYSC_FLLCR1_FLLEN_0 = 0x0
	// FLL function is enabled.
	SYSC_FLLCR1_FLLEN_1 = 0x1

	// FLLCR2: FLL Control Register2
	// Position of FLLCNTL field.
	SYSC_FLLCR2_FLLCNTL_Pos = 0x0
	// Bit mask of FLLCNTL field.
	SYSC_FLLCR2_FLLCNTL_Msk = 0x7ff

	// OSCSF: Oscillation Stabilization Flag Register
	// Position of HOCOSF field.
	SYSC_OSCSF_HOCOSF_Pos = 0x0
	// Bit mask of HOCOSF field.
	SYSC_OSCSF_HOCOSF_Msk = 0x1
	// Bit HOCOSF.
	SYSC_OSCSF_HOCOSF = 0x1
	// The HOCO clock is stopped or is not yet stable
	SYSC_OSCSF_HOCOSF_0 = 0x0
	// The HOCO clock is stable, so is available for use as the system clock
	SYSC_OSCSF_HOCOSF_1 = 0x1
	// Position of MOSCSF field.
	SYSC_OSCSF_MOSCSF_Pos = 0x3
	// Bit mask of MOSCSF field.
	SYSC_OSCSF_MOSCSF_Msk = 0x8
	// Bit MOSCSF.
	SYSC_OSCSF_MOSCSF = 0x8
	// The main clock oscillator is stopped (MOSTP = 1) or is not yet stable
	SYSC_OSCSF_MOSCSF_0 = 0x0
	// The main clock oscillator is stable, so is available for use as the system clock
	SYSC_OSCSF_MOSCSF_1 = 0x1
	// Position of PLLSF field.
	SYSC_OSCSF_PLLSF_Pos = 0x5
	// Bit mask of PLLSF field.
	SYSC_OSCSF_PLLSF_Msk = 0x20
	// Bit PLLSF.
	SYSC_OSCSF_PLLSF = 0x20
	// The PLL clock is stopped, or oscillation of the PLL clock is not stable yet
	SYSC_OSCSF_PLLSF_0 = 0x0
	// The PLL clock is stable, so is available for use as the system clock
	SYSC_OSCSF_PLLSF_1 = 0x1

	// CKOCR: Clock Out Control Register
	// Position of CKOSEL field.
	SYSC_CKOCR_CKOSEL_Pos = 0x0
	// Bit mask of CKOSEL field.
	SYSC_CKOCR_CKOSEL_Msk = 0x7
	// HOCO (value after reset)
	SYSC_CKOCR_CKOSEL_000 = 0x0
	// MOCO
	SYSC_CKOCR_CKOSEL_001 = 0x1
	// LOCO
	SYSC_CKOCR_CKOSEL_010 = 0x2
	// MOSC
	SYSC_CKOCR_CKOSEL_011 = 0x3
	// SOSC
	SYSC_CKOCR_CKOSEL_100 = 0x4
	// Setting prohibited
	SYSC_CKOCR_CKOSEL_101 = 0x5
	// Setting prohibited
	SYSC_CKOCR_CKOSEL_Others = 0x6
	// Position of CKODIV field.
	SYSC_CKOCR_CKODIV_Pos = 0x4
	// Bit mask of CKODIV field.
	SYSC_CKOCR_CKODIV_Msk = 0x70
	// x 1/1
	SYSC_CKOCR_CKODIV_000 = 0x0
	// x 1/2
	SYSC_CKOCR_CKODIV_001 = 0x1
	// x 1/4
	SYSC_CKOCR_CKODIV_010 = 0x2
	// x 1/8
	SYSC_CKOCR_CKODIV_011 = 0x3
	// x 1/16
	SYSC_CKOCR_CKODIV_100 = 0x4
	// x 1/32
	SYSC_CKOCR_CKODIV_101 = 0x5
	// x 1/64
	SYSC_CKOCR_CKODIV_110 = 0x6
	// x 1/128
	SYSC_CKOCR_CKODIV_111 = 0x7
	// Position of CKOEN field.
	SYSC_CKOCR_CKOEN_Pos = 0x7
	// Bit mask of CKOEN field.
	SYSC_CKOCR_CKOEN_Msk = 0x80
	// Bit CKOEN.
	SYSC_CKOCR_CKOEN = 0x80
	// Disable clock out
	SYSC_CKOCR_CKOEN_0 = 0x0
	// Enable clock out
	SYSC_CKOCR_CKOEN_1 = 0x1

	// OSTDCR: Oscillation Stop Detection Control Register
	// Position of OSTDIE field.
	SYSC_OSTDCR_OSTDIE_Pos = 0x0
	// Bit mask of OSTDIE field.
	SYSC_OSTDCR_OSTDIE_Msk = 0x1
	// Bit OSTDIE.
	SYSC_OSTDCR_OSTDIE = 0x1
	// Disable oscillation stop detection interrupt (do not notify the POEG)
	SYSC_OSTDCR_OSTDIE_0 = 0x0
	// Enable oscillation stop detection interrupt (notify the POEG)
	SYSC_OSTDCR_OSTDIE_1 = 0x1
	// Position of OSTDE field.
	SYSC_OSTDCR_OSTDE_Pos = 0x7
	// Bit mask of OSTDE field.
	SYSC_OSTDCR_OSTDE_Msk = 0x80
	// Bit OSTDE.
	SYSC_OSTDCR_OSTDE = 0x80
	// Disable oscillation stop detection function
	SYSC_OSTDCR_OSTDE_0 = 0x0
	// Enable oscillation stop detection function
	SYSC_OSTDCR_OSTDE_1 = 0x1

	// OSTDSR: Oscillation Stop Detection Status Register
	// Position of OSTDF field.
	SYSC_OSTDSR_OSTDF_Pos = 0x0
	// Bit mask of OSTDF field.
	SYSC_OSTDSR_OSTDF_Msk = 0x1
	// Bit OSTDF.
	SYSC_OSTDSR_OSTDF = 0x1
	// Main clock oscillation stop not detected
	SYSC_OSTDSR_OSTDF_0 = 0x0
	// Main clock oscillation stop detected
	SYSC_OSTDSR_OSTDF_1 = 0x1

	// MOCOUTCR: MOCO User Trimming Control Register
	// Position of MOCOUTRM field.
	SYSC_MOCOUTCR_MOCOUTRM_Pos = 0x0
	// Bit mask of MOCOUTRM field.
	SYSC_MOCOUTCR_MOCOUTRM_Msk = 0xff

	// HOCOUTCR: HOCO User Trimming Control Register
	// Position of HOCOUTRM field.
	SYSC_HOCOUTCR_HOCOUTRM_Pos = 0x0
	// Bit mask of HOCOUTRM field.
	SYSC_HOCOUTCR_HOCOUTRM_Msk = 0xff

	// USBCKDIVCR: USB Clock Division Control Register
	// Position of USBCKDIV field.
	SYSC_USBCKDIVCR_USBCKDIV_Pos = 0x0
	// Bit mask of USBCKDIV field.
	SYSC_USBCKDIVCR_USBCKDIV_Msk = 0x7
	// Setting prohibited.
	SYSC_USBCKDIVCR_USBCKDIV_Others = 0x0
	// ∕ 4
	SYSC_USBCKDIVCR_USBCKDIV_010 = 0x2
	// ∕ 3
	SYSC_USBCKDIVCR_USBCKDIV_101 = 0x5
	// ∕ 5
	SYSC_USBCKDIVCR_USBCKDIV_110 = 0x6

	// CANFDCKDIVCR: CANFD Clock Division Control Register
	// Position of CANFDCKDIV field.
	SYSC_CANFDCKDIVCR_CANFDCKDIV_Pos = 0x0
	// Bit mask of CANFDCKDIV field.
	SYSC_CANFDCKDIVCR_CANFDCKDIV_Msk = 0x7
	// /1 (value after reset) /2 /4 /6 /8 /3 /5
	SYSC_CANFDCKDIVCR_CANFDCKDIV_000 = 0x0

	// CECCKDIVCR: CEC Clock Division Control Register
	// Position of CECCKDIV field.
	SYSC_CECCKDIVCR_CECCKDIV_Pos = 0x0
	// Bit mask of CECCKDIV field.
	SYSC_CECCKDIVCR_CECCKDIV_Msk = 0x7
	// /1 (value after reset)
	SYSC_CECCKDIVCR_CECCKDIV_000 = 0x0
	// /2
	SYSC_CECCKDIVCR_CECCKDIV_001 = 0x1
	// Setting prohibited
	SYSC_CECCKDIVCR_CECCKDIV_Others = 0x2

	// I3CCKDIVCR: I3C Clock Division Control Register
	// Position of I3CCKDIV field.
	SYSC_I3CCKDIVCR_I3CCKDIV_Pos = 0x0
	// Bit mask of I3CCKDIV field.
	SYSC_I3CCKDIVCR_I3CCKDIV_Msk = 0x7
	// /1 (value after reset)
	SYSC_I3CCKDIVCR_I3CCKDIV_000 = 0x0
	// /2
	SYSC_I3CCKDIVCR_I3CCKDIV_001 = 0x1
	// /4
	SYSC_I3CCKDIVCR_I3CCKDIV_010 = 0x2
	// /6
	SYSC_I3CCKDIVCR_I3CCKDIV_011 = 0x3
	// /8
	SYSC_I3CCKDIVCR_I3CCKDIV_100 = 0x4
	// Setting prohibited
	SYSC_I3CCKDIVCR_I3CCKDIV_Others = 0x5

	// USBCKCR: USB Clock Control Register
	// Position of USBCKSEL field.
	SYSC_USBCKCR_USBCKSEL_Pos = 0x0
	// Bit mask of USBCKSEL field.
	SYSC_USBCKCR_USBCKSEL_Msk = 0x7
	// Setting prohibited.
	SYSC_USBCKCR_USBCKSEL_Others = 0x0
	// PLL
	SYSC_USBCKCR_USBCKSEL_101 = 0x5
	// Position of USBCKSREQ field.
	SYSC_USBCKCR_USBCKSREQ_Pos = 0x6
	// Bit mask of USBCKSREQ field.
	SYSC_USBCKCR_USBCKSREQ_Msk = 0x40
	// Bit USBCKSREQ.
	SYSC_USBCKCR_USBCKSREQ = 0x40
	// No request
	SYSC_USBCKCR_USBCKSREQ_0 = 0x0
	// Request switching.
	SYSC_USBCKCR_USBCKSREQ_1 = 0x1
	// Position of USBCKSRDY field.
	SYSC_USBCKCR_USBCKSRDY_Pos = 0x7
	// Bit mask of USBCKSRDY field.
	SYSC_USBCKCR_USBCKSRDY_Msk = 0x80
	// Bit USBCKSRDY.
	SYSC_USBCKCR_USBCKSRDY = 0x80
	// Impossible to Switch
	SYSC_USBCKCR_USBCKSRDY_0 = 0x0
	// Possible to Switch
	SYSC_USBCKCR_USBCKSRDY_1 = 0x1

	// CANFDCKCR: CANFD Clock Control Register
	// Position of CANFDCKSEL field.
	SYSC_CANFDCKCR_CANFDCKSEL_Pos = 0x0
	// Bit mask of CANFDCKSEL field.
	SYSC_CANFDCKCR_CANFDCKSEL_Msk = 0x7
	// Setting prohibited
	SYSC_CANFDCKCR_CANFDCKSEL_Others = 0x0
	// PLL
	SYSC_CANFDCKCR_CANFDCKSEL_101 = 0x5
	// Position of CANFDCKSREQ field.
	SYSC_CANFDCKCR_CANFDCKSREQ_Pos = 0x6
	// Bit mask of CANFDCKSREQ field.
	SYSC_CANFDCKCR_CANFDCKSREQ_Msk = 0x40
	// Bit CANFDCKSREQ.
	SYSC_CANFDCKCR_CANFDCKSREQ = 0x40
	// No request
	SYSC_CANFDCKCR_CANFDCKSREQ_0 = 0x0
	// Request switching
	SYSC_CANFDCKCR_CANFDCKSREQ_1 = 0x1
	// Position of CANFDCKSRDY field.
	SYSC_CANFDCKCR_CANFDCKSRDY_Pos = 0x7
	// Bit mask of CANFDCKSRDY field.
	SYSC_CANFDCKCR_CANFDCKSRDY_Msk = 0x80
	// Bit CANFDCKSRDY.
	SYSC_CANFDCKCR_CANFDCKSRDY = 0x80
	// Impossible to Switch
	SYSC_CANFDCKCR_CANFDCKSRDY_0 = 0x0
	// Possible to Switch
	SYSC_CANFDCKCR_CANFDCKSRDY_1 = 0x1

	// CECCKCR: CEC Clock Control Register
	// Position of CECCKSEL field.
	SYSC_CECCKCR_CECCKSEL_Pos = 0x0
	// Bit mask of CECCKSEL field.
	SYSC_CECCKCR_CECCKSEL_Msk = 0x7
	// Setting prohibited
	SYSC_CECCKCR_CECCKSEL_Others = 0x0
	// Main clock oscillator
	SYSC_CECCKCR_CECCKSEL_011 = 0x3
	// Sub-clock oscillator
	SYSC_CECCKCR_CECCKSEL_100 = 0x4
	// Position of CECCKSREQ field.
	SYSC_CECCKCR_CECCKSREQ_Pos = 0x6
	// Bit mask of CECCKSREQ field.
	SYSC_CECCKCR_CECCKSREQ_Msk = 0x40
	// Bit CECCKSREQ.
	SYSC_CECCKCR_CECCKSREQ = 0x40
	// No request
	SYSC_CECCKCR_CECCKSREQ_0 = 0x0
	// Request switching
	SYSC_CECCKCR_CECCKSREQ_1 = 0x1
	// Position of CECCKSRDY field.
	SYSC_CECCKCR_CECCKSRDY_Pos = 0x7
	// Bit mask of CECCKSRDY field.
	SYSC_CECCKCR_CECCKSRDY_Msk = 0x80
	// Bit CECCKSRDY.
	SYSC_CECCKCR_CECCKSRDY = 0x80
	// Impossible to Switch
	SYSC_CECCKCR_CECCKSRDY_0 = 0x0
	// Possible to Switch
	SYSC_CECCKCR_CECCKSRDY_1 = 0x1

	// I3CCKCR: I3C Clock Control Register
	// Position of I3CCKSEL field.
	SYSC_I3CCKCR_I3CCKSEL_Pos = 0x0
	// Bit mask of I3CCKSEL field.
	SYSC_I3CCKCR_I3CCKSEL_Msk = 0x7
	// HOCO
	SYSC_I3CCKCR_I3CCKSEL_000 = 0x0
	// MOCO (value after reset)
	SYSC_I3CCKCR_I3CCKSEL_001 = 0x1
	// LOCO
	SYSC_I3CCKCR_I3CCKSEL_010 = 0x2
	// Main clock oscillator
	SYSC_I3CCKCR_I3CCKSEL_011 = 0x3
	// Sub-clock oscillator
	SYSC_I3CCKCR_I3CCKSEL_100 = 0x4
	// PLL
	SYSC_I3CCKCR_I3CCKSEL_101 = 0x5
	// Setting prohibited
	SYSC_I3CCKCR_I3CCKSEL_Others = 0x6
	// Position of I3CCKSREQ field.
	SYSC_I3CCKCR_I3CCKSREQ_Pos = 0x6
	// Bit mask of I3CCKSREQ field.
	SYSC_I3CCKCR_I3CCKSREQ_Msk = 0x40
	// Bit I3CCKSREQ.
	SYSC_I3CCKCR_I3CCKSREQ = 0x40
	// No request
	SYSC_I3CCKCR_I3CCKSREQ_0 = 0x0
	// Request switching
	SYSC_I3CCKCR_I3CCKSREQ_1 = 0x1
	// Position of I3CCKSRDY field.
	SYSC_I3CCKCR_I3CCKSRDY_Pos = 0x7
	// Bit mask of I3CCKSRDY field.
	SYSC_I3CCKCR_I3CCKSRDY_Msk = 0x80
	// Bit I3CCKSRDY.
	SYSC_I3CCKCR_I3CCKSRDY = 0x80
	// Impossible to Switch
	SYSC_I3CCKCR_I3CCKSRDY_0 = 0x0
	// Possible to Switch
	SYSC_I3CCKCR_I3CCKSRDY_1 = 0x1

	// SNZCR: Snooze Control Register
	// Position of RXDREQEN field.
	SYSC_SNZCR_RXDREQEN_Pos = 0x0
	// Bit mask of RXDREQEN field.
	SYSC_SNZCR_RXDREQEN_Msk = 0x1
	// Bit RXDREQEN.
	SYSC_SNZCR_RXDREQEN = 0x1
	// Ignore RXD0 falling edge in Software Standby mode
	SYSC_SNZCR_RXDREQEN_0 = 0x0
	// Detect RXD0 falling edge in Software Standby mode
	SYSC_SNZCR_RXDREQEN_1 = 0x1
	// Position of SNZDTCEN field.
	SYSC_SNZCR_SNZDTCEN_Pos = 0x1
	// Bit mask of SNZDTCEN field.
	SYSC_SNZCR_SNZDTCEN_Msk = 0x2
	// Bit SNZDTCEN.
	SYSC_SNZCR_SNZDTCEN = 0x2
	// Disable DTC operation
	SYSC_SNZCR_SNZDTCEN_0 = 0x0
	// Enable DTC operation
	SYSC_SNZCR_SNZDTCEN_1 = 0x1
	// Position of SNZE field.
	SYSC_SNZCR_SNZE_Pos = 0x7
	// Bit mask of SNZE field.
	SYSC_SNZCR_SNZE_Msk = 0x80
	// Bit SNZE.
	SYSC_SNZCR_SNZE = 0x80
	// Disable Snooze mode
	SYSC_SNZCR_SNZE_0 = 0x0
	// Enable Snooze mode
	SYSC_SNZCR_SNZE_1 = 0x1

	// SNZEDCR0: Snooze End Control Register 0
	// Position of AGTUNFED field.
	SYSC_SNZEDCR0_AGTUNFED_Pos = 0x0
	// Bit mask of AGTUNFED field.
	SYSC_SNZEDCR0_AGTUNFED_Msk = 0x1
	// Bit AGTUNFED.
	SYSC_SNZEDCR0_AGTUNFED = 0x1
	// Disable the snooze end request
	SYSC_SNZEDCR0_AGTUNFED_0 = 0x0
	// Enable the snooze end request
	SYSC_SNZEDCR0_AGTUNFED_1 = 0x1
	// Position of DTCZRED field.
	SYSC_SNZEDCR0_DTCZRED_Pos = 0x1
	// Bit mask of DTCZRED field.
	SYSC_SNZEDCR0_DTCZRED_Msk = 0x2
	// Bit DTCZRED.
	SYSC_SNZEDCR0_DTCZRED = 0x2
	// Disable the snooze end request
	SYSC_SNZEDCR0_DTCZRED_0 = 0x0
	// Enable the snooze end request
	SYSC_SNZEDCR0_DTCZRED_1 = 0x1
	// Position of DTCNZRED field.
	SYSC_SNZEDCR0_DTCNZRED_Pos = 0x2
	// Bit mask of DTCNZRED field.
	SYSC_SNZEDCR0_DTCNZRED_Msk = 0x4
	// Bit DTCNZRED.
	SYSC_SNZEDCR0_DTCNZRED = 0x4
	// Disable the snooze end request
	SYSC_SNZEDCR0_DTCNZRED_0 = 0x0
	// Enable the snooze end request
	SYSC_SNZEDCR0_DTCNZRED_1 = 0x1
	// Position of AD0MATED field.
	SYSC_SNZEDCR0_AD0MATED_Pos = 0x3
	// Bit mask of AD0MATED field.
	SYSC_SNZEDCR0_AD0MATED_Msk = 0x8
	// Bit AD0MATED.
	SYSC_SNZEDCR0_AD0MATED = 0x8
	// Disable the snooze end request
	SYSC_SNZEDCR0_AD0MATED_0 = 0x0
	// Enable the snooze end request
	SYSC_SNZEDCR0_AD0MATED_1 = 0x1
	// Position of AD0UMTED field.
	SYSC_SNZEDCR0_AD0UMTED_Pos = 0x4
	// Bit mask of AD0UMTED field.
	SYSC_SNZEDCR0_AD0UMTED_Msk = 0x10
	// Bit AD0UMTED.
	SYSC_SNZEDCR0_AD0UMTED = 0x10
	// Disable the snooze end request
	SYSC_SNZEDCR0_AD0UMTED_0 = 0x0
	// Enable the snooze end request
	SYSC_SNZEDCR0_AD0UMTED_1 = 0x1
	// Position of SCI0UMTED field.
	SYSC_SNZEDCR0_SCI0UMTED_Pos = 0x7
	// Bit mask of SCI0UMTED field.
	SYSC_SNZEDCR0_SCI0UMTED_Msk = 0x80
	// Bit SCI0UMTED.
	SYSC_SNZEDCR0_SCI0UMTED = 0x80
	// Disable the snooze end request
	SYSC_SNZEDCR0_SCI0UMTED_0 = 0x0
	// Enable the snooze end request
	SYSC_SNZEDCR0_SCI0UMTED_1 = 0x1

	// SNZREQCR0: Snooze Request Control Register 0
	// Position of SNZREQEN0 field.
	SYSC_SNZREQCR0_SNZREQEN0_Pos = 0x0
	// Bit mask of SNZREQEN0 field.
	SYSC_SNZREQCR0_SNZREQEN0_Msk = 0x1
	// Bit SNZREQEN0.
	SYSC_SNZREQCR0_SNZREQEN0 = 0x1
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN0_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN0_1 = 0x1
	// Position of SNZREQEN1 field.
	SYSC_SNZREQCR0_SNZREQEN1_Pos = 0x1
	// Bit mask of SNZREQEN1 field.
	SYSC_SNZREQCR0_SNZREQEN1_Msk = 0x2
	// Bit SNZREQEN1.
	SYSC_SNZREQCR0_SNZREQEN1 = 0x2
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN1_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN1_1 = 0x1
	// Position of SNZREQEN2 field.
	SYSC_SNZREQCR0_SNZREQEN2_Pos = 0x2
	// Bit mask of SNZREQEN2 field.
	SYSC_SNZREQCR0_SNZREQEN2_Msk = 0x4
	// Bit SNZREQEN2.
	SYSC_SNZREQCR0_SNZREQEN2 = 0x4
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN2_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN2_1 = 0x1
	// Position of SNZREQEN3 field.
	SYSC_SNZREQCR0_SNZREQEN3_Pos = 0x3
	// Bit mask of SNZREQEN3 field.
	SYSC_SNZREQCR0_SNZREQEN3_Msk = 0x8
	// Bit SNZREQEN3.
	SYSC_SNZREQCR0_SNZREQEN3 = 0x8
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN3_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN3_1 = 0x1
	// Position of SNZREQEN4 field.
	SYSC_SNZREQCR0_SNZREQEN4_Pos = 0x4
	// Bit mask of SNZREQEN4 field.
	SYSC_SNZREQCR0_SNZREQEN4_Msk = 0x10
	// Bit SNZREQEN4.
	SYSC_SNZREQCR0_SNZREQEN4 = 0x10
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN4_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN4_1 = 0x1
	// Position of SNZREQEN5 field.
	SYSC_SNZREQCR0_SNZREQEN5_Pos = 0x5
	// Bit mask of SNZREQEN5 field.
	SYSC_SNZREQCR0_SNZREQEN5_Msk = 0x20
	// Bit SNZREQEN5.
	SYSC_SNZREQCR0_SNZREQEN5 = 0x20
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN5_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN5_1 = 0x1
	// Position of SNZREQEN6 field.
	SYSC_SNZREQCR0_SNZREQEN6_Pos = 0x6
	// Bit mask of SNZREQEN6 field.
	SYSC_SNZREQCR0_SNZREQEN6_Msk = 0x40
	// Bit SNZREQEN6.
	SYSC_SNZREQCR0_SNZREQEN6 = 0x40
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN6_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN6_1 = 0x1
	// Position of SNZREQEN7 field.
	SYSC_SNZREQCR0_SNZREQEN7_Pos = 0x7
	// Bit mask of SNZREQEN7 field.
	SYSC_SNZREQCR0_SNZREQEN7_Msk = 0x80
	// Bit SNZREQEN7.
	SYSC_SNZREQCR0_SNZREQEN7 = 0x80
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN7_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN7_1 = 0x1
	// Position of SNZREQEN8 field.
	SYSC_SNZREQCR0_SNZREQEN8_Pos = 0x8
	// Bit mask of SNZREQEN8 field.
	SYSC_SNZREQCR0_SNZREQEN8_Msk = 0x100
	// Bit SNZREQEN8.
	SYSC_SNZREQCR0_SNZREQEN8 = 0x100
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN8_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN8_1 = 0x1
	// Position of SNZREQEN9 field.
	SYSC_SNZREQCR0_SNZREQEN9_Pos = 0x9
	// Bit mask of SNZREQEN9 field.
	SYSC_SNZREQCR0_SNZREQEN9_Msk = 0x200
	// Bit SNZREQEN9.
	SYSC_SNZREQCR0_SNZREQEN9 = 0x200
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN9_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN9_1 = 0x1
	// Position of SNZREQEN10 field.
	SYSC_SNZREQCR0_SNZREQEN10_Pos = 0xa
	// Bit mask of SNZREQEN10 field.
	SYSC_SNZREQCR0_SNZREQEN10_Msk = 0x400
	// Bit SNZREQEN10.
	SYSC_SNZREQCR0_SNZREQEN10 = 0x400
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN10_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN10_1 = 0x1
	// Position of SNZREQEN11 field.
	SYSC_SNZREQCR0_SNZREQEN11_Pos = 0xb
	// Bit mask of SNZREQEN11 field.
	SYSC_SNZREQCR0_SNZREQEN11_Msk = 0x800
	// Bit SNZREQEN11.
	SYSC_SNZREQCR0_SNZREQEN11 = 0x800
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN11_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN11_1 = 0x1
	// Position of SNZREQEN12 field.
	SYSC_SNZREQCR0_SNZREQEN12_Pos = 0xc
	// Bit mask of SNZREQEN12 field.
	SYSC_SNZREQCR0_SNZREQEN12_Msk = 0x1000
	// Bit SNZREQEN12.
	SYSC_SNZREQCR0_SNZREQEN12 = 0x1000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN12_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN12_1 = 0x1
	// Position of SNZREQEN13 field.
	SYSC_SNZREQCR0_SNZREQEN13_Pos = 0xd
	// Bit mask of SNZREQEN13 field.
	SYSC_SNZREQCR0_SNZREQEN13_Msk = 0x2000
	// Bit SNZREQEN13.
	SYSC_SNZREQCR0_SNZREQEN13 = 0x2000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN13_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN13_1 = 0x1
	// Position of SNZREQEN14 field.
	SYSC_SNZREQCR0_SNZREQEN14_Pos = 0xe
	// Bit mask of SNZREQEN14 field.
	SYSC_SNZREQCR0_SNZREQEN14_Msk = 0x4000
	// Bit SNZREQEN14.
	SYSC_SNZREQCR0_SNZREQEN14 = 0x4000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN14_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN14_1 = 0x1
	// Position of SNZREQEN24 field.
	SYSC_SNZREQCR0_SNZREQEN24_Pos = 0x18
	// Bit mask of SNZREQEN24 field.
	SYSC_SNZREQCR0_SNZREQEN24_Msk = 0x1000000
	// Bit SNZREQEN24.
	SYSC_SNZREQCR0_SNZREQEN24 = 0x1000000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN24_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN24_1 = 0x1
	// Position of SNZREQEN25 field.
	SYSC_SNZREQCR0_SNZREQEN25_Pos = 0x19
	// Bit mask of SNZREQEN25 field.
	SYSC_SNZREQCR0_SNZREQEN25_Msk = 0x2000000
	// Bit SNZREQEN25.
	SYSC_SNZREQCR0_SNZREQEN25 = 0x2000000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN25_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN25_1 = 0x1
	// Position of SNZREQEN28 field.
	SYSC_SNZREQCR0_SNZREQEN28_Pos = 0x1c
	// Bit mask of SNZREQEN28 field.
	SYSC_SNZREQCR0_SNZREQEN28_Msk = 0x10000000
	// Bit SNZREQEN28.
	SYSC_SNZREQCR0_SNZREQEN28 = 0x10000000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN28_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN28_1 = 0x1
	// Position of SNZREQEN29 field.
	SYSC_SNZREQCR0_SNZREQEN29_Pos = 0x1d
	// Bit mask of SNZREQEN29 field.
	SYSC_SNZREQCR0_SNZREQEN29_Msk = 0x20000000
	// Bit SNZREQEN29.
	SYSC_SNZREQCR0_SNZREQEN29 = 0x20000000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN29_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN29_1 = 0x1
	// Position of SNZREQEN30 field.
	SYSC_SNZREQCR0_SNZREQEN30_Pos = 0x1e
	// Bit mask of SNZREQEN30 field.
	SYSC_SNZREQCR0_SNZREQEN30_Msk = 0x40000000
	// Bit SNZREQEN30.
	SYSC_SNZREQCR0_SNZREQEN30 = 0x40000000
	// Disable the snooze request
	SYSC_SNZREQCR0_SNZREQEN30_0 = 0x0
	// Enable the snooze request
	SYSC_SNZREQCR0_SNZREQEN30_1 = 0x1

	// OPCCR: Operating Power Control Register
	// Position of OPCM field.
	SYSC_OPCCR_OPCM_Pos = 0x0
	// Bit mask of OPCM field.
	SYSC_OPCCR_OPCM_Msk = 0x3
	// High-speed mode
	SYSC_OPCCR_OPCM_00 = 0x0
	// Setting prohibited
	SYSC_OPCCR_OPCM_01 = 0x1
	// Setting prohibited
	SYSC_OPCCR_OPCM_10 = 0x2
	// Low-speed mode
	SYSC_OPCCR_OPCM_11 = 0x3
	// Position of OPCMTSF field.
	SYSC_OPCCR_OPCMTSF_Pos = 0x4
	// Bit mask of OPCMTSF field.
	SYSC_OPCCR_OPCMTSF_Msk = 0x10
	// Bit OPCMTSF.
	SYSC_OPCCR_OPCMTSF = 0x10
	// Transition completed
	SYSC_OPCCR_OPCMTSF_0 = 0x0
	// During transition
	SYSC_OPCCR_OPCMTSF_1 = 0x1

	// MOSCWTCR: Main Clock Oscillator Wait Control Register
	// Position of MSTS field.
	SYSC_MOSCWTCR_MSTS_Pos = 0x0
	// Bit mask of MSTS field.
	SYSC_MOSCWTCR_MSTS_Msk = 0xf
	// Wait time = 3 cycles (11.4 us)
	SYSC_MOSCWTCR_MSTS_0x0 = 0x0
	// Wait time = 35 cycles (133.5 us)
	SYSC_MOSCWTCR_MSTS_0x1 = 0x1
	// Wait time = 67 cycles (255.6 us)
	SYSC_MOSCWTCR_MSTS_0x2 = 0x2
	// Wait time = 131 cycles (499.7 us)
	SYSC_MOSCWTCR_MSTS_0x3 = 0x3
	// Wait time = 259 cycles (988.0 us)
	SYSC_MOSCWTCR_MSTS_0x4 = 0x4
	// Wait time = 547 cycles (2086.6 us)
	SYSC_MOSCWTCR_MSTS_0x5 = 0x5
	// Wait time = 1059 cycles (4039.8 us)
	SYSC_MOSCWTCR_MSTS_0x6 = 0x6
	// Wait time = 2147 cycles (8190.2 us)
	SYSC_MOSCWTCR_MSTS_0x7 = 0x7
	// Wait time = 4291 cycles (16368.9 us)
	SYSC_MOSCWTCR_MSTS_0x8 = 0x8
	// Wait time = 8163 cycles (31139.4 us)
	SYSC_MOSCWTCR_MSTS_0x9 = 0x9
	// Setting prohibited
	SYSC_MOSCWTCR_MSTS_Others = 0xa

	// SOPCCR: Sub Operating Power Control Register
	// Position of SOPCM field.
	SYSC_SOPCCR_SOPCM_Pos = 0x0
	// Bit mask of SOPCM field.
	SYSC_SOPCCR_SOPCM_Msk = 0x1
	// Bit SOPCM.
	SYSC_SOPCCR_SOPCM = 0x1
	// Other than Subosc-speed mode
	SYSC_SOPCCR_SOPCM_0 = 0x0
	// Subosc-speed mode
	SYSC_SOPCCR_SOPCM_1 = 0x1
	// Position of SOPCMTSF field.
	SYSC_SOPCCR_SOPCMTSF_Pos = 0x4
	// Bit mask of SOPCMTSF field.
	SYSC_SOPCCR_SOPCMTSF_Msk = 0x10
	// Bit SOPCMTSF.
	SYSC_SOPCCR_SOPCMTSF = 0x10
	// Transition completed
	SYSC_SOPCCR_SOPCMTSF_0 = 0x0
	// During transition
	SYSC_SOPCCR_SOPCMTSF_1 = 0x1

	// RSTSR1: Reset Status Register 1
	// Position of IWDTRF field.
	SYSC_RSTSR1_IWDTRF_Pos = 0x0
	// Bit mask of IWDTRF field.
	SYSC_RSTSR1_IWDTRF_Msk = 0x1
	// Bit IWDTRF.
	SYSC_RSTSR1_IWDTRF = 0x1
	// Independent watchdog timer reset not detected
	SYSC_RSTSR1_IWDTRF_0 = 0x0
	// Independent watchdog timer reset detected
	SYSC_RSTSR1_IWDTRF_1 = 0x1
	// Position of WDTRF field.
	SYSC_RSTSR1_WDTRF_Pos = 0x1
	// Bit mask of WDTRF field.
	SYSC_RSTSR1_WDTRF_Msk = 0x2
	// Bit WDTRF.
	SYSC_RSTSR1_WDTRF = 0x2
	// Watchdog timer reset not detected
	SYSC_RSTSR1_WDTRF_0 = 0x0
	// Watchdog timer reset detected
	SYSC_RSTSR1_WDTRF_1 = 0x1
	// Position of SWRF field.
	SYSC_RSTSR1_SWRF_Pos = 0x2
	// Bit mask of SWRF field.
	SYSC_RSTSR1_SWRF_Msk = 0x4
	// Bit SWRF.
	SYSC_RSTSR1_SWRF = 0x4
	// Software reset not detected
	SYSC_RSTSR1_SWRF_0 = 0x0
	// Software reset detected
	SYSC_RSTSR1_SWRF_1 = 0x1
	// Position of RPERF field.
	SYSC_RSTSR1_RPERF_Pos = 0x8
	// Bit mask of RPERF field.
	SYSC_RSTSR1_RPERF_Msk = 0x100
	// Bit RPERF.
	SYSC_RSTSR1_RPERF = 0x100
	// SRAM parity error reset not detected
	SYSC_RSTSR1_RPERF_0 = 0x0
	// SRAM parity error reset detected
	SYSC_RSTSR1_RPERF_1 = 0x1
	// Position of REERF field.
	SYSC_RSTSR1_REERF_Pos = 0x9
	// Bit mask of REERF field.
	SYSC_RSTSR1_REERF_Msk = 0x200
	// Bit REERF.
	SYSC_RSTSR1_REERF = 0x200
	// SRAM ECC error reset not detected
	SYSC_RSTSR1_REERF_0 = 0x0
	// SRAM ECC error reset detected
	SYSC_RSTSR1_REERF_1 = 0x1
	// Position of BUSMRF field.
	SYSC_RSTSR1_BUSMRF_Pos = 0xb
	// Bit mask of BUSMRF field.
	SYSC_RSTSR1_BUSMRF_Msk = 0x800
	// Bit BUSMRF.
	SYSC_RSTSR1_BUSMRF = 0x800
	// Bus master MPU error reset not detected
	SYSC_RSTSR1_BUSMRF_0 = 0x0
	// Bus master MPU error reset detected
	SYSC_RSTSR1_BUSMRF_1 = 0x1
	// Position of TZERF field.
	SYSC_RSTSR1_TZERF_Pos = 0xd
	// Bit mask of TZERF field.
	SYSC_RSTSR1_TZERF_Msk = 0x2000
	// Bit TZERF.
	SYSC_RSTSR1_TZERF = 0x2000
	// TrustZone error reset not detected.
	SYSC_RSTSR1_TZERF_0 = 0x0
	// TrustZone error reset detected.
	SYSC_RSTSR1_TZERF_1 = 0x1
	// Position of CPERF field.
	SYSC_RSTSR1_CPERF_Pos = 0xf
	// Bit mask of CPERF field.
	SYSC_RSTSR1_CPERF_Msk = 0x8000
	// Bit CPERF.
	SYSC_RSTSR1_CPERF = 0x8000
	// Cache Parity error reset not detected.
	SYSC_RSTSR1_CPERF_0 = 0x0
	// Cache Parity error reset detected.
	SYSC_RSTSR1_CPERF_1 = 0x1

	// LVD1CR1: Voltage Monitor 1 Circuit Control Register
	// Position of IDTSEL field.
	SYSC_LVD1CR1_IDTSEL_Pos = 0x0
	// Bit mask of IDTSEL field.
	SYSC_LVD1CR1_IDTSEL_Msk = 0x3
	// When VCC >= Vdet1 (rise) is detected
	SYSC_LVD1CR1_IDTSEL_00 = 0x0
	// When VCC < Vdet1 (fall) is detected
	SYSC_LVD1CR1_IDTSEL_01 = 0x1
	// When fall and rise are detected
	SYSC_LVD1CR1_IDTSEL_10 = 0x2
	// Settings prohibited
	SYSC_LVD1CR1_IDTSEL_11 = 0x3
	// Position of IRQSEL field.
	SYSC_LVD1CR1_IRQSEL_Pos = 0x2
	// Bit mask of IRQSEL field.
	SYSC_LVD1CR1_IRQSEL_Msk = 0x4
	// Bit IRQSEL.
	SYSC_LVD1CR1_IRQSEL = 0x4
	// Non-maskable interrupt
	SYSC_LVD1CR1_IRQSEL_0 = 0x0
	// Maskable interrupt
	SYSC_LVD1CR1_IRQSEL_1 = 0x1

	// LVD1SR: Voltage Monitor 1 Circuit Status Register
	// Position of DET field.
	SYSC_LVD1SR_DET_Pos = 0x0
	// Bit mask of DET field.
	SYSC_LVD1SR_DET_Msk = 0x1
	// Bit DET.
	SYSC_LVD1SR_DET = 0x1
	// Not detected
	SYSC_LVD1SR_DET_0 = 0x0
	// Vdet1 crossing is detected
	SYSC_LVD1SR_DET_1 = 0x1
	// Position of MON field.
	SYSC_LVD1SR_MON_Pos = 0x1
	// Bit mask of MON field.
	SYSC_LVD1SR_MON_Msk = 0x2
	// Bit MON.
	SYSC_LVD1SR_MON = 0x2
	// VCC < Vdet1
	SYSC_LVD1SR_MON_0 = 0x0
	// VCC >= Vdet1 or MON is disabled
	SYSC_LVD1SR_MON_1 = 0x1

	// LVD2CR1: Voltage Monitor 2 Circuit Control Register 1
	// Position of IDTSEL field.
	SYSC_LVD2CR1_IDTSEL_Pos = 0x0
	// Bit mask of IDTSEL field.
	SYSC_LVD2CR1_IDTSEL_Msk = 0x3
	// When VCC>= Vdet2 (rise) is detected
	SYSC_LVD2CR1_IDTSEL_00 = 0x0
	// When VCC < Vdet2 (fall) is detected
	SYSC_LVD2CR1_IDTSEL_01 = 0x1
	// When fall and rise are detected
	SYSC_LVD2CR1_IDTSEL_10 = 0x2
	// Settings prohibited
	SYSC_LVD2CR1_IDTSEL_11 = 0x3
	// Position of IRQSEL field.
	SYSC_LVD2CR1_IRQSEL_Pos = 0x2
	// Bit mask of IRQSEL field.
	SYSC_LVD2CR1_IRQSEL_Msk = 0x4
	// Bit IRQSEL.
	SYSC_LVD2CR1_IRQSEL = 0x4
	// Non-maskable interrupt
	SYSC_LVD2CR1_IRQSEL_0 = 0x0
	// Maskable interrupt
	SYSC_LVD2CR1_IRQSEL_1 = 0x1

	// LVD2SR: Voltage Monitor 2 Circuit Status Register
	// Position of DET field.
	SYSC_LVD2SR_DET_Pos = 0x0
	// Bit mask of DET field.
	SYSC_LVD2SR_DET_Msk = 0x1
	// Bit DET.
	SYSC_LVD2SR_DET = 0x1
	// Not detected
	SYSC_LVD2SR_DET_0 = 0x0
	// Vdet2 crossing is detected
	SYSC_LVD2SR_DET_1 = 0x1
	// Position of MON field.
	SYSC_LVD2SR_MON_Pos = 0x1
	// Bit mask of MON field.
	SYSC_LVD2SR_MON_Msk = 0x2
	// Bit MON.
	SYSC_LVD2SR_MON = 0x2
	// VCC < Vdet2
	SYSC_LVD2SR_MON_0 = 0x0
	// VCC>= Vdet2 or MON is disabled
	SYSC_LVD2SR_MON_1 = 0x1

	// CGFSAR: Clock Generation Function Security Attribute Register
	// Position of NONSEC00 field.
	SYSC_CGFSAR_NONSEC00_Pos = 0x0
	// Bit mask of NONSEC00 field.
	SYSC_CGFSAR_NONSEC00_Msk = 0x1
	// Bit NONSEC00.
	SYSC_CGFSAR_NONSEC00 = 0x1
	// Secure
	SYSC_CGFSAR_NONSEC00_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC00_1 = 0x1
	// Position of NONSEC02 field.
	SYSC_CGFSAR_NONSEC02_Pos = 0x2
	// Bit mask of NONSEC02 field.
	SYSC_CGFSAR_NONSEC02_Msk = 0x4
	// Bit NONSEC02.
	SYSC_CGFSAR_NONSEC02 = 0x4
	// Secure
	SYSC_CGFSAR_NONSEC02_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC02_1 = 0x1
	// Position of NONSEC03 field.
	SYSC_CGFSAR_NONSEC03_Pos = 0x3
	// Bit mask of NONSEC03 field.
	SYSC_CGFSAR_NONSEC03_Msk = 0x8
	// Bit NONSEC03.
	SYSC_CGFSAR_NONSEC03 = 0x8
	// Secure
	SYSC_CGFSAR_NONSEC03_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC03_1 = 0x1
	// Position of NONSEC04 field.
	SYSC_CGFSAR_NONSEC04_Pos = 0x4
	// Bit mask of NONSEC04 field.
	SYSC_CGFSAR_NONSEC04_Msk = 0x10
	// Bit NONSEC04.
	SYSC_CGFSAR_NONSEC04 = 0x10
	// Secure
	SYSC_CGFSAR_NONSEC04_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC04_1 = 0x1
	// Position of NONSEC05 field.
	SYSC_CGFSAR_NONSEC05_Pos = 0x5
	// Bit mask of NONSEC05 field.
	SYSC_CGFSAR_NONSEC05_Msk = 0x20
	// Bit NONSEC05.
	SYSC_CGFSAR_NONSEC05 = 0x20
	// Secure
	SYSC_CGFSAR_NONSEC05_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC05_1 = 0x1
	// Position of NONSEC06 field.
	SYSC_CGFSAR_NONSEC06_Pos = 0x6
	// Bit mask of NONSEC06 field.
	SYSC_CGFSAR_NONSEC06_Msk = 0x40
	// Bit NONSEC06.
	SYSC_CGFSAR_NONSEC06 = 0x40
	// Secure
	SYSC_CGFSAR_NONSEC06_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC06_1 = 0x1
	// Position of NONSEC07 field.
	SYSC_CGFSAR_NONSEC07_Pos = 0x7
	// Bit mask of NONSEC07 field.
	SYSC_CGFSAR_NONSEC07_Msk = 0x80
	// Bit NONSEC07.
	SYSC_CGFSAR_NONSEC07 = 0x80
	// Secure
	SYSC_CGFSAR_NONSEC07_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC07_1 = 0x1
	// Position of NONSEC08 field.
	SYSC_CGFSAR_NONSEC08_Pos = 0x8
	// Bit mask of NONSEC08 field.
	SYSC_CGFSAR_NONSEC08_Msk = 0x100
	// Bit NONSEC08.
	SYSC_CGFSAR_NONSEC08 = 0x100
	// Secure
	SYSC_CGFSAR_NONSEC08_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC08_1 = 0x1
	// Position of NONSEC11 field.
	SYSC_CGFSAR_NONSEC11_Pos = 0xb
	// Bit mask of NONSEC11 field.
	SYSC_CGFSAR_NONSEC11_Msk = 0x800
	// Bit NONSEC11.
	SYSC_CGFSAR_NONSEC11 = 0x800
	// Secure
	SYSC_CGFSAR_NONSEC11_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC11_1 = 0x1
	// Position of NONSEC16 field.
	SYSC_CGFSAR_NONSEC16_Pos = 0x10
	// Bit mask of NONSEC16 field.
	SYSC_CGFSAR_NONSEC16_Msk = 0x10000
	// Bit NONSEC16.
	SYSC_CGFSAR_NONSEC16 = 0x10000
	// Secure
	SYSC_CGFSAR_NONSEC16_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC16_1 = 0x1
	// Position of NONSEC18 field.
	SYSC_CGFSAR_NONSEC18_Pos = 0x12
	// Bit mask of NONSEC18 field.
	SYSC_CGFSAR_NONSEC18_Msk = 0x40000
	// Bit NONSEC18.
	SYSC_CGFSAR_NONSEC18 = 0x40000
	// Secure
	SYSC_CGFSAR_NONSEC18_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC18_1 = 0x1
	// Position of NONSEC20 field.
	SYSC_CGFSAR_NONSEC20_Pos = 0x14
	// Bit mask of NONSEC20 field.
	SYSC_CGFSAR_NONSEC20_Msk = 0x100000
	// Bit NONSEC20.
	SYSC_CGFSAR_NONSEC20 = 0x100000
	// Secure
	SYSC_CGFSAR_NONSEC20_0 = 0x0
	// Non Secure
	SYSC_CGFSAR_NONSEC20_1 = 0x1

	// RSTSAR: Reset Security Attribution Register
	// Position of NONSEC0 field.
	SYSC_RSTSAR_NONSEC0_Pos = 0x0
	// Bit mask of NONSEC0 field.
	SYSC_RSTSAR_NONSEC0_Msk = 0x1
	// Bit NONSEC0.
	SYSC_RSTSAR_NONSEC0 = 0x1
	// Secure
	SYSC_RSTSAR_NONSEC0_0 = 0x0
	// Non Secure
	SYSC_RSTSAR_NONSEC0_1 = 0x1
	// Position of NONSEC1 field.
	SYSC_RSTSAR_NONSEC1_Pos = 0x1
	// Bit mask of NONSEC1 field.
	SYSC_RSTSAR_NONSEC1_Msk = 0x2
	// Bit NONSEC1.
	SYSC_RSTSAR_NONSEC1 = 0x2
	// Secure
	SYSC_RSTSAR_NONSEC1_0 = 0x0
	// Non Secure
	SYSC_RSTSAR_NONSEC1_1 = 0x1
	// Position of NONSEC2 field.
	SYSC_RSTSAR_NONSEC2_Pos = 0x2
	// Bit mask of NONSEC2 field.
	SYSC_RSTSAR_NONSEC2_Msk = 0x4
	// Bit NONSEC2.
	SYSC_RSTSAR_NONSEC2 = 0x4
	// Secure
	SYSC_RSTSAR_NONSEC2_0 = 0x0
	// Non Secure
	SYSC_RSTSAR_NONSEC2_1 = 0x1

	// LPMSAR: Low Power Mode Security Attribution Register
	// Position of NONSEC0 field.
	SYSC_LPMSAR_NONSEC0_Pos = 0x0
	// Bit mask of NONSEC0 field.
	SYSC_LPMSAR_NONSEC0_Msk = 0x1
	// Bit NONSEC0.
	SYSC_LPMSAR_NONSEC0 = 0x1
	// Secure
	SYSC_LPMSAR_NONSEC0_0 = 0x0
	// Non Secure
	SYSC_LPMSAR_NONSEC0_1 = 0x1
	// Position of NONSEC2 field.
	SYSC_LPMSAR_NONSEC2_Pos = 0x2
	// Bit mask of NONSEC2 field.
	SYSC_LPMSAR_NONSEC2_Msk = 0x4
	// Bit NONSEC2.
	SYSC_LPMSAR_NONSEC2 = 0x4
	// Secure
	SYSC_LPMSAR_NONSEC2_0 = 0x0
	// Non Secure
	SYSC_LPMSAR_NONSEC2_1 = 0x1
	// Position of NONSEC4 field.
	SYSC_LPMSAR_NONSEC4_Pos = 0x4
	// Bit mask of NONSEC4 field.
	SYSC_LPMSAR_NONSEC4_Msk = 0x10
	// Bit NONSEC4.
	SYSC_LPMSAR_NONSEC4 = 0x10
	// Secure
	SYSC_LPMSAR_NONSEC4_0 = 0x0
	// Non Secure
	SYSC_LPMSAR_NONSEC4_1 = 0x1
	// Position of NONSEC8 field.
	SYSC_LPMSAR_NONSEC8_Pos = 0x8
	// Bit mask of NONSEC8 field.
	SYSC_LPMSAR_NONSEC8_Msk = 0x100
	// Bit NONSEC8.
	SYSC_LPMSAR_NONSEC8 = 0x100
	// Secure
	SYSC_LPMSAR_NONSEC8_0 = 0x0
	// Non Secure
	SYSC_LPMSAR_NONSEC8_1 = 0x1
	// Position of NONSEC9 field.
	SYSC_LPMSAR_NONSEC9_Pos = 0x9
	// Bit mask of NONSEC9 field.
	SYSC_LPMSAR_NONSEC9_Msk = 0x200
	// Bit NONSEC9.
	SYSC_LPMSAR_NONSEC9 = 0x200
	// Secure
	SYSC_LPMSAR_NONSEC9_0 = 0x0
	// Non Secure
	SYSC_LPMSAR_NONSEC9_1 = 0x1

	// LVDSAR: Low Voltage Detection Security Attribution Register
	// Position of NONSEC0 field.
	SYSC_LVDSAR_NONSEC0_Pos = 0x0
	// Bit mask of NONSEC0 field.
	SYSC_LVDSAR_NONSEC0_Msk = 0x1
	// Bit NONSEC0.
	SYSC_LVDSAR_NONSEC0 = 0x1
	// Secure
	SYSC_LVDSAR_NONSEC0_0 = 0x0
	// Non Secure
	SYSC_LVDSAR_NONSEC0_1 = 0x1
	// Position of NONSEC1 field.
	SYSC_LVDSAR_NONSEC1_Pos = 0x1
	// Bit mask of NONSEC1 field.
	SYSC_LVDSAR_NONSEC1_Msk = 0x2
	// Bit NONSEC1.
	SYSC_LVDSAR_NONSEC1 = 0x2
	// Secure
	SYSC_LVDSAR_NONSEC1_0 = 0x0
	// Non Secure
	SYSC_LVDSAR_NONSEC1_1 = 0x1

	// DPFSAR: Deep Standby Interrupt Factor Security Attribution Register
	// Position of DPFSA0 field.
	SYSC_DPFSAR_DPFSA0_Pos = 0x0
	// Bit mask of DPFSA0 field.
	SYSC_DPFSAR_DPFSA0_Msk = 0x1
	// Bit DPFSA0.
	SYSC_DPFSAR_DPFSA0 = 0x1
	// Secure
	SYSC_DPFSAR_DPFSA0_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA0_1 = 0x1
	// Position of DPFSA1 field.
	SYSC_DPFSAR_DPFSA1_Pos = 0x1
	// Bit mask of DPFSA1 field.
	SYSC_DPFSAR_DPFSA1_Msk = 0x2
	// Bit DPFSA1.
	SYSC_DPFSAR_DPFSA1 = 0x2
	// Secure
	SYSC_DPFSAR_DPFSA1_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA1_1 = 0x1
	// Position of DPFSA04 field.
	SYSC_DPFSAR_DPFSA04_Pos = 0x4
	// Bit mask of DPFSA04 field.
	SYSC_DPFSAR_DPFSA04_Msk = 0x10
	// Bit DPFSA04.
	SYSC_DPFSAR_DPFSA04 = 0x10
	// Secure
	SYSC_DPFSAR_DPFSA04_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA04_1 = 0x1
	// Position of DPFSA05 field.
	SYSC_DPFSAR_DPFSA05_Pos = 0x5
	// Bit mask of DPFSA05 field.
	SYSC_DPFSAR_DPFSA05_Msk = 0x20
	// Bit DPFSA05.
	SYSC_DPFSAR_DPFSA05 = 0x20
	// Secure
	SYSC_DPFSAR_DPFSA05_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA05_1 = 0x1
	// Position of DPFSA06 field.
	SYSC_DPFSAR_DPFSA06_Pos = 0x6
	// Bit mask of DPFSA06 field.
	SYSC_DPFSAR_DPFSA06_Msk = 0x40
	// Bit DPFSA06.
	SYSC_DPFSAR_DPFSA06 = 0x40
	// Secure
	SYSC_DPFSAR_DPFSA06_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA06_1 = 0x1
	// Position of DPFSA07 field.
	SYSC_DPFSAR_DPFSA07_Pos = 0x7
	// Bit mask of DPFSA07 field.
	SYSC_DPFSAR_DPFSA07_Msk = 0x80
	// Bit DPFSA07.
	SYSC_DPFSAR_DPFSA07 = 0x80
	// Secure
	SYSC_DPFSAR_DPFSA07_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA07_1 = 0x1
	// Position of DPFSA08 field.
	SYSC_DPFSAR_DPFSA08_Pos = 0x8
	// Bit mask of DPFSA08 field.
	SYSC_DPFSAR_DPFSA08_Msk = 0x100
	// Bit DPFSA08.
	SYSC_DPFSAR_DPFSA08 = 0x100
	// Secure
	SYSC_DPFSAR_DPFSA08_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA08_1 = 0x1
	// Position of DPFSA09 field.
	SYSC_DPFSAR_DPFSA09_Pos = 0x9
	// Bit mask of DPFSA09 field.
	SYSC_DPFSAR_DPFSA09_Msk = 0x200
	// Bit DPFSA09.
	SYSC_DPFSAR_DPFSA09 = 0x200
	// Secure
	SYSC_DPFSAR_DPFSA09_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA09_1 = 0x1
	// Position of DPFSA10 field.
	SYSC_DPFSAR_DPFSA10_Pos = 0xa
	// Bit mask of DPFSA10 field.
	SYSC_DPFSAR_DPFSA10_Msk = 0x400
	// Bit DPFSA10.
	SYSC_DPFSAR_DPFSA10 = 0x400
	// Secure
	SYSC_DPFSAR_DPFSA10_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA10_1 = 0x1
	// Position of DPFSA11 field.
	SYSC_DPFSAR_DPFSA11_Pos = 0xb
	// Bit mask of DPFSA11 field.
	SYSC_DPFSAR_DPFSA11_Msk = 0x800
	// Bit DPFSA11.
	SYSC_DPFSAR_DPFSA11 = 0x800
	// Secure
	SYSC_DPFSAR_DPFSA11_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA11_1 = 0x1
	// Position of DPFSA12 field.
	SYSC_DPFSAR_DPFSA12_Pos = 0xc
	// Bit mask of DPFSA12 field.
	SYSC_DPFSAR_DPFSA12_Msk = 0x1000
	// Bit DPFSA12.
	SYSC_DPFSAR_DPFSA12 = 0x1000
	// Secure
	SYSC_DPFSAR_DPFSA12_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA12_1 = 0x1
	// Position of DPFSA14 field.
	SYSC_DPFSAR_DPFSA14_Pos = 0xe
	// Bit mask of DPFSA14 field.
	SYSC_DPFSAR_DPFSA14_Msk = 0x4000
	// Bit DPFSA14.
	SYSC_DPFSAR_DPFSA14 = 0x4000
	// Secure
	SYSC_DPFSAR_DPFSA14_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA14_1 = 0x1
	// Position of DPFSA16 field.
	SYSC_DPFSAR_DPFSA16_Pos = 0x10
	// Bit mask of DPFSA16 field.
	SYSC_DPFSAR_DPFSA16_Msk = 0x10000
	// Bit DPFSA16.
	SYSC_DPFSAR_DPFSA16 = 0x10000
	// Secure
	SYSC_DPFSAR_DPFSA16_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA16_1 = 0x1
	// Position of DPFSA17 field.
	SYSC_DPFSAR_DPFSA17_Pos = 0x11
	// Bit mask of DPFSA17 field.
	SYSC_DPFSAR_DPFSA17_Msk = 0x20000
	// Bit DPFSA17.
	SYSC_DPFSAR_DPFSA17 = 0x20000
	// Secure
	SYSC_DPFSAR_DPFSA17_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA17_1 = 0x1
	// Position of DPFSA18 field.
	SYSC_DPFSAR_DPFSA18_Pos = 0x12
	// Bit mask of DPFSA18 field.
	SYSC_DPFSAR_DPFSA18_Msk = 0x40000
	// Bit DPFSA18.
	SYSC_DPFSAR_DPFSA18 = 0x40000
	// Secure
	SYSC_DPFSAR_DPFSA18_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA18_1 = 0x1
	// Position of DPFSA19 field.
	SYSC_DPFSAR_DPFSA19_Pos = 0x13
	// Bit mask of DPFSA19 field.
	SYSC_DPFSAR_DPFSA19_Msk = 0x80000
	// Bit DPFSA19.
	SYSC_DPFSAR_DPFSA19 = 0x80000
	// Secure
	SYSC_DPFSAR_DPFSA19_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA19_1 = 0x1
	// Position of DPFSA20 field.
	SYSC_DPFSAR_DPFSA20_Pos = 0x14
	// Bit mask of DPFSA20 field.
	SYSC_DPFSAR_DPFSA20_Msk = 0x100000
	// Bit DPFSA20.
	SYSC_DPFSAR_DPFSA20 = 0x100000
	// Secure
	SYSC_DPFSAR_DPFSA20_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA20_1 = 0x1
	// Position of DPFSA24 field.
	SYSC_DPFSAR_DPFSA24_Pos = 0x18
	// Bit mask of DPFSA24 field.
	SYSC_DPFSAR_DPFSA24_Msk = 0x1000000
	// Bit DPFSA24.
	SYSC_DPFSAR_DPFSA24 = 0x1000000
	// Secure
	SYSC_DPFSAR_DPFSA24_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA24_1 = 0x1
	// Position of DPFSA26 field.
	SYSC_DPFSAR_DPFSA26_Pos = 0x1a
	// Bit mask of DPFSA26 field.
	SYSC_DPFSAR_DPFSA26_Msk = 0x4000000
	// Bit DPFSA26.
	SYSC_DPFSAR_DPFSA26 = 0x4000000
	// Secure
	SYSC_DPFSAR_DPFSA26_0 = 0x0
	// Non Secure
	SYSC_DPFSAR_DPFSA26_1 = 0x1

	// PRCR: Protect Register
	// Position of PRC0 field.
	SYSC_PRCR_PRC0_Pos = 0x0
	// Bit mask of PRC0 field.
	SYSC_PRCR_PRC0_Msk = 0x1
	// Bit PRC0.
	SYSC_PRCR_PRC0 = 0x1
	// Disable writes
	SYSC_PRCR_PRC0_0 = 0x0
	// Enable writes
	SYSC_PRCR_PRC0_1 = 0x1
	// Position of PRC1 field.
	SYSC_PRCR_PRC1_Pos = 0x1
	// Bit mask of PRC1 field.
	SYSC_PRCR_PRC1_Msk = 0x2
	// Bit PRC1.
	SYSC_PRCR_PRC1 = 0x2
	// Disable writes
	SYSC_PRCR_PRC1_0 = 0x0
	// Enable writes
	SYSC_PRCR_PRC1_1 = 0x1
	// Position of PRC3 field.
	SYSC_PRCR_PRC3_Pos = 0x3
	// Bit mask of PRC3 field.
	SYSC_PRCR_PRC3_Msk = 0x8
	// Bit PRC3.
	SYSC_PRCR_PRC3 = 0x8
	// Disable writes
	SYSC_PRCR_PRC3_0 = 0x0
	// Enable writes
	SYSC_PRCR_PRC3_1 = 0x1
	// Position of PRC4 field.
	SYSC_PRCR_PRC4_Pos = 0x4
	// Bit mask of PRC4 field.
	SYSC_PRCR_PRC4_Msk = 0x10
	// Bit PRC4.
	SYSC_PRCR_PRC4 = 0x10
	// Disable writes
	SYSC_PRCR_PRC4_0 = 0x0
	// Enable writes
	SYSC_PRCR_PRC4_1 = 0x1
	// Position of PRKEY field.
	SYSC_PRCR_PRKEY_Pos = 0x8
	// Bit mask of PRKEY field.
	SYSC_PRCR_PRKEY_Msk = 0xff00

	// DPSBYCR: Deep Standby Control Register
	// Position of DEEPCUT field.
	SYSC_DPSBYCR_DEEPCUT_Pos = 0x0
	// Bit mask of DEEPCUT field.
	SYSC_DPSBYCR_DEEPCUT_Msk = 0x3
	// Power to the standby RAM, Low-speed on-chip oscillator, AGTn (n = 0, 1), and USBFS resume detecting unit is supplied in Deep Software Standby mode.
	SYSC_DPSBYCR_DEEPCUT_00 = 0x0
	// Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode.
	SYSC_DPSBYCR_DEEPCUT_01 = 0x1
	// Setting prohibited
	SYSC_DPSBYCR_DEEPCUT_10 = 0x2
	// Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled.
	SYSC_DPSBYCR_DEEPCUT_11 = 0x3
	// Position of IOKEEP field.
	SYSC_DPSBYCR_IOKEEP_Pos = 0x6
	// Bit mask of IOKEEP field.
	SYSC_DPSBYCR_IOKEEP_Msk = 0x40
	// Bit IOKEEP.
	SYSC_DPSBYCR_IOKEEP = 0x40
	// When the Deep Software Standby mode is canceled, the I/O ports are in the reset state.
	SYSC_DPSBYCR_IOKEEP_0 = 0x0
	// When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode.
	SYSC_DPSBYCR_IOKEEP_1 = 0x1
	// Position of DPSBY field.
	SYSC_DPSBYCR_DPSBY_Pos = 0x7
	// Bit mask of DPSBY field.
	SYSC_DPSBYCR_DPSBY_Msk = 0x80
	// Bit DPSBY.
	SYSC_DPSBYCR_DPSBY = 0x80
	// Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)
	SYSC_DPSBYCR_DPSBY_0 = 0x0
	// Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)
	SYSC_DPSBYCR_DPSBY_1 = 0x1

	// DPSWCR: Deep Standby Wait Control Register
	// Position of WTSTS field.
	SYSC_DPSWCR_WTSTS_Pos = 0x0
	// Bit mask of WTSTS field.
	SYSC_DPSWCR_WTSTS_Msk = 0x3f
	// Setting prohibited
	SYSC_DPSWCR_WTSTS_Others = 0x0
	// Wait cycle for fast recovery
	SYSC_DPSWCR_WTSTS_0x0E = 0xe
	// Wait cycle for slow recovery
	SYSC_DPSWCR_WTSTS_0x19 = 0x19

	// DPSIER0: Deep Standby Interrupt Enable Register 0
	// Position of DIRQ0E field.
	SYSC_DPSIER0_DIRQ0E_Pos = 0x0
	// Bit mask of DIRQ0E field.
	SYSC_DPSIER0_DIRQ0E_Msk = 0x1
	// Bit DIRQ0E.
	SYSC_DPSIER0_DIRQ0E = 0x1
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER0_DIRQ0E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER0_DIRQ0E_1 = 0x1
	// Position of DIRQ1E field.
	SYSC_DPSIER0_DIRQ1E_Pos = 0x1
	// Bit mask of DIRQ1E field.
	SYSC_DPSIER0_DIRQ1E_Msk = 0x2
	// Bit DIRQ1E.
	SYSC_DPSIER0_DIRQ1E = 0x2
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER0_DIRQ1E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER0_DIRQ1E_1 = 0x1
	// Position of DIRQ4E field.
	SYSC_DPSIER0_DIRQ4E_Pos = 0x4
	// Bit mask of DIRQ4E field.
	SYSC_DPSIER0_DIRQ4E_Msk = 0x10
	// Bit DIRQ4E.
	SYSC_DPSIER0_DIRQ4E = 0x10
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER0_DIRQ4E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER0_DIRQ4E_1 = 0x1
	// Position of DIRQ5E field.
	SYSC_DPSIER0_DIRQ5E_Pos = 0x5
	// Bit mask of DIRQ5E field.
	SYSC_DPSIER0_DIRQ5E_Msk = 0x20
	// Bit DIRQ5E.
	SYSC_DPSIER0_DIRQ5E = 0x20
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER0_DIRQ5E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER0_DIRQ5E_1 = 0x1
	// Position of DIRQ6E field.
	SYSC_DPSIER0_DIRQ6E_Pos = 0x6
	// Bit mask of DIRQ6E field.
	SYSC_DPSIER0_DIRQ6E_Msk = 0x40
	// Bit DIRQ6E.
	SYSC_DPSIER0_DIRQ6E = 0x40
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER0_DIRQ6E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER0_DIRQ6E_1 = 0x1
	// Position of DIRQ7E field.
	SYSC_DPSIER0_DIRQ7E_Pos = 0x7
	// Bit mask of DIRQ7E field.
	SYSC_DPSIER0_DIRQ7E_Msk = 0x80
	// Bit DIRQ7E.
	SYSC_DPSIER0_DIRQ7E = 0x80
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER0_DIRQ7E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER0_DIRQ7E_1 = 0x1

	// DPSIER1: Deep Standby Interrupt Enable Register 1
	// Position of DIRQ8E field.
	SYSC_DPSIER1_DIRQ8E_Pos = 0x0
	// Bit mask of DIRQ8E field.
	SYSC_DPSIER1_DIRQ8E_Msk = 0x1
	// Bit DIRQ8E.
	SYSC_DPSIER1_DIRQ8E = 0x1
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER1_DIRQ8E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER1_DIRQ8E_1 = 0x1
	// Position of DIRQ9E field.
	SYSC_DPSIER1_DIRQ9E_Pos = 0x1
	// Bit mask of DIRQ9E field.
	SYSC_DPSIER1_DIRQ9E_Msk = 0x2
	// Bit DIRQ9E.
	SYSC_DPSIER1_DIRQ9E = 0x2
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER1_DIRQ9E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER1_DIRQ9E_1 = 0x1
	// Position of DIRQ10E field.
	SYSC_DPSIER1_DIRQ10E_Pos = 0x2
	// Bit mask of DIRQ10E field.
	SYSC_DPSIER1_DIRQ10E_Msk = 0x4
	// Bit DIRQ10E.
	SYSC_DPSIER1_DIRQ10E = 0x4
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER1_DIRQ10E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER1_DIRQ10E_1 = 0x1
	// Position of DIRQ11E field.
	SYSC_DPSIER1_DIRQ11E_Pos = 0x3
	// Bit mask of DIRQ11E field.
	SYSC_DPSIER1_DIRQ11E_Msk = 0x8
	// Bit DIRQ11E.
	SYSC_DPSIER1_DIRQ11E = 0x8
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER1_DIRQ11E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER1_DIRQ11E_1 = 0x1
	// Position of DIRQ12E field.
	SYSC_DPSIER1_DIRQ12E_Pos = 0x4
	// Bit mask of DIRQ12E field.
	SYSC_DPSIER1_DIRQ12E_Msk = 0x10
	// Bit DIRQ12E.
	SYSC_DPSIER1_DIRQ12E = 0x10
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER1_DIRQ12E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER1_DIRQ12E_1 = 0x1
	// Position of DIRQ14E field.
	SYSC_DPSIER1_DIRQ14E_Pos = 0x6
	// Bit mask of DIRQ14E field.
	SYSC_DPSIER1_DIRQ14E_Msk = 0x40
	// Bit DIRQ14E.
	SYSC_DPSIER1_DIRQ14E = 0x40
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER1_DIRQ14E_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER1_DIRQ14E_1 = 0x1

	// DPSIER2: Deep Software Standby Interrupt Enable Register 2
	// Position of DLVD1IE field.
	SYSC_DPSIER2_DLVD1IE_Pos = 0x0
	// Bit mask of DLVD1IE field.
	SYSC_DPSIER2_DLVD1IE_Msk = 0x1
	// Bit DLVD1IE.
	SYSC_DPSIER2_DLVD1IE = 0x1
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER2_DLVD1IE_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER2_DLVD1IE_1 = 0x1
	// Position of DLVD2IE field.
	SYSC_DPSIER2_DLVD2IE_Pos = 0x1
	// Bit mask of DLVD2IE field.
	SYSC_DPSIER2_DLVD2IE_Msk = 0x2
	// Bit DLVD2IE.
	SYSC_DPSIER2_DLVD2IE = 0x2
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER2_DLVD2IE_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER2_DLVD2IE_1 = 0x1
	// Position of DRTCIIE field.
	SYSC_DPSIER2_DRTCIIE_Pos = 0x2
	// Bit mask of DRTCIIE field.
	SYSC_DPSIER2_DRTCIIE_Msk = 0x4
	// Bit DRTCIIE.
	SYSC_DPSIER2_DRTCIIE = 0x4
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER2_DRTCIIE_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER2_DRTCIIE_1 = 0x1
	// Position of DRTCAIE field.
	SYSC_DPSIER2_DRTCAIE_Pos = 0x3
	// Bit mask of DRTCAIE field.
	SYSC_DPSIER2_DRTCAIE_Msk = 0x8
	// Bit DRTCAIE.
	SYSC_DPSIER2_DRTCAIE = 0x8
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER2_DRTCAIE_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER2_DRTCAIE_1 = 0x1
	// Position of DNMIE field.
	SYSC_DPSIER2_DNMIE_Pos = 0x4
	// Bit mask of DNMIE field.
	SYSC_DPSIER2_DNMIE_Msk = 0x10
	// Bit DNMIE.
	SYSC_DPSIER2_DNMIE = 0x10
	// Cancelling Deep Software Standby mode is disabled
	SYSC_DPSIER2_DNMIE_0 = 0x0
	// Cancelling Deep Software Standby mode is enabled
	SYSC_DPSIER2_DNMIE_1 = 0x1

	// DPSIER3: Deep Standby Interrupt Enable Register 3
	// Position of DUSBFS0IE field.
	SYSC_DPSIER3_DUSBFS0IE_Pos = 0x0
	// Bit mask of DUSBFS0IE field.
	SYSC_DPSIER3_DUSBFS0IE_Msk = 0x1
	// Bit DUSBFS0IE.
	SYSC_DPSIER3_DUSBFS0IE = 0x1
	// Cancelling deep standby mode is disabled
	SYSC_DPSIER3_DUSBFS0IE_0 = 0x0
	// Cancelling deep standby mode is enabled
	SYSC_DPSIER3_DUSBFS0IE_1 = 0x1
	// Position of DAGT1IE field.
	SYSC_DPSIER3_DAGT1IE_Pos = 0x2
	// Bit mask of DAGT1IE field.
	SYSC_DPSIER3_DAGT1IE_Msk = 0x4
	// Bit DAGT1IE.
	SYSC_DPSIER3_DAGT1IE = 0x4
	// Cancelling deep standby mode is disabled
	SYSC_DPSIER3_DAGT1IE_0 = 0x0
	// Cancelling deep standby mode is enabled
	SYSC_DPSIER3_DAGT1IE_1 = 0x1

	// DPSIFR0: Deep Standby Interrupt Flag Register 0
	// Position of DIRQ0F field.
	SYSC_DPSIFR0_DIRQ0F_Pos = 0x0
	// Bit mask of DIRQ0F field.
	SYSC_DPSIFR0_DIRQ0F_Msk = 0x1
	// Bit DIRQ0F.
	SYSC_DPSIFR0_DIRQ0F = 0x1
	// The cancel request is not generated
	SYSC_DPSIFR0_DIRQ0F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR0_DIRQ0F_1 = 0x1
	// Position of DIRQ1F field.
	SYSC_DPSIFR0_DIRQ1F_Pos = 0x1
	// Bit mask of DIRQ1F field.
	SYSC_DPSIFR0_DIRQ1F_Msk = 0x2
	// Bit DIRQ1F.
	SYSC_DPSIFR0_DIRQ1F = 0x2
	// The cancel request is not generated
	SYSC_DPSIFR0_DIRQ1F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR0_DIRQ1F_1 = 0x1
	// Position of DIRQ4F field.
	SYSC_DPSIFR0_DIRQ4F_Pos = 0x4
	// Bit mask of DIRQ4F field.
	SYSC_DPSIFR0_DIRQ4F_Msk = 0x10
	// Bit DIRQ4F.
	SYSC_DPSIFR0_DIRQ4F = 0x10
	// The cancel request is not generated
	SYSC_DPSIFR0_DIRQ4F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR0_DIRQ4F_1 = 0x1
	// Position of DIRQ5F field.
	SYSC_DPSIFR0_DIRQ5F_Pos = 0x5
	// Bit mask of DIRQ5F field.
	SYSC_DPSIFR0_DIRQ5F_Msk = 0x20
	// Bit DIRQ5F.
	SYSC_DPSIFR0_DIRQ5F = 0x20
	// The cancel request is not generated
	SYSC_DPSIFR0_DIRQ5F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR0_DIRQ5F_1 = 0x1
	// Position of DIRQ6F field.
	SYSC_DPSIFR0_DIRQ6F_Pos = 0x6
	// Bit mask of DIRQ6F field.
	SYSC_DPSIFR0_DIRQ6F_Msk = 0x40
	// Bit DIRQ6F.
	SYSC_DPSIFR0_DIRQ6F = 0x40
	// The cancel request is not generated
	SYSC_DPSIFR0_DIRQ6F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR0_DIRQ6F_1 = 0x1
	// Position of DIRQ7F field.
	SYSC_DPSIFR0_DIRQ7F_Pos = 0x7
	// Bit mask of DIRQ7F field.
	SYSC_DPSIFR0_DIRQ7F_Msk = 0x80
	// Bit DIRQ7F.
	SYSC_DPSIFR0_DIRQ7F = 0x80
	// The cancel request is not generated
	SYSC_DPSIFR0_DIRQ7F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR0_DIRQ7F_1 = 0x1

	// DPSIFR1: Deep Standby Interrupt Flag Register 1
	// Position of DIRQ8F field.
	SYSC_DPSIFR1_DIRQ8F_Pos = 0x0
	// Bit mask of DIRQ8F field.
	SYSC_DPSIFR1_DIRQ8F_Msk = 0x1
	// Bit DIRQ8F.
	SYSC_DPSIFR1_DIRQ8F = 0x1
	// The cancel request is not generated
	SYSC_DPSIFR1_DIRQ8F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR1_DIRQ8F_1 = 0x1
	// Position of DIRQ9F field.
	SYSC_DPSIFR1_DIRQ9F_Pos = 0x1
	// Bit mask of DIRQ9F field.
	SYSC_DPSIFR1_DIRQ9F_Msk = 0x2
	// Bit DIRQ9F.
	SYSC_DPSIFR1_DIRQ9F = 0x2
	// The cancel request is not generated
	SYSC_DPSIFR1_DIRQ9F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR1_DIRQ9F_1 = 0x1
	// Position of DIRQ10F field.
	SYSC_DPSIFR1_DIRQ10F_Pos = 0x2
	// Bit mask of DIRQ10F field.
	SYSC_DPSIFR1_DIRQ10F_Msk = 0x4
	// Bit DIRQ10F.
	SYSC_DPSIFR1_DIRQ10F = 0x4
	// The cancel request is not generated
	SYSC_DPSIFR1_DIRQ10F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR1_DIRQ10F_1 = 0x1
	// Position of DIRQ11F field.
	SYSC_DPSIFR1_DIRQ11F_Pos = 0x3
	// Bit mask of DIRQ11F field.
	SYSC_DPSIFR1_DIRQ11F_Msk = 0x8
	// Bit DIRQ11F.
	SYSC_DPSIFR1_DIRQ11F = 0x8
	// The cancel request is not generated
	SYSC_DPSIFR1_DIRQ11F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR1_DIRQ11F_1 = 0x1
	// Position of DIRQ12F field.
	SYSC_DPSIFR1_DIRQ12F_Pos = 0x4
	// Bit mask of DIRQ12F field.
	SYSC_DPSIFR1_DIRQ12F_Msk = 0x10
	// Bit DIRQ12F.
	SYSC_DPSIFR1_DIRQ12F = 0x10
	// The cancel request is not generated
	SYSC_DPSIFR1_DIRQ12F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR1_DIRQ12F_1 = 0x1
	// Position of DIRQ14F field.
	SYSC_DPSIFR1_DIRQ14F_Pos = 0x6
	// Bit mask of DIRQ14F field.
	SYSC_DPSIFR1_DIRQ14F_Msk = 0x40
	// Bit DIRQ14F.
	SYSC_DPSIFR1_DIRQ14F = 0x40
	// The cancel request is not generated
	SYSC_DPSIFR1_DIRQ14F_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR1_DIRQ14F_1 = 0x1

	// DPSIFR2: Deep Software Standby Interrupt Flag Register 2
	// Position of DLVD1IF field.
	SYSC_DPSIFR2_DLVD1IF_Pos = 0x0
	// Bit mask of DLVD1IF field.
	SYSC_DPSIFR2_DLVD1IF_Msk = 0x1
	// Bit DLVD1IF.
	SYSC_DPSIFR2_DLVD1IF = 0x1
	// The cancel request is not generated
	SYSC_DPSIFR2_DLVD1IF_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR2_DLVD1IF_1 = 0x1
	// Position of DLVD2IF field.
	SYSC_DPSIFR2_DLVD2IF_Pos = 0x1
	// Bit mask of DLVD2IF field.
	SYSC_DPSIFR2_DLVD2IF_Msk = 0x2
	// Bit DLVD2IF.
	SYSC_DPSIFR2_DLVD2IF = 0x2
	// The cancel request is not generated
	SYSC_DPSIFR2_DLVD2IF_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR2_DLVD2IF_1 = 0x1
	// Position of DRTCIIF field.
	SYSC_DPSIFR2_DRTCIIF_Pos = 0x2
	// Bit mask of DRTCIIF field.
	SYSC_DPSIFR2_DRTCIIF_Msk = 0x4
	// Bit DRTCIIF.
	SYSC_DPSIFR2_DRTCIIF = 0x4
	// The cancel request is not generated
	SYSC_DPSIFR2_DRTCIIF_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR2_DRTCIIF_1 = 0x1
	// Position of DRTCAIF field.
	SYSC_DPSIFR2_DRTCAIF_Pos = 0x3
	// Bit mask of DRTCAIF field.
	SYSC_DPSIFR2_DRTCAIF_Msk = 0x8
	// Bit DRTCAIF.
	SYSC_DPSIFR2_DRTCAIF = 0x8
	// The cancel request is not generated
	SYSC_DPSIFR2_DRTCAIF_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR2_DRTCAIF_1 = 0x1
	// Position of DNMIF field.
	SYSC_DPSIFR2_DNMIF_Pos = 0x4
	// Bit mask of DNMIF field.
	SYSC_DPSIFR2_DNMIF_Msk = 0x10
	// Bit DNMIF.
	SYSC_DPSIFR2_DNMIF = 0x10
	// The cancel request is not generated
	SYSC_DPSIFR2_DNMIF_0 = 0x0
	// The cancel request is generated
	SYSC_DPSIFR2_DNMIF_1 = 0x1

	// DPSIFR3: Deep Standby Interrupt Flag Register 3
	// Position of DUSBFS0IF field.
	SYSC_DPSIFR3_DUSBFS0IF_Pos = 0x0
	// Bit mask of DUSBFS0IF field.
	SYSC_DPSIFR3_DUSBFS0IF_Msk = 0x1
	// Bit DUSBFS0IF.
	SYSC_DPSIFR3_DUSBFS0IF = 0x1
	// The cancel request is not generated.
	SYSC_DPSIFR3_DUSBFS0IF_0 = 0x0
	// The cancel request is generated.
	SYSC_DPSIFR3_DUSBFS0IF_1 = 0x1
	// Position of DAGT1IF field.
	SYSC_DPSIFR3_DAGT1IF_Pos = 0x2
	// Bit mask of DAGT1IF field.
	SYSC_DPSIFR3_DAGT1IF_Msk = 0x4
	// Bit DAGT1IF.
	SYSC_DPSIFR3_DAGT1IF = 0x4
	// The cancel request is not generated.
	SYSC_DPSIFR3_DAGT1IF_0 = 0x0
	// The cancel request is generated.
	SYSC_DPSIFR3_DAGT1IF_1 = 0x1

	// DPSIEGR0: Deep Standby Interrupt Edge Register 0
	// Position of DIRQ0EG field.
	SYSC_DPSIEGR0_DIRQ0EG_Pos = 0x0
	// Bit mask of DIRQ0EG field.
	SYSC_DPSIEGR0_DIRQ0EG_Msk = 0x1
	// Bit DIRQ0EG.
	SYSC_DPSIEGR0_DIRQ0EG = 0x1
	// A cancel request is generated at a falling edge
	SYSC_DPSIEGR0_DIRQ0EG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR0_DIRQ0EG_1 = 0x1
	// Position of DIRQ1EG field.
	SYSC_DPSIEGR0_DIRQ1EG_Pos = 0x1
	// Bit mask of DIRQ1EG field.
	SYSC_DPSIEGR0_DIRQ1EG_Msk = 0x2
	// Bit DIRQ1EG.
	SYSC_DPSIEGR0_DIRQ1EG = 0x2
	// A cancel request is generated at a falling edge
	SYSC_DPSIEGR0_DIRQ1EG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR0_DIRQ1EG_1 = 0x1
	// Position of DIRQ4EG field.
	SYSC_DPSIEGR0_DIRQ4EG_Pos = 0x4
	// Bit mask of DIRQ4EG field.
	SYSC_DPSIEGR0_DIRQ4EG_Msk = 0x10
	// Bit DIRQ4EG.
	SYSC_DPSIEGR0_DIRQ4EG = 0x10
	// A cancel request is generated at a falling edge
	SYSC_DPSIEGR0_DIRQ4EG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR0_DIRQ4EG_1 = 0x1
	// Position of DIRQ5EG field.
	SYSC_DPSIEGR0_DIRQ5EG_Pos = 0x5
	// Bit mask of DIRQ5EG field.
	SYSC_DPSIEGR0_DIRQ5EG_Msk = 0x20
	// Bit DIRQ5EG.
	SYSC_DPSIEGR0_DIRQ5EG = 0x20
	// A cancel request is generated at a falling edge
	SYSC_DPSIEGR0_DIRQ5EG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR0_DIRQ5EG_1 = 0x1
	// Position of DIRQ6EG field.
	SYSC_DPSIEGR0_DIRQ6EG_Pos = 0x6
	// Bit mask of DIRQ6EG field.
	SYSC_DPSIEGR0_DIRQ6EG_Msk = 0x40
	// Bit DIRQ6EG.
	SYSC_DPSIEGR0_DIRQ6EG = 0x40
	// A cancel request is generated at a falling edge
	SYSC_DPSIEGR0_DIRQ6EG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR0_DIRQ6EG_1 = 0x1
	// Position of DIRQ7EG field.
	SYSC_DPSIEGR0_DIRQ7EG_Pos = 0x7
	// Bit mask of DIRQ7EG field.
	SYSC_DPSIEGR0_DIRQ7EG_Msk = 0x80
	// Bit DIRQ7EG.
	SYSC_DPSIEGR0_DIRQ7EG = 0x80
	// A cancel request is generated at a falling edge
	SYSC_DPSIEGR0_DIRQ7EG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR0_DIRQ7EG_1 = 0x1

	// DPSIEGR1: Deep Standby Interrupt Edge Register 1
	// Position of DIRQ8EG field.
	SYSC_DPSIEGR1_DIRQ8EG_Pos = 0x0
	// Bit mask of DIRQ8EG field.
	SYSC_DPSIEGR1_DIRQ8EG_Msk = 0x1
	// Bit DIRQ8EG.
	SYSC_DPSIEGR1_DIRQ8EG = 0x1
	// A cancel request is generated at a falling edge.
	SYSC_DPSIEGR1_DIRQ8EG_0 = 0x0
	// A cancel request is generated at a rising edge.
	SYSC_DPSIEGR1_DIRQ8EG_1 = 0x1
	// Position of DIRQ9EG field.
	SYSC_DPSIEGR1_DIRQ9EG_Pos = 0x1
	// Bit mask of DIRQ9EG field.
	SYSC_DPSIEGR1_DIRQ9EG_Msk = 0x2
	// Bit DIRQ9EG.
	SYSC_DPSIEGR1_DIRQ9EG = 0x2
	// A cancel request is generated at a falling edge.
	SYSC_DPSIEGR1_DIRQ9EG_0 = 0x0
	// A cancel request is generated at a rising edge.
	SYSC_DPSIEGR1_DIRQ9EG_1 = 0x1
	// Position of DIRQ10EG field.
	SYSC_DPSIEGR1_DIRQ10EG_Pos = 0x2
	// Bit mask of DIRQ10EG field.
	SYSC_DPSIEGR1_DIRQ10EG_Msk = 0x4
	// Bit DIRQ10EG.
	SYSC_DPSIEGR1_DIRQ10EG = 0x4
	// A cancel request is generated at a falling edge.
	SYSC_DPSIEGR1_DIRQ10EG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR1_DIRQ10EG_1 = 0x1
	// Position of DIRQ11EG field.
	SYSC_DPSIEGR1_DIRQ11EG_Pos = 0x3
	// Bit mask of DIRQ11EG field.
	SYSC_DPSIEGR1_DIRQ11EG_Msk = 0x8
	// Bit DIRQ11EG.
	SYSC_DPSIEGR1_DIRQ11EG = 0x8
	// A cancel request is generated at a falling edge.
	SYSC_DPSIEGR1_DIRQ11EG_0 = 0x0
	// A cancel request is generated at a rising edge.
	SYSC_DPSIEGR1_DIRQ11EG_1 = 0x1
	// Position of DIRQ12EG field.
	SYSC_DPSIEGR1_DIRQ12EG_Pos = 0x4
	// Bit mask of DIRQ12EG field.
	SYSC_DPSIEGR1_DIRQ12EG_Msk = 0x10
	// Bit DIRQ12EG.
	SYSC_DPSIEGR1_DIRQ12EG = 0x10
	// A cancel request is generated at a falling edge.
	SYSC_DPSIEGR1_DIRQ12EG_0 = 0x0
	// A cancel request is generated at a rising edge.
	SYSC_DPSIEGR1_DIRQ12EG_1 = 0x1
	// Position of DIRQ14EG field.
	SYSC_DPSIEGR1_DIRQ14EG_Pos = 0x6
	// Bit mask of DIRQ14EG field.
	SYSC_DPSIEGR1_DIRQ14EG_Msk = 0x40
	// Bit DIRQ14EG.
	SYSC_DPSIEGR1_DIRQ14EG = 0x40
	// A cancel request is generated at a falling edge.
	SYSC_DPSIEGR1_DIRQ14EG_0 = 0x0
	// A cancel request is generated at a rising edge.
	SYSC_DPSIEGR1_DIRQ14EG_1 = 0x1

	// DPSIEGR2: Deep Software Standby Interrupt Edge Register 2
	// Position of DLVD1EG field.
	SYSC_DPSIEGR2_DLVD1EG_Pos = 0x0
	// Bit mask of DLVD1EG field.
	SYSC_DPSIEGR2_DLVD1EG_Msk = 0x1
	// Bit DLVD1EG.
	SYSC_DPSIEGR2_DLVD1EG = 0x1
	// A cancel request is generated when VCC < Vdet1 (fall) is detected
	SYSC_DPSIEGR2_DLVD1EG_0 = 0x0
	// A cancel request is generated when VCC ≥ Vdet1 (rise) is detected
	SYSC_DPSIEGR2_DLVD1EG_1 = 0x1
	// Position of DLVD2EG field.
	SYSC_DPSIEGR2_DLVD2EG_Pos = 0x1
	// Bit mask of DLVD2EG field.
	SYSC_DPSIEGR2_DLVD2EG_Msk = 0x2
	// Bit DLVD2EG.
	SYSC_DPSIEGR2_DLVD2EG = 0x2
	// A cancel request is generated when VCC < Vdet2 (fall) is detected
	SYSC_DPSIEGR2_DLVD2EG_0 = 0x0
	// A cancel request is generated when VCC ≥ Vdet2 (rise) is detected
	SYSC_DPSIEGR2_DLVD2EG_1 = 0x1
	// Position of DNMIEG field.
	SYSC_DPSIEGR2_DNMIEG_Pos = 0x4
	// Bit mask of DNMIEG field.
	SYSC_DPSIEGR2_DNMIEG_Msk = 0x10
	// Bit DNMIEG.
	SYSC_DPSIEGR2_DNMIEG = 0x10
	// A cancel request is generated at a falling edge
	SYSC_DPSIEGR2_DNMIEG_0 = 0x0
	// A cancel request is generated at a rising edge
	SYSC_DPSIEGR2_DNMIEG_1 = 0x1

	// SYOCDCR: System Control OCD Control Register
	// Position of DOCDF field.
	SYSC_SYOCDCR_DOCDF_Pos = 0x0
	// Bit mask of DOCDF field.
	SYSC_SYOCDCR_DOCDF_Msk = 0x1
	// Bit DOCDF.
	SYSC_SYOCDCR_DOCDF = 0x1
	// DBIRQ is not generated
	SYSC_SYOCDCR_DOCDF_0 = 0x0
	// DBIRQ is generated
	SYSC_SYOCDCR_DOCDF_1 = 0x1
	// Position of DBGEN field.
	SYSC_SYOCDCR_DBGEN_Pos = 0x7
	// Bit mask of DBGEN field.
	SYSC_SYOCDCR_DBGEN_Msk = 0x80
	// Bit DBGEN.
	SYSC_SYOCDCR_DBGEN = 0x80
	// On-chip debugger is disabled
	SYSC_SYOCDCR_DBGEN_0 = 0x0
	// On-chip debugger is enabled
	SYSC_SYOCDCR_DBGEN_1 = 0x1

	// RSTSR0: Reset Status Register 0
	// Position of PORF field.
	SYSC_RSTSR0_PORF_Pos = 0x0
	// Bit mask of PORF field.
	SYSC_RSTSR0_PORF_Msk = 0x1
	// Bit PORF.
	SYSC_RSTSR0_PORF = 0x1
	// Power-on reset not detected
	SYSC_RSTSR0_PORF_0 = 0x0
	// Power-on reset detected
	SYSC_RSTSR0_PORF_1 = 0x1
	// Position of LVD0RF field.
	SYSC_RSTSR0_LVD0RF_Pos = 0x1
	// Bit mask of LVD0RF field.
	SYSC_RSTSR0_LVD0RF_Msk = 0x2
	// Bit LVD0RF.
	SYSC_RSTSR0_LVD0RF = 0x2
	// Voltage monitor 0 reset not detected
	SYSC_RSTSR0_LVD0RF_0 = 0x0
	// Voltage monitor 0 reset detected
	SYSC_RSTSR0_LVD0RF_1 = 0x1
	// Position of LVD1RF field.
	SYSC_RSTSR0_LVD1RF_Pos = 0x2
	// Bit mask of LVD1RF field.
	SYSC_RSTSR0_LVD1RF_Msk = 0x4
	// Bit LVD1RF.
	SYSC_RSTSR0_LVD1RF = 0x4
	// Voltage monitor 1 reset not detected
	SYSC_RSTSR0_LVD1RF_0 = 0x0
	// Voltage monitor 1 reset detected
	SYSC_RSTSR0_LVD1RF_1 = 0x1
	// Position of LVD2RF field.
	SYSC_RSTSR0_LVD2RF_Pos = 0x3
	// Bit mask of LVD2RF field.
	SYSC_RSTSR0_LVD2RF_Msk = 0x8
	// Bit LVD2RF.
	SYSC_RSTSR0_LVD2RF = 0x8
	// Voltage monitor 2 reset not detected
	SYSC_RSTSR0_LVD2RF_0 = 0x0
	// Voltage monitor 2 reset detected
	SYSC_RSTSR0_LVD2RF_1 = 0x1
	// Position of DPSRSTF field.
	SYSC_RSTSR0_DPSRSTF_Pos = 0x7
	// Bit mask of DPSRSTF field.
	SYSC_RSTSR0_DPSRSTF_Msk = 0x80
	// Bit DPSRSTF.
	SYSC_RSTSR0_DPSRSTF = 0x80
	// Deep software standby mode cancellation not requested by an interrupt.
	SYSC_RSTSR0_DPSRSTF_0 = 0x0
	// Deep software standby mode cancellation requested by an interrupt.
	SYSC_RSTSR0_DPSRSTF_1 = 0x1

	// RSTSR2: Reset Status Register 2
	// Position of CWSF field.
	SYSC_RSTSR2_CWSF_Pos = 0x0
	// Bit mask of CWSF field.
	SYSC_RSTSR2_CWSF_Msk = 0x1
	// Bit CWSF.
	SYSC_RSTSR2_CWSF = 0x1
	// Cold start
	SYSC_RSTSR2_CWSF_0 = 0x0
	// Warm start
	SYSC_RSTSR2_CWSF_1 = 0x1

	// MOMCR: Main Clock Oscillator Mode Oscillation Control Register
	// Position of MODRV field.
	SYSC_MOMCR_MODRV_Pos = 0x4
	// Bit mask of MODRV field.
	SYSC_MOMCR_MODRV_Msk = 0x30
	// 20 MHz to 24 MHz
	SYSC_MOMCR_MODRV_00 = 0x0
	// 16 MHz to 20 MHz
	SYSC_MOMCR_MODRV_01 = 0x1
	// 8 MHz to 16 MHz
	SYSC_MOMCR_MODRV_10 = 0x2
	// 8 MHz
	SYSC_MOMCR_MODRV_11 = 0x3
	// Position of MOSEL field.
	SYSC_MOMCR_MOSEL_Pos = 0x6
	// Bit mask of MOSEL field.
	SYSC_MOMCR_MOSEL_Msk = 0x40
	// Bit MOSEL.
	SYSC_MOMCR_MOSEL = 0x40
	// Resonator
	SYSC_MOMCR_MOSEL_0 = 0x0
	// External clock input
	SYSC_MOMCR_MOSEL_1 = 0x1

	// FWEPROR: Flash P/E Protect Register
	// Position of FLWE field.
	SYSC_FWEPROR_FLWE_Pos = 0x0
	// Bit mask of FLWE field.
	SYSC_FWEPROR_FLWE_Msk = 0x3
	// Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
	SYSC_FWEPROR_FLWE_00 = 0x0
	// Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
	SYSC_FWEPROR_FLWE_01 = 0x1
	// Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
	SYSC_FWEPROR_FLWE_10 = 0x2
	// Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing.
	SYSC_FWEPROR_FLWE_11 = 0x3

	// LVD1CMPCR: Voltage Monitoring 1 Comparator Control Register
	// Position of LVD1LVL field.
	SYSC_LVD1CMPCR_LVD1LVL_Pos = 0x0
	// Bit mask of LVD1LVL field.
	SYSC_LVD1CMPCR_LVD1LVL_Msk = 0x1f
	// Setting prohibited
	SYSC_LVD1CMPCR_LVD1LVL_Others = 0x0
	// 2.99 V (Vdet1_1)
	SYSC_LVD1CMPCR_LVD1LVL_0x11 = 0x11
	// 2.92 V (Vdet1_2)
	SYSC_LVD1CMPCR_LVD1LVL_0x12 = 0x12
	// 2.85 V (Vdet1_3)
	SYSC_LVD1CMPCR_LVD1LVL_0x13 = 0x13
	// Position of LVD1E field.
	SYSC_LVD1CMPCR_LVD1E_Pos = 0x7
	// Bit mask of LVD1E field.
	SYSC_LVD1CMPCR_LVD1E_Msk = 0x80
	// Bit LVD1E.
	SYSC_LVD1CMPCR_LVD1E = 0x80
	// Voltage detection 1 circuit disabled
	SYSC_LVD1CMPCR_LVD1E_0 = 0x0
	// Voltage detection 1 circuit enabled
	SYSC_LVD1CMPCR_LVD1E_1 = 0x1

	// LVD2CMPCR: Voltage Monitoring 2 Comparator Control Register
	// Position of LVD2LVL field.
	SYSC_LVD2CMPCR_LVD2LVL_Pos = 0x0
	// Bit mask of LVD2LVL field.
	SYSC_LVD2CMPCR_LVD2LVL_Msk = 0x7
	// Setting prohibited
	SYSC_LVD2CMPCR_LVD2LVL_Others = 0x0
	// 2.99 V (Vdet2_1)
	SYSC_LVD2CMPCR_LVD2LVL_101 = 0x5
	// 2.92 V (Vdet2_2)
	SYSC_LVD2CMPCR_LVD2LVL_110 = 0x6
	// 2.85 V (Vdet2_3)
	SYSC_LVD2CMPCR_LVD2LVL_111 = 0x7
	// Position of LVD2E field.
	SYSC_LVD2CMPCR_LVD2E_Pos = 0x7
	// Bit mask of LVD2E field.
	SYSC_LVD2CMPCR_LVD2E_Msk = 0x80
	// Bit LVD2E.
	SYSC_LVD2CMPCR_LVD2E = 0x80
	// Voltage detection 2 circuit disabled
	SYSC_LVD2CMPCR_LVD2E_0 = 0x0
	// Voltage detection 2 circuit enabled
	SYSC_LVD2CMPCR_LVD2E_1 = 0x1

	// LVD1CR0: Voltage Monitor 1 Circuit Control Register 0
	// Position of RIE field.
	SYSC_LVD1CR0_RIE_Pos = 0x0
	// Bit mask of RIE field.
	SYSC_LVD1CR0_RIE_Msk = 0x1
	// Bit RIE.
	SYSC_LVD1CR0_RIE = 0x1
	// Disable
	SYSC_LVD1CR0_RIE_0 = 0x0
	// Enable
	SYSC_LVD1CR0_RIE_1 = 0x1
	// Position of DFDIS field.
	SYSC_LVD1CR0_DFDIS_Pos = 0x1
	// Bit mask of DFDIS field.
	SYSC_LVD1CR0_DFDIS_Msk = 0x2
	// Bit DFDIS.
	SYSC_LVD1CR0_DFDIS = 0x2
	// Enable the digital filter
	SYSC_LVD1CR0_DFDIS_0 = 0x0
	// Disable the digital filter
	SYSC_LVD1CR0_DFDIS_1 = 0x1
	// Position of CMPE field.
	SYSC_LVD1CR0_CMPE_Pos = 0x2
	// Bit mask of CMPE field.
	SYSC_LVD1CR0_CMPE_Msk = 0x4
	// Bit CMPE.
	SYSC_LVD1CR0_CMPE = 0x4
	// Disable voltage monitor 1 circuit comparison result output
	SYSC_LVD1CR0_CMPE_0 = 0x0
	// Enable voltage monitor 1 circuit comparison result output
	SYSC_LVD1CR0_CMPE_1 = 0x1
	// Position of FSAMP field.
	SYSC_LVD1CR0_FSAMP_Pos = 0x4
	// Bit mask of FSAMP field.
	SYSC_LVD1CR0_FSAMP_Msk = 0x30
	// 1/2 LOCO frequency
	SYSC_LVD1CR0_FSAMP_00 = 0x0
	// 1/4 LOCO frequency
	SYSC_LVD1CR0_FSAMP_01 = 0x1
	// 1/8 LOCO frequency
	SYSC_LVD1CR0_FSAMP_10 = 0x2
	// 1/16 LOCO frequency
	SYSC_LVD1CR0_FSAMP_11 = 0x3
	// Position of RI field.
	SYSC_LVD1CR0_RI_Pos = 0x6
	// Bit mask of RI field.
	SYSC_LVD1CR0_RI_Msk = 0x40
	// Bit RI.
	SYSC_LVD1CR0_RI = 0x40
	// Generate voltage monitor 1 interrupt on Vdet1 crossing
	SYSC_LVD1CR0_RI_0 = 0x0
	// Enable voltage monitor 1 reset when the voltage falls to and below Vdet1
	SYSC_LVD1CR0_RI_1 = 0x1
	// Position of RN field.
	SYSC_LVD1CR0_RN_Pos = 0x7
	// Bit mask of RN field.
	SYSC_LVD1CR0_RN_Msk = 0x80
	// Bit RN.
	SYSC_LVD1CR0_RN = 0x80
	// Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected
	SYSC_LVD1CR0_RN_0 = 0x0
	// Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset
	SYSC_LVD1CR0_RN_1 = 0x1

	// LVD2CR0: Voltage Monitor 2 Circuit Control Register 0
	// Position of RIE field.
	SYSC_LVD2CR0_RIE_Pos = 0x0
	// Bit mask of RIE field.
	SYSC_LVD2CR0_RIE_Msk = 0x1
	// Bit RIE.
	SYSC_LVD2CR0_RIE = 0x1
	// Disable
	SYSC_LVD2CR0_RIE_0 = 0x0
	// Enable
	SYSC_LVD2CR0_RIE_1 = 0x1
	// Position of DFDIS field.
	SYSC_LVD2CR0_DFDIS_Pos = 0x1
	// Bit mask of DFDIS field.
	SYSC_LVD2CR0_DFDIS_Msk = 0x2
	// Bit DFDIS.
	SYSC_LVD2CR0_DFDIS = 0x2
	// Enable the digital filter
	SYSC_LVD2CR0_DFDIS_0 = 0x0
	// Disable the digital filter
	SYSC_LVD2CR0_DFDIS_1 = 0x1
	// Position of CMPE field.
	SYSC_LVD2CR0_CMPE_Pos = 0x2
	// Bit mask of CMPE field.
	SYSC_LVD2CR0_CMPE_Msk = 0x4
	// Bit CMPE.
	SYSC_LVD2CR0_CMPE = 0x4
	// Disable voltage monitor 2 circuit comparison result output
	SYSC_LVD2CR0_CMPE_0 = 0x0
	// Enable voltage monitor 2 circuit comparison result output
	SYSC_LVD2CR0_CMPE_1 = 0x1
	// Position of FSAMP field.
	SYSC_LVD2CR0_FSAMP_Pos = 0x4
	// Bit mask of FSAMP field.
	SYSC_LVD2CR0_FSAMP_Msk = 0x30
	// 1/2 LOCO frequency
	SYSC_LVD2CR0_FSAMP_00 = 0x0
	// 1/4 LOCO frequency
	SYSC_LVD2CR0_FSAMP_01 = 0x1
	// 1/8 LOCO frequency
	SYSC_LVD2CR0_FSAMP_10 = 0x2
	// 1/16 LOCO frequency
	SYSC_LVD2CR0_FSAMP_11 = 0x3
	// Position of RI field.
	SYSC_LVD2CR0_RI_Pos = 0x6
	// Bit mask of RI field.
	SYSC_LVD2CR0_RI_Msk = 0x40
	// Bit RI.
	SYSC_LVD2CR0_RI = 0x40
	// Generate voltage monitor 2 interrupt on Vdet2 crossing
	SYSC_LVD2CR0_RI_0 = 0x0
	// Enable voltage monitor 2 reset when the voltage falls to and below Vdet2
	SYSC_LVD2CR0_RI_1 = 0x1
	// Position of RN field.
	SYSC_LVD2CR0_RN_Pos = 0x7
	// Bit mask of RN field.
	SYSC_LVD2CR0_RN_Msk = 0x80
	// Bit RN.
	SYSC_LVD2CR0_RN = 0x80
	// Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected
	SYSC_LVD2CR0_RN_0 = 0x0
	// Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset
	SYSC_LVD2CR0_RN_1 = 0x1

	// SOSCCR: Sub-Clock Oscillator Control Register
	// Position of SOSTP field.
	SYSC_SOSCCR_SOSTP_Pos = 0x0
	// Bit mask of SOSTP field.
	SYSC_SOSCCR_SOSTP_Msk = 0x1
	// Bit SOSTP.
	SYSC_SOSCCR_SOSTP = 0x1
	// Operate the sub-clock oscillator
	SYSC_SOSCCR_SOSTP_0 = 0x0
	// Stop the sub-clock oscillator
	SYSC_SOSCCR_SOSTP_1 = 0x1

	// SOMCR: Sub-Clock Oscillator Mode Control Register
	// Position of SODRV field.
	SYSC_SOMCR_SODRV_Pos = 0x1
	// Bit mask of SODRV field.
	SYSC_SOMCR_SODRV_Msk = 0x2
	// Bit SODRV.
	SYSC_SOMCR_SODRV = 0x2
	// Standard
	SYSC_SOMCR_SODRV_0 = 0x0
	// Low
	SYSC_SOMCR_SODRV_1 = 0x1

	// LOCOCR: Low-Speed On-Chip Oscillator Control Register
	// Position of LCSTP field.
	SYSC_LOCOCR_LCSTP_Pos = 0x0
	// Bit mask of LCSTP field.
	SYSC_LOCOCR_LCSTP_Msk = 0x1
	// Bit LCSTP.
	SYSC_LOCOCR_LCSTP = 0x1
	// Operate the LOCO clock
	SYSC_LOCOCR_LCSTP_0 = 0x0
	// Stop the LOCO clock
	SYSC_LOCOCR_LCSTP_1 = 0x1

	// LOCOUTCR: LOCO User Trimming Control Register
	// Position of LOCOUTRM field.
	SYSC_LOCOUTCR_LOCOUTRM_Pos = 0x0
	// Bit mask of LOCOUTRM field.
	SYSC_LOCOUTCR_LOCOUTRM_Msk = 0xff
)

// Constants for PORT0: Pmn Pin FunctionPort 0 Control RegistersPmn Pin Function Control Register
const (
	// PCNTR1: Port Control Register 1
	// Position of PDR00 field.
	PORT0_PCNTR1_PDR00_Pos = 0x0
	// Bit mask of PDR00 field.
	PORT0_PCNTR1_PDR00_Msk = 0x1
	// Bit PDR00.
	PORT0_PCNTR1_PDR00 = 0x1
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR00_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR00_1 = 0x1
	// Position of PDR01 field.
	PORT0_PCNTR1_PDR01_Pos = 0x1
	// Bit mask of PDR01 field.
	PORT0_PCNTR1_PDR01_Msk = 0x2
	// Bit PDR01.
	PORT0_PCNTR1_PDR01 = 0x2
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR01_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR01_1 = 0x1
	// Position of PDR02 field.
	PORT0_PCNTR1_PDR02_Pos = 0x2
	// Bit mask of PDR02 field.
	PORT0_PCNTR1_PDR02_Msk = 0x4
	// Bit PDR02.
	PORT0_PCNTR1_PDR02 = 0x4
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR02_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR02_1 = 0x1
	// Position of PDR03 field.
	PORT0_PCNTR1_PDR03_Pos = 0x3
	// Bit mask of PDR03 field.
	PORT0_PCNTR1_PDR03_Msk = 0x8
	// Bit PDR03.
	PORT0_PCNTR1_PDR03 = 0x8
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR03_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR03_1 = 0x1
	// Position of PDR04 field.
	PORT0_PCNTR1_PDR04_Pos = 0x4
	// Bit mask of PDR04 field.
	PORT0_PCNTR1_PDR04_Msk = 0x10
	// Bit PDR04.
	PORT0_PCNTR1_PDR04 = 0x10
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR04_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR04_1 = 0x1
	// Position of PDR05 field.
	PORT0_PCNTR1_PDR05_Pos = 0x5
	// Bit mask of PDR05 field.
	PORT0_PCNTR1_PDR05_Msk = 0x20
	// Bit PDR05.
	PORT0_PCNTR1_PDR05 = 0x20
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR05_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR05_1 = 0x1
	// Position of PDR06 field.
	PORT0_PCNTR1_PDR06_Pos = 0x6
	// Bit mask of PDR06 field.
	PORT0_PCNTR1_PDR06_Msk = 0x40
	// Bit PDR06.
	PORT0_PCNTR1_PDR06 = 0x40
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR06_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR06_1 = 0x1
	// Position of PDR07 field.
	PORT0_PCNTR1_PDR07_Pos = 0x7
	// Bit mask of PDR07 field.
	PORT0_PCNTR1_PDR07_Msk = 0x80
	// Bit PDR07.
	PORT0_PCNTR1_PDR07 = 0x80
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR07_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR07_1 = 0x1
	// Position of PDR08 field.
	PORT0_PCNTR1_PDR08_Pos = 0x8
	// Bit mask of PDR08 field.
	PORT0_PCNTR1_PDR08_Msk = 0x100
	// Bit PDR08.
	PORT0_PCNTR1_PDR08 = 0x100
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR08_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR08_1 = 0x1
	// Position of PDR09 field.
	PORT0_PCNTR1_PDR09_Pos = 0x9
	// Bit mask of PDR09 field.
	PORT0_PCNTR1_PDR09_Msk = 0x200
	// Bit PDR09.
	PORT0_PCNTR1_PDR09 = 0x200
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR09_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR09_1 = 0x1
	// Position of PDR10 field.
	PORT0_PCNTR1_PDR10_Pos = 0xa
	// Bit mask of PDR10 field.
	PORT0_PCNTR1_PDR10_Msk = 0x400
	// Bit PDR10.
	PORT0_PCNTR1_PDR10 = 0x400
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR10_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR10_1 = 0x1
	// Position of PDR11 field.
	PORT0_PCNTR1_PDR11_Pos = 0xb
	// Bit mask of PDR11 field.
	PORT0_PCNTR1_PDR11_Msk = 0x800
	// Bit PDR11.
	PORT0_PCNTR1_PDR11 = 0x800
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR11_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR11_1 = 0x1
	// Position of PDR12 field.
	PORT0_PCNTR1_PDR12_Pos = 0xc
	// Bit mask of PDR12 field.
	PORT0_PCNTR1_PDR12_Msk = 0x1000
	// Bit PDR12.
	PORT0_PCNTR1_PDR12 = 0x1000
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR12_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR12_1 = 0x1
	// Position of PDR13 field.
	PORT0_PCNTR1_PDR13_Pos = 0xd
	// Bit mask of PDR13 field.
	PORT0_PCNTR1_PDR13_Msk = 0x2000
	// Bit PDR13.
	PORT0_PCNTR1_PDR13 = 0x2000
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR13_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR13_1 = 0x1
	// Position of PDR14 field.
	PORT0_PCNTR1_PDR14_Pos = 0xe
	// Bit mask of PDR14 field.
	PORT0_PCNTR1_PDR14_Msk = 0x4000
	// Bit PDR14.
	PORT0_PCNTR1_PDR14 = 0x4000
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR14_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR14_1 = 0x1
	// Position of PDR15 field.
	PORT0_PCNTR1_PDR15_Pos = 0xf
	// Bit mask of PDR15 field.
	PORT0_PCNTR1_PDR15_Msk = 0x8000
	// Bit PDR15.
	PORT0_PCNTR1_PDR15 = 0x8000
	// Input (functions as an input pin)
	PORT0_PCNTR1_PDR15_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PCNTR1_PDR15_1 = 0x1
	// Position of PODR00 field.
	PORT0_PCNTR1_PODR00_Pos = 0x10
	// Bit mask of PODR00 field.
	PORT0_PCNTR1_PODR00_Msk = 0x10000
	// Bit PODR00.
	PORT0_PCNTR1_PODR00 = 0x10000
	// Low output
	PORT0_PCNTR1_PODR00_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR00_1 = 0x1
	// Position of PODR01 field.
	PORT0_PCNTR1_PODR01_Pos = 0x11
	// Bit mask of PODR01 field.
	PORT0_PCNTR1_PODR01_Msk = 0x20000
	// Bit PODR01.
	PORT0_PCNTR1_PODR01 = 0x20000
	// Low output
	PORT0_PCNTR1_PODR01_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR01_1 = 0x1
	// Position of PODR02 field.
	PORT0_PCNTR1_PODR02_Pos = 0x12
	// Bit mask of PODR02 field.
	PORT0_PCNTR1_PODR02_Msk = 0x40000
	// Bit PODR02.
	PORT0_PCNTR1_PODR02 = 0x40000
	// Low output
	PORT0_PCNTR1_PODR02_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR02_1 = 0x1
	// Position of PODR03 field.
	PORT0_PCNTR1_PODR03_Pos = 0x13
	// Bit mask of PODR03 field.
	PORT0_PCNTR1_PODR03_Msk = 0x80000
	// Bit PODR03.
	PORT0_PCNTR1_PODR03 = 0x80000
	// Low output
	PORT0_PCNTR1_PODR03_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR03_1 = 0x1
	// Position of PODR04 field.
	PORT0_PCNTR1_PODR04_Pos = 0x14
	// Bit mask of PODR04 field.
	PORT0_PCNTR1_PODR04_Msk = 0x100000
	// Bit PODR04.
	PORT0_PCNTR1_PODR04 = 0x100000
	// Low output
	PORT0_PCNTR1_PODR04_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR04_1 = 0x1
	// Position of PODR05 field.
	PORT0_PCNTR1_PODR05_Pos = 0x15
	// Bit mask of PODR05 field.
	PORT0_PCNTR1_PODR05_Msk = 0x200000
	// Bit PODR05.
	PORT0_PCNTR1_PODR05 = 0x200000
	// Low output
	PORT0_PCNTR1_PODR05_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR05_1 = 0x1
	// Position of PODR06 field.
	PORT0_PCNTR1_PODR06_Pos = 0x16
	// Bit mask of PODR06 field.
	PORT0_PCNTR1_PODR06_Msk = 0x400000
	// Bit PODR06.
	PORT0_PCNTR1_PODR06 = 0x400000
	// Low output
	PORT0_PCNTR1_PODR06_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR06_1 = 0x1
	// Position of PODR07 field.
	PORT0_PCNTR1_PODR07_Pos = 0x17
	// Bit mask of PODR07 field.
	PORT0_PCNTR1_PODR07_Msk = 0x800000
	// Bit PODR07.
	PORT0_PCNTR1_PODR07 = 0x800000
	// Low output
	PORT0_PCNTR1_PODR07_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR07_1 = 0x1
	// Position of PODR08 field.
	PORT0_PCNTR1_PODR08_Pos = 0x18
	// Bit mask of PODR08 field.
	PORT0_PCNTR1_PODR08_Msk = 0x1000000
	// Bit PODR08.
	PORT0_PCNTR1_PODR08 = 0x1000000
	// Low output
	PORT0_PCNTR1_PODR08_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR08_1 = 0x1
	// Position of PODR09 field.
	PORT0_PCNTR1_PODR09_Pos = 0x19
	// Bit mask of PODR09 field.
	PORT0_PCNTR1_PODR09_Msk = 0x2000000
	// Bit PODR09.
	PORT0_PCNTR1_PODR09 = 0x2000000
	// Low output
	PORT0_PCNTR1_PODR09_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR09_1 = 0x1
	// Position of PODR10 field.
	PORT0_PCNTR1_PODR10_Pos = 0x1a
	// Bit mask of PODR10 field.
	PORT0_PCNTR1_PODR10_Msk = 0x4000000
	// Bit PODR10.
	PORT0_PCNTR1_PODR10 = 0x4000000
	// Low output
	PORT0_PCNTR1_PODR10_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR10_1 = 0x1
	// Position of PODR11 field.
	PORT0_PCNTR1_PODR11_Pos = 0x1b
	// Bit mask of PODR11 field.
	PORT0_PCNTR1_PODR11_Msk = 0x8000000
	// Bit PODR11.
	PORT0_PCNTR1_PODR11 = 0x8000000
	// Low output
	PORT0_PCNTR1_PODR11_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR11_1 = 0x1
	// Position of PODR12 field.
	PORT0_PCNTR1_PODR12_Pos = 0x1c
	// Bit mask of PODR12 field.
	PORT0_PCNTR1_PODR12_Msk = 0x10000000
	// Bit PODR12.
	PORT0_PCNTR1_PODR12 = 0x10000000
	// Low output
	PORT0_PCNTR1_PODR12_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR12_1 = 0x1
	// Position of PODR13 field.
	PORT0_PCNTR1_PODR13_Pos = 0x1d
	// Bit mask of PODR13 field.
	PORT0_PCNTR1_PODR13_Msk = 0x20000000
	// Bit PODR13.
	PORT0_PCNTR1_PODR13 = 0x20000000
	// Low output
	PORT0_PCNTR1_PODR13_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR13_1 = 0x1
	// Position of PODR14 field.
	PORT0_PCNTR1_PODR14_Pos = 0x1e
	// Bit mask of PODR14 field.
	PORT0_PCNTR1_PODR14_Msk = 0x40000000
	// Bit PODR14.
	PORT0_PCNTR1_PODR14 = 0x40000000
	// Low output
	PORT0_PCNTR1_PODR14_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR14_1 = 0x1
	// Position of PODR15 field.
	PORT0_PCNTR1_PODR15_Pos = 0x1f
	// Bit mask of PODR15 field.
	PORT0_PCNTR1_PODR15_Msk = 0x80000000
	// Bit PODR15.
	PORT0_PCNTR1_PODR15 = 0x80000000
	// Low output
	PORT0_PCNTR1_PODR15_0 = 0x0
	// High output
	PORT0_PCNTR1_PODR15_1 = 0x1

	// PODR: Port Control Register 1
	// Position of PODR00 field.
	PORT0_PODR_PODR00_Pos = 0x0
	// Bit mask of PODR00 field.
	PORT0_PODR_PODR00_Msk = 0x1
	// Bit PODR00.
	PORT0_PODR_PODR00 = 0x1
	// Low output
	PORT0_PODR_PODR00_0 = 0x0
	// High output
	PORT0_PODR_PODR00_1 = 0x1
	// Position of PODR01 field.
	PORT0_PODR_PODR01_Pos = 0x1
	// Bit mask of PODR01 field.
	PORT0_PODR_PODR01_Msk = 0x2
	// Bit PODR01.
	PORT0_PODR_PODR01 = 0x2
	// Low output
	PORT0_PODR_PODR01_0 = 0x0
	// High output
	PORT0_PODR_PODR01_1 = 0x1
	// Position of PODR02 field.
	PORT0_PODR_PODR02_Pos = 0x2
	// Bit mask of PODR02 field.
	PORT0_PODR_PODR02_Msk = 0x4
	// Bit PODR02.
	PORT0_PODR_PODR02 = 0x4
	// Low output
	PORT0_PODR_PODR02_0 = 0x0
	// High output
	PORT0_PODR_PODR02_1 = 0x1
	// Position of PODR03 field.
	PORT0_PODR_PODR03_Pos = 0x3
	// Bit mask of PODR03 field.
	PORT0_PODR_PODR03_Msk = 0x8
	// Bit PODR03.
	PORT0_PODR_PODR03 = 0x8
	// Low output
	PORT0_PODR_PODR03_0 = 0x0
	// High output
	PORT0_PODR_PODR03_1 = 0x1
	// Position of PODR04 field.
	PORT0_PODR_PODR04_Pos = 0x4
	// Bit mask of PODR04 field.
	PORT0_PODR_PODR04_Msk = 0x10
	// Bit PODR04.
	PORT0_PODR_PODR04 = 0x10
	// Low output
	PORT0_PODR_PODR04_0 = 0x0
	// High output
	PORT0_PODR_PODR04_1 = 0x1
	// Position of PODR05 field.
	PORT0_PODR_PODR05_Pos = 0x5
	// Bit mask of PODR05 field.
	PORT0_PODR_PODR05_Msk = 0x20
	// Bit PODR05.
	PORT0_PODR_PODR05 = 0x20
	// Low output
	PORT0_PODR_PODR05_0 = 0x0
	// High output
	PORT0_PODR_PODR05_1 = 0x1
	// Position of PODR06 field.
	PORT0_PODR_PODR06_Pos = 0x6
	// Bit mask of PODR06 field.
	PORT0_PODR_PODR06_Msk = 0x40
	// Bit PODR06.
	PORT0_PODR_PODR06 = 0x40
	// Low output
	PORT0_PODR_PODR06_0 = 0x0
	// High output
	PORT0_PODR_PODR06_1 = 0x1
	// Position of PODR07 field.
	PORT0_PODR_PODR07_Pos = 0x7
	// Bit mask of PODR07 field.
	PORT0_PODR_PODR07_Msk = 0x80
	// Bit PODR07.
	PORT0_PODR_PODR07 = 0x80
	// Low output
	PORT0_PODR_PODR07_0 = 0x0
	// High output
	PORT0_PODR_PODR07_1 = 0x1
	// Position of PODR08 field.
	PORT0_PODR_PODR08_Pos = 0x8
	// Bit mask of PODR08 field.
	PORT0_PODR_PODR08_Msk = 0x100
	// Bit PODR08.
	PORT0_PODR_PODR08 = 0x100
	// Low output
	PORT0_PODR_PODR08_0 = 0x0
	// High output
	PORT0_PODR_PODR08_1 = 0x1
	// Position of PODR09 field.
	PORT0_PODR_PODR09_Pos = 0x9
	// Bit mask of PODR09 field.
	PORT0_PODR_PODR09_Msk = 0x200
	// Bit PODR09.
	PORT0_PODR_PODR09 = 0x200
	// Low output
	PORT0_PODR_PODR09_0 = 0x0
	// High output
	PORT0_PODR_PODR09_1 = 0x1
	// Position of PODR10 field.
	PORT0_PODR_PODR10_Pos = 0xa
	// Bit mask of PODR10 field.
	PORT0_PODR_PODR10_Msk = 0x400
	// Bit PODR10.
	PORT0_PODR_PODR10 = 0x400
	// Low output
	PORT0_PODR_PODR10_0 = 0x0
	// High output
	PORT0_PODR_PODR10_1 = 0x1
	// Position of PODR11 field.
	PORT0_PODR_PODR11_Pos = 0xb
	// Bit mask of PODR11 field.
	PORT0_PODR_PODR11_Msk = 0x800
	// Bit PODR11.
	PORT0_PODR_PODR11 = 0x800
	// Low output
	PORT0_PODR_PODR11_0 = 0x0
	// High output
	PORT0_PODR_PODR11_1 = 0x1
	// Position of PODR12 field.
	PORT0_PODR_PODR12_Pos = 0xc
	// Bit mask of PODR12 field.
	PORT0_PODR_PODR12_Msk = 0x1000
	// Bit PODR12.
	PORT0_PODR_PODR12 = 0x1000
	// Low output
	PORT0_PODR_PODR12_0 = 0x0
	// High output
	PORT0_PODR_PODR12_1 = 0x1
	// Position of PODR13 field.
	PORT0_PODR_PODR13_Pos = 0xd
	// Bit mask of PODR13 field.
	PORT0_PODR_PODR13_Msk = 0x2000
	// Bit PODR13.
	PORT0_PODR_PODR13 = 0x2000
	// Low output
	PORT0_PODR_PODR13_0 = 0x0
	// High output
	PORT0_PODR_PODR13_1 = 0x1
	// Position of PODR14 field.
	PORT0_PODR_PODR14_Pos = 0xe
	// Bit mask of PODR14 field.
	PORT0_PODR_PODR14_Msk = 0x4000
	// Bit PODR14.
	PORT0_PODR_PODR14 = 0x4000
	// Low output
	PORT0_PODR_PODR14_0 = 0x0
	// High output
	PORT0_PODR_PODR14_1 = 0x1
	// Position of PODR15 field.
	PORT0_PODR_PODR15_Pos = 0xf
	// Bit mask of PODR15 field.
	PORT0_PODR_PODR15_Msk = 0x8000
	// Bit PODR15.
	PORT0_PODR_PODR15 = 0x8000
	// Low output
	PORT0_PODR_PODR15_0 = 0x0
	// High output
	PORT0_PODR_PODR15_1 = 0x1

	// PDR: Port Control Register 1
	// Position of PDR00 field.
	PORT0_PDR_PDR00_Pos = 0x0
	// Bit mask of PDR00 field.
	PORT0_PDR_PDR00_Msk = 0x1
	// Bit PDR00.
	PORT0_PDR_PDR00 = 0x1
	// Input (functions as an input pin)
	PORT0_PDR_PDR00_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR00_1 = 0x1
	// Position of PDR01 field.
	PORT0_PDR_PDR01_Pos = 0x1
	// Bit mask of PDR01 field.
	PORT0_PDR_PDR01_Msk = 0x2
	// Bit PDR01.
	PORT0_PDR_PDR01 = 0x2
	// Input (functions as an input pin)
	PORT0_PDR_PDR01_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR01_1 = 0x1
	// Position of PDR02 field.
	PORT0_PDR_PDR02_Pos = 0x2
	// Bit mask of PDR02 field.
	PORT0_PDR_PDR02_Msk = 0x4
	// Bit PDR02.
	PORT0_PDR_PDR02 = 0x4
	// Input (functions as an input pin)
	PORT0_PDR_PDR02_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR02_1 = 0x1
	// Position of PDR03 field.
	PORT0_PDR_PDR03_Pos = 0x3
	// Bit mask of PDR03 field.
	PORT0_PDR_PDR03_Msk = 0x8
	// Bit PDR03.
	PORT0_PDR_PDR03 = 0x8
	// Input (functions as an input pin)
	PORT0_PDR_PDR03_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR03_1 = 0x1
	// Position of PDR04 field.
	PORT0_PDR_PDR04_Pos = 0x4
	// Bit mask of PDR04 field.
	PORT0_PDR_PDR04_Msk = 0x10
	// Bit PDR04.
	PORT0_PDR_PDR04 = 0x10
	// Input (functions as an input pin)
	PORT0_PDR_PDR04_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR04_1 = 0x1
	// Position of PDR05 field.
	PORT0_PDR_PDR05_Pos = 0x5
	// Bit mask of PDR05 field.
	PORT0_PDR_PDR05_Msk = 0x20
	// Bit PDR05.
	PORT0_PDR_PDR05 = 0x20
	// Input (functions as an input pin)
	PORT0_PDR_PDR05_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR05_1 = 0x1
	// Position of PDR06 field.
	PORT0_PDR_PDR06_Pos = 0x6
	// Bit mask of PDR06 field.
	PORT0_PDR_PDR06_Msk = 0x40
	// Bit PDR06.
	PORT0_PDR_PDR06 = 0x40
	// Input (functions as an input pin)
	PORT0_PDR_PDR06_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR06_1 = 0x1
	// Position of PDR07 field.
	PORT0_PDR_PDR07_Pos = 0x7
	// Bit mask of PDR07 field.
	PORT0_PDR_PDR07_Msk = 0x80
	// Bit PDR07.
	PORT0_PDR_PDR07 = 0x80
	// Input (functions as an input pin)
	PORT0_PDR_PDR07_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR07_1 = 0x1
	// Position of PDR08 field.
	PORT0_PDR_PDR08_Pos = 0x8
	// Bit mask of PDR08 field.
	PORT0_PDR_PDR08_Msk = 0x100
	// Bit PDR08.
	PORT0_PDR_PDR08 = 0x100
	// Input (functions as an input pin)
	PORT0_PDR_PDR08_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR08_1 = 0x1
	// Position of PDR09 field.
	PORT0_PDR_PDR09_Pos = 0x9
	// Bit mask of PDR09 field.
	PORT0_PDR_PDR09_Msk = 0x200
	// Bit PDR09.
	PORT0_PDR_PDR09 = 0x200
	// Input (functions as an input pin)
	PORT0_PDR_PDR09_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR09_1 = 0x1
	// Position of PDR10 field.
	PORT0_PDR_PDR10_Pos = 0xa
	// Bit mask of PDR10 field.
	PORT0_PDR_PDR10_Msk = 0x400
	// Bit PDR10.
	PORT0_PDR_PDR10 = 0x400
	// Input (functions as an input pin)
	PORT0_PDR_PDR10_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR10_1 = 0x1
	// Position of PDR11 field.
	PORT0_PDR_PDR11_Pos = 0xb
	// Bit mask of PDR11 field.
	PORT0_PDR_PDR11_Msk = 0x800
	// Bit PDR11.
	PORT0_PDR_PDR11 = 0x800
	// Input (functions as an input pin)
	PORT0_PDR_PDR11_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR11_1 = 0x1
	// Position of PDR12 field.
	PORT0_PDR_PDR12_Pos = 0xc
	// Bit mask of PDR12 field.
	PORT0_PDR_PDR12_Msk = 0x1000
	// Bit PDR12.
	PORT0_PDR_PDR12 = 0x1000
	// Input (functions as an input pin)
	PORT0_PDR_PDR12_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR12_1 = 0x1
	// Position of PDR13 field.
	PORT0_PDR_PDR13_Pos = 0xd
	// Bit mask of PDR13 field.
	PORT0_PDR_PDR13_Msk = 0x2000
	// Bit PDR13.
	PORT0_PDR_PDR13 = 0x2000
	// Input (functions as an input pin)
	PORT0_PDR_PDR13_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR13_1 = 0x1
	// Position of PDR14 field.
	PORT0_PDR_PDR14_Pos = 0xe
	// Bit mask of PDR14 field.
	PORT0_PDR_PDR14_Msk = 0x4000
	// Bit PDR14.
	PORT0_PDR_PDR14 = 0x4000
	// Input (functions as an input pin)
	PORT0_PDR_PDR14_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR14_1 = 0x1
	// Position of PDR15 field.
	PORT0_PDR_PDR15_Pos = 0xf
	// Bit mask of PDR15 field.
	PORT0_PDR_PDR15_Msk = 0x8000
	// Bit PDR15.
	PORT0_PDR_PDR15 = 0x8000
	// Input (functions as an input pin)
	PORT0_PDR_PDR15_0 = 0x0
	// Output (functions as an output pin)
	PORT0_PDR_PDR15_1 = 0x1

	// PCNTR2: Port Control Register 2
	// Position of PIDR00 field.
	PORT0_PCNTR2_PIDR00_Pos = 0x0
	// Bit mask of PIDR00 field.
	PORT0_PCNTR2_PIDR00_Msk = 0x1
	// Bit PIDR00.
	PORT0_PCNTR2_PIDR00 = 0x1
	// Low level
	PORT0_PCNTR2_PIDR00_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR00_1 = 0x1
	// Position of PIDR01 field.
	PORT0_PCNTR2_PIDR01_Pos = 0x1
	// Bit mask of PIDR01 field.
	PORT0_PCNTR2_PIDR01_Msk = 0x2
	// Bit PIDR01.
	PORT0_PCNTR2_PIDR01 = 0x2
	// Low level
	PORT0_PCNTR2_PIDR01_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR01_1 = 0x1
	// Position of PIDR02 field.
	PORT0_PCNTR2_PIDR02_Pos = 0x2
	// Bit mask of PIDR02 field.
	PORT0_PCNTR2_PIDR02_Msk = 0x4
	// Bit PIDR02.
	PORT0_PCNTR2_PIDR02 = 0x4
	// Low level
	PORT0_PCNTR2_PIDR02_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR02_1 = 0x1
	// Position of PIDR03 field.
	PORT0_PCNTR2_PIDR03_Pos = 0x3
	// Bit mask of PIDR03 field.
	PORT0_PCNTR2_PIDR03_Msk = 0x8
	// Bit PIDR03.
	PORT0_PCNTR2_PIDR03 = 0x8
	// Low level
	PORT0_PCNTR2_PIDR03_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR03_1 = 0x1
	// Position of PIDR04 field.
	PORT0_PCNTR2_PIDR04_Pos = 0x4
	// Bit mask of PIDR04 field.
	PORT0_PCNTR2_PIDR04_Msk = 0x10
	// Bit PIDR04.
	PORT0_PCNTR2_PIDR04 = 0x10
	// Low level
	PORT0_PCNTR2_PIDR04_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR04_1 = 0x1
	// Position of PIDR05 field.
	PORT0_PCNTR2_PIDR05_Pos = 0x5
	// Bit mask of PIDR05 field.
	PORT0_PCNTR2_PIDR05_Msk = 0x20
	// Bit PIDR05.
	PORT0_PCNTR2_PIDR05 = 0x20
	// Low level
	PORT0_PCNTR2_PIDR05_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR05_1 = 0x1
	// Position of PIDR06 field.
	PORT0_PCNTR2_PIDR06_Pos = 0x6
	// Bit mask of PIDR06 field.
	PORT0_PCNTR2_PIDR06_Msk = 0x40
	// Bit PIDR06.
	PORT0_PCNTR2_PIDR06 = 0x40
	// Low level
	PORT0_PCNTR2_PIDR06_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR06_1 = 0x1
	// Position of PIDR07 field.
	PORT0_PCNTR2_PIDR07_Pos = 0x7
	// Bit mask of PIDR07 field.
	PORT0_PCNTR2_PIDR07_Msk = 0x80
	// Bit PIDR07.
	PORT0_PCNTR2_PIDR07 = 0x80
	// Low level
	PORT0_PCNTR2_PIDR07_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR07_1 = 0x1
	// Position of PIDR08 field.
	PORT0_PCNTR2_PIDR08_Pos = 0x8
	// Bit mask of PIDR08 field.
	PORT0_PCNTR2_PIDR08_Msk = 0x100
	// Bit PIDR08.
	PORT0_PCNTR2_PIDR08 = 0x100
	// Low level
	PORT0_PCNTR2_PIDR08_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR08_1 = 0x1
	// Position of PIDR09 field.
	PORT0_PCNTR2_PIDR09_Pos = 0x9
	// Bit mask of PIDR09 field.
	PORT0_PCNTR2_PIDR09_Msk = 0x200
	// Bit PIDR09.
	PORT0_PCNTR2_PIDR09 = 0x200
	// Low level
	PORT0_PCNTR2_PIDR09_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR09_1 = 0x1
	// Position of PIDR10 field.
	PORT0_PCNTR2_PIDR10_Pos = 0xa
	// Bit mask of PIDR10 field.
	PORT0_PCNTR2_PIDR10_Msk = 0x400
	// Bit PIDR10.
	PORT0_PCNTR2_PIDR10 = 0x400
	// Low level
	PORT0_PCNTR2_PIDR10_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR10_1 = 0x1
	// Position of PIDR11 field.
	PORT0_PCNTR2_PIDR11_Pos = 0xb
	// Bit mask of PIDR11 field.
	PORT0_PCNTR2_PIDR11_Msk = 0x800
	// Bit PIDR11.
	PORT0_PCNTR2_PIDR11 = 0x800
	// Low level
	PORT0_PCNTR2_PIDR11_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR11_1 = 0x1
	// Position of PIDR12 field.
	PORT0_PCNTR2_PIDR12_Pos = 0xc
	// Bit mask of PIDR12 field.
	PORT0_PCNTR2_PIDR12_Msk = 0x1000
	// Bit PIDR12.
	PORT0_PCNTR2_PIDR12 = 0x1000
	// Low level
	PORT0_PCNTR2_PIDR12_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR12_1 = 0x1
	// Position of PIDR13 field.
	PORT0_PCNTR2_PIDR13_Pos = 0xd
	// Bit mask of PIDR13 field.
	PORT0_PCNTR2_PIDR13_Msk = 0x2000
	// Bit PIDR13.
	PORT0_PCNTR2_PIDR13 = 0x2000
	// Low level
	PORT0_PCNTR2_PIDR13_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR13_1 = 0x1
	// Position of PIDR14 field.
	PORT0_PCNTR2_PIDR14_Pos = 0xe
	// Bit mask of PIDR14 field.
	PORT0_PCNTR2_PIDR14_Msk = 0x4000
	// Bit PIDR14.
	PORT0_PCNTR2_PIDR14 = 0x4000
	// Low level
	PORT0_PCNTR2_PIDR14_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR14_1 = 0x1
	// Position of PIDR15 field.
	PORT0_PCNTR2_PIDR15_Pos = 0xf
	// Bit mask of PIDR15 field.
	PORT0_PCNTR2_PIDR15_Msk = 0x8000
	// Bit PIDR15.
	PORT0_PCNTR2_PIDR15 = 0x8000
	// Low level
	PORT0_PCNTR2_PIDR15_0 = 0x0
	// High level
	PORT0_PCNTR2_PIDR15_1 = 0x1

	// PIDR: Port Control Register 2
	// Position of PIDR00 field.
	PORT0_PIDR_PIDR00_Pos = 0x0
	// Bit mask of PIDR00 field.
	PORT0_PIDR_PIDR00_Msk = 0x1
	// Bit PIDR00.
	PORT0_PIDR_PIDR00 = 0x1
	// Low level
	PORT0_PIDR_PIDR00_0 = 0x0
	// High level
	PORT0_PIDR_PIDR00_1 = 0x1
	// Position of PIDR01 field.
	PORT0_PIDR_PIDR01_Pos = 0x1
	// Bit mask of PIDR01 field.
	PORT0_PIDR_PIDR01_Msk = 0x2
	// Bit PIDR01.
	PORT0_PIDR_PIDR01 = 0x2
	// Low level
	PORT0_PIDR_PIDR01_0 = 0x0
	// High level
	PORT0_PIDR_PIDR01_1 = 0x1
	// Position of PIDR02 field.
	PORT0_PIDR_PIDR02_Pos = 0x2
	// Bit mask of PIDR02 field.
	PORT0_PIDR_PIDR02_Msk = 0x4
	// Bit PIDR02.
	PORT0_PIDR_PIDR02 = 0x4
	// Low level
	PORT0_PIDR_PIDR02_0 = 0x0
	// High level
	PORT0_PIDR_PIDR02_1 = 0x1
	// Position of PIDR03 field.
	PORT0_PIDR_PIDR03_Pos = 0x3
	// Bit mask of PIDR03 field.
	PORT0_PIDR_PIDR03_Msk = 0x8
	// Bit PIDR03.
	PORT0_PIDR_PIDR03 = 0x8
	// Low level
	PORT0_PIDR_PIDR03_0 = 0x0
	// High level
	PORT0_PIDR_PIDR03_1 = 0x1
	// Position of PIDR04 field.
	PORT0_PIDR_PIDR04_Pos = 0x4
	// Bit mask of PIDR04 field.
	PORT0_PIDR_PIDR04_Msk = 0x10
	// Bit PIDR04.
	PORT0_PIDR_PIDR04 = 0x10
	// Low level
	PORT0_PIDR_PIDR04_0 = 0x0
	// High level
	PORT0_PIDR_PIDR04_1 = 0x1
	// Position of PIDR05 field.
	PORT0_PIDR_PIDR05_Pos = 0x5
	// Bit mask of PIDR05 field.
	PORT0_PIDR_PIDR05_Msk = 0x20
	// Bit PIDR05.
	PORT0_PIDR_PIDR05 = 0x20
	// Low level
	PORT0_PIDR_PIDR05_0 = 0x0
	// High level
	PORT0_PIDR_PIDR05_1 = 0x1
	// Position of PIDR06 field.
	PORT0_PIDR_PIDR06_Pos = 0x6
	// Bit mask of PIDR06 field.
	PORT0_PIDR_PIDR06_Msk = 0x40
	// Bit PIDR06.
	PORT0_PIDR_PIDR06 = 0x40
	// Low level
	PORT0_PIDR_PIDR06_0 = 0x0
	// High level
	PORT0_PIDR_PIDR06_1 = 0x1
	// Position of PIDR07 field.
	PORT0_PIDR_PIDR07_Pos = 0x7
	// Bit mask of PIDR07 field.
	PORT0_PIDR_PIDR07_Msk = 0x80
	// Bit PIDR07.
	PORT0_PIDR_PIDR07 = 0x80
	// Low level
	PORT0_PIDR_PIDR07_0 = 0x0
	// High level
	PORT0_PIDR_PIDR07_1 = 0x1
	// Position of PIDR08 field.
	PORT0_PIDR_PIDR08_Pos = 0x8
	// Bit mask of PIDR08 field.
	PORT0_PIDR_PIDR08_Msk = 0x100
	// Bit PIDR08.
	PORT0_PIDR_PIDR08 = 0x100
	// Low level
	PORT0_PIDR_PIDR08_0 = 0x0
	// High level
	PORT0_PIDR_PIDR08_1 = 0x1
	// Position of PIDR09 field.
	PORT0_PIDR_PIDR09_Pos = 0x9
	// Bit mask of PIDR09 field.
	PORT0_PIDR_PIDR09_Msk = 0x200
	// Bit PIDR09.
	PORT0_PIDR_PIDR09 = 0x200
	// Low level
	PORT0_PIDR_PIDR09_0 = 0x0
	// High level
	PORT0_PIDR_PIDR09_1 = 0x1
	// Position of PIDR10 field.
	PORT0_PIDR_PIDR10_Pos = 0xa
	// Bit mask of PIDR10 field.
	PORT0_PIDR_PIDR10_Msk = 0x400
	// Bit PIDR10.
	PORT0_PIDR_PIDR10 = 0x400
	// Low level
	PORT0_PIDR_PIDR10_0 = 0x0
	// High level
	PORT0_PIDR_PIDR10_1 = 0x1
	// Position of PIDR11 field.
	PORT0_PIDR_PIDR11_Pos = 0xb
	// Bit mask of PIDR11 field.
	PORT0_PIDR_PIDR11_Msk = 0x800
	// Bit PIDR11.
	PORT0_PIDR_PIDR11 = 0x800
	// Low level
	PORT0_PIDR_PIDR11_0 = 0x0
	// High level
	PORT0_PIDR_PIDR11_1 = 0x1
	// Position of PIDR12 field.
	PORT0_PIDR_PIDR12_Pos = 0xc
	// Bit mask of PIDR12 field.
	PORT0_PIDR_PIDR12_Msk = 0x1000
	// Bit PIDR12.
	PORT0_PIDR_PIDR12 = 0x1000
	// Low level
	PORT0_PIDR_PIDR12_0 = 0x0
	// High level
	PORT0_PIDR_PIDR12_1 = 0x1
	// Position of PIDR13 field.
	PORT0_PIDR_PIDR13_Pos = 0xd
	// Bit mask of PIDR13 field.
	PORT0_PIDR_PIDR13_Msk = 0x2000
	// Bit PIDR13.
	PORT0_PIDR_PIDR13 = 0x2000
	// Low level
	PORT0_PIDR_PIDR13_0 = 0x0
	// High level
	PORT0_PIDR_PIDR13_1 = 0x1
	// Position of PIDR14 field.
	PORT0_PIDR_PIDR14_Pos = 0xe
	// Bit mask of PIDR14 field.
	PORT0_PIDR_PIDR14_Msk = 0x4000
	// Bit PIDR14.
	PORT0_PIDR_PIDR14 = 0x4000
	// Low level
	PORT0_PIDR_PIDR14_0 = 0x0
	// High level
	PORT0_PIDR_PIDR14_1 = 0x1
	// Position of PIDR15 field.
	PORT0_PIDR_PIDR15_Pos = 0xf
	// Bit mask of PIDR15 field.
	PORT0_PIDR_PIDR15_Msk = 0x8000
	// Bit PIDR15.
	PORT0_PIDR_PIDR15 = 0x8000
	// Low level
	PORT0_PIDR_PIDR15_0 = 0x0
	// High level
	PORT0_PIDR_PIDR15_1 = 0x1

	// PCNTR3: Port Control Register 3
	// Position of POSR00 field.
	PORT0_PCNTR3_POSR00_Pos = 0x0
	// Bit mask of POSR00 field.
	PORT0_PCNTR3_POSR00_Msk = 0x1
	// Bit POSR00.
	PORT0_PCNTR3_POSR00 = 0x1
	// No effect on output
	PORT0_PCNTR3_POSR00_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR00_1 = 0x1
	// Position of POSR01 field.
	PORT0_PCNTR3_POSR01_Pos = 0x1
	// Bit mask of POSR01 field.
	PORT0_PCNTR3_POSR01_Msk = 0x2
	// Bit POSR01.
	PORT0_PCNTR3_POSR01 = 0x2
	// No effect on output
	PORT0_PCNTR3_POSR01_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR01_1 = 0x1
	// Position of POSR02 field.
	PORT0_PCNTR3_POSR02_Pos = 0x2
	// Bit mask of POSR02 field.
	PORT0_PCNTR3_POSR02_Msk = 0x4
	// Bit POSR02.
	PORT0_PCNTR3_POSR02 = 0x4
	// No effect on output
	PORT0_PCNTR3_POSR02_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR02_1 = 0x1
	// Position of POSR03 field.
	PORT0_PCNTR3_POSR03_Pos = 0x3
	// Bit mask of POSR03 field.
	PORT0_PCNTR3_POSR03_Msk = 0x8
	// Bit POSR03.
	PORT0_PCNTR3_POSR03 = 0x8
	// No effect on output
	PORT0_PCNTR3_POSR03_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR03_1 = 0x1
	// Position of POSR04 field.
	PORT0_PCNTR3_POSR04_Pos = 0x4
	// Bit mask of POSR04 field.
	PORT0_PCNTR3_POSR04_Msk = 0x10
	// Bit POSR04.
	PORT0_PCNTR3_POSR04 = 0x10
	// No effect on output
	PORT0_PCNTR3_POSR04_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR04_1 = 0x1
	// Position of POSR05 field.
	PORT0_PCNTR3_POSR05_Pos = 0x5
	// Bit mask of POSR05 field.
	PORT0_PCNTR3_POSR05_Msk = 0x20
	// Bit POSR05.
	PORT0_PCNTR3_POSR05 = 0x20
	// No effect on output
	PORT0_PCNTR3_POSR05_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR05_1 = 0x1
	// Position of POSR06 field.
	PORT0_PCNTR3_POSR06_Pos = 0x6
	// Bit mask of POSR06 field.
	PORT0_PCNTR3_POSR06_Msk = 0x40
	// Bit POSR06.
	PORT0_PCNTR3_POSR06 = 0x40
	// No effect on output
	PORT0_PCNTR3_POSR06_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR06_1 = 0x1
	// Position of POSR07 field.
	PORT0_PCNTR3_POSR07_Pos = 0x7
	// Bit mask of POSR07 field.
	PORT0_PCNTR3_POSR07_Msk = 0x80
	// Bit POSR07.
	PORT0_PCNTR3_POSR07 = 0x80
	// No effect on output
	PORT0_PCNTR3_POSR07_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR07_1 = 0x1
	// Position of POSR08 field.
	PORT0_PCNTR3_POSR08_Pos = 0x8
	// Bit mask of POSR08 field.
	PORT0_PCNTR3_POSR08_Msk = 0x100
	// Bit POSR08.
	PORT0_PCNTR3_POSR08 = 0x100
	// No effect on output
	PORT0_PCNTR3_POSR08_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR08_1 = 0x1
	// Position of POSR09 field.
	PORT0_PCNTR3_POSR09_Pos = 0x9
	// Bit mask of POSR09 field.
	PORT0_PCNTR3_POSR09_Msk = 0x200
	// Bit POSR09.
	PORT0_PCNTR3_POSR09 = 0x200
	// No effect on output
	PORT0_PCNTR3_POSR09_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR09_1 = 0x1
	// Position of POSR10 field.
	PORT0_PCNTR3_POSR10_Pos = 0xa
	// Bit mask of POSR10 field.
	PORT0_PCNTR3_POSR10_Msk = 0x400
	// Bit POSR10.
	PORT0_PCNTR3_POSR10 = 0x400
	// No effect on output
	PORT0_PCNTR3_POSR10_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR10_1 = 0x1
	// Position of POSR11 field.
	PORT0_PCNTR3_POSR11_Pos = 0xb
	// Bit mask of POSR11 field.
	PORT0_PCNTR3_POSR11_Msk = 0x800
	// Bit POSR11.
	PORT0_PCNTR3_POSR11 = 0x800
	// No effect on output
	PORT0_PCNTR3_POSR11_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR11_1 = 0x1
	// Position of POSR12 field.
	PORT0_PCNTR3_POSR12_Pos = 0xc
	// Bit mask of POSR12 field.
	PORT0_PCNTR3_POSR12_Msk = 0x1000
	// Bit POSR12.
	PORT0_PCNTR3_POSR12 = 0x1000
	// No effect on output
	PORT0_PCNTR3_POSR12_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR12_1 = 0x1
	// Position of POSR13 field.
	PORT0_PCNTR3_POSR13_Pos = 0xd
	// Bit mask of POSR13 field.
	PORT0_PCNTR3_POSR13_Msk = 0x2000
	// Bit POSR13.
	PORT0_PCNTR3_POSR13 = 0x2000
	// No effect on output
	PORT0_PCNTR3_POSR13_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR13_1 = 0x1
	// Position of POSR14 field.
	PORT0_PCNTR3_POSR14_Pos = 0xe
	// Bit mask of POSR14 field.
	PORT0_PCNTR3_POSR14_Msk = 0x4000
	// Bit POSR14.
	PORT0_PCNTR3_POSR14 = 0x4000
	// No effect on output
	PORT0_PCNTR3_POSR14_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR14_1 = 0x1
	// Position of POSR15 field.
	PORT0_PCNTR3_POSR15_Pos = 0xf
	// Bit mask of POSR15 field.
	PORT0_PCNTR3_POSR15_Msk = 0x8000
	// Bit POSR15.
	PORT0_PCNTR3_POSR15 = 0x8000
	// No effect on output
	PORT0_PCNTR3_POSR15_0 = 0x0
	// High output
	PORT0_PCNTR3_POSR15_1 = 0x1
	// Position of PORR00 field.
	PORT0_PCNTR3_PORR00_Pos = 0x10
	// Bit mask of PORR00 field.
	PORT0_PCNTR3_PORR00_Msk = 0x10000
	// Bit PORR00.
	PORT0_PCNTR3_PORR00 = 0x10000
	// No effect on output
	PORT0_PCNTR3_PORR00_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR00_1 = 0x1
	// Position of PORR01 field.
	PORT0_PCNTR3_PORR01_Pos = 0x11
	// Bit mask of PORR01 field.
	PORT0_PCNTR3_PORR01_Msk = 0x20000
	// Bit PORR01.
	PORT0_PCNTR3_PORR01 = 0x20000
	// No effect on output
	PORT0_PCNTR3_PORR01_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR01_1 = 0x1
	// Position of PORR02 field.
	PORT0_PCNTR3_PORR02_Pos = 0x12
	// Bit mask of PORR02 field.
	PORT0_PCNTR3_PORR02_Msk = 0x40000
	// Bit PORR02.
	PORT0_PCNTR3_PORR02 = 0x40000
	// No effect on output
	PORT0_PCNTR3_PORR02_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR02_1 = 0x1
	// Position of PORR03 field.
	PORT0_PCNTR3_PORR03_Pos = 0x13
	// Bit mask of PORR03 field.
	PORT0_PCNTR3_PORR03_Msk = 0x80000
	// Bit PORR03.
	PORT0_PCNTR3_PORR03 = 0x80000
	// No effect on output
	PORT0_PCNTR3_PORR03_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR03_1 = 0x1
	// Position of PORR04 field.
	PORT0_PCNTR3_PORR04_Pos = 0x14
	// Bit mask of PORR04 field.
	PORT0_PCNTR3_PORR04_Msk = 0x100000
	// Bit PORR04.
	PORT0_PCNTR3_PORR04 = 0x100000
	// No effect on output
	PORT0_PCNTR3_PORR04_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR04_1 = 0x1
	// Position of PORR05 field.
	PORT0_PCNTR3_PORR05_Pos = 0x15
	// Bit mask of PORR05 field.
	PORT0_PCNTR3_PORR05_Msk = 0x200000
	// Bit PORR05.
	PORT0_PCNTR3_PORR05 = 0x200000
	// No effect on output
	PORT0_PCNTR3_PORR05_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR05_1 = 0x1
	// Position of PORR06 field.
	PORT0_PCNTR3_PORR06_Pos = 0x16
	// Bit mask of PORR06 field.
	PORT0_PCNTR3_PORR06_Msk = 0x400000
	// Bit PORR06.
	PORT0_PCNTR3_PORR06 = 0x400000
	// No effect on output
	PORT0_PCNTR3_PORR06_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR06_1 = 0x1
	// Position of PORR07 field.
	PORT0_PCNTR3_PORR07_Pos = 0x17
	// Bit mask of PORR07 field.
	PORT0_PCNTR3_PORR07_Msk = 0x800000
	// Bit PORR07.
	PORT0_PCNTR3_PORR07 = 0x800000
	// No effect on output
	PORT0_PCNTR3_PORR07_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR07_1 = 0x1
	// Position of PORR08 field.
	PORT0_PCNTR3_PORR08_Pos = 0x18
	// Bit mask of PORR08 field.
	PORT0_PCNTR3_PORR08_Msk = 0x1000000
	// Bit PORR08.
	PORT0_PCNTR3_PORR08 = 0x1000000
	// No effect on output
	PORT0_PCNTR3_PORR08_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR08_1 = 0x1
	// Position of PORR09 field.
	PORT0_PCNTR3_PORR09_Pos = 0x19
	// Bit mask of PORR09 field.
	PORT0_PCNTR3_PORR09_Msk = 0x2000000
	// Bit PORR09.
	PORT0_PCNTR3_PORR09 = 0x2000000
	// No effect on output
	PORT0_PCNTR3_PORR09_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR09_1 = 0x1
	// Position of PORR10 field.
	PORT0_PCNTR3_PORR10_Pos = 0x1a
	// Bit mask of PORR10 field.
	PORT0_PCNTR3_PORR10_Msk = 0x4000000
	// Bit PORR10.
	PORT0_PCNTR3_PORR10 = 0x4000000
	// No effect on output
	PORT0_PCNTR3_PORR10_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR10_1 = 0x1
	// Position of PORR11 field.
	PORT0_PCNTR3_PORR11_Pos = 0x1b
	// Bit mask of PORR11 field.
	PORT0_PCNTR3_PORR11_Msk = 0x8000000
	// Bit PORR11.
	PORT0_PCNTR3_PORR11 = 0x8000000
	// No effect on output
	PORT0_PCNTR3_PORR11_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR11_1 = 0x1
	// Position of PORR12 field.
	PORT0_PCNTR3_PORR12_Pos = 0x1c
	// Bit mask of PORR12 field.
	PORT0_PCNTR3_PORR12_Msk = 0x10000000
	// Bit PORR12.
	PORT0_PCNTR3_PORR12 = 0x10000000
	// No effect on output
	PORT0_PCNTR3_PORR12_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR12_1 = 0x1
	// Position of PORR13 field.
	PORT0_PCNTR3_PORR13_Pos = 0x1d
	// Bit mask of PORR13 field.
	PORT0_PCNTR3_PORR13_Msk = 0x20000000
	// Bit PORR13.
	PORT0_PCNTR3_PORR13 = 0x20000000
	// No effect on output
	PORT0_PCNTR3_PORR13_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR13_1 = 0x1
	// Position of PORR14 field.
	PORT0_PCNTR3_PORR14_Pos = 0x1e
	// Bit mask of PORR14 field.
	PORT0_PCNTR3_PORR14_Msk = 0x40000000
	// Bit PORR14.
	PORT0_PCNTR3_PORR14 = 0x40000000
	// No effect on output
	PORT0_PCNTR3_PORR14_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR14_1 = 0x1
	// Position of PORR15 field.
	PORT0_PCNTR3_PORR15_Pos = 0x1f
	// Bit mask of PORR15 field.
	PORT0_PCNTR3_PORR15_Msk = 0x80000000
	// Bit PORR15.
	PORT0_PCNTR3_PORR15 = 0x80000000
	// No effect on output
	PORT0_PCNTR3_PORR15_0 = 0x0
	// Low output
	PORT0_PCNTR3_PORR15_1 = 0x1

	// PORR: Port Control Register 3
	// Position of PORR00 field.
	PORT0_PORR_PORR00_Pos = 0x0
	// Bit mask of PORR00 field.
	PORT0_PORR_PORR00_Msk = 0x1
	// Bit PORR00.
	PORT0_PORR_PORR00 = 0x1
	// No effect on output
	PORT0_PORR_PORR00_0 = 0x0
	// Low output
	PORT0_PORR_PORR00_1 = 0x1
	// Position of PORR01 field.
	PORT0_PORR_PORR01_Pos = 0x1
	// Bit mask of PORR01 field.
	PORT0_PORR_PORR01_Msk = 0x2
	// Bit PORR01.
	PORT0_PORR_PORR01 = 0x2
	// No effect on output
	PORT0_PORR_PORR01_0 = 0x0
	// Low output
	PORT0_PORR_PORR01_1 = 0x1
	// Position of PORR02 field.
	PORT0_PORR_PORR02_Pos = 0x2
	// Bit mask of PORR02 field.
	PORT0_PORR_PORR02_Msk = 0x4
	// Bit PORR02.
	PORT0_PORR_PORR02 = 0x4
	// No effect on output
	PORT0_PORR_PORR02_0 = 0x0
	// Low output
	PORT0_PORR_PORR02_1 = 0x1
	// Position of PORR03 field.
	PORT0_PORR_PORR03_Pos = 0x3
	// Bit mask of PORR03 field.
	PORT0_PORR_PORR03_Msk = 0x8
	// Bit PORR03.
	PORT0_PORR_PORR03 = 0x8
	// No effect on output
	PORT0_PORR_PORR03_0 = 0x0
	// Low output
	PORT0_PORR_PORR03_1 = 0x1
	// Position of PORR04 field.
	PORT0_PORR_PORR04_Pos = 0x4
	// Bit mask of PORR04 field.
	PORT0_PORR_PORR04_Msk = 0x10
	// Bit PORR04.
	PORT0_PORR_PORR04 = 0x10
	// No effect on output
	PORT0_PORR_PORR04_0 = 0x0
	// Low output
	PORT0_PORR_PORR04_1 = 0x1
	// Position of PORR05 field.
	PORT0_PORR_PORR05_Pos = 0x5
	// Bit mask of PORR05 field.
	PORT0_PORR_PORR05_Msk = 0x20
	// Bit PORR05.
	PORT0_PORR_PORR05 = 0x20
	// No effect on output
	PORT0_PORR_PORR05_0 = 0x0
	// Low output
	PORT0_PORR_PORR05_1 = 0x1
	// Position of PORR06 field.
	PORT0_PORR_PORR06_Pos = 0x6
	// Bit mask of PORR06 field.
	PORT0_PORR_PORR06_Msk = 0x40
	// Bit PORR06.
	PORT0_PORR_PORR06 = 0x40
	// No effect on output
	PORT0_PORR_PORR06_0 = 0x0
	// Low output
	PORT0_PORR_PORR06_1 = 0x1
	// Position of PORR07 field.
	PORT0_PORR_PORR07_Pos = 0x7
	// Bit mask of PORR07 field.
	PORT0_PORR_PORR07_Msk = 0x80
	// Bit PORR07.
	PORT0_PORR_PORR07 = 0x80
	// No effect on output
	PORT0_PORR_PORR07_0 = 0x0
	// Low output
	PORT0_PORR_PORR07_1 = 0x1
	// Position of PORR08 field.
	PORT0_PORR_PORR08_Pos = 0x8
	// Bit mask of PORR08 field.
	PORT0_PORR_PORR08_Msk = 0x100
	// Bit PORR08.
	PORT0_PORR_PORR08 = 0x100
	// No effect on output
	PORT0_PORR_PORR08_0 = 0x0
	// Low output
	PORT0_PORR_PORR08_1 = 0x1
	// Position of PORR09 field.
	PORT0_PORR_PORR09_Pos = 0x9
	// Bit mask of PORR09 field.
	PORT0_PORR_PORR09_Msk = 0x200
	// Bit PORR09.
	PORT0_PORR_PORR09 = 0x200
	// No effect on output
	PORT0_PORR_PORR09_0 = 0x0
	// Low output
	PORT0_PORR_PORR09_1 = 0x1
	// Position of PORR10 field.
	PORT0_PORR_PORR10_Pos = 0xa
	// Bit mask of PORR10 field.
	PORT0_PORR_PORR10_Msk = 0x400
	// Bit PORR10.
	PORT0_PORR_PORR10 = 0x400
	// No effect on output
	PORT0_PORR_PORR10_0 = 0x0
	// Low output
	PORT0_PORR_PORR10_1 = 0x1
	// Position of PORR11 field.
	PORT0_PORR_PORR11_Pos = 0xb
	// Bit mask of PORR11 field.
	PORT0_PORR_PORR11_Msk = 0x800
	// Bit PORR11.
	PORT0_PORR_PORR11 = 0x800
	// No effect on output
	PORT0_PORR_PORR11_0 = 0x0
	// Low output
	PORT0_PORR_PORR11_1 = 0x1
	// Position of PORR12 field.
	PORT0_PORR_PORR12_Pos = 0xc
	// Bit mask of PORR12 field.
	PORT0_PORR_PORR12_Msk = 0x1000
	// Bit PORR12.
	PORT0_PORR_PORR12 = 0x1000
	// No effect on output
	PORT0_PORR_PORR12_0 = 0x0
	// Low output
	PORT0_PORR_PORR12_1 = 0x1
	// Position of PORR13 field.
	PORT0_PORR_PORR13_Pos = 0xd
	// Bit mask of PORR13 field.
	PORT0_PORR_PORR13_Msk = 0x2000
	// Bit PORR13.
	PORT0_PORR_PORR13 = 0x2000
	// No effect on output
	PORT0_PORR_PORR13_0 = 0x0
	// Low output
	PORT0_PORR_PORR13_1 = 0x1
	// Position of PORR14 field.
	PORT0_PORR_PORR14_Pos = 0xe
	// Bit mask of PORR14 field.
	PORT0_PORR_PORR14_Msk = 0x4000
	// Bit PORR14.
	PORT0_PORR_PORR14 = 0x4000
	// No effect on output
	PORT0_PORR_PORR14_0 = 0x0
	// Low output
	PORT0_PORR_PORR14_1 = 0x1
	// Position of PORR15 field.
	PORT0_PORR_PORR15_Pos = 0xf
	// Bit mask of PORR15 field.
	PORT0_PORR_PORR15_Msk = 0x8000
	// Bit PORR15.
	PORT0_PORR_PORR15 = 0x8000
	// No effect on output
	PORT0_PORR_PORR15_0 = 0x0
	// Low output
	PORT0_PORR_PORR15_1 = 0x1

	// POSR: Port Control Register 3
	// Position of POSR00 field.
	PORT0_POSR_POSR00_Pos = 0x0
	// Bit mask of POSR00 field.
	PORT0_POSR_POSR00_Msk = 0x1
	// Bit POSR00.
	PORT0_POSR_POSR00 = 0x1
	// No effect on output
	PORT0_POSR_POSR00_0 = 0x0
	// High output
	PORT0_POSR_POSR00_1 = 0x1
	// Position of POSR01 field.
	PORT0_POSR_POSR01_Pos = 0x1
	// Bit mask of POSR01 field.
	PORT0_POSR_POSR01_Msk = 0x2
	// Bit POSR01.
	PORT0_POSR_POSR01 = 0x2
	// No effect on output
	PORT0_POSR_POSR01_0 = 0x0
	// High output
	PORT0_POSR_POSR01_1 = 0x1
	// Position of POSR02 field.
	PORT0_POSR_POSR02_Pos = 0x2
	// Bit mask of POSR02 field.
	PORT0_POSR_POSR02_Msk = 0x4
	// Bit POSR02.
	PORT0_POSR_POSR02 = 0x4
	// No effect on output
	PORT0_POSR_POSR02_0 = 0x0
	// High output
	PORT0_POSR_POSR02_1 = 0x1
	// Position of POSR03 field.
	PORT0_POSR_POSR03_Pos = 0x3
	// Bit mask of POSR03 field.
	PORT0_POSR_POSR03_Msk = 0x8
	// Bit POSR03.
	PORT0_POSR_POSR03 = 0x8
	// No effect on output
	PORT0_POSR_POSR03_0 = 0x0
	// High output
	PORT0_POSR_POSR03_1 = 0x1
	// Position of POSR04 field.
	PORT0_POSR_POSR04_Pos = 0x4
	// Bit mask of POSR04 field.
	PORT0_POSR_POSR04_Msk = 0x10
	// Bit POSR04.
	PORT0_POSR_POSR04 = 0x10
	// No effect on output
	PORT0_POSR_POSR04_0 = 0x0
	// High output
	PORT0_POSR_POSR04_1 = 0x1
	// Position of POSR05 field.
	PORT0_POSR_POSR05_Pos = 0x5
	// Bit mask of POSR05 field.
	PORT0_POSR_POSR05_Msk = 0x20
	// Bit POSR05.
	PORT0_POSR_POSR05 = 0x20
	// No effect on output
	PORT0_POSR_POSR05_0 = 0x0
	// High output
	PORT0_POSR_POSR05_1 = 0x1
	// Position of POSR06 field.
	PORT0_POSR_POSR06_Pos = 0x6
	// Bit mask of POSR06 field.
	PORT0_POSR_POSR06_Msk = 0x40
	// Bit POSR06.
	PORT0_POSR_POSR06 = 0x40
	// No effect on output
	PORT0_POSR_POSR06_0 = 0x0
	// High output
	PORT0_POSR_POSR06_1 = 0x1
	// Position of POSR07 field.
	PORT0_POSR_POSR07_Pos = 0x7
	// Bit mask of POSR07 field.
	PORT0_POSR_POSR07_Msk = 0x80
	// Bit POSR07.
	PORT0_POSR_POSR07 = 0x80
	// No effect on output
	PORT0_POSR_POSR07_0 = 0x0
	// High output
	PORT0_POSR_POSR07_1 = 0x1
	// Position of POSR08 field.
	PORT0_POSR_POSR08_Pos = 0x8
	// Bit mask of POSR08 field.
	PORT0_POSR_POSR08_Msk = 0x100
	// Bit POSR08.
	PORT0_POSR_POSR08 = 0x100
	// No effect on output
	PORT0_POSR_POSR08_0 = 0x0
	// High output
	PORT0_POSR_POSR08_1 = 0x1
	// Position of POSR09 field.
	PORT0_POSR_POSR09_Pos = 0x9
	// Bit mask of POSR09 field.
	PORT0_POSR_POSR09_Msk = 0x200
	// Bit POSR09.
	PORT0_POSR_POSR09 = 0x200
	// No effect on output
	PORT0_POSR_POSR09_0 = 0x0
	// High output
	PORT0_POSR_POSR09_1 = 0x1
	// Position of POSR10 field.
	PORT0_POSR_POSR10_Pos = 0xa
	// Bit mask of POSR10 field.
	PORT0_POSR_POSR10_Msk = 0x400
	// Bit POSR10.
	PORT0_POSR_POSR10 = 0x400
	// No effect on output
	PORT0_POSR_POSR10_0 = 0x0
	// High output
	PORT0_POSR_POSR10_1 = 0x1
	// Position of POSR11 field.
	PORT0_POSR_POSR11_Pos = 0xb
	// Bit mask of POSR11 field.
	PORT0_POSR_POSR11_Msk = 0x800
	// Bit POSR11.
	PORT0_POSR_POSR11 = 0x800
	// No effect on output
	PORT0_POSR_POSR11_0 = 0x0
	// High output
	PORT0_POSR_POSR11_1 = 0x1
	// Position of POSR12 field.
	PORT0_POSR_POSR12_Pos = 0xc
	// Bit mask of POSR12 field.
	PORT0_POSR_POSR12_Msk = 0x1000
	// Bit POSR12.
	PORT0_POSR_POSR12 = 0x1000
	// No effect on output
	PORT0_POSR_POSR12_0 = 0x0
	// High output
	PORT0_POSR_POSR12_1 = 0x1
	// Position of POSR13 field.
	PORT0_POSR_POSR13_Pos = 0xd
	// Bit mask of POSR13 field.
	PORT0_POSR_POSR13_Msk = 0x2000
	// Bit POSR13.
	PORT0_POSR_POSR13 = 0x2000
	// No effect on output
	PORT0_POSR_POSR13_0 = 0x0
	// High output
	PORT0_POSR_POSR13_1 = 0x1
	// Position of POSR14 field.
	PORT0_POSR_POSR14_Pos = 0xe
	// Bit mask of POSR14 field.
	PORT0_POSR_POSR14_Msk = 0x4000
	// Bit POSR14.
	PORT0_POSR_POSR14 = 0x4000
	// No effect on output
	PORT0_POSR_POSR14_0 = 0x0
	// High output
	PORT0_POSR_POSR14_1 = 0x1
	// Position of POSR15 field.
	PORT0_POSR_POSR15_Pos = 0xf
	// Bit mask of POSR15 field.
	PORT0_POSR_POSR15_Msk = 0x8000
	// Bit POSR15.
	PORT0_POSR_POSR15 = 0x8000
	// No effect on output
	PORT0_POSR_POSR15_0 = 0x0
	// High output
	PORT0_POSR_POSR15_1 = 0x1
)

// Constants for PORT1: Pmn Pin FunctionPort 1 Control RegistersPmn Pin Function Control Register
const (
	// PCNTR1: Port Control Register 1
	// Position of PDR00 field.
	PORT1_PCNTR1_PDR00_Pos = 0x0
	// Bit mask of PDR00 field.
	PORT1_PCNTR1_PDR00_Msk = 0x1
	// Bit PDR00.
	PORT1_PCNTR1_PDR00 = 0x1
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR00_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR00_1 = 0x1
	// Position of PDR01 field.
	PORT1_PCNTR1_PDR01_Pos = 0x1
	// Bit mask of PDR01 field.
	PORT1_PCNTR1_PDR01_Msk = 0x2
	// Bit PDR01.
	PORT1_PCNTR1_PDR01 = 0x2
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR01_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR01_1 = 0x1
	// Position of PDR02 field.
	PORT1_PCNTR1_PDR02_Pos = 0x2
	// Bit mask of PDR02 field.
	PORT1_PCNTR1_PDR02_Msk = 0x4
	// Bit PDR02.
	PORT1_PCNTR1_PDR02 = 0x4
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR02_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR02_1 = 0x1
	// Position of PDR03 field.
	PORT1_PCNTR1_PDR03_Pos = 0x3
	// Bit mask of PDR03 field.
	PORT1_PCNTR1_PDR03_Msk = 0x8
	// Bit PDR03.
	PORT1_PCNTR1_PDR03 = 0x8
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR03_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR03_1 = 0x1
	// Position of PDR04 field.
	PORT1_PCNTR1_PDR04_Pos = 0x4
	// Bit mask of PDR04 field.
	PORT1_PCNTR1_PDR04_Msk = 0x10
	// Bit PDR04.
	PORT1_PCNTR1_PDR04 = 0x10
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR04_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR04_1 = 0x1
	// Position of PDR05 field.
	PORT1_PCNTR1_PDR05_Pos = 0x5
	// Bit mask of PDR05 field.
	PORT1_PCNTR1_PDR05_Msk = 0x20
	// Bit PDR05.
	PORT1_PCNTR1_PDR05 = 0x20
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR05_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR05_1 = 0x1
	// Position of PDR06 field.
	PORT1_PCNTR1_PDR06_Pos = 0x6
	// Bit mask of PDR06 field.
	PORT1_PCNTR1_PDR06_Msk = 0x40
	// Bit PDR06.
	PORT1_PCNTR1_PDR06 = 0x40
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR06_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR06_1 = 0x1
	// Position of PDR07 field.
	PORT1_PCNTR1_PDR07_Pos = 0x7
	// Bit mask of PDR07 field.
	PORT1_PCNTR1_PDR07_Msk = 0x80
	// Bit PDR07.
	PORT1_PCNTR1_PDR07 = 0x80
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR07_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR07_1 = 0x1
	// Position of PDR08 field.
	PORT1_PCNTR1_PDR08_Pos = 0x8
	// Bit mask of PDR08 field.
	PORT1_PCNTR1_PDR08_Msk = 0x100
	// Bit PDR08.
	PORT1_PCNTR1_PDR08 = 0x100
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR08_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR08_1 = 0x1
	// Position of PDR09 field.
	PORT1_PCNTR1_PDR09_Pos = 0x9
	// Bit mask of PDR09 field.
	PORT1_PCNTR1_PDR09_Msk = 0x200
	// Bit PDR09.
	PORT1_PCNTR1_PDR09 = 0x200
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR09_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR09_1 = 0x1
	// Position of PDR10 field.
	PORT1_PCNTR1_PDR10_Pos = 0xa
	// Bit mask of PDR10 field.
	PORT1_PCNTR1_PDR10_Msk = 0x400
	// Bit PDR10.
	PORT1_PCNTR1_PDR10 = 0x400
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR10_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR10_1 = 0x1
	// Position of PDR11 field.
	PORT1_PCNTR1_PDR11_Pos = 0xb
	// Bit mask of PDR11 field.
	PORT1_PCNTR1_PDR11_Msk = 0x800
	// Bit PDR11.
	PORT1_PCNTR1_PDR11 = 0x800
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR11_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR11_1 = 0x1
	// Position of PDR12 field.
	PORT1_PCNTR1_PDR12_Pos = 0xc
	// Bit mask of PDR12 field.
	PORT1_PCNTR1_PDR12_Msk = 0x1000
	// Bit PDR12.
	PORT1_PCNTR1_PDR12 = 0x1000
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR12_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR12_1 = 0x1
	// Position of PDR13 field.
	PORT1_PCNTR1_PDR13_Pos = 0xd
	// Bit mask of PDR13 field.
	PORT1_PCNTR1_PDR13_Msk = 0x2000
	// Bit PDR13.
	PORT1_PCNTR1_PDR13 = 0x2000
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR13_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR13_1 = 0x1
	// Position of PDR14 field.
	PORT1_PCNTR1_PDR14_Pos = 0xe
	// Bit mask of PDR14 field.
	PORT1_PCNTR1_PDR14_Msk = 0x4000
	// Bit PDR14.
	PORT1_PCNTR1_PDR14 = 0x4000
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR14_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR14_1 = 0x1
	// Position of PDR15 field.
	PORT1_PCNTR1_PDR15_Pos = 0xf
	// Bit mask of PDR15 field.
	PORT1_PCNTR1_PDR15_Msk = 0x8000
	// Bit PDR15.
	PORT1_PCNTR1_PDR15 = 0x8000
	// Input (functions as an input pin)
	PORT1_PCNTR1_PDR15_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PCNTR1_PDR15_1 = 0x1
	// Position of PODR00 field.
	PORT1_PCNTR1_PODR00_Pos = 0x10
	// Bit mask of PODR00 field.
	PORT1_PCNTR1_PODR00_Msk = 0x10000
	// Bit PODR00.
	PORT1_PCNTR1_PODR00 = 0x10000
	// Low output
	PORT1_PCNTR1_PODR00_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR00_1 = 0x1
	// Position of PODR01 field.
	PORT1_PCNTR1_PODR01_Pos = 0x11
	// Bit mask of PODR01 field.
	PORT1_PCNTR1_PODR01_Msk = 0x20000
	// Bit PODR01.
	PORT1_PCNTR1_PODR01 = 0x20000
	// Low output
	PORT1_PCNTR1_PODR01_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR01_1 = 0x1
	// Position of PODR02 field.
	PORT1_PCNTR1_PODR02_Pos = 0x12
	// Bit mask of PODR02 field.
	PORT1_PCNTR1_PODR02_Msk = 0x40000
	// Bit PODR02.
	PORT1_PCNTR1_PODR02 = 0x40000
	// Low output
	PORT1_PCNTR1_PODR02_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR02_1 = 0x1
	// Position of PODR03 field.
	PORT1_PCNTR1_PODR03_Pos = 0x13
	// Bit mask of PODR03 field.
	PORT1_PCNTR1_PODR03_Msk = 0x80000
	// Bit PODR03.
	PORT1_PCNTR1_PODR03 = 0x80000
	// Low output
	PORT1_PCNTR1_PODR03_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR03_1 = 0x1
	// Position of PODR04 field.
	PORT1_PCNTR1_PODR04_Pos = 0x14
	// Bit mask of PODR04 field.
	PORT1_PCNTR1_PODR04_Msk = 0x100000
	// Bit PODR04.
	PORT1_PCNTR1_PODR04 = 0x100000
	// Low output
	PORT1_PCNTR1_PODR04_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR04_1 = 0x1
	// Position of PODR05 field.
	PORT1_PCNTR1_PODR05_Pos = 0x15
	// Bit mask of PODR05 field.
	PORT1_PCNTR1_PODR05_Msk = 0x200000
	// Bit PODR05.
	PORT1_PCNTR1_PODR05 = 0x200000
	// Low output
	PORT1_PCNTR1_PODR05_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR05_1 = 0x1
	// Position of PODR06 field.
	PORT1_PCNTR1_PODR06_Pos = 0x16
	// Bit mask of PODR06 field.
	PORT1_PCNTR1_PODR06_Msk = 0x400000
	// Bit PODR06.
	PORT1_PCNTR1_PODR06 = 0x400000
	// Low output
	PORT1_PCNTR1_PODR06_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR06_1 = 0x1
	// Position of PODR07 field.
	PORT1_PCNTR1_PODR07_Pos = 0x17
	// Bit mask of PODR07 field.
	PORT1_PCNTR1_PODR07_Msk = 0x800000
	// Bit PODR07.
	PORT1_PCNTR1_PODR07 = 0x800000
	// Low output
	PORT1_PCNTR1_PODR07_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR07_1 = 0x1
	// Position of PODR08 field.
	PORT1_PCNTR1_PODR08_Pos = 0x18
	// Bit mask of PODR08 field.
	PORT1_PCNTR1_PODR08_Msk = 0x1000000
	// Bit PODR08.
	PORT1_PCNTR1_PODR08 = 0x1000000
	// Low output
	PORT1_PCNTR1_PODR08_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR08_1 = 0x1
	// Position of PODR09 field.
	PORT1_PCNTR1_PODR09_Pos = 0x19
	// Bit mask of PODR09 field.
	PORT1_PCNTR1_PODR09_Msk = 0x2000000
	// Bit PODR09.
	PORT1_PCNTR1_PODR09 = 0x2000000
	// Low output
	PORT1_PCNTR1_PODR09_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR09_1 = 0x1
	// Position of PODR10 field.
	PORT1_PCNTR1_PODR10_Pos = 0x1a
	// Bit mask of PODR10 field.
	PORT1_PCNTR1_PODR10_Msk = 0x4000000
	// Bit PODR10.
	PORT1_PCNTR1_PODR10 = 0x4000000
	// Low output
	PORT1_PCNTR1_PODR10_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR10_1 = 0x1
	// Position of PODR11 field.
	PORT1_PCNTR1_PODR11_Pos = 0x1b
	// Bit mask of PODR11 field.
	PORT1_PCNTR1_PODR11_Msk = 0x8000000
	// Bit PODR11.
	PORT1_PCNTR1_PODR11 = 0x8000000
	// Low output
	PORT1_PCNTR1_PODR11_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR11_1 = 0x1
	// Position of PODR12 field.
	PORT1_PCNTR1_PODR12_Pos = 0x1c
	// Bit mask of PODR12 field.
	PORT1_PCNTR1_PODR12_Msk = 0x10000000
	// Bit PODR12.
	PORT1_PCNTR1_PODR12 = 0x10000000
	// Low output
	PORT1_PCNTR1_PODR12_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR12_1 = 0x1
	// Position of PODR13 field.
	PORT1_PCNTR1_PODR13_Pos = 0x1d
	// Bit mask of PODR13 field.
	PORT1_PCNTR1_PODR13_Msk = 0x20000000
	// Bit PODR13.
	PORT1_PCNTR1_PODR13 = 0x20000000
	// Low output
	PORT1_PCNTR1_PODR13_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR13_1 = 0x1
	// Position of PODR14 field.
	PORT1_PCNTR1_PODR14_Pos = 0x1e
	// Bit mask of PODR14 field.
	PORT1_PCNTR1_PODR14_Msk = 0x40000000
	// Bit PODR14.
	PORT1_PCNTR1_PODR14 = 0x40000000
	// Low output
	PORT1_PCNTR1_PODR14_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR14_1 = 0x1
	// Position of PODR15 field.
	PORT1_PCNTR1_PODR15_Pos = 0x1f
	// Bit mask of PODR15 field.
	PORT1_PCNTR1_PODR15_Msk = 0x80000000
	// Bit PODR15.
	PORT1_PCNTR1_PODR15 = 0x80000000
	// Low output
	PORT1_PCNTR1_PODR15_0 = 0x0
	// High output
	PORT1_PCNTR1_PODR15_1 = 0x1

	// PODR: Port Control Register 1
	// Position of PODR00 field.
	PORT1_PODR_PODR00_Pos = 0x0
	// Bit mask of PODR00 field.
	PORT1_PODR_PODR00_Msk = 0x1
	// Bit PODR00.
	PORT1_PODR_PODR00 = 0x1
	// Low output
	PORT1_PODR_PODR00_0 = 0x0
	// High output
	PORT1_PODR_PODR00_1 = 0x1
	// Position of PODR01 field.
	PORT1_PODR_PODR01_Pos = 0x1
	// Bit mask of PODR01 field.
	PORT1_PODR_PODR01_Msk = 0x2
	// Bit PODR01.
	PORT1_PODR_PODR01 = 0x2
	// Low output
	PORT1_PODR_PODR01_0 = 0x0
	// High output
	PORT1_PODR_PODR01_1 = 0x1
	// Position of PODR02 field.
	PORT1_PODR_PODR02_Pos = 0x2
	// Bit mask of PODR02 field.
	PORT1_PODR_PODR02_Msk = 0x4
	// Bit PODR02.
	PORT1_PODR_PODR02 = 0x4
	// Low output
	PORT1_PODR_PODR02_0 = 0x0
	// High output
	PORT1_PODR_PODR02_1 = 0x1
	// Position of PODR03 field.
	PORT1_PODR_PODR03_Pos = 0x3
	// Bit mask of PODR03 field.
	PORT1_PODR_PODR03_Msk = 0x8
	// Bit PODR03.
	PORT1_PODR_PODR03 = 0x8
	// Low output
	PORT1_PODR_PODR03_0 = 0x0
	// High output
	PORT1_PODR_PODR03_1 = 0x1
	// Position of PODR04 field.
	PORT1_PODR_PODR04_Pos = 0x4
	// Bit mask of PODR04 field.
	PORT1_PODR_PODR04_Msk = 0x10
	// Bit PODR04.
	PORT1_PODR_PODR04 = 0x10
	// Low output
	PORT1_PODR_PODR04_0 = 0x0
	// High output
	PORT1_PODR_PODR04_1 = 0x1
	// Position of PODR05 field.
	PORT1_PODR_PODR05_Pos = 0x5
	// Bit mask of PODR05 field.
	PORT1_PODR_PODR05_Msk = 0x20
	// Bit PODR05.
	PORT1_PODR_PODR05 = 0x20
	// Low output
	PORT1_PODR_PODR05_0 = 0x0
	// High output
	PORT1_PODR_PODR05_1 = 0x1
	// Position of PODR06 field.
	PORT1_PODR_PODR06_Pos = 0x6
	// Bit mask of PODR06 field.
	PORT1_PODR_PODR06_Msk = 0x40
	// Bit PODR06.
	PORT1_PODR_PODR06 = 0x40
	// Low output
	PORT1_PODR_PODR06_0 = 0x0
	// High output
	PORT1_PODR_PODR06_1 = 0x1
	// Position of PODR07 field.
	PORT1_PODR_PODR07_Pos = 0x7
	// Bit mask of PODR07 field.
	PORT1_PODR_PODR07_Msk = 0x80
	// Bit PODR07.
	PORT1_PODR_PODR07 = 0x80
	// Low output
	PORT1_PODR_PODR07_0 = 0x0
	// High output
	PORT1_PODR_PODR07_1 = 0x1
	// Position of PODR08 field.
	PORT1_PODR_PODR08_Pos = 0x8
	// Bit mask of PODR08 field.
	PORT1_PODR_PODR08_Msk = 0x100
	// Bit PODR08.
	PORT1_PODR_PODR08 = 0x100
	// Low output
	PORT1_PODR_PODR08_0 = 0x0
	// High output
	PORT1_PODR_PODR08_1 = 0x1
	// Position of PODR09 field.
	PORT1_PODR_PODR09_Pos = 0x9
	// Bit mask of PODR09 field.
	PORT1_PODR_PODR09_Msk = 0x200
	// Bit PODR09.
	PORT1_PODR_PODR09 = 0x200
	// Low output
	PORT1_PODR_PODR09_0 = 0x0
	// High output
	PORT1_PODR_PODR09_1 = 0x1
	// Position of PODR10 field.
	PORT1_PODR_PODR10_Pos = 0xa
	// Bit mask of PODR10 field.
	PORT1_PODR_PODR10_Msk = 0x400
	// Bit PODR10.
	PORT1_PODR_PODR10 = 0x400
	// Low output
	PORT1_PODR_PODR10_0 = 0x0
	// High output
	PORT1_PODR_PODR10_1 = 0x1
	// Position of PODR11 field.
	PORT1_PODR_PODR11_Pos = 0xb
	// Bit mask of PODR11 field.
	PORT1_PODR_PODR11_Msk = 0x800
	// Bit PODR11.
	PORT1_PODR_PODR11 = 0x800
	// Low output
	PORT1_PODR_PODR11_0 = 0x0
	// High output
	PORT1_PODR_PODR11_1 = 0x1
	// Position of PODR12 field.
	PORT1_PODR_PODR12_Pos = 0xc
	// Bit mask of PODR12 field.
	PORT1_PODR_PODR12_Msk = 0x1000
	// Bit PODR12.
	PORT1_PODR_PODR12 = 0x1000
	// Low output
	PORT1_PODR_PODR12_0 = 0x0
	// High output
	PORT1_PODR_PODR12_1 = 0x1
	// Position of PODR13 field.
	PORT1_PODR_PODR13_Pos = 0xd
	// Bit mask of PODR13 field.
	PORT1_PODR_PODR13_Msk = 0x2000
	// Bit PODR13.
	PORT1_PODR_PODR13 = 0x2000
	// Low output
	PORT1_PODR_PODR13_0 = 0x0
	// High output
	PORT1_PODR_PODR13_1 = 0x1
	// Position of PODR14 field.
	PORT1_PODR_PODR14_Pos = 0xe
	// Bit mask of PODR14 field.
	PORT1_PODR_PODR14_Msk = 0x4000
	// Bit PODR14.
	PORT1_PODR_PODR14 = 0x4000
	// Low output
	PORT1_PODR_PODR14_0 = 0x0
	// High output
	PORT1_PODR_PODR14_1 = 0x1
	// Position of PODR15 field.
	PORT1_PODR_PODR15_Pos = 0xf
	// Bit mask of PODR15 field.
	PORT1_PODR_PODR15_Msk = 0x8000
	// Bit PODR15.
	PORT1_PODR_PODR15 = 0x8000
	// Low output
	PORT1_PODR_PODR15_0 = 0x0
	// High output
	PORT1_PODR_PODR15_1 = 0x1

	// PDR: Port Control Register 1
	// Position of PDR00 field.
	PORT1_PDR_PDR00_Pos = 0x0
	// Bit mask of PDR00 field.
	PORT1_PDR_PDR00_Msk = 0x1
	// Bit PDR00.
	PORT1_PDR_PDR00 = 0x1
	// Input (functions as an input pin)
	PORT1_PDR_PDR00_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR00_1 = 0x1
	// Position of PDR01 field.
	PORT1_PDR_PDR01_Pos = 0x1
	// Bit mask of PDR01 field.
	PORT1_PDR_PDR01_Msk = 0x2
	// Bit PDR01.
	PORT1_PDR_PDR01 = 0x2
	// Input (functions as an input pin)
	PORT1_PDR_PDR01_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR01_1 = 0x1
	// Position of PDR02 field.
	PORT1_PDR_PDR02_Pos = 0x2
	// Bit mask of PDR02 field.
	PORT1_PDR_PDR02_Msk = 0x4
	// Bit PDR02.
	PORT1_PDR_PDR02 = 0x4
	// Input (functions as an input pin)
	PORT1_PDR_PDR02_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR02_1 = 0x1
	// Position of PDR03 field.
	PORT1_PDR_PDR03_Pos = 0x3
	// Bit mask of PDR03 field.
	PORT1_PDR_PDR03_Msk = 0x8
	// Bit PDR03.
	PORT1_PDR_PDR03 = 0x8
	// Input (functions as an input pin)
	PORT1_PDR_PDR03_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR03_1 = 0x1
	// Position of PDR04 field.
	PORT1_PDR_PDR04_Pos = 0x4
	// Bit mask of PDR04 field.
	PORT1_PDR_PDR04_Msk = 0x10
	// Bit PDR04.
	PORT1_PDR_PDR04 = 0x10
	// Input (functions as an input pin)
	PORT1_PDR_PDR04_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR04_1 = 0x1
	// Position of PDR05 field.
	PORT1_PDR_PDR05_Pos = 0x5
	// Bit mask of PDR05 field.
	PORT1_PDR_PDR05_Msk = 0x20
	// Bit PDR05.
	PORT1_PDR_PDR05 = 0x20
	// Input (functions as an input pin)
	PORT1_PDR_PDR05_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR05_1 = 0x1
	// Position of PDR06 field.
	PORT1_PDR_PDR06_Pos = 0x6
	// Bit mask of PDR06 field.
	PORT1_PDR_PDR06_Msk = 0x40
	// Bit PDR06.
	PORT1_PDR_PDR06 = 0x40
	// Input (functions as an input pin)
	PORT1_PDR_PDR06_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR06_1 = 0x1
	// Position of PDR07 field.
	PORT1_PDR_PDR07_Pos = 0x7
	// Bit mask of PDR07 field.
	PORT1_PDR_PDR07_Msk = 0x80
	// Bit PDR07.
	PORT1_PDR_PDR07 = 0x80
	// Input (functions as an input pin)
	PORT1_PDR_PDR07_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR07_1 = 0x1
	// Position of PDR08 field.
	PORT1_PDR_PDR08_Pos = 0x8
	// Bit mask of PDR08 field.
	PORT1_PDR_PDR08_Msk = 0x100
	// Bit PDR08.
	PORT1_PDR_PDR08 = 0x100
	// Input (functions as an input pin)
	PORT1_PDR_PDR08_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR08_1 = 0x1
	// Position of PDR09 field.
	PORT1_PDR_PDR09_Pos = 0x9
	// Bit mask of PDR09 field.
	PORT1_PDR_PDR09_Msk = 0x200
	// Bit PDR09.
	PORT1_PDR_PDR09 = 0x200
	// Input (functions as an input pin)
	PORT1_PDR_PDR09_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR09_1 = 0x1
	// Position of PDR10 field.
	PORT1_PDR_PDR10_Pos = 0xa
	// Bit mask of PDR10 field.
	PORT1_PDR_PDR10_Msk = 0x400
	// Bit PDR10.
	PORT1_PDR_PDR10 = 0x400
	// Input (functions as an input pin)
	PORT1_PDR_PDR10_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR10_1 = 0x1
	// Position of PDR11 field.
	PORT1_PDR_PDR11_Pos = 0xb
	// Bit mask of PDR11 field.
	PORT1_PDR_PDR11_Msk = 0x800
	// Bit PDR11.
	PORT1_PDR_PDR11 = 0x800
	// Input (functions as an input pin)
	PORT1_PDR_PDR11_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR11_1 = 0x1
	// Position of PDR12 field.
	PORT1_PDR_PDR12_Pos = 0xc
	// Bit mask of PDR12 field.
	PORT1_PDR_PDR12_Msk = 0x1000
	// Bit PDR12.
	PORT1_PDR_PDR12 = 0x1000
	// Input (functions as an input pin)
	PORT1_PDR_PDR12_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR12_1 = 0x1
	// Position of PDR13 field.
	PORT1_PDR_PDR13_Pos = 0xd
	// Bit mask of PDR13 field.
	PORT1_PDR_PDR13_Msk = 0x2000
	// Bit PDR13.
	PORT1_PDR_PDR13 = 0x2000
	// Input (functions as an input pin)
	PORT1_PDR_PDR13_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR13_1 = 0x1
	// Position of PDR14 field.
	PORT1_PDR_PDR14_Pos = 0xe
	// Bit mask of PDR14 field.
	PORT1_PDR_PDR14_Msk = 0x4000
	// Bit PDR14.
	PORT1_PDR_PDR14 = 0x4000
	// Input (functions as an input pin)
	PORT1_PDR_PDR14_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR14_1 = 0x1
	// Position of PDR15 field.
	PORT1_PDR_PDR15_Pos = 0xf
	// Bit mask of PDR15 field.
	PORT1_PDR_PDR15_Msk = 0x8000
	// Bit PDR15.
	PORT1_PDR_PDR15 = 0x8000
	// Input (functions as an input pin)
	PORT1_PDR_PDR15_0 = 0x0
	// Output (functions as an output pin)
	PORT1_PDR_PDR15_1 = 0x1

	// PCNTR2: Port Control Register 2
	// Position of PIDR00 field.
	PORT1_PCNTR2_PIDR00_Pos = 0x0
	// Bit mask of PIDR00 field.
	PORT1_PCNTR2_PIDR00_Msk = 0x1
	// Bit PIDR00.
	PORT1_PCNTR2_PIDR00 = 0x1
	// Low level
	PORT1_PCNTR2_PIDR00_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR00_1 = 0x1
	// Position of PIDR01 field.
	PORT1_PCNTR2_PIDR01_Pos = 0x1
	// Bit mask of PIDR01 field.
	PORT1_PCNTR2_PIDR01_Msk = 0x2
	// Bit PIDR01.
	PORT1_PCNTR2_PIDR01 = 0x2
	// Low level
	PORT1_PCNTR2_PIDR01_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR01_1 = 0x1
	// Position of PIDR02 field.
	PORT1_PCNTR2_PIDR02_Pos = 0x2
	// Bit mask of PIDR02 field.
	PORT1_PCNTR2_PIDR02_Msk = 0x4
	// Bit PIDR02.
	PORT1_PCNTR2_PIDR02 = 0x4
	// Low level
	PORT1_PCNTR2_PIDR02_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR02_1 = 0x1
	// Position of PIDR03 field.
	PORT1_PCNTR2_PIDR03_Pos = 0x3
	// Bit mask of PIDR03 field.
	PORT1_PCNTR2_PIDR03_Msk = 0x8
	// Bit PIDR03.
	PORT1_PCNTR2_PIDR03 = 0x8
	// Low level
	PORT1_PCNTR2_PIDR03_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR03_1 = 0x1
	// Position of PIDR04 field.
	PORT1_PCNTR2_PIDR04_Pos = 0x4
	// Bit mask of PIDR04 field.
	PORT1_PCNTR2_PIDR04_Msk = 0x10
	// Bit PIDR04.
	PORT1_PCNTR2_PIDR04 = 0x10
	// Low level
	PORT1_PCNTR2_PIDR04_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR04_1 = 0x1
	// Position of PIDR05 field.
	PORT1_PCNTR2_PIDR05_Pos = 0x5
	// Bit mask of PIDR05 field.
	PORT1_PCNTR2_PIDR05_Msk = 0x20
	// Bit PIDR05.
	PORT1_PCNTR2_PIDR05 = 0x20
	// Low level
	PORT1_PCNTR2_PIDR05_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR05_1 = 0x1
	// Position of PIDR06 field.
	PORT1_PCNTR2_PIDR06_Pos = 0x6
	// Bit mask of PIDR06 field.
	PORT1_PCNTR2_PIDR06_Msk = 0x40
	// Bit PIDR06.
	PORT1_PCNTR2_PIDR06 = 0x40
	// Low level
	PORT1_PCNTR2_PIDR06_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR06_1 = 0x1
	// Position of PIDR07 field.
	PORT1_PCNTR2_PIDR07_Pos = 0x7
	// Bit mask of PIDR07 field.
	PORT1_PCNTR2_PIDR07_Msk = 0x80
	// Bit PIDR07.
	PORT1_PCNTR2_PIDR07 = 0x80
	// Low level
	PORT1_PCNTR2_PIDR07_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR07_1 = 0x1
	// Position of PIDR08 field.
	PORT1_PCNTR2_PIDR08_Pos = 0x8
	// Bit mask of PIDR08 field.
	PORT1_PCNTR2_PIDR08_Msk = 0x100
	// Bit PIDR08.
	PORT1_PCNTR2_PIDR08 = 0x100
	// Low level
	PORT1_PCNTR2_PIDR08_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR08_1 = 0x1
	// Position of PIDR09 field.
	PORT1_PCNTR2_PIDR09_Pos = 0x9
	// Bit mask of PIDR09 field.
	PORT1_PCNTR2_PIDR09_Msk = 0x200
	// Bit PIDR09.
	PORT1_PCNTR2_PIDR09 = 0x200
	// Low level
	PORT1_PCNTR2_PIDR09_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR09_1 = 0x1
	// Position of PIDR10 field.
	PORT1_PCNTR2_PIDR10_Pos = 0xa
	// Bit mask of PIDR10 field.
	PORT1_PCNTR2_PIDR10_Msk = 0x400
	// Bit PIDR10.
	PORT1_PCNTR2_PIDR10 = 0x400
	// Low level
	PORT1_PCNTR2_PIDR10_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR10_1 = 0x1
	// Position of PIDR11 field.
	PORT1_PCNTR2_PIDR11_Pos = 0xb
	// Bit mask of PIDR11 field.
	PORT1_PCNTR2_PIDR11_Msk = 0x800
	// Bit PIDR11.
	PORT1_PCNTR2_PIDR11 = 0x800
	// Low level
	PORT1_PCNTR2_PIDR11_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR11_1 = 0x1
	// Position of PIDR12 field.
	PORT1_PCNTR2_PIDR12_Pos = 0xc
	// Bit mask of PIDR12 field.
	PORT1_PCNTR2_PIDR12_Msk = 0x1000
	// Bit PIDR12.
	PORT1_PCNTR2_PIDR12 = 0x1000
	// Low level
	PORT1_PCNTR2_PIDR12_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR12_1 = 0x1
	// Position of PIDR13 field.
	PORT1_PCNTR2_PIDR13_Pos = 0xd
	// Bit mask of PIDR13 field.
	PORT1_PCNTR2_PIDR13_Msk = 0x2000
	// Bit PIDR13.
	PORT1_PCNTR2_PIDR13 = 0x2000
	// Low level
	PORT1_PCNTR2_PIDR13_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR13_1 = 0x1
	// Position of PIDR14 field.
	PORT1_PCNTR2_PIDR14_Pos = 0xe
	// Bit mask of PIDR14 field.
	PORT1_PCNTR2_PIDR14_Msk = 0x4000
	// Bit PIDR14.
	PORT1_PCNTR2_PIDR14 = 0x4000
	// Low level
	PORT1_PCNTR2_PIDR14_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR14_1 = 0x1
	// Position of PIDR15 field.
	PORT1_PCNTR2_PIDR15_Pos = 0xf
	// Bit mask of PIDR15 field.
	PORT1_PCNTR2_PIDR15_Msk = 0x8000
	// Bit PIDR15.
	PORT1_PCNTR2_PIDR15 = 0x8000
	// Low level
	PORT1_PCNTR2_PIDR15_0 = 0x0
	// High level
	PORT1_PCNTR2_PIDR15_1 = 0x1
	// Position of EIDR00 field.
	PORT1_PCNTR2_EIDR00_Pos = 0x10
	// Bit mask of EIDR00 field.
	PORT1_PCNTR2_EIDR00_Msk = 0x10000
	// Bit EIDR00.
	PORT1_PCNTR2_EIDR00 = 0x10000
	// Low input
	PORT1_PCNTR2_EIDR00_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR00_1 = 0x1
	// Position of EIDR01 field.
	PORT1_PCNTR2_EIDR01_Pos = 0x11
	// Bit mask of EIDR01 field.
	PORT1_PCNTR2_EIDR01_Msk = 0x20000
	// Bit EIDR01.
	PORT1_PCNTR2_EIDR01 = 0x20000
	// Low input
	PORT1_PCNTR2_EIDR01_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR01_1 = 0x1
	// Position of EIDR02 field.
	PORT1_PCNTR2_EIDR02_Pos = 0x12
	// Bit mask of EIDR02 field.
	PORT1_PCNTR2_EIDR02_Msk = 0x40000
	// Bit EIDR02.
	PORT1_PCNTR2_EIDR02 = 0x40000
	// Low input
	PORT1_PCNTR2_EIDR02_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR02_1 = 0x1
	// Position of EIDR03 field.
	PORT1_PCNTR2_EIDR03_Pos = 0x13
	// Bit mask of EIDR03 field.
	PORT1_PCNTR2_EIDR03_Msk = 0x80000
	// Bit EIDR03.
	PORT1_PCNTR2_EIDR03 = 0x80000
	// Low input
	PORT1_PCNTR2_EIDR03_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR03_1 = 0x1
	// Position of EIDR04 field.
	PORT1_PCNTR2_EIDR04_Pos = 0x14
	// Bit mask of EIDR04 field.
	PORT1_PCNTR2_EIDR04_Msk = 0x100000
	// Bit EIDR04.
	PORT1_PCNTR2_EIDR04 = 0x100000
	// Low input
	PORT1_PCNTR2_EIDR04_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR04_1 = 0x1
	// Position of EIDR05 field.
	PORT1_PCNTR2_EIDR05_Pos = 0x15
	// Bit mask of EIDR05 field.
	PORT1_PCNTR2_EIDR05_Msk = 0x200000
	// Bit EIDR05.
	PORT1_PCNTR2_EIDR05 = 0x200000
	// Low input
	PORT1_PCNTR2_EIDR05_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR05_1 = 0x1
	// Position of EIDR06 field.
	PORT1_PCNTR2_EIDR06_Pos = 0x16
	// Bit mask of EIDR06 field.
	PORT1_PCNTR2_EIDR06_Msk = 0x400000
	// Bit EIDR06.
	PORT1_PCNTR2_EIDR06 = 0x400000
	// Low input
	PORT1_PCNTR2_EIDR06_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR06_1 = 0x1
	// Position of EIDR07 field.
	PORT1_PCNTR2_EIDR07_Pos = 0x17
	// Bit mask of EIDR07 field.
	PORT1_PCNTR2_EIDR07_Msk = 0x800000
	// Bit EIDR07.
	PORT1_PCNTR2_EIDR07 = 0x800000
	// Low input
	PORT1_PCNTR2_EIDR07_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR07_1 = 0x1
	// Position of EIDR08 field.
	PORT1_PCNTR2_EIDR08_Pos = 0x18
	// Bit mask of EIDR08 field.
	PORT1_PCNTR2_EIDR08_Msk = 0x1000000
	// Bit EIDR08.
	PORT1_PCNTR2_EIDR08 = 0x1000000
	// Low input
	PORT1_PCNTR2_EIDR08_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR08_1 = 0x1
	// Position of EIDR09 field.
	PORT1_PCNTR2_EIDR09_Pos = 0x19
	// Bit mask of EIDR09 field.
	PORT1_PCNTR2_EIDR09_Msk = 0x2000000
	// Bit EIDR09.
	PORT1_PCNTR2_EIDR09 = 0x2000000
	// Low input
	PORT1_PCNTR2_EIDR09_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR09_1 = 0x1
	// Position of EIDR10 field.
	PORT1_PCNTR2_EIDR10_Pos = 0x1a
	// Bit mask of EIDR10 field.
	PORT1_PCNTR2_EIDR10_Msk = 0x4000000
	// Bit EIDR10.
	PORT1_PCNTR2_EIDR10 = 0x4000000
	// Low input
	PORT1_PCNTR2_EIDR10_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR10_1 = 0x1
	// Position of EIDR11 field.
	PORT1_PCNTR2_EIDR11_Pos = 0x1b
	// Bit mask of EIDR11 field.
	PORT1_PCNTR2_EIDR11_Msk = 0x8000000
	// Bit EIDR11.
	PORT1_PCNTR2_EIDR11 = 0x8000000
	// Low input
	PORT1_PCNTR2_EIDR11_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR11_1 = 0x1
	// Position of EIDR12 field.
	PORT1_PCNTR2_EIDR12_Pos = 0x1c
	// Bit mask of EIDR12 field.
	PORT1_PCNTR2_EIDR12_Msk = 0x10000000
	// Bit EIDR12.
	PORT1_PCNTR2_EIDR12 = 0x10000000
	// Low input
	PORT1_PCNTR2_EIDR12_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR12_1 = 0x1
	// Position of EIDR13 field.
	PORT1_PCNTR2_EIDR13_Pos = 0x1d
	// Bit mask of EIDR13 field.
	PORT1_PCNTR2_EIDR13_Msk = 0x20000000
	// Bit EIDR13.
	PORT1_PCNTR2_EIDR13 = 0x20000000
	// Low input
	PORT1_PCNTR2_EIDR13_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR13_1 = 0x1
	// Position of EIDR14 field.
	PORT1_PCNTR2_EIDR14_Pos = 0x1e
	// Bit mask of EIDR14 field.
	PORT1_PCNTR2_EIDR14_Msk = 0x40000000
	// Bit EIDR14.
	PORT1_PCNTR2_EIDR14 = 0x40000000
	// Low input
	PORT1_PCNTR2_EIDR14_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR14_1 = 0x1
	// Position of EIDR15 field.
	PORT1_PCNTR2_EIDR15_Pos = 0x1f
	// Bit mask of EIDR15 field.
	PORT1_PCNTR2_EIDR15_Msk = 0x80000000
	// Bit EIDR15.
	PORT1_PCNTR2_EIDR15 = 0x80000000
	// Low input
	PORT1_PCNTR2_EIDR15_0 = 0x0
	// High input
	PORT1_PCNTR2_EIDR15_1 = 0x1

	// EIDR: Port Control Register 2
	// Position of EIDR00 field.
	PORT1_EIDR_EIDR00_Pos = 0x0
	// Bit mask of EIDR00 field.
	PORT1_EIDR_EIDR00_Msk = 0x1
	// Bit EIDR00.
	PORT1_EIDR_EIDR00 = 0x1
	// Low input
	PORT1_EIDR_EIDR00_0 = 0x0
	// High input
	PORT1_EIDR_EIDR00_1 = 0x1
	// Position of EIDR01 field.
	PORT1_EIDR_EIDR01_Pos = 0x1
	// Bit mask of EIDR01 field.
	PORT1_EIDR_EIDR01_Msk = 0x2
	// Bit EIDR01.
	PORT1_EIDR_EIDR01 = 0x2
	// Low input
	PORT1_EIDR_EIDR01_0 = 0x0
	// High input
	PORT1_EIDR_EIDR01_1 = 0x1
	// Position of EIDR02 field.
	PORT1_EIDR_EIDR02_Pos = 0x2
	// Bit mask of EIDR02 field.
	PORT1_EIDR_EIDR02_Msk = 0x4
	// Bit EIDR02.
	PORT1_EIDR_EIDR02 = 0x4
	// Low input
	PORT1_EIDR_EIDR02_0 = 0x0
	// High input
	PORT1_EIDR_EIDR02_1 = 0x1
	// Position of EIDR03 field.
	PORT1_EIDR_EIDR03_Pos = 0x3
	// Bit mask of EIDR03 field.
	PORT1_EIDR_EIDR03_Msk = 0x8
	// Bit EIDR03.
	PORT1_EIDR_EIDR03 = 0x8
	// Low input
	PORT1_EIDR_EIDR03_0 = 0x0
	// High input
	PORT1_EIDR_EIDR03_1 = 0x1
	// Position of EIDR04 field.
	PORT1_EIDR_EIDR04_Pos = 0x4
	// Bit mask of EIDR04 field.
	PORT1_EIDR_EIDR04_Msk = 0x10
	// Bit EIDR04.
	PORT1_EIDR_EIDR04 = 0x10
	// Low input
	PORT1_EIDR_EIDR04_0 = 0x0
	// High input
	PORT1_EIDR_EIDR04_1 = 0x1
	// Position of EIDR05 field.
	PORT1_EIDR_EIDR05_Pos = 0x5
	// Bit mask of EIDR05 field.
	PORT1_EIDR_EIDR05_Msk = 0x20
	// Bit EIDR05.
	PORT1_EIDR_EIDR05 = 0x20
	// Low input
	PORT1_EIDR_EIDR05_0 = 0x0
	// High input
	PORT1_EIDR_EIDR05_1 = 0x1
	// Position of EIDR06 field.
	PORT1_EIDR_EIDR06_Pos = 0x6
	// Bit mask of EIDR06 field.
	PORT1_EIDR_EIDR06_Msk = 0x40
	// Bit EIDR06.
	PORT1_EIDR_EIDR06 = 0x40
	// Low input
	PORT1_EIDR_EIDR06_0 = 0x0
	// High input
	PORT1_EIDR_EIDR06_1 = 0x1
	// Position of EIDR07 field.
	PORT1_EIDR_EIDR07_Pos = 0x7
	// Bit mask of EIDR07 field.
	PORT1_EIDR_EIDR07_Msk = 0x80
	// Bit EIDR07.
	PORT1_EIDR_EIDR07 = 0x80
	// Low input
	PORT1_EIDR_EIDR07_0 = 0x0
	// High input
	PORT1_EIDR_EIDR07_1 = 0x1
	// Position of EIDR08 field.
	PORT1_EIDR_EIDR08_Pos = 0x8
	// Bit mask of EIDR08 field.
	PORT1_EIDR_EIDR08_Msk = 0x100
	// Bit EIDR08.
	PORT1_EIDR_EIDR08 = 0x100
	// Low input
	PORT1_EIDR_EIDR08_0 = 0x0
	// High input
	PORT1_EIDR_EIDR08_1 = 0x1
	// Position of EIDR09 field.
	PORT1_EIDR_EIDR09_Pos = 0x9
	// Bit mask of EIDR09 field.
	PORT1_EIDR_EIDR09_Msk = 0x200
	// Bit EIDR09.
	PORT1_EIDR_EIDR09 = 0x200
	// Low input
	PORT1_EIDR_EIDR09_0 = 0x0
	// High input
	PORT1_EIDR_EIDR09_1 = 0x1
	// Position of EIDR10 field.
	PORT1_EIDR_EIDR10_Pos = 0xa
	// Bit mask of EIDR10 field.
	PORT1_EIDR_EIDR10_Msk = 0x400
	// Bit EIDR10.
	PORT1_EIDR_EIDR10 = 0x400
	// Low input
	PORT1_EIDR_EIDR10_0 = 0x0
	// High input
	PORT1_EIDR_EIDR10_1 = 0x1
	// Position of EIDR11 field.
	PORT1_EIDR_EIDR11_Pos = 0xb
	// Bit mask of EIDR11 field.
	PORT1_EIDR_EIDR11_Msk = 0x800
	// Bit EIDR11.
	PORT1_EIDR_EIDR11 = 0x800
	// Low input
	PORT1_EIDR_EIDR11_0 = 0x0
	// High input
	PORT1_EIDR_EIDR11_1 = 0x1
	// Position of EIDR12 field.
	PORT1_EIDR_EIDR12_Pos = 0xc
	// Bit mask of EIDR12 field.
	PORT1_EIDR_EIDR12_Msk = 0x1000
	// Bit EIDR12.
	PORT1_EIDR_EIDR12 = 0x1000
	// Low input
	PORT1_EIDR_EIDR12_0 = 0x0
	// High input
	PORT1_EIDR_EIDR12_1 = 0x1
	// Position of EIDR13 field.
	PORT1_EIDR_EIDR13_Pos = 0xd
	// Bit mask of EIDR13 field.
	PORT1_EIDR_EIDR13_Msk = 0x2000
	// Bit EIDR13.
	PORT1_EIDR_EIDR13 = 0x2000
	// Low input
	PORT1_EIDR_EIDR13_0 = 0x0
	// High input
	PORT1_EIDR_EIDR13_1 = 0x1
	// Position of EIDR14 field.
	PORT1_EIDR_EIDR14_Pos = 0xe
	// Bit mask of EIDR14 field.
	PORT1_EIDR_EIDR14_Msk = 0x4000
	// Bit EIDR14.
	PORT1_EIDR_EIDR14 = 0x4000
	// Low input
	PORT1_EIDR_EIDR14_0 = 0x0
	// High input
	PORT1_EIDR_EIDR14_1 = 0x1
	// Position of EIDR15 field.
	PORT1_EIDR_EIDR15_Pos = 0xf
	// Bit mask of EIDR15 field.
	PORT1_EIDR_EIDR15_Msk = 0x8000
	// Bit EIDR15.
	PORT1_EIDR_EIDR15 = 0x8000
	// Low input
	PORT1_EIDR_EIDR15_0 = 0x0
	// High input
	PORT1_EIDR_EIDR15_1 = 0x1

	// PIDR: Port Control Register 2
	// Position of PIDR00 field.
	PORT1_PIDR_PIDR00_Pos = 0x0
	// Bit mask of PIDR00 field.
	PORT1_PIDR_PIDR00_Msk = 0x1
	// Bit PIDR00.
	PORT1_PIDR_PIDR00 = 0x1
	// Low level
	PORT1_PIDR_PIDR00_0 = 0x0
	// High level
	PORT1_PIDR_PIDR00_1 = 0x1
	// Position of PIDR01 field.
	PORT1_PIDR_PIDR01_Pos = 0x1
	// Bit mask of PIDR01 field.
	PORT1_PIDR_PIDR01_Msk = 0x2
	// Bit PIDR01.
	PORT1_PIDR_PIDR01 = 0x2
	// Low level
	PORT1_PIDR_PIDR01_0 = 0x0
	// High level
	PORT1_PIDR_PIDR01_1 = 0x1
	// Position of PIDR02 field.
	PORT1_PIDR_PIDR02_Pos = 0x2
	// Bit mask of PIDR02 field.
	PORT1_PIDR_PIDR02_Msk = 0x4
	// Bit PIDR02.
	PORT1_PIDR_PIDR02 = 0x4
	// Low level
	PORT1_PIDR_PIDR02_0 = 0x0
	// High level
	PORT1_PIDR_PIDR02_1 = 0x1
	// Position of PIDR03 field.
	PORT1_PIDR_PIDR03_Pos = 0x3
	// Bit mask of PIDR03 field.
	PORT1_PIDR_PIDR03_Msk = 0x8
	// Bit PIDR03.
	PORT1_PIDR_PIDR03 = 0x8
	// Low level
	PORT1_PIDR_PIDR03_0 = 0x0
	// High level
	PORT1_PIDR_PIDR03_1 = 0x1
	// Position of PIDR04 field.
	PORT1_PIDR_PIDR04_Pos = 0x4
	// Bit mask of PIDR04 field.
	PORT1_PIDR_PIDR04_Msk = 0x10
	// Bit PIDR04.
	PORT1_PIDR_PIDR04 = 0x10
	// Low level
	PORT1_PIDR_PIDR04_0 = 0x0
	// High level
	PORT1_PIDR_PIDR04_1 = 0x1
	// Position of PIDR05 field.
	PORT1_PIDR_PIDR05_Pos = 0x5
	// Bit mask of PIDR05 field.
	PORT1_PIDR_PIDR05_Msk = 0x20
	// Bit PIDR05.
	PORT1_PIDR_PIDR05 = 0x20
	// Low level
	PORT1_PIDR_PIDR05_0 = 0x0
	// High level
	PORT1_PIDR_PIDR05_1 = 0x1
	// Position of PIDR06 field.
	PORT1_PIDR_PIDR06_Pos = 0x6
	// Bit mask of PIDR06 field.
	PORT1_PIDR_PIDR06_Msk = 0x40
	// Bit PIDR06.
	PORT1_PIDR_PIDR06 = 0x40
	// Low level
	PORT1_PIDR_PIDR06_0 = 0x0
	// High level
	PORT1_PIDR_PIDR06_1 = 0x1
	// Position of PIDR07 field.
	PORT1_PIDR_PIDR07_Pos = 0x7
	// Bit mask of PIDR07 field.
	PORT1_PIDR_PIDR07_Msk = 0x80
	// Bit PIDR07.
	PORT1_PIDR_PIDR07 = 0x80
	// Low level
	PORT1_PIDR_PIDR07_0 = 0x0
	// High level
	PORT1_PIDR_PIDR07_1 = 0x1
	// Position of PIDR08 field.
	PORT1_PIDR_PIDR08_Pos = 0x8
	// Bit mask of PIDR08 field.
	PORT1_PIDR_PIDR08_Msk = 0x100
	// Bit PIDR08.
	PORT1_PIDR_PIDR08 = 0x100
	// Low level
	PORT1_PIDR_PIDR08_0 = 0x0
	// High level
	PORT1_PIDR_PIDR08_1 = 0x1
	// Position of PIDR09 field.
	PORT1_PIDR_PIDR09_Pos = 0x9
	// Bit mask of PIDR09 field.
	PORT1_PIDR_PIDR09_Msk = 0x200
	// Bit PIDR09.
	PORT1_PIDR_PIDR09 = 0x200
	// Low level
	PORT1_PIDR_PIDR09_0 = 0x0
	// High level
	PORT1_PIDR_PIDR09_1 = 0x1
	// Position of PIDR10 field.
	PORT1_PIDR_PIDR10_Pos = 0xa
	// Bit mask of PIDR10 field.
	PORT1_PIDR_PIDR10_Msk = 0x400
	// Bit PIDR10.
	PORT1_PIDR_PIDR10 = 0x400
	// Low level
	PORT1_PIDR_PIDR10_0 = 0x0
	// High level
	PORT1_PIDR_PIDR10_1 = 0x1
	// Position of PIDR11 field.
	PORT1_PIDR_PIDR11_Pos = 0xb
	// Bit mask of PIDR11 field.
	PORT1_PIDR_PIDR11_Msk = 0x800
	// Bit PIDR11.
	PORT1_PIDR_PIDR11 = 0x800
	// Low level
	PORT1_PIDR_PIDR11_0 = 0x0
	// High level
	PORT1_PIDR_PIDR11_1 = 0x1
	// Position of PIDR12 field.
	PORT1_PIDR_PIDR12_Pos = 0xc
	// Bit mask of PIDR12 field.
	PORT1_PIDR_PIDR12_Msk = 0x1000
	// Bit PIDR12.
	PORT1_PIDR_PIDR12 = 0x1000
	// Low level
	PORT1_PIDR_PIDR12_0 = 0x0
	// High level
	PORT1_PIDR_PIDR12_1 = 0x1
	// Position of PIDR13 field.
	PORT1_PIDR_PIDR13_Pos = 0xd
	// Bit mask of PIDR13 field.
	PORT1_PIDR_PIDR13_Msk = 0x2000
	// Bit PIDR13.
	PORT1_PIDR_PIDR13 = 0x2000
	// Low level
	PORT1_PIDR_PIDR13_0 = 0x0
	// High level
	PORT1_PIDR_PIDR13_1 = 0x1
	// Position of PIDR14 field.
	PORT1_PIDR_PIDR14_Pos = 0xe
	// Bit mask of PIDR14 field.
	PORT1_PIDR_PIDR14_Msk = 0x4000
	// Bit PIDR14.
	PORT1_PIDR_PIDR14 = 0x4000
	// Low level
	PORT1_PIDR_PIDR14_0 = 0x0
	// High level
	PORT1_PIDR_PIDR14_1 = 0x1
	// Position of PIDR15 field.
	PORT1_PIDR_PIDR15_Pos = 0xf
	// Bit mask of PIDR15 field.
	PORT1_PIDR_PIDR15_Msk = 0x8000
	// Bit PIDR15.
	PORT1_PIDR_PIDR15 = 0x8000
	// Low level
	PORT1_PIDR_PIDR15_0 = 0x0
	// High level
	PORT1_PIDR_PIDR15_1 = 0x1

	// PCNTR3: Port Control Register 3
	// Position of POSR00 field.
	PORT1_PCNTR3_POSR00_Pos = 0x0
	// Bit mask of POSR00 field.
	PORT1_PCNTR3_POSR00_Msk = 0x1
	// Bit POSR00.
	PORT1_PCNTR3_POSR00 = 0x1
	// No effect on output
	PORT1_PCNTR3_POSR00_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR00_1 = 0x1
	// Position of POSR01 field.
	PORT1_PCNTR3_POSR01_Pos = 0x1
	// Bit mask of POSR01 field.
	PORT1_PCNTR3_POSR01_Msk = 0x2
	// Bit POSR01.
	PORT1_PCNTR3_POSR01 = 0x2
	// No effect on output
	PORT1_PCNTR3_POSR01_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR01_1 = 0x1
	// Position of POSR02 field.
	PORT1_PCNTR3_POSR02_Pos = 0x2
	// Bit mask of POSR02 field.
	PORT1_PCNTR3_POSR02_Msk = 0x4
	// Bit POSR02.
	PORT1_PCNTR3_POSR02 = 0x4
	// No effect on output
	PORT1_PCNTR3_POSR02_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR02_1 = 0x1
	// Position of POSR03 field.
	PORT1_PCNTR3_POSR03_Pos = 0x3
	// Bit mask of POSR03 field.
	PORT1_PCNTR3_POSR03_Msk = 0x8
	// Bit POSR03.
	PORT1_PCNTR3_POSR03 = 0x8
	// No effect on output
	PORT1_PCNTR3_POSR03_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR03_1 = 0x1
	// Position of POSR04 field.
	PORT1_PCNTR3_POSR04_Pos = 0x4
	// Bit mask of POSR04 field.
	PORT1_PCNTR3_POSR04_Msk = 0x10
	// Bit POSR04.
	PORT1_PCNTR3_POSR04 = 0x10
	// No effect on output
	PORT1_PCNTR3_POSR04_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR04_1 = 0x1
	// Position of POSR05 field.
	PORT1_PCNTR3_POSR05_Pos = 0x5
	// Bit mask of POSR05 field.
	PORT1_PCNTR3_POSR05_Msk = 0x20
	// Bit POSR05.
	PORT1_PCNTR3_POSR05 = 0x20
	// No effect on output
	PORT1_PCNTR3_POSR05_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR05_1 = 0x1
	// Position of POSR06 field.
	PORT1_PCNTR3_POSR06_Pos = 0x6
	// Bit mask of POSR06 field.
	PORT1_PCNTR3_POSR06_Msk = 0x40
	// Bit POSR06.
	PORT1_PCNTR3_POSR06 = 0x40
	// No effect on output
	PORT1_PCNTR3_POSR06_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR06_1 = 0x1
	// Position of POSR07 field.
	PORT1_PCNTR3_POSR07_Pos = 0x7
	// Bit mask of POSR07 field.
	PORT1_PCNTR3_POSR07_Msk = 0x80
	// Bit POSR07.
	PORT1_PCNTR3_POSR07 = 0x80
	// No effect on output
	PORT1_PCNTR3_POSR07_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR07_1 = 0x1
	// Position of POSR08 field.
	PORT1_PCNTR3_POSR08_Pos = 0x8
	// Bit mask of POSR08 field.
	PORT1_PCNTR3_POSR08_Msk = 0x100
	// Bit POSR08.
	PORT1_PCNTR3_POSR08 = 0x100
	// No effect on output
	PORT1_PCNTR3_POSR08_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR08_1 = 0x1
	// Position of POSR09 field.
	PORT1_PCNTR3_POSR09_Pos = 0x9
	// Bit mask of POSR09 field.
	PORT1_PCNTR3_POSR09_Msk = 0x200
	// Bit POSR09.
	PORT1_PCNTR3_POSR09 = 0x200
	// No effect on output
	PORT1_PCNTR3_POSR09_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR09_1 = 0x1
	// Position of POSR10 field.
	PORT1_PCNTR3_POSR10_Pos = 0xa
	// Bit mask of POSR10 field.
	PORT1_PCNTR3_POSR10_Msk = 0x400
	// Bit POSR10.
	PORT1_PCNTR3_POSR10 = 0x400
	// No effect on output
	PORT1_PCNTR3_POSR10_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR10_1 = 0x1
	// Position of POSR11 field.
	PORT1_PCNTR3_POSR11_Pos = 0xb
	// Bit mask of POSR11 field.
	PORT1_PCNTR3_POSR11_Msk = 0x800
	// Bit POSR11.
	PORT1_PCNTR3_POSR11 = 0x800
	// No effect on output
	PORT1_PCNTR3_POSR11_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR11_1 = 0x1
	// Position of POSR12 field.
	PORT1_PCNTR3_POSR12_Pos = 0xc
	// Bit mask of POSR12 field.
	PORT1_PCNTR3_POSR12_Msk = 0x1000
	// Bit POSR12.
	PORT1_PCNTR3_POSR12 = 0x1000
	// No effect on output
	PORT1_PCNTR3_POSR12_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR12_1 = 0x1
	// Position of POSR13 field.
	PORT1_PCNTR3_POSR13_Pos = 0xd
	// Bit mask of POSR13 field.
	PORT1_PCNTR3_POSR13_Msk = 0x2000
	// Bit POSR13.
	PORT1_PCNTR3_POSR13 = 0x2000
	// No effect on output
	PORT1_PCNTR3_POSR13_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR13_1 = 0x1
	// Position of POSR14 field.
	PORT1_PCNTR3_POSR14_Pos = 0xe
	// Bit mask of POSR14 field.
	PORT1_PCNTR3_POSR14_Msk = 0x4000
	// Bit POSR14.
	PORT1_PCNTR3_POSR14 = 0x4000
	// No effect on output
	PORT1_PCNTR3_POSR14_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR14_1 = 0x1
	// Position of POSR15 field.
	PORT1_PCNTR3_POSR15_Pos = 0xf
	// Bit mask of POSR15 field.
	PORT1_PCNTR3_POSR15_Msk = 0x8000
	// Bit POSR15.
	PORT1_PCNTR3_POSR15 = 0x8000
	// No effect on output
	PORT1_PCNTR3_POSR15_0 = 0x0
	// High output
	PORT1_PCNTR3_POSR15_1 = 0x1
	// Position of PORR00 field.
	PORT1_PCNTR3_PORR00_Pos = 0x10
	// Bit mask of PORR00 field.
	PORT1_PCNTR3_PORR00_Msk = 0x10000
	// Bit PORR00.
	PORT1_PCNTR3_PORR00 = 0x10000
	// No effect on output
	PORT1_PCNTR3_PORR00_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR00_1 = 0x1
	// Position of PORR01 field.
	PORT1_PCNTR3_PORR01_Pos = 0x11
	// Bit mask of PORR01 field.
	PORT1_PCNTR3_PORR01_Msk = 0x20000
	// Bit PORR01.
	PORT1_PCNTR3_PORR01 = 0x20000
	// No effect on output
	PORT1_PCNTR3_PORR01_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR01_1 = 0x1
	// Position of PORR02 field.
	PORT1_PCNTR3_PORR02_Pos = 0x12
	// Bit mask of PORR02 field.
	PORT1_PCNTR3_PORR02_Msk = 0x40000
	// Bit PORR02.
	PORT1_PCNTR3_PORR02 = 0x40000
	// No effect on output
	PORT1_PCNTR3_PORR02_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR02_1 = 0x1
	// Position of PORR03 field.
	PORT1_PCNTR3_PORR03_Pos = 0x13
	// Bit mask of PORR03 field.
	PORT1_PCNTR3_PORR03_Msk = 0x80000
	// Bit PORR03.
	PORT1_PCNTR3_PORR03 = 0x80000
	// No effect on output
	PORT1_PCNTR3_PORR03_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR03_1 = 0x1
	// Position of PORR04 field.
	PORT1_PCNTR3_PORR04_Pos = 0x14
	// Bit mask of PORR04 field.
	PORT1_PCNTR3_PORR04_Msk = 0x100000
	// Bit PORR04.
	PORT1_PCNTR3_PORR04 = 0x100000
	// No effect on output
	PORT1_PCNTR3_PORR04_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR04_1 = 0x1
	// Position of PORR05 field.
	PORT1_PCNTR3_PORR05_Pos = 0x15
	// Bit mask of PORR05 field.
	PORT1_PCNTR3_PORR05_Msk = 0x200000
	// Bit PORR05.
	PORT1_PCNTR3_PORR05 = 0x200000
	// No effect on output
	PORT1_PCNTR3_PORR05_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR05_1 = 0x1
	// Position of PORR06 field.
	PORT1_PCNTR3_PORR06_Pos = 0x16
	// Bit mask of PORR06 field.
	PORT1_PCNTR3_PORR06_Msk = 0x400000
	// Bit PORR06.
	PORT1_PCNTR3_PORR06 = 0x400000
	// No effect on output
	PORT1_PCNTR3_PORR06_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR06_1 = 0x1
	// Position of PORR07 field.
	PORT1_PCNTR3_PORR07_Pos = 0x17
	// Bit mask of PORR07 field.
	PORT1_PCNTR3_PORR07_Msk = 0x800000
	// Bit PORR07.
	PORT1_PCNTR3_PORR07 = 0x800000
	// No effect on output
	PORT1_PCNTR3_PORR07_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR07_1 = 0x1
	// Position of PORR08 field.
	PORT1_PCNTR3_PORR08_Pos = 0x18
	// Bit mask of PORR08 field.
	PORT1_PCNTR3_PORR08_Msk = 0x1000000
	// Bit PORR08.
	PORT1_PCNTR3_PORR08 = 0x1000000
	// No effect on output
	PORT1_PCNTR3_PORR08_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR08_1 = 0x1
	// Position of PORR09 field.
	PORT1_PCNTR3_PORR09_Pos = 0x19
	// Bit mask of PORR09 field.
	PORT1_PCNTR3_PORR09_Msk = 0x2000000
	// Bit PORR09.
	PORT1_PCNTR3_PORR09 = 0x2000000
	// No effect on output
	PORT1_PCNTR3_PORR09_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR09_1 = 0x1
	// Position of PORR10 field.
	PORT1_PCNTR3_PORR10_Pos = 0x1a
	// Bit mask of PORR10 field.
	PORT1_PCNTR3_PORR10_Msk = 0x4000000
	// Bit PORR10.
	PORT1_PCNTR3_PORR10 = 0x4000000
	// No effect on output
	PORT1_PCNTR3_PORR10_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR10_1 = 0x1
	// Position of PORR11 field.
	PORT1_PCNTR3_PORR11_Pos = 0x1b
	// Bit mask of PORR11 field.
	PORT1_PCNTR3_PORR11_Msk = 0x8000000
	// Bit PORR11.
	PORT1_PCNTR3_PORR11 = 0x8000000
	// No effect on output
	PORT1_PCNTR3_PORR11_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR11_1 = 0x1
	// Position of PORR12 field.
	PORT1_PCNTR3_PORR12_Pos = 0x1c
	// Bit mask of PORR12 field.
	PORT1_PCNTR3_PORR12_Msk = 0x10000000
	// Bit PORR12.
	PORT1_PCNTR3_PORR12 = 0x10000000
	// No effect on output
	PORT1_PCNTR3_PORR12_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR12_1 = 0x1
	// Position of PORR13 field.
	PORT1_PCNTR3_PORR13_Pos = 0x1d
	// Bit mask of PORR13 field.
	PORT1_PCNTR3_PORR13_Msk = 0x20000000
	// Bit PORR13.
	PORT1_PCNTR3_PORR13 = 0x20000000
	// No effect on output
	PORT1_PCNTR3_PORR13_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR13_1 = 0x1
	// Position of PORR14 field.
	PORT1_PCNTR3_PORR14_Pos = 0x1e
	// Bit mask of PORR14 field.
	PORT1_PCNTR3_PORR14_Msk = 0x40000000
	// Bit PORR14.
	PORT1_PCNTR3_PORR14 = 0x40000000
	// No effect on output
	PORT1_PCNTR3_PORR14_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR14_1 = 0x1
	// Position of PORR15 field.
	PORT1_PCNTR3_PORR15_Pos = 0x1f
	// Bit mask of PORR15 field.
	PORT1_PCNTR3_PORR15_Msk = 0x80000000
	// Bit PORR15.
	PORT1_PCNTR3_PORR15 = 0x80000000
	// No effect on output
	PORT1_PCNTR3_PORR15_0 = 0x0
	// Low output
	PORT1_PCNTR3_PORR15_1 = 0x1

	// PORR: Port Control Register 3
	// Position of PORR00 field.
	PORT1_PORR_PORR00_Pos = 0x0
	// Bit mask of PORR00 field.
	PORT1_PORR_PORR00_Msk = 0x1
	// Bit PORR00.
	PORT1_PORR_PORR00 = 0x1
	// No effect on output
	PORT1_PORR_PORR00_0 = 0x0
	// Low output
	PORT1_PORR_PORR00_1 = 0x1
	// Position of PORR01 field.
	PORT1_PORR_PORR01_Pos = 0x1
	// Bit mask of PORR01 field.
	PORT1_PORR_PORR01_Msk = 0x2
	// Bit PORR01.
	PORT1_PORR_PORR01 = 0x2
	// No effect on output
	PORT1_PORR_PORR01_0 = 0x0
	// Low output
	PORT1_PORR_PORR01_1 = 0x1
	// Position of PORR02 field.
	PORT1_PORR_PORR02_Pos = 0x2
	// Bit mask of PORR02 field.
	PORT1_PORR_PORR02_Msk = 0x4
	// Bit PORR02.
	PORT1_PORR_PORR02 = 0x4
	// No effect on output
	PORT1_PORR_PORR02_0 = 0x0
	// Low output
	PORT1_PORR_PORR02_1 = 0x1
	// Position of PORR03 field.
	PORT1_PORR_PORR03_Pos = 0x3
	// Bit mask of PORR03 field.
	PORT1_PORR_PORR03_Msk = 0x8
	// Bit PORR03.
	PORT1_PORR_PORR03 = 0x8
	// No effect on output
	PORT1_PORR_PORR03_0 = 0x0
	// Low output
	PORT1_PORR_PORR03_1 = 0x1
	// Position of PORR04 field.
	PORT1_PORR_PORR04_Pos = 0x4
	// Bit mask of PORR04 field.
	PORT1_PORR_PORR04_Msk = 0x10
	// Bit PORR04.
	PORT1_PORR_PORR04 = 0x10
	// No effect on output
	PORT1_PORR_PORR04_0 = 0x0
	// Low output
	PORT1_PORR_PORR04_1 = 0x1
	// Position of PORR05 field.
	PORT1_PORR_PORR05_Pos = 0x5
	// Bit mask of PORR05 field.
	PORT1_PORR_PORR05_Msk = 0x20
	// Bit PORR05.
	PORT1_PORR_PORR05 = 0x20
	// No effect on output
	PORT1_PORR_PORR05_0 = 0x0
	// Low output
	PORT1_PORR_PORR05_1 = 0x1
	// Position of PORR06 field.
	PORT1_PORR_PORR06_Pos = 0x6
	// Bit mask of PORR06 field.
	PORT1_PORR_PORR06_Msk = 0x40
	// Bit PORR06.
	PORT1_PORR_PORR06 = 0x40
	// No effect on output
	PORT1_PORR_PORR06_0 = 0x0
	// Low output
	PORT1_PORR_PORR06_1 = 0x1
	// Position of PORR07 field.
	PORT1_PORR_PORR07_Pos = 0x7
	// Bit mask of PORR07 field.
	PORT1_PORR_PORR07_Msk = 0x80
	// Bit PORR07.
	PORT1_PORR_PORR07 = 0x80
	// No effect on output
	PORT1_PORR_PORR07_0 = 0x0
	// Low output
	PORT1_PORR_PORR07_1 = 0x1
	// Position of PORR08 field.
	PORT1_PORR_PORR08_Pos = 0x8
	// Bit mask of PORR08 field.
	PORT1_PORR_PORR08_Msk = 0x100
	// Bit PORR08.
	PORT1_PORR_PORR08 = 0x100
	// No effect on output
	PORT1_PORR_PORR08_0 = 0x0
	// Low output
	PORT1_PORR_PORR08_1 = 0x1
	// Position of PORR09 field.
	PORT1_PORR_PORR09_Pos = 0x9
	// Bit mask of PORR09 field.
	PORT1_PORR_PORR09_Msk = 0x200
	// Bit PORR09.
	PORT1_PORR_PORR09 = 0x200
	// No effect on output
	PORT1_PORR_PORR09_0 = 0x0
	// Low output
	PORT1_PORR_PORR09_1 = 0x1
	// Position of PORR10 field.
	PORT1_PORR_PORR10_Pos = 0xa
	// Bit mask of PORR10 field.
	PORT1_PORR_PORR10_Msk = 0x400
	// Bit PORR10.
	PORT1_PORR_PORR10 = 0x400
	// No effect on output
	PORT1_PORR_PORR10_0 = 0x0
	// Low output
	PORT1_PORR_PORR10_1 = 0x1
	// Position of PORR11 field.
	PORT1_PORR_PORR11_Pos = 0xb
	// Bit mask of PORR11 field.
	PORT1_PORR_PORR11_Msk = 0x800
	// Bit PORR11.
	PORT1_PORR_PORR11 = 0x800
	// No effect on output
	PORT1_PORR_PORR11_0 = 0x0
	// Low output
	PORT1_PORR_PORR11_1 = 0x1
	// Position of PORR12 field.
	PORT1_PORR_PORR12_Pos = 0xc
	// Bit mask of PORR12 field.
	PORT1_PORR_PORR12_Msk = 0x1000
	// Bit PORR12.
	PORT1_PORR_PORR12 = 0x1000
	// No effect on output
	PORT1_PORR_PORR12_0 = 0x0
	// Low output
	PORT1_PORR_PORR12_1 = 0x1
	// Position of PORR13 field.
	PORT1_PORR_PORR13_Pos = 0xd
	// Bit mask of PORR13 field.
	PORT1_PORR_PORR13_Msk = 0x2000
	// Bit PORR13.
	PORT1_PORR_PORR13 = 0x2000
	// No effect on output
	PORT1_PORR_PORR13_0 = 0x0
	// Low output
	PORT1_PORR_PORR13_1 = 0x1
	// Position of PORR14 field.
	PORT1_PORR_PORR14_Pos = 0xe
	// Bit mask of PORR14 field.
	PORT1_PORR_PORR14_Msk = 0x4000
	// Bit PORR14.
	PORT1_PORR_PORR14 = 0x4000
	// No effect on output
	PORT1_PORR_PORR14_0 = 0x0
	// Low output
	PORT1_PORR_PORR14_1 = 0x1
	// Position of PORR15 field.
	PORT1_PORR_PORR15_Pos = 0xf
	// Bit mask of PORR15 field.
	PORT1_PORR_PORR15_Msk = 0x8000
	// Bit PORR15.
	PORT1_PORR_PORR15 = 0x8000
	// No effect on output
	PORT1_PORR_PORR15_0 = 0x0
	// Low output
	PORT1_PORR_PORR15_1 = 0x1

	// POSR: Port Control Register 3
	// Position of POSR00 field.
	PORT1_POSR_POSR00_Pos = 0x0
	// Bit mask of POSR00 field.
	PORT1_POSR_POSR00_Msk = 0x1
	// Bit POSR00.
	PORT1_POSR_POSR00 = 0x1
	// No effect on output
	PORT1_POSR_POSR00_0 = 0x0
	// High output
	PORT1_POSR_POSR00_1 = 0x1
	// Position of POSR01 field.
	PORT1_POSR_POSR01_Pos = 0x1
	// Bit mask of POSR01 field.
	PORT1_POSR_POSR01_Msk = 0x2
	// Bit POSR01.
	PORT1_POSR_POSR01 = 0x2
	// No effect on output
	PORT1_POSR_POSR01_0 = 0x0
	// High output
	PORT1_POSR_POSR01_1 = 0x1
	// Position of POSR02 field.
	PORT1_POSR_POSR02_Pos = 0x2
	// Bit mask of POSR02 field.
	PORT1_POSR_POSR02_Msk = 0x4
	// Bit POSR02.
	PORT1_POSR_POSR02 = 0x4
	// No effect on output
	PORT1_POSR_POSR02_0 = 0x0
	// High output
	PORT1_POSR_POSR02_1 = 0x1
	// Position of POSR03 field.
	PORT1_POSR_POSR03_Pos = 0x3
	// Bit mask of POSR03 field.
	PORT1_POSR_POSR03_Msk = 0x8
	// Bit POSR03.
	PORT1_POSR_POSR03 = 0x8
	// No effect on output
	PORT1_POSR_POSR03_0 = 0x0
	// High output
	PORT1_POSR_POSR03_1 = 0x1
	// Position of POSR04 field.
	PORT1_POSR_POSR04_Pos = 0x4
	// Bit mask of POSR04 field.
	PORT1_POSR_POSR04_Msk = 0x10
	// Bit POSR04.
	PORT1_POSR_POSR04 = 0x10
	// No effect on output
	PORT1_POSR_POSR04_0 = 0x0
	// High output
	PORT1_POSR_POSR04_1 = 0x1
	// Position of POSR05 field.
	PORT1_POSR_POSR05_Pos = 0x5
	// Bit mask of POSR05 field.
	PORT1_POSR_POSR05_Msk = 0x20
	// Bit POSR05.
	PORT1_POSR_POSR05 = 0x20
	// No effect on output
	PORT1_POSR_POSR05_0 = 0x0
	// High output
	PORT1_POSR_POSR05_1 = 0x1
	// Position of POSR06 field.
	PORT1_POSR_POSR06_Pos = 0x6
	// Bit mask of POSR06 field.
	PORT1_POSR_POSR06_Msk = 0x40
	// Bit POSR06.
	PORT1_POSR_POSR06 = 0x40
	// No effect on output
	PORT1_POSR_POSR06_0 = 0x0
	// High output
	PORT1_POSR_POSR06_1 = 0x1
	// Position of POSR07 field.
	PORT1_POSR_POSR07_Pos = 0x7
	// Bit mask of POSR07 field.
	PORT1_POSR_POSR07_Msk = 0x80
	// Bit POSR07.
	PORT1_POSR_POSR07 = 0x80
	// No effect on output
	PORT1_POSR_POSR07_0 = 0x0
	// High output
	PORT1_POSR_POSR07_1 = 0x1
	// Position of POSR08 field.
	PORT1_POSR_POSR08_Pos = 0x8
	// Bit mask of POSR08 field.
	PORT1_POSR_POSR08_Msk = 0x100
	// Bit POSR08.
	PORT1_POSR_POSR08 = 0x100
	// No effect on output
	PORT1_POSR_POSR08_0 = 0x0
	// High output
	PORT1_POSR_POSR08_1 = 0x1
	// Position of POSR09 field.
	PORT1_POSR_POSR09_Pos = 0x9
	// Bit mask of POSR09 field.
	PORT1_POSR_POSR09_Msk = 0x200
	// Bit POSR09.
	PORT1_POSR_POSR09 = 0x200
	// No effect on output
	PORT1_POSR_POSR09_0 = 0x0
	// High output
	PORT1_POSR_POSR09_1 = 0x1
	// Position of POSR10 field.
	PORT1_POSR_POSR10_Pos = 0xa
	// Bit mask of POSR10 field.
	PORT1_POSR_POSR10_Msk = 0x400
	// Bit POSR10.
	PORT1_POSR_POSR10 = 0x400
	// No effect on output
	PORT1_POSR_POSR10_0 = 0x0
	// High output
	PORT1_POSR_POSR10_1 = 0x1
	// Position of POSR11 field.
	PORT1_POSR_POSR11_Pos = 0xb
	// Bit mask of POSR11 field.
	PORT1_POSR_POSR11_Msk = 0x800
	// Bit POSR11.
	PORT1_POSR_POSR11 = 0x800
	// No effect on output
	PORT1_POSR_POSR11_0 = 0x0
	// High output
	PORT1_POSR_POSR11_1 = 0x1
	// Position of POSR12 field.
	PORT1_POSR_POSR12_Pos = 0xc
	// Bit mask of POSR12 field.
	PORT1_POSR_POSR12_Msk = 0x1000
	// Bit POSR12.
	PORT1_POSR_POSR12 = 0x1000
	// No effect on output
	PORT1_POSR_POSR12_0 = 0x0
	// High output
	PORT1_POSR_POSR12_1 = 0x1
	// Position of POSR13 field.
	PORT1_POSR_POSR13_Pos = 0xd
	// Bit mask of POSR13 field.
	PORT1_POSR_POSR13_Msk = 0x2000
	// Bit POSR13.
	PORT1_POSR_POSR13 = 0x2000
	// No effect on output
	PORT1_POSR_POSR13_0 = 0x0
	// High output
	PORT1_POSR_POSR13_1 = 0x1
	// Position of POSR14 field.
	PORT1_POSR_POSR14_Pos = 0xe
	// Bit mask of POSR14 field.
	PORT1_POSR_POSR14_Msk = 0x4000
	// Bit POSR14.
	PORT1_POSR_POSR14 = 0x4000
	// No effect on output
	PORT1_POSR_POSR14_0 = 0x0
	// High output
	PORT1_POSR_POSR14_1 = 0x1
	// Position of POSR15 field.
	PORT1_POSR_POSR15_Pos = 0xf
	// Bit mask of POSR15 field.
	PORT1_POSR_POSR15_Msk = 0x8000
	// Bit POSR15.
	PORT1_POSR_POSR15 = 0x8000
	// No effect on output
	PORT1_POSR_POSR15_0 = 0x0
	// High output
	PORT1_POSR_POSR15_1 = 0x1

	// PCNTR4: Port Control Register 4
	// Position of EOSR00 field.
	PORT1_PCNTR4_EOSR00_Pos = 0x0
	// Bit mask of EOSR00 field.
	PORT1_PCNTR4_EOSR00_Msk = 0x1
	// Bit EOSR00.
	PORT1_PCNTR4_EOSR00 = 0x1
	// No effect on output
	PORT1_PCNTR4_EOSR00_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR00_1 = 0x1
	// Position of EOSR01 field.
	PORT1_PCNTR4_EOSR01_Pos = 0x1
	// Bit mask of EOSR01 field.
	PORT1_PCNTR4_EOSR01_Msk = 0x2
	// Bit EOSR01.
	PORT1_PCNTR4_EOSR01 = 0x2
	// No effect on output
	PORT1_PCNTR4_EOSR01_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR01_1 = 0x1
	// Position of EOSR02 field.
	PORT1_PCNTR4_EOSR02_Pos = 0x2
	// Bit mask of EOSR02 field.
	PORT1_PCNTR4_EOSR02_Msk = 0x4
	// Bit EOSR02.
	PORT1_PCNTR4_EOSR02 = 0x4
	// No effect on output
	PORT1_PCNTR4_EOSR02_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR02_1 = 0x1
	// Position of EOSR03 field.
	PORT1_PCNTR4_EOSR03_Pos = 0x3
	// Bit mask of EOSR03 field.
	PORT1_PCNTR4_EOSR03_Msk = 0x8
	// Bit EOSR03.
	PORT1_PCNTR4_EOSR03 = 0x8
	// No effect on output
	PORT1_PCNTR4_EOSR03_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR03_1 = 0x1
	// Position of EOSR04 field.
	PORT1_PCNTR4_EOSR04_Pos = 0x4
	// Bit mask of EOSR04 field.
	PORT1_PCNTR4_EOSR04_Msk = 0x10
	// Bit EOSR04.
	PORT1_PCNTR4_EOSR04 = 0x10
	// No effect on output
	PORT1_PCNTR4_EOSR04_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR04_1 = 0x1
	// Position of EOSR05 field.
	PORT1_PCNTR4_EOSR05_Pos = 0x5
	// Bit mask of EOSR05 field.
	PORT1_PCNTR4_EOSR05_Msk = 0x20
	// Bit EOSR05.
	PORT1_PCNTR4_EOSR05 = 0x20
	// No effect on output
	PORT1_PCNTR4_EOSR05_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR05_1 = 0x1
	// Position of EOSR06 field.
	PORT1_PCNTR4_EOSR06_Pos = 0x6
	// Bit mask of EOSR06 field.
	PORT1_PCNTR4_EOSR06_Msk = 0x40
	// Bit EOSR06.
	PORT1_PCNTR4_EOSR06 = 0x40
	// No effect on output
	PORT1_PCNTR4_EOSR06_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR06_1 = 0x1
	// Position of EOSR07 field.
	PORT1_PCNTR4_EOSR07_Pos = 0x7
	// Bit mask of EOSR07 field.
	PORT1_PCNTR4_EOSR07_Msk = 0x80
	// Bit EOSR07.
	PORT1_PCNTR4_EOSR07 = 0x80
	// No effect on output
	PORT1_PCNTR4_EOSR07_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR07_1 = 0x1
	// Position of EOSR08 field.
	PORT1_PCNTR4_EOSR08_Pos = 0x8
	// Bit mask of EOSR08 field.
	PORT1_PCNTR4_EOSR08_Msk = 0x100
	// Bit EOSR08.
	PORT1_PCNTR4_EOSR08 = 0x100
	// No effect on output
	PORT1_PCNTR4_EOSR08_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR08_1 = 0x1
	// Position of EOSR09 field.
	PORT1_PCNTR4_EOSR09_Pos = 0x9
	// Bit mask of EOSR09 field.
	PORT1_PCNTR4_EOSR09_Msk = 0x200
	// Bit EOSR09.
	PORT1_PCNTR4_EOSR09 = 0x200
	// No effect on output
	PORT1_PCNTR4_EOSR09_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR09_1 = 0x1
	// Position of EOSR10 field.
	PORT1_PCNTR4_EOSR10_Pos = 0xa
	// Bit mask of EOSR10 field.
	PORT1_PCNTR4_EOSR10_Msk = 0x400
	// Bit EOSR10.
	PORT1_PCNTR4_EOSR10 = 0x400
	// No effect on output
	PORT1_PCNTR4_EOSR10_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR10_1 = 0x1
	// Position of EOSR11 field.
	PORT1_PCNTR4_EOSR11_Pos = 0xb
	// Bit mask of EOSR11 field.
	PORT1_PCNTR4_EOSR11_Msk = 0x800
	// Bit EOSR11.
	PORT1_PCNTR4_EOSR11 = 0x800
	// No effect on output
	PORT1_PCNTR4_EOSR11_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR11_1 = 0x1
	// Position of EOSR12 field.
	PORT1_PCNTR4_EOSR12_Pos = 0xc
	// Bit mask of EOSR12 field.
	PORT1_PCNTR4_EOSR12_Msk = 0x1000
	// Bit EOSR12.
	PORT1_PCNTR4_EOSR12 = 0x1000
	// No effect on output
	PORT1_PCNTR4_EOSR12_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR12_1 = 0x1
	// Position of EOSR13 field.
	PORT1_PCNTR4_EOSR13_Pos = 0xd
	// Bit mask of EOSR13 field.
	PORT1_PCNTR4_EOSR13_Msk = 0x2000
	// Bit EOSR13.
	PORT1_PCNTR4_EOSR13 = 0x2000
	// No effect on output
	PORT1_PCNTR4_EOSR13_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR13_1 = 0x1
	// Position of EOSR14 field.
	PORT1_PCNTR4_EOSR14_Pos = 0xe
	// Bit mask of EOSR14 field.
	PORT1_PCNTR4_EOSR14_Msk = 0x4000
	// Bit EOSR14.
	PORT1_PCNTR4_EOSR14 = 0x4000
	// No effect on output
	PORT1_PCNTR4_EOSR14_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR14_1 = 0x1
	// Position of EOSR15 field.
	PORT1_PCNTR4_EOSR15_Pos = 0xf
	// Bit mask of EOSR15 field.
	PORT1_PCNTR4_EOSR15_Msk = 0x8000
	// Bit EOSR15.
	PORT1_PCNTR4_EOSR15 = 0x8000
	// No effect on output
	PORT1_PCNTR4_EOSR15_0 = 0x0
	// High output
	PORT1_PCNTR4_EOSR15_1 = 0x1
	// Position of EORR00 field.
	PORT1_PCNTR4_EORR00_Pos = 0x10
	// Bit mask of EORR00 field.
	PORT1_PCNTR4_EORR00_Msk = 0x10000
	// Bit EORR00.
	PORT1_PCNTR4_EORR00 = 0x10000
	// No effect on output
	PORT1_PCNTR4_EORR00_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR00_1 = 0x1
	// Position of EORR01 field.
	PORT1_PCNTR4_EORR01_Pos = 0x11
	// Bit mask of EORR01 field.
	PORT1_PCNTR4_EORR01_Msk = 0x20000
	// Bit EORR01.
	PORT1_PCNTR4_EORR01 = 0x20000
	// No effect on output
	PORT1_PCNTR4_EORR01_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR01_1 = 0x1
	// Position of EORR02 field.
	PORT1_PCNTR4_EORR02_Pos = 0x12
	// Bit mask of EORR02 field.
	PORT1_PCNTR4_EORR02_Msk = 0x40000
	// Bit EORR02.
	PORT1_PCNTR4_EORR02 = 0x40000
	// No effect on output
	PORT1_PCNTR4_EORR02_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR02_1 = 0x1
	// Position of EORR03 field.
	PORT1_PCNTR4_EORR03_Pos = 0x13
	// Bit mask of EORR03 field.
	PORT1_PCNTR4_EORR03_Msk = 0x80000
	// Bit EORR03.
	PORT1_PCNTR4_EORR03 = 0x80000
	// No effect on output
	PORT1_PCNTR4_EORR03_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR03_1 = 0x1
	// Position of EORR04 field.
	PORT1_PCNTR4_EORR04_Pos = 0x14
	// Bit mask of EORR04 field.
	PORT1_PCNTR4_EORR04_Msk = 0x100000
	// Bit EORR04.
	PORT1_PCNTR4_EORR04 = 0x100000
	// No effect on output
	PORT1_PCNTR4_EORR04_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR04_1 = 0x1
	// Position of EORR05 field.
	PORT1_PCNTR4_EORR05_Pos = 0x15
	// Bit mask of EORR05 field.
	PORT1_PCNTR4_EORR05_Msk = 0x200000
	// Bit EORR05.
	PORT1_PCNTR4_EORR05 = 0x200000
	// No effect on output
	PORT1_PCNTR4_EORR05_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR05_1 = 0x1
	// Position of EORR06 field.
	PORT1_PCNTR4_EORR06_Pos = 0x16
	// Bit mask of EORR06 field.
	PORT1_PCNTR4_EORR06_Msk = 0x400000
	// Bit EORR06.
	PORT1_PCNTR4_EORR06 = 0x400000
	// No effect on output
	PORT1_PCNTR4_EORR06_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR06_1 = 0x1
	// Position of EORR07 field.
	PORT1_PCNTR4_EORR07_Pos = 0x17
	// Bit mask of EORR07 field.
	PORT1_PCNTR4_EORR07_Msk = 0x800000
	// Bit EORR07.
	PORT1_PCNTR4_EORR07 = 0x800000
	// No effect on output
	PORT1_PCNTR4_EORR07_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR07_1 = 0x1
	// Position of EORR08 field.
	PORT1_PCNTR4_EORR08_Pos = 0x18
	// Bit mask of EORR08 field.
	PORT1_PCNTR4_EORR08_Msk = 0x1000000
	// Bit EORR08.
	PORT1_PCNTR4_EORR08 = 0x1000000
	// No effect on output
	PORT1_PCNTR4_EORR08_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR08_1 = 0x1
	// Position of EORR09 field.
	PORT1_PCNTR4_EORR09_Pos = 0x19
	// Bit mask of EORR09 field.
	PORT1_PCNTR4_EORR09_Msk = 0x2000000
	// Bit EORR09.
	PORT1_PCNTR4_EORR09 = 0x2000000
	// No effect on output
	PORT1_PCNTR4_EORR09_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR09_1 = 0x1
	// Position of EORR10 field.
	PORT1_PCNTR4_EORR10_Pos = 0x1a
	// Bit mask of EORR10 field.
	PORT1_PCNTR4_EORR10_Msk = 0x4000000
	// Bit EORR10.
	PORT1_PCNTR4_EORR10 = 0x4000000
	// No effect on output
	PORT1_PCNTR4_EORR10_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR10_1 = 0x1
	// Position of EORR11 field.
	PORT1_PCNTR4_EORR11_Pos = 0x1b
	// Bit mask of EORR11 field.
	PORT1_PCNTR4_EORR11_Msk = 0x8000000
	// Bit EORR11.
	PORT1_PCNTR4_EORR11 = 0x8000000
	// No effect on output
	PORT1_PCNTR4_EORR11_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR11_1 = 0x1
	// Position of EORR12 field.
	PORT1_PCNTR4_EORR12_Pos = 0x1c
	// Bit mask of EORR12 field.
	PORT1_PCNTR4_EORR12_Msk = 0x10000000
	// Bit EORR12.
	PORT1_PCNTR4_EORR12 = 0x10000000
	// No effect on output
	PORT1_PCNTR4_EORR12_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR12_1 = 0x1
	// Position of EORR13 field.
	PORT1_PCNTR4_EORR13_Pos = 0x1d
	// Bit mask of EORR13 field.
	PORT1_PCNTR4_EORR13_Msk = 0x20000000
	// Bit EORR13.
	PORT1_PCNTR4_EORR13 = 0x20000000
	// No effect on output
	PORT1_PCNTR4_EORR13_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR13_1 = 0x1
	// Position of EORR14 field.
	PORT1_PCNTR4_EORR14_Pos = 0x1e
	// Bit mask of EORR14 field.
	PORT1_PCNTR4_EORR14_Msk = 0x40000000
	// Bit EORR14.
	PORT1_PCNTR4_EORR14 = 0x40000000
	// No effect on output
	PORT1_PCNTR4_EORR14_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR14_1 = 0x1
	// Position of EORR15 field.
	PORT1_PCNTR4_EORR15_Pos = 0x1f
	// Bit mask of EORR15 field.
	PORT1_PCNTR4_EORR15_Msk = 0x80000000
	// Bit EORR15.
	PORT1_PCNTR4_EORR15 = 0x80000000
	// No effect on output
	PORT1_PCNTR4_EORR15_0 = 0x0
	// Low output
	PORT1_PCNTR4_EORR15_1 = 0x1

	// EORR: Port Control Register 4
	// Position of EORR00 field.
	PORT1_EORR_EORR00_Pos = 0x0
	// Bit mask of EORR00 field.
	PORT1_EORR_EORR00_Msk = 0x1
	// Bit EORR00.
	PORT1_EORR_EORR00 = 0x1
	// No effect on output
	PORT1_EORR_EORR00_0 = 0x0
	// Low output
	PORT1_EORR_EORR00_1 = 0x1
	// Position of EORR01 field.
	PORT1_EORR_EORR01_Pos = 0x1
	// Bit mask of EORR01 field.
	PORT1_EORR_EORR01_Msk = 0x2
	// Bit EORR01.
	PORT1_EORR_EORR01 = 0x2
	// No effect on output
	PORT1_EORR_EORR01_0 = 0x0
	// Low output
	PORT1_EORR_EORR01_1 = 0x1
	// Position of EORR02 field.
	PORT1_EORR_EORR02_Pos = 0x2
	// Bit mask of EORR02 field.
	PORT1_EORR_EORR02_Msk = 0x4
	// Bit EORR02.
	PORT1_EORR_EORR02 = 0x4
	// No effect on output
	PORT1_EORR_EORR02_0 = 0x0
	// Low output
	PORT1_EORR_EORR02_1 = 0x1
	// Position of EORR03 field.
	PORT1_EORR_EORR03_Pos = 0x3
	// Bit mask of EORR03 field.
	PORT1_EORR_EORR03_Msk = 0x8
	// Bit EORR03.
	PORT1_EORR_EORR03 = 0x8
	// No effect on output
	PORT1_EORR_EORR03_0 = 0x0
	// Low output
	PORT1_EORR_EORR03_1 = 0x1
	// Position of EORR04 field.
	PORT1_EORR_EORR04_Pos = 0x4
	// Bit mask of EORR04 field.
	PORT1_EORR_EORR04_Msk = 0x10
	// Bit EORR04.
	PORT1_EORR_EORR04 = 0x10
	// No effect on output
	PORT1_EORR_EORR04_0 = 0x0
	// Low output
	PORT1_EORR_EORR04_1 = 0x1
	// Position of EORR05 field.
	PORT1_EORR_EORR05_Pos = 0x5
	// Bit mask of EORR05 field.
	PORT1_EORR_EORR05_Msk = 0x20
	// Bit EORR05.
	PORT1_EORR_EORR05 = 0x20
	// No effect on output
	PORT1_EORR_EORR05_0 = 0x0
	// Low output
	PORT1_EORR_EORR05_1 = 0x1
	// Position of EORR06 field.
	PORT1_EORR_EORR06_Pos = 0x6
	// Bit mask of EORR06 field.
	PORT1_EORR_EORR06_Msk = 0x40
	// Bit EORR06.
	PORT1_EORR_EORR06 = 0x40
	// No effect on output
	PORT1_EORR_EORR06_0 = 0x0
	// Low output
	PORT1_EORR_EORR06_1 = 0x1
	// Position of EORR07 field.
	PORT1_EORR_EORR07_Pos = 0x7
	// Bit mask of EORR07 field.
	PORT1_EORR_EORR07_Msk = 0x80
	// Bit EORR07.
	PORT1_EORR_EORR07 = 0x80
	// No effect on output
	PORT1_EORR_EORR07_0 = 0x0
	// Low output
	PORT1_EORR_EORR07_1 = 0x1
	// Position of EORR08 field.
	PORT1_EORR_EORR08_Pos = 0x8
	// Bit mask of EORR08 field.
	PORT1_EORR_EORR08_Msk = 0x100
	// Bit EORR08.
	PORT1_EORR_EORR08 = 0x100
	// No effect on output
	PORT1_EORR_EORR08_0 = 0x0
	// Low output
	PORT1_EORR_EORR08_1 = 0x1
	// Position of EORR09 field.
	PORT1_EORR_EORR09_Pos = 0x9
	// Bit mask of EORR09 field.
	PORT1_EORR_EORR09_Msk = 0x200
	// Bit EORR09.
	PORT1_EORR_EORR09 = 0x200
	// No effect on output
	PORT1_EORR_EORR09_0 = 0x0
	// Low output
	PORT1_EORR_EORR09_1 = 0x1
	// Position of EORR10 field.
	PORT1_EORR_EORR10_Pos = 0xa
	// Bit mask of EORR10 field.
	PORT1_EORR_EORR10_Msk = 0x400
	// Bit EORR10.
	PORT1_EORR_EORR10 = 0x400
	// No effect on output
	PORT1_EORR_EORR10_0 = 0x0
	// Low output
	PORT1_EORR_EORR10_1 = 0x1
	// Position of EORR11 field.
	PORT1_EORR_EORR11_Pos = 0xb
	// Bit mask of EORR11 field.
	PORT1_EORR_EORR11_Msk = 0x800
	// Bit EORR11.
	PORT1_EORR_EORR11 = 0x800
	// No effect on output
	PORT1_EORR_EORR11_0 = 0x0
	// Low output
	PORT1_EORR_EORR11_1 = 0x1
	// Position of EORR12 field.
	PORT1_EORR_EORR12_Pos = 0xc
	// Bit mask of EORR12 field.
	PORT1_EORR_EORR12_Msk = 0x1000
	// Bit EORR12.
	PORT1_EORR_EORR12 = 0x1000
	// No effect on output
	PORT1_EORR_EORR12_0 = 0x0
	// Low output
	PORT1_EORR_EORR12_1 = 0x1
	// Position of EORR13 field.
	PORT1_EORR_EORR13_Pos = 0xd
	// Bit mask of EORR13 field.
	PORT1_EORR_EORR13_Msk = 0x2000
	// Bit EORR13.
	PORT1_EORR_EORR13 = 0x2000
	// No effect on output
	PORT1_EORR_EORR13_0 = 0x0
	// Low output
	PORT1_EORR_EORR13_1 = 0x1
	// Position of EORR14 field.
	PORT1_EORR_EORR14_Pos = 0xe
	// Bit mask of EORR14 field.
	PORT1_EORR_EORR14_Msk = 0x4000
	// Bit EORR14.
	PORT1_EORR_EORR14 = 0x4000
	// No effect on output
	PORT1_EORR_EORR14_0 = 0x0
	// Low output
	PORT1_EORR_EORR14_1 = 0x1
	// Position of EORR15 field.
	PORT1_EORR_EORR15_Pos = 0xf
	// Bit mask of EORR15 field.
	PORT1_EORR_EORR15_Msk = 0x8000
	// Bit EORR15.
	PORT1_EORR_EORR15 = 0x8000
	// No effect on output
	PORT1_EORR_EORR15_0 = 0x0
	// Low output
	PORT1_EORR_EORR15_1 = 0x1

	// EOSR: Port Control Register 4
	// Position of EOSR00 field.
	PORT1_EOSR_EOSR00_Pos = 0x0
	// Bit mask of EOSR00 field.
	PORT1_EOSR_EOSR00_Msk = 0x1
	// Bit EOSR00.
	PORT1_EOSR_EOSR00 = 0x1
	// No effect on output
	PORT1_EOSR_EOSR00_0 = 0x0
	// High output
	PORT1_EOSR_EOSR00_1 = 0x1
	// Position of EOSR01 field.
	PORT1_EOSR_EOSR01_Pos = 0x1
	// Bit mask of EOSR01 field.
	PORT1_EOSR_EOSR01_Msk = 0x2
	// Bit EOSR01.
	PORT1_EOSR_EOSR01 = 0x2
	// No effect on output
	PORT1_EOSR_EOSR01_0 = 0x0
	// High output
	PORT1_EOSR_EOSR01_1 = 0x1
	// Position of EOSR02 field.
	PORT1_EOSR_EOSR02_Pos = 0x2
	// Bit mask of EOSR02 field.
	PORT1_EOSR_EOSR02_Msk = 0x4
	// Bit EOSR02.
	PORT1_EOSR_EOSR02 = 0x4
	// No effect on output
	PORT1_EOSR_EOSR02_0 = 0x0
	// High output
	PORT1_EOSR_EOSR02_1 = 0x1
	// Position of EOSR03 field.
	PORT1_EOSR_EOSR03_Pos = 0x3
	// Bit mask of EOSR03 field.
	PORT1_EOSR_EOSR03_Msk = 0x8
	// Bit EOSR03.
	PORT1_EOSR_EOSR03 = 0x8
	// No effect on output
	PORT1_EOSR_EOSR03_0 = 0x0
	// High output
	PORT1_EOSR_EOSR03_1 = 0x1
	// Position of EOSR04 field.
	PORT1_EOSR_EOSR04_Pos = 0x4
	// Bit mask of EOSR04 field.
	PORT1_EOSR_EOSR04_Msk = 0x10
	// Bit EOSR04.
	PORT1_EOSR_EOSR04 = 0x10
	// No effect on output
	PORT1_EOSR_EOSR04_0 = 0x0
	// High output
	PORT1_EOSR_EOSR04_1 = 0x1
	// Position of EOSR05 field.
	PORT1_EOSR_EOSR05_Pos = 0x5
	// Bit mask of EOSR05 field.
	PORT1_EOSR_EOSR05_Msk = 0x20
	// Bit EOSR05.
	PORT1_EOSR_EOSR05 = 0x20
	// No effect on output
	PORT1_EOSR_EOSR05_0 = 0x0
	// High output
	PORT1_EOSR_EOSR05_1 = 0x1
	// Position of EOSR06 field.
	PORT1_EOSR_EOSR06_Pos = 0x6
	// Bit mask of EOSR06 field.
	PORT1_EOSR_EOSR06_Msk = 0x40
	// Bit EOSR06.
	PORT1_EOSR_EOSR06 = 0x40
	// No effect on output
	PORT1_EOSR_EOSR06_0 = 0x0
	// High output
	PORT1_EOSR_EOSR06_1 = 0x1
	// Position of EOSR07 field.
	PORT1_EOSR_EOSR07_Pos = 0x7
	// Bit mask of EOSR07 field.
	PORT1_EOSR_EOSR07_Msk = 0x80
	// Bit EOSR07.
	PORT1_EOSR_EOSR07 = 0x80
	// No effect on output
	PORT1_EOSR_EOSR07_0 = 0x0
	// High output
	PORT1_EOSR_EOSR07_1 = 0x1
	// Position of EOSR08 field.
	PORT1_EOSR_EOSR08_Pos = 0x8
	// Bit mask of EOSR08 field.
	PORT1_EOSR_EOSR08_Msk = 0x100
	// Bit EOSR08.
	PORT1_EOSR_EOSR08 = 0x100
	// No effect on output
	PORT1_EOSR_EOSR08_0 = 0x0
	// High output
	PORT1_EOSR_EOSR08_1 = 0x1
	// Position of EOSR09 field.
	PORT1_EOSR_EOSR09_Pos = 0x9
	// Bit mask of EOSR09 field.
	PORT1_EOSR_EOSR09_Msk = 0x200
	// Bit EOSR09.
	PORT1_EOSR_EOSR09 = 0x200
	// No effect on output
	PORT1_EOSR_EOSR09_0 = 0x0
	// High output
	PORT1_EOSR_EOSR09_1 = 0x1
	// Position of EOSR10 field.
	PORT1_EOSR_EOSR10_Pos = 0xa
	// Bit mask of EOSR10 field.
	PORT1_EOSR_EOSR10_Msk = 0x400
	// Bit EOSR10.
	PORT1_EOSR_EOSR10 = 0x400
	// No effect on output
	PORT1_EOSR_EOSR10_0 = 0x0
	// High output
	PORT1_EOSR_EOSR10_1 = 0x1
	// Position of EOSR11 field.
	PORT1_EOSR_EOSR11_Pos = 0xb
	// Bit mask of EOSR11 field.
	PORT1_EOSR_EOSR11_Msk = 0x800
	// Bit EOSR11.
	PORT1_EOSR_EOSR11 = 0x800
	// No effect on output
	PORT1_EOSR_EOSR11_0 = 0x0
	// High output
	PORT1_EOSR_EOSR11_1 = 0x1
	// Position of EOSR12 field.
	PORT1_EOSR_EOSR12_Pos = 0xc
	// Bit mask of EOSR12 field.
	PORT1_EOSR_EOSR12_Msk = 0x1000
	// Bit EOSR12.
	PORT1_EOSR_EOSR12 = 0x1000
	// No effect on output
	PORT1_EOSR_EOSR12_0 = 0x0
	// High output
	PORT1_EOSR_EOSR12_1 = 0x1
	// Position of EOSR13 field.
	PORT1_EOSR_EOSR13_Pos = 0xd
	// Bit mask of EOSR13 field.
	PORT1_EOSR_EOSR13_Msk = 0x2000
	// Bit EOSR13.
	PORT1_EOSR_EOSR13 = 0x2000
	// No effect on output
	PORT1_EOSR_EOSR13_0 = 0x0
	// High output
	PORT1_EOSR_EOSR13_1 = 0x1
	// Position of EOSR14 field.
	PORT1_EOSR_EOSR14_Pos = 0xe
	// Bit mask of EOSR14 field.
	PORT1_EOSR_EOSR14_Msk = 0x4000
	// Bit EOSR14.
	PORT1_EOSR_EOSR14 = 0x4000
	// No effect on output
	PORT1_EOSR_EOSR14_0 = 0x0
	// High output
	PORT1_EOSR_EOSR14_1 = 0x1
	// Position of EOSR15 field.
	PORT1_EOSR_EOSR15_Pos = 0xf
	// Bit mask of EOSR15 field.
	PORT1_EOSR_EOSR15_Msk = 0x8000
	// Bit EOSR15.
	PORT1_EOSR_EOSR15 = 0x8000
	// No effect on output
	PORT1_EOSR_EOSR15_0 = 0x0
	// High output
	PORT1_EOSR_EOSR15_1 = 0x1
)

// Constants for PFS: Control Register
const (
	// P000PFS: Port 00%s Pin Function Select Register
	// Position of PODR field.
	PFS_P00PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P00PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P00PFS_PODR = 0x1
	// Output low
	PFS_P00PFS_PODR_0 = 0x0
	// Output high
	PFS_P00PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P00PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P00PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P00PFS_PIDR = 0x2
	// Low level
	PFS_P00PFS_PIDR_0 = 0x0
	// High level
	PFS_P00PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P00PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P00PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P00PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P00PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P00PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P00PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P00PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P00PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P00PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P00PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P00PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P00PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P00PFS_NCODR = 0x40
	// Output CMOS
	PFS_P00PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P00PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P00PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P00PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P00PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P00PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P00PFS_DSCR_10 = 0x2
	// High drive
	PFS_P00PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P00PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P00PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P00PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P00PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P00PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P00PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P00PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P00PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P00PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P00PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P00PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P00PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P00PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P00PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P00PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P00PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P00PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P00PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P00PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P00PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P00PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P00PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P00PFS_PSEL_Msk = 0x1f000000

	// P000PFS_HA: Port 00%s Pin Function Select Register
	// Position of PODR field.
	PFS_P00PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P00PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P00PFS_HA_PODR = 0x1
	// Output low
	PFS_P00PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P00PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P00PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P00PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P00PFS_HA_PIDR = 0x2
	// Low level
	PFS_P00PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P00PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P00PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P00PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P00PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P00PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P00PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P00PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P00PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P00PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P00PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P00PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P00PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P00PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P00PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P00PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P00PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P00PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P00PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P00PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P00PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P00PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P00PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P00PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P00PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P00PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P00PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P00PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P00PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P00PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P00PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P00PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P00PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P00PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P00PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P00PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P00PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P00PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P00PFS_HA_ASEL_1 = 0x1

	// P000PFS_BY: Port 00%s Pin Function Select Register
	// Position of PODR field.
	PFS_P00PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P00PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P00PFS_BY_PODR = 0x1
	// Output low
	PFS_P00PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P00PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P00PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P00PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P00PFS_BY_PIDR = 0x2
	// Low level
	PFS_P00PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P00PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P00PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P00PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P00PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P00PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P00PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P00PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P00PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P00PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P00PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P00PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P00PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P00PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P00PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P00PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P00PFS_BY_NCODR_1 = 0x1

	// P004PFS: Port 00%s Pin Function Select Register
	// Position of PODR field.
	PFS_P00PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P00PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P00PFS_PODR = 0x1
	// Output low
	PFS_P00PFS_PODR_0 = 0x0
	// Output high
	PFS_P00PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P00PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P00PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P00PFS_PIDR = 0x2
	// Low level
	PFS_P00PFS_PIDR_0 = 0x0
	// High level
	PFS_P00PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P00PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P00PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P00PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P00PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P00PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P00PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P00PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P00PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P00PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P00PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P00PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P00PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P00PFS_NCODR = 0x40
	// Output CMOS
	PFS_P00PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P00PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P00PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P00PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P00PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P00PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P00PFS_DSCR_10 = 0x2
	// High drive
	PFS_P00PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P00PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P00PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P00PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P00PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P00PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P00PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P00PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P00PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P00PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P00PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P00PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P00PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P00PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P00PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P00PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P00PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P00PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P00PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P00PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P00PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P00PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P00PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P00PFS_PSEL_Msk = 0x1f000000

	// P004PFS_HA: Port 00%s Pin Function Select Register
	// Position of PODR field.
	PFS_P00PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P00PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P00PFS_HA_PODR = 0x1
	// Output low
	PFS_P00PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P00PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P00PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P00PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P00PFS_HA_PIDR = 0x2
	// Low level
	PFS_P00PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P00PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P00PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P00PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P00PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P00PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P00PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P00PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P00PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P00PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P00PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P00PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P00PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P00PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P00PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P00PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P00PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P00PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P00PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P00PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P00PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P00PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P00PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P00PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P00PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P00PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P00PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P00PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P00PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P00PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P00PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P00PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P00PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P00PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P00PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P00PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P00PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P00PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P00PFS_HA_ASEL_1 = 0x1

	// P004PFS_BY: Port 00%s Pin Function Select Register
	// Position of PODR field.
	PFS_P00PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P00PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P00PFS_BY_PODR = 0x1
	// Output low
	PFS_P00PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P00PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P00PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P00PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P00PFS_BY_PIDR = 0x2
	// Low level
	PFS_P00PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P00PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P00PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P00PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P00PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P00PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P00PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P00PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P00PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P00PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P00PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P00PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P00PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P00PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P00PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P00PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P00PFS_BY_NCODR_1 = 0x1

	// P008PFS: Port 008 Pin Function Select Register
	// Position of PODR field.
	PFS_P008PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P008PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P008PFS_PODR = 0x1
	// Output low
	PFS_P008PFS_PODR_0 = 0x0
	// Output high
	PFS_P008PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P008PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P008PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P008PFS_PIDR = 0x2
	// Low level
	PFS_P008PFS_PIDR_0 = 0x0
	// High level
	PFS_P008PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P008PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P008PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P008PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P008PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P008PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P008PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P008PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P008PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P008PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P008PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P008PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P008PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P008PFS_NCODR = 0x40
	// Output CMOS
	PFS_P008PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P008PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P008PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P008PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P008PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P008PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P008PFS_DSCR_10 = 0x2
	// High drive
	PFS_P008PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P008PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P008PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P008PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P008PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P008PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P008PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P008PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P008PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P008PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P008PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P008PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P008PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P008PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P008PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P008PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P008PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P008PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P008PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P008PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P008PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P008PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P008PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P008PFS_PSEL_Msk = 0x1f000000

	// P008PFS_HA: Port 008 Pin Function Select Register
	// Position of PODR field.
	PFS_P008PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P008PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P008PFS_HA_PODR = 0x1
	// Output low
	PFS_P008PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P008PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P008PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P008PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P008PFS_HA_PIDR = 0x2
	// Low level
	PFS_P008PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P008PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P008PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P008PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P008PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P008PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P008PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P008PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P008PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P008PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P008PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P008PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P008PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P008PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P008PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P008PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P008PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P008PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P008PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P008PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P008PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P008PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P008PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P008PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P008PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P008PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P008PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P008PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P008PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P008PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P008PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P008PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P008PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P008PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P008PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P008PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P008PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P008PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P008PFS_HA_ASEL_1 = 0x1

	// P008PFS_BY: Port 008 Pin Function Select Register
	// Position of PODR field.
	PFS_P008PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P008PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P008PFS_BY_PODR = 0x1
	// Output low
	PFS_P008PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P008PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P008PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P008PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P008PFS_BY_PIDR = 0x2
	// Low level
	PFS_P008PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P008PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P008PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P008PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P008PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P008PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P008PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P008PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P008PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P008PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P008PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P008PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P008PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P008PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P008PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P008PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P008PFS_BY_NCODR_1 = 0x1

	// P013PFS: Port 0%s Pin Function Select Register
	// Position of PODR field.
	PFS_P0PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P0PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P0PFS_PODR = 0x1
	// Output low
	PFS_P0PFS_PODR_0 = 0x0
	// Output high
	PFS_P0PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P0PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P0PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P0PFS_PIDR = 0x2
	// Low level
	PFS_P0PFS_PIDR_0 = 0x0
	// High level
	PFS_P0PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P0PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P0PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P0PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P0PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P0PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P0PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P0PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P0PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P0PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P0PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P0PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P0PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P0PFS_NCODR = 0x40
	// Output CMOS
	PFS_P0PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P0PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P0PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P0PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P0PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P0PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P0PFS_DSCR_10 = 0x2
	// High drive
	PFS_P0PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P0PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P0PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P0PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P0PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P0PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P0PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P0PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P0PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P0PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P0PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P0PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P0PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P0PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P0PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P0PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P0PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P0PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P0PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P0PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P0PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P0PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P0PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P0PFS_PSEL_Msk = 0x1f000000

	// P013PFS_HA: Port 0%s Pin Function Select Register
	// Position of PODR field.
	PFS_P0PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P0PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P0PFS_HA_PODR = 0x1
	// Output low
	PFS_P0PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P0PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P0PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P0PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P0PFS_HA_PIDR = 0x2
	// Low level
	PFS_P0PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P0PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P0PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P0PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P0PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P0PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P0PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P0PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P0PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P0PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P0PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P0PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P0PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P0PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P0PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P0PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P0PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P0PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P0PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P0PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P0PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P0PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P0PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P0PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P0PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P0PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P0PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P0PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P0PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P0PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P0PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P0PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P0PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P0PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P0PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P0PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P0PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P0PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P0PFS_HA_ASEL_1 = 0x1

	// P013PFS_BY: Port 0%s Pin Function Select Register
	// Position of PODR field.
	PFS_P0PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P0PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P0PFS_BY_PODR = 0x1
	// Output low
	PFS_P0PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P0PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P0PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P0PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P0PFS_BY_PIDR = 0x2
	// Low level
	PFS_P0PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P0PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P0PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P0PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P0PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P0PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P0PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P0PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P0PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P0PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P0PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P0PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P0PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P0PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P0PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P0PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P0PFS_BY_NCODR_1 = 0x1

	// P100PFS: Port 10%s Pin Function Select Register
	// Position of PODR field.
	PFS_P10PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P10PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P10PFS_PODR = 0x1
	// Output low
	PFS_P10PFS_PODR_0 = 0x0
	// Output high
	PFS_P10PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P10PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P10PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P10PFS_PIDR = 0x2
	// Low level
	PFS_P10PFS_PIDR_0 = 0x0
	// High level
	PFS_P10PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P10PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P10PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P10PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P10PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P10PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P10PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P10PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P10PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P10PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P10PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P10PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P10PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P10PFS_NCODR = 0x40
	// Output CMOS
	PFS_P10PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P10PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P10PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P10PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P10PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P10PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P10PFS_DSCR_10 = 0x2
	// High drive
	PFS_P10PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P10PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P10PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P10PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P10PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P10PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P10PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P10PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P10PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P10PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P10PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P10PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P10PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P10PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P10PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P10PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P10PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P10PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P10PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P10PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P10PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P10PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P10PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P10PFS_PSEL_Msk = 0x1f000000

	// P100PFS_HA: Port 10%s Pin Function Select Register
	// Position of PODR field.
	PFS_P10PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P10PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P10PFS_HA_PODR = 0x1
	// Output low
	PFS_P10PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P10PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P10PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P10PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P10PFS_HA_PIDR = 0x2
	// Low level
	PFS_P10PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P10PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P10PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P10PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P10PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P10PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P10PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P10PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P10PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P10PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P10PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P10PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P10PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P10PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P10PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P10PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P10PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P10PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P10PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P10PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P10PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P10PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P10PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P10PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P10PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P10PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P10PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P10PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P10PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P10PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P10PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P10PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P10PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P10PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P10PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P10PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P10PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P10PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P10PFS_HA_ASEL_1 = 0x1

	// P100PFS_BY: Port 10%s Pin Function Select Register
	// Position of PODR field.
	PFS_P10PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P10PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P10PFS_BY_PODR = 0x1
	// Output low
	PFS_P10PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P10PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P10PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P10PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P10PFS_BY_PIDR = 0x2
	// Low level
	PFS_P10PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P10PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P10PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P10PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P10PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P10PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P10PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P10PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P10PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P10PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P10PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P10PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P10PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P10PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P10PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P10PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P10PFS_BY_NCODR_1 = 0x1

	// P102PFS: Port 10%s Pin Function Select Register
	// Position of PODR field.
	PFS_P10PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P10PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P10PFS_PODR = 0x1
	// Output low
	PFS_P10PFS_PODR_0 = 0x0
	// Output high
	PFS_P10PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P10PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P10PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P10PFS_PIDR = 0x2
	// Low level
	PFS_P10PFS_PIDR_0 = 0x0
	// High level
	PFS_P10PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P10PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P10PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P10PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P10PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P10PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P10PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P10PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P10PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P10PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P10PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P10PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P10PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P10PFS_NCODR = 0x40
	// Output CMOS
	PFS_P10PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P10PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P10PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P10PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P10PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P10PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P10PFS_DSCR_10 = 0x2
	// High drive
	PFS_P10PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P10PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P10PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P10PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P10PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P10PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P10PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P10PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P10PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P10PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P10PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P10PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P10PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P10PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P10PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P10PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P10PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P10PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P10PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P10PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P10PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P10PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P10PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P10PFS_PSEL_Msk = 0x1f000000

	// P102PFS_HA: Port 10%s Pin Function Select Register
	// Position of PODR field.
	PFS_P10PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P10PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P10PFS_HA_PODR = 0x1
	// Output low
	PFS_P10PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P10PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P10PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P10PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P10PFS_HA_PIDR = 0x2
	// Low level
	PFS_P10PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P10PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P10PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P10PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P10PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P10PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P10PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P10PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P10PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P10PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P10PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P10PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P10PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P10PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P10PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P10PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P10PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P10PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P10PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P10PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P10PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P10PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P10PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P10PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P10PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P10PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P10PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P10PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P10PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P10PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P10PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P10PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P10PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P10PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P10PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P10PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P10PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P10PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P10PFS_HA_ASEL_1 = 0x1

	// P102PFS_BY: Port 10%s Pin Function Select Register
	// Position of PODR field.
	PFS_P10PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P10PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P10PFS_BY_PODR = 0x1
	// Output low
	PFS_P10PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P10PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P10PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P10PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P10PFS_BY_PIDR = 0x2
	// Low level
	PFS_P10PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P10PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P10PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P10PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P10PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P10PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P10PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P10PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P10PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P10PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P10PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P10PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P10PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P10PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P10PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P10PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P10PFS_BY_NCODR_1 = 0x1

	// P110PFS: Port 1%s Pin Function Select Register
	// Position of PODR field.
	PFS_P1PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P1PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P1PFS_PODR = 0x1
	// Output low
	PFS_P1PFS_PODR_0 = 0x0
	// Output high
	PFS_P1PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P1PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P1PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P1PFS_PIDR = 0x2
	// Low level
	PFS_P1PFS_PIDR_0 = 0x0
	// High level
	PFS_P1PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P1PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P1PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P1PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P1PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P1PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P1PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P1PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P1PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P1PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P1PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P1PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P1PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P1PFS_NCODR = 0x40
	// Output CMOS
	PFS_P1PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P1PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P1PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P1PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P1PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P1PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P1PFS_DSCR_10 = 0x2
	// High drive
	PFS_P1PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P1PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P1PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P1PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P1PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P1PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P1PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P1PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P1PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P1PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P1PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P1PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P1PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P1PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P1PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P1PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P1PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P1PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P1PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P1PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P1PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P1PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P1PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P1PFS_PSEL_Msk = 0x1f000000

	// P110PFS_HA: Port 1%s Pin Function Select Register
	// Position of PODR field.
	PFS_P1PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P1PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P1PFS_HA_PODR = 0x1
	// Output low
	PFS_P1PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P1PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P1PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P1PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P1PFS_HA_PIDR = 0x2
	// Low level
	PFS_P1PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P1PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P1PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P1PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P1PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P1PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P1PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P1PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P1PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P1PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P1PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P1PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P1PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P1PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P1PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P1PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P1PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P1PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P1PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P1PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P1PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P1PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P1PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P1PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P1PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P1PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P1PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P1PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P1PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P1PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P1PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P1PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P1PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P1PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P1PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P1PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P1PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P1PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P1PFS_HA_ASEL_1 = 0x1

	// P110PFS_BY: Port 1%s Pin Function Select Register
	// Position of PODR field.
	PFS_P1PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P1PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P1PFS_BY_PODR = 0x1
	// Output low
	PFS_P1PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P1PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P1PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P1PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P1PFS_BY_PIDR = 0x2
	// Low level
	PFS_P1PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P1PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P1PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P1PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P1PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P1PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P1PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P1PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P1PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P1PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P1PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P1PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P1PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P1PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P1PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P1PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P1PFS_BY_NCODR_1 = 0x1

	// P200PFS: Port 200 Pin Function Select Register
	// Position of PODR field.
	PFS_P200PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P200PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P200PFS_PODR = 0x1
	// Output low
	PFS_P200PFS_PODR_0 = 0x0
	// Output high
	PFS_P200PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P200PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P200PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P200PFS_PIDR = 0x2
	// Low level
	PFS_P200PFS_PIDR_0 = 0x0
	// High level
	PFS_P200PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P200PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P200PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P200PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P200PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P200PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P200PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P200PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P200PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P200PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P200PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P200PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P200PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P200PFS_NCODR = 0x40
	// Output CMOS
	PFS_P200PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P200PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P200PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P200PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P200PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P200PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P200PFS_DSCR_10 = 0x2
	// High drive
	PFS_P200PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P200PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P200PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P200PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P200PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P200PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P200PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P200PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P200PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P200PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P200PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P200PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P200PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P200PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P200PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P200PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P200PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P200PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P200PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P200PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P200PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P200PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P200PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P200PFS_PSEL_Msk = 0x1f000000

	// P200PFS_HA: Port 200 Pin Function Select Register
	// Position of PODR field.
	PFS_P200PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P200PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P200PFS_HA_PODR = 0x1
	// Output low
	PFS_P200PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P200PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P200PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P200PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P200PFS_HA_PIDR = 0x2
	// Low level
	PFS_P200PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P200PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P200PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P200PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P200PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P200PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P200PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P200PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P200PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P200PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P200PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P200PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P200PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P200PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P200PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P200PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P200PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P200PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P200PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P200PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P200PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P200PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P200PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P200PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P200PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P200PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P200PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P200PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P200PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P200PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P200PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P200PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P200PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P200PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P200PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P200PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P200PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P200PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P200PFS_HA_ASEL_1 = 0x1

	// P200PFS_BY: Port 200 Pin Function Select Register
	// Position of PODR field.
	PFS_P200PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P200PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P200PFS_BY_PODR = 0x1
	// Output low
	PFS_P200PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P200PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P200PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P200PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P200PFS_BY_PIDR = 0x2
	// Low level
	PFS_P200PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P200PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P200PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P200PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P200PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P200PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P200PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P200PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P200PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P200PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P200PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P200PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P200PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P200PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P200PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P200PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P200PFS_BY_NCODR_1 = 0x1

	// P201PFS: Port 201 Pin Function Select Register
	// Position of PODR field.
	PFS_P201PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P201PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P201PFS_PODR = 0x1
	// Output low
	PFS_P201PFS_PODR_0 = 0x0
	// Output high
	PFS_P201PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P201PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P201PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P201PFS_PIDR = 0x2
	// Low level
	PFS_P201PFS_PIDR_0 = 0x0
	// High level
	PFS_P201PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P201PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P201PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P201PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P201PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P201PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P201PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P201PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P201PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P201PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P201PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P201PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P201PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P201PFS_NCODR = 0x40
	// Output CMOS
	PFS_P201PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P201PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P201PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P201PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P201PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P201PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P201PFS_DSCR_10 = 0x2
	// High drive
	PFS_P201PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P201PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P201PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P201PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P201PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P201PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P201PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P201PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P201PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P201PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P201PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P201PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P201PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P201PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P201PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P201PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P201PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P201PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P201PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P201PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P201PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P201PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P201PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P201PFS_PSEL_Msk = 0x1f000000

	// P201PFS_HA: Port 201 Pin Function Select Register
	// Position of PODR field.
	PFS_P201PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P201PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P201PFS_HA_PODR = 0x1
	// Output low
	PFS_P201PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P201PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P201PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P201PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P201PFS_HA_PIDR = 0x2
	// Low level
	PFS_P201PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P201PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P201PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P201PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P201PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P201PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P201PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P201PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P201PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P201PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P201PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P201PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P201PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P201PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P201PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P201PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P201PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P201PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P201PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P201PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P201PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P201PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P201PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P201PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P201PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P201PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P201PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P201PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P201PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P201PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P201PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P201PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P201PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P201PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P201PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P201PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P201PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P201PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P201PFS_HA_ASEL_1 = 0x1

	// P201PFS_BY: Port 201 Pin Function Select Register
	// Position of PODR field.
	PFS_P201PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P201PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P201PFS_BY_PODR = 0x1
	// Output low
	PFS_P201PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P201PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P201PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P201PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P201PFS_BY_PIDR = 0x2
	// Low level
	PFS_P201PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P201PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P201PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P201PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P201PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P201PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P201PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P201PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P201PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P201PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P201PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P201PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P201PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P201PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P201PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P201PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P201PFS_BY_NCODR_1 = 0x1

	// P205PFS: Port 20%s Pin Function Select Register
	// Position of PODR field.
	PFS_P20PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P20PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P20PFS_PODR = 0x1
	// Output low
	PFS_P20PFS_PODR_0 = 0x0
	// Output high
	PFS_P20PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P20PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P20PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P20PFS_PIDR = 0x2
	// Low level
	PFS_P20PFS_PIDR_0 = 0x0
	// High level
	PFS_P20PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P20PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P20PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P20PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P20PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P20PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P20PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P20PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P20PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P20PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P20PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P20PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P20PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P20PFS_NCODR = 0x40
	// Output CMOS
	PFS_P20PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P20PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P20PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P20PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P20PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P20PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P20PFS_DSCR_10 = 0x2
	// High drive
	PFS_P20PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P20PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P20PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P20PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P20PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P20PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P20PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P20PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P20PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P20PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P20PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P20PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P20PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P20PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P20PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P20PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P20PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P20PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P20PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P20PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P20PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P20PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P20PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P20PFS_PSEL_Msk = 0x1f000000

	// P205PFS_HA: Port 20%s Pin Function Select Register
	// Position of PODR field.
	PFS_P20PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P20PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P20PFS_HA_PODR = 0x1
	// Output low
	PFS_P20PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P20PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P20PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P20PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P20PFS_HA_PIDR = 0x2
	// Low level
	PFS_P20PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P20PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P20PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P20PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P20PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P20PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P20PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P20PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P20PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P20PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P20PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P20PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P20PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P20PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P20PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P20PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P20PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P20PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P20PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P20PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P20PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P20PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P20PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P20PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P20PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P20PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P20PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P20PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P20PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P20PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P20PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P20PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P20PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P20PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P20PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P20PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P20PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P20PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P20PFS_HA_ASEL_1 = 0x1

	// P205PFS_BY: Port 20%s Pin Function Select Register
	// Position of PODR field.
	PFS_P20PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P20PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P20PFS_BY_PODR = 0x1
	// Output low
	PFS_P20PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P20PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P20PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P20PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P20PFS_BY_PIDR = 0x2
	// Low level
	PFS_P20PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P20PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P20PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P20PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P20PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P20PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P20PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P20PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P20PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P20PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P20PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P20PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P20PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P20PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P20PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P20PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P20PFS_BY_NCODR_1 = 0x1

	// P212PFS: Port 2%s Pin Function Select Register
	// Position of PODR field.
	PFS_P2PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P2PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P2PFS_PODR = 0x1
	// Output low
	PFS_P2PFS_PODR_0 = 0x0
	// Output high
	PFS_P2PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P2PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P2PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P2PFS_PIDR = 0x2
	// Low level
	PFS_P2PFS_PIDR_0 = 0x0
	// High level
	PFS_P2PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P2PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P2PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P2PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P2PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P2PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P2PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P2PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P2PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P2PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P2PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P2PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P2PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P2PFS_NCODR = 0x40
	// Output CMOS
	PFS_P2PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P2PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P2PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P2PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P2PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P2PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P2PFS_DSCR_10 = 0x2
	// High drive
	PFS_P2PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P2PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P2PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P2PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P2PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P2PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P2PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P2PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P2PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P2PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P2PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P2PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P2PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P2PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P2PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P2PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P2PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P2PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P2PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P2PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P2PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P2PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P2PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P2PFS_PSEL_Msk = 0x1f000000

	// P212PFS_HA: Port 2%s Pin Function Select Register
	// Position of PODR field.
	PFS_P2PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P2PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P2PFS_HA_PODR = 0x1
	// Output low
	PFS_P2PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P2PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P2PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P2PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P2PFS_HA_PIDR = 0x2
	// Low level
	PFS_P2PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P2PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P2PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P2PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P2PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P2PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P2PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P2PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P2PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P2PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P2PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P2PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P2PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P2PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P2PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P2PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P2PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P2PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P2PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P2PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P2PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P2PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P2PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P2PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P2PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P2PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P2PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P2PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P2PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P2PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P2PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P2PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P2PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P2PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P2PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P2PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P2PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P2PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P2PFS_HA_ASEL_1 = 0x1

	// P212PFS_BY: Port 2%s Pin Function Select Register
	// Position of PODR field.
	PFS_P2PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P2PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P2PFS_BY_PODR = 0x1
	// Output low
	PFS_P2PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P2PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P2PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P2PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P2PFS_BY_PIDR = 0x2
	// Low level
	PFS_P2PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P2PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P2PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P2PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P2PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P2PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P2PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P2PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P2PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P2PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P2PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P2PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P2PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P2PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P2PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P2PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P2PFS_BY_NCODR_1 = 0x1

	// P300PFS: Port 300 Pin Function Select Register
	// Position of PODR field.
	PFS_P300PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P300PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P300PFS_PODR = 0x1
	// Output low
	PFS_P300PFS_PODR_0 = 0x0
	// Output high
	PFS_P300PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P300PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P300PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P300PFS_PIDR = 0x2
	// Low level
	PFS_P300PFS_PIDR_0 = 0x0
	// High level
	PFS_P300PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P300PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P300PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P300PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P300PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P300PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P300PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P300PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P300PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P300PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P300PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P300PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P300PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P300PFS_NCODR = 0x40
	// Output CMOS
	PFS_P300PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P300PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P300PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P300PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P300PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P300PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P300PFS_DSCR_10 = 0x2
	// High drive
	PFS_P300PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P300PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P300PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P300PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P300PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P300PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P300PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P300PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P300PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P300PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P300PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P300PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P300PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P300PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P300PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P300PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P300PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P300PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P300PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P300PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P300PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P300PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P300PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P300PFS_PSEL_Msk = 0x1f000000

	// P300PFS_HA: Port 300 Pin Function Select Register
	// Position of PODR field.
	PFS_P300PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P300PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P300PFS_HA_PODR = 0x1
	// Output low
	PFS_P300PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P300PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P300PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P300PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P300PFS_HA_PIDR = 0x2
	// Low level
	PFS_P300PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P300PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P300PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P300PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P300PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P300PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P300PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P300PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P300PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P300PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P300PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P300PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P300PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P300PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P300PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P300PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P300PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P300PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P300PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P300PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P300PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P300PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P300PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P300PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P300PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P300PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P300PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P300PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P300PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P300PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P300PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P300PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P300PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P300PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P300PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P300PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P300PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P300PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P300PFS_HA_ASEL_1 = 0x1

	// P300PFS_BY: Port 300 Pin Function Select Register
	// Position of PODR field.
	PFS_P300PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P300PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P300PFS_BY_PODR = 0x1
	// Output low
	PFS_P300PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P300PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P300PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P300PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P300PFS_BY_PIDR = 0x2
	// Low level
	PFS_P300PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P300PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P300PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P300PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P300PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P300PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P300PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P300PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P300PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P300PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P300PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P300PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P300PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P300PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P300PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P300PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P300PFS_BY_NCODR_1 = 0x1

	// P301PFS: Port 30%s Pin Function Select Register
	// Position of PODR field.
	PFS_P30PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P30PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P30PFS_PODR = 0x1
	// Output low
	PFS_P30PFS_PODR_0 = 0x0
	// Output high
	PFS_P30PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P30PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P30PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P30PFS_PIDR = 0x2
	// Low level
	PFS_P30PFS_PIDR_0 = 0x0
	// High level
	PFS_P30PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P30PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P30PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P30PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P30PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P30PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P30PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P30PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P30PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P30PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P30PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P30PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P30PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P30PFS_NCODR = 0x40
	// Output CMOS
	PFS_P30PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P30PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P30PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P30PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P30PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P30PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P30PFS_DSCR_10 = 0x2
	// High drive
	PFS_P30PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P30PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P30PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P30PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P30PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P30PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P30PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P30PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P30PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P30PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P30PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P30PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P30PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P30PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P30PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P30PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P30PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P30PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P30PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P30PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P30PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P30PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P30PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P30PFS_PSEL_Msk = 0x1f000000

	// P301PFS_HA: Port 30%s Pin Function Select Register
	// Position of PODR field.
	PFS_P30PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P30PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P30PFS_HA_PODR = 0x1
	// Output low
	PFS_P30PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P30PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P30PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P30PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P30PFS_HA_PIDR = 0x2
	// Low level
	PFS_P30PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P30PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P30PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P30PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P30PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P30PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P30PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P30PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P30PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P30PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P30PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P30PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P30PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P30PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P30PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P30PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P30PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P30PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P30PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P30PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P30PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P30PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P30PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P30PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P30PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P30PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P30PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P30PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P30PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P30PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P30PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P30PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P30PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P30PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P30PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P30PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P30PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P30PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P30PFS_HA_ASEL_1 = 0x1

	// P301PFS_BY: Port 30%s Pin Function Select Register
	// Position of PODR field.
	PFS_P30PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P30PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P30PFS_BY_PODR = 0x1
	// Output low
	PFS_P30PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P30PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P30PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P30PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P30PFS_BY_PIDR = 0x2
	// Low level
	PFS_P30PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P30PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P30PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P30PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P30PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P30PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P30PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P30PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P30PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P30PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P30PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P30PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P30PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P30PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P30PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P30PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P30PFS_BY_NCODR_1 = 0x1

	// P400PFS: Port 40%s Pin Function Select Register
	// Position of PODR field.
	PFS_P40PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P40PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P40PFS_PODR = 0x1
	// Output low
	PFS_P40PFS_PODR_0 = 0x0
	// Output high
	PFS_P40PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P40PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P40PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P40PFS_PIDR = 0x2
	// Low level
	PFS_P40PFS_PIDR_0 = 0x0
	// High level
	PFS_P40PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P40PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P40PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P40PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P40PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P40PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P40PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P40PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P40PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P40PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P40PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P40PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P40PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P40PFS_NCODR = 0x40
	// Output CMOS
	PFS_P40PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P40PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P40PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P40PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P40PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P40PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P40PFS_DSCR_10 = 0x2
	// High drive
	PFS_P40PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P40PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P40PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P40PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P40PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P40PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P40PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P40PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P40PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P40PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P40PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P40PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P40PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P40PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P40PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P40PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P40PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P40PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P40PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P40PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P40PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P40PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P40PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P40PFS_PSEL_Msk = 0x1f000000

	// P400PFS_HA: Port 40%s Pin Function Select Register
	// Position of PODR field.
	PFS_P40PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P40PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P40PFS_HA_PODR = 0x1
	// Output low
	PFS_P40PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P40PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P40PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P40PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P40PFS_HA_PIDR = 0x2
	// Low level
	PFS_P40PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P40PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P40PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P40PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P40PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P40PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P40PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P40PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P40PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P40PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P40PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P40PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P40PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P40PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P40PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P40PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P40PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P40PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P40PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P40PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P40PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P40PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P40PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P40PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P40PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P40PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P40PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P40PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P40PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P40PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P40PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P40PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P40PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P40PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P40PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P40PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P40PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P40PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P40PFS_HA_ASEL_1 = 0x1

	// P400PFS_BY: Port 40%s Pin Function Select Register
	// Position of PODR field.
	PFS_P40PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P40PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P40PFS_BY_PODR = 0x1
	// Output low
	PFS_P40PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P40PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P40PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P40PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P40PFS_BY_PIDR = 0x2
	// Low level
	PFS_P40PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P40PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P40PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P40PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P40PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P40PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P40PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P40PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P40PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P40PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P40PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P40PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P40PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P40PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P40PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P40PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P40PFS_BY_NCODR_1 = 0x1

	// P407PFS: Port 40%s Pin Function Select Register
	// Position of PODR field.
	PFS_P40PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P40PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P40PFS_PODR = 0x1
	// Output low
	PFS_P40PFS_PODR_0 = 0x0
	// Output high
	PFS_P40PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P40PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P40PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P40PFS_PIDR = 0x2
	// Low level
	PFS_P40PFS_PIDR_0 = 0x0
	// High level
	PFS_P40PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P40PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P40PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P40PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P40PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P40PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P40PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P40PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P40PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P40PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P40PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P40PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P40PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P40PFS_NCODR = 0x40
	// Output CMOS
	PFS_P40PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P40PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P40PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P40PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P40PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P40PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P40PFS_DSCR_10 = 0x2
	// High drive
	PFS_P40PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P40PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P40PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P40PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P40PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P40PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P40PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P40PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P40PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P40PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P40PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P40PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P40PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P40PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P40PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P40PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P40PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P40PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P40PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P40PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P40PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P40PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P40PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P40PFS_PSEL_Msk = 0x1f000000

	// P407PFS_HA: Port 40%s Pin Function Select Register
	// Position of PODR field.
	PFS_P40PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P40PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P40PFS_HA_PODR = 0x1
	// Output low
	PFS_P40PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P40PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P40PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P40PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P40PFS_HA_PIDR = 0x2
	// Low level
	PFS_P40PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P40PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P40PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P40PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P40PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P40PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P40PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P40PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P40PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P40PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P40PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P40PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P40PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P40PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P40PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P40PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P40PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P40PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P40PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P40PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P40PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P40PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P40PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P40PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P40PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P40PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P40PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P40PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P40PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P40PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P40PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P40PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P40PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P40PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P40PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P40PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P40PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P40PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P40PFS_HA_ASEL_1 = 0x1

	// P407PFS_BY: Port 40%s Pin Function Select Register
	// Position of PODR field.
	PFS_P40PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P40PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P40PFS_BY_PODR = 0x1
	// Output low
	PFS_P40PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P40PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P40PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P40PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P40PFS_BY_PIDR = 0x2
	// Low level
	PFS_P40PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P40PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P40PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P40PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P40PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P40PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P40PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P40PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P40PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P40PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P40PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P40PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P40PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P40PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P40PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P40PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P40PFS_BY_NCODR_1 = 0x1

	// P410PFS: Port 4%s Pin Function Select Register
	// Position of PODR field.
	PFS_P4PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P4PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P4PFS_PODR = 0x1
	// Output low
	PFS_P4PFS_PODR_0 = 0x0
	// Output high
	PFS_P4PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P4PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P4PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P4PFS_PIDR = 0x2
	// Low level
	PFS_P4PFS_PIDR_0 = 0x0
	// High level
	PFS_P4PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P4PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P4PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P4PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P4PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P4PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P4PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P4PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P4PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P4PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P4PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P4PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P4PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P4PFS_NCODR = 0x40
	// Output CMOS
	PFS_P4PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P4PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P4PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P4PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P4PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P4PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P4PFS_DSCR_10 = 0x2
	// High drive
	PFS_P4PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P4PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P4PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P4PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P4PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P4PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P4PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P4PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P4PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P4PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P4PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P4PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P4PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P4PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P4PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P4PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P4PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P4PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P4PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P4PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P4PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P4PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P4PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P4PFS_PSEL_Msk = 0x1f000000

	// P410PFS_HA: Port 4%s Pin Function Select Register
	// Position of PODR field.
	PFS_P4PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P4PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P4PFS_HA_PODR = 0x1
	// Output low
	PFS_P4PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P4PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P4PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P4PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P4PFS_HA_PIDR = 0x2
	// Low level
	PFS_P4PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P4PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P4PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P4PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P4PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P4PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P4PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P4PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P4PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P4PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P4PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P4PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P4PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P4PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P4PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P4PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P4PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P4PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P4PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P4PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P4PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P4PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P4PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P4PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P4PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P4PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P4PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P4PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P4PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P4PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P4PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P4PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P4PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P4PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P4PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P4PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P4PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P4PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P4PFS_HA_ASEL_1 = 0x1

	// P410PFS_BY: Port 4%s Pin Function Select Register
	// Position of PODR field.
	PFS_P4PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P4PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P4PFS_BY_PODR = 0x1
	// Output low
	PFS_P4PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P4PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P4PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P4PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P4PFS_BY_PIDR = 0x2
	// Low level
	PFS_P4PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P4PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P4PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P4PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P4PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P4PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P4PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P4PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P4PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P4PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P4PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P4PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P4PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P4PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P4PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P4PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P4PFS_BY_NCODR_1 = 0x1

	// P500PFS: Port 500 Pin Function Select Register
	// Position of PODR field.
	PFS_P500PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P500PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P500PFS_PODR = 0x1
	// Output low
	PFS_P500PFS_PODR_0 = 0x0
	// Output high
	PFS_P500PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P500PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P500PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P500PFS_PIDR = 0x2
	// Low level
	PFS_P500PFS_PIDR_0 = 0x0
	// High level
	PFS_P500PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P500PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P500PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P500PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P500PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P500PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P500PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P500PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P500PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P500PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P500PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P500PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P500PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P500PFS_NCODR = 0x40
	// Output CMOS
	PFS_P500PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P500PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P500PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P500PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P500PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P500PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P500PFS_DSCR_10 = 0x2
	// High drive
	PFS_P500PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P500PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P500PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P500PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P500PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P500PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P500PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P500PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P500PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P500PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P500PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P500PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P500PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P500PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P500PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P500PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P500PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P500PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P500PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P500PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P500PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P500PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P500PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P500PFS_PSEL_Msk = 0x1f000000

	// P500PFS_HA: Port 500 Pin Function Select Register
	// Position of PODR field.
	PFS_P500PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P500PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P500PFS_HA_PODR = 0x1
	// Output low
	PFS_P500PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P500PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P500PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P500PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P500PFS_HA_PIDR = 0x2
	// Low level
	PFS_P500PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P500PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P500PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P500PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P500PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P500PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P500PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P500PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P500PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P500PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P500PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P500PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P500PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P500PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P500PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P500PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P500PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P500PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P500PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P500PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P500PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P500PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P500PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P500PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P500PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P500PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P500PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P500PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P500PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P500PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P500PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P500PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P500PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P500PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P500PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P500PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P500PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P500PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P500PFS_HA_ASEL_1 = 0x1

	// P500PFS_BY: Port 500 Pin Function Select Register
	// Position of PODR field.
	PFS_P500PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P500PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P500PFS_BY_PODR = 0x1
	// Output low
	PFS_P500PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P500PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P500PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P500PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P500PFS_BY_PIDR = 0x2
	// Low level
	PFS_P500PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P500PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P500PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P500PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P500PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P500PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P500PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P500PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P500PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P500PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P500PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P500PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P500PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P500PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P500PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P500PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P500PFS_BY_NCODR_1 = 0x1

	// P8014PFS: Port 80%s Pin Function Select Register
	// Position of PODR field.
	PFS_P80PFS_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P80PFS_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P80PFS_PODR = 0x1
	// Output low
	PFS_P80PFS_PODR_0 = 0x0
	// Output high
	PFS_P80PFS_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P80PFS_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P80PFS_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P80PFS_PIDR = 0x2
	// Low level
	PFS_P80PFS_PIDR_0 = 0x0
	// High level
	PFS_P80PFS_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P80PFS_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P80PFS_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P80PFS_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P80PFS_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P80PFS_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P80PFS_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P80PFS_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P80PFS_PCR = 0x10
	// Disable input pull-up
	PFS_P80PFS_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P80PFS_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P80PFS_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P80PFS_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P80PFS_NCODR = 0x40
	// Output CMOS
	PFS_P80PFS_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P80PFS_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P80PFS_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P80PFS_DSCR_Msk = 0xc00
	// Low drive
	PFS_P80PFS_DSCR_00 = 0x0
	// Middle drive
	PFS_P80PFS_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P80PFS_DSCR_10 = 0x2
	// High drive
	PFS_P80PFS_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P80PFS_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P80PFS_EOFR_Msk = 0x3000
	// Don't care
	PFS_P80PFS_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P80PFS_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P80PFS_EOFR_10 = 0x2
	// Detect both edges
	PFS_P80PFS_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P80PFS_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P80PFS_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P80PFS_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P80PFS_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P80PFS_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P80PFS_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P80PFS_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P80PFS_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P80PFS_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P80PFS_ASEL_1 = 0x1
	// Position of PMR field.
	PFS_P80PFS_PMR_Pos = 0x10
	// Bit mask of PMR field.
	PFS_P80PFS_PMR_Msk = 0x10000
	// Bit PMR.
	PFS_P80PFS_PMR = 0x10000
	// Use as general I/O pin
	PFS_P80PFS_PMR_0 = 0x0
	// Use as I/O port for peripheral functions
	PFS_P80PFS_PMR_1 = 0x1
	// Position of PSEL field.
	PFS_P80PFS_PSEL_Pos = 0x18
	// Bit mask of PSEL field.
	PFS_P80PFS_PSEL_Msk = 0x1f000000

	// P8014PFS_HA: Port 80%s Pin Function Select Register
	// Position of PODR field.
	PFS_P80PFS_HA_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P80PFS_HA_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P80PFS_HA_PODR = 0x1
	// Output low
	PFS_P80PFS_HA_PODR_0 = 0x0
	// Output high
	PFS_P80PFS_HA_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P80PFS_HA_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P80PFS_HA_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P80PFS_HA_PIDR = 0x2
	// Low level
	PFS_P80PFS_HA_PIDR_0 = 0x0
	// High level
	PFS_P80PFS_HA_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P80PFS_HA_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P80PFS_HA_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P80PFS_HA_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P80PFS_HA_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P80PFS_HA_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P80PFS_HA_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P80PFS_HA_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P80PFS_HA_PCR = 0x10
	// Disable input pull-up
	PFS_P80PFS_HA_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P80PFS_HA_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P80PFS_HA_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P80PFS_HA_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P80PFS_HA_NCODR = 0x40
	// Output CMOS
	PFS_P80PFS_HA_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P80PFS_HA_NCODR_1 = 0x1
	// Position of DSCR field.
	PFS_P80PFS_HA_DSCR_Pos = 0xa
	// Bit mask of DSCR field.
	PFS_P80PFS_HA_DSCR_Msk = 0xc00
	// Low drive
	PFS_P80PFS_HA_DSCR_00 = 0x0
	// Middle drive
	PFS_P80PFS_HA_DSCR_01 = 0x1
	// Setting prohibited
	PFS_P80PFS_HA_DSCR_10 = 0x2
	// High drive
	PFS_P80PFS_HA_DSCR_11 = 0x3
	// Position of EOFR field.
	PFS_P80PFS_HA_EOFR_Pos = 0xc
	// Bit mask of EOFR field.
	PFS_P80PFS_HA_EOFR_Msk = 0x3000
	// Don't care
	PFS_P80PFS_HA_EOFR_00 = 0x0
	// Detect rising edge
	PFS_P80PFS_HA_EOFR_01 = 0x1
	// Detect falling edge
	PFS_P80PFS_HA_EOFR_10 = 0x2
	// Detect both edges
	PFS_P80PFS_HA_EOFR_11 = 0x3
	// Position of ISEL field.
	PFS_P80PFS_HA_ISEL_Pos = 0xe
	// Bit mask of ISEL field.
	PFS_P80PFS_HA_ISEL_Msk = 0x4000
	// Bit ISEL.
	PFS_P80PFS_HA_ISEL = 0x4000
	// Do not use as IRQn input pin
	PFS_P80PFS_HA_ISEL_0 = 0x0
	// Use as IRQn input pin
	PFS_P80PFS_HA_ISEL_1 = 0x1
	// Position of ASEL field.
	PFS_P80PFS_HA_ASEL_Pos = 0xf
	// Bit mask of ASEL field.
	PFS_P80PFS_HA_ASEL_Msk = 0x8000
	// Bit ASEL.
	PFS_P80PFS_HA_ASEL = 0x8000
	// Do not use as analog pin
	PFS_P80PFS_HA_ASEL_0 = 0x0
	// Use as analog pin
	PFS_P80PFS_HA_ASEL_1 = 0x1

	// P8014PFS_BY: Port 80%s Pin Function Select Register
	// Position of PODR field.
	PFS_P80PFS_BY_PODR_Pos = 0x0
	// Bit mask of PODR field.
	PFS_P80PFS_BY_PODR_Msk = 0x1
	// Bit PODR.
	PFS_P80PFS_BY_PODR = 0x1
	// Output low
	PFS_P80PFS_BY_PODR_0 = 0x0
	// Output high
	PFS_P80PFS_BY_PODR_1 = 0x1
	// Position of PIDR field.
	PFS_P80PFS_BY_PIDR_Pos = 0x1
	// Bit mask of PIDR field.
	PFS_P80PFS_BY_PIDR_Msk = 0x2
	// Bit PIDR.
	PFS_P80PFS_BY_PIDR = 0x2
	// Low level
	PFS_P80PFS_BY_PIDR_0 = 0x0
	// High level
	PFS_P80PFS_BY_PIDR_1 = 0x1
	// Position of PDR field.
	PFS_P80PFS_BY_PDR_Pos = 0x2
	// Bit mask of PDR field.
	PFS_P80PFS_BY_PDR_Msk = 0x4
	// Bit PDR.
	PFS_P80PFS_BY_PDR = 0x4
	// Input (functions as an input pin)
	PFS_P80PFS_BY_PDR_0 = 0x0
	// Output (functions as an output pin)
	PFS_P80PFS_BY_PDR_1 = 0x1
	// Position of PCR field.
	PFS_P80PFS_BY_PCR_Pos = 0x4
	// Bit mask of PCR field.
	PFS_P80PFS_BY_PCR_Msk = 0x10
	// Bit PCR.
	PFS_P80PFS_BY_PCR = 0x10
	// Disable input pull-up
	PFS_P80PFS_BY_PCR_0 = 0x0
	// Enable input pull-up
	PFS_P80PFS_BY_PCR_1 = 0x1
	// Position of NCODR field.
	PFS_P80PFS_BY_NCODR_Pos = 0x6
	// Bit mask of NCODR field.
	PFS_P80PFS_BY_NCODR_Msk = 0x40
	// Bit NCODR.
	PFS_P80PFS_BY_NCODR = 0x40
	// Output CMOS
	PFS_P80PFS_BY_NCODR_0 = 0x0
	// Output NMOS open-drain
	PFS_P80PFS_BY_NCODR_1 = 0x1

	// PWPR: Write-Protect Register
	// Position of PFSWE field.
	PFS_PWPR_PFSWE_Pos = 0x6
	// Bit mask of PFSWE field.
	PFS_PWPR_PFSWE_Msk = 0x40
	// Bit PFSWE.
	PFS_PWPR_PFSWE = 0x40
	// Writing to the PmnPFS register is disabled
	PFS_PWPR_PFSWE_0 = 0x0
	// Writing to the PmnPFS register is enabled
	PFS_PWPR_PFSWE_1 = 0x1
	// Position of B0WI field.
	PFS_PWPR_B0WI_Pos = 0x7
	// Bit mask of B0WI field.
	PFS_PWPR_B0WI_Msk = 0x80
	// Bit B0WI.
	PFS_PWPR_B0WI = 0x80
	// Writing to the PFSWE bit is enabled
	PFS_PWPR_B0WI_0 = 0x0
	// Writing to the PFSWE bit is disabled
	PFS_PWPR_B0WI_1 = 0x1

	// PWPRS: Write-Protect Register for Secure
	// Position of PFSWE field.
	PFS_PWPRS_PFSWE_Pos = 0x6
	// Bit mask of PFSWE field.
	PFS_PWPRS_PFSWE_Msk = 0x40
	// Bit PFSWE.
	PFS_PWPRS_PFSWE = 0x40
	// Disable writes to the PmnPFS register
	PFS_PWPRS_PFSWE_0 = 0x0
	// Enable writes to the PmnPFS register
	PFS_PWPRS_PFSWE_1 = 0x1
	// Position of B0WI field.
	PFS_PWPRS_B0WI_Pos = 0x7
	// Bit mask of B0WI field.
	PFS_PWPRS_B0WI_Msk = 0x80
	// Bit B0WI.
	PFS_PWPRS_B0WI = 0x80
	// Enable writes the PFSWE bit
	PFS_PWPRS_B0WI_0 = 0x0
	// Disable writes to the PFSWE bit
	PFS_PWPRS_B0WI_1 = 0x1

	// PFI3C: RI3C Slope Control Register
	// Position of I3CSLOPE0 field.
	PFS_PFI3C_I3CSLOPE0_Pos = 0x0
	// Bit mask of I3CSLOPE0 field.
	PFS_PFI3C_I3CSLOPE0_Msk = 0x1
	// Bit I3CSLOPE0.
	PFS_PFI3C_I3CSLOPE0 = 0x1
	// I3C mode slope control disable
	PFS_PFI3C_I3CSLOPE0_0 = 0x0
	// I3C mode slope control enable
	PFS_PFI3C_I3CSLOPE0_1 = 0x1

	// P0SAR: Port Security Attribution register
	// Position of PMNSA field.
	PFS_PSAR_PMNSA_Pos = 0x0
	// Bit mask of PMNSA field.
	PFS_PSAR_PMNSA_Msk = 0xffff
	// Secure
	PFS_PSAR_PMNSA_0 = 0x0
	// Non Secure
	PFS_PSAR_PMNSA_1 = 0x1

	// P8SAR: Port Security Attribution register
	// Position of PMNSA field.
	PFS_P8SAR_PMNSA_Pos = 0x0
	// Bit mask of PMNSA field.
	PFS_P8SAR_PMNSA_Msk = 0xffff
	// Secure
	PFS_P8SAR_PMNSA_0 = 0x0
	// Non Secure
	PFS_P8SAR_PMNSA_1 = 0x1
)

// Constants for ELC: Event Link Controller
const (
	// ELCR: Event Link Controller Register
	// Position of ELCON field.
	ELC_ELCR_ELCON_Pos = 0x7
	// Bit mask of ELCON field.
	ELC_ELCR_ELCON_Msk = 0x80
	// Bit ELCON.
	ELC_ELCR_ELCON = 0x80
	// ELC function is disabled.
	ELC_ELCR_ELCON_0 = 0x0
	// ELC function is enabled.
	ELC_ELCR_ELCON_1 = 0x1

	// ELSEGR0: Event Link Software Event Generation Register %s
	// Position of SEG field.
	ELC_ELSEGR_SEG_Pos = 0x0
	// Bit mask of SEG field.
	ELC_ELSEGR_SEG_Msk = 0x1
	// Bit SEG.
	ELC_ELSEGR_SEG = 0x1
	// Normal operation
	ELC_ELSEGR_SEG_0 = 0x0
	// Software event is generated.
	ELC_ELSEGR_SEG_1 = 0x1
	// Position of WE field.
	ELC_ELSEGR_WE_Pos = 0x6
	// Bit mask of WE field.
	ELC_ELSEGR_WE_Msk = 0x40
	// Bit WE.
	ELC_ELSEGR_WE = 0x40
	// Write to SEG bit disabled.
	ELC_ELSEGR_WE_0 = 0x0
	// Write to SEG bit enabled.
	ELC_ELSEGR_WE_1 = 0x1
	// Position of WI field.
	ELC_ELSEGR_WI_Pos = 0x7
	// Bit mask of WI field.
	ELC_ELSEGR_WI_Msk = 0x80
	// Bit WI.
	ELC_ELSEGR_WI = 0x80
	// Write to ELSEGR register enabled.
	ELC_ELSEGR_WI_0 = 0x0
	// Write to ELSEGR register disabled.
	ELC_ELSEGR_WI_1 = 0x1

	// ELSR0: Event Link Setting Register %s
	// Position of ELS field.
	ELC_ELSR_ELS_Pos = 0x0
	// Bit mask of ELS field.
	ELC_ELSR_ELS_Msk = 0x1ff

	// ELSR12: Event Link Setting Register %s
	// Position of ELS field.
	ELC_ELSR_ELS_Pos = 0x0
	// Bit mask of ELS field.
	ELC_ELSR_ELS_Msk = 0x1ff

	// ELSR23: Event Link Setting Register 23
	// Position of ELS field.
	ELC_ELSR23_ELS_Pos = 0x0
	// Bit mask of ELS field.
	ELC_ELSR23_ELS_Msk = 0x1ff

	// ELCSARA: Event Link Controller Security Attribution Register A
	// Position of ELCR field.
	ELC_ELCSARA_ELCR_Pos = 0x0
	// Bit mask of ELCR field.
	ELC_ELCSARA_ELCR_Msk = 0x1
	// Bit ELCR.
	ELC_ELCSARA_ELCR = 0x1
	// Secure
	ELC_ELCSARA_ELCR_0 = 0x0
	// Non-secure
	ELC_ELCSARA_ELCR_1 = 0x1
	// Position of ELSEGR0 field.
	ELC_ELCSARA_ELSEGR0_Pos = 0x1
	// Bit mask of ELSEGR0 field.
	ELC_ELCSARA_ELSEGR0_Msk = 0x2
	// Bit ELSEGR0.
	ELC_ELCSARA_ELSEGR0 = 0x2
	// Secure
	ELC_ELCSARA_ELSEGR0_0 = 0x0
	// Non-secure
	ELC_ELCSARA_ELSEGR0_1 = 0x1
	// Position of ELSEGR1 field.
	ELC_ELCSARA_ELSEGR1_Pos = 0x2
	// Bit mask of ELSEGR1 field.
	ELC_ELCSARA_ELSEGR1_Msk = 0x4
	// Bit ELSEGR1.
	ELC_ELCSARA_ELSEGR1 = 0x4
	// Secure
	ELC_ELCSARA_ELSEGR1_0 = 0x0
	// Non-secure
	ELC_ELCSARA_ELSEGR1_1 = 0x1

	// ELCSARB: Event Link Controller Security Attribution Register B
	// Position of ELSR field.
	ELC_ELCSARB_ELSR_Pos = 0x0
	// Bit mask of ELSR field.
	ELC_ELCSARB_ELSR_Msk = 0xffff
	// Secure
	ELC_ELCSARB_ELSR_0 = 0x0
	// Non-secure
	ELC_ELCSARB_ELSR_1 = 0x1

	// ELCSARC: Event Link Controller Security Attribution Register C
	// Position of ELSR field.
	ELC_ELCSARC_ELSR_Pos = 0x0
	// Bit mask of ELSR field.
	ELC_ELCSARC_ELSR_Msk = 0xff
	// Secure
	ELC_ELCSARC_ELSR_0 = 0x0
	// Non-secure
	ELC_ELCSARC_ELSR_1 = 0x1
)

// Constants for RTC: Realtime Clock
const (
	// R64CNT: 64-Hz Counter
	// Position of F64HZ field.
	RTC_R64CNT_F64HZ_Pos = 0x0
	// Bit mask of F64HZ field.
	RTC_R64CNT_F64HZ_Msk = 0x1
	// Bit F64HZ.
	RTC_R64CNT_F64HZ = 0x1
	// Position of F32HZ field.
	RTC_R64CNT_F32HZ_Pos = 0x1
	// Bit mask of F32HZ field.
	RTC_R64CNT_F32HZ_Msk = 0x2
	// Bit F32HZ.
	RTC_R64CNT_F32HZ = 0x2
	// Position of F16HZ field.
	RTC_R64CNT_F16HZ_Pos = 0x2
	// Bit mask of F16HZ field.
	RTC_R64CNT_F16HZ_Msk = 0x4
	// Bit F16HZ.
	RTC_R64CNT_F16HZ = 0x4
	// Position of F8HZ field.
	RTC_R64CNT_F8HZ_Pos = 0x3
	// Bit mask of F8HZ field.
	RTC_R64CNT_F8HZ_Msk = 0x8
	// Bit F8HZ.
	RTC_R64CNT_F8HZ = 0x8
	// Position of F4HZ field.
	RTC_R64CNT_F4HZ_Pos = 0x4
	// Bit mask of F4HZ field.
	RTC_R64CNT_F4HZ_Msk = 0x10
	// Bit F4HZ.
	RTC_R64CNT_F4HZ = 0x10
	// Position of F2HZ field.
	RTC_R64CNT_F2HZ_Pos = 0x5
	// Bit mask of F2HZ field.
	RTC_R64CNT_F2HZ_Msk = 0x20
	// Bit F2HZ.
	RTC_R64CNT_F2HZ = 0x20
	// Position of F1HZ field.
	RTC_R64CNT_F1HZ_Pos = 0x6
	// Bit mask of F1HZ field.
	RTC_R64CNT_F1HZ_Msk = 0x40
	// Bit F1HZ.
	RTC_R64CNT_F1HZ = 0x40

	// BCNT0: Binary Counter %s
	// Position of BCNT field.
	RTC_BCNT_BCNT_Pos = 0x0
	// Bit mask of BCNT field.
	RTC_BCNT_BCNT_Msk = 0xff

	// RSECCNT: Second Counter (in Calendar Count Mode)
	// Position of SEC1 field.
	RTC_RSECCNT_SEC1_Pos = 0x0
	// Bit mask of SEC1 field.
	RTC_RSECCNT_SEC1_Msk = 0xf
	// Position of SEC10 field.
	RTC_RSECCNT_SEC10_Pos = 0x4
	// Bit mask of SEC10 field.
	RTC_RSECCNT_SEC10_Msk = 0x70

	// RMINCNT: Minute Counter (in Calendar Count Mode)
	// Position of MIN1 field.
	RTC_RMINCNT_MIN1_Pos = 0x0
	// Bit mask of MIN1 field.
	RTC_RMINCNT_MIN1_Msk = 0xf
	// Position of MIN10 field.
	RTC_RMINCNT_MIN10_Pos = 0x4
	// Bit mask of MIN10 field.
	RTC_RMINCNT_MIN10_Msk = 0x70

	// RHRCNT: Hour Counter (in Calendar Count Mode)
	// Position of HR1 field.
	RTC_RHRCNT_HR1_Pos = 0x0
	// Bit mask of HR1 field.
	RTC_RHRCNT_HR1_Msk = 0xf
	// Position of HR10 field.
	RTC_RHRCNT_HR10_Pos = 0x4
	// Bit mask of HR10 field.
	RTC_RHRCNT_HR10_Msk = 0x30
	// Position of PM field.
	RTC_RHRCNT_PM_Pos = 0x6
	// Bit mask of PM field.
	RTC_RHRCNT_PM_Msk = 0x40
	// Bit PM.
	RTC_RHRCNT_PM = 0x40
	// AM
	RTC_RHRCNT_PM_0 = 0x0
	// PM
	RTC_RHRCNT_PM_1 = 0x1

	// RWKCNT: Day-of-Week Counter (in Calendar Count Mode)
	// Position of DAYW field.
	RTC_RWKCNT_DAYW_Pos = 0x0
	// Bit mask of DAYW field.
	RTC_RWKCNT_DAYW_Msk = 0x7
	// Sunday
	RTC_RWKCNT_DAYW_000 = 0x0
	// Monday
	RTC_RWKCNT_DAYW_001 = 0x1
	// Tuesday
	RTC_RWKCNT_DAYW_010 = 0x2
	// Wednesday
	RTC_RWKCNT_DAYW_011 = 0x3
	// Thursday
	RTC_RWKCNT_DAYW_100 = 0x4
	// Friday
	RTC_RWKCNT_DAYW_101 = 0x5
	// Saturday
	RTC_RWKCNT_DAYW_110 = 0x6
	// Setting prohibited
	RTC_RWKCNT_DAYW_111 = 0x7

	// RDAYCNT: Day Counter
	// Position of DATE1 field.
	RTC_RDAYCNT_DATE1_Pos = 0x0
	// Bit mask of DATE1 field.
	RTC_RDAYCNT_DATE1_Msk = 0xf
	// Position of DATE10 field.
	RTC_RDAYCNT_DATE10_Pos = 0x4
	// Bit mask of DATE10 field.
	RTC_RDAYCNT_DATE10_Msk = 0x30

	// RMONCNT: Month Counter
	// Position of MON1 field.
	RTC_RMONCNT_MON1_Pos = 0x0
	// Bit mask of MON1 field.
	RTC_RMONCNT_MON1_Msk = 0xf
	// Position of MON10 field.
	RTC_RMONCNT_MON10_Pos = 0x4
	// Bit mask of MON10 field.
	RTC_RMONCNT_MON10_Msk = 0x10
	// Bit MON10.
	RTC_RMONCNT_MON10 = 0x10

	// RYRCNT: Year Counter
	// Position of YR1 field.
	RTC_RYRCNT_YR1_Pos = 0x0
	// Bit mask of YR1 field.
	RTC_RYRCNT_YR1_Msk = 0xf
	// Position of YR10 field.
	RTC_RYRCNT_YR10_Pos = 0x4
	// Bit mask of YR10 field.
	RTC_RYRCNT_YR10_Msk = 0xf0

	// BCNT0AR: Binary Counter %s Alarm Register
	// Position of BCNTAR field.
	RTC_BCNTAR_BCNTAR_Pos = 0x0
	// Bit mask of BCNTAR field.
	RTC_BCNTAR_BCNTAR_Msk = 0xff

	// RSECAR: Second Alarm Register (in Calendar Count Mode)
	// Position of SEC1 field.
	RTC_RSECAR_SEC1_Pos = 0x0
	// Bit mask of SEC1 field.
	RTC_RSECAR_SEC1_Msk = 0xf
	// Position of SEC10 field.
	RTC_RSECAR_SEC10_Pos = 0x4
	// Bit mask of SEC10 field.
	RTC_RSECAR_SEC10_Msk = 0x70
	// Position of ENB field.
	RTC_RSECAR_ENB_Pos = 0x7
	// Bit mask of ENB field.
	RTC_RSECAR_ENB_Msk = 0x80
	// Bit ENB.
	RTC_RSECAR_ENB = 0x80
	// Do not compare register value with RSECCNT counter value
	RTC_RSECAR_ENB_0 = 0x0
	// Compare register value with RSECCNT counter value
	RTC_RSECAR_ENB_1 = 0x1

	// RMINAR: Minute Alarm Register (in Calendar Count Mode)
	// Position of MIN1 field.
	RTC_RMINAR_MIN1_Pos = 0x0
	// Bit mask of MIN1 field.
	RTC_RMINAR_MIN1_Msk = 0xf
	// Position of MIN10 field.
	RTC_RMINAR_MIN10_Pos = 0x4
	// Bit mask of MIN10 field.
	RTC_RMINAR_MIN10_Msk = 0x70
	// Position of ENB field.
	RTC_RMINAR_ENB_Pos = 0x7
	// Bit mask of ENB field.
	RTC_RMINAR_ENB_Msk = 0x80
	// Bit ENB.
	RTC_RMINAR_ENB = 0x80
	// Do not compare register value with RMINCNT counter value
	RTC_RMINAR_ENB_0 = 0x0
	// Compare register value with RMINCNT counter value
	RTC_RMINAR_ENB_1 = 0x1

	// RHRAR: Hour Alarm Register (in Calendar Count Mode)
	// Position of HR1 field.
	RTC_RHRAR_HR1_Pos = 0x0
	// Bit mask of HR1 field.
	RTC_RHRAR_HR1_Msk = 0xf
	// Position of HR10 field.
	RTC_RHRAR_HR10_Pos = 0x4
	// Bit mask of HR10 field.
	RTC_RHRAR_HR10_Msk = 0x30
	// Position of PM field.
	RTC_RHRAR_PM_Pos = 0x6
	// Bit mask of PM field.
	RTC_RHRAR_PM_Msk = 0x40
	// Bit PM.
	RTC_RHRAR_PM = 0x40
	// AM
	RTC_RHRAR_PM_0 = 0x0
	// PM
	RTC_RHRAR_PM_1 = 0x1
	// Position of ENB field.
	RTC_RHRAR_ENB_Pos = 0x7
	// Bit mask of ENB field.
	RTC_RHRAR_ENB_Msk = 0x80
	// Bit ENB.
	RTC_RHRAR_ENB = 0x80
	// Do not compare register value with RHRCNT counter value
	RTC_RHRAR_ENB_0 = 0x0
	// Compare register value with RHRCNT counter value
	RTC_RHRAR_ENB_1 = 0x1

	// RWKAR: Day-of-Week Alarm Register (in Calendar Count Mode)
	// Position of DAYW field.
	RTC_RWKAR_DAYW_Pos = 0x0
	// Bit mask of DAYW field.
	RTC_RWKAR_DAYW_Msk = 0x7
	// Sunday
	RTC_RWKAR_DAYW_000 = 0x0
	// Monday
	RTC_RWKAR_DAYW_001 = 0x1
	// Tuesday
	RTC_RWKAR_DAYW_010 = 0x2
	// Wednesday
	RTC_RWKAR_DAYW_011 = 0x3
	// Thursday
	RTC_RWKAR_DAYW_100 = 0x4
	// Friday
	RTC_RWKAR_DAYW_101 = 0x5
	// Saturday
	RTC_RWKAR_DAYW_110 = 0x6
	// Setting prohibited
	RTC_RWKAR_DAYW_111 = 0x7
	// Position of ENB field.
	RTC_RWKAR_ENB_Pos = 0x7
	// Bit mask of ENB field.
	RTC_RWKAR_ENB_Msk = 0x80
	// Bit ENB.
	RTC_RWKAR_ENB = 0x80
	// Do not compare register value with RWKCNT counter value
	RTC_RWKAR_ENB_0 = 0x0
	// Compare register value with RWKCNT counter value
	RTC_RWKAR_ENB_1 = 0x1

	// BCNT0AER: Binary Counter %s Alarm Enable Register
	// Position of ENB field.
	RTC_BCNTAER_ENB_Pos = 0x0
	// Bit mask of ENB field.
	RTC_BCNTAER_ENB_Msk = 0xff

	// RDAYAR: Date Alarm Register (in Calendar Count Mode)
	// Position of DATE1 field.
	RTC_RDAYAR_DATE1_Pos = 0x0
	// Bit mask of DATE1 field.
	RTC_RDAYAR_DATE1_Msk = 0xf
	// Position of DATE10 field.
	RTC_RDAYAR_DATE10_Pos = 0x4
	// Bit mask of DATE10 field.
	RTC_RDAYAR_DATE10_Msk = 0x30
	// Position of ENB field.
	RTC_RDAYAR_ENB_Pos = 0x7
	// Bit mask of ENB field.
	RTC_RDAYAR_ENB_Msk = 0x80
	// Bit ENB.
	RTC_RDAYAR_ENB = 0x80
	// Do not compare register value with RDAYCNT counter value
	RTC_RDAYAR_ENB_0 = 0x0
	// Compare register value with RDAYCNT counter value
	RTC_RDAYAR_ENB_1 = 0x1

	// RMONAR: Month Alarm Register (in Calendar Count Mode)
	// Position of MON1 field.
	RTC_RMONAR_MON1_Pos = 0x0
	// Bit mask of MON1 field.
	RTC_RMONAR_MON1_Msk = 0xf
	// Position of MON10 field.
	RTC_RMONAR_MON10_Pos = 0x4
	// Bit mask of MON10 field.
	RTC_RMONAR_MON10_Msk = 0x10
	// Bit MON10.
	RTC_RMONAR_MON10 = 0x10
	// Position of ENB field.
	RTC_RMONAR_ENB_Pos = 0x7
	// Bit mask of ENB field.
	RTC_RMONAR_ENB_Msk = 0x80
	// Bit ENB.
	RTC_RMONAR_ENB = 0x80
	// Do not compare register value with RMONCNT counter value
	RTC_RMONAR_ENB_0 = 0x0
	// Compare register value with RMONCNT counter value
	RTC_RMONAR_ENB_1 = 0x1

	// BCNT2AER: Binary Counter 2 Alarm Enable Register
	// Position of ENB field.
	RTC_BCNT2AER_ENB_Pos = 0x0
	// Bit mask of ENB field.
	RTC_BCNT2AER_ENB_Msk = 0xff

	// RYRAR: Year Alarm Register (in Calendar Count Mode)
	// Position of YR1 field.
	RTC_RYRAR_YR1_Pos = 0x0
	// Bit mask of YR1 field.
	RTC_RYRAR_YR1_Msk = 0xf
	// Position of YR10 field.
	RTC_RYRAR_YR10_Pos = 0x4
	// Bit mask of YR10 field.
	RTC_RYRAR_YR10_Msk = 0xf0

	// BCNT3AER: Binary Counter 3 Alarm Enable Register
	// Position of ENB field.
	RTC_BCNT3AER_ENB_Pos = 0x0
	// Bit mask of ENB field.
	RTC_BCNT3AER_ENB_Msk = 0xff

	// RYRAREN: Year Alarm Enable Register (in Calendar Count Mode)
	// Position of ENB field.
	RTC_RYRAREN_ENB_Pos = 0x7
	// Bit mask of ENB field.
	RTC_RYRAREN_ENB_Msk = 0x80
	// Bit ENB.
	RTC_RYRAREN_ENB = 0x80
	// Do not compare register value with the RYRCNT counter value
	RTC_RYRAREN_ENB_0 = 0x0
	// Compare register value with the RYRCNT counter value
	RTC_RYRAREN_ENB_1 = 0x1

	// RCR1: RTC Control Register 1
	// Position of AIE field.
	RTC_RCR1_AIE_Pos = 0x0
	// Bit mask of AIE field.
	RTC_RCR1_AIE_Msk = 0x1
	// Bit AIE.
	RTC_RCR1_AIE = 0x1
	// Disable alarm interrupt requests
	RTC_RCR1_AIE_0 = 0x0
	// Enable alarm interrupt requests
	RTC_RCR1_AIE_1 = 0x1
	// Position of CIE field.
	RTC_RCR1_CIE_Pos = 0x1
	// Bit mask of CIE field.
	RTC_RCR1_CIE_Msk = 0x2
	// Bit CIE.
	RTC_RCR1_CIE = 0x2
	// Disable carry interrupt requests
	RTC_RCR1_CIE_0 = 0x0
	// Enable carry interrupt requests
	RTC_RCR1_CIE_1 = 0x1
	// Position of PIE field.
	RTC_RCR1_PIE_Pos = 0x2
	// Bit mask of PIE field.
	RTC_RCR1_PIE_Msk = 0x4
	// Bit PIE.
	RTC_RCR1_PIE = 0x4
	// Disable periodic interrupt requests
	RTC_RCR1_PIE_0 = 0x0
	// Enable periodic interrupt requests
	RTC_RCR1_PIE_1 = 0x1
	// Position of RTCOS field.
	RTC_RCR1_RTCOS_Pos = 0x3
	// Bit mask of RTCOS field.
	RTC_RCR1_RTCOS_Msk = 0x8
	// Bit RTCOS.
	RTC_RCR1_RTCOS = 0x8
	// Outputs 1 Hz on RTCOUT
	RTC_RCR1_RTCOS_0 = 0x0
	// Outputs 64 Hz RTCOUT
	RTC_RCR1_RTCOS_1 = 0x1
	// Position of PES field.
	RTC_RCR1_PES_Pos = 0x4
	// Bit mask of PES field.
	RTC_RCR1_PES_Msk = 0xf0
	// Do not generate periodic interrupts
	RTC_RCR1_PES_Others = 0x0
	// Generate periodic interrupt every 1/256 second
	RTC_RCR1_PES_0x6 = 0x6
	// Generate periodic interrupt every 1/128 second
	RTC_RCR1_PES_0x7 = 0x7
	// Generate periodic interrupt every 1/64 second
	RTC_RCR1_PES_0x8 = 0x8
	// Generate periodic interrupt every 1/32 second
	RTC_RCR1_PES_0x9 = 0x9
	// Generate periodic interrupt every 1/16 second
	RTC_RCR1_PES_0xA = 0xa
	// Generate periodic interrupt every 1/8 second
	RTC_RCR1_PES_0xB = 0xb
	// Generate periodic interrupt every 1/4 second
	RTC_RCR1_PES_0xC = 0xc
	// Generate periodic interrupt every 1/2 second
	RTC_RCR1_PES_0xD = 0xd
	// Generate periodic interrupt every 1 second
	RTC_RCR1_PES_0xE = 0xe
	// Generate periodic interrupt every 2 seconds
	RTC_RCR1_PES_0xF = 0xf

	// RCR2: RTC Control Register 2 (in Calendar Count Mode)
	// Position of START field.
	RTC_RCR2_START_Pos = 0x0
	// Bit mask of START field.
	RTC_RCR2_START_Msk = 0x1
	// Bit START.
	RTC_RCR2_START = 0x1
	// Stop prescaler and time counter
	RTC_RCR2_START_0 = 0x0
	// Operate prescaler and time counter normally
	RTC_RCR2_START_1 = 0x1
	// Position of RESET field.
	RTC_RCR2_RESET_Pos = 0x1
	// Bit mask of RESET field.
	RTC_RCR2_RESET_Msk = 0x2
	// Bit RESET.
	RTC_RCR2_RESET = 0x2
	// In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or an RTC software reset has completed.
	RTC_RCR2_RESET_0 = 0x0
	// In writing: Initialize the prescaler and target registers for RTC software reset. In reading: RTC software reset in progress.
	RTC_RCR2_RESET_1 = 0x1
	// Position of ADJ30 field.
	RTC_RCR2_ADJ30_Pos = 0x2
	// Bit mask of ADJ30 field.
	RTC_RCR2_ADJ30_Msk = 0x4
	// Bit ADJ30.
	RTC_RCR2_ADJ30 = 0x4
	// In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or 30-second adjustment has completed.
	RTC_RCR2_ADJ30_0 = 0x0
	// In writing: Execute 30-second adjustment. In reading: 30-second adjustment in progress.
	RTC_RCR2_ADJ30_1 = 0x1
	// Position of RTCOE field.
	RTC_RCR2_RTCOE_Pos = 0x3
	// Bit mask of RTCOE field.
	RTC_RCR2_RTCOE_Msk = 0x8
	// Bit RTCOE.
	RTC_RCR2_RTCOE = 0x8
	// Disable RTCOUT output
	RTC_RCR2_RTCOE_0 = 0x0
	// Enable RTCOUT output
	RTC_RCR2_RTCOE_1 = 0x1
	// Position of AADJE field.
	RTC_RCR2_AADJE_Pos = 0x4
	// Bit mask of AADJE field.
	RTC_RCR2_AADJE_Msk = 0x10
	// Bit AADJE.
	RTC_RCR2_AADJE = 0x10
	// Disable automatic adjustment
	RTC_RCR2_AADJE_0 = 0x0
	// Enable automatic adjustment
	RTC_RCR2_AADJE_1 = 0x1
	// Position of AADJP field.
	RTC_RCR2_AADJP_Pos = 0x5
	// Bit mask of AADJP field.
	RTC_RCR2_AADJP_Msk = 0x20
	// Bit AADJP.
	RTC_RCR2_AADJP = 0x20
	// The RADJ.ADJ[5:0] setting from the count value of the prescaler every minute.
	RTC_RCR2_AADJP_0 = 0x0
	// The RADJ.ADJ[5:0] setting value is adjusted from the coun tvalue of the prescaler every 10 seconds.
	RTC_RCR2_AADJP_1 = 0x1
	// Position of HR24 field.
	RTC_RCR2_HR24_Pos = 0x6
	// Bit mask of HR24 field.
	RTC_RCR2_HR24_Msk = 0x40
	// Bit HR24.
	RTC_RCR2_HR24 = 0x40
	// Operate RTC in 12-hour mode
	RTC_RCR2_HR24_0 = 0x0
	// Operate RTC in 24-hour mode
	RTC_RCR2_HR24_1 = 0x1
	// Position of CNTMD field.
	RTC_RCR2_CNTMD_Pos = 0x7
	// Bit mask of CNTMD field.
	RTC_RCR2_CNTMD_Msk = 0x80
	// Bit CNTMD.
	RTC_RCR2_CNTMD = 0x80
	// Calendar count mode
	RTC_RCR2_CNTMD_0 = 0x0
	// Binary count mode
	RTC_RCR2_CNTMD_1 = 0x1

	// RCR2_BCNT: RTC Control Register 2 (in Binary Count Mode)
	// Position of START field.
	RTC_RCR2_BCNT_START_Pos = 0x0
	// Bit mask of START field.
	RTC_RCR2_BCNT_START_Msk = 0x1
	// Bit START.
	RTC_RCR2_BCNT_START = 0x1
	// Stop the 32-bit binary counter, 64-Hz counter, and prescaler
	RTC_RCR2_BCNT_START_0 = 0x0
	// Operate the 32-bit binary counter, 64-Hz counter, and prescaler normally
	RTC_RCR2_BCNT_START_1 = 0x1
	// Position of RESET field.
	RTC_RCR2_BCNT_RESET_Pos = 0x1
	// Bit mask of RESET field.
	RTC_RCR2_BCNT_RESET_Msk = 0x2
	// Bit RESET.
	RTC_RCR2_BCNT_RESET = 0x2
	// In writing: Invalid (writing 0 has no effect). In reading: Normal time operation in progress, or an RTC software reset has completed.
	RTC_RCR2_BCNT_RESET_0 = 0x0
	// In writing: Initialize the prescaler and target registers for RTC software reset. In reading: RTC software reset in progress.
	RTC_RCR2_BCNT_RESET_1 = 0x1
	// Position of RTCOE field.
	RTC_RCR2_BCNT_RTCOE_Pos = 0x3
	// Bit mask of RTCOE field.
	RTC_RCR2_BCNT_RTCOE_Msk = 0x8
	// Bit RTCOE.
	RTC_RCR2_BCNT_RTCOE = 0x8
	// Disable RTCOUT output
	RTC_RCR2_BCNT_RTCOE_0 = 0x0
	// Enable RTCOUT output
	RTC_RCR2_BCNT_RTCOE_1 = 0x1
	// Position of AADJE field.
	RTC_RCR2_BCNT_AADJE_Pos = 0x4
	// Bit mask of AADJE field.
	RTC_RCR2_BCNT_AADJE_Msk = 0x10
	// Bit AADJE.
	RTC_RCR2_BCNT_AADJE = 0x10
	// Disable automatic adjustment
	RTC_RCR2_BCNT_AADJE_0 = 0x0
	// Enable automatic adjustment
	RTC_RCR2_BCNT_AADJE_1 = 0x1
	// Position of AADJP field.
	RTC_RCR2_BCNT_AADJP_Pos = 0x5
	// Bit mask of AADJP field.
	RTC_RCR2_BCNT_AADJP_Msk = 0x20
	// Bit AADJP.
	RTC_RCR2_BCNT_AADJP = 0x20
	// Add or subtract RADJ.ADJ [5:0] bits from prescaler count value every 32 seconds
	RTC_RCR2_BCNT_AADJP_0 = 0x0
	// Add or subtract RADJ.ADJ [5:0] bits from prescaler countvalue every 8 seconds.
	RTC_RCR2_BCNT_AADJP_1 = 0x1
	// Position of CNTMD field.
	RTC_RCR2_BCNT_CNTMD_Pos = 0x7
	// Bit mask of CNTMD field.
	RTC_RCR2_BCNT_CNTMD_Msk = 0x80
	// Bit CNTMD.
	RTC_RCR2_BCNT_CNTMD = 0x80
	// Calendar count mode
	RTC_RCR2_BCNT_CNTMD_0 = 0x0
	// Binary count mode
	RTC_RCR2_BCNT_CNTMD_1 = 0x1

	// RCR4: RTC Control Register 4
	// Position of RCKSEL field.
	RTC_RCR4_RCKSEL_Pos = 0x0
	// Bit mask of RCKSEL field.
	RTC_RCR4_RCKSEL_Msk = 0x1
	// Bit RCKSEL.
	RTC_RCR4_RCKSEL = 0x1
	// Sub-clock oscillator is selected
	RTC_RCR4_RCKSEL_0 = 0x0
	// LOCO is selected
	RTC_RCR4_RCKSEL_1 = 0x1

	// RFRH: Frequency Register H
	// Position of RFC16 field.
	RTC_RFRH_RFC16_Pos = 0x0
	// Bit mask of RFC16 field.
	RTC_RFRH_RFC16_Msk = 0x1
	// Bit RFC16.
	RTC_RFRH_RFC16 = 0x1

	// RFRL: Frequency Register L
	// Position of RFC field.
	RTC_RFRL_RFC_Pos = 0x0
	// Bit mask of RFC field.
	RTC_RFRL_RFC_Msk = 0xffff

	// RADJ: Time Error Adjustment Register
	// Position of ADJ field.
	RTC_RADJ_ADJ_Pos = 0x0
	// Bit mask of ADJ field.
	RTC_RADJ_ADJ_Msk = 0x3f
	// Position of PMADJ field.
	RTC_RADJ_PMADJ_Pos = 0x6
	// Bit mask of PMADJ field.
	RTC_RADJ_PMADJ_Msk = 0xc0
	// Do not perform adjustment.
	RTC_RADJ_PMADJ_00 = 0x0
	// Adjustment is performed by the addition to the prescaler
	RTC_RADJ_PMADJ_01 = 0x1
	// Adjustment is performed by the subtraction from the prescaler
	RTC_RADJ_PMADJ_10 = 0x2
	// Setting prohibited.
	RTC_RADJ_PMADJ_11 = 0x3

	// RTCCR0: Time Capture Control Register %s
	// Position of TCCT field.
	RTC_RTCCR_TCCT_Pos = 0x0
	// Bit mask of TCCT field.
	RTC_RTCCR_TCCT_Msk = 0x3
	// Do not detect events
	RTC_RTCCR_TCCT_00 = 0x0
	// Detect rising edge
	RTC_RTCCR_TCCT_01 = 0x1
	// Detect falling edge
	RTC_RTCCR_TCCT_10 = 0x2
	// Detect both edges
	RTC_RTCCR_TCCT_11 = 0x3
	// Position of TCST field.
	RTC_RTCCR_TCST_Pos = 0x2
	// Bit mask of TCST field.
	RTC_RTCCR_TCST_Msk = 0x4
	// Bit TCST.
	RTC_RTCCR_TCST = 0x4
	// No event detected
	RTC_RTCCR_TCST_0 = 0x0
	// Event detected
	RTC_RTCCR_TCST_1 = 0x1
	// Position of TCNF field.
	RTC_RTCCR_TCNF_Pos = 0x4
	// Bit mask of TCNF field.
	RTC_RTCCR_TCNF_Msk = 0x30
	// Turn noise filter off
	RTC_RTCCR_TCNF_00 = 0x0
	// Setting prohibited
	RTC_RTCCR_TCNF_01 = 0x1
	// Turn noise filter on (count source)
	RTC_RTCCR_TCNF_10 = 0x2
	// Turn noise filter on (count source by divided by 32)
	RTC_RTCCR_TCNF_11 = 0x3
	// Position of TCEN field.
	RTC_RTCCR_TCEN_Pos = 0x7
	// Bit mask of TCEN field.
	RTC_RTCCR_TCEN_Msk = 0x80
	// Bit TCEN.
	RTC_RTCCR_TCEN = 0x80
	// Disable the RTCICn pin as the time capture event input pin
	RTC_RTCCR_TCEN_0 = 0x0
	// Enable the RTCICn pin as the time capture event input pin
	RTC_RTCCR_TCEN_1 = 0x1

	// RSECCP0: Second Capture Register %s
	// Position of SEC1 field.
	RTC_RSECCP_SEC1_Pos = 0x0
	// Bit mask of SEC1 field.
	RTC_RSECCP_SEC1_Msk = 0xf
	// Position of SEC10 field.
	RTC_RSECCP_SEC10_Pos = 0x4
	// Bit mask of SEC10 field.
	RTC_RSECCP_SEC10_Msk = 0x70

	// RMINCP0: Minute Capture Register %s
	// Position of MIN1 field.
	RTC_RMINCP_MIN1_Pos = 0x0
	// Bit mask of MIN1 field.
	RTC_RMINCP_MIN1_Msk = 0xf
	// Position of MIN10 field.
	RTC_RMINCP_MIN10_Pos = 0x4
	// Bit mask of MIN10 field.
	RTC_RMINCP_MIN10_Msk = 0x70

	// RHRCP0: Hour Capture Register %s
	// Position of HR1 field.
	RTC_RHRCP_HR1_Pos = 0x0
	// Bit mask of HR1 field.
	RTC_RHRCP_HR1_Msk = 0xf
	// Position of HR10 field.
	RTC_RHRCP_HR10_Pos = 0x4
	// Bit mask of HR10 field.
	RTC_RHRCP_HR10_Msk = 0x30
	// Position of PM field.
	RTC_RHRCP_PM_Pos = 0x6
	// Bit mask of PM field.
	RTC_RHRCP_PM_Msk = 0x40
	// Bit PM.
	RTC_RHRCP_PM = 0x40
	// AM
	RTC_RHRCP_PM_0 = 0x0
	// PM
	RTC_RHRCP_PM_1 = 0x1

	// RDAYCP0: Date Capture Register %s
	// Position of DATE1 field.
	RTC_RDAYCP_DATE1_Pos = 0x0
	// Bit mask of DATE1 field.
	RTC_RDAYCP_DATE1_Msk = 0xf
	// Position of DATE10 field.
	RTC_RDAYCP_DATE10_Pos = 0x4
	// Bit mask of DATE10 field.
	RTC_RDAYCP_DATE10_Msk = 0x30

	// RMONCP0: Month Capture Register %s
	// Position of MON1 field.
	RTC_RMONCP_MON1_Pos = 0x0
	// Bit mask of MON1 field.
	RTC_RMONCP_MON1_Msk = 0xf
	// Position of MON10 field.
	RTC_RMONCP_MON10_Pos = 0x4
	// Bit mask of MON10 field.
	RTC_RMONCP_MON10_Msk = 0x10
	// Bit MON10.
	RTC_RMONCP_MON10 = 0x10
)

// Constants for IWDT: Independent Watchdog Timer
const (
	// IWDTSR: IWDT Status Register
	// Position of CNTVAL field.
	IWDT_IWDTSR_CNTVAL_Pos = 0x0
	// Bit mask of CNTVAL field.
	IWDT_IWDTSR_CNTVAL_Msk = 0x3fff
	// Position of UNDFF field.
	IWDT_IWDTSR_UNDFF_Pos = 0xe
	// Bit mask of UNDFF field.
	IWDT_IWDTSR_UNDFF_Msk = 0x4000
	// Bit UNDFF.
	IWDT_IWDTSR_UNDFF = 0x4000
	// No underflow occurred
	IWDT_IWDTSR_UNDFF_0 = 0x0
	// Underflow occurred
	IWDT_IWDTSR_UNDFF_1 = 0x1
	// Position of REFEF field.
	IWDT_IWDTSR_REFEF_Pos = 0xf
	// Bit mask of REFEF field.
	IWDT_IWDTSR_REFEF_Msk = 0x8000
	// Bit REFEF.
	IWDT_IWDTSR_REFEF = 0x8000
	// No refresh error occurred
	IWDT_IWDTSR_REFEF_0 = 0x0
	// Refresh error occurred
	IWDT_IWDTSR_REFEF_1 = 0x1
)

// Constants for WDT: Watchdog Timer
const (
	// WDTCR: WDT Control Register
	// Position of TOPS field.
	WDT_WDTCR_TOPS_Pos = 0x0
	// Bit mask of TOPS field.
	WDT_WDTCR_TOPS_Msk = 0x3
	// 1024 cycles (0x03FF)
	WDT_WDTCR_TOPS_00 = 0x0
	// 4096 cycles (0x0FFF)
	WDT_WDTCR_TOPS_01 = 0x1
	// 8192 cycles (0x1FFF)
	WDT_WDTCR_TOPS_10 = 0x2
	// 16384 cycles (0x3FFF)
	WDT_WDTCR_TOPS_11 = 0x3
	// Position of CKS field.
	WDT_WDTCR_CKS_Pos = 0x4
	// Bit mask of CKS field.
	WDT_WDTCR_CKS_Msk = 0xf0
	// Setting prohibited
	WDT_WDTCR_CKS_Others = 0x0
	// PCLKB/4
	WDT_WDTCR_CKS_0x1 = 0x1
	// PCLKB/64
	WDT_WDTCR_CKS_0x4 = 0x4
	// PCLKB/128
	WDT_WDTCR_CKS_0xF = 0xf
	// PCLKB/512
	WDT_WDTCR_CKS_0x6 = 0x6
	// PCLKB/2048
	WDT_WDTCR_CKS_0x7 = 0x7
	// PCLKB/8192
	WDT_WDTCR_CKS_0x8 = 0x8
	// Position of RPES field.
	WDT_WDTCR_RPES_Pos = 0x8
	// Bit mask of RPES field.
	WDT_WDTCR_RPES_Msk = 0x300
	// 75%
	WDT_WDTCR_RPES_00 = 0x0
	// 50%
	WDT_WDTCR_RPES_01 = 0x1
	// 25%
	WDT_WDTCR_RPES_10 = 0x2
	// 0% (do not specify window end position).
	WDT_WDTCR_RPES_11 = 0x3
	// Position of RPSS field.
	WDT_WDTCR_RPSS_Pos = 0xc
	// Bit mask of RPSS field.
	WDT_WDTCR_RPSS_Msk = 0x3000
	// 25%
	WDT_WDTCR_RPSS_00 = 0x0
	// 50%
	WDT_WDTCR_RPSS_01 = 0x1
	// 75%
	WDT_WDTCR_RPSS_10 = 0x2
	// 100% (do not specify window start position).
	WDT_WDTCR_RPSS_11 = 0x3

	// WDTSR: WDT Status Register
	// Position of CNTVAL field.
	WDT_WDTSR_CNTVAL_Pos = 0x0
	// Bit mask of CNTVAL field.
	WDT_WDTSR_CNTVAL_Msk = 0x3fff
	// Position of UNDFF field.
	WDT_WDTSR_UNDFF_Pos = 0xe
	// Bit mask of UNDFF field.
	WDT_WDTSR_UNDFF_Msk = 0x4000
	// Bit UNDFF.
	WDT_WDTSR_UNDFF = 0x4000
	// No underflow occurred
	WDT_WDTSR_UNDFF_0 = 0x0
	// Underflow occurred
	WDT_WDTSR_UNDFF_1 = 0x1
	// Position of REFEF field.
	WDT_WDTSR_REFEF_Pos = 0xf
	// Bit mask of REFEF field.
	WDT_WDTSR_REFEF_Msk = 0x8000
	// Bit REFEF.
	WDT_WDTSR_REFEF = 0x8000
	// No refresh error occurred
	WDT_WDTSR_REFEF_0 = 0x0
	// Refresh error occurred
	WDT_WDTSR_REFEF_1 = 0x1

	// WDTRCR: WDT Reset Control Register
	// Position of RSTIRQS field.
	WDT_WDTRCR_RSTIRQS_Pos = 0x7
	// Bit mask of RSTIRQS field.
	WDT_WDTRCR_RSTIRQS_Msk = 0x80
	// Bit RSTIRQS.
	WDT_WDTRCR_RSTIRQS = 0x80
	// Interrupt
	WDT_WDTRCR_RSTIRQS_0 = 0x0
	// Reset
	WDT_WDTRCR_RSTIRQS_1 = 0x1

	// WDTCSTPR: WDT Count Stop Control Register
	// Position of SLCSTP field.
	WDT_WDTCSTPR_SLCSTP_Pos = 0x7
	// Bit mask of SLCSTP field.
	WDT_WDTCSTPR_SLCSTP_Msk = 0x80
	// Bit SLCSTP.
	WDT_WDTCSTPR_SLCSTP = 0x80
	// Disable count stop
	WDT_WDTCSTPR_SLCSTP_0 = 0x0
	// Stop count on transition to Sleep mode
	WDT_WDTCSTPR_SLCSTP_1 = 0x1
)

// Constants for CAC: Clock Frequency Accuracy Measurement Circuit
const (
	// CACR0: CAC Control Register 0
	// Position of CFME field.
	CAC_CACR0_CFME_Pos = 0x0
	// Bit mask of CFME field.
	CAC_CACR0_CFME_Msk = 0x1
	// Bit CFME.
	CAC_CACR0_CFME = 0x1
	// Disable
	CAC_CACR0_CFME_0 = 0x0
	// Enable
	CAC_CACR0_CFME_1 = 0x1

	// CACR1: CAC Control Register 1
	// Position of CACREFE field.
	CAC_CACR1_CACREFE_Pos = 0x0
	// Bit mask of CACREFE field.
	CAC_CACR1_CACREFE_Msk = 0x1
	// Bit CACREFE.
	CAC_CACR1_CACREFE = 0x1
	// Disable
	CAC_CACR1_CACREFE_0 = 0x0
	// Enable
	CAC_CACR1_CACREFE_1 = 0x1
	// Position of FMCS field.
	CAC_CACR1_FMCS_Pos = 0x1
	// Bit mask of FMCS field.
	CAC_CACR1_FMCS_Msk = 0xe
	// Main clock oscillator
	CAC_CACR1_FMCS_000 = 0x0
	// Sub-clock oscillator
	CAC_CACR1_FMCS_001 = 0x1
	// HOCO clock
	CAC_CACR1_FMCS_010 = 0x2
	// MOCO clock
	CAC_CACR1_FMCS_011 = 0x3
	// LOCO clock
	CAC_CACR1_FMCS_100 = 0x4
	// Peripheral module clock B (PCLKB)
	CAC_CACR1_FMCS_101 = 0x5
	// IWDT-dedicated clock
	CAC_CACR1_FMCS_110 = 0x6
	// Setting prohibited
	CAC_CACR1_FMCS_111 = 0x7
	// Position of TCSS field.
	CAC_CACR1_TCSS_Pos = 0x4
	// Bit mask of TCSS field.
	CAC_CACR1_TCSS_Msk = 0x30
	// No division
	CAC_CACR1_TCSS_00 = 0x0
	// x 1/4 clock
	CAC_CACR1_TCSS_01 = 0x1
	// x 1/8 clock
	CAC_CACR1_TCSS_10 = 0x2
	// x 1/32 clock
	CAC_CACR1_TCSS_11 = 0x3
	// Position of EDGES field.
	CAC_CACR1_EDGES_Pos = 0x6
	// Bit mask of EDGES field.
	CAC_CACR1_EDGES_Msk = 0xc0
	// Rising edge
	CAC_CACR1_EDGES_00 = 0x0
	// Falling edge
	CAC_CACR1_EDGES_01 = 0x1
	// Both rising and falling edges
	CAC_CACR1_EDGES_10 = 0x2
	// Setting prohibited
	CAC_CACR1_EDGES_11 = 0x3

	// CACR2: CAC Control Register 2
	// Position of RPS field.
	CAC_CACR2_RPS_Pos = 0x0
	// Bit mask of RPS field.
	CAC_CACR2_RPS_Msk = 0x1
	// Bit RPS.
	CAC_CACR2_RPS = 0x1
	// CACREF pin input
	CAC_CACR2_RPS_0 = 0x0
	// Internal clock (internally generated signal)
	CAC_CACR2_RPS_1 = 0x1
	// Position of RSCS field.
	CAC_CACR2_RSCS_Pos = 0x1
	// Bit mask of RSCS field.
	CAC_CACR2_RSCS_Msk = 0xe
	// Main clock oscillator
	CAC_CACR2_RSCS_000 = 0x0
	// Sub-clock oscillator
	CAC_CACR2_RSCS_001 = 0x1
	// HOCO clock
	CAC_CACR2_RSCS_010 = 0x2
	// MOCO clock
	CAC_CACR2_RSCS_011 = 0x3
	// LOCO clock
	CAC_CACR2_RSCS_100 = 0x4
	// Peripheral module clock B (PCLKB)
	CAC_CACR2_RSCS_101 = 0x5
	// IWDT-dedicated clock
	CAC_CACR2_RSCS_110 = 0x6
	// Setting prohibited
	CAC_CACR2_RSCS_111 = 0x7
	// Position of RCDS field.
	CAC_CACR2_RCDS_Pos = 0x4
	// Bit mask of RCDS field.
	CAC_CACR2_RCDS_Msk = 0x30
	// x 1/32 clock
	CAC_CACR2_RCDS_00 = 0x0
	// x 1/128 clock
	CAC_CACR2_RCDS_01 = 0x1
	// x 1/1024 clock
	CAC_CACR2_RCDS_10 = 0x2
	// x 1/8192 clock
	CAC_CACR2_RCDS_11 = 0x3
	// Position of DFS field.
	CAC_CACR2_DFS_Pos = 0x6
	// Bit mask of DFS field.
	CAC_CACR2_DFS_Msk = 0xc0
	// Disable digital filtering
	CAC_CACR2_DFS_00 = 0x0
	// Use sampling clock for the digital filter as the frequency measuring clock
	CAC_CACR2_DFS_01 = 0x1
	// Use sampling clock for the digital filter as the frequency measuring clock divided by 4
	CAC_CACR2_DFS_10 = 0x2
	// Use sampling clock for the digital filter as the frequency measuring clock divided by 16.
	CAC_CACR2_DFS_11 = 0x3

	// CAICR: CAC Interrupt Control Register
	// Position of FERRIE field.
	CAC_CAICR_FERRIE_Pos = 0x0
	// Bit mask of FERRIE field.
	CAC_CAICR_FERRIE_Msk = 0x1
	// Bit FERRIE.
	CAC_CAICR_FERRIE = 0x1
	// Disable
	CAC_CAICR_FERRIE_0 = 0x0
	// Enable
	CAC_CAICR_FERRIE_1 = 0x1
	// Position of MENDIE field.
	CAC_CAICR_MENDIE_Pos = 0x1
	// Bit mask of MENDIE field.
	CAC_CAICR_MENDIE_Msk = 0x2
	// Bit MENDIE.
	CAC_CAICR_MENDIE = 0x2
	// Disable
	CAC_CAICR_MENDIE_0 = 0x0
	// Enable
	CAC_CAICR_MENDIE_1 = 0x1
	// Position of OVFIE field.
	CAC_CAICR_OVFIE_Pos = 0x2
	// Bit mask of OVFIE field.
	CAC_CAICR_OVFIE_Msk = 0x4
	// Bit OVFIE.
	CAC_CAICR_OVFIE = 0x4
	// Disable
	CAC_CAICR_OVFIE_0 = 0x0
	// Enable
	CAC_CAICR_OVFIE_1 = 0x1
	// Position of FERRFCL field.
	CAC_CAICR_FERRFCL_Pos = 0x4
	// Bit mask of FERRFCL field.
	CAC_CAICR_FERRFCL_Msk = 0x10
	// Bit FERRFCL.
	CAC_CAICR_FERRFCL = 0x10
	// No effect
	CAC_CAICR_FERRFCL_0 = 0x0
	// The CASTR.FERRF flag is cleared
	CAC_CAICR_FERRFCL_1 = 0x1
	// Position of MENDFCL field.
	CAC_CAICR_MENDFCL_Pos = 0x5
	// Bit mask of MENDFCL field.
	CAC_CAICR_MENDFCL_Msk = 0x20
	// Bit MENDFCL.
	CAC_CAICR_MENDFCL = 0x20
	// No effect
	CAC_CAICR_MENDFCL_0 = 0x0
	// The CASTR.MENDF flag is cleared
	CAC_CAICR_MENDFCL_1 = 0x1
	// Position of OVFFCL field.
	CAC_CAICR_OVFFCL_Pos = 0x6
	// Bit mask of OVFFCL field.
	CAC_CAICR_OVFFCL_Msk = 0x40
	// Bit OVFFCL.
	CAC_CAICR_OVFFCL = 0x40
	// No effect
	CAC_CAICR_OVFFCL_0 = 0x0
	// The CASTR.OVFF flag is cleared.
	CAC_CAICR_OVFFCL_1 = 0x1

	// CASTR: CAC Status Register
	// Position of FERRF field.
	CAC_CASTR_FERRF_Pos = 0x0
	// Bit mask of FERRF field.
	CAC_CASTR_FERRF_Msk = 0x1
	// Bit FERRF.
	CAC_CASTR_FERRF = 0x1
	// Clock frequency is within the allowable range
	CAC_CASTR_FERRF_0 = 0x0
	// Clock frequency has deviated beyond the allowable range (frequency error).
	CAC_CASTR_FERRF_1 = 0x1
	// Position of MENDF field.
	CAC_CASTR_MENDF_Pos = 0x1
	// Bit mask of MENDF field.
	CAC_CASTR_MENDF_Msk = 0x2
	// Bit MENDF.
	CAC_CASTR_MENDF = 0x2
	// Measurement is in progress
	CAC_CASTR_MENDF_0 = 0x0
	// Measurement ended
	CAC_CASTR_MENDF_1 = 0x1
	// Position of OVFF field.
	CAC_CASTR_OVFF_Pos = 0x2
	// Bit mask of OVFF field.
	CAC_CASTR_OVFF_Msk = 0x4
	// Bit OVFF.
	CAC_CASTR_OVFF = 0x4
	// Counter has not overflowed
	CAC_CASTR_OVFF_0 = 0x0
	// Counter overflowed
	CAC_CASTR_OVFF_1 = 0x1
)

// Constants for MSTP: Module Stop Control
const (
	// MSTPCRA: Module Stop Control Register A
	// Position of MSTPA0 field.
	MSTP_MSTPCRA_MSTPA0_Pos = 0x0
	// Bit mask of MSTPA0 field.
	MSTP_MSTPCRA_MSTPA0_Msk = 0x1
	// Bit MSTPA0.
	MSTP_MSTPCRA_MSTPA0 = 0x1
	// Cancel the module-stop state
	MSTP_MSTPCRA_MSTPA0_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRA_MSTPA0_1 = 0x1
	// Position of MSTPA7 field.
	MSTP_MSTPCRA_MSTPA7_Pos = 0x7
	// Bit mask of MSTPA7 field.
	MSTP_MSTPCRA_MSTPA7_Msk = 0x80
	// Bit MSTPA7.
	MSTP_MSTPCRA_MSTPA7 = 0x80
	// Cancel the module-stop state
	MSTP_MSTPCRA_MSTPA7_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRA_MSTPA7_1 = 0x1
	// Position of MSTPA22 field.
	MSTP_MSTPCRA_MSTPA22_Pos = 0x16
	// Bit mask of MSTPA22 field.
	MSTP_MSTPCRA_MSTPA22_Msk = 0x400000
	// Bit MSTPA22.
	MSTP_MSTPCRA_MSTPA22 = 0x400000
	// Cancel the module-stop state
	MSTP_MSTPCRA_MSTPA22_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRA_MSTPA22_1 = 0x1

	// MSTPCRB: Module Stop Control Register B
	// Position of MSTPB3 field.
	MSTP_MSTPCRB_MSTPB3_Pos = 0x3
	// Bit mask of MSTPB3 field.
	MSTP_MSTPCRB_MSTPB3_Msk = 0x8
	// Bit MSTPB3.
	MSTP_MSTPCRB_MSTPB3 = 0x8
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB3_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB3_1 = 0x1
	// Position of MSTPB4 field.
	MSTP_MSTPCRB_MSTPB4_Pos = 0x4
	// Bit mask of MSTPB4 field.
	MSTP_MSTPCRB_MSTPB4_Msk = 0x10
	// Bit MSTPB4.
	MSTP_MSTPCRB_MSTPB4 = 0x10
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB4_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB4_1 = 0x1
	// Position of MSTPB6 field.
	MSTP_MSTPCRB_MSTPB6_Pos = 0x6
	// Bit mask of MSTPB6 field.
	MSTP_MSTPCRB_MSTPB6_Msk = 0x40
	// Bit MSTPB6.
	MSTP_MSTPCRB_MSTPB6 = 0x40
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB6_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB6_1 = 0x1
	// Position of MSTPB11 field.
	MSTP_MSTPCRB_MSTPB11_Pos = 0xb
	// Bit mask of MSTPB11 field.
	MSTP_MSTPCRB_MSTPB11_Msk = 0x800
	// Bit MSTPB11.
	MSTP_MSTPCRB_MSTPB11 = 0x800
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB11_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB11_1 = 0x1
	// Position of MSTPB18 field.
	MSTP_MSTPCRB_MSTPB18_Pos = 0x12
	// Bit mask of MSTPB18 field.
	MSTP_MSTPCRB_MSTPB18_Msk = 0x40000
	// Bit MSTPB18.
	MSTP_MSTPCRB_MSTPB18 = 0x40000
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB18_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB18_1 = 0x1
	// Position of MSTPB19 field.
	MSTP_MSTPCRB_MSTPB19_Pos = 0x13
	// Bit mask of MSTPB19 field.
	MSTP_MSTPCRB_MSTPB19_Msk = 0x80000
	// Bit MSTPB19.
	MSTP_MSTPCRB_MSTPB19 = 0x80000
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB19_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB19_1 = 0x1
	// Position of MSTPB22 field.
	MSTP_MSTPCRB_MSTPB22_Pos = 0x16
	// Bit mask of MSTPB22 field.
	MSTP_MSTPCRB_MSTPB22_Msk = 0x400000
	// Bit MSTPB22.
	MSTP_MSTPCRB_MSTPB22 = 0x400000
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB22_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB22_1 = 0x1
	// Position of MSTPB31 field.
	MSTP_MSTPCRB_MSTPB31_Pos = 0x1f
	// Bit mask of MSTPB31 field.
	MSTP_MSTPCRB_MSTPB31_Msk = 0x80000000
	// Bit MSTPB31.
	MSTP_MSTPCRB_MSTPB31 = 0x80000000
	// Cancel the module-stop state
	MSTP_MSTPCRB_MSTPB31_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRB_MSTPB31_1 = 0x1

	// MSTPCRC: Module Stop Control Register C
	// Position of MSTPC0 field.
	MSTP_MSTPCRC_MSTPC0_Pos = 0x0
	// Bit mask of MSTPC0 field.
	MSTP_MSTPCRC_MSTPC0_Msk = 0x1
	// Bit MSTPC0.
	MSTP_MSTPCRC_MSTPC0 = 0x1
	// Cancel the module-stop state
	MSTP_MSTPCRC_MSTPC0_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRC_MSTPC0_1 = 0x1
	// Position of MSTPC1 field.
	MSTP_MSTPCRC_MSTPC1_Pos = 0x1
	// Bit mask of MSTPC1 field.
	MSTP_MSTPCRC_MSTPC1_Msk = 0x2
	// Bit MSTPC1.
	MSTP_MSTPCRC_MSTPC1 = 0x2
	// Cancel the module-stop state
	MSTP_MSTPCRC_MSTPC1_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRC_MSTPC1_1 = 0x1
	// Position of MSTPC8 field.
	MSTP_MSTPCRC_MSTPC8_Pos = 0x8
	// Bit mask of MSTPC8 field.
	MSTP_MSTPCRC_MSTPC8_Msk = 0x100
	// Bit MSTPC8.
	MSTP_MSTPCRC_MSTPC8 = 0x100
	// Cancel the module-stop state
	MSTP_MSTPCRC_MSTPC8_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRC_MSTPC8_1 = 0x1
	// Position of MSTPC13 field.
	MSTP_MSTPCRC_MSTPC13_Pos = 0xd
	// Bit mask of MSTPC13 field.
	MSTP_MSTPCRC_MSTPC13_Msk = 0x2000
	// Bit MSTPC13.
	MSTP_MSTPCRC_MSTPC13 = 0x2000
	// Cancel the module-stop state
	MSTP_MSTPCRC_MSTPC13_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRC_MSTPC13_1 = 0x1
	// Position of MSTPC14 field.
	MSTP_MSTPCRC_MSTPC14_Pos = 0xe
	// Bit mask of MSTPC14 field.
	MSTP_MSTPCRC_MSTPC14_Msk = 0x4000
	// Bit MSTPC14.
	MSTP_MSTPCRC_MSTPC14 = 0x4000
	// Cancel the module-stop state
	MSTP_MSTPCRC_MSTPC14_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRC_MSTPC14_1 = 0x1
	// Position of MSTPC27 field.
	MSTP_MSTPCRC_MSTPC27_Pos = 0x1b
	// Bit mask of MSTPC27 field.
	MSTP_MSTPCRC_MSTPC27_Msk = 0x8000000
	// Bit MSTPC27.
	MSTP_MSTPCRC_MSTPC27 = 0x8000000
	// Cancel the module-stop state
	MSTP_MSTPCRC_MSTPC27_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRC_MSTPC27_1 = 0x1
	// Position of MSTPC28 field.
	MSTP_MSTPCRC_MSTPC28_Pos = 0x1c
	// Bit mask of MSTPC28 field.
	MSTP_MSTPCRC_MSTPC28_Msk = 0x10000000
	// Bit MSTPC28.
	MSTP_MSTPCRC_MSTPC28 = 0x10000000
	// Cancel the module-stop state
	MSTP_MSTPCRC_MSTPC28_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRC_MSTPC28_1 = 0x1

	// MSTPCRD: Module Stop Control Register D
	// Position of MSTPD2 field.
	MSTP_MSTPCRD_MSTPD2_Pos = 0x2
	// Bit mask of MSTPD2 field.
	MSTP_MSTPCRD_MSTPD2_Msk = 0x4
	// Bit MSTPD2.
	MSTP_MSTPCRD_MSTPD2 = 0x4
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD2_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD2_1 = 0x1
	// Position of MSTPD3 field.
	MSTP_MSTPCRD_MSTPD3_Pos = 0x3
	// Bit mask of MSTPD3 field.
	MSTP_MSTPCRD_MSTPD3_Msk = 0x8
	// Bit MSTPD3.
	MSTP_MSTPCRD_MSTPD3 = 0x8
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD3_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD3_1 = 0x1
	// Position of MSTPD11 field.
	MSTP_MSTPCRD_MSTPD11_Pos = 0xb
	// Bit mask of MSTPD11 field.
	MSTP_MSTPCRD_MSTPD11_Msk = 0x800
	// Bit MSTPD11.
	MSTP_MSTPCRD_MSTPD11 = 0x800
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD11_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD11_1 = 0x1
	// Position of MSTPD12 field.
	MSTP_MSTPCRD_MSTPD12_Pos = 0xc
	// Bit mask of MSTPD12 field.
	MSTP_MSTPCRD_MSTPD12_Msk = 0x1000
	// Bit MSTPD12.
	MSTP_MSTPCRD_MSTPD12 = 0x1000
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD12_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD12_1 = 0x1
	// Position of MSTPD13 field.
	MSTP_MSTPCRD_MSTPD13_Pos = 0xd
	// Bit mask of MSTPD13 field.
	MSTP_MSTPCRD_MSTPD13_Msk = 0x2000
	// Bit MSTPD13.
	MSTP_MSTPCRD_MSTPD13 = 0x2000
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD13_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD13_1 = 0x1
	// Position of MSTPD14 field.
	MSTP_MSTPCRD_MSTPD14_Pos = 0xe
	// Bit mask of MSTPD14 field.
	MSTP_MSTPCRD_MSTPD14_Msk = 0x4000
	// Bit MSTPD14.
	MSTP_MSTPCRD_MSTPD14 = 0x4000
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD14_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD14_1 = 0x1
	// Position of MSTPD16 field.
	MSTP_MSTPCRD_MSTPD16_Pos = 0x10
	// Bit mask of MSTPD16 field.
	MSTP_MSTPCRD_MSTPD16_Msk = 0x10000
	// Bit MSTPD16.
	MSTP_MSTPCRD_MSTPD16 = 0x10000
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD16_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD16_1 = 0x1
	// Position of MSTPD20 field.
	MSTP_MSTPCRD_MSTPD20_Pos = 0x14
	// Bit mask of MSTPD20 field.
	MSTP_MSTPCRD_MSTPD20_Msk = 0x100000
	// Bit MSTPD20.
	MSTP_MSTPCRD_MSTPD20 = 0x100000
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD20_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD20_1 = 0x1
	// Position of MSTPD22 field.
	MSTP_MSTPCRD_MSTPD22_Pos = 0x16
	// Bit mask of MSTPD22 field.
	MSTP_MSTPCRD_MSTPD22_Msk = 0x400000
	// Bit MSTPD22.
	MSTP_MSTPCRD_MSTPD22 = 0x400000
	// Cancel the module-stop state
	MSTP_MSTPCRD_MSTPD22_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRD_MSTPD22_1 = 0x1

	// MSTPCRE: Module Stop Control Register E
	// Position of MSTPE26 field.
	MSTP_MSTPCRE_MSTPE26_Pos = 0x1a
	// Bit mask of MSTPE26 field.
	MSTP_MSTPCRE_MSTPE26_Msk = 0x4000000
	// Bit MSTPE26.
	MSTP_MSTPCRE_MSTPE26 = 0x4000000
	// Cancel the module-stop state
	MSTP_MSTPCRE_MSTPE26_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRE_MSTPE26_1 = 0x1
	// Position of MSTPE27 field.
	MSTP_MSTPCRE_MSTPE27_Pos = 0x1b
	// Bit mask of MSTPE27 field.
	MSTP_MSTPCRE_MSTPE27_Msk = 0x8000000
	// Bit MSTPE27.
	MSTP_MSTPCRE_MSTPE27 = 0x8000000
	// Cancel the module-stop state
	MSTP_MSTPCRE_MSTPE27_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRE_MSTPE27_1 = 0x1
	// Position of MSTPE28 field.
	MSTP_MSTPCRE_MSTPE28_Pos = 0x1c
	// Bit mask of MSTPE28 field.
	MSTP_MSTPCRE_MSTPE28_Msk = 0x10000000
	// Bit MSTPE28.
	MSTP_MSTPCRE_MSTPE28 = 0x10000000
	// Cancel the module-stop state
	MSTP_MSTPCRE_MSTPE28_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRE_MSTPE28_1 = 0x1
	// Position of MSTPE29 field.
	MSTP_MSTPCRE_MSTPE29_Pos = 0x1d
	// Bit mask of MSTPE29 field.
	MSTP_MSTPCRE_MSTPE29_Msk = 0x20000000
	// Bit MSTPE29.
	MSTP_MSTPCRE_MSTPE29 = 0x20000000
	// Cancel the module-stop state
	MSTP_MSTPCRE_MSTPE29_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRE_MSTPE29_1 = 0x1
	// Position of MSTPE30 field.
	MSTP_MSTPCRE_MSTPE30_Pos = 0x1e
	// Bit mask of MSTPE30 field.
	MSTP_MSTPCRE_MSTPE30_Msk = 0x40000000
	// Bit MSTPE30.
	MSTP_MSTPCRE_MSTPE30 = 0x40000000
	// Cancel the module-stop state
	MSTP_MSTPCRE_MSTPE30_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRE_MSTPE30_1 = 0x1
	// Position of MSTPE31 field.
	MSTP_MSTPCRE_MSTPE31_Pos = 0x1f
	// Bit mask of MSTPE31 field.
	MSTP_MSTPCRE_MSTPE31_Msk = 0x80000000
	// Bit MSTPE31.
	MSTP_MSTPCRE_MSTPE31 = 0x80000000
	// Cancel the module-stop state
	MSTP_MSTPCRE_MSTPE31_0 = 0x0
	// Enter the module-stop state
	MSTP_MSTPCRE_MSTPE31_1 = 0x1
)

// Constants for POEG: Port Output Enable Module for GPT
const (
	// POEGGA: POEG Group A Setting Register
	// Position of PIDF field.
	POEG_POEGGA_PIDF_Pos = 0x0
	// Bit mask of PIDF field.
	POEG_POEGGA_PIDF_Msk = 0x1
	// Bit PIDF.
	POEG_POEGGA_PIDF = 0x1
	// No output-disable request from the GTETRGn pin occurred
	POEG_POEGGA_PIDF_0 = 0x0
	// Output-disable request from the GTETRGn pin occurred.
	POEG_POEGGA_PIDF_1 = 0x1
	// Position of IOCF field.
	POEG_POEGGA_IOCF_Pos = 0x1
	// Bit mask of IOCF field.
	POEG_POEGGA_IOCF_Msk = 0x2
	// Bit IOCF.
	POEG_POEGGA_IOCF = 0x2
	// No output-disable request from GPT occurred.
	POEG_POEGGA_IOCF_0 = 0x0
	// Output-disable request from GPT occurred.
	POEG_POEGGA_IOCF_1 = 0x1
	// Position of OSTPF field.
	POEG_POEGGA_OSTPF_Pos = 0x2
	// Bit mask of OSTPF field.
	POEG_POEGGA_OSTPF_Msk = 0x4
	// Bit OSTPF.
	POEG_POEGGA_OSTPF = 0x4
	// No output-disable request from oscillation stop detection occurred
	POEG_POEGGA_OSTPF_0 = 0x0
	// Output-disable request from oscillation stop detection occurred
	POEG_POEGGA_OSTPF_1 = 0x1
	// Position of SSF field.
	POEG_POEGGA_SSF_Pos = 0x3
	// Bit mask of SSF field.
	POEG_POEGGA_SSF_Msk = 0x8
	// Bit SSF.
	POEG_POEGGA_SSF = 0x8
	// No output-disable request from software occurred
	POEG_POEGGA_SSF_0 = 0x0
	// Output-disable request from software occurred
	POEG_POEGGA_SSF_1 = 0x1
	// Position of PIDE field.
	POEG_POEGGA_PIDE_Pos = 0x4
	// Bit mask of PIDE field.
	POEG_POEGGA_PIDE_Msk = 0x10
	// Bit PIDE.
	POEG_POEGGA_PIDE = 0x10
	// Disable output-disable requests from the GTETRGn pins
	POEG_POEGGA_PIDE_0 = 0x0
	// Enable output-disable requests from the GTETRGn pins
	POEG_POEGGA_PIDE_1 = 0x1
	// Position of IOCE field.
	POEG_POEGGA_IOCE_Pos = 0x5
	// Bit mask of IOCE field.
	POEG_POEGGA_IOCE_Msk = 0x20
	// Bit IOCE.
	POEG_POEGGA_IOCE = 0x20
	// Disable output-disable requests from GPT
	POEG_POEGGA_IOCE_0 = 0x0
	// Enable output-disable requests from GPT
	POEG_POEGGA_IOCE_1 = 0x1
	// Position of OSTPE field.
	POEG_POEGGA_OSTPE_Pos = 0x6
	// Bit mask of OSTPE field.
	POEG_POEGGA_OSTPE_Msk = 0x40
	// Bit OSTPE.
	POEG_POEGGA_OSTPE = 0x40
	// Disable output-disable requests from oscillation stop detection
	POEG_POEGGA_OSTPE_0 = 0x0
	// Enable output-disable requests from oscillation stop detection
	POEG_POEGGA_OSTPE_1 = 0x1
	// Position of ST field.
	POEG_POEGGA_ST_Pos = 0x10
	// Bit mask of ST field.
	POEG_POEGGA_ST_Msk = 0x10000
	// Bit ST.
	POEG_POEGGA_ST = 0x10000
	// GTETRGn input after filtering was 0
	POEG_POEGGA_ST_0 = 0x0
	// GTETRGn input after filtering was 1
	POEG_POEGGA_ST_1 = 0x1
	// Position of INV field.
	POEG_POEGGA_INV_Pos = 0x1c
	// Bit mask of INV field.
	POEG_POEGGA_INV_Msk = 0x10000000
	// Bit INV.
	POEG_POEGGA_INV = 0x10000000
	// Input GTETRGn as-is
	POEG_POEGGA_INV_0 = 0x0
	// Input GTETRGn in reverse
	POEG_POEGGA_INV_1 = 0x1
	// Position of NFEN field.
	POEG_POEGGA_NFEN_Pos = 0x1d
	// Bit mask of NFEN field.
	POEG_POEGGA_NFEN_Msk = 0x20000000
	// Bit NFEN.
	POEG_POEGGA_NFEN = 0x20000000
	// Disable noise filtering
	POEG_POEGGA_NFEN_0 = 0x0
	// Enable noise filtering
	POEG_POEGGA_NFEN_1 = 0x1
	// Position of NFCS field.
	POEG_POEGGA_NFCS_Pos = 0x1e
	// Bit mask of NFCS field.
	POEG_POEGGA_NFCS_Msk = 0xc0000000
	// Sample GTETRGn pin input level three times every PCLKB
	POEG_POEGGA_NFCS_00 = 0x0
	// Sample GTETRGn pin input level three times every PCLKB/8
	POEG_POEGGA_NFCS_01 = 0x1
	// Sample GTETRGn pin input level three times every PCLKB/32
	POEG_POEGGA_NFCS_10 = 0x2
	// Sample GTETRGn pin input level three times every PCLKB/128
	POEG_POEGGA_NFCS_11 = 0x3

	// POEGGB: POEG Group B Setting Register
	// Position of PIDF field.
	POEG_POEGGB_PIDF_Pos = 0x0
	// Bit mask of PIDF field.
	POEG_POEGGB_PIDF_Msk = 0x1
	// Bit PIDF.
	POEG_POEGGB_PIDF = 0x1
	// No output-disable request from the GTETRGn pin occurred
	POEG_POEGGB_PIDF_0 = 0x0
	// Output-disable request from the GTETRGn pin occurred.
	POEG_POEGGB_PIDF_1 = 0x1
	// Position of IOCF field.
	POEG_POEGGB_IOCF_Pos = 0x1
	// Bit mask of IOCF field.
	POEG_POEGGB_IOCF_Msk = 0x2
	// Bit IOCF.
	POEG_POEGGB_IOCF = 0x2
	// No output-disable request from GPT occurred.
	POEG_POEGGB_IOCF_0 = 0x0
	// Output-disable request from GPT occurred.
	POEG_POEGGB_IOCF_1 = 0x1
	// Position of OSTPF field.
	POEG_POEGGB_OSTPF_Pos = 0x2
	// Bit mask of OSTPF field.
	POEG_POEGGB_OSTPF_Msk = 0x4
	// Bit OSTPF.
	POEG_POEGGB_OSTPF = 0x4
	// No output-disable request from oscillation stop detection occurred
	POEG_POEGGB_OSTPF_0 = 0x0
	// Output-disable request from oscillation stop detection occurred
	POEG_POEGGB_OSTPF_1 = 0x1
	// Position of SSF field.
	POEG_POEGGB_SSF_Pos = 0x3
	// Bit mask of SSF field.
	POEG_POEGGB_SSF_Msk = 0x8
	// Bit SSF.
	POEG_POEGGB_SSF = 0x8
	// No output-disable request from software occurred
	POEG_POEGGB_SSF_0 = 0x0
	// Output-disable request from software occurred
	POEG_POEGGB_SSF_1 = 0x1
	// Position of PIDE field.
	POEG_POEGGB_PIDE_Pos = 0x4
	// Bit mask of PIDE field.
	POEG_POEGGB_PIDE_Msk = 0x10
	// Bit PIDE.
	POEG_POEGGB_PIDE = 0x10
	// Disable output-disable requests from the GTETRGn pins
	POEG_POEGGB_PIDE_0 = 0x0
	// Enable output-disable requests from the GTETRGn pins
	POEG_POEGGB_PIDE_1 = 0x1
	// Position of IOCE field.
	POEG_POEGGB_IOCE_Pos = 0x5
	// Bit mask of IOCE field.
	POEG_POEGGB_IOCE_Msk = 0x20
	// Bit IOCE.
	POEG_POEGGB_IOCE = 0x20
	// Disable output-disable requests from GPT
	POEG_POEGGB_IOCE_0 = 0x0
	// Enable output-disable requests from GPT
	POEG_POEGGB_IOCE_1 = 0x1
	// Position of OSTPE field.
	POEG_POEGGB_OSTPE_Pos = 0x6
	// Bit mask of OSTPE field.
	POEG_POEGGB_OSTPE_Msk = 0x40
	// Bit OSTPE.
	POEG_POEGGB_OSTPE = 0x40
	// Disable output-disable requests from oscillation stop detection
	POEG_POEGGB_OSTPE_0 = 0x0
	// Enable output-disable requests from oscillation stop detection
	POEG_POEGGB_OSTPE_1 = 0x1
	// Position of ST field.
	POEG_POEGGB_ST_Pos = 0x10
	// Bit mask of ST field.
	POEG_POEGGB_ST_Msk = 0x10000
	// Bit ST.
	POEG_POEGGB_ST = 0x10000
	// GTETRGn input after filtering was 0
	POEG_POEGGB_ST_0 = 0x0
	// GTETRGn input after filtering was 1
	POEG_POEGGB_ST_1 = 0x1
	// Position of INV field.
	POEG_POEGGB_INV_Pos = 0x1c
	// Bit mask of INV field.
	POEG_POEGGB_INV_Msk = 0x10000000
	// Bit INV.
	POEG_POEGGB_INV = 0x10000000
	// Input GTETRGn as-is
	POEG_POEGGB_INV_0 = 0x0
	// Input GTETRGn in reverse
	POEG_POEGGB_INV_1 = 0x1
	// Position of NFEN field.
	POEG_POEGGB_NFEN_Pos = 0x1d
	// Bit mask of NFEN field.
	POEG_POEGGB_NFEN_Msk = 0x20000000
	// Bit NFEN.
	POEG_POEGGB_NFEN = 0x20000000
	// Disable noise filtering
	POEG_POEGGB_NFEN_0 = 0x0
	// Enable noise filtering
	POEG_POEGGB_NFEN_1 = 0x1
	// Position of NFCS field.
	POEG_POEGGB_NFCS_Pos = 0x1e
	// Bit mask of NFCS field.
	POEG_POEGGB_NFCS_Msk = 0xc0000000
	// Sample GTETRGn pin input level three times every PCLKB
	POEG_POEGGB_NFCS_00 = 0x0
	// Sample GTETRGn pin input level three times every PCLKB/8
	POEG_POEGGB_NFCS_01 = 0x1
	// Sample GTETRGn pin input level three times every PCLKB/32
	POEG_POEGGB_NFCS_10 = 0x2
	// Sample GTETRGn pin input level three times every PCLKB/128
	POEG_POEGGB_NFCS_11 = 0x3

	// POEGGC: POEG Group C Setting Register
	// Position of PIDF field.
	POEG_POEGGC_PIDF_Pos = 0x0
	// Bit mask of PIDF field.
	POEG_POEGGC_PIDF_Msk = 0x1
	// Bit PIDF.
	POEG_POEGGC_PIDF = 0x1
	// No output-disable request from the GTETRGn pin occurred
	POEG_POEGGC_PIDF_0 = 0x0
	// Output-disable request from the GTETRGn pin occurred.
	POEG_POEGGC_PIDF_1 = 0x1
	// Position of IOCF field.
	POEG_POEGGC_IOCF_Pos = 0x1
	// Bit mask of IOCF field.
	POEG_POEGGC_IOCF_Msk = 0x2
	// Bit IOCF.
	POEG_POEGGC_IOCF = 0x2
	// No output-disable request from GPT occurred.
	POEG_POEGGC_IOCF_0 = 0x0
	// Output-disable request from GPT occurred.
	POEG_POEGGC_IOCF_1 = 0x1
	// Position of OSTPF field.
	POEG_POEGGC_OSTPF_Pos = 0x2
	// Bit mask of OSTPF field.
	POEG_POEGGC_OSTPF_Msk = 0x4
	// Bit OSTPF.
	POEG_POEGGC_OSTPF = 0x4
	// No output-disable request from oscillation stop detection occurred
	POEG_POEGGC_OSTPF_0 = 0x0
	// Output-disable request from oscillation stop detection occurred
	POEG_POEGGC_OSTPF_1 = 0x1
	// Position of SSF field.
	POEG_POEGGC_SSF_Pos = 0x3
	// Bit mask of SSF field.
	POEG_POEGGC_SSF_Msk = 0x8
	// Bit SSF.
	POEG_POEGGC_SSF = 0x8
	// No output-disable request from software occurred
	POEG_POEGGC_SSF_0 = 0x0
	// Output-disable request from software occurred
	POEG_POEGGC_SSF_1 = 0x1
	// Position of PIDE field.
	POEG_POEGGC_PIDE_Pos = 0x4
	// Bit mask of PIDE field.
	POEG_POEGGC_PIDE_Msk = 0x10
	// Bit PIDE.
	POEG_POEGGC_PIDE = 0x10
	// Disable output-disable requests from the GTETRGn pins
	POEG_POEGGC_PIDE_0 = 0x0
	// Enable output-disable requests from the GTETRGn pins
	POEG_POEGGC_PIDE_1 = 0x1
	// Position of IOCE field.
	POEG_POEGGC_IOCE_Pos = 0x5
	// Bit mask of IOCE field.
	POEG_POEGGC_IOCE_Msk = 0x20
	// Bit IOCE.
	POEG_POEGGC_IOCE = 0x20
	// Disable output-disable requests from GPT
	POEG_POEGGC_IOCE_0 = 0x0
	// Enable output-disable requests from GPT
	POEG_POEGGC_IOCE_1 = 0x1
	// Position of OSTPE field.
	POEG_POEGGC_OSTPE_Pos = 0x6
	// Bit mask of OSTPE field.
	POEG_POEGGC_OSTPE_Msk = 0x40
	// Bit OSTPE.
	POEG_POEGGC_OSTPE = 0x40
	// Disable output-disable requests from oscillation stop detection
	POEG_POEGGC_OSTPE_0 = 0x0
	// Enable output-disable requests from oscillation stop detection
	POEG_POEGGC_OSTPE_1 = 0x1
	// Position of ST field.
	POEG_POEGGC_ST_Pos = 0x10
	// Bit mask of ST field.
	POEG_POEGGC_ST_Msk = 0x10000
	// Bit ST.
	POEG_POEGGC_ST = 0x10000
	// GTETRGn input after filtering was 0
	POEG_POEGGC_ST_0 = 0x0
	// GTETRGn input after filtering was 1
	POEG_POEGGC_ST_1 = 0x1
	// Position of INV field.
	POEG_POEGGC_INV_Pos = 0x1c
	// Bit mask of INV field.
	POEG_POEGGC_INV_Msk = 0x10000000
	// Bit INV.
	POEG_POEGGC_INV = 0x10000000
	// Input GTETRGn as-is
	POEG_POEGGC_INV_0 = 0x0
	// Input GTETRGn in reverse
	POEG_POEGGC_INV_1 = 0x1
	// Position of NFEN field.
	POEG_POEGGC_NFEN_Pos = 0x1d
	// Bit mask of NFEN field.
	POEG_POEGGC_NFEN_Msk = 0x20000000
	// Bit NFEN.
	POEG_POEGGC_NFEN = 0x20000000
	// Disable noise filtering
	POEG_POEGGC_NFEN_0 = 0x0
	// Enable noise filtering
	POEG_POEGGC_NFEN_1 = 0x1
	// Position of NFCS field.
	POEG_POEGGC_NFCS_Pos = 0x1e
	// Bit mask of NFCS field.
	POEG_POEGGC_NFCS_Msk = 0xc0000000
	// Sample GTETRGn pin input level three times every PCLKB
	POEG_POEGGC_NFCS_00 = 0x0
	// Sample GTETRGn pin input level three times every PCLKB/8
	POEG_POEGGC_NFCS_01 = 0x1
	// Sample GTETRGn pin input level three times every PCLKB/32
	POEG_POEGGC_NFCS_10 = 0x2
	// Sample GTETRGn pin input level three times every PCLKB/128
	POEG_POEGGC_NFCS_11 = 0x3

	// POEGGD: POEG Group D Setting Register
	// Position of PIDF field.
	POEG_POEGGD_PIDF_Pos = 0x0
	// Bit mask of PIDF field.
	POEG_POEGGD_PIDF_Msk = 0x1
	// Bit PIDF.
	POEG_POEGGD_PIDF = 0x1
	// No output-disable request from the GTETRGn pin occurred
	POEG_POEGGD_PIDF_0 = 0x0
	// Output-disable request from the GTETRGn pin occurred.
	POEG_POEGGD_PIDF_1 = 0x1
	// Position of IOCF field.
	POEG_POEGGD_IOCF_Pos = 0x1
	// Bit mask of IOCF field.
	POEG_POEGGD_IOCF_Msk = 0x2
	// Bit IOCF.
	POEG_POEGGD_IOCF = 0x2
	// No output-disable request from GPT occurred.
	POEG_POEGGD_IOCF_0 = 0x0
	// Output-disable request from GPT occurred.
	POEG_POEGGD_IOCF_1 = 0x1
	// Position of OSTPF field.
	POEG_POEGGD_OSTPF_Pos = 0x2
	// Bit mask of OSTPF field.
	POEG_POEGGD_OSTPF_Msk = 0x4
	// Bit OSTPF.
	POEG_POEGGD_OSTPF = 0x4
	// No output-disable request from oscillation stop detection occurred
	POEG_POEGGD_OSTPF_0 = 0x0
	// Output-disable request from oscillation stop detection occurred
	POEG_POEGGD_OSTPF_1 = 0x1
	// Position of SSF field.
	POEG_POEGGD_SSF_Pos = 0x3
	// Bit mask of SSF field.
	POEG_POEGGD_SSF_Msk = 0x8
	// Bit SSF.
	POEG_POEGGD_SSF = 0x8
	// No output-disable request from software occurred
	POEG_POEGGD_SSF_0 = 0x0
	// Output-disable request from software occurred
	POEG_POEGGD_SSF_1 = 0x1
	// Position of PIDE field.
	POEG_POEGGD_PIDE_Pos = 0x4
	// Bit mask of PIDE field.
	POEG_POEGGD_PIDE_Msk = 0x10
	// Bit PIDE.
	POEG_POEGGD_PIDE = 0x10
	// Disable output-disable requests from the GTETRGn pins
	POEG_POEGGD_PIDE_0 = 0x0
	// Enable output-disable requests from the GTETRGn pins
	POEG_POEGGD_PIDE_1 = 0x1
	// Position of IOCE field.
	POEG_POEGGD_IOCE_Pos = 0x5
	// Bit mask of IOCE field.
	POEG_POEGGD_IOCE_Msk = 0x20
	// Bit IOCE.
	POEG_POEGGD_IOCE = 0x20
	// Disable output-disable requests from GPT
	POEG_POEGGD_IOCE_0 = 0x0
	// Enable output-disable requests from GPT
	POEG_POEGGD_IOCE_1 = 0x1
	// Position of OSTPE field.
	POEG_POEGGD_OSTPE_Pos = 0x6
	// Bit mask of OSTPE field.
	POEG_POEGGD_OSTPE_Msk = 0x40
	// Bit OSTPE.
	POEG_POEGGD_OSTPE = 0x40
	// Disable output-disable requests from oscillation stop detection
	POEG_POEGGD_OSTPE_0 = 0x0
	// Enable output-disable requests from oscillation stop detection
	POEG_POEGGD_OSTPE_1 = 0x1
	// Position of ST field.
	POEG_POEGGD_ST_Pos = 0x10
	// Bit mask of ST field.
	POEG_POEGGD_ST_Msk = 0x10000
	// Bit ST.
	POEG_POEGGD_ST = 0x10000
	// GTETRGn input after filtering was 0
	POEG_POEGGD_ST_0 = 0x0
	// GTETRGn input after filtering was 1
	POEG_POEGGD_ST_1 = 0x1
	// Position of INV field.
	POEG_POEGGD_INV_Pos = 0x1c
	// Bit mask of INV field.
	POEG_POEGGD_INV_Msk = 0x10000000
	// Bit INV.
	POEG_POEGGD_INV = 0x10000000
	// Input GTETRGn as-is
	POEG_POEGGD_INV_0 = 0x0
	// Input GTETRGn in reverse
	POEG_POEGGD_INV_1 = 0x1
	// Position of NFEN field.
	POEG_POEGGD_NFEN_Pos = 0x1d
	// Bit mask of NFEN field.
	POEG_POEGGD_NFEN_Msk = 0x20000000
	// Bit NFEN.
	POEG_POEGGD_NFEN = 0x20000000
	// Disable noise filtering
	POEG_POEGGD_NFEN_0 = 0x0
	// Enable noise filtering
	POEG_POEGGD_NFEN_1 = 0x1
	// Position of NFCS field.
	POEG_POEGGD_NFCS_Pos = 0x1e
	// Bit mask of NFCS field.
	POEG_POEGGD_NFCS_Msk = 0xc0000000
	// Sample GTETRGn pin input level three times every PCLKB
	POEG_POEGGD_NFCS_00 = 0x0
	// Sample GTETRGn pin input level three times every PCLKB/8
	POEG_POEGGD_NFCS_01 = 0x1
	// Sample GTETRGn pin input level three times every PCLKB/32
	POEG_POEGGD_NFCS_10 = 0x2
	// Sample GTETRGn pin input level three times every PCLKB/128
	POEG_POEGGD_NFCS_11 = 0x3
)

// Constants for USBFS: USB 2.0 Full-Speed Module
const (
	// SYSCFG: System Configuration Control Register
	// Position of USBE field.
	USBFS_SYSCFG_USBE_Pos = 0x0
	// Bit mask of USBE field.
	USBFS_SYSCFG_USBE_Msk = 0x1
	// Bit USBE.
	USBFS_SYSCFG_USBE = 0x1
	// Disable
	USBFS_SYSCFG_USBE_0 = 0x0
	// Enable
	USBFS_SYSCFG_USBE_1 = 0x1
	// Position of DPRPU field.
	USBFS_SYSCFG_DPRPU_Pos = 0x4
	// Bit mask of DPRPU field.
	USBFS_SYSCFG_DPRPU_Msk = 0x10
	// Bit DPRPU.
	USBFS_SYSCFG_DPRPU = 0x10
	// Disable line pull-up
	USBFS_SYSCFG_DPRPU_0 = 0x0
	// Enable line pull-up
	USBFS_SYSCFG_DPRPU_1 = 0x1
	// Position of SCKE field.
	USBFS_SYSCFG_SCKE_Pos = 0xa
	// Bit mask of SCKE field.
	USBFS_SYSCFG_SCKE_Msk = 0x400
	// Bit SCKE.
	USBFS_SYSCFG_SCKE = 0x400
	// Stop clock supply to the USBFS
	USBFS_SYSCFG_SCKE_0 = 0x0
	// Enable clock supply to the USBFS
	USBFS_SYSCFG_SCKE_1 = 0x1

	// SYSSTS0: System Configuration Status Register 0
	// Position of LNST field.
	USBFS_SYSSTS0_LNST_Pos = 0x0
	// Bit mask of LNST field.
	USBFS_SYSSTS0_LNST_Msk = 0x3

	// DVSTCTR0: Device State Control Register 0
	// Position of RHST field.
	USBFS_DVSTCTR0_RHST_Pos = 0x0
	// Bit mask of RHST field.
	USBFS_DVSTCTR0_RHST_Msk = 0x7
	// Communication speed indeterminate
	USBFS_DVSTCTR0_RHST_000 = 0x0
	// USB bus reset in progress
	USBFS_DVSTCTR0_RHST_001 = 0x1
	// USB bus reset in progress or full-speed connection
	USBFS_DVSTCTR0_RHST_010 = 0x2
	// Setting prohibited
	USBFS_DVSTCTR0_RHST_Others = 0x3
	// Position of WKUP field.
	USBFS_DVSTCTR0_WKUP_Pos = 0x8
	// Bit mask of WKUP field.
	USBFS_DVSTCTR0_WKUP_Msk = 0x100
	// Bit WKUP.
	USBFS_DVSTCTR0_WKUP = 0x100
	// Do not output remote wakeup signal
	USBFS_DVSTCTR0_WKUP_0 = 0x0
	// Output remote wakeup signal
	USBFS_DVSTCTR0_WKUP_1 = 0x1

	// CFIFO: CFIFO Port Register
	// Position of FIFOPORT field.
	USBFS_CFIFO_FIFOPORT_Pos = 0x0
	// Bit mask of FIFOPORT field.
	USBFS_CFIFO_FIFOPORT_Msk = 0xffff

	// CFIFOSEL: CFIFO Port Select Register
	// Position of CURPIPE field.
	USBFS_CFIFOSEL_CURPIPE_Pos = 0x0
	// Bit mask of CURPIPE field.
	USBFS_CFIFOSEL_CURPIPE_Msk = 0xf
	// Default Control Pipe
	USBFS_CFIFOSEL_CURPIPE_0x0 = 0x0
	// Pipe 4
	USBFS_CFIFOSEL_CURPIPE_0x4 = 0x4
	// Pipe 5
	USBFS_CFIFOSEL_CURPIPE_0x5 = 0x5
	// Pipe 6
	USBFS_CFIFOSEL_CURPIPE_0x6 = 0x6
	// Pipe 7
	USBFS_CFIFOSEL_CURPIPE_0x7 = 0x7
	// Setting prohibited
	USBFS_CFIFOSEL_CURPIPE_Others = 0x8
	// Position of ISEL field.
	USBFS_CFIFOSEL_ISEL_Pos = 0x5
	// Bit mask of ISEL field.
	USBFS_CFIFOSEL_ISEL_Msk = 0x20
	// Bit ISEL.
	USBFS_CFIFOSEL_ISEL = 0x20
	// Select reading from the FIFO buffer
	USBFS_CFIFOSEL_ISEL_0 = 0x0
	// Select writing to the FIFO buffer
	USBFS_CFIFOSEL_ISEL_1 = 0x1
	// Position of BIGEND field.
	USBFS_CFIFOSEL_BIGEND_Pos = 0x8
	// Bit mask of BIGEND field.
	USBFS_CFIFOSEL_BIGEND_Msk = 0x100
	// Bit BIGEND.
	USBFS_CFIFOSEL_BIGEND = 0x100
	// Little endian
	USBFS_CFIFOSEL_BIGEND_0 = 0x0
	// Big endian
	USBFS_CFIFOSEL_BIGEND_1 = 0x1
	// Position of MBW field.
	USBFS_CFIFOSEL_MBW_Pos = 0xa
	// Bit mask of MBW field.
	USBFS_CFIFOSEL_MBW_Msk = 0x400
	// Bit MBW.
	USBFS_CFIFOSEL_MBW = 0x400
	// 8-bit width
	USBFS_CFIFOSEL_MBW_0 = 0x0
	// 16-bit width
	USBFS_CFIFOSEL_MBW_1 = 0x1
	// Position of REW field.
	USBFS_CFIFOSEL_REW_Pos = 0xe
	// Bit mask of REW field.
	USBFS_CFIFOSEL_REW_Msk = 0x4000
	// Bit REW.
	USBFS_CFIFOSEL_REW = 0x4000
	// Do not rewind buffer pointer
	USBFS_CFIFOSEL_REW_0 = 0x0
	// Rewind buffer pointer
	USBFS_CFIFOSEL_REW_1 = 0x1
	// Position of RCNT field.
	USBFS_CFIFOSEL_RCNT_Pos = 0xf
	// Bit mask of RCNT field.
	USBFS_CFIFOSEL_RCNT_Msk = 0x8000
	// Bit RCNT.
	USBFS_CFIFOSEL_RCNT = 0x8000
	// The DTLN[8:0] bits (CFIFOCTR.DTLN[8:0]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN[8:0] value is cleared when all data is read from only a single plane.
	USBFS_CFIFOSEL_RCNT_0 = 0x0
	// The DTLN[8:0] bits are decremented each time the receive data is read from the CFIFO.
	USBFS_CFIFOSEL_RCNT_1 = 0x1

	// CFIFOCTR: CFIFO Port Control Register
	// Position of DTLN field.
	USBFS_CFIFOCTR_DTLN_Pos = 0x0
	// Bit mask of DTLN field.
	USBFS_CFIFOCTR_DTLN_Msk = 0x1ff
	// Position of FRDY field.
	USBFS_CFIFOCTR_FRDY_Pos = 0xd
	// Bit mask of FRDY field.
	USBFS_CFIFOCTR_FRDY_Msk = 0x2000
	// Bit FRDY.
	USBFS_CFIFOCTR_FRDY = 0x2000
	// FIFO port access disabled
	USBFS_CFIFOCTR_FRDY_0 = 0x0
	// FIFO port access enabled
	USBFS_CFIFOCTR_FRDY_1 = 0x1
	// Position of BCLR field.
	USBFS_CFIFOCTR_BCLR_Pos = 0xe
	// Bit mask of BCLR field.
	USBFS_CFIFOCTR_BCLR_Msk = 0x4000
	// Bit BCLR.
	USBFS_CFIFOCTR_BCLR = 0x4000
	// No operation
	USBFS_CFIFOCTR_BCLR_0 = 0x0
	// Clear FIFO buffer on the CPU side
	USBFS_CFIFOCTR_BCLR_1 = 0x1
	// Position of BVAL field.
	USBFS_CFIFOCTR_BVAL_Pos = 0xf
	// Bit mask of BVAL field.
	USBFS_CFIFOCTR_BVAL_Msk = 0x8000
	// Bit BVAL.
	USBFS_CFIFOCTR_BVAL = 0x8000
	// Invalid (writing 0 has no effect)
	USBFS_CFIFOCTR_BVAL_0 = 0x0
	// Writing ended
	USBFS_CFIFOCTR_BVAL_1 = 0x1

	// INTENB0: Interrupt Enable Register 0
	// Position of BRDYE field.
	USBFS_INTENB0_BRDYE_Pos = 0x8
	// Bit mask of BRDYE field.
	USBFS_INTENB0_BRDYE_Msk = 0x100
	// Bit BRDYE.
	USBFS_INTENB0_BRDYE = 0x100
	// Disable interrupt request
	USBFS_INTENB0_BRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_BRDYE_1 = 0x1
	// Position of NRDYE field.
	USBFS_INTENB0_NRDYE_Pos = 0x9
	// Bit mask of NRDYE field.
	USBFS_INTENB0_NRDYE_Msk = 0x200
	// Bit NRDYE.
	USBFS_INTENB0_NRDYE = 0x200
	// Disable interrupt request
	USBFS_INTENB0_NRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_NRDYE_1 = 0x1
	// Position of BEMPE field.
	USBFS_INTENB0_BEMPE_Pos = 0xa
	// Bit mask of BEMPE field.
	USBFS_INTENB0_BEMPE_Msk = 0x400
	// Bit BEMPE.
	USBFS_INTENB0_BEMPE = 0x400
	// Disable interrupt request
	USBFS_INTENB0_BEMPE_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_BEMPE_1 = 0x1
	// Position of CTRE field.
	USBFS_INTENB0_CTRE_Pos = 0xb
	// Bit mask of CTRE field.
	USBFS_INTENB0_CTRE_Msk = 0x800
	// Bit CTRE.
	USBFS_INTENB0_CTRE = 0x800
	// Disable interrupt request
	USBFS_INTENB0_CTRE_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_CTRE_1 = 0x1
	// Position of DVSE field.
	USBFS_INTENB0_DVSE_Pos = 0xc
	// Bit mask of DVSE field.
	USBFS_INTENB0_DVSE_Msk = 0x1000
	// Bit DVSE.
	USBFS_INTENB0_DVSE = 0x1000
	// Disable interrupt request
	USBFS_INTENB0_DVSE_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_DVSE_1 = 0x1
	// Position of SOFE field.
	USBFS_INTENB0_SOFE_Pos = 0xd
	// Bit mask of SOFE field.
	USBFS_INTENB0_SOFE_Msk = 0x2000
	// Bit SOFE.
	USBFS_INTENB0_SOFE = 0x2000
	// Disable interrupt request
	USBFS_INTENB0_SOFE_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_SOFE_1 = 0x1
	// Position of RSME field.
	USBFS_INTENB0_RSME_Pos = 0xe
	// Bit mask of RSME field.
	USBFS_INTENB0_RSME_Msk = 0x4000
	// Bit RSME.
	USBFS_INTENB0_RSME = 0x4000
	// Disable interrupt request
	USBFS_INTENB0_RSME_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_RSME_1 = 0x1
	// Position of VBSE field.
	USBFS_INTENB0_VBSE_Pos = 0xf
	// Bit mask of VBSE field.
	USBFS_INTENB0_VBSE_Msk = 0x8000
	// Bit VBSE.
	USBFS_INTENB0_VBSE = 0x8000
	// Disable interrupt request
	USBFS_INTENB0_VBSE_0 = 0x0
	// Enable interrupt request
	USBFS_INTENB0_VBSE_1 = 0x1

	// BRDYENB: BRDY Interrupt Enable Register
	// Position of PIPE0BRDYE field.
	USBFS_BRDYENB_PIPE0BRDYE_Pos = 0x0
	// Bit mask of PIPE0BRDYE field.
	USBFS_BRDYENB_PIPE0BRDYE_Msk = 0x1
	// Bit PIPE0BRDYE.
	USBFS_BRDYENB_PIPE0BRDYE = 0x1
	// Disable interrupt request
	USBFS_BRDYENB_PIPE0BRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_BRDYENB_PIPE0BRDYE_1 = 0x1
	// Position of PIPE4BRDYE field.
	USBFS_BRDYENB_PIPE4BRDYE_Pos = 0x4
	// Bit mask of PIPE4BRDYE field.
	USBFS_BRDYENB_PIPE4BRDYE_Msk = 0x10
	// Bit PIPE4BRDYE.
	USBFS_BRDYENB_PIPE4BRDYE = 0x10
	// Disable interrupt request
	USBFS_BRDYENB_PIPE4BRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_BRDYENB_PIPE4BRDYE_1 = 0x1
	// Position of PIPE5BRDYE field.
	USBFS_BRDYENB_PIPE5BRDYE_Pos = 0x5
	// Bit mask of PIPE5BRDYE field.
	USBFS_BRDYENB_PIPE5BRDYE_Msk = 0x20
	// Bit PIPE5BRDYE.
	USBFS_BRDYENB_PIPE5BRDYE = 0x20
	// Disable interrupt request
	USBFS_BRDYENB_PIPE5BRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_BRDYENB_PIPE5BRDYE_1 = 0x1
	// Position of PIPE6BRDYE field.
	USBFS_BRDYENB_PIPE6BRDYE_Pos = 0x6
	// Bit mask of PIPE6BRDYE field.
	USBFS_BRDYENB_PIPE6BRDYE_Msk = 0x40
	// Bit PIPE6BRDYE.
	USBFS_BRDYENB_PIPE6BRDYE = 0x40
	// Disable interrupt request
	USBFS_BRDYENB_PIPE6BRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_BRDYENB_PIPE6BRDYE_1 = 0x1
	// Position of PIPE7BRDYE field.
	USBFS_BRDYENB_PIPE7BRDYE_Pos = 0x7
	// Bit mask of PIPE7BRDYE field.
	USBFS_BRDYENB_PIPE7BRDYE_Msk = 0x80
	// Bit PIPE7BRDYE.
	USBFS_BRDYENB_PIPE7BRDYE = 0x80
	// Disable interrupt request
	USBFS_BRDYENB_PIPE7BRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_BRDYENB_PIPE7BRDYE_1 = 0x1

	// NRDYENB: NRDY Interrupt Enable Register
	// Position of PIPE0NRDYE field.
	USBFS_NRDYENB_PIPE0NRDYE_Pos = 0x0
	// Bit mask of PIPE0NRDYE field.
	USBFS_NRDYENB_PIPE0NRDYE_Msk = 0x1
	// Bit PIPE0NRDYE.
	USBFS_NRDYENB_PIPE0NRDYE = 0x1
	// Disable interrupt request
	USBFS_NRDYENB_PIPE0NRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_NRDYENB_PIPE0NRDYE_1 = 0x1
	// Position of PIPE4NRDYE field.
	USBFS_NRDYENB_PIPE4NRDYE_Pos = 0x4
	// Bit mask of PIPE4NRDYE field.
	USBFS_NRDYENB_PIPE4NRDYE_Msk = 0x10
	// Bit PIPE4NRDYE.
	USBFS_NRDYENB_PIPE4NRDYE = 0x10
	// Disable interrupt request
	USBFS_NRDYENB_PIPE4NRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_NRDYENB_PIPE4NRDYE_1 = 0x1
	// Position of PIPE5NRDYE field.
	USBFS_NRDYENB_PIPE5NRDYE_Pos = 0x5
	// Bit mask of PIPE5NRDYE field.
	USBFS_NRDYENB_PIPE5NRDYE_Msk = 0x20
	// Bit PIPE5NRDYE.
	USBFS_NRDYENB_PIPE5NRDYE = 0x20
	// Disable interrupt request
	USBFS_NRDYENB_PIPE5NRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_NRDYENB_PIPE5NRDYE_1 = 0x1
	// Position of PIPE6NRDYE field.
	USBFS_NRDYENB_PIPE6NRDYE_Pos = 0x6
	// Bit mask of PIPE6NRDYE field.
	USBFS_NRDYENB_PIPE6NRDYE_Msk = 0x40
	// Bit PIPE6NRDYE.
	USBFS_NRDYENB_PIPE6NRDYE = 0x40
	// Disable interrupt request
	USBFS_NRDYENB_PIPE6NRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_NRDYENB_PIPE6NRDYE_1 = 0x1
	// Position of PIPE7NRDYE field.
	USBFS_NRDYENB_PIPE7NRDYE_Pos = 0x7
	// Bit mask of PIPE7NRDYE field.
	USBFS_NRDYENB_PIPE7NRDYE_Msk = 0x80
	// Bit PIPE7NRDYE.
	USBFS_NRDYENB_PIPE7NRDYE = 0x80
	// Disable interrupt request
	USBFS_NRDYENB_PIPE7NRDYE_0 = 0x0
	// Enable interrupt request
	USBFS_NRDYENB_PIPE7NRDYE_1 = 0x1

	// BEMPENB: BEMP Interrupt Enable Register
	// Position of PIPE0BEMPE field.
	USBFS_BEMPENB_PIPE0BEMPE_Pos = 0x0
	// Bit mask of PIPE0BEMPE field.
	USBFS_BEMPENB_PIPE0BEMPE_Msk = 0x1
	// Bit PIPE0BEMPE.
	USBFS_BEMPENB_PIPE0BEMPE = 0x1
	// Disable interrupt request
	USBFS_BEMPENB_PIPE0BEMPE_0 = 0x0
	// Enable interrupt request
	USBFS_BEMPENB_PIPE0BEMPE_1 = 0x1
	// Position of PIPE4BEMPE field.
	USBFS_BEMPENB_PIPE4BEMPE_Pos = 0x4
	// Bit mask of PIPE4BEMPE field.
	USBFS_BEMPENB_PIPE4BEMPE_Msk = 0x10
	// Bit PIPE4BEMPE.
	USBFS_BEMPENB_PIPE4BEMPE = 0x10
	// Disable interrupt request
	USBFS_BEMPENB_PIPE4BEMPE_0 = 0x0
	// Enable interrupt request
	USBFS_BEMPENB_PIPE4BEMPE_1 = 0x1
	// Position of PIPE5BEMPE field.
	USBFS_BEMPENB_PIPE5BEMPE_Pos = 0x5
	// Bit mask of PIPE5BEMPE field.
	USBFS_BEMPENB_PIPE5BEMPE_Msk = 0x20
	// Bit PIPE5BEMPE.
	USBFS_BEMPENB_PIPE5BEMPE = 0x20
	// Disable interrupt request
	USBFS_BEMPENB_PIPE5BEMPE_0 = 0x0
	// Enable interrupt request
	USBFS_BEMPENB_PIPE5BEMPE_1 = 0x1
	// Position of PIPE6BEMPE field.
	USBFS_BEMPENB_PIPE6BEMPE_Pos = 0x6
	// Bit mask of PIPE6BEMPE field.
	USBFS_BEMPENB_PIPE6BEMPE_Msk = 0x40
	// Bit PIPE6BEMPE.
	USBFS_BEMPENB_PIPE6BEMPE = 0x40
	// Disable interrupt request
	USBFS_BEMPENB_PIPE6BEMPE_0 = 0x0
	// Enable interrupt request
	USBFS_BEMPENB_PIPE6BEMPE_1 = 0x1
	// Position of PIPE7BEMPE field.
	USBFS_BEMPENB_PIPE7BEMPE_Pos = 0x7
	// Bit mask of PIPE7BEMPE field.
	USBFS_BEMPENB_PIPE7BEMPE_Msk = 0x80
	// Bit PIPE7BEMPE.
	USBFS_BEMPENB_PIPE7BEMPE = 0x80
	// Disable interrupt request
	USBFS_BEMPENB_PIPE7BEMPE_0 = 0x0
	// Enable interrupt request
	USBFS_BEMPENB_PIPE7BEMPE_1 = 0x1

	// SOFCFG: SOF Output Configuration Register
	// Position of EDGESTS field.
	USBFS_SOFCFG_EDGESTS_Pos = 0x4
	// Bit mask of EDGESTS field.
	USBFS_SOFCFG_EDGESTS_Msk = 0x10
	// Bit EDGESTS.
	USBFS_SOFCFG_EDGESTS = 0x10
	// Position of BRDYM field.
	USBFS_SOFCFG_BRDYM_Pos = 0x6
	// Bit mask of BRDYM field.
	USBFS_SOFCFG_BRDYM_Msk = 0x40
	// Bit BRDYM.
	USBFS_SOFCFG_BRDYM = 0x40
	// Clear BRDY flag by software
	USBFS_SOFCFG_BRDYM_0 = 0x0
	// Clear BRDY flag by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer
	USBFS_SOFCFG_BRDYM_1 = 0x1

	// INTSTS0: Interrupt Status Register 0
	// Position of CTSQ field.
	USBFS_INTSTS0_CTSQ_Pos = 0x0
	// Bit mask of CTSQ field.
	USBFS_INTSTS0_CTSQ_Msk = 0x7
	// Idle or setup stage
	USBFS_INTSTS0_CTSQ_000 = 0x0
	// Control read data stage
	USBFS_INTSTS0_CTSQ_001 = 0x1
	// Control read status stage
	USBFS_INTSTS0_CTSQ_010 = 0x2
	// Control write data stage
	USBFS_INTSTS0_CTSQ_011 = 0x3
	// Control write status stage
	USBFS_INTSTS0_CTSQ_100 = 0x4
	// Control write (no data) status stage
	USBFS_INTSTS0_CTSQ_101 = 0x5
	// Control transfer sequence error
	USBFS_INTSTS0_CTSQ_110 = 0x6
	// Position of VALID field.
	USBFS_INTSTS0_VALID_Pos = 0x3
	// Bit mask of VALID field.
	USBFS_INTSTS0_VALID_Msk = 0x8
	// Bit VALID.
	USBFS_INTSTS0_VALID = 0x8
	// Setup packet not received
	USBFS_INTSTS0_VALID_0 = 0x0
	// Setup packet received
	USBFS_INTSTS0_VALID_1 = 0x1
	// Position of DVSQ field.
	USBFS_INTSTS0_DVSQ_Pos = 0x4
	// Bit mask of DVSQ field.
	USBFS_INTSTS0_DVSQ_Msk = 0x70
	// Powered state
	USBFS_INTSTS0_DVSQ_000 = 0x0
	// Default state
	USBFS_INTSTS0_DVSQ_001 = 0x1
	// Address state
	USBFS_INTSTS0_DVSQ_010 = 0x2
	// Configured state
	USBFS_INTSTS0_DVSQ_011 = 0x3
	// Suspend state
	USBFS_INTSTS0_DVSQ_Others = 0x4
	// Position of VBSTS field.
	USBFS_INTSTS0_VBSTS_Pos = 0x7
	// Bit mask of VBSTS field.
	USBFS_INTSTS0_VBSTS_Msk = 0x80
	// Bit VBSTS.
	USBFS_INTSTS0_VBSTS = 0x80
	// USB_VBUS pin is low
	USBFS_INTSTS0_VBSTS_0 = 0x0
	// USB_VBUS pin is high
	USBFS_INTSTS0_VBSTS_1 = 0x1
	// Position of BRDY field.
	USBFS_INTSTS0_BRDY_Pos = 0x8
	// Bit mask of BRDY field.
	USBFS_INTSTS0_BRDY_Msk = 0x100
	// Bit BRDY.
	USBFS_INTSTS0_BRDY = 0x100
	// No BRDY interrupt occurred
	USBFS_INTSTS0_BRDY_0 = 0x0
	// BRDY interrupt occurred
	USBFS_INTSTS0_BRDY_1 = 0x1
	// Position of NRDY field.
	USBFS_INTSTS0_NRDY_Pos = 0x9
	// Bit mask of NRDY field.
	USBFS_INTSTS0_NRDY_Msk = 0x200
	// Bit NRDY.
	USBFS_INTSTS0_NRDY = 0x200
	// No NRDY interrupt occurred
	USBFS_INTSTS0_NRDY_0 = 0x0
	// NRDY interrupt occurred
	USBFS_INTSTS0_NRDY_1 = 0x1
	// Position of BEMP field.
	USBFS_INTSTS0_BEMP_Pos = 0xa
	// Bit mask of BEMP field.
	USBFS_INTSTS0_BEMP_Msk = 0x400
	// Bit BEMP.
	USBFS_INTSTS0_BEMP = 0x400
	// No BEMP interrupt occurred
	USBFS_INTSTS0_BEMP_0 = 0x0
	// BEMP interrupt occurred
	USBFS_INTSTS0_BEMP_1 = 0x1
	// Position of CTRT field.
	USBFS_INTSTS0_CTRT_Pos = 0xb
	// Bit mask of CTRT field.
	USBFS_INTSTS0_CTRT_Msk = 0x800
	// Bit CTRT.
	USBFS_INTSTS0_CTRT = 0x800
	// No control transfer stage transition interrupt occurred
	USBFS_INTSTS0_CTRT_0 = 0x0
	// Control transfer stage transition interrupt occurred
	USBFS_INTSTS0_CTRT_1 = 0x1
	// Position of DVST field.
	USBFS_INTSTS0_DVST_Pos = 0xc
	// Bit mask of DVST field.
	USBFS_INTSTS0_DVST_Msk = 0x1000
	// Bit DVST.
	USBFS_INTSTS0_DVST = 0x1000
	// No device state transition interrupt occurred
	USBFS_INTSTS0_DVST_0 = 0x0
	// Device state transition interrupt occurred
	USBFS_INTSTS0_DVST_1 = 0x1
	// Position of SOFR field.
	USBFS_INTSTS0_SOFR_Pos = 0xd
	// Bit mask of SOFR field.
	USBFS_INTSTS0_SOFR_Msk = 0x2000
	// Bit SOFR.
	USBFS_INTSTS0_SOFR = 0x2000
	// No SOF interrupt occurred
	USBFS_INTSTS0_SOFR_0 = 0x0
	// SOF interrupt occurred
	USBFS_INTSTS0_SOFR_1 = 0x1
	// Position of RESM field.
	USBFS_INTSTS0_RESM_Pos = 0xe
	// Bit mask of RESM field.
	USBFS_INTSTS0_RESM_Msk = 0x4000
	// Bit RESM.
	USBFS_INTSTS0_RESM = 0x4000
	// No resume interrupt occurred
	USBFS_INTSTS0_RESM_0 = 0x0
	// Resume interrupt occurred
	USBFS_INTSTS0_RESM_1 = 0x1
	// Position of VBINT field.
	USBFS_INTSTS0_VBINT_Pos = 0xf
	// Bit mask of VBINT field.
	USBFS_INTSTS0_VBINT_Msk = 0x8000
	// Bit VBINT.
	USBFS_INTSTS0_VBINT = 0x8000
	// No VBUS interrupt occurred
	USBFS_INTSTS0_VBINT_0 = 0x0
	// VBUS interrupt occurred
	USBFS_INTSTS0_VBINT_1 = 0x1

	// BRDYSTS: BRDY Interrupt Status Register
	// Position of PIPE0BRDY field.
	USBFS_BRDYSTS_PIPE0BRDY_Pos = 0x0
	// Bit mask of PIPE0BRDY field.
	USBFS_BRDYSTS_PIPE0BRDY_Msk = 0x1
	// Bit PIPE0BRDY.
	USBFS_BRDYSTS_PIPE0BRDY = 0x1
	// No BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE0BRDY_0 = 0x0
	// BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE0BRDY_1 = 0x1
	// Position of PIPE4BRDY field.
	USBFS_BRDYSTS_PIPE4BRDY_Pos = 0x4
	// Bit mask of PIPE4BRDY field.
	USBFS_BRDYSTS_PIPE4BRDY_Msk = 0x10
	// Bit PIPE4BRDY.
	USBFS_BRDYSTS_PIPE4BRDY = 0x10
	// No BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE4BRDY_0 = 0x0
	// BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE4BRDY_1 = 0x1
	// Position of PIPE5BRDY field.
	USBFS_BRDYSTS_PIPE5BRDY_Pos = 0x5
	// Bit mask of PIPE5BRDY field.
	USBFS_BRDYSTS_PIPE5BRDY_Msk = 0x20
	// Bit PIPE5BRDY.
	USBFS_BRDYSTS_PIPE5BRDY = 0x20
	// No BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE5BRDY_0 = 0x0
	// BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE5BRDY_1 = 0x1
	// Position of PIPE6BRDY field.
	USBFS_BRDYSTS_PIPE6BRDY_Pos = 0x6
	// Bit mask of PIPE6BRDY field.
	USBFS_BRDYSTS_PIPE6BRDY_Msk = 0x40
	// Bit PIPE6BRDY.
	USBFS_BRDYSTS_PIPE6BRDY = 0x40
	// No BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE6BRDY_0 = 0x0
	// BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE6BRDY_1 = 0x1
	// Position of PIPE7BRDY field.
	USBFS_BRDYSTS_PIPE7BRDY_Pos = 0x7
	// Bit mask of PIPE7BRDY field.
	USBFS_BRDYSTS_PIPE7BRDY_Msk = 0x80
	// Bit PIPE7BRDY.
	USBFS_BRDYSTS_PIPE7BRDY = 0x80
	// No BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE7BRDY_0 = 0x0
	// BRDY interrupt occurred
	USBFS_BRDYSTS_PIPE7BRDY_1 = 0x1

	// NRDYSTS: NRDY Interrupt Status Register
	// Position of PIPE0NRDY field.
	USBFS_NRDYSTS_PIPE0NRDY_Pos = 0x0
	// Bit mask of PIPE0NRDY field.
	USBFS_NRDYSTS_PIPE0NRDY_Msk = 0x1
	// Bit PIPE0NRDY.
	USBFS_NRDYSTS_PIPE0NRDY = 0x1
	// No NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE0NRDY_0 = 0x0
	// NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE0NRDY_1 = 0x1
	// Position of PIPE4NRDY field.
	USBFS_NRDYSTS_PIPE4NRDY_Pos = 0x4
	// Bit mask of PIPE4NRDY field.
	USBFS_NRDYSTS_PIPE4NRDY_Msk = 0x10
	// Bit PIPE4NRDY.
	USBFS_NRDYSTS_PIPE4NRDY = 0x10
	// No NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE4NRDY_0 = 0x0
	// NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE4NRDY_1 = 0x1
	// Position of PIPE5NRDY field.
	USBFS_NRDYSTS_PIPE5NRDY_Pos = 0x5
	// Bit mask of PIPE5NRDY field.
	USBFS_NRDYSTS_PIPE5NRDY_Msk = 0x20
	// Bit PIPE5NRDY.
	USBFS_NRDYSTS_PIPE5NRDY = 0x20
	// No NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE5NRDY_0 = 0x0
	// NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE5NRDY_1 = 0x1
	// Position of PIPE6NRDY field.
	USBFS_NRDYSTS_PIPE6NRDY_Pos = 0x6
	// Bit mask of PIPE6NRDY field.
	USBFS_NRDYSTS_PIPE6NRDY_Msk = 0x40
	// Bit PIPE6NRDY.
	USBFS_NRDYSTS_PIPE6NRDY = 0x40
	// No NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE6NRDY_0 = 0x0
	// NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE6NRDY_1 = 0x1
	// Position of PIPE7NRDY field.
	USBFS_NRDYSTS_PIPE7NRDY_Pos = 0x7
	// Bit mask of PIPE7NRDY field.
	USBFS_NRDYSTS_PIPE7NRDY_Msk = 0x80
	// Bit PIPE7NRDY.
	USBFS_NRDYSTS_PIPE7NRDY = 0x80
	// No NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE7NRDY_0 = 0x0
	// NRDY interrupt occurred
	USBFS_NRDYSTS_PIPE7NRDY_1 = 0x1

	// BEMPSTS: BEMP Interrupt Status Register
	// Position of PIPE0BEMP field.
	USBFS_BEMPSTS_PIPE0BEMP_Pos = 0x0
	// Bit mask of PIPE0BEMP field.
	USBFS_BEMPSTS_PIPE0BEMP_Msk = 0x1
	// Bit PIPE0BEMP.
	USBFS_BEMPSTS_PIPE0BEMP = 0x1
	// No BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE0BEMP_0 = 0x0
	// BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE0BEMP_1 = 0x1
	// Position of PIPE4BEMP field.
	USBFS_BEMPSTS_PIPE4BEMP_Pos = 0x4
	// Bit mask of PIPE4BEMP field.
	USBFS_BEMPSTS_PIPE4BEMP_Msk = 0x10
	// Bit PIPE4BEMP.
	USBFS_BEMPSTS_PIPE4BEMP = 0x10
	// No BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE4BEMP_0 = 0x0
	// BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE4BEMP_1 = 0x1
	// Position of PIPE5BEMP field.
	USBFS_BEMPSTS_PIPE5BEMP_Pos = 0x5
	// Bit mask of PIPE5BEMP field.
	USBFS_BEMPSTS_PIPE5BEMP_Msk = 0x20
	// Bit PIPE5BEMP.
	USBFS_BEMPSTS_PIPE5BEMP = 0x20
	// No BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE5BEMP_0 = 0x0
	// BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE5BEMP_1 = 0x1
	// Position of PIPE6BEMP field.
	USBFS_BEMPSTS_PIPE6BEMP_Pos = 0x6
	// Bit mask of PIPE6BEMP field.
	USBFS_BEMPSTS_PIPE6BEMP_Msk = 0x40
	// Bit PIPE6BEMP.
	USBFS_BEMPSTS_PIPE6BEMP = 0x40
	// No BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE6BEMP_0 = 0x0
	// BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE6BEMP_1 = 0x1
	// Position of PIPE7BEMP field.
	USBFS_BEMPSTS_PIPE7BEMP_Pos = 0x7
	// Bit mask of PIPE7BEMP field.
	USBFS_BEMPSTS_PIPE7BEMP_Msk = 0x80
	// Bit PIPE7BEMP.
	USBFS_BEMPSTS_PIPE7BEMP = 0x80
	// No BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE7BEMP_0 = 0x0
	// BEMP interrupt occurred
	USBFS_BEMPSTS_PIPE7BEMP_1 = 0x1

	// FRMNUM: Frame Number Register
	// Position of FRNM field.
	USBFS_FRMNUM_FRNM_Pos = 0x0
	// Bit mask of FRNM field.
	USBFS_FRMNUM_FRNM_Msk = 0x7ff

	// DVCHGR: Device State Change Register
	// Position of DVCHG field.
	USBFS_DVCHGR_DVCHG_Pos = 0xf
	// Bit mask of DVCHG field.
	USBFS_DVCHGR_DVCHG_Msk = 0x8000
	// Bit DVCHG.
	USBFS_DVCHGR_DVCHG = 0x8000
	// Disable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits
	USBFS_DVCHGR_DVCHG_0 = 0x0
	// Enable writes to the USBADDR.STSRECOV[3:0] and USBADDR.USBADDR[6:0] bits
	USBFS_DVCHGR_DVCHG_1 = 0x1

	// USBADDR: USB Address Register
	// Position of USBADDR field.
	USBFS_USBADDR_USBADDR_Pos = 0x0
	// Bit mask of USBADDR field.
	USBFS_USBADDR_USBADDR_Msk = 0x7f
	// Position of STSRECOV field.
	USBFS_USBADDR_STSRECOV_Pos = 0x8
	// Bit mask of STSRECOV field.
	USBFS_USBADDR_STSRECOV_Msk = 0xf00
	// Setting prohibited
	USBFS_USBADDR_STSRECOV_Others = 0x0
	// Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 001b (default state)
	USBFS_USBADDR_STSRECOV_0x9 = 0x9
	// Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 010b (address state)
	USBFS_USBADDR_STSRECOV_0xA = 0xa
	// Return to the full-speed state (bits DVSTCTR0.RHST[2:0] = 010b), bits INTSTS0.DVSQ[2:0] = 011b (configured state)
	USBFS_USBADDR_STSRECOV_0xB = 0xb

	// USBREQ: USB Request Type Register
	// Position of BMREQUESTTYPE field.
	USBFS_USBREQ_BMREQUESTTYPE_Pos = 0x0
	// Bit mask of BMREQUESTTYPE field.
	USBFS_USBREQ_BMREQUESTTYPE_Msk = 0xff
	// Position of BREQUEST field.
	USBFS_USBREQ_BREQUEST_Pos = 0x8
	// Bit mask of BREQUEST field.
	USBFS_USBREQ_BREQUEST_Msk = 0xff00

	// USBVAL: USB Request Value Register
	// Position of WVALUE field.
	USBFS_USBVAL_WVALUE_Pos = 0x0
	// Bit mask of WVALUE field.
	USBFS_USBVAL_WVALUE_Msk = 0xffff

	// USBINDX: USB Request Index Register
	// Position of WINDEX field.
	USBFS_USBINDX_WINDEX_Pos = 0x0
	// Bit mask of WINDEX field.
	USBFS_USBINDX_WINDEX_Msk = 0xffff

	// USBLENG: USB Request Length Register
	// Position of WLENTUH field.
	USBFS_USBLENG_WLENTUH_Pos = 0x0
	// Bit mask of WLENTUH field.
	USBFS_USBLENG_WLENTUH_Msk = 0xffff

	// DCPCFG: DCP Configuration Register
	// Position of SHTNAK field.
	USBFS_DCPCFG_SHTNAK_Pos = 0x7
	// Bit mask of SHTNAK field.
	USBFS_DCPCFG_SHTNAK_Msk = 0x80
	// Bit SHTNAK.
	USBFS_DCPCFG_SHTNAK = 0x80
	// Keep pipe open after transfer ends
	USBFS_DCPCFG_SHTNAK_0 = 0x0
	// Disable pipe after transfer ends
	USBFS_DCPCFG_SHTNAK_1 = 0x1

	// DCPMAXP: DCP Maximum Packet Size Register
	// Position of MXPS field.
	USBFS_DCPMAXP_MXPS_Pos = 0x0
	// Bit mask of MXPS field.
	USBFS_DCPMAXP_MXPS_Msk = 0x7f

	// DCPCTR: DCP Control Register
	// Position of PID field.
	USBFS_DCPCTR_PID_Pos = 0x0
	// Bit mask of PID field.
	USBFS_DCPCTR_PID_Msk = 0x3
	// NAK response
	USBFS_DCPCTR_PID_00 = 0x0
	// BUF response (depends on the buffer state)
	USBFS_DCPCTR_PID_01 = 0x1
	// STALL response
	USBFS_DCPCTR_PID_10 = 0x2
	// STALL response
	USBFS_DCPCTR_PID_11 = 0x3
	// Position of CCPL field.
	USBFS_DCPCTR_CCPL_Pos = 0x2
	// Bit mask of CCPL field.
	USBFS_DCPCTR_CCPL_Msk = 0x4
	// Bit CCPL.
	USBFS_DCPCTR_CCPL = 0x4
	// Disable control transfer completion
	USBFS_DCPCTR_CCPL_0 = 0x0
	// Enable control transfer completion
	USBFS_DCPCTR_CCPL_1 = 0x1
	// Position of PBUSY field.
	USBFS_DCPCTR_PBUSY_Pos = 0x5
	// Bit mask of PBUSY field.
	USBFS_DCPCTR_PBUSY_Msk = 0x20
	// Bit PBUSY.
	USBFS_DCPCTR_PBUSY = 0x20
	// DCP not used for the USB bus
	USBFS_DCPCTR_PBUSY_0 = 0x0
	// DCP in use for the USB bus
	USBFS_DCPCTR_PBUSY_1 = 0x1
	// Position of SQMON field.
	USBFS_DCPCTR_SQMON_Pos = 0x6
	// Bit mask of SQMON field.
	USBFS_DCPCTR_SQMON_Msk = 0x40
	// Bit SQMON.
	USBFS_DCPCTR_SQMON = 0x40
	// DATA0
	USBFS_DCPCTR_SQMON_0 = 0x0
	// ATA1
	USBFS_DCPCTR_SQMON_1 = 0x1
	// Position of SQSET field.
	USBFS_DCPCTR_SQSET_Pos = 0x7
	// Bit mask of SQSET field.
	USBFS_DCPCTR_SQSET_Msk = 0x80
	// Bit SQSET.
	USBFS_DCPCTR_SQSET = 0x80
	// Invalid (writing 0 has no effect)
	USBFS_DCPCTR_SQSET_0 = 0x0
	// Set the expected value for the next transaction to DATA1
	USBFS_DCPCTR_SQSET_1 = 0x1
	// Position of SQCLR field.
	USBFS_DCPCTR_SQCLR_Pos = 0x8
	// Bit mask of SQCLR field.
	USBFS_DCPCTR_SQCLR_Msk = 0x100
	// Bit SQCLR.
	USBFS_DCPCTR_SQCLR = 0x100
	// Invalid (writing 0 has no effect)
	USBFS_DCPCTR_SQCLR_0 = 0x0
	// Clear the expected value for the next transaction to DATA0
	USBFS_DCPCTR_SQCLR_1 = 0x1
	// Position of BSTS field.
	USBFS_DCPCTR_BSTS_Pos = 0xf
	// Bit mask of BSTS field.
	USBFS_DCPCTR_BSTS_Msk = 0x8000
	// Bit BSTS.
	USBFS_DCPCTR_BSTS = 0x8000
	// Buffer access disabled
	USBFS_DCPCTR_BSTS_0 = 0x0
	// Buffer access enabled
	USBFS_DCPCTR_BSTS_1 = 0x1

	// PIPESEL: Pipe Window Select Register
	// Position of PIPESEL field.
	USBFS_PIPESEL_PIPESEL_Pos = 0x0
	// Bit mask of PIPESEL field.
	USBFS_PIPESEL_PIPESEL_Msk = 0xf
	// No pipe selected
	USBFS_PIPESEL_PIPESEL_0x0 = 0x0
	// Pipe 4
	USBFS_PIPESEL_PIPESEL_0x4 = 0x4
	// Pipe 5
	USBFS_PIPESEL_PIPESEL_0x5 = 0x5
	// Pipe 6
	USBFS_PIPESEL_PIPESEL_0x6 = 0x6
	// Pipe 7
	USBFS_PIPESEL_PIPESEL_0x7 = 0x7
	// Setting prohibited
	USBFS_PIPESEL_PIPESEL_Others = 0x8

	// PIPECFG: Pipe Configuration Register
	// Position of EPNUM field.
	USBFS_PIPECFG_EPNUM_Pos = 0x0
	// Bit mask of EPNUM field.
	USBFS_PIPECFG_EPNUM_Msk = 0xf
	// Position of DIR field.
	USBFS_PIPECFG_DIR_Pos = 0x4
	// Bit mask of DIR field.
	USBFS_PIPECFG_DIR_Msk = 0x10
	// Bit DIR.
	USBFS_PIPECFG_DIR = 0x10
	// Receiving direction
	USBFS_PIPECFG_DIR_0 = 0x0
	// Transmitting direction
	USBFS_PIPECFG_DIR_1 = 0x1
	// Position of SHTNAK field.
	USBFS_PIPECFG_SHTNAK_Pos = 0x7
	// Bit mask of SHTNAK field.
	USBFS_PIPECFG_SHTNAK_Msk = 0x80
	// Bit SHTNAK.
	USBFS_PIPECFG_SHTNAK = 0x80
	// Continue pipe operation after transfer ends
	USBFS_PIPECFG_SHTNAK_0 = 0x0
	// Disable pipe after transfer ends
	USBFS_PIPECFG_SHTNAK_1 = 0x1
	// Position of DBLB field.
	USBFS_PIPECFG_DBLB_Pos = 0x9
	// Bit mask of DBLB field.
	USBFS_PIPECFG_DBLB_Msk = 0x200
	// Bit DBLB.
	USBFS_PIPECFG_DBLB = 0x200
	// Single buffer
	USBFS_PIPECFG_DBLB_0 = 0x0
	// Double buffer
	USBFS_PIPECFG_DBLB_1 = 0x1
	// Position of BFRE field.
	USBFS_PIPECFG_BFRE_Pos = 0xa
	// Bit mask of BFRE field.
	USBFS_PIPECFG_BFRE_Msk = 0x400
	// Bit BFRE.
	USBFS_PIPECFG_BFRE = 0x400
	// Generate BRDY interrupt on transmitting or receiving data
	USBFS_PIPECFG_BFRE_0 = 0x0
	// Generate BRDY interrupt on completion of reading data
	USBFS_PIPECFG_BFRE_1 = 0x1
	// Position of TYPE field.
	USBFS_PIPECFG_TYPE_Pos = 0xe
	// Bit mask of TYPE field.
	USBFS_PIPECFG_TYPE_Msk = 0xc000
	// Pipe not used
	USBFS_PIPECFG_TYPE_00 = 0x0
	// Pipes 4 and 5: Bulk transfer Pipes 6 and 7: Setting prohibited
	USBFS_PIPECFG_TYPE_01 = 0x1
	// Pipes 4 and 5: Setting prohibited Pipes 6 and 7: Interrupt transfer
	USBFS_PIPECFG_TYPE_10 = 0x2
	// Pipes 4 and 5: Setting prohibited Pipes 6 and 7: Setting prohibited
	USBFS_PIPECFG_TYPE_11 = 0x3

	// PIPEMAXP: Pipe Maximum Packet Size Register
	// Position of MXPS field.
	USBFS_PIPEMAXP_MXPS_Pos = 0x0
	// Bit mask of MXPS field.
	USBFS_PIPEMAXP_MXPS_Msk = 0x1ff

	// PIPE4CTR: PIPE%s Control Registers
	// Position of PID field.
	USBFS_PIPECTR_PID_Pos = 0x0
	// Bit mask of PID field.
	USBFS_PIPECTR_PID_Msk = 0x3
	// NAK response
	USBFS_PIPECTR_PID_00 = 0x0
	// BUF response (depends buffer state)
	USBFS_PIPECTR_PID_01 = 0x1
	// STALL response
	USBFS_PIPECTR_PID_10 = 0x2
	// STALL response
	USBFS_PIPECTR_PID_11 = 0x3
	// Position of PBUSY field.
	USBFS_PIPECTR_PBUSY_Pos = 0x5
	// Bit mask of PBUSY field.
	USBFS_PIPECTR_PBUSY_Msk = 0x20
	// Bit PBUSY.
	USBFS_PIPECTR_PBUSY = 0x20
	// Pipe n not in use for the transaction
	USBFS_PIPECTR_PBUSY_0 = 0x0
	// Pipe n in use for the transaction
	USBFS_PIPECTR_PBUSY_1 = 0x1
	// Position of SQMON field.
	USBFS_PIPECTR_SQMON_Pos = 0x6
	// Bit mask of SQMON field.
	USBFS_PIPECTR_SQMON_Msk = 0x40
	// Bit SQMON.
	USBFS_PIPECTR_SQMON = 0x40
	// DATA0
	USBFS_PIPECTR_SQMON_0 = 0x0
	// DATA1
	USBFS_PIPECTR_SQMON_1 = 0x1
	// Position of SQSET field.
	USBFS_PIPECTR_SQSET_Pos = 0x7
	// Bit mask of SQSET field.
	USBFS_PIPECTR_SQSET_Msk = 0x80
	// Bit SQSET.
	USBFS_PIPECTR_SQSET = 0x80
	// Invalid (writing 0 has no effect)
	USBFS_PIPECTR_SQSET_0 = 0x0
	// Set the expected value for the next transaction to DATA1
	USBFS_PIPECTR_SQSET_1 = 0x1
	// Position of SQCLR field.
	USBFS_PIPECTR_SQCLR_Pos = 0x8
	// Bit mask of SQCLR field.
	USBFS_PIPECTR_SQCLR_Msk = 0x100
	// Bit SQCLR.
	USBFS_PIPECTR_SQCLR = 0x100
	// Invalid (writing 0 has no effect)
	USBFS_PIPECTR_SQCLR_0 = 0x0
	// Clear the expected value for the next transaction to DATA0
	USBFS_PIPECTR_SQCLR_1 = 0x1
	// Position of ACLRM field.
	USBFS_PIPECTR_ACLRM_Pos = 0x9
	// Bit mask of ACLRM field.
	USBFS_PIPECTR_ACLRM_Msk = 0x200
	// Bit ACLRM.
	USBFS_PIPECTR_ACLRM = 0x200
	// Disable
	USBFS_PIPECTR_ACLRM_0 = 0x0
	// Enable (initialize all buffers)
	USBFS_PIPECTR_ACLRM_1 = 0x1
	// Position of ATREPM field.
	USBFS_PIPECTR_ATREPM_Pos = 0xa
	// Bit mask of ATREPM field.
	USBFS_PIPECTR_ATREPM_Msk = 0x400
	// Bit ATREPM.
	USBFS_PIPECTR_ATREPM = 0x400
	// Disable auto response mode
	USBFS_PIPECTR_ATREPM_0 = 0x0
	// Enable auto response mode
	USBFS_PIPECTR_ATREPM_1 = 0x1
	// Position of INBUFM field.
	USBFS_PIPECTR_INBUFM_Pos = 0xe
	// Bit mask of INBUFM field.
	USBFS_PIPECTR_INBUFM_Msk = 0x4000
	// Bit INBUFM.
	USBFS_PIPECTR_INBUFM = 0x4000
	// No data to be transmitted is in the FIFO buffer
	USBFS_PIPECTR_INBUFM_0 = 0x0
	// Data to be transmitted is in the FIFO buffer
	USBFS_PIPECTR_INBUFM_1 = 0x1
	// Position of BSTS field.
	USBFS_PIPECTR_BSTS_Pos = 0xf
	// Bit mask of BSTS field.
	USBFS_PIPECTR_BSTS_Msk = 0x8000
	// Bit BSTS.
	USBFS_PIPECTR_BSTS = 0x8000
	// Buffer access by the CPU disabled
	USBFS_PIPECTR_BSTS_0 = 0x0
	// Buffer access by the CPU enabled
	USBFS_PIPECTR_BSTS_1 = 0x1

	// PIPE6CTR: PIPE%s Control Registers
	// Position of PID field.
	USBFS_PIPECTR_PID_Pos = 0x0
	// Bit mask of PID field.
	USBFS_PIPECTR_PID_Msk = 0x3
	// NAK response
	USBFS_PIPECTR_PID_00 = 0x0
	// BUF response (depends buffer state)
	USBFS_PIPECTR_PID_01 = 0x1
	// STALL response
	USBFS_PIPECTR_PID_10 = 0x2
	// STALL response
	USBFS_PIPECTR_PID_11 = 0x3
	// Position of PBUSY field.
	USBFS_PIPECTR_PBUSY_Pos = 0x5
	// Bit mask of PBUSY field.
	USBFS_PIPECTR_PBUSY_Msk = 0x20
	// Bit PBUSY.
	USBFS_PIPECTR_PBUSY = 0x20
	// Pipe n not in use for the transaction
	USBFS_PIPECTR_PBUSY_0 = 0x0
	// Pipe n in use for the transaction
	USBFS_PIPECTR_PBUSY_1 = 0x1
	// Position of SQMON field.
	USBFS_PIPECTR_SQMON_Pos = 0x6
	// Bit mask of SQMON field.
	USBFS_PIPECTR_SQMON_Msk = 0x40
	// Bit SQMON.
	USBFS_PIPECTR_SQMON = 0x40
	// DATA0
	USBFS_PIPECTR_SQMON_0 = 0x0
	// DATA1
	USBFS_PIPECTR_SQMON_1 = 0x1
	// Position of SQSET field.
	USBFS_PIPECTR_SQSET_Pos = 0x7
	// Bit mask of SQSET field.
	USBFS_PIPECTR_SQSET_Msk = 0x80
	// Bit SQSET.
	USBFS_PIPECTR_SQSET = 0x80
	// Invalid (writing 0 has no effect)
	USBFS_PIPECTR_SQSET_0 = 0x0
	// Set the expected value for the next transaction to DATA0
	USBFS_PIPECTR_SQSET_1 = 0x1
	// Position of SQCLR field.
	USBFS_PIPECTR_SQCLR_Pos = 0x8
	// Bit mask of SQCLR field.
	USBFS_PIPECTR_SQCLR_Msk = 0x100
	// Bit SQCLR.
	USBFS_PIPECTR_SQCLR = 0x100
	// Invalid (writing 0 has no effect)
	USBFS_PIPECTR_SQCLR_0 = 0x0
	// Clear the expected value for the next transaction to DATA0
	USBFS_PIPECTR_SQCLR_1 = 0x1
	// Position of ACLRM field.
	USBFS_PIPECTR_ACLRM_Pos = 0x9
	// Bit mask of ACLRM field.
	USBFS_PIPECTR_ACLRM_Msk = 0x200
	// Bit ACLRM.
	USBFS_PIPECTR_ACLRM = 0x200
	// Disable
	USBFS_PIPECTR_ACLRM_0 = 0x0
	// Enable (all buffers initialized)
	USBFS_PIPECTR_ACLRM_1 = 0x1
	// Position of BSTS field.
	USBFS_PIPECTR_BSTS_Pos = 0xf
	// Bit mask of BSTS field.
	USBFS_PIPECTR_BSTS_Msk = 0x8000
	// Bit BSTS.
	USBFS_PIPECTR_BSTS = 0x8000
	// Buffer access disabled
	USBFS_PIPECTR_BSTS_0 = 0x0
	// Buffer access enabled
	USBFS_PIPECTR_BSTS_1 = 0x1

	// PIPE4TRE: PIPE%s Transaction Counter Enable Register
	// Position of TRCLR field.
	USBFS_PIPETRE_TRCLR_Pos = 0x8
	// Bit mask of TRCLR field.
	USBFS_PIPETRE_TRCLR_Msk = 0x100
	// Bit TRCLR.
	USBFS_PIPETRE_TRCLR = 0x100
	// Invalid (writing 0 has no effect)
	USBFS_PIPETRE_TRCLR_0 = 0x0
	// Clear counter value
	USBFS_PIPETRE_TRCLR_1 = 0x1
	// Position of TRENB field.
	USBFS_PIPETRE_TRENB_Pos = 0x9
	// Bit mask of TRENB field.
	USBFS_PIPETRE_TRENB_Msk = 0x200
	// Bit TRENB.
	USBFS_PIPETRE_TRENB = 0x200
	// Disable transaction counter
	USBFS_PIPETRE_TRENB_0 = 0x0
	// Enable transaction counter
	USBFS_PIPETRE_TRENB_1 = 0x1

	// PIPE4TRN: PIPE%s Transaction Counter Register
	// Position of TRNCNT field.
	USBFS_PIPETRN_TRNCNT_Pos = 0x0
	// Bit mask of TRNCNT field.
	USBFS_PIPETRN_TRNCNT_Msk = 0xffff

	// PHYSECTRL: PHY Single-ended Receiver Control Register
	// Position of CNEN field.
	USBFS_PHYSECTRL_CNEN_Pos = 0x4
	// Bit mask of CNEN field.
	USBFS_PHYSECTRL_CNEN_Msk = 0x10
	// Bit CNEN.
	USBFS_PHYSECTRL_CNEN = 0x10
	// Single-ended receiver operation is disabled
	USBFS_PHYSECTRL_CNEN_0 = 0x0
	// Single-ended receiver operation is enabled
	USBFS_PHYSECTRL_CNEN_1 = 0x1

	// DPUSR0R: Deep Software Standby USB Transceiver Control/Pin Monitor Register
	// Position of SRPC0 field.
	USBFS_DPUSR0R_SRPC0_Pos = 0x0
	// Bit mask of SRPC0 field.
	USBFS_DPUSR0R_SRPC0_Msk = 0x1
	// Bit SRPC0.
	USBFS_DPUSR0R_SRPC0 = 0x1
	// Disable input through DP and DM inputs
	USBFS_DPUSR0R_SRPC0_0 = 0x0
	// Enable input through DP and DM inputs
	USBFS_DPUSR0R_SRPC0_1 = 0x1
	// Position of RPUE0 field.
	USBFS_DPUSR0R_RPUE0_Pos = 0x1
	// Bit mask of RPUE0 field.
	USBFS_DPUSR0R_RPUE0_Msk = 0x2
	// Bit RPUE0.
	USBFS_DPUSR0R_RPUE0 = 0x2
	// Disable DP pull-up resistor
	USBFS_DPUSR0R_RPUE0_0 = 0x0
	// Enable DP pull-up resistor
	USBFS_DPUSR0R_RPUE0_1 = 0x1
	// Position of FIXPHY0 field.
	USBFS_DPUSR0R_FIXPHY0_Pos = 0x4
	// Bit mask of FIXPHY0 field.
	USBFS_DPUSR0R_FIXPHY0_Msk = 0x10
	// Bit FIXPHY0.
	USBFS_DPUSR0R_FIXPHY0 = 0x10
	// Fix outputs in Normal mode and on return from Deep Software Standby mode
	USBFS_DPUSR0R_FIXPHY0_0 = 0x0
	// Fix outputs on transition to Deep Software Standby mode
	USBFS_DPUSR0R_FIXPHY0_1 = 0x1
	// Position of DP0 field.
	USBFS_DPUSR0R_DP0_Pos = 0x10
	// Bit mask of DP0 field.
	USBFS_DPUSR0R_DP0_Msk = 0x10000
	// Bit DP0.
	USBFS_DPUSR0R_DP0 = 0x10000
	// Position of DM0 field.
	USBFS_DPUSR0R_DM0_Pos = 0x11
	// Bit mask of DM0 field.
	USBFS_DPUSR0R_DM0_Msk = 0x20000
	// Bit DM0.
	USBFS_DPUSR0R_DM0 = 0x20000
	// Position of DVBSTS0 field.
	USBFS_DPUSR0R_DVBSTS0_Pos = 0x17
	// Bit mask of DVBSTS0 field.
	USBFS_DPUSR0R_DVBSTS0_Msk = 0x800000
	// Bit DVBSTS0.
	USBFS_DPUSR0R_DVBSTS0 = 0x800000

	// DPUSR1R: Deep Software Standby USB Suspend/Resume Interrupt Register
	// Position of DPINTE0 field.
	USBFS_DPUSR1R_DPINTE0_Pos = 0x0
	// Bit mask of DPINTE0 field.
	USBFS_DPUSR1R_DPINTE0_Msk = 0x1
	// Bit DPINTE0.
	USBFS_DPUSR1R_DPINTE0 = 0x1
	// Disable recovery from Deep Software Standby mode by DP input
	USBFS_DPUSR1R_DPINTE0_0 = 0x0
	// Enable recovery from Deep Software Standby mode by DP input
	USBFS_DPUSR1R_DPINTE0_1 = 0x1
	// Position of DMINTE0 field.
	USBFS_DPUSR1R_DMINTE0_Pos = 0x1
	// Bit mask of DMINTE0 field.
	USBFS_DPUSR1R_DMINTE0_Msk = 0x2
	// Bit DMINTE0.
	USBFS_DPUSR1R_DMINTE0 = 0x2
	// Disable recovery from Deep Software Standby mode by DM input
	USBFS_DPUSR1R_DMINTE0_0 = 0x0
	// Enable recovery from Deep Software Standby mode by DM input
	USBFS_DPUSR1R_DMINTE0_1 = 0x1
	// Position of DVBSE0 field.
	USBFS_DPUSR1R_DVBSE0_Pos = 0x7
	// Bit mask of DVBSE0 field.
	USBFS_DPUSR1R_DVBSE0_Msk = 0x80
	// Bit DVBSE0.
	USBFS_DPUSR1R_DVBSE0 = 0x80
	// Disable recovery from Deep Software Standby mode by VBUS input
	USBFS_DPUSR1R_DVBSE0_0 = 0x0
	// Enable recovery from Deep Software Standby mode by VBUS input
	USBFS_DPUSR1R_DVBSE0_1 = 0x1
	// Position of DPINT0 field.
	USBFS_DPUSR1R_DPINT0_Pos = 0x10
	// Bit mask of DPINT0 field.
	USBFS_DPUSR1R_DPINT0_Msk = 0x10000
	// Bit DPINT0.
	USBFS_DPUSR1R_DPINT0 = 0x10000
	// System has not recovered from Deep Software Standby mode
	USBFS_DPUSR1R_DPINT0_0 = 0x0
	// System recovered from Deep Software Standby mode because of DP
	USBFS_DPUSR1R_DPINT0_1 = 0x1
	// Position of DMINT0 field.
	USBFS_DPUSR1R_DMINT0_Pos = 0x11
	// Bit mask of DMINT0 field.
	USBFS_DPUSR1R_DMINT0_Msk = 0x20000
	// Bit DMINT0.
	USBFS_DPUSR1R_DMINT0 = 0x20000
	// System has not recovered from Deep Software Standby mode
	USBFS_DPUSR1R_DMINT0_0 = 0x0
	// System recovered from Deep Software Standby mode because of DM input
	USBFS_DPUSR1R_DMINT0_1 = 0x1
	// Position of DVBINT0 field.
	USBFS_DPUSR1R_DVBINT0_Pos = 0x17
	// Bit mask of DVBINT0 field.
	USBFS_DPUSR1R_DVBINT0_Msk = 0x800000
	// Bit DVBINT0.
	USBFS_DPUSR1R_DVBINT0 = 0x800000
	// System has not recovered from Deep Software Standby mode
	USBFS_DPUSR1R_DVBINT0_0 = 0x0
	// System recovered from Deep Software Standby mode because of VBUS input
	USBFS_DPUSR1R_DVBINT0_1 = 0x1
)

// Constants for SSIE0: Serial Sound Interface Enhanced (SSIE)
const (
	// SSICR: Control Register
	// Position of REN field.
	SSIE0_SSICR_REN_Pos = 0x0
	// Bit mask of REN field.
	SSIE0_SSICR_REN_Msk = 0x1
	// Bit REN.
	SSIE0_SSICR_REN = 0x1
	// Disables reception
	SSIE0_SSICR_REN_0 = 0x0
	// Enables reception (starts reception)
	SSIE0_SSICR_REN_1 = 0x1
	// Position of TEN field.
	SSIE0_SSICR_TEN_Pos = 0x1
	// Bit mask of TEN field.
	SSIE0_SSICR_TEN_Msk = 0x2
	// Bit TEN.
	SSIE0_SSICR_TEN = 0x2
	// Disables transmission
	SSIE0_SSICR_TEN_0 = 0x0
	// Enables transmission (starts transmission)
	SSIE0_SSICR_TEN_1 = 0x1
	// Position of MUEN field.
	SSIE0_SSICR_MUEN_Pos = 0x3
	// Bit mask of MUEN field.
	SSIE0_SSICR_MUEN_Msk = 0x8
	// Bit MUEN.
	SSIE0_SSICR_MUEN = 0x8
	// Disables muting on the next frame boundary
	SSIE0_SSICR_MUEN_0 = 0x0
	// Enables muting on the next frame boundary
	SSIE0_SSICR_MUEN_1 = 0x1
	// Position of CKDV field.
	SSIE0_SSICR_CKDV_Pos = 0x4
	// Bit mask of CKDV field.
	SSIE0_SSICR_CKDV_Msk = 0xf0
	// AUDIO_MCK
	SSIE0_SSICR_CKDV_0x0 = 0x0
	// AUDIO_MCK/2
	SSIE0_SSICR_CKDV_0x1 = 0x1
	// AUDIO_MCK/4
	SSIE0_SSICR_CKDV_0x2 = 0x2
	// AUDIO_MCK/8
	SSIE0_SSICR_CKDV_0x3 = 0x3
	// AUDIO_MCK/16
	SSIE0_SSICR_CKDV_0x4 = 0x4
	// AUDIO_MCK/32
	SSIE0_SSICR_CKDV_0x5 = 0x5
	// AUDIO_MCK/64
	SSIE0_SSICR_CKDV_0x6 = 0x6
	// AUDIO_MCK/128
	SSIE0_SSICR_CKDV_0x7 = 0x7
	// AUDIO_MCK/6
	SSIE0_SSICR_CKDV_0x8 = 0x8
	// AUDIO_MCK/12
	SSIE0_SSICR_CKDV_0x9 = 0x9
	// AUDIO_MCK/24
	SSIE0_SSICR_CKDV_0xA = 0xa
	// AUDIO_MCK/48
	SSIE0_SSICR_CKDV_0xB = 0xb
	// AUDIO_MCK/96
	SSIE0_SSICR_CKDV_0xC = 0xc
	// Setting prohibited
	SSIE0_SSICR_CKDV_Others = 0xd
	// Position of DEL field.
	SSIE0_SSICR_DEL_Pos = 0x8
	// Bit mask of DEL field.
	SSIE0_SSICR_DEL_Msk = 0x100
	// Bit DEL.
	SSIE0_SSICR_DEL = 0x100
	// Delay of 1 cycle of SSIBCK between SSILRCK/SSIFS and SSITXD0/SSIRXD0/SSIDATA0
	SSIE0_SSICR_DEL_0 = 0x0
	// No delay between SSILRCK/SSIFS and SSITXD0/SSIRXD0/SSIDATA0
	SSIE0_SSICR_DEL_1 = 0x1
	// Position of PDTA field.
	SSIE0_SSICR_PDTA_Pos = 0x9
	// Bit mask of PDTA field.
	SSIE0_SSICR_PDTA_Msk = 0x200
	// Bit PDTA.
	SSIE0_SSICR_PDTA = 0x200
	// Left-justifies placement data (SSIFTDR, SSIFRDR)
	SSIE0_SSICR_PDTA_0 = 0x0
	// Right-justifies placement data (SSIFTDR, SSIFRDR)
	SSIE0_SSICR_PDTA_1 = 0x1
	// Position of SDTA field.
	SSIE0_SSICR_SDTA_Pos = 0xa
	// Bit mask of SDTA field.
	SSIE0_SSICR_SDTA_Msk = 0x400
	// Bit SDTA.
	SSIE0_SSICR_SDTA = 0x400
	// Transmits and receives serial data first and then padding bits
	SSIE0_SSICR_SDTA_0 = 0x0
	// Transmit and receives padding bits first and then serial data
	SSIE0_SSICR_SDTA_1 = 0x1
	// Position of SPDP field.
	SSIE0_SSICR_SPDP_Pos = 0xb
	// Bit mask of SPDP field.
	SSIE0_SSICR_SPDP_Msk = 0x800
	// Bit SPDP.
	SSIE0_SSICR_SPDP = 0x800
	// Padding data is at a low level
	SSIE0_SSICR_SPDP_0 = 0x0
	// Padding data is at a high level
	SSIE0_SSICR_SPDP_1 = 0x1
	// Position of LRCKP field.
	SSIE0_SSICR_LRCKP_Pos = 0xc
	// Bit mask of LRCKP field.
	SSIE0_SSICR_LRCKP_Msk = 0x1000
	// Bit LRCKP.
	SSIE0_SSICR_LRCKP = 0x1000
	// The initial value is at a high level. The start trigger for a frame is synchronized with a falling edge of SSILRCK/SSIFS.
	SSIE0_SSICR_LRCKP_0 = 0x0
	// The initial value is at a low level. The start trigger for a frame is synchronized with a rising edge of SSILRCK/SSIFS.
	SSIE0_SSICR_LRCKP_1 = 0x1
	// Position of BCKP field.
	SSIE0_SSICR_BCKP_Pos = 0xd
	// Bit mask of BCKP field.
	SSIE0_SSICR_BCKP_Msk = 0x2000
	// Bit BCKP.
	SSIE0_SSICR_BCKP = 0x2000
	// SSILRCK/SSIFS and SSITXD0/SSIRXD0/SSIDATA0 change at a falling edge (SSILRCK/SSIFS and SSIRXD0/SSIDATA0 are sampled at a rising edge of SSIBCK).
	SSIE0_SSICR_BCKP_0 = 0x0
	// SSILRCK/SSIFS and SSITXD0/SSIRXD0/SSIDATA0 change at a rising edge (SSILRCK/SSIFS and SSIRXD0/SSIDATA0 are sampled at a falling edge of SSIBCK).
	SSIE0_SSICR_BCKP_1 = 0x1
	// Position of MST field.
	SSIE0_SSICR_MST_Pos = 0xe
	// Bit mask of MST field.
	SSIE0_SSICR_MST_Msk = 0x4000
	// Bit MST.
	SSIE0_SSICR_MST = 0x4000
	// Slave-mode communication
	SSIE0_SSICR_MST_0 = 0x0
	// Master-mode communication
	SSIE0_SSICR_MST_1 = 0x1
	// Position of SWL field.
	SSIE0_SSICR_SWL_Pos = 0x10
	// Bit mask of SWL field.
	SSIE0_SSICR_SWL_Msk = 0x70000
	// 8 bits
	SSIE0_SSICR_SWL_000 = 0x0
	// 16 bits
	SSIE0_SSICR_SWL_001 = 0x1
	// 24 bits
	SSIE0_SSICR_SWL_010 = 0x2
	// 32 bits
	SSIE0_SSICR_SWL_011 = 0x3
	// 48 bits
	SSIE0_SSICR_SWL_100 = 0x4
	// 64 bits
	SSIE0_SSICR_SWL_101 = 0x5
	// 128 bits
	SSIE0_SSICR_SWL_110 = 0x6
	// 256 bits
	SSIE0_SSICR_SWL_111 = 0x7
	// Position of DWL field.
	SSIE0_SSICR_DWL_Pos = 0x13
	// Bit mask of DWL field.
	SSIE0_SSICR_DWL_Msk = 0x380000
	// 8 bits
	SSIE0_SSICR_DWL_000 = 0x0
	// 16 bits
	SSIE0_SSICR_DWL_001 = 0x1
	// 18 bits
	SSIE0_SSICR_DWL_010 = 0x2
	// 20 bits
	SSIE0_SSICR_DWL_011 = 0x3
	// 22 bits
	SSIE0_SSICR_DWL_100 = 0x4
	// 24 bits
	SSIE0_SSICR_DWL_101 = 0x5
	// 32 bits
	SSIE0_SSICR_DWL_110 = 0x6
	// Setting prohibited
	SSIE0_SSICR_DWL_111 = 0x7
	// Position of FRM field.
	SSIE0_SSICR_FRM_Pos = 0x16
	// Bit mask of FRM field.
	SSIE0_SSICR_FRM_Msk = 0xc00000
	// Position of IIEN field.
	SSIE0_SSICR_IIEN_Pos = 0x19
	// Bit mask of IIEN field.
	SSIE0_SSICR_IIEN_Msk = 0x2000000
	// Bit IIEN.
	SSIE0_SSICR_IIEN = 0x2000000
	// Disables idle mode interrupt output
	SSIE0_SSICR_IIEN_0 = 0x0
	// Enables idle mode interrupt output
	SSIE0_SSICR_IIEN_1 = 0x1
	// Position of ROIEN field.
	SSIE0_SSICR_ROIEN_Pos = 0x1a
	// Bit mask of ROIEN field.
	SSIE0_SSICR_ROIEN_Msk = 0x4000000
	// Bit ROIEN.
	SSIE0_SSICR_ROIEN = 0x4000000
	// Disables receive overflow interrupt output
	SSIE0_SSICR_ROIEN_0 = 0x0
	// Enables receive overflow interrupt output
	SSIE0_SSICR_ROIEN_1 = 0x1
	// Position of RUIEN field.
	SSIE0_SSICR_RUIEN_Pos = 0x1b
	// Bit mask of RUIEN field.
	SSIE0_SSICR_RUIEN_Msk = 0x8000000
	// Bit RUIEN.
	SSIE0_SSICR_RUIEN = 0x8000000
	// Disables receive underflow interrupt output
	SSIE0_SSICR_RUIEN_0 = 0x0
	// Enables receive underflow interrupt output
	SSIE0_SSICR_RUIEN_1 = 0x1
	// Position of TOIEN field.
	SSIE0_SSICR_TOIEN_Pos = 0x1c
	// Bit mask of TOIEN field.
	SSIE0_SSICR_TOIEN_Msk = 0x10000000
	// Bit TOIEN.
	SSIE0_SSICR_TOIEN = 0x10000000
	// Disables transmit overflow interrupt output
	SSIE0_SSICR_TOIEN_0 = 0x0
	// Enables transmit overflow interrupt output
	SSIE0_SSICR_TOIEN_1 = 0x1
	// Position of TUIEN field.
	SSIE0_SSICR_TUIEN_Pos = 0x1d
	// Bit mask of TUIEN field.
	SSIE0_SSICR_TUIEN_Msk = 0x20000000
	// Bit TUIEN.
	SSIE0_SSICR_TUIEN = 0x20000000
	// Disables transmit underflow interrupt output
	SSIE0_SSICR_TUIEN_0 = 0x0
	// Enables transmit underflow interrupt output
	SSIE0_SSICR_TUIEN_1 = 0x1
	// Position of CKS field.
	SSIE0_SSICR_CKS_Pos = 0x1e
	// Bit mask of CKS field.
	SSIE0_SSICR_CKS_Msk = 0x40000000
	// Bit CKS.
	SSIE0_SSICR_CKS = 0x40000000
	// Selects the AUDIO_CLK input
	SSIE0_SSICR_CKS_0 = 0x0
	// Selects the GTIOC2A (GPT output)
	SSIE0_SSICR_CKS_1 = 0x1

	// SSISR: Status Register
	// Position of IIRQ field.
	SSIE0_SSISR_IIRQ_Pos = 0x19
	// Bit mask of IIRQ field.
	SSIE0_SSISR_IIRQ_Msk = 0x2000000
	// Bit IIRQ.
	SSIE0_SSISR_IIRQ = 0x2000000
	// In the communication state
	SSIE0_SSISR_IIRQ_0 = 0x0
	// In the idle state
	SSIE0_SSISR_IIRQ_1 = 0x1
	// Position of ROIRQ field.
	SSIE0_SSISR_ROIRQ_Pos = 0x1a
	// Bit mask of ROIRQ field.
	SSIE0_SSISR_ROIRQ_Msk = 0x4000000
	// Bit ROIRQ.
	SSIE0_SSISR_ROIRQ = 0x4000000
	// No receive overflow error is generated.
	SSIE0_SSISR_ROIRQ_0 = 0x0
	// A receive overflow error is generated.
	SSIE0_SSISR_ROIRQ_1 = 0x1
	// Position of RUIRQ field.
	SSIE0_SSISR_RUIRQ_Pos = 0x1b
	// Bit mask of RUIRQ field.
	SSIE0_SSISR_RUIRQ_Msk = 0x8000000
	// Bit RUIRQ.
	SSIE0_SSISR_RUIRQ = 0x8000000
	// No receive underflow error is generated.
	SSIE0_SSISR_RUIRQ_0 = 0x0
	// A receive underflow error is generated.
	SSIE0_SSISR_RUIRQ_1 = 0x1
	// Position of TOIRQ field.
	SSIE0_SSISR_TOIRQ_Pos = 0x1c
	// Bit mask of TOIRQ field.
	SSIE0_SSISR_TOIRQ_Msk = 0x10000000
	// Bit TOIRQ.
	SSIE0_SSISR_TOIRQ = 0x10000000
	// No transmit overflow error is generated.
	SSIE0_SSISR_TOIRQ_0 = 0x0
	// A transmit overflow error is generated.
	SSIE0_SSISR_TOIRQ_1 = 0x1
	// Position of TUIRQ field.
	SSIE0_SSISR_TUIRQ_Pos = 0x1d
	// Bit mask of TUIRQ field.
	SSIE0_SSISR_TUIRQ_Msk = 0x20000000
	// Bit TUIRQ.
	SSIE0_SSISR_TUIRQ = 0x20000000
	// No transmit underflow error is generated.
	SSIE0_SSISR_TUIRQ_0 = 0x0
	// A transmit underflow error is generated.
	SSIE0_SSISR_TUIRQ_1 = 0x1

	// SSIFCR: FIFO Control Register
	// Position of RFRST field.
	SSIE0_SSIFCR_RFRST_Pos = 0x0
	// Bit mask of RFRST field.
	SSIE0_SSIFCR_RFRST_Msk = 0x1
	// Bit RFRST.
	SSIE0_SSIFCR_RFRST = 0x1
	// Clears a receive data FIFO reset condition
	SSIE0_SSIFCR_RFRST_0 = 0x0
	// Sets a receive data FIFO reset condition
	SSIE0_SSIFCR_RFRST_1 = 0x1
	// Position of TFRST field.
	SSIE0_SSIFCR_TFRST_Pos = 0x1
	// Bit mask of TFRST field.
	SSIE0_SSIFCR_TFRST_Msk = 0x2
	// Bit TFRST.
	SSIE0_SSIFCR_TFRST = 0x2
	// Clears a transmit data FIFO reset condition
	SSIE0_SSIFCR_TFRST_0 = 0x0
	// Sets a transmit data FIFO reset condition
	SSIE0_SSIFCR_TFRST_1 = 0x1
	// Position of RIE field.
	SSIE0_SSIFCR_RIE_Pos = 0x2
	// Bit mask of RIE field.
	SSIE0_SSIFCR_RIE_Msk = 0x4
	// Bit RIE.
	SSIE0_SSIFCR_RIE = 0x4
	// Disables receive data full interrupts
	SSIE0_SSIFCR_RIE_0 = 0x0
	// Enables receive data full interrupts
	SSIE0_SSIFCR_RIE_1 = 0x1
	// Position of TIE field.
	SSIE0_SSIFCR_TIE_Pos = 0x3
	// Bit mask of TIE field.
	SSIE0_SSIFCR_TIE_Msk = 0x8
	// Bit TIE.
	SSIE0_SSIFCR_TIE = 0x8
	// Disables transmit data empty interrupts
	SSIE0_SSIFCR_TIE_0 = 0x0
	// Enables transmit data empty interrupts
	SSIE0_SSIFCR_TIE_1 = 0x1
	// Position of BSW field.
	SSIE0_SSIFCR_BSW_Pos = 0xb
	// Bit mask of BSW field.
	SSIE0_SSIFCR_BSW_Msk = 0x800
	// Bit BSW.
	SSIE0_SSIFCR_BSW = 0x800
	// Disables byte swap
	SSIE0_SSIFCR_BSW_0 = 0x0
	// Enables byte swap
	SSIE0_SSIFCR_BSW_1 = 0x1
	// Position of SSIRST field.
	SSIE0_SSIFCR_SSIRST_Pos = 0x10
	// Bit mask of SSIRST field.
	SSIE0_SSIFCR_SSIRST_Msk = 0x10000
	// Bit SSIRST.
	SSIE0_SSIFCR_SSIRST = 0x10000
	// Clears a software reset condition
	SSIE0_SSIFCR_SSIRST_0 = 0x0
	// Sets a software reset condition
	SSIE0_SSIFCR_SSIRST_1 = 0x1
	// Position of AUCKE field.
	SSIE0_SSIFCR_AUCKE_Pos = 0x1f
	// Bit mask of AUCKE field.
	SSIE0_SSIFCR_AUCKE_Msk = 0x80000000
	// Bit AUCKE.
	SSIE0_SSIFCR_AUCKE = 0x80000000
	// Disables supply of AUDIO_MCK
	SSIE0_SSIFCR_AUCKE_0 = 0x0
	// Enables supply of AUDIO_MCK
	SSIE0_SSIFCR_AUCKE_1 = 0x1

	// SSIFSR: FIFO Status Register
	// Position of RDF field.
	SSIE0_SSIFSR_RDF_Pos = 0x0
	// Bit mask of RDF field.
	SSIE0_SSIFSR_RDF_Msk = 0x1
	// Bit RDF.
	SSIE0_SSIFSR_RDF = 0x1
	// The size of received data in SSIFRDR is not more than the value of SSISCR.RDFS.
	SSIE0_SSIFSR_RDF_0 = 0x0
	// The size of received data in SSIFRDR is not less than the value of SSISCR.RDFS plus one.
	SSIE0_SSIFSR_RDF_1 = 0x1
	// Position of RDC field.
	SSIE0_SSIFSR_RDC_Pos = 0x8
	// Bit mask of RDC field.
	SSIE0_SSIFSR_RDC_Msk = 0x3f00
	// Position of TDE field.
	SSIE0_SSIFSR_TDE_Pos = 0x10
	// Bit mask of TDE field.
	SSIE0_SSIFSR_TDE_Msk = 0x10000
	// Bit TDE.
	SSIE0_SSIFSR_TDE = 0x10000
	// The free space of SSIFTDR is not more than the value of SSISCR.TDES.
	SSIE0_SSIFSR_TDE_0 = 0x0
	// The free space of SSIFTDR is not less than the value of SSISCR.TDES plus one.
	SSIE0_SSIFSR_TDE_1 = 0x1
	// Position of TDC field.
	SSIE0_SSIFSR_TDC_Pos = 0x18
	// Bit mask of TDC field.
	SSIE0_SSIFSR_TDC_Msk = 0x3f000000

	// SSIFTDR: Transmit FIFO Data Register
	// Position of SSIFTDR field.
	SSIE0_SSIFTDR_SSIFTDR_Pos = 0x0
	// Bit mask of SSIFTDR field.
	SSIE0_SSIFTDR_SSIFTDR_Msk = 0xffffffff

	// SSIFRDR: Receive FIFO Data Register
	// Position of SSIFRDR field.
	SSIE0_SSIFRDR_SSIFRDR_Pos = 0x0
	// Bit mask of SSIFRDR field.
	SSIE0_SSIFRDR_SSIFRDR_Msk = 0xffffffff

	// SSIOFR: Audio Format Register
	// Position of OMOD field.
	SSIE0_SSIOFR_OMOD_Pos = 0x0
	// Bit mask of OMOD field.
	SSIE0_SSIOFR_OMOD_Msk = 0x3
	// I2S format
	SSIE0_SSIOFR_OMOD_00 = 0x0
	// TDM format
	SSIE0_SSIOFR_OMOD_01 = 0x1
	// Monaural format
	SSIE0_SSIOFR_OMOD_10 = 0x2
	// Setting prohibited
	SSIE0_SSIOFR_OMOD_11 = 0x3
	// Position of LRCONT field.
	SSIE0_SSIOFR_LRCONT_Pos = 0x8
	// Bit mask of LRCONT field.
	SSIE0_SSIOFR_LRCONT_Msk = 0x100
	// Bit LRCONT.
	SSIE0_SSIOFR_LRCONT = 0x100
	// Disables LRCK/FS continuation
	SSIE0_SSIOFR_LRCONT_0 = 0x0
	// Enables LRCK/FS continuation
	SSIE0_SSIOFR_LRCONT_1 = 0x1
	// Position of BCKASTP field.
	SSIE0_SSIOFR_BCKASTP_Pos = 0x9
	// Bit mask of BCKASTP field.
	SSIE0_SSIOFR_BCKASTP_Msk = 0x200
	// Bit BCKASTP.
	SSIE0_SSIOFR_BCKASTP = 0x200
	// Always outputs BCK to the SSIBCK pin
	SSIE0_SSIOFR_BCKASTP_0 = 0x0
	// Automatically controls output of BCK to the SSIBCK pin
	SSIE0_SSIOFR_BCKASTP_1 = 0x1

	// SSISCR: Status Control Register
	// Position of RDFS field.
	SSIE0_SSISCR_RDFS_Pos = 0x0
	// Bit mask of RDFS field.
	SSIE0_SSISCR_RDFS_Msk = 0x1f
	// Position of TDES field.
	SSIE0_SSISCR_TDES_Pos = 0x8
	// Bit mask of TDES field.
	SSIE0_SSISCR_TDES_Msk = 0x1f00
)

// Constants for CEC: Consumer Electronics Control
const (
	// CADR: CEC Local Address Setting Register
	// Position of ADR00 field.
	CEC_CADR_ADR00_Pos = 0x0
	// Bit mask of ADR00 field.
	CEC_CADR_ADR00_Msk = 0x1
	// Bit ADR00.
	CEC_CADR_ADR00 = 0x1
	// Does not set as local address.
	CEC_CADR_ADR00_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR00_1 = 0x1
	// Position of ADR01 field.
	CEC_CADR_ADR01_Pos = 0x1
	// Bit mask of ADR01 field.
	CEC_CADR_ADR01_Msk = 0x2
	// Bit ADR01.
	CEC_CADR_ADR01 = 0x2
	// Does not set as local address.
	CEC_CADR_ADR01_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR01_1 = 0x1
	// Position of ADR02 field.
	CEC_CADR_ADR02_Pos = 0x2
	// Bit mask of ADR02 field.
	CEC_CADR_ADR02_Msk = 0x4
	// Bit ADR02.
	CEC_CADR_ADR02 = 0x4
	// Does not set as local address.
	CEC_CADR_ADR02_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR02_1 = 0x1
	// Position of ADR03 field.
	CEC_CADR_ADR03_Pos = 0x3
	// Bit mask of ADR03 field.
	CEC_CADR_ADR03_Msk = 0x8
	// Bit ADR03.
	CEC_CADR_ADR03 = 0x8
	// Does not set as local address.
	CEC_CADR_ADR03_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR03_1 = 0x1
	// Position of ADR04 field.
	CEC_CADR_ADR04_Pos = 0x4
	// Bit mask of ADR04 field.
	CEC_CADR_ADR04_Msk = 0x10
	// Bit ADR04.
	CEC_CADR_ADR04 = 0x10
	// Does not set as local address.
	CEC_CADR_ADR04_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR04_1 = 0x1
	// Position of ADR05 field.
	CEC_CADR_ADR05_Pos = 0x5
	// Bit mask of ADR05 field.
	CEC_CADR_ADR05_Msk = 0x20
	// Bit ADR05.
	CEC_CADR_ADR05 = 0x20
	// Does not set as local address.
	CEC_CADR_ADR05_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR05_1 = 0x1
	// Position of ADR06 field.
	CEC_CADR_ADR06_Pos = 0x6
	// Bit mask of ADR06 field.
	CEC_CADR_ADR06_Msk = 0x40
	// Bit ADR06.
	CEC_CADR_ADR06 = 0x40
	// Does not set as local address.
	CEC_CADR_ADR06_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR06_1 = 0x1
	// Position of ADR07 field.
	CEC_CADR_ADR07_Pos = 0x7
	// Bit mask of ADR07 field.
	CEC_CADR_ADR07_Msk = 0x80
	// Bit ADR07.
	CEC_CADR_ADR07 = 0x80
	// Does not set as local address.
	CEC_CADR_ADR07_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR07_1 = 0x1
	// Position of ADR08 field.
	CEC_CADR_ADR08_Pos = 0x8
	// Bit mask of ADR08 field.
	CEC_CADR_ADR08_Msk = 0x100
	// Bit ADR08.
	CEC_CADR_ADR08 = 0x100
	// Does not set as local address.
	CEC_CADR_ADR08_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR08_1 = 0x1
	// Position of ADR09 field.
	CEC_CADR_ADR09_Pos = 0x9
	// Bit mask of ADR09 field.
	CEC_CADR_ADR09_Msk = 0x200
	// Bit ADR09.
	CEC_CADR_ADR09 = 0x200
	// Does not set as local address.
	CEC_CADR_ADR09_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR09_1 = 0x1
	// Position of ADR10 field.
	CEC_CADR_ADR10_Pos = 0xa
	// Bit mask of ADR10 field.
	CEC_CADR_ADR10_Msk = 0x400
	// Bit ADR10.
	CEC_CADR_ADR10 = 0x400
	// Does not set as local address.
	CEC_CADR_ADR10_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR10_1 = 0x1
	// Position of ADR11 field.
	CEC_CADR_ADR11_Pos = 0xb
	// Bit mask of ADR11 field.
	CEC_CADR_ADR11_Msk = 0x800
	// Bit ADR11.
	CEC_CADR_ADR11 = 0x800
	// Does not set as local address.
	CEC_CADR_ADR11_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR11_1 = 0x1
	// Position of ADR12 field.
	CEC_CADR_ADR12_Pos = 0xc
	// Bit mask of ADR12 field.
	CEC_CADR_ADR12_Msk = 0x1000
	// Bit ADR12.
	CEC_CADR_ADR12 = 0x1000
	// Does not set as local address.
	CEC_CADR_ADR12_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR12_1 = 0x1
	// Position of ADR13 field.
	CEC_CADR_ADR13_Pos = 0xd
	// Bit mask of ADR13 field.
	CEC_CADR_ADR13_Msk = 0x2000
	// Bit ADR13.
	CEC_CADR_ADR13 = 0x2000
	// Does not set as local address.
	CEC_CADR_ADR13_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR13_1 = 0x1
	// Position of ADR14 field.
	CEC_CADR_ADR14_Pos = 0xe
	// Bit mask of ADR14 field.
	CEC_CADR_ADR14_Msk = 0x4000
	// Bit ADR14.
	CEC_CADR_ADR14 = 0x4000
	// Does not set as local address.
	CEC_CADR_ADR14_0 = 0x0
	// Sets as local address.
	CEC_CADR_ADR14_1 = 0x1

	// CECCTL1: CEC Control Register 1
	// Position of SFT field.
	CEC_CECCTL1_SFT_Pos = 0x0
	// Bit mask of SFT field.
	CEC_CECCTL1_SFT_Msk = 0x3
	// 3-data bit width
	CEC_CECCTL1_SFT_00 = 0x0
	// 5-data bit width
	CEC_CECCTL1_SFT_01 = 0x1
	// 7-data bit width
	CEC_CECCTL1_SFT_10 = 0x2
	// Does not detect signal-free time.
	CEC_CECCTL1_SFT_11 = 0x3
	// Position of CESEL field.
	CEC_CECCTL1_CESEL_Pos = 0x2
	// Bit mask of CESEL field.
	CEC_CECCTL1_CESEL_Msk = 0xc
	// Generates communication complete interrupt once after ACK transmission (reception) of the last frame (EOM = 1) is complete and another time after signal-free time is detected.
	CEC_CECCTL1_CESEL_00 = 0x0
	// Generates communication complete interrupt after ACK transmission (reception) of the last frame (EOM = 1) is completed.
	CEC_CECCTL1_CESEL_01 = 0x1
	// Generates communication complete interrupt after signal-free time is detected.
	CEC_CECCTL1_CESEL_10 = 0x2
	// Setting prohibited
	CEC_CECCTL1_CESEL_11 = 0x3
	// Position of STERRD field.
	CEC_CECCTL1_STERRD_Pos = 0x4
	// Bit mask of STERRD field.
	CEC_CECCTL1_STERRD_Msk = 0x10
	// Bit STERRD.
	CEC_CECCTL1_STERRD = 0x10
	// Does not detect timing errors during start bit reception.
	CEC_CECCTL1_STERRD_0 = 0x0
	// Detects timing errors during start bit reception.
	CEC_CECCTL1_STERRD_1 = 0x1
	// Position of BLERRD field.
	CEC_CECCTL1_BLERRD_Pos = 0x5
	// Bit mask of BLERRD field.
	CEC_CECCTL1_BLERRD_Msk = 0x20
	// Bit BLERRD.
	CEC_CECCTL1_BLERRD = 0x20
	// Does not detect sticking of receive data to high or low
	CEC_CECCTL1_BLERRD_0 = 0x0
	// Detects sticking of receive data to high or low.
	CEC_CECCTL1_BLERRD_1 = 0x1
	// Position of CINTMK field.
	CEC_CECCTL1_CINTMK_Pos = 0x6
	// Bit mask of CINTMK field.
	CEC_CECCTL1_CINTMK_Msk = 0x40
	// Bit CINTMK.
	CEC_CECCTL1_CINTMK = 0x40
	// Does not generate an interrupt when the addresses do not match.
	CEC_CECCTL1_CINTMK_0 = 0x0
	// Generates an interrupt when the addresses do not match.
	CEC_CECCTL1_CINTMK_1 = 0x1
	// Position of CDFC field.
	CEC_CECCTL1_CDFC_Pos = 0x7
	// Bit mask of CDFC field.
	CEC_CECCTL1_CDFC_Msk = 0x80
	// Bit CDFC.
	CEC_CECCTL1_CDFC = 0x80
	// Does not use a digital filter.
	CEC_CECCTL1_CDFC_0 = 0x0
	// Uses a digital filter.
	CEC_CECCTL1_CDFC_1 = 0x1

	// STATB: CEC Transmission Start Bit Width Setting Register
	// Position of STATB field.
	CEC_STATB_STATB_Pos = 0x0
	// Bit mask of STATB field.
	CEC_STATB_STATB_Msk = 0x1ff

	// STATL: CEC Transmission Start Bit Low Width Setting Register
	// Position of STATL field.
	CEC_STATL_STATL_Pos = 0x0
	// Bit mask of STATL field.
	CEC_STATL_STATL_Msk = 0x1ff

	// LGC0L: CEC Transmission Logical 0 Low Width Setting Register
	// Position of LGC0L field.
	CEC_LGC0L_LGC0L_Pos = 0x0
	// Bit mask of LGC0L field.
	CEC_LGC0L_LGC0L_Msk = 0x1ff

	// LGC1L: CEC Transmission Logical 1 Low Width Setting Register
	// Position of LGC1L field.
	CEC_LGC1L_LGC1L_Pos = 0x0
	// Bit mask of LGC1L field.
	CEC_LGC1L_LGC1L_Msk = 0x1ff

	// DATB: CEC Transmission Data Bit Width Setting Register
	// Position of DATB field.
	CEC_DATB_DATB_Pos = 0x0
	// Bit mask of DATB field.
	CEC_DATB_DATB_Msk = 0x1ff

	// NOMT: CEC Reception Data Sampling Time Setting Register
	// Position of NOMT field.
	CEC_NOMT_NOMT_Pos = 0x0
	// Bit mask of NOMT field.
	CEC_NOMT_NOMT_Msk = 0x1ff

	// STATLL: CEC Reception Start Bit Minimum Low Width Setting Register
	// Position of STATLL field.
	CEC_STATLL_STATLL_Pos = 0x0
	// Bit mask of STATLL field.
	CEC_STATLL_STATLL_Msk = 0x1ff

	// STATLH: CEC Reception Start Bit Maximum Low Width Setting Register
	// Position of STATLH field.
	CEC_STATLH_STATLH_Pos = 0x0
	// Bit mask of STATLH field.
	CEC_STATLH_STATLH_Msk = 0x1ff

	// STATBL: CEC Reception Start Bit Minimum Bit Width Setting Register
	// Position of STATBL field.
	CEC_STATBL_STATBL_Pos = 0x0
	// Bit mask of STATBL field.
	CEC_STATBL_STATBL_Msk = 0x1ff

	// STATBH: CEC Reception Start Bit Maximum Bit Width Setting Register
	// Position of STATBH field.
	CEC_STATBH_STATBH_Pos = 0x0
	// Bit mask of STATBH field.
	CEC_STATBH_STATBH_Msk = 0x1ff

	// LGC0LL: CEC Reception Logical 0 Minimum Low Width Setting Register
	// Position of LGC0LL field.
	CEC_LGC0LL_LGC0LL_Pos = 0x0
	// Bit mask of LGC0LL field.
	CEC_LGC0LL_LGC0LL_Msk = 0x1ff

	// LGC0LH: CEC Reception Logical 0 Maximum Low Width Setting Register
	// Position of LGC0LH field.
	CEC_LGC0LH_LGC0LH_Pos = 0x0
	// Bit mask of LGC0LH field.
	CEC_LGC0LH_LGC0LH_Msk = 0x1ff

	// LGC1LL: CEC Reception Logical 1 Minimum Low Width Setting Register
	// Position of LGC1LL field.
	CEC_LGC1LL_LGC1LL_Pos = 0x0
	// Bit mask of LGC1LL field.
	CEC_LGC1LL_LGC1LL_Msk = 0x1ff

	// LGC1LH: CEC Reception Logical 1 Maximum Low Width Setting Register
	// Position of LGC1LH field.
	CEC_LGC1LH_LGC1LH_Pos = 0x0
	// Bit mask of LGC1LH field.
	CEC_LGC1LH_LGC1LH_Msk = 0x1ff

	// DATBL: CEC Reception Data Bit Minimum Bit Width Setting Register
	// Position of DATBL field.
	CEC_DATBL_DATBL_Pos = 0x0
	// Bit mask of DATBL field.
	CEC_DATBL_DATBL_Msk = 0x1ff

	// DATBH: CEC Reception Data Bit Maximum Bit Width Setting Register
	// Position of DATBH field.
	CEC_DATBH_DATBH_Pos = 0x0
	// Bit mask of DATBH field.
	CEC_DATBH_DATBH_Msk = 0x1ff

	// NOMP: CEC Data Bit Reference Width Setting Register
	// Position of NOMP field.
	CEC_NOMP_NOMP_Pos = 0x0
	// Bit mask of NOMP field.
	CEC_NOMP_NOMP_Msk = 0x1ff

	// CECEXMD: CEC Extension Mode Register
	// Position of LERPLEN field.
	CEC_CECEXMD_LERPLEN_Pos = 0x4
	// Bit mask of LERPLEN field.
	CEC_CECEXMD_LERPLEN_Msk = 0x10
	// Bit LERPLEN.
	CEC_CECEXMD_LERPLEN = 0x10
	// Detects only a long bit width error.
	CEC_CECEXMD_LERPLEN_0 = 0x0
	// Detects a long bit width error and outputs an error handling pulse.
	CEC_CECEXMD_LERPLEN_1 = 0x1
	// Position of RERCVEN field.
	CEC_CECEXMD_RERCVEN_Pos = 0x5
	// Bit mask of RERCVEN field.
	CEC_CECEXMD_RERCVEN_Msk = 0x20
	// Bit RERCVEN.
	CEC_CECEXMD_RERCVEN = 0x20
	// Does not restart reception when the start bit is detected during reception.
	CEC_CECEXMD_RERCVEN_0 = 0x0
	// Restarts reception when the start bit is detected during reception.
	CEC_CECEXMD_RERCVEN_1 = 0x1
	// Position of RCVINTDSEL field.
	CEC_CECEXMD_RCVINTDSEL_Pos = 0x7
	// Bit mask of RCVINTDSEL field.
	CEC_CECEXMD_RCVINTDSEL_Msk = 0x80
	// Bit RCVINTDSEL.
	CEC_CECEXMD_RCVINTDSEL = 0x80
	// EOM timing (9th bit of data)
	CEC_CECEXMD_RCVINTDSEL_0 = 0x0
	// ACK timing (10th bit of data)
	CEC_CECEXMD_RCVINTDSEL_1 = 0x1

	// CECEXMON: CEC Extension Monitor Register
	// Position of CECLNMON field.
	CEC_CECEXMON_CECLNMON_Pos = 0x0
	// Bit mask of CECLNMON field.
	CEC_CECEXMON_CECLNMON_Msk = 0x1
	// Bit CECLNMON.
	CEC_CECEXMON_CECLNMON = 0x1
	// Low level
	CEC_CECEXMON_CECLNMON_0 = 0x0
	// High level
	CEC_CECEXMON_CECLNMON_1 = 0x1
	// Position of ACKF field.
	CEC_CECEXMON_ACKF_Pos = 0x1
	// Bit mask of ACKF field.
	CEC_CECEXMON_ACKF_Msk = 0x2
	// Bit ACKF.
	CEC_CECEXMON_ACKF = 0x2

	// CECES: CEC Communication Error Status Register
	// Position of OERR field.
	CEC_CECES_OERR_Pos = 0x0
	// Bit mask of OERR field.
	CEC_CECES_OERR_Msk = 0x1
	// Bit OERR.
	CEC_CECES_OERR = 0x1
	// No overrun error has occurred.
	CEC_CECES_OERR_0 = 0x0
	// An overrun error has occurred.
	CEC_CECES_OERR_1 = 0x1
	// Position of UERR field.
	CEC_CECES_UERR_Pos = 0x1
	// Bit mask of UERR field.
	CEC_CECES_UERR_Msk = 0x2
	// Bit UERR.
	CEC_CECES_UERR = 0x2
	// No underrun error has occurred.
	CEC_CECES_UERR_0 = 0x0
	// An underrun error has occurred.
	CEC_CECES_UERR_1 = 0x1
	// Position of ACKERR field.
	CEC_CECES_ACKERR_Pos = 0x2
	// Bit mask of ACKERR field.
	CEC_CECES_ACKERR_Msk = 0x4
	// Bit ACKERR.
	CEC_CECES_ACKERR = 0x4
	// No ACK error has occurred.
	CEC_CECES_ACKERR_0 = 0x0
	// An ACK error has occurred.
	CEC_CECES_ACKERR_1 = 0x1
	// Position of TERR field.
	CEC_CECES_TERR_Pos = 0x3
	// Bit mask of TERR field.
	CEC_CECES_TERR_Msk = 0x8
	// Bit TERR.
	CEC_CECES_TERR = 0x8
	// No timing error has occurred.
	CEC_CECES_TERR_0 = 0x0
	// A timing error has occurred.
	CEC_CECES_TERR_1 = 0x1
	// Position of TXERR field.
	CEC_CECES_TXERR_Pos = 0x4
	// Bit mask of TXERR field.
	CEC_CECES_TXERR_Msk = 0x10
	// Bit TXERR.
	CEC_CECES_TXERR = 0x10
	// No transmission error has occurred.
	CEC_CECES_TXERR_0 = 0x0
	// A transmission error has occurred.
	CEC_CECES_TXERR_1 = 0x1
	// Position of AERR field.
	CEC_CECES_AERR_Pos = 0x5
	// Bit mask of AERR field.
	CEC_CECES_AERR_Msk = 0x20
	// Bit AERR.
	CEC_CECES_AERR = 0x20
	// No arbitration loss has occurred.
	CEC_CECES_AERR_0 = 0x0
	// An arbitration loss has occurred.
	CEC_CECES_AERR_1 = 0x1
	// Position of BLERR field.
	CEC_CECES_BLERR_Pos = 0x6
	// Bit mask of BLERR field.
	CEC_CECES_BLERR_Msk = 0x40
	// Bit BLERR.
	CEC_CECES_BLERR = 0x40
	// No bus lock error has occurred.
	CEC_CECES_BLERR_0 = 0x0
	// A bus lock error has occurred.
	CEC_CECES_BLERR_1 = 0x1

	// CECS: CEC Communication Status Register
	// Position of ADRF field.
	CEC_CECS_ADRF_Pos = 0x0
	// Bit mask of ADRF field.
	CEC_CECS_ADRF_Msk = 0x1
	// Bit ADRF.
	CEC_CECS_ADRF = 0x1
	// During communication between other stations, while communication is stopped, or while the local station is transmitting
	CEC_CECS_ADRF_0 = 0x0
	// During local reception
	CEC_CECS_ADRF_1 = 0x1
	// Position of BUSST field.
	CEC_CECS_BUSST_Pos = 0x1
	// Bit mask of BUSST field.
	CEC_CECS_BUSST_Msk = 0x2
	// Bit BUSST.
	CEC_CECS_BUSST = 0x2
	// Bus-free state
	CEC_CECS_BUSST_0 = 0x0
	// Bus-busy state
	CEC_CECS_BUSST_1 = 0x1
	// Position of TXST field.
	CEC_CECS_TXST_Pos = 0x2
	// Bit mask of TXST field.
	CEC_CECS_TXST_Msk = 0x4
	// Bit TXST.
	CEC_CECS_TXST = 0x4
	// During communication standby state or reception (a follower is operating.)
	CEC_CECS_TXST_0 = 0x0
	// During transmission (an initiator is operating.)
	CEC_CECS_TXST_1 = 0x1
	// Position of EOMF field.
	CEC_CECS_EOMF_Pos = 0x3
	// Bit mask of EOMF field.
	CEC_CECS_EOMF_Msk = 0x8
	// Bit EOMF.
	CEC_CECS_EOMF = 0x8
	// The EOM flag received immediately before is logically 0.
	CEC_CECS_EOMF_0 = 0x0
	// The EOM flag received immediately before is logically 1.
	CEC_CECS_EOMF_1 = 0x1
	// Position of ITCEF field.
	CEC_CECS_ITCEF_Pos = 0x4
	// Bit mask of ITCEF field.
	CEC_CECS_ITCEF_Msk = 0x10
	// Bit ITCEF.
	CEC_CECS_ITCEF = 0x10
	// Generates a communication complete interrupt (INTCE) if the signal-free time is counted.
	CEC_CECS_ITCEF_0 = 0x0
	// Generates INTCE if communication is complete or an error is detected.
	CEC_CECS_ITCEF_1 = 0x1
	// Position of SFTST field.
	CEC_CECS_SFTST_Pos = 0x7
	// Bit mask of SFTST field.
	CEC_CECS_SFTST_Msk = 0x80
	// Bit SFTST.
	CEC_CECS_SFTST = 0x80
	// Enables rewriting CECCTL1.SFT[1:0].
	CEC_CECS_SFTST_0 = 0x0
	// Disables rewriting CECCTL1.SFT[1:0].
	CEC_CECS_SFTST_1 = 0x1

	// CECFC: CEC Communication Error Flag Clear Trigger Register
	// Position of OCTRG field.
	CEC_CECFC_OCTRG_Pos = 0x0
	// Bit mask of OCTRG field.
	CEC_CECFC_OCTRG_Msk = 0x1
	// Bit OCTRG.
	CEC_CECFC_OCTRG = 0x1
	// Does not clear overrun error detection flag.
	CEC_CECFC_OCTRG_0 = 0x0
	// Clears overrun error detection flag.
	CEC_CECFC_OCTRG_1 = 0x1
	// Position of UCTRG field.
	CEC_CECFC_UCTRG_Pos = 0x1
	// Bit mask of UCTRG field.
	CEC_CECFC_UCTRG_Msk = 0x2
	// Bit UCTRG.
	CEC_CECFC_UCTRG = 0x2
	// Does not clear underrun error detection flag.
	CEC_CECFC_UCTRG_0 = 0x0
	// Clears underrun error detection flag.
	CEC_CECFC_UCTRG_1 = 0x1
	// Position of ACKCTRG field.
	CEC_CECFC_ACKCTRG_Pos = 0x2
	// Bit mask of ACKCTRG field.
	CEC_CECFC_ACKCTRG_Msk = 0x4
	// Bit ACKCTRG.
	CEC_CECFC_ACKCTRG = 0x4
	// Does not clear ACK error detection flag.
	CEC_CECFC_ACKCTRG_0 = 0x0
	// Clears ACK error detection flag.
	CEC_CECFC_ACKCTRG_1 = 0x1
	// Position of TCTRG field.
	CEC_CECFC_TCTRG_Pos = 0x3
	// Bit mask of TCTRG field.
	CEC_CECFC_TCTRG_Msk = 0x8
	// Bit TCTRG.
	CEC_CECFC_TCTRG = 0x8
	// Does not clear timing error detection flag.
	CEC_CECFC_TCTRG_0 = 0x0
	// Clears timing error detection flag.
	CEC_CECFC_TCTRG_1 = 0x1
	// Position of TXCTRG field.
	CEC_CECFC_TXCTRG_Pos = 0x4
	// Bit mask of TXCTRG field.
	CEC_CECFC_TXCTRG_Msk = 0x10
	// Bit TXCTRG.
	CEC_CECFC_TXCTRG = 0x10
	// Does not clear transmission error detection flag.
	CEC_CECFC_TXCTRG_0 = 0x0
	// Clears transmission error detection flag.
	CEC_CECFC_TXCTRG_1 = 0x1
	// Position of ACTRG field.
	CEC_CECFC_ACTRG_Pos = 0x5
	// Bit mask of ACTRG field.
	CEC_CECFC_ACTRG_Msk = 0x20
	// Bit ACTRG.
	CEC_CECFC_ACTRG = 0x20
	// Does not clear arbitration loss detection flag.
	CEC_CECFC_ACTRG_0 = 0x0
	// Clears arbitration loss detection flag.
	CEC_CECFC_ACTRG_1 = 0x1
	// Position of BLCTRG field.
	CEC_CECFC_BLCTRG_Pos = 0x6
	// Bit mask of BLCTRG field.
	CEC_CECFC_BLCTRG_Msk = 0x40
	// Bit BLCTRG.
	CEC_CECFC_BLCTRG = 0x40
	// Does not clear bus lock error detection flag.
	CEC_CECFC_BLCTRG_0 = 0x0
	// Clears bus lock error detection flag.
	CEC_CECFC_BLCTRG_1 = 0x1

	// CECCTL0: CEC Control Register 0
	// Position of EOM field.
	CEC_CECCTL0_EOM_Pos = 0x0
	// Bit mask of EOM field.
	CEC_CECCTL0_EOM_Msk = 0x1
	// Bit EOM.
	CEC_CECCTL0_EOM = 0x1
	// Continues transmission.
	CEC_CECCTL0_EOM_0 = 0x0
	// Last frame
	CEC_CECCTL0_EOM_1 = 0x1
	// Position of CECRXEN field.
	CEC_CECCTL0_CECRXEN_Pos = 0x1
	// Bit mask of CECRXEN field.
	CEC_CECCTL0_CECRXEN_Msk = 0x2
	// Bit CECRXEN.
	CEC_CECCTL0_CECRXEN = 0x2
	// Disables continuing reception or reports abnormal reception.
	CEC_CECCTL0_CECRXEN_0 = 0x0
	// Enables continuing reception or reports normal reception. lists the reception status and ACK/NACK timing output.
	CEC_CECCTL0_CECRXEN_1 = 0x1
	// Position of TXTRG field.
	CEC_CECCTL0_TXTRG_Pos = 0x2
	// Bit mask of TXTRG field.
	CEC_CECCTL0_TXTRG_Msk = 0x4
	// Bit TXTRG.
	CEC_CECCTL0_TXTRG = 0x4
	// No effect
	CEC_CECCTL0_TXTRG_0 = 0x0
	// Starts CEC transmission.
	CEC_CECCTL0_TXTRG_1 = 0x1
	// Position of CCL field.
	CEC_CECCTL0_CCL_Pos = 0x3
	// Bit mask of CCL field.
	CEC_CECCTL0_CCL_Msk = 0x38
	// PCLKB/25
	CEC_CECCTL0_CCL_000 = 0x0
	// PCLKB/26
	CEC_CECCTL0_CCL_001 = 0x1
	// PCLKB/27
	CEC_CECCTL0_CCL_010 = 0x2
	// PCLKB/28
	CEC_CECCTL0_CCL_011 = 0x3
	// PCLKB/29
	CEC_CECCTL0_CCL_100 = 0x4
	// PCLKB/210
	CEC_CECCTL0_CCL_101 = 0x5
	// CECCLK (when using SOSC)
	CEC_CECCTL0_CCL_110 = 0x6
	// CECCLK/28 (when using MOSC)
	CEC_CECCTL0_CCL_111 = 0x7
	// Position of ACKTEN field.
	CEC_CECCTL0_ACKTEN_Pos = 0x6
	// Bit mask of ACKTEN field.
	CEC_CECCTL0_ACKTEN_Msk = 0x40
	// Bit ACKTEN.
	CEC_CECCTL0_ACKTEN = 0x40
	// Does not detect ACK bit timing errors.
	CEC_CECCTL0_ACKTEN_0 = 0x0
	// Detects ACK bit timing errors.
	CEC_CECCTL0_ACKTEN_1 = 0x1
	// Position of CECE field.
	CEC_CECCTL0_CECE_Pos = 0x7
	// Bit mask of CECE field.
	CEC_CECCTL0_CECE_Msk = 0x80
	// Bit CECE.
	CEC_CECCTL0_CECE = 0x80
	// Disables CEC operation.
	CEC_CECCTL0_CECE_0 = 0x0
	// Enables CEC operation.
	CEC_CECCTL0_CECE_1 = 0x1
)

// Constants for CANFD_B: CANFD
const (
	// CFDC0NCFG: Channel 0 Nominal Bitrate Configuration Register
	// Position of NBRP field.
	CANFD_B_CFDC0NCFG_NBRP_Pos = 0x0
	// Bit mask of NBRP field.
	CANFD_B_CFDC0NCFG_NBRP_Msk = 0x3ff
	// Position of NSJW field.
	CANFD_B_CFDC0NCFG_NSJW_Pos = 0xa
	// Bit mask of NSJW field.
	CANFD_B_CFDC0NCFG_NSJW_Msk = 0x1fc00
	// Position of NTSEG1 field.
	CANFD_B_CFDC0NCFG_NTSEG1_Pos = 0x11
	// Bit mask of NTSEG1 field.
	CANFD_B_CFDC0NCFG_NTSEG1_Msk = 0x1fe0000
	// Position of NTSEG2 field.
	CANFD_B_CFDC0NCFG_NTSEG2_Pos = 0x19
	// Bit mask of NTSEG2 field.
	CANFD_B_CFDC0NCFG_NTSEG2_Msk = 0xfe000000

	// CFDC0CTR: Channel 0 Control Register
	// Position of CHMDC field.
	CANFD_B_CFDC0CTR_CHMDC_Pos = 0x0
	// Bit mask of CHMDC field.
	CANFD_B_CFDC0CTR_CHMDC_Msk = 0x3
	// Channel operation mode request
	CANFD_B_CFDC0CTR_CHMDC_00 = 0x0
	// Channel reset request
	CANFD_B_CFDC0CTR_CHMDC_01 = 0x1
	// Channel halt request
	CANFD_B_CFDC0CTR_CHMDC_10 = 0x2
	// Keep current value
	CANFD_B_CFDC0CTR_CHMDC_11 = 0x3
	// Position of CSLPR field.
	CANFD_B_CFDC0CTR_CSLPR_Pos = 0x2
	// Bit mask of CSLPR field.
	CANFD_B_CFDC0CTR_CSLPR_Msk = 0x4
	// Bit CSLPR.
	CANFD_B_CFDC0CTR_CSLPR = 0x4
	// Channel sleep request disabled
	CANFD_B_CFDC0CTR_CSLPR_0 = 0x0
	// Channel sleep request enabled
	CANFD_B_CFDC0CTR_CSLPR_1 = 0x1
	// Position of RTBO field.
	CANFD_B_CFDC0CTR_RTBO_Pos = 0x3
	// Bit mask of RTBO field.
	CANFD_B_CFDC0CTR_RTBO_Msk = 0x8
	// Bit RTBO.
	CANFD_B_CFDC0CTR_RTBO = 0x8
	// Channel is not forced to return from bus-off
	CANFD_B_CFDC0CTR_RTBO_0 = 0x0
	// Channel is forced to return from bus-off
	CANFD_B_CFDC0CTR_RTBO_1 = 0x1
	// Position of BEIE field.
	CANFD_B_CFDC0CTR_BEIE_Pos = 0x8
	// Bit mask of BEIE field.
	CANFD_B_CFDC0CTR_BEIE_Msk = 0x100
	// Bit BEIE.
	CANFD_B_CFDC0CTR_BEIE = 0x100
	// Bus error interrupt disabled
	CANFD_B_CFDC0CTR_BEIE_0 = 0x0
	// Bus error interrupt enabled
	CANFD_B_CFDC0CTR_BEIE_1 = 0x1
	// Position of EWIE field.
	CANFD_B_CFDC0CTR_EWIE_Pos = 0x9
	// Bit mask of EWIE field.
	CANFD_B_CFDC0CTR_EWIE_Msk = 0x200
	// Bit EWIE.
	CANFD_B_CFDC0CTR_EWIE = 0x200
	// Error warning interrupt disabled
	CANFD_B_CFDC0CTR_EWIE_0 = 0x0
	// Error warning interrupt enabled
	CANFD_B_CFDC0CTR_EWIE_1 = 0x1
	// Position of EPIE field.
	CANFD_B_CFDC0CTR_EPIE_Pos = 0xa
	// Bit mask of EPIE field.
	CANFD_B_CFDC0CTR_EPIE_Msk = 0x400
	// Bit EPIE.
	CANFD_B_CFDC0CTR_EPIE = 0x400
	// Error passive interrupt disabled
	CANFD_B_CFDC0CTR_EPIE_0 = 0x0
	// Error passive interrupt enabled
	CANFD_B_CFDC0CTR_EPIE_1 = 0x1
	// Position of BOEIE field.
	CANFD_B_CFDC0CTR_BOEIE_Pos = 0xb
	// Bit mask of BOEIE field.
	CANFD_B_CFDC0CTR_BOEIE_Msk = 0x800
	// Bit BOEIE.
	CANFD_B_CFDC0CTR_BOEIE = 0x800
	// Bus-off entry interrupt disabled
	CANFD_B_CFDC0CTR_BOEIE_0 = 0x0
	// Bus-off entry interrupt enabled
	CANFD_B_CFDC0CTR_BOEIE_1 = 0x1
	// Position of BORIE field.
	CANFD_B_CFDC0CTR_BORIE_Pos = 0xc
	// Bit mask of BORIE field.
	CANFD_B_CFDC0CTR_BORIE_Msk = 0x1000
	// Bit BORIE.
	CANFD_B_CFDC0CTR_BORIE = 0x1000
	// Bus-off recovery interrupt disabled
	CANFD_B_CFDC0CTR_BORIE_0 = 0x0
	// Bus-off recovery interrupt enabled
	CANFD_B_CFDC0CTR_BORIE_1 = 0x1
	// Position of OLIE field.
	CANFD_B_CFDC0CTR_OLIE_Pos = 0xd
	// Bit mask of OLIE field.
	CANFD_B_CFDC0CTR_OLIE_Msk = 0x2000
	// Bit OLIE.
	CANFD_B_CFDC0CTR_OLIE = 0x2000
	// Overload interrupt disabled
	CANFD_B_CFDC0CTR_OLIE_0 = 0x0
	// Overload interrupt enabled
	CANFD_B_CFDC0CTR_OLIE_1 = 0x1
	// Position of BLIE field.
	CANFD_B_CFDC0CTR_BLIE_Pos = 0xe
	// Bit mask of BLIE field.
	CANFD_B_CFDC0CTR_BLIE_Msk = 0x4000
	// Bit BLIE.
	CANFD_B_CFDC0CTR_BLIE = 0x4000
	// Bus lock interrupt disabled
	CANFD_B_CFDC0CTR_BLIE_0 = 0x0
	// Bus lock interrupt enabled
	CANFD_B_CFDC0CTR_BLIE_1 = 0x1
	// Position of ALIE field.
	CANFD_B_CFDC0CTR_ALIE_Pos = 0xf
	// Bit mask of ALIE field.
	CANFD_B_CFDC0CTR_ALIE_Msk = 0x8000
	// Bit ALIE.
	CANFD_B_CFDC0CTR_ALIE = 0x8000
	// Arbitration lost interrupt disabled
	CANFD_B_CFDC0CTR_ALIE_0 = 0x0
	// Arbitration lost interrupt enabled
	CANFD_B_CFDC0CTR_ALIE_1 = 0x1
	// Position of TAIE field.
	CANFD_B_CFDC0CTR_TAIE_Pos = 0x10
	// Bit mask of TAIE field.
	CANFD_B_CFDC0CTR_TAIE_Msk = 0x10000
	// Bit TAIE.
	CANFD_B_CFDC0CTR_TAIE = 0x10000
	// TX abort interrupt disabled
	CANFD_B_CFDC0CTR_TAIE_0 = 0x0
	// TX abort interrupt enabled
	CANFD_B_CFDC0CTR_TAIE_1 = 0x1
	// Position of EOCOIE field.
	CANFD_B_CFDC0CTR_EOCOIE_Pos = 0x11
	// Bit mask of EOCOIE field.
	CANFD_B_CFDC0CTR_EOCOIE_Msk = 0x20000
	// Bit EOCOIE.
	CANFD_B_CFDC0CTR_EOCOIE = 0x20000
	// Error occurrence counter overflow interrupt disabled
	CANFD_B_CFDC0CTR_EOCOIE_0 = 0x0
	// Error occurrence counter overflow interrupt enabled
	CANFD_B_CFDC0CTR_EOCOIE_1 = 0x1
	// Position of SOCOIE field.
	CANFD_B_CFDC0CTR_SOCOIE_Pos = 0x12
	// Bit mask of SOCOIE field.
	CANFD_B_CFDC0CTR_SOCOIE_Msk = 0x40000
	// Bit SOCOIE.
	CANFD_B_CFDC0CTR_SOCOIE = 0x40000
	// Successful occurrence counter overflow interrupt disabled
	CANFD_B_CFDC0CTR_SOCOIE_0 = 0x0
	// Successful occurrence counter overflow interrupt enabled
	CANFD_B_CFDC0CTR_SOCOIE_1 = 0x1
	// Position of TDCVFIE field.
	CANFD_B_CFDC0CTR_TDCVFIE_Pos = 0x13
	// Bit mask of TDCVFIE field.
	CANFD_B_CFDC0CTR_TDCVFIE_Msk = 0x80000
	// Bit TDCVFIE.
	CANFD_B_CFDC0CTR_TDCVFIE = 0x80000
	// Transceiver delay compensation violation interrupt disabled
	CANFD_B_CFDC0CTR_TDCVFIE_0 = 0x0
	// Transceiver delay compensation violation interrupt enabled
	CANFD_B_CFDC0CTR_TDCVFIE_1 = 0x1
	// Position of BOM field.
	CANFD_B_CFDC0CTR_BOM_Pos = 0x15
	// Bit mask of BOM field.
	CANFD_B_CFDC0CTR_BOM_Msk = 0x600000
	// Normal mode (comply with ISO 11898-1)
	CANFD_B_CFDC0CTR_BOM_00 = 0x0
	// Entry to Halt mode automatically at bus-off start
	CANFD_B_CFDC0CTR_BOM_01 = 0x1
	// Entry to Halt mode automatically at bus-off end
	CANFD_B_CFDC0CTR_BOM_10 = 0x2
	// Entry to Halt mode (during bus-off recovery period) by software
	CANFD_B_CFDC0CTR_BOM_11 = 0x3
	// Position of ERRD field.
	CANFD_B_CFDC0CTR_ERRD_Pos = 0x17
	// Bit mask of ERRD field.
	CANFD_B_CFDC0CTR_ERRD_Msk = 0x800000
	// Bit ERRD.
	CANFD_B_CFDC0CTR_ERRD = 0x800000
	// Only the first set of error codes displayed
	CANFD_B_CFDC0CTR_ERRD_0 = 0x0
	// Accumulated error codes displayed
	CANFD_B_CFDC0CTR_ERRD_1 = 0x1
	// Position of CTME field.
	CANFD_B_CFDC0CTR_CTME_Pos = 0x18
	// Bit mask of CTME field.
	CANFD_B_CFDC0CTR_CTME_Msk = 0x1000000
	// Bit CTME.
	CANFD_B_CFDC0CTR_CTME = 0x1000000
	// Channel test mode disabled
	CANFD_B_CFDC0CTR_CTME_0 = 0x0
	// Channel test mode enabled
	CANFD_B_CFDC0CTR_CTME_1 = 0x1
	// Position of CTMS field.
	CANFD_B_CFDC0CTR_CTMS_Pos = 0x19
	// Bit mask of CTMS field.
	CANFD_B_CFDC0CTR_CTMS_Msk = 0x6000000
	// Basic test mode
	CANFD_B_CFDC0CTR_CTMS_00 = 0x0
	// Listen-only mode
	CANFD_B_CFDC0CTR_CTMS_01 = 0x1
	// Self-test mode 0 (External loopback mode)
	CANFD_B_CFDC0CTR_CTMS_10 = 0x2
	// Self-test mode 1 (Internal loopback mode)
	CANFD_B_CFDC0CTR_CTMS_11 = 0x3
	// Position of BFT field.
	CANFD_B_CFDC0CTR_BFT_Pos = 0x1e
	// Bit mask of BFT field.
	CANFD_B_CFDC0CTR_BFT_Msk = 0x40000000
	// Bit BFT.
	CANFD_B_CFDC0CTR_BFT = 0x40000000
	// First data bit of reception stream not inverted
	CANFD_B_CFDC0CTR_BFT_0 = 0x0
	// First data bit of reception stream inverted
	CANFD_B_CFDC0CTR_BFT_1 = 0x1
	// Position of ROM field.
	CANFD_B_CFDC0CTR_ROM_Pos = 0x1f
	// Bit mask of ROM field.
	CANFD_B_CFDC0CTR_ROM_Msk = 0x80000000
	// Bit ROM.
	CANFD_B_CFDC0CTR_ROM = 0x80000000
	// Restricted operation mode disabled
	CANFD_B_CFDC0CTR_ROM_0 = 0x0
	// Restricted operation mode enabled
	CANFD_B_CFDC0CTR_ROM_1 = 0x1

	// CFDC0STS: Channel 0 Status Register
	// Position of CRSTSTS field.
	CANFD_B_CFDC0STS_CRSTSTS_Pos = 0x0
	// Bit mask of CRSTSTS field.
	CANFD_B_CFDC0STS_CRSTSTS_Msk = 0x1
	// Bit CRSTSTS.
	CANFD_B_CFDC0STS_CRSTSTS = 0x1
	// Channel not in Reset mode
	CANFD_B_CFDC0STS_CRSTSTS_0 = 0x0
	// Channel in Reset mode
	CANFD_B_CFDC0STS_CRSTSTS_1 = 0x1
	// Position of CHLTSTS field.
	CANFD_B_CFDC0STS_CHLTSTS_Pos = 0x1
	// Bit mask of CHLTSTS field.
	CANFD_B_CFDC0STS_CHLTSTS_Msk = 0x2
	// Bit CHLTSTS.
	CANFD_B_CFDC0STS_CHLTSTS = 0x2
	// Channel not in Halt mode
	CANFD_B_CFDC0STS_CHLTSTS_0 = 0x0
	// Channel in Halt mode
	CANFD_B_CFDC0STS_CHLTSTS_1 = 0x1
	// Position of CSLPSTS field.
	CANFD_B_CFDC0STS_CSLPSTS_Pos = 0x2
	// Bit mask of CSLPSTS field.
	CANFD_B_CFDC0STS_CSLPSTS_Msk = 0x4
	// Bit CSLPSTS.
	CANFD_B_CFDC0STS_CSLPSTS = 0x4
	// Channel not in Sleep mode
	CANFD_B_CFDC0STS_CSLPSTS_0 = 0x0
	// Channel in Sleep mode
	CANFD_B_CFDC0STS_CSLPSTS_1 = 0x1
	// Position of EPSTS field.
	CANFD_B_CFDC0STS_EPSTS_Pos = 0x3
	// Bit mask of EPSTS field.
	CANFD_B_CFDC0STS_EPSTS_Msk = 0x8
	// Bit EPSTS.
	CANFD_B_CFDC0STS_EPSTS = 0x8
	// Channel not in error passive state
	CANFD_B_CFDC0STS_EPSTS_0 = 0x0
	// Channel in error passive state
	CANFD_B_CFDC0STS_EPSTS_1 = 0x1
	// Position of BOSTS field.
	CANFD_B_CFDC0STS_BOSTS_Pos = 0x4
	// Bit mask of BOSTS field.
	CANFD_B_CFDC0STS_BOSTS_Msk = 0x10
	// Bit BOSTS.
	CANFD_B_CFDC0STS_BOSTS = 0x10
	// Channel not in bus-off state
	CANFD_B_CFDC0STS_BOSTS_0 = 0x0
	// Channel in bus-off state
	CANFD_B_CFDC0STS_BOSTS_1 = 0x1
	// Position of TRMSTS field.
	CANFD_B_CFDC0STS_TRMSTS_Pos = 0x5
	// Bit mask of TRMSTS field.
	CANFD_B_CFDC0STS_TRMSTS_Msk = 0x20
	// Bit TRMSTS.
	CANFD_B_CFDC0STS_TRMSTS = 0x20
	// Channel is not transmitting
	CANFD_B_CFDC0STS_TRMSTS_0 = 0x0
	// Channel is transmitting
	CANFD_B_CFDC0STS_TRMSTS_1 = 0x1
	// Position of RECSTS field.
	CANFD_B_CFDC0STS_RECSTS_Pos = 0x6
	// Bit mask of RECSTS field.
	CANFD_B_CFDC0STS_RECSTS_Msk = 0x40
	// Bit RECSTS.
	CANFD_B_CFDC0STS_RECSTS = 0x40
	// Channel is not receiving
	CANFD_B_CFDC0STS_RECSTS_0 = 0x0
	// Channel is receiving
	CANFD_B_CFDC0STS_RECSTS_1 = 0x1
	// Position of COMSTS field.
	CANFD_B_CFDC0STS_COMSTS_Pos = 0x7
	// Bit mask of COMSTS field.
	CANFD_B_CFDC0STS_COMSTS_Msk = 0x80
	// Bit COMSTS.
	CANFD_B_CFDC0STS_COMSTS = 0x80
	// Channel is not ready for communication
	CANFD_B_CFDC0STS_COMSTS_0 = 0x0
	// Channel is ready for communication
	CANFD_B_CFDC0STS_COMSTS_1 = 0x1
	// Position of ESIF field.
	CANFD_B_CFDC0STS_ESIF_Pos = 0x8
	// Bit mask of ESIF field.
	CANFD_B_CFDC0STS_ESIF_Msk = 0x100
	// Bit ESIF.
	CANFD_B_CFDC0STS_ESIF = 0x100
	// No CANFD message has been received when the ESI flag was set
	CANFD_B_CFDC0STS_ESIF_0 = 0x0
	// At least one CANFD message was received when the ESI flag was set
	CANFD_B_CFDC0STS_ESIF_1 = 0x1
	// Position of REC field.
	CANFD_B_CFDC0STS_REC_Pos = 0x10
	// Bit mask of REC field.
	CANFD_B_CFDC0STS_REC_Msk = 0xff0000
	// Position of TEC field.
	CANFD_B_CFDC0STS_TEC_Pos = 0x18
	// Bit mask of TEC field.
	CANFD_B_CFDC0STS_TEC_Msk = 0xff000000

	// CFDC0ERFL: Channel 0 Error Flag Register
	// Position of BEF field.
	CANFD_B_CFDC0ERFL_BEF_Pos = 0x0
	// Bit mask of BEF field.
	CANFD_B_CFDC0ERFL_BEF_Msk = 0x1
	// Bit BEF.
	CANFD_B_CFDC0ERFL_BEF = 0x1
	// Channel bus error not detected
	CANFD_B_CFDC0ERFL_BEF_0 = 0x0
	// Channel bus error detected
	CANFD_B_CFDC0ERFL_BEF_1 = 0x1
	// Position of EWF field.
	CANFD_B_CFDC0ERFL_EWF_Pos = 0x1
	// Bit mask of EWF field.
	CANFD_B_CFDC0ERFL_EWF_Msk = 0x2
	// Bit EWF.
	CANFD_B_CFDC0ERFL_EWF = 0x2
	// Channel error warning not detected
	CANFD_B_CFDC0ERFL_EWF_0 = 0x0
	// Channel error warning detected
	CANFD_B_CFDC0ERFL_EWF_1 = 0x1
	// Position of EPF field.
	CANFD_B_CFDC0ERFL_EPF_Pos = 0x2
	// Bit mask of EPF field.
	CANFD_B_CFDC0ERFL_EPF_Msk = 0x4
	// Bit EPF.
	CANFD_B_CFDC0ERFL_EPF = 0x4
	// Channel error passive not detected
	CANFD_B_CFDC0ERFL_EPF_0 = 0x0
	// Channel error passive detected
	CANFD_B_CFDC0ERFL_EPF_1 = 0x1
	// Position of BOEF field.
	CANFD_B_CFDC0ERFL_BOEF_Pos = 0x3
	// Bit mask of BOEF field.
	CANFD_B_CFDC0ERFL_BOEF_Msk = 0x8
	// Bit BOEF.
	CANFD_B_CFDC0ERFL_BOEF = 0x8
	// Channel bus-off entry not detected
	CANFD_B_CFDC0ERFL_BOEF_0 = 0x0
	// Channel bus-off entry detected
	CANFD_B_CFDC0ERFL_BOEF_1 = 0x1
	// Position of BORF field.
	CANFD_B_CFDC0ERFL_BORF_Pos = 0x4
	// Bit mask of BORF field.
	CANFD_B_CFDC0ERFL_BORF_Msk = 0x10
	// Bit BORF.
	CANFD_B_CFDC0ERFL_BORF = 0x10
	// Channel bus-off recovery not detected
	CANFD_B_CFDC0ERFL_BORF_0 = 0x0
	// Channel bus-off recovery detected
	CANFD_B_CFDC0ERFL_BORF_1 = 0x1
	// Position of OVLF field.
	CANFD_B_CFDC0ERFL_OVLF_Pos = 0x5
	// Bit mask of OVLF field.
	CANFD_B_CFDC0ERFL_OVLF_Msk = 0x20
	// Bit OVLF.
	CANFD_B_CFDC0ERFL_OVLF = 0x20
	// Channel overload not detected
	CANFD_B_CFDC0ERFL_OVLF_0 = 0x0
	// Channel overload detected
	CANFD_B_CFDC0ERFL_OVLF_1 = 0x1
	// Position of BLF field.
	CANFD_B_CFDC0ERFL_BLF_Pos = 0x6
	// Bit mask of BLF field.
	CANFD_B_CFDC0ERFL_BLF_Msk = 0x40
	// Bit BLF.
	CANFD_B_CFDC0ERFL_BLF = 0x40
	// Channel bus lock not detected
	CANFD_B_CFDC0ERFL_BLF_0 = 0x0
	// Channel bus lock detected
	CANFD_B_CFDC0ERFL_BLF_1 = 0x1
	// Position of ALF field.
	CANFD_B_CFDC0ERFL_ALF_Pos = 0x7
	// Bit mask of ALF field.
	CANFD_B_CFDC0ERFL_ALF_Msk = 0x80
	// Bit ALF.
	CANFD_B_CFDC0ERFL_ALF = 0x80
	// Channel arbitration lost not detected
	CANFD_B_CFDC0ERFL_ALF_0 = 0x0
	// Channel arbitration lost detected
	CANFD_B_CFDC0ERFL_ALF_1 = 0x1
	// Position of SERR field.
	CANFD_B_CFDC0ERFL_SERR_Pos = 0x8
	// Bit mask of SERR field.
	CANFD_B_CFDC0ERFL_SERR_Msk = 0x100
	// Bit SERR.
	CANFD_B_CFDC0ERFL_SERR = 0x100
	// Channel stuff error not detected
	CANFD_B_CFDC0ERFL_SERR_0 = 0x0
	// Channel stuff error detected
	CANFD_B_CFDC0ERFL_SERR_1 = 0x1
	// Position of FERR field.
	CANFD_B_CFDC0ERFL_FERR_Pos = 0x9
	// Bit mask of FERR field.
	CANFD_B_CFDC0ERFL_FERR_Msk = 0x200
	// Bit FERR.
	CANFD_B_CFDC0ERFL_FERR = 0x200
	// Channel form error not detected
	CANFD_B_CFDC0ERFL_FERR_0 = 0x0
	// Channel form error detected
	CANFD_B_CFDC0ERFL_FERR_1 = 0x1
	// Position of AERR field.
	CANFD_B_CFDC0ERFL_AERR_Pos = 0xa
	// Bit mask of AERR field.
	CANFD_B_CFDC0ERFL_AERR_Msk = 0x400
	// Bit AERR.
	CANFD_B_CFDC0ERFL_AERR = 0x400
	// Channel acknowledge error not detected
	CANFD_B_CFDC0ERFL_AERR_0 = 0x0
	// Channel acknowledge error detected
	CANFD_B_CFDC0ERFL_AERR_1 = 0x1
	// Position of CERR field.
	CANFD_B_CFDC0ERFL_CERR_Pos = 0xb
	// Bit mask of CERR field.
	CANFD_B_CFDC0ERFL_CERR_Msk = 0x800
	// Bit CERR.
	CANFD_B_CFDC0ERFL_CERR = 0x800
	// Channel CRC error not detected
	CANFD_B_CFDC0ERFL_CERR_0 = 0x0
	// Channel CRC error detected
	CANFD_B_CFDC0ERFL_CERR_1 = 0x1
	// Position of B1ERR field.
	CANFD_B_CFDC0ERFL_B1ERR_Pos = 0xc
	// Bit mask of B1ERR field.
	CANFD_B_CFDC0ERFL_B1ERR_Msk = 0x1000
	// Bit B1ERR.
	CANFD_B_CFDC0ERFL_B1ERR = 0x1000
	// Channel bit 1 error not detected
	CANFD_B_CFDC0ERFL_B1ERR_0 = 0x0
	// Channel bit 1 error detected
	CANFD_B_CFDC0ERFL_B1ERR_1 = 0x1
	// Position of B0ERR field.
	CANFD_B_CFDC0ERFL_B0ERR_Pos = 0xd
	// Bit mask of B0ERR field.
	CANFD_B_CFDC0ERFL_B0ERR_Msk = 0x2000
	// Bit B0ERR.
	CANFD_B_CFDC0ERFL_B0ERR = 0x2000
	// Channel bit 0 error not detected
	CANFD_B_CFDC0ERFL_B0ERR_0 = 0x0
	// Channel bit 0 error detected
	CANFD_B_CFDC0ERFL_B0ERR_1 = 0x1
	// Position of ADERR field.
	CANFD_B_CFDC0ERFL_ADERR_Pos = 0xe
	// Bit mask of ADERR field.
	CANFD_B_CFDC0ERFL_ADERR_Msk = 0x4000
	// Bit ADERR.
	CANFD_B_CFDC0ERFL_ADERR = 0x4000
	// Channel acknowledge delimiter error not detected
	CANFD_B_CFDC0ERFL_ADERR_0 = 0x0
	// Channel acknowledge delimiter error detected
	CANFD_B_CFDC0ERFL_ADERR_1 = 0x1
	// Position of CRCREG field.
	CANFD_B_CFDC0ERFL_CRCREG_Pos = 0x10
	// Bit mask of CRCREG field.
	CANFD_B_CFDC0ERFL_CRCREG_Msk = 0x7fff0000

	// CFDGCFG: Global Configuration Register
	// Position of TPRI field.
	CANFD_B_CFDGCFG_TPRI_Pos = 0x0
	// Bit mask of TPRI field.
	CANFD_B_CFDGCFG_TPRI_Msk = 0x1
	// Bit TPRI.
	CANFD_B_CFDGCFG_TPRI = 0x1
	// ID priority
	CANFD_B_CFDGCFG_TPRI_0 = 0x0
	// Message buffer number priority
	CANFD_B_CFDGCFG_TPRI_1 = 0x1
	// Position of DCE field.
	CANFD_B_CFDGCFG_DCE_Pos = 0x1
	// Bit mask of DCE field.
	CANFD_B_CFDGCFG_DCE_Msk = 0x2
	// Bit DCE.
	CANFD_B_CFDGCFG_DCE = 0x2
	// DLC check disabled
	CANFD_B_CFDGCFG_DCE_0 = 0x0
	// DLC check enabled
	CANFD_B_CFDGCFG_DCE_1 = 0x1
	// Position of DRE field.
	CANFD_B_CFDGCFG_DRE_Pos = 0x2
	// Bit mask of DRE field.
	CANFD_B_CFDGCFG_DRE_Msk = 0x4
	// Bit DRE.
	CANFD_B_CFDGCFG_DRE = 0x4
	// DLC replacement disabled
	CANFD_B_CFDGCFG_DRE_0 = 0x0
	// DLC replacement enabled
	CANFD_B_CFDGCFG_DRE_1 = 0x1
	// Position of MME field.
	CANFD_B_CFDGCFG_MME_Pos = 0x3
	// Bit mask of MME field.
	CANFD_B_CFDGCFG_MME_Msk = 0x8
	// Bit MME.
	CANFD_B_CFDGCFG_MME = 0x8
	// Mirror mode disabled
	CANFD_B_CFDGCFG_MME_0 = 0x0
	// Mirror mode enabled
	CANFD_B_CFDGCFG_MME_1 = 0x1
	// Position of DCS field.
	CANFD_B_CFDGCFG_DCS_Pos = 0x4
	// Bit mask of DCS field.
	CANFD_B_CFDGCFG_DCS_Msk = 0x10
	// Bit DCS.
	CANFD_B_CFDGCFG_DCS = 0x10
	// Internal clean clock
	CANFD_B_CFDGCFG_DCS_0 = 0x0
	// External clock source connected to CANMCLK pin
	CANFD_B_CFDGCFG_DCS_1 = 0x1
	// Position of CMPOC field.
	CANFD_B_CFDGCFG_CMPOC_Pos = 0x5
	// Bit mask of CMPOC field.
	CANFD_B_CFDGCFG_CMPOC_Msk = 0x20
	// Bit CMPOC.
	CANFD_B_CFDGCFG_CMPOC = 0x20
	// Message is rejected
	CANFD_B_CFDGCFG_CMPOC_0 = 0x0
	// Message payload is cut to fit to configured message size
	CANFD_B_CFDGCFG_CMPOC_1 = 0x1
	// Position of TSP field.
	CANFD_B_CFDGCFG_TSP_Pos = 0x8
	// Bit mask of TSP field.
	CANFD_B_CFDGCFG_TSP_Msk = 0xf00
	// Position of TSSS field.
	CANFD_B_CFDGCFG_TSSS_Pos = 0xc
	// Bit mask of TSSS field.
	CANFD_B_CFDGCFG_TSSS_Msk = 0x1000
	// Bit TSSS.
	CANFD_B_CFDGCFG_TSSS = 0x1000
	// Source clock for timestamp counter is peripheral clock
	CANFD_B_CFDGCFG_TSSS_0 = 0x0
	// Source clock for timestamp counter is bit time clock
	CANFD_B_CFDGCFG_TSSS_1 = 0x1
	// Position of ITRCP field.
	CANFD_B_CFDGCFG_ITRCP_Pos = 0x10
	// Bit mask of ITRCP field.
	CANFD_B_CFDGCFG_ITRCP_Msk = 0xffff0000

	// CFDGCTR: Global Control Register
	// Position of GMDC field.
	CANFD_B_CFDGCTR_GMDC_Pos = 0x0
	// Bit mask of GMDC field.
	CANFD_B_CFDGCTR_GMDC_Msk = 0x3
	// Global operation mode request
	CANFD_B_CFDGCTR_GMDC_00 = 0x0
	// Global reset mode request
	CANFD_B_CFDGCTR_GMDC_01 = 0x1
	// Global halt mode request
	CANFD_B_CFDGCTR_GMDC_10 = 0x2
	// Keep current value
	CANFD_B_CFDGCTR_GMDC_11 = 0x3
	// Position of GSLPR field.
	CANFD_B_CFDGCTR_GSLPR_Pos = 0x2
	// Bit mask of GSLPR field.
	CANFD_B_CFDGCTR_GSLPR_Msk = 0x4
	// Bit GSLPR.
	CANFD_B_CFDGCTR_GSLPR = 0x4
	// Global sleep request disabled
	CANFD_B_CFDGCTR_GSLPR_0 = 0x0
	// Global sleep request enabled
	CANFD_B_CFDGCTR_GSLPR_1 = 0x1
	// Position of DEIE field.
	CANFD_B_CFDGCTR_DEIE_Pos = 0x8
	// Bit mask of DEIE field.
	CANFD_B_CFDGCTR_DEIE_Msk = 0x100
	// Bit DEIE.
	CANFD_B_CFDGCTR_DEIE = 0x100
	// DLC check interrupt disabled
	CANFD_B_CFDGCTR_DEIE_0 = 0x0
	// DLC check interrupt enabled
	CANFD_B_CFDGCTR_DEIE_1 = 0x1
	// Position of MEIE field.
	CANFD_B_CFDGCTR_MEIE_Pos = 0x9
	// Bit mask of MEIE field.
	CANFD_B_CFDGCTR_MEIE_Msk = 0x200
	// Bit MEIE.
	CANFD_B_CFDGCTR_MEIE = 0x200
	// Message lost error interrupt disabled
	CANFD_B_CFDGCTR_MEIE_0 = 0x0
	// Message lost error interrupt enabled
	CANFD_B_CFDGCTR_MEIE_1 = 0x1
	// Position of THLEIE field.
	CANFD_B_CFDGCTR_THLEIE_Pos = 0xa
	// Bit mask of THLEIE field.
	CANFD_B_CFDGCTR_THLEIE_Msk = 0x400
	// Bit THLEIE.
	CANFD_B_CFDGCTR_THLEIE = 0x400
	// TX history list entry lost interrupt disabled
	CANFD_B_CFDGCTR_THLEIE_0 = 0x0
	// TX history list entry lost interrupt enabled
	CANFD_B_CFDGCTR_THLEIE_1 = 0x1
	// Position of CMPOFIE field.
	CANFD_B_CFDGCTR_CMPOFIE_Pos = 0xb
	// Bit mask of CMPOFIE field.
	CANFD_B_CFDGCTR_CMPOFIE_Msk = 0x800
	// Bit CMPOFIE.
	CANFD_B_CFDGCTR_CMPOFIE = 0x800
	// CANFD message payload overflow flag interrupt disabled
	CANFD_B_CFDGCTR_CMPOFIE_0 = 0x0
	// CANFD message payload overflow flag interrupt enabled
	CANFD_B_CFDGCTR_CMPOFIE_1 = 0x1
	// Position of TSRST field.
	CANFD_B_CFDGCTR_TSRST_Pos = 0x10
	// Bit mask of TSRST field.
	CANFD_B_CFDGCTR_TSRST_Msk = 0x10000
	// Bit TSRST.
	CANFD_B_CFDGCTR_TSRST = 0x10000
	// Timestamp not reset
	CANFD_B_CFDGCTR_TSRST_0 = 0x0
	// Timestamp reset
	CANFD_B_CFDGCTR_TSRST_1 = 0x1

	// CFDGSTS: Global Status Register
	// Position of GRSTSTS field.
	CANFD_B_CFDGSTS_GRSTSTS_Pos = 0x0
	// Bit mask of GRSTSTS field.
	CANFD_B_CFDGSTS_GRSTSTS_Msk = 0x1
	// Bit GRSTSTS.
	CANFD_B_CFDGSTS_GRSTSTS = 0x1
	// Not in Reset mode
	CANFD_B_CFDGSTS_GRSTSTS_0 = 0x0
	// In Reset mode
	CANFD_B_CFDGSTS_GRSTSTS_1 = 0x1
	// Position of GHLTSTS field.
	CANFD_B_CFDGSTS_GHLTSTS_Pos = 0x1
	// Bit mask of GHLTSTS field.
	CANFD_B_CFDGSTS_GHLTSTS_Msk = 0x2
	// Bit GHLTSTS.
	CANFD_B_CFDGSTS_GHLTSTS = 0x2
	// Not in Halt mode
	CANFD_B_CFDGSTS_GHLTSTS_0 = 0x0
	// In Halt mode
	CANFD_B_CFDGSTS_GHLTSTS_1 = 0x1
	// Position of GSLPSTS field.
	CANFD_B_CFDGSTS_GSLPSTS_Pos = 0x2
	// Bit mask of GSLPSTS field.
	CANFD_B_CFDGSTS_GSLPSTS_Msk = 0x4
	// Bit GSLPSTS.
	CANFD_B_CFDGSTS_GSLPSTS = 0x4
	// Not in Sleep mode
	CANFD_B_CFDGSTS_GSLPSTS_0 = 0x0
	// In Sleep mode
	CANFD_B_CFDGSTS_GSLPSTS_1 = 0x1
	// Position of GRAMINIT field.
	CANFD_B_CFDGSTS_GRAMINIT_Pos = 0x3
	// Bit mask of GRAMINIT field.
	CANFD_B_CFDGSTS_GRAMINIT_Msk = 0x8
	// Bit GRAMINIT.
	CANFD_B_CFDGSTS_GRAMINIT = 0x8
	// RAM initialization is complete
	CANFD_B_CFDGSTS_GRAMINIT_0 = 0x0
	// RAM initialization is ongoing
	CANFD_B_CFDGSTS_GRAMINIT_1 = 0x1

	// CFDGERFL: Global Error Flag Register
	// Position of DEF field.
	CANFD_B_CFDGERFL_DEF_Pos = 0x0
	// Bit mask of DEF field.
	CANFD_B_CFDGERFL_DEF_Msk = 0x1
	// Bit DEF.
	CANFD_B_CFDGERFL_DEF = 0x1
	// DLC error not detected
	CANFD_B_CFDGERFL_DEF_0 = 0x0
	// DLC error detected
	CANFD_B_CFDGERFL_DEF_1 = 0x1
	// Position of MES field.
	CANFD_B_CFDGERFL_MES_Pos = 0x1
	// Bit mask of MES field.
	CANFD_B_CFDGERFL_MES_Msk = 0x2
	// Bit MES.
	CANFD_B_CFDGERFL_MES = 0x2
	// Message lost error not detected
	CANFD_B_CFDGERFL_MES_0 = 0x0
	// Message lost error detected
	CANFD_B_CFDGERFL_MES_1 = 0x1
	// Position of THLES field.
	CANFD_B_CFDGERFL_THLES_Pos = 0x2
	// Bit mask of THLES field.
	CANFD_B_CFDGERFL_THLES_Msk = 0x4
	// Bit THLES.
	CANFD_B_CFDGERFL_THLES = 0x4
	// TX history list entry lost error not detected
	CANFD_B_CFDGERFL_THLES_0 = 0x0
	// TX history list entry lost error detected
	CANFD_B_CFDGERFL_THLES_1 = 0x1
	// Position of CMPOF field.
	CANFD_B_CFDGERFL_CMPOF_Pos = 0x3
	// Bit mask of CMPOF field.
	CANFD_B_CFDGERFL_CMPOF_Msk = 0x8
	// Bit CMPOF.
	CANFD_B_CFDGERFL_CMPOF = 0x8
	// CANFD message payload overflow not detected
	CANFD_B_CFDGERFL_CMPOF_0 = 0x0
	// CANFD message payload overflow detected
	CANFD_B_CFDGERFL_CMPOF_1 = 0x1
	// Position of EEF0 field.
	CANFD_B_CFDGERFL_EEF0_Pos = 0x10
	// Bit mask of EEF0 field.
	CANFD_B_CFDGERFL_EEF0_Msk = 0x10000
	// Bit EEF0.
	CANFD_B_CFDGERFL_EEF0 = 0x10000
	// ECC error not detected during TX-SCAN
	CANFD_B_CFDGERFL_EEF0_0 = 0x0
	// ECC error detected during TX-SCAN
	CANFD_B_CFDGERFL_EEF0_1 = 0x1

	// CFDGTSC: Global Timestamp Counter Register
	// Position of TS field.
	CANFD_B_CFDGTSC_TS_Pos = 0x0
	// Bit mask of TS field.
	CANFD_B_CFDGTSC_TS_Msk = 0xffff

	// CFDGAFLECTR: Global Acceptance Filter List Entry Control Register
	// Position of AFLPN field.
	CANFD_B_CFDGAFLECTR_AFLPN_Pos = 0x0
	// Bit mask of AFLPN field.
	CANFD_B_CFDGAFLECTR_AFLPN_Msk = 0x1
	// Bit AFLPN.
	CANFD_B_CFDGAFLECTR_AFLPN = 0x1
	// Position of AFLDAE field.
	CANFD_B_CFDGAFLECTR_AFLDAE_Pos = 0x8
	// Bit mask of AFLDAE field.
	CANFD_B_CFDGAFLECTR_AFLDAE_Msk = 0x100
	// Bit AFLDAE.
	CANFD_B_CFDGAFLECTR_AFLDAE = 0x100
	// Acceptance Filter List data access disabled
	CANFD_B_CFDGAFLECTR_AFLDAE_0 = 0x0
	// Acceptance Filter List data access enabled
	CANFD_B_CFDGAFLECTR_AFLDAE_1 = 0x1

	// CFDGAFLCFG: Global Acceptance Filter List Configuration Register
	// Position of RNC0 field.
	CANFD_B_CFDGAFLCFG_RNC0_Pos = 0x10
	// Bit mask of RNC0 field.
	CANFD_B_CFDGAFLCFG_RNC0_Msk = 0x3f0000

	// CFDRMNB: RX Message Buffer Number Register
	// Position of NRXMB field.
	CANFD_B_CFDRMNB_NRXMB_Pos = 0x0
	// Bit mask of NRXMB field.
	CANFD_B_CFDRMNB_NRXMB_Msk = 0x3f
	// Position of RMPLS field.
	CANFD_B_CFDRMNB_RMPLS_Pos = 0x8
	// Bit mask of RMPLS field.
	CANFD_B_CFDRMNB_RMPLS_Msk = 0x700
	// 8 bytes
	CANFD_B_CFDRMNB_RMPLS_000 = 0x0
	// 12 bytes
	CANFD_B_CFDRMNB_RMPLS_001 = 0x1
	// 16 bytes
	CANFD_B_CFDRMNB_RMPLS_010 = 0x2
	// 20 bytes
	CANFD_B_CFDRMNB_RMPLS_011 = 0x3
	// 24 bytes
	CANFD_B_CFDRMNB_RMPLS_100 = 0x4
	// 32 bytes
	CANFD_B_CFDRMNB_RMPLS_101 = 0x5
	// 48 bytes
	CANFD_B_CFDRMNB_RMPLS_110 = 0x6
	// 64 bytes
	CANFD_B_CFDRMNB_RMPLS_111 = 0x7

	// CFDRMND: RX Message Buffer New Data Register
	// Position of RMNS field.
	CANFD_B_CFDRMND_RMNS_Pos = 0x0
	// Bit mask of RMNS field.
	CANFD_B_CFDRMND_RMNS_Msk = 0xffffffff
	// New data not stored in corresponding RX message buffer
	CANFD_B_CFDRMND_RMNS_0 = 0x0
	// New data stored in corresponding RX message buffer
	CANFD_B_CFDRMND_RMNS_1 = 0x1

	// CFDRMIEC: RX Message Buffer Interrupt Enable Configuration Register
	// Position of RMIEg field.
	CANFD_B_CFDRMIEC_RMIEg_Pos = 0x0
	// Bit mask of RMIEg field.
	CANFD_B_CFDRMIEC_RMIEg_Msk = 0xffffffff
	// RX Message Buffer Interrupt disabled for corresponding RX message buffer
	CANFD_B_CFDRMIEC_RMIEg_0 = 0x0
	// RX Message Buffer Interrupt enabled for corresponding RX message buffer
	CANFD_B_CFDRMIEC_RMIEg_1 = 0x1

	// CFDRFCC0: RX FIFO Configuration/Control Registers %s
	// Position of RFE field.
	CANFD_B_CFDRFCC_RFE_Pos = 0x0
	// Bit mask of RFE field.
	CANFD_B_CFDRFCC_RFE_Msk = 0x1
	// Bit RFE.
	CANFD_B_CFDRFCC_RFE = 0x1
	// FIFO disabled
	CANFD_B_CFDRFCC_RFE_0 = 0x0
	// FIFO enabled
	CANFD_B_CFDRFCC_RFE_1 = 0x1
	// Position of RFIE field.
	CANFD_B_CFDRFCC_RFIE_Pos = 0x1
	// Bit mask of RFIE field.
	CANFD_B_CFDRFCC_RFIE_Msk = 0x2
	// Bit RFIE.
	CANFD_B_CFDRFCC_RFIE = 0x2
	// FIFO interrupt generation disabled
	CANFD_B_CFDRFCC_RFIE_0 = 0x0
	// FIFO interrupt generation enabled
	CANFD_B_CFDRFCC_RFIE_1 = 0x1
	// Position of RFPLS field.
	CANFD_B_CFDRFCC_RFPLS_Pos = 0x4
	// Bit mask of RFPLS field.
	CANFD_B_CFDRFCC_RFPLS_Msk = 0x70
	// 8 bytes
	CANFD_B_CFDRFCC_RFPLS_000 = 0x0
	// 12 bytes
	CANFD_B_CFDRFCC_RFPLS_001 = 0x1
	// 16 bytes
	CANFD_B_CFDRFCC_RFPLS_010 = 0x2
	// 20 bytes
	CANFD_B_CFDRFCC_RFPLS_011 = 0x3
	// 24 bytes
	CANFD_B_CFDRFCC_RFPLS_100 = 0x4
	// 32 bytes
	CANFD_B_CFDRFCC_RFPLS_101 = 0x5
	// 48 bytes
	CANFD_B_CFDRFCC_RFPLS_110 = 0x6
	// 64 bytes
	CANFD_B_CFDRFCC_RFPLS_111 = 0x7
	// Position of RFDC field.
	CANFD_B_CFDRFCC_RFDC_Pos = 0x8
	// Bit mask of RFDC field.
	CANFD_B_CFDRFCC_RFDC_Msk = 0x700
	// FIFO Depth = 0 message
	CANFD_B_CFDRFCC_RFDC_000 = 0x0
	// FIFO Depth = 4 messages
	CANFD_B_CFDRFCC_RFDC_001 = 0x1
	// FIFO Depth = 8 messages
	CANFD_B_CFDRFCC_RFDC_010 = 0x2
	// FIFO Depth = 16 messages
	CANFD_B_CFDRFCC_RFDC_011 = 0x3
	// FIFO Depth = 32 essages
	CANFD_B_CFDRFCC_RFDC_100 = 0x4
	// FIFO Depth = 48 messages
	CANFD_B_CFDRFCC_RFDC_101 = 0x5
	// Reserved
	CANFD_B_CFDRFCC_RFDC_110 = 0x6
	// Reserved
	CANFD_B_CFDRFCC_RFDC_111 = 0x7
	// Position of RFIM field.
	CANFD_B_CFDRFCC_RFIM_Pos = 0xc
	// Bit mask of RFIM field.
	CANFD_B_CFDRFCC_RFIM_Msk = 0x1000
	// Bit RFIM.
	CANFD_B_CFDRFCC_RFIM = 0x1000
	// Interrupt generated when RX FIFO counter reaches RFIGCV value from values smaller than RFIGCV
	CANFD_B_CFDRFCC_RFIM_0 = 0x0
	// Interrupt generated at the end of every received message storage
	CANFD_B_CFDRFCC_RFIM_1 = 0x1
	// Position of RFIGCV field.
	CANFD_B_CFDRFCC_RFIGCV_Pos = 0xd
	// Bit mask of RFIGCV field.
	CANFD_B_CFDRFCC_RFIGCV_Msk = 0xe000
	// Interrupt generated when FIFO is 1/8th full
	CANFD_B_CFDRFCC_RFIGCV_000 = 0x0
	// Interrupt generated when FIFO is 1/4th full
	CANFD_B_CFDRFCC_RFIGCV_001 = 0x1
	// Interrupt generated when FIFO is 3/8th full
	CANFD_B_CFDRFCC_RFIGCV_010 = 0x2
	// Interrupt generated when FIFO is 1/2 full
	CANFD_B_CFDRFCC_RFIGCV_011 = 0x3
	// Interrupt generated when FIFO is 5/8th full
	CANFD_B_CFDRFCC_RFIGCV_100 = 0x4
	// Interrupt generated when FIFO is 3/4th full
	CANFD_B_CFDRFCC_RFIGCV_101 = 0x5
	// Interrupt generated when FIFO is 7/8th full
	CANFD_B_CFDRFCC_RFIGCV_110 = 0x6
	// Interrupt generated when FIFO is full
	CANFD_B_CFDRFCC_RFIGCV_111 = 0x7

	// CFDRFSTS0: RX FIFO Status Registers %s
	// Position of RFEMP field.
	CANFD_B_CFDRFSTS_RFEMP_Pos = 0x0
	// Bit mask of RFEMP field.
	CANFD_B_CFDRFSTS_RFEMP_Msk = 0x1
	// Bit RFEMP.
	CANFD_B_CFDRFSTS_RFEMP = 0x1
	// FIFO not empty
	CANFD_B_CFDRFSTS_RFEMP_0 = 0x0
	// FIFO empty
	CANFD_B_CFDRFSTS_RFEMP_1 = 0x1
	// Position of RFFLL field.
	CANFD_B_CFDRFSTS_RFFLL_Pos = 0x1
	// Bit mask of RFFLL field.
	CANFD_B_CFDRFSTS_RFFLL_Msk = 0x2
	// Bit RFFLL.
	CANFD_B_CFDRFSTS_RFFLL = 0x2
	// FIFO not full
	CANFD_B_CFDRFSTS_RFFLL_0 = 0x0
	// FIFO full
	CANFD_B_CFDRFSTS_RFFLL_1 = 0x1
	// Position of RFMLT field.
	CANFD_B_CFDRFSTS_RFMLT_Pos = 0x2
	// Bit mask of RFMLT field.
	CANFD_B_CFDRFSTS_RFMLT_Msk = 0x4
	// Bit RFMLT.
	CANFD_B_CFDRFSTS_RFMLT = 0x4
	// No message lost in FIFO
	CANFD_B_CFDRFSTS_RFMLT_0 = 0x0
	// FIFO message lost
	CANFD_B_CFDRFSTS_RFMLT_1 = 0x1
	// Position of RFIF field.
	CANFD_B_CFDRFSTS_RFIF_Pos = 0x3
	// Bit mask of RFIF field.
	CANFD_B_CFDRFSTS_RFIF_Msk = 0x8
	// Bit RFIF.
	CANFD_B_CFDRFSTS_RFIF = 0x8
	// FIFO interrupt condition not satisfied
	CANFD_B_CFDRFSTS_RFIF_0 = 0x0
	// FIFO interrupt condition satisfied
	CANFD_B_CFDRFSTS_RFIF_1 = 0x1
	// Position of RFMC field.
	CANFD_B_CFDRFSTS_RFMC_Pos = 0x8
	// Bit mask of RFMC field.
	CANFD_B_CFDRFSTS_RFMC_Msk = 0x3f00

	// CFDRFPCTR0: RX FIFO Pointer Control Registers %s
	// Position of RFPC field.
	CANFD_B_CFDRFPCTR_RFPC_Pos = 0x0
	// Bit mask of RFPC field.
	CANFD_B_CFDRFPCTR_RFPC_Msk = 0xff

	// CFDCFCC: Common FIFO Configuration/Control Register
	// Position of CFE field.
	CANFD_B_CFDCFCC_CFE_Pos = 0x0
	// Bit mask of CFE field.
	CANFD_B_CFDCFCC_CFE_Msk = 0x1
	// Bit CFE.
	CANFD_B_CFDCFCC_CFE = 0x1
	// FIFO disabled
	CANFD_B_CFDCFCC_CFE_0 = 0x0
	// FIFO enabled
	CANFD_B_CFDCFCC_CFE_1 = 0x1
	// Position of CFRXIE field.
	CANFD_B_CFDCFCC_CFRXIE_Pos = 0x1
	// Bit mask of CFRXIE field.
	CANFD_B_CFDCFCC_CFRXIE_Msk = 0x2
	// Bit CFRXIE.
	CANFD_B_CFDCFCC_CFRXIE = 0x2
	// FIFO interrupt generation disabled for Frame RX
	CANFD_B_CFDCFCC_CFRXIE_0 = 0x0
	// FIFO interrupt generation enabled for Frame RX
	CANFD_B_CFDCFCC_CFRXIE_1 = 0x1
	// Position of CFTXIE field.
	CANFD_B_CFDCFCC_CFTXIE_Pos = 0x2
	// Bit mask of CFTXIE field.
	CANFD_B_CFDCFCC_CFTXIE_Msk = 0x4
	// Bit CFTXIE.
	CANFD_B_CFDCFCC_CFTXIE = 0x4
	// FIFO interrupt generation disabled for Frame TX
	CANFD_B_CFDCFCC_CFTXIE_0 = 0x0
	// FIFO interrupt generation enabled for Frame TX
	CANFD_B_CFDCFCC_CFTXIE_1 = 0x1
	// Position of CFPLS field.
	CANFD_B_CFDCFCC_CFPLS_Pos = 0x4
	// Bit mask of CFPLS field.
	CANFD_B_CFDCFCC_CFPLS_Msk = 0x70
	// 8 bytes
	CANFD_B_CFDCFCC_CFPLS_000 = 0x0
	// 12 bytes
	CANFD_B_CFDCFCC_CFPLS_001 = 0x1
	// 16 bytes
	CANFD_B_CFDCFCC_CFPLS_010 = 0x2
	// 20 bytes
	CANFD_B_CFDCFCC_CFPLS_011 = 0x3
	// 24 bytes
	CANFD_B_CFDCFCC_CFPLS_100 = 0x4
	// 32 bytes
	CANFD_B_CFDCFCC_CFPLS_101 = 0x5
	// 48 bytes
	CANFD_B_CFDCFCC_CFPLS_110 = 0x6
	// 64 bytes
	CANFD_B_CFDCFCC_CFPLS_111 = 0x7
	// Position of CFM field.
	CANFD_B_CFDCFCC_CFM_Pos = 0x8
	// Bit mask of CFM field.
	CANFD_B_CFDCFCC_CFM_Msk = 0x100
	// Bit CFM.
	CANFD_B_CFDCFCC_CFM = 0x100
	// RX FIFO mode
	CANFD_B_CFDCFCC_CFM_0 = 0x0
	// TX FIFO mode
	CANFD_B_CFDCFCC_CFM_1 = 0x1
	// Position of CFITSS field.
	CANFD_B_CFDCFCC_CFITSS_Pos = 0xa
	// Bit mask of CFITSS field.
	CANFD_B_CFDCFCC_CFITSS_Msk = 0x400
	// Bit CFITSS.
	CANFD_B_CFDCFCC_CFITSS = 0x400
	// Reference clock (× 1 / × 10 period)
	CANFD_B_CFDCFCC_CFITSS_0 = 0x0
	// Bit time clock of related channel (FIFO is linked to fixed channel)
	CANFD_B_CFDCFCC_CFITSS_1 = 0x1
	// Position of CFITR field.
	CANFD_B_CFDCFCC_CFITR_Pos = 0xb
	// Bit mask of CFITR field.
	CANFD_B_CFDCFCC_CFITR_Msk = 0x800
	// Bit CFITR.
	CANFD_B_CFDCFCC_CFITR = 0x800
	// Reference clock period × 1
	CANFD_B_CFDCFCC_CFITR_0 = 0x0
	// Reference clock period × 10
	CANFD_B_CFDCFCC_CFITR_1 = 0x1
	// Position of CFIM field.
	CANFD_B_CFDCFCC_CFIM_Pos = 0xc
	// Bit mask of CFIM field.
	CANFD_B_CFDCFCC_CFIM_Msk = 0x1000
	// Bit CFIM.
	CANFD_B_CFDCFCC_CFIM = 0x1000
	// RX FIFO mode: RX interrupt generated when Common FIFO counter reaches CFIGCV value from a lower value TX FIFO mode: TX interrupt generated when Common FIFO transmits the last message successfully
	CANFD_B_CFDCFCC_CFIM_0 = 0x0
	// RX FIFO mode: RX interrupt generated at the end of every received message storage TX FIFO mode: interrupt generated for every successfully transmitted message
	CANFD_B_CFDCFCC_CFIM_1 = 0x1
	// Position of CFIGCV field.
	CANFD_B_CFDCFCC_CFIGCV_Pos = 0xd
	// Bit mask of CFIGCV field.
	CANFD_B_CFDCFCC_CFIGCV_Msk = 0xe000
	// Interrupt generated when FIFO is 1/8th full
	CANFD_B_CFDCFCC_CFIGCV_000 = 0x0
	// Interrupt generated when FIFO is 1/4th full
	CANFD_B_CFDCFCC_CFIGCV_001 = 0x1
	// Interrupt generated when FIFO is 3/8th full
	CANFD_B_CFDCFCC_CFIGCV_010 = 0x2
	// Interrupt generated when FIFO is 1/2 full
	CANFD_B_CFDCFCC_CFIGCV_011 = 0x3
	// Interrupt generated when FIFO is 5/8th full
	CANFD_B_CFDCFCC_CFIGCV_100 = 0x4
	// Interrupt generated when FIFO is 3/4th full
	CANFD_B_CFDCFCC_CFIGCV_101 = 0x5
	// Interrupt generated when FIFO is 7/8th full
	CANFD_B_CFDCFCC_CFIGCV_110 = 0x6
	// Interrupt generated when FIFO is full
	CANFD_B_CFDCFCC_CFIGCV_111 = 0x7
	// Position of CFTML field.
	CANFD_B_CFDCFCC_CFTML_Pos = 0x10
	// Bit mask of CFTML field.
	CANFD_B_CFDCFCC_CFTML_Msk = 0x30000
	// Position of CFDC field.
	CANFD_B_CFDCFCC_CFDC_Pos = 0x15
	// Bit mask of CFDC field.
	CANFD_B_CFDCFCC_CFDC_Msk = 0xe00000
	// FIFO Depth = 0 message
	CANFD_B_CFDCFCC_CFDC_000 = 0x0
	// FIFO Depth = 4 messages
	CANFD_B_CFDCFCC_CFDC_001 = 0x1
	// FIFO Depth = 8 messages
	CANFD_B_CFDCFCC_CFDC_010 = 0x2
	// FIFO Depth = 16 messages
	CANFD_B_CFDCFCC_CFDC_011 = 0x3
	// FIFO Depth = 32 messages
	CANFD_B_CFDCFCC_CFDC_100 = 0x4
	// FIFO Depth = 48 messages
	CANFD_B_CFDCFCC_CFDC_101 = 0x5
	// FIFO Depth = Reserved
	CANFD_B_CFDCFCC_CFDC_110 = 0x6
	// FIFO Depth = Reserved
	CANFD_B_CFDCFCC_CFDC_111 = 0x7
	// Position of CFITT field.
	CANFD_B_CFDCFCC_CFITT_Pos = 0x18
	// Bit mask of CFITT field.
	CANFD_B_CFDCFCC_CFITT_Msk = 0xff000000

	// CFDCFSTS: Common FIFO Status Register
	// Position of CFEMP field.
	CANFD_B_CFDCFSTS_CFEMP_Pos = 0x0
	// Bit mask of CFEMP field.
	CANFD_B_CFDCFSTS_CFEMP_Msk = 0x1
	// Bit CFEMP.
	CANFD_B_CFDCFSTS_CFEMP = 0x1
	// FIFO not empty
	CANFD_B_CFDCFSTS_CFEMP_0 = 0x0
	// FIFO empty
	CANFD_B_CFDCFSTS_CFEMP_1 = 0x1
	// Position of CFFLL field.
	CANFD_B_CFDCFSTS_CFFLL_Pos = 0x1
	// Bit mask of CFFLL field.
	CANFD_B_CFDCFSTS_CFFLL_Msk = 0x2
	// Bit CFFLL.
	CANFD_B_CFDCFSTS_CFFLL = 0x2
	// FIFO not full
	CANFD_B_CFDCFSTS_CFFLL_0 = 0x0
	// FIFO full
	CANFD_B_CFDCFSTS_CFFLL_1 = 0x1
	// Position of CFMLT field.
	CANFD_B_CFDCFSTS_CFMLT_Pos = 0x2
	// Bit mask of CFMLT field.
	CANFD_B_CFDCFSTS_CFMLT_Msk = 0x4
	// Bit CFMLT.
	CANFD_B_CFDCFSTS_CFMLT = 0x4
	// Number of message lost in FIFO
	CANFD_B_CFDCFSTS_CFMLT_0 = 0x0
	// FIFO message lost
	CANFD_B_CFDCFSTS_CFMLT_1 = 0x1
	// Position of CFRXIF field.
	CANFD_B_CFDCFSTS_CFRXIF_Pos = 0x3
	// Bit mask of CFRXIF field.
	CANFD_B_CFDCFSTS_CFRXIF_Msk = 0x8
	// Bit CFRXIF.
	CANFD_B_CFDCFSTS_CFRXIF = 0x8
	// FIFO interrupt condition not satisfied after frame reception
	CANFD_B_CFDCFSTS_CFRXIF_0 = 0x0
	// FIFO interrupt condition satisfied after frame reception
	CANFD_B_CFDCFSTS_CFRXIF_1 = 0x1
	// Position of CFTXIF field.
	CANFD_B_CFDCFSTS_CFTXIF_Pos = 0x4
	// Bit mask of CFTXIF field.
	CANFD_B_CFDCFSTS_CFTXIF_Msk = 0x10
	// Bit CFTXIF.
	CANFD_B_CFDCFSTS_CFTXIF = 0x10
	// FIFO interrupt condition not satisfied after frame transmission
	CANFD_B_CFDCFSTS_CFTXIF_0 = 0x0
	// FIFO Interrupt condition satisfied after frame transmission
	CANFD_B_CFDCFSTS_CFTXIF_1 = 0x1
	// Position of CFMC field.
	CANFD_B_CFDCFSTS_CFMC_Pos = 0x8
	// Bit mask of CFMC field.
	CANFD_B_CFDCFSTS_CFMC_Msk = 0x3f00

	// CFDCFPCTR: Common FIFO Pointer Control Register
	// Position of CFPC field.
	CANFD_B_CFDCFPCTR_CFPC_Pos = 0x0
	// Bit mask of CFPC field.
	CANFD_B_CFDCFPCTR_CFPC_Msk = 0xff

	// CFDFESTS: FIFO Empty Status Register
	// Position of RFXEMP field.
	CANFD_B_CFDFESTS_RFXEMP_Pos = 0x0
	// Bit mask of RFXEMP field.
	CANFD_B_CFDFESTS_RFXEMP_Msk = 0x3
	// Corresponding FIFO not empty
	CANFD_B_CFDFESTS_RFXEMP_0 = 0x0
	// Corresponding FIFO empty
	CANFD_B_CFDFESTS_RFXEMP_1 = 0x1
	// Position of CFEMP field.
	CANFD_B_CFDFESTS_CFEMP_Pos = 0x8
	// Bit mask of CFEMP field.
	CANFD_B_CFDFESTS_CFEMP_Msk = 0x100
	// Bit CFEMP.
	CANFD_B_CFDFESTS_CFEMP = 0x100
	// Corresponding FIFO not empty
	CANFD_B_CFDFESTS_CFEMP_0 = 0x0
	// Corresponding FIFO empty
	CANFD_B_CFDFESTS_CFEMP_1 = 0x1

	// CFDFFSTS: FIFO Full Status Register
	// Position of RFXFLL field.
	CANFD_B_CFDFFSTS_RFXFLL_Pos = 0x0
	// Bit mask of RFXFLL field.
	CANFD_B_CFDFFSTS_RFXFLL_Msk = 0x3
	// Corresponding FIFO not full
	CANFD_B_CFDFFSTS_RFXFLL_0 = 0x0
	// Corresponding FIFO full
	CANFD_B_CFDFFSTS_RFXFLL_1 = 0x1
	// Position of CFFLL field.
	CANFD_B_CFDFFSTS_CFFLL_Pos = 0x8
	// Bit mask of CFFLL field.
	CANFD_B_CFDFFSTS_CFFLL_Msk = 0x100
	// Bit CFFLL.
	CANFD_B_CFDFFSTS_CFFLL = 0x100
	// Corresponding FIFO not full
	CANFD_B_CFDFFSTS_CFFLL_0 = 0x0
	// Corresponding FIFO full
	CANFD_B_CFDFFSTS_CFFLL_1 = 0x1

	// CFDFMSTS: FIFO Message Lost Status Register
	// Position of RFXMLT field.
	CANFD_B_CFDFMSTS_RFXMLT_Pos = 0x0
	// Bit mask of RFXMLT field.
	CANFD_B_CFDFMSTS_RFXMLT_Msk = 0x3
	// Corresponding FIFO Message Lost flag not set
	CANFD_B_CFDFMSTS_RFXMLT_0 = 0x0
	// Corresponding FIFO Message Lost flag set
	CANFD_B_CFDFMSTS_RFXMLT_1 = 0x1
	// Position of CFMLT field.
	CANFD_B_CFDFMSTS_CFMLT_Pos = 0x8
	// Bit mask of CFMLT field.
	CANFD_B_CFDFMSTS_CFMLT_Msk = 0x100
	// Bit CFMLT.
	CANFD_B_CFDFMSTS_CFMLT = 0x100
	// Corresponding FIFO Message Lost flag not set
	CANFD_B_CFDFMSTS_CFMLT_0 = 0x0
	// Corresponding FIFO Message Lost flag set
	CANFD_B_CFDFMSTS_CFMLT_1 = 0x1

	// CFDRFISTS: RX FIFO Interrupt Flag Status Register
	// Position of RFXIF field.
	CANFD_B_CFDRFISTS_RFXIF_Pos = 0x0
	// Bit mask of RFXIF field.
	CANFD_B_CFDRFISTS_RFXIF_Msk = 0x3
	// Corresponding RX FIFO Interrupt flag not set
	CANFD_B_CFDRFISTS_RFXIF_0 = 0x0
	// Corresponding RX FIFO Interrupt flag set
	CANFD_B_CFDRFISTS_RFXIF_1 = 0x1

	// CFDTMC0: TX Message Buffer Control Registers %s
	// Position of TMTR field.
	CANFD_B_CFDTMC_TMTR_Pos = 0x0
	// Bit mask of TMTR field.
	CANFD_B_CFDTMC_TMTR_Msk = 0x1
	// Bit TMTR.
	CANFD_B_CFDTMC_TMTR = 0x1
	// TX Message buffer transmission not requested
	CANFD_B_CFDTMC_TMTR_0 = 0x0
	// TX message buffer transmission requested
	CANFD_B_CFDTMC_TMTR_1 = 0x1
	// Position of TMTAR field.
	CANFD_B_CFDTMC_TMTAR_Pos = 0x1
	// Bit mask of TMTAR field.
	CANFD_B_CFDTMC_TMTAR_Msk = 0x2
	// Bit TMTAR.
	CANFD_B_CFDTMC_TMTAR = 0x2
	// TX message buffer transmission request abort not requested
	CANFD_B_CFDTMC_TMTAR_0 = 0x0
	// TX message buffer transmission request abort requested
	CANFD_B_CFDTMC_TMTAR_1 = 0x1
	// Position of TMOM field.
	CANFD_B_CFDTMC_TMOM_Pos = 0x2
	// Bit mask of TMOM field.
	CANFD_B_CFDTMC_TMOM_Msk = 0x4
	// Bit TMOM.
	CANFD_B_CFDTMC_TMOM = 0x4
	// TX message buffer not configured in one-shot mode
	CANFD_B_CFDTMC_TMOM_0 = 0x0
	// TX message buffer configured in one-shot mode
	CANFD_B_CFDTMC_TMOM_1 = 0x1

	// CFDTMSTS0: TX Message Buffer Status Registers %s
	// Position of TMTSTS field.
	CANFD_B_CFDTMSTS_TMTSTS_Pos = 0x0
	// Bit mask of TMTSTS field.
	CANFD_B_CFDTMSTS_TMTSTS_Msk = 0x1
	// Bit TMTSTS.
	CANFD_B_CFDTMSTS_TMTSTS = 0x1
	// No on-going transmission
	CANFD_B_CFDTMSTS_TMTSTS_0 = 0x0
	// On-going transmission
	CANFD_B_CFDTMSTS_TMTSTS_1 = 0x1
	// Position of TMTRF field.
	CANFD_B_CFDTMSTS_TMTRF_Pos = 0x1
	// Bit mask of TMTRF field.
	CANFD_B_CFDTMSTS_TMTRF_Msk = 0x6
	// No result
	CANFD_B_CFDTMSTS_TMTRF_00 = 0x0
	// Transmission aborted from the TX message buffer
	CANFD_B_CFDTMSTS_TMTRF_01 = 0x1
	// Transmission successful from the TX message buffer and transmission abort was not requested
	CANFD_B_CFDTMSTS_TMTRF_10 = 0x2
	// Transmission successful from the TX message buffer and transmission abort was requested
	CANFD_B_CFDTMSTS_TMTRF_11 = 0x3
	// Position of TMTRM field.
	CANFD_B_CFDTMSTS_TMTRM_Pos = 0x3
	// Bit mask of TMTRM field.
	CANFD_B_CFDTMSTS_TMTRM_Msk = 0x8
	// Bit TMTRM.
	CANFD_B_CFDTMSTS_TMTRM = 0x8
	// TX message buffer transmission not requested
	CANFD_B_CFDTMSTS_TMTRM_0 = 0x0
	// TX message buffer transmission requested
	CANFD_B_CFDTMSTS_TMTRM_1 = 0x1
	// Position of TMTARM field.
	CANFD_B_CFDTMSTS_TMTARM_Pos = 0x4
	// Bit mask of TMTARM field.
	CANFD_B_CFDTMSTS_TMTARM_Msk = 0x10
	// Bit TMTARM.
	CANFD_B_CFDTMSTS_TMTARM = 0x10
	// TX message buffer transmission request abort not requested
	CANFD_B_CFDTMSTS_TMTARM_0 = 0x0
	// TX message buffer transmission request abort requested
	CANFD_B_CFDTMSTS_TMTARM_1 = 0x1

	// CFDTMTRSTS: TX Message Buffer Transmission Request Status Register
	// Position of CFDTMTRSTS field.
	CANFD_B_CFDTMTRSTS_CFDTMTRSTS_Pos = 0x0
	// Bit mask of CFDTMTRSTS field.
	CANFD_B_CFDTMTRSTS_CFDTMTRSTS_Msk = 0xf
	// Transmission not requested for corresponding TX message buffer
	CANFD_B_CFDTMTRSTS_CFDTMTRSTS_0 = 0x0
	// Transmission requested for corresponding TX message buffer
	CANFD_B_CFDTMTRSTS_CFDTMTRSTS_1 = 0x1

	// CFDTMTARSTS: TX Message Buffer Transmission Abort Request Status Register
	// Position of CFDTMTARSTS field.
	CANFD_B_CFDTMTARSTS_CFDTMTARSTS_Pos = 0x0
	// Bit mask of CFDTMTARSTS field.
	CANFD_B_CFDTMTARSTS_CFDTMTARSTS_Msk = 0xf
	// Transmission abort not requested for corresponding TX message buffer
	CANFD_B_CFDTMTARSTS_CFDTMTARSTS_0 = 0x0
	// Transmission abort requested for corresponding TX message buffer
	CANFD_B_CFDTMTARSTS_CFDTMTARSTS_1 = 0x1

	// CFDTMTCSTS: TX Message Buffer Transmission Completion Status Register
	// Position of CFDTMTCSTS field.
	CANFD_B_CFDTMTCSTS_CFDTMTCSTS_Pos = 0x0
	// Bit mask of CFDTMTCSTS field.
	CANFD_B_CFDTMTCSTS_CFDTMTCSTS_Msk = 0xf
	// Transmission not complete for corresponding TX message buffer
	CANFD_B_CFDTMTCSTS_CFDTMTCSTS_0 = 0x0
	// Transmission completed for corresponding TX message buffer
	CANFD_B_CFDTMTCSTS_CFDTMTCSTS_1 = 0x1

	// CFDTMTASTS: TX Message Buffer Transmission Abort Status Register
	// Position of CFDTMTASTS field.
	CANFD_B_CFDTMTASTS_CFDTMTASTS_Pos = 0x0
	// Bit mask of CFDTMTASTS field.
	CANFD_B_CFDTMTASTS_CFDTMTASTS_Msk = 0xf
	// Transmission not aborted for corresponding TX message buffer
	CANFD_B_CFDTMTASTS_CFDTMTASTS_0 = 0x0
	// Transmission aborted for corresponding TX message buffer
	CANFD_B_CFDTMTASTS_CFDTMTASTS_1 = 0x1

	// CFDTMIEC: TX Message Buffer Interrupt Enable Configuration Register
	// Position of TMIEg field.
	CANFD_B_CFDTMIEC_TMIEg_Pos = 0x0
	// Bit mask of TMIEg field.
	CANFD_B_CFDTMIEC_TMIEg_Msk = 0xf
	// TX message buffer interrupt disabled for corresponding TX message buffer
	CANFD_B_CFDTMIEC_TMIEg_0 = 0x0
	// TX message buffer interrupt enabled for corresponding TX message buffer
	CANFD_B_CFDTMIEC_TMIEg_1 = 0x1

	// CFDTXQCC: TX Queue Configuration/Control Register
	// Position of TXQE field.
	CANFD_B_CFDTXQCC_TXQE_Pos = 0x0
	// Bit mask of TXQE field.
	CANFD_B_CFDTXQCC_TXQE_Msk = 0x1
	// Bit TXQE.
	CANFD_B_CFDTXQCC_TXQE = 0x1
	// TX Queue disabled
	CANFD_B_CFDTXQCC_TXQE_0 = 0x0
	// TX Queue enabled
	CANFD_B_CFDTXQCC_TXQE_1 = 0x1
	// Position of TXQTXIE field.
	CANFD_B_CFDTXQCC_TXQTXIE_Pos = 0x5
	// Bit mask of TXQTXIE field.
	CANFD_B_CFDTXQCC_TXQTXIE_Msk = 0x20
	// Bit TXQTXIE.
	CANFD_B_CFDTXQCC_TXQTXIE = 0x20
	// TX Queue TX interrupt disabled
	CANFD_B_CFDTXQCC_TXQTXIE_0 = 0x0
	// TX Queue TX interrupt enabled
	CANFD_B_CFDTXQCC_TXQTXIE_1 = 0x1
	// Position of TXQIM field.
	CANFD_B_CFDTXQCC_TXQIM_Pos = 0x7
	// Bit mask of TXQIM field.
	CANFD_B_CFDTXQCC_TXQIM_Msk = 0x80
	// Bit TXQIM.
	CANFD_B_CFDTXQCC_TXQIM = 0x80
	// When the last message is successfully transmitted
	CANFD_B_CFDTXQCC_TXQIM_0 = 0x0
	// At every successful transmission
	CANFD_B_CFDTXQCC_TXQIM_1 = 0x1
	// Position of TXQDC field.
	CANFD_B_CFDTXQCC_TXQDC_Pos = 0x8
	// Bit mask of TXQDC field.
	CANFD_B_CFDTXQCC_TXQDC_Msk = 0x300
	// 0 messages
	CANFD_B_CFDTXQCC_TXQDC_0x00 = 0x0
	// Reserved
	CANFD_B_CFDTXQCC_TXQDC_0x01 = 0x1
	// 3 messages
	CANFD_B_CFDTXQCC_TXQDC_0x10 = 0x10
	// 4 messages
	CANFD_B_CFDTXQCC_TXQDC_0x11 = 0x11

	// CFDTXQSTS: TX Queue Status Register
	// Position of TXQEMP field.
	CANFD_B_CFDTXQSTS_TXQEMP_Pos = 0x0
	// Bit mask of TXQEMP field.
	CANFD_B_CFDTXQSTS_TXQEMP_Msk = 0x1
	// Bit TXQEMP.
	CANFD_B_CFDTXQSTS_TXQEMP = 0x1
	// TX Queue not empty
	CANFD_B_CFDTXQSTS_TXQEMP_0 = 0x0
	// TX Queue empty
	CANFD_B_CFDTXQSTS_TXQEMP_1 = 0x1
	// Position of TXQFLL field.
	CANFD_B_CFDTXQSTS_TXQFLL_Pos = 0x1
	// Bit mask of TXQFLL field.
	CANFD_B_CFDTXQSTS_TXQFLL_Msk = 0x2
	// Bit TXQFLL.
	CANFD_B_CFDTXQSTS_TXQFLL = 0x2
	// TX Queue not full
	CANFD_B_CFDTXQSTS_TXQFLL_0 = 0x0
	// TX Queue full
	CANFD_B_CFDTXQSTS_TXQFLL_1 = 0x1
	// Position of TXQTXIF field.
	CANFD_B_CFDTXQSTS_TXQTXIF_Pos = 0x2
	// Bit mask of TXQTXIF field.
	CANFD_B_CFDTXQSTS_TXQTXIF_Msk = 0x4
	// Bit TXQTXIF.
	CANFD_B_CFDTXQSTS_TXQTXIF = 0x4
	// TX Queue interrupt condition not satisfied after a frame TX
	CANFD_B_CFDTXQSTS_TXQTXIF_0 = 0x0
	// TX Queue interrupt condition satisfied after a frame TX
	CANFD_B_CFDTXQSTS_TXQTXIF_1 = 0x1
	// Position of TXQMC field.
	CANFD_B_CFDTXQSTS_TXQMC_Pos = 0x8
	// Bit mask of TXQMC field.
	CANFD_B_CFDTXQSTS_TXQMC_Msk = 0x700

	// CFDTXQPCTR: TX Queue Pointer Control Register
	// Position of TXQPC field.
	CANFD_B_CFDTXQPCTR_TXQPC_Pos = 0x0
	// Bit mask of TXQPC field.
	CANFD_B_CFDTXQPCTR_TXQPC_Msk = 0xff

	// CFDTHLCC: TX History List Configuration/Control Register
	// Position of THLE field.
	CANFD_B_CFDTHLCC_THLE_Pos = 0x0
	// Bit mask of THLE field.
	CANFD_B_CFDTHLCC_THLE_Msk = 0x1
	// Bit THLE.
	CANFD_B_CFDTHLCC_THLE = 0x1
	// TX History List disabled
	CANFD_B_CFDTHLCC_THLE_0 = 0x0
	// TX History List enabled
	CANFD_B_CFDTHLCC_THLE_1 = 0x1
	// Position of THLIE field.
	CANFD_B_CFDTHLCC_THLIE_Pos = 0x8
	// Bit mask of THLIE field.
	CANFD_B_CFDTHLCC_THLIE_Msk = 0x100
	// Bit THLIE.
	CANFD_B_CFDTHLCC_THLIE = 0x100
	// TX History List Interrupt disabled
	CANFD_B_CFDTHLCC_THLIE_0 = 0x0
	// TX History List Interrupt enabled
	CANFD_B_CFDTHLCC_THLIE_1 = 0x1
	// Position of THLIM field.
	CANFD_B_CFDTHLCC_THLIM_Pos = 0x9
	// Bit mask of THLIM field.
	CANFD_B_CFDTHLCC_THLIM_Msk = 0x200
	// Bit THLIM.
	CANFD_B_CFDTHLCC_THLIM = 0x200
	// Interrupt generated if TX History List level reaches ¾ of the TX History List depth
	CANFD_B_CFDTHLCC_THLIM_0 = 0x0
	// Interrupt generated for every successfully stored entry
	CANFD_B_CFDTHLCC_THLIM_1 = 0x1
	// Position of THLDTE field.
	CANFD_B_CFDTHLCC_THLDTE_Pos = 0xa
	// Bit mask of THLDTE field.
	CANFD_B_CFDTHLCC_THLDTE_Msk = 0x400
	// Bit THLDTE.
	CANFD_B_CFDTHLCC_THLDTE = 0x400
	// TX FIFO + TX Queue
	CANFD_B_CFDTHLCC_THLDTE_0 = 0x0
	// Flat TX MB + TX FIFO + TX Queue
	CANFD_B_CFDTHLCC_THLDTE_1 = 0x1

	// CFDTHLSTS: TX History List Status Register
	// Position of THLEMP field.
	CANFD_B_CFDTHLSTS_THLEMP_Pos = 0x0
	// Bit mask of THLEMP field.
	CANFD_B_CFDTHLSTS_THLEMP_Msk = 0x1
	// Bit THLEMP.
	CANFD_B_CFDTHLSTS_THLEMP = 0x1
	// TX History List not empty
	CANFD_B_CFDTHLSTS_THLEMP_0 = 0x0
	// TX History List empty
	CANFD_B_CFDTHLSTS_THLEMP_1 = 0x1
	// Position of THLFLL field.
	CANFD_B_CFDTHLSTS_THLFLL_Pos = 0x1
	// Bit mask of THLFLL field.
	CANFD_B_CFDTHLSTS_THLFLL_Msk = 0x2
	// Bit THLFLL.
	CANFD_B_CFDTHLSTS_THLFLL = 0x2
	// TX History List not full
	CANFD_B_CFDTHLSTS_THLFLL_0 = 0x0
	// TX History List full
	CANFD_B_CFDTHLSTS_THLFLL_1 = 0x1
	// Position of THLELT field.
	CANFD_B_CFDTHLSTS_THLELT_Pos = 0x2
	// Bit mask of THLELT field.
	CANFD_B_CFDTHLSTS_THLELT_Msk = 0x4
	// Bit THLELT.
	CANFD_B_CFDTHLSTS_THLELT = 0x4
	// No entry lost in TX History List
	CANFD_B_CFDTHLSTS_THLELT_0 = 0x0
	// TX History List entry Lost
	CANFD_B_CFDTHLSTS_THLELT_1 = 0x1
	// Position of THLIF field.
	CANFD_B_CFDTHLSTS_THLIF_Pos = 0x3
	// Bit mask of THLIF field.
	CANFD_B_CFDTHLSTS_THLIF_Msk = 0x8
	// Bit THLIF.
	CANFD_B_CFDTHLSTS_THLIF = 0x8
	// TX History List interrupt condition not satisfied
	CANFD_B_CFDTHLSTS_THLIF_0 = 0x0
	// TX History List interrupt condition satisfied
	CANFD_B_CFDTHLSTS_THLIF_1 = 0x1
	// Position of THLMC field.
	CANFD_B_CFDTHLSTS_THLMC_Pos = 0x8
	// Bit mask of THLMC field.
	CANFD_B_CFDTHLSTS_THLMC_Msk = 0xf00

	// CFDTHLPCTR: TX History List Pointer Control Register
	// Position of THLPC field.
	CANFD_B_CFDTHLPCTR_THLPC_Pos = 0x0
	// Bit mask of THLPC field.
	CANFD_B_CFDTHLPCTR_THLPC_Msk = 0xff

	// CFDGTINTSTS: Global TX Interrupt Status Register
	// Position of TSIF0 field.
	CANFD_B_CFDGTINTSTS_TSIF0_Pos = 0x0
	// Bit mask of TSIF0 field.
	CANFD_B_CFDGTINTSTS_TSIF0_Msk = 0x1
	// Bit TSIF0.
	CANFD_B_CFDGTINTSTS_TSIF0 = 0x1
	// Channel n TX Successful Interrupt flag not set
	CANFD_B_CFDGTINTSTS_TSIF0_0 = 0x0
	// Channel n TX Successful Interrupt flag set
	CANFD_B_CFDGTINTSTS_TSIF0_1 = 0x1
	// Position of TAI0 field.
	CANFD_B_CFDGTINTSTS_TAI0_Pos = 0x1
	// Bit mask of TAI0 field.
	CANFD_B_CFDGTINTSTS_TAI0_Msk = 0x2
	// Bit TAI0.
	CANFD_B_CFDGTINTSTS_TAI0 = 0x2
	// Channel n TX Abort Interrupt flag not set
	CANFD_B_CFDGTINTSTS_TAI0_0 = 0x0
	// Channel n TX Abort Interrupt flag set
	CANFD_B_CFDGTINTSTS_TAI0_1 = 0x1
	// Position of TQIF0 field.
	CANFD_B_CFDGTINTSTS_TQIF0_Pos = 0x2
	// Bit mask of TQIF0 field.
	CANFD_B_CFDGTINTSTS_TQIF0_Msk = 0x4
	// Bit TQIF0.
	CANFD_B_CFDGTINTSTS_TQIF0 = 0x4
	// Channel n TX Queue Interrupt flag not set
	CANFD_B_CFDGTINTSTS_TQIF0_0 = 0x0
	// Channel n TX Queue Interrupt flag set
	CANFD_B_CFDGTINTSTS_TQIF0_1 = 0x1
	// Position of CFTIF0 field.
	CANFD_B_CFDGTINTSTS_CFTIF0_Pos = 0x3
	// Bit mask of CFTIF0 field.
	CANFD_B_CFDGTINTSTS_CFTIF0_Msk = 0x8
	// Bit CFTIF0.
	CANFD_B_CFDGTINTSTS_CFTIF0 = 0x8
	// Channel n COM FIFO TX Mode Interrupt flag not set
	CANFD_B_CFDGTINTSTS_CFTIF0_0 = 0x0
	// Channel n COM FIFO TX Mode Interrupt flag set
	CANFD_B_CFDGTINTSTS_CFTIF0_1 = 0x1
	// Position of THIF0 field.
	CANFD_B_CFDGTINTSTS_THIF0_Pos = 0x4
	// Bit mask of THIF0 field.
	CANFD_B_CFDGTINTSTS_THIF0_Msk = 0x10
	// Bit THIF0.
	CANFD_B_CFDGTINTSTS_THIF0 = 0x10
	// Channel n TX History List Interrupt flag not set
	CANFD_B_CFDGTINTSTS_THIF0_0 = 0x0
	// Channel n TX History List Interrupt flag set
	CANFD_B_CFDGTINTSTS_THIF0_1 = 0x1

	// CFDGTSTCFG: Global Test Configuration Register
	// Position of RTMPS field.
	CANFD_B_CFDGTSTCFG_RTMPS_Pos = 0x10
	// Bit mask of RTMPS field.
	CANFD_B_CFDGTSTCFG_RTMPS_Msk = 0xf0000

	// CFDGTSTCTR: Global Test Control Register
	// Position of RTME field.
	CANFD_B_CFDGTSTCTR_RTME_Pos = 0x2
	// Bit mask of RTME field.
	CANFD_B_CFDGTSTCTR_RTME_Msk = 0x4
	// Bit RTME.
	CANFD_B_CFDGTSTCTR_RTME = 0x4
	// RAM test mode disabled
	CANFD_B_CFDGTSTCTR_RTME_0 = 0x0
	// RAM test mode enabled
	CANFD_B_CFDGTSTCTR_RTME_1 = 0x1

	// CFDGFDCFG: Global FD Configuration Register
	// Position of RPED field.
	CANFD_B_CFDGFDCFG_RPED_Pos = 0x0
	// Bit mask of RPED field.
	CANFD_B_CFDGFDCFG_RPED_Msk = 0x1
	// Bit RPED.
	CANFD_B_CFDGFDCFG_RPED = 0x1
	// Protocol exception event detection enabled
	CANFD_B_CFDGFDCFG_RPED_0 = 0x0
	// Protocol exception event detection disabled
	CANFD_B_CFDGFDCFG_RPED_1 = 0x1
	// Position of TSCCFG field.
	CANFD_B_CFDGFDCFG_TSCCFG_Pos = 0x8
	// Bit mask of TSCCFG field.
	CANFD_B_CFDGFDCFG_TSCCFG_Msk = 0x300
	// Timestamp capture at the sample point of SOF (start of frame)
	CANFD_B_CFDGFDCFG_TSCCFG_00 = 0x0
	// Timestamp capture at frame valid indication
	CANFD_B_CFDGFDCFG_TSCCFG_01 = 0x1
	// Timestamp capture at the sample point of RES bit
	CANFD_B_CFDGFDCFG_TSCCFG_10 = 0x2
	// Reserved
	CANFD_B_CFDGFDCFG_TSCCFG_11 = 0x3

	// CFDGLOCKK: Global Lock Key Register
	// Position of LOCK field.
	CANFD_B_CFDGLOCKK_LOCK_Pos = 0x0
	// Bit mask of LOCK field.
	CANFD_B_CFDGLOCKK_LOCK_Msk = 0xffff

	// CFDGAFLIGNENT: Global AFL Ignore Entry Register
	// Position of IRN field.
	CANFD_B_CFDGAFLIGNENT_IRN_Pos = 0x0
	// Bit mask of IRN field.
	CANFD_B_CFDGAFLIGNENT_IRN_Msk = 0x1f

	// CFDGAFLIGNCTR: Global AFL Ignore Control Register
	// Position of IREN field.
	CANFD_B_CFDGAFLIGNCTR_IREN_Pos = 0x0
	// Bit mask of IREN field.
	CANFD_B_CFDGAFLIGNCTR_IREN_Msk = 0x1
	// Bit IREN.
	CANFD_B_CFDGAFLIGNCTR_IREN = 0x1
	// AFL entry number is not ignored
	CANFD_B_CFDGAFLIGNCTR_IREN_0 = 0x0
	// AFL entry number is ignored
	CANFD_B_CFDGAFLIGNCTR_IREN_1 = 0x1
	// Position of KEY field.
	CANFD_B_CFDGAFLIGNCTR_KEY_Pos = 0x8
	// Bit mask of KEY field.
	CANFD_B_CFDGAFLIGNCTR_KEY_Msk = 0xff00

	// CFDCDTCT: DMA Transfer Control Register
	// Position of RFDMAE0 field.
	CANFD_B_CFDCDTCT_RFDMAE0_Pos = 0x0
	// Bit mask of RFDMAE0 field.
	CANFD_B_CFDCDTCT_RFDMAE0_Msk = 0x1
	// Bit RFDMAE0.
	CANFD_B_CFDCDTCT_RFDMAE0 = 0x1
	// DMA transfer request disabled
	CANFD_B_CFDCDTCT_RFDMAE0_0 = 0x0
	// DMA transfer request enabled
	CANFD_B_CFDCDTCT_RFDMAE0_1 = 0x1
	// Position of RFDMAE1 field.
	CANFD_B_CFDCDTCT_RFDMAE1_Pos = 0x1
	// Bit mask of RFDMAE1 field.
	CANFD_B_CFDCDTCT_RFDMAE1_Msk = 0x2
	// Bit RFDMAE1.
	CANFD_B_CFDCDTCT_RFDMAE1 = 0x2
	// DMA transfer request disabled
	CANFD_B_CFDCDTCT_RFDMAE1_0 = 0x0
	// DMA transfer request enabled
	CANFD_B_CFDCDTCT_RFDMAE1_1 = 0x1
	// Position of CFDMAE field.
	CANFD_B_CFDCDTCT_CFDMAE_Pos = 0x8
	// Bit mask of CFDMAE field.
	CANFD_B_CFDCDTCT_CFDMAE_Msk = 0x100
	// Bit CFDMAE.
	CANFD_B_CFDCDTCT_CFDMAE = 0x100
	// DMA transfer request disabled
	CANFD_B_CFDCDTCT_CFDMAE_0 = 0x0
	// DMA transfer request enabled
	CANFD_B_CFDCDTCT_CFDMAE_1 = 0x1

	// CFDCDTSTS: DMA Transfer Status Register
	// Position of RFDMASTS0 field.
	CANFD_B_CFDCDTSTS_RFDMASTS0_Pos = 0x0
	// Bit mask of RFDMASTS0 field.
	CANFD_B_CFDCDTSTS_RFDMASTS0_Msk = 0x1
	// Bit RFDMASTS0.
	CANFD_B_CFDCDTSTS_RFDMASTS0 = 0x1
	// DMA transfer stopped
	CANFD_B_CFDCDTSTS_RFDMASTS0_0 = 0x0
	// DMA transfer on going
	CANFD_B_CFDCDTSTS_RFDMASTS0_1 = 0x1
	// Position of RFDMASTS1 field.
	CANFD_B_CFDCDTSTS_RFDMASTS1_Pos = 0x1
	// Bit mask of RFDMASTS1 field.
	CANFD_B_CFDCDTSTS_RFDMASTS1_Msk = 0x2
	// Bit RFDMASTS1.
	CANFD_B_CFDCDTSTS_RFDMASTS1 = 0x2
	// DMA transfer stopped
	CANFD_B_CFDCDTSTS_RFDMASTS1_0 = 0x0
	// DMA transfer on going
	CANFD_B_CFDCDTSTS_RFDMASTS1_1 = 0x1
	// Position of CFDMASTS field.
	CANFD_B_CFDCDTSTS_CFDMASTS_Pos = 0x8
	// Bit mask of CFDMASTS field.
	CANFD_B_CFDCDTSTS_CFDMASTS_Msk = 0x100
	// Bit CFDMASTS.
	CANFD_B_CFDCDTSTS_CFDMASTS = 0x100
	// DMA transfer stopped
	CANFD_B_CFDCDTSTS_CFDMASTS_0 = 0x0
	// DMA transfer on going
	CANFD_B_CFDCDTSTS_CFDMASTS_1 = 0x1

	// CFDGRSTC: Global SW reset Register
	// Position of SRST field.
	CANFD_B_CFDGRSTC_SRST_Pos = 0x0
	// Bit mask of SRST field.
	CANFD_B_CFDGRSTC_SRST_Msk = 0x1
	// Bit SRST.
	CANFD_B_CFDGRSTC_SRST = 0x1
	// Normal state
	CANFD_B_CFDGRSTC_SRST_0 = 0x0
	// SW reset state
	CANFD_B_CFDGRSTC_SRST_1 = 0x1
	// Position of KEY field.
	CANFD_B_CFDGRSTC_KEY_Pos = 0x8
	// Bit mask of KEY field.
	CANFD_B_CFDGRSTC_KEY_Msk = 0xff00

	// CFDC0DCFG: Channel 0 Data Bitrate Configuration Register
	// Position of DBRP field.
	CANFD_B_CFDC0DCFG_DBRP_Pos = 0x0
	// Bit mask of DBRP field.
	CANFD_B_CFDC0DCFG_DBRP_Msk = 0xff
	// Position of DTSEG1 field.
	CANFD_B_CFDC0DCFG_DTSEG1_Pos = 0x8
	// Bit mask of DTSEG1 field.
	CANFD_B_CFDC0DCFG_DTSEG1_Msk = 0x1f00
	// Position of DTSEG2 field.
	CANFD_B_CFDC0DCFG_DTSEG2_Pos = 0x10
	// Bit mask of DTSEG2 field.
	CANFD_B_CFDC0DCFG_DTSEG2_Msk = 0xf0000
	// Position of DSJW field.
	CANFD_B_CFDC0DCFG_DSJW_Pos = 0x18
	// Bit mask of DSJW field.
	CANFD_B_CFDC0DCFG_DSJW_Msk = 0xf000000

	// CFDC0FDCFG: Channel 0 CANFD Configuration Register
	// Position of EOCCFG field.
	CANFD_B_CFDC0FDCFG_EOCCFG_Pos = 0x0
	// Bit mask of EOCCFG field.
	CANFD_B_CFDC0FDCFG_EOCCFG_Msk = 0x7
	// All transmitter or receiver CAN frames
	CANFD_B_CFDC0FDCFG_EOCCFG_000 = 0x0
	// All transmitter CAN frames
	CANFD_B_CFDC0FDCFG_EOCCFG_001 = 0x1
	// All receiver CAN frames
	CANFD_B_CFDC0FDCFG_EOCCFG_010 = 0x2
	// Reserved
	CANFD_B_CFDC0FDCFG_EOCCFG_011 = 0x3
	// Only transmitter or receiver CANFD data-phase (fast bits)
	CANFD_B_CFDC0FDCFG_EOCCFG_100 = 0x4
	// Only transmitter CANFD data-phase (fast bits)
	CANFD_B_CFDC0FDCFG_EOCCFG_101 = 0x5
	// Only receiver CANFD data-phase (fast bits)
	CANFD_B_CFDC0FDCFG_EOCCFG_110 = 0x6
	// Reserved
	CANFD_B_CFDC0FDCFG_EOCCFG_111 = 0x7
	// Position of TDCOC field.
	CANFD_B_CFDC0FDCFG_TDCOC_Pos = 0x8
	// Bit mask of TDCOC field.
	CANFD_B_CFDC0FDCFG_TDCOC_Msk = 0x100
	// Bit TDCOC.
	CANFD_B_CFDC0FDCFG_TDCOC = 0x100
	// Measured + offset
	CANFD_B_CFDC0FDCFG_TDCOC_0 = 0x0
	// Offset-only
	CANFD_B_CFDC0FDCFG_TDCOC_1 = 0x1
	// Position of TDCE field.
	CANFD_B_CFDC0FDCFG_TDCE_Pos = 0x9
	// Bit mask of TDCE field.
	CANFD_B_CFDC0FDCFG_TDCE_Msk = 0x200
	// Bit TDCE.
	CANFD_B_CFDC0FDCFG_TDCE = 0x200
	// Transceiver delay compensation disabled
	CANFD_B_CFDC0FDCFG_TDCE_0 = 0x0
	// Transceiver delay compensation enabled
	CANFD_B_CFDC0FDCFG_TDCE_1 = 0x1
	// Position of ESIC field.
	CANFD_B_CFDC0FDCFG_ESIC_Pos = 0xa
	// Bit mask of ESIC field.
	CANFD_B_CFDC0FDCFG_ESIC_Msk = 0x400
	// Bit ESIC.
	CANFD_B_CFDC0FDCFG_ESIC = 0x400
	// The ESI bit in the frame represents the error state of the node itself
	CANFD_B_CFDC0FDCFG_ESIC_0 = 0x0
	// The ESI bit in the frame represents the error state of the message buffer if the node itself is not in error passive. If the node is in error passive, then the ESI bit is driven by the node itself.
	CANFD_B_CFDC0FDCFG_ESIC_1 = 0x1
	// Position of TDCO field.
	CANFD_B_CFDC0FDCFG_TDCO_Pos = 0x10
	// Bit mask of TDCO field.
	CANFD_B_CFDC0FDCFG_TDCO_Msk = 0xff0000
	// Position of FDOE field.
	CANFD_B_CFDC0FDCFG_FDOE_Pos = 0x1c
	// Bit mask of FDOE field.
	CANFD_B_CFDC0FDCFG_FDOE_Msk = 0x10000000
	// Bit FDOE.
	CANFD_B_CFDC0FDCFG_FDOE = 0x10000000
	// FD-only mode disabled
	CANFD_B_CFDC0FDCFG_FDOE_0 = 0x0
	// FD-only mode enabled
	CANFD_B_CFDC0FDCFG_FDOE_1 = 0x1
	// Position of REFE field.
	CANFD_B_CFDC0FDCFG_REFE_Pos = 0x1d
	// Bit mask of REFE field.
	CANFD_B_CFDC0FDCFG_REFE_Msk = 0x20000000
	// Bit REFE.
	CANFD_B_CFDC0FDCFG_REFE = 0x20000000
	// RX edge filter disabled
	CANFD_B_CFDC0FDCFG_REFE_0 = 0x0
	// RX edge filter enabled
	CANFD_B_CFDC0FDCFG_REFE_1 = 0x1
	// Position of CLOE field.
	CANFD_B_CFDC0FDCFG_CLOE_Pos = 0x1e
	// Bit mask of CLOE field.
	CANFD_B_CFDC0FDCFG_CLOE_Msk = 0x40000000
	// Bit CLOE.
	CANFD_B_CFDC0FDCFG_CLOE = 0x40000000
	// Classical CAN mode disabled
	CANFD_B_CFDC0FDCFG_CLOE_0 = 0x0
	// Classical CAN mode enabled
	CANFD_B_CFDC0FDCFG_CLOE_1 = 0x1

	// CFDC0FDCTR: Channel 0 CANFD Control Register
	// Position of EOCCLR field.
	CANFD_B_CFDC0FDCTR_EOCCLR_Pos = 0x0
	// Bit mask of EOCCLR field.
	CANFD_B_CFDC0FDCTR_EOCCLR_Msk = 0x1
	// Bit EOCCLR.
	CANFD_B_CFDC0FDCTR_EOCCLR = 0x1
	// No error occurrence counter clear
	CANFD_B_CFDC0FDCTR_EOCCLR_0 = 0x0
	// Clear error occurrence counter
	CANFD_B_CFDC0FDCTR_EOCCLR_1 = 0x1
	// Position of SOCCLR field.
	CANFD_B_CFDC0FDCTR_SOCCLR_Pos = 0x1
	// Bit mask of SOCCLR field.
	CANFD_B_CFDC0FDCTR_SOCCLR_Msk = 0x2
	// Bit SOCCLR.
	CANFD_B_CFDC0FDCTR_SOCCLR = 0x2
	// No successful occurrence counter clear
	CANFD_B_CFDC0FDCTR_SOCCLR_0 = 0x0
	// Clear successful occurrence counter
	CANFD_B_CFDC0FDCTR_SOCCLR_1 = 0x1

	// CFDC0FDSTS: Channel 0 CANFD Status Register
	// Position of TDCR field.
	CANFD_B_CFDC0FDSTS_TDCR_Pos = 0x0
	// Bit mask of TDCR field.
	CANFD_B_CFDC0FDSTS_TDCR_Msk = 0xff
	// Position of EOCO field.
	CANFD_B_CFDC0FDSTS_EOCO_Pos = 0x8
	// Bit mask of EOCO field.
	CANFD_B_CFDC0FDSTS_EOCO_Msk = 0x100
	// Bit EOCO.
	CANFD_B_CFDC0FDSTS_EOCO = 0x100
	// Error occurrence counter has not overflowed
	CANFD_B_CFDC0FDSTS_EOCO_0 = 0x0
	// Error occurrence counter has overflowed
	CANFD_B_CFDC0FDSTS_EOCO_1 = 0x1
	// Position of SOCO field.
	CANFD_B_CFDC0FDSTS_SOCO_Pos = 0x9
	// Bit mask of SOCO field.
	CANFD_B_CFDC0FDSTS_SOCO_Msk = 0x200
	// Bit SOCO.
	CANFD_B_CFDC0FDSTS_SOCO = 0x200
	// Successful occurrence counter has not overflowed
	CANFD_B_CFDC0FDSTS_SOCO_0 = 0x0
	// Successful occurrence counter has overflowed
	CANFD_B_CFDC0FDSTS_SOCO_1 = 0x1
	// Position of TDCVF field.
	CANFD_B_CFDC0FDSTS_TDCVF_Pos = 0xf
	// Bit mask of TDCVF field.
	CANFD_B_CFDC0FDSTS_TDCVF_Msk = 0x8000
	// Bit TDCVF.
	CANFD_B_CFDC0FDSTS_TDCVF = 0x8000
	// Transceiver delay compensation violation has not occurred
	CANFD_B_CFDC0FDSTS_TDCVF_0 = 0x0
	// Transceiver delay compensation violation has occurred
	CANFD_B_CFDC0FDSTS_TDCVF_1 = 0x1
	// Position of EOC field.
	CANFD_B_CFDC0FDSTS_EOC_Pos = 0x10
	// Bit mask of EOC field.
	CANFD_B_CFDC0FDSTS_EOC_Msk = 0xff0000
	// Position of SOC field.
	CANFD_B_CFDC0FDSTS_SOC_Pos = 0x18
	// Bit mask of SOC field.
	CANFD_B_CFDC0FDSTS_SOC_Msk = 0xff000000

	// CFDC0FDCRC: Channel 0 CANFD CRC Register
	// Position of CRCREG field.
	CANFD_B_CFDC0FDCRC_CRCREG_Pos = 0x0
	// Bit mask of CRCREG field.
	CANFD_B_CFDC0FDCRC_CRCREG_Msk = 0x1fffff
	// Position of SCNT field.
	CANFD_B_CFDC0FDCRC_SCNT_Pos = 0x18
	// Bit mask of SCNT field.
	CANFD_B_CFDC0FDCRC_SCNT_Msk = 0xf000000

	// CFDGAFLID1: Global Acceptance Filter List ID Registers
	// Position of GAFLID field.
	CANFD_B_CFDGAFLID_GAFLID_Pos = 0x0
	// Bit mask of GAFLID field.
	CANFD_B_CFDGAFLID_GAFLID_Msk = 0x1fffffff
	// Position of GAFLLB field.
	CANFD_B_CFDGAFLID_GAFLLB_Pos = 0x1d
	// Bit mask of GAFLLB field.
	CANFD_B_CFDGAFLID_GAFLLB_Msk = 0x20000000
	// Bit GAFLLB.
	CANFD_B_CFDGAFLID_GAFLLB = 0x20000000
	// Global Acceptance Filter List entry ID for acceptance filtering with attribute RX
	CANFD_B_CFDGAFLID_GAFLLB_0 = 0x0
	// Global Acceptance Filter List entry ID for acceptance filtering with attribute TX
	CANFD_B_CFDGAFLID_GAFLLB_1 = 0x1
	// Position of GAFLRTR field.
	CANFD_B_CFDGAFLID_GAFLRTR_Pos = 0x1e
	// Bit mask of GAFLRTR field.
	CANFD_B_CFDGAFLID_GAFLRTR_Msk = 0x40000000
	// Bit GAFLRTR.
	CANFD_B_CFDGAFLID_GAFLRTR = 0x40000000
	// Data frame
	CANFD_B_CFDGAFLID_GAFLRTR_0 = 0x0
	// Remote frame
	CANFD_B_CFDGAFLID_GAFLRTR_1 = 0x1
	// Position of GAFLIDE field.
	CANFD_B_CFDGAFLID_GAFLIDE_Pos = 0x1f
	// Bit mask of GAFLIDE field.
	CANFD_B_CFDGAFLID_GAFLIDE_Msk = 0x80000000
	// Bit GAFLIDE.
	CANFD_B_CFDGAFLID_GAFLIDE = 0x80000000
	// Standard identifier of rule entry ID is valid for acceptance filtering
	CANFD_B_CFDGAFLID_GAFLIDE_0 = 0x0
	// Extended identifier of rule entry ID is valid for acceptance filtering
	CANFD_B_CFDGAFLID_GAFLIDE_1 = 0x1

	// CFDGAFLM1: Global Acceptance Filter List Mask Registers
	// Position of GAFLIDM field.
	CANFD_B_CFDGAFLM_GAFLIDM_Pos = 0x0
	// Bit mask of GAFLIDM field.
	CANFD_B_CFDGAFLM_GAFLIDM_Msk = 0x1fffffff
	// Position of GAFLIFL1 field.
	CANFD_B_CFDGAFLM_GAFLIFL1_Pos = 0x1d
	// Bit mask of GAFLIFL1 field.
	CANFD_B_CFDGAFLM_GAFLIFL1_Msk = 0x20000000
	// Bit GAFLIFL1.
	CANFD_B_CFDGAFLM_GAFLIFL1 = 0x20000000
	// Position of GAFLRTRM field.
	CANFD_B_CFDGAFLM_GAFLRTRM_Pos = 0x1e
	// Bit mask of GAFLRTRM field.
	CANFD_B_CFDGAFLM_GAFLRTRM_Msk = 0x40000000
	// Bit GAFLRTRM.
	CANFD_B_CFDGAFLM_GAFLRTRM = 0x40000000
	// RTR bit is not used for ID matching
	CANFD_B_CFDGAFLM_GAFLRTRM_0 = 0x0
	// RTR bit is used for ID matching
	CANFD_B_CFDGAFLM_GAFLRTRM_1 = 0x1
	// Position of GAFLIDEM field.
	CANFD_B_CFDGAFLM_GAFLIDEM_Pos = 0x1f
	// Bit mask of GAFLIDEM field.
	CANFD_B_CFDGAFLM_GAFLIDEM_Msk = 0x80000000
	// Bit GAFLIDEM.
	CANFD_B_CFDGAFLM_GAFLIDEM = 0x80000000
	// IDE bit is not used for ID matching
	CANFD_B_CFDGAFLM_GAFLIDEM_0 = 0x0
	// IDE bit is used for ID matching
	CANFD_B_CFDGAFLM_GAFLIDEM_1 = 0x1

	// CFDGAFLP01: Global Acceptance Filter List Pointer 0 Registers
	// Position of GAFLDLC field.
	CANFD_B_CFDGAFLP0_GAFLDLC_Pos = 0x0
	// Bit mask of GAFLDLC field.
	CANFD_B_CFDGAFLP0_GAFLDLC_Msk = 0xf
	// Position of GAFLIFL0 field.
	CANFD_B_CFDGAFLP0_GAFLIFL0_Pos = 0x7
	// Bit mask of GAFLIFL0 field.
	CANFD_B_CFDGAFLP0_GAFLIFL0_Msk = 0x80
	// Bit GAFLIFL0.
	CANFD_B_CFDGAFLP0_GAFLIFL0 = 0x80
	// Position of GAFLRMDP field.
	CANFD_B_CFDGAFLP0_GAFLRMDP_Pos = 0x8
	// Bit mask of GAFLRMDP field.
	CANFD_B_CFDGAFLP0_GAFLRMDP_Msk = 0x1f00
	// Position of GAFLRMV field.
	CANFD_B_CFDGAFLP0_GAFLRMV_Pos = 0xf
	// Bit mask of GAFLRMV field.
	CANFD_B_CFDGAFLP0_GAFLRMV_Msk = 0x8000
	// Bit GAFLRMV.
	CANFD_B_CFDGAFLP0_GAFLRMV = 0x8000
	// Single message buffer direction pointer is invalid
	CANFD_B_CFDGAFLP0_GAFLRMV_0 = 0x0
	// Single message buffer direction pointer is valid
	CANFD_B_CFDGAFLP0_GAFLRMV_1 = 0x1
	// Position of GAFLPTR field.
	CANFD_B_CFDGAFLP0_GAFLPTR_Pos = 0x10
	// Bit mask of GAFLPTR field.
	CANFD_B_CFDGAFLP0_GAFLPTR_Msk = 0xffff0000

	// CFDGAFLP11: Global Acceptance Filter List Pointer 1 Registers
	// Position of GAFLFDP0 field.
	CANFD_B_CFDGAFLP1_GAFLFDP0_Pos = 0x0
	// Bit mask of GAFLFDP0 field.
	CANFD_B_CFDGAFLP1_GAFLFDP0_Msk = 0x1
	// Bit GAFLFDP0.
	CANFD_B_CFDGAFLP1_GAFLFDP0 = 0x1
	// Disable RX FIFO 0 as target for reception
	CANFD_B_CFDGAFLP1_GAFLFDP0_0 = 0x0
	// Enable RX FIFO 0 as target for reception
	CANFD_B_CFDGAFLP1_GAFLFDP0_1 = 0x1
	// Position of GAFLFDP1 field.
	CANFD_B_CFDGAFLP1_GAFLFDP1_Pos = 0x1
	// Bit mask of GAFLFDP1 field.
	CANFD_B_CFDGAFLP1_GAFLFDP1_Msk = 0x2
	// Bit GAFLFDP1.
	CANFD_B_CFDGAFLP1_GAFLFDP1 = 0x2
	// Disable RX FIFO 1 as target for reception
	CANFD_B_CFDGAFLP1_GAFLFDP1_0 = 0x0
	// Enable RX FIFO 1 as target for reception
	CANFD_B_CFDGAFLP1_GAFLFDP1_1 = 0x1
	// Position of GAFLFDP8 field.
	CANFD_B_CFDGAFLP1_GAFLFDP8_Pos = 0x8
	// Bit mask of GAFLFDP8 field.
	CANFD_B_CFDGAFLP1_GAFLFDP8_Msk = 0x100
	// Bit GAFLFDP8.
	CANFD_B_CFDGAFLP1_GAFLFDP8 = 0x100
	// Disable Common FIFO as target for reception
	CANFD_B_CFDGAFLP1_GAFLFDP8_0 = 0x0
	// Enable Common FIFO as target for reception
	CANFD_B_CFDGAFLP1_GAFLFDP8_1 = 0x1

	// CFDRPGACC0: RAM Test Page Access Registers %s
	// Position of RDTA field.
	CANFD_B_CFDRPGACC_RDTA_Pos = 0x0
	// Bit mask of RDTA field.
	CANFD_B_CFDRPGACC_RDTA_Msk = 0xffffffff

	// CFDRFID0: RX FIFO Access ID Register %s
	// Position of RFID field.
	CANFD_B_CFDRFID_RFID_Pos = 0x0
	// Bit mask of RFID field.
	CANFD_B_CFDRFID_RFID_Msk = 0x1fffffff
	// Position of RFRTR field.
	CANFD_B_CFDRFID_RFRTR_Pos = 0x1e
	// Bit mask of RFRTR field.
	CANFD_B_CFDRFID_RFRTR_Msk = 0x40000000
	// Bit RFRTR.
	CANFD_B_CFDRFID_RFRTR = 0x40000000
	// Data frame
	CANFD_B_CFDRFID_RFRTR_0 = 0x0
	// Remote frame
	CANFD_B_CFDRFID_RFRTR_1 = 0x1
	// Position of RFIDE field.
	CANFD_B_CFDRFID_RFIDE_Pos = 0x1f
	// Bit mask of RFIDE field.
	CANFD_B_CFDRFID_RFIDE_Msk = 0x80000000
	// Bit RFIDE.
	CANFD_B_CFDRFID_RFIDE = 0x80000000
	// STD-ID has been received
	CANFD_B_CFDRFID_RFIDE_0 = 0x0
	// EXT-ID has been received
	CANFD_B_CFDRFID_RFIDE_1 = 0x1

	// CFDRFPTR0: RX FIFO Access Pointer Register %s
	// Position of RFTS field.
	CANFD_B_CFDRFPTR_RFTS_Pos = 0x0
	// Bit mask of RFTS field.
	CANFD_B_CFDRFPTR_RFTS_Msk = 0xffff
	// Position of RFDLC field.
	CANFD_B_CFDRFPTR_RFDLC_Pos = 0x1c
	// Bit mask of RFDLC field.
	CANFD_B_CFDRFPTR_RFDLC_Msk = 0xf0000000

	// CFDRFFDSTS0: RX FIFO Access CANFD Status Register %s
	// Position of RFESI field.
	CANFD_B_CFDRFFDSTS_RFESI_Pos = 0x0
	// Bit mask of RFESI field.
	CANFD_B_CFDRFFDSTS_RFESI_Msk = 0x1
	// Bit RFESI.
	CANFD_B_CFDRFFDSTS_RFESI = 0x1
	// CANFD frame received from error active node
	CANFD_B_CFDRFFDSTS_RFESI_0 = 0x0
	// CANFD frame received from error passive node
	CANFD_B_CFDRFFDSTS_RFESI_1 = 0x1
	// Position of RFBRS field.
	CANFD_B_CFDRFFDSTS_RFBRS_Pos = 0x1
	// Bit mask of RFBRS field.
	CANFD_B_CFDRFFDSTS_RFBRS_Msk = 0x2
	// Bit RFBRS.
	CANFD_B_CFDRFFDSTS_RFBRS = 0x2
	// CANFD frame received with no bit rate switch
	CANFD_B_CFDRFFDSTS_RFBRS_0 = 0x0
	// CANFD frame received with bit rate switch
	CANFD_B_CFDRFFDSTS_RFBRS_1 = 0x1
	// Position of RFFDF field.
	CANFD_B_CFDRFFDSTS_RFFDF_Pos = 0x2
	// Bit mask of RFFDF field.
	CANFD_B_CFDRFFDSTS_RFFDF_Msk = 0x4
	// Bit RFFDF.
	CANFD_B_CFDRFFDSTS_RFFDF = 0x4
	// Non CANFD frame received
	CANFD_B_CFDRFFDSTS_RFFDF_0 = 0x0
	// CANFD frame received
	CANFD_B_CFDRFFDSTS_RFFDF_1 = 0x1
	// Position of RFIFL field.
	CANFD_B_CFDRFFDSTS_RFIFL_Pos = 0x8
	// Bit mask of RFIFL field.
	CANFD_B_CFDRFFDSTS_RFIFL_Msk = 0x300
	// Position of CFDRFPTR field.
	CANFD_B_CFDRFFDSTS_CFDRFPTR_Pos = 0x10
	// Bit mask of CFDRFPTR field.
	CANFD_B_CFDRFFDSTS_CFDRFPTR_Msk = 0xffff0000

	// CFDRFDF0_0: RX FIFO Access Data Field 0 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_0_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_0_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_0_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_0_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_0_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_0_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_0_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_0_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_1: RX FIFO Access Data Field 1 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_1_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_1_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_1_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_1_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_1_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_1_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_1_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_1_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_2: RX FIFO Access Data Field 2 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_2_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_2_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_2_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_2_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_2_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_2_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_2_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_2_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_3: RX FIFO Access Data Field 3 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_3_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_3_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_3_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_3_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_3_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_3_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_3_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_3_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_4: RX FIFO Access Data Field 4 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_4_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_4_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_4_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_4_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_4_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_4_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_4_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_4_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_5: RX FIFO Access Data Field 5 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_5_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_5_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_5_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_5_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_5_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_5_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_5_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_5_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_6: RX FIFO Access Data Field 6 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_6_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_6_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_6_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_6_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_6_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_6_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_6_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_6_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_7: RX FIFO Access Data Field 7 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_7_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_7_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_7_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_7_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_7_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_7_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_7_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_7_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_8: RX FIFO Access Data Field 8 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_8_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_8_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_8_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_8_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_8_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_8_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_8_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_8_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_9: RX FIFO Access Data Field 9 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_9_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_9_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_9_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_9_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_9_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_9_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_9_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_9_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_10: RX FIFO Access Data Field 10 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_10_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_10_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_10_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_10_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_10_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_10_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_10_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_10_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_11: RX FIFO Access Data Field 11 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_11_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_11_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_11_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_11_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_11_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_11_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_11_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_11_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_12: RX FIFO Access Data Field 12 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_12_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_12_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_12_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_12_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_12_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_12_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_12_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_12_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_13: RX FIFO Access Data Field 13 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_13_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_13_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_13_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_13_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_13_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_13_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_13_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_13_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_14: RX FIFO Access Data Field 14 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_14_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_14_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_14_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_14_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_14_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_14_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_14_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_14_RFDB_HH_Msk = 0xff000000

	// CFDRFDF0_15: RX FIFO Access Data Field 15 Register %s
	// Position of RFDB_LL field.
	CANFD_B_CFDRFDF_15_RFDB_LL_Pos = 0x0
	// Bit mask of RFDB_LL field.
	CANFD_B_CFDRFDF_15_RFDB_LL_Msk = 0xff
	// Position of RFDB_LH field.
	CANFD_B_CFDRFDF_15_RFDB_LH_Pos = 0x8
	// Bit mask of RFDB_LH field.
	CANFD_B_CFDRFDF_15_RFDB_LH_Msk = 0xff00
	// Position of RFDB_HL field.
	CANFD_B_CFDRFDF_15_RFDB_HL_Pos = 0x10
	// Bit mask of RFDB_HL field.
	CANFD_B_CFDRFDF_15_RFDB_HL_Msk = 0xff0000
	// Position of RFDB_HH field.
	CANFD_B_CFDRFDF_15_RFDB_HH_Pos = 0x18
	// Bit mask of RFDB_HH field.
	CANFD_B_CFDRFDF_15_RFDB_HH_Msk = 0xff000000

	// CFDCFID: Common FIFO Access ID Register
	// Position of CFID field.
	CANFD_B_CFDCFID_CFID_Pos = 0x0
	// Bit mask of CFID field.
	CANFD_B_CFDCFID_CFID_Msk = 0x1fffffff
	// Position of THLEN field.
	CANFD_B_CFDCFID_THLEN_Pos = 0x1d
	// Bit mask of THLEN field.
	CANFD_B_CFDCFID_THLEN_Msk = 0x20000000
	// Bit THLEN.
	CANFD_B_CFDCFID_THLEN = 0x20000000
	// Entry will not be stored in THL after successful TX.
	CANFD_B_CFDCFID_THLEN_0 = 0x0
	// Entry will be stored in THL after successful TX.
	CANFD_B_CFDCFID_THLEN_1 = 0x1
	// Position of CFRTR field.
	CANFD_B_CFDCFID_CFRTR_Pos = 0x1e
	// Bit mask of CFRTR field.
	CANFD_B_CFDCFID_CFRTR_Msk = 0x40000000
	// Bit CFRTR.
	CANFD_B_CFDCFID_CFRTR = 0x40000000
	// Data Frame
	CANFD_B_CFDCFID_CFRTR_0 = 0x0
	// Remote Frame
	CANFD_B_CFDCFID_CFRTR_1 = 0x1
	// Position of CFIDE field.
	CANFD_B_CFDCFID_CFIDE_Pos = 0x1f
	// Bit mask of CFIDE field.
	CANFD_B_CFDCFID_CFIDE_Msk = 0x80000000
	// Bit CFIDE.
	CANFD_B_CFDCFID_CFIDE = 0x80000000
	// STD-ID will be transmitted or has been received
	CANFD_B_CFDCFID_CFIDE_0 = 0x0
	// EXT-ID will be transmitted or has been received
	CANFD_B_CFDCFID_CFIDE_1 = 0x1

	// CFDCFPTR: Common FIFO Access Pointer Register
	// Position of CFTS field.
	CANFD_B_CFDCFPTR_CFTS_Pos = 0x0
	// Bit mask of CFTS field.
	CANFD_B_CFDCFPTR_CFTS_Msk = 0xffff
	// Position of CFDLC field.
	CANFD_B_CFDCFPTR_CFDLC_Pos = 0x1c
	// Bit mask of CFDLC field.
	CANFD_B_CFDCFPTR_CFDLC_Msk = 0xf0000000

	// CFDCFFDCSTS: Common FIFO Access CANFD Control/Status Register
	// Position of CFESI field.
	CANFD_B_CFDCFFDCSTS_CFESI_Pos = 0x0
	// Bit mask of CFESI field.
	CANFD_B_CFDCFFDCSTS_CFESI_Msk = 0x1
	// Bit CFESI.
	CANFD_B_CFDCFFDCSTS_CFESI = 0x1
	// CANFD frame received or to transmit by error active node
	CANFD_B_CFDCFFDCSTS_CFESI_0 = 0x0
	// CANFD frame received or to transmit by error passive node
	CANFD_B_CFDCFFDCSTS_CFESI_1 = 0x1
	// Position of CFBRS field.
	CANFD_B_CFDCFFDCSTS_CFBRS_Pos = 0x1
	// Bit mask of CFBRS field.
	CANFD_B_CFDCFFDCSTS_CFBRS_Msk = 0x2
	// Bit CFBRS.
	CANFD_B_CFDCFFDCSTS_CFBRS = 0x2
	// CANFD frame received or to transmit with no bit rate switch
	CANFD_B_CFDCFFDCSTS_CFBRS_0 = 0x0
	// CANFD frame received or to transmit with bit rate switch
	CANFD_B_CFDCFFDCSTS_CFBRS_1 = 0x1
	// Position of CFFDF field.
	CANFD_B_CFDCFFDCSTS_CFFDF_Pos = 0x2
	// Bit mask of CFFDF field.
	CANFD_B_CFDCFFDCSTS_CFFDF_Msk = 0x4
	// Bit CFFDF.
	CANFD_B_CFDCFFDCSTS_CFFDF = 0x4
	// Non CANFD frame received or to transmit
	CANFD_B_CFDCFFDCSTS_CFFDF_0 = 0x0
	// CANFD frame received or to transmit
	CANFD_B_CFDCFFDCSTS_CFFDF_1 = 0x1
	// Position of CFIFL field.
	CANFD_B_CFDCFFDCSTS_CFIFL_Pos = 0x8
	// Bit mask of CFIFL field.
	CANFD_B_CFDCFFDCSTS_CFIFL_Msk = 0x300
	// Position of CFPTR field.
	CANFD_B_CFDCFFDCSTS_CFPTR_Pos = 0x10
	// Bit mask of CFPTR field.
	CANFD_B_CFDCFFDCSTS_CFPTR_Msk = 0xffff0000

	// CFDCFDF0: Common FIFO Access Data Field %s Registers
	// Position of CFDB_LL field.
	CANFD_B_CFDCFDF_CFDB_LL_Pos = 0x0
	// Bit mask of CFDB_LL field.
	CANFD_B_CFDCFDF_CFDB_LL_Msk = 0xff
	// Position of CFDB_LH field.
	CANFD_B_CFDCFDF_CFDB_LH_Pos = 0x8
	// Bit mask of CFDB_LH field.
	CANFD_B_CFDCFDF_CFDB_LH_Msk = 0xff00
	// Position of CFDB_HL field.
	CANFD_B_CFDCFDF_CFDB_HL_Pos = 0x10
	// Bit mask of CFDB_HL field.
	CANFD_B_CFDCFDF_CFDB_HL_Msk = 0xff0000
	// Position of CFDB_HH field.
	CANFD_B_CFDCFDF_CFDB_HH_Pos = 0x18
	// Bit mask of CFDB_HH field.
	CANFD_B_CFDCFDF_CFDB_HH_Msk = 0xff000000

	// CFDTMID0: TX Message Buffer ID Registers
	// Position of TMID field.
	CANFD_B_CFDTMID_TMID_Pos = 0x0
	// Bit mask of TMID field.
	CANFD_B_CFDTMID_TMID_Msk = 0x1fffffff
	// Position of THLEN field.
	CANFD_B_CFDTMID_THLEN_Pos = 0x1d
	// Bit mask of THLEN field.
	CANFD_B_CFDTMID_THLEN_Msk = 0x20000000
	// Bit THLEN.
	CANFD_B_CFDTMID_THLEN = 0x20000000
	// Entry not stored in THL after successful TX
	CANFD_B_CFDTMID_THLEN_0 = 0x0
	// Entry stored in THL after successful TX
	CANFD_B_CFDTMID_THLEN_1 = 0x1
	// Position of TMRTR field.
	CANFD_B_CFDTMID_TMRTR_Pos = 0x1e
	// Bit mask of TMRTR field.
	CANFD_B_CFDTMID_TMRTR_Msk = 0x40000000
	// Bit TMRTR.
	CANFD_B_CFDTMID_TMRTR = 0x40000000
	// Data frame
	CANFD_B_CFDTMID_TMRTR_0 = 0x0
	// Remote frame
	CANFD_B_CFDTMID_TMRTR_1 = 0x1
	// Position of TMIDE field.
	CANFD_B_CFDTMID_TMIDE_Pos = 0x1f
	// Bit mask of TMIDE field.
	CANFD_B_CFDTMID_TMIDE_Msk = 0x80000000
	// Bit TMIDE.
	CANFD_B_CFDTMID_TMIDE = 0x80000000
	// STD-ID is transmitted
	CANFD_B_CFDTMID_TMIDE_0 = 0x0
	// EXT-ID is transmitted
	CANFD_B_CFDTMID_TMIDE_1 = 0x1

	// CFDTMPTR0: TX Message Buffer Pointer Register
	// Position of TMDLC field.
	CANFD_B_CFDTMPTR_TMDLC_Pos = 0x1c
	// Bit mask of TMDLC field.
	CANFD_B_CFDTMPTR_TMDLC_Msk = 0xf0000000

	// CFDTMFDCTR0: TX Message Buffer CANFD Control Register
	// Position of TMESI field.
	CANFD_B_CFDTMFDCTR_TMESI_Pos = 0x0
	// Bit mask of TMESI field.
	CANFD_B_CFDTMFDCTR_TMESI_Msk = 0x1
	// Bit TMESI.
	CANFD_B_CFDTMFDCTR_TMESI = 0x1
	// CANFD frame to transmit by error active node
	CANFD_B_CFDTMFDCTR_TMESI_0 = 0x0
	// CANFD frame to transmit by error passive node
	CANFD_B_CFDTMFDCTR_TMESI_1 = 0x1
	// Position of TMBRS field.
	CANFD_B_CFDTMFDCTR_TMBRS_Pos = 0x1
	// Bit mask of TMBRS field.
	CANFD_B_CFDTMFDCTR_TMBRS_Msk = 0x2
	// Bit TMBRS.
	CANFD_B_CFDTMFDCTR_TMBRS = 0x2
	// CANFD frame to transmit with no bit rate switch
	CANFD_B_CFDTMFDCTR_TMBRS_0 = 0x0
	// CANFD frame to transmit with bit rate switch
	CANFD_B_CFDTMFDCTR_TMBRS_1 = 0x1
	// Position of TMFDF field.
	CANFD_B_CFDTMFDCTR_TMFDF_Pos = 0x2
	// Bit mask of TMFDF field.
	CANFD_B_CFDTMFDCTR_TMFDF_Msk = 0x4
	// Bit TMFDF.
	CANFD_B_CFDTMFDCTR_TMFDF = 0x4
	// Non CANFD frame to transmit
	CANFD_B_CFDTMFDCTR_TMFDF_0 = 0x0
	// CANFD frame to transmit
	CANFD_B_CFDTMFDCTR_TMFDF_1 = 0x1
	// Position of TMIFL field.
	CANFD_B_CFDTMFDCTR_TMIFL_Pos = 0x8
	// Bit mask of TMIFL field.
	CANFD_B_CFDTMFDCTR_TMIFL_Msk = 0x300
	// Position of TMPTR field.
	CANFD_B_CFDTMFDCTR_TMPTR_Pos = 0x10
	// Bit mask of TMPTR field.
	CANFD_B_CFDTMFDCTR_TMPTR_Msk = 0xffff0000

	// CFDTMDF0_0: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_0_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_0_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_0_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_0_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_0_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_0_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_0_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_0_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_1: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_1_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_1_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_1_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_1_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_1_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_1_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_1_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_1_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_2: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_2_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_2_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_2_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_2_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_2_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_2_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_2_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_2_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_3: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_3_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_3_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_3_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_3_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_3_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_3_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_3_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_3_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_4: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_4_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_4_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_4_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_4_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_4_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_4_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_4_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_4_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_5: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_5_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_5_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_5_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_5_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_5_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_5_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_5_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_5_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_6: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_6_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_6_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_6_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_6_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_6_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_6_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_6_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_6_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_7: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_7_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_7_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_7_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_7_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_7_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_7_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_7_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_7_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_8: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_8_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_8_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_8_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_8_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_8_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_8_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_8_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_8_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_9: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_9_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_9_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_9_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_9_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_9_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_9_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_9_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_9_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_10: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_10_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_10_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_10_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_10_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_10_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_10_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_10_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_10_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_11: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_11_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_11_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_11_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_11_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_11_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_11_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_11_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_11_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_12: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_12_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_12_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_12_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_12_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_12_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_12_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_12_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_12_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_13: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_13_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_13_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_13_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_13_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_13_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_13_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_13_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_13_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_14: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_14_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_14_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_14_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_14_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_14_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_14_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_14_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_14_TMDB_HH_Msk = 0xff000000

	// CFDTMDF0_15: TX Message Buffer Data Field Register
	// Position of TMDB_LL field.
	CANFD_B_CFDTMDF_15_TMDB_LL_Pos = 0x0
	// Bit mask of TMDB_LL field.
	CANFD_B_CFDTMDF_15_TMDB_LL_Msk = 0xff
	// Position of TMDB_LH field.
	CANFD_B_CFDTMDF_15_TMDB_LH_Pos = 0x8
	// Bit mask of TMDB_LH field.
	CANFD_B_CFDTMDF_15_TMDB_LH_Msk = 0xff00
	// Position of TMDB_HL field.
	CANFD_B_CFDTMDF_15_TMDB_HL_Pos = 0x10
	// Bit mask of TMDB_HL field.
	CANFD_B_CFDTMDF_15_TMDB_HL_Msk = 0xff0000
	// Position of TMDB_HH field.
	CANFD_B_CFDTMDF_15_TMDB_HH_Pos = 0x18
	// Bit mask of TMDB_HH field.
	CANFD_B_CFDTMDF_15_TMDB_HH_Msk = 0xff000000

	// CFDTHLACC0: TX History List Access Register 0
	// Position of BT field.
	CANFD_B_CFDTHLACC0_BT_Pos = 0x0
	// Bit mask of BT field.
	CANFD_B_CFDTHLACC0_BT_Msk = 0x7
	// Flat TX message buffer
	CANFD_B_CFDTHLACC0_BT_001 = 0x1
	// TX FIFO message buffer number
	CANFD_B_CFDTHLACC0_BT_010 = 0x2
	// TX Queue message buffer number
	CANFD_B_CFDTHLACC0_BT_100 = 0x4
	// Position of BN field.
	CANFD_B_CFDTHLACC0_BN_Pos = 0x3
	// Bit mask of BN field.
	CANFD_B_CFDTHLACC0_BN_Msk = 0x18
	// Position of TMTS field.
	CANFD_B_CFDTHLACC0_TMTS_Pos = 0x10
	// Bit mask of TMTS field.
	CANFD_B_CFDTHLACC0_TMTS_Msk = 0xffff0000

	// CFDTHLACC1: TX History List Access Register 1
	// Position of TID field.
	CANFD_B_CFDTHLACC1_TID_Pos = 0x0
	// Bit mask of TID field.
	CANFD_B_CFDTHLACC1_TID_Msk = 0xffff
	// Position of TIFL field.
	CANFD_B_CFDTHLACC1_TIFL_Pos = 0x10
	// Bit mask of TIFL field.
	CANFD_B_CFDTHLACC1_TIFL_Msk = 0x30000

	// CFDRMID0: RX Message Buffer ID Registers
	// Position of RMID field.
	CANFD_B_CFDRMID_RMID_Pos = 0x0
	// Bit mask of RMID field.
	CANFD_B_CFDRMID_RMID_Msk = 0x1fffffff
	// Position of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Pos = 0x1e
	// Bit mask of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Msk = 0x40000000
	// Bit RMRTR.
	CANFD_B_CFDRMID_RMRTR = 0x40000000
	// Data frame
	CANFD_B_CFDRMID_RMRTR_0 = 0x0
	// Remote frame
	CANFD_B_CFDRMID_RMRTR_1 = 0x1
	// Position of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Pos = 0x1f
	// Bit mask of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Msk = 0x80000000
	// Bit RMIDE.
	CANFD_B_CFDRMID_RMIDE = 0x80000000
	// STD-ID is stored
	CANFD_B_CFDRMID_RMIDE_0 = 0x0
	// EXT-ID is stored
	CANFD_B_CFDRMID_RMIDE_1 = 0x1

	// CFDRMPTR0: RX Message Buffer Pointer Registers
	// Position of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Pos = 0x0
	// Bit mask of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Msk = 0xffff
	// Position of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Pos = 0x1c
	// Bit mask of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Msk = 0xf0000000

	// CFDRMFDSTS0: RX Message Buffer CANFD Status Registers
	// Position of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Pos = 0x0
	// Bit mask of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Msk = 0x1
	// Bit RMESI.
	CANFD_B_CFDRMFDSTS_RMESI = 0x1
	// CANFD frame received from error active node
	CANFD_B_CFDRMFDSTS_RMESI_0 = 0x0
	// CANFD frame received from error passive node
	CANFD_B_CFDRMFDSTS_RMESI_1 = 0x1
	// Position of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Pos = 0x1
	// Bit mask of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Msk = 0x2
	// Bit RMBRS.
	CANFD_B_CFDRMFDSTS_RMBRS = 0x2
	// CANFD frame received with no bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_0 = 0x0
	// CANFD frame received with bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_1 = 0x1
	// Position of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Pos = 0x2
	// Bit mask of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Msk = 0x4
	// Bit RMFDF.
	CANFD_B_CFDRMFDSTS_RMFDF = 0x4
	// Non CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_0 = 0x0
	// CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_1 = 0x1
	// Position of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Pos = 0x8
	// Bit mask of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Msk = 0x300
	// Position of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Pos = 0x10
	// Bit mask of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Msk = 0xffff0000

	// CFDRMDF0_0: RX Message Buffer Data Field 0 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_1: RX Message Buffer Data Field 1 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_2: RX Message Buffer Data Field 2 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_3: RX Message Buffer Data Field 3 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_4: RX Message Buffer Data Field 4 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_5: RX Message Buffer Data Field 5 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_6: RX Message Buffer Data Field 6 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_7: RX Message Buffer Data Field 7 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_8: RX Message Buffer Data Field 8 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_9: RX Message Buffer Data Field 9 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_10: RX Message Buffer Data Field 10 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_11: RX Message Buffer Data Field 11 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_12: RX Message Buffer Data Field 12 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_13: RX Message Buffer Data Field 13 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_14: RX Message Buffer Data Field 14 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Msk = 0xff000000

	// CFDRMDF0_15: RX Message Buffer Data Field 15 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Msk = 0xff000000

	// CFDRMID8: RX Message Buffer ID Registers
	// Position of RMID field.
	CANFD_B_CFDRMID_RMID_Pos = 0x0
	// Bit mask of RMID field.
	CANFD_B_CFDRMID_RMID_Msk = 0x1fffffff
	// Position of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Pos = 0x1e
	// Bit mask of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Msk = 0x40000000
	// Bit RMRTR.
	CANFD_B_CFDRMID_RMRTR = 0x40000000
	// Data frame
	CANFD_B_CFDRMID_RMRTR_0 = 0x0
	// Remote frame
	CANFD_B_CFDRMID_RMRTR_1 = 0x1
	// Position of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Pos = 0x1f
	// Bit mask of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Msk = 0x80000000
	// Bit RMIDE.
	CANFD_B_CFDRMID_RMIDE = 0x80000000
	// STD-ID is stored
	CANFD_B_CFDRMID_RMIDE_0 = 0x0
	// EXT-ID is stored
	CANFD_B_CFDRMID_RMIDE_1 = 0x1

	// CFDRMPTR8: RX Message Buffer Pointer Registers
	// Position of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Pos = 0x0
	// Bit mask of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Msk = 0xffff
	// Position of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Pos = 0x1c
	// Bit mask of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Msk = 0xf0000000

	// CFDRMFDSTS8: RX Message Buffer CANFD Status Registers
	// Position of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Pos = 0x0
	// Bit mask of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Msk = 0x1
	// Bit RMESI.
	CANFD_B_CFDRMFDSTS_RMESI = 0x1
	// CANFD frame received from error active node
	CANFD_B_CFDRMFDSTS_RMESI_0 = 0x0
	// CANFD frame received from error passive node
	CANFD_B_CFDRMFDSTS_RMESI_1 = 0x1
	// Position of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Pos = 0x1
	// Bit mask of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Msk = 0x2
	// Bit RMBRS.
	CANFD_B_CFDRMFDSTS_RMBRS = 0x2
	// CANFD frame received with no bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_0 = 0x0
	// CANFD frame received with bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_1 = 0x1
	// Position of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Pos = 0x2
	// Bit mask of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Msk = 0x4
	// Bit RMFDF.
	CANFD_B_CFDRMFDSTS_RMFDF = 0x4
	// Non CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_0 = 0x0
	// CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_1 = 0x1
	// Position of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Pos = 0x8
	// Bit mask of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Msk = 0x300
	// Position of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Pos = 0x10
	// Bit mask of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Msk = 0xffff0000

	// CFDRMDF8_0: RX Message Buffer Data Field 0 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_1: RX Message Buffer Data Field 1 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_2: RX Message Buffer Data Field 2 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_3: RX Message Buffer Data Field 3 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_4: RX Message Buffer Data Field 4 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_5: RX Message Buffer Data Field 5 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_6: RX Message Buffer Data Field 6 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_7: RX Message Buffer Data Field 7 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_8: RX Message Buffer Data Field 8 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_9: RX Message Buffer Data Field 9 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_10: RX Message Buffer Data Field 10 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_11: RX Message Buffer Data Field 11 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_12: RX Message Buffer Data Field 12 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_13: RX Message Buffer Data Field 13 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_14: RX Message Buffer Data Field 14 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Msk = 0xff000000

	// CFDRMDF8_15: RX Message Buffer Data Field 15 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Msk = 0xff000000

	// CFDRMID16: RX Message Buffer ID Registers
	// Position of RMID field.
	CANFD_B_CFDRMID_RMID_Pos = 0x0
	// Bit mask of RMID field.
	CANFD_B_CFDRMID_RMID_Msk = 0x1fffffff
	// Position of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Pos = 0x1e
	// Bit mask of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Msk = 0x40000000
	// Bit RMRTR.
	CANFD_B_CFDRMID_RMRTR = 0x40000000
	// Data frame
	CANFD_B_CFDRMID_RMRTR_0 = 0x0
	// Remote frame
	CANFD_B_CFDRMID_RMRTR_1 = 0x1
	// Position of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Pos = 0x1f
	// Bit mask of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Msk = 0x80000000
	// Bit RMIDE.
	CANFD_B_CFDRMID_RMIDE = 0x80000000
	// STD-ID is stored
	CANFD_B_CFDRMID_RMIDE_0 = 0x0
	// EXT-ID is stored
	CANFD_B_CFDRMID_RMIDE_1 = 0x1

	// CFDRMPTR16: RX Message Buffer Pointer Registers
	// Position of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Pos = 0x0
	// Bit mask of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Msk = 0xffff
	// Position of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Pos = 0x1c
	// Bit mask of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Msk = 0xf0000000

	// CFDRMFDSTS16: RX Message Buffer CANFD Status Registers
	// Position of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Pos = 0x0
	// Bit mask of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Msk = 0x1
	// Bit RMESI.
	CANFD_B_CFDRMFDSTS_RMESI = 0x1
	// CANFD frame received from error active node
	CANFD_B_CFDRMFDSTS_RMESI_0 = 0x0
	// CANFD frame received from error passive node
	CANFD_B_CFDRMFDSTS_RMESI_1 = 0x1
	// Position of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Pos = 0x1
	// Bit mask of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Msk = 0x2
	// Bit RMBRS.
	CANFD_B_CFDRMFDSTS_RMBRS = 0x2
	// CANFD frame received with no bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_0 = 0x0
	// CANFD frame received with bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_1 = 0x1
	// Position of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Pos = 0x2
	// Bit mask of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Msk = 0x4
	// Bit RMFDF.
	CANFD_B_CFDRMFDSTS_RMFDF = 0x4
	// Non CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_0 = 0x0
	// CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_1 = 0x1
	// Position of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Pos = 0x8
	// Bit mask of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Msk = 0x300
	// Position of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Pos = 0x10
	// Bit mask of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Msk = 0xffff0000

	// CFDRMDF16_0: RX Message Buffer Data Field 0 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_1: RX Message Buffer Data Field 1 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_2: RX Message Buffer Data Field 2 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_3: RX Message Buffer Data Field 3 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_4: RX Message Buffer Data Field 4 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_5: RX Message Buffer Data Field 5 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_6: RX Message Buffer Data Field 6 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_7: RX Message Buffer Data Field 7 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_8: RX Message Buffer Data Field 8 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_9: RX Message Buffer Data Field 9 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_10: RX Message Buffer Data Field 10 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_11: RX Message Buffer Data Field 11 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_12: RX Message Buffer Data Field 12 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_13: RX Message Buffer Data Field 13 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_14: RX Message Buffer Data Field 14 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Msk = 0xff000000

	// CFDRMDF16_15: RX Message Buffer Data Field 15 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Msk = 0xff000000

	// CFDRMID24: RX Message Buffer ID Registers
	// Position of RMID field.
	CANFD_B_CFDRMID_RMID_Pos = 0x0
	// Bit mask of RMID field.
	CANFD_B_CFDRMID_RMID_Msk = 0x1fffffff
	// Position of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Pos = 0x1e
	// Bit mask of RMRTR field.
	CANFD_B_CFDRMID_RMRTR_Msk = 0x40000000
	// Bit RMRTR.
	CANFD_B_CFDRMID_RMRTR = 0x40000000
	// Data frame
	CANFD_B_CFDRMID_RMRTR_0 = 0x0
	// Remote frame
	CANFD_B_CFDRMID_RMRTR_1 = 0x1
	// Position of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Pos = 0x1f
	// Bit mask of RMIDE field.
	CANFD_B_CFDRMID_RMIDE_Msk = 0x80000000
	// Bit RMIDE.
	CANFD_B_CFDRMID_RMIDE = 0x80000000
	// STD-ID is stored
	CANFD_B_CFDRMID_RMIDE_0 = 0x0
	// EXT-ID is stored
	CANFD_B_CFDRMID_RMIDE_1 = 0x1

	// CFDRMPTR24: RX Message Buffer Pointer Registers
	// Position of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Pos = 0x0
	// Bit mask of RMTS field.
	CANFD_B_CFDRMPTR_RMTS_Msk = 0xffff
	// Position of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Pos = 0x1c
	// Bit mask of RMDLC field.
	CANFD_B_CFDRMPTR_RMDLC_Msk = 0xf0000000

	// CFDRMFDSTS24: RX Message Buffer CANFD Status Registers
	// Position of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Pos = 0x0
	// Bit mask of RMESI field.
	CANFD_B_CFDRMFDSTS_RMESI_Msk = 0x1
	// Bit RMESI.
	CANFD_B_CFDRMFDSTS_RMESI = 0x1
	// CANFD frame received from error active node
	CANFD_B_CFDRMFDSTS_RMESI_0 = 0x0
	// CANFD frame received from error passive node
	CANFD_B_CFDRMFDSTS_RMESI_1 = 0x1
	// Position of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Pos = 0x1
	// Bit mask of RMBRS field.
	CANFD_B_CFDRMFDSTS_RMBRS_Msk = 0x2
	// Bit RMBRS.
	CANFD_B_CFDRMFDSTS_RMBRS = 0x2
	// CANFD frame received with no bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_0 = 0x0
	// CANFD frame received with bit rate switch
	CANFD_B_CFDRMFDSTS_RMBRS_1 = 0x1
	// Position of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Pos = 0x2
	// Bit mask of RMFDF field.
	CANFD_B_CFDRMFDSTS_RMFDF_Msk = 0x4
	// Bit RMFDF.
	CANFD_B_CFDRMFDSTS_RMFDF = 0x4
	// Non CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_0 = 0x0
	// CANFD frame received
	CANFD_B_CFDRMFDSTS_RMFDF_1 = 0x1
	// Position of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Pos = 0x8
	// Bit mask of RMIFL field.
	CANFD_B_CFDRMFDSTS_RMIFL_Msk = 0x300
	// Position of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Pos = 0x10
	// Bit mask of RMPTR field.
	CANFD_B_CFDRMFDSTS_RMPTR_Msk = 0xffff0000

	// CFDRMDF24_0: RX Message Buffer Data Field 0 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_0_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_0_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_0_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_0_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_1: RX Message Buffer Data Field 1 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_1_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_1_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_1_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_1_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_2: RX Message Buffer Data Field 2 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_2_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_2_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_2_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_2_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_3: RX Message Buffer Data Field 3 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_3_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_3_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_3_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_3_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_4: RX Message Buffer Data Field 4 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_4_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_4_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_4_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_4_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_5: RX Message Buffer Data Field 5 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_5_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_5_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_5_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_5_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_6: RX Message Buffer Data Field 6 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_6_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_6_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_6_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_6_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_7: RX Message Buffer Data Field 7 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_7_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_7_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_7_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_7_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_8: RX Message Buffer Data Field 8 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_8_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_8_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_8_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_8_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_9: RX Message Buffer Data Field 9 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_9_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_9_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_9_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_9_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_10: RX Message Buffer Data Field 10 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_10_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_10_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_10_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_10_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_11: RX Message Buffer Data Field 11 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_11_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_11_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_11_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_11_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_12: RX Message Buffer Data Field 12 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_12_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_12_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_12_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_12_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_13: RX Message Buffer Data Field 13 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_13_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_13_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_13_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_13_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_14: RX Message Buffer Data Field 14 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_14_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_14_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_14_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_14_RMDB_HH_Msk = 0xff000000

	// CFDRMDF24_15: RX Message Buffer Data Field 15 Registers
	// Position of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Pos = 0x0
	// Bit mask of RMDB_LL field.
	CANFD_B_CFDRMDF_15_RMDB_LL_Msk = 0xff
	// Position of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Pos = 0x8
	// Bit mask of RMDB_LH field.
	CANFD_B_CFDRMDF_15_RMDB_LH_Msk = 0xff00
	// Position of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Pos = 0x10
	// Bit mask of RMDB_HL field.
	CANFD_B_CFDRMDF_15_RMDB_HL_Msk = 0xff0000
	// Position of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Pos = 0x18
	// Bit mask of RMDB_HH field.
	CANFD_B_CFDRMDF_15_RMDB_HH_Msk = 0xff000000
)

// Constants for PSCU: Peripheral Security Control Unit
const (
	// PSARB: Peripheral Security Attribution Register B
	// Position of PSARB3 field.
	PSCU_PSARB_PSARB3_Pos = 0x3
	// Bit mask of PSARB3 field.
	PSCU_PSARB_PSARB3_Msk = 0x8
	// Bit PSARB3.
	PSCU_PSARB_PSARB3 = 0x8
	// Secure
	PSCU_PSARB_PSARB3_0 = 0x0
	// Non-secure
	PSCU_PSARB_PSARB3_1 = 0x1
	// Position of PSARB4 field.
	PSCU_PSARB_PSARB4_Pos = 0x4
	// Bit mask of PSARB4 field.
	PSCU_PSARB_PSARB4_Msk = 0x10
	// Bit PSARB4.
	PSCU_PSARB_PSARB4 = 0x10
	// Secure
	PSCU_PSARB_PSARB4_0 = 0x0
	// Non-secure
	PSCU_PSARB_PSARB4_1 = 0x1
	// Position of PSARB6 field.
	PSCU_PSARB_PSARB6_Pos = 0x6
	// Bit mask of PSARB6 field.
	PSCU_PSARB_PSARB6_Msk = 0x40
	// Bit PSARB6.
	PSCU_PSARB_PSARB6 = 0x40
	// Position of PSARB11 field.
	PSCU_PSARB_PSARB11_Pos = 0xb
	// Bit mask of PSARB11 field.
	PSCU_PSARB_PSARB11_Msk = 0x800
	// Bit PSARB11.
	PSCU_PSARB_PSARB11 = 0x800
	// Secure
	PSCU_PSARB_PSARB11_0 = 0x0
	// Non-secure
	PSCU_PSARB_PSARB11_1 = 0x1
	// Position of PSARB18 field.
	PSCU_PSARB_PSARB18_Pos = 0x12
	// Bit mask of PSARB18 field.
	PSCU_PSARB_PSARB18_Msk = 0x40000
	// Bit PSARB18.
	PSCU_PSARB_PSARB18 = 0x40000
	// Secure
	PSCU_PSARB_PSARB18_0 = 0x0
	// Non-secure
	PSCU_PSARB_PSARB18_1 = 0x1
	// Position of PSARB19 field.
	PSCU_PSARB_PSARB19_Pos = 0x13
	// Bit mask of PSARB19 field.
	PSCU_PSARB_PSARB19_Msk = 0x80000
	// Bit PSARB19.
	PSCU_PSARB_PSARB19 = 0x80000
	// Secure
	PSCU_PSARB_PSARB19_0 = 0x0
	// Non-secure
	PSCU_PSARB_PSARB19_1 = 0x1
	// Position of PSARB22 field.
	PSCU_PSARB_PSARB22_Pos = 0x16
	// Bit mask of PSARB22 field.
	PSCU_PSARB_PSARB22_Msk = 0x400000
	// Bit PSARB22.
	PSCU_PSARB_PSARB22 = 0x400000
	// Secure
	PSCU_PSARB_PSARB22_0 = 0x0
	// Non-secure
	PSCU_PSARB_PSARB22_1 = 0x1
	// Position of PSARB31 field.
	PSCU_PSARB_PSARB31_Pos = 0x1f
	// Bit mask of PSARB31 field.
	PSCU_PSARB_PSARB31_Msk = 0x80000000
	// Bit PSARB31.
	PSCU_PSARB_PSARB31 = 0x80000000
	// Secure
	PSCU_PSARB_PSARB31_0 = 0x0
	// Non-secure
	PSCU_PSARB_PSARB31_1 = 0x1

	// PSARC: Peripheral Security Attribution Register C
	// Position of PSARC0 field.
	PSCU_PSARC_PSARC0_Pos = 0x0
	// Bit mask of PSARC0 field.
	PSCU_PSARC_PSARC0_Msk = 0x1
	// Bit PSARC0.
	PSCU_PSARC_PSARC0 = 0x1
	// Secure
	PSCU_PSARC_PSARC0_0 = 0x0
	// Non-secure
	PSCU_PSARC_PSARC0_1 = 0x1
	// Position of PSARC1 field.
	PSCU_PSARC_PSARC1_Pos = 0x1
	// Bit mask of PSARC1 field.
	PSCU_PSARC_PSARC1_Msk = 0x2
	// Bit PSARC1.
	PSCU_PSARC_PSARC1 = 0x2
	// Secure
	PSCU_PSARC_PSARC1_0 = 0x0
	// Non-secure
	PSCU_PSARC_PSARC1_1 = 0x1
	// Position of PSARC8 field.
	PSCU_PSARC_PSARC8_Pos = 0x8
	// Bit mask of PSARC8 field.
	PSCU_PSARC_PSARC8_Msk = 0x100
	// Bit PSARC8.
	PSCU_PSARC_PSARC8 = 0x100
	// Secure
	PSCU_PSARC_PSARC8_0 = 0x0
	// Non-secure
	PSCU_PSARC_PSARC8_1 = 0x1
	// Position of PSARC13 field.
	PSCU_PSARC_PSARC13_Pos = 0xd
	// Bit mask of PSARC13 field.
	PSCU_PSARC_PSARC13_Msk = 0x2000
	// Bit PSARC13.
	PSCU_PSARC_PSARC13 = 0x2000
	// Secure
	PSCU_PSARC_PSARC13_0 = 0x0
	// Non-secure
	PSCU_PSARC_PSARC13_1 = 0x1
	// Position of PSARC27 field.
	PSCU_PSARC_PSARC27_Pos = 0x1b
	// Bit mask of PSARC27 field.
	PSCU_PSARC_PSARC27_Msk = 0x8000000
	// Bit PSARC27.
	PSCU_PSARC_PSARC27 = 0x8000000
	// Secure
	PSCU_PSARC_PSARC27_0 = 0x0
	// Non-secure
	PSCU_PSARC_PSARC27_1 = 0x1
	// Position of PSARC28 field.
	PSCU_PSARC_PSARC28_Pos = 0x1c
	// Bit mask of PSARC28 field.
	PSCU_PSARC_PSARC28_Msk = 0x10000000
	// Bit PSARC28.
	PSCU_PSARC_PSARC28 = 0x10000000
	// Secure
	PSCU_PSARC_PSARC28_0 = 0x0
	// Non-secure
	PSCU_PSARC_PSARC28_1 = 0x1

	// PSARD: Peripheral Security Attribution Register D
	// Position of PSARD2 field.
	PSCU_PSARD_PSARD2_Pos = 0x2
	// Bit mask of PSARD2 field.
	PSCU_PSARD_PSARD2_Msk = 0x4
	// Bit PSARD2.
	PSCU_PSARD_PSARD2 = 0x4
	// Secure
	PSCU_PSARD_PSARD2_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD2_1 = 0x1
	// Position of PSARD3 field.
	PSCU_PSARD_PSARD3_Pos = 0x3
	// Bit mask of PSARD3 field.
	PSCU_PSARD_PSARD3_Msk = 0x8
	// Bit PSARD3.
	PSCU_PSARD_PSARD3 = 0x8
	// Secure
	PSCU_PSARD_PSARD3_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD3_1 = 0x1
	// Position of PSARD11 field.
	PSCU_PSARD_PSARD11_Pos = 0xb
	// Bit mask of PSARD11 field.
	PSCU_PSARD_PSARD11_Msk = 0x800
	// Bit PSARD11.
	PSCU_PSARD_PSARD11 = 0x800
	// Secure
	PSCU_PSARD_PSARD11_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD11_1 = 0x1
	// Position of PSARD12 field.
	PSCU_PSARD_PSARD12_Pos = 0xc
	// Bit mask of PSARD12 field.
	PSCU_PSARD_PSARD12_Msk = 0x1000
	// Bit PSARD12.
	PSCU_PSARD_PSARD12 = 0x1000
	// Secure
	PSCU_PSARD_PSARD12_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD12_1 = 0x1
	// Position of PSARD13 field.
	PSCU_PSARD_PSARD13_Pos = 0xd
	// Bit mask of PSARD13 field.
	PSCU_PSARD_PSARD13_Msk = 0x2000
	// Bit PSARD13.
	PSCU_PSARD_PSARD13 = 0x2000
	// Secure
	PSCU_PSARD_PSARD13_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD13_1 = 0x1
	// Position of PSARD14 field.
	PSCU_PSARD_PSARD14_Pos = 0xe
	// Bit mask of PSARD14 field.
	PSCU_PSARD_PSARD14_Msk = 0x4000
	// Bit PSARD14.
	PSCU_PSARD_PSARD14 = 0x4000
	// Secure
	PSCU_PSARD_PSARD14_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD14_1 = 0x1
	// Position of PSARD16 field.
	PSCU_PSARD_PSARD16_Pos = 0x10
	// Bit mask of PSARD16 field.
	PSCU_PSARD_PSARD16_Msk = 0x10000
	// Bit PSARD16.
	PSCU_PSARD_PSARD16 = 0x10000
	// Secure
	PSCU_PSARD_PSARD16_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD16_1 = 0x1
	// Position of PSARD20 field.
	PSCU_PSARD_PSARD20_Pos = 0x14
	// Bit mask of PSARD20 field.
	PSCU_PSARD_PSARD20_Msk = 0x100000
	// Bit PSARD20.
	PSCU_PSARD_PSARD20 = 0x100000
	// Secure
	PSCU_PSARD_PSARD20_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD20_1 = 0x1
	// Position of PSARD22 field.
	PSCU_PSARD_PSARD22_Pos = 0x16
	// Bit mask of PSARD22 field.
	PSCU_PSARD_PSARD22_Msk = 0x400000
	// Bit PSARD22.
	PSCU_PSARD_PSARD22 = 0x400000
	// Secure
	PSCU_PSARD_PSARD22_0 = 0x0
	// Non-secure
	PSCU_PSARD_PSARD22_1 = 0x1

	// PSARE: Peripheral Security Attribution Register E
	// Position of PSARE0 field.
	PSCU_PSARE_PSARE0_Pos = 0x0
	// Bit mask of PSARE0 field.
	PSCU_PSARE_PSARE0_Msk = 0x1
	// Bit PSARE0.
	PSCU_PSARE_PSARE0 = 0x1
	// Secure
	PSCU_PSARE_PSARE0_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE0_1 = 0x1
	// Position of PSARE1 field.
	PSCU_PSARE_PSARE1_Pos = 0x1
	// Bit mask of PSARE1 field.
	PSCU_PSARE_PSARE1_Msk = 0x2
	// Bit PSARE1.
	PSCU_PSARE_PSARE1 = 0x2
	// Secure
	PSCU_PSARE_PSARE1_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE1_1 = 0x1
	// Position of PSARE2 field.
	PSCU_PSARE_PSARE2_Pos = 0x2
	// Bit mask of PSARE2 field.
	PSCU_PSARE_PSARE2_Msk = 0x4
	// Bit PSARE2.
	PSCU_PSARE_PSARE2 = 0x4
	// Secure
	PSCU_PSARE_PSARE2_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE2_1 = 0x1
	// Position of PSARE26 field.
	PSCU_PSARE_PSARE26_Pos = 0x1a
	// Bit mask of PSARE26 field.
	PSCU_PSARE_PSARE26_Msk = 0x4000000
	// Bit PSARE26.
	PSCU_PSARE_PSARE26 = 0x4000000
	// Secure
	PSCU_PSARE_PSARE26_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE26_1 = 0x1
	// Position of PSARE27 field.
	PSCU_PSARE_PSARE27_Pos = 0x1b
	// Bit mask of PSARE27 field.
	PSCU_PSARE_PSARE27_Msk = 0x8000000
	// Bit PSARE27.
	PSCU_PSARE_PSARE27 = 0x8000000
	// Secure
	PSCU_PSARE_PSARE27_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE27_1 = 0x1
	// Position of PSARE28 field.
	PSCU_PSARE_PSARE28_Pos = 0x1c
	// Bit mask of PSARE28 field.
	PSCU_PSARE_PSARE28_Msk = 0x10000000
	// Bit PSARE28.
	PSCU_PSARE_PSARE28 = 0x10000000
	// Secure
	PSCU_PSARE_PSARE28_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE28_1 = 0x1
	// Position of PSARE29 field.
	PSCU_PSARE_PSARE29_Pos = 0x1d
	// Bit mask of PSARE29 field.
	PSCU_PSARE_PSARE29_Msk = 0x20000000
	// Bit PSARE29.
	PSCU_PSARE_PSARE29 = 0x20000000
	// Secure
	PSCU_PSARE_PSARE29_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE29_1 = 0x1
	// Position of PSARE30 field.
	PSCU_PSARE_PSARE30_Pos = 0x1e
	// Bit mask of PSARE30 field.
	PSCU_PSARE_PSARE30_Msk = 0x40000000
	// Bit PSARE30.
	PSCU_PSARE_PSARE30 = 0x40000000
	// Secure
	PSCU_PSARE_PSARE30_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE30_1 = 0x1
	// Position of PSARE31 field.
	PSCU_PSARE_PSARE31_Pos = 0x1f
	// Bit mask of PSARE31 field.
	PSCU_PSARE_PSARE31_Msk = 0x80000000
	// Bit PSARE31.
	PSCU_PSARE_PSARE31 = 0x80000000
	// Secure
	PSCU_PSARE_PSARE31_0 = 0x0
	// Non-secure
	PSCU_PSARE_PSARE31_1 = 0x1

	// MSSAR: Module Stop Security Attribution Register
	// Position of MSSAR0 field.
	PSCU_MSSAR_MSSAR0_Pos = 0x0
	// Bit mask of MSSAR0 field.
	PSCU_MSSAR_MSSAR0_Msk = 0x1
	// Bit MSSAR0.
	PSCU_MSSAR_MSSAR0 = 0x1
	// Secure
	PSCU_MSSAR_MSSAR0_0 = 0x0
	// Non-secure
	PSCU_MSSAR_MSSAR0_1 = 0x1
	// Position of MSSAR1 field.
	PSCU_MSSAR_MSSAR1_Pos = 0x1
	// Bit mask of MSSAR1 field.
	PSCU_MSSAR_MSSAR1_Msk = 0x2
	// Bit MSSAR1.
	PSCU_MSSAR_MSSAR1 = 0x2
	// Secure
	PSCU_MSSAR_MSSAR1_0 = 0x0
	// Non-secure
	PSCU_MSSAR_MSSAR1_1 = 0x1
	// Position of MSSAR2 field.
	PSCU_MSSAR_MSSAR2_Pos = 0x2
	// Bit mask of MSSAR2 field.
	PSCU_MSSAR_MSSAR2_Msk = 0x4
	// Bit MSSAR2.
	PSCU_MSSAR_MSSAR2 = 0x4
	// Secure
	PSCU_MSSAR_MSSAR2_0 = 0x0
	// Non-secure
	PSCU_MSSAR_MSSAR2_1 = 0x1
	// Position of MSSAR3 field.
	PSCU_MSSAR_MSSAR3_Pos = 0x3
	// Bit mask of MSSAR3 field.
	PSCU_MSSAR_MSSAR3_Msk = 0x8
	// Bit MSSAR3.
	PSCU_MSSAR_MSSAR3 = 0x8
	// Secure
	PSCU_MSSAR_MSSAR3_0 = 0x0
	// Non-secure
	PSCU_MSSAR_MSSAR3_1 = 0x1

	// CFSAMONA: Code Flash Security Attribution Register A
	// Position of CFS2 field.
	PSCU_CFSAMONA_CFS2_Pos = 0xf
	// Bit mask of CFS2 field.
	PSCU_CFSAMONA_CFS2_Msk = 0xff8000

	// CFSAMONB: Code Flash Security Attribution Register B
	// Position of CFS1 field.
	PSCU_CFSAMONB_CFS1_Pos = 0xa
	// Bit mask of CFS1 field.
	PSCU_CFSAMONB_CFS1_Msk = 0xfffc00

	// DFSAMON: Data Flash Security Attribution Register
	// Position of DFS field.
	PSCU_DFSAMON_DFS_Pos = 0xa
	// Bit mask of DFS field.
	PSCU_DFSAMON_DFS_Msk = 0xfc00
	// 0 KB
	PSCU_DFSAMON_DFS_0x00 = 0x0
	// 1 KB
	PSCU_DFSAMON_DFS_0x01 = 0x1
	// 2 KB
	PSCU_DFSAMON_DFS_0x02 = 0x2
	// 3 KB
	PSCU_DFSAMON_DFS_0x03 = 0x3
	// 4 KB
	PSCU_DFSAMON_DFS_0x04 = 0x4
	// Setting prohibited
	PSCU_DFSAMON_DFS_Others = 0x5

	// SSAMONA: SRAM Security Attribution Register A
	// Position of SS2 field.
	PSCU_SSAMONA_SS2_Pos = 0xd
	// Bit mask of SS2 field.
	PSCU_SSAMONA_SS2_Msk = 0x1fe000
	// 0 KB
	PSCU_SSAMONA_SS2_0x000 = 0x0
	// 8 KB
	PSCU_SSAMONA_SS2_0x001 = 0x1
	// 16 KB
	PSCU_SSAMONA_SS2_0x002 = 0x2
	// 24 KB
	PSCU_SSAMONA_SS2_0x003 = 0x3
	// 32 KB
	PSCU_SSAMONA_SS2_0x004 = 0x4
	// 40 KB
	PSCU_SSAMONA_SS2_0x005 = 0x5
	// Setting prohibited
	PSCU_SSAMONA_SS2_Others = 0x6

	// SSAMONB: SRAM Security Attribution Register B
	// Position of SS1 field.
	PSCU_SSAMONB_SS1_Pos = 0xa
	// Bit mask of SS1 field.
	PSCU_SSAMONB_SS1_Msk = 0x1ffc00
)

// Constants for AGTW0: Low Power Asynchronous General Purpose Timer 0
const (
	// AGTCR: AGT Control Register
	// Position of TSTART field.
	AGTW0_AGTCR_TSTART_Pos = 0x0
	// Bit mask of TSTART field.
	AGTW0_AGTCR_TSTART_Msk = 0x1
	// Bit TSTART.
	AGTW0_AGTCR_TSTART = 0x1
	// Count stops
	AGTW0_AGTCR_TSTART_0 = 0x0
	// Count starts
	AGTW0_AGTCR_TSTART_1 = 0x1
	// Position of TCSTF field.
	AGTW0_AGTCR_TCSTF_Pos = 0x1
	// Bit mask of TCSTF field.
	AGTW0_AGTCR_TCSTF_Msk = 0x2
	// Bit TCSTF.
	AGTW0_AGTCR_TCSTF = 0x2
	// Count stopped
	AGTW0_AGTCR_TCSTF_0 = 0x0
	// Count in progress
	AGTW0_AGTCR_TCSTF_1 = 0x1
	// Position of TSTOP field.
	AGTW0_AGTCR_TSTOP_Pos = 0x2
	// Bit mask of TSTOP field.
	AGTW0_AGTCR_TSTOP_Msk = 0x4
	// Bit TSTOP.
	AGTW0_AGTCR_TSTOP = 0x4
	// Writing is invalid
	AGTW0_AGTCR_TSTOP_0 = 0x0
	// The count is forcibly stopped
	AGTW0_AGTCR_TSTOP_1 = 0x1
	// Position of TEDGF field.
	AGTW0_AGTCR_TEDGF_Pos = 0x4
	// Bit mask of TEDGF field.
	AGTW0_AGTCR_TEDGF_Msk = 0x10
	// Bit TEDGF.
	AGTW0_AGTCR_TEDGF = 0x10
	// No active edge received
	AGTW0_AGTCR_TEDGF_0 = 0x0
	// Active edge received
	AGTW0_AGTCR_TEDGF_1 = 0x1
	// Position of TUNDF field.
	AGTW0_AGTCR_TUNDF_Pos = 0x5
	// Bit mask of TUNDF field.
	AGTW0_AGTCR_TUNDF_Msk = 0x20
	// Bit TUNDF.
	AGTW0_AGTCR_TUNDF = 0x20
	// No underflow
	AGTW0_AGTCR_TUNDF_0 = 0x0
	// Underflow
	AGTW0_AGTCR_TUNDF_1 = 0x1
	// Position of TCMAF field.
	AGTW0_AGTCR_TCMAF_Pos = 0x6
	// Bit mask of TCMAF field.
	AGTW0_AGTCR_TCMAF_Msk = 0x40
	// Bit TCMAF.
	AGTW0_AGTCR_TCMAF = 0x40
	// No match
	AGTW0_AGTCR_TCMAF_0 = 0x0
	// Match
	AGTW0_AGTCR_TCMAF_1 = 0x1
	// Position of TCMBF field.
	AGTW0_AGTCR_TCMBF_Pos = 0x7
	// Bit mask of TCMBF field.
	AGTW0_AGTCR_TCMBF_Msk = 0x80
	// Bit TCMBF.
	AGTW0_AGTCR_TCMBF = 0x80
	// No match
	AGTW0_AGTCR_TCMBF_0 = 0x0
	// Match
	AGTW0_AGTCR_TCMBF_1 = 0x1

	// AGTMR1: AGT Mode Register 1
	// Position of TMOD field.
	AGTW0_AGTMR1_TMOD_Pos = 0x0
	// Bit mask of TMOD field.
	AGTW0_AGTMR1_TMOD_Msk = 0x7
	// Timer mode
	AGTW0_AGTMR1_TMOD_000 = 0x0
	// Pulse output mode
	AGTW0_AGTMR1_TMOD_001 = 0x1
	// Event counter mode
	AGTW0_AGTMR1_TMOD_010 = 0x2
	// Pulse width measurement mode
	AGTW0_AGTMR1_TMOD_011 = 0x3
	// Pulse period measurement mode
	AGTW0_AGTMR1_TMOD_100 = 0x4
	// Setting prohibited
	AGTW0_AGTMR1_TMOD_Others = 0x5
	// Position of TEDGPL field.
	AGTW0_AGTMR1_TEDGPL_Pos = 0x3
	// Bit mask of TEDGPL field.
	AGTW0_AGTMR1_TEDGPL_Msk = 0x8
	// Bit TEDGPL.
	AGTW0_AGTMR1_TEDGPL = 0x8
	// Single-edge
	AGTW0_AGTMR1_TEDGPL_0 = 0x0
	// Both-edge
	AGTW0_AGTMR1_TEDGPL_1 = 0x1
	// Position of TCK field.
	AGTW0_AGTMR1_TCK_Pos = 0x4
	// Bit mask of TCK field.
	AGTW0_AGTMR1_TCK_Msk = 0x70
	// PCLKB
	AGTW0_AGTMR1_TCK_000 = 0x0
	// PCLKB/8
	AGTW0_AGTMR1_TCK_001 = 0x1
	// PCLKB/2
	AGTW0_AGTMR1_TCK_011 = 0x3
	// Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register
	AGTW0_AGTMR1_TCK_100 = 0x4
	// Underflow event signal from AGT0
	AGTW0_AGTMR1_TCK_101 = 0x5
	// Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register
	AGTW0_AGTMR1_TCK_110 = 0x6
	// Setting prohibited
	AGTW0_AGTMR1_TCK_Others = 0x7

	// AGTMR2: AGT Mode Register 2
	// Position of CKS field.
	AGTW0_AGTMR2_CKS_Pos = 0x0
	// Bit mask of CKS field.
	AGTW0_AGTMR2_CKS_Msk = 0x7
	// 1/1
	AGTW0_AGTMR2_CKS_000 = 0x0
	// 1/2
	AGTW0_AGTMR2_CKS_001 = 0x1
	// 1/4
	AGTW0_AGTMR2_CKS_010 = 0x2
	// 1/8
	AGTW0_AGTMR2_CKS_011 = 0x3
	// 1/16
	AGTW0_AGTMR2_CKS_100 = 0x4
	// 1/32
	AGTW0_AGTMR2_CKS_101 = 0x5
	// 1/64
	AGTW0_AGTMR2_CKS_110 = 0x6
	// 1/128
	AGTW0_AGTMR2_CKS_111 = 0x7
	// Position of LPM field.
	AGTW0_AGTMR2_LPM_Pos = 0x7
	// Bit mask of LPM field.
	AGTW0_AGTMR2_LPM_Msk = 0x80
	// Bit LPM.
	AGTW0_AGTMR2_LPM = 0x80
	// Normal mode
	AGTW0_AGTMR2_LPM_0 = 0x0
	// Low power mode
	AGTW0_AGTMR2_LPM_1 = 0x1

	// AGTIOC: AGT I/O Control Register
	// Position of TEDGSEL field.
	AGTW0_AGTIOC_TEDGSEL_Pos = 0x0
	// Bit mask of TEDGSEL field.
	AGTW0_AGTIOC_TEDGSEL_Msk = 0x1
	// Bit TEDGSEL.
	AGTW0_AGTIOC_TEDGSEL = 0x1
	// Position of TOE field.
	AGTW0_AGTIOC_TOE_Pos = 0x2
	// Bit mask of TOE field.
	AGTW0_AGTIOC_TOE_Msk = 0x4
	// Bit TOE.
	AGTW0_AGTIOC_TOE = 0x4
	// AGTOn pin output disabled
	AGTW0_AGTIOC_TOE_0 = 0x0
	// AGTOn pin output enabled
	AGTW0_AGTIOC_TOE_1 = 0x1
	// Position of TIPF field.
	AGTW0_AGTIOC_TIPF_Pos = 0x4
	// Bit mask of TIPF field.
	AGTW0_AGTIOC_TIPF_Msk = 0x30
	// No filter
	AGTW0_AGTIOC_TIPF_00 = 0x0
	// Filter sampled at PCLKB
	AGTW0_AGTIOC_TIPF_01 = 0x1
	// Filter sampled at PCLKB/8
	AGTW0_AGTIOC_TIPF_10 = 0x2
	// Filter sampled at PCLKB/32
	AGTW0_AGTIOC_TIPF_11 = 0x3
	// Position of TIOGT field.
	AGTW0_AGTIOC_TIOGT_Pos = 0x6
	// Bit mask of TIOGT field.
	AGTW0_AGTIOC_TIOGT_Msk = 0xc0
	// Event is always counted
	AGTW0_AGTIOC_TIOGT_00 = 0x0
	// Event is counted during polarity period specified for AGTEEn pin
	AGTW0_AGTIOC_TIOGT_01 = 0x1
	// Setting prohibited
	AGTW0_AGTIOC_TIOGT_Others = 0x2

	// AGTISR: AGT Event Pin Select Register
	// Position of EEPS field.
	AGTW0_AGTISR_EEPS_Pos = 0x2
	// Bit mask of EEPS field.
	AGTW0_AGTISR_EEPS_Msk = 0x4
	// Bit EEPS.
	AGTW0_AGTISR_EEPS = 0x4
	// An event is counted during the low-level period
	AGTW0_AGTISR_EEPS_0 = 0x0
	// An event is counted during the high-level period
	AGTW0_AGTISR_EEPS_1 = 0x1

	// AGTCMSR: AGT Compare Match Function Select Register
	// Position of TCMEA field.
	AGTW0_AGTCMSR_TCMEA_Pos = 0x0
	// Bit mask of TCMEA field.
	AGTW0_AGTCMSR_TCMEA_Msk = 0x1
	// Bit TCMEA.
	AGTW0_AGTCMSR_TCMEA = 0x1
	// AGT Compare match A register disabled
	AGTW0_AGTCMSR_TCMEA_0 = 0x0
	// AGT Compare match A register enabled
	AGTW0_AGTCMSR_TCMEA_1 = 0x1
	// Position of TOEA field.
	AGTW0_AGTCMSR_TOEA_Pos = 0x1
	// Bit mask of TOEA field.
	AGTW0_AGTCMSR_TOEA_Msk = 0x2
	// Bit TOEA.
	AGTW0_AGTCMSR_TOEA = 0x2
	// AGTOAn pin output disabled
	AGTW0_AGTCMSR_TOEA_0 = 0x0
	// AGTOAn pin output enabled
	AGTW0_AGTCMSR_TOEA_1 = 0x1
	// Position of TOPOLA field.
	AGTW0_AGTCMSR_TOPOLA_Pos = 0x2
	// Bit mask of TOPOLA field.
	AGTW0_AGTCMSR_TOPOLA_Msk = 0x4
	// Bit TOPOLA.
	AGTW0_AGTCMSR_TOPOLA = 0x4
	// AGTOAn pin output is started on low. i.e. normal output
	AGTW0_AGTCMSR_TOPOLA_0 = 0x0
	// AGTOAn pin output is started on high. i.e. inverted output
	AGTW0_AGTCMSR_TOPOLA_1 = 0x1
	// Position of TCMEB field.
	AGTW0_AGTCMSR_TCMEB_Pos = 0x4
	// Bit mask of TCMEB field.
	AGTW0_AGTCMSR_TCMEB_Msk = 0x10
	// Bit TCMEB.
	AGTW0_AGTCMSR_TCMEB = 0x10
	// Compare match B register disabled
	AGTW0_AGTCMSR_TCMEB_0 = 0x0
	// Compare match B register enabled
	AGTW0_AGTCMSR_TCMEB_1 = 0x1
	// Position of TOEB field.
	AGTW0_AGTCMSR_TOEB_Pos = 0x5
	// Bit mask of TOEB field.
	AGTW0_AGTCMSR_TOEB_Msk = 0x20
	// Bit TOEB.
	AGTW0_AGTCMSR_TOEB = 0x20
	// AGTOBn pin output disabled
	AGTW0_AGTCMSR_TOEB_0 = 0x0
	// AGTOBn pin output enabled
	AGTW0_AGTCMSR_TOEB_1 = 0x1
	// Position of TOPOLB field.
	AGTW0_AGTCMSR_TOPOLB_Pos = 0x6
	// Bit mask of TOPOLB field.
	AGTW0_AGTCMSR_TOPOLB_Msk = 0x40
	// Bit TOPOLB.
	AGTW0_AGTCMSR_TOPOLB = 0x40
	// AGTOBn pin output is started on low. i.e. normal output
	AGTW0_AGTCMSR_TOPOLB_0 = 0x0
	// AGTOBn pin output is started on high. i.e. inverted output
	AGTW0_AGTCMSR_TOPOLB_1 = 0x1

	// AGTIOSEL: AGT Pin Select Register
	// Position of SEL field.
	AGTW0_AGTIOSEL_SEL_Pos = 0x0
	// Bit mask of SEL field.
	AGTW0_AGTIOSEL_SEL_Msk = 0x3
	// Select Pm/AGTIO as AGTIO. Pm/AGTIO can not be used as AGTIO input pin in Deep Software Standby mode. (m = 100, 301, and 407 (AGT0), m = P104, 207 and 400 (AGT1).)
	AGTW0_AGTIOSEL_SEL_00 = 0x0
	// Setting prohibited
	AGTW0_AGTIOSEL_SEL_01 = 0x1
	// Select P402/AGTIO as AGTIO. P402/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P402/AGTIOn is input only. It cannot be used for output.
	AGTW0_AGTIOSEL_SEL_10 = 0x2
	// Select P403/AGTIO as AGTIO. P403/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P403/AGTIOn is input only. It cannot be used for output.
	AGTW0_AGTIOSEL_SEL_11 = 0x3
	// Position of TIES field.
	AGTW0_AGTIOSEL_TIES_Pos = 0x4
	// Bit mask of TIES field.
	AGTW0_AGTIOSEL_TIES_Msk = 0x10
	// Bit TIES.
	AGTW0_AGTIOSEL_TIES = 0x10
	// External event input is disabled during Software Standby mode
	AGTW0_AGTIOSEL_TIES_0 = 0x0
	// External event input is enabled during Software Standby mode
	AGTW0_AGTIOSEL_TIES_1 = 0x1
)

// Constants for TSN: Temperature Sensor
const (
	// TSCR: Temperature Sensor Control Register
	// Position of TSOE field.
	TSN_TSCR_TSOE_Pos = 0x4
	// Bit mask of TSOE field.
	TSN_TSCR_TSOE_Msk = 0x10
	// Bit TSOE.
	TSN_TSCR_TSOE = 0x10
	// Disable output from the temperature sensor to the ADC12
	TSN_TSCR_TSOE_0 = 0x0
	// Enable output from the temperature sensor to the ADC12
	TSN_TSCR_TSOE_1 = 0x1
	// Position of TSEN field.
	TSN_TSCR_TSEN_Pos = 0x7
	// Bit mask of TSEN field.
	TSN_TSCR_TSEN_Msk = 0x80
	// Bit TSEN.
	TSN_TSCR_TSEN = 0x80
	// Stop the temperature sensor
	TSN_TSCR_TSEN_0 = 0x0
	// Start the temperature sensor.
	TSN_TSCR_TSEN_1 = 0x1
)

// Constants for CRC: Cyclic Redundancy Check Calculator
const (
	// CRCCR0: CRC Control Register 0
	// Position of GPS field.
	CRC_CRCCR0_GPS_Pos = 0x0
	// Bit mask of GPS field.
	CRC_CRCCR0_GPS_Msk = 0x7
	// No calculation is executed
	CRC_CRCCR0_GPS_Others = 0x0
	// 8-bit CRC-8 (X8 + X2 + X + 1)
	CRC_CRCCR0_GPS_001 = 0x1
	// 16-bit CRC-16 (X16 + X15 + X2 + 1)
	CRC_CRCCR0_GPS_010 = 0x2
	// 16-bit CRC-CCITT (X16 + X12 + X5 + 1)
	CRC_CRCCR0_GPS_011 = 0x3
	// 32-bit CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 +X10 + X8 + X7 + X5 + X4 + X2 + X + 1)
	CRC_CRCCR0_GPS_100 = 0x4
	// 32-bit CRC-32C (X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1)
	CRC_CRCCR0_GPS_101 = 0x5
	// Position of LMS field.
	CRC_CRCCR0_LMS_Pos = 0x6
	// Bit mask of LMS field.
	CRC_CRCCR0_LMS_Msk = 0x40
	// Bit LMS.
	CRC_CRCCR0_LMS = 0x40
	// Generate CRC code for LSB-first communication
	CRC_CRCCR0_LMS_0 = 0x0
	// Generate CRC code for MSB-first communication
	CRC_CRCCR0_LMS_1 = 0x1
	// Position of DORCLR field.
	CRC_CRCCR0_DORCLR_Pos = 0x7
	// Bit mask of DORCLR field.
	CRC_CRCCR0_DORCLR_Msk = 0x80
	// Bit DORCLR.
	CRC_CRCCR0_DORCLR = 0x80
	// No effect
	CRC_CRCCR0_DORCLR_0 = 0x0
	// Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register
	CRC_CRCCR0_DORCLR_1 = 0x1
)

// Constants for DOC: Data Operation Circuit
const (
	// DOCR: DOC Control Register
	// Position of OMS field.
	DOC_DOCR_OMS_Pos = 0x0
	// Bit mask of OMS field.
	DOC_DOCR_OMS_Msk = 0x3
	// Data comparison mode
	DOC_DOCR_OMS_00 = 0x0
	// Data addition mode
	DOC_DOCR_OMS_01 = 0x1
	// Data subtraction mode
	DOC_DOCR_OMS_10 = 0x2
	// Setting prohibited
	DOC_DOCR_OMS_11 = 0x3
	// Position of DCSEL field.
	DOC_DOCR_DCSEL_Pos = 0x2
	// Bit mask of DCSEL field.
	DOC_DOCR_DCSEL_Msk = 0x4
	// Bit DCSEL.
	DOC_DOCR_DCSEL = 0x4
	// Set DOPCF flag when data mismatch is detected
	DOC_DOCR_DCSEL_0 = 0x0
	// Set DOPCF flag when data match is detected
	DOC_DOCR_DCSEL_1 = 0x1
	// Position of DOPCF field.
	DOC_DOCR_DOPCF_Pos = 0x5
	// Bit mask of DOPCF field.
	DOC_DOCR_DOPCF_Msk = 0x20
	// Bit DOPCF.
	DOC_DOCR_DOPCF = 0x20
	// Position of DOPCFCL field.
	DOC_DOCR_DOPCFCL_Pos = 0x6
	// Bit mask of DOPCFCL field.
	DOC_DOCR_DOPCFCL_Msk = 0x40
	// Bit DOPCFCL.
	DOC_DOCR_DOPCFCL = 0x40
	// Retain DOPCF flag state
	DOC_DOCR_DOPCFCL_0 = 0x0
	// Clear DOPCF flag
	DOC_DOCR_DOPCFCL_1 = 0x1
)

// Constants for SCI0: Serial Communication Interface
const (
	// SMR: Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
	// Position of CKS field.
	SCI0_SMR_CKS_Pos = 0x0
	// Bit mask of CKS field.
	SCI0_SMR_CKS_Msk = 0x3
	// PCLK clock (n = 0)
	SCI0_SMR_CKS_00 = 0x0
	// PCLK/4 clock (n = 1)
	SCI0_SMR_CKS_01 = 0x1
	// PCLK/16 clock (n = 2)
	SCI0_SMR_CKS_10 = 0x2
	// PCLK/64 clock (n = 3)
	SCI0_SMR_CKS_11 = 0x3
	// Position of MP field.
	SCI0_SMR_MP_Pos = 0x2
	// Bit mask of MP field.
	SCI0_SMR_MP_Msk = 0x4
	// Bit MP.
	SCI0_SMR_MP = 0x4
	// Disable multi-processor communications function
	SCI0_SMR_MP_0 = 0x0
	// Enable multi-processor communications function
	SCI0_SMR_MP_1 = 0x1
	// Position of STOP field.
	SCI0_SMR_STOP_Pos = 0x3
	// Bit mask of STOP field.
	SCI0_SMR_STOP_Msk = 0x8
	// Bit STOP.
	SCI0_SMR_STOP = 0x8
	// 1 stop bit
	SCI0_SMR_STOP_0 = 0x0
	// 2 stop bits
	SCI0_SMR_STOP_1 = 0x1
	// Position of PM field.
	SCI0_SMR_PM_Pos = 0x4
	// Bit mask of PM field.
	SCI0_SMR_PM_Msk = 0x10
	// Bit PM.
	SCI0_SMR_PM = 0x10
	// Even parity
	SCI0_SMR_PM_0 = 0x0
	// Odd parity
	SCI0_SMR_PM_1 = 0x1
	// Position of PE field.
	SCI0_SMR_PE_Pos = 0x5
	// Bit mask of PE field.
	SCI0_SMR_PE_Msk = 0x20
	// Bit PE.
	SCI0_SMR_PE = 0x20
	// When transmitting: Do not add parity bit When receiving: Do not check parity bit
	SCI0_SMR_PE_0 = 0x0
	// When transmitting: Add parity bit When receiving: Check parity bit
	SCI0_SMR_PE_1 = 0x1
	// Position of CHR field.
	SCI0_SMR_CHR_Pos = 0x6
	// Bit mask of CHR field.
	SCI0_SMR_CHR_Msk = 0x40
	// Bit CHR.
	SCI0_SMR_CHR = 0x40
	// SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value)
	SCI0_SMR_CHR_0 = 0x0
	// SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length
	SCI0_SMR_CHR_1 = 0x1
	// Position of CM field.
	SCI0_SMR_CM_Pos = 0x7
	// Bit mask of CM field.
	SCI0_SMR_CM_Msk = 0x80
	// Bit CM.
	SCI0_SMR_CM = 0x80
	// Asynchronous mode or simple IIC mode
	SCI0_SMR_CM_0 = 0x0
	// Clock synchronous mode or simple SPI mode
	SCI0_SMR_CM_1 = 0x1

	// SMR_SMCI: Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)
	// Position of CKS field.
	SCI0_SMR_SMCI_CKS_Pos = 0x0
	// Bit mask of CKS field.
	SCI0_SMR_SMCI_CKS_Msk = 0x3
	// PCLK clock (n = 0)
	SCI0_SMR_SMCI_CKS_00 = 0x0
	// PCLK/4 clock (n = 1)
	SCI0_SMR_SMCI_CKS_01 = 0x1
	// PCLK/16 clock (n = 2)
	SCI0_SMR_SMCI_CKS_10 = 0x2
	// PCLK/64 clock (n = 3)
	SCI0_SMR_SMCI_CKS_11 = 0x3
	// Position of BCP field.
	SCI0_SMR_SMCI_BCP_Pos = 0x2
	// Bit mask of BCP field.
	SCI0_SMR_SMCI_BCP_Msk = 0xc
	// Position of PM field.
	SCI0_SMR_SMCI_PM_Pos = 0x4
	// Bit mask of PM field.
	SCI0_SMR_SMCI_PM_Msk = 0x10
	// Bit PM.
	SCI0_SMR_SMCI_PM = 0x10
	// Even parity
	SCI0_SMR_SMCI_PM_0 = 0x0
	// Odd parity
	SCI0_SMR_SMCI_PM_1 = 0x1
	// Position of PE field.
	SCI0_SMR_SMCI_PE_Pos = 0x5
	// Bit mask of PE field.
	SCI0_SMR_SMCI_PE_Msk = 0x20
	// Bit PE.
	SCI0_SMR_SMCI_PE = 0x20
	// Position of BLK field.
	SCI0_SMR_SMCI_BLK_Pos = 0x6
	// Bit mask of BLK field.
	SCI0_SMR_SMCI_BLK_Msk = 0x40
	// Bit BLK.
	SCI0_SMR_SMCI_BLK = 0x40
	// Normal mode operation
	SCI0_SMR_SMCI_BLK_0 = 0x0
	// Block transfer mode operation
	SCI0_SMR_SMCI_BLK_1 = 0x1
	// Position of GM field.
	SCI0_SMR_SMCI_GM_Pos = 0x7
	// Bit mask of GM field.
	SCI0_SMR_SMCI_GM_Msk = 0x80
	// Bit GM.
	SCI0_SMR_SMCI_GM = 0x80
	// Normal mode operation
	SCI0_SMR_SMCI_GM_0 = 0x0
	// GSM mode operation
	SCI0_SMR_SMCI_GM_1 = 0x1

	// SCR: Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)
	// Position of CKE field.
	SCI0_SCR_CKE_Pos = 0x0
	// Bit mask of CKE field.
	SCI0_SCR_CKE_Msk = 0x3
	// In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin.
	SCI0_SCR_CKE_00 = 0x0
	// In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin.
	SCI0_SCR_CKE_01 = 0x1
	// In asynchronous mode, input a clock with a frequency 16 times the bit rate from the SCKn pin when the SEMR.ABCS bit is 0. Input a clock signal with a frequency 8 times the bit rate when the SEMR.ABCS bit is 1. In clock synchronous mode, the SCKn pin functions as the clock input pin.
	SCI0_SCR_CKE_Others = 0x2
	// Position of TEIE field.
	SCI0_SCR_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	SCI0_SCR_TEIE_Msk = 0x4
	// Bit TEIE.
	SCI0_SCR_TEIE = 0x4
	// Disable SCIn_TEI interrupt requests
	SCI0_SCR_TEIE_0 = 0x0
	// Enable SCIn_TEI interrupt requests
	SCI0_SCR_TEIE_1 = 0x1
	// Position of MPIE field.
	SCI0_SCR_MPIE_Pos = 0x3
	// Bit mask of MPIE field.
	SCI0_SCR_MPIE_Msk = 0x8
	// Bit MPIE.
	SCI0_SCR_MPIE = 0x8
	// Normal reception
	SCI0_SCR_MPIE_0 = 0x0
	// When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 and the status flags SYER, PFER, and SBER in MESR are disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed.
	SCI0_SCR_MPIE_1 = 0x1
	// Position of RE field.
	SCI0_SCR_RE_Pos = 0x4
	// Bit mask of RE field.
	SCI0_SCR_RE_Msk = 0x10
	// Bit RE.
	SCI0_SCR_RE = 0x10
	// Disable serial reception
	SCI0_SCR_RE_0 = 0x0
	// Enable serial reception
	SCI0_SCR_RE_1 = 0x1
	// Position of TE field.
	SCI0_SCR_TE_Pos = 0x5
	// Bit mask of TE field.
	SCI0_SCR_TE_Msk = 0x20
	// Bit TE.
	SCI0_SCR_TE = 0x20
	// Disable serial transmission
	SCI0_SCR_TE_0 = 0x0
	// Enable serial transmission
	SCI0_SCR_TE_1 = 0x1
	// Position of RIE field.
	SCI0_SCR_RIE_Pos = 0x6
	// Bit mask of RIE field.
	SCI0_SCR_RIE_Msk = 0x40
	// Bit RIE.
	SCI0_SCR_RIE = 0x40
	// Disable SCIn_RXI and SCIn_ERI interrupt requests
	SCI0_SCR_RIE_0 = 0x0
	// Enable SCIn_RXI and SCIn_ERI interrupt requests
	SCI0_SCR_RIE_1 = 0x1
	// Position of TIE field.
	SCI0_SCR_TIE_Pos = 0x7
	// Bit mask of TIE field.
	SCI0_SCR_TIE_Msk = 0x80
	// Bit TIE.
	SCI0_SCR_TIE = 0x80
	// Disable SCIn_TXI interrupt requests
	SCI0_SCR_TIE_0 = 0x0
	// Enable SCIn_TXI interrupt requests
	SCI0_SCR_TIE_1 = 0x1

	// SCR_SMCI: Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)
	// Position of CKE field.
	SCI0_SCR_SMCI_CKE_Pos = 0x0
	// Bit mask of CKE field.
	SCI0_SCR_SMCI_CKE_Msk = 0x3
	// When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low
	SCI0_SCR_SMCI_CKE_00 = 0x0
	// When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock
	SCI0_SCR_SMCI_CKE_01 = 0x1
	// When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high
	SCI0_SCR_SMCI_CKE_10 = 0x2
	// When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock
	SCI0_SCR_SMCI_CKE_11 = 0x3
	// Position of TEIE field.
	SCI0_SCR_SMCI_TEIE_Pos = 0x2
	// Bit mask of TEIE field.
	SCI0_SCR_SMCI_TEIE_Msk = 0x4
	// Bit TEIE.
	SCI0_SCR_SMCI_TEIE = 0x4
	// Position of MPIE field.
	SCI0_SCR_SMCI_MPIE_Pos = 0x3
	// Bit mask of MPIE field.
	SCI0_SCR_SMCI_MPIE_Msk = 0x8
	// Bit MPIE.
	SCI0_SCR_SMCI_MPIE = 0x8
	// Position of RE field.
	SCI0_SCR_SMCI_RE_Pos = 0x4
	// Bit mask of RE field.
	SCI0_SCR_SMCI_RE_Msk = 0x10
	// Bit RE.
	SCI0_SCR_SMCI_RE = 0x10
	// Disable serial reception
	SCI0_SCR_SMCI_RE_0 = 0x0
	// Enable serial reception
	SCI0_SCR_SMCI_RE_1 = 0x1
	// Position of TE field.
	SCI0_SCR_SMCI_TE_Pos = 0x5
	// Bit mask of TE field.
	SCI0_SCR_SMCI_TE_Msk = 0x20
	// Bit TE.
	SCI0_SCR_SMCI_TE = 0x20
	// Disable serial transmission
	SCI0_SCR_SMCI_TE_0 = 0x0
	// Enable serial transmission
	SCI0_SCR_SMCI_TE_1 = 0x1
	// Position of RIE field.
	SCI0_SCR_SMCI_RIE_Pos = 0x6
	// Bit mask of RIE field.
	SCI0_SCR_SMCI_RIE_Msk = 0x40
	// Bit RIE.
	SCI0_SCR_SMCI_RIE = 0x40
	// Disable SCIn_RXI and SCIn_ERI interrupt requests
	SCI0_SCR_SMCI_RIE_0 = 0x0
	// Enable SCIn_RXI and SCIn_ERI interrupt requests
	SCI0_SCR_SMCI_RIE_1 = 0x1
	// Position of TIE field.
	SCI0_SCR_SMCI_TIE_Pos = 0x7
	// Bit mask of TIE field.
	SCI0_SCR_SMCI_TIE_Msk = 0x80
	// Bit TIE.
	SCI0_SCR_SMCI_TIE = 0x80
	// Disable SCIn_TXI interrupt requests
	SCI0_SCR_SMCI_TIE_0 = 0x0
	// Enable SCIn_TXI interrupt requests
	SCI0_SCR_SMCI_TIE_1 = 0x1

	// SSR: Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0, and MMR.MANEN = 0)
	// Position of MPBT field.
	SCI0_SSR_MPBT_Pos = 0x0
	// Bit mask of MPBT field.
	SCI0_SSR_MPBT_Msk = 0x1
	// Bit MPBT.
	SCI0_SSR_MPBT = 0x1
	// Data transmission cycle
	SCI0_SSR_MPBT_0 = 0x0
	// ID transmission cycle
	SCI0_SSR_MPBT_1 = 0x1
	// Position of MPB field.
	SCI0_SSR_MPB_Pos = 0x1
	// Bit mask of MPB field.
	SCI0_SSR_MPB_Msk = 0x2
	// Bit MPB.
	SCI0_SSR_MPB = 0x2
	// Data transmission cycle
	SCI0_SSR_MPB_0 = 0x0
	// ID transmission cycle
	SCI0_SSR_MPB_1 = 0x1
	// Position of TEND field.
	SCI0_SSR_TEND_Pos = 0x2
	// Bit mask of TEND field.
	SCI0_SSR_TEND_Msk = 0x4
	// Bit TEND.
	SCI0_SSR_TEND = 0x4
	// A character is being transmitted
	SCI0_SSR_TEND_0 = 0x0
	// Character transfer is complete
	SCI0_SSR_TEND_1 = 0x1
	// Position of PER field.
	SCI0_SSR_PER_Pos = 0x3
	// Bit mask of PER field.
	SCI0_SSR_PER_Msk = 0x8
	// Bit PER.
	SCI0_SSR_PER = 0x8
	// No parity error occurred
	SCI0_SSR_PER_0 = 0x0
	// Parity error occurred
	SCI0_SSR_PER_1 = 0x1
	// Position of FER field.
	SCI0_SSR_FER_Pos = 0x4
	// Bit mask of FER field.
	SCI0_SSR_FER_Msk = 0x10
	// Bit FER.
	SCI0_SSR_FER = 0x10
	// No framing error occurred
	SCI0_SSR_FER_0 = 0x0
	// Framing error occurred
	SCI0_SSR_FER_1 = 0x1
	// Position of ORER field.
	SCI0_SSR_ORER_Pos = 0x5
	// Bit mask of ORER field.
	SCI0_SSR_ORER_Msk = 0x20
	// Bit ORER.
	SCI0_SSR_ORER = 0x20
	// No overrun error occurred
	SCI0_SSR_ORER_0 = 0x0
	// Overrun error occurred
	SCI0_SSR_ORER_1 = 0x1
	// Position of RDRF field.
	SCI0_SSR_RDRF_Pos = 0x6
	// Bit mask of RDRF field.
	SCI0_SSR_RDRF_Msk = 0x40
	// Bit RDRF.
	SCI0_SSR_RDRF = 0x40
	// No received data in RDR register
	SCI0_SSR_RDRF_0 = 0x0
	// Received data in RDR register
	SCI0_SSR_RDRF_1 = 0x1
	// Position of TDRE field.
	SCI0_SSR_TDRE_Pos = 0x7
	// Bit mask of TDRE field.
	SCI0_SSR_TDRE_Msk = 0x80
	// Bit TDRE.
	SCI0_SSR_TDRE = 0x80
	// Transmit data in TDR register
	SCI0_SSR_TDRE_0 = 0x0
	// No transmit data in TDR register
	SCI0_SSR_TDRE_1 = 0x1

	// SSR_FIFO: Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0, FCR.FM = 1, and MMR.MANEN = 0)
	// Position of DR field.
	SCI0_SSR_FIFO_DR_Pos = 0x0
	// Bit mask of DR field.
	SCI0_SSR_FIFO_DR_Msk = 0x1
	// Bit DR.
	SCI0_SSR_FIFO_DR = 0x1
	// Receiving is in progress, or no received data remains in FRDRHL after successfully completed reception (receive FIFO empty)
	SCI0_SSR_FIFO_DR_0 = 0x0
	// Next receive data is not received for a period after normal receiving is complete, when the amount of data stored in the FIFO is equal to or less than the receive triggering number
	SCI0_SSR_FIFO_DR_1 = 0x1
	// Position of TEND field.
	SCI0_SSR_FIFO_TEND_Pos = 0x2
	// Bit mask of TEND field.
	SCI0_SSR_FIFO_TEND_Msk = 0x4
	// Bit TEND.
	SCI0_SSR_FIFO_TEND = 0x4
	// A character is being transmitted
	SCI0_SSR_FIFO_TEND_0 = 0x0
	// Character transfer is complete
	SCI0_SSR_FIFO_TEND_1 = 0x1
	// Position of PER field.
	SCI0_SSR_FIFO_PER_Pos = 0x3
	// Bit mask of PER field.
	SCI0_SSR_FIFO_PER_Msk = 0x8
	// Bit PER.
	SCI0_SSR_FIFO_PER = 0x8
	// No parity error occurred
	SCI0_SSR_FIFO_PER_0 = 0x0
	// Parity error occurred
	SCI0_SSR_FIFO_PER_1 = 0x1
	// Position of FER field.
	SCI0_SSR_FIFO_FER_Pos = 0x4
	// Bit mask of FER field.
	SCI0_SSR_FIFO_FER_Msk = 0x10
	// Bit FER.
	SCI0_SSR_FIFO_FER = 0x10
	// No framing error occurred
	SCI0_SSR_FIFO_FER_0 = 0x0
	// Framing error occurred
	SCI0_SSR_FIFO_FER_1 = 0x1
	// Position of ORER field.
	SCI0_SSR_FIFO_ORER_Pos = 0x5
	// Bit mask of ORER field.
	SCI0_SSR_FIFO_ORER_Msk = 0x20
	// Bit ORER.
	SCI0_SSR_FIFO_ORER = 0x20
	// No overrun error occurred
	SCI0_SSR_FIFO_ORER_0 = 0x0
	// Overrun error occurred
	SCI0_SSR_FIFO_ORER_1 = 0x1
	// Position of RDF field.
	SCI0_SSR_FIFO_RDF_Pos = 0x6
	// Bit mask of RDF field.
	SCI0_SSR_FIFO_RDF_Msk = 0x40
	// Bit RDF.
	SCI0_SSR_FIFO_RDF = 0x40
	// The amount of receive data written in FRDRHL is less than the specified receive triggering number
	SCI0_SSR_FIFO_RDF_0 = 0x0
	// The amount of receive data written in FRDRHL is equal to or greater than the specified receive triggering number
	SCI0_SSR_FIFO_RDF_1 = 0x1
	// Position of TDFE field.
	SCI0_SSR_FIFO_TDFE_Pos = 0x7
	// Bit mask of TDFE field.
	SCI0_SSR_FIFO_TDFE_Msk = 0x80
	// Bit TDFE.
	SCI0_SSR_FIFO_TDFE = 0x80
	// The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number
	SCI0_SSR_FIFO_TDFE_0 = 0x0
	// The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number
	SCI0_SSR_FIFO_TDFE_1 = 0x1

	// SSR_MANC: Serial Status Register for Manchester Mode (SCMR.SMIF = 0, and MMR.MANEN = 1)
	// Position of MER field.
	SCI0_SSR_MANC_MER_Pos = 0x0
	// Bit mask of MER field.
	SCI0_SSR_MANC_MER_Msk = 0x1
	// Bit MER.
	SCI0_SSR_MANC_MER = 0x1
	// No Manchester error occurred
	SCI0_SSR_MANC_MER_0 = 0x0
	// Manchester error has occurred
	SCI0_SSR_MANC_MER_1 = 0x1
	// Position of MPB field.
	SCI0_SSR_MANC_MPB_Pos = 0x1
	// Bit mask of MPB field.
	SCI0_SSR_MANC_MPB_Msk = 0x2
	// Bit MPB.
	SCI0_SSR_MANC_MPB = 0x2
	// Data transmission cycles
	SCI0_SSR_MANC_MPB_0 = 0x0
	// ID transmission cycles
	SCI0_SSR_MANC_MPB_1 = 0x1
	// Position of TEND field.
	SCI0_SSR_MANC_TEND_Pos = 0x2
	// Bit mask of TEND field.
	SCI0_SSR_MANC_TEND_Msk = 0x4
	// Bit TEND.
	SCI0_SSR_MANC_TEND = 0x4
	// A character is being transmitted
	SCI0_SSR_MANC_TEND_0 = 0x0
	// Character transfer has been completed.
	SCI0_SSR_MANC_TEND_1 = 0x1
	// Position of PER field.
	SCI0_SSR_MANC_PER_Pos = 0x3
	// Bit mask of PER field.
	SCI0_SSR_MANC_PER_Msk = 0x8
	// Bit PER.
	SCI0_SSR_MANC_PER = 0x8
	// No parity error occurred
	SCI0_SSR_MANC_PER_0 = 0x0
	// A parity error has occurred
	SCI0_SSR_MANC_PER_1 = 0x1
	// Position of FER field.
	SCI0_SSR_MANC_FER_Pos = 0x4
	// Bit mask of FER field.
	SCI0_SSR_MANC_FER_Msk = 0x10
	// Bit FER.
	SCI0_SSR_MANC_FER = 0x10
	// No framing error occurred
	SCI0_SSR_MANC_FER_0 = 0x0
	// A framing error has occurred
	SCI0_SSR_MANC_FER_1 = 0x1
	// Position of ORER field.
	SCI0_SSR_MANC_ORER_Pos = 0x5
	// Bit mask of ORER field.
	SCI0_SSR_MANC_ORER_Msk = 0x20
	// Bit ORER.
	SCI0_SSR_MANC_ORER = 0x20
	// No overrun error occurred
	SCI0_SSR_MANC_ORER_0 = 0x0
	// An overrun error has occurred
	SCI0_SSR_MANC_ORER_1 = 0x1
	// Position of RDRF field.
	SCI0_SSR_MANC_RDRF_Pos = 0x6
	// Bit mask of RDRF field.
	SCI0_SSR_MANC_RDRF_Msk = 0x40
	// Bit RDRF.
	SCI0_SSR_MANC_RDRF = 0x40
	// No received data is in RDR register
	SCI0_SSR_MANC_RDRF_0 = 0x0
	// Received data is in RDR register
	SCI0_SSR_MANC_RDRF_1 = 0x1
	// Position of TDRE field.
	SCI0_SSR_MANC_TDRE_Pos = 0x7
	// Bit mask of TDRE field.
	SCI0_SSR_MANC_TDRE_Msk = 0x80
	// Bit TDRE.
	SCI0_SSR_MANC_TDRE = 0x80
	// Transmit data is in TDR register
	SCI0_SSR_MANC_TDRE_0 = 0x0
	// No transmit data is in TDR register
	SCI0_SSR_MANC_TDRE_1 = 0x1

	// SSR_SMCI: Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1, and MMR.MANEN = 0)
	// Position of MPBT field.
	SCI0_SSR_SMCI_MPBT_Pos = 0x0
	// Bit mask of MPBT field.
	SCI0_SSR_SMCI_MPBT_Msk = 0x1
	// Bit MPBT.
	SCI0_SSR_SMCI_MPBT = 0x1
	// Position of MPB field.
	SCI0_SSR_SMCI_MPB_Pos = 0x1
	// Bit mask of MPB field.
	SCI0_SSR_SMCI_MPB_Msk = 0x2
	// Bit MPB.
	SCI0_SSR_SMCI_MPB = 0x2
	// Position of TEND field.
	SCI0_SSR_SMCI_TEND_Pos = 0x2
	// Bit mask of TEND field.
	SCI0_SSR_SMCI_TEND_Msk = 0x4
	// Bit TEND.
	SCI0_SSR_SMCI_TEND = 0x4
	// A character is being transmitted
	SCI0_SSR_SMCI_TEND_0 = 0x0
	// Character transfer is complete
	SCI0_SSR_SMCI_TEND_1 = 0x1
	// Position of PER field.
	SCI0_SSR_SMCI_PER_Pos = 0x3
	// Bit mask of PER field.
	SCI0_SSR_SMCI_PER_Msk = 0x8
	// Bit PER.
	SCI0_SSR_SMCI_PER = 0x8
	// No parity error occurred
	SCI0_SSR_SMCI_PER_0 = 0x0
	// Parity error occurred
	SCI0_SSR_SMCI_PER_1 = 0x1
	// Position of ERS field.
	SCI0_SSR_SMCI_ERS_Pos = 0x4
	// Bit mask of ERS field.
	SCI0_SSR_SMCI_ERS_Msk = 0x10
	// Bit ERS.
	SCI0_SSR_SMCI_ERS = 0x10
	// No low error signal response
	SCI0_SSR_SMCI_ERS_0 = 0x0
	// Low error signal response occurred
	SCI0_SSR_SMCI_ERS_1 = 0x1
	// Position of ORER field.
	SCI0_SSR_SMCI_ORER_Pos = 0x5
	// Bit mask of ORER field.
	SCI0_SSR_SMCI_ORER_Msk = 0x20
	// Bit ORER.
	SCI0_SSR_SMCI_ORER = 0x20
	// No overrun error occurred
	SCI0_SSR_SMCI_ORER_0 = 0x0
	// Overrun error occurred
	SCI0_SSR_SMCI_ORER_1 = 0x1
	// Position of RDRF field.
	SCI0_SSR_SMCI_RDRF_Pos = 0x6
	// Bit mask of RDRF field.
	SCI0_SSR_SMCI_RDRF_Msk = 0x40
	// Bit RDRF.
	SCI0_SSR_SMCI_RDRF = 0x40
	// No received data in RDR register
	SCI0_SSR_SMCI_RDRF_0 = 0x0
	// Received data in RDR register
	SCI0_SSR_SMCI_RDRF_1 = 0x1
	// Position of TDRE field.
	SCI0_SSR_SMCI_TDRE_Pos = 0x7
	// Bit mask of TDRE field.
	SCI0_SSR_SMCI_TDRE_Msk = 0x80
	// Bit TDRE.
	SCI0_SSR_SMCI_TDRE = 0x80
	// Transmit data in TDR register
	SCI0_SSR_SMCI_TDRE_0 = 0x0
	// No transmit data in TDR register
	SCI0_SSR_SMCI_TDRE_1 = 0x1

	// SCMR: Smart Card Mode Register
	// Position of SMIF field.
	SCI0_SCMR_SMIF_Pos = 0x0
	// Bit mask of SMIF field.
	SCI0_SCMR_SMIF_Msk = 0x1
	// Bit SMIF.
	SCI0_SCMR_SMIF = 0x1
	// Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode)
	SCI0_SCMR_SMIF_0 = 0x0
	// Smart card interface mode
	SCI0_SCMR_SMIF_1 = 0x1
	// Position of SINV field.
	SCI0_SCMR_SINV_Pos = 0x2
	// Bit mask of SINV field.
	SCI0_SCMR_SINV_Msk = 0x4
	// Bit SINV.
	SCI0_SCMR_SINV = 0x4
	// TDR contents are transmitted as they are. Received data is stored as received in the RDR register.
	SCI0_SCMR_SINV_0 = 0x0
	// TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register.
	SCI0_SCMR_SINV_1 = 0x1
	// Position of SDIR field.
	SCI0_SCMR_SDIR_Pos = 0x3
	// Bit mask of SDIR field.
	SCI0_SCMR_SDIR_Msk = 0x8
	// Bit SDIR.
	SCI0_SCMR_SDIR = 0x8
	// Transfer LSB-first
	SCI0_SCMR_SDIR_0 = 0x0
	// Transfer MSB-first
	SCI0_SCMR_SDIR_1 = 0x1
	// Position of CHR1 field.
	SCI0_SCMR_CHR1_Pos = 0x4
	// Bit mask of CHR1 field.
	SCI0_SCMR_CHR1_Msk = 0x10
	// Bit CHR1.
	SCI0_SCMR_CHR1 = 0x10
	// SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length
	SCI0_SCMR_CHR1_0 = 0x0
	// SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length
	SCI0_SCMR_CHR1_1 = 0x1
	// Position of BCP2 field.
	SCI0_SCMR_BCP2_Pos = 0x7
	// Bit mask of BCP2 field.
	SCI0_SCMR_BCP2_Msk = 0x80
	// Bit BCP2.
	SCI0_SCMR_BCP2 = 0x80

	// SEMR: Serial Extended Mode Register
	// Position of PADIS field.
	SCI0_SEMR_PADIS_Pos = 0x1
	// Bit mask of PADIS field.
	SCI0_SEMR_PADIS_Msk = 0x2
	// Bit PADIS.
	SCI0_SEMR_PADIS = 0x2
	// Preamble output function is enabled
	SCI0_SEMR_PADIS_0 = 0x0
	// Preamble output function is disabled
	SCI0_SEMR_PADIS_1 = 0x1
	// Position of BRME field.
	SCI0_SEMR_BRME_Pos = 0x2
	// Bit mask of BRME field.
	SCI0_SEMR_BRME_Msk = 0x4
	// Bit BRME.
	SCI0_SEMR_BRME = 0x4
	// Disable bit rate modulation function
	SCI0_SEMR_BRME_0 = 0x0
	// Enable bit rate modulation function
	SCI0_SEMR_BRME_1 = 0x1
	// Position of ABCSE field.
	SCI0_SEMR_ABCSE_Pos = 0x3
	// Bit mask of ABCSE field.
	SCI0_SEMR_ABCSE_Msk = 0x8
	// Bit ABCSE.
	SCI0_SEMR_ABCSE = 0x8
	// Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register
	SCI0_SEMR_ABCSE_0 = 0x0
	// Baud rate is 6 base clock cycles for 1-bit period
	SCI0_SEMR_ABCSE_1 = 0x1
	// Position of ABCS field.
	SCI0_SEMR_ABCS_Pos = 0x4
	// Bit mask of ABCS field.
	SCI0_SEMR_ABCS_Msk = 0x10
	// Bit ABCS.
	SCI0_SEMR_ABCS = 0x10
	// Select 16 base clock cycles for 1-bit period
	SCI0_SEMR_ABCS_0 = 0x0
	// Select 8 base clock cycles for 1-bit period
	SCI0_SEMR_ABCS_1 = 0x1
	// Position of NFEN field.
	SCI0_SEMR_NFEN_Pos = 0x5
	// Bit mask of NFEN field.
	SCI0_SEMR_NFEN_Msk = 0x20
	// Bit NFEN.
	SCI0_SEMR_NFEN = 0x20
	// In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals
	SCI0_SEMR_NFEN_0 = 0x0
	// In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals
	SCI0_SEMR_NFEN_1 = 0x1
	// Position of BGDM field.
	SCI0_SEMR_BGDM_Pos = 0x6
	// Bit mask of BGDM field.
	SCI0_SEMR_BGDM_Msk = 0x40
	// Bit BGDM.
	SCI0_SEMR_BGDM = 0x40
	// Output clock from baud rate generator with normal frequency
	SCI0_SEMR_BGDM_0 = 0x0
	// Output clock from baud rate generator with doubled frequency
	SCI0_SEMR_BGDM_1 = 0x1
	// Position of RXDESEL field.
	SCI0_SEMR_RXDESEL_Pos = 0x7
	// Bit mask of RXDESEL field.
	SCI0_SEMR_RXDESEL_Msk = 0x80
	// Bit RXDESEL.
	SCI0_SEMR_RXDESEL = 0x80
	// Detect low level on RXDn pin as start bit
	SCI0_SEMR_RXDESEL_0 = 0x0
	// Detect falling edge of RXDn pin as start bit
	SCI0_SEMR_RXDESEL_1 = 0x1

	// SNFR: Noise Filter Setting Register
	// Position of NFCS field.
	SCI0_SNFR_NFCS_Pos = 0x0
	// Bit mask of NFCS field.
	SCI0_SNFR_NFCS_Msk = 0x7
	// In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited
	SCI0_SNFR_NFCS_000 = 0x0
	// In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter
	SCI0_SNFR_NFCS_001 = 0x1
	// In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter
	SCI0_SNFR_NFCS_010 = 0x2
	// In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter
	SCI0_SNFR_NFCS_011 = 0x3
	// In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter
	SCI0_SNFR_NFCS_100 = 0x4
	// Setting prohibited
	SCI0_SNFR_NFCS_Others = 0x5

	// SIMR1: IIC Mode Register 1
	// Position of IICM field.
	SCI0_SIMR1_IICM_Pos = 0x0
	// Bit mask of IICM field.
	SCI0_SIMR1_IICM_Msk = 0x1
	// Bit IICM.
	SCI0_SIMR1_IICM = 0x1
	// SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode
	SCI0_SIMR1_IICM_0 = 0x0
	// SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited
	SCI0_SIMR1_IICM_1 = 0x1
	// Position of IICDL field.
	SCI0_SIMR1_IICDL_Pos = 0x3
	// Bit mask of IICDL field.
	SCI0_SIMR1_IICDL_Msk = 0xf8
	// No output delay
	SCI0_SIMR1_IICDL_0x00 = 0x0
	// (IICDL - 1) to (IICDL) cycles
	SCI0_SIMR1_IICDL_Others = 0x1

	// SIMR2: IIC Mode Register 2
	// Position of IICINTM field.
	SCI0_SIMR2_IICINTM_Pos = 0x0
	// Bit mask of IICINTM field.
	SCI0_SIMR2_IICINTM_Msk = 0x1
	// Bit IICINTM.
	SCI0_SIMR2_IICINTM = 0x1
	// Use ACK/NACK interrupts
	SCI0_SIMR2_IICINTM_0 = 0x0
	// Use reception and transmission interrupts
	SCI0_SIMR2_IICINTM_1 = 0x1
	// Position of IICCSC field.
	SCI0_SIMR2_IICCSC_Pos = 0x1
	// Bit mask of IICCSC field.
	SCI0_SIMR2_IICCSC_Msk = 0x2
	// Bit IICCSC.
	SCI0_SIMR2_IICCSC = 0x2
	// Do not synchronize with clock signal
	SCI0_SIMR2_IICCSC_0 = 0x0
	// Synchronize with clock signal
	SCI0_SIMR2_IICCSC_1 = 0x1
	// Position of IICACKT field.
	SCI0_SIMR2_IICACKT_Pos = 0x5
	// Bit mask of IICACKT field.
	SCI0_SIMR2_IICACKT_Msk = 0x20
	// Bit IICACKT.
	SCI0_SIMR2_IICACKT = 0x20
	// ACK transmission
	SCI0_SIMR2_IICACKT_0 = 0x0
	// NACK transmission and ACK/NACK reception
	SCI0_SIMR2_IICACKT_1 = 0x1

	// SIMR3: IIC Mode Register 3
	// Position of IICSTAREQ field.
	SCI0_SIMR3_IICSTAREQ_Pos = 0x0
	// Bit mask of IICSTAREQ field.
	SCI0_SIMR3_IICSTAREQ_Msk = 0x1
	// Bit IICSTAREQ.
	SCI0_SIMR3_IICSTAREQ = 0x1
	// Do not generate start condition
	SCI0_SIMR3_IICSTAREQ_0 = 0x0
	// Generate start condition
	SCI0_SIMR3_IICSTAREQ_1 = 0x1
	// Position of IICRSTAREQ field.
	SCI0_SIMR3_IICRSTAREQ_Pos = 0x1
	// Bit mask of IICRSTAREQ field.
	SCI0_SIMR3_IICRSTAREQ_Msk = 0x2
	// Bit IICRSTAREQ.
	SCI0_SIMR3_IICRSTAREQ = 0x2
	// Do not generate restart condition
	SCI0_SIMR3_IICRSTAREQ_0 = 0x0
	// Generate restart condition
	SCI0_SIMR3_IICRSTAREQ_1 = 0x1
	// Position of IICSTPREQ field.
	SCI0_SIMR3_IICSTPREQ_Pos = 0x2
	// Bit mask of IICSTPREQ field.
	SCI0_SIMR3_IICSTPREQ_Msk = 0x4
	// Bit IICSTPREQ.
	SCI0_SIMR3_IICSTPREQ = 0x4
	// Do not generate stop condition
	SCI0_SIMR3_IICSTPREQ_0 = 0x0
	// Generate stop condition
	SCI0_SIMR3_IICSTPREQ_1 = 0x1
	// Position of IICSTIF field.
	SCI0_SIMR3_IICSTIF_Pos = 0x3
	// Bit mask of IICSTIF field.
	SCI0_SIMR3_IICSTIF_Msk = 0x8
	// Bit IICSTIF.
	SCI0_SIMR3_IICSTIF = 0x8
	// No requests are being made for generating conditions, or a condition is being generated
	SCI0_SIMR3_IICSTIF_0 = 0x0
	// Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0
	SCI0_SIMR3_IICSTIF_1 = 0x1
	// Position of IICSDAS field.
	SCI0_SIMR3_IICSDAS_Pos = 0x4
	// Bit mask of IICSDAS field.
	SCI0_SIMR3_IICSDAS_Msk = 0x30
	// Output serial data
	SCI0_SIMR3_IICSDAS_00 = 0x0
	// Generate start, restart, or stop condition
	SCI0_SIMR3_IICSDAS_01 = 0x1
	// Output low on SDAn pin
	SCI0_SIMR3_IICSDAS_10 = 0x2
	// Drive SDAn pin to high-impedance state
	SCI0_SIMR3_IICSDAS_11 = 0x3
	// Position of IICSCLS field.
	SCI0_SIMR3_IICSCLS_Pos = 0x6
	// Bit mask of IICSCLS field.
	SCI0_SIMR3_IICSCLS_Msk = 0xc0
	// Output serial clock
	SCI0_SIMR3_IICSCLS_00 = 0x0
	// Generate start, restart, or stop condition
	SCI0_SIMR3_IICSCLS_01 = 0x1
	// Output low on SCLn pin
	SCI0_SIMR3_IICSCLS_10 = 0x2
	// Drive SCLn pin to high-impedance state
	SCI0_SIMR3_IICSCLS_11 = 0x3

	// SISR: IIC Status Register
	// Position of IICACKR field.
	SCI0_SISR_IICACKR_Pos = 0x0
	// Bit mask of IICACKR field.
	SCI0_SISR_IICACKR_Msk = 0x1
	// Bit IICACKR.
	SCI0_SISR_IICACKR = 0x1
	// ACK received
	SCI0_SISR_IICACKR_0 = 0x0
	// NACK received
	SCI0_SISR_IICACKR_1 = 0x1

	// SPMR: SPI Mode Register
	// Position of SSE field.
	SCI0_SPMR_SSE_Pos = 0x0
	// Bit mask of SSE field.
	SCI0_SPMR_SSE_Msk = 0x1
	// Bit SSE.
	SCI0_SPMR_SSE = 0x1
	// Disable SSn pin function
	SCI0_SPMR_SSE_0 = 0x0
	// Enable SSn pin function
	SCI0_SPMR_SSE_1 = 0x1
	// Position of CTSE field.
	SCI0_SPMR_CTSE_Pos = 0x1
	// Bit mask of CTSE field.
	SCI0_SPMR_CTSE_Msk = 0x2
	// Bit CTSE.
	SCI0_SPMR_CTSE = 0x2
	// Disable CTS function (enable RTS output function)
	SCI0_SPMR_CTSE_0 = 0x0
	// Enable CTS function
	SCI0_SPMR_CTSE_1 = 0x1
	// Position of MSS field.
	SCI0_SPMR_MSS_Pos = 0x2
	// Bit mask of MSS field.
	SCI0_SPMR_MSS_Msk = 0x4
	// Bit MSS.
	SCI0_SPMR_MSS = 0x4
	// Transmit through TXDn pin and receive through RXDn pin (master mode)
	SCI0_SPMR_MSS_0 = 0x0
	// Receive through TXDn pin and transmit through RXDn pin (slave mode)
	SCI0_SPMR_MSS_1 = 0x1
	// Position of CTSPEN field.
	SCI0_SPMR_CTSPEN_Pos = 0x3
	// Bit mask of CTSPEN field.
	SCI0_SPMR_CTSPEN_Msk = 0x8
	// Bit CTSPEN.
	SCI0_SPMR_CTSPEN = 0x8
	// Alternate setting to use CTS and RTS functions as either one terminal
	SCI0_SPMR_CTSPEN_0 = 0x0
	// Dedicated setting for separately using CTS and RTS functions with 2 terminals
	SCI0_SPMR_CTSPEN_1 = 0x1
	// Position of MFF field.
	SCI0_SPMR_MFF_Pos = 0x4
	// Bit mask of MFF field.
	SCI0_SPMR_MFF_Msk = 0x10
	// Bit MFF.
	SCI0_SPMR_MFF = 0x10
	// No mode fault error
	SCI0_SPMR_MFF_0 = 0x0
	// Mode fault error
	SCI0_SPMR_MFF_1 = 0x1
	// Position of CKPOL field.
	SCI0_SPMR_CKPOL_Pos = 0x6
	// Bit mask of CKPOL field.
	SCI0_SPMR_CKPOL_Msk = 0x40
	// Bit CKPOL.
	SCI0_SPMR_CKPOL = 0x40
	// Do not invert clock polarity
	SCI0_SPMR_CKPOL_0 = 0x0
	// Invert clock polarity
	SCI0_SPMR_CKPOL_1 = 0x1
	// Position of CKPH field.
	SCI0_SPMR_CKPH_Pos = 0x7
	// Bit mask of CKPH field.
	SCI0_SPMR_CKPH_Msk = 0x80
	// Bit CKPH.
	SCI0_SPMR_CKPH = 0x80
	// Do not delay clock
	SCI0_SPMR_CKPH_0 = 0x0
	// Delay clock
	SCI0_SPMR_CKPH_1 = 0x1

	// FTDRHL: Transmit FIFO Data Register
	// Position of TDAT field.
	SCI0_FTDRHL_TDAT_Pos = 0x0
	// Bit mask of TDAT field.
	SCI0_FTDRHL_TDAT_Msk = 0x1ff
	// Position of MPBT field.
	SCI0_FTDRHL_MPBT_Pos = 0x9
	// Bit mask of MPBT field.
	SCI0_FTDRHL_MPBT_Msk = 0x200
	// Bit MPBT.
	SCI0_FTDRHL_MPBT = 0x200
	// Data transmission cycle
	SCI0_FTDRHL_MPBT_0 = 0x0
	// ID transmission cycle
	SCI0_FTDRHL_MPBT_1 = 0x1

	// TDRHL: Transmit Data Register for Non-Manchester mode (MMR.MANEN = 0)
	// Position of TDAT field.
	SCI0_TDRHL_TDAT_Pos = 0x0
	// Bit mask of TDAT field.
	SCI0_TDRHL_TDAT_Msk = 0x1ff

	// TDRHL_MAN: Transmit Data Register for Manchester mode (MMR.MANEN = 1)
	// Position of TDAT field.
	SCI0_TDRHL_MAN_TDAT_Pos = 0x0
	// Bit mask of TDAT field.
	SCI0_TDRHL_MAN_TDAT_Msk = 0x1ff
	// Position of MPBT field.
	SCI0_TDRHL_MAN_MPBT_Pos = 0x9
	// Bit mask of MPBT field.
	SCI0_TDRHL_MAN_MPBT_Msk = 0x200
	// Bit MPBT.
	SCI0_TDRHL_MAN_MPBT = 0x200
	// Data transmission cycles
	SCI0_TDRHL_MAN_MPBT_0 = 0x0
	// ID transmission cycles
	SCI0_TDRHL_MAN_MPBT_1 = 0x1
	// Position of TSYNC field.
	SCI0_TDRHL_MAN_TSYNC_Pos = 0xc
	// Bit mask of TSYNC field.
	SCI0_TDRHL_MAN_TSYNC_Msk = 0x1000
	// Bit TSYNC.
	SCI0_TDRHL_MAN_TSYNC = 0x1000
	// The Start Bit is transmitted as DATA SYNC.
	SCI0_TDRHL_MAN_TSYNC_0 = 0x0
	// The Start Bit is transmitted as COMMAND SYNC.
	SCI0_TDRHL_MAN_TSYNC_1 = 0x1

	// FTDRH: Transmit FIFO Data Register
	// Position of MPBT field.
	SCI0_FTDRH_MPBT_Pos = 0x1
	// Bit mask of MPBT field.
	SCI0_FTDRH_MPBT_Msk = 0x2
	// Bit MPBT.
	SCI0_FTDRH_MPBT = 0x2
	// Data transmission cycle
	SCI0_FTDRH_MPBT_0 = 0x0
	// ID transmission cycle
	SCI0_FTDRH_MPBT_1 = 0x1

	// FTDRL: Transmit FIFO Data Register
	// Position of TDAT field.
	SCI0_FTDRL_TDAT_Pos = 0x0
	// Bit mask of TDAT field.
	SCI0_FTDRL_TDAT_Msk = 0xff

	// FRDRHL: Receive FIFO Data Register
	// Position of RDAT field.
	SCI0_FRDRHL_RDAT_Pos = 0x0
	// Bit mask of RDAT field.
	SCI0_FRDRHL_RDAT_Msk = 0x1ff
	// Position of MPB field.
	SCI0_FRDRHL_MPB_Pos = 0x9
	// Bit mask of MPB field.
	SCI0_FRDRHL_MPB_Msk = 0x200
	// Bit MPB.
	SCI0_FRDRHL_MPB = 0x200
	// Data transmission cycle
	SCI0_FRDRHL_MPB_0 = 0x0
	// ID transmission cycle
	SCI0_FRDRHL_MPB_1 = 0x1
	// Position of DR field.
	SCI0_FRDRHL_DR_Pos = 0xa
	// Bit mask of DR field.
	SCI0_FRDRHL_DR_Msk = 0x400
	// Bit DR.
	SCI0_FRDRHL_DR = 0x400
	// Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception
	SCI0_FRDRHL_DR_0 = 0x0
	// Next receive data is not received for a period after successfully completed reception
	SCI0_FRDRHL_DR_1 = 0x1
	// Position of PER field.
	SCI0_FRDRHL_PER_Pos = 0xb
	// Bit mask of PER field.
	SCI0_FRDRHL_PER_Msk = 0x800
	// Bit PER.
	SCI0_FRDRHL_PER = 0x800
	// No parity error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRHL_PER_0 = 0x0
	// Parity error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRHL_PER_1 = 0x1
	// Position of FER field.
	SCI0_FRDRHL_FER_Pos = 0xc
	// Bit mask of FER field.
	SCI0_FRDRHL_FER_Msk = 0x1000
	// Bit FER.
	SCI0_FRDRHL_FER = 0x1000
	// No framing error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRHL_FER_0 = 0x0
	// Framing error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRHL_FER_1 = 0x1
	// Position of ORER field.
	SCI0_FRDRHL_ORER_Pos = 0xd
	// Bit mask of ORER field.
	SCI0_FRDRHL_ORER_Msk = 0x2000
	// Bit ORER.
	SCI0_FRDRHL_ORER = 0x2000
	// No overrun error occurred
	SCI0_FRDRHL_ORER_0 = 0x0
	// Overrun error occurred
	SCI0_FRDRHL_ORER_1 = 0x1
	// Position of RDF field.
	SCI0_FRDRHL_RDF_Pos = 0xe
	// Bit mask of RDF field.
	SCI0_FRDRHL_RDF_Msk = 0x4000
	// Bit RDF.
	SCI0_FRDRHL_RDF = 0x4000
	// The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number
	SCI0_FRDRHL_RDF_0 = 0x0
	// The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number
	SCI0_FRDRHL_RDF_1 = 0x1

	// RDRHL: Receive Data Register for Non-Manchester mode (MMR.MANEN = 0)
	// Position of RDAT field.
	SCI0_RDRHL_RDAT_Pos = 0x0
	// Bit mask of RDAT field.
	SCI0_RDRHL_RDAT_Msk = 0x1ff

	// RDRHL_MAN: Receive Data Register for Manchester mode (MMR.MANEN = 1)
	// Position of RDAT field.
	SCI0_RDRHL_MAN_RDAT_Pos = 0x0
	// Bit mask of RDAT field.
	SCI0_RDRHL_MAN_RDAT_Msk = 0x1ff
	// Position of MPB field.
	SCI0_RDRHL_MAN_MPB_Pos = 0x9
	// Bit mask of MPB field.
	SCI0_RDRHL_MAN_MPB_Msk = 0x200
	// Bit MPB.
	SCI0_RDRHL_MAN_MPB = 0x200
	// Data transmission cycles
	SCI0_RDRHL_MAN_MPB_0 = 0x0
	// ID transmission cycles
	SCI0_RDRHL_MAN_MPB_1 = 0x1
	// Position of RSYNC field.
	SCI0_RDRHL_MAN_RSYNC_Pos = 0xc
	// Bit mask of RSYNC field.
	SCI0_RDRHL_MAN_RSYNC_Msk = 0x1000
	// Bit RSYNC.
	SCI0_RDRHL_MAN_RSYNC = 0x1000
	// The received the Start Bit is DATA SYNC
	SCI0_RDRHL_MAN_RSYNC_0 = 0x0
	// The received the Start Bit is COMMAND SYNC
	SCI0_RDRHL_MAN_RSYNC_1 = 0x1

	// FRDRH: Receive FIFO Data Register
	// Position of MPB field.
	SCI0_FRDRH_MPB_Pos = 0x1
	// Bit mask of MPB field.
	SCI0_FRDRH_MPB_Msk = 0x2
	// Bit MPB.
	SCI0_FRDRH_MPB = 0x2
	// Data transmission cycle
	SCI0_FRDRH_MPB_0 = 0x0
	// ID transmission cycle
	SCI0_FRDRH_MPB_1 = 0x1
	// Position of DR field.
	SCI0_FRDRH_DR_Pos = 0x2
	// Bit mask of DR field.
	SCI0_FRDRH_DR_Msk = 0x4
	// Bit DR.
	SCI0_FRDRH_DR = 0x4
	// Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception
	SCI0_FRDRH_DR_0 = 0x0
	// Next receive data is not received for a period after successfully completed reception
	SCI0_FRDRH_DR_1 = 0x1
	// Position of PER field.
	SCI0_FRDRH_PER_Pos = 0x3
	// Bit mask of PER field.
	SCI0_FRDRH_PER_Msk = 0x8
	// Bit PER.
	SCI0_FRDRH_PER = 0x8
	// No parity error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRH_PER_0 = 0x0
	// Parity error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRH_PER_1 = 0x1
	// Position of FER field.
	SCI0_FRDRH_FER_Pos = 0x4
	// Bit mask of FER field.
	SCI0_FRDRH_FER_Msk = 0x10
	// Bit FER.
	SCI0_FRDRH_FER = 0x10
	// No framing error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRH_FER_0 = 0x0
	// Framing error occurred in the first data of FRDRH and FRDRL
	SCI0_FRDRH_FER_1 = 0x1
	// Position of ORER field.
	SCI0_FRDRH_ORER_Pos = 0x5
	// Bit mask of ORER field.
	SCI0_FRDRH_ORER_Msk = 0x20
	// Bit ORER.
	SCI0_FRDRH_ORER = 0x20
	// No overrun error occurred
	SCI0_FRDRH_ORER_0 = 0x0
	// Overrun error occurred
	SCI0_FRDRH_ORER_1 = 0x1
	// Position of RDF field.
	SCI0_FRDRH_RDF_Pos = 0x6
	// Bit mask of RDF field.
	SCI0_FRDRH_RDF_Msk = 0x40
	// Bit RDF.
	SCI0_FRDRH_RDF = 0x40
	// The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number
	SCI0_FRDRH_RDF_0 = 0x0
	// The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number
	SCI0_FRDRH_RDF_1 = 0x1

	// FRDRL: Receive FIFO Data Register
	// Position of RDAT field.
	SCI0_FRDRL_RDAT_Pos = 0x0
	// Bit mask of RDAT field.
	SCI0_FRDRL_RDAT_Msk = 0xff

	// DCCR: Data Compare Match Control Register
	// Position of DCMF field.
	SCI0_DCCR_DCMF_Pos = 0x0
	// Bit mask of DCMF field.
	SCI0_DCCR_DCMF_Msk = 0x1
	// Bit DCMF.
	SCI0_DCCR_DCMF = 0x1
	// Not matched
	SCI0_DCCR_DCMF_0 = 0x0
	// Matched
	SCI0_DCCR_DCMF_1 = 0x1
	// Position of DPER field.
	SCI0_DCCR_DPER_Pos = 0x3
	// Bit mask of DPER field.
	SCI0_DCCR_DPER_Msk = 0x8
	// Bit DPER.
	SCI0_DCCR_DPER = 0x8
	// No parity error occurred
	SCI0_DCCR_DPER_0 = 0x0
	// Parity error occurred
	SCI0_DCCR_DPER_1 = 0x1
	// Position of DFER field.
	SCI0_DCCR_DFER_Pos = 0x4
	// Bit mask of DFER field.
	SCI0_DCCR_DFER_Msk = 0x10
	// Bit DFER.
	SCI0_DCCR_DFER = 0x10
	// No framing error occurred
	SCI0_DCCR_DFER_0 = 0x0
	// Framing error occurred
	SCI0_DCCR_DFER_1 = 0x1
	// Position of IDSEL field.
	SCI0_DCCR_IDSEL_Pos = 0x6
	// Bit mask of IDSEL field.
	SCI0_DCCR_IDSEL_Msk = 0x40
	// Bit IDSEL.
	SCI0_DCCR_IDSEL = 0x40
	// Always compare data regardless of the MPB bit value
	SCI0_DCCR_IDSEL_0 = 0x0
	// Only compare data when MPB bit = 1 (ID frame)
	SCI0_DCCR_IDSEL_1 = 0x1
	// Position of DCME field.
	SCI0_DCCR_DCME_Pos = 0x7
	// Bit mask of DCME field.
	SCI0_DCCR_DCME_Msk = 0x80
	// Bit DCME.
	SCI0_DCCR_DCME = 0x80
	// Disable address match function
	SCI0_DCCR_DCME_0 = 0x0
	// Enable address match function
	SCI0_DCCR_DCME_1 = 0x1

	// FCR: FIFO Control Register
	// Position of FM field.
	SCI0_FCR_FM_Pos = 0x0
	// Bit mask of FM field.
	SCI0_FCR_FM_Msk = 0x1
	// Bit FM.
	SCI0_FCR_FM = 0x1
	// Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL for communication.
	SCI0_FCR_FM_0 = 0x0
	// FIFO mode. Selects FTDRHL/FRDRHL for communication.
	SCI0_FCR_FM_1 = 0x1
	// Position of RFRST field.
	SCI0_FCR_RFRST_Pos = 0x1
	// Bit mask of RFRST field.
	SCI0_FCR_RFRST_Msk = 0x2
	// Bit RFRST.
	SCI0_FCR_RFRST = 0x2
	// Do not reset FRDRHL
	SCI0_FCR_RFRST_0 = 0x0
	// Reset FRDRHL
	SCI0_FCR_RFRST_1 = 0x1
	// Position of TFRST field.
	SCI0_FCR_TFRST_Pos = 0x2
	// Bit mask of TFRST field.
	SCI0_FCR_TFRST_Msk = 0x4
	// Bit TFRST.
	SCI0_FCR_TFRST = 0x4
	// Do not reset FTDRHL
	SCI0_FCR_TFRST_0 = 0x0
	// Reset FTDRHL
	SCI0_FCR_TFRST_1 = 0x1
	// Position of DRES field.
	SCI0_FCR_DRES_Pos = 0x3
	// Bit mask of DRES field.
	SCI0_FCR_DRES_Msk = 0x8
	// Bit DRES.
	SCI0_FCR_DRES = 0x8
	// Receive data full interrupt (SCIn_RXI)
	SCI0_FCR_DRES_0 = 0x0
	// Receive error interrupt (SCIn_ERI)
	SCI0_FCR_DRES_1 = 0x1
	// Position of TTRG field.
	SCI0_FCR_TTRG_Pos = 0x4
	// Bit mask of TTRG field.
	SCI0_FCR_TTRG_Msk = 0xf0
	// Position of RTRG field.
	SCI0_FCR_RTRG_Pos = 0x8
	// Bit mask of RTRG field.
	SCI0_FCR_RTRG_Msk = 0xf00
	// Position of RSTRG field.
	SCI0_FCR_RSTRG_Pos = 0xc
	// Bit mask of RSTRG field.
	SCI0_FCR_RSTRG_Msk = 0xf000

	// FDR: FIFO Data Count Register
	// Position of R field.
	SCI0_FDR_R_Pos = 0x0
	// Bit mask of R field.
	SCI0_FDR_R_Msk = 0x1f
	// Position of T field.
	SCI0_FDR_T_Pos = 0x8
	// Bit mask of T field.
	SCI0_FDR_T_Msk = 0x1f00

	// LSR: Line Status Register
	// Position of ORER field.
	SCI0_LSR_ORER_Pos = 0x0
	// Bit mask of ORER field.
	SCI0_LSR_ORER_Msk = 0x1
	// Bit ORER.
	SCI0_LSR_ORER = 0x1
	// No overrun error occurred
	SCI0_LSR_ORER_0 = 0x0
	// Overrun error occurred
	SCI0_LSR_ORER_1 = 0x1
	// Position of FNUM field.
	SCI0_LSR_FNUM_Pos = 0x2
	// Bit mask of FNUM field.
	SCI0_LSR_FNUM_Msk = 0x7c
	// Position of PNUM field.
	SCI0_LSR_PNUM_Pos = 0x8
	// Bit mask of PNUM field.
	SCI0_LSR_PNUM_Msk = 0x1f00

	// CDR: Compare Match Data Register
	// Position of CMPD field.
	SCI0_CDR_CMPD_Pos = 0x0
	// Bit mask of CMPD field.
	SCI0_CDR_CMPD_Msk = 0x1ff

	// SPTR: Serial Port Register
	// Position of RXDMON field.
	SCI0_SPTR_RXDMON_Pos = 0x0
	// Bit mask of RXDMON field.
	SCI0_SPTR_RXDMON_Msk = 0x1
	// Bit RXDMON.
	SCI0_SPTR_RXDMON = 0x1
	// When RINV is 0, RXDn terminal is the low level. When RINV is 1, RXDn terminal is the High level.
	SCI0_SPTR_RXDMON_0 = 0x0
	// When RINV is 0, RXDn terminal is the High level. When RINV is 1, RXDn terminal is the Low level.
	SCI0_SPTR_RXDMON_1 = 0x1
	// Position of SPB2DT field.
	SCI0_SPTR_SPB2DT_Pos = 0x1
	// Bit mask of SPB2DT field.
	SCI0_SPTR_SPB2DT_Msk = 0x2
	// Bit SPB2DT.
	SCI0_SPTR_SPB2DT = 0x2
	// When TINV is 0, Low level is output in TXDn terminal. When TINV is 1, High level is output in TXDn terminal.
	SCI0_SPTR_SPB2DT_0 = 0x0
	// When TINV is 0, High level is output in TXDn terminal. When TINV is 1, Low level is output in TXDn terminal.
	SCI0_SPTR_SPB2DT_1 = 0x1
	// Position of SPB2IO field.
	SCI0_SPTR_SPB2IO_Pos = 0x2
	// Bit mask of SPB2IO field.
	SCI0_SPTR_SPB2IO_Msk = 0x4
	// Bit SPB2IO.
	SCI0_SPTR_SPB2IO = 0x4
	// Do not output value of SPB2DT bit on TXDn pin
	SCI0_SPTR_SPB2IO_0 = 0x0
	// Output value of SPB2DT bit on TXDn pin
	SCI0_SPTR_SPB2IO_1 = 0x1
	// Position of RINV field.
	SCI0_SPTR_RINV_Pos = 0x4
	// Bit mask of RINV field.
	SCI0_SPTR_RINV_Msk = 0x10
	// Bit RINV.
	SCI0_SPTR_RINV = 0x10
	// Received data from RXDn is not inverted and input.
	SCI0_SPTR_RINV_0 = 0x0
	// Received data from RXDn is inverted and input.
	SCI0_SPTR_RINV_1 = 0x1
	// Position of TINV field.
	SCI0_SPTR_TINV_Pos = 0x5
	// Bit mask of TINV field.
	SCI0_SPTR_TINV_Msk = 0x20
	// Bit TINV.
	SCI0_SPTR_TINV = 0x20
	// Transmit data is not inverted and output to TXDn.
	SCI0_SPTR_TINV_0 = 0x0
	// Transmit data is inverted and output to TXDn.
	SCI0_SPTR_TINV_1 = 0x1
	// Position of ASEN field.
	SCI0_SPTR_ASEN_Pos = 0x6
	// Bit mask of ASEN field.
	SCI0_SPTR_ASEN_Msk = 0x40
	// Bit ASEN.
	SCI0_SPTR_ASEN = 0x40
	// Adjust sampling timing disable.
	SCI0_SPTR_ASEN_0 = 0x0
	// Adjust sampling timing enable.
	SCI0_SPTR_ASEN_1 = 0x1
	// Position of ATEN field.
	SCI0_SPTR_ATEN_Pos = 0x7
	// Bit mask of ATEN field.
	SCI0_SPTR_ATEN_Msk = 0x80
	// Bit ATEN.
	SCI0_SPTR_ATEN = 0x80
	// Adjust transmit timing disable.
	SCI0_SPTR_ATEN_0 = 0x0
	// Adjust transmit timing enable.
	SCI0_SPTR_ATEN_1 = 0x1

	// ACTR: Adjustment Communication Timing Register
	// Position of AST field.
	SCI0_ACTR_AST_Pos = 0x0
	// Bit mask of AST field.
	SCI0_ACTR_AST_Msk = 0x7
	// Position of AJD field.
	SCI0_ACTR_AJD_Pos = 0x3
	// Bit mask of AJD field.
	SCI0_ACTR_AJD_Msk = 0x8
	// Bit AJD.
	SCI0_ACTR_AJD = 0x8
	// The sampling timing is adjusted backward to the middle of bit.
	SCI0_ACTR_AJD_0 = 0x0
	// The sampling timing is adjusted forward to the middle of bit.
	SCI0_ACTR_AJD_1 = 0x1
	// Position of ATT field.
	SCI0_ACTR_ATT_Pos = 0x4
	// Bit mask of ATT field.
	SCI0_ACTR_ATT_Msk = 0x70
	// Position of AET field.
	SCI0_ACTR_AET_Pos = 0x7
	// Bit mask of AET field.
	SCI0_ACTR_AET_Msk = 0x80
	// Bit AET.
	SCI0_ACTR_AET = 0x80
	// Adjust the rising edge timing.
	SCI0_ACTR_AET_0 = 0x0
	// Adjust the falling edge timing.
	SCI0_ACTR_AET_1 = 0x1

	// MMR: Manchester Mode Register
	// Position of RMPOL field.
	SCI0_MMR_RMPOL_Pos = 0x0
	// Bit mask of RMPOL field.
	SCI0_MMR_RMPOL_Msk = 0x1
	// Bit RMPOL.
	SCI0_MMR_RMPOL = 0x1
	// Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code
	SCI0_MMR_RMPOL_0 = 0x0
	// Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code
	SCI0_MMR_RMPOL_1 = 0x1
	// Position of TMPOL field.
	SCI0_MMR_TMPOL_Pos = 0x1
	// Bit mask of TMPOL field.
	SCI0_MMR_TMPOL_Msk = 0x2
	// Bit TMPOL.
	SCI0_MMR_TMPOL = 0x2
	// Logic 0 is coded as a zero-to-one transition in Manchester code Logic 1 is coded as a one-to-zero transition in Manchester code
	SCI0_MMR_TMPOL_0 = 0x0
	// Logic 0 is coded as a one-to-zero transition in Manchester code Logic 1 is coded as a zero-to-one transition in Manchester code
	SCI0_MMR_TMPOL_1 = 0x1
	// Position of ERTEN field.
	SCI0_MMR_ERTEN_Pos = 0x2
	// Bit mask of ERTEN field.
	SCI0_MMR_ERTEN_Msk = 0x4
	// Bit ERTEN.
	SCI0_MMR_ERTEN = 0x4
	// Disables the receive retiming function
	SCI0_MMR_ERTEN_0 = 0x0
	// Enables the receive retiming function
	SCI0_MMR_ERTEN_1 = 0x1
	// Position of SYNVAL field.
	SCI0_MMR_SYNVAL_Pos = 0x4
	// Bit mask of SYNVAL field.
	SCI0_MMR_SYNVAL_Msk = 0x10
	// Bit SYNVAL.
	SCI0_MMR_SYNVAL = 0x10
	// The start bit is added as a zero-to-one transition.
	SCI0_MMR_SYNVAL_0 = 0x0
	// The start bit is added as a one-to-zero transition.
	SCI0_MMR_SYNVAL_1 = 0x1
	// Position of SYNSEL field.
	SCI0_MMR_SYNSEL_Pos = 0x5
	// Bit mask of SYNSEL field.
	SCI0_MMR_SYNSEL_Msk = 0x20
	// Bit SYNSEL.
	SCI0_MMR_SYNSEL = 0x20
	// The start bit pattern is set with the SYNVAL bit
	SCI0_MMR_SYNSEL_0 = 0x0
	// The start bit pattern is set with the TSYNC bit.
	SCI0_MMR_SYNSEL_1 = 0x1
	// Position of SBSEL field.
	SCI0_MMR_SBSEL_Pos = 0x6
	// Bit mask of SBSEL field.
	SCI0_MMR_SBSEL_Msk = 0x40
	// Bit SBSEL.
	SCI0_MMR_SBSEL = 0x40
	// The start bit area consists of one bit.
	SCI0_MMR_SBSEL_0 = 0x0
	// The start bit area consists of three bits (COMMAND SYNC or DATA SYNC)
	SCI0_MMR_SBSEL_1 = 0x1
	// Position of MANEN field.
	SCI0_MMR_MANEN_Pos = 0x7
	// Bit mask of MANEN field.
	SCI0_MMR_MANEN_Msk = 0x80
	// Bit MANEN.
	SCI0_MMR_MANEN = 0x80
	// Disables the Manchester mode
	SCI0_MMR_MANEN_0 = 0x0
	// Enables the Manchester mode
	SCI0_MMR_MANEN_1 = 0x1

	// TMPR: Transmit Manchester Preface Setting Register
	// Position of TPLEN field.
	SCI0_TMPR_TPLEN_Pos = 0x0
	// Bit mask of TPLEN field.
	SCI0_TMPR_TPLEN_Msk = 0xf
	// Disables the transmit preface generation
	SCI0_TMPR_TPLEN_0x0 = 0x0
	// Transmit preface length (bit length)
	SCI0_TMPR_TPLEN_Others = 0x1
	// Position of TPPAT field.
	SCI0_TMPR_TPPAT_Pos = 0x4
	// Bit mask of TPPAT field.
	SCI0_TMPR_TPPAT_Msk = 0x30
	// ALL ZERO
	SCI0_TMPR_TPPAT_00 = 0x0
	// ZERO ONE
	SCI0_TMPR_TPPAT_01 = 0x1
	// ONE ZERO
	SCI0_TMPR_TPPAT_10 = 0x2
	// ALL ONE
	SCI0_TMPR_TPPAT_11 = 0x3

	// RMPR: Receive Manchester Preface Setting Register
	// Position of RPLEN field.
	SCI0_RMPR_RPLEN_Pos = 0x0
	// Bit mask of RPLEN field.
	SCI0_RMPR_RPLEN_Msk = 0xf
	// Disables the receive preface generation
	SCI0_RMPR_RPLEN_0 = 0x0
	// Receive preface length (bit length)
	SCI0_RMPR_RPLEN_Others = 0x1
	// Position of RPPAT field.
	SCI0_RMPR_RPPAT_Pos = 0x4
	// Bit mask of RPPAT field.
	SCI0_RMPR_RPPAT_Msk = 0x30
	// ALL ZERO
	SCI0_RMPR_RPPAT_00 = 0x0
	// ZERO ONE
	SCI0_RMPR_RPPAT_01 = 0x1
	// ONE ZERO
	SCI0_RMPR_RPPAT_10 = 0x2
	// ALL ONE
	SCI0_RMPR_RPPAT_11 = 0x3

	// MESR: Manchester Extended Error Status Register
	// Position of PFER field.
	SCI0_MESR_PFER_Pos = 0x0
	// Bit mask of PFER field.
	SCI0_MESR_PFER_Msk = 0x1
	// Bit PFER.
	SCI0_MESR_PFER = 0x1
	// No preface error detected
	SCI0_MESR_PFER_0 = 0x0
	// Preface error detected
	SCI0_MESR_PFER_1 = 0x1
	// Position of SYER field.
	SCI0_MESR_SYER_Pos = 0x1
	// Bit mask of SYER field.
	SCI0_MESR_SYER_Msk = 0x2
	// Bit SYER.
	SCI0_MESR_SYER = 0x2
	// No receive SYNC error detected
	SCI0_MESR_SYER_0 = 0x0
	// Receive SYNC error detected
	SCI0_MESR_SYER_1 = 0x1
	// Position of SBER field.
	SCI0_MESR_SBER_Pos = 0x2
	// Bit mask of SBER field.
	SCI0_MESR_SBER_Msk = 0x4
	// Bit SBER.
	SCI0_MESR_SBER = 0x4
	// No start bit error detected
	SCI0_MESR_SBER_0 = 0x0
	// Start bit error detected
	SCI0_MESR_SBER_1 = 0x1

	// MECR: Manchester Extended Error Control Register
	// Position of PFEREN field.
	SCI0_MECR_PFEREN_Pos = 0x0
	// Bit mask of PFEREN field.
	SCI0_MECR_PFEREN_Msk = 0x1
	// Bit PFEREN.
	SCI0_MECR_PFEREN = 0x1
	// Does not handle a preface error as an interrupt source
	SCI0_MECR_PFEREN_0 = 0x0
	// Handles a preface error as an interrupt source
	SCI0_MECR_PFEREN_1 = 0x1
	// Position of SYEREN field.
	SCI0_MECR_SYEREN_Pos = 0x1
	// Bit mask of SYEREN field.
	SCI0_MECR_SYEREN_Msk = 0x2
	// Bit SYEREN.
	SCI0_MECR_SYEREN = 0x2
	// Does not handle a receive SYNC error as an interrupt source
	SCI0_MECR_SYEREN_0 = 0x0
	// Handles a receive SYNC error as an interrupt source
	SCI0_MECR_SYEREN_1 = 0x1
	// Position of SBEREN field.
	SCI0_MECR_SBEREN_Pos = 0x2
	// Bit mask of SBEREN field.
	SCI0_MECR_SBEREN_Msk = 0x4
	// Bit SBEREN.
	SCI0_MECR_SBEREN = 0x4
	// Does not handle a start bit error as an interrupt source
	SCI0_MECR_SBEREN_0 = 0x0
	// Handles a start bit error as an interrupt source
	SCI0_MECR_SBEREN_1 = 0x1
)

// Constants for SPI0: Serial Peripheral Interface 0
const (
	// SPCR: SPI Control Register
	// Position of SPMS field.
	SPI0_SPCR_SPMS_Pos = 0x0
	// Bit mask of SPMS field.
	SPI0_SPCR_SPMS_Msk = 0x1
	// Bit SPMS.
	SPI0_SPCR_SPMS = 0x1
	// Select SPI operation (4-wire method)
	SPI0_SPCR_SPMS_0 = 0x0
	// Select clock synchronous operation (3-wire method)
	SPI0_SPCR_SPMS_1 = 0x1
	// Position of TXMD field.
	SPI0_SPCR_TXMD_Pos = 0x1
	// Bit mask of TXMD field.
	SPI0_SPCR_TXMD_Msk = 0x2
	// Bit TXMD.
	SPI0_SPCR_TXMD = 0x2
	// Select full-duplex synchronous serial communications
	SPI0_SPCR_TXMD_0 = 0x0
	// Select serial communications with transmit-only
	SPI0_SPCR_TXMD_1 = 0x1
	// Position of MODFEN field.
	SPI0_SPCR_MODFEN_Pos = 0x2
	// Bit mask of MODFEN field.
	SPI0_SPCR_MODFEN_Msk = 0x4
	// Bit MODFEN.
	SPI0_SPCR_MODFEN = 0x4
	// Disable detection of mode fault errors
	SPI0_SPCR_MODFEN_0 = 0x0
	// Enable detection of mode fault errors
	SPI0_SPCR_MODFEN_1 = 0x1
	// Position of MSTR field.
	SPI0_SPCR_MSTR_Pos = 0x3
	// Bit mask of MSTR field.
	SPI0_SPCR_MSTR_Msk = 0x8
	// Bit MSTR.
	SPI0_SPCR_MSTR = 0x8
	// Select slave mode
	SPI0_SPCR_MSTR_0 = 0x0
	// Select master mode
	SPI0_SPCR_MSTR_1 = 0x1
	// Position of SPEIE field.
	SPI0_SPCR_SPEIE_Pos = 0x4
	// Bit mask of SPEIE field.
	SPI0_SPCR_SPEIE_Msk = 0x10
	// Bit SPEIE.
	SPI0_SPCR_SPEIE = 0x10
	// Disable SPI error interrupt requests
	SPI0_SPCR_SPEIE_0 = 0x0
	// Enable SPI error interrupt requests
	SPI0_SPCR_SPEIE_1 = 0x1
	// Position of SPTIE field.
	SPI0_SPCR_SPTIE_Pos = 0x5
	// Bit mask of SPTIE field.
	SPI0_SPCR_SPTIE_Msk = 0x20
	// Bit SPTIE.
	SPI0_SPCR_SPTIE = 0x20
	// Disable transmit buffer empty interrupt requests
	SPI0_SPCR_SPTIE_0 = 0x0
	// Enable transmit buffer empty interrupt requests
	SPI0_SPCR_SPTIE_1 = 0x1
	// Position of SPE field.
	SPI0_SPCR_SPE_Pos = 0x6
	// Bit mask of SPE field.
	SPI0_SPCR_SPE_Msk = 0x40
	// Bit SPE.
	SPI0_SPCR_SPE = 0x40
	// Disable SPI function
	SPI0_SPCR_SPE_0 = 0x0
	// Enable SPI function
	SPI0_SPCR_SPE_1 = 0x1
	// Position of SPRIE field.
	SPI0_SPCR_SPRIE_Pos = 0x7
	// Bit mask of SPRIE field.
	SPI0_SPCR_SPRIE_Msk = 0x80
	// Bit SPRIE.
	SPI0_SPCR_SPRIE = 0x80
	// Disable SPI receive buffer full interrupt requests
	SPI0_SPCR_SPRIE_0 = 0x0
	// Enable SPI receive buffer full interrupt requests
	SPI0_SPCR_SPRIE_1 = 0x1

	// SSLP: SPI Slave Select Polarity Register
	// Position of SSL0P field.
	SPI0_SSLP_SSL0P_Pos = 0x0
	// Bit mask of SSL0P field.
	SPI0_SSLP_SSL0P_Msk = 0x1
	// Bit SSL0P.
	SPI0_SSLP_SSL0P = 0x1
	// Set SSLn0 signal to active-low
	SPI0_SSLP_SSL0P_0 = 0x0
	// Set SSLn0 signal to active-high
	SPI0_SSLP_SSL0P_1 = 0x1
	// Position of SSL1P field.
	SPI0_SSLP_SSL1P_Pos = 0x1
	// Bit mask of SSL1P field.
	SPI0_SSLP_SSL1P_Msk = 0x2
	// Bit SSL1P.
	SPI0_SSLP_SSL1P = 0x2
	// Set SSLn1 signal to active-low
	SPI0_SSLP_SSL1P_0 = 0x0
	// Set SSLn1 signal to active-high
	SPI0_SSLP_SSL1P_1 = 0x1
	// Position of SSL2P field.
	SPI0_SSLP_SSL2P_Pos = 0x2
	// Bit mask of SSL2P field.
	SPI0_SSLP_SSL2P_Msk = 0x4
	// Bit SSL2P.
	SPI0_SSLP_SSL2P = 0x4
	// Set SSLn2 signal to active-low
	SPI0_SSLP_SSL2P_0 = 0x0
	// Set SSLn2 signal to active-high
	SPI0_SSLP_SSL2P_1 = 0x1
	// Position of SSL3P field.
	SPI0_SSLP_SSL3P_Pos = 0x3
	// Bit mask of SSL3P field.
	SPI0_SSLP_SSL3P_Msk = 0x8
	// Bit SSL3P.
	SPI0_SSLP_SSL3P = 0x8
	// Set SSLn3 signal to active-low
	SPI0_SSLP_SSL3P_0 = 0x0
	// Set SSLn3 signal to active-high
	SPI0_SSLP_SSL3P_1 = 0x1

	// SPPCR: SPI Pin Control Register
	// Position of SPLP field.
	SPI0_SPPCR_SPLP_Pos = 0x0
	// Bit mask of SPLP field.
	SPI0_SPPCR_SPLP_Msk = 0x1
	// Bit SPLP.
	SPI0_SPPCR_SPLP = 0x1
	// Normal mode
	SPI0_SPPCR_SPLP_0 = 0x0
	// Loopback mode (receive data = inverted transmit data)
	SPI0_SPPCR_SPLP_1 = 0x1
	// Position of SPLP2 field.
	SPI0_SPPCR_SPLP2_Pos = 0x1
	// Bit mask of SPLP2 field.
	SPI0_SPPCR_SPLP2_Msk = 0x2
	// Bit SPLP2.
	SPI0_SPPCR_SPLP2 = 0x2
	// Normal mode
	SPI0_SPPCR_SPLP2_0 = 0x0
	// Loopback mode (receive data = transmit data)
	SPI0_SPPCR_SPLP2_1 = 0x1
	// Position of MOIFV field.
	SPI0_SPPCR_MOIFV_Pos = 0x4
	// Bit mask of MOIFV field.
	SPI0_SPPCR_MOIFV_Msk = 0x10
	// Bit MOIFV.
	SPI0_SPPCR_MOIFV = 0x10
	// Set level output on MOSIn pin during MOSI idling to low
	SPI0_SPPCR_MOIFV_0 = 0x0
	// Set level output on MOSIn pin during MOSI idling to high
	SPI0_SPPCR_MOIFV_1 = 0x1
	// Position of MOIFE field.
	SPI0_SPPCR_MOIFE_Pos = 0x5
	// Bit mask of MOIFE field.
	SPI0_SPPCR_MOIFE_Msk = 0x20
	// Bit MOIFE.
	SPI0_SPPCR_MOIFE = 0x20
	// Set MOSI output value to equal final data from previous transfer
	SPI0_SPPCR_MOIFE_0 = 0x0
	// Set MOSI output value to equal value set in the MOIFV bit
	SPI0_SPPCR_MOIFE_1 = 0x1

	// SPSR: SPI Status Register
	// Position of OVRF field.
	SPI0_SPSR_OVRF_Pos = 0x0
	// Bit mask of OVRF field.
	SPI0_SPSR_OVRF_Msk = 0x1
	// Bit OVRF.
	SPI0_SPSR_OVRF = 0x1
	// No overrun error occurred
	SPI0_SPSR_OVRF_0 = 0x0
	// Overrun error occurred
	SPI0_SPSR_OVRF_1 = 0x1
	// Position of IDLNF field.
	SPI0_SPSR_IDLNF_Pos = 0x1
	// Bit mask of IDLNF field.
	SPI0_SPSR_IDLNF_Msk = 0x2
	// Bit IDLNF.
	SPI0_SPSR_IDLNF = 0x2
	// SPI is in the idle state
	SPI0_SPSR_IDLNF_0 = 0x0
	// SPI is in the transfer state
	SPI0_SPSR_IDLNF_1 = 0x1
	// Position of MODF field.
	SPI0_SPSR_MODF_Pos = 0x2
	// Bit mask of MODF field.
	SPI0_SPSR_MODF_Msk = 0x4
	// Bit MODF.
	SPI0_SPSR_MODF = 0x4
	// No mode fault or underrun error occurred
	SPI0_SPSR_MODF_0 = 0x0
	// Mode fault error or underrun error occurred
	SPI0_SPSR_MODF_1 = 0x1
	// Position of PERF field.
	SPI0_SPSR_PERF_Pos = 0x3
	// Bit mask of PERF field.
	SPI0_SPSR_PERF_Msk = 0x8
	// Bit PERF.
	SPI0_SPSR_PERF = 0x8
	// No parity error occurred
	SPI0_SPSR_PERF_0 = 0x0
	// Parity error occurred
	SPI0_SPSR_PERF_1 = 0x1
	// Position of UDRF field.
	SPI0_SPSR_UDRF_Pos = 0x4
	// Bit mask of UDRF field.
	SPI0_SPSR_UDRF_Msk = 0x10
	// Bit UDRF.
	SPI0_SPSR_UDRF = 0x10
	// Mode fault error occurred (MODF = 1)
	SPI0_SPSR_UDRF_0 = 0x0
	// Underrun error occurred (MODF = 1)
	SPI0_SPSR_UDRF_1 = 0x1
	// Position of SPTEF field.
	SPI0_SPSR_SPTEF_Pos = 0x5
	// Bit mask of SPTEF field.
	SPI0_SPSR_SPTEF_Msk = 0x20
	// Bit SPTEF.
	SPI0_SPSR_SPTEF = 0x20
	// Data is in the transmit buffer
	SPI0_SPSR_SPTEF_0 = 0x0
	// No data is in the transmit buffer
	SPI0_SPSR_SPTEF_1 = 0x1
	// Position of CENDF field.
	SPI0_SPSR_CENDF_Pos = 0x6
	// Bit mask of CENDF field.
	SPI0_SPSR_CENDF_Msk = 0x40
	// Bit CENDF.
	SPI0_SPSR_CENDF = 0x40
	// Not communicating or communicating
	SPI0_SPSR_CENDF_0 = 0x0
	// Communication completed
	SPI0_SPSR_CENDF_1 = 0x1
	// Position of SPRF field.
	SPI0_SPSR_SPRF_Pos = 0x7
	// Bit mask of SPRF field.
	SPI0_SPSR_SPRF_Msk = 0x80
	// Bit SPRF.
	SPI0_SPSR_SPRF = 0x80
	// No valid data is in SPDR/SPDR_HA
	SPI0_SPSR_SPRF_0 = 0x0
	// Valid data is in SPDR/SPDR_HA
	SPI0_SPSR_SPRF_1 = 0x1

	// SPSCR: SPI Sequence Control Register
	// Position of SPSLN field.
	SPI0_SPSCR_SPSLN_Pos = 0x0
	// Bit mask of SPSLN field.
	SPI0_SPSCR_SPSLN_Msk = 0x7
	// Sequence Length is 1 (Referenced SPCMDn, n = 0→0→…)
	SPI0_SPSCR_SPSLN_000 = 0x0
	// Sequence Length is 2 (Referenced SPCMDn, n = 0→1→0→…)
	SPI0_SPSCR_SPSLN_001 = 0x1
	// Sequence Length is 3 (Referenced SPCMDn, n = 0→1→2→0→…)
	SPI0_SPSCR_SPSLN_010 = 0x2
	// Sequence Length is 4 (Referenced SPCMDn, n = 0→1→2→3→0→…)
	SPI0_SPSCR_SPSLN_011 = 0x3
	// Sequence Length is 5 (Referenced SPCMDn, n = 0→1→2→3→4→0→…)
	SPI0_SPSCR_SPSLN_100 = 0x4
	// Sequence Length is 6 (Referenced SPCMDn, n = 0→1→2→3→4→5→0→…)
	SPI0_SPSCR_SPSLN_101 = 0x5
	// Sequence Length is 7 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→0→…)
	SPI0_SPSCR_SPSLN_110 = 0x6
	// Sequence Length is 8 (Referenced SPCMDn, n = 0→1→2→3→4→5→6→7→0→…)
	SPI0_SPSCR_SPSLN_111 = 0x7

	// SPSSR: SPI Sequence Status Register
	// Position of SPCP field.
	SPI0_SPSSR_SPCP_Pos = 0x0
	// Bit mask of SPCP field.
	SPI0_SPSSR_SPCP_Msk = 0x7
	// SPCMD0
	SPI0_SPSSR_SPCP_000 = 0x0
	// SPCMD1
	SPI0_SPSSR_SPCP_001 = 0x1
	// SPCMD2
	SPI0_SPSSR_SPCP_010 = 0x2
	// SPCMD3
	SPI0_SPSSR_SPCP_011 = 0x3
	// SPCMD4
	SPI0_SPSSR_SPCP_100 = 0x4
	// SPCMD5
	SPI0_SPSSR_SPCP_101 = 0x5
	// SPCMD6
	SPI0_SPSSR_SPCP_110 = 0x6
	// SPCMD7
	SPI0_SPSSR_SPCP_111 = 0x7
	// Position of SPECM field.
	SPI0_SPSSR_SPECM_Pos = 0x4
	// Bit mask of SPECM field.
	SPI0_SPSSR_SPECM_Msk = 0x70
	// SPCMD0
	SPI0_SPSSR_SPECM_000 = 0x0
	// SPCMD1
	SPI0_SPSSR_SPECM_001 = 0x1
	// SPCMD2
	SPI0_SPSSR_SPECM_010 = 0x2
	// SPCMD3
	SPI0_SPSSR_SPECM_011 = 0x3
	// SPCMD4
	SPI0_SPSSR_SPECM_100 = 0x4
	// SPCMD5
	SPI0_SPSSR_SPECM_101 = 0x5
	// SPCMD6
	SPI0_SPSSR_SPECM_110 = 0x6
	// SPCMD7
	SPI0_SPSSR_SPECM_111 = 0x7

	// SPDCR: SPI Data Control Register
	// Position of SPFC field.
	SPI0_SPDCR_SPFC_Pos = 0x0
	// Bit mask of SPFC field.
	SPI0_SPDCR_SPFC_Msk = 0x3
	// 1 frame
	SPI0_SPDCR_SPFC_00 = 0x0
	// 2 frames
	SPI0_SPDCR_SPFC_01 = 0x1
	// 3 frames
	SPI0_SPDCR_SPFC_10 = 0x2
	// 4 frames
	SPI0_SPDCR_SPFC_11 = 0x3
	// Position of SPRDTD field.
	SPI0_SPDCR_SPRDTD_Pos = 0x4
	// Bit mask of SPRDTD field.
	SPI0_SPDCR_SPRDTD_Msk = 0x10
	// Bit SPRDTD.
	SPI0_SPDCR_SPRDTD = 0x10
	// Read SPDR/SPDR_HA values from receive buffer
	SPI0_SPDCR_SPRDTD_0 = 0x0
	// Read SPDR/SPDR_HA values from transmit buffer, but only if the transmit buffer is empty
	SPI0_SPDCR_SPRDTD_1 = 0x1
	// Position of SPLW field.
	SPI0_SPDCR_SPLW_Pos = 0x5
	// Bit mask of SPLW field.
	SPI0_SPDCR_SPLW_Msk = 0x20
	// Bit SPLW.
	SPI0_SPDCR_SPLW = 0x20
	// Set SPDR_HA to valid for halfword access
	SPI0_SPDCR_SPLW_0 = 0x0
	// Set SPDR to valid for word access
	SPI0_SPDCR_SPLW_1 = 0x1
	// Position of SPBYT field.
	SPI0_SPDCR_SPBYT_Pos = 0x6
	// Bit mask of SPBYT field.
	SPI0_SPDCR_SPBYT_Msk = 0x40
	// Bit SPBYT.
	SPI0_SPDCR_SPBYT = 0x40
	// SPDR/SPDR_HA is accessed in halfword or word (SPLW is valid)
	SPI0_SPDCR_SPBYT_0 = 0x0
	// SPDR_BY is accessed in byte (SPLW is invalid)
	SPI0_SPDCR_SPBYT_1 = 0x1

	// SPCKD: SPI Clock Delay Register
	// Position of SCKDL field.
	SPI0_SPCKD_SCKDL_Pos = 0x0
	// Bit mask of SCKDL field.
	SPI0_SPCKD_SCKDL_Msk = 0x7
	// 1 RSPCK
	SPI0_SPCKD_SCKDL_000 = 0x0
	// 2 RSPCK
	SPI0_SPCKD_SCKDL_001 = 0x1
	// 3 RSPCK
	SPI0_SPCKD_SCKDL_010 = 0x2
	// 4 RSPCK
	SPI0_SPCKD_SCKDL_011 = 0x3
	// 5 RSPCK
	SPI0_SPCKD_SCKDL_100 = 0x4
	// 6 RSPCK
	SPI0_SPCKD_SCKDL_101 = 0x5
	// 7 RSPCK
	SPI0_SPCKD_SCKDL_110 = 0x6
	// 8 RSPCK
	SPI0_SPCKD_SCKDL_111 = 0x7

	// SSLND: SPI Slave Select Negation Delay Register
	// Position of SLNDL field.
	SPI0_SSLND_SLNDL_Pos = 0x0
	// Bit mask of SLNDL field.
	SPI0_SSLND_SLNDL_Msk = 0x7
	// 1 RSPCK
	SPI0_SSLND_SLNDL_000 = 0x0
	// 2 RSPCK
	SPI0_SSLND_SLNDL_001 = 0x1
	// 3 RSPCK
	SPI0_SSLND_SLNDL_010 = 0x2
	// 4 RSPCK
	SPI0_SSLND_SLNDL_011 = 0x3
	// 5 RSPCK
	SPI0_SSLND_SLNDL_100 = 0x4
	// 6 RSPCK
	SPI0_SSLND_SLNDL_101 = 0x5
	// 7 RSPCK
	SPI0_SSLND_SLNDL_110 = 0x6
	// 8 RSPCK
	SPI0_SSLND_SLNDL_111 = 0x7

	// SPND: SPI Next-Access Delay Register
	// Position of SPNDL field.
	SPI0_SPND_SPNDL_Pos = 0x0
	// Bit mask of SPNDL field.
	SPI0_SPND_SPNDL_Msk = 0x7
	// 1 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_000 = 0x0
	// 2 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_001 = 0x1
	// 3 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_010 = 0x2
	// 4 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_011 = 0x3
	// 5 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_100 = 0x4
	// 6 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_101 = 0x5
	// 7 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_110 = 0x6
	// 8 RSPCK + 2 PCLKA
	SPI0_SPND_SPNDL_111 = 0x7

	// SPCR2: SPI Control Register 2
	// Position of SPPE field.
	SPI0_SPCR2_SPPE_Pos = 0x0
	// Bit mask of SPPE field.
	SPI0_SPCR2_SPPE_Msk = 0x1
	// Bit SPPE.
	SPI0_SPCR2_SPPE = 0x1
	// Do not add parity bit to transmit data and do not check parity bit of receive data
	SPI0_SPCR2_SPPE_0 = 0x0
	// When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data
	SPI0_SPCR2_SPPE_1 = 0x1
	// Position of SPOE field.
	SPI0_SPCR2_SPOE_Pos = 0x1
	// Bit mask of SPOE field.
	SPI0_SPCR2_SPOE_Msk = 0x2
	// Bit SPOE.
	SPI0_SPCR2_SPOE = 0x2
	// Select even parity for transmission and reception
	SPI0_SPCR2_SPOE_0 = 0x0
	// Select odd parity for transmission and reception
	SPI0_SPCR2_SPOE_1 = 0x1
	// Position of SPIIE field.
	SPI0_SPCR2_SPIIE_Pos = 0x2
	// Bit mask of SPIIE field.
	SPI0_SPCR2_SPIIE_Msk = 0x4
	// Bit SPIIE.
	SPI0_SPCR2_SPIIE = 0x4
	// Disable idle interrupt requests
	SPI0_SPCR2_SPIIE_0 = 0x0
	// Enable idle interrupt requests
	SPI0_SPCR2_SPIIE_1 = 0x1
	// Position of PTE field.
	SPI0_SPCR2_PTE_Pos = 0x3
	// Bit mask of PTE field.
	SPI0_SPCR2_PTE_Msk = 0x8
	// Bit PTE.
	SPI0_SPCR2_PTE = 0x8
	// Disable self-diagnosis function of the parity circuit
	SPI0_SPCR2_PTE_0 = 0x0
	// Enable self-diagnosis function of the parity circuit
	SPI0_SPCR2_PTE_1 = 0x1
	// Position of SCKASE field.
	SPI0_SPCR2_SCKASE_Pos = 0x4
	// Bit mask of SCKASE field.
	SPI0_SPCR2_SCKASE_Msk = 0x10
	// Bit SCKASE.
	SPI0_SPCR2_SCKASE = 0x10
	// Disable RSPCK auto-stop function
	SPI0_SPCR2_SCKASE_0 = 0x0
	// Enable RSPCK auto-stop function
	SPI0_SPCR2_SCKASE_1 = 0x1

	// SPCMD0: SPI Command Register %s
	// Position of CPHA field.
	SPI0_SPCMD_CPHA_Pos = 0x0
	// Bit mask of CPHA field.
	SPI0_SPCMD_CPHA_Msk = 0x1
	// Bit CPHA.
	SPI0_SPCMD_CPHA = 0x1
	// Select data sampling on leading edge, data change on trailing edge
	SPI0_SPCMD_CPHA_0 = 0x0
	// Select data change on leading edge, data sampling on trailing edge
	SPI0_SPCMD_CPHA_1 = 0x1
	// Position of CPOL field.
	SPI0_SPCMD_CPOL_Pos = 0x1
	// Bit mask of CPOL field.
	SPI0_SPCMD_CPOL_Msk = 0x2
	// Bit CPOL.
	SPI0_SPCMD_CPOL = 0x2
	// Set RSPCK low during idle
	SPI0_SPCMD_CPOL_0 = 0x0
	// Set RSPCK high during idle
	SPI0_SPCMD_CPOL_1 = 0x1
	// Position of BRDV field.
	SPI0_SPCMD_BRDV_Pos = 0x2
	// Bit mask of BRDV field.
	SPI0_SPCMD_BRDV_Msk = 0xc
	// Base bit rate
	SPI0_SPCMD_BRDV_00 = 0x0
	// Base bit rate divided by 2
	SPI0_SPCMD_BRDV_01 = 0x1
	// Base bit rate divided by 4
	SPI0_SPCMD_BRDV_10 = 0x2
	// Base bit rate divided by 8
	SPI0_SPCMD_BRDV_11 = 0x3
	// Position of SSLA field.
	SPI0_SPCMD_SSLA_Pos = 0x4
	// Bit mask of SSLA field.
	SPI0_SPCMD_SSLA_Msk = 0x70
	// SSL0
	SPI0_SPCMD_SSLA_000 = 0x0
	// SSL1
	SPI0_SPCMD_SSLA_001 = 0x1
	// SSL2
	SPI0_SPCMD_SSLA_010 = 0x2
	// SSL3
	SPI0_SPCMD_SSLA_011 = 0x3
	// Setting prohibited
	SPI0_SPCMD_SSLA_Others = 0x4
	// Position of SSLKP field.
	SPI0_SPCMD_SSLKP_Pos = 0x7
	// Bit mask of SSLKP field.
	SPI0_SPCMD_SSLKP_Msk = 0x80
	// Bit SSLKP.
	SPI0_SPCMD_SSLKP = 0x80
	// Negate all SSL signals on completion of transfer
	SPI0_SPCMD_SSLKP_0 = 0x0
	// Keep SSL signal level from the end of transfer until the beginning of the next access
	SPI0_SPCMD_SSLKP_1 = 0x1
	// Position of SPB field.
	SPI0_SPCMD_SPB_Pos = 0x8
	// Bit mask of SPB field.
	SPI0_SPCMD_SPB_Msk = 0xf00
	// 20 bits
	SPI0_SPCMD_SPB_0x0 = 0x0
	// 24 bits
	SPI0_SPCMD_SPB_0x1 = 0x1
	// 32 bits
	SPI0_SPCMD_SPB_0x2 = 0x2
	// 32 bits
	SPI0_SPCMD_SPB_0x3 = 0x3
	// 9 bits
	SPI0_SPCMD_SPB_0x8 = 0x8
	// 10 bits
	SPI0_SPCMD_SPB_0x9 = 0x9
	// 11 bits
	SPI0_SPCMD_SPB_0xA = 0xa
	// 12 bits
	SPI0_SPCMD_SPB_0xB = 0xb
	// 13 bits
	SPI0_SPCMD_SPB_0xC = 0xc
	// 14 bits
	SPI0_SPCMD_SPB_0xD = 0xd
	// 15 bits
	SPI0_SPCMD_SPB_0xE = 0xe
	// 16 bits
	SPI0_SPCMD_SPB_0xF = 0xf
	// 8 bits
	SPI0_SPCMD_SPB_Others = 0x4
	// Position of LSBF field.
	SPI0_SPCMD_LSBF_Pos = 0xc
	// Bit mask of LSBF field.
	SPI0_SPCMD_LSBF_Msk = 0x1000
	// Bit LSBF.
	SPI0_SPCMD_LSBF = 0x1000
	// MSB-first
	SPI0_SPCMD_LSBF_0 = 0x0
	// LSB-first
	SPI0_SPCMD_LSBF_1 = 0x1
	// Position of SPNDEN field.
	SPI0_SPCMD_SPNDEN_Pos = 0xd
	// Bit mask of SPNDEN field.
	SPI0_SPCMD_SPNDEN_Msk = 0x2000
	// Bit SPNDEN.
	SPI0_SPCMD_SPNDEN = 0x2000
	// Select next-access delay of 1 RSPCK + 2 PCLKA
	SPI0_SPCMD_SPNDEN_0 = 0x0
	// Select next-access delay equal to the setting in the SPI Next-Access Delay Register (SPND)
	SPI0_SPCMD_SPNDEN_1 = 0x1
	// Position of SLNDEN field.
	SPI0_SPCMD_SLNDEN_Pos = 0xe
	// Bit mask of SLNDEN field.
	SPI0_SPCMD_SLNDEN_Msk = 0x4000
	// Bit SLNDEN.
	SPI0_SPCMD_SLNDEN = 0x4000
	// Select SSL negation delay of 1 RSPCK
	SPI0_SPCMD_SLNDEN_0 = 0x0
	// Select SSL negation delay equal to the setting in the SPI Slave Select Negation Delay Register (SSLND)
	SPI0_SPCMD_SLNDEN_1 = 0x1
	// Position of SCKDEN field.
	SPI0_SPCMD_SCKDEN_Pos = 0xf
	// Bit mask of SCKDEN field.
	SPI0_SPCMD_SCKDEN_Msk = 0x8000
	// Bit SCKDEN.
	SPI0_SPCMD_SCKDEN = 0x8000
	// Select RSPCK delay of 1 RSPCK
	SPI0_SPCMD_SCKDEN_0 = 0x0
	// Select RSPCK delay equal to the setting in the SPI Clock Delay Register (SPCKD)
	SPI0_SPCMD_SCKDEN_1 = 0x1

	// SPDCR2: SPI Data Control Register 2
	// Position of BYSW field.
	SPI0_SPDCR2_BYSW_Pos = 0x0
	// Bit mask of BYSW field.
	SPI0_SPDCR2_BYSW_Msk = 0x1
	// Bit BYSW.
	SPI0_SPDCR2_BYSW = 0x1
	// Byte Swap OFF
	SPI0_SPDCR2_BYSW_0 = 0x0
	// Byte Swap ON
	SPI0_SPDCR2_BYSW_1 = 0x1
	// Position of SINV field.
	SPI0_SPDCR2_SINV_Pos = 0x1
	// Bit mask of SINV field.
	SPI0_SPDCR2_SINV_Msk = 0x2
	// Bit SINV.
	SPI0_SPDCR2_SINV = 0x2
	// Not invert serial data
	SPI0_SPDCR2_SINV_0 = 0x0
	// Invert serial data
	SPI0_SPDCR2_SINV_1 = 0x1

	// SPCR3: SPI Control Register 3
	// Position of ETXMD field.
	SPI0_SPCR3_ETXMD_Pos = 0x0
	// Bit mask of ETXMD field.
	SPI0_SPCR3_ETXMD_Msk = 0x1
	// Bit ETXMD.
	SPI0_SPCR3_ETXMD = 0x1
	// Full-duplex synchronous or transmit-only serial communications. [the SPCR.TXMD bit is enabled]
	SPI0_SPCR3_ETXMD_0 = 0x0
	// Receive-only serial communications in slave mode (SPCR.MSTR bit = 0). [the SPCR.TXMD bit is disabled] Setting is prohibited in master mode (SPCR.MSTR bit = 1).
	SPI0_SPCR3_ETXMD_1 = 0x1
	// Position of BFDS field.
	SPI0_SPCR3_BFDS_Pos = 0x1
	// Bit mask of BFDS field.
	SPI0_SPCR3_BFDS_Msk = 0x2
	// Bit BFDS.
	SPI0_SPCR3_BFDS = 0x2
	// Delay (RSPCK delay, SSL negation delay and next-access delay) between frames is inserted in burst transfer.
	SPI0_SPCR3_BFDS_0 = 0x0
	// Delay between frames is not inserted in burst transfer.
	SPI0_SPCR3_BFDS_1 = 0x1
	// Position of CENDIE field.
	SPI0_SPCR3_CENDIE_Pos = 0x4
	// Bit mask of CENDIE field.
	SPI0_SPCR3_CENDIE_Msk = 0x10
	// Bit CENDIE.
	SPI0_SPCR3_CENDIE = 0x10
	// Communication end interrupt request is disabled.
	SPI0_SPCR3_CENDIE_0 = 0x0
	// Communication end interrupt request is enabled.
	SPI0_SPCR3_CENDIE_1 = 0x1
)

// Constants for I3C: I3C Bus Interface
const (
	// PRTS: Protocol Selection Register
	// Position of PRTMD field.
	I3C_PRTS_PRTMD_Pos = 0x0
	// Bit mask of PRTMD field.
	I3C_PRTS_PRTMD_Msk = 0x1
	// Bit PRTMD.
	I3C_PRTS_PRTMD = 0x1
	// I3C protocol mode
	I3C_PRTS_PRTMD_0 = 0x0
	// I2C protocol mode
	I3C_PRTS_PRTMD_1 = 0x1

	// CECTL: Clock Enable Control Resisters
	// Position of CLKE field.
	I3C_CECTL_CLKE_Pos = 0x0
	// Bit mask of CLKE field.
	I3C_CECTL_CLKE_Msk = 0x1
	// Bit CLKE.
	I3C_CECTL_CLKE = 0x1
	// Clock disable
	I3C_CECTL_CLKE_0 = 0x0
	// Clock enable
	I3C_CECTL_CLKE_1 = 0x1

	// BCTL: Bus Control Register
	// Position of INCBA field.
	I3C_BCTL_INCBA_Pos = 0x0
	// Bit mask of INCBA field.
	I3C_BCTL_INCBA_Msk = 0x1
	// Bit INCBA.
	I3C_BCTL_INCBA = 0x1
	// Do not include I3C broadcast address for private transfers
	I3C_BCTL_INCBA_0 = 0x0
	// Include I3C broadcast address for private transfers
	I3C_BCTL_INCBA_1 = 0x1
	// Position of ABT field.
	I3C_BCTL_ABT_Pos = 0x1d
	// Bit mask of ABT field.
	I3C_BCTL_ABT_Msk = 0x20000000
	// Bit ABT.
	I3C_BCTL_ABT = 0x20000000
	// I3C is running.
	I3C_BCTL_ABT_0 = 0x0
	// I3C has aborted a transfer.
	I3C_BCTL_ABT_1 = 0x1
	// Position of RSM field.
	I3C_BCTL_RSM_Pos = 0x1e
	// Bit mask of RSM field.
	I3C_BCTL_RSM_Msk = 0x40000000
	// Bit RSM.
	I3C_BCTL_RSM = 0x40000000
	// I3C is running.
	I3C_BCTL_RSM_0 = 0x0
	// I3C is suspended.
	I3C_BCTL_RSM_1 = 0x1
	// Position of BUSE field.
	I3C_BCTL_BUSE_Pos = 0x1f
	// Bit mask of BUSE field.
	I3C_BCTL_BUSE_Msk = 0x80000000
	// Bit BUSE.
	I3C_BCTL_BUSE = 0x80000000
	// I3C bus operation is disabled.
	I3C_BCTL_BUSE_0 = 0x0
	// I3C bus operation is enabled.
	I3C_BCTL_BUSE_1 = 0x1

	// MSDVAD: Master Device Address Register
	// Position of MDYAD field.
	I3C_MSDVAD_MDYAD_Pos = 0x10
	// Bit mask of MDYAD field.
	I3C_MSDVAD_MDYAD_Msk = 0x7f0000
	// Position of MDYADV field.
	I3C_MSDVAD_MDYADV_Pos = 0x1f
	// Bit mask of MDYADV field.
	I3C_MSDVAD_MDYADV_Msk = 0x80000000
	// Bit MDYADV.
	I3C_MSDVAD_MDYADV = 0x80000000
	// The master dynamic address field is not valid.
	I3C_MSDVAD_MDYADV_0 = 0x0
	// The master dynamic address field is valid.
	I3C_MSDVAD_MDYADV_1 = 0x1

	// RSTCTL: Reset Control Register
	// Position of RI3CRST field.
	I3C_RSTCTL_RI3CRST_Pos = 0x0
	// Bit mask of RI3CRST field.
	I3C_RSTCTL_RI3CRST_Msk = 0x1
	// Bit RI3CRST.
	I3C_RSTCTL_RI3CRST = 0x1
	// Release I3C reset.
	I3C_RSTCTL_RI3CRST_0 = 0x0
	// Initiate I3C reset.
	I3C_RSTCTL_RI3CRST_1 = 0x1
	// Position of CMDQRST field.
	I3C_RSTCTL_CMDQRST_Pos = 0x1
	// Bit mask of CMDQRST field.
	I3C_RSTCTL_CMDQRST_Msk = 0x2
	// Bit CMDQRST.
	I3C_RSTCTL_CMDQRST = 0x2
	// The Command Queues in I3C is not flushed.
	I3C_RSTCTL_CMDQRST_0 = 0x0
	// The Command Queues in I3C is flushed.
	I3C_RSTCTL_CMDQRST_1 = 0x1
	// Position of RSPQRST field.
	I3C_RSTCTL_RSPQRST_Pos = 0x2
	// Bit mask of RSPQRST field.
	I3C_RSTCTL_RSPQRST_Msk = 0x4
	// Bit RSPQRST.
	I3C_RSTCTL_RSPQRST = 0x4
	// The Response Queues in I3C is not flushed.
	I3C_RSTCTL_RSPQRST_0 = 0x0
	// The Response Queues in I3C is flushed.
	I3C_RSTCTL_RSPQRST_1 = 0x1
	// Position of TDBRST field.
	I3C_RSTCTL_TDBRST_Pos = 0x3
	// Bit mask of TDBRST field.
	I3C_RSTCTL_TDBRST_Msk = 0x8
	// Bit TDBRST.
	I3C_RSTCTL_TDBRST = 0x8
	// The Transmit Queues in I3C is not flushed.
	I3C_RSTCTL_TDBRST_0 = 0x0
	// The Transmit Queues in I3C is flushed.
	I3C_RSTCTL_TDBRST_1 = 0x1
	// Position of RDBRST field.
	I3C_RSTCTL_RDBRST_Pos = 0x4
	// Bit mask of RDBRST field.
	I3C_RSTCTL_RDBRST_Msk = 0x10
	// Bit RDBRST.
	I3C_RSTCTL_RDBRST = 0x10
	// The Receive Queues in I3C is not flushed.
	I3C_RSTCTL_RDBRST_0 = 0x0
	// The Receive Queues in I3C is flushed.
	I3C_RSTCTL_RDBRST_1 = 0x1
	// Position of IBIQRST field.
	I3C_RSTCTL_IBIQRST_Pos = 0x5
	// Bit mask of IBIQRST field.
	I3C_RSTCTL_IBIQRST_Msk = 0x20
	// Bit IBIQRST.
	I3C_RSTCTL_IBIQRST = 0x20
	// The IBI Queues in I3C is not flushed.
	I3C_RSTCTL_IBIQRST_0 = 0x0
	// The IBI Queues in I3C is flushed.
	I3C_RSTCTL_IBIQRST_1 = 0x1
	// Position of RSQRST field.
	I3C_RSTCTL_RSQRST_Pos = 0x6
	// Bit mask of RSQRST field.
	I3C_RSTCTL_RSQRST_Msk = 0x40
	// Bit RSQRST.
	I3C_RSTCTL_RSQRST = 0x40
	// The Receive Status Queue in I3C is not flushed.
	I3C_RSTCTL_RSQRST_0 = 0x0
	// The Receive Status Queue in I3C is flushed.
	I3C_RSTCTL_RSQRST_1 = 0x1
	// Position of HCMDQRST field.
	I3C_RSTCTL_HCMDQRST_Pos = 0x9
	// Bit mask of HCMDQRST field.
	I3C_RSTCTL_HCMDQRST_Msk = 0x200
	// Bit HCMDQRST.
	I3C_RSTCTL_HCMDQRST = 0x200
	// The High Priority Command Queues in I3C is not flushed.
	I3C_RSTCTL_HCMDQRST_0 = 0x0
	// The High Priority Command Queues in I3C is flushed.
	I3C_RSTCTL_HCMDQRST_1 = 0x1
	// Position of HRSPQRST field.
	I3C_RSTCTL_HRSPQRST_Pos = 0xa
	// Bit mask of HRSPQRST field.
	I3C_RSTCTL_HRSPQRST_Msk = 0x400
	// Bit HRSPQRST.
	I3C_RSTCTL_HRSPQRST = 0x400
	// The High Priority Response Queues in I3C is not flushed.
	I3C_RSTCTL_HRSPQRST_0 = 0x0
	// The High Priority Response Queues in I3C is flushed.
	I3C_RSTCTL_HRSPQRST_1 = 0x1
	// Position of HTDBRST field.
	I3C_RSTCTL_HTDBRST_Pos = 0xb
	// Bit mask of HTDBRST field.
	I3C_RSTCTL_HTDBRST_Msk = 0x800
	// Bit HTDBRST.
	I3C_RSTCTL_HTDBRST = 0x800
	// The High Priority Transmit Queues in I3C is not flushed.
	I3C_RSTCTL_HTDBRST_0 = 0x0
	// The High Priority Transmit Queues in I3C is flushed.
	I3C_RSTCTL_HTDBRST_1 = 0x1
	// Position of HRDBRST field.
	I3C_RSTCTL_HRDBRST_Pos = 0xc
	// Bit mask of HRDBRST field.
	I3C_RSTCTL_HRDBRST_Msk = 0x1000
	// Bit HRDBRST.
	I3C_RSTCTL_HRDBRST = 0x1000
	// The High Priority Receive Queues in I3C is not flushed.
	I3C_RSTCTL_HRDBRST_0 = 0x0
	// The High Priority Receive Queues in I3C is flushed.
	I3C_RSTCTL_HRDBRST_1 = 0x1
	// Position of INTLRST field.
	I3C_RSTCTL_INTLRST_Pos = 0x10
	// Bit mask of INTLRST field.
	I3C_RSTCTL_INTLRST_Msk = 0x10000
	// Bit INTLRST.
	I3C_RSTCTL_INTLRST = 0x10000
	// Releases of some registers and internal state.
	I3C_RSTCTL_INTLRST_0 = 0x0
	// Resets of some registers and internal state.
	I3C_RSTCTL_INTLRST_1 = 0x1

	// PRSST: Present State Register
	// Position of CRMS field.
	I3C_PRSST_CRMS_Pos = 0x2
	// Bit mask of CRMS field.
	I3C_PRSST_CRMS_Msk = 0x4
	// Bit CRMS.
	I3C_PRSST_CRMS = 0x4
	// The Master is not the Current Master, and must request and acquire bus ownership before initiating any transfer.
	I3C_PRSST_CRMS_0 = 0x0
	// The Master is the Current Master, and as a result can initiate transfers.
	I3C_PRSST_CRMS_1 = 0x1
	// Position of TRMD field.
	I3C_PRSST_TRMD_Pos = 0x4
	// Bit mask of TRMD field.
	I3C_PRSST_TRMD_Msk = 0x10
	// Bit TRMD.
	I3C_PRSST_TRMD = 0x10
	// Receive mode
	I3C_PRSST_TRMD_0 = 0x0
	// Transmit mode
	I3C_PRSST_TRMD_1 = 0x1
	// Position of PRSSTWP field.
	I3C_PRSST_PRSSTWP_Pos = 0x7
	// Bit mask of PRSSTWP field.
	I3C_PRSST_PRSSTWP_Msk = 0x80
	// Bit PRSSTWP.
	I3C_PRSST_PRSSTWP = 0x80
	// CRMS bit is protected.
	I3C_PRSST_PRSSTWP_0 = 0x0
	// CRMS bit can be written when writing simultaneously with the value of the target bit.
	I3C_PRSST_PRSSTWP_1 = 0x1

	// INST: Internal Status Register
	// Position of INEF field.
	I3C_INST_INEF_Pos = 0xa
	// Bit mask of INEF field.
	I3C_INST_INEF_Msk = 0x400
	// Bit INEF.
	I3C_INST_INEF = 0x400
	// I3C Internal Error has not detected.
	I3C_INST_INEF_0 = 0x0
	// I3C Internal Error has detected.
	I3C_INST_INEF_1 = 0x1

	// INSTE: Internal Status Enable Register
	// Position of INEE field.
	I3C_INSTE_INEE_Pos = 0xa
	// Bit mask of INEE field.
	I3C_INSTE_INEE_Msk = 0x400
	// Bit INEE.
	I3C_INSTE_INEE = 0x400
	// Disable INST.INEF
	I3C_INSTE_INEE_0 = 0x0
	// Enable INST.INEF
	I3C_INSTE_INEE_1 = 0x1

	// INIE: Internal Interrupt Enable Register
	// Position of INEIE field.
	I3C_INIE_INEIE_Pos = 0xa
	// Bit mask of INEIE field.
	I3C_INIE_INEIE_Msk = 0x400
	// Bit INEIE.
	I3C_INIE_INEIE = 0x400
	// Disables Non-recoverable Internal Error Interrupt Signal.
	I3C_INIE_INEIE_0 = 0x0
	// Enables Non-recoverable Internal Error Interrupt Signal.
	I3C_INIE_INEIE_1 = 0x1

	// INSTFC: Internal Status Force Register
	// Position of INEFC field.
	I3C_INSTFC_INEFC_Pos = 0xa
	// Bit mask of INEFC field.
	I3C_INSTFC_INEFC_Msk = 0x400
	// Bit INEFC.
	I3C_INSTFC_INEFC = 0x400
	// Not force a specific interrupt
	I3C_INSTFC_INEFC_0 = 0x0
	// Force a specific interrupt
	I3C_INSTFC_INEFC_1 = 0x1

	// DVCT: Device Characteristic Table Register
	// Position of IDX field.
	I3C_DVCT_IDX_Pos = 0x13
	// Bit mask of IDX field.
	I3C_DVCT_IDX_Msk = 0xf80000

	// IBINCTL: IBI Notify Control Register
	// Position of NRMRCTL field.
	I3C_IBINCTL_NRMRCTL_Pos = 0x1
	// Bit mask of NRMRCTL field.
	I3C_IBINCTL_NRMRCTL_Msk = 0x2
	// Bit NRMRCTL.
	I3C_IBINCTL_NRMRCTL = 0x2
	// Do not pass rejected IBI Status to IBI Queue/Ring, if the incoming Master Request is NACKed and is auto-disabled based on DVMRRJ field in relevant DAT entry.
	I3C_IBINCTL_NRMRCTL_0 = 0x0
	// Pass rejected IBI Status to the IBI Queue, if the incoming Master Request is NACKed and is autodisabled based on DVMRRJ field in relevant DAT entry.
	I3C_IBINCTL_NRMRCTL_1 = 0x1
	// Position of NRSIRCTL field.
	I3C_IBINCTL_NRSIRCTL_Pos = 0x3
	// Bit mask of NRSIRCTL field.
	I3C_IBINCTL_NRSIRCTL_Msk = 0x8
	// Bit NRSIRCTL.
	I3C_IBINCTL_NRSIRCTL = 0x8
	// Do not pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry.
	I3C_IBINCTL_NRSIRCTL_0 = 0x0
	// Pass rejected IBI Status to the IBI Queue/Rings, if the incoming SIR is NACKed and is auto-disabled based on DVSIRRJ field in relevant DAT entry.
	I3C_IBINCTL_NRSIRCTL_1 = 0x1

	// BFCTL: Bus Function Control Register
	// Position of MALE field.
	I3C_BFCTL_MALE_Pos = 0x0
	// Bit mask of MALE field.
	I3C_BFCTL_MALE_Msk = 0x1
	// Bit MALE.
	I3C_BFCTL_MALE = 0x1
	// Master arbitration-lost detection disables. Disables the arbitration-lost detection function and does not clear the CRMS and TRMD bits in PRSST automatically when arbitration is lost.
	I3C_BFCTL_MALE_0 = 0x0
	// Master arbitration-lost detection enables. Enables the arbitration-lost detection function and clears the CRMS and TRMD bits in PRSST automatically when arbitration is lost.
	I3C_BFCTL_MALE_1 = 0x1
	// Position of NALE field.
	I3C_BFCTL_NALE_Pos = 0x1
	// Bit mask of NALE field.
	I3C_BFCTL_NALE_Msk = 0x2
	// Bit NALE.
	I3C_BFCTL_NALE = 0x2
	// NACK transmission arbitration-lost detection disables.
	I3C_BFCTL_NALE_0 = 0x0
	// NACK transmission arbitration-lost detection enables.
	I3C_BFCTL_NALE_1 = 0x1
	// Position of SALE field.
	I3C_BFCTL_SALE_Pos = 0x2
	// Bit mask of SALE field.
	I3C_BFCTL_SALE_Msk = 0x4
	// Bit SALE.
	I3C_BFCTL_SALE = 0x4
	// Slave arbitration-lost detection disables.
	I3C_BFCTL_SALE_0 = 0x0
	// Slave arbitration-lost detection enables.
	I3C_BFCTL_SALE_1 = 0x1
	// Position of SCSYNE field.
	I3C_BFCTL_SCSYNE_Pos = 0x8
	// Bit mask of SCSYNE field.
	I3C_BFCTL_SCSYNE_Msk = 0x100
	// Bit SCSYNE.
	I3C_BFCTL_SCSYNE = 0x100
	// No SCL synchronous circuit uses.
	I3C_BFCTL_SCSYNE_0 = 0x0
	// An SCL synchronous circuit uses.
	I3C_BFCTL_SCSYNE_1 = 0x1
	// Position of SMBS field.
	I3C_BFCTL_SMBS_Pos = 0xc
	// Bit mask of SMBS field.
	I3C_BFCTL_SMBS_Msk = 0x1000
	// Bit SMBS.
	I3C_BFCTL_SMBS = 0x1000
	// The I2C bus select.
	I3C_BFCTL_SMBS_0 = 0x0
	// The SMBus select.
	I3C_BFCTL_SMBS_1 = 0x1
	// Position of FMPE field.
	I3C_BFCTL_FMPE_Pos = 0xe
	// Bit mask of FMPE field.
	I3C_BFCTL_FMPE_Msk = 0x4000
	// Bit FMPE.
	I3C_BFCTL_FMPE = 0x4000
	// No Fm+ slope control circuit uses for the I3C_SCL pin and I3C_SDA pin. (n = 0)
	I3C_BFCTL_FMPE_0 = 0x0
	// An Fm+ slope control circuit uses for the I3C_SCL pin and I3C_SDA pin. (n = 0)
	I3C_BFCTL_FMPE_1 = 0x1
	// Position of HSME field.
	I3C_BFCTL_HSME_Pos = 0xf
	// Bit mask of HSME field.
	I3C_BFCTL_HSME_Msk = 0x8000
	// Bit HSME.
	I3C_BFCTL_HSME = 0x8000
	// Disable High Speed Mode.
	I3C_BFCTL_HSME_0 = 0x0
	// Enable High Speed Mode.
	I3C_BFCTL_HSME_1 = 0x1

	// SVCTL: Slave Control Register
	// Position of GCAE field.
	I3C_SVCTL_GCAE_Pos = 0x0
	// Bit mask of GCAE field.
	I3C_SVCTL_GCAE_Msk = 0x1
	// Bit GCAE.
	I3C_SVCTL_GCAE = 0x1
	// General call address detection disables.
	I3C_SVCTL_GCAE_0 = 0x0
	// General call address detection enables.
	I3C_SVCTL_GCAE_1 = 0x1
	// Position of HSMCE field.
	I3C_SVCTL_HSMCE_Pos = 0x5
	// Bit mask of HSMCE field.
	I3C_SVCTL_HSMCE_Msk = 0x20
	// Bit HSMCE.
	I3C_SVCTL_HSMCE = 0x20
	// Hs-mode Master Code Detection disables.
	I3C_SVCTL_HSMCE_0 = 0x0
	// Hs-mode Master Code Detection enables.
	I3C_SVCTL_HSMCE_1 = 0x1
	// Position of DVIDE field.
	I3C_SVCTL_DVIDE_Pos = 0x6
	// Bit mask of DVIDE field.
	I3C_SVCTL_DVIDE_Msk = 0x40
	// Bit DVIDE.
	I3C_SVCTL_DVIDE = 0x40
	// Device-ID address detection disables.
	I3C_SVCTL_DVIDE_0 = 0x0
	// Device-ID address detection enables.
	I3C_SVCTL_DVIDE_1 = 0x1
	// Position of HOAE field.
	I3C_SVCTL_HOAE_Pos = 0xf
	// Bit mask of HOAE field.
	I3C_SVCTL_HOAE_Msk = 0x8000
	// Bit HOAE.
	I3C_SVCTL_HOAE = 0x8000
	// Host address detection disables.
	I3C_SVCTL_HOAE_0 = 0x0
	// Host address detection enables.
	I3C_SVCTL_HOAE_1 = 0x1
	// Position of SVAE field.
	I3C_SVCTL_SVAE_Pos = 0x10
	// Bit mask of SVAE field.
	I3C_SVCTL_SVAE_Msk = 0x70000
	// Slave n disables
	I3C_SVCTL_SVAE_0 = 0x0
	// Slave n enables
	I3C_SVCTL_SVAE_1 = 0x1

	// REFCKCTL: Reference Clock Control Register
	// Position of IREFCKS field.
	I3C_REFCKCTL_IREFCKS_Pos = 0x0
	// Bit mask of IREFCKS field.
	I3C_REFCKCTL_IREFCKS_Msk = 0x7
	// TCLK/1 clock
	I3C_REFCKCTL_IREFCKS_000 = 0x0
	// TCLK/2 clock
	I3C_REFCKCTL_IREFCKS_001 = 0x1
	// TCLK/4 clock
	I3C_REFCKCTL_IREFCKS_010 = 0x2
	// TCLK/8 clock
	I3C_REFCKCTL_IREFCKS_011 = 0x3
	// TCLK/16 clock
	I3C_REFCKCTL_IREFCKS_100 = 0x4
	// TCLK/32 clock
	I3C_REFCKCTL_IREFCKS_101 = 0x5
	// TCLK/64 clock
	I3C_REFCKCTL_IREFCKS_110 = 0x6
	// TCLK/128 clock
	I3C_REFCKCTL_IREFCKS_111 = 0x7

	// STDBR: Standard Bit Rate Register
	// Position of SBRLO field.
	I3C_STDBR_SBRLO_Pos = 0x0
	// Bit mask of SBRLO field.
	I3C_STDBR_SBRLO_Msk = 0xff
	// Position of SBRHO field.
	I3C_STDBR_SBRHO_Pos = 0x8
	// Bit mask of SBRHO field.
	I3C_STDBR_SBRHO_Msk = 0xff00
	// Position of SBRLP field.
	I3C_STDBR_SBRLP_Pos = 0x10
	// Bit mask of SBRLP field.
	I3C_STDBR_SBRLP_Msk = 0x3f0000
	// Position of SBRHP field.
	I3C_STDBR_SBRHP_Pos = 0x18
	// Bit mask of SBRHP field.
	I3C_STDBR_SBRHP_Msk = 0x3f000000
	// Position of DSBRPO field.
	I3C_STDBR_DSBRPO_Pos = 0x1f
	// Bit mask of DSBRPO field.
	I3C_STDBR_DSBRPO_Msk = 0x80000000
	// Bit DSBRPO.
	I3C_STDBR_DSBRPO = 0x80000000
	// The time period set for SBRHO[7:0] and SBRLO[7:0] is not doubled.
	I3C_STDBR_DSBRPO_0 = 0x0
	// The time period set for SBRHO[7:0] and SBRLO[7:0] is doubled.
	I3C_STDBR_DSBRPO_1 = 0x1

	// EXTBR: Extended Bit Rate Register
	// Position of EBRLO field.
	I3C_EXTBR_EBRLO_Pos = 0x0
	// Bit mask of EBRLO field.
	I3C_EXTBR_EBRLO_Msk = 0xff
	// Position of EBRHO field.
	I3C_EXTBR_EBRHO_Pos = 0x8
	// Bit mask of EBRHO field.
	I3C_EXTBR_EBRHO_Msk = 0xff00
	// Position of EBRLP field.
	I3C_EXTBR_EBRLP_Pos = 0x10
	// Bit mask of EBRLP field.
	I3C_EXTBR_EBRLP_Msk = 0x3f0000
	// Position of EBRHP field.
	I3C_EXTBR_EBRHP_Pos = 0x18
	// Bit mask of EBRHP field.
	I3C_EXTBR_EBRHP_Msk = 0x3f000000

	// BFRECDT: Bus Free Condition Detection Time Register
	// Position of FRECYC field.
	I3C_BFRECDT_FRECYC_Pos = 0x0
	// Bit mask of FRECYC field.
	I3C_BFRECDT_FRECYC_Msk = 0x1ff

	// BAVLCDT: Bus Available Condition Detection Time Register
	// Position of AVLCYC field.
	I3C_BAVLCDT_AVLCYC_Pos = 0x0
	// Bit mask of AVLCYC field.
	I3C_BAVLCDT_AVLCYC_Msk = 0x1ff

	// BIDLCDT: Bus Idle Condition Detection Time Register
	// Position of IDLCYC field.
	I3C_BIDLCDT_IDLCYC_Pos = 0x0
	// Bit mask of IDLCYC field.
	I3C_BIDLCDT_IDLCYC_Msk = 0x3ffff

	// OUTCTL: Output Control Register
	// Position of SDOC field.
	I3C_OUTCTL_SDOC_Pos = 0x0
	// Bit mask of SDOC field.
	I3C_OUTCTL_SDOC_Msk = 0x1
	// Bit SDOC.
	I3C_OUTCTL_SDOC = 0x1
	// I3C drives the I3C_SDA pin low.
	I3C_OUTCTL_SDOC_0 = 0x0
	// I3C releases the I3C_SDA pin.
	I3C_OUTCTL_SDOC_1 = 0x1
	// Position of SCOC field.
	I3C_OUTCTL_SCOC_Pos = 0x1
	// Bit mask of SCOC field.
	I3C_OUTCTL_SCOC_Msk = 0x2
	// Bit SCOC.
	I3C_OUTCTL_SCOC = 0x2
	// I3C drives the I3C_SCL pin low.
	I3C_OUTCTL_SCOC_0 = 0x0
	// I3C releases the I3C_SCL pin.
	I3C_OUTCTL_SCOC_1 = 0x1
	// Position of SOCWP field.
	I3C_OUTCTL_SOCWP_Pos = 0x2
	// Bit mask of SOCWP field.
	I3C_OUTCTL_SOCWP_Msk = 0x4
	// Bit SOCWP.
	I3C_OUTCTL_SOCWP = 0x4
	// Bits SCOC and SDOC are protected.
	I3C_OUTCTL_SOCWP_0 = 0x0
	// Bits SCOC and SDOC can be written (When writing simultaneously with the value of the target bit). This bit is read as 0.
	I3C_OUTCTL_SOCWP_1 = 0x1
	// Position of EXCYC field.
	I3C_OUTCTL_EXCYC_Pos = 0x4
	// Bit mask of EXCYC field.
	I3C_OUTCTL_EXCYC_Msk = 0x10
	// Bit EXCYC.
	I3C_OUTCTL_EXCYC = 0x10
	// Does not output an extra SCL clock cycle (default).
	I3C_OUTCTL_EXCYC_0 = 0x0
	// Outputs an extra SCL clock cycle.
	I3C_OUTCTL_EXCYC_1 = 0x1
	// Position of SDOD field.
	I3C_OUTCTL_SDOD_Pos = 0x8
	// Bit mask of SDOD field.
	I3C_OUTCTL_SDOD_Msk = 0x700
	// No output delay
	I3C_OUTCTL_SDOD_000 = 0x0
	// 1 I3Cφ cycle (When OUTCTL.SDODCS = 0 (I3Cφ)) 1 or 2 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
	I3C_OUTCTL_SDOD_001 = 0x1
	// 2 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 3 or 4 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
	I3C_OUTCTL_SDOD_010 = 0x2
	// 3 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 5 or 6 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
	I3C_OUTCTL_SDOD_011 = 0x3
	// 4 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 7 or 8 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
	I3C_OUTCTL_SDOD_100 = 0x4
	// 5 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 9 or 10 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
	I3C_OUTCTL_SDOD_101 = 0x5
	// 6 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 11 or 12 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
	I3C_OUTCTL_SDOD_110 = 0x6
	// 7 I3Cφ cycles (When OUTCTL.SDODCS = 0 (I3Cφ)) 13 or 14 I3Cφ cycles (When OUTCTL.SDODCS = 1 (I3Cφ/2))
	I3C_OUTCTL_SDOD_111 = 0x7
	// Position of SDODCS field.
	I3C_OUTCTL_SDODCS_Pos = 0xf
	// Bit mask of SDODCS field.
	I3C_OUTCTL_SDODCS_Msk = 0x8000
	// Bit SDODCS.
	I3C_OUTCTL_SDODCS = 0x8000
	// The internal reference clock (I3Cφ) is selected as the clock source of the SDA output delay counter.
	I3C_OUTCTL_SDODCS_0 = 0x0
	// The internal reference clock divided by 2 (I3Cφ/2) is selected as the clock source of the SDA output delay counter.
	I3C_OUTCTL_SDODCS_1 = 0x1

	// INCTL: Input Control Register
	// Position of DNFS field.
	I3C_INCTL_DNFS_Pos = 0x0
	// Bit mask of DNFS field.
	I3C_INCTL_DNFS_Msk = 0xf
	// Position of DNFE field.
	I3C_INCTL_DNFE_Pos = 0x4
	// Bit mask of DNFE field.
	I3C_INCTL_DNFE_Msk = 0x10
	// Bit DNFE.
	I3C_INCTL_DNFE = 0x10
	// No digital noise filter circuit is used.
	I3C_INCTL_DNFE_0 = 0x0
	// A digital noise filter circuit is used.
	I3C_INCTL_DNFE_1 = 0x1

	// TMOCTL: Timeout Control Register
	// Position of TODTS field.
	I3C_TMOCTL_TODTS_Pos = 0x0
	// Bit mask of TODTS field.
	I3C_TMOCTL_TODTS_Msk = 0x3
	// 16bit-timeout
	I3C_TMOCTL_TODTS_00 = 0x0
	// 14bit-timeout
	I3C_TMOCTL_TODTS_01 = 0x1
	// 8bit-timeout
	I3C_TMOCTL_TODTS_10 = 0x2
	// 6bit-timeout
	I3C_TMOCTL_TODTS_11 = 0x3
	// Position of TOLCTL field.
	I3C_TMOCTL_TOLCTL_Pos = 0x4
	// Bit mask of TOLCTL field.
	I3C_TMOCTL_TOLCTL_Msk = 0x10
	// Bit TOLCTL.
	I3C_TMOCTL_TOLCTL = 0x10
	// Count is disabled while the I3C_SCL line is at a low level.
	I3C_TMOCTL_TOLCTL_0 = 0x0
	// Count is enabled while the I3C_SCL line is at a low level.
	I3C_TMOCTL_TOLCTL_1 = 0x1
	// Position of TOHCTL field.
	I3C_TMOCTL_TOHCTL_Pos = 0x5
	// Bit mask of TOHCTL field.
	I3C_TMOCTL_TOHCTL_Msk = 0x20
	// Bit TOHCTL.
	I3C_TMOCTL_TOHCTL = 0x20
	// Count is disabled while the I3C_SCL line is at a high level.
	I3C_TMOCTL_TOHCTL_0 = 0x0
	// Count is enabled while the I3C_SCL line is at a high level.
	I3C_TMOCTL_TOHCTL_1 = 0x1
	// Position of TOMDS field.
	I3C_TMOCTL_TOMDS_Pos = 0x6
	// Bit mask of TOMDS field.
	I3C_TMOCTL_TOMDS_Msk = 0xc0
	// Timeout is detected during the following conditions: The bus is busy (BCST.BFREF = 0) in master mode.I3C’s own slave address is detected and the bus is busy in slave mode.The bus is free (BCST.BFREF = 1) while generation of a START condition is requested (CNDCTL.STCND = 1).
	I3C_TMOCTL_TOMDS_00 = 0x0
	// Timeout is detected while the bus is busy.
	I3C_TMOCTL_TOMDS_01 = 0x1
	// Timeout is detected while the bus is free.
	I3C_TMOCTL_TOMDS_10 = 0x2
	// Setting prohibited
	I3C_TMOCTL_TOMDS_11 = 0x3

	// WUCTL: Wake Up Unit Control Register
	// Position of WUACKS field.
	I3C_WUCTL_WUACKS_Pos = 0x0
	// Bit mask of WUACKS field.
	I3C_WUCTL_WUACKS_Msk = 0x1
	// Bit WUACKS.
	I3C_WUCTL_WUACKS = 0x1
	// Position of WUANFS field.
	I3C_WUCTL_WUANFS_Pos = 0x4
	// Bit mask of WUANFS field.
	I3C_WUCTL_WUANFS_Msk = 0x10
	// Bit WUANFS.
	I3C_WUCTL_WUANFS = 0x10
	// Do not add the Wake Up analog filter.
	I3C_WUCTL_WUANFS_0 = 0x0
	// Add the Wake Up analog filter.
	I3C_WUCTL_WUANFS_1 = 0x1
	// Position of WUFSYNE field.
	I3C_WUCTL_WUFSYNE_Pos = 0x6
	// Bit mask of WUFSYNE field.
	I3C_WUCTL_WUFSYNE_Msk = 0x40
	// Bit WUFSYNE.
	I3C_WUCTL_WUFSYNE = 0x40
	// I3C asynchronous circuit enable
	I3C_WUCTL_WUFSYNE_0 = 0x0
	// I3C synchronous circuit enable
	I3C_WUCTL_WUFSYNE_1 = 0x1
	// Position of WUFE field.
	I3C_WUCTL_WUFE_Pos = 0x7
	// Bit mask of WUFE field.
	I3C_WUCTL_WUFE_Msk = 0x80
	// Bit WUFE.
	I3C_WUCTL_WUFE = 0x80
	// Wake-up function disables
	I3C_WUCTL_WUFE_0 = 0x0
	// Wake-up function enables
	I3C_WUCTL_WUFE_1 = 0x1

	// ACKCTL: Acknowledge Control Register
	// Position of ACKR field.
	I3C_ACKCTL_ACKR_Pos = 0x0
	// Bit mask of ACKR field.
	I3C_ACKCTL_ACKR_Msk = 0x1
	// Bit ACKR.
	I3C_ACKCTL_ACKR = 0x1
	// A 0 is received as the acknowledge bit (ACK reception).
	I3C_ACKCTL_ACKR_0 = 0x0
	// A 1 is received as the acknowledge bit (NACK reception).
	I3C_ACKCTL_ACKR_1 = 0x1
	// Position of ACKT field.
	I3C_ACKCTL_ACKT_Pos = 0x1
	// Bit mask of ACKT field.
	I3C_ACKCTL_ACKT_Msk = 0x2
	// Bit ACKT.
	I3C_ACKCTL_ACKT = 0x2
	// A 0 is sent as the acknowledge bit (ACK transmission).
	I3C_ACKCTL_ACKT_0 = 0x0
	// A 1 is sent as the acknowledge bit (NACK transmission).
	I3C_ACKCTL_ACKT_1 = 0x1
	// Position of ACKTWP field.
	I3C_ACKCTL_ACKTWP_Pos = 0x2
	// Bit mask of ACKTWP field.
	I3C_ACKCTL_ACKTWP_Msk = 0x4
	// Bit ACKTWP.
	I3C_ACKCTL_ACKTWP = 0x4
	// The ACKT bit are protected.
	I3C_ACKCTL_ACKTWP_0 = 0x0
	// The ACKT bit can be written (when writing simultaneously with the value of the target bit). This bit is read as 0.
	I3C_ACKCTL_ACKTWP_1 = 0x1

	// SCSTRCTL: SCL Stretch Control Register
	// Position of ACKTWE field.
	I3C_SCSTRCTL_ACKTWE_Pos = 0x0
	// Bit mask of ACKTWE field.
	I3C_SCSTRCTL_ACKTWE_Msk = 0x1
	// Bit ACKTWE.
	I3C_SCSTRCTL_ACKTWE = 0x1
	// NTST.RDBFF0 is set at the rising edge of the ninth SCL clock cycle. (The I3C_SCL line is not held low at the falling edge of the eighth clock cycle.)
	I3C_SCSTRCTL_ACKTWE_0 = 0x0
	// NTST.RDBFF0 is set at the rising edge of the eighth SCL clock cycle. (The I3C_SCL line is held low at the falling edge of the eighth clock cycle.) Low-hold is released by writing a value to the ACKCTL.ACKT bit.
	I3C_SCSTRCTL_ACKTWE_1 = 0x1
	// Position of RWE field.
	I3C_SCSTRCTL_RWE_Pos = 0x1
	// Bit mask of RWE field.
	I3C_SCSTRCTL_RWE_Msk = 0x2
	// Bit RWE.
	I3C_SCSTRCTL_RWE = 0x2
	// No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)
	I3C_SCSTRCTL_RWE_0 = 0x0
	// WAIT (The period between ninth clock cycle and first clock cycle is held low.) Low-hold is released by reading NTDTBP0.
	I3C_SCSTRCTL_RWE_1 = 0x1

	// SCSTLCTL: SCL Stalling Control Register
	// Position of STLCYC field.
	I3C_SCSTLCTL_STLCYC_Pos = 0x0
	// Bit mask of STLCYC field.
	I3C_SCSTLCTL_STLCYC_Msk = 0xffff
	// Position of AAPE field.
	I3C_SCSTLCTL_AAPE_Pos = 0x1c
	// Bit mask of AAPE field.
	I3C_SCSTLCTL_AAPE_Msk = 0x10000000
	// Bit AAPE.
	I3C_SCSTLCTL_AAPE = 0x10000000
	// Does not stall the SCL clock during the address assignment phase.
	I3C_SCSTLCTL_AAPE_0 = 0x0
	// Stall the SCL clock during address assignment phase.
	I3C_SCSTLCTL_AAPE_1 = 0x1
	// Position of PARPE field.
	I3C_SCSTLCTL_PARPE_Pos = 0x1e
	// Bit mask of PARPE field.
	I3C_SCSTLCTL_PARPE_Msk = 0x40000000
	// Bit PARPE.
	I3C_SCSTLCTL_PARPE = 0x40000000
	// Does not stall the SCL clock during the parity bit period.
	I3C_SCSTLCTL_PARPE_0 = 0x0
	// Stall the SCL clock during the parity bit period.
	I3C_SCSTLCTL_PARPE_1 = 0x1
	// Position of ACKPE field.
	I3C_SCSTLCTL_ACKPE_Pos = 0x1f
	// Bit mask of ACKPE field.
	I3C_SCSTLCTL_ACKPE_Msk = 0x80000000
	// Bit ACKPE.
	I3C_SCSTLCTL_ACKPE = 0x80000000
	// Does not stall the SCL clock during the ACK/NACK phase.
	I3C_SCSTLCTL_ACKPE_0 = 0x0
	// Stall the SCL clock during the ACK/NACK phase.
	I3C_SCSTLCTL_ACKPE_1 = 0x1

	// SVTDLG0: Slave Transfer Data Length Register 0
	// Position of STDLG field.
	I3C_SVTDLG0_STDLG_Pos = 0x10
	// Bit mask of STDLG field.
	I3C_SVTDLG0_STDLG_Msk = 0xffff0000

	// STCTL: Synchronous Timing Control Register
	// Position of STOE field.
	I3C_STCTL_STOE_Pos = 0x0
	// Bit mask of STOE field.
	I3C_STCTL_STOE_Msk = 0x1
	// Bit STOE.
	I3C_STCTL_STOE = 0x1
	// Disable
	I3C_STCTL_STOE_0 = 0x0
	// Enable
	I3C_STCTL_STOE_1 = 0x1

	// ATCTL: Asynchronous Timing Control Register
	// Position of ATTRGS field.
	I3C_ATCTL_ATTRGS_Pos = 0x0
	// Bit mask of ATTRGS field.
	I3C_ATCTL_ATTRGS_Msk = 0x1
	// Bit ATTRGS.
	I3C_ATCTL_ATTRGS = 0x1
	// Software trigger
	I3C_ATCTL_ATTRGS_0 = 0x0
	// Hardware trigger
	I3C_ATCTL_ATTRGS_1 = 0x1
	// Position of MREFOE field.
	I3C_ATCTL_MREFOE_Pos = 0x1
	// Bit mask of MREFOE field.
	I3C_ATCTL_MREFOE_Msk = 0x2
	// Bit MREFOE.
	I3C_ATCTL_MREFOE = 0x2
	// Disable
	I3C_ATCTL_MREFOE_0 = 0x0
	// Enable
	I3C_ATCTL_MREFOE_1 = 0x1
	// Position of AMEOE field.
	I3C_ATCTL_AMEOE_Pos = 0x2
	// Bit mask of AMEOE field.
	I3C_ATCTL_AMEOE_Msk = 0x4
	// Bit AMEOE.
	I3C_ATCTL_AMEOE = 0x4
	// Disable
	I3C_ATCTL_AMEOE_0 = 0x0
	// Enable
	I3C_ATCTL_AMEOE_1 = 0x1
	// Position of CDIV field.
	I3C_ATCTL_CDIV_Pos = 0x8
	// Bit mask of CDIV field.
	I3C_ATCTL_CDIV_Msk = 0xff00

	// ATTRG: Asynchronous Timing Trigger Register
	// Position of ATSTRG field.
	I3C_ATTRG_ATSTRG_Pos = 0x0
	// Bit mask of ATSTRG field.
	I3C_ATTRG_ATSTRG_Msk = 0x1
	// Bit ATSTRG.
	I3C_ATTRG_ATSTRG = 0x1
	// Do nothing
	I3C_ATTRG_ATSTRG_0 = 0x0
	// Software trigger (one-shot pulse) output This bit is always read as 0.
	I3C_ATTRG_ATSTRG_1 = 0x1

	// ATCCNTE: Asynchronous Timing Contorol Counter enable Register
	// Position of ATCE field.
	I3C_ATCCNTE_ATCE_Pos = 0x0
	// Bit mask of ATCE field.
	I3C_ATCCNTE_ATCE_Msk = 0x1
	// Bit ATCE.
	I3C_ATCCNTE_ATCE = 0x1
	// Disable
	I3C_ATCCNTE_ATCE_0 = 0x0
	// Enable
	I3C_ATCCNTE_ATCE_1 = 0x1

	// CNDCTL: Condition Control Register
	// Position of STCND field.
	I3C_CNDCTL_STCND_Pos = 0x0
	// Bit mask of STCND field.
	I3C_CNDCTL_STCND_Msk = 0x1
	// Bit STCND.
	I3C_CNDCTL_STCND = 0x1
	// Does not request to issue a START condition.
	I3C_CNDCTL_STCND_0 = 0x0
	// Requests to issue a START condition.
	I3C_CNDCTL_STCND_1 = 0x1
	// Position of SRCND field.
	I3C_CNDCTL_SRCND_Pos = 0x1
	// Bit mask of SRCND field.
	I3C_CNDCTL_SRCND_Msk = 0x2
	// Bit SRCND.
	I3C_CNDCTL_SRCND = 0x2
	// Does not request to issue a Repeated START condition.
	I3C_CNDCTL_SRCND_0 = 0x0
	// Requests to issue a Repeated START condition.
	I3C_CNDCTL_SRCND_1 = 0x1
	// Position of SPCND field.
	I3C_CNDCTL_SPCND_Pos = 0x2
	// Bit mask of SPCND field.
	I3C_CNDCTL_SPCND_Msk = 0x4
	// Bit SPCND.
	I3C_CNDCTL_SPCND = 0x4
	// Does not request to issue a STOP condition.
	I3C_CNDCTL_SPCND_0 = 0x0
	// Requests to issue a STOP condition.
	I3C_CNDCTL_SPCND_1 = 0x1

	// NQTHCTL: Normal Queue Threshold Control Register
	// Position of CMDQTH field.
	I3C_NQTHCTL_CMDQTH_Pos = 0x0
	// Bit mask of CMDQTH field.
	I3C_NQTHCTL_CMDQTH_Msk = 0xff
	// Interrupt is issued when Command Queue is completely empty.
	I3C_NQTHCTL_CMDQTH_0x00 = 0x0
	// Interrupt is issued when Command Queue contains N empties. (N = CMDQTH[7:0])
	I3C_NQTHCTL_CMDQTH_Others = 0x1
	// Position of RSPQTH field.
	I3C_NQTHCTL_RSPQTH_Pos = 0x8
	// Bit mask of RSPQTH field.
	I3C_NQTHCTL_RSPQTH_Msk = 0xff00
	// Interrupt is issued when Response Queue contains 1 entry (DWORD).
	I3C_NQTHCTL_RSPQTH_0x00 = 0x0
	// Interrupt is triggered when Response Queue contains N+1 entries (DWORD). (N = CMDQTH[7:0])
	I3C_NQTHCTL_RSPQTH_Others = 0x1
	// Position of IBIDSSZ field.
	I3C_NQTHCTL_IBIDSSZ_Pos = 0x10
	// Bit mask of IBIDSSZ field.
	I3C_NQTHCTL_IBIDSSZ_Msk = 0xff0000
	// Position of IBIQTH field.
	I3C_NQTHCTL_IBIQTH_Pos = 0x18
	// Bit mask of IBIQTH field.
	I3C_NQTHCTL_IBIQTH_Msk = 0xff000000
	// I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is 1 or more. I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer is completely empty.
	I3C_NQTHCTL_IBIQTH_0x00 = 0x0
	// I3C Protocol mode (Master): Interrupt is generated when the Outstanding IBI Status count is N + 1 or more. (N = CMDQTH[7:0]) I3C Protocol mode (Slave): Interrupt is issued when IBI Data Buffer contains N empties.
	I3C_NQTHCTL_IBIQTH_Others = 0x1

	// NTBTHCTL0: Normal Transfer Data Buffer Threshold Control Register 0
	// Position of TXDBTH field.
	I3C_NTBTHCTL0_TXDBTH_Pos = 0x0
	// Bit mask of TXDBTH field.
	I3C_NTBTHCTL0_TXDBTH_Msk = 0x7
	// Interrupt triggers at 2 Tx Buffer empties, DWORDs
	I3C_NTBTHCTL0_TXDBTH_000 = 0x0
	// Interrupt triggers at 4 Tx Buffer empties, DWORDs
	I3C_NTBTHCTL0_TXDBTH_001 = 0x1
	// Interrupt triggers at 8 Tx Buffer empties, DWORDs
	I3C_NTBTHCTL0_TXDBTH_010 = 0x2
	// Interrupt triggers at 16 Tx Buffer empties, DWORDs
	I3C_NTBTHCTL0_TXDBTH_011 = 0x3
	// Setting prohibited
	I3C_NTBTHCTL0_TXDBTH_Others = 0x4
	// Position of RXDBTH field.
	I3C_NTBTHCTL0_RXDBTH_Pos = 0x8
	// Bit mask of RXDBTH field.
	I3C_NTBTHCTL0_RXDBTH_Msk = 0x700
	// Interrupt triggers at 2 Rx Buffer entries, DWORDs
	I3C_NTBTHCTL0_RXDBTH_000 = 0x0
	// Interrupt triggers at 4 Rx Buffer entries, DWORDs
	I3C_NTBTHCTL0_RXDBTH_001 = 0x1
	// Interrupt triggers at 8 Rx Buffer entries, DWORDs
	I3C_NTBTHCTL0_RXDBTH_010 = 0x2
	// Interrupt triggers at 16 Rx Buffer entries, DWORDs
	I3C_NTBTHCTL0_RXDBTH_011 = 0x3
	// Setting prohibited
	I3C_NTBTHCTL0_RXDBTH_Others = 0x4
	// Position of TXSTTH field.
	I3C_NTBTHCTL0_TXSTTH_Pos = 0x10
	// Bit mask of TXSTTH field.
	I3C_NTBTHCTL0_TXSTTH_Msk = 0x70000
	// Wait for 2 entry DWORDs
	I3C_NTBTHCTL0_TXSTTH_000 = 0x0
	// Wait for 4 entry DWORDs
	I3C_NTBTHCTL0_TXSTTH_001 = 0x1
	// Wait for 8 entry DWORDs
	I3C_NTBTHCTL0_TXSTTH_010 = 0x2
	// Wait for 16 entry DWORDs
	I3C_NTBTHCTL0_TXSTTH_011 = 0x3
	// Setting prohibited
	I3C_NTBTHCTL0_TXSTTH_Others = 0x4
	// Position of RXSTTH field.
	I3C_NTBTHCTL0_RXSTTH_Pos = 0x18
	// Bit mask of RXSTTH field.
	I3C_NTBTHCTL0_RXSTTH_Msk = 0x7000000
	// Wait for 2 empty DWORDs
	I3C_NTBTHCTL0_RXSTTH_000 = 0x0
	// Wait for 4 empty DWORDs
	I3C_NTBTHCTL0_RXSTTH_001 = 0x1
	// Wait for 8 empty DWORDs
	I3C_NTBTHCTL0_RXSTTH_010 = 0x2
	// Wait for 16 empty DWORDs
	I3C_NTBTHCTL0_RXSTTH_011 = 0x3
	// Setting prohibited
	I3C_NTBTHCTL0_RXSTTH_Others = 0x4

	// NRQTHCTL: Normal Receive Status Queue Threshold Control Register
	// Position of RSQTH field.
	I3C_NRQTHCTL_RSQTH_Pos = 0x0
	// Bit mask of RSQTH field.
	I3C_NRQTHCTL_RSQTH_Msk = 0xff
	// Interrupt is issued when Receive Status Queue contains 1 entry (DWORD).
	I3C_NRQTHCTL_RSQTH_0x00 = 0x0
	// Interrupt is triggered when Receive Status Queue contains N+1 entries (DWORD). (N = RSQTH[7:0])
	I3C_NRQTHCTL_RSQTH_Others = 0x1

	// HQTHCTL: High Priority Queue Threshold Control Register
	// Position of CMDQTH field.
	I3C_HQTHCTL_CMDQTH_Pos = 0x0
	// Bit mask of CMDQTH field.
	I3C_HQTHCTL_CMDQTH_Msk = 0xff
	// Interrupt is issued when High Priority Command Queue is completely empty.
	I3C_HQTHCTL_CMDQTH_0x00 = 0x0
	// Interrupt is issued when High Priority Command Queue contains N entries. (N = CMDQTH[7:0])
	I3C_HQTHCTL_CMDQTH_Others = 0x1
	// Position of RSPQTH field.
	I3C_HQTHCTL_RSPQTH_Pos = 0x8
	// Bit mask of RSPQTH field.
	I3C_HQTHCTL_RSPQTH_Msk = 0xff00
	// Interrupt is issued when High Priority Response Queue contains 1 entry (DWORD).
	I3C_HQTHCTL_RSPQTH_0x00 = 0x0
	// Interrupt is triggered when High Priority Response Queue contains N+1 entries (DWORD). (N = RSPQTH[7:0])
	I3C_HQTHCTL_RSPQTH_Others = 0x1

	// HTBTHCTL: High Priority Transfer Data Buffer Threshold Control Register
	// Position of TXDBTH field.
	I3C_HTBTHCTL_TXDBTH_Pos = 0x0
	// Bit mask of TXDBTH field.
	I3C_HTBTHCTL_TXDBTH_Msk = 0x7
	// Interrupt triggers at 2 High Priority Tx Buffer empties, DWORDs
	I3C_HTBTHCTL_TXDBTH_000 = 0x0
	// Reserved
	I3C_HTBTHCTL_TXDBTH_001 = 0x1
	// Setting prohibited
	I3C_HTBTHCTL_TXDBTH_Others = 0x2
	// Position of RXDBTH field.
	I3C_HTBTHCTL_RXDBTH_Pos = 0x8
	// Bit mask of RXDBTH field.
	I3C_HTBTHCTL_RXDBTH_Msk = 0x700
	// Interrupt triggers at 2 High Priority Rx Buffer entries, DWORDs
	I3C_HTBTHCTL_RXDBTH_000 = 0x0
	// Reserved
	I3C_HTBTHCTL_RXDBTH_001 = 0x1
	// Setting prohibited
	I3C_HTBTHCTL_RXDBTH_Others = 0x2
	// Position of TXSTTH field.
	I3C_HTBTHCTL_TXSTTH_Pos = 0x10
	// Bit mask of TXSTTH field.
	I3C_HTBTHCTL_TXSTTH_Msk = 0x70000
	// Wait for 2 entry DWORDs
	I3C_HTBTHCTL_TXSTTH_000 = 0x0
	// Reserved
	I3C_HTBTHCTL_TXSTTH_001 = 0x1
	// Setting prohibited
	I3C_HTBTHCTL_TXSTTH_Others = 0x2
	// Position of RXSTTH field.
	I3C_HTBTHCTL_RXSTTH_Pos = 0x18
	// Bit mask of RXSTTH field.
	I3C_HTBTHCTL_RXSTTH_Msk = 0x7000000
	// Wait for 2 empty DWORDs
	I3C_HTBTHCTL_RXSTTH_000 = 0x0
	// Reserved
	I3C_HTBTHCTL_RXSTTH_001 = 0x1
	// Setting prohibited
	I3C_HTBTHCTL_RXSTTH_Others = 0x2

	// BST: Bus Status Register
	// Position of STCNDDF field.
	I3C_BST_STCNDDF_Pos = 0x0
	// Bit mask of STCNDDF field.
	I3C_BST_STCNDDF_Msk = 0x1
	// Bit STCNDDF.
	I3C_BST_STCNDDF = 0x1
	// START condition is not detected.
	I3C_BST_STCNDDF_0 = 0x0
	// START condition is detected.
	I3C_BST_STCNDDF_1 = 0x1
	// Position of SPCNDDF field.
	I3C_BST_SPCNDDF_Pos = 0x1
	// Bit mask of SPCNDDF field.
	I3C_BST_SPCNDDF_Msk = 0x2
	// Bit SPCNDDF.
	I3C_BST_SPCNDDF = 0x2
	// STOP condition is not detected.
	I3C_BST_SPCNDDF_0 = 0x0
	// STOP condition is detected.
	I3C_BST_SPCNDDF_1 = 0x1
	// Position of HDREXDF field.
	I3C_BST_HDREXDF_Pos = 0x2
	// Bit mask of HDREXDF field.
	I3C_BST_HDREXDF_Msk = 0x4
	// Bit HDREXDF.
	I3C_BST_HDREXDF = 0x4
	// HDR Exit Pattern is not detected
	I3C_BST_HDREXDF_0 = 0x0
	// HDR Exit Pattern is detected.
	I3C_BST_HDREXDF_1 = 0x1
	// Position of NACKDF field.
	I3C_BST_NACKDF_Pos = 0x4
	// Bit mask of NACKDF field.
	I3C_BST_NACKDF_Msk = 0x10
	// Bit NACKDF.
	I3C_BST_NACKDF = 0x10
	// NACK is not detected.
	I3C_BST_NACKDF_0 = 0x0
	// NACK is detected.
	I3C_BST_NACKDF_1 = 0x1
	// Position of TENDF field.
	I3C_BST_TENDF_Pos = 0x8
	// Bit mask of TENDF field.
	I3C_BST_TENDF_Msk = 0x100
	// Bit TENDF.
	I3C_BST_TENDF = 0x100
	// Data is being transmitted.
	I3C_BST_TENDF_0 = 0x0
	// Data has been transmitted.
	I3C_BST_TENDF_1 = 0x1
	// Position of ALF field.
	I3C_BST_ALF_Pos = 0x10
	// Bit mask of ALF field.
	I3C_BST_ALF_Msk = 0x10000
	// Bit ALF.
	I3C_BST_ALF = 0x10000
	// Arbitration is not lost
	I3C_BST_ALF_0 = 0x0
	// Arbitration is lost.
	I3C_BST_ALF_1 = 0x1
	// Position of TODF field.
	I3C_BST_TODF_Pos = 0x14
	// Bit mask of TODF field.
	I3C_BST_TODF_Msk = 0x100000
	// Bit TODF.
	I3C_BST_TODF = 0x100000
	// Timeout is not detected.
	I3C_BST_TODF_0 = 0x0
	// Timeout is detected.
	I3C_BST_TODF_1 = 0x1
	// Position of WUCNDDF field.
	I3C_BST_WUCNDDF_Pos = 0x18
	// Bit mask of WUCNDDF field.
	I3C_BST_WUCNDDF_Msk = 0x1000000
	// Bit WUCNDDF.
	I3C_BST_WUCNDDF = 0x1000000
	// Wake-Up is not detected.
	I3C_BST_WUCNDDF_0 = 0x0
	// Wake-Up is detected.
	I3C_BST_WUCNDDF_1 = 0x1

	// BSTE: Bus Status Enable Register
	// Position of STCNDDE field.
	I3C_BSTE_STCNDDE_Pos = 0x0
	// Bit mask of STCNDDE field.
	I3C_BSTE_STCNDDE_Msk = 0x1
	// Bit STCNDDE.
	I3C_BSTE_STCNDDE = 0x1
	// Disables START condition Detection Interrupt Status logging.
	I3C_BSTE_STCNDDE_0 = 0x0
	// Enables START condition Detection Interrupt Status logging.
	I3C_BSTE_STCNDDE_1 = 0x1
	// Position of SPCNDDE field.
	I3C_BSTE_SPCNDDE_Pos = 0x1
	// Bit mask of SPCNDDE field.
	I3C_BSTE_SPCNDDE_Msk = 0x2
	// Bit SPCNDDE.
	I3C_BSTE_SPCNDDE = 0x2
	// Disables STOP condition Detection Interrupt Status logging.
	I3C_BSTE_SPCNDDE_0 = 0x0
	// Enables STOP condition Detection Interrupt Status logging.
	I3C_BSTE_SPCNDDE_1 = 0x1
	// Position of HDREXDE field.
	I3C_BSTE_HDREXDE_Pos = 0x2
	// Bit mask of HDREXDE field.
	I3C_BSTE_HDREXDE_Msk = 0x4
	// Bit HDREXDE.
	I3C_BSTE_HDREXDE = 0x4
	// Disables HDR Exit Pattern Detection Interrupt Status logging.
	I3C_BSTE_HDREXDE_0 = 0x0
	// Enables HDR Exit Pattern Detection Interrupt Status logging.
	I3C_BSTE_HDREXDE_1 = 0x1
	// Position of NACKDE field.
	I3C_BSTE_NACKDE_Pos = 0x4
	// Bit mask of NACKDE field.
	I3C_BSTE_NACKDE_Msk = 0x10
	// Bit NACKDE.
	I3C_BSTE_NACKDE = 0x10
	// Disables NACK Detection Interrupt Status logging.
	I3C_BSTE_NACKDE_0 = 0x0
	// Enables NACK Detection Interrupt Status logging.
	I3C_BSTE_NACKDE_1 = 0x1
	// Position of TENDE field.
	I3C_BSTE_TENDE_Pos = 0x8
	// Bit mask of TENDE field.
	I3C_BSTE_TENDE_Msk = 0x100
	// Bit TENDE.
	I3C_BSTE_TENDE = 0x100
	// Disables Transmit End Interrupt Status logging.
	I3C_BSTE_TENDE_0 = 0x0
	// Enables Transmit End Interrupt Status logging.
	I3C_BSTE_TENDE_1 = 0x1
	// Position of ALE field.
	I3C_BSTE_ALE_Pos = 0x10
	// Bit mask of ALE field.
	I3C_BSTE_ALE_Msk = 0x10000
	// Bit ALE.
	I3C_BSTE_ALE = 0x10000
	// Disables Arbitration Lost Interrupt Status logging.
	I3C_BSTE_ALE_0 = 0x0
	// Enables Arbitration Lost Interrupt Status logging.
	I3C_BSTE_ALE_1 = 0x1
	// Position of TODE field.
	I3C_BSTE_TODE_Pos = 0x14
	// Bit mask of TODE field.
	I3C_BSTE_TODE_Msk = 0x100000
	// Bit TODE.
	I3C_BSTE_TODE = 0x100000
	// Disables Timeout Detection Interrupt Status logging.
	I3C_BSTE_TODE_0 = 0x0
	// Enables Timeout Detection Interrupt Status logging.
	I3C_BSTE_TODE_1 = 0x1
	// Position of WUCNDDE field.
	I3C_BSTE_WUCNDDE_Pos = 0x18
	// Bit mask of WUCNDDE field.
	I3C_BSTE_WUCNDDE_Msk = 0x1000000
	// Bit WUCNDDE.
	I3C_BSTE_WUCNDDE = 0x1000000
	// Disables Wake-up Condition Detection Status logging.
	I3C_BSTE_WUCNDDE_0 = 0x0
	// Enables Wake-up Condition Detection Status logging.
	I3C_BSTE_WUCNDDE_1 = 0x1

	// BIE: Bus Interrupt Enable Register
	// Position of STCNDDIE field.
	I3C_BIE_STCNDDIE_Pos = 0x0
	// Bit mask of STCNDDIE field.
	I3C_BIE_STCNDDIE_Msk = 0x1
	// Bit STCNDDIE.
	I3C_BIE_STCNDDIE = 0x1
	// Disables START condition Detection Interrupt Signal.
	I3C_BIE_STCNDDIE_0 = 0x0
	// Enables START condition Detection Interrupt Signal.
	I3C_BIE_STCNDDIE_1 = 0x1
	// Position of SPCNDDIE field.
	I3C_BIE_SPCNDDIE_Pos = 0x1
	// Bit mask of SPCNDDIE field.
	I3C_BIE_SPCNDDIE_Msk = 0x2
	// Bit SPCNDDIE.
	I3C_BIE_SPCNDDIE = 0x2
	// Disables STOP condition Detection Interrupt Signal.
	I3C_BIE_SPCNDDIE_0 = 0x0
	// Enables STOP condition Detection Interrupt Signal.
	I3C_BIE_SPCNDDIE_1 = 0x1
	// Position of HDREXDIE field.
	I3C_BIE_HDREXDIE_Pos = 0x2
	// Bit mask of HDREXDIE field.
	I3C_BIE_HDREXDIE_Msk = 0x4
	// Bit HDREXDIE.
	I3C_BIE_HDREXDIE = 0x4
	// Disables HDR Exit Pattern Detection Interrupt Signal.
	I3C_BIE_HDREXDIE_0 = 0x0
	// Enables HDR Exit Pattern Detection Interrupt Signal.
	I3C_BIE_HDREXDIE_1 = 0x1
	// Position of NACKDIE field.
	I3C_BIE_NACKDIE_Pos = 0x4
	// Bit mask of NACKDIE field.
	I3C_BIE_NACKDIE_Msk = 0x10
	// Bit NACKDIE.
	I3C_BIE_NACKDIE = 0x10
	// Disables NACK Detection Interrupt Signal.
	I3C_BIE_NACKDIE_0 = 0x0
	// Enables NACK Detection Interrupt Signal.
	I3C_BIE_NACKDIE_1 = 0x1
	// Position of TENDIE field.
	I3C_BIE_TENDIE_Pos = 0x8
	// Bit mask of TENDIE field.
	I3C_BIE_TENDIE_Msk = 0x100
	// Bit TENDIE.
	I3C_BIE_TENDIE = 0x100
	// Disables Transmit End Interrupt Signal.
	I3C_BIE_TENDIE_0 = 0x0
	// Enables Transmit End Interrupt Signal.
	I3C_BIE_TENDIE_1 = 0x1
	// Position of ALIE field.
	I3C_BIE_ALIE_Pos = 0x10
	// Bit mask of ALIE field.
	I3C_BIE_ALIE_Msk = 0x10000
	// Bit ALIE.
	I3C_BIE_ALIE = 0x10000
	// Disables Arbitration Lost Interrupt Signal.
	I3C_BIE_ALIE_0 = 0x0
	// Enables Arbitration Lost Interrupt Signal.
	I3C_BIE_ALIE_1 = 0x1
	// Position of TODIE field.
	I3C_BIE_TODIE_Pos = 0x14
	// Bit mask of TODIE field.
	I3C_BIE_TODIE_Msk = 0x100000
	// Bit TODIE.
	I3C_BIE_TODIE = 0x100000
	// Disables Timeout Detection Interrupt Signal.
	I3C_BIE_TODIE_0 = 0x0
	// Enables Timeout Detection Interrupt Signal.
	I3C_BIE_TODIE_1 = 0x1
	// Position of WUCNDDIE field.
	I3C_BIE_WUCNDDIE_Pos = 0x18
	// Bit mask of WUCNDDIE field.
	I3C_BIE_WUCNDDIE_Msk = 0x1000000
	// Bit WUCNDDIE.
	I3C_BIE_WUCNDDIE = 0x1000000
	// Disables Wake-Up Condition Detection Interrupt Signal.
	I3C_BIE_WUCNDDIE_0 = 0x0
	// Enables Wake-Up Condition Detection Interrupt Signal.
	I3C_BIE_WUCNDDIE_1 = 0x1

	// BSTFC: Bus Status Force Register
	// Position of STCNDDFC field.
	I3C_BSTFC_STCNDDFC_Pos = 0x0
	// Bit mask of STCNDDFC field.
	I3C_BSTFC_STCNDDFC_Msk = 0x1
	// Bit STCNDDFC.
	I3C_BSTFC_STCNDDFC = 0x1
	// Not Force START condition Detection Interrupt for software testing.
	I3C_BSTFC_STCNDDFC_0 = 0x0
	// Force START condition Detection Interrupt for software testing.
	I3C_BSTFC_STCNDDFC_1 = 0x1
	// Position of SPCNDDFC field.
	I3C_BSTFC_SPCNDDFC_Pos = 0x1
	// Bit mask of SPCNDDFC field.
	I3C_BSTFC_SPCNDDFC_Msk = 0x2
	// Bit SPCNDDFC.
	I3C_BSTFC_SPCNDDFC = 0x2
	// Not Force STOP condition Detection Interrupt for software testing.
	I3C_BSTFC_SPCNDDFC_0 = 0x0
	// Force STOP condition Detection Interrupt for software testing.
	I3C_BSTFC_SPCNDDFC_1 = 0x1
	// Position of HDREXDFC field.
	I3C_BSTFC_HDREXDFC_Pos = 0x2
	// Bit mask of HDREXDFC field.
	I3C_BSTFC_HDREXDFC_Msk = 0x4
	// Bit HDREXDFC.
	I3C_BSTFC_HDREXDFC = 0x4
	// Not Force HDR Exit Pattern Detection Interrupt for software testing.
	I3C_BSTFC_HDREXDFC_0 = 0x0
	// Force HDR Exit Pattern Detection Interrupt for software testing.
	I3C_BSTFC_HDREXDFC_1 = 0x1
	// Position of NACKDFC field.
	I3C_BSTFC_NACKDFC_Pos = 0x4
	// Bit mask of NACKDFC field.
	I3C_BSTFC_NACKDFC_Msk = 0x10
	// Bit NACKDFC.
	I3C_BSTFC_NACKDFC = 0x10
	// Not Force NACK Detection Interrupt for software testing.
	I3C_BSTFC_NACKDFC_0 = 0x0
	// Force NACK Detection Interrupt for software testing.
	I3C_BSTFC_NACKDFC_1 = 0x1
	// Position of TENDFC field.
	I3C_BSTFC_TENDFC_Pos = 0x8
	// Bit mask of TENDFC field.
	I3C_BSTFC_TENDFC_Msk = 0x100
	// Bit TENDFC.
	I3C_BSTFC_TENDFC = 0x100
	// Not Force Transmit End Interrupt for software testing.
	I3C_BSTFC_TENDFC_0 = 0x0
	// Force Transmit End Interrupt for software testing.
	I3C_BSTFC_TENDFC_1 = 0x1
	// Position of ALFC field.
	I3C_BSTFC_ALFC_Pos = 0x10
	// Bit mask of ALFC field.
	I3C_BSTFC_ALFC_Msk = 0x10000
	// Bit ALFC.
	I3C_BSTFC_ALFC = 0x10000
	// Not Force Arbitration Lost Interrupt for software testing.
	I3C_BSTFC_ALFC_0 = 0x0
	// Force Arbitration Lost Interrupt for software testing.
	I3C_BSTFC_ALFC_1 = 0x1
	// Position of TODFC field.
	I3C_BSTFC_TODFC_Pos = 0x14
	// Bit mask of TODFC field.
	I3C_BSTFC_TODFC_Msk = 0x100000
	// Bit TODFC.
	I3C_BSTFC_TODFC = 0x100000
	// Not Force Timeout Detection Interrupt for software testing.
	I3C_BSTFC_TODFC_0 = 0x0
	// Force Timeout Detection Interrupt for software testing.
	I3C_BSTFC_TODFC_1 = 0x1
	// Position of WUCNDDFC field.
	I3C_BSTFC_WUCNDDFC_Pos = 0x18
	// Bit mask of WUCNDDFC field.
	I3C_BSTFC_WUCNDDFC_Msk = 0x1000000
	// Bit WUCNDDFC.
	I3C_BSTFC_WUCNDDFC = 0x1000000
	// Not Force Wake-Up Condition Detection Interrupt for software testing.
	I3C_BSTFC_WUCNDDFC_0 = 0x0
	// Force Wake-Up Condition Detection Interrupt for software testing.
	I3C_BSTFC_WUCNDDFC_1 = 0x1

	// NTST: Normal Transfer Status Register
	// Position of TDBEF0 field.
	I3C_NTST_TDBEF0_Pos = 0x0
	// Bit mask of TDBEF0 field.
	I3C_NTST_TDBEF0_Msk = 0x1
	// Bit TDBEF0.
	I3C_NTST_TDBEF0 = 0x1
	// For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is less than the NTBTHCTL0.TXDBTH[2:0] threshold.
	I3C_NTST_TDBEF0_0 = 0x0
	// For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Transmit Data Buffer 0 contains no transmit data. For I3C protocol mode: PRTS.PRTMD bit = 0. The number of empties in the Normal Transmit Data Buffer 0 is the NTBTHCTL0.TXDBTH[2:0] threshold or more.
	I3C_NTST_TDBEF0_1 = 0x1
	// Position of RDBFF0 field.
	I3C_NTST_RDBFF0_Pos = 0x1
	// Bit mask of RDBFF0 field.
	I3C_NTST_RDBFF0_Msk = 0x2
	// Bit RDBFF0.
	I3C_NTST_RDBFF0 = 0x2
	// For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains no receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is less than the NTBTHCTL0.RXDBTH[2:0] threshold.
	I3C_NTST_RDBFF0_0 = 0x0
	// For I2C protocol mode: PRTS.PRTMD bit = 1. Normal Receive Data Buffer0 contains receive data. For I3C Protocol mode: PRTS.PRTMD bit = 0. The number of entries in the Normal Receive Data Buffer 0 is the NTBTHCTL0.RXDBTH[2:0] threshold or more.
	I3C_NTST_RDBFF0_1 = 0x1
	// Position of IBIQEFF field.
	I3C_NTST_IBIQEFF_Pos = 0x2
	// Bit mask of IBIQEFF field.
	I3C_NTST_IBIQEFF_Msk = 0x4
	// Bit IBIQEFF.
	I3C_NTST_IBIQEFF = 0x4
	// For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is the NQTHCTL.IBIQTH threshold or less. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is less than the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is less than the NQTHCTL.IBIQTH threshold.
	I3C_NTST_IBIQEFF_0 = 0x0
	// For I3C protocol mode (Master): PRTS.PRTMD bit = 0, PRSST.CRMS bit = 1. The number of IBI Status Queue entries is more than the NQTHCTL.IBIQTH threshold. For I3C protocol mode (Slave) : PRTS.PRTMD bit = 0, PRSST.CRMS bit = 0. If the NQTHCTL.IBIQTH = 0: The number of IBI Data Buffer empties is the IBI Data Buffer size. If the NQTHCTL.IBIQTH is other than 0: The number of IBI Data Buffer empties is the NQTHCTL.IBIQTH threshold or more.
	I3C_NTST_IBIQEFF_1 = 0x1
	// Position of CMDQEF field.
	I3C_NTST_CMDQEF_Pos = 0x3
	// Bit mask of CMDQEF field.
	I3C_NTST_CMDQEF_Msk = 0x8
	// Bit CMDQEF.
	I3C_NTST_CMDQEF = 0x8
	// If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is less than the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: The number of Command Queue empties is less than the NQTHCTL.CMDQTH threshold.
	I3C_NTST_CMDQEF_0 = 0x0
	// If the NQTHCTL.CMDQTH = 0: The number of Command Queue empties is the Command Queue size. If the NQTHCTL.CMDQTH is other than 0: 1: The number of Command Queue empties is the NQTHCTL.CMDQTH threshold or more.
	I3C_NTST_CMDQEF_1 = 0x1
	// Position of RSPQFF field.
	I3C_NTST_RSPQFF_Pos = 0x4
	// Bit mask of RSPQFF field.
	I3C_NTST_RSPQFF_Msk = 0x10
	// Bit RSPQFF.
	I3C_NTST_RSPQFF = 0x10
	// The number of Response Queue entries is the NQTHCTL.RSPQTH threshold or less.
	I3C_NTST_RSPQFF_0 = 0x0
	// The number of Response Queue entries is more than the NQTHCTL.RSPQTH threshold.
	I3C_NTST_RSPQFF_1 = 0x1
	// Position of TABTF field.
	I3C_NTST_TABTF_Pos = 0x5
	// Bit mask of TABTF field.
	I3C_NTST_TABTF_Msk = 0x20
	// Bit TABTF.
	I3C_NTST_TABTF = 0x20
	// Transfer Abort does not occur.
	I3C_NTST_TABTF_0 = 0x0
	// Transfer Abort occur. To clear, write 0 to this bit after 1 state is read.
	I3C_NTST_TABTF_1 = 0x1
	// Position of TEF field.
	I3C_NTST_TEF_Pos = 0x9
	// Bit mask of TEF field.
	I3C_NTST_TEF_Msk = 0x200
	// Bit TEF.
	I3C_NTST_TEF = 0x200
	// Transfer Error does not occur.
	I3C_NTST_TEF_0 = 0x0
	// Transfer Error occurs. To clear, write 0 to this bit after 1 state is read.
	I3C_NTST_TEF_1 = 0x1
	// Position of RSQFF field.
	I3C_NTST_RSQFF_Pos = 0x14
	// Bit mask of RSQFF field.
	I3C_NTST_RSQFF_Msk = 0x100000
	// Bit RSQFF.
	I3C_NTST_RSQFF = 0x100000
	// The number of Receive Status Queue entries is the NRQTHCTL.RSQTH threshold or less.
	I3C_NTST_RSQFF_0 = 0x0
	// The number of Receive Status Queue entries is more than the NRQTHCTL.RSQTH threshold.
	I3C_NTST_RSQFF_1 = 0x1

	// NTSTE: Normal Transfer Status Enable Register
	// Position of TDBEE0 field.
	I3C_NTSTE_TDBEE0_Pos = 0x0
	// Bit mask of TDBEE0 field.
	I3C_NTSTE_TDBEE0_Msk = 0x1
	// Bit TDBEE0.
	I3C_NTSTE_TDBEE0 = 0x1
	// Disables Tx0 Data Buffer Empty Interrupt Status logging.
	I3C_NTSTE_TDBEE0_0 = 0x0
	// Enables Tx0 Data Buffer Empty Interrupt Status logging.
	I3C_NTSTE_TDBEE0_1 = 0x1
	// Position of RDBFE0 field.
	I3C_NTSTE_RDBFE0_Pos = 0x1
	// Bit mask of RDBFE0 field.
	I3C_NTSTE_RDBFE0_Msk = 0x2
	// Bit RDBFE0.
	I3C_NTSTE_RDBFE0 = 0x2
	// Disables Rx0 Data Buffer Full Interrupt Status logging.
	I3C_NTSTE_RDBFE0_0 = 0x0
	// Enables Rx0 Data Buffer Full Interrupt Status logging.
	I3C_NTSTE_RDBFE0_1 = 0x1
	// Position of IBIQEFE field.
	I3C_NTSTE_IBIQEFE_Pos = 0x2
	// Bit mask of IBIQEFE field.
	I3C_NTSTE_IBIQEFE_Msk = 0x4
	// Bit IBIQEFE.
	I3C_NTSTE_IBIQEFE = 0x4
	// Disables IBI Status Buffer Empty/Full Interrupt Status logging.
	I3C_NTSTE_IBIQEFE_0 = 0x0
	// Enables IBI Status Buffer Empty/Full Interrupt Status logging.
	I3C_NTSTE_IBIQEFE_1 = 0x1
	// Position of CMDQEE field.
	I3C_NTSTE_CMDQEE_Pos = 0x3
	// Bit mask of CMDQEE field.
	I3C_NTSTE_CMDQEE_Msk = 0x8
	// Bit CMDQEE.
	I3C_NTSTE_CMDQEE = 0x8
	// Disables Command Buffer Empty Interrupt Status logging.
	I3C_NTSTE_CMDQEE_0 = 0x0
	// Enables Command Buffer Empty Interrupt Status logging.
	I3C_NTSTE_CMDQEE_1 = 0x1
	// Position of RSPQFE field.
	I3C_NTSTE_RSPQFE_Pos = 0x4
	// Bit mask of RSPQFE field.
	I3C_NTSTE_RSPQFE_Msk = 0x10
	// Bit RSPQFE.
	I3C_NTSTE_RSPQFE = 0x10
	// Disables Response Buffer Full Interrupt Status logging.
	I3C_NTSTE_RSPQFE_0 = 0x0
	// Enables Response Buffer Full Interrupt Status logging.
	I3C_NTSTE_RSPQFE_1 = 0x1
	// Position of TABTE field.
	I3C_NTSTE_TABTE_Pos = 0x5
	// Bit mask of TABTE field.
	I3C_NTSTE_TABTE_Msk = 0x20
	// Bit TABTE.
	I3C_NTSTE_TABTE = 0x20
	// Disables Transfer Abort Interrupt Status logging.
	I3C_NTSTE_TABTE_0 = 0x0
	// Enables Transfer Abort Interrupt Status logging.
	I3C_NTSTE_TABTE_1 = 0x1
	// Position of TEE field.
	I3C_NTSTE_TEE_Pos = 0x9
	// Bit mask of TEE field.
	I3C_NTSTE_TEE_Msk = 0x200
	// Bit TEE.
	I3C_NTSTE_TEE = 0x200
	// Disables Transfer Error Interrupt Status logging.
	I3C_NTSTE_TEE_0 = 0x0
	// Enables Transfer Error Interrupt Status logging.
	I3C_NTSTE_TEE_1 = 0x1
	// Position of RSQFE field.
	I3C_NTSTE_RSQFE_Pos = 0x14
	// Bit mask of RSQFE field.
	I3C_NTSTE_RSQFE_Msk = 0x100000
	// Bit RSQFE.
	I3C_NTSTE_RSQFE = 0x100000
	// Disables Receive Status Buffer Full Interrupt Status logging.
	I3C_NTSTE_RSQFE_0 = 0x0
	// Enables Receive Status Buffer Full Interrupt Status logging.
	I3C_NTSTE_RSQFE_1 = 0x1

	// NTIE: Normal Transfer Interrupt Enable Register
	// Position of TDBEIE0 field.
	I3C_NTIE_TDBEIE0_Pos = 0x0
	// Bit mask of TDBEIE0 field.
	I3C_NTIE_TDBEIE0_Msk = 0x1
	// Bit TDBEIE0.
	I3C_NTIE_TDBEIE0 = 0x1
	// Disables Tx0 Data Buffer Empty Interrupt Signal.
	I3C_NTIE_TDBEIE0_0 = 0x0
	// Enables Tx0 Data Buffer Empty Interrupt Signal.
	I3C_NTIE_TDBEIE0_1 = 0x1
	// Position of RDBFIE0 field.
	I3C_NTIE_RDBFIE0_Pos = 0x1
	// Bit mask of RDBFIE0 field.
	I3C_NTIE_RDBFIE0_Msk = 0x2
	// Bit RDBFIE0.
	I3C_NTIE_RDBFIE0 = 0x2
	// Disables Rx0 Data Buffer Full Interrupt Signal.
	I3C_NTIE_RDBFIE0_0 = 0x0
	// Enables Rx0 Data Buffer Full Interrupt Signal.
	I3C_NTIE_RDBFIE0_1 = 0x1
	// Position of IBIQEFIE field.
	I3C_NTIE_IBIQEFIE_Pos = 0x2
	// Bit mask of IBIQEFIE field.
	I3C_NTIE_IBIQEFIE_Msk = 0x4
	// Bit IBIQEFIE.
	I3C_NTIE_IBIQEFIE = 0x4
	// Disables IBI Status Buffer Empty/Full Interrupt Signal.
	I3C_NTIE_IBIQEFIE_0 = 0x0
	// Enables IBI Status Buffer Empty/Full Interrupt Signal.
	I3C_NTIE_IBIQEFIE_1 = 0x1
	// Position of CMDQEIE field.
	I3C_NTIE_CMDQEIE_Pos = 0x3
	// Bit mask of CMDQEIE field.
	I3C_NTIE_CMDQEIE_Msk = 0x8
	// Bit CMDQEIE.
	I3C_NTIE_CMDQEIE = 0x8
	// Disables Command Buffer Empty Interrupt Signal.
	I3C_NTIE_CMDQEIE_0 = 0x0
	// Enables Command Buffer Empty Interrupt Signal.
	I3C_NTIE_CMDQEIE_1 = 0x1
	// Position of RSPQFIE field.
	I3C_NTIE_RSPQFIE_Pos = 0x4
	// Bit mask of RSPQFIE field.
	I3C_NTIE_RSPQFIE_Msk = 0x10
	// Bit RSPQFIE.
	I3C_NTIE_RSPQFIE = 0x10
	// Disables Response Buffer Full Interrupt Signal.
	I3C_NTIE_RSPQFIE_0 = 0x0
	// Enables Response Buffer Full Interrupt Signal.
	I3C_NTIE_RSPQFIE_1 = 0x1
	// Position of TABTIE field.
	I3C_NTIE_TABTIE_Pos = 0x5
	// Bit mask of TABTIE field.
	I3C_NTIE_TABTIE_Msk = 0x20
	// Bit TABTIE.
	I3C_NTIE_TABTIE = 0x20
	// Disables Transfer Abort Interrupt Signal.
	I3C_NTIE_TABTIE_0 = 0x0
	// Enables Transfer Abort Interrupt Signal.
	I3C_NTIE_TABTIE_1 = 0x1
	// Position of TEIE field.
	I3C_NTIE_TEIE_Pos = 0x9
	// Bit mask of TEIE field.
	I3C_NTIE_TEIE_Msk = 0x200
	// Bit TEIE.
	I3C_NTIE_TEIE = 0x200
	// Disables Transfer Error Interrupt Signal.
	I3C_NTIE_TEIE_0 = 0x0
	// Enables Transfer Error Interrupt Signal.
	I3C_NTIE_TEIE_1 = 0x1
	// Position of RSQFIE field.
	I3C_NTIE_RSQFIE_Pos = 0x14
	// Bit mask of RSQFIE field.
	I3C_NTIE_RSQFIE_Msk = 0x100000
	// Bit RSQFIE.
	I3C_NTIE_RSQFIE = 0x100000
	// Disables Receive Status Buffer Full Interrupt Signal.
	I3C_NTIE_RSQFIE_0 = 0x0
	// Enables Receive Status Buffer Full Interrupt Signal.
	I3C_NTIE_RSQFIE_1 = 0x1

	// NTSTFC: Normal Transfer Status Force Register
	// Position of TDBEFC0 field.
	I3C_NTSTFC_TDBEFC0_Pos = 0x0
	// Bit mask of TDBEFC0 field.
	I3C_NTSTFC_TDBEFC0_Msk = 0x1
	// Bit TDBEFC0.
	I3C_NTSTFC_TDBEFC0 = 0x1
	// Not Force Tx0 Data Buffer Empty Interrupt for software testing.
	I3C_NTSTFC_TDBEFC0_0 = 0x0
	// Force Tx0 Data Buffer Empty Interrupt for software testing.
	I3C_NTSTFC_TDBEFC0_1 = 0x1
	// Position of RDBFFC0 field.
	I3C_NTSTFC_RDBFFC0_Pos = 0x1
	// Bit mask of RDBFFC0 field.
	I3C_NTSTFC_RDBFFC0_Msk = 0x2
	// Bit RDBFFC0.
	I3C_NTSTFC_RDBFFC0 = 0x2
	// Not Force Rx0 Data Buffer Full Interrupt for software testing.
	I3C_NTSTFC_RDBFFC0_0 = 0x0
	// Force Rx0 Data Buffer Full Interrupt for software testing.
	I3C_NTSTFC_RDBFFC0_1 = 0x1
	// Position of IBIQEFFC field.
	I3C_NTSTFC_IBIQEFFC_Pos = 0x2
	// Bit mask of IBIQEFFC field.
	I3C_NTSTFC_IBIQEFFC_Msk = 0x4
	// Bit IBIQEFFC.
	I3C_NTSTFC_IBIQEFFC = 0x4
	// Not Force IBI Status Buffer Full Interrupt for software testing.
	I3C_NTSTFC_IBIQEFFC_0 = 0x0
	// Force IBI Status Buffer Full Interrupt for software testing.
	I3C_NTSTFC_IBIQEFFC_1 = 0x1
	// Position of CMDQEFC field.
	I3C_NTSTFC_CMDQEFC_Pos = 0x3
	// Bit mask of CMDQEFC field.
	I3C_NTSTFC_CMDQEFC_Msk = 0x8
	// Bit CMDQEFC.
	I3C_NTSTFC_CMDQEFC = 0x8
	// Not Force Command Buffer Empty Interrupt for software testing.
	I3C_NTSTFC_CMDQEFC_0 = 0x0
	// Force Command Buffer Empty Interrupt for software testing.
	I3C_NTSTFC_CMDQEFC_1 = 0x1
	// Position of RSPQFFC field.
	I3C_NTSTFC_RSPQFFC_Pos = 0x4
	// Bit mask of RSPQFFC field.
	I3C_NTSTFC_RSPQFFC_Msk = 0x10
	// Bit RSPQFFC.
	I3C_NTSTFC_RSPQFFC = 0x10
	// Not Force Response Buffer Full Interrupt for software testing.
	I3C_NTSTFC_RSPQFFC_0 = 0x0
	// Force Response Buffer Full Interrupt for software testing.
	I3C_NTSTFC_RSPQFFC_1 = 0x1
	// Position of TABTFC field.
	I3C_NTSTFC_TABTFC_Pos = 0x5
	// Bit mask of TABTFC field.
	I3C_NTSTFC_TABTFC_Msk = 0x20
	// Bit TABTFC.
	I3C_NTSTFC_TABTFC = 0x20
	// Not Force Transfer Abort Interrupt for software testing.
	I3C_NTSTFC_TABTFC_0 = 0x0
	// Force Transfer Abort Interrupt for software testing.
	I3C_NTSTFC_TABTFC_1 = 0x1
	// Position of TEFC field.
	I3C_NTSTFC_TEFC_Pos = 0x9
	// Bit mask of TEFC field.
	I3C_NTSTFC_TEFC_Msk = 0x200
	// Bit TEFC.
	I3C_NTSTFC_TEFC = 0x200
	// Not Force Transfer Error Interrupt for software testing.
	I3C_NTSTFC_TEFC_0 = 0x0
	// Force Transfer Error Interrupt for software testing.
	I3C_NTSTFC_TEFC_1 = 0x1
	// Position of RSQFFC field.
	I3C_NTSTFC_RSQFFC_Pos = 0x14
	// Bit mask of RSQFFC field.
	I3C_NTSTFC_RSQFFC_Msk = 0x100000
	// Bit RSQFFC.
	I3C_NTSTFC_RSQFFC = 0x100000
	// Not Force Receive Status Buffer Full Interrupt for software testing.
	I3C_NTSTFC_RSQFFC_0 = 0x0
	// Force Receive Status Buffer Full Interrupt for software testing.
	I3C_NTSTFC_RSQFFC_1 = 0x1

	// HTST: High Priority Transfer Status Register
	// Position of TDBEF field.
	I3C_HTST_TDBEF_Pos = 0x0
	// Bit mask of TDBEF field.
	I3C_HTST_TDBEF_Msk = 0x1
	// Bit TDBEF.
	I3C_HTST_TDBEF = 0x1
	// The number of empties in the High Priority Transmit Data Buffer is less than the HTBTHCTL.TXDBTH[2:0] threshold.
	I3C_HTST_TDBEF_0 = 0x0
	// The number of empties in the High Priority Transmit Data Buffer is the HTBTHCTL.TXDBTH[2:0] threshold or more.
	I3C_HTST_TDBEF_1 = 0x1
	// Position of RDBFF field.
	I3C_HTST_RDBFF_Pos = 0x1
	// Bit mask of RDBFF field.
	I3C_HTST_RDBFF_Msk = 0x2
	// Bit RDBFF.
	I3C_HTST_RDBFF = 0x2
	// The number of entries in the High Priority Receive Data Buffer is less than the HTBTHCTL.RXDBTH[2:0] threshold.
	I3C_HTST_RDBFF_0 = 0x0
	// The number of entries in the High Priority Receive Data Buffer is the HTBTHCTL.RXDBTH[2:0] threshold or more.
	I3C_HTST_RDBFF_1 = 0x1
	// Position of CMDQEF field.
	I3C_HTST_CMDQEF_Pos = 0x3
	// Bit mask of CMDQEF field.
	I3C_HTST_CMDQEF_Msk = 0x8
	// Bit CMDQEF.
	I3C_HTST_CMDQEF = 0x8
	// If HQTHCTL.CMDQTH is 0, the number of Command Queue empties is less than the Command Queue size. If HQTHCTL.CMDQTH is other than 0, the number of High Priority Command Queue empties is less than the HQTHCTL.CMDQTH threshold.
	I3C_HTST_CMDQEF_0 = 0x0
	// If HQTHCTL.CMDQTH is 0, the number of Command Queue empties is the Command Queue size. If HQTHCTL.CMDQTH is other than 0, the number of High Priority Command Queue empties is the HQTHCTL.CMDQTH threshold or more.
	I3C_HTST_CMDQEF_1 = 0x1
	// Position of RSPQFF field.
	I3C_HTST_RSPQFF_Pos = 0x4
	// Bit mask of RSPQFF field.
	I3C_HTST_RSPQFF_Msk = 0x10
	// Bit RSPQFF.
	I3C_HTST_RSPQFF = 0x10
	// The number of High Priority Response Queue entries is less than the HQTHCTL .RSPQTH threshold.
	I3C_HTST_RSPQFF_0 = 0x0
	// The number of High Priority Response Queue entries is the HQTHCTL .RSPQTH threshold or more.
	I3C_HTST_RSPQFF_1 = 0x1
	// Position of TABTF field.
	I3C_HTST_TABTF_Pos = 0x5
	// Bit mask of TABTF field.
	I3C_HTST_TABTF_Msk = 0x20
	// Bit TABTF.
	I3C_HTST_TABTF = 0x20
	// High Priority Transfer Abort does not occur.
	I3C_HTST_TABTF_0 = 0x0
	// High Priority Transfer Abort occurs. To clear, write 0 to this bit after 1 is read.
	I3C_HTST_TABTF_1 = 0x1
	// Position of TEF field.
	I3C_HTST_TEF_Pos = 0x9
	// Bit mask of TEF field.
	I3C_HTST_TEF_Msk = 0x200
	// Bit TEF.
	I3C_HTST_TEF = 0x200
	// High Priority Transfer Error does not occur.
	I3C_HTST_TEF_0 = 0x0
	// High Priority Transfer Error occurs. To clear, write 0 to this bit after 1 is read.
	I3C_HTST_TEF_1 = 0x1

	// HTSTE: High Priority Transfer Status Enable Register
	// Position of TDBEE field.
	I3C_HTSTE_TDBEE_Pos = 0x0
	// Bit mask of TDBEE field.
	I3C_HTSTE_TDBEE_Msk = 0x1
	// Bit TDBEE.
	I3C_HTSTE_TDBEE = 0x1
	// Disables High Priority Transmit Data Buffer Empty Interrupt Status logging.
	I3C_HTSTE_TDBEE_0 = 0x0
	// Enables High Priority Transmit Data Buffer Empty Interrupt Status logging.
	I3C_HTSTE_TDBEE_1 = 0x1
	// Position of RDBFE field.
	I3C_HTSTE_RDBFE_Pos = 0x1
	// Bit mask of RDBFE field.
	I3C_HTSTE_RDBFE_Msk = 0x2
	// Bit RDBFE.
	I3C_HTSTE_RDBFE = 0x2
	// Disables High Priority Receive Data Buffer Full Interrupt Status logging.
	I3C_HTSTE_RDBFE_0 = 0x0
	// Enables High Priority Receive Data Buffer Full Interrupt Status logging.
	I3C_HTSTE_RDBFE_1 = 0x1
	// Position of CMDQEE field.
	I3C_HTSTE_CMDQEE_Pos = 0x3
	// Bit mask of CMDQEE field.
	I3C_HTSTE_CMDQEE_Msk = 0x8
	// Bit CMDQEE.
	I3C_HTSTE_CMDQEE = 0x8
	// Disables High Priority Command Buffer Empty Interrupt Status logging.
	I3C_HTSTE_CMDQEE_0 = 0x0
	// Enables High Priority Command Buffer Empty Interrupt Status logging.
	I3C_HTSTE_CMDQEE_1 = 0x1
	// Position of RSPQFE field.
	I3C_HTSTE_RSPQFE_Pos = 0x4
	// Bit mask of RSPQFE field.
	I3C_HTSTE_RSPQFE_Msk = 0x10
	// Bit RSPQFE.
	I3C_HTSTE_RSPQFE = 0x10
	// Disables High Priority Response Buffer Full Interrupt Status logging.
	I3C_HTSTE_RSPQFE_0 = 0x0
	// Enables High Priority Response Buffer Full Interrupt Status logging.
	I3C_HTSTE_RSPQFE_1 = 0x1
	// Position of TABTE field.
	I3C_HTSTE_TABTE_Pos = 0x5
	// Bit mask of TABTE field.
	I3C_HTSTE_TABTE_Msk = 0x20
	// Bit TABTE.
	I3C_HTSTE_TABTE = 0x20
	// Disables High PriorityTransfer Abort Interrupt Status logging.
	I3C_HTSTE_TABTE_0 = 0x0
	// Enables High Priority Transfer Abort Interrupt Status logging.
	I3C_HTSTE_TABTE_1 = 0x1
	// Position of TEE field.
	I3C_HTSTE_TEE_Pos = 0x9
	// Bit mask of TEE field.
	I3C_HTSTE_TEE_Msk = 0x200
	// Bit TEE.
	I3C_HTSTE_TEE = 0x200
	// Disables High Priority Transfer Error interrupt Stats logging.
	I3C_HTSTE_TEE_0 = 0x0
	// Enables High Priority Transfer Error interrupt Stats logging.
	I3C_HTSTE_TEE_1 = 0x1

	// HTIE: High Priority Transfer Interrupt Enable Register
	// Position of TDBEIE field.
	I3C_HTIE_TDBEIE_Pos = 0x0
	// Bit mask of TDBEIE field.
	I3C_HTIE_TDBEIE_Msk = 0x1
	// Bit TDBEIE.
	I3C_HTIE_TDBEIE = 0x1
	// Disables High Priority Transmit Data Buffer Empty Interrupt Signal.
	I3C_HTIE_TDBEIE_0 = 0x0
	// Enables High Priority Transmit Data Buffer Empty Interrupt Signal.
	I3C_HTIE_TDBEIE_1 = 0x1
	// Position of RDBFIE field.
	I3C_HTIE_RDBFIE_Pos = 0x1
	// Bit mask of RDBFIE field.
	I3C_HTIE_RDBFIE_Msk = 0x2
	// Bit RDBFIE.
	I3C_HTIE_RDBFIE = 0x2
	// Disables High Priority Receive Data Buffer Full Interrupt Signal.
	I3C_HTIE_RDBFIE_0 = 0x0
	// Enables High Priority Receive Data Buffer Full Interrupt Signal.
	I3C_HTIE_RDBFIE_1 = 0x1
	// Position of CMDQEIE field.
	I3C_HTIE_CMDQEIE_Pos = 0x3
	// Bit mask of CMDQEIE field.
	I3C_HTIE_CMDQEIE_Msk = 0x8
	// Bit CMDQEIE.
	I3C_HTIE_CMDQEIE = 0x8
	// Disables High Priority Command Buffer Empty Interrupt Signal.
	I3C_HTIE_CMDQEIE_0 = 0x0
	// Enables High Priority Command Buffer Empty Interrupt Signal.
	I3C_HTIE_CMDQEIE_1 = 0x1
	// Position of RSPQFIE field.
	I3C_HTIE_RSPQFIE_Pos = 0x4
	// Bit mask of RSPQFIE field.
	I3C_HTIE_RSPQFIE_Msk = 0x10
	// Bit RSPQFIE.
	I3C_HTIE_RSPQFIE = 0x10
	// Disables High Priority Response Buffer Full Interrupt Signal.
	I3C_HTIE_RSPQFIE_0 = 0x0
	// Enables High Priority Response Buffer Full Interrupt Signal.
	I3C_HTIE_RSPQFIE_1 = 0x1
	// Position of TABTIE field.
	I3C_HTIE_TABTIE_Pos = 0x5
	// Bit mask of TABTIE field.
	I3C_HTIE_TABTIE_Msk = 0x20
	// Bit TABTIE.
	I3C_HTIE_TABTIE = 0x20
	// Disables High Priority Transfer Abort interrupt Signal.
	I3C_HTIE_TABTIE_0 = 0x0
	// Enables High Priority Transfer Abort interrupt Signal.
	I3C_HTIE_TABTIE_1 = 0x1
	// Position of TEIE field.
	I3C_HTIE_TEIE_Pos = 0x9
	// Bit mask of TEIE field.
	I3C_HTIE_TEIE_Msk = 0x200
	// Bit TEIE.
	I3C_HTIE_TEIE = 0x200
	// Disables High Priority Transfer Error Interrupt Signal.
	I3C_HTIE_TEIE_0 = 0x0
	// Enables High Priority Transfer Error Interrupt Signal.
	I3C_HTIE_TEIE_1 = 0x1

	// HTSTFC: High Priority Transfer Status Force Register
	// Position of TDBEFC field.
	I3C_HTSTFC_TDBEFC_Pos = 0x0
	// Bit mask of TDBEFC field.
	I3C_HTSTFC_TDBEFC_Msk = 0x1
	// Bit TDBEFC.
	I3C_HTSTFC_TDBEFC = 0x1
	// Not Force High Priority Transmit Data Buffer Empty Interrupt for software testing.
	I3C_HTSTFC_TDBEFC_0 = 0x0
	// Force High Priority Transmit Data Buffer Empty Interrupt for software testing.
	I3C_HTSTFC_TDBEFC_1 = 0x1
	// Position of RDBFFC field.
	I3C_HTSTFC_RDBFFC_Pos = 0x1
	// Bit mask of RDBFFC field.
	I3C_HTSTFC_RDBFFC_Msk = 0x2
	// Bit RDBFFC.
	I3C_HTSTFC_RDBFFC = 0x2
	// Not Force High Priority Receive Data Buffer Full Interrupt for software testing.
	I3C_HTSTFC_RDBFFC_0 = 0x0
	// Force High Priority Receive Data Buffer Full Interrupt for software testing.
	I3C_HTSTFC_RDBFFC_1 = 0x1
	// Position of CMDQEFC field.
	I3C_HTSTFC_CMDQEFC_Pos = 0x3
	// Bit mask of CMDQEFC field.
	I3C_HTSTFC_CMDQEFC_Msk = 0x8
	// Bit CMDQEFC.
	I3C_HTSTFC_CMDQEFC = 0x8
	// Not Force High Priority Command Buffer Empty Interrupt for software testing.
	I3C_HTSTFC_CMDQEFC_0 = 0x0
	// Force High Priority Command Buffer Empty Interrupt for software testing.
	I3C_HTSTFC_CMDQEFC_1 = 0x1
	// Position of RSPQFFC field.
	I3C_HTSTFC_RSPQFFC_Pos = 0x4
	// Bit mask of RSPQFFC field.
	I3C_HTSTFC_RSPQFFC_Msk = 0x10
	// Bit RSPQFFC.
	I3C_HTSTFC_RSPQFFC = 0x10
	// Not Force High Priority Response Buffer Full Interrupt for software testing.
	I3C_HTSTFC_RSPQFFC_0 = 0x0
	// Force High Priority Response Buffer Full Interrupt for software testing.
	I3C_HTSTFC_RSPQFFC_1 = 0x1
	// Position of TABTFC field.
	I3C_HTSTFC_TABTFC_Pos = 0x5
	// Bit mask of TABTFC field.
	I3C_HTSTFC_TABTFC_Msk = 0x20
	// Bit TABTFC.
	I3C_HTSTFC_TABTFC = 0x20
	// Not Force High Priority Transfer Abort Interrupt for software testing.
	I3C_HTSTFC_TABTFC_0 = 0x0
	// Force High Priority Transfer Abort Interrupt for software testing.
	I3C_HTSTFC_TABTFC_1 = 0x1
	// Position of TEFC field.
	I3C_HTSTFC_TEFC_Pos = 0x9
	// Bit mask of TEFC field.
	I3C_HTSTFC_TEFC_Msk = 0x200
	// Bit TEFC.
	I3C_HTSTFC_TEFC = 0x200
	// Not Force High Priority Transfer Error Interrupt for software testing.
	I3C_HTSTFC_TEFC_0 = 0x0
	// Force High Priority Transfer Error Interrupt for software testing.
	I3C_HTSTFC_TEFC_1 = 0x1

	// BCST: Bus Condition Status Register
	// Position of BFREF field.
	I3C_BCST_BFREF_Pos = 0x0
	// Bit mask of BFREF field.
	I3C_BCST_BFREF_Msk = 0x1
	// Bit BFREF.
	I3C_BCST_BFREF = 0x1
	// Have not Detected Bus Free
	I3C_BCST_BFREF_0 = 0x0
	// Have Detected Bus Free
	I3C_BCST_BFREF_1 = 0x1
	// Position of BAVLF field.
	I3C_BCST_BAVLF_Pos = 0x1
	// Bit mask of BAVLF field.
	I3C_BCST_BAVLF_Msk = 0x2
	// Bit BAVLF.
	I3C_BCST_BAVLF = 0x2
	// Have not Detected Bus Available
	I3C_BCST_BAVLF_0 = 0x0
	// Have Detected Bus Available
	I3C_BCST_BAVLF_1 = 0x1
	// Position of BIDLF field.
	I3C_BCST_BIDLF_Pos = 0x2
	// Bit mask of BIDLF field.
	I3C_BCST_BIDLF_Msk = 0x4
	// Bit BIDLF.
	I3C_BCST_BIDLF = 0x4
	// Have not Detected Bus Idle
	I3C_BCST_BIDLF_0 = 0x0
	// Have Detected Bus Idle
	I3C_BCST_BIDLF_1 = 0x1

	// SVST: Slave Status Register
	// Position of GCAF field.
	I3C_SVST_GCAF_Pos = 0x0
	// Bit mask of GCAF field.
	I3C_SVST_GCAF_Msk = 0x1
	// Bit GCAF.
	I3C_SVST_GCAF = 0x1
	// General call address does not detect.
	I3C_SVST_GCAF_0 = 0x0
	// General call address detects.
	I3C_SVST_GCAF_1 = 0x1
	// Position of HSMCF field.
	I3C_SVST_HSMCF_Pos = 0x5
	// Bit mask of HSMCF field.
	I3C_SVST_HSMCF_Msk = 0x20
	// Bit HSMCF.
	I3C_SVST_HSMCF = 0x20
	// Hs-mode Master Code does not detect.
	I3C_SVST_HSMCF_0 = 0x0
	// Hs-mode Master Code detects.
	I3C_SVST_HSMCF_1 = 0x1
	// Position of DVIDF field.
	I3C_SVST_DVIDF_Pos = 0x6
	// Bit mask of DVIDF field.
	I3C_SVST_DVIDF_Msk = 0x40
	// Bit DVIDF.
	I3C_SVST_DVIDF = 0x40
	// Device-ID command does not detect.
	I3C_SVST_DVIDF_0 = 0x0
	// Device-ID command detects. This bit set to 1 when the first frame received immediately after a START condition is detected matches a value of (device ID (1111 100) + 0[W]).
	I3C_SVST_DVIDF_1 = 0x1
	// Position of HOAF field.
	I3C_SVST_HOAF_Pos = 0xf
	// Bit mask of HOAF field.
	I3C_SVST_HOAF_Msk = 0x8000
	// Bit HOAF.
	I3C_SVST_HOAF = 0x8000
	// Host address does not detect.
	I3C_SVST_HOAF_0 = 0x0
	// Host address detects. This bit set to 1 when the received slave address matches the host address (0001 000).
	I3C_SVST_HOAF_1 = 0x1
	// Position of SVAF field.
	I3C_SVST_SVAF_Pos = 0x10
	// Bit mask of SVAF field.
	I3C_SVST_SVAF_Msk = 0x70000
	// Slave n does not detect
	I3C_SVST_SVAF_0 = 0x0
	// Slave n detect
	I3C_SVST_SVAF_1 = 0x1

	// WUST: Wake Up Unit Operating Status Register
	// Position of WUASYNF field.
	I3C_WUST_WUASYNF_Pos = 0x0
	// Bit mask of WUASYNF field.
	I3C_WUST_WUASYNF_Msk = 0x1
	// Bit WUASYNF.
	I3C_WUST_WUASYNF = 0x1
	// I3C synchronous circuit enable condition.
	I3C_WUST_WUASYNF_0 = 0x0
	// I3C asynchronous circuit enable condition.
	I3C_WUST_WUASYNF_1 = 0x1

	// DATBAS0: Device Address Table Basic Register %s
	// Position of DVSTAD field.
	I3C_DATBAS_DVSTAD_Pos = 0x0
	// Bit mask of DVSTAD field.
	I3C_DATBAS_DVSTAD_Msk = 0x7f
	// Position of DVIBIPL field.
	I3C_DATBAS_DVIBIPL_Pos = 0xc
	// Bit mask of DVIBIPL field.
	I3C_DATBAS_DVIBIPL_Msk = 0x1000
	// Bit DVIBIPL.
	I3C_DATBAS_DVIBIPL = 0x1000
	// IBIs from this Device do not carry a Data Payload.
	I3C_DATBAS_DVIBIPL_0 = 0x0
	// IBIs from this Device do carry a Data Payload.
	I3C_DATBAS_DVIBIPL_1 = 0x1
	// Position of DVSIRRJ field.
	I3C_DATBAS_DVSIRRJ_Pos = 0xd
	// Bit mask of DVSIRRJ field.
	I3C_DATBAS_DVSIRRJ_Msk = 0x2000
	// Bit DVSIRRJ.
	I3C_DATBAS_DVSIRRJ = 0x2000
	// This Device shall ACK the SIR.
	I3C_DATBAS_DVSIRRJ_0 = 0x0
	// This Device shall NACK the SIR and send the auto-disable CCC.
	I3C_DATBAS_DVSIRRJ_1 = 0x1
	// Position of DVMRRJ field.
	I3C_DATBAS_DVMRRJ_Pos = 0xe
	// Bit mask of DVMRRJ field.
	I3C_DATBAS_DVMRRJ_Msk = 0x4000
	// Bit DVMRRJ.
	I3C_DATBAS_DVMRRJ = 0x4000
	// This Device shall ACK Master Requests.
	I3C_DATBAS_DVMRRJ_0 = 0x0
	// This Device shall NACK Master Requests and send the auto-disable command.
	I3C_DATBAS_DVMRRJ_1 = 0x1
	// Position of DVIBITS field.
	I3C_DATBAS_DVIBITS_Pos = 0xf
	// Bit mask of DVIBITS field.
	I3C_DATBAS_DVIBITS_Msk = 0x8000
	// Bit DVIBITS.
	I3C_DATBAS_DVIBITS = 0x8000
	// The Master shall not time-stamp IBIs from this Device with Master Time-stamps.
	I3C_DATBAS_DVIBITS_0 = 0x0
	// The Master shall time-stamp IBIs for this Device with Master Time-stamps.
	I3C_DATBAS_DVIBITS_1 = 0x1
	// Position of DVDYAD field.
	I3C_DATBAS_DVDYAD_Pos = 0x10
	// Bit mask of DVDYAD field.
	I3C_DATBAS_DVDYAD_Msk = 0xff0000
	// Position of DVNACK field.
	I3C_DATBAS_DVNACK_Pos = 0x1d
	// Bit mask of DVNACK field.
	I3C_DATBAS_DVNACK_Msk = 0x60000000
	// Position of DVTYP field.
	I3C_DATBAS_DVTYP_Pos = 0x1f
	// Bit mask of DVTYP field.
	I3C_DATBAS_DVTYP_Msk = 0x80000000
	// Bit DVTYP.
	I3C_DATBAS_DVTYP = 0x80000000
	// I3C Device
	I3C_DATBAS_DVTYP_0 = 0x0
	// I2C Device
	I3C_DATBAS_DVTYP_1 = 0x1

	// EXDATBAS: Extended Device Address Table Basic Register
	// Position of EDSTAD field.
	I3C_EXDATBAS_EDSTAD_Pos = 0x0
	// Bit mask of EDSTAD field.
	I3C_EXDATBAS_EDSTAD_Msk = 0x7f
	// Position of EDDYAD field.
	I3C_EXDATBAS_EDDYAD_Pos = 0x10
	// Bit mask of EDDYAD field.
	I3C_EXDATBAS_EDDYAD_Msk = 0xff0000
	// Position of EDNACK field.
	I3C_EXDATBAS_EDNACK_Pos = 0x1d
	// Bit mask of EDNACK field.
	I3C_EXDATBAS_EDNACK_Msk = 0x60000000
	// Position of EDTYP field.
	I3C_EXDATBAS_EDTYP_Pos = 0x1f
	// Bit mask of EDTYP field.
	I3C_EXDATBAS_EDTYP_Msk = 0x80000000
	// Bit EDTYP.
	I3C_EXDATBAS_EDTYP = 0x80000000
	// I3C Device
	I3C_EXDATBAS_EDTYP_0 = 0x0
	// I2C Device
	I3C_EXDATBAS_EDTYP_1 = 0x1

	// SDATBAS0: Slave Device Address Table Basic Register 0
	// Position of SDSTAD field.
	I3C_SDATBAS0_SDSTAD_Pos = 0x0
	// Bit mask of SDSTAD field.
	I3C_SDATBAS0_SDSTAD_Msk = 0x3ff
	// Position of SDADLS field.
	I3C_SDATBAS0_SDADLS_Pos = 0xa
	// Bit mask of SDADLS field.
	I3C_SDATBAS0_SDADLS_Msk = 0x400
	// Bit SDADLS.
	I3C_SDATBAS0_SDADLS = 0x400
	// Slave device address length 7 bits selected.
	I3C_SDATBAS0_SDADLS_0 = 0x0
	// Slave device address length 10 bits selected. (I2C device only)
	I3C_SDATBAS0_SDADLS_1 = 0x1
	// Position of SDIBIPL field.
	I3C_SDATBAS0_SDIBIPL_Pos = 0xc
	// Bit mask of SDIBIPL field.
	I3C_SDATBAS0_SDIBIPL_Msk = 0x1000
	// Bit SDIBIPL.
	I3C_SDATBAS0_SDIBIPL = 0x1000
	// IBIs from this device do not carry a data payload.
	I3C_SDATBAS0_SDIBIPL_0 = 0x0
	// IBIs from this device carry a data payload.
	I3C_SDATBAS0_SDIBIPL_1 = 0x1
	// Position of SDDYAD field.
	I3C_SDATBAS0_SDDYAD_Pos = 0x10
	// Bit mask of SDDYAD field.
	I3C_SDATBAS0_SDDYAD_Msk = 0x7f0000

	// SDATBAS1: Slave Device Address Table Basic Register 1
	// Position of SDSTAD field.
	I3C_SDATBAS1_SDSTAD_Pos = 0x0
	// Bit mask of SDSTAD field.
	I3C_SDATBAS1_SDSTAD_Msk = 0x3ff
	// Position of SDADLS field.
	I3C_SDATBAS1_SDADLS_Pos = 0xa
	// Bit mask of SDADLS field.
	I3C_SDATBAS1_SDADLS_Msk = 0x400
	// Bit SDADLS.
	I3C_SDATBAS1_SDADLS = 0x400
	// Slave device address length 7 bits selected.
	I3C_SDATBAS1_SDADLS_0 = 0x0
	// Slave device address length 10 bits selected. (I2C device only)
	I3C_SDATBAS1_SDADLS_1 = 0x1
	// Position of SDIBIPL field.
	I3C_SDATBAS1_SDIBIPL_Pos = 0xc
	// Bit mask of SDIBIPL field.
	I3C_SDATBAS1_SDIBIPL_Msk = 0x1000
	// Bit SDIBIPL.
	I3C_SDATBAS1_SDIBIPL = 0x1000
	// IBIs from this device do not carry a data payload.
	I3C_SDATBAS1_SDIBIPL_0 = 0x0
	// IBIs from this device carry a data payload.
	I3C_SDATBAS1_SDIBIPL_1 = 0x1
	// Position of SDDYAD field.
	I3C_SDATBAS1_SDDYAD_Pos = 0x10
	// Bit mask of SDDYAD field.
	I3C_SDATBAS1_SDDYAD_Msk = 0x7f0000

	// SDATBAS2: Slave Device Address Table Basic Register 2
	// Position of SDSTAD field.
	I3C_SDATBAS2_SDSTAD_Pos = 0x0
	// Bit mask of SDSTAD field.
	I3C_SDATBAS2_SDSTAD_Msk = 0x3ff
	// Position of SDADLS field.
	I3C_SDATBAS2_SDADLS_Pos = 0xa
	// Bit mask of SDADLS field.
	I3C_SDATBAS2_SDADLS_Msk = 0x400
	// Bit SDADLS.
	I3C_SDATBAS2_SDADLS = 0x400
	// Slave device address length 7 bits selected.
	I3C_SDATBAS2_SDADLS_0 = 0x0
	// Slave device address length 10 bits selected. (I2C device only)
	I3C_SDATBAS2_SDADLS_1 = 0x1
	// Position of SDIBIPL field.
	I3C_SDATBAS2_SDIBIPL_Pos = 0xc
	// Bit mask of SDIBIPL field.
	I3C_SDATBAS2_SDIBIPL_Msk = 0x1000
	// Bit SDIBIPL.
	I3C_SDATBAS2_SDIBIPL = 0x1000
	// IBIs from this device do not carry a data payload.
	I3C_SDATBAS2_SDIBIPL_0 = 0x0
	// IBIs from this device carry a data payload.
	I3C_SDATBAS2_SDIBIPL_1 = 0x1
	// Position of SDDYAD field.
	I3C_SDATBAS2_SDDYAD_Pos = 0x10
	// Bit mask of SDDYAD field.
	I3C_SDATBAS2_SDDYAD_Msk = 0x7f0000

	// MSDCT0: Master Device Characteristic Table Register %s
	// Position of RBCR0 field.
	I3C_MSDCT_RBCR0_Pos = 0x8
	// Bit mask of RBCR0 field.
	I3C_MSDCT_RBCR0_Msk = 0x100
	// Bit RBCR0.
	I3C_MSDCT_RBCR0 = 0x100
	// No Limitation
	I3C_MSDCT_RBCR0_0 = 0x0
	// Limitation
	I3C_MSDCT_RBCR0_1 = 0x1
	// Position of RBCR1 field.
	I3C_MSDCT_RBCR1_Pos = 0x9
	// Bit mask of RBCR1 field.
	I3C_MSDCT_RBCR1_Msk = 0x200
	// Bit RBCR1.
	I3C_MSDCT_RBCR1 = 0x200
	// Not Capable
	I3C_MSDCT_RBCR1_0 = 0x0
	// Capable
	I3C_MSDCT_RBCR1_1 = 0x1
	// Position of RBCR2 field.
	I3C_MSDCT_RBCR2_Pos = 0xa
	// Bit mask of RBCR2 field.
	I3C_MSDCT_RBCR2_Msk = 0x400
	// Bit RBCR2.
	I3C_MSDCT_RBCR2 = 0x400
	// No data byte follows the accepted IBI.
	I3C_MSDCT_RBCR2_0 = 0x0
	// Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit.
	I3C_MSDCT_RBCR2_1 = 0x1
	// Position of RBCR3 field.
	I3C_MSDCT_RBCR3_Pos = 0xb
	// Bit mask of RBCR3 field.
	I3C_MSDCT_RBCR3_Msk = 0x800
	// Bit RBCR3.
	I3C_MSDCT_RBCR3 = 0x800
	// Device will always respond to I3C bus commands.
	I3C_MSDCT_RBCR3_0 = 0x0
	// Device will not always respond to I3C bus commands.
	I3C_MSDCT_RBCR3_1 = 0x1
	// Position of RBCR4 field.
	I3C_MSDCT_RBCR4_Pos = 0xc
	// Bit mask of RBCR4 field.
	I3C_MSDCT_RBCR4_Msk = 0x1000
	// Bit RBCR4.
	I3C_MSDCT_RBCR4 = 0x1000
	// Not a Bridge Device
	I3C_MSDCT_RBCR4_0 = 0x0
	// A Bridge Device
	I3C_MSDCT_RBCR4_1 = 0x1
	// Position of RBCR76 field.
	I3C_MSDCT_RBCR76_Pos = 0xe
	// Bit mask of RBCR76 field.
	I3C_MSDCT_RBCR76_Msk = 0xc000
	// I3C Slave
	I3C_MSDCT_RBCR76_00 = 0x0
	// I3C Master
	I3C_MSDCT_RBCR76_01 = 0x1
	// Setting prohibited
	I3C_MSDCT_RBCR76_Others = 0x2

	// SVDCT: Slave Device Characteristic Table Register
	// Position of TDCR field.
	I3C_SVDCT_TDCR_Pos = 0x0
	// Bit mask of TDCR field.
	I3C_SVDCT_TDCR_Msk = 0xff
	// Position of TBCR0 field.
	I3C_SVDCT_TBCR0_Pos = 0x8
	// Bit mask of TBCR0 field.
	I3C_SVDCT_TBCR0_Msk = 0x100
	// Bit TBCR0.
	I3C_SVDCT_TBCR0 = 0x100
	// No Limitation
	I3C_SVDCT_TBCR0_0 = 0x0
	// Limitation
	I3C_SVDCT_TBCR0_1 = 0x1
	// Position of TBCR1 field.
	I3C_SVDCT_TBCR1_Pos = 0x9
	// Bit mask of TBCR1 field.
	I3C_SVDCT_TBCR1_Msk = 0x200
	// Bit TBCR1.
	I3C_SVDCT_TBCR1 = 0x200
	// Not Capable
	I3C_SVDCT_TBCR1_0 = 0x0
	// Capable
	I3C_SVDCT_TBCR1_1 = 0x1
	// Position of TBCR2 field.
	I3C_SVDCT_TBCR2_Pos = 0xa
	// Bit mask of TBCR2 field.
	I3C_SVDCT_TBCR2_Msk = 0x400
	// Bit TBCR2.
	I3C_SVDCT_TBCR2 = 0x400
	// No data byte follows the accepted IBI.
	I3C_SVDCT_TBCR2_0 = 0x0
	// Mandatory one or more data bytes follow the accepted IBI. Data byte continuation is indicated by T-Bit.
	I3C_SVDCT_TBCR2_1 = 0x1
	// Position of TBCR3 field.
	I3C_SVDCT_TBCR3_Pos = 0xb
	// Bit mask of TBCR3 field.
	I3C_SVDCT_TBCR3_Msk = 0x800
	// Bit TBCR3.
	I3C_SVDCT_TBCR3 = 0x800
	// Device will always respond to I3C bus commands.
	I3C_SVDCT_TBCR3_0 = 0x0
	// Device will not always respond to I3C bus commands.
	I3C_SVDCT_TBCR3_1 = 0x1
	// Position of TBCR4 field.
	I3C_SVDCT_TBCR4_Pos = 0xc
	// Bit mask of TBCR4 field.
	I3C_SVDCT_TBCR4_Msk = 0x1000
	// Bit TBCR4.
	I3C_SVDCT_TBCR4 = 0x1000
	// Not a Bridge Device
	I3C_SVDCT_TBCR4_0 = 0x0
	// A Bridge Device
	I3C_SVDCT_TBCR4_1 = 0x1
	// Position of TBCR76 field.
	I3C_SVDCT_TBCR76_Pos = 0xe
	// Bit mask of TBCR76 field.
	I3C_SVDCT_TBCR76_Msk = 0xc000
	// I3C Slave
	I3C_SVDCT_TBCR76_00 = 0x0
	// I3C Master
	I3C_SVDCT_TBCR76_01 = 0x1
	// Setting prohibited
	I3C_SVDCT_TBCR76_Others = 0x2

	// SVDVAD0: Slave Device Address Register %s
	// Position of SVAD field.
	I3C_SVDVAD_SVAD_Pos = 0x10
	// Bit mask of SVAD field.
	I3C_SVDVAD_SVAD_Msk = 0x3ff0000
	// Position of SADLG field.
	I3C_SVDVAD_SADLG_Pos = 0x1b
	// Bit mask of SADLG field.
	I3C_SVDVAD_SADLG_Msk = 0x8000000
	// Bit SADLG.
	I3C_SVDVAD_SADLG = 0x8000000
	// The 7-bit address format is selected.
	I3C_SVDVAD_SADLG_0 = 0x0
	// The 10-bit address format is selected.
	I3C_SVDVAD_SADLG_1 = 0x1
	// Position of SSTADV field.
	I3C_SVDVAD_SSTADV_Pos = 0x1e
	// Bit mask of SSTADV field.
	I3C_SVDVAD_SSTADV_Msk = 0x40000000
	// Bit SSTADV.
	I3C_SVDVAD_SSTADV = 0x40000000
	// Slave address is disabled.
	I3C_SVDVAD_SSTADV_0 = 0x0
	// Slave address is enabled.
	I3C_SVDVAD_SSTADV_1 = 0x1
	// Position of SDYADV field.
	I3C_SVDVAD_SDYADV_Pos = 0x1f
	// Bit mask of SDYADV field.
	I3C_SVDVAD_SDYADV_Msk = 0x80000000
	// Bit SDYADV.
	I3C_SVDVAD_SDYADV = 0x80000000
	// Dynamic Address is disabled.
	I3C_SVDVAD_SDYADV_0 = 0x0
	// Dynamic Address is enabled.
	I3C_SVDVAD_SDYADV_1 = 0x1

	// CSECMD: CCC Slave Events Command Register
	// Position of SVIRQE field.
	I3C_CSECMD_SVIRQE_Pos = 0x0
	// Bit mask of SVIRQE field.
	I3C_CSECMD_SVIRQE_Msk = 0x1
	// Bit SVIRQE.
	I3C_CSECMD_SVIRQE = 0x1
	// DISABLED: Slave-initiated Interrupts is Disabled by the Master to control.
	I3C_CSECMD_SVIRQE_0 = 0x0
	// ENABLED: Slave-initiated Interrupts is Enabled by the Master to control.
	I3C_CSECMD_SVIRQE_1 = 0x1
	// Position of MSRQE field.
	I3C_CSECMD_MSRQE_Pos = 0x1
	// Bit mask of MSRQE field.
	I3C_CSECMD_MSRQE_Msk = 0x2
	// Bit MSRQE.
	I3C_CSECMD_MSRQE = 0x2
	// DISABLED: Mastership requests from Secondary Masters is Disabled by the Current Master to control.
	I3C_CSECMD_MSRQE_0 = 0x0
	// ENABLED: Mastership requests from Secondary Masters is Enabled by the Current Master to control.
	I3C_CSECMD_MSRQE_1 = 0x1

	// CEACTST: CCC Enter Activity State Register
	// Position of ACTST field.
	I3C_CEACTST_ACTST_Pos = 0x0
	// Bit mask of ACTST field.
	I3C_CEACTST_ACTST_Msk = 0xf
	// Setting prohibited
	I3C_CEACTST_ACTST_Others = 0x0
	// ENTAS0 (1µs: Latency-free operation)
	I3C_CEACTST_ACTST_0x1 = 0x1
	// ENTAS1 (100 µs)
	I3C_CEACTST_ACTST_0x2 = 0x2
	// ENTAS2 (2 ms)
	I3C_CEACTST_ACTST_0x4 = 0x4
	// ENTAS3 (50 ms: Lowest-activity operation)
	I3C_CEACTST_ACTST_0x8 = 0x8

	// CMWLG: CCC Max Write Length Register
	// Position of MWLG field.
	I3C_CMWLG_MWLG_Pos = 0x0
	// Bit mask of MWLG field.
	I3C_CMWLG_MWLG_Msk = 0xffff

	// CMRLG: CCC Max Read Length Register
	// Position of MRLG field.
	I3C_CMRLG_MRLG_Pos = 0x0
	// Bit mask of MRLG field.
	I3C_CMRLG_MRLG_Msk = 0xffff
	// Position of IBIPSZ field.
	I3C_CMRLG_IBIPSZ_Pos = 0x10
	// Bit mask of IBIPSZ field.
	I3C_CMRLG_IBIPSZ_Msk = 0xff0000

	// CETSTMD: CCC Enter Test Mode Register
	// Position of TSTMD field.
	I3C_CETSTMD_TSTMD_Pos = 0x0
	// Bit mask of TSTMD field.
	I3C_CETSTMD_TSTMD_Msk = 0xff
	// Exit Test Mode This value removes all I3C devices from Test Mode.
	I3C_CETSTMD_TSTMD_0x00 = 0x0
	// Vendor Test Mode This value indicates that I3C devices shall return a random 32bit value in the provisional ID during the Dynamic Address Assignment procedure.
	I3C_CETSTMD_TSTMD_0x01 = 0x1
	// Setting prohibited
	I3C_CETSTMD_TSTMD_Others = 0x2

	// CGDVST: CCC Get Device Status Register
	// Position of PNDINT field.
	I3C_CGDVST_PNDINT_Pos = 0x0
	// Bit mask of PNDINT field.
	I3C_CGDVST_PNDINT_Msk = 0xf
	// Position of PRTE field.
	I3C_CGDVST_PRTE_Pos = 0x5
	// Bit mask of PRTE field.
	I3C_CGDVST_PRTE_Msk = 0x20
	// Bit PRTE.
	I3C_CGDVST_PRTE = 0x20
	// The Slave has not detected a protocol error since the last Status read.
	I3C_CGDVST_PRTE_0 = 0x0
	// The Slave has detected a protocol error since the last Status read.
	I3C_CGDVST_PRTE_1 = 0x1
	// Position of ACTMD field.
	I3C_CGDVST_ACTMD_Pos = 0x6
	// Bit mask of ACTMD field.
	I3C_CGDVST_ACTMD_Msk = 0xc0
	// Activity Mode 0
	I3C_CGDVST_ACTMD_00 = 0x0
	// Activity Mode 1
	I3C_CGDVST_ACTMD_01 = 0x1
	// Activity Mode 2
	I3C_CGDVST_ACTMD_10 = 0x2
	// Activity Mode 3
	I3C_CGDVST_ACTMD_11 = 0x3
	// Position of VDRSV field.
	I3C_CGDVST_VDRSV_Pos = 0x8
	// Bit mask of VDRSV field.
	I3C_CGDVST_VDRSV_Msk = 0xff00

	// CMDSPW: CCC Max Data Speed W (Write) Register
	// Position of MSWDR field.
	I3C_CMDSPW_MSWDR_Pos = 0x0
	// Bit mask of MSWDR field.
	I3C_CMDSPW_MSWDR_Msk = 0x7
	// fscl Max (default value)
	I3C_CMDSPW_MSWDR_000 = 0x0
	// 8 MHz
	I3C_CMDSPW_MSWDR_001 = 0x1
	// 6 MHz
	I3C_CMDSPW_MSWDR_010 = 0x2
	// 4 MHz
	I3C_CMDSPW_MSWDR_011 = 0x3
	// 2 MHz
	I3C_CMDSPW_MSWDR_100 = 0x4
	// Setting prohibited
	I3C_CMDSPW_MSWDR_Others = 0x5

	// CMDSPR: CCC Max Data Speed R (Read) Register
	// Position of MSRDR field.
	I3C_CMDSPR_MSRDR_Pos = 0x0
	// Bit mask of MSRDR field.
	I3C_CMDSPR_MSRDR_Msk = 0x7
	// fscl Max (default value)
	I3C_CMDSPR_MSRDR_000 = 0x0
	// 8 MHz
	I3C_CMDSPR_MSRDR_001 = 0x1
	// 6 MHz
	I3C_CMDSPR_MSRDR_010 = 0x2
	// 4 MHz
	I3C_CMDSPR_MSRDR_011 = 0x3
	// 2 MHz
	I3C_CMDSPR_MSRDR_100 = 0x4
	// Setting prohibited
	I3C_CMDSPR_MSRDR_Others = 0x5
	// Position of CDTTIM field.
	I3C_CMDSPR_CDTTIM_Pos = 0x3
	// Bit mask of CDTTIM field.
	I3C_CMDSPR_CDTTIM_Msk = 0x38
	// 8 ns or less (default value)
	I3C_CMDSPR_CDTTIM_000 = 0x0
	// 9 ns or less
	I3C_CMDSPR_CDTTIM_001 = 0x1
	// 10 ns or less
	I3C_CMDSPR_CDTTIM_010 = 0x2
	// 11 ns or less
	I3C_CMDSPR_CDTTIM_011 = 0x3
	// 12 ns or less
	I3C_CMDSPR_CDTTIM_100 = 0x4
	// TSCO is more than 12 ns, and is reported by private agreement.
	I3C_CMDSPR_CDTTIM_111 = 0x7
	// Setting prohibited
	I3C_CMDSPR_CDTTIM_Others = 0x5

	// CMDSPT: CCC Max Data Speed T (Turnaround) Register
	// Position of MRTTIM field.
	I3C_CMDSPT_MRTTIM_Pos = 0x0
	// Bit mask of MRTTIM field.
	I3C_CMDSPT_MRTTIM_Msk = 0xffffff
	// Position of MRTE field.
	I3C_CMDSPT_MRTE_Pos = 0x1f
	// Bit mask of MRTE field.
	I3C_CMDSPT_MRTE_Msk = 0x80000000
	// Bit MRTE.
	I3C_CMDSPT_MRTE = 0x80000000
	// Disables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 1: Without Turnaround)
	I3C_CMDSPT_MRTE_0 = 0x0
	// Enables transmission of the Maximum Read Turnaround Time. (GETMXDS Format 2: With Turnaround)
	I3C_CMDSPT_MRTE_1 = 0x1

	// CETSM: CCC Exchange Timing Support Information M (Mode) Register
	// Position of SPTSYN field.
	I3C_CETSM_SPTSYN_Pos = 0x0
	// Bit mask of SPTSYN field.
	I3C_CETSM_SPTSYN_Msk = 0x1
	// Bit SPTSYN.
	I3C_CETSM_SPTSYN = 0x1
	// Sync Mode is not supported.
	I3C_CETSM_SPTSYN_0 = 0x0
	// Sync Mode is supported.
	I3C_CETSM_SPTSYN_1 = 0x1
	// Position of SPTASYN0 field.
	I3C_CETSM_SPTASYN0_Pos = 0x1
	// Bit mask of SPTASYN0 field.
	I3C_CETSM_SPTASYN0_Msk = 0x2
	// Bit SPTASYN0.
	I3C_CETSM_SPTASYN0 = 0x2
	// Async Mode 0 is not supported.
	I3C_CETSM_SPTASYN0_0 = 0x0
	// Async Mode 0 is supported.
	I3C_CETSM_SPTASYN0_1 = 0x1
	// Position of SPTASYN1 field.
	I3C_CETSM_SPTASYN1_Pos = 0x2
	// Bit mask of SPTASYN1 field.
	I3C_CETSM_SPTASYN1_Msk = 0x4
	// Bit SPTASYN1.
	I3C_CETSM_SPTASYN1 = 0x4
	// Async Mode 1 is not supported.
	I3C_CETSM_SPTASYN1_0 = 0x0
	// Async Mode 1 is supported.
	I3C_CETSM_SPTASYN1_1 = 0x1
	// Position of FREQ field.
	I3C_CETSM_FREQ_Pos = 0x8
	// Bit mask of FREQ field.
	I3C_CETSM_FREQ_Msk = 0xff00
	// Position of INAC field.
	I3C_CETSM_INAC_Pos = 0x10
	// Bit mask of INAC field.
	I3C_CETSM_INAC_Msk = 0xff0000

	// CETSS: CCC Exchange Timing Support Information S (State) Register
	// Position of SYNE field.
	I3C_CETSS_SYNE_Pos = 0x0
	// Bit mask of SYNE field.
	I3C_CETSS_SYNE_Msk = 0x1
	// Bit SYNE.
	I3C_CETSS_SYNE = 0x1
	// Sync Mode Disabled
	I3C_CETSS_SYNE_0 = 0x0
	// Sync Mode Enabled
	I3C_CETSS_SYNE_1 = 0x1
	// Position of ASYNE field.
	I3C_CETSS_ASYNE_Pos = 0x1
	// Bit mask of ASYNE field.
	I3C_CETSS_ASYNE_Msk = 0x6
	// All Mode Disable
	I3C_CETSS_ASYNE_00 = 0x0
	// Async Mode 0 Enabled
	I3C_CETSS_ASYNE_01 = 0x1
	// Async Mode 1 Enabled
	I3C_CETSS_ASYNE_10 = 0x2
	// Setting prohibited
	I3C_CETSS_ASYNE_Others = 0x3
	// Position of ICOVF field.
	I3C_CETSS_ICOVF_Pos = 0x7
	// Bit mask of ICOVF field.
	I3C_CETSS_ICOVF_Msk = 0x80
	// Bit ICOVF.
	I3C_CETSS_ICOVF = 0x80
	// Slave has not experienced a counter overflow since the most recent previous check.
	I3C_CETSS_ICOVF_0 = 0x0
	// Slave experienced a counter overflow since the most recent previous check.
	I3C_CETSS_ICOVF_1 = 0x1

	// BITCNT: Bit Count Register
	// Position of BCNT field.
	I3C_BITCNT_BCNT_Pos = 0x0
	// Bit mask of BCNT field.
	I3C_BITCNT_BCNT_Msk = 0x1f

	// NQSTLV: Normal Queue Status Level Register
	// Position of CMDQFLV field.
	I3C_NQSTLV_CMDQFLV_Pos = 0x0
	// Bit mask of CMDQFLV field.
	I3C_NQSTLV_CMDQFLV_Msk = 0xff
	// Position of RSPQLV field.
	I3C_NQSTLV_RSPQLV_Pos = 0x8
	// Bit mask of RSPQLV field.
	I3C_NQSTLV_RSPQLV_Msk = 0xff00
	// Position of IBIQLV field.
	I3C_NQSTLV_IBIQLV_Pos = 0x10
	// Bit mask of IBIQLV field.
	I3C_NQSTLV_IBIQLV_Msk = 0xff0000
	// Position of IBISCNT field.
	I3C_NQSTLV_IBISCNT_Pos = 0x18
	// Bit mask of IBISCNT field.
	I3C_NQSTLV_IBISCNT_Msk = 0x1f000000

	// NDBSTLV0: Normal Data Buffer Status Level Register 0
	// Position of TDBFLV field.
	I3C_NDBSTLV0_TDBFLV_Pos = 0x0
	// Bit mask of TDBFLV field.
	I3C_NDBSTLV0_TDBFLV_Msk = 0xff
	// Position of RDBLV field.
	I3C_NDBSTLV0_RDBLV_Pos = 0x8
	// Bit mask of RDBLV field.
	I3C_NDBSTLV0_RDBLV_Msk = 0xff00

	// NRSQSTLV: Normal Receive Status Queue Status Level Register
	// Position of RSQLV field.
	I3C_NRSQSTLV_RSQLV_Pos = 0x0
	// Bit mask of RSQLV field.
	I3C_NRSQSTLV_RSQLV_Msk = 0xff

	// HQSTLV: High Priority Queue Status Level Register
	// Position of CMDQLV field.
	I3C_HQSTLV_CMDQLV_Pos = 0x0
	// Bit mask of CMDQLV field.
	I3C_HQSTLV_CMDQLV_Msk = 0xff
	// Position of RSPQLV field.
	I3C_HQSTLV_RSPQLV_Pos = 0x8
	// Bit mask of RSPQLV field.
	I3C_HQSTLV_RSPQLV_Msk = 0xff00

	// HDBSTLV: High Priority Data Buffer Status Level Register
	// Position of TDBFLV field.
	I3C_HDBSTLV_TDBFLV_Pos = 0x0
	// Bit mask of TDBFLV field.
	I3C_HDBSTLV_TDBFLV_Msk = 0xff
	// Position of RDBLV field.
	I3C_HDBSTLV_RDBLV_Pos = 0x8
	// Bit mask of RDBLV field.
	I3C_HDBSTLV_RDBLV_Msk = 0xff00

	// PRSTDBG: Present State Debug Register
	// Position of SCILV field.
	I3C_PRSTDBG_SCILV_Pos = 0x0
	// Bit mask of SCILV field.
	I3C_PRSTDBG_SCILV_Msk = 0x1
	// Bit SCILV.
	I3C_PRSTDBG_SCILV = 0x1
	// Position of SDILV field.
	I3C_PRSTDBG_SDILV_Pos = 0x1
	// Bit mask of SDILV field.
	I3C_PRSTDBG_SDILV_Msk = 0x2
	// Bit SDILV.
	I3C_PRSTDBG_SDILV = 0x2
	// Position of SCOLV field.
	I3C_PRSTDBG_SCOLV_Pos = 0x2
	// Bit mask of SCOLV field.
	I3C_PRSTDBG_SCOLV_Msk = 0x4
	// Bit SCOLV.
	I3C_PRSTDBG_SCOLV = 0x4
	// I3C has driven the SCL pin low.
	I3C_PRSTDBG_SCOLV_0 = 0x0
	// I3C has released the SCL pin.
	I3C_PRSTDBG_SCOLV_1 = 0x1
	// Position of SDOLV field.
	I3C_PRSTDBG_SDOLV_Pos = 0x3
	// Bit mask of SDOLV field.
	I3C_PRSTDBG_SDOLV_Msk = 0x8
	// Bit SDOLV.
	I3C_PRSTDBG_SDOLV = 0x8
	// I3C has driven the SDA pin low.
	I3C_PRSTDBG_SDOLV_0 = 0x0
	// I3C has released the SDA pin.
	I3C_PRSTDBG_SDOLV_1 = 0x1

	// MSERRCNT: Master Error Counters Register
	// Position of M2ECNT field.
	I3C_MSERRCNT_M2ECNT_Pos = 0x0
	// Bit mask of M2ECNT field.
	I3C_MSERRCNT_M2ECNT_Msk = 0xff

	// SC1CPT: SC1 Capture monitor Register
	// Position of SC1C field.
	I3C_SC1CPT_SC1C_Pos = 0x0
	// Bit mask of SC1C field.
	I3C_SC1CPT_SC1C_Msk = 0xffff

	// SC2CPT: SC2 Capture monitor Register
	// Position of SC2C field.
	I3C_SC2CPT_SC2C_Pos = 0x0
	// Bit mask of SC2C field.
	I3C_SC2CPT_SC2C_Msk = 0xffff
)

// Constants for ECCMB: ECCMB
const (
	// EC710CTL: ECC Control Register
	// Position of ECEMF field.
	ECCMB_EC710CTL_ECEMF_Pos = 0x0
	// Bit mask of ECEMF field.
	ECCMB_EC710CTL_ECEMF_Msk = 0x1
	// Bit ECEMF.
	ECCMB_EC710CTL_ECEMF = 0x1
	// There is no bit error in present RAM output data
	ECCMB_EC710CTL_ECEMF_0 = 0x0
	// There is bit error in present RAM output data
	ECCMB_EC710CTL_ECEMF_1 = 0x1
	// Position of ECER1F field.
	ECCMB_EC710CTL_ECER1F_Pos = 0x1
	// Bit mask of ECER1F field.
	ECCMB_EC710CTL_ECER1F_Msk = 0x2
	// Bit ECER1F.
	ECCMB_EC710CTL_ECER1F = 0x2
	// After clearing this bit, 1-bit error correction has not occurred
	ECCMB_EC710CTL_ECER1F_0 = 0x0
	// 1-bit error has occurred
	ECCMB_EC710CTL_ECER1F_1 = 0x1
	// Position of ECER2F field.
	ECCMB_EC710CTL_ECER2F_Pos = 0x2
	// Bit mask of ECER2F field.
	ECCMB_EC710CTL_ECER2F_Msk = 0x4
	// Bit ECER2F.
	ECCMB_EC710CTL_ECER2F = 0x4
	// After clearing this bit, 2-bit error has not occurred
	ECCMB_EC710CTL_ECER2F_0 = 0x0
	// 2-bit error has occurred
	ECCMB_EC710CTL_ECER2F_1 = 0x1
	// Position of EC1EDIC field.
	ECCMB_EC710CTL_EC1EDIC_Pos = 0x3
	// Bit mask of EC1EDIC field.
	ECCMB_EC710CTL_EC1EDIC_Msk = 0x8
	// Bit EC1EDIC.
	ECCMB_EC710CTL_EC1EDIC = 0x8
	// Disable 1-bit error detection interrupt request
	ECCMB_EC710CTL_EC1EDIC_0 = 0x0
	// Enable 1-bit error detection interrupt request
	ECCMB_EC710CTL_EC1EDIC_1 = 0x1
	// Position of EC2EDIC field.
	ECCMB_EC710CTL_EC2EDIC_Pos = 0x4
	// Bit mask of EC2EDIC field.
	ECCMB_EC710CTL_EC2EDIC_Msk = 0x10
	// Bit EC2EDIC.
	ECCMB_EC710CTL_EC2EDIC = 0x10
	// Disable 2-bit error detection interrupt request
	ECCMB_EC710CTL_EC2EDIC_0 = 0x0
	// Enable 2-bit error detection interrupt request
	ECCMB_EC710CTL_EC2EDIC_1 = 0x1
	// Position of EC1ECP field.
	ECCMB_EC710CTL_EC1ECP_Pos = 0x5
	// Bit mask of EC1ECP field.
	ECCMB_EC710CTL_EC1ECP_Msk = 0x20
	// Bit EC1ECP.
	ECCMB_EC710CTL_EC1ECP = 0x20
	// At 1-bit error detection, the error correction is executed
	ECCMB_EC710CTL_EC1ECP_0 = 0x0
	// At 1-bit error detection, the error correction is not executed
	ECCMB_EC710CTL_EC1ECP_1 = 0x1
	// Position of ECERVF field.
	ECCMB_EC710CTL_ECERVF_Pos = 0x6
	// Bit mask of ECERVF field.
	ECCMB_EC710CTL_ECERVF_Msk = 0x40
	// Bit ECERVF.
	ECCMB_EC710CTL_ECERVF = 0x40
	// Error judgment disable
	ECCMB_EC710CTL_ECERVF_0 = 0x0
	// Error judgment enable
	ECCMB_EC710CTL_ECERVF_1 = 0x1
	// Position of ECER1C field.
	ECCMB_EC710CTL_ECER1C_Pos = 0x9
	// Bit mask of ECER1C field.
	ECCMB_EC710CTL_ECER1C_Msk = 0x200
	// Bit ECER1C.
	ECCMB_EC710CTL_ECER1C = 0x200
	// No effect
	ECCMB_EC710CTL_ECER1C_0 = 0x0
	// Clear accumulating ECC error detection and correction flag
	ECCMB_EC710CTL_ECER1C_1 = 0x1
	// Position of ECER2C field.
	ECCMB_EC710CTL_ECER2C_Pos = 0xa
	// Bit mask of ECER2C field.
	ECCMB_EC710CTL_ECER2C_Msk = 0x400
	// Bit ECER2C.
	ECCMB_EC710CTL_ECER2C = 0x400
	// No effect
	ECCMB_EC710CTL_ECER2C_0 = 0x0
	// Clear 2-bit ECC error detection flag
	ECCMB_EC710CTL_ECER2C_1 = 0x1
	// Position of ECOVFF field.
	ECCMB_EC710CTL_ECOVFF_Pos = 0xb
	// Bit mask of ECOVFF field.
	ECCMB_EC710CTL_ECOVFF_Msk = 0x800
	// Bit ECOVFF.
	ECCMB_EC710CTL_ECOVFF = 0x800
	// No effect
	ECCMB_EC710CTL_ECOVFF_0 = 0x0
	// ECC overflow detection flag
	ECCMB_EC710CTL_ECOVFF_1 = 0x1
	// Position of EMCA field.
	ECCMB_EC710CTL_EMCA_Pos = 0xe
	// Bit mask of EMCA field.
	ECCMB_EC710CTL_EMCA_Msk = 0xc000
	// Position of ECSEDF0 field.
	ECCMB_EC710CTL_ECSEDF0_Pos = 0x10
	// Bit mask of ECSEDF0 field.
	ECCMB_EC710CTL_ECSEDF0_Msk = 0x10000
	// Bit ECSEDF0.
	ECCMB_EC710CTL_ECSEDF0 = 0x10000
	// There is no bit error in EC710EAD0 after reset or clearing ECER1F bit
	ECCMB_EC710CTL_ECSEDF0_0 = 0x0
	// Address captured in EC710EAD0 shows that 1-bit error occurred and captured
	ECCMB_EC710CTL_ECSEDF0_1 = 0x1
	// Position of ECDEDF0 field.
	ECCMB_EC710CTL_ECDEDF0_Pos = 0x11
	// Bit mask of ECDEDF0 field.
	ECCMB_EC710CTL_ECDEDF0_Msk = 0x20000
	// Bit ECDEDF0.
	ECCMB_EC710CTL_ECDEDF0 = 0x20000
	// There is no bit error in EC710EAD0 after reset or clearing ECER2F bit
	ECCMB_EC710CTL_ECDEDF0_0 = 0x0
	// Address captured in EC710EAD0 shows that 2-bit error occurred and captured
	ECCMB_EC710CTL_ECDEDF0_1 = 0x1

	// EC710TMC: ECC Test Mode Control Register
	// Position of ECDCS field.
	ECCMB_EC710TMC_ECDCS_Pos = 0x1
	// Bit mask of ECDCS field.
	ECCMB_EC710TMC_ECDCS_Msk = 0x2
	// Bit ECDCS.
	ECCMB_EC710TMC_ECDCS = 0x2
	// Input lower 32 bits of RAM output data to data area of decode circuit
	ECCMB_EC710TMC_ECDCS_0 = 0x0
	// Input ECEDB31-0 in EC710TED register to data area of decode circuit
	ECCMB_EC710TMC_ECDCS_1 = 0x1
	// Position of ECTMCE field.
	ECCMB_EC710TMC_ECTMCE_Pos = 0x7
	// Bit mask of ECTMCE field.
	ECCMB_EC710TMC_ECTMCE_Msk = 0x80
	// Bit ECTMCE.
	ECCMB_EC710TMC_ECTMCE = 0x80
	// The access to test mode register and bit is disabled
	ECCMB_EC710TMC_ECTMCE_0 = 0x0
	// The access to test mode register and bit is enabled
	ECCMB_EC710TMC_ECTMCE_1 = 0x1
	// Position of ETMA field.
	ECCMB_EC710TMC_ETMA_Pos = 0xe
	// Bit mask of ETMA field.
	ECCMB_EC710TMC_ETMA_Msk = 0xc000

	// EC710TED: ECC Test Substitute Data Register
	// Position of ECEDB field.
	ECCMB_EC710TED_ECEDB_Pos = 0x0
	// Bit mask of ECEDB field.
	ECCMB_EC710TED_ECEDB_Msk = 0xffffffff

	// EC710EAD0: ECC Error Address Register
	// Position of ECEAD field.
	ECCMB_EC710EAD0_ECEAD_Pos = 0x0
	// Bit mask of ECEAD field.
	ECCMB_EC710EAD0_ECEAD_Msk = 0x7ff
)

// Constants for GPT16E0: General PWM 16-bit Timer 0
const (
	// GTWP: General PWM Timer Write-Protection Register
	// Position of WP field.
	GPT16E0_GTWP_WP_Pos = 0x0
	// Bit mask of WP field.
	GPT16E0_GTWP_WP_Msk = 0x1
	// Bit WP.
	GPT16E0_GTWP_WP = 0x1
	// Write to the register enabled
	GPT16E0_GTWP_WP_0 = 0x0
	// Write to the register disabled
	GPT16E0_GTWP_WP_1 = 0x1
	// Position of STRWP field.
	GPT16E0_GTWP_STRWP_Pos = 0x1
	// Bit mask of STRWP field.
	GPT16E0_GTWP_STRWP_Msk = 0x2
	// Bit STRWP.
	GPT16E0_GTWP_STRWP = 0x2
	// Write to the bit is enabled
	GPT16E0_GTWP_STRWP_0 = 0x0
	// Write to the bit is disabled
	GPT16E0_GTWP_STRWP_1 = 0x1
	// Position of STPWP field.
	GPT16E0_GTWP_STPWP_Pos = 0x2
	// Bit mask of STPWP field.
	GPT16E0_GTWP_STPWP_Msk = 0x4
	// Bit STPWP.
	GPT16E0_GTWP_STPWP = 0x4
	// Write to the bit is enabled
	GPT16E0_GTWP_STPWP_0 = 0x0
	// Write to the bit is disabled
	GPT16E0_GTWP_STPWP_1 = 0x1
	// Position of CLRWP field.
	GPT16E0_GTWP_CLRWP_Pos = 0x3
	// Bit mask of CLRWP field.
	GPT16E0_GTWP_CLRWP_Msk = 0x8
	// Bit CLRWP.
	GPT16E0_GTWP_CLRWP = 0x8
	// Write to the bit is enabled
	GPT16E0_GTWP_CLRWP_0 = 0x0
	// Write to the bit is disabled
	GPT16E0_GTWP_CLRWP_1 = 0x1
	// Position of CMNWP field.
	GPT16E0_GTWP_CMNWP_Pos = 0x4
	// Bit mask of CMNWP field.
	GPT16E0_GTWP_CMNWP_Msk = 0x10
	// Bit CMNWP.
	GPT16E0_GTWP_CMNWP = 0x10
	// Write to the register is enabled
	GPT16E0_GTWP_CMNWP_0 = 0x0
	// Write to the register is disabled
	GPT16E0_GTWP_CMNWP_1 = 0x1
	// Position of PRKEY field.
	GPT16E0_GTWP_PRKEY_Pos = 0x8
	// Bit mask of PRKEY field.
	GPT16E0_GTWP_PRKEY_Msk = 0xff00

	// GTSTR: General PWM Timer Software Start Register
	// Position of CSTRT0 field.
	GPT16E0_GTSTR_CSTRT0_Pos = 0x0
	// Bit mask of CSTRT0 field.
	GPT16E0_GTSTR_CSTRT0_Msk = 0x1
	// Bit CSTRT0.
	GPT16E0_GTSTR_CSTRT0 = 0x1
	// GTCNT counter not start
	GPT16E0_GTSTR_CSTRT0_0 = 0x0
	// GTCNT counter start
	GPT16E0_GTSTR_CSTRT0_1 = 0x1
	// Position of CSTRT1 field.
	GPT16E0_GTSTR_CSTRT1_Pos = 0x1
	// Bit mask of CSTRT1 field.
	GPT16E0_GTSTR_CSTRT1_Msk = 0x2
	// Bit CSTRT1.
	GPT16E0_GTSTR_CSTRT1 = 0x2
	// GTCNT counter not start
	GPT16E0_GTSTR_CSTRT1_0 = 0x0
	// GTCNT counter start
	GPT16E0_GTSTR_CSTRT1_1 = 0x1
	// Position of CSTRT2 field.
	GPT16E0_GTSTR_CSTRT2_Pos = 0x2
	// Bit mask of CSTRT2 field.
	GPT16E0_GTSTR_CSTRT2_Msk = 0x4
	// Bit CSTRT2.
	GPT16E0_GTSTR_CSTRT2 = 0x4
	// GTCNT counter not start
	GPT16E0_GTSTR_CSTRT2_0 = 0x0
	// GTCNT counter start
	GPT16E0_GTSTR_CSTRT2_1 = 0x1
	// Position of CSTRT3 field.
	GPT16E0_GTSTR_CSTRT3_Pos = 0x3
	// Bit mask of CSTRT3 field.
	GPT16E0_GTSTR_CSTRT3_Msk = 0x8
	// Bit CSTRT3.
	GPT16E0_GTSTR_CSTRT3 = 0x8
	// GTCNT counter not start
	GPT16E0_GTSTR_CSTRT3_0 = 0x0
	// GTCNT counter start
	GPT16E0_GTSTR_CSTRT3_1 = 0x1
	// Position of CSTRT4 field.
	GPT16E0_GTSTR_CSTRT4_Pos = 0x4
	// Bit mask of CSTRT4 field.
	GPT16E0_GTSTR_CSTRT4_Msk = 0x10
	// Bit CSTRT4.
	GPT16E0_GTSTR_CSTRT4 = 0x10
	// GTCNT counter not start
	GPT16E0_GTSTR_CSTRT4_0 = 0x0
	// GTCNT counter start
	GPT16E0_GTSTR_CSTRT4_1 = 0x1
	// Position of CSTRT5 field.
	GPT16E0_GTSTR_CSTRT5_Pos = 0x5
	// Bit mask of CSTRT5 field.
	GPT16E0_GTSTR_CSTRT5_Msk = 0x20
	// Bit CSTRT5.
	GPT16E0_GTSTR_CSTRT5 = 0x20
	// GTCNT counter not start
	GPT16E0_GTSTR_CSTRT5_0 = 0x0
	// GTCNT counter start
	GPT16E0_GTSTR_CSTRT5_1 = 0x1

	// GTSTP: General PWM Timer Software Stop Register
	// Position of CSTOP0 field.
	GPT16E0_GTSTP_CSTOP0_Pos = 0x0
	// Bit mask of CSTOP0 field.
	GPT16E0_GTSTP_CSTOP0_Msk = 0x1
	// Bit CSTOP0.
	GPT16E0_GTSTP_CSTOP0 = 0x1
	// GTCNT counter not stop
	GPT16E0_GTSTP_CSTOP0_0 = 0x0
	// GTCNT counter stop
	GPT16E0_GTSTP_CSTOP0_1 = 0x1
	// Position of CSTOP1 field.
	GPT16E0_GTSTP_CSTOP1_Pos = 0x1
	// Bit mask of CSTOP1 field.
	GPT16E0_GTSTP_CSTOP1_Msk = 0x2
	// Bit CSTOP1.
	GPT16E0_GTSTP_CSTOP1 = 0x2
	// GTCNT counter not stop
	GPT16E0_GTSTP_CSTOP1_0 = 0x0
	// GTCNT counter stop
	GPT16E0_GTSTP_CSTOP1_1 = 0x1
	// Position of CSTOP2 field.
	GPT16E0_GTSTP_CSTOP2_Pos = 0x2
	// Bit mask of CSTOP2 field.
	GPT16E0_GTSTP_CSTOP2_Msk = 0x4
	// Bit CSTOP2.
	GPT16E0_GTSTP_CSTOP2 = 0x4
	// GTCNT counter not stop
	GPT16E0_GTSTP_CSTOP2_0 = 0x0
	// GTCNT counter stop
	GPT16E0_GTSTP_CSTOP2_1 = 0x1
	// Position of CSTOP3 field.
	GPT16E0_GTSTP_CSTOP3_Pos = 0x3
	// Bit mask of CSTOP3 field.
	GPT16E0_GTSTP_CSTOP3_Msk = 0x8
	// Bit CSTOP3.
	GPT16E0_GTSTP_CSTOP3 = 0x8
	// GTCNT counter not stop
	GPT16E0_GTSTP_CSTOP3_0 = 0x0
	// GTCNT counter stop
	GPT16E0_GTSTP_CSTOP3_1 = 0x1
	// Position of CSTOP4 field.
	GPT16E0_GTSTP_CSTOP4_Pos = 0x4
	// Bit mask of CSTOP4 field.
	GPT16E0_GTSTP_CSTOP4_Msk = 0x10
	// Bit CSTOP4.
	GPT16E0_GTSTP_CSTOP4 = 0x10
	// GTCNT counter not stop
	GPT16E0_GTSTP_CSTOP4_0 = 0x0
	// GTCNT counter stop
	GPT16E0_GTSTP_CSTOP4_1 = 0x1
	// Position of CSTOP5 field.
	GPT16E0_GTSTP_CSTOP5_Pos = 0x5
	// Bit mask of CSTOP5 field.
	GPT16E0_GTSTP_CSTOP5_Msk = 0x20
	// Bit CSTOP5.
	GPT16E0_GTSTP_CSTOP5 = 0x20
	// GTCNT counter not stop
	GPT16E0_GTSTP_CSTOP5_0 = 0x0
	// GTCNT counter stop
	GPT16E0_GTSTP_CSTOP5_1 = 0x1

	// GTCLR: General PWM Timer Software Clear Register
	// Position of CCLR0 field.
	GPT16E0_GTCLR_CCLR0_Pos = 0x0
	// Bit mask of CCLR0 field.
	GPT16E0_GTCLR_CCLR0_Msk = 0x1
	// Bit CCLR0.
	GPT16E0_GTCLR_CCLR0 = 0x1
	// GTCNT counter is not cleared
	GPT16E0_GTCLR_CCLR0_0 = 0x0
	// GTCNT counter is cleared
	GPT16E0_GTCLR_CCLR0_1 = 0x1
	// Position of CCLR1 field.
	GPT16E0_GTCLR_CCLR1_Pos = 0x1
	// Bit mask of CCLR1 field.
	GPT16E0_GTCLR_CCLR1_Msk = 0x2
	// Bit CCLR1.
	GPT16E0_GTCLR_CCLR1 = 0x2
	// GTCNT counter is not cleared
	GPT16E0_GTCLR_CCLR1_0 = 0x0
	// GTCNT counter is cleared
	GPT16E0_GTCLR_CCLR1_1 = 0x1
	// Position of CCLR2 field.
	GPT16E0_GTCLR_CCLR2_Pos = 0x2
	// Bit mask of CCLR2 field.
	GPT16E0_GTCLR_CCLR2_Msk = 0x4
	// Bit CCLR2.
	GPT16E0_GTCLR_CCLR2 = 0x4
	// GTCNT counter is not cleared
	GPT16E0_GTCLR_CCLR2_0 = 0x0
	// GTCNT counter is cleared
	GPT16E0_GTCLR_CCLR2_1 = 0x1
	// Position of CCLR3 field.
	GPT16E0_GTCLR_CCLR3_Pos = 0x3
	// Bit mask of CCLR3 field.
	GPT16E0_GTCLR_CCLR3_Msk = 0x8
	// Bit CCLR3.
	GPT16E0_GTCLR_CCLR3 = 0x8
	// GTCNT counter is not cleared
	GPT16E0_GTCLR_CCLR3_0 = 0x0
	// GTCNT counter is cleared
	GPT16E0_GTCLR_CCLR3_1 = 0x1
	// Position of CCLR4 field.
	GPT16E0_GTCLR_CCLR4_Pos = 0x4
	// Bit mask of CCLR4 field.
	GPT16E0_GTCLR_CCLR4_Msk = 0x10
	// Bit CCLR4.
	GPT16E0_GTCLR_CCLR4 = 0x10
	// GTCNT counter is not cleared
	GPT16E0_GTCLR_CCLR4_0 = 0x0
	// GTCNT counter is cleared
	GPT16E0_GTCLR_CCLR4_1 = 0x1
	// Position of CCLR5 field.
	GPT16E0_GTCLR_CCLR5_Pos = 0x5
	// Bit mask of CCLR5 field.
	GPT16E0_GTCLR_CCLR5_Msk = 0x20
	// Bit CCLR5.
	GPT16E0_GTCLR_CCLR5 = 0x20
	// GTCNT counter is not cleared
	GPT16E0_GTCLR_CCLR5_0 = 0x0
	// GTCNT counter is cleared
	GPT16E0_GTCLR_CCLR5_1 = 0x1

	// GTSSR: General PWM Timer Start Source Select Register
	// Position of SSGTRGAR field.
	GPT16E0_GTSSR_SSGTRGAR_Pos = 0x0
	// Bit mask of SSGTRGAR field.
	GPT16E0_GTSSR_SSGTRGAR_Msk = 0x1
	// Bit SSGTRGAR.
	GPT16E0_GTSSR_SSGTRGAR = 0x1
	// Counter start disabled on the rising edge of GTETRGA input
	GPT16E0_GTSSR_SSGTRGAR_0 = 0x0
	// Counter start enabled on the rising edge of GTETRGA input
	GPT16E0_GTSSR_SSGTRGAR_1 = 0x1
	// Position of SSGTRGAF field.
	GPT16E0_GTSSR_SSGTRGAF_Pos = 0x1
	// Bit mask of SSGTRGAF field.
	GPT16E0_GTSSR_SSGTRGAF_Msk = 0x2
	// Bit SSGTRGAF.
	GPT16E0_GTSSR_SSGTRGAF = 0x2
	// Counter start disabled on the falling edge of GTETRGA input
	GPT16E0_GTSSR_SSGTRGAF_0 = 0x0
	// Counter start enabled on the falling edge of GTETRGA input
	GPT16E0_GTSSR_SSGTRGAF_1 = 0x1
	// Position of SSGTRGBR field.
	GPT16E0_GTSSR_SSGTRGBR_Pos = 0x2
	// Bit mask of SSGTRGBR field.
	GPT16E0_GTSSR_SSGTRGBR_Msk = 0x4
	// Bit SSGTRGBR.
	GPT16E0_GTSSR_SSGTRGBR = 0x4
	// Counter start disabled on the rising edge of GTETRGB input
	GPT16E0_GTSSR_SSGTRGBR_0 = 0x0
	// Counter start enabled on the rising edge of GTETRGB input
	GPT16E0_GTSSR_SSGTRGBR_1 = 0x1
	// Position of SSGTRGBF field.
	GPT16E0_GTSSR_SSGTRGBF_Pos = 0x3
	// Bit mask of SSGTRGBF field.
	GPT16E0_GTSSR_SSGTRGBF_Msk = 0x8
	// Bit SSGTRGBF.
	GPT16E0_GTSSR_SSGTRGBF = 0x8
	// Counter start disabled on the falling edge of GTETRGB input
	GPT16E0_GTSSR_SSGTRGBF_0 = 0x0
	// Counter start enabled on the falling edge of GTETRGB input
	GPT16E0_GTSSR_SSGTRGBF_1 = 0x1
	// Position of SSGTRGCR field.
	GPT16E0_GTSSR_SSGTRGCR_Pos = 0x4
	// Bit mask of SSGTRGCR field.
	GPT16E0_GTSSR_SSGTRGCR_Msk = 0x10
	// Bit SSGTRGCR.
	GPT16E0_GTSSR_SSGTRGCR = 0x10
	// Counter start disabled on the rising edge of GTETRGC input
	GPT16E0_GTSSR_SSGTRGCR_0 = 0x0
	// Counter start enabled on the rising edge of GTETRGC input
	GPT16E0_GTSSR_SSGTRGCR_1 = 0x1
	// Position of SSGTRGCF field.
	GPT16E0_GTSSR_SSGTRGCF_Pos = 0x5
	// Bit mask of SSGTRGCF field.
	GPT16E0_GTSSR_SSGTRGCF_Msk = 0x20
	// Bit SSGTRGCF.
	GPT16E0_GTSSR_SSGTRGCF = 0x20
	// Counter start disabled on the falling edge of GTETRGC input
	GPT16E0_GTSSR_SSGTRGCF_0 = 0x0
	// Counter start enabled on the falling edge of GTETRGC input
	GPT16E0_GTSSR_SSGTRGCF_1 = 0x1
	// Position of SSGTRGDR field.
	GPT16E0_GTSSR_SSGTRGDR_Pos = 0x6
	// Bit mask of SSGTRGDR field.
	GPT16E0_GTSSR_SSGTRGDR_Msk = 0x40
	// Bit SSGTRGDR.
	GPT16E0_GTSSR_SSGTRGDR = 0x40
	// Counter start disabled on the rising edge of GTETRGD input
	GPT16E0_GTSSR_SSGTRGDR_0 = 0x0
	// Counter start enabled on the rising edge of GTETRGD input
	GPT16E0_GTSSR_SSGTRGDR_1 = 0x1
	// Position of SSGTRGDF field.
	GPT16E0_GTSSR_SSGTRGDF_Pos = 0x7
	// Bit mask of SSGTRGDF field.
	GPT16E0_GTSSR_SSGTRGDF_Msk = 0x80
	// Bit SSGTRGDF.
	GPT16E0_GTSSR_SSGTRGDF = 0x80
	// Counter start disabled on the falling edge of GTETRGD input
	GPT16E0_GTSSR_SSGTRGDF_0 = 0x0
	// Counter start enabled on the falling edge of GTETRGD input
	GPT16E0_GTSSR_SSGTRGDF_1 = 0x1
	// Position of SSCARBL field.
	GPT16E0_GTSSR_SSCARBL_Pos = 0x8
	// Bit mask of SSCARBL field.
	GPT16E0_GTSSR_SSCARBL_Msk = 0x100
	// Bit SSCARBL.
	GPT16E0_GTSSR_SSCARBL = 0x100
	// Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTSSR_SSCARBL_0 = 0x0
	// Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTSSR_SSCARBL_1 = 0x1
	// Position of SSCARBH field.
	GPT16E0_GTSSR_SSCARBH_Pos = 0x9
	// Bit mask of SSCARBH field.
	GPT16E0_GTSSR_SSCARBH_Msk = 0x200
	// Bit SSCARBH.
	GPT16E0_GTSSR_SSCARBH = 0x200
	// Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTSSR_SSCARBH_0 = 0x0
	// Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTSSR_SSCARBH_1 = 0x1
	// Position of SSCAFBL field.
	GPT16E0_GTSSR_SSCAFBL_Pos = 0xa
	// Bit mask of SSCAFBL field.
	GPT16E0_GTSSR_SSCAFBL_Msk = 0x400
	// Bit SSCAFBL.
	GPT16E0_GTSSR_SSCAFBL = 0x400
	// Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTSSR_SSCAFBL_0 = 0x0
	// Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTSSR_SSCAFBL_1 = 0x1
	// Position of SSCAFBH field.
	GPT16E0_GTSSR_SSCAFBH_Pos = 0xb
	// Bit mask of SSCAFBH field.
	GPT16E0_GTSSR_SSCAFBH_Msk = 0x800
	// Bit SSCAFBH.
	GPT16E0_GTSSR_SSCAFBH = 0x800
	// Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTSSR_SSCAFBH_0 = 0x0
	// Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTSSR_SSCAFBH_1 = 0x1
	// Position of SSCBRAL field.
	GPT16E0_GTSSR_SSCBRAL_Pos = 0xc
	// Bit mask of SSCBRAL field.
	GPT16E0_GTSSR_SSCBRAL_Msk = 0x1000
	// Bit SSCBRAL.
	GPT16E0_GTSSR_SSCBRAL = 0x1000
	// Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTSSR_SSCBRAL_0 = 0x0
	// Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTSSR_SSCBRAL_1 = 0x1
	// Position of SSCBRAH field.
	GPT16E0_GTSSR_SSCBRAH_Pos = 0xd
	// Bit mask of SSCBRAH field.
	GPT16E0_GTSSR_SSCBRAH_Msk = 0x2000
	// Bit SSCBRAH.
	GPT16E0_GTSSR_SSCBRAH = 0x2000
	// Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTSSR_SSCBRAH_0 = 0x0
	// Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTSSR_SSCBRAH_1 = 0x1
	// Position of SSCBFAL field.
	GPT16E0_GTSSR_SSCBFAL_Pos = 0xe
	// Bit mask of SSCBFAL field.
	GPT16E0_GTSSR_SSCBFAL_Msk = 0x4000
	// Bit SSCBFAL.
	GPT16E0_GTSSR_SSCBFAL = 0x4000
	// Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTSSR_SSCBFAL_0 = 0x0
	// Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTSSR_SSCBFAL_1 = 0x1
	// Position of SSCBFAH field.
	GPT16E0_GTSSR_SSCBFAH_Pos = 0xf
	// Bit mask of SSCBFAH field.
	GPT16E0_GTSSR_SSCBFAH_Msk = 0x8000
	// Bit SSCBFAH.
	GPT16E0_GTSSR_SSCBFAH = 0x8000
	// Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTSSR_SSCBFAH_0 = 0x0
	// Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTSSR_SSCBFAH_1 = 0x1
	// Position of SSELCA field.
	GPT16E0_GTSSR_SSELCA_Pos = 0x10
	// Bit mask of SSELCA field.
	GPT16E0_GTSSR_SSELCA_Msk = 0x10000
	// Bit SSELCA.
	GPT16E0_GTSSR_SSELCA = 0x10000
	// Counter start disabled at the ELC_GPTA input
	GPT16E0_GTSSR_SSELCA_0 = 0x0
	// Counter start enabled at the ELC_GPTA input
	GPT16E0_GTSSR_SSELCA_1 = 0x1
	// Position of SSELCB field.
	GPT16E0_GTSSR_SSELCB_Pos = 0x11
	// Bit mask of SSELCB field.
	GPT16E0_GTSSR_SSELCB_Msk = 0x20000
	// Bit SSELCB.
	GPT16E0_GTSSR_SSELCB = 0x20000
	// Counter start disabled at the ELC_GPTB input
	GPT16E0_GTSSR_SSELCB_0 = 0x0
	// Counter start enabled at the ELC_GPTB input
	GPT16E0_GTSSR_SSELCB_1 = 0x1
	// Position of SSELCC field.
	GPT16E0_GTSSR_SSELCC_Pos = 0x12
	// Bit mask of SSELCC field.
	GPT16E0_GTSSR_SSELCC_Msk = 0x40000
	// Bit SSELCC.
	GPT16E0_GTSSR_SSELCC = 0x40000
	// Counter start disabled at the ELC_GPTC input
	GPT16E0_GTSSR_SSELCC_0 = 0x0
	// Counter start enabled at the ELC_GPTC input
	GPT16E0_GTSSR_SSELCC_1 = 0x1
	// Position of SSELCD field.
	GPT16E0_GTSSR_SSELCD_Pos = 0x13
	// Bit mask of SSELCD field.
	GPT16E0_GTSSR_SSELCD_Msk = 0x80000
	// Bit SSELCD.
	GPT16E0_GTSSR_SSELCD = 0x80000
	// Counter start disabled at the ELC_GPTD input
	GPT16E0_GTSSR_SSELCD_0 = 0x0
	// Counter start enabled at the ELC_GPTD input
	GPT16E0_GTSSR_SSELCD_1 = 0x1
	// Position of SSELCE field.
	GPT16E0_GTSSR_SSELCE_Pos = 0x14
	// Bit mask of SSELCE field.
	GPT16E0_GTSSR_SSELCE_Msk = 0x100000
	// Bit SSELCE.
	GPT16E0_GTSSR_SSELCE = 0x100000
	// Counter start disabled at the ELC_GPTE input
	GPT16E0_GTSSR_SSELCE_0 = 0x0
	// Counter start enabled at the ELC_GPTE input
	GPT16E0_GTSSR_SSELCE_1 = 0x1
	// Position of SSELCF field.
	GPT16E0_GTSSR_SSELCF_Pos = 0x15
	// Bit mask of SSELCF field.
	GPT16E0_GTSSR_SSELCF_Msk = 0x200000
	// Bit SSELCF.
	GPT16E0_GTSSR_SSELCF = 0x200000
	// Counter start disabled at the ELC_GPTF input
	GPT16E0_GTSSR_SSELCF_0 = 0x0
	// Counter start enabled at the ELC_GPTF input
	GPT16E0_GTSSR_SSELCF_1 = 0x1
	// Position of SSELCG field.
	GPT16E0_GTSSR_SSELCG_Pos = 0x16
	// Bit mask of SSELCG field.
	GPT16E0_GTSSR_SSELCG_Msk = 0x400000
	// Bit SSELCG.
	GPT16E0_GTSSR_SSELCG = 0x400000
	// Counter start disabled at the ELC_GPTG input
	GPT16E0_GTSSR_SSELCG_0 = 0x0
	// Counter start enabled at the ELC_GPTG input
	GPT16E0_GTSSR_SSELCG_1 = 0x1
	// Position of SSELCH field.
	GPT16E0_GTSSR_SSELCH_Pos = 0x17
	// Bit mask of SSELCH field.
	GPT16E0_GTSSR_SSELCH_Msk = 0x800000
	// Bit SSELCH.
	GPT16E0_GTSSR_SSELCH = 0x800000
	// Counter start disabled at the ELC_GPTH input
	GPT16E0_GTSSR_SSELCH_0 = 0x0
	// Counter start enabled at the ELC_GPTH input
	GPT16E0_GTSSR_SSELCH_1 = 0x1
	// Position of CSTRT field.
	GPT16E0_GTSSR_CSTRT_Pos = 0x1f
	// Bit mask of CSTRT field.
	GPT16E0_GTSSR_CSTRT_Msk = 0x80000000
	// Bit CSTRT.
	GPT16E0_GTSSR_CSTRT = 0x80000000
	// Counter start disabled by the GTSTR register
	GPT16E0_GTSSR_CSTRT_0 = 0x0
	// Counter start enabled by the GTSTR register
	GPT16E0_GTSSR_CSTRT_1 = 0x1

	// GTPSR: General PWM Timer Stop Source Select Register
	// Position of PSGTRGAR field.
	GPT16E0_GTPSR_PSGTRGAR_Pos = 0x0
	// Bit mask of PSGTRGAR field.
	GPT16E0_GTPSR_PSGTRGAR_Msk = 0x1
	// Bit PSGTRGAR.
	GPT16E0_GTPSR_PSGTRGAR = 0x1
	// Counter stop disabled on the rising edge of GTETRGA input
	GPT16E0_GTPSR_PSGTRGAR_0 = 0x0
	// Counter stop enabled on the rising edge of GTETRGA input
	GPT16E0_GTPSR_PSGTRGAR_1 = 0x1
	// Position of PSGTRGAF field.
	GPT16E0_GTPSR_PSGTRGAF_Pos = 0x1
	// Bit mask of PSGTRGAF field.
	GPT16E0_GTPSR_PSGTRGAF_Msk = 0x2
	// Bit PSGTRGAF.
	GPT16E0_GTPSR_PSGTRGAF = 0x2
	// Counter stop disabled on the falling edge of GTETRGA input
	GPT16E0_GTPSR_PSGTRGAF_0 = 0x0
	// Counter stop enabled on the falling edge of GTETRGA input
	GPT16E0_GTPSR_PSGTRGAF_1 = 0x1
	// Position of PSGTRGBR field.
	GPT16E0_GTPSR_PSGTRGBR_Pos = 0x2
	// Bit mask of PSGTRGBR field.
	GPT16E0_GTPSR_PSGTRGBR_Msk = 0x4
	// Bit PSGTRGBR.
	GPT16E0_GTPSR_PSGTRGBR = 0x4
	// Counter stop disabled on the rising edge of GTETRGB input
	GPT16E0_GTPSR_PSGTRGBR_0 = 0x0
	// Counter stop enabled on the rising edge of GTETRGB input
	GPT16E0_GTPSR_PSGTRGBR_1 = 0x1
	// Position of PSGTRGBF field.
	GPT16E0_GTPSR_PSGTRGBF_Pos = 0x3
	// Bit mask of PSGTRGBF field.
	GPT16E0_GTPSR_PSGTRGBF_Msk = 0x8
	// Bit PSGTRGBF.
	GPT16E0_GTPSR_PSGTRGBF = 0x8
	// Counter stop disabled on the falling edge of GTETRGB input
	GPT16E0_GTPSR_PSGTRGBF_0 = 0x0
	// Counter stop enabled on the falling edge of GTETRGB input
	GPT16E0_GTPSR_PSGTRGBF_1 = 0x1
	// Position of PSGTRGCR field.
	GPT16E0_GTPSR_PSGTRGCR_Pos = 0x4
	// Bit mask of PSGTRGCR field.
	GPT16E0_GTPSR_PSGTRGCR_Msk = 0x10
	// Bit PSGTRGCR.
	GPT16E0_GTPSR_PSGTRGCR = 0x10
	// Counter stop disabled on the rising edge of GTETRGC input
	GPT16E0_GTPSR_PSGTRGCR_0 = 0x0
	// Counter stop enabled on the rising edge of GTETRGC input
	GPT16E0_GTPSR_PSGTRGCR_1 = 0x1
	// Position of PSGTRGCF field.
	GPT16E0_GTPSR_PSGTRGCF_Pos = 0x5
	// Bit mask of PSGTRGCF field.
	GPT16E0_GTPSR_PSGTRGCF_Msk = 0x20
	// Bit PSGTRGCF.
	GPT16E0_GTPSR_PSGTRGCF = 0x20
	// Counter stop disabled on the falling edge of GTETRGC input
	GPT16E0_GTPSR_PSGTRGCF_0 = 0x0
	// Counter stop enabled on the falling edge of GTETRGC input
	GPT16E0_GTPSR_PSGTRGCF_1 = 0x1
	// Position of PSGTRGDR field.
	GPT16E0_GTPSR_PSGTRGDR_Pos = 0x6
	// Bit mask of PSGTRGDR field.
	GPT16E0_GTPSR_PSGTRGDR_Msk = 0x40
	// Bit PSGTRGDR.
	GPT16E0_GTPSR_PSGTRGDR = 0x40
	// Counter stop disabled on the rising edge of GTETRGD input
	GPT16E0_GTPSR_PSGTRGDR_0 = 0x0
	// Counter stop enabled on the rising edge of GTETRGD input
	GPT16E0_GTPSR_PSGTRGDR_1 = 0x1
	// Position of PSGTRGDF field.
	GPT16E0_GTPSR_PSGTRGDF_Pos = 0x7
	// Bit mask of PSGTRGDF field.
	GPT16E0_GTPSR_PSGTRGDF_Msk = 0x80
	// Bit PSGTRGDF.
	GPT16E0_GTPSR_PSGTRGDF = 0x80
	// Counter stop disabled on the falling edge of GTETRGD input
	GPT16E0_GTPSR_PSGTRGDF_0 = 0x0
	// Counter stop enabled on the falling edge of GTETRGD input
	GPT16E0_GTPSR_PSGTRGDF_1 = 0x1
	// Position of PSCARBL field.
	GPT16E0_GTPSR_PSCARBL_Pos = 0x8
	// Bit mask of PSCARBL field.
	GPT16E0_GTPSR_PSCARBL_Msk = 0x100
	// Bit PSCARBL.
	GPT16E0_GTPSR_PSCARBL = 0x100
	// Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTPSR_PSCARBL_0 = 0x0
	// Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTPSR_PSCARBL_1 = 0x1
	// Position of PSCARBH field.
	GPT16E0_GTPSR_PSCARBH_Pos = 0x9
	// Bit mask of PSCARBH field.
	GPT16E0_GTPSR_PSCARBH_Msk = 0x200
	// Bit PSCARBH.
	GPT16E0_GTPSR_PSCARBH = 0x200
	// Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTPSR_PSCARBH_0 = 0x0
	// Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTPSR_PSCARBH_1 = 0x1
	// Position of PSCAFBL field.
	GPT16E0_GTPSR_PSCAFBL_Pos = 0xa
	// Bit mask of PSCAFBL field.
	GPT16E0_GTPSR_PSCAFBL_Msk = 0x400
	// Bit PSCAFBL.
	GPT16E0_GTPSR_PSCAFBL = 0x400
	// Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTPSR_PSCAFBL_0 = 0x0
	// Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTPSR_PSCAFBL_1 = 0x1
	// Position of PSCAFBH field.
	GPT16E0_GTPSR_PSCAFBH_Pos = 0xb
	// Bit mask of PSCAFBH field.
	GPT16E0_GTPSR_PSCAFBH_Msk = 0x800
	// Bit PSCAFBH.
	GPT16E0_GTPSR_PSCAFBH = 0x800
	// Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTPSR_PSCAFBH_0 = 0x0
	// Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTPSR_PSCAFBH_1 = 0x1
	// Position of PSCBRAL field.
	GPT16E0_GTPSR_PSCBRAL_Pos = 0xc
	// Bit mask of PSCBRAL field.
	GPT16E0_GTPSR_PSCBRAL_Msk = 0x1000
	// Bit PSCBRAL.
	GPT16E0_GTPSR_PSCBRAL = 0x1000
	// Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTPSR_PSCBRAL_0 = 0x0
	// Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTPSR_PSCBRAL_1 = 0x1
	// Position of PSCBRAH field.
	GPT16E0_GTPSR_PSCBRAH_Pos = 0xd
	// Bit mask of PSCBRAH field.
	GPT16E0_GTPSR_PSCBRAH_Msk = 0x2000
	// Bit PSCBRAH.
	GPT16E0_GTPSR_PSCBRAH = 0x2000
	// Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTPSR_PSCBRAH_0 = 0x0
	// Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTPSR_PSCBRAH_1 = 0x1
	// Position of PSCBFAL field.
	GPT16E0_GTPSR_PSCBFAL_Pos = 0xe
	// Bit mask of PSCBFAL field.
	GPT16E0_GTPSR_PSCBFAL_Msk = 0x4000
	// Bit PSCBFAL.
	GPT16E0_GTPSR_PSCBFAL = 0x4000
	// Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTPSR_PSCBFAL_0 = 0x0
	// Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTPSR_PSCBFAL_1 = 0x1
	// Position of PSCBFAH field.
	GPT16E0_GTPSR_PSCBFAH_Pos = 0xf
	// Bit mask of PSCBFAH field.
	GPT16E0_GTPSR_PSCBFAH_Msk = 0x8000
	// Bit PSCBFAH.
	GPT16E0_GTPSR_PSCBFAH = 0x8000
	// Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTPSR_PSCBFAH_0 = 0x0
	// Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTPSR_PSCBFAH_1 = 0x1
	// Position of PSELCA field.
	GPT16E0_GTPSR_PSELCA_Pos = 0x10
	// Bit mask of PSELCA field.
	GPT16E0_GTPSR_PSELCA_Msk = 0x10000
	// Bit PSELCA.
	GPT16E0_GTPSR_PSELCA = 0x10000
	// Counter stop disabled at the ELC_GPTA input
	GPT16E0_GTPSR_PSELCA_0 = 0x0
	// Counter stop enabled at the ELC_GPTA input
	GPT16E0_GTPSR_PSELCA_1 = 0x1
	// Position of PSELCB field.
	GPT16E0_GTPSR_PSELCB_Pos = 0x11
	// Bit mask of PSELCB field.
	GPT16E0_GTPSR_PSELCB_Msk = 0x20000
	// Bit PSELCB.
	GPT16E0_GTPSR_PSELCB = 0x20000
	// Counter stop disabled at the ELC_GPTB input
	GPT16E0_GTPSR_PSELCB_0 = 0x0
	// Counter stop enabled at the ELC_GPTB input
	GPT16E0_GTPSR_PSELCB_1 = 0x1
	// Position of PSELCC field.
	GPT16E0_GTPSR_PSELCC_Pos = 0x12
	// Bit mask of PSELCC field.
	GPT16E0_GTPSR_PSELCC_Msk = 0x40000
	// Bit PSELCC.
	GPT16E0_GTPSR_PSELCC = 0x40000
	// Counter stop disabled at the ELC_GPTC input
	GPT16E0_GTPSR_PSELCC_0 = 0x0
	// Counter stop enabled at the ELC_GPTC input
	GPT16E0_GTPSR_PSELCC_1 = 0x1
	// Position of PSELCD field.
	GPT16E0_GTPSR_PSELCD_Pos = 0x13
	// Bit mask of PSELCD field.
	GPT16E0_GTPSR_PSELCD_Msk = 0x80000
	// Bit PSELCD.
	GPT16E0_GTPSR_PSELCD = 0x80000
	// Counter stop disabled at the ELC_GPTD input
	GPT16E0_GTPSR_PSELCD_0 = 0x0
	// Counter stop enabled at the ELC_GPTD input
	GPT16E0_GTPSR_PSELCD_1 = 0x1
	// Position of PSELCE field.
	GPT16E0_GTPSR_PSELCE_Pos = 0x14
	// Bit mask of PSELCE field.
	GPT16E0_GTPSR_PSELCE_Msk = 0x100000
	// Bit PSELCE.
	GPT16E0_GTPSR_PSELCE = 0x100000
	// Counter stop disabled at the ELC_GPTE input
	GPT16E0_GTPSR_PSELCE_0 = 0x0
	// Counter stop enabled at the ELC_GPTE input
	GPT16E0_GTPSR_PSELCE_1 = 0x1
	// Position of PSELCF field.
	GPT16E0_GTPSR_PSELCF_Pos = 0x15
	// Bit mask of PSELCF field.
	GPT16E0_GTPSR_PSELCF_Msk = 0x200000
	// Bit PSELCF.
	GPT16E0_GTPSR_PSELCF = 0x200000
	// Counter stop disabled at the ELC_GPTF input
	GPT16E0_GTPSR_PSELCF_0 = 0x0
	// Counter stop enabled at the ELC_GPTF input
	GPT16E0_GTPSR_PSELCF_1 = 0x1
	// Position of PSELCG field.
	GPT16E0_GTPSR_PSELCG_Pos = 0x16
	// Bit mask of PSELCG field.
	GPT16E0_GTPSR_PSELCG_Msk = 0x400000
	// Bit PSELCG.
	GPT16E0_GTPSR_PSELCG = 0x400000
	// Counter stop disabled at the ELC_GPTG input
	GPT16E0_GTPSR_PSELCG_0 = 0x0
	// Counter stop enabled at the ELC_GPTG input
	GPT16E0_GTPSR_PSELCG_1 = 0x1
	// Position of PSELCH field.
	GPT16E0_GTPSR_PSELCH_Pos = 0x17
	// Bit mask of PSELCH field.
	GPT16E0_GTPSR_PSELCH_Msk = 0x800000
	// Bit PSELCH.
	GPT16E0_GTPSR_PSELCH = 0x800000
	// Counter stop disabled at the ELC_GPTH input
	GPT16E0_GTPSR_PSELCH_0 = 0x0
	// Counter stop enabled at the ELC_GPTH input
	GPT16E0_GTPSR_PSELCH_1 = 0x1
	// Position of CSTOP field.
	GPT16E0_GTPSR_CSTOP_Pos = 0x1f
	// Bit mask of CSTOP field.
	GPT16E0_GTPSR_CSTOP_Msk = 0x80000000
	// Bit CSTOP.
	GPT16E0_GTPSR_CSTOP = 0x80000000
	// Counter stop disabled by the GTSTP register
	GPT16E0_GTPSR_CSTOP_0 = 0x0
	// Counter stop enabled by the GTSTP register
	GPT16E0_GTPSR_CSTOP_1 = 0x1

	// GTCSR: General PWM Timer Clear Source Select Register
	// Position of CSGTRGAR field.
	GPT16E0_GTCSR_CSGTRGAR_Pos = 0x0
	// Bit mask of CSGTRGAR field.
	GPT16E0_GTCSR_CSGTRGAR_Msk = 0x1
	// Bit CSGTRGAR.
	GPT16E0_GTCSR_CSGTRGAR = 0x1
	// Counter clear disabled on the rising edge of GTETRGA input
	GPT16E0_GTCSR_CSGTRGAR_0 = 0x0
	// Counter clear enabled on the rising edge of GTETRGA input
	GPT16E0_GTCSR_CSGTRGAR_1 = 0x1
	// Position of CSGTRGAF field.
	GPT16E0_GTCSR_CSGTRGAF_Pos = 0x1
	// Bit mask of CSGTRGAF field.
	GPT16E0_GTCSR_CSGTRGAF_Msk = 0x2
	// Bit CSGTRGAF.
	GPT16E0_GTCSR_CSGTRGAF = 0x2
	// Counter clear disabled on the falling edge of GTETRGA input
	GPT16E0_GTCSR_CSGTRGAF_0 = 0x0
	// Counter clear enabled on the falling edge of GTETRGA input
	GPT16E0_GTCSR_CSGTRGAF_1 = 0x1
	// Position of CSGTRGBR field.
	GPT16E0_GTCSR_CSGTRGBR_Pos = 0x2
	// Bit mask of CSGTRGBR field.
	GPT16E0_GTCSR_CSGTRGBR_Msk = 0x4
	// Bit CSGTRGBR.
	GPT16E0_GTCSR_CSGTRGBR = 0x4
	// Disable counter clear on the rising edge of GTETRGB input
	GPT16E0_GTCSR_CSGTRGBR_0 = 0x0
	// Enable counter clear on the rising edge of GTETRGB input
	GPT16E0_GTCSR_CSGTRGBR_1 = 0x1
	// Position of CSGTRGBF field.
	GPT16E0_GTCSR_CSGTRGBF_Pos = 0x3
	// Bit mask of CSGTRGBF field.
	GPT16E0_GTCSR_CSGTRGBF_Msk = 0x8
	// Bit CSGTRGBF.
	GPT16E0_GTCSR_CSGTRGBF = 0x8
	// Counter clear disabled on the falling edge of GTETRGB input
	GPT16E0_GTCSR_CSGTRGBF_0 = 0x0
	// Counter clear enabled on the falling edge of GTETRGB input
	GPT16E0_GTCSR_CSGTRGBF_1 = 0x1
	// Position of CSGTRGCR field.
	GPT16E0_GTCSR_CSGTRGCR_Pos = 0x4
	// Bit mask of CSGTRGCR field.
	GPT16E0_GTCSR_CSGTRGCR_Msk = 0x10
	// Bit CSGTRGCR.
	GPT16E0_GTCSR_CSGTRGCR = 0x10
	// Disable counter clear on the rising edge of GTETRGC input
	GPT16E0_GTCSR_CSGTRGCR_0 = 0x0
	// Enable counter clear on the rising edge of GTETRGC input
	GPT16E0_GTCSR_CSGTRGCR_1 = 0x1
	// Position of CSGTRGCF field.
	GPT16E0_GTCSR_CSGTRGCF_Pos = 0x5
	// Bit mask of CSGTRGCF field.
	GPT16E0_GTCSR_CSGTRGCF_Msk = 0x20
	// Bit CSGTRGCF.
	GPT16E0_GTCSR_CSGTRGCF = 0x20
	// Counter clear disabled on the falling edge of GTETRGC input
	GPT16E0_GTCSR_CSGTRGCF_0 = 0x0
	// Counter clear enabled on the falling edge of GTETRGC input
	GPT16E0_GTCSR_CSGTRGCF_1 = 0x1
	// Position of CSGTRGDR field.
	GPT16E0_GTCSR_CSGTRGDR_Pos = 0x6
	// Bit mask of CSGTRGDR field.
	GPT16E0_GTCSR_CSGTRGDR_Msk = 0x40
	// Bit CSGTRGDR.
	GPT16E0_GTCSR_CSGTRGDR = 0x40
	// Disable counter clear on the rising edge of GTETRGD input
	GPT16E0_GTCSR_CSGTRGDR_0 = 0x0
	// Enable counter clear on the rising edge of GTETRGD input
	GPT16E0_GTCSR_CSGTRGDR_1 = 0x1
	// Position of CSGTRGDF field.
	GPT16E0_GTCSR_CSGTRGDF_Pos = 0x7
	// Bit mask of CSGTRGDF field.
	GPT16E0_GTCSR_CSGTRGDF_Msk = 0x80
	// Bit CSGTRGDF.
	GPT16E0_GTCSR_CSGTRGDF = 0x80
	// Counter clear disabled on the falling edge of GTETRGD input
	GPT16E0_GTCSR_CSGTRGDF_0 = 0x0
	// Counter clear enabled on the falling edge of GTETRGD input
	GPT16E0_GTCSR_CSGTRGDF_1 = 0x1
	// Position of CSCARBL field.
	GPT16E0_GTCSR_CSCARBL_Pos = 0x8
	// Bit mask of CSCARBL field.
	GPT16E0_GTCSR_CSCARBL_Msk = 0x100
	// Bit CSCARBL.
	GPT16E0_GTCSR_CSCARBL = 0x100
	// Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTCSR_CSCARBL_0 = 0x0
	// Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTCSR_CSCARBL_1 = 0x1
	// Position of CSCARBH field.
	GPT16E0_GTCSR_CSCARBH_Pos = 0x9
	// Bit mask of CSCARBH field.
	GPT16E0_GTCSR_CSCARBH_Msk = 0x200
	// Bit CSCARBH.
	GPT16E0_GTCSR_CSCARBH = 0x200
	// Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTCSR_CSCARBH_0 = 0x0
	// Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTCSR_CSCARBH_1 = 0x1
	// Position of CSCAFBL field.
	GPT16E0_GTCSR_CSCAFBL_Pos = 0xa
	// Bit mask of CSCAFBL field.
	GPT16E0_GTCSR_CSCAFBL_Msk = 0x400
	// Bit CSCAFBL.
	GPT16E0_GTCSR_CSCAFBL = 0x400
	// Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTCSR_CSCAFBL_0 = 0x0
	// Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTCSR_CSCAFBL_1 = 0x1
	// Position of CSCAFBH field.
	GPT16E0_GTCSR_CSCAFBH_Pos = 0xb
	// Bit mask of CSCAFBH field.
	GPT16E0_GTCSR_CSCAFBH_Msk = 0x800
	// Bit CSCAFBH.
	GPT16E0_GTCSR_CSCAFBH = 0x800
	// Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTCSR_CSCAFBH_0 = 0x0
	// Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTCSR_CSCAFBH_1 = 0x1
	// Position of CSCBRAL field.
	GPT16E0_GTCSR_CSCBRAL_Pos = 0xc
	// Bit mask of CSCBRAL field.
	GPT16E0_GTCSR_CSCBRAL_Msk = 0x1000
	// Bit CSCBRAL.
	GPT16E0_GTCSR_CSCBRAL = 0x1000
	// Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTCSR_CSCBRAL_0 = 0x0
	// Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTCSR_CSCBRAL_1 = 0x1
	// Position of CSCBRAH field.
	GPT16E0_GTCSR_CSCBRAH_Pos = 0xd
	// Bit mask of CSCBRAH field.
	GPT16E0_GTCSR_CSCBRAH_Msk = 0x2000
	// Bit CSCBRAH.
	GPT16E0_GTCSR_CSCBRAH = 0x2000
	// Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTCSR_CSCBRAH_0 = 0x0
	// Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTCSR_CSCBRAH_1 = 0x1
	// Position of CSCBFAL field.
	GPT16E0_GTCSR_CSCBFAL_Pos = 0xe
	// Bit mask of CSCBFAL field.
	GPT16E0_GTCSR_CSCBFAL_Msk = 0x4000
	// Bit CSCBFAL.
	GPT16E0_GTCSR_CSCBFAL = 0x4000
	// Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTCSR_CSCBFAL_0 = 0x0
	// Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTCSR_CSCBFAL_1 = 0x1
	// Position of CSCBFAH field.
	GPT16E0_GTCSR_CSCBFAH_Pos = 0xf
	// Bit mask of CSCBFAH field.
	GPT16E0_GTCSR_CSCBFAH_Msk = 0x8000
	// Bit CSCBFAH.
	GPT16E0_GTCSR_CSCBFAH = 0x8000
	// Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTCSR_CSCBFAH_0 = 0x0
	// Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTCSR_CSCBFAH_1 = 0x1
	// Position of CSELCA field.
	GPT16E0_GTCSR_CSELCA_Pos = 0x10
	// Bit mask of CSELCA field.
	GPT16E0_GTCSR_CSELCA_Msk = 0x10000
	// Bit CSELCA.
	GPT16E0_GTCSR_CSELCA = 0x10000
	// Counter clear disabled at the ELC_GPTA input
	GPT16E0_GTCSR_CSELCA_0 = 0x0
	// Counter clear enabled at the ELC_GPTA input
	GPT16E0_GTCSR_CSELCA_1 = 0x1
	// Position of CSELCB field.
	GPT16E0_GTCSR_CSELCB_Pos = 0x11
	// Bit mask of CSELCB field.
	GPT16E0_GTCSR_CSELCB_Msk = 0x20000
	// Bit CSELCB.
	GPT16E0_GTCSR_CSELCB = 0x20000
	// Counter clear disabled at the ELC_GPTB input
	GPT16E0_GTCSR_CSELCB_0 = 0x0
	// Counter clear enabled at the ELC_GPTB input
	GPT16E0_GTCSR_CSELCB_1 = 0x1
	// Position of CSELCC field.
	GPT16E0_GTCSR_CSELCC_Pos = 0x12
	// Bit mask of CSELCC field.
	GPT16E0_GTCSR_CSELCC_Msk = 0x40000
	// Bit CSELCC.
	GPT16E0_GTCSR_CSELCC = 0x40000
	// Counter clear disabled at the ELC_GPTC input
	GPT16E0_GTCSR_CSELCC_0 = 0x0
	// Counter clear enabled at the ELC_GPTC input
	GPT16E0_GTCSR_CSELCC_1 = 0x1
	// Position of CSELCD field.
	GPT16E0_GTCSR_CSELCD_Pos = 0x13
	// Bit mask of CSELCD field.
	GPT16E0_GTCSR_CSELCD_Msk = 0x80000
	// Bit CSELCD.
	GPT16E0_GTCSR_CSELCD = 0x80000
	// Counter clear disabled at the ELC_GPTD input
	GPT16E0_GTCSR_CSELCD_0 = 0x0
	// Counter clear enabled at the ELC_GPTD input
	GPT16E0_GTCSR_CSELCD_1 = 0x1
	// Position of CSELCE field.
	GPT16E0_GTCSR_CSELCE_Pos = 0x14
	// Bit mask of CSELCE field.
	GPT16E0_GTCSR_CSELCE_Msk = 0x100000
	// Bit CSELCE.
	GPT16E0_GTCSR_CSELCE = 0x100000
	// Counter clear disabled at the ELC_GPTE input
	GPT16E0_GTCSR_CSELCE_0 = 0x0
	// Counter clear enabled at the ELC_GPTE input
	GPT16E0_GTCSR_CSELCE_1 = 0x1
	// Position of CSELCF field.
	GPT16E0_GTCSR_CSELCF_Pos = 0x15
	// Bit mask of CSELCF field.
	GPT16E0_GTCSR_CSELCF_Msk = 0x200000
	// Bit CSELCF.
	GPT16E0_GTCSR_CSELCF = 0x200000
	// Counter clear disabled at the ELC_GPTF input
	GPT16E0_GTCSR_CSELCF_0 = 0x0
	// Counter clear enabled at the ELC_GPTF input
	GPT16E0_GTCSR_CSELCF_1 = 0x1
	// Position of CSELCG field.
	GPT16E0_GTCSR_CSELCG_Pos = 0x16
	// Bit mask of CSELCG field.
	GPT16E0_GTCSR_CSELCG_Msk = 0x400000
	// Bit CSELCG.
	GPT16E0_GTCSR_CSELCG = 0x400000
	// Counter clear disabled at the ELC_GPTG input
	GPT16E0_GTCSR_CSELCG_0 = 0x0
	// Counter clear enabled at the ELC_GPTG input
	GPT16E0_GTCSR_CSELCG_1 = 0x1
	// Position of CSELCH field.
	GPT16E0_GTCSR_CSELCH_Pos = 0x17
	// Bit mask of CSELCH field.
	GPT16E0_GTCSR_CSELCH_Msk = 0x800000
	// Bit CSELCH.
	GPT16E0_GTCSR_CSELCH = 0x800000
	// Counter clear disabled at the ELC_GPTH input
	GPT16E0_GTCSR_CSELCH_0 = 0x0
	// Counter clear enabled at the ELC_GPTH input
	GPT16E0_GTCSR_CSELCH_1 = 0x1
	// Position of CCLR field.
	GPT16E0_GTCSR_CCLR_Pos = 0x1f
	// Bit mask of CCLR field.
	GPT16E0_GTCSR_CCLR_Msk = 0x80000000
	// Bit CCLR.
	GPT16E0_GTCSR_CCLR = 0x80000000
	// Counter clear disabled by the GTCLR register
	GPT16E0_GTCSR_CCLR_0 = 0x0
	// Counter clear enabled by the GTCLR register
	GPT16E0_GTCSR_CCLR_1 = 0x1

	// GTUPSR: General PWM Timer Up Count Source Select Register
	// Position of USGTRGAR field.
	GPT16E0_GTUPSR_USGTRGAR_Pos = 0x0
	// Bit mask of USGTRGAR field.
	GPT16E0_GTUPSR_USGTRGAR_Msk = 0x1
	// Bit USGTRGAR.
	GPT16E0_GTUPSR_USGTRGAR = 0x1
	// Counter count up disabled on the rising edge of GTETRGA input
	GPT16E0_GTUPSR_USGTRGAR_0 = 0x0
	// Counter count up enabled on the rising edge of GTETRGA input
	GPT16E0_GTUPSR_USGTRGAR_1 = 0x1
	// Position of USGTRGAF field.
	GPT16E0_GTUPSR_USGTRGAF_Pos = 0x1
	// Bit mask of USGTRGAF field.
	GPT16E0_GTUPSR_USGTRGAF_Msk = 0x2
	// Bit USGTRGAF.
	GPT16E0_GTUPSR_USGTRGAF = 0x2
	// Counter count up disabled on the falling edge of GTETRGA input
	GPT16E0_GTUPSR_USGTRGAF_0 = 0x0
	// Counter count up enabled on the falling edge of GTETRGA input
	GPT16E0_GTUPSR_USGTRGAF_1 = 0x1
	// Position of USGTRGBR field.
	GPT16E0_GTUPSR_USGTRGBR_Pos = 0x2
	// Bit mask of USGTRGBR field.
	GPT16E0_GTUPSR_USGTRGBR_Msk = 0x4
	// Bit USGTRGBR.
	GPT16E0_GTUPSR_USGTRGBR = 0x4
	// Counter count up disabled on the rising edge of GTETRGB input
	GPT16E0_GTUPSR_USGTRGBR_0 = 0x0
	// Counter count up enabled on the rising edge of GTETRGB input
	GPT16E0_GTUPSR_USGTRGBR_1 = 0x1
	// Position of USGTRGBF field.
	GPT16E0_GTUPSR_USGTRGBF_Pos = 0x3
	// Bit mask of USGTRGBF field.
	GPT16E0_GTUPSR_USGTRGBF_Msk = 0x8
	// Bit USGTRGBF.
	GPT16E0_GTUPSR_USGTRGBF = 0x8
	// Counter count up disabled on the falling edge of GTETRGB input
	GPT16E0_GTUPSR_USGTRGBF_0 = 0x0
	// Counter count up enabled on the falling edge of GTETRGB input
	GPT16E0_GTUPSR_USGTRGBF_1 = 0x1
	// Position of USGTRGCR field.
	GPT16E0_GTUPSR_USGTRGCR_Pos = 0x4
	// Bit mask of USGTRGCR field.
	GPT16E0_GTUPSR_USGTRGCR_Msk = 0x10
	// Bit USGTRGCR.
	GPT16E0_GTUPSR_USGTRGCR = 0x10
	// Counter count up disabled on the rising edge of GTETRGC input
	GPT16E0_GTUPSR_USGTRGCR_0 = 0x0
	// Counter count up enabled on the rising edge of GTETRGC input
	GPT16E0_GTUPSR_USGTRGCR_1 = 0x1
	// Position of USGTRGCF field.
	GPT16E0_GTUPSR_USGTRGCF_Pos = 0x5
	// Bit mask of USGTRGCF field.
	GPT16E0_GTUPSR_USGTRGCF_Msk = 0x20
	// Bit USGTRGCF.
	GPT16E0_GTUPSR_USGTRGCF = 0x20
	// Counter count up disabled on the falling edge of GTETRGC input
	GPT16E0_GTUPSR_USGTRGCF_0 = 0x0
	// Counter count up enabled on the falling edge of GTETRGC input
	GPT16E0_GTUPSR_USGTRGCF_1 = 0x1
	// Position of USGTRGDR field.
	GPT16E0_GTUPSR_USGTRGDR_Pos = 0x6
	// Bit mask of USGTRGDR field.
	GPT16E0_GTUPSR_USGTRGDR_Msk = 0x40
	// Bit USGTRGDR.
	GPT16E0_GTUPSR_USGTRGDR = 0x40
	// Counter count up disabled on the rising edge of GTETRGD input
	GPT16E0_GTUPSR_USGTRGDR_0 = 0x0
	// Counter count up enabled on the rising edge of GTETRGD input
	GPT16E0_GTUPSR_USGTRGDR_1 = 0x1
	// Position of USGTRGDF field.
	GPT16E0_GTUPSR_USGTRGDF_Pos = 0x7
	// Bit mask of USGTRGDF field.
	GPT16E0_GTUPSR_USGTRGDF_Msk = 0x80
	// Bit USGTRGDF.
	GPT16E0_GTUPSR_USGTRGDF = 0x80
	// Counter count up disabled on the falling edge of GTETRGD input
	GPT16E0_GTUPSR_USGTRGDF_0 = 0x0
	// Counter count up enabled on the falling edge of GTETRGD input
	GPT16E0_GTUPSR_USGTRGDF_1 = 0x1
	// Position of USCARBL field.
	GPT16E0_GTUPSR_USCARBL_Pos = 0x8
	// Bit mask of USCARBL field.
	GPT16E0_GTUPSR_USCARBL_Msk = 0x100
	// Bit USCARBL.
	GPT16E0_GTUPSR_USCARBL = 0x100
	// Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTUPSR_USCARBL_0 = 0x0
	// Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTUPSR_USCARBL_1 = 0x1
	// Position of USCARBH field.
	GPT16E0_GTUPSR_USCARBH_Pos = 0x9
	// Bit mask of USCARBH field.
	GPT16E0_GTUPSR_USCARBH_Msk = 0x200
	// Bit USCARBH.
	GPT16E0_GTUPSR_USCARBH = 0x200
	// Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTUPSR_USCARBH_0 = 0x0
	// Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTUPSR_USCARBH_1 = 0x1
	// Position of USCAFBL field.
	GPT16E0_GTUPSR_USCAFBL_Pos = 0xa
	// Bit mask of USCAFBL field.
	GPT16E0_GTUPSR_USCAFBL_Msk = 0x400
	// Bit USCAFBL.
	GPT16E0_GTUPSR_USCAFBL = 0x400
	// Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTUPSR_USCAFBL_0 = 0x0
	// Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTUPSR_USCAFBL_1 = 0x1
	// Position of USCAFBH field.
	GPT16E0_GTUPSR_USCAFBH_Pos = 0xb
	// Bit mask of USCAFBH field.
	GPT16E0_GTUPSR_USCAFBH_Msk = 0x800
	// Bit USCAFBH.
	GPT16E0_GTUPSR_USCAFBH = 0x800
	// Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTUPSR_USCAFBH_0 = 0x0
	// Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTUPSR_USCAFBH_1 = 0x1
	// Position of USCBRAL field.
	GPT16E0_GTUPSR_USCBRAL_Pos = 0xc
	// Bit mask of USCBRAL field.
	GPT16E0_GTUPSR_USCBRAL_Msk = 0x1000
	// Bit USCBRAL.
	GPT16E0_GTUPSR_USCBRAL = 0x1000
	// Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTUPSR_USCBRAL_0 = 0x0
	// Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTUPSR_USCBRAL_1 = 0x1
	// Position of USCBRAH field.
	GPT16E0_GTUPSR_USCBRAH_Pos = 0xd
	// Bit mask of USCBRAH field.
	GPT16E0_GTUPSR_USCBRAH_Msk = 0x2000
	// Bit USCBRAH.
	GPT16E0_GTUPSR_USCBRAH = 0x2000
	// Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTUPSR_USCBRAH_0 = 0x0
	// Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTUPSR_USCBRAH_1 = 0x1
	// Position of USCBFAL field.
	GPT16E0_GTUPSR_USCBFAL_Pos = 0xe
	// Bit mask of USCBFAL field.
	GPT16E0_GTUPSR_USCBFAL_Msk = 0x4000
	// Bit USCBFAL.
	GPT16E0_GTUPSR_USCBFAL = 0x4000
	// Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTUPSR_USCBFAL_0 = 0x0
	// Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTUPSR_USCBFAL_1 = 0x1
	// Position of USCBFAH field.
	GPT16E0_GTUPSR_USCBFAH_Pos = 0xf
	// Bit mask of USCBFAH field.
	GPT16E0_GTUPSR_USCBFAH_Msk = 0x8000
	// Bit USCBFAH.
	GPT16E0_GTUPSR_USCBFAH = 0x8000
	// Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTUPSR_USCBFAH_0 = 0x0
	// Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTUPSR_USCBFAH_1 = 0x1
	// Position of USELCA field.
	GPT16E0_GTUPSR_USELCA_Pos = 0x10
	// Bit mask of USELCA field.
	GPT16E0_GTUPSR_USELCA_Msk = 0x10000
	// Bit USELCA.
	GPT16E0_GTUPSR_USELCA = 0x10000
	// Counter count up disabled at the ELC_GPTA input
	GPT16E0_GTUPSR_USELCA_0 = 0x0
	// Counter count up enabled at the ELC_GPTA input
	GPT16E0_GTUPSR_USELCA_1 = 0x1
	// Position of USELCB field.
	GPT16E0_GTUPSR_USELCB_Pos = 0x11
	// Bit mask of USELCB field.
	GPT16E0_GTUPSR_USELCB_Msk = 0x20000
	// Bit USELCB.
	GPT16E0_GTUPSR_USELCB = 0x20000
	// Counter count up disabled at the ELC_GPTB input
	GPT16E0_GTUPSR_USELCB_0 = 0x0
	// Counter count up enabled at the ELC_GPTB input
	GPT16E0_GTUPSR_USELCB_1 = 0x1
	// Position of USELCC field.
	GPT16E0_GTUPSR_USELCC_Pos = 0x12
	// Bit mask of USELCC field.
	GPT16E0_GTUPSR_USELCC_Msk = 0x40000
	// Bit USELCC.
	GPT16E0_GTUPSR_USELCC = 0x40000
	// Counter count up disabled at the ELC_GPTC input
	GPT16E0_GTUPSR_USELCC_0 = 0x0
	// Counter count up enabled at the ELC_GPTC input
	GPT16E0_GTUPSR_USELCC_1 = 0x1
	// Position of USELCD field.
	GPT16E0_GTUPSR_USELCD_Pos = 0x13
	// Bit mask of USELCD field.
	GPT16E0_GTUPSR_USELCD_Msk = 0x80000
	// Bit USELCD.
	GPT16E0_GTUPSR_USELCD = 0x80000
	// Counter count up disabled at the ELC_GPTD input
	GPT16E0_GTUPSR_USELCD_0 = 0x0
	// Counter count up enabled at the ELC_GPTD input
	GPT16E0_GTUPSR_USELCD_1 = 0x1
	// Position of USELCE field.
	GPT16E0_GTUPSR_USELCE_Pos = 0x14
	// Bit mask of USELCE field.
	GPT16E0_GTUPSR_USELCE_Msk = 0x100000
	// Bit USELCE.
	GPT16E0_GTUPSR_USELCE = 0x100000
	// Counter count up disabled at the ELC_GPTE input
	GPT16E0_GTUPSR_USELCE_0 = 0x0
	// Counter count up enabled at the ELC_GPTE input
	GPT16E0_GTUPSR_USELCE_1 = 0x1
	// Position of USELCF field.
	GPT16E0_GTUPSR_USELCF_Pos = 0x15
	// Bit mask of USELCF field.
	GPT16E0_GTUPSR_USELCF_Msk = 0x200000
	// Bit USELCF.
	GPT16E0_GTUPSR_USELCF = 0x200000
	// Counter count up disabled at the ELC_GPTF input
	GPT16E0_GTUPSR_USELCF_0 = 0x0
	// Counter count up enabled at the ELC_GPTF input
	GPT16E0_GTUPSR_USELCF_1 = 0x1
	// Position of USELCG field.
	GPT16E0_GTUPSR_USELCG_Pos = 0x16
	// Bit mask of USELCG field.
	GPT16E0_GTUPSR_USELCG_Msk = 0x400000
	// Bit USELCG.
	GPT16E0_GTUPSR_USELCG = 0x400000
	// Counter count up disabled at the ELC_GPTG input
	GPT16E0_GTUPSR_USELCG_0 = 0x0
	// Counter count up enabled at the ELC_GPTG input
	GPT16E0_GTUPSR_USELCG_1 = 0x1
	// Position of USELCH field.
	GPT16E0_GTUPSR_USELCH_Pos = 0x17
	// Bit mask of USELCH field.
	GPT16E0_GTUPSR_USELCH_Msk = 0x800000
	// Bit USELCH.
	GPT16E0_GTUPSR_USELCH = 0x800000
	// Counter count up disabled at the ELC_GPTH input
	GPT16E0_GTUPSR_USELCH_0 = 0x0
	// Counter count up enabled at the ELC_GPTH input
	GPT16E0_GTUPSR_USELCH_1 = 0x1

	// GTDNSR: General PWM Timer Down Count Source Select Register
	// Position of DSGTRGAR field.
	GPT16E0_GTDNSR_DSGTRGAR_Pos = 0x0
	// Bit mask of DSGTRGAR field.
	GPT16E0_GTDNSR_DSGTRGAR_Msk = 0x1
	// Bit DSGTRGAR.
	GPT16E0_GTDNSR_DSGTRGAR = 0x1
	// Counter count down disabled on the rising edge of GTETRGA input
	GPT16E0_GTDNSR_DSGTRGAR_0 = 0x0
	// Counter count down enabled on the rising edge of GTETRGA input
	GPT16E0_GTDNSR_DSGTRGAR_1 = 0x1
	// Position of DSGTRGAF field.
	GPT16E0_GTDNSR_DSGTRGAF_Pos = 0x1
	// Bit mask of DSGTRGAF field.
	GPT16E0_GTDNSR_DSGTRGAF_Msk = 0x2
	// Bit DSGTRGAF.
	GPT16E0_GTDNSR_DSGTRGAF = 0x2
	// Counter count down disabled on the falling edge of GTETRGA input
	GPT16E0_GTDNSR_DSGTRGAF_0 = 0x0
	// Counter count down enabled on the falling edge of GTETRGA input
	GPT16E0_GTDNSR_DSGTRGAF_1 = 0x1
	// Position of DSGTRGBR field.
	GPT16E0_GTDNSR_DSGTRGBR_Pos = 0x2
	// Bit mask of DSGTRGBR field.
	GPT16E0_GTDNSR_DSGTRGBR_Msk = 0x4
	// Bit DSGTRGBR.
	GPT16E0_GTDNSR_DSGTRGBR = 0x4
	// Counter count down disabled on the rising edge of GTETRGB input
	GPT16E0_GTDNSR_DSGTRGBR_0 = 0x0
	// Counter count down enabled on the rising edge of GTETRGB input
	GPT16E0_GTDNSR_DSGTRGBR_1 = 0x1
	// Position of DSGTRGBF field.
	GPT16E0_GTDNSR_DSGTRGBF_Pos = 0x3
	// Bit mask of DSGTRGBF field.
	GPT16E0_GTDNSR_DSGTRGBF_Msk = 0x8
	// Bit DSGTRGBF.
	GPT16E0_GTDNSR_DSGTRGBF = 0x8
	// Counter count down disabled on the falling edge of GTETRGB input
	GPT16E0_GTDNSR_DSGTRGBF_0 = 0x0
	// Counter count down enabled on the falling edge of GTETRGB input
	GPT16E0_GTDNSR_DSGTRGBF_1 = 0x1
	// Position of DSGTRGCR field.
	GPT16E0_GTDNSR_DSGTRGCR_Pos = 0x4
	// Bit mask of DSGTRGCR field.
	GPT16E0_GTDNSR_DSGTRGCR_Msk = 0x10
	// Bit DSGTRGCR.
	GPT16E0_GTDNSR_DSGTRGCR = 0x10
	// Counter count down disabled on the rising edge of GTETRGC input
	GPT16E0_GTDNSR_DSGTRGCR_0 = 0x0
	// Counter count down enabled on the rising edge of GTETRGC input
	GPT16E0_GTDNSR_DSGTRGCR_1 = 0x1
	// Position of DSGTRGCF field.
	GPT16E0_GTDNSR_DSGTRGCF_Pos = 0x5
	// Bit mask of DSGTRGCF field.
	GPT16E0_GTDNSR_DSGTRGCF_Msk = 0x20
	// Bit DSGTRGCF.
	GPT16E0_GTDNSR_DSGTRGCF = 0x20
	// Counter count down disabled on the falling edge of GTETRGC input
	GPT16E0_GTDNSR_DSGTRGCF_0 = 0x0
	// Counter count down enabled on the falling edge of GTETRGC input
	GPT16E0_GTDNSR_DSGTRGCF_1 = 0x1
	// Position of DSGTRGDR field.
	GPT16E0_GTDNSR_DSGTRGDR_Pos = 0x6
	// Bit mask of DSGTRGDR field.
	GPT16E0_GTDNSR_DSGTRGDR_Msk = 0x40
	// Bit DSGTRGDR.
	GPT16E0_GTDNSR_DSGTRGDR = 0x40
	// Counter count down disabled on the rising edge of GTETRGD input
	GPT16E0_GTDNSR_DSGTRGDR_0 = 0x0
	// Counter count down enabled on the rising edge of GTETRGD input
	GPT16E0_GTDNSR_DSGTRGDR_1 = 0x1
	// Position of DSGTRGDF field.
	GPT16E0_GTDNSR_DSGTRGDF_Pos = 0x7
	// Bit mask of DSGTRGDF field.
	GPT16E0_GTDNSR_DSGTRGDF_Msk = 0x80
	// Bit DSGTRGDF.
	GPT16E0_GTDNSR_DSGTRGDF = 0x80
	// Counter count down disabled on the falling edge of GTETRGD input
	GPT16E0_GTDNSR_DSGTRGDF_0 = 0x0
	// Counter count down enabled on the falling edge of GTETRGD input
	GPT16E0_GTDNSR_DSGTRGDF_1 = 0x1
	// Position of DSCARBL field.
	GPT16E0_GTDNSR_DSCARBL_Pos = 0x8
	// Bit mask of DSCARBL field.
	GPT16E0_GTDNSR_DSCARBL_Msk = 0x100
	// Bit DSCARBL.
	GPT16E0_GTDNSR_DSCARBL = 0x100
	// Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTDNSR_DSCARBL_0 = 0x0
	// Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTDNSR_DSCARBL_1 = 0x1
	// Position of DSCARBH field.
	GPT16E0_GTDNSR_DSCARBH_Pos = 0x9
	// Bit mask of DSCARBH field.
	GPT16E0_GTDNSR_DSCARBH_Msk = 0x200
	// Bit DSCARBH.
	GPT16E0_GTDNSR_DSCARBH = 0x200
	// Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTDNSR_DSCARBH_0 = 0x0
	// Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTDNSR_DSCARBH_1 = 0x1
	// Position of DSCAFBL field.
	GPT16E0_GTDNSR_DSCAFBL_Pos = 0xa
	// Bit mask of DSCAFBL field.
	GPT16E0_GTDNSR_DSCAFBL_Msk = 0x400
	// Bit DSCAFBL.
	GPT16E0_GTDNSR_DSCAFBL = 0x400
	// Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTDNSR_DSCAFBL_0 = 0x0
	// Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTDNSR_DSCAFBL_1 = 0x1
	// Position of DSCAFBH field.
	GPT16E0_GTDNSR_DSCAFBH_Pos = 0xb
	// Bit mask of DSCAFBH field.
	GPT16E0_GTDNSR_DSCAFBH_Msk = 0x800
	// Bit DSCAFBH.
	GPT16E0_GTDNSR_DSCAFBH = 0x800
	// Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTDNSR_DSCAFBH_0 = 0x0
	// Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTDNSR_DSCAFBH_1 = 0x1
	// Position of DSCBRAL field.
	GPT16E0_GTDNSR_DSCBRAL_Pos = 0xc
	// Bit mask of DSCBRAL field.
	GPT16E0_GTDNSR_DSCBRAL_Msk = 0x1000
	// Bit DSCBRAL.
	GPT16E0_GTDNSR_DSCBRAL = 0x1000
	// Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTDNSR_DSCBRAL_0 = 0x0
	// Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTDNSR_DSCBRAL_1 = 0x1
	// Position of DSCBRAH field.
	GPT16E0_GTDNSR_DSCBRAH_Pos = 0xd
	// Bit mask of DSCBRAH field.
	GPT16E0_GTDNSR_DSCBRAH_Msk = 0x2000
	// Bit DSCBRAH.
	GPT16E0_GTDNSR_DSCBRAH = 0x2000
	// Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTDNSR_DSCBRAH_0 = 0x0
	// Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTDNSR_DSCBRAH_1 = 0x1
	// Position of DSCBFAL field.
	GPT16E0_GTDNSR_DSCBFAL_Pos = 0xe
	// Bit mask of DSCBFAL field.
	GPT16E0_GTDNSR_DSCBFAL_Msk = 0x4000
	// Bit DSCBFAL.
	GPT16E0_GTDNSR_DSCBFAL = 0x4000
	// Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTDNSR_DSCBFAL_0 = 0x0
	// Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTDNSR_DSCBFAL_1 = 0x1
	// Position of DSCBFAH field.
	GPT16E0_GTDNSR_DSCBFAH_Pos = 0xf
	// Bit mask of DSCBFAH field.
	GPT16E0_GTDNSR_DSCBFAH_Msk = 0x8000
	// Bit DSCBFAH.
	GPT16E0_GTDNSR_DSCBFAH = 0x8000
	// Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTDNSR_DSCBFAH_0 = 0x0
	// Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTDNSR_DSCBFAH_1 = 0x1
	// Position of DSELCA field.
	GPT16E0_GTDNSR_DSELCA_Pos = 0x10
	// Bit mask of DSELCA field.
	GPT16E0_GTDNSR_DSELCA_Msk = 0x10000
	// Bit DSELCA.
	GPT16E0_GTDNSR_DSELCA = 0x10000
	// Counter count down disabled at the ELC_GPTA input
	GPT16E0_GTDNSR_DSELCA_0 = 0x0
	// Counter count down enabled at the ELC_GPTA input
	GPT16E0_GTDNSR_DSELCA_1 = 0x1
	// Position of DSELCB field.
	GPT16E0_GTDNSR_DSELCB_Pos = 0x11
	// Bit mask of DSELCB field.
	GPT16E0_GTDNSR_DSELCB_Msk = 0x20000
	// Bit DSELCB.
	GPT16E0_GTDNSR_DSELCB = 0x20000
	// Counter count down disabled at the ELC_GPTB input
	GPT16E0_GTDNSR_DSELCB_0 = 0x0
	// Counter count down enabled at the ELC_GPTB input
	GPT16E0_GTDNSR_DSELCB_1 = 0x1
	// Position of DSELCC field.
	GPT16E0_GTDNSR_DSELCC_Pos = 0x12
	// Bit mask of DSELCC field.
	GPT16E0_GTDNSR_DSELCC_Msk = 0x40000
	// Bit DSELCC.
	GPT16E0_GTDNSR_DSELCC = 0x40000
	// Counter count down disabled at the ELC_GPTC input
	GPT16E0_GTDNSR_DSELCC_0 = 0x0
	// Counter count down enabled at the ELC_GPTC input
	GPT16E0_GTDNSR_DSELCC_1 = 0x1
	// Position of DSELCD field.
	GPT16E0_GTDNSR_DSELCD_Pos = 0x13
	// Bit mask of DSELCD field.
	GPT16E0_GTDNSR_DSELCD_Msk = 0x80000
	// Bit DSELCD.
	GPT16E0_GTDNSR_DSELCD = 0x80000
	// Counter count down disabled at the ELC_GPTD input
	GPT16E0_GTDNSR_DSELCD_0 = 0x0
	// Counter count down enabled at the ELC_GPTD input
	GPT16E0_GTDNSR_DSELCD_1 = 0x1
	// Position of DSELCE field.
	GPT16E0_GTDNSR_DSELCE_Pos = 0x14
	// Bit mask of DSELCE field.
	GPT16E0_GTDNSR_DSELCE_Msk = 0x100000
	// Bit DSELCE.
	GPT16E0_GTDNSR_DSELCE = 0x100000
	// Counter count down disabled at the ELC_GPTE input
	GPT16E0_GTDNSR_DSELCE_0 = 0x0
	// Counter count down enabled at the ELC_GPTE input
	GPT16E0_GTDNSR_DSELCE_1 = 0x1
	// Position of DSELCF field.
	GPT16E0_GTDNSR_DSELCF_Pos = 0x15
	// Bit mask of DSELCF field.
	GPT16E0_GTDNSR_DSELCF_Msk = 0x200000
	// Bit DSELCF.
	GPT16E0_GTDNSR_DSELCF = 0x200000
	// Counter count down disabled at the ELC_GPTF input
	GPT16E0_GTDNSR_DSELCF_0 = 0x0
	// Counter count down enabled at the ELC_GPTF input
	GPT16E0_GTDNSR_DSELCF_1 = 0x1
	// Position of DSELCG field.
	GPT16E0_GTDNSR_DSELCG_Pos = 0x16
	// Bit mask of DSELCG field.
	GPT16E0_GTDNSR_DSELCG_Msk = 0x400000
	// Bit DSELCG.
	GPT16E0_GTDNSR_DSELCG = 0x400000
	// Counter count down disabled at the ELC_GPTG input
	GPT16E0_GTDNSR_DSELCG_0 = 0x0
	// Counter count down enabled at the ELC_GPTG input
	GPT16E0_GTDNSR_DSELCG_1 = 0x1
	// Position of DSELCH field.
	GPT16E0_GTDNSR_DSELCH_Pos = 0x17
	// Bit mask of DSELCH field.
	GPT16E0_GTDNSR_DSELCH_Msk = 0x800000
	// Bit DSELCH.
	GPT16E0_GTDNSR_DSELCH = 0x800000
	// Counter count down disabled at the ELC_GPTH input
	GPT16E0_GTDNSR_DSELCH_0 = 0x0
	// Counter count down enabled at the ELC_GPTH input
	GPT16E0_GTDNSR_DSELCH_1 = 0x1

	// GTICASR: General PWM Timer Input Capture Source Select Register A
	// Position of ASGTRGAR field.
	GPT16E0_GTICASR_ASGTRGAR_Pos = 0x0
	// Bit mask of ASGTRGAR field.
	GPT16E0_GTICASR_ASGTRGAR_Msk = 0x1
	// Bit ASGTRGAR.
	GPT16E0_GTICASR_ASGTRGAR = 0x1
	// GTCCRA input capture disabled on the rising edge of GTETRGA input
	GPT16E0_GTICASR_ASGTRGAR_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTETRGA input
	GPT16E0_GTICASR_ASGTRGAR_1 = 0x1
	// Position of ASGTRGAF field.
	GPT16E0_GTICASR_ASGTRGAF_Pos = 0x1
	// Bit mask of ASGTRGAF field.
	GPT16E0_GTICASR_ASGTRGAF_Msk = 0x2
	// Bit ASGTRGAF.
	GPT16E0_GTICASR_ASGTRGAF = 0x2
	// GTCCRA input capture disabled on the falling edge of GTETRGA input
	GPT16E0_GTICASR_ASGTRGAF_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTETRGA input
	GPT16E0_GTICASR_ASGTRGAF_1 = 0x1
	// Position of ASGTRGBR field.
	GPT16E0_GTICASR_ASGTRGBR_Pos = 0x2
	// Bit mask of ASGTRGBR field.
	GPT16E0_GTICASR_ASGTRGBR_Msk = 0x4
	// Bit ASGTRGBR.
	GPT16E0_GTICASR_ASGTRGBR = 0x4
	// GTCCRA input capture disabled on the rising edge of GTETRGB input
	GPT16E0_GTICASR_ASGTRGBR_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTETRGB input
	GPT16E0_GTICASR_ASGTRGBR_1 = 0x1
	// Position of ASGTRGBF field.
	GPT16E0_GTICASR_ASGTRGBF_Pos = 0x3
	// Bit mask of ASGTRGBF field.
	GPT16E0_GTICASR_ASGTRGBF_Msk = 0x8
	// Bit ASGTRGBF.
	GPT16E0_GTICASR_ASGTRGBF = 0x8
	// GTCCRA input capture disabled on the falling edge of GTETRGB input
	GPT16E0_GTICASR_ASGTRGBF_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTETRGB input
	GPT16E0_GTICASR_ASGTRGBF_1 = 0x1
	// Position of ASGTRGCR field.
	GPT16E0_GTICASR_ASGTRGCR_Pos = 0x4
	// Bit mask of ASGTRGCR field.
	GPT16E0_GTICASR_ASGTRGCR_Msk = 0x10
	// Bit ASGTRGCR.
	GPT16E0_GTICASR_ASGTRGCR = 0x10
	// GTCCRA input capture disabled on the rising edge of GTETRGC input
	GPT16E0_GTICASR_ASGTRGCR_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTETRGC input
	GPT16E0_GTICASR_ASGTRGCR_1 = 0x1
	// Position of ASGTRGCF field.
	GPT16E0_GTICASR_ASGTRGCF_Pos = 0x5
	// Bit mask of ASGTRGCF field.
	GPT16E0_GTICASR_ASGTRGCF_Msk = 0x20
	// Bit ASGTRGCF.
	GPT16E0_GTICASR_ASGTRGCF = 0x20
	// GTCCRA input capture disabled on the falling edge of GTETRGC input
	GPT16E0_GTICASR_ASGTRGCF_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTETRGC input
	GPT16E0_GTICASR_ASGTRGCF_1 = 0x1
	// Position of ASGTRGDR field.
	GPT16E0_GTICASR_ASGTRGDR_Pos = 0x6
	// Bit mask of ASGTRGDR field.
	GPT16E0_GTICASR_ASGTRGDR_Msk = 0x40
	// Bit ASGTRGDR.
	GPT16E0_GTICASR_ASGTRGDR = 0x40
	// GTCCRA input capture disabled on the rising edge of GTETRGD input
	GPT16E0_GTICASR_ASGTRGDR_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTETRGD input
	GPT16E0_GTICASR_ASGTRGDR_1 = 0x1
	// Position of ASGTRGDF field.
	GPT16E0_GTICASR_ASGTRGDF_Pos = 0x7
	// Bit mask of ASGTRGDF field.
	GPT16E0_GTICASR_ASGTRGDF_Msk = 0x80
	// Bit ASGTRGDF.
	GPT16E0_GTICASR_ASGTRGDF = 0x80
	// GTCCRA input capture disabled on the falling edge of GTETRGD input
	GPT16E0_GTICASR_ASGTRGDF_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTETRGD input
	GPT16E0_GTICASR_ASGTRGDF_1 = 0x1
	// Position of ASCARBL field.
	GPT16E0_GTICASR_ASCARBL_Pos = 0x8
	// Bit mask of ASCARBL field.
	GPT16E0_GTICASR_ASCARBL_Msk = 0x100
	// Bit ASCARBL.
	GPT16E0_GTICASR_ASCARBL = 0x100
	// GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICASR_ASCARBL_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICASR_ASCARBL_1 = 0x1
	// Position of ASCARBH field.
	GPT16E0_GTICASR_ASCARBH_Pos = 0x9
	// Bit mask of ASCARBH field.
	GPT16E0_GTICASR_ASCARBH_Msk = 0x200
	// Bit ASCARBH.
	GPT16E0_GTICASR_ASCARBH = 0x200
	// GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICASR_ASCARBH_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICASR_ASCARBH_1 = 0x1
	// Position of ASCAFBL field.
	GPT16E0_GTICASR_ASCAFBL_Pos = 0xa
	// Bit mask of ASCAFBL field.
	GPT16E0_GTICASR_ASCAFBL_Msk = 0x400
	// Bit ASCAFBL.
	GPT16E0_GTICASR_ASCAFBL = 0x400
	// GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICASR_ASCAFBL_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICASR_ASCAFBL_1 = 0x1
	// Position of ASCAFBH field.
	GPT16E0_GTICASR_ASCAFBH_Pos = 0xb
	// Bit mask of ASCAFBH field.
	GPT16E0_GTICASR_ASCAFBH_Msk = 0x800
	// Bit ASCAFBH.
	GPT16E0_GTICASR_ASCAFBH = 0x800
	// GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICASR_ASCAFBH_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICASR_ASCAFBH_1 = 0x1
	// Position of ASCBRAL field.
	GPT16E0_GTICASR_ASCBRAL_Pos = 0xc
	// Bit mask of ASCBRAL field.
	GPT16E0_GTICASR_ASCBRAL_Msk = 0x1000
	// Bit ASCBRAL.
	GPT16E0_GTICASR_ASCBRAL = 0x1000
	// GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICASR_ASCBRAL_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICASR_ASCBRAL_1 = 0x1
	// Position of ASCBRAH field.
	GPT16E0_GTICASR_ASCBRAH_Pos = 0xd
	// Bit mask of ASCBRAH field.
	GPT16E0_GTICASR_ASCBRAH_Msk = 0x2000
	// Bit ASCBRAH.
	GPT16E0_GTICASR_ASCBRAH = 0x2000
	// GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICASR_ASCBRAH_0 = 0x0
	// GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICASR_ASCBRAH_1 = 0x1
	// Position of ASCBFAL field.
	GPT16E0_GTICASR_ASCBFAL_Pos = 0xe
	// Bit mask of ASCBFAL field.
	GPT16E0_GTICASR_ASCBFAL_Msk = 0x4000
	// Bit ASCBFAL.
	GPT16E0_GTICASR_ASCBFAL = 0x4000
	// GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICASR_ASCBFAL_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICASR_ASCBFAL_1 = 0x1
	// Position of ASCBFAH field.
	GPT16E0_GTICASR_ASCBFAH_Pos = 0xf
	// Bit mask of ASCBFAH field.
	GPT16E0_GTICASR_ASCBFAH_Msk = 0x8000
	// Bit ASCBFAH.
	GPT16E0_GTICASR_ASCBFAH = 0x8000
	// GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICASR_ASCBFAH_0 = 0x0
	// GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICASR_ASCBFAH_1 = 0x1
	// Position of ASELCA field.
	GPT16E0_GTICASR_ASELCA_Pos = 0x10
	// Bit mask of ASELCA field.
	GPT16E0_GTICASR_ASELCA_Msk = 0x10000
	// Bit ASELCA.
	GPT16E0_GTICASR_ASELCA = 0x10000
	// GTCCRA input capture disabled at the ELC_GPTA input
	GPT16E0_GTICASR_ASELCA_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTA input
	GPT16E0_GTICASR_ASELCA_1 = 0x1
	// Position of ASELCB field.
	GPT16E0_GTICASR_ASELCB_Pos = 0x11
	// Bit mask of ASELCB field.
	GPT16E0_GTICASR_ASELCB_Msk = 0x20000
	// Bit ASELCB.
	GPT16E0_GTICASR_ASELCB = 0x20000
	// GTCCRA input capture disabled at the ELC_GPTB input
	GPT16E0_GTICASR_ASELCB_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTB input
	GPT16E0_GTICASR_ASELCB_1 = 0x1
	// Position of ASELCC field.
	GPT16E0_GTICASR_ASELCC_Pos = 0x12
	// Bit mask of ASELCC field.
	GPT16E0_GTICASR_ASELCC_Msk = 0x40000
	// Bit ASELCC.
	GPT16E0_GTICASR_ASELCC = 0x40000
	// GTCCRA input capture disabled at the ELC_GPTC input
	GPT16E0_GTICASR_ASELCC_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTC input
	GPT16E0_GTICASR_ASELCC_1 = 0x1
	// Position of ASELCD field.
	GPT16E0_GTICASR_ASELCD_Pos = 0x13
	// Bit mask of ASELCD field.
	GPT16E0_GTICASR_ASELCD_Msk = 0x80000
	// Bit ASELCD.
	GPT16E0_GTICASR_ASELCD = 0x80000
	// GTCCRA input capture disabled at the ELC_GPTD input
	GPT16E0_GTICASR_ASELCD_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTD input
	GPT16E0_GTICASR_ASELCD_1 = 0x1
	// Position of ASELCE field.
	GPT16E0_GTICASR_ASELCE_Pos = 0x14
	// Bit mask of ASELCE field.
	GPT16E0_GTICASR_ASELCE_Msk = 0x100000
	// Bit ASELCE.
	GPT16E0_GTICASR_ASELCE = 0x100000
	// GTCCRA input capture disabled at the ELC_GPTE input
	GPT16E0_GTICASR_ASELCE_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTE input
	GPT16E0_GTICASR_ASELCE_1 = 0x1
	// Position of ASELCF field.
	GPT16E0_GTICASR_ASELCF_Pos = 0x15
	// Bit mask of ASELCF field.
	GPT16E0_GTICASR_ASELCF_Msk = 0x200000
	// Bit ASELCF.
	GPT16E0_GTICASR_ASELCF = 0x200000
	// GTCCRA input capture disabled at the ELC_GPTF input
	GPT16E0_GTICASR_ASELCF_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTF input
	GPT16E0_GTICASR_ASELCF_1 = 0x1
	// Position of ASELCG field.
	GPT16E0_GTICASR_ASELCG_Pos = 0x16
	// Bit mask of ASELCG field.
	GPT16E0_GTICASR_ASELCG_Msk = 0x400000
	// Bit ASELCG.
	GPT16E0_GTICASR_ASELCG = 0x400000
	// GTCCRA input capture disabled at the ELC_GPTG input
	GPT16E0_GTICASR_ASELCG_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTG input
	GPT16E0_GTICASR_ASELCG_1 = 0x1
	// Position of ASELCH field.
	GPT16E0_GTICASR_ASELCH_Pos = 0x17
	// Bit mask of ASELCH field.
	GPT16E0_GTICASR_ASELCH_Msk = 0x800000
	// Bit ASELCH.
	GPT16E0_GTICASR_ASELCH = 0x800000
	// GTCCRA input capture disabled at the ELC_GPTH input
	GPT16E0_GTICASR_ASELCH_0 = 0x0
	// GTCCRA input capture enabled at the ELC_GPTH input
	GPT16E0_GTICASR_ASELCH_1 = 0x1

	// GTICBSR: General PWM Timer Input Capture Source Select Register B
	// Position of BSGTRGAR field.
	GPT16E0_GTICBSR_BSGTRGAR_Pos = 0x0
	// Bit mask of BSGTRGAR field.
	GPT16E0_GTICBSR_BSGTRGAR_Msk = 0x1
	// Bit BSGTRGAR.
	GPT16E0_GTICBSR_BSGTRGAR = 0x1
	// GTCCRB input capture disabled on the rising edge of GTETRGA input
	GPT16E0_GTICBSR_BSGTRGAR_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTETRGA input
	GPT16E0_GTICBSR_BSGTRGAR_1 = 0x1
	// Position of BSGTRGAF field.
	GPT16E0_GTICBSR_BSGTRGAF_Pos = 0x1
	// Bit mask of BSGTRGAF field.
	GPT16E0_GTICBSR_BSGTRGAF_Msk = 0x2
	// Bit BSGTRGAF.
	GPT16E0_GTICBSR_BSGTRGAF = 0x2
	// GTCCRB input capture disabled on the falling edge of GTETRGA input
	GPT16E0_GTICBSR_BSGTRGAF_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTETRGA input
	GPT16E0_GTICBSR_BSGTRGAF_1 = 0x1
	// Position of BSGTRGBR field.
	GPT16E0_GTICBSR_BSGTRGBR_Pos = 0x2
	// Bit mask of BSGTRGBR field.
	GPT16E0_GTICBSR_BSGTRGBR_Msk = 0x4
	// Bit BSGTRGBR.
	GPT16E0_GTICBSR_BSGTRGBR = 0x4
	// GTCCRB input capture disabled on the rising edge of GTETRGB input
	GPT16E0_GTICBSR_BSGTRGBR_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTETRGB input
	GPT16E0_GTICBSR_BSGTRGBR_1 = 0x1
	// Position of BSGTRGBF field.
	GPT16E0_GTICBSR_BSGTRGBF_Pos = 0x3
	// Bit mask of BSGTRGBF field.
	GPT16E0_GTICBSR_BSGTRGBF_Msk = 0x8
	// Bit BSGTRGBF.
	GPT16E0_GTICBSR_BSGTRGBF = 0x8
	// GTCCRB input capture disabled on the falling edge of GTETRGB input
	GPT16E0_GTICBSR_BSGTRGBF_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTETRGB input
	GPT16E0_GTICBSR_BSGTRGBF_1 = 0x1
	// Position of BSGTRGCR field.
	GPT16E0_GTICBSR_BSGTRGCR_Pos = 0x4
	// Bit mask of BSGTRGCR field.
	GPT16E0_GTICBSR_BSGTRGCR_Msk = 0x10
	// Bit BSGTRGCR.
	GPT16E0_GTICBSR_BSGTRGCR = 0x10
	// GTCCRB input capture disabled on the rising edge of GTETRGC input
	GPT16E0_GTICBSR_BSGTRGCR_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTETRGC input
	GPT16E0_GTICBSR_BSGTRGCR_1 = 0x1
	// Position of BSGTRGCF field.
	GPT16E0_GTICBSR_BSGTRGCF_Pos = 0x5
	// Bit mask of BSGTRGCF field.
	GPT16E0_GTICBSR_BSGTRGCF_Msk = 0x20
	// Bit BSGTRGCF.
	GPT16E0_GTICBSR_BSGTRGCF = 0x20
	// GTCCRB input capture disabled on the falling edge of GTETRGC input
	GPT16E0_GTICBSR_BSGTRGCF_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTETRGC input
	GPT16E0_GTICBSR_BSGTRGCF_1 = 0x1
	// Position of BSGTRGDR field.
	GPT16E0_GTICBSR_BSGTRGDR_Pos = 0x6
	// Bit mask of BSGTRGDR field.
	GPT16E0_GTICBSR_BSGTRGDR_Msk = 0x40
	// Bit BSGTRGDR.
	GPT16E0_GTICBSR_BSGTRGDR = 0x40
	// GTCCRB input capture disabled on the rising edge of GTETRGD input
	GPT16E0_GTICBSR_BSGTRGDR_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTETRGD input
	GPT16E0_GTICBSR_BSGTRGDR_1 = 0x1
	// Position of BSGTRGDF field.
	GPT16E0_GTICBSR_BSGTRGDF_Pos = 0x7
	// Bit mask of BSGTRGDF field.
	GPT16E0_GTICBSR_BSGTRGDF_Msk = 0x80
	// Bit BSGTRGDF.
	GPT16E0_GTICBSR_BSGTRGDF = 0x80
	// GTCCRB input capture disabled on the falling edge of GTETRGD input
	GPT16E0_GTICBSR_BSGTRGDF_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTETRGD input
	GPT16E0_GTICBSR_BSGTRGDF_1 = 0x1
	// Position of BSCARBL field.
	GPT16E0_GTICBSR_BSCARBL_Pos = 0x8
	// Bit mask of BSCARBL field.
	GPT16E0_GTICBSR_BSCARBL_Msk = 0x100
	// Bit BSCARBL.
	GPT16E0_GTICBSR_BSCARBL = 0x100
	// GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICBSR_BSCARBL_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICBSR_BSCARBL_1 = 0x1
	// Position of BSCARBH field.
	GPT16E0_GTICBSR_BSCARBH_Pos = 0x9
	// Bit mask of BSCARBH field.
	GPT16E0_GTICBSR_BSCARBH_Msk = 0x200
	// Bit BSCARBH.
	GPT16E0_GTICBSR_BSCARBH = 0x200
	// GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICBSR_BSCARBH_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICBSR_BSCARBH_1 = 0x1
	// Position of BSCAFBL field.
	GPT16E0_GTICBSR_BSCAFBL_Pos = 0xa
	// Bit mask of BSCAFBL field.
	GPT16E0_GTICBSR_BSCAFBL_Msk = 0x400
	// Bit BSCAFBL.
	GPT16E0_GTICBSR_BSCAFBL = 0x400
	// GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICBSR_BSCAFBL_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
	GPT16E0_GTICBSR_BSCAFBL_1 = 0x1
	// Position of BSCAFBH field.
	GPT16E0_GTICBSR_BSCAFBH_Pos = 0xb
	// Bit mask of BSCAFBH field.
	GPT16E0_GTICBSR_BSCAFBH_Msk = 0x800
	// Bit BSCAFBH.
	GPT16E0_GTICBSR_BSCAFBH = 0x800
	// GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICBSR_BSCAFBH_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
	GPT16E0_GTICBSR_BSCAFBH_1 = 0x1
	// Position of BSCBRAL field.
	GPT16E0_GTICBSR_BSCBRAL_Pos = 0xc
	// Bit mask of BSCBRAL field.
	GPT16E0_GTICBSR_BSCBRAL_Msk = 0x1000
	// Bit BSCBRAL.
	GPT16E0_GTICBSR_BSCBRAL = 0x1000
	// GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICBSR_BSCBRAL_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICBSR_BSCBRAL_1 = 0x1
	// Position of BSCBRAH field.
	GPT16E0_GTICBSR_BSCBRAH_Pos = 0xd
	// Bit mask of BSCBRAH field.
	GPT16E0_GTICBSR_BSCBRAH_Msk = 0x2000
	// Bit BSCBRAH.
	GPT16E0_GTICBSR_BSCBRAH = 0x2000
	// GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICBSR_BSCBRAH_0 = 0x0
	// GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICBSR_BSCBRAH_1 = 0x1
	// Position of BSCBFAL field.
	GPT16E0_GTICBSR_BSCBFAL_Pos = 0xe
	// Bit mask of BSCBFAL field.
	GPT16E0_GTICBSR_BSCBFAL_Msk = 0x4000
	// Bit BSCBFAL.
	GPT16E0_GTICBSR_BSCBFAL = 0x4000
	// GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICBSR_BSCBFAL_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
	GPT16E0_GTICBSR_BSCBFAL_1 = 0x1
	// Position of BSCBFAH field.
	GPT16E0_GTICBSR_BSCBFAH_Pos = 0xf
	// Bit mask of BSCBFAH field.
	GPT16E0_GTICBSR_BSCBFAH_Msk = 0x8000
	// Bit BSCBFAH.
	GPT16E0_GTICBSR_BSCBFAH = 0x8000
	// GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICBSR_BSCBFAH_0 = 0x0
	// GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
	GPT16E0_GTICBSR_BSCBFAH_1 = 0x1
	// Position of BSELCA field.
	GPT16E0_GTICBSR_BSELCA_Pos = 0x10
	// Bit mask of BSELCA field.
	GPT16E0_GTICBSR_BSELCA_Msk = 0x10000
	// Bit BSELCA.
	GPT16E0_GTICBSR_BSELCA = 0x10000
	// GTCCRB input capture disabled at the ELC_GPTA input
	GPT16E0_GTICBSR_BSELCA_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTA input
	GPT16E0_GTICBSR_BSELCA_1 = 0x1
	// Position of BSELCB field.
	GPT16E0_GTICBSR_BSELCB_Pos = 0x11
	// Bit mask of BSELCB field.
	GPT16E0_GTICBSR_BSELCB_Msk = 0x20000
	// Bit BSELCB.
	GPT16E0_GTICBSR_BSELCB = 0x20000
	// GTCCRB input capture disabled at the ELC_GPTB input
	GPT16E0_GTICBSR_BSELCB_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTB input
	GPT16E0_GTICBSR_BSELCB_1 = 0x1
	// Position of BSELCC field.
	GPT16E0_GTICBSR_BSELCC_Pos = 0x12
	// Bit mask of BSELCC field.
	GPT16E0_GTICBSR_BSELCC_Msk = 0x40000
	// Bit BSELCC.
	GPT16E0_GTICBSR_BSELCC = 0x40000
	// GTCCRB input capture disabled at the ELC_GPTC input
	GPT16E0_GTICBSR_BSELCC_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTC input
	GPT16E0_GTICBSR_BSELCC_1 = 0x1
	// Position of BSELCD field.
	GPT16E0_GTICBSR_BSELCD_Pos = 0x13
	// Bit mask of BSELCD field.
	GPT16E0_GTICBSR_BSELCD_Msk = 0x80000
	// Bit BSELCD.
	GPT16E0_GTICBSR_BSELCD = 0x80000
	// GTCCRB input capture disabled at the ELC_GPTD input
	GPT16E0_GTICBSR_BSELCD_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTD input
	GPT16E0_GTICBSR_BSELCD_1 = 0x1
	// Position of BSELCE field.
	GPT16E0_GTICBSR_BSELCE_Pos = 0x14
	// Bit mask of BSELCE field.
	GPT16E0_GTICBSR_BSELCE_Msk = 0x100000
	// Bit BSELCE.
	GPT16E0_GTICBSR_BSELCE = 0x100000
	// GTCCRB input capture disabled at the ELC_GPTE input
	GPT16E0_GTICBSR_BSELCE_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTE input
	GPT16E0_GTICBSR_BSELCE_1 = 0x1
	// Position of BSELCF field.
	GPT16E0_GTICBSR_BSELCF_Pos = 0x15
	// Bit mask of BSELCF field.
	GPT16E0_GTICBSR_BSELCF_Msk = 0x200000
	// Bit BSELCF.
	GPT16E0_GTICBSR_BSELCF = 0x200000
	// GTCCRB input capture disabled at the ELC_GPTF input
	GPT16E0_GTICBSR_BSELCF_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTF input
	GPT16E0_GTICBSR_BSELCF_1 = 0x1
	// Position of BSELCG field.
	GPT16E0_GTICBSR_BSELCG_Pos = 0x16
	// Bit mask of BSELCG field.
	GPT16E0_GTICBSR_BSELCG_Msk = 0x400000
	// Bit BSELCG.
	GPT16E0_GTICBSR_BSELCG = 0x400000
	// GTCCRB input capture disabled at the ELC_GPTG input
	GPT16E0_GTICBSR_BSELCG_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTG input
	GPT16E0_GTICBSR_BSELCG_1 = 0x1
	// Position of BSELCH field.
	GPT16E0_GTICBSR_BSELCH_Pos = 0x17
	// Bit mask of BSELCH field.
	GPT16E0_GTICBSR_BSELCH_Msk = 0x800000
	// Bit BSELCH.
	GPT16E0_GTICBSR_BSELCH = 0x800000
	// GTCCRB input capture disabled at the ELC_GPTH input
	GPT16E0_GTICBSR_BSELCH_0 = 0x0
	// GTCCRB input capture enabled at the ELC_GPTH input
	GPT16E0_GTICBSR_BSELCH_1 = 0x1

	// GTCR: General PWM Timer Control Register
	// Position of CST field.
	GPT16E0_GTCR_CST_Pos = 0x0
	// Bit mask of CST field.
	GPT16E0_GTCR_CST_Msk = 0x1
	// Bit CST.
	GPT16E0_GTCR_CST = 0x1
	// Count operation is stopped
	GPT16E0_GTCR_CST_0 = 0x0
	// Count operation is performed
	GPT16E0_GTCR_CST_1 = 0x1
	// Position of MD field.
	GPT16E0_GTCR_MD_Pos = 0x10
	// Bit mask of MD field.
	GPT16E0_GTCR_MD_Msk = 0x70000
	// Saw-wave PWM mode (single buffer or double buffer possible)
	GPT16E0_GTCR_MD_000 = 0x0
	// Saw-wave one-shot pulse mode (fixed buffer operation)
	GPT16E0_GTCR_MD_001 = 0x1
	// Setting prohibited
	GPT16E0_GTCR_MD_010 = 0x2
	// Setting prohibited
	GPT16E0_GTCR_MD_011 = 0x3
	// Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible)
	GPT16E0_GTCR_MD_100 = 0x4
	// Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible)
	GPT16E0_GTCR_MD_101 = 0x5
	// Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation)
	GPT16E0_GTCR_MD_110 = 0x6
	// Setting prohibited
	GPT16E0_GTCR_MD_111 = 0x7
	// Position of TPCS field.
	GPT16E0_GTCR_TPCS_Pos = 0x17
	// Bit mask of TPCS field.
	GPT16E0_GTCR_TPCS_Msk = 0x7800000
	// PCLKD/1
	GPT16E0_GTCR_TPCS_0x0 = 0x0
	// PCLKD/2
	GPT16E0_GTCR_TPCS_0x1 = 0x1
	// PCLKD/4
	GPT16E0_GTCR_TPCS_0x2 = 0x2
	// PCLKD/8
	GPT16E0_GTCR_TPCS_0x3 = 0x3
	// PCLKD/16
	GPT16E0_GTCR_TPCS_0x4 = 0x4
	// PCLKD/32
	GPT16E0_GTCR_TPCS_0x5 = 0x5
	// PCLKD/64
	GPT16E0_GTCR_TPCS_0x6 = 0x6
	// Setting prohibited
	GPT16E0_GTCR_TPCS_0x7 = 0x7
	// PCLKD/256
	GPT16E0_GTCR_TPCS_0x8 = 0x8
	// Setting prohibited
	GPT16E0_GTCR_TPCS_0x9 = 0x9
	// PCLKD/1024
	GPT16E0_GTCR_TPCS_0xA = 0xa
	// Setting prohibited
	GPT16E0_GTCR_TPCS_0xB = 0xb
	// GTETRGA (Via the POEG)
	GPT16E0_GTCR_TPCS_0xC = 0xc
	// GTETRGB (Via the POEG)
	GPT16E0_GTCR_TPCS_0xD = 0xd
	// GTETRGC (Via the POEG)
	GPT16E0_GTCR_TPCS_0xE = 0xe
	// GTETRGD (Via the POEG)
	GPT16E0_GTCR_TPCS_0xF = 0xf

	// GTUDDTYC: General PWM Timer Count Direction and Duty Setting Register
	// Position of UD field.
	GPT16E0_GTUDDTYC_UD_Pos = 0x0
	// Bit mask of UD field.
	GPT16E0_GTUDDTYC_UD_Msk = 0x1
	// Bit UD.
	GPT16E0_GTUDDTYC_UD = 0x1
	// GTCNT counts down
	GPT16E0_GTUDDTYC_UD_0 = 0x0
	// GTCNT counts up
	GPT16E0_GTUDDTYC_UD_1 = 0x1
	// Position of UDF field.
	GPT16E0_GTUDDTYC_UDF_Pos = 0x1
	// Bit mask of UDF field.
	GPT16E0_GTUDDTYC_UDF_Msk = 0x2
	// Bit UDF.
	GPT16E0_GTUDDTYC_UDF = 0x2
	// Not forcibly set
	GPT16E0_GTUDDTYC_UDF_0 = 0x0
	// Forcibly set
	GPT16E0_GTUDDTYC_UDF_1 = 0x1
	// Position of OADTY field.
	GPT16E0_GTUDDTYC_OADTY_Pos = 0x10
	// Bit mask of OADTY field.
	GPT16E0_GTUDDTYC_OADTY_Msk = 0x30000
	// GTIOCnA pin duty depends on the compare match
	GPT16E0_GTUDDTYC_OADTY_00 = 0x0
	// GTIOCnA pin duty depends on the compare match
	GPT16E0_GTUDDTYC_OADTY_01 = 0x1
	// GTIOCnA pin duty 0%
	GPT16E0_GTUDDTYC_OADTY_10 = 0x2
	// GTIOCnA pin duty 100%
	GPT16E0_GTUDDTYC_OADTY_11 = 0x3
	// Position of OADTYF field.
	GPT16E0_GTUDDTYC_OADTYF_Pos = 0x12
	// Bit mask of OADTYF field.
	GPT16E0_GTUDDTYC_OADTYF_Msk = 0x40000
	// Bit OADTYF.
	GPT16E0_GTUDDTYC_OADTYF = 0x40000
	// Not forcibly set
	GPT16E0_GTUDDTYC_OADTYF_0 = 0x0
	// Forcibly set
	GPT16E0_GTUDDTYC_OADTYF_1 = 0x1
	// Position of OADTYR field.
	GPT16E0_GTUDDTYC_OADTYR_Pos = 0x13
	// Bit mask of OADTYR field.
	GPT16E0_GTUDDTYC_OADTYR_Msk = 0x80000
	// Bit OADTYR.
	GPT16E0_GTUDDTYC_OADTYR = 0x80000
	// The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting.
	GPT16E0_GTUDDTYC_OADTYR_0 = 0x0
	// The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting.
	GPT16E0_GTUDDTYC_OADTYR_1 = 0x1
	// Position of OBDTY field.
	GPT16E0_GTUDDTYC_OBDTY_Pos = 0x18
	// Bit mask of OBDTY field.
	GPT16E0_GTUDDTYC_OBDTY_Msk = 0x3000000
	// GTIOCnB pin duty depends on the compare match
	GPT16E0_GTUDDTYC_OBDTY_00 = 0x0
	// GTIOCnB pin duty depends on the compare match
	GPT16E0_GTUDDTYC_OBDTY_01 = 0x1
	// GTIOCnB pin duty 0%
	GPT16E0_GTUDDTYC_OBDTY_10 = 0x2
	// GTIOCnB pin duty 100%
	GPT16E0_GTUDDTYC_OBDTY_11 = 0x3
	// Position of OBDTYF field.
	GPT16E0_GTUDDTYC_OBDTYF_Pos = 0x1a
	// Bit mask of OBDTYF field.
	GPT16E0_GTUDDTYC_OBDTYF_Msk = 0x4000000
	// Bit OBDTYF.
	GPT16E0_GTUDDTYC_OBDTYF = 0x4000000
	// Not forcibly set
	GPT16E0_GTUDDTYC_OBDTYF_0 = 0x0
	// Forcibly set
	GPT16E0_GTUDDTYC_OBDTYF_1 = 0x1
	// Position of OBDTYR field.
	GPT16E0_GTUDDTYC_OBDTYR_Pos = 0x1b
	// Bit mask of OBDTYR field.
	GPT16E0_GTUDDTYC_OBDTYR_Msk = 0x8000000
	// Bit OBDTYR.
	GPT16E0_GTUDDTYC_OBDTYR = 0x8000000
	// The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting.
	GPT16E0_GTUDDTYC_OBDTYR_0 = 0x0
	// The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting.
	GPT16E0_GTUDDTYC_OBDTYR_1 = 0x1

	// GTIOR: General PWM Timer I/O Control Register
	// Position of GTIOA field.
	GPT16E0_GTIOR_GTIOA_Pos = 0x0
	// Bit mask of GTIOA field.
	GPT16E0_GTIOR_GTIOA_Msk = 0x1f
	// Position of OADFLT field.
	GPT16E0_GTIOR_OADFLT_Pos = 0x6
	// Bit mask of OADFLT field.
	GPT16E0_GTIOR_OADFLT_Msk = 0x40
	// Bit OADFLT.
	GPT16E0_GTIOR_OADFLT = 0x40
	// The GTIOCnA pin outputs low when counting stops
	GPT16E0_GTIOR_OADFLT_0 = 0x0
	// The GTIOCnA pin outputs high when counting stops
	GPT16E0_GTIOR_OADFLT_1 = 0x1
	// Position of OAHLD field.
	GPT16E0_GTIOR_OAHLD_Pos = 0x7
	// Bit mask of OAHLD field.
	GPT16E0_GTIOR_OAHLD_Msk = 0x80
	// Bit OAHLD.
	GPT16E0_GTIOR_OAHLD = 0x80
	// The GTIOCnA pin output level at the start or stop of counting depends on the register setting
	GPT16E0_GTIOR_OAHLD_0 = 0x0
	// The GTIOCnA pin output level is retained at the start or stop of counting
	GPT16E0_GTIOR_OAHLD_1 = 0x1
	// Position of OAE field.
	GPT16E0_GTIOR_OAE_Pos = 0x8
	// Bit mask of OAE field.
	GPT16E0_GTIOR_OAE_Msk = 0x100
	// Bit OAE.
	GPT16E0_GTIOR_OAE = 0x100
	// Output is disabled
	GPT16E0_GTIOR_OAE_0 = 0x0
	// Output is enabled
	GPT16E0_GTIOR_OAE_1 = 0x1
	// Position of OADF field.
	GPT16E0_GTIOR_OADF_Pos = 0x9
	// Bit mask of OADF field.
	GPT16E0_GTIOR_OADF_Msk = 0x600
	// None of the below options are specified
	GPT16E0_GTIOR_OADF_00 = 0x0
	// GTIOCnA pin is set to Hi-Z in response to controlling the output negation
	GPT16E0_GTIOR_OADF_01 = 0x1
	// GTIOCnA pin is set to 0 in response to controlling the output negation
	GPT16E0_GTIOR_OADF_10 = 0x2
	// GTIOCnA pin is set to 1 in response to controlling the output negation
	GPT16E0_GTIOR_OADF_11 = 0x3
	// Position of NFAEN field.
	GPT16E0_GTIOR_NFAEN_Pos = 0xd
	// Bit mask of NFAEN field.
	GPT16E0_GTIOR_NFAEN_Msk = 0x2000
	// Bit NFAEN.
	GPT16E0_GTIOR_NFAEN = 0x2000
	// The noise filter for the GTIOCnA pin is disabled
	GPT16E0_GTIOR_NFAEN_0 = 0x0
	// The noise filter for the GTIOCnA pin is enabled
	GPT16E0_GTIOR_NFAEN_1 = 0x1
	// Position of NFCSA field.
	GPT16E0_GTIOR_NFCSA_Pos = 0xe
	// Bit mask of NFCSA field.
	GPT16E0_GTIOR_NFCSA_Msk = 0xc000
	// PCLKD/1
	GPT16E0_GTIOR_NFCSA_00 = 0x0
	// PCLKD/4
	GPT16E0_GTIOR_NFCSA_01 = 0x1
	// PCLKD/16
	GPT16E0_GTIOR_NFCSA_10 = 0x2
	// PCLKD/64
	GPT16E0_GTIOR_NFCSA_11 = 0x3
	// Position of GTIOB field.
	GPT16E0_GTIOR_GTIOB_Pos = 0x10
	// Bit mask of GTIOB field.
	GPT16E0_GTIOR_GTIOB_Msk = 0x1f0000
	// Position of OBDFLT field.
	GPT16E0_GTIOR_OBDFLT_Pos = 0x16
	// Bit mask of OBDFLT field.
	GPT16E0_GTIOR_OBDFLT_Msk = 0x400000
	// Bit OBDFLT.
	GPT16E0_GTIOR_OBDFLT = 0x400000
	// The GTIOCnB pin outputs low when counting stops
	GPT16E0_GTIOR_OBDFLT_0 = 0x0
	// The GTIOCnB pin outputs high when counting stops
	GPT16E0_GTIOR_OBDFLT_1 = 0x1
	// Position of OBHLD field.
	GPT16E0_GTIOR_OBHLD_Pos = 0x17
	// Bit mask of OBHLD field.
	GPT16E0_GTIOR_OBHLD_Msk = 0x800000
	// Bit OBHLD.
	GPT16E0_GTIOR_OBHLD = 0x800000
	// The GTIOCnB pin output level at the start/stop of counting depends on the register setting
	GPT16E0_GTIOR_OBHLD_0 = 0x0
	// The GTIOCnB pin output level is retained at the start/stop of counting
	GPT16E0_GTIOR_OBHLD_1 = 0x1
	// Position of OBE field.
	GPT16E0_GTIOR_OBE_Pos = 0x18
	// Bit mask of OBE field.
	GPT16E0_GTIOR_OBE_Msk = 0x1000000
	// Bit OBE.
	GPT16E0_GTIOR_OBE = 0x1000000
	// Output is disabled
	GPT16E0_GTIOR_OBE_0 = 0x0
	// Output is enabled
	GPT16E0_GTIOR_OBE_1 = 0x1
	// Position of OBDF field.
	GPT16E0_GTIOR_OBDF_Pos = 0x19
	// Bit mask of OBDF field.
	GPT16E0_GTIOR_OBDF_Msk = 0x6000000
	// None of the below options are specified
	GPT16E0_GTIOR_OBDF_00 = 0x0
	// GTIOCnB pin is set to Hi-Z in response to controlling the output negation
	GPT16E0_GTIOR_OBDF_01 = 0x1
	// GTIOCnB pin is set to 0 in response to controlling the output negation
	GPT16E0_GTIOR_OBDF_10 = 0x2
	// GTIOCnB pin is set to 1 in response to controlling the output negation
	GPT16E0_GTIOR_OBDF_11 = 0x3
	// Position of NFBEN field.
	GPT16E0_GTIOR_NFBEN_Pos = 0x1d
	// Bit mask of NFBEN field.
	GPT16E0_GTIOR_NFBEN_Msk = 0x20000000
	// Bit NFBEN.
	GPT16E0_GTIOR_NFBEN = 0x20000000
	// The noise filter for the GTIOCnB pin is disabled
	GPT16E0_GTIOR_NFBEN_0 = 0x0
	// The noise filter for the GTIOCnB pin is enabled
	GPT16E0_GTIOR_NFBEN_1 = 0x1
	// Position of NFCSB field.
	GPT16E0_GTIOR_NFCSB_Pos = 0x1e
	// Bit mask of NFCSB field.
	GPT16E0_GTIOR_NFCSB_Msk = 0xc0000000
	// PCLKD/1
	GPT16E0_GTIOR_NFCSB_00 = 0x0
	// PCLKD/4
	GPT16E0_GTIOR_NFCSB_01 = 0x1
	// PCLKD/16
	GPT16E0_GTIOR_NFCSB_10 = 0x2
	// PCLKD/64
	GPT16E0_GTIOR_NFCSB_11 = 0x3

	// GTINTAD: General PWM Timer Interrupt Output Setting Register
	// Position of GRP field.
	GPT16E0_GTINTAD_GRP_Pos = 0x18
	// Bit mask of GRP field.
	GPT16E0_GTINTAD_GRP_Msk = 0x3000000
	// Group A output disable request is selected
	GPT16E0_GTINTAD_GRP_00 = 0x0
	// Group B output disable request is selected
	GPT16E0_GTINTAD_GRP_01 = 0x1
	// Group C output disable request is selected
	GPT16E0_GTINTAD_GRP_10 = 0x2
	// Group D output disable request is selected
	GPT16E0_GTINTAD_GRP_11 = 0x3
	// Position of GRPABH field.
	GPT16E0_GTINTAD_GRPABH_Pos = 0x1d
	// Bit mask of GRPABH field.
	GPT16E0_GTINTAD_GRPABH_Msk = 0x20000000
	// Bit GRPABH.
	GPT16E0_GTINTAD_GRPABH = 0x20000000
	// Same time output level high disable request disabled
	GPT16E0_GTINTAD_GRPABH_0 = 0x0
	// Same time output level high disable request enabled
	GPT16E0_GTINTAD_GRPABH_1 = 0x1
	// Position of GRPABL field.
	GPT16E0_GTINTAD_GRPABL_Pos = 0x1e
	// Bit mask of GRPABL field.
	GPT16E0_GTINTAD_GRPABL_Msk = 0x40000000
	// Bit GRPABL.
	GPT16E0_GTINTAD_GRPABL = 0x40000000
	// Same time output level low disable request disabled
	GPT16E0_GTINTAD_GRPABL_0 = 0x0
	// Same time output level low disable request enabled
	GPT16E0_GTINTAD_GRPABL_1 = 0x1

	// GTST: General PWM Timer Status Register
	// Position of TCFA field.
	GPT16E0_GTST_TCFA_Pos = 0x0
	// Bit mask of TCFA field.
	GPT16E0_GTST_TCFA_Msk = 0x1
	// Bit TCFA.
	GPT16E0_GTST_TCFA = 0x1
	// No input capture/compare match of GTCCRA is generated
	GPT16E0_GTST_TCFA_0 = 0x0
	// An input capture/compare match of GTCCRA is generated
	GPT16E0_GTST_TCFA_1 = 0x1
	// Position of TCFB field.
	GPT16E0_GTST_TCFB_Pos = 0x1
	// Bit mask of TCFB field.
	GPT16E0_GTST_TCFB_Msk = 0x2
	// Bit TCFB.
	GPT16E0_GTST_TCFB = 0x2
	// No input capture/compare match of GTCCRB is generated
	GPT16E0_GTST_TCFB_0 = 0x0
	// An input capture/compare match of GTCCRB is generated
	GPT16E0_GTST_TCFB_1 = 0x1
	// Position of TCFC field.
	GPT16E0_GTST_TCFC_Pos = 0x2
	// Bit mask of TCFC field.
	GPT16E0_GTST_TCFC_Msk = 0x4
	// Bit TCFC.
	GPT16E0_GTST_TCFC = 0x4
	// No compare match of GTCCRC is generated
	GPT16E0_GTST_TCFC_0 = 0x0
	// A compare match of GTCCRC is generated
	GPT16E0_GTST_TCFC_1 = 0x1
	// Position of TCFD field.
	GPT16E0_GTST_TCFD_Pos = 0x3
	// Bit mask of TCFD field.
	GPT16E0_GTST_TCFD_Msk = 0x8
	// Bit TCFD.
	GPT16E0_GTST_TCFD = 0x8
	// No compare match of GTCCRD is generated
	GPT16E0_GTST_TCFD_0 = 0x0
	// A compare match of GTCCRD is generated
	GPT16E0_GTST_TCFD_1 = 0x1
	// Position of TCFE field.
	GPT16E0_GTST_TCFE_Pos = 0x4
	// Bit mask of TCFE field.
	GPT16E0_GTST_TCFE_Msk = 0x10
	// Bit TCFE.
	GPT16E0_GTST_TCFE = 0x10
	// No compare match of GTCCRE is generated
	GPT16E0_GTST_TCFE_0 = 0x0
	// A compare match of GTCCRE is generated
	GPT16E0_GTST_TCFE_1 = 0x1
	// Position of TCFF field.
	GPT16E0_GTST_TCFF_Pos = 0x5
	// Bit mask of TCFF field.
	GPT16E0_GTST_TCFF_Msk = 0x20
	// Bit TCFF.
	GPT16E0_GTST_TCFF = 0x20
	// No compare match of GTCCRF is generated
	GPT16E0_GTST_TCFF_0 = 0x0
	// A compare match of GTCCRF is generated
	GPT16E0_GTST_TCFF_1 = 0x1
	// Position of TCFPO field.
	GPT16E0_GTST_TCFPO_Pos = 0x6
	// Bit mask of TCFPO field.
	GPT16E0_GTST_TCFPO_Msk = 0x40
	// Bit TCFPO.
	GPT16E0_GTST_TCFPO = 0x40
	// No overflow (crest) occurred
	GPT16E0_GTST_TCFPO_0 = 0x0
	// An overflow (crest) occurred
	GPT16E0_GTST_TCFPO_1 = 0x1
	// Position of TCFPU field.
	GPT16E0_GTST_TCFPU_Pos = 0x7
	// Bit mask of TCFPU field.
	GPT16E0_GTST_TCFPU_Msk = 0x80
	// Bit TCFPU.
	GPT16E0_GTST_TCFPU = 0x80
	// No underflow (trough) occurred
	GPT16E0_GTST_TCFPU_0 = 0x0
	// An underflow (trough) occurred
	GPT16E0_GTST_TCFPU_1 = 0x1
	// Position of ITCNT field.
	GPT16E0_GTST_ITCNT_Pos = 0x8
	// Bit mask of ITCNT field.
	GPT16E0_GTST_ITCNT_Msk = 0x700
	// Position of TUCF field.
	GPT16E0_GTST_TUCF_Pos = 0xf
	// Bit mask of TUCF field.
	GPT16E0_GTST_TUCF_Msk = 0x8000
	// Bit TUCF.
	GPT16E0_GTST_TUCF = 0x8000
	// GTCNT counter counts downward
	GPT16E0_GTST_TUCF_0 = 0x0
	// GTCNT counter counts upward
	GPT16E0_GTST_TUCF_1 = 0x1
	// Position of ADTRAUF field.
	GPT16E0_GTST_ADTRAUF_Pos = 0x10
	// Bit mask of ADTRAUF field.
	GPT16E0_GTST_ADTRAUF_Msk = 0x10000
	// Bit ADTRAUF.
	GPT16E0_GTST_ADTRAUF = 0x10000
	// No GTADTRA register compare match has occurred in up-counting
	GPT16E0_GTST_ADTRAUF_0 = 0x0
	// A GTADTRA register compare match has occurred in up-counting
	GPT16E0_GTST_ADTRAUF_1 = 0x1
	// Position of ADTRADF field.
	GPT16E0_GTST_ADTRADF_Pos = 0x11
	// Bit mask of ADTRADF field.
	GPT16E0_GTST_ADTRADF_Msk = 0x20000
	// Bit ADTRADF.
	GPT16E0_GTST_ADTRADF = 0x20000
	// No GTADTRA register compare match has occurred in down-counting
	GPT16E0_GTST_ADTRADF_0 = 0x0
	// A GTADTRA register compare match has occurred in down-counting
	GPT16E0_GTST_ADTRADF_1 = 0x1
	// Position of ADTRBUF field.
	GPT16E0_GTST_ADTRBUF_Pos = 0x12
	// Bit mask of ADTRBUF field.
	GPT16E0_GTST_ADTRBUF_Msk = 0x40000
	// Bit ADTRBUF.
	GPT16E0_GTST_ADTRBUF = 0x40000
	// No GTADTRB register compare match has occurred in up-counting
	GPT16E0_GTST_ADTRBUF_0 = 0x0
	// A GTADTRB register compare match has occurred in up-counting
	GPT16E0_GTST_ADTRBUF_1 = 0x1
	// Position of ADTRBDF field.
	GPT16E0_GTST_ADTRBDF_Pos = 0x13
	// Bit mask of ADTRBDF field.
	GPT16E0_GTST_ADTRBDF_Msk = 0x80000
	// Bit ADTRBDF.
	GPT16E0_GTST_ADTRBDF = 0x80000
	// No GTADTRB register compare match has occurred in down-counting
	GPT16E0_GTST_ADTRBDF_0 = 0x0
	// A GTADTRB register compare match has occurred in down-counting
	GPT16E0_GTST_ADTRBDF_1 = 0x1
	// Position of ODF field.
	GPT16E0_GTST_ODF_Pos = 0x18
	// Bit mask of ODF field.
	GPT16E0_GTST_ODF_Msk = 0x1000000
	// Bit ODF.
	GPT16E0_GTST_ODF = 0x1000000
	// No output disable request is generated
	GPT16E0_GTST_ODF_0 = 0x0
	// An output disable request is generated
	GPT16E0_GTST_ODF_1 = 0x1
	// Position of DTEF field.
	GPT16E0_GTST_DTEF_Pos = 0x1c
	// Bit mask of DTEF field.
	GPT16E0_GTST_DTEF_Msk = 0x10000000
	// Bit DTEF.
	GPT16E0_GTST_DTEF = 0x10000000
	// No dead time error has occurred
	GPT16E0_GTST_DTEF_0 = 0x0
	// A dead time error has occurred
	GPT16E0_GTST_DTEF_1 = 0x1
	// Position of OABHF field.
	GPT16E0_GTST_OABHF_Pos = 0x1d
	// Bit mask of OABHF field.
	GPT16E0_GTST_OABHF_Msk = 0x20000000
	// Bit OABHF.
	GPT16E0_GTST_OABHF = 0x20000000
	// No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred
	GPT16E0_GTST_OABHF_0 = 0x0
	// A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred
	GPT16E0_GTST_OABHF_1 = 0x1
	// Position of OABLF field.
	GPT16E0_GTST_OABLF_Pos = 0x1e
	// Bit mask of OABLF field.
	GPT16E0_GTST_OABLF_Msk = 0x40000000
	// Bit OABLF.
	GPT16E0_GTST_OABLF = 0x40000000
	// No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred
	GPT16E0_GTST_OABLF_0 = 0x0
	// A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred
	GPT16E0_GTST_OABLF_1 = 0x1
	// Position of PCF field.
	GPT16E0_GTST_PCF_Pos = 0x1f
	// Bit mask of PCF field.
	GPT16E0_GTST_PCF_Msk = 0x80000000
	// Bit PCF.
	GPT16E0_GTST_PCF = 0x80000000
	// No period count function finish has occurred
	GPT16E0_GTST_PCF_0 = 0x0
	// A period count function finish has occurred
	GPT16E0_GTST_PCF_1 = 0x1

	// GTBER: General PWM Timer Buffer Enable Register
	// Position of BD0 field.
	GPT16E0_GTBER_BD0_Pos = 0x0
	// Bit mask of BD0 field.
	GPT16E0_GTBER_BD0_Msk = 0x1
	// Bit BD0.
	GPT16E0_GTBER_BD0 = 0x1
	// Buffer operation is enabled
	GPT16E0_GTBER_BD0_0 = 0x0
	// Buffer operation is disabled
	GPT16E0_GTBER_BD0_1 = 0x1
	// Position of BD1 field.
	GPT16E0_GTBER_BD1_Pos = 0x1
	// Bit mask of BD1 field.
	GPT16E0_GTBER_BD1_Msk = 0x2
	// Bit BD1.
	GPT16E0_GTBER_BD1 = 0x2
	// Buffer operation is enabled
	GPT16E0_GTBER_BD1_0 = 0x0
	// Buffer operation is disabled
	GPT16E0_GTBER_BD1_1 = 0x1
	// Position of BD2 field.
	GPT16E0_GTBER_BD2_Pos = 0x2
	// Bit mask of BD2 field.
	GPT16E0_GTBER_BD2_Msk = 0x4
	// Bit BD2.
	GPT16E0_GTBER_BD2 = 0x4
	// Buffer operation is enabled
	GPT16E0_GTBER_BD2_0 = 0x0
	// Buffer operation is disabled
	GPT16E0_GTBER_BD2_1 = 0x1
	// Position of BD3 field.
	GPT16E0_GTBER_BD3_Pos = 0x3
	// Bit mask of BD3 field.
	GPT16E0_GTBER_BD3_Msk = 0x8
	// Bit BD3.
	GPT16E0_GTBER_BD3 = 0x8
	// Buffer operation is enabled
	GPT16E0_GTBER_BD3_0 = 0x0
	// Buffer operation is disabled
	GPT16E0_GTBER_BD3_1 = 0x1
	// Position of CCRA field.
	GPT16E0_GTBER_CCRA_Pos = 0x10
	// Bit mask of CCRA field.
	GPT16E0_GTBER_CCRA_Msk = 0x30000
	// No buffer operation
	GPT16E0_GTBER_CCRA_00 = 0x0
	// Single buffer operation (GTCCRA ↔ GTCCRC)
	GPT16E0_GTBER_CCRA_01 = 0x1
	// Double buffer operation (GTCCRA ↔ GTCCRD)
	GPT16E0_GTBER_CCRA_Others = 0x2
	// Position of CCRB field.
	GPT16E0_GTBER_CCRB_Pos = 0x12
	// Bit mask of CCRB field.
	GPT16E0_GTBER_CCRB_Msk = 0xc0000
	// No buffer operation
	GPT16E0_GTBER_CCRB_00 = 0x0
	// Single buffer operation (GTCCRB ↔ GTCCRE)
	GPT16E0_GTBER_CCRB_01 = 0x1
	// Double buffer operation (GTCCRB ↔ GTCCRE ↔ GTCCRF)
	GPT16E0_GTBER_CCRB_Others = 0x2
	// Position of PR field.
	GPT16E0_GTBER_PR_Pos = 0x14
	// Bit mask of PR field.
	GPT16E0_GTBER_PR_Msk = 0x300000
	// No buffer operation
	GPT16E0_GTBER_PR_00 = 0x0
	// Single buffer operation (GTPBR → GTPR)
	GPT16E0_GTBER_PR_01 = 0x1
	// Double buffer operation (GTPDBR → GTPBR → GTPR)
	GPT16E0_GTBER_PR_Others = 0x2
	// Position of CCRSWT field.
	GPT16E0_GTBER_CCRSWT_Pos = 0x16
	// Bit mask of CCRSWT field.
	GPT16E0_GTBER_CCRSWT_Msk = 0x400000
	// Bit CCRSWT.
	GPT16E0_GTBER_CCRSWT = 0x400000
	// Position of ADTTA field.
	GPT16E0_GTBER_ADTTA_Pos = 0x18
	// Bit mask of ADTTA field.
	GPT16E0_GTBER_ADTTA_Msk = 0x3000000
	// In triangle wave, no transfer. In saw-wave mode, no transfer.
	GPT16E0_GTBER_ADTTA_00 = 0x0
	// In triangle wave, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.
	GPT16E0_GTBER_ADTTA_01 = 0x1
	// In triangle wave, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.
	GPT16E0_GTBER_ADTTA_10 = 0x2
	// In triangle wave, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.
	GPT16E0_GTBER_ADTTA_11 = 0x3
	// Position of ADTDA field.
	GPT16E0_GTBER_ADTDA_Pos = 0x1a
	// Bit mask of ADTDA field.
	GPT16E0_GTBER_ADTDA_Msk = 0x4000000
	// Bit ADTDA.
	GPT16E0_GTBER_ADTDA = 0x4000000
	// Single buffer operation (GTADTBRA → GTADTRA)
	GPT16E0_GTBER_ADTDA_0 = 0x0
	// Double buffer operation (GTADTDBRA → GTADTBRA → GTADTRA)
	GPT16E0_GTBER_ADTDA_1 = 0x1
	// Position of ADTTB field.
	GPT16E0_GTBER_ADTTB_Pos = 0x1c
	// Bit mask of ADTTB field.
	GPT16E0_GTBER_ADTTB_Msk = 0x30000000
	// In triangle wave, no transfer. In saw-wave mode, no transfer.
	GPT16E0_GTBER_ADTTB_00 = 0x0
	// In triangle wave, transfer at crest. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.
	GPT16E0_GTBER_ADTTB_01 = 0x1
	// In triangle wave, transfer at trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.
	GPT16E0_GTBER_ADTTB_10 = 0x2
	// In triangle wave, transfer at both crest and trough. In saw-wave mode, transfer at underflow (in down-counting), overflow (in up-counting), or counter clearing.
	GPT16E0_GTBER_ADTTB_11 = 0x3
	// Position of ADTDB field.
	GPT16E0_GTBER_ADTDB_Pos = 0x1e
	// Bit mask of ADTDB field.
	GPT16E0_GTBER_ADTDB_Msk = 0x40000000
	// Bit ADTDB.
	GPT16E0_GTBER_ADTDB = 0x40000000
	// Single buffer operation (GTADTBRB → GTADTRB)
	GPT16E0_GTBER_ADTDB_0 = 0x0
	// Double buffer operation (GTADTDBRB → GTADTRB)
	GPT16E0_GTBER_ADTDB_1 = 0x1

	// GTITC: General PWM Timer Interrupt and A/D Conversion Start Request Skipping Setting Register
	// Position of ITLA field.
	GPT16E0_GTITC_ITLA_Pos = 0x0
	// Bit mask of ITLA field.
	GPT16E0_GTITC_ITLA_Msk = 0x1
	// Bit ITLA.
	GPT16E0_GTITC_ITLA = 0x1
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLA_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLA_1 = 0x1
	// Position of ITLB field.
	GPT16E0_GTITC_ITLB_Pos = 0x1
	// Bit mask of ITLB field.
	GPT16E0_GTITC_ITLB_Msk = 0x2
	// Bit ITLB.
	GPT16E0_GTITC_ITLB = 0x2
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLB_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLB_1 = 0x1
	// Position of ITLC field.
	GPT16E0_GTITC_ITLC_Pos = 0x2
	// Bit mask of ITLC field.
	GPT16E0_GTITC_ITLC_Msk = 0x4
	// Bit ITLC.
	GPT16E0_GTITC_ITLC = 0x4
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLC_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLC_1 = 0x1
	// Position of ITLD field.
	GPT16E0_GTITC_ITLD_Pos = 0x3
	// Bit mask of ITLD field.
	GPT16E0_GTITC_ITLD_Msk = 0x8
	// Bit ITLD.
	GPT16E0_GTITC_ITLD = 0x8
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLD_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLD_1 = 0x1
	// Position of ITLE field.
	GPT16E0_GTITC_ITLE_Pos = 0x4
	// Bit mask of ITLE field.
	GPT16E0_GTITC_ITLE_Msk = 0x10
	// Bit ITLE.
	GPT16E0_GTITC_ITLE = 0x10
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLE_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLE_1 = 0x1
	// Position of ITLF field.
	GPT16E0_GTITC_ITLF_Pos = 0x5
	// Bit mask of ITLF field.
	GPT16E0_GTITC_ITLF_Msk = 0x20
	// Bit ITLF.
	GPT16E0_GTITC_ITLF = 0x20
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLF_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ITLF_1 = 0x1
	// Position of IVTC field.
	GPT16E0_GTITC_IVTC_Pos = 0x6
	// Bit mask of IVTC field.
	GPT16E0_GTITC_IVTC_Msk = 0xc0
	// Skipping is not performed
	GPT16E0_GTITC_IVTC_00 = 0x0
	// Both overflow and underflow for saw waves and crest for triangle waves are counted and skipped
	GPT16E0_GTITC_IVTC_01 = 0x1
	// Both overflow and underflow for saw waves and trough for triangle waves are counted and skipped
	GPT16E0_GTITC_IVTC_10 = 0x2
	// Position of IVTT field.
	GPT16E0_GTITC_IVTT_Pos = 0x8
	// Bit mask of IVTT field.
	GPT16E0_GTITC_IVTT_Msk = 0x700
	// Skipping is not performed
	GPT16E0_GTITC_IVTT_000 = 0x0
	// Skipping count of 1
	GPT16E0_GTITC_IVTT_001 = 0x1
	// Skipping count of 2
	GPT16E0_GTITC_IVTT_010 = 0x2
	// Skipping count of 3
	GPT16E0_GTITC_IVTT_011 = 0x3
	// Skipping count of 4
	GPT16E0_GTITC_IVTT_100 = 0x4
	// Skipping count of 5
	GPT16E0_GTITC_IVTT_101 = 0x5
	// Skipping count of 6
	GPT16E0_GTITC_IVTT_110 = 0x6
	// Skipping count of 7
	GPT16E0_GTITC_IVTT_111 = 0x7
	// Position of ADTAL field.
	GPT16E0_GTITC_ADTAL_Pos = 0xc
	// Bit mask of ADTAL field.
	GPT16E0_GTITC_ADTAL_Msk = 0x1000
	// Bit ADTAL.
	GPT16E0_GTITC_ADTAL = 0x1000
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ADTAL_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ADTAL_1 = 0x1
	// Position of ADTBL field.
	GPT16E0_GTITC_ADTBL_Pos = 0xe
	// Bit mask of ADTBL field.
	GPT16E0_GTITC_ADTBL_Msk = 0x4000
	// Bit ADTBL.
	GPT16E0_GTITC_ADTBL = 0x4000
	// Not linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ADTBL_0 = 0x0
	// Linked with GPTn_OVF/GPTn_UDF interrupt skipping function
	GPT16E0_GTITC_ADTBL_1 = 0x1

	// GTDTCR: General PWM Timer Dead Time Control Register
	// Position of TDE field.
	GPT16E0_GTDTCR_TDE_Pos = 0x0
	// Bit mask of TDE field.
	GPT16E0_GTDTCR_TDE_Msk = 0x1
	// Bit TDE.
	GPT16E0_GTDTCR_TDE = 0x1
	// GTCCRB is set without using DTDVU and GTDVD
	GPT16E0_GTDTCR_TDE_0 = 0x0
	// DTDVU and GTDVD are used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB
	GPT16E0_GTDTCR_TDE_1 = 0x1
	// Position of TDBUE field.
	GPT16E0_GTDTCR_TDBUE_Pos = 0x4
	// Bit mask of TDBUE field.
	GPT16E0_GTDTCR_TDBUE_Msk = 0x10
	// Bit TDBUE.
	GPT16E0_GTDTCR_TDBUE = 0x10
	// GTDVU register buffer operation is disabled
	GPT16E0_GTDTCR_TDBUE_0 = 0x0
	// GTDVU register buffer operation is enabled
	GPT16E0_GTDTCR_TDBUE_1 = 0x1
	// Position of TDBDE field.
	GPT16E0_GTDTCR_TDBDE_Pos = 0x5
	// Bit mask of TDBDE field.
	GPT16E0_GTDTCR_TDBDE_Msk = 0x20
	// Bit TDBDE.
	GPT16E0_GTDTCR_TDBDE = 0x20
	// GTDVD register buffer operation is disabled
	GPT16E0_GTDTCR_TDBDE_0 = 0x0
	// GTDVD register buffer operation is enabled
	GPT16E0_GTDTCR_TDBDE_1 = 0x1
	// Position of TDFER field.
	GPT16E0_GTDTCR_TDFER_Pos = 0x8
	// Bit mask of TDFER field.
	GPT16E0_GTDTCR_TDFER_Msk = 0x100
	// Bit TDFER.
	GPT16E0_GTDTCR_TDFER = 0x100
	// GTDVU and GTDVD registers are set separately.
	GPT16E0_GTDTCR_TDFER_0 = 0x0
	// The value written to GTDVU register is automatically set to GTDVD register
	GPT16E0_GTDTCR_TDFER_1 = 0x1

	// GTSOS: General PWM Timer Output Protection Function Status Register
	// Position of SOS field.
	GPT16E0_GTSOS_SOS_Pos = 0x0
	// Bit mask of SOS field.
	GPT16E0_GTSOS_SOS_Msk = 0x3
	// Normal operation
	GPT16E0_GTSOS_SOS_00 = 0x0
	// Protected state (GTCCRA = 0 is set during transfer at trough or crest)
	GPT16E0_GTSOS_SOS_01 = 0x1
	// Protected state (GTCCRA ≥ GTPR is set during transfer at trough)
	GPT16E0_GTSOS_SOS_10 = 0x2
	// Protected state (GTCCRA ≥ GTPR is set during transfer at crest)
	GPT16E0_GTSOS_SOS_11 = 0x3

	// GTSOTR: General PWM Timer Output Protection Function Temporary Release Register
	// Position of SOTR field.
	GPT16E0_GTSOTR_SOTR_Pos = 0x0
	// Bit mask of SOTR field.
	GPT16E0_GTSOTR_SOTR_Msk = 0x1
	// Bit SOTR.
	GPT16E0_GTSOTR_SOTR = 0x1
	// Protected state is not released
	GPT16E0_GTSOTR_SOTR_0 = 0x0
	// Protected state is released
	GPT16E0_GTSOTR_SOTR_1 = 0x1

	// GTADSMR: General PWM Timer A/D Conversion Start Request Signal Monitoring Register
	// Position of ADSMS0 field.
	GPT16E0_GTADSMR_ADSMS0_Pos = 0x0
	// Bit mask of ADSMS0 field.
	GPT16E0_GTADSMR_ADSMS0_Msk = 0x3
	// A/D conversion start request signal generated by the GTADTRA register during up-counting
	GPT16E0_GTADSMR_ADSMS0_00 = 0x0
	// A/D conversion start request signal generated by the GTADTRA register during down-counting
	GPT16E0_GTADSMR_ADSMS0_01 = 0x1
	// A/D conversion start request signal generated by the GTADTRB register during up-counting
	GPT16E0_GTADSMR_ADSMS0_10 = 0x2
	// A/D conversion start request signal generated by the GTADTRB register during down-counting
	GPT16E0_GTADSMR_ADSMS0_11 = 0x3
	// Position of ADSMEN0 field.
	GPT16E0_GTADSMR_ADSMEN0_Pos = 0x8
	// Bit mask of ADSMEN0 field.
	GPT16E0_GTADSMR_ADSMEN0_Msk = 0x100
	// Bit ADSMEN0.
	GPT16E0_GTADSMR_ADSMEN0 = 0x100
	// Output of A/D conversion start request signal monitor 0 is disabled
	GPT16E0_GTADSMR_ADSMEN0_0 = 0x0
	// Output of A/D conversion start request signal monitor 0 is enabled
	GPT16E0_GTADSMR_ADSMEN0_1 = 0x1
	// Position of ADSMS1 field.
	GPT16E0_GTADSMR_ADSMS1_Pos = 0x10
	// Bit mask of ADSMS1 field.
	GPT16E0_GTADSMR_ADSMS1_Msk = 0x30000
	// A/D conversion start request signal generated by the GTADTRA register during up-counting
	GPT16E0_GTADSMR_ADSMS1_00 = 0x0
	// A/D conversion start request signal generated by the GTADTRA register during down-counting
	GPT16E0_GTADSMR_ADSMS1_01 = 0x1
	// A/D conversion start request signal generated by the GTADTRB register during up-counting
	GPT16E0_GTADSMR_ADSMS1_10 = 0x2
	// A/D conversion start request signal generated by the GTADTRB register during down-counting
	GPT16E0_GTADSMR_ADSMS1_11 = 0x3
	// Position of ADSMEN1 field.
	GPT16E0_GTADSMR_ADSMEN1_Pos = 0x18
	// Bit mask of ADSMEN1 field.
	GPT16E0_GTADSMR_ADSMEN1_Msk = 0x1000000
	// Bit ADSMEN1.
	GPT16E0_GTADSMR_ADSMEN1 = 0x1000000
	// Output of A/D conversion start request signal monitor 1 is disabled
	GPT16E0_GTADSMR_ADSMEN1_0 = 0x0
	// Output of A/D conversion start request signal monitor 1 is enabled
	GPT16E0_GTADSMR_ADSMEN1_1 = 0x1

	// GTICLF: General PWM Timer Inter Channel Logical Operation Function Setting Register
	// Position of ICLFA field.
	GPT16E0_GTICLF_ICLFA_Pos = 0x0
	// Bit mask of ICLFA field.
	GPT16E0_GTICLF_ICLFA_Msk = 0x7
	// A (no delay)
	GPT16E0_GTICLF_ICLFA_000 = 0x0
	// NOT A (no delay)
	GPT16E0_GTICLF_ICLFA_001 = 0x1
	// C (1PCLKD delay)
	GPT16E0_GTICLF_ICLFA_010 = 0x2
	// NOT C (1PCLKD delay)
	GPT16E0_GTICLF_ICLFA_011 = 0x3
	// A AND C (1PCLKD delay)
	GPT16E0_GTICLF_ICLFA_100 = 0x4
	// A OR C (1PCLKD delay)
	GPT16E0_GTICLF_ICLFA_101 = 0x5
	// A EXOR C (1PCLKD delay)
	GPT16E0_GTICLF_ICLFA_110 = 0x6
	// A NOR C (1PCLKD delay)
	GPT16E0_GTICLF_ICLFA_111 = 0x7
	// Position of ICLFSELC field.
	GPT16E0_GTICLF_ICLFSELC_Pos = 0x4
	// Bit mask of ICLFSELC field.
	GPT16E0_GTICLF_ICLFSELC_Msk = 0x3f0
	// GTIOC0A
	GPT16E0_GTICLF_ICLFSELC_0x00 = 0x0
	// GTIOC0B
	GPT16E0_GTICLF_ICLFSELC_0x01 = 0x1
	// GTIOC1A
	GPT16E0_GTICLF_ICLFSELC_0x02 = 0x2
	// GTIOC1B
	GPT16E0_GTICLF_ICLFSELC_0x03 = 0x3
	// GTIOC2A
	GPT16E0_GTICLF_ICLFSELC_0x04 = 0x4
	// GTIOC2B
	GPT16E0_GTICLF_ICLFSELC_0x05 = 0x5
	// GTIOC3A
	GPT16E0_GTICLF_ICLFSELC_0x06 = 0x6
	// GTIOC3B
	GPT16E0_GTICLF_ICLFSELC_0x07 = 0x7
	// GTIOC4A
	GPT16E0_GTICLF_ICLFSELC_0x08 = 0x8
	// GTIOC4B
	GPT16E0_GTICLF_ICLFSELC_0x09 = 0x9
	// GTIOC5A
	GPT16E0_GTICLF_ICLFSELC_0x0A = 0xa
	// GTIOC5B
	GPT16E0_GTICLF_ICLFSELC_0x0B = 0xb
	// Setting prohibited
	GPT16E0_GTICLF_ICLFSELC_Others = 0xc
	// Position of ICLFB field.
	GPT16E0_GTICLF_ICLFB_Pos = 0x10
	// Bit mask of ICLFB field.
	GPT16E0_GTICLF_ICLFB_Msk = 0x70000
	// B (no delay)
	GPT16E0_GTICLF_ICLFB_000 = 0x0
	// NOT B (no delay)
	GPT16E0_GTICLF_ICLFB_001 = 0x1
	// D (1PCLKD delay)
	GPT16E0_GTICLF_ICLFB_010 = 0x2
	// NOT D (1PCLKD delay)
	GPT16E0_GTICLF_ICLFB_011 = 0x3
	// B AND D (1PCLKD delay)
	GPT16E0_GTICLF_ICLFB_100 = 0x4
	// B OR D (1PCLKD delay)
	GPT16E0_GTICLF_ICLFB_101 = 0x5
	// B EXOR D (1PCLKD delay)
	GPT16E0_GTICLF_ICLFB_110 = 0x6
	// B NOR D (1PCLKD delay)
	GPT16E0_GTICLF_ICLFB_111 = 0x7
	// Position of ICLFSELD field.
	GPT16E0_GTICLF_ICLFSELD_Pos = 0x14
	// Bit mask of ICLFSELD field.
	GPT16E0_GTICLF_ICLFSELD_Msk = 0x3f00000
	// GTIOC0A
	GPT16E0_GTICLF_ICLFSELD_0x00 = 0x0
	// GTIOC0B
	GPT16E0_GTICLF_ICLFSELD_0x01 = 0x1
	// GTIOC1A
	GPT16E0_GTICLF_ICLFSELD_0x02 = 0x2
	// GTIOC1B
	GPT16E0_GTICLF_ICLFSELD_0x03 = 0x3
	// GTIOC2A
	GPT16E0_GTICLF_ICLFSELD_0x04 = 0x4
	// GTIOC2B
	GPT16E0_GTICLF_ICLFSELD_0x05 = 0x5
	// GTIOC3A
	GPT16E0_GTICLF_ICLFSELD_0x06 = 0x6
	// GTIOC3B
	GPT16E0_GTICLF_ICLFSELD_0x07 = 0x7
	// GTIOC4A
	GPT16E0_GTICLF_ICLFSELD_0x08 = 0x8
	// GTIOC4B
	GPT16E0_GTICLF_ICLFSELD_0x09 = 0x9
	// GTIOC5A
	GPT16E0_GTICLF_ICLFSELD_0x0A = 0xa
	// GTIOC5B
	GPT16E0_GTICLF_ICLFSELD_0x0B = 0xb
	// Setting prohibited
	GPT16E0_GTICLF_ICLFSELD_Others = 0xc

	// GTPC: General PWM Timer Period Count Register
	// Position of PCEN field.
	GPT16E0_GTPC_PCEN_Pos = 0x0
	// Bit mask of PCEN field.
	GPT16E0_GTPC_PCEN_Msk = 0x1
	// Bit PCEN.
	GPT16E0_GTPC_PCEN = 0x1
	// Period count function is disabled
	GPT16E0_GTPC_PCEN_0 = 0x0
	// Period count function is enabled
	GPT16E0_GTPC_PCEN_1 = 0x1
	// Position of ASTP field.
	GPT16E0_GTPC_ASTP_Pos = 0x8
	// Bit mask of ASTP field.
	GPT16E0_GTPC_ASTP_Msk = 0x100
	// Bit ASTP.
	GPT16E0_GTPC_ASTP = 0x100
	// Automatic stop function is disabled
	GPT16E0_GTPC_ASTP_0 = 0x0
	// Automatic stop function is enabled
	GPT16E0_GTPC_ASTP_1 = 0x1
	// Position of PCNT field.
	GPT16E0_GTPC_PCNT_Pos = 0x10
	// Bit mask of PCNT field.
	GPT16E0_GTPC_PCNT_Msk = 0xfff0000

	// GTSECSR: General PWM Timer Operation Enable Bit Simultaneous Control Channel Select Register
	// Position of SECSEL0 field.
	GPT16E0_GTSECSR_SECSEL0_Pos = 0x0
	// Bit mask of SECSEL0 field.
	GPT16E0_GTSECSR_SECSEL0_Msk = 0x1
	// Bit SECSEL0.
	GPT16E0_GTSECSR_SECSEL0 = 0x1
	// Disable simultaneous control
	GPT16E0_GTSECSR_SECSEL0_0 = 0x0
	// Enable simultaneous control
	GPT16E0_GTSECSR_SECSEL0_1 = 0x1
	// Position of SECSEL1 field.
	GPT16E0_GTSECSR_SECSEL1_Pos = 0x1
	// Bit mask of SECSEL1 field.
	GPT16E0_GTSECSR_SECSEL1_Msk = 0x2
	// Bit SECSEL1.
	GPT16E0_GTSECSR_SECSEL1 = 0x2
	// Disable simultaneous control
	GPT16E0_GTSECSR_SECSEL1_0 = 0x0
	// Enable simultaneous control
	GPT16E0_GTSECSR_SECSEL1_1 = 0x1
	// Position of SECSEL2 field.
	GPT16E0_GTSECSR_SECSEL2_Pos = 0x2
	// Bit mask of SECSEL2 field.
	GPT16E0_GTSECSR_SECSEL2_Msk = 0x4
	// Bit SECSEL2.
	GPT16E0_GTSECSR_SECSEL2 = 0x4
	// Disable simultaneous control
	GPT16E0_GTSECSR_SECSEL2_0 = 0x0
	// Enable simultaneous control
	GPT16E0_GTSECSR_SECSEL2_1 = 0x1
	// Position of SECSEL3 field.
	GPT16E0_GTSECSR_SECSEL3_Pos = 0x3
	// Bit mask of SECSEL3 field.
	GPT16E0_GTSECSR_SECSEL3_Msk = 0x8
	// Bit SECSEL3.
	GPT16E0_GTSECSR_SECSEL3 = 0x8
	// Disable simultaneous control
	GPT16E0_GTSECSR_SECSEL3_0 = 0x0
	// Enable simultaneous control
	GPT16E0_GTSECSR_SECSEL3_1 = 0x1
	// Position of SECSEL4 field.
	GPT16E0_GTSECSR_SECSEL4_Pos = 0x4
	// Bit mask of SECSEL4 field.
	GPT16E0_GTSECSR_SECSEL4_Msk = 0x10
	// Bit SECSEL4.
	GPT16E0_GTSECSR_SECSEL4 = 0x10
	// Disable simultaneous control
	GPT16E0_GTSECSR_SECSEL4_0 = 0x0
	// Enable simultaneous control
	GPT16E0_GTSECSR_SECSEL4_1 = 0x1
	// Position of SECSEL5 field.
	GPT16E0_GTSECSR_SECSEL5_Pos = 0x5
	// Bit mask of SECSEL5 field.
	GPT16E0_GTSECSR_SECSEL5_Msk = 0x20
	// Bit SECSEL5.
	GPT16E0_GTSECSR_SECSEL5 = 0x20
	// Disable simultaneous control
	GPT16E0_GTSECSR_SECSEL5_0 = 0x0
	// Enable simultaneous control
	GPT16E0_GTSECSR_SECSEL5_1 = 0x1

	// GTSECR: General PWM Timer Operation Enable Bit Simultaneous Control Register
	// Position of SBDCE field.
	GPT16E0_GTSECR_SBDCE_Pos = 0x0
	// Bit mask of SBDCE field.
	GPT16E0_GTSECR_SBDCE_Msk = 0x1
	// Bit SBDCE.
	GPT16E0_GTSECR_SBDCE = 0x1
	// Disable simultaneous enabling GTCCR buffer operations
	GPT16E0_GTSECR_SBDCE_0 = 0x0
	// Enable GTCCR register buffer operations simultaneously
	GPT16E0_GTSECR_SBDCE_1 = 0x1
	// Position of SBDPE field.
	GPT16E0_GTSECR_SBDPE_Pos = 0x1
	// Bit mask of SBDPE field.
	GPT16E0_GTSECR_SBDPE_Msk = 0x2
	// Bit SBDPE.
	GPT16E0_GTSECR_SBDPE = 0x2
	// Disable simultaneous enabling GTPR buffer operations
	GPT16E0_GTSECR_SBDPE_0 = 0x0
	// Enable GTPR register buffer operations simultaneously
	GPT16E0_GTSECR_SBDPE_1 = 0x1
	// Position of SBDAE field.
	GPT16E0_GTSECR_SBDAE_Pos = 0x2
	// Bit mask of SBDAE field.
	GPT16E0_GTSECR_SBDAE_Msk = 0x4
	// Bit SBDAE.
	GPT16E0_GTSECR_SBDAE = 0x4
	// Disable simultaneous enabling GTADTR buffer operations
	GPT16E0_GTSECR_SBDAE_0 = 0x0
	// Enable GTADTR register buffer operations simultaneously
	GPT16E0_GTSECR_SBDAE_1 = 0x1
	// Position of SBDDE field.
	GPT16E0_GTSECR_SBDDE_Pos = 0x3
	// Bit mask of SBDDE field.
	GPT16E0_GTSECR_SBDDE_Msk = 0x8
	// Bit SBDDE.
	GPT16E0_GTSECR_SBDDE = 0x8
	// Disable simultaneous enabling GTDV buffer operations
	GPT16E0_GTSECR_SBDDE_0 = 0x0
	// Enable GTDV register buffer operations simultaneously
	GPT16E0_GTSECR_SBDDE_1 = 0x1
	// Position of SBDCD field.
	GPT16E0_GTSECR_SBDCD_Pos = 0x8
	// Bit mask of SBDCD field.
	GPT16E0_GTSECR_SBDCD_Msk = 0x100
	// Bit SBDCD.
	GPT16E0_GTSECR_SBDCD = 0x100
	// Disable simultaneous disabling GTCCR buffer operations
	GPT16E0_GTSECR_SBDCD_0 = 0x0
	// Disable GTCCR register buffer operations simultaneously
	GPT16E0_GTSECR_SBDCD_1 = 0x1
	// Position of SBDPD field.
	GPT16E0_GTSECR_SBDPD_Pos = 0x9
	// Bit mask of SBDPD field.
	GPT16E0_GTSECR_SBDPD_Msk = 0x200
	// Bit SBDPD.
	GPT16E0_GTSECR_SBDPD = 0x200
	// Disable simultaneous disabling GTPR buffer operations
	GPT16E0_GTSECR_SBDPD_0 = 0x0
	// Disable GTPR register buffer operations simultaneously
	GPT16E0_GTSECR_SBDPD_1 = 0x1
	// Position of SBDAD field.
	GPT16E0_GTSECR_SBDAD_Pos = 0xa
	// Bit mask of SBDAD field.
	GPT16E0_GTSECR_SBDAD_Msk = 0x400
	// Bit SBDAD.
	GPT16E0_GTSECR_SBDAD = 0x400
	// Disable simultaneous disabling GTADTR buffer operations
	GPT16E0_GTSECR_SBDAD_0 = 0x0
	// Disable GTADTR register buffer operations simultaneously
	GPT16E0_GTSECR_SBDAD_1 = 0x1
	// Position of SBDDD field.
	GPT16E0_GTSECR_SBDDD_Pos = 0xb
	// Bit mask of SBDDD field.
	GPT16E0_GTSECR_SBDDD_Msk = 0x800
	// Bit SBDDD.
	GPT16E0_GTSECR_SBDDD = 0x800
	// Disable simultaneous disabling GTDV buffer operations
	GPT16E0_GTSECR_SBDDD_0 = 0x0
	// Disable GTDV register buffer operations simultaneously
	GPT16E0_GTSECR_SBDDD_1 = 0x1
	// Position of SPCE field.
	GPT16E0_GTSECR_SPCE_Pos = 0x10
	// Bit mask of SPCE field.
	GPT16E0_GTSECR_SPCE_Msk = 0x10000
	// Bit SPCE.
	GPT16E0_GTSECR_SPCE = 0x10000
	// Disable simultaneous enabling period count function
	GPT16E0_GTSECR_SPCE_0 = 0x0
	// Enable period count function simultaneously
	GPT16E0_GTSECR_SPCE_1 = 0x1
	// Position of SPCD field.
	GPT16E0_GTSECR_SPCD_Pos = 0x18
	// Bit mask of SPCD field.
	GPT16E0_GTSECR_SPCD_Msk = 0x1000000
	// Bit SPCD.
	GPT16E0_GTSECR_SPCD = 0x1000000
	// Disable simultaneous disabling period count function
	GPT16E0_GTSECR_SPCD_0 = 0x0
	// Disable period count function simultaneously
	GPT16E0_GTSECR_SPCD_1 = 0x1
)

// Constants for GPT_OPS: Output Phase Switching Controller
const (
	// OPSCR: Output Phase Switching Control Register
	// Position of UF field.
	GPT_OPS_OPSCR_UF_Pos = 0x0
	// Bit mask of UF field.
	GPT_OPS_OPSCR_UF_Msk = 0x1
	// Bit UF.
	GPT_OPS_OPSCR_UF = 0x1
	// Position of VF field.
	GPT_OPS_OPSCR_VF_Pos = 0x1
	// Bit mask of VF field.
	GPT_OPS_OPSCR_VF_Msk = 0x2
	// Bit VF.
	GPT_OPS_OPSCR_VF = 0x2
	// Position of WF field.
	GPT_OPS_OPSCR_WF_Pos = 0x2
	// Bit mask of WF field.
	GPT_OPS_OPSCR_WF_Msk = 0x4
	// Bit WF.
	GPT_OPS_OPSCR_WF = 0x4
	// Position of U field.
	GPT_OPS_OPSCR_U_Pos = 0x4
	// Bit mask of U field.
	GPT_OPS_OPSCR_U_Msk = 0x10
	// Bit U.
	GPT_OPS_OPSCR_U = 0x10
	// Position of V field.
	GPT_OPS_OPSCR_V_Pos = 0x5
	// Bit mask of V field.
	GPT_OPS_OPSCR_V_Msk = 0x20
	// Bit V.
	GPT_OPS_OPSCR_V = 0x20
	// Position of W field.
	GPT_OPS_OPSCR_W_Pos = 0x6
	// Bit mask of W field.
	GPT_OPS_OPSCR_W_Msk = 0x40
	// Bit W.
	GPT_OPS_OPSCR_W = 0x40
	// Position of EN field.
	GPT_OPS_OPSCR_EN_Pos = 0x8
	// Bit mask of EN field.
	GPT_OPS_OPSCR_EN_Msk = 0x100
	// Bit EN.
	GPT_OPS_OPSCR_EN = 0x100
	// Do not output (Hi-Z external pin)
	GPT_OPS_OPSCR_EN_0 = 0x0
	// Output
	GPT_OPS_OPSCR_EN_1 = 0x1
	// Position of FB field.
	GPT_OPS_OPSCR_FB_Pos = 0x10
	// Bit mask of FB field.
	GPT_OPS_OPSCR_FB_Msk = 0x10000
	// Bit FB.
	GPT_OPS_OPSCR_FB = 0x10000
	// Select the external input
	GPT_OPS_OPSCR_FB_0 = 0x0
	// Select the soft setting (OPSCR.UF, VF, WF)
	GPT_OPS_OPSCR_FB_1 = 0x1
	// Position of P field.
	GPT_OPS_OPSCR_P_Pos = 0x11
	// Bit mask of P field.
	GPT_OPS_OPSCR_P_Msk = 0x20000
	// Bit P.
	GPT_OPS_OPSCR_P = 0x20000
	// Level signal output
	GPT_OPS_OPSCR_P_0 = 0x0
	// PWM signal output
	GPT_OPS_OPSCR_P_1 = 0x1
	// Position of N field.
	GPT_OPS_OPSCR_N_Pos = 0x12
	// Bit mask of N field.
	GPT_OPS_OPSCR_N_Msk = 0x40000
	// Bit N.
	GPT_OPS_OPSCR_N = 0x40000
	// Level signal output
	GPT_OPS_OPSCR_N_0 = 0x0
	// PWM signal output
	GPT_OPS_OPSCR_N_1 = 0x1
	// Position of INV field.
	GPT_OPS_OPSCR_INV_Pos = 0x13
	// Bit mask of INV field.
	GPT_OPS_OPSCR_INV_Msk = 0x80000
	// Bit INV.
	GPT_OPS_OPSCR_INV = 0x80000
	// Positive logic (active-high) output
	GPT_OPS_OPSCR_INV_0 = 0x0
	// Negative logic (active-low) output
	GPT_OPS_OPSCR_INV_1 = 0x1
	// Position of RV field.
	GPT_OPS_OPSCR_RV_Pos = 0x14
	// Bit mask of RV field.
	GPT_OPS_OPSCR_RV_Msk = 0x100000
	// Bit RV.
	GPT_OPS_OPSCR_RV = 0x100000
	// Positive rotation
	GPT_OPS_OPSCR_RV_0 = 0x0
	// Reverse rotation
	GPT_OPS_OPSCR_RV_1 = 0x1
	// Position of ALIGN field.
	GPT_OPS_OPSCR_ALIGN_Pos = 0x15
	// Bit mask of ALIGN field.
	GPT_OPS_OPSCR_ALIGN_Msk = 0x200000
	// Bit ALIGN.
	GPT_OPS_OPSCR_ALIGN = 0x200000
	// Input phase aligned to PCLKD
	GPT_OPS_OPSCR_ALIGN_0 = 0x0
	// Input phase aligned to the falling edge of PWM
	GPT_OPS_OPSCR_ALIGN_1 = 0x1
	// Position of GRP field.
	GPT_OPS_OPSCR_GRP_Pos = 0x18
	// Bit mask of GRP field.
	GPT_OPS_OPSCR_GRP_Msk = 0x3000000
	// Position of GODF field.
	GPT_OPS_OPSCR_GODF_Pos = 0x1a
	// Bit mask of GODF field.
	GPT_OPS_OPSCR_GODF_Msk = 0x4000000
	// Bit GODF.
	GPT_OPS_OPSCR_GODF = 0x4000000
	// This bit function is ignored
	GPT_OPS_OPSCR_GODF_0 = 0x0
	// Group disable clears the OPSCR.EN bit
	GPT_OPS_OPSCR_GODF_1 = 0x1
	// Position of NFEN field.
	GPT_OPS_OPSCR_NFEN_Pos = 0x1d
	// Bit mask of NFEN field.
	GPT_OPS_OPSCR_NFEN_Msk = 0x20000000
	// Bit NFEN.
	GPT_OPS_OPSCR_NFEN = 0x20000000
	// Do not use a noise filter on the external input
	GPT_OPS_OPSCR_NFEN_0 = 0x0
	// Use a noise filter on the external input
	GPT_OPS_OPSCR_NFEN_1 = 0x1
	// Position of NFCS field.
	GPT_OPS_OPSCR_NFCS_Pos = 0x1e
	// Bit mask of NFCS field.
	GPT_OPS_OPSCR_NFCS_Msk = 0xc0000000
	// PCLKD/1
	GPT_OPS_OPSCR_NFCS_00 = 0x0
	// PCLKD/4
	GPT_OPS_OPSCR_NFCS_01 = 0x1
	// PCLKD/16
	GPT_OPS_OPSCR_NFCS_10 = 0x2
	// PCLKD/64
	GPT_OPS_OPSCR_NFCS_11 = 0x3
)

// Constants for ADC120: 12-bit A/D Converter
const (
	// ADCSR: A/D Control Register
	// Position of DBLANS field.
	ADC120_ADCSR_DBLANS_Pos = 0x0
	// Bit mask of DBLANS field.
	ADC120_ADCSR_DBLANS_Msk = 0x1f
	// Position of GBADIE field.
	ADC120_ADCSR_GBADIE_Pos = 0x6
	// Bit mask of GBADIE field.
	ADC120_ADCSR_GBADIE_Msk = 0x40
	// Bit GBADIE.
	ADC120_ADCSR_GBADIE = 0x40
	// Disable ADC120_GBADI interrupt generation on group B scan completion.
	ADC120_ADCSR_GBADIE_0 = 0x0
	// Enable ADC120_GBADI interrupt generation on group B scan completion.
	ADC120_ADCSR_GBADIE_1 = 0x1
	// Position of DBLE field.
	ADC120_ADCSR_DBLE_Pos = 0x7
	// Bit mask of DBLE field.
	ADC120_ADCSR_DBLE_Msk = 0x80
	// Bit DBLE.
	ADC120_ADCSR_DBLE = 0x80
	// Deselect double-trigger mode.
	ADC120_ADCSR_DBLE_0 = 0x0
	// Select double-trigger mode.
	ADC120_ADCSR_DBLE_1 = 0x1
	// Position of EXTRG field.
	ADC120_ADCSR_EXTRG_Pos = 0x8
	// Bit mask of EXTRG field.
	ADC120_ADCSR_EXTRG_Msk = 0x100
	// Bit EXTRG.
	ADC120_ADCSR_EXTRG = 0x100
	// Start A/D conversion by the synchronous trigger (ELC).
	ADC120_ADCSR_EXTRG_0 = 0x0
	// Start A/D conversion by the asynchronous trigger (ADTRG0).
	ADC120_ADCSR_EXTRG_1 = 0x1
	// Position of TRGE field.
	ADC120_ADCSR_TRGE_Pos = 0x9
	// Bit mask of TRGE field.
	ADC120_ADCSR_TRGE_Msk = 0x200
	// Bit TRGE.
	ADC120_ADCSR_TRGE = 0x200
	// Disable A/D conversion to be started by the synchronous or asynchronous trigger
	ADC120_ADCSR_TRGE_0 = 0x0
	// Enable A/D conversion to be started by the synchronous or asynchronous trigger
	ADC120_ADCSR_TRGE_1 = 0x1
	// Position of ADCS field.
	ADC120_ADCSR_ADCS_Pos = 0xd
	// Bit mask of ADCS field.
	ADC120_ADCSR_ADCS_Msk = 0x6000
	// Single scan mode
	ADC120_ADCSR_ADCS_00 = 0x0
	// Group scan mode
	ADC120_ADCSR_ADCS_01 = 0x1
	// Continuous scan mode
	ADC120_ADCSR_ADCS_10 = 0x2
	// Setting prohibited
	ADC120_ADCSR_ADCS_11 = 0x3
	// Position of ADST field.
	ADC120_ADCSR_ADST_Pos = 0xf
	// Bit mask of ADST field.
	ADC120_ADCSR_ADST_Msk = 0x8000
	// Bit ADST.
	ADC120_ADCSR_ADST = 0x8000
	// Stop A/D conversion process.
	ADC120_ADCSR_ADST_0 = 0x0
	// Start A/D conversion process.
	ADC120_ADCSR_ADST_1 = 0x1

	// ADANSA0: A/D Channel Select Register A0
	// Position of ANSA00 field.
	ADC120_ADANSA0_ANSA00_Pos = 0x0
	// Bit mask of ANSA00 field.
	ADC120_ADANSA0_ANSA00_Msk = 0x1
	// Bit ANSA00.
	ADC120_ADANSA0_ANSA00 = 0x1
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA00_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA00_1 = 0x1
	// Position of ANSA01 field.
	ADC120_ADANSA0_ANSA01_Pos = 0x1
	// Bit mask of ANSA01 field.
	ADC120_ADANSA0_ANSA01_Msk = 0x2
	// Bit ANSA01.
	ADC120_ADANSA0_ANSA01 = 0x2
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA01_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA01_1 = 0x1
	// Position of ANSA02 field.
	ADC120_ADANSA0_ANSA02_Pos = 0x2
	// Bit mask of ANSA02 field.
	ADC120_ADANSA0_ANSA02_Msk = 0x4
	// Bit ANSA02.
	ADC120_ADANSA0_ANSA02 = 0x4
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA02_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA02_1 = 0x1
	// Position of ANSA03 field.
	ADC120_ADANSA0_ANSA03_Pos = 0x3
	// Bit mask of ANSA03 field.
	ADC120_ADANSA0_ANSA03_Msk = 0x8
	// Bit ANSA03.
	ADC120_ADANSA0_ANSA03 = 0x8
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA03_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA03_1 = 0x1
	// Position of ANSA04 field.
	ADC120_ADANSA0_ANSA04_Pos = 0x4
	// Bit mask of ANSA04 field.
	ADC120_ADANSA0_ANSA04_Msk = 0x10
	// Bit ANSA04.
	ADC120_ADANSA0_ANSA04 = 0x10
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA04_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA04_1 = 0x1
	// Position of ANSA05 field.
	ADC120_ADANSA0_ANSA05_Pos = 0x5
	// Bit mask of ANSA05 field.
	ADC120_ADANSA0_ANSA05_Msk = 0x20
	// Bit ANSA05.
	ADC120_ADANSA0_ANSA05 = 0x20
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA05_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA05_1 = 0x1
	// Position of ANSA06 field.
	ADC120_ADANSA0_ANSA06_Pos = 0x6
	// Bit mask of ANSA06 field.
	ADC120_ADANSA0_ANSA06_Msk = 0x40
	// Bit ANSA06.
	ADC120_ADANSA0_ANSA06 = 0x40
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA06_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA06_1 = 0x1
	// Position of ANSA07 field.
	ADC120_ADANSA0_ANSA07_Pos = 0x7
	// Bit mask of ANSA07 field.
	ADC120_ADANSA0_ANSA07_Msk = 0x80
	// Bit ANSA07.
	ADC120_ADANSA0_ANSA07 = 0x80
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA07_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA07_1 = 0x1
	// Position of ANSA08 field.
	ADC120_ADANSA0_ANSA08_Pos = 0x8
	// Bit mask of ANSA08 field.
	ADC120_ADANSA0_ANSA08_Msk = 0x100
	// Bit ANSA08.
	ADC120_ADANSA0_ANSA08 = 0x100
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA08_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA08_1 = 0x1
	// Position of ANSA09 field.
	ADC120_ADANSA0_ANSA09_Pos = 0x9
	// Bit mask of ANSA09 field.
	ADC120_ADANSA0_ANSA09_Msk = 0x200
	// Bit ANSA09.
	ADC120_ADANSA0_ANSA09 = 0x200
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA09_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA09_1 = 0x1
	// Position of ANSA10 field.
	ADC120_ADANSA0_ANSA10_Pos = 0xa
	// Bit mask of ANSA10 field.
	ADC120_ADANSA0_ANSA10_Msk = 0x400
	// Bit ANSA10.
	ADC120_ADANSA0_ANSA10 = 0x400
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA10_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA10_1 = 0x1
	// Position of ANSA11 field.
	ADC120_ADANSA0_ANSA11_Pos = 0xb
	// Bit mask of ANSA11 field.
	ADC120_ADANSA0_ANSA11_Msk = 0x800
	// Bit ANSA11.
	ADC120_ADANSA0_ANSA11 = 0x800
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA11_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA11_1 = 0x1
	// Position of ANSA12 field.
	ADC120_ADANSA0_ANSA12_Pos = 0xc
	// Bit mask of ANSA12 field.
	ADC120_ADANSA0_ANSA12_Msk = 0x1000
	// Bit ANSA12.
	ADC120_ADANSA0_ANSA12 = 0x1000
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA12_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA12_1 = 0x1
	// Position of ANSA13 field.
	ADC120_ADANSA0_ANSA13_Pos = 0xd
	// Bit mask of ANSA13 field.
	ADC120_ADANSA0_ANSA13_Msk = 0x2000
	// Bit ANSA13.
	ADC120_ADANSA0_ANSA13 = 0x2000
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA13_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA13_1 = 0x1
	// Position of ANSA14 field.
	ADC120_ADANSA0_ANSA14_Pos = 0xe
	// Bit mask of ANSA14 field.
	ADC120_ADANSA0_ANSA14_Msk = 0x4000
	// Bit ANSA14.
	ADC120_ADANSA0_ANSA14 = 0x4000
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA14_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA14_1 = 0x1
	// Position of ANSA15 field.
	ADC120_ADANSA0_ANSA15_Pos = 0xf
	// Bit mask of ANSA15 field.
	ADC120_ADANSA0_ANSA15_Msk = 0x8000
	// Bit ANSA15.
	ADC120_ADANSA0_ANSA15 = 0x8000
	// Do not select associated input channel.
	ADC120_ADANSA0_ANSA15_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA0_ANSA15_1 = 0x1

	// ADANSA1: A/D Channel Select Register A1
	// Position of ANSA16 field.
	ADC120_ADANSA1_ANSA16_Pos = 0x0
	// Bit mask of ANSA16 field.
	ADC120_ADANSA1_ANSA16_Msk = 0x1
	// Bit ANSA16.
	ADC120_ADANSA1_ANSA16 = 0x1
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA16_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA16_1 = 0x1
	// Position of ANSA17 field.
	ADC120_ADANSA1_ANSA17_Pos = 0x1
	// Bit mask of ANSA17 field.
	ADC120_ADANSA1_ANSA17_Msk = 0x2
	// Bit ANSA17.
	ADC120_ADANSA1_ANSA17 = 0x2
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA17_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA17_1 = 0x1
	// Position of ANSA18 field.
	ADC120_ADANSA1_ANSA18_Pos = 0x2
	// Bit mask of ANSA18 field.
	ADC120_ADANSA1_ANSA18_Msk = 0x4
	// Bit ANSA18.
	ADC120_ADANSA1_ANSA18 = 0x4
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA18_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA18_1 = 0x1
	// Position of ANSA19 field.
	ADC120_ADANSA1_ANSA19_Pos = 0x3
	// Bit mask of ANSA19 field.
	ADC120_ADANSA1_ANSA19_Msk = 0x8
	// Bit ANSA19.
	ADC120_ADANSA1_ANSA19 = 0x8
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA19_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA19_1 = 0x1
	// Position of ANSA20 field.
	ADC120_ADANSA1_ANSA20_Pos = 0x4
	// Bit mask of ANSA20 field.
	ADC120_ADANSA1_ANSA20_Msk = 0x10
	// Bit ANSA20.
	ADC120_ADANSA1_ANSA20 = 0x10
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA20_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA20_1 = 0x1
	// Position of ANSA21 field.
	ADC120_ADANSA1_ANSA21_Pos = 0x5
	// Bit mask of ANSA21 field.
	ADC120_ADANSA1_ANSA21_Msk = 0x20
	// Bit ANSA21.
	ADC120_ADANSA1_ANSA21 = 0x20
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA21_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA21_1 = 0x1
	// Position of ANSA22 field.
	ADC120_ADANSA1_ANSA22_Pos = 0x6
	// Bit mask of ANSA22 field.
	ADC120_ADANSA1_ANSA22_Msk = 0x40
	// Bit ANSA22.
	ADC120_ADANSA1_ANSA22 = 0x40
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA22_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA22_1 = 0x1
	// Position of ANSA23 field.
	ADC120_ADANSA1_ANSA23_Pos = 0x7
	// Bit mask of ANSA23 field.
	ADC120_ADANSA1_ANSA23_Msk = 0x80
	// Bit ANSA23.
	ADC120_ADANSA1_ANSA23 = 0x80
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA23_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA23_1 = 0x1
	// Position of ANSA24 field.
	ADC120_ADANSA1_ANSA24_Pos = 0x8
	// Bit mask of ANSA24 field.
	ADC120_ADANSA1_ANSA24_Msk = 0x100
	// Bit ANSA24.
	ADC120_ADANSA1_ANSA24 = 0x100
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA24_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA24_1 = 0x1
	// Position of ANSA25 field.
	ADC120_ADANSA1_ANSA25_Pos = 0x9
	// Bit mask of ANSA25 field.
	ADC120_ADANSA1_ANSA25_Msk = 0x200
	// Bit ANSA25.
	ADC120_ADANSA1_ANSA25 = 0x200
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA25_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA25_1 = 0x1
	// Position of ANSA26 field.
	ADC120_ADANSA1_ANSA26_Pos = 0xa
	// Bit mask of ANSA26 field.
	ADC120_ADANSA1_ANSA26_Msk = 0x400
	// Bit ANSA26.
	ADC120_ADANSA1_ANSA26 = 0x400
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA26_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA26_1 = 0x1
	// Position of ANSA27 field.
	ADC120_ADANSA1_ANSA27_Pos = 0xb
	// Bit mask of ANSA27 field.
	ADC120_ADANSA1_ANSA27_Msk = 0x800
	// Bit ANSA27.
	ADC120_ADANSA1_ANSA27 = 0x800
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA27_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA27_1 = 0x1
	// Position of ANSA28 field.
	ADC120_ADANSA1_ANSA28_Pos = 0xc
	// Bit mask of ANSA28 field.
	ADC120_ADANSA1_ANSA28_Msk = 0x1000
	// Bit ANSA28.
	ADC120_ADANSA1_ANSA28 = 0x1000
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA28_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA28_1 = 0x1
	// Position of ANSA29 field.
	ADC120_ADANSA1_ANSA29_Pos = 0xd
	// Bit mask of ANSA29 field.
	ADC120_ADANSA1_ANSA29_Msk = 0x2000
	// Bit ANSA29.
	ADC120_ADANSA1_ANSA29 = 0x2000
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA29_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA29_1 = 0x1
	// Position of ANSA30 field.
	ADC120_ADANSA1_ANSA30_Pos = 0xe
	// Bit mask of ANSA30 field.
	ADC120_ADANSA1_ANSA30_Msk = 0x4000
	// Bit ANSA30.
	ADC120_ADANSA1_ANSA30 = 0x4000
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA30_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA30_1 = 0x1
	// Position of ANSA31 field.
	ADC120_ADANSA1_ANSA31_Pos = 0xf
	// Bit mask of ANSA31 field.
	ADC120_ADANSA1_ANSA31_Msk = 0x8000
	// Bit ANSA31.
	ADC120_ADANSA1_ANSA31 = 0x8000
	// Do not select associated input channel.
	ADC120_ADANSA1_ANSA31_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSA1_ANSA31_1 = 0x1

	// ADADS0: A/D-Converted Value Addition/Average Channel Select Register 0
	// Position of ADS00 field.
	ADC120_ADADS0_ADS00_Pos = 0x0
	// Bit mask of ADS00 field.
	ADC120_ADADS0_ADS00_Msk = 0x1
	// Bit ADS00.
	ADC120_ADADS0_ADS00 = 0x1
	// Do not select associated input channel.
	ADC120_ADADS0_ADS00_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS00_1 = 0x1
	// Position of ADS01 field.
	ADC120_ADADS0_ADS01_Pos = 0x1
	// Bit mask of ADS01 field.
	ADC120_ADADS0_ADS01_Msk = 0x2
	// Bit ADS01.
	ADC120_ADADS0_ADS01 = 0x2
	// Do not select associated input channel.
	ADC120_ADADS0_ADS01_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS01_1 = 0x1
	// Position of ADS02 field.
	ADC120_ADADS0_ADS02_Pos = 0x2
	// Bit mask of ADS02 field.
	ADC120_ADADS0_ADS02_Msk = 0x4
	// Bit ADS02.
	ADC120_ADADS0_ADS02 = 0x4
	// Do not select associated input channel.
	ADC120_ADADS0_ADS02_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS02_1 = 0x1
	// Position of ADS03 field.
	ADC120_ADADS0_ADS03_Pos = 0x3
	// Bit mask of ADS03 field.
	ADC120_ADADS0_ADS03_Msk = 0x8
	// Bit ADS03.
	ADC120_ADADS0_ADS03 = 0x8
	// Do not select associated input channel.
	ADC120_ADADS0_ADS03_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS03_1 = 0x1
	// Position of ADS04 field.
	ADC120_ADADS0_ADS04_Pos = 0x4
	// Bit mask of ADS04 field.
	ADC120_ADADS0_ADS04_Msk = 0x10
	// Bit ADS04.
	ADC120_ADADS0_ADS04 = 0x10
	// Do not select associated input channel.
	ADC120_ADADS0_ADS04_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS04_1 = 0x1
	// Position of ADS05 field.
	ADC120_ADADS0_ADS05_Pos = 0x5
	// Bit mask of ADS05 field.
	ADC120_ADADS0_ADS05_Msk = 0x20
	// Bit ADS05.
	ADC120_ADADS0_ADS05 = 0x20
	// Do not select associated input channel.
	ADC120_ADADS0_ADS05_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS05_1 = 0x1
	// Position of ADS06 field.
	ADC120_ADADS0_ADS06_Pos = 0x6
	// Bit mask of ADS06 field.
	ADC120_ADADS0_ADS06_Msk = 0x40
	// Bit ADS06.
	ADC120_ADADS0_ADS06 = 0x40
	// Do not select associated input channel.
	ADC120_ADADS0_ADS06_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS06_1 = 0x1
	// Position of ADS07 field.
	ADC120_ADADS0_ADS07_Pos = 0x7
	// Bit mask of ADS07 field.
	ADC120_ADADS0_ADS07_Msk = 0x80
	// Bit ADS07.
	ADC120_ADADS0_ADS07 = 0x80
	// Do not select associated input channel.
	ADC120_ADADS0_ADS07_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS07_1 = 0x1
	// Position of ADS08 field.
	ADC120_ADADS0_ADS08_Pos = 0x8
	// Bit mask of ADS08 field.
	ADC120_ADADS0_ADS08_Msk = 0x100
	// Bit ADS08.
	ADC120_ADADS0_ADS08 = 0x100
	// Do not select associated input channel.
	ADC120_ADADS0_ADS08_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS08_1 = 0x1
	// Position of ADS09 field.
	ADC120_ADADS0_ADS09_Pos = 0x9
	// Bit mask of ADS09 field.
	ADC120_ADADS0_ADS09_Msk = 0x200
	// Bit ADS09.
	ADC120_ADADS0_ADS09 = 0x200
	// Do not select associated input channel.
	ADC120_ADADS0_ADS09_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS09_1 = 0x1
	// Position of ADS10 field.
	ADC120_ADADS0_ADS10_Pos = 0xa
	// Bit mask of ADS10 field.
	ADC120_ADADS0_ADS10_Msk = 0x400
	// Bit ADS10.
	ADC120_ADADS0_ADS10 = 0x400
	// Do not select associated input channel.
	ADC120_ADADS0_ADS10_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS10_1 = 0x1
	// Position of ADS11 field.
	ADC120_ADADS0_ADS11_Pos = 0xb
	// Bit mask of ADS11 field.
	ADC120_ADADS0_ADS11_Msk = 0x800
	// Bit ADS11.
	ADC120_ADADS0_ADS11 = 0x800
	// Do not select associated input channel.
	ADC120_ADADS0_ADS11_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS11_1 = 0x1
	// Position of ADS12 field.
	ADC120_ADADS0_ADS12_Pos = 0xc
	// Bit mask of ADS12 field.
	ADC120_ADADS0_ADS12_Msk = 0x1000
	// Bit ADS12.
	ADC120_ADADS0_ADS12 = 0x1000
	// Do not select associated input channel.
	ADC120_ADADS0_ADS12_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS12_1 = 0x1
	// Position of ADS13 field.
	ADC120_ADADS0_ADS13_Pos = 0xd
	// Bit mask of ADS13 field.
	ADC120_ADADS0_ADS13_Msk = 0x2000
	// Bit ADS13.
	ADC120_ADADS0_ADS13 = 0x2000
	// Do not select associated input channel.
	ADC120_ADADS0_ADS13_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS13_1 = 0x1
	// Position of ADS14 field.
	ADC120_ADADS0_ADS14_Pos = 0xe
	// Bit mask of ADS14 field.
	ADC120_ADADS0_ADS14_Msk = 0x4000
	// Bit ADS14.
	ADC120_ADADS0_ADS14 = 0x4000
	// Do not select associated input channel.
	ADC120_ADADS0_ADS14_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS14_1 = 0x1
	// Position of ADS15 field.
	ADC120_ADADS0_ADS15_Pos = 0xf
	// Bit mask of ADS15 field.
	ADC120_ADADS0_ADS15_Msk = 0x8000
	// Bit ADS15.
	ADC120_ADADS0_ADS15 = 0x8000
	// Do not select associated input channel.
	ADC120_ADADS0_ADS15_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS0_ADS15_1 = 0x1

	// ADADS1: A/D-Converted Value Addition/Average Channel Select Register 1
	// Position of ADS16 field.
	ADC120_ADADS1_ADS16_Pos = 0x0
	// Bit mask of ADS16 field.
	ADC120_ADADS1_ADS16_Msk = 0x1
	// Bit ADS16.
	ADC120_ADADS1_ADS16 = 0x1
	// Do not select associated input channel.
	ADC120_ADADS1_ADS16_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS16_1 = 0x1
	// Position of ADS17 field.
	ADC120_ADADS1_ADS17_Pos = 0x1
	// Bit mask of ADS17 field.
	ADC120_ADADS1_ADS17_Msk = 0x2
	// Bit ADS17.
	ADC120_ADADS1_ADS17 = 0x2
	// Do not select associated input channel.
	ADC120_ADADS1_ADS17_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS17_1 = 0x1
	// Position of ADS18 field.
	ADC120_ADADS1_ADS18_Pos = 0x2
	// Bit mask of ADS18 field.
	ADC120_ADADS1_ADS18_Msk = 0x4
	// Bit ADS18.
	ADC120_ADADS1_ADS18 = 0x4
	// Do not select associated input channel.
	ADC120_ADADS1_ADS18_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS18_1 = 0x1
	// Position of ADS19 field.
	ADC120_ADADS1_ADS19_Pos = 0x3
	// Bit mask of ADS19 field.
	ADC120_ADADS1_ADS19_Msk = 0x8
	// Bit ADS19.
	ADC120_ADADS1_ADS19 = 0x8
	// Do not select associated input channel.
	ADC120_ADADS1_ADS19_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS19_1 = 0x1
	// Position of ADS20 field.
	ADC120_ADADS1_ADS20_Pos = 0x4
	// Bit mask of ADS20 field.
	ADC120_ADADS1_ADS20_Msk = 0x10
	// Bit ADS20.
	ADC120_ADADS1_ADS20 = 0x10
	// Do not select associated input channel.
	ADC120_ADADS1_ADS20_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS20_1 = 0x1
	// Position of ADS21 field.
	ADC120_ADADS1_ADS21_Pos = 0x5
	// Bit mask of ADS21 field.
	ADC120_ADADS1_ADS21_Msk = 0x20
	// Bit ADS21.
	ADC120_ADADS1_ADS21 = 0x20
	// Do not select associated input channel.
	ADC120_ADADS1_ADS21_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS21_1 = 0x1
	// Position of ADS22 field.
	ADC120_ADADS1_ADS22_Pos = 0x6
	// Bit mask of ADS22 field.
	ADC120_ADADS1_ADS22_Msk = 0x40
	// Bit ADS22.
	ADC120_ADADS1_ADS22 = 0x40
	// Do not select associated input channel.
	ADC120_ADADS1_ADS22_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS22_1 = 0x1
	// Position of ADS23 field.
	ADC120_ADADS1_ADS23_Pos = 0x7
	// Bit mask of ADS23 field.
	ADC120_ADADS1_ADS23_Msk = 0x80
	// Bit ADS23.
	ADC120_ADADS1_ADS23 = 0x80
	// Do not select associated input channel.
	ADC120_ADADS1_ADS23_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS23_1 = 0x1
	// Position of ADS24 field.
	ADC120_ADADS1_ADS24_Pos = 0x8
	// Bit mask of ADS24 field.
	ADC120_ADADS1_ADS24_Msk = 0x100
	// Bit ADS24.
	ADC120_ADADS1_ADS24 = 0x100
	// Do not select associated input channel.
	ADC120_ADADS1_ADS24_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS24_1 = 0x1
	// Position of ADS25 field.
	ADC120_ADADS1_ADS25_Pos = 0x9
	// Bit mask of ADS25 field.
	ADC120_ADADS1_ADS25_Msk = 0x200
	// Bit ADS25.
	ADC120_ADADS1_ADS25 = 0x200
	// Do not select associated input channel.
	ADC120_ADADS1_ADS25_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS25_1 = 0x1
	// Position of ADS26 field.
	ADC120_ADADS1_ADS26_Pos = 0xa
	// Bit mask of ADS26 field.
	ADC120_ADADS1_ADS26_Msk = 0x400
	// Bit ADS26.
	ADC120_ADADS1_ADS26 = 0x400
	// Do not select associated input channel.
	ADC120_ADADS1_ADS26_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS26_1 = 0x1
	// Position of ADS27 field.
	ADC120_ADADS1_ADS27_Pos = 0xb
	// Bit mask of ADS27 field.
	ADC120_ADADS1_ADS27_Msk = 0x800
	// Bit ADS27.
	ADC120_ADADS1_ADS27 = 0x800
	// Do not select associated input channel.
	ADC120_ADADS1_ADS27_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS27_1 = 0x1
	// Position of ADS28 field.
	ADC120_ADADS1_ADS28_Pos = 0xc
	// Bit mask of ADS28 field.
	ADC120_ADADS1_ADS28_Msk = 0x1000
	// Bit ADS28.
	ADC120_ADADS1_ADS28 = 0x1000
	// Do not select associated input channel.
	ADC120_ADADS1_ADS28_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS28_1 = 0x1
	// Position of ADS29 field.
	ADC120_ADADS1_ADS29_Pos = 0xd
	// Bit mask of ADS29 field.
	ADC120_ADADS1_ADS29_Msk = 0x2000
	// Bit ADS29.
	ADC120_ADADS1_ADS29 = 0x2000
	// Do not select associated input channel.
	ADC120_ADADS1_ADS29_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS29_1 = 0x1
	// Position of ADS30 field.
	ADC120_ADADS1_ADS30_Pos = 0xe
	// Bit mask of ADS30 field.
	ADC120_ADADS1_ADS30_Msk = 0x4000
	// Bit ADS30.
	ADC120_ADADS1_ADS30 = 0x4000
	// Do not select associated input channel.
	ADC120_ADADS1_ADS30_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS30_1 = 0x1
	// Position of ADS31 field.
	ADC120_ADADS1_ADS31_Pos = 0xf
	// Bit mask of ADS31 field.
	ADC120_ADADS1_ADS31_Msk = 0x8000
	// Bit ADS31.
	ADC120_ADADS1_ADS31 = 0x8000
	// Do not select associated input channel.
	ADC120_ADADS1_ADS31_0 = 0x0
	// Select associated input channel.
	ADC120_ADADS1_ADS31_1 = 0x1

	// ADADC: A/D-Converted Value Addition/Average Count Select Register
	// Position of ADC field.
	ADC120_ADADC_ADC_Pos = 0x0
	// Bit mask of ADC field.
	ADC120_ADADC_ADC_Msk = 0x7
	// 1-time conversion (no addition, same as normal conversion)
	ADC120_ADADC_ADC_000 = 0x0
	// 2-time conversion (1 addition)
	ADC120_ADADC_ADC_001 = 0x1
	// 3-time conversion (2 additions)
	ADC120_ADADC_ADC_010 = 0x2
	// 4-time conversion (3 additions)
	ADC120_ADADC_ADC_011 = 0x3
	// 16-time conversion (15 additions)
	ADC120_ADADC_ADC_101 = 0x5
	// Setting prohibited
	ADC120_ADADC_ADC_Others = 0x6
	// Position of AVEE field.
	ADC120_ADADC_AVEE_Pos = 0x7
	// Bit mask of AVEE field.
	ADC120_ADADC_AVEE_Msk = 0x80
	// Bit AVEE.
	ADC120_ADADC_AVEE = 0x80
	// Enable addition mode
	ADC120_ADADC_AVEE_0 = 0x0
	// Enable average mode
	ADC120_ADADC_AVEE_1 = 0x1

	// ADCER: A/D Control Extended Register
	// Position of ADPRC field.
	ADC120_ADCER_ADPRC_Pos = 0x1
	// Bit mask of ADPRC field.
	ADC120_ADCER_ADPRC_Msk = 0x6
	// 12-bit accuracy
	ADC120_ADCER_ADPRC_00 = 0x0
	// 10-bit accuracy
	ADC120_ADCER_ADPRC_01 = 0x1
	// 8-bit accuracy
	ADC120_ADCER_ADPRC_10 = 0x2
	// Setting prohibited
	ADC120_ADCER_ADPRC_11 = 0x3
	// Position of ACE field.
	ADC120_ADCER_ACE_Pos = 0x5
	// Bit mask of ACE field.
	ADC120_ADCER_ACE_Msk = 0x20
	// Bit ACE.
	ADC120_ADCER_ACE = 0x20
	// Disable automatic clearing
	ADC120_ADCER_ACE_0 = 0x0
	// Enable automatic clearing
	ADC120_ADCER_ACE_1 = 0x1
	// Position of DIAGVAL field.
	ADC120_ADCER_DIAGVAL_Pos = 0x8
	// Bit mask of DIAGVAL field.
	ADC120_ADCER_DIAGVAL_Msk = 0x300
	// Setting prohibited when self-diagnosis is enabled
	ADC120_ADCER_DIAGVAL_00 = 0x0
	// 0 volts
	ADC120_ADCER_DIAGVAL_01 = 0x1
	// Reference voltage × 1/2
	ADC120_ADCER_DIAGVAL_10 = 0x2
	// Reference voltage
	ADC120_ADCER_DIAGVAL_11 = 0x3
	// Position of DIAGLD field.
	ADC120_ADCER_DIAGLD_Pos = 0xa
	// Bit mask of DIAGLD field.
	ADC120_ADCER_DIAGLD_Msk = 0x400
	// Bit DIAGLD.
	ADC120_ADCER_DIAGLD = 0x400
	// Select rotation mode for self-diagnosis voltage
	ADC120_ADCER_DIAGLD_0 = 0x0
	// Select mixed mode for self-diagnosis voltage
	ADC120_ADCER_DIAGLD_1 = 0x1
	// Position of DIAGM field.
	ADC120_ADCER_DIAGM_Pos = 0xb
	// Bit mask of DIAGM field.
	ADC120_ADCER_DIAGM_Msk = 0x800
	// Bit DIAGM.
	ADC120_ADCER_DIAGM = 0x800
	// Disable ADC12 self-diagnosis
	ADC120_ADCER_DIAGM_0 = 0x0
	// Enable ADC12 self-diagnosis
	ADC120_ADCER_DIAGM_1 = 0x1
	// Position of ADRFMT field.
	ADC120_ADCER_ADRFMT_Pos = 0xf
	// Bit mask of ADRFMT field.
	ADC120_ADCER_ADRFMT_Msk = 0x8000
	// Bit ADRFMT.
	ADC120_ADCER_ADRFMT = 0x8000
	// Select right-justified for the A/D data register format
	ADC120_ADCER_ADRFMT_0 = 0x0
	// Select left-justified for the A/D data register format
	ADC120_ADCER_ADRFMT_1 = 0x1

	// ADSTRGR: A/D Conversion Start Trigger Select Register
	// Position of TRSB field.
	ADC120_ADSTRGR_TRSB_Pos = 0x0
	// Bit mask of TRSB field.
	ADC120_ADSTRGR_TRSB_Msk = 0x3f
	// Position of TRSA field.
	ADC120_ADSTRGR_TRSA_Pos = 0x8
	// Bit mask of TRSA field.
	ADC120_ADSTRGR_TRSA_Msk = 0x3f00

	// ADEXICR: A/D Conversion Extended Input Control Registers
	// Position of TSSAD field.
	ADC120_ADEXICR_TSSAD_Pos = 0x0
	// Bit mask of TSSAD field.
	ADC120_ADEXICR_TSSAD_Msk = 0x1
	// Bit TSSAD.
	ADC120_ADEXICR_TSSAD = 0x1
	// Do not select addition/average mode for temperature sensor output.
	ADC120_ADEXICR_TSSAD_0 = 0x0
	// Select addition/average mode for temperature sensor output.
	ADC120_ADEXICR_TSSAD_1 = 0x1
	// Position of OCSAD field.
	ADC120_ADEXICR_OCSAD_Pos = 0x1
	// Bit mask of OCSAD field.
	ADC120_ADEXICR_OCSAD_Msk = 0x2
	// Bit OCSAD.
	ADC120_ADEXICR_OCSAD = 0x2
	// Do not select addition/average mode for internal reference voltage.
	ADC120_ADEXICR_OCSAD_0 = 0x0
	// Select addition/average mode for internal reference voltage.
	ADC120_ADEXICR_OCSAD_1 = 0x1
	// Position of TSSA field.
	ADC120_ADEXICR_TSSA_Pos = 0x8
	// Bit mask of TSSA field.
	ADC120_ADEXICR_TSSA_Msk = 0x100
	// Bit TSSA.
	ADC120_ADEXICR_TSSA = 0x100
	// Disable A/D conversion of temperature sensor output
	ADC120_ADEXICR_TSSA_0 = 0x0
	// Enable A/D conversion of temperature sensor output
	ADC120_ADEXICR_TSSA_1 = 0x1
	// Position of OCSA field.
	ADC120_ADEXICR_OCSA_Pos = 0x9
	// Bit mask of OCSA field.
	ADC120_ADEXICR_OCSA_Msk = 0x200
	// Bit OCSA.
	ADC120_ADEXICR_OCSA = 0x200
	// Disable A/D conversion of internal reference voltage
	ADC120_ADEXICR_OCSA_0 = 0x0
	// Enable A/D conversion of internal reference voltage
	ADC120_ADEXICR_OCSA_1 = 0x1
	// Position of TSSB field.
	ADC120_ADEXICR_TSSB_Pos = 0xa
	// Bit mask of TSSB field.
	ADC120_ADEXICR_TSSB_Msk = 0x400
	// Bit TSSB.
	ADC120_ADEXICR_TSSB = 0x400
	// Disable A/D conversion of temperature sensor output
	ADC120_ADEXICR_TSSB_0 = 0x0
	// Enable A/D conversion of temperature sensor output
	ADC120_ADEXICR_TSSB_1 = 0x1
	// Position of OCSB field.
	ADC120_ADEXICR_OCSB_Pos = 0xb
	// Bit mask of OCSB field.
	ADC120_ADEXICR_OCSB_Msk = 0x800
	// Bit OCSB.
	ADC120_ADEXICR_OCSB = 0x800
	// Disable A/D conversion of internal reference voltage
	ADC120_ADEXICR_OCSB_0 = 0x0
	// Enable A/D conversion of internal reference voltage
	ADC120_ADEXICR_OCSB_1 = 0x1

	// ADANSB0: A/D Channel Select Register B0
	// Position of ANSB00 field.
	ADC120_ADANSB0_ANSB00_Pos = 0x0
	// Bit mask of ANSB00 field.
	ADC120_ADANSB0_ANSB00_Msk = 0x1
	// Bit ANSB00.
	ADC120_ADANSB0_ANSB00 = 0x1
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB00_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB00_1 = 0x1
	// Position of ANSB01 field.
	ADC120_ADANSB0_ANSB01_Pos = 0x1
	// Bit mask of ANSB01 field.
	ADC120_ADANSB0_ANSB01_Msk = 0x2
	// Bit ANSB01.
	ADC120_ADANSB0_ANSB01 = 0x2
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB01_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB01_1 = 0x1
	// Position of ANSB02 field.
	ADC120_ADANSB0_ANSB02_Pos = 0x2
	// Bit mask of ANSB02 field.
	ADC120_ADANSB0_ANSB02_Msk = 0x4
	// Bit ANSB02.
	ADC120_ADANSB0_ANSB02 = 0x4
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB02_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB02_1 = 0x1
	// Position of ANSB03 field.
	ADC120_ADANSB0_ANSB03_Pos = 0x3
	// Bit mask of ANSB03 field.
	ADC120_ADANSB0_ANSB03_Msk = 0x8
	// Bit ANSB03.
	ADC120_ADANSB0_ANSB03 = 0x8
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB03_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB03_1 = 0x1
	// Position of ANSB04 field.
	ADC120_ADANSB0_ANSB04_Pos = 0x4
	// Bit mask of ANSB04 field.
	ADC120_ADANSB0_ANSB04_Msk = 0x10
	// Bit ANSB04.
	ADC120_ADANSB0_ANSB04 = 0x10
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB04_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB04_1 = 0x1
	// Position of ANSB05 field.
	ADC120_ADANSB0_ANSB05_Pos = 0x5
	// Bit mask of ANSB05 field.
	ADC120_ADANSB0_ANSB05_Msk = 0x20
	// Bit ANSB05.
	ADC120_ADANSB0_ANSB05 = 0x20
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB05_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB05_1 = 0x1
	// Position of ANSB06 field.
	ADC120_ADANSB0_ANSB06_Pos = 0x6
	// Bit mask of ANSB06 field.
	ADC120_ADANSB0_ANSB06_Msk = 0x40
	// Bit ANSB06.
	ADC120_ADANSB0_ANSB06 = 0x40
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB06_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB06_1 = 0x1
	// Position of ANSB07 field.
	ADC120_ADANSB0_ANSB07_Pos = 0x7
	// Bit mask of ANSB07 field.
	ADC120_ADANSB0_ANSB07_Msk = 0x80
	// Bit ANSB07.
	ADC120_ADANSB0_ANSB07 = 0x80
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB07_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB07_1 = 0x1
	// Position of ANSB08 field.
	ADC120_ADANSB0_ANSB08_Pos = 0x8
	// Bit mask of ANSB08 field.
	ADC120_ADANSB0_ANSB08_Msk = 0x100
	// Bit ANSB08.
	ADC120_ADANSB0_ANSB08 = 0x100
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB08_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB08_1 = 0x1
	// Position of ANSB09 field.
	ADC120_ADANSB0_ANSB09_Pos = 0x9
	// Bit mask of ANSB09 field.
	ADC120_ADANSB0_ANSB09_Msk = 0x200
	// Bit ANSB09.
	ADC120_ADANSB0_ANSB09 = 0x200
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB09_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB09_1 = 0x1
	// Position of ANSB10 field.
	ADC120_ADANSB0_ANSB10_Pos = 0xa
	// Bit mask of ANSB10 field.
	ADC120_ADANSB0_ANSB10_Msk = 0x400
	// Bit ANSB10.
	ADC120_ADANSB0_ANSB10 = 0x400
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB10_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB10_1 = 0x1
	// Position of ANSB11 field.
	ADC120_ADANSB0_ANSB11_Pos = 0xb
	// Bit mask of ANSB11 field.
	ADC120_ADANSB0_ANSB11_Msk = 0x800
	// Bit ANSB11.
	ADC120_ADANSB0_ANSB11 = 0x800
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB11_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB11_1 = 0x1
	// Position of ANSB12 field.
	ADC120_ADANSB0_ANSB12_Pos = 0xc
	// Bit mask of ANSB12 field.
	ADC120_ADANSB0_ANSB12_Msk = 0x1000
	// Bit ANSB12.
	ADC120_ADANSB0_ANSB12 = 0x1000
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB12_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB12_1 = 0x1
	// Position of ANSB13 field.
	ADC120_ADANSB0_ANSB13_Pos = 0xd
	// Bit mask of ANSB13 field.
	ADC120_ADANSB0_ANSB13_Msk = 0x2000
	// Bit ANSB13.
	ADC120_ADANSB0_ANSB13 = 0x2000
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB13_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB13_1 = 0x1
	// Position of ANSB14 field.
	ADC120_ADANSB0_ANSB14_Pos = 0xe
	// Bit mask of ANSB14 field.
	ADC120_ADANSB0_ANSB14_Msk = 0x4000
	// Bit ANSB14.
	ADC120_ADANSB0_ANSB14 = 0x4000
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB14_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB14_1 = 0x1
	// Position of ANSB15 field.
	ADC120_ADANSB0_ANSB15_Pos = 0xf
	// Bit mask of ANSB15 field.
	ADC120_ADANSB0_ANSB15_Msk = 0x8000
	// Bit ANSB15.
	ADC120_ADANSB0_ANSB15 = 0x8000
	// Do not select associated input channel.
	ADC120_ADANSB0_ANSB15_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB0_ANSB15_1 = 0x1

	// ADANSB1: A/D Channel Select Register B1
	// Position of ANSB16 field.
	ADC120_ADANSB1_ANSB16_Pos = 0x0
	// Bit mask of ANSB16 field.
	ADC120_ADANSB1_ANSB16_Msk = 0x1
	// Bit ANSB16.
	ADC120_ADANSB1_ANSB16 = 0x1
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB16_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB16_1 = 0x1
	// Position of ANSB17 field.
	ADC120_ADANSB1_ANSB17_Pos = 0x1
	// Bit mask of ANSB17 field.
	ADC120_ADANSB1_ANSB17_Msk = 0x2
	// Bit ANSB17.
	ADC120_ADANSB1_ANSB17 = 0x2
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB17_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB17_1 = 0x1
	// Position of ANSB18 field.
	ADC120_ADANSB1_ANSB18_Pos = 0x2
	// Bit mask of ANSB18 field.
	ADC120_ADANSB1_ANSB18_Msk = 0x4
	// Bit ANSB18.
	ADC120_ADANSB1_ANSB18 = 0x4
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB18_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB18_1 = 0x1
	// Position of ANSB19 field.
	ADC120_ADANSB1_ANSB19_Pos = 0x3
	// Bit mask of ANSB19 field.
	ADC120_ADANSB1_ANSB19_Msk = 0x8
	// Bit ANSB19.
	ADC120_ADANSB1_ANSB19 = 0x8
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB19_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB19_1 = 0x1
	// Position of ANSB20 field.
	ADC120_ADANSB1_ANSB20_Pos = 0x4
	// Bit mask of ANSB20 field.
	ADC120_ADANSB1_ANSB20_Msk = 0x10
	// Bit ANSB20.
	ADC120_ADANSB1_ANSB20 = 0x10
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB20_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB20_1 = 0x1
	// Position of ANSB21 field.
	ADC120_ADANSB1_ANSB21_Pos = 0x5
	// Bit mask of ANSB21 field.
	ADC120_ADANSB1_ANSB21_Msk = 0x20
	// Bit ANSB21.
	ADC120_ADANSB1_ANSB21 = 0x20
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB21_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB21_1 = 0x1
	// Position of ANSB22 field.
	ADC120_ADANSB1_ANSB22_Pos = 0x6
	// Bit mask of ANSB22 field.
	ADC120_ADANSB1_ANSB22_Msk = 0x40
	// Bit ANSB22.
	ADC120_ADANSB1_ANSB22 = 0x40
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB22_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB22_1 = 0x1
	// Position of ANSB23 field.
	ADC120_ADANSB1_ANSB23_Pos = 0x7
	// Bit mask of ANSB23 field.
	ADC120_ADANSB1_ANSB23_Msk = 0x80
	// Bit ANSB23.
	ADC120_ADANSB1_ANSB23 = 0x80
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB23_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB23_1 = 0x1
	// Position of ANSB24 field.
	ADC120_ADANSB1_ANSB24_Pos = 0x8
	// Bit mask of ANSB24 field.
	ADC120_ADANSB1_ANSB24_Msk = 0x100
	// Bit ANSB24.
	ADC120_ADANSB1_ANSB24 = 0x100
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB24_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB24_1 = 0x1
	// Position of ANSB25 field.
	ADC120_ADANSB1_ANSB25_Pos = 0x9
	// Bit mask of ANSB25 field.
	ADC120_ADANSB1_ANSB25_Msk = 0x200
	// Bit ANSB25.
	ADC120_ADANSB1_ANSB25 = 0x200
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB25_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB25_1 = 0x1
	// Position of ANSB26 field.
	ADC120_ADANSB1_ANSB26_Pos = 0xa
	// Bit mask of ANSB26 field.
	ADC120_ADANSB1_ANSB26_Msk = 0x400
	// Bit ANSB26.
	ADC120_ADANSB1_ANSB26 = 0x400
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB26_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB26_1 = 0x1
	// Position of ANSB27 field.
	ADC120_ADANSB1_ANSB27_Pos = 0xb
	// Bit mask of ANSB27 field.
	ADC120_ADANSB1_ANSB27_Msk = 0x800
	// Bit ANSB27.
	ADC120_ADANSB1_ANSB27 = 0x800
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB27_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB27_1 = 0x1
	// Position of ANSB28 field.
	ADC120_ADANSB1_ANSB28_Pos = 0xc
	// Bit mask of ANSB28 field.
	ADC120_ADANSB1_ANSB28_Msk = 0x1000
	// Bit ANSB28.
	ADC120_ADANSB1_ANSB28 = 0x1000
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB28_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB28_1 = 0x1
	// Position of ANSB29 field.
	ADC120_ADANSB1_ANSB29_Pos = 0xd
	// Bit mask of ANSB29 field.
	ADC120_ADANSB1_ANSB29_Msk = 0x2000
	// Bit ANSB29.
	ADC120_ADANSB1_ANSB29 = 0x2000
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB29_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB29_1 = 0x1
	// Position of ANSB30 field.
	ADC120_ADANSB1_ANSB30_Pos = 0xe
	// Bit mask of ANSB30 field.
	ADC120_ADANSB1_ANSB30_Msk = 0x4000
	// Bit ANSB30.
	ADC120_ADANSB1_ANSB30 = 0x4000
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB30_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB30_1 = 0x1
	// Position of ANSB31 field.
	ADC120_ADANSB1_ANSB31_Pos = 0xf
	// Bit mask of ANSB31 field.
	ADC120_ADANSB1_ANSB31_Msk = 0x8000
	// Bit ANSB31.
	ADC120_ADANSB1_ANSB31 = 0x8000
	// Do not select associated input channel.
	ADC120_ADANSB1_ANSB31_0 = 0x0
	// Select associated input channel.
	ADC120_ADANSB1_ANSB31_1 = 0x1

	// ADDBLDR: A/D Data Duplexing Register
	// Position of ADDBLDR field.
	ADC120_ADDBLDR_ADDBLDR_Pos = 0x0
	// Bit mask of ADDBLDR field.
	ADC120_ADDBLDR_ADDBLDR_Msk = 0xffff

	// ADTSDR: A/D Temperature Sensor Data Register
	// Position of ADTSDR field.
	ADC120_ADTSDR_ADTSDR_Pos = 0x0
	// Bit mask of ADTSDR field.
	ADC120_ADTSDR_ADTSDR_Msk = 0xffff

	// ADOCDR: A/D Internal Reference Voltage Data Register
	// Position of ADOCDR field.
	ADC120_ADOCDR_ADOCDR_Pos = 0x0
	// Bit mask of ADOCDR field.
	ADC120_ADOCDR_ADOCDR_Msk = 0xffff

	// ADRD: A/D Self-Diagnosis Data Register
	// Position of AD field.
	ADC120_ADRD_AD_Pos = 0x0
	// Bit mask of AD field.
	ADC120_ADRD_AD_Msk = 0xfff
	// Position of DIAGST field.
	ADC120_ADRD_DIAGST_Pos = 0xe
	// Bit mask of DIAGST field.
	ADC120_ADRD_DIAGST_Msk = 0xc000
	// Self-diagnosis not executed after power-on.
	ADC120_ADRD_DIAGST_00 = 0x0
	// Self-diagnosis was executed using the 0 V voltage.
	ADC120_ADRD_DIAGST_01 = 0x1
	// Self-diagnosis was executed using the reference voltage × 1/2.
	ADC120_ADRD_DIAGST_10 = 0x2
	// Self-diagnosis was executed using the reference voltage .
	ADC120_ADRD_DIAGST_11 = 0x3

	// ADDR0: A/D Data Registers %s
	// Position of ADDR field.
	ADC120_ADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	ADC120_ADDR_ADDR_Msk = 0xffff

	// ADDR4: A/D Data Registers %s
	// Position of ADDR field.
	ADC120_ADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	ADC120_ADDR_ADDR_Msk = 0xffff

	// ADDR11: A/D Data Registers %s
	// Position of ADDR field.
	ADC120_ADDR_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	ADC120_ADDR_ADDR_Msk = 0xffff

	// ADDR16: A/D Data Registers 16
	// Position of ADDR field.
	ADC120_ADDR16_ADDR_Pos = 0x0
	// Bit mask of ADDR field.
	ADC120_ADDR16_ADDR_Msk = 0xffff

	// ADDISCR: A/D Disconnection Detection Control Register
	// Position of ADNDIS field.
	ADC120_ADDISCR_ADNDIS_Pos = 0x0
	// Bit mask of ADNDIS field.
	ADC120_ADDISCR_ADNDIS_Msk = 0xf
	// The disconnection detection assist function is disabled
	ADC120_ADDISCR_ADNDIS_0x0 = 0x0
	// Setting prohibited
	ADC120_ADDISCR_ADNDIS_0x1 = 0x1
	// The number of states for the discharge or precharge period.
	ADC120_ADDISCR_ADNDIS_Others = 0x2
	// Position of PCHG field.
	ADC120_ADDISCR_PCHG_Pos = 0x4
	// Bit mask of PCHG field.
	ADC120_ADDISCR_PCHG_Msk = 0x10
	// Bit PCHG.
	ADC120_ADDISCR_PCHG = 0x10
	// Discharge
	ADC120_ADDISCR_PCHG_0 = 0x0
	// Precharge
	ADC120_ADDISCR_PCHG_1 = 0x1

	// ADGSPCR: A/D Group Scan Priority Control Register
	// Position of PGS field.
	ADC120_ADGSPCR_PGS_Pos = 0x0
	// Bit mask of PGS field.
	ADC120_ADGSPCR_PGS_Msk = 0x1
	// Bit PGS.
	ADC120_ADGSPCR_PGS = 0x1
	// Operate without group priority control.
	ADC120_ADGSPCR_PGS_0 = 0x0
	// Operate with group priority control.
	ADC120_ADGSPCR_PGS_1 = 0x1
	// Position of GBRSCN field.
	ADC120_ADGSPCR_GBRSCN_Pos = 0x1
	// Bit mask of GBRSCN field.
	ADC120_ADGSPCR_GBRSCN_Msk = 0x2
	// Bit GBRSCN.
	ADC120_ADGSPCR_GBRSCN = 0x2
	// Disable rescanning of the group that was stopped in group priority operation
	ADC120_ADGSPCR_GBRSCN_0 = 0x0
	// Enable rescanning of the group that was stopped in group priority operation.
	ADC120_ADGSPCR_GBRSCN_1 = 0x1
	// Position of LGRRS field.
	ADC120_ADGSPCR_LGRRS_Pos = 0xe
	// Bit mask of LGRRS field.
	ADC120_ADGSPCR_LGRRS_Msk = 0x4000
	// Bit LGRRS.
	ADC120_ADGSPCR_LGRRS = 0x4000
	// Start rescanning from the first channel for scanning
	ADC120_ADGSPCR_LGRRS_0 = 0x0
	// Start rescanning from the channel for which A/D conversion is not completed.
	ADC120_ADGSPCR_LGRRS_1 = 0x1
	// Position of GBRP field.
	ADC120_ADGSPCR_GBRP_Pos = 0xf
	// Bit mask of GBRP field.
	ADC120_ADGSPCR_GBRP_Msk = 0x8000
	// Bit GBRP.
	ADC120_ADGSPCR_GBRP = 0x8000
	// Single scan is not continuously activated.
	ADC120_ADGSPCR_GBRP_0 = 0x0
	// Single scan for the group with the lower-priority is continuously activated.
	ADC120_ADGSPCR_GBRP_1 = 0x1

	// ADDBLDRA: A/D Data Duplexing Register A
	// Position of ADDBLDR field.
	ADC120_ADDBLDRA_ADDBLDR_Pos = 0x0
	// Bit mask of ADDBLDR field.
	ADC120_ADDBLDRA_ADDBLDR_Msk = 0xffff

	// ADDBLDRB: A/D Data Duplexing Register B
	// Position of ADDBLDR field.
	ADC120_ADDBLDRB_ADDBLDR_Pos = 0x0
	// Bit mask of ADDBLDR field.
	ADC120_ADDBLDRB_ADDBLDR_Msk = 0xffff

	// ADWINMON: A/D Compare Function Window A/B Status Monitor Register
	// Position of MONCOMB field.
	ADC120_ADWINMON_MONCOMB_Pos = 0x0
	// Bit mask of MONCOMB field.
	ADC120_ADWINMON_MONCOMB_Msk = 0x1
	// Bit MONCOMB.
	ADC120_ADWINMON_MONCOMB = 0x1
	// Window A/B composite conditions are not met.
	ADC120_ADWINMON_MONCOMB_0 = 0x0
	// Window A/B composite conditions are met.
	ADC120_ADWINMON_MONCOMB_1 = 0x1
	// Position of MONCMPA field.
	ADC120_ADWINMON_MONCMPA_Pos = 0x4
	// Bit mask of MONCMPA field.
	ADC120_ADWINMON_MONCMPA_Msk = 0x10
	// Bit MONCMPA.
	ADC120_ADWINMON_MONCMPA = 0x10
	// Window A comparison conditions are not met.
	ADC120_ADWINMON_MONCMPA_0 = 0x0
	// Window A comparison conditions are met.
	ADC120_ADWINMON_MONCMPA_1 = 0x1
	// Position of MONCMPB field.
	ADC120_ADWINMON_MONCMPB_Pos = 0x5
	// Bit mask of MONCMPB field.
	ADC120_ADWINMON_MONCMPB_Msk = 0x20
	// Bit MONCMPB.
	ADC120_ADWINMON_MONCMPB = 0x20
	// Window B comparison conditions are not met.
	ADC120_ADWINMON_MONCMPB_0 = 0x0
	// Window B comparison conditions are met.
	ADC120_ADWINMON_MONCMPB_1 = 0x1

	// ADCMPCR: A/D Compare Function Control Register
	// Position of CMPAB field.
	ADC120_ADCMPCR_CMPAB_Pos = 0x0
	// Bit mask of CMPAB field.
	ADC120_ADCMPCR_CMPAB_Msk = 0x3
	// Output ADC120_WCMPM when window A OR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM.
	ADC120_ADCMPCR_CMPAB_00 = 0x0
	// Output ADC120_WCMPM when window A EXOR window B comparison conditions are met. Otherwise, output ADC120_WCMPUM.
	ADC120_ADCMPCR_CMPAB_01 = 0x1
	// Output ADC120_WCMPM when window A AND window B comparison conditions are met. Otherwise, output ADC120_WCMPUM.
	ADC120_ADCMPCR_CMPAB_10 = 0x2
	// Setting prohibited.
	ADC120_ADCMPCR_CMPAB_11 = 0x3
	// Position of CMPBE field.
	ADC120_ADCMPCR_CMPBE_Pos = 0x9
	// Bit mask of CMPBE field.
	ADC120_ADCMPCR_CMPBE_Msk = 0x200
	// Bit CMPBE.
	ADC120_ADCMPCR_CMPBE = 0x200
	// Disable compare window B operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs.
	ADC120_ADCMPCR_CMPBE_0 = 0x0
	// Enable compare window B operation.
	ADC120_ADCMPCR_CMPBE_1 = 0x1
	// Position of CMPAE field.
	ADC120_ADCMPCR_CMPAE_Pos = 0xb
	// Bit mask of CMPAE field.
	ADC120_ADCMPCR_CMPAE_Msk = 0x800
	// Bit CMPAE.
	ADC120_ADCMPCR_CMPAE = 0x800
	// Disable compare window A operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs.
	ADC120_ADCMPCR_CMPAE_0 = 0x0
	// Enable compare window A operation.
	ADC120_ADCMPCR_CMPAE_1 = 0x1
	// Position of CMPBIE field.
	ADC120_ADCMPCR_CMPBIE_Pos = 0xd
	// Bit mask of CMPBIE field.
	ADC120_ADCMPCR_CMPBIE_Msk = 0x2000
	// Bit CMPBIE.
	ADC120_ADCMPCR_CMPBIE = 0x2000
	// Disable ADC120_CMPBI interrupt when comparison conditions (window B) are met.
	ADC120_ADCMPCR_CMPBIE_0 = 0x0
	// Enable ADC120_CMPBI interrupt when comparison conditions (window B) are met.
	ADC120_ADCMPCR_CMPBIE_1 = 0x1
	// Position of WCMPE field.
	ADC120_ADCMPCR_WCMPE_Pos = 0xe
	// Bit mask of WCMPE field.
	ADC120_ADCMPCR_WCMPE_Msk = 0x4000
	// Bit WCMPE.
	ADC120_ADCMPCR_WCMPE = 0x4000
	// Disable window function Window A and window B operate as a comparator to compare the single value on the lower side with the A/D conversion result.
	ADC120_ADCMPCR_WCMPE_0 = 0x0
	// Enable window function Window A and window B operate as a comparator to compare the two values on the upper and lower sides with the A/D conversion result.
	ADC120_ADCMPCR_WCMPE_1 = 0x1
	// Position of CMPAIE field.
	ADC120_ADCMPCR_CMPAIE_Pos = 0xf
	// Bit mask of CMPAIE field.
	ADC120_ADCMPCR_CMPAIE_Msk = 0x8000
	// Bit CMPAIE.
	ADC120_ADCMPCR_CMPAIE = 0x8000
	// Disable ADC120_CMPAI interrupt when comparison conditions (window A) are met.
	ADC120_ADCMPCR_CMPAIE_0 = 0x0
	// Enable ADC120_CMPAI interrupt when comparison conditions (window A) are met.
	ADC120_ADCMPCR_CMPAIE_1 = 0x1

	// ADCMPANSER: A/D Compare Function Window A Extended Input Select Register
	// Position of CMPTSA field.
	ADC120_ADCMPANSER_CMPTSA_Pos = 0x0
	// Bit mask of CMPTSA field.
	ADC120_ADCMPANSER_CMPTSA_Msk = 0x1
	// Bit CMPTSA.
	ADC120_ADCMPANSER_CMPTSA = 0x1
	// Exclude the temperature sensor output from the compare Window A target range.
	ADC120_ADCMPANSER_CMPTSA_0 = 0x0
	// Include the temperature sensor output in the compare Window A target range.
	ADC120_ADCMPANSER_CMPTSA_1 = 0x1
	// Position of CMPOCA field.
	ADC120_ADCMPANSER_CMPOCA_Pos = 0x1
	// Bit mask of CMPOCA field.
	ADC120_ADCMPANSER_CMPOCA_Msk = 0x2
	// Bit CMPOCA.
	ADC120_ADCMPANSER_CMPOCA = 0x2
	// Exclude the internal reference voltage from the compare Window A target range.
	ADC120_ADCMPANSER_CMPOCA_0 = 0x0
	// Include the internal reference voltage in the compare Window A target range.
	ADC120_ADCMPANSER_CMPOCA_1 = 0x1

	// ADCMPLER: A/D Compare Function Window A Extended Input Comparison Condition Setting Register
	// Position of CMPLTSA field.
	ADC120_ADCMPLER_CMPLTSA_Pos = 0x0
	// Bit mask of CMPLTSA field.
	ADC120_ADCMPLER_CMPLTSA_Msk = 0x1
	// Bit CMPLTSA.
	ADC120_ADCMPLER_CMPLTSA = 0x1
	// When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted valueCompare Window A Temperature Sensor Output Comparison Condition Select When window function is enabled (ADCMPCR.WCMPE = 1) : Compare Window A Temperature Sensor Output Comparison ConditionA/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value
	ADC120_ADCMPLER_CMPLTSA_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1) : ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLER_CMPLTSA_1 = 0x1
	// Position of CMPLOCA field.
	ADC120_ADCMPLER_CMPLOCA_Pos = 0x1
	// Bit mask of CMPLOCA field.
	ADC120_ADCMPLER_CMPLOCA_Msk = 0x2
	// Bit CMPLOCA.
	ADC120_ADCMPLER_CMPLOCA = 0x2
	// When window function is disabled (ADCMPCR.WCMPE = 0) : ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or A/D-converted value > ADCMPDR1 value
	ADC120_ADCMPLER_CMPLOCA_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLER_CMPLOCA_1 = 0x1

	// ADCMPANSR0: A/D Compare Function Window A Channel Select Register 0
	// Position of CMPCHA00 field.
	ADC120_ADCMPANSR0_CMPCHA00_Pos = 0x0
	// Bit mask of CMPCHA00 field.
	ADC120_ADCMPANSR0_CMPCHA00_Msk = 0x1
	// Bit CMPCHA00.
	ADC120_ADCMPANSR0_CMPCHA00 = 0x1
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA00_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA00_1 = 0x1
	// Position of CMPCHA01 field.
	ADC120_ADCMPANSR0_CMPCHA01_Pos = 0x1
	// Bit mask of CMPCHA01 field.
	ADC120_ADCMPANSR0_CMPCHA01_Msk = 0x2
	// Bit CMPCHA01.
	ADC120_ADCMPANSR0_CMPCHA01 = 0x2
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA01_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA01_1 = 0x1
	// Position of CMPCHA02 field.
	ADC120_ADCMPANSR0_CMPCHA02_Pos = 0x2
	// Bit mask of CMPCHA02 field.
	ADC120_ADCMPANSR0_CMPCHA02_Msk = 0x4
	// Bit CMPCHA02.
	ADC120_ADCMPANSR0_CMPCHA02 = 0x4
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA02_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA02_1 = 0x1
	// Position of CMPCHA03 field.
	ADC120_ADCMPANSR0_CMPCHA03_Pos = 0x3
	// Bit mask of CMPCHA03 field.
	ADC120_ADCMPANSR0_CMPCHA03_Msk = 0x8
	// Bit CMPCHA03.
	ADC120_ADCMPANSR0_CMPCHA03 = 0x8
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA03_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA03_1 = 0x1
	// Position of CMPCHA04 field.
	ADC120_ADCMPANSR0_CMPCHA04_Pos = 0x4
	// Bit mask of CMPCHA04 field.
	ADC120_ADCMPANSR0_CMPCHA04_Msk = 0x10
	// Bit CMPCHA04.
	ADC120_ADCMPANSR0_CMPCHA04 = 0x10
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA04_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA04_1 = 0x1
	// Position of CMPCHA05 field.
	ADC120_ADCMPANSR0_CMPCHA05_Pos = 0x5
	// Bit mask of CMPCHA05 field.
	ADC120_ADCMPANSR0_CMPCHA05_Msk = 0x20
	// Bit CMPCHA05.
	ADC120_ADCMPANSR0_CMPCHA05 = 0x20
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA05_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA05_1 = 0x1
	// Position of CMPCHA06 field.
	ADC120_ADCMPANSR0_CMPCHA06_Pos = 0x6
	// Bit mask of CMPCHA06 field.
	ADC120_ADCMPANSR0_CMPCHA06_Msk = 0x40
	// Bit CMPCHA06.
	ADC120_ADCMPANSR0_CMPCHA06 = 0x40
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA06_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA06_1 = 0x1
	// Position of CMPCHA07 field.
	ADC120_ADCMPANSR0_CMPCHA07_Pos = 0x7
	// Bit mask of CMPCHA07 field.
	ADC120_ADCMPANSR0_CMPCHA07_Msk = 0x80
	// Bit CMPCHA07.
	ADC120_ADCMPANSR0_CMPCHA07 = 0x80
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA07_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA07_1 = 0x1
	// Position of CMPCHA08 field.
	ADC120_ADCMPANSR0_CMPCHA08_Pos = 0x8
	// Bit mask of CMPCHA08 field.
	ADC120_ADCMPANSR0_CMPCHA08_Msk = 0x100
	// Bit CMPCHA08.
	ADC120_ADCMPANSR0_CMPCHA08 = 0x100
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA08_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA08_1 = 0x1
	// Position of CMPCHA09 field.
	ADC120_ADCMPANSR0_CMPCHA09_Pos = 0x9
	// Bit mask of CMPCHA09 field.
	ADC120_ADCMPANSR0_CMPCHA09_Msk = 0x200
	// Bit CMPCHA09.
	ADC120_ADCMPANSR0_CMPCHA09 = 0x200
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA09_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA09_1 = 0x1
	// Position of CMPCHA10 field.
	ADC120_ADCMPANSR0_CMPCHA10_Pos = 0xa
	// Bit mask of CMPCHA10 field.
	ADC120_ADCMPANSR0_CMPCHA10_Msk = 0x400
	// Bit CMPCHA10.
	ADC120_ADCMPANSR0_CMPCHA10 = 0x400
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA10_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA10_1 = 0x1
	// Position of CMPCHA11 field.
	ADC120_ADCMPANSR0_CMPCHA11_Pos = 0xb
	// Bit mask of CMPCHA11 field.
	ADC120_ADCMPANSR0_CMPCHA11_Msk = 0x800
	// Bit CMPCHA11.
	ADC120_ADCMPANSR0_CMPCHA11 = 0x800
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA11_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA11_1 = 0x1
	// Position of CMPCHA12 field.
	ADC120_ADCMPANSR0_CMPCHA12_Pos = 0xc
	// Bit mask of CMPCHA12 field.
	ADC120_ADCMPANSR0_CMPCHA12_Msk = 0x1000
	// Bit CMPCHA12.
	ADC120_ADCMPANSR0_CMPCHA12 = 0x1000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA12_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA12_1 = 0x1
	// Position of CMPCHA13 field.
	ADC120_ADCMPANSR0_CMPCHA13_Pos = 0xd
	// Bit mask of CMPCHA13 field.
	ADC120_ADCMPANSR0_CMPCHA13_Msk = 0x2000
	// Bit CMPCHA13.
	ADC120_ADCMPANSR0_CMPCHA13 = 0x2000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA13_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA13_1 = 0x1
	// Position of CMPCHA14 field.
	ADC120_ADCMPANSR0_CMPCHA14_Pos = 0xe
	// Bit mask of CMPCHA14 field.
	ADC120_ADCMPANSR0_CMPCHA14_Msk = 0x4000
	// Bit CMPCHA14.
	ADC120_ADCMPANSR0_CMPCHA14 = 0x4000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA14_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA14_1 = 0x1
	// Position of CMPCHA15 field.
	ADC120_ADCMPANSR0_CMPCHA15_Pos = 0xf
	// Bit mask of CMPCHA15 field.
	ADC120_ADCMPANSR0_CMPCHA15_Msk = 0x8000
	// Bit CMPCHA15.
	ADC120_ADCMPANSR0_CMPCHA15 = 0x8000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA15_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR0_CMPCHA15_1 = 0x1

	// ADCMPANSR1: A/D Compare Function Window A Channel Select Register 1
	// Position of CMPCHA16 field.
	ADC120_ADCMPANSR1_CMPCHA16_Pos = 0x0
	// Bit mask of CMPCHA16 field.
	ADC120_ADCMPANSR1_CMPCHA16_Msk = 0x1
	// Bit CMPCHA16.
	ADC120_ADCMPANSR1_CMPCHA16 = 0x1
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA16_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA16_1 = 0x1
	// Position of CMPCHA17 field.
	ADC120_ADCMPANSR1_CMPCHA17_Pos = 0x1
	// Bit mask of CMPCHA17 field.
	ADC120_ADCMPANSR1_CMPCHA17_Msk = 0x2
	// Bit CMPCHA17.
	ADC120_ADCMPANSR1_CMPCHA17 = 0x2
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA17_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA17_1 = 0x1
	// Position of CMPCHA18 field.
	ADC120_ADCMPANSR1_CMPCHA18_Pos = 0x2
	// Bit mask of CMPCHA18 field.
	ADC120_ADCMPANSR1_CMPCHA18_Msk = 0x4
	// Bit CMPCHA18.
	ADC120_ADCMPANSR1_CMPCHA18 = 0x4
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA18_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA18_1 = 0x1
	// Position of CMPCHA19 field.
	ADC120_ADCMPANSR1_CMPCHA19_Pos = 0x3
	// Bit mask of CMPCHA19 field.
	ADC120_ADCMPANSR1_CMPCHA19_Msk = 0x8
	// Bit CMPCHA19.
	ADC120_ADCMPANSR1_CMPCHA19 = 0x8
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA19_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA19_1 = 0x1
	// Position of CMPCHA20 field.
	ADC120_ADCMPANSR1_CMPCHA20_Pos = 0x4
	// Bit mask of CMPCHA20 field.
	ADC120_ADCMPANSR1_CMPCHA20_Msk = 0x10
	// Bit CMPCHA20.
	ADC120_ADCMPANSR1_CMPCHA20 = 0x10
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA20_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA20_1 = 0x1
	// Position of CMPCHA21 field.
	ADC120_ADCMPANSR1_CMPCHA21_Pos = 0x5
	// Bit mask of CMPCHA21 field.
	ADC120_ADCMPANSR1_CMPCHA21_Msk = 0x20
	// Bit CMPCHA21.
	ADC120_ADCMPANSR1_CMPCHA21 = 0x20
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA21_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA21_1 = 0x1
	// Position of CMPCHA22 field.
	ADC120_ADCMPANSR1_CMPCHA22_Pos = 0x6
	// Bit mask of CMPCHA22 field.
	ADC120_ADCMPANSR1_CMPCHA22_Msk = 0x40
	// Bit CMPCHA22.
	ADC120_ADCMPANSR1_CMPCHA22 = 0x40
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA22_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA22_1 = 0x1
	// Position of CMPCHA23 field.
	ADC120_ADCMPANSR1_CMPCHA23_Pos = 0x7
	// Bit mask of CMPCHA23 field.
	ADC120_ADCMPANSR1_CMPCHA23_Msk = 0x80
	// Bit CMPCHA23.
	ADC120_ADCMPANSR1_CMPCHA23 = 0x80
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA23_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA23_1 = 0x1
	// Position of CMPCHA24 field.
	ADC120_ADCMPANSR1_CMPCHA24_Pos = 0x8
	// Bit mask of CMPCHA24 field.
	ADC120_ADCMPANSR1_CMPCHA24_Msk = 0x100
	// Bit CMPCHA24.
	ADC120_ADCMPANSR1_CMPCHA24 = 0x100
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA24_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA24_1 = 0x1
	// Position of CMPCHA25 field.
	ADC120_ADCMPANSR1_CMPCHA25_Pos = 0x9
	// Bit mask of CMPCHA25 field.
	ADC120_ADCMPANSR1_CMPCHA25_Msk = 0x200
	// Bit CMPCHA25.
	ADC120_ADCMPANSR1_CMPCHA25 = 0x200
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA25_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA25_1 = 0x1
	// Position of CMPCHA26 field.
	ADC120_ADCMPANSR1_CMPCHA26_Pos = 0xa
	// Bit mask of CMPCHA26 field.
	ADC120_ADCMPANSR1_CMPCHA26_Msk = 0x400
	// Bit CMPCHA26.
	ADC120_ADCMPANSR1_CMPCHA26 = 0x400
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA26_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA26_1 = 0x1
	// Position of CMPCHA27 field.
	ADC120_ADCMPANSR1_CMPCHA27_Pos = 0xb
	// Bit mask of CMPCHA27 field.
	ADC120_ADCMPANSR1_CMPCHA27_Msk = 0x800
	// Bit CMPCHA27.
	ADC120_ADCMPANSR1_CMPCHA27 = 0x800
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA27_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA27_1 = 0x1
	// Position of CMPCHA28 field.
	ADC120_ADCMPANSR1_CMPCHA28_Pos = 0xc
	// Bit mask of CMPCHA28 field.
	ADC120_ADCMPANSR1_CMPCHA28_Msk = 0x1000
	// Bit CMPCHA28.
	ADC120_ADCMPANSR1_CMPCHA28 = 0x1000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA28_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA28_1 = 0x1
	// Position of CMPCHA29 field.
	ADC120_ADCMPANSR1_CMPCHA29_Pos = 0xd
	// Bit mask of CMPCHA29 field.
	ADC120_ADCMPANSR1_CMPCHA29_Msk = 0x2000
	// Bit CMPCHA29.
	ADC120_ADCMPANSR1_CMPCHA29 = 0x2000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA29_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA29_1 = 0x1
	// Position of CMPCHA30 field.
	ADC120_ADCMPANSR1_CMPCHA30_Pos = 0xe
	// Bit mask of CMPCHA30 field.
	ADC120_ADCMPANSR1_CMPCHA30_Msk = 0x4000
	// Bit CMPCHA30.
	ADC120_ADCMPANSR1_CMPCHA30 = 0x4000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA30_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA30_1 = 0x1
	// Position of CMPCHA31 field.
	ADC120_ADCMPANSR1_CMPCHA31_Pos = 0xf
	// Bit mask of CMPCHA31 field.
	ADC120_ADCMPANSR1_CMPCHA31_Msk = 0x8000
	// Bit CMPCHA31.
	ADC120_ADCMPANSR1_CMPCHA31 = 0x8000
	// Disable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA31_0 = 0x0
	// Enable compare function for associated input channel
	ADC120_ADCMPANSR1_CMPCHA31_1 = 0x1

	// ADCMPLR0: A/D Compare Function Window A Comparison Condition Setting Register 0
	// Position of CMPLCHA00 field.
	ADC120_ADCMPLR0_CMPLCHA00_Pos = 0x0
	// Bit mask of CMPLCHA00 field.
	ADC120_ADCMPLR0_CMPLCHA00_Msk = 0x1
	// Bit CMPLCHA00.
	ADC120_ADCMPLR0_CMPLCHA00 = 0x1
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA00_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA00_1 = 0x1
	// Position of CMPLCHA01 field.
	ADC120_ADCMPLR0_CMPLCHA01_Pos = 0x1
	// Bit mask of CMPLCHA01 field.
	ADC120_ADCMPLR0_CMPLCHA01_Msk = 0x2
	// Bit CMPLCHA01.
	ADC120_ADCMPLR0_CMPLCHA01 = 0x2
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA01_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA01_1 = 0x1
	// Position of CMPLCHA02 field.
	ADC120_ADCMPLR0_CMPLCHA02_Pos = 0x2
	// Bit mask of CMPLCHA02 field.
	ADC120_ADCMPLR0_CMPLCHA02_Msk = 0x4
	// Bit CMPLCHA02.
	ADC120_ADCMPLR0_CMPLCHA02 = 0x4
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA02_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA02_1 = 0x1
	// Position of CMPLCHA03 field.
	ADC120_ADCMPLR0_CMPLCHA03_Pos = 0x3
	// Bit mask of CMPLCHA03 field.
	ADC120_ADCMPLR0_CMPLCHA03_Msk = 0x8
	// Bit CMPLCHA03.
	ADC120_ADCMPLR0_CMPLCHA03 = 0x8
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA03_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA03_1 = 0x1
	// Position of CMPLCHA04 field.
	ADC120_ADCMPLR0_CMPLCHA04_Pos = 0x4
	// Bit mask of CMPLCHA04 field.
	ADC120_ADCMPLR0_CMPLCHA04_Msk = 0x10
	// Bit CMPLCHA04.
	ADC120_ADCMPLR0_CMPLCHA04 = 0x10
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA04_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA04_1 = 0x1
	// Position of CMPLCHA05 field.
	ADC120_ADCMPLR0_CMPLCHA05_Pos = 0x5
	// Bit mask of CMPLCHA05 field.
	ADC120_ADCMPLR0_CMPLCHA05_Msk = 0x20
	// Bit CMPLCHA05.
	ADC120_ADCMPLR0_CMPLCHA05 = 0x20
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA05_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA05_1 = 0x1
	// Position of CMPLCHA06 field.
	ADC120_ADCMPLR0_CMPLCHA06_Pos = 0x6
	// Bit mask of CMPLCHA06 field.
	ADC120_ADCMPLR0_CMPLCHA06_Msk = 0x40
	// Bit CMPLCHA06.
	ADC120_ADCMPLR0_CMPLCHA06 = 0x40
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA06_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA06_1 = 0x1
	// Position of CMPLCHA07 field.
	ADC120_ADCMPLR0_CMPLCHA07_Pos = 0x7
	// Bit mask of CMPLCHA07 field.
	ADC120_ADCMPLR0_CMPLCHA07_Msk = 0x80
	// Bit CMPLCHA07.
	ADC120_ADCMPLR0_CMPLCHA07 = 0x80
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA07_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA07_1 = 0x1
	// Position of CMPLCHA08 field.
	ADC120_ADCMPLR0_CMPLCHA08_Pos = 0x8
	// Bit mask of CMPLCHA08 field.
	ADC120_ADCMPLR0_CMPLCHA08_Msk = 0x100
	// Bit CMPLCHA08.
	ADC120_ADCMPLR0_CMPLCHA08 = 0x100
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA08_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA08_1 = 0x1
	// Position of CMPLCHA09 field.
	ADC120_ADCMPLR0_CMPLCHA09_Pos = 0x9
	// Bit mask of CMPLCHA09 field.
	ADC120_ADCMPLR0_CMPLCHA09_Msk = 0x200
	// Bit CMPLCHA09.
	ADC120_ADCMPLR0_CMPLCHA09 = 0x200
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA09_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA09_1 = 0x1
	// Position of CMPLCHA10 field.
	ADC120_ADCMPLR0_CMPLCHA10_Pos = 0xa
	// Bit mask of CMPLCHA10 field.
	ADC120_ADCMPLR0_CMPLCHA10_Msk = 0x400
	// Bit CMPLCHA10.
	ADC120_ADCMPLR0_CMPLCHA10 = 0x400
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA10_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA10_1 = 0x1
	// Position of CMPLCHA11 field.
	ADC120_ADCMPLR0_CMPLCHA11_Pos = 0xb
	// Bit mask of CMPLCHA11 field.
	ADC120_ADCMPLR0_CMPLCHA11_Msk = 0x800
	// Bit CMPLCHA11.
	ADC120_ADCMPLR0_CMPLCHA11 = 0x800
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA11_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA11_1 = 0x1
	// Position of CMPLCHA12 field.
	ADC120_ADCMPLR0_CMPLCHA12_Pos = 0xc
	// Bit mask of CMPLCHA12 field.
	ADC120_ADCMPLR0_CMPLCHA12_Msk = 0x1000
	// Bit CMPLCHA12.
	ADC120_ADCMPLR0_CMPLCHA12 = 0x1000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA12_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA12_1 = 0x1
	// Position of CMPLCHA13 field.
	ADC120_ADCMPLR0_CMPLCHA13_Pos = 0xd
	// Bit mask of CMPLCHA13 field.
	ADC120_ADCMPLR0_CMPLCHA13_Msk = 0x2000
	// Bit CMPLCHA13.
	ADC120_ADCMPLR0_CMPLCHA13 = 0x2000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA13_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA13_1 = 0x1
	// Position of CMPLCHA14 field.
	ADC120_ADCMPLR0_CMPLCHA14_Pos = 0xe
	// Bit mask of CMPLCHA14 field.
	ADC120_ADCMPLR0_CMPLCHA14_Msk = 0x4000
	// Bit CMPLCHA14.
	ADC120_ADCMPLR0_CMPLCHA14 = 0x4000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA14_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA14_1 = 0x1
	// Position of CMPLCHA15 field.
	ADC120_ADCMPLR0_CMPLCHA15_Pos = 0xf
	// Bit mask of CMPLCHA15 field.
	ADC120_ADCMPLR0_CMPLCHA15_Msk = 0x8000
	// Bit CMPLCHA15.
	ADC120_ADCMPLR0_CMPLCHA15 = 0x8000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR0_CMPLCHA15_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR0_CMPLCHA15_1 = 0x1

	// ADCMPLR1: A/D Compare Function Window A Comparison Condition Setting Register 1
	// Position of CMPLCHA16 field.
	ADC120_ADCMPLR1_CMPLCHA16_Pos = 0x0
	// Bit mask of CMPLCHA16 field.
	ADC120_ADCMPLR1_CMPLCHA16_Msk = 0x1
	// Bit CMPLCHA16.
	ADC120_ADCMPLR1_CMPLCHA16 = 0x1
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA16_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA16_1 = 0x1
	// Position of CMPLCHA17 field.
	ADC120_ADCMPLR1_CMPLCHA17_Pos = 0x1
	// Bit mask of CMPLCHA17 field.
	ADC120_ADCMPLR1_CMPLCHA17_Msk = 0x2
	// Bit CMPLCHA17.
	ADC120_ADCMPLR1_CMPLCHA17 = 0x2
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA17_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA17_1 = 0x1
	// Position of CMPLCHA18 field.
	ADC120_ADCMPLR1_CMPLCHA18_Pos = 0x2
	// Bit mask of CMPLCHA18 field.
	ADC120_ADCMPLR1_CMPLCHA18_Msk = 0x4
	// Bit CMPLCHA18.
	ADC120_ADCMPLR1_CMPLCHA18 = 0x4
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA18_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA18_1 = 0x1
	// Position of CMPLCHA19 field.
	ADC120_ADCMPLR1_CMPLCHA19_Pos = 0x3
	// Bit mask of CMPLCHA19 field.
	ADC120_ADCMPLR1_CMPLCHA19_Msk = 0x8
	// Bit CMPLCHA19.
	ADC120_ADCMPLR1_CMPLCHA19 = 0x8
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA19_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA19_1 = 0x1
	// Position of CMPLCHA20 field.
	ADC120_ADCMPLR1_CMPLCHA20_Pos = 0x4
	// Bit mask of CMPLCHA20 field.
	ADC120_ADCMPLR1_CMPLCHA20_Msk = 0x10
	// Bit CMPLCHA20.
	ADC120_ADCMPLR1_CMPLCHA20 = 0x10
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA20_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA20_1 = 0x1
	// Position of CMPLCHA21 field.
	ADC120_ADCMPLR1_CMPLCHA21_Pos = 0x5
	// Bit mask of CMPLCHA21 field.
	ADC120_ADCMPLR1_CMPLCHA21_Msk = 0x20
	// Bit CMPLCHA21.
	ADC120_ADCMPLR1_CMPLCHA21 = 0x20
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA21_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA21_1 = 0x1
	// Position of CMPLCHA22 field.
	ADC120_ADCMPLR1_CMPLCHA22_Pos = 0x6
	// Bit mask of CMPLCHA22 field.
	ADC120_ADCMPLR1_CMPLCHA22_Msk = 0x40
	// Bit CMPLCHA22.
	ADC120_ADCMPLR1_CMPLCHA22 = 0x40
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA22_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA22_1 = 0x1
	// Position of CMPLCHA23 field.
	ADC120_ADCMPLR1_CMPLCHA23_Pos = 0x7
	// Bit mask of CMPLCHA23 field.
	ADC120_ADCMPLR1_CMPLCHA23_Msk = 0x80
	// Bit CMPLCHA23.
	ADC120_ADCMPLR1_CMPLCHA23 = 0x80
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA23_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA23_1 = 0x1
	// Position of CMPLCHA24 field.
	ADC120_ADCMPLR1_CMPLCHA24_Pos = 0x8
	// Bit mask of CMPLCHA24 field.
	ADC120_ADCMPLR1_CMPLCHA24_Msk = 0x100
	// Bit CMPLCHA24.
	ADC120_ADCMPLR1_CMPLCHA24 = 0x100
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA24_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA24_1 = 0x1
	// Position of CMPLCHA25 field.
	ADC120_ADCMPLR1_CMPLCHA25_Pos = 0x9
	// Bit mask of CMPLCHA25 field.
	ADC120_ADCMPLR1_CMPLCHA25_Msk = 0x200
	// Bit CMPLCHA25.
	ADC120_ADCMPLR1_CMPLCHA25 = 0x200
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA25_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA25_1 = 0x1
	// Position of CMPLCHA26 field.
	ADC120_ADCMPLR1_CMPLCHA26_Pos = 0xa
	// Bit mask of CMPLCHA26 field.
	ADC120_ADCMPLR1_CMPLCHA26_Msk = 0x400
	// Bit CMPLCHA26.
	ADC120_ADCMPLR1_CMPLCHA26 = 0x400
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA26_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA26_1 = 0x1
	// Position of CMPLCHA27 field.
	ADC120_ADCMPLR1_CMPLCHA27_Pos = 0xb
	// Bit mask of CMPLCHA27 field.
	ADC120_ADCMPLR1_CMPLCHA27_Msk = 0x800
	// Bit CMPLCHA27.
	ADC120_ADCMPLR1_CMPLCHA27 = 0x800
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA27_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA27_1 = 0x1
	// Position of CMPLCHA28 field.
	ADC120_ADCMPLR1_CMPLCHA28_Pos = 0xc
	// Bit mask of CMPLCHA28 field.
	ADC120_ADCMPLR1_CMPLCHA28_Msk = 0x1000
	// Bit CMPLCHA28.
	ADC120_ADCMPLR1_CMPLCHA28 = 0x1000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA28_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA28_1 = 0x1
	// Position of CMPLCHA29 field.
	ADC120_ADCMPLR1_CMPLCHA29_Pos = 0xd
	// Bit mask of CMPLCHA29 field.
	ADC120_ADCMPLR1_CMPLCHA29_Msk = 0x2000
	// Bit CMPLCHA29.
	ADC120_ADCMPLR1_CMPLCHA29 = 0x2000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA29_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA29_1 = 0x1
	// Position of CMPLCHA30 field.
	ADC120_ADCMPLR1_CMPLCHA30_Pos = 0xe
	// Bit mask of CMPLCHA30 field.
	ADC120_ADCMPLR1_CMPLCHA30_Msk = 0x4000
	// Bit CMPLCHA30.
	ADC120_ADCMPLR1_CMPLCHA30 = 0x4000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA30_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA30_1 = 0x1
	// Position of CMPLCHA31 field.
	ADC120_ADCMPLR1_CMPLCHA31_Pos = 0xf
	// Bit mask of CMPLCHA31 field.
	ADC120_ADCMPLR1_CMPLCHA31_Msk = 0x8000
	// Bit CMPLCHA31.
	ADC120_ADCMPLR1_CMPLCHA31 = 0x8000
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADCMPDR0 value, or ADCMPDR1 value < A/D-converted value
	ADC120_ADCMPLR1_CMPLCHA31_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADCMPDR0 value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADCMPDR0 value < A/D-converted value < ADCMPDR1 value
	ADC120_ADCMPLR1_CMPLCHA31_1 = 0x1

	// ADCMPSR0: A/D Compare Function Window A Channel Status Register 0
	// Position of CMPSTCHA00 field.
	ADC120_ADCMPSR0_CMPSTCHA00_Pos = 0x0
	// Bit mask of CMPSTCHA00 field.
	ADC120_ADCMPSR0_CMPSTCHA00_Msk = 0x1
	// Bit CMPSTCHA00.
	ADC120_ADCMPSR0_CMPSTCHA00 = 0x1
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA00_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA00_1 = 0x1
	// Position of CMPSTCHA01 field.
	ADC120_ADCMPSR0_CMPSTCHA01_Pos = 0x1
	// Bit mask of CMPSTCHA01 field.
	ADC120_ADCMPSR0_CMPSTCHA01_Msk = 0x2
	// Bit CMPSTCHA01.
	ADC120_ADCMPSR0_CMPSTCHA01 = 0x2
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA01_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA01_1 = 0x1
	// Position of CMPSTCHA02 field.
	ADC120_ADCMPSR0_CMPSTCHA02_Pos = 0x2
	// Bit mask of CMPSTCHA02 field.
	ADC120_ADCMPSR0_CMPSTCHA02_Msk = 0x4
	// Bit CMPSTCHA02.
	ADC120_ADCMPSR0_CMPSTCHA02 = 0x4
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA02_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA02_1 = 0x1
	// Position of CMPSTCHA03 field.
	ADC120_ADCMPSR0_CMPSTCHA03_Pos = 0x3
	// Bit mask of CMPSTCHA03 field.
	ADC120_ADCMPSR0_CMPSTCHA03_Msk = 0x8
	// Bit CMPSTCHA03.
	ADC120_ADCMPSR0_CMPSTCHA03 = 0x8
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA03_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA03_1 = 0x1
	// Position of CMPSTCHA04 field.
	ADC120_ADCMPSR0_CMPSTCHA04_Pos = 0x4
	// Bit mask of CMPSTCHA04 field.
	ADC120_ADCMPSR0_CMPSTCHA04_Msk = 0x10
	// Bit CMPSTCHA04.
	ADC120_ADCMPSR0_CMPSTCHA04 = 0x10
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA04_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA04_1 = 0x1
	// Position of CMPSTCHA05 field.
	ADC120_ADCMPSR0_CMPSTCHA05_Pos = 0x5
	// Bit mask of CMPSTCHA05 field.
	ADC120_ADCMPSR0_CMPSTCHA05_Msk = 0x20
	// Bit CMPSTCHA05.
	ADC120_ADCMPSR0_CMPSTCHA05 = 0x20
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA05_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA05_1 = 0x1
	// Position of CMPSTCHA06 field.
	ADC120_ADCMPSR0_CMPSTCHA06_Pos = 0x6
	// Bit mask of CMPSTCHA06 field.
	ADC120_ADCMPSR0_CMPSTCHA06_Msk = 0x40
	// Bit CMPSTCHA06.
	ADC120_ADCMPSR0_CMPSTCHA06 = 0x40
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA06_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA06_1 = 0x1
	// Position of CMPSTCHA07 field.
	ADC120_ADCMPSR0_CMPSTCHA07_Pos = 0x7
	// Bit mask of CMPSTCHA07 field.
	ADC120_ADCMPSR0_CMPSTCHA07_Msk = 0x80
	// Bit CMPSTCHA07.
	ADC120_ADCMPSR0_CMPSTCHA07 = 0x80
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA07_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA07_1 = 0x1
	// Position of CMPSTCHA08 field.
	ADC120_ADCMPSR0_CMPSTCHA08_Pos = 0x8
	// Bit mask of CMPSTCHA08 field.
	ADC120_ADCMPSR0_CMPSTCHA08_Msk = 0x100
	// Bit CMPSTCHA08.
	ADC120_ADCMPSR0_CMPSTCHA08 = 0x100
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA08_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA08_1 = 0x1
	// Position of CMPSTCHA09 field.
	ADC120_ADCMPSR0_CMPSTCHA09_Pos = 0x9
	// Bit mask of CMPSTCHA09 field.
	ADC120_ADCMPSR0_CMPSTCHA09_Msk = 0x200
	// Bit CMPSTCHA09.
	ADC120_ADCMPSR0_CMPSTCHA09 = 0x200
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA09_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA09_1 = 0x1
	// Position of CMPSTCHA10 field.
	ADC120_ADCMPSR0_CMPSTCHA10_Pos = 0xa
	// Bit mask of CMPSTCHA10 field.
	ADC120_ADCMPSR0_CMPSTCHA10_Msk = 0x400
	// Bit CMPSTCHA10.
	ADC120_ADCMPSR0_CMPSTCHA10 = 0x400
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA10_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA10_1 = 0x1
	// Position of CMPSTCHA11 field.
	ADC120_ADCMPSR0_CMPSTCHA11_Pos = 0xb
	// Bit mask of CMPSTCHA11 field.
	ADC120_ADCMPSR0_CMPSTCHA11_Msk = 0x800
	// Bit CMPSTCHA11.
	ADC120_ADCMPSR0_CMPSTCHA11 = 0x800
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA11_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA11_1 = 0x1
	// Position of CMPSTCHA12 field.
	ADC120_ADCMPSR0_CMPSTCHA12_Pos = 0xc
	// Bit mask of CMPSTCHA12 field.
	ADC120_ADCMPSR0_CMPSTCHA12_Msk = 0x1000
	// Bit CMPSTCHA12.
	ADC120_ADCMPSR0_CMPSTCHA12 = 0x1000
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA12_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA12_1 = 0x1
	// Position of CMPSTCHA13 field.
	ADC120_ADCMPSR0_CMPSTCHA13_Pos = 0xd
	// Bit mask of CMPSTCHA13 field.
	ADC120_ADCMPSR0_CMPSTCHA13_Msk = 0x2000
	// Bit CMPSTCHA13.
	ADC120_ADCMPSR0_CMPSTCHA13 = 0x2000
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA13_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA13_1 = 0x1
	// Position of CMPSTCHA14 field.
	ADC120_ADCMPSR0_CMPSTCHA14_Pos = 0xe
	// Bit mask of CMPSTCHA14 field.
	ADC120_ADCMPSR0_CMPSTCHA14_Msk = 0x4000
	// Bit CMPSTCHA14.
	ADC120_ADCMPSR0_CMPSTCHA14 = 0x4000
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA14_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA14_1 = 0x1
	// Position of CMPSTCHA15 field.
	ADC120_ADCMPSR0_CMPSTCHA15_Pos = 0xf
	// Bit mask of CMPSTCHA15 field.
	ADC120_ADCMPSR0_CMPSTCHA15_Msk = 0x8000
	// Bit CMPSTCHA15.
	ADC120_ADCMPSR0_CMPSTCHA15 = 0x8000
	// Comparison conditions are not met.
	ADC120_ADCMPSR0_CMPSTCHA15_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR0_CMPSTCHA15_1 = 0x1

	// ADCMPSR1: A/D Compare Function Window A Channel Status Register1
	// Position of CMPSTCHA16 field.
	ADC120_ADCMPSR1_CMPSTCHA16_Pos = 0x0
	// Bit mask of CMPSTCHA16 field.
	ADC120_ADCMPSR1_CMPSTCHA16_Msk = 0x1
	// Bit CMPSTCHA16.
	ADC120_ADCMPSR1_CMPSTCHA16 = 0x1
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA16_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA16_1 = 0x1
	// Position of CMPSTCHA17 field.
	ADC120_ADCMPSR1_CMPSTCHA17_Pos = 0x1
	// Bit mask of CMPSTCHA17 field.
	ADC120_ADCMPSR1_CMPSTCHA17_Msk = 0x2
	// Bit CMPSTCHA17.
	ADC120_ADCMPSR1_CMPSTCHA17 = 0x2
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA17_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA17_1 = 0x1
	// Position of CMPSTCHA18 field.
	ADC120_ADCMPSR1_CMPSTCHA18_Pos = 0x2
	// Bit mask of CMPSTCHA18 field.
	ADC120_ADCMPSR1_CMPSTCHA18_Msk = 0x4
	// Bit CMPSTCHA18.
	ADC120_ADCMPSR1_CMPSTCHA18 = 0x4
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA18_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA18_1 = 0x1
	// Position of CMPSTCHA19 field.
	ADC120_ADCMPSR1_CMPSTCHA19_Pos = 0x3
	// Bit mask of CMPSTCHA19 field.
	ADC120_ADCMPSR1_CMPSTCHA19_Msk = 0x8
	// Bit CMPSTCHA19.
	ADC120_ADCMPSR1_CMPSTCHA19 = 0x8
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA19_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA19_1 = 0x1
	// Position of CMPSTCHA20 field.
	ADC120_ADCMPSR1_CMPSTCHA20_Pos = 0x4
	// Bit mask of CMPSTCHA20 field.
	ADC120_ADCMPSR1_CMPSTCHA20_Msk = 0x10
	// Bit CMPSTCHA20.
	ADC120_ADCMPSR1_CMPSTCHA20 = 0x10
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA20_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA20_1 = 0x1
	// Position of CMPSTCHA21 field.
	ADC120_ADCMPSR1_CMPSTCHA21_Pos = 0x5
	// Bit mask of CMPSTCHA21 field.
	ADC120_ADCMPSR1_CMPSTCHA21_Msk = 0x20
	// Bit CMPSTCHA21.
	ADC120_ADCMPSR1_CMPSTCHA21 = 0x20
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA21_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA21_1 = 0x1
	// Position of CMPSTCHA22 field.
	ADC120_ADCMPSR1_CMPSTCHA22_Pos = 0x6
	// Bit mask of CMPSTCHA22 field.
	ADC120_ADCMPSR1_CMPSTCHA22_Msk = 0x40
	// Bit CMPSTCHA22.
	ADC120_ADCMPSR1_CMPSTCHA22 = 0x40
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA22_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA22_1 = 0x1
	// Position of CMPSTCHA23 field.
	ADC120_ADCMPSR1_CMPSTCHA23_Pos = 0x7
	// Bit mask of CMPSTCHA23 field.
	ADC120_ADCMPSR1_CMPSTCHA23_Msk = 0x80
	// Bit CMPSTCHA23.
	ADC120_ADCMPSR1_CMPSTCHA23 = 0x80
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA23_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA23_1 = 0x1
	// Position of CMPSTCHA24 field.
	ADC120_ADCMPSR1_CMPSTCHA24_Pos = 0x8
	// Bit mask of CMPSTCHA24 field.
	ADC120_ADCMPSR1_CMPSTCHA24_Msk = 0x100
	// Bit CMPSTCHA24.
	ADC120_ADCMPSR1_CMPSTCHA24 = 0x100
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA24_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA24_1 = 0x1
	// Position of CMPSTCHA25 field.
	ADC120_ADCMPSR1_CMPSTCHA25_Pos = 0x9
	// Bit mask of CMPSTCHA25 field.
	ADC120_ADCMPSR1_CMPSTCHA25_Msk = 0x200
	// Bit CMPSTCHA25.
	ADC120_ADCMPSR1_CMPSTCHA25 = 0x200
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA25_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA25_1 = 0x1
	// Position of CMPSTCHA26 field.
	ADC120_ADCMPSR1_CMPSTCHA26_Pos = 0xa
	// Bit mask of CMPSTCHA26 field.
	ADC120_ADCMPSR1_CMPSTCHA26_Msk = 0x400
	// Bit CMPSTCHA26.
	ADC120_ADCMPSR1_CMPSTCHA26 = 0x400
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA26_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA26_1 = 0x1
	// Position of CMPSTCHA27 field.
	ADC120_ADCMPSR1_CMPSTCHA27_Pos = 0xb
	// Bit mask of CMPSTCHA27 field.
	ADC120_ADCMPSR1_CMPSTCHA27_Msk = 0x800
	// Bit CMPSTCHA27.
	ADC120_ADCMPSR1_CMPSTCHA27 = 0x800
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA27_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA27_1 = 0x1
	// Position of CMPSTCHA28 field.
	ADC120_ADCMPSR1_CMPSTCHA28_Pos = 0xc
	// Bit mask of CMPSTCHA28 field.
	ADC120_ADCMPSR1_CMPSTCHA28_Msk = 0x1000
	// Bit CMPSTCHA28.
	ADC120_ADCMPSR1_CMPSTCHA28 = 0x1000
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA28_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA28_1 = 0x1
	// Position of CMPSTCHA29 field.
	ADC120_ADCMPSR1_CMPSTCHA29_Pos = 0xd
	// Bit mask of CMPSTCHA29 field.
	ADC120_ADCMPSR1_CMPSTCHA29_Msk = 0x2000
	// Bit CMPSTCHA29.
	ADC120_ADCMPSR1_CMPSTCHA29 = 0x2000
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA29_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA29_1 = 0x1
	// Position of CMPSTCHA30 field.
	ADC120_ADCMPSR1_CMPSTCHA30_Pos = 0xe
	// Bit mask of CMPSTCHA30 field.
	ADC120_ADCMPSR1_CMPSTCHA30_Msk = 0x4000
	// Bit CMPSTCHA30.
	ADC120_ADCMPSR1_CMPSTCHA30 = 0x4000
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA30_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA30_1 = 0x1
	// Position of CMPSTCHA31 field.
	ADC120_ADCMPSR1_CMPSTCHA31_Pos = 0xf
	// Bit mask of CMPSTCHA31 field.
	ADC120_ADCMPSR1_CMPSTCHA31_Msk = 0x8000
	// Bit CMPSTCHA31.
	ADC120_ADCMPSR1_CMPSTCHA31 = 0x8000
	// Comparison conditions are not met.
	ADC120_ADCMPSR1_CMPSTCHA31_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSR1_CMPSTCHA31_1 = 0x1

	// ADCMPSER: A/D Compare Function Window A Extended Input Channel Status Register
	// Position of CMPSTTSA field.
	ADC120_ADCMPSER_CMPSTTSA_Pos = 0x0
	// Bit mask of CMPSTTSA field.
	ADC120_ADCMPSER_CMPSTTSA_Msk = 0x1
	// Bit CMPSTTSA.
	ADC120_ADCMPSER_CMPSTTSA = 0x1
	// Comparison conditions are not met.
	ADC120_ADCMPSER_CMPSTTSA_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSER_CMPSTTSA_1 = 0x1
	// Position of CMPSTOCA field.
	ADC120_ADCMPSER_CMPSTOCA_Pos = 0x1
	// Bit mask of CMPSTOCA field.
	ADC120_ADCMPSER_CMPSTOCA_Msk = 0x2
	// Bit CMPSTOCA.
	ADC120_ADCMPSER_CMPSTOCA = 0x2
	// Comparison conditions are not met.
	ADC120_ADCMPSER_CMPSTOCA_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPSER_CMPSTOCA_1 = 0x1

	// ADCMPBNSR: A/D Compare Function Window B Channel Select Register
	// Position of CMPCHB field.
	ADC120_ADCMPBNSR_CMPCHB_Pos = 0x0
	// Bit mask of CMPCHB field.
	ADC120_ADCMPBNSR_CMPCHB_Msk = 0x3f
	// Position of CMPLB field.
	ADC120_ADCMPBNSR_CMPLB_Pos = 0x7
	// Bit mask of CMPLB field.
	ADC120_ADCMPBNSR_CMPLB_Msk = 0x80
	// Bit CMPLB.
	ADC120_ADCMPBNSR_CMPLB = 0x80
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value > A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): A/D-converted value < ADWINLLB value, or ADWINULB value < A/D-converted value
	ADC120_ADCMPBNSR_CMPLB_0 = 0x0
	// When window function is disabled (ADCMPCR.WCMPE = 0): ADWINLLB value < A/D-converted value When window function is enabled (ADCMPCR.WCMPE = 1): ADWINLLB value < A/D-converted value < ADWINULB value
	ADC120_ADCMPBNSR_CMPLB_1 = 0x1

	// ADCMPBSR: A/D Compare Function Window B Status Register
	// Position of CMPSTB field.
	ADC120_ADCMPBSR_CMPSTB_Pos = 0x0
	// Bit mask of CMPSTB field.
	ADC120_ADCMPBSR_CMPSTB_Msk = 0x1
	// Bit CMPSTB.
	ADC120_ADCMPBSR_CMPSTB = 0x1
	// Comparison conditions are not met.
	ADC120_ADCMPBSR_CMPSTB_0 = 0x0
	// Comparison conditions are met.
	ADC120_ADCMPBSR_CMPSTB_1 = 0x1

	// ADBUF0: A/D Data Buffer Registers %s
	// Position of ADBUF field.
	ADC120_ADBUF_ADBUF_Pos = 0x0
	// Bit mask of ADBUF field.
	ADC120_ADBUF_ADBUF_Msk = 0xffff

	// ADBUFEN: A/D Data Buffer Enable Register
	// Position of BUFEN field.
	ADC120_ADBUFEN_BUFEN_Pos = 0x0
	// Bit mask of BUFEN field.
	ADC120_ADBUFEN_BUFEN_Msk = 0x1
	// Bit BUFEN.
	ADC120_ADBUFEN_BUFEN = 0x1
	// The data buffer is not used.
	ADC120_ADBUFEN_BUFEN_0 = 0x0
	// The data buffer is used.
	ADC120_ADBUFEN_BUFEN_1 = 0x1

	// ADBUFPTR: A/D Data Buffer Pointer Register
	// Position of BUFPTR field.
	ADC120_ADBUFPTR_BUFPTR_Pos = 0x0
	// Bit mask of BUFPTR field.
	ADC120_ADBUFPTR_BUFPTR_Msk = 0xf
	// Position of PTROVF field.
	ADC120_ADBUFPTR_PTROVF_Pos = 0x4
	// Bit mask of PTROVF field.
	ADC120_ADBUFPTR_PTROVF_Msk = 0x10
	// Bit PTROVF.
	ADC120_ADBUFPTR_PTROVF = 0x10
	// The data buffer pointer has not overflowed.
	ADC120_ADBUFPTR_PTROVF_0 = 0x0
	// The data buffer pointer has overflowed.
	ADC120_ADBUFPTR_PTROVF_1 = 0x1

	// ADSSTRL: A/D Sampling State Register
	// Position of SST field.
	ADC120_ADSSTRL_SST_Pos = 0x0
	// Bit mask of SST field.
	ADC120_ADSSTRL_SST_Msk = 0xff

	// ADSSTRT: A/D Sampling State Register
	// Position of SST field.
	ADC120_ADSSTRT_SST_Pos = 0x0
	// Bit mask of SST field.
	ADC120_ADSSTRT_SST_Msk = 0xff

	// ADSSTRO: A/D Sampling State Register
	// Position of SST field.
	ADC120_ADSSTRO_SST_Pos = 0x0
	// Bit mask of SST field.
	ADC120_ADSSTRO_SST_Msk = 0xff

	// ADSSTR0: A/D Sampling State Register
	// Position of SST field.
	ADC120_ADSSTR_SST_Pos = 0x0
	// Bit mask of SST field.
	ADC120_ADSSTR_SST_Msk = 0xff

	// ADSSTR4: A/D Sampling State Register
	// Position of SST field.
	ADC120_ADSSTR_SST_Pos = 0x0
	// Bit mask of SST field.
	ADC120_ADSSTR_SST_Msk = 0xff

	// ADSSTR11: A/D Sampling State Register
	// Position of SST field.
	ADC120_ADSSTR_SST_Pos = 0x0
	// Bit mask of SST field.
	ADC120_ADSSTR_SST_Msk = 0xff
)

// Constants for DAC12: 12-bit D/A converter
const (
	// DACR: D/A Control Register
	// Position of DAE field.
	DAC12_DACR_DAE_Pos = 0x5
	// Bit mask of DAE field.
	DAC12_DACR_DAE_Msk = 0x20
	// Bit DAE.
	DAC12_DACR_DAE = 0x20
	// Control D/A conversion of channels 0 and 1 individually
	DAC12_DACR_DAE_0 = 0x0
	// Control D/A conversion of channels 0 and 1 collectively
	DAC12_DACR_DAE_1 = 0x1
	// Position of DAOE0 field.
	DAC12_DACR_DAOE0_Pos = 0x6
	// Bit mask of DAOE0 field.
	DAC12_DACR_DAOE0_Msk = 0x40
	// Bit DAOE0.
	DAC12_DACR_DAOE0 = 0x40
	// Disable analog output of channel 0 (DA0)
	DAC12_DACR_DAOE0_0 = 0x0
	// Enable D/A conversion of channel 0 (DA0)
	DAC12_DACR_DAOE0_1 = 0x1
	// Position of DAOE1 field.
	DAC12_DACR_DAOE1_Pos = 0x7
	// Bit mask of DAOE1 field.
	DAC12_DACR_DAOE1_Msk = 0x80
	// Bit DAOE1.
	DAC12_DACR_DAOE1 = 0x80
	// Disable analog output of channel 1 (DA1)
	DAC12_DACR_DAOE1_0 = 0x0
	// Enable D/A conversion of channel 1 (DA1)
	DAC12_DACR_DAOE1_1 = 0x1

	// DADPR: DADRn Format Select Register
	// Position of DPSEL field.
	DAC12_DADPR_DPSEL_Pos = 0x7
	// Bit mask of DPSEL field.
	DAC12_DADPR_DPSEL_Msk = 0x80
	// Bit DPSEL.
	DAC12_DADPR_DPSEL = 0x80
	// Right-justified format
	DAC12_DADPR_DPSEL_0 = 0x0
	// Left-justified format
	DAC12_DADPR_DPSEL_1 = 0x1

	// DAADSCR: D/A A/D Synchronous Start Control Register
	// Position of DAADST field.
	DAC12_DAADSCR_DAADST_Pos = 0x7
	// Bit mask of DAADST field.
	DAC12_DAADSCR_DAADST_Msk = 0x80
	// Bit DAADST.
	DAC12_DAADSCR_DAADST = 0x80
	// Do not synchronize DAC12 with ADC12 operation (disable interference reduction between D/A and A/D conversion).
	DAC12_DAADSCR_DAADST_0 = 0x0
	// Synchronize DAC12 with ADC12 operation (enable interference reduction between D/A and A/D conversion).
	DAC12_DAADSCR_DAADST_1 = 0x1

	// DAAMPCR: D/A Output Amplifier Control Register
	// Position of DAAMP0 field.
	DAC12_DAAMPCR_DAAMP0_Pos = 0x6
	// Bit mask of DAAMP0 field.
	DAC12_DAAMPCR_DAAMP0_Msk = 0x40
	// Bit DAAMP0.
	DAC12_DAAMPCR_DAAMP0 = 0x40
	// Do not use channel 0 output amplifier
	DAC12_DAAMPCR_DAAMP0_0 = 0x0
	// Use channel 0 output amplifier
	DAC12_DAAMPCR_DAAMP0_1 = 0x1
	// Position of DAAMP1 field.
	DAC12_DAAMPCR_DAAMP1_Pos = 0x7
	// Bit mask of DAAMP1 field.
	DAC12_DAAMPCR_DAAMP1_Msk = 0x80
	// Bit DAAMP1.
	DAC12_DAAMPCR_DAAMP1 = 0x80
	// Do not use channel 1 output amplifier
	DAC12_DAAMPCR_DAAMP1_0 = 0x0
	// Use channel 1 output amplifier
	DAC12_DAAMPCR_DAAMP1_1 = 0x1

	// DAASWCR: D/A Amplifier Stabilization Wait Control Register
	// Position of DAASW0 field.
	DAC12_DAASWCR_DAASW0_Pos = 0x6
	// Bit mask of DAASW0 field.
	DAC12_DAASWCR_DAASW0_Msk = 0x40
	// Bit DAASW0.
	DAC12_DAASWCR_DAASW0 = 0x40
	// Amplifier stabilization wait off (output) for channel 0
	DAC12_DAASWCR_DAASW0_0 = 0x0
	// Amplifier stabilization wait on (high-Z) for channel 0
	DAC12_DAASWCR_DAASW0_1 = 0x1
	// Position of DAASW1 field.
	DAC12_DAASWCR_DAASW1_Pos = 0x7
	// Bit mask of DAASW1 field.
	DAC12_DAASWCR_DAASW1_Msk = 0x80
	// Bit DAASW1.
	DAC12_DAASWCR_DAASW1 = 0x80
	// Amplifier stabilization wait off (output) for channel 1
	DAC12_DAASWCR_DAASW1_0 = 0x0
	// Amplifier stabilization wait on (high-Z) for channel 1
	DAC12_DAASWCR_DAASW1_1 = 0x1

	// DAADUSR: D/A A/D Synchronous Unit Select Register
	// Position of AMADSEL0 field.
	DAC12_DAADUSR_AMADSEL0_Pos = 0x0
	// Bit mask of AMADSEL0 field.
	DAC12_DAADUSR_AMADSEL0_Msk = 0x1
	// Bit AMADSEL0.
	DAC12_DAADUSR_AMADSEL0 = 0x1
	// Do not select unit 0
	DAC12_DAADUSR_AMADSEL0_0 = 0x0
	// Select unit 0
	DAC12_DAADUSR_AMADSEL0_1 = 0x1
)

// Constants for TSD: Temperature Sensor Calibration Data
const (
	// TSCDR: Temperature Sensor Calibration Data Register
	// Position of TSCDR field.
	TSD_TSCDR_TSCDR_Pos = 0x0
	// Bit mask of TSCDR field.
	TSD_TSCDR_TSCDR_Msk = 0xffff
)

// Constants for FLAD: Data Flash
const (
	// FCKMHZ: Data Flash Access Frequency Register
	// Position of FCKMHZ field.
	FLAD_FCKMHZ_FCKMHZ_Pos = 0x0
	// Bit mask of FCKMHZ field.
	FLAD_FCKMHZ_FCKMHZ_Msk = 0xff
)

// Constants for FACI: Flash/CPU Interface
const (
	// FASTAT: Flash Access Status Register
	// Position of DFAE field.
	FACI_FASTAT_DFAE_Pos = 0x3
	// Bit mask of DFAE field.
	FACI_FASTAT_DFAE_Msk = 0x8
	// Bit DFAE.
	FACI_FASTAT_DFAE = 0x8
	// No data flash memory access violation has occurred
	FACI_FASTAT_DFAE_0 = 0x0
	// A data flash memory access violation has occurred.
	FACI_FASTAT_DFAE_1 = 0x1
	// Position of CMDLK field.
	FACI_FASTAT_CMDLK_Pos = 0x4
	// Bit mask of CMDLK field.
	FACI_FASTAT_CMDLK_Msk = 0x10
	// Bit CMDLK.
	FACI_FASTAT_CMDLK = 0x10
	// The flash sequencer is not in the command-locked state
	FACI_FASTAT_CMDLK_0 = 0x0
	// The flash sequencer is in the command-locked state.
	FACI_FASTAT_CMDLK_1 = 0x1
	// Position of CFAE field.
	FACI_FASTAT_CFAE_Pos = 0x7
	// Bit mask of CFAE field.
	FACI_FASTAT_CFAE_Msk = 0x80
	// Bit CFAE.
	FACI_FASTAT_CFAE = 0x80
	// No code flash memory access violation has occurred
	FACI_FASTAT_CFAE_0 = 0x0
	// A code flash memory access violation has occurred.
	FACI_FASTAT_CFAE_1 = 0x1

	// FAEINT: Flash Access Error Interrupt Enable Register
	// Position of DFAEIE field.
	FACI_FAEINT_DFAEIE_Pos = 0x3
	// Bit mask of DFAEIE field.
	FACI_FAEINT_DFAEIE_Msk = 0x8
	// Bit DFAEIE.
	FACI_FAEINT_DFAEIE = 0x8
	// Generation of an FIFERR interrupt request is disabled when FASTAT.DFAE is set to 1
	FACI_FAEINT_DFAEIE_0 = 0x0
	// Generation of an FIFERR interrupt request is enabled when FASTAT.DFAE is set to 1.
	FACI_FAEINT_DFAEIE_1 = 0x1
	// Position of CMDLKIE field.
	FACI_FAEINT_CMDLKIE_Pos = 0x4
	// Bit mask of CMDLKIE field.
	FACI_FAEINT_CMDLKIE_Msk = 0x10
	// Bit CMDLKIE.
	FACI_FAEINT_CMDLKIE = 0x10
	// Generation of an FIFERR interrupt request is disabled when FASTAT.CMDLK is set to 1
	FACI_FAEINT_CMDLKIE_0 = 0x0
	// Generation of an FIFERR interrupt request is enabled when FASTAT.CMDLK is set to 1.
	FACI_FAEINT_CMDLKIE_1 = 0x1
	// Position of CFAEIE field.
	FACI_FAEINT_CFAEIE_Pos = 0x7
	// Bit mask of CFAEIE field.
	FACI_FAEINT_CFAEIE_Msk = 0x80
	// Bit CFAEIE.
	FACI_FAEINT_CFAEIE = 0x80
	// Generation of an FIFERR interrupt request is disabled when FASTAT.CFAE is set to 1
	FACI_FAEINT_CFAEIE_0 = 0x0
	// Generation of an FIFERR interrupt request is enabled when FASTAT.CFAE is set to 1.
	FACI_FAEINT_CFAEIE_1 = 0x1

	// FRDYIE: Flash Ready Interrupt Enable Register
	// Position of FRDYIE field.
	FACI_FRDYIE_FRDYIE_Pos = 0x0
	// Bit mask of FRDYIE field.
	FACI_FRDYIE_FRDYIE_Msk = 0x1
	// Bit FRDYIE.
	FACI_FRDYIE_FRDYIE = 0x1
	// Generation of an FRDY interrupt request is disabled
	FACI_FRDYIE_FRDYIE_0 = 0x0
	// Generation of an FRDY interrupt request is enabled.
	FACI_FRDYIE_FRDYIE_1 = 0x1

	// FEADDR: FACI Command End Address Register
	// Position of FEADDR field.
	FACI_FEADDR_FEADDR_Pos = 0x0
	// Bit mask of FEADDR field.
	FACI_FEADDR_FEADDR_Msk = 0xffffffff

	// FMEPROT: Flash P/E Mode Entry Protection Register
	// Position of CEPROT field.
	FACI_FMEPROT_CEPROT_Pos = 0x0
	// Bit mask of CEPROT field.
	FACI_FMEPROT_CEPROT_Msk = 0x1
	// Bit CEPROT.
	FACI_FMEPROT_CEPROT = 0x1
	// FENTRYC bit is not protected
	FACI_FMEPROT_CEPROT_0 = 0x0
	// FENTRYC bit is protected.
	FACI_FMEPROT_CEPROT_1 = 0x1
	// Position of KEY field.
	FACI_FMEPROT_KEY_Pos = 0x8
	// Bit mask of KEY field.
	FACI_FMEPROT_KEY_Msk = 0xff00

	// FBPROT1: Flash Block Protection for Secure Register
	// Position of BPCN1 field.
	FACI_FBPROT1_BPCN1_Pos = 0x0
	// Bit mask of BPCN1 field.
	FACI_FBPROT1_BPCN1_Msk = 0x1
	// Bit BPCN1.
	FACI_FBPROT1_BPCN1 = 0x1
	// Block protection is enabled
	FACI_FBPROT1_BPCN1_0 = 0x0
	// Block protection is disabled.
	FACI_FBPROT1_BPCN1_1 = 0x1
	// Position of KEY field.
	FACI_FBPROT1_KEY_Pos = 0x8
	// Bit mask of KEY field.
	FACI_FBPROT1_KEY_Msk = 0xff00

	// FSTATR: Flash Status Register
	// Position of FLWEERR field.
	FACI_FSTATR_FLWEERR_Pos = 0x6
	// Bit mask of FLWEERR field.
	FACI_FSTATR_FLWEERR_Msk = 0x40
	// Bit FLWEERR.
	FACI_FSTATR_FLWEERR = 0x40
	// An error has not occurred
	FACI_FSTATR_FLWEERR_0 = 0x0
	// An error has occurred.
	FACI_FSTATR_FLWEERR_1 = 0x1
	// Position of PRGSPD field.
	FACI_FSTATR_PRGSPD_Pos = 0x8
	// Bit mask of PRGSPD field.
	FACI_FSTATR_PRGSPD_Msk = 0x100
	// Bit PRGSPD.
	FACI_FSTATR_PRGSPD = 0x100
	// The flash sequencer is not in the programming suspension processing state or programming suspended state
	FACI_FSTATR_PRGSPD_0 = 0x0
	// The flash sequencer is in the programming suspension processing state or programming suspended state.
	FACI_FSTATR_PRGSPD_1 = 0x1
	// Position of ERSSPD field.
	FACI_FSTATR_ERSSPD_Pos = 0x9
	// Bit mask of ERSSPD field.
	FACI_FSTATR_ERSSPD_Msk = 0x200
	// Bit ERSSPD.
	FACI_FSTATR_ERSSPD = 0x200
	// The flash sequencer is not in the erasure suspension processing state or the erasure suspended state
	FACI_FSTATR_ERSSPD_0 = 0x0
	// The flash sequencer is in the erasure suspension processing state or the erasure suspended state.
	FACI_FSTATR_ERSSPD_1 = 0x1
	// Position of DBFULL field.
	FACI_FSTATR_DBFULL_Pos = 0xa
	// Bit mask of DBFULL field.
	FACI_FSTATR_DBFULL_Msk = 0x400
	// Bit DBFULL.
	FACI_FSTATR_DBFULL = 0x400
	// The data buffer is empty
	FACI_FSTATR_DBFULL_0 = 0x0
	// The data buffer is full.
	FACI_FSTATR_DBFULL_1 = 0x1
	// Position of SUSRDY field.
	FACI_FSTATR_SUSRDY_Pos = 0xb
	// Bit mask of SUSRDY field.
	FACI_FSTATR_SUSRDY_Msk = 0x800
	// Bit SUSRDY.
	FACI_FSTATR_SUSRDY = 0x800
	// The flash sequencer cannot receive P/E suspend commands
	FACI_FSTATR_SUSRDY_0 = 0x0
	// The flash sequencer can receive P/E suspend commands.
	FACI_FSTATR_SUSRDY_1 = 0x1
	// Position of PRGERR field.
	FACI_FSTATR_PRGERR_Pos = 0xc
	// Bit mask of PRGERR field.
	FACI_FSTATR_PRGERR_Msk = 0x1000
	// Bit PRGERR.
	FACI_FSTATR_PRGERR = 0x1000
	// Programming has completed successfully
	FACI_FSTATR_PRGERR_0 = 0x0
	// An error has occurred during programming.
	FACI_FSTATR_PRGERR_1 = 0x1
	// Position of ERSERR field.
	FACI_FSTATR_ERSERR_Pos = 0xd
	// Bit mask of ERSERR field.
	FACI_FSTATR_ERSERR_Msk = 0x2000
	// Bit ERSERR.
	FACI_FSTATR_ERSERR = 0x2000
	// Erasure has completed successfully
	FACI_FSTATR_ERSERR_0 = 0x0
	// An error has occurred during erasure.
	FACI_FSTATR_ERSERR_1 = 0x1
	// Position of ILGLERR field.
	FACI_FSTATR_ILGLERR_Pos = 0xe
	// Bit mask of ILGLERR field.
	FACI_FSTATR_ILGLERR_Msk = 0x4000
	// Bit ILGLERR.
	FACI_FSTATR_ILGLERR = 0x4000
	// The flash sequencer has not detected an illegal FACI command or illegal flash memory access
	FACI_FSTATR_ILGLERR_0 = 0x0
	// The flash sequencer has detected an illegal FACI command or illegal flash memory access.
	FACI_FSTATR_ILGLERR_1 = 0x1
	// Position of FRDY field.
	FACI_FSTATR_FRDY_Pos = 0xf
	// Bit mask of FRDY field.
	FACI_FSTATR_FRDY_Msk = 0x8000
	// Bit FRDY.
	FACI_FSTATR_FRDY = 0x8000
	// Program, Block Erase, Multi Block Erase, P/E suspend, P/E resume, Forced Stop, Blank Check, or Configuration set command processing is in progress
	FACI_FSTATR_FRDY_0 = 0x0
	// None of the above is in progress.
	FACI_FSTATR_FRDY_1 = 0x1
	// Position of OTERR field.
	FACI_FSTATR_OTERR_Pos = 0x14
	// Bit mask of OTERR field.
	FACI_FSTATR_OTERR_Msk = 0x100000
	// Bit OTERR.
	FACI_FSTATR_OTERR = 0x100000
	// A status clear or forced stop command processing is complete
	FACI_FSTATR_OTERR_0 = 0x0
	// An error has occurred.
	FACI_FSTATR_OTERR_1 = 0x1
	// Position of SECERR field.
	FACI_FSTATR_SECERR_Pos = 0x15
	// Bit mask of SECERR field.
	FACI_FSTATR_SECERR_Msk = 0x200000
	// Bit SECERR.
	FACI_FSTATR_SECERR = 0x200000
	// A status clear or forced stop command processing is complete
	FACI_FSTATR_SECERR_0 = 0x0
	// An error has occurred.
	FACI_FSTATR_SECERR_1 = 0x1
	// Position of FESETERR field.
	FACI_FSTATR_FESETERR_Pos = 0x16
	// Bit mask of FESETERR field.
	FACI_FSTATR_FESETERR_Msk = 0x400000
	// Bit FESETERR.
	FACI_FSTATR_FESETERR = 0x400000
	// A status clear or forced stop command processing is complete
	FACI_FSTATR_FESETERR_0 = 0x0
	// An error has occurred.
	FACI_FSTATR_FESETERR_1 = 0x1
	// Position of ILGCOMERR field.
	FACI_FSTATR_ILGCOMERR_Pos = 0x17
	// Bit mask of ILGCOMERR field.
	FACI_FSTATR_ILGCOMERR_Msk = 0x800000
	// Bit ILGCOMERR.
	FACI_FSTATR_ILGCOMERR = 0x800000
	// A status clear or forced stop command processing is complete
	FACI_FSTATR_ILGCOMERR_0 = 0x0
	// An error has occurred.
	FACI_FSTATR_ILGCOMERR_1 = 0x1

	// FENTRYR: Flash P/E Mode Entry Register
	// Position of FENTRYC field.
	FACI_FENTRYR_FENTRYC_Pos = 0x0
	// Bit mask of FENTRYC field.
	FACI_FENTRYR_FENTRYC_Msk = 0x1
	// Bit FENTRYC.
	FACI_FENTRYR_FENTRYC = 0x1
	// Code flash is in read mode
	FACI_FENTRYR_FENTRYC_0 = 0x0
	// Code flash is in P/E mode.
	FACI_FENTRYR_FENTRYC_1 = 0x1
	// Position of FENTRYD field.
	FACI_FENTRYR_FENTRYD_Pos = 0x7
	// Bit mask of FENTRYD field.
	FACI_FENTRYR_FENTRYD_Msk = 0x80
	// Bit FENTRYD.
	FACI_FENTRYR_FENTRYD = 0x80
	// Data flash is in read mode
	FACI_FENTRYR_FENTRYD_0 = 0x0
	// Data flash is in P/E mode.
	FACI_FENTRYR_FENTRYD_1 = 0x1
	// Position of KEY field.
	FACI_FENTRYR_KEY_Pos = 0x8
	// Bit mask of KEY field.
	FACI_FENTRYR_KEY_Msk = 0xff00

	// FSUINITR: Flash Sequencer Setup Initialization Register
	// Position of SUINIT field.
	FACI_FSUINITR_SUINIT_Pos = 0x0
	// Bit mask of SUINIT field.
	FACI_FSUINITR_SUINIT_Msk = 0x1
	// Bit SUINIT.
	FACI_FSUINITR_SUINIT = 0x1
	// The FSADDR, FEADDR, FBPROT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers keep their current values
	FACI_FSUINITR_SUINIT_0 = 0x0
	// The FSADDR, FEADDR, FBRPOT1, FENTRYR, FBCCNT, and FCPSR flash sequencer setup registers are initialized.
	FACI_FSUINITR_SUINIT_1 = 0x1
	// Position of KEY field.
	FACI_FSUINITR_KEY_Pos = 0x8
	// Bit mask of KEY field.
	FACI_FSUINITR_KEY_Msk = 0xff00

	// FCMDR: FACI Command Register
	// Position of PCMDR field.
	FACI_FCMDR_PCMDR_Pos = 0x0
	// Bit mask of PCMDR field.
	FACI_FCMDR_PCMDR_Msk = 0xff
	// Position of CMDR field.
	FACI_FCMDR_CMDR_Pos = 0x8
	// Bit mask of CMDR field.
	FACI_FCMDR_CMDR_Msk = 0xff00

	// FBCCNT: Blank Check Control Register
	// Position of BCDIR field.
	FACI_FBCCNT_BCDIR_Pos = 0x0
	// Bit mask of BCDIR field.
	FACI_FBCCNT_BCDIR_Msk = 0x1
	// Bit BCDIR.
	FACI_FBCCNT_BCDIR = 0x1
	// Blank checking is executed from the lower addresses to the higher addresses (incremental mode)
	FACI_FBCCNT_BCDIR_0 = 0x0
	// Blank checking is executed from the higher addresses to the lower addresses (decremental mode).
	FACI_FBCCNT_BCDIR_1 = 0x1

	// FBCSTAT: Blank Check Status Register
	// Position of BCST field.
	FACI_FBCSTAT_BCST_Pos = 0x0
	// Bit mask of BCST field.
	FACI_FBCSTAT_BCST_Msk = 0x1
	// Bit BCST.
	FACI_FBCSTAT_BCST = 0x1
	// The target area is in the non-programmed state, that is, the area has been erased but has not yet been reprogrammed
	FACI_FBCSTAT_BCST_0 = 0x0
	// The target area has been programmed with 0s or 1s.
	FACI_FBCSTAT_BCST_1 = 0x1

	// FPSADDR: Data Flash Programming Start Address Register
	// Position of PSADR field.
	FACI_FPSADDR_PSADR_Pos = 0x0
	// Bit mask of PSADR field.
	FACI_FPSADDR_PSADR_Msk = 0x1ffff

	// FSUASMON: Flash Startup Area Select Monitor Register
	// Position of FSPR field.
	FACI_FSUASMON_FSPR_Pos = 0xf
	// Bit mask of FSPR field.
	FACI_FSUASMON_FSPR_Msk = 0x8000
	// Bit FSPR.
	FACI_FSUASMON_FSPR = 0x8000
	// Protected state
	FACI_FSUASMON_FSPR_0 = 0x0
	// Non-protected state.
	FACI_FSUASMON_FSPR_1 = 0x1
	// Position of BTFLG field.
	FACI_FSUASMON_BTFLG_Pos = 0x1f
	// Bit mask of BTFLG field.
	FACI_FSUASMON_BTFLG_Msk = 0x80000000
	// Bit BTFLG.
	FACI_FSUASMON_BTFLG = 0x80000000
	// The startup area is the alternate block (block 1)
	FACI_FSUASMON_BTFLG_0 = 0x0
	// The startup area is the default block (block 0).
	FACI_FSUASMON_BTFLG_1 = 0x1

	// FCPSR: Flash Sequencer Processing Switching Register
	// Position of ESUSPMD field.
	FACI_FCPSR_ESUSPMD_Pos = 0x0
	// Bit mask of ESUSPMD field.
	FACI_FCPSR_ESUSPMD_Msk = 0x1
	// Bit ESUSPMD.
	FACI_FCPSR_ESUSPMD = 0x1
	// Suspension priority mode
	FACI_FCPSR_ESUSPMD_0 = 0x0
	// Erasure priority mode.
	FACI_FCPSR_ESUSPMD_1 = 0x1

	// FPCKAR: Flash Sequencer Processing Clock Notification Register
	// Position of PCKA field.
	FACI_FPCKAR_PCKA_Pos = 0x0
	// Bit mask of PCKA field.
	FACI_FPCKAR_PCKA_Msk = 0xff
	// Position of KEY field.
	FACI_FPCKAR_KEY_Pos = 0x8
	// Bit mask of KEY field.
	FACI_FPCKAR_KEY_Msk = 0xff00

	// FSUACR: Flash Startup Area Control Register
	// Position of SAS field.
	FACI_FSUACR_SAS_Pos = 0x0
	// Bit mask of SAS field.
	FACI_FSUACR_SAS_Msk = 0x3
	// Startup area is selected by BTFLG bit
	FACI_FSUACR_SAS_00 = 0x0
	// Startup area is selected by BTFLG bit
	FACI_FSUACR_SAS_01 = 0x1
	// Startup area is temporarily switched to the default area (block 0)
	FACI_FSUACR_SAS_10 = 0x2
	// Startup area is temporarily switched to the alternate area (block 1).
	FACI_FSUACR_SAS_11 = 0x3
	// Position of KEY field.
	FACI_FSUACR_KEY_Pos = 0x8
	// Bit mask of KEY field.
	FACI_FSUACR_KEY_Msk = 0xff00
)

// Constants for QSPI: Quad Serial Peripheral Interface
const (
	// SFMSMD: Transfer Mode Control Register
	// Position of SFMRM field.
	QSPI_SFMSMD_SFMRM_Pos = 0x0
	// Bit mask of SFMRM field.
	QSPI_SFMSMD_SFMRM_Msk = 0x7
	// Standard Read
	QSPI_SFMSMD_SFMRM_000 = 0x0
	// Fast Read
	QSPI_SFMSMD_SFMRM_001 = 0x1
	// Fast Read Dual Output
	QSPI_SFMSMD_SFMRM_010 = 0x2
	// Fast Read Dual I/O
	QSPI_SFMSMD_SFMRM_011 = 0x3
	// Fast Read Quad Output
	QSPI_SFMSMD_SFMRM_100 = 0x4
	// Fast Read Quad I/O
	QSPI_SFMSMD_SFMRM_101 = 0x5
	// Setting prohibited
	QSPI_SFMSMD_SFMRM_Others = 0x6
	// Position of SFMSE field.
	QSPI_SFMSMD_SFMSE_Pos = 0x4
	// Bit mask of SFMSE field.
	QSPI_SFMSMD_SFMSE_Msk = 0x30
	// Do not extend QSSL
	QSPI_SFMSMD_SFMSE_00 = 0x0
	// Extend QSSL by 33 QSPCLK
	QSPI_SFMSMD_SFMSE_01 = 0x1
	// Extend QSSL by 129 QSPCLK
	QSPI_SFMSMD_SFMSE_10 = 0x2
	// Extend QSSL infinitely
	QSPI_SFMSMD_SFMSE_11 = 0x3
	// Position of SFMPFE field.
	QSPI_SFMSMD_SFMPFE_Pos = 0x6
	// Bit mask of SFMPFE field.
	QSPI_SFMSMD_SFMPFE_Msk = 0x40
	// Bit SFMPFE.
	QSPI_SFMSMD_SFMPFE = 0x40
	// Disable function
	QSPI_SFMSMD_SFMPFE_0 = 0x0
	// Enable function
	QSPI_SFMSMD_SFMPFE_1 = 0x1
	// Position of SFMPAE field.
	QSPI_SFMSMD_SFMPAE_Pos = 0x7
	// Bit mask of SFMPAE field.
	QSPI_SFMSMD_SFMPAE_Msk = 0x80
	// Bit SFMPAE.
	QSPI_SFMSMD_SFMPAE = 0x80
	// Disable function
	QSPI_SFMSMD_SFMPAE_0 = 0x0
	// Enable function
	QSPI_SFMSMD_SFMPAE_1 = 0x1
	// Position of SFMMD3 field.
	QSPI_SFMSMD_SFMMD3_Pos = 0x8
	// Bit mask of SFMMD3 field.
	QSPI_SFMSMD_SFMMD3_Msk = 0x100
	// Bit SFMMD3.
	QSPI_SFMSMD_SFMMD3 = 0x100
	// SPI mode 0
	QSPI_SFMSMD_SFMMD3_0 = 0x0
	// SPI mode 3
	QSPI_SFMSMD_SFMMD3_1 = 0x1
	// Position of SFMOEX field.
	QSPI_SFMSMD_SFMOEX_Pos = 0x9
	// Bit mask of SFMOEX field.
	QSPI_SFMSMD_SFMOEX_Msk = 0x200
	// Bit SFMOEX.
	QSPI_SFMSMD_SFMOEX = 0x200
	// Do not extend
	QSPI_SFMSMD_SFMOEX_0 = 0x0
	// Extend by 1 QSPCLK
	QSPI_SFMSMD_SFMOEX_1 = 0x1
	// Position of SFMOHW field.
	QSPI_SFMSMD_SFMOHW_Pos = 0xa
	// Bit mask of SFMOHW field.
	QSPI_SFMSMD_SFMOHW_Msk = 0x400
	// Bit SFMOHW.
	QSPI_SFMSMD_SFMOHW = 0x400
	// Do not extend high-level width of QSPCLK during transmission
	QSPI_SFMSMD_SFMOHW_0 = 0x0
	// Extend high-level width of QSPCLK by 1 PCLKA during transmission
	QSPI_SFMSMD_SFMOHW_1 = 0x1
	// Position of SFMOSW field.
	QSPI_SFMSMD_SFMOSW_Pos = 0xb
	// Bit mask of SFMOSW field.
	QSPI_SFMSMD_SFMOSW_Msk = 0x800
	// Bit SFMOSW.
	QSPI_SFMSMD_SFMOSW = 0x800
	// Do not extend low-level width of QSPCLK during transmission
	QSPI_SFMSMD_SFMOSW_0 = 0x0
	// Extend low-level width of QSPCLK by 1 PCLKA during transmission
	QSPI_SFMSMD_SFMOSW_1 = 0x1
	// Position of SFMCCE field.
	QSPI_SFMSMD_SFMCCE_Pos = 0xf
	// Bit mask of SFMCCE field.
	QSPI_SFMSMD_SFMCCE_Msk = 0x8000
	// Bit SFMCCE.
	QSPI_SFMSMD_SFMCCE = 0x8000
	// Uses automatically generated SPI instruction code
	QSPI_SFMSMD_SFMCCE_0 = 0x0
	// Use instruction code in the SFMSIC register
	QSPI_SFMSMD_SFMCCE_1 = 0x1

	// SFMSSC: Chip Selection Control Register
	// Position of SFMSW field.
	QSPI_SFMSSC_SFMSW_Pos = 0x0
	// Bit mask of SFMSW field.
	QSPI_SFMSSC_SFMSW_Msk = 0xf
	// 1 QSPCLK
	QSPI_SFMSSC_SFMSW_0x0 = 0x0
	// 2 QSPCLK
	QSPI_SFMSSC_SFMSW_0x1 = 0x1
	// 3 QSPCLK
	QSPI_SFMSSC_SFMSW_0x2 = 0x2
	// 4 QSPCLK
	QSPI_SFMSSC_SFMSW_0x3 = 0x3
	// 5 QSPCLK
	QSPI_SFMSSC_SFMSW_0x4 = 0x4
	// 6 QSPCLK
	QSPI_SFMSSC_SFMSW_0x5 = 0x5
	// 7 QSPCLK
	QSPI_SFMSSC_SFMSW_0x6 = 0x6
	// 8 QSPCLK
	QSPI_SFMSSC_SFMSW_0x7 = 0x7
	// 9 QSPCLK
	QSPI_SFMSSC_SFMSW_0x8 = 0x8
	// 10 QSPCLK
	QSPI_SFMSSC_SFMSW_0x9 = 0x9
	// 11 QSPCLK
	QSPI_SFMSSC_SFMSW_0xA = 0xa
	// 12 QSPCLK
	QSPI_SFMSSC_SFMSW_0xB = 0xb
	// 13 QSPCLK
	QSPI_SFMSSC_SFMSW_0xC = 0xc
	// 14 QSPCLK
	QSPI_SFMSSC_SFMSW_0xD = 0xd
	// 15 QSPCLK
	QSPI_SFMSSC_SFMSW_0xE = 0xe
	// 16 QSPCLK
	QSPI_SFMSSC_SFMSW_0xF = 0xf
	// Position of SFMSHD field.
	QSPI_SFMSSC_SFMSHD_Pos = 0x4
	// Bit mask of SFMSHD field.
	QSPI_SFMSSC_SFMSHD_Msk = 0x10
	// Bit SFMSHD.
	QSPI_SFMSSC_SFMSHD = 0x10
	// QSSL outputs high after 0.5 QSPCLK cycles from the last rising edge of QSPCLK.
	QSPI_SFMSSC_SFMSHD_0 = 0x0
	// QSSL outputs high after 1.5 QSPCLK cycles from the last rising edge of QSPCLK.
	QSPI_SFMSSC_SFMSHD_1 = 0x1
	// Position of SFMSLD field.
	QSPI_SFMSSC_SFMSLD_Pos = 0x5
	// Bit mask of SFMSLD field.
	QSPI_SFMSSC_SFMSLD_Msk = 0x20
	// Bit SFMSLD.
	QSPI_SFMSSC_SFMSLD = 0x20
	// QSSL outputs low before 0.5 QSPCLK cycles from the first rising edge of QSPCLK.
	QSPI_SFMSSC_SFMSLD_0 = 0x0
	// QSSL outputs low before 1.5 QSPCLK cycles from the first rising edge of QSPCLK.
	QSPI_SFMSSC_SFMSLD_1 = 0x1

	// SFMSKC: Clock Control Register
	// Position of SFMDV field.
	QSPI_SFMSKC_SFMDV_Pos = 0x0
	// Bit mask of SFMDV field.
	QSPI_SFMSKC_SFMDV_Msk = 0x1f
	// 2 PCLKA
	QSPI_SFMSKC_SFMDV_0x00 = 0x0
	// 3 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x01 = 0x1
	// 4 PCLKA
	QSPI_SFMSKC_SFMDV_0x02 = 0x2
	// 5 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x03 = 0x3
	// 6 PCLKA
	QSPI_SFMSKC_SFMDV_0x04 = 0x4
	// 7 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x05 = 0x5
	// 8 PCLKA
	QSPI_SFMSKC_SFMDV_0x06 = 0x6
	// 9 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x07 = 0x7
	// 10 PCLKA
	QSPI_SFMSKC_SFMDV_0x08 = 0x8
	// 11 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x09 = 0x9
	// 12 PCLKA
	QSPI_SFMSKC_SFMDV_0x0A = 0xa
	// 13 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x0B = 0xb
	// 14 PCLKA
	QSPI_SFMSKC_SFMDV_0x0C = 0xc
	// 15 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x0D = 0xd
	// 16 PCLKA
	QSPI_SFMSKC_SFMDV_0x0E = 0xe
	// 17 PCLKA (divided by an odd number)
	QSPI_SFMSKC_SFMDV_0x0F = 0xf
	// 18 PCLKA
	QSPI_SFMSKC_SFMDV_0x10 = 0x10
	// 20 PCLKA
	QSPI_SFMSKC_SFMDV_0x11 = 0x11
	// 22 PCLKA
	QSPI_SFMSKC_SFMDV_0x12 = 0x12
	// 24 PCLKA
	QSPI_SFMSKC_SFMDV_0x13 = 0x13
	// 26 PCLKA
	QSPI_SFMSKC_SFMDV_0x14 = 0x14
	// 28 PCLKA
	QSPI_SFMSKC_SFMDV_0x15 = 0x15
	// 30 PCLKA
	QSPI_SFMSKC_SFMDV_0x16 = 0x16
	// 32 PCLKA
	QSPI_SFMSKC_SFMDV_0x17 = 0x17
	// 34 PCLKA
	QSPI_SFMSKC_SFMDV_0x18 = 0x18
	// 36 PCLKA
	QSPI_SFMSKC_SFMDV_0x19 = 0x19
	// 38 PCLKA
	QSPI_SFMSKC_SFMDV_0x1A = 0x1a
	// 40 PCLKA
	QSPI_SFMSKC_SFMDV_0x1B = 0x1b
	// 42 PCLKA
	QSPI_SFMSKC_SFMDV_0x1C = 0x1c
	// 44 PCLKA
	QSPI_SFMSKC_SFMDV_0x1D = 0x1d
	// 46 PCLKA
	QSPI_SFMSKC_SFMDV_0x1E = 0x1e
	// 48 PCLKA
	QSPI_SFMSKC_SFMDV_0x1F = 0x1f
	// Position of SFMDTY field.
	QSPI_SFMSKC_SFMDTY_Pos = 0x5
	// Bit mask of SFMDTY field.
	QSPI_SFMSKC_SFMDTY_Msk = 0x20
	// Bit SFMDTY.
	QSPI_SFMSKC_SFMDTY = 0x20
	// Make no correction
	QSPI_SFMSKC_SFMDTY_0 = 0x0
	// Make correction
	QSPI_SFMSKC_SFMDTY_1 = 0x1

	// SFMSST: Status Register
	// Position of PFCNT field.
	QSPI_SFMSST_PFCNT_Pos = 0x0
	// Bit mask of PFCNT field.
	QSPI_SFMSST_PFCNT_Msk = 0x1f
	// 0 byte
	QSPI_SFMSST_PFCNT_0x00 = 0x0
	// 1 byte
	QSPI_SFMSST_PFCNT_0x01 = 0x1
	// 2 bytes
	QSPI_SFMSST_PFCNT_0x02 = 0x2
	// 3 bytes
	QSPI_SFMSST_PFCNT_0x03 = 0x3
	// 4 bytes
	QSPI_SFMSST_PFCNT_0x04 = 0x4
	// 5 bytes
	QSPI_SFMSST_PFCNT_0x05 = 0x5
	// 6 bytes
	QSPI_SFMSST_PFCNT_0x06 = 0x6
	// 7 bytes
	QSPI_SFMSST_PFCNT_0x07 = 0x7
	// 8 bytes
	QSPI_SFMSST_PFCNT_0x08 = 0x8
	// 9 bytes
	QSPI_SFMSST_PFCNT_0x09 = 0x9
	// 10 bytes
	QSPI_SFMSST_PFCNT_0x0A = 0xa
	// 11 bytes
	QSPI_SFMSST_PFCNT_0x0B = 0xb
	// 12 bytes
	QSPI_SFMSST_PFCNT_0x0C = 0xc
	// 13 bytes
	QSPI_SFMSST_PFCNT_0x0D = 0xd
	// 14 bytes
	QSPI_SFMSST_PFCNT_0x0E = 0xe
	// 15 bytes
	QSPI_SFMSST_PFCNT_0x0F = 0xf
	// 16 bytes
	QSPI_SFMSST_PFCNT_0x10 = 0x10
	// 17 bytes
	QSPI_SFMSST_PFCNT_0x11 = 0x11
	// 18 bytes
	QSPI_SFMSST_PFCNT_0x12 = 0x12
	// Reserved
	QSPI_SFMSST_PFCNT_Others = 0x13
	// Position of PFFUL field.
	QSPI_SFMSST_PFFUL_Pos = 0x6
	// Bit mask of PFFUL field.
	QSPI_SFMSST_PFFUL_Msk = 0x40
	// Bit PFFUL.
	QSPI_SFMSST_PFFUL = 0x40
	// Prefetch buffer has free space
	QSPI_SFMSST_PFFUL_0 = 0x0
	// Prefetch buffer is full
	QSPI_SFMSST_PFFUL_1 = 0x1
	// Position of PFOFF field.
	QSPI_SFMSST_PFOFF_Pos = 0x7
	// Bit mask of PFOFF field.
	QSPI_SFMSST_PFOFF_Msk = 0x80
	// Bit PFOFF.
	QSPI_SFMSST_PFOFF = 0x80
	// Prefetch function operating
	QSPI_SFMSST_PFOFF_0 = 0x0
	// Prefetch function not enabled or not operating
	QSPI_SFMSST_PFOFF_1 = 0x1

	// SFMCOM: Communication Port Register
	// Position of SFMD field.
	QSPI_SFMCOM_SFMD_Pos = 0x0
	// Bit mask of SFMD field.
	QSPI_SFMCOM_SFMD_Msk = 0xff

	// SFMCMD: Communication Mode Control Register
	// Position of DCOM field.
	QSPI_SFMCMD_DCOM_Pos = 0x0
	// Bit mask of DCOM field.
	QSPI_SFMCMD_DCOM_Msk = 0x1
	// Bit DCOM.
	QSPI_SFMCMD_DCOM = 0x1
	// ROM access mode
	QSPI_SFMCMD_DCOM_0 = 0x0
	// Direct communication mode
	QSPI_SFMCMD_DCOM_1 = 0x1

	// SFMCST: Communication Status Register
	// Position of COMBSY field.
	QSPI_SFMCST_COMBSY_Pos = 0x0
	// Bit mask of COMBSY field.
	QSPI_SFMCST_COMBSY_Msk = 0x1
	// Bit COMBSY.
	QSPI_SFMCST_COMBSY = 0x1
	// No serial transfer being processed
	QSPI_SFMCST_COMBSY_0 = 0x0
	// Serial transfer being processed
	QSPI_SFMCST_COMBSY_1 = 0x1
	// Position of EROMR field.
	QSPI_SFMCST_EROMR_Pos = 0x7
	// Bit mask of EROMR field.
	QSPI_SFMCST_EROMR_Msk = 0x80
	// Bit EROMR.
	QSPI_SFMCST_EROMR = 0x80
	// ROM access not detected
	QSPI_SFMCST_EROMR_0 = 0x0
	// ROM access detected
	QSPI_SFMCST_EROMR_1 = 0x1

	// SFMSIC: Instruction Code Register
	// Position of SFMCIC field.
	QSPI_SFMSIC_SFMCIC_Pos = 0x0
	// Bit mask of SFMCIC field.
	QSPI_SFMSIC_SFMCIC_Msk = 0xff

	// SFMSAC: Address Mode Control Register
	// Position of SFMAS field.
	QSPI_SFMSAC_SFMAS_Pos = 0x0
	// Bit mask of SFMAS field.
	QSPI_SFMSAC_SFMAS_Msk = 0x3
	// 1 byte
	QSPI_SFMSAC_SFMAS_00 = 0x0
	// 2 bytes
	QSPI_SFMSAC_SFMAS_01 = 0x1
	// 3 bytes
	QSPI_SFMSAC_SFMAS_10 = 0x2
	// 4 bytes
	QSPI_SFMSAC_SFMAS_11 = 0x3
	// Position of SFM4BC field.
	QSPI_SFMSAC_SFM4BC_Pos = 0x4
	// Bit mask of SFM4BC field.
	QSPI_SFMSAC_SFM4BC_Msk = 0x10
	// Bit SFM4BC.
	QSPI_SFMSAC_SFM4BC = 0x10
	// Do not use 4-byte address read instruction code
	QSPI_SFMSAC_SFM4BC_0 = 0x0
	// Use 4-byte address read instruction code
	QSPI_SFMSAC_SFM4BC_1 = 0x1

	// SFMSDC: Dummy Cycle Control Register
	// Position of SFMDN field.
	QSPI_SFMSDC_SFMDN_Pos = 0x0
	// Bit mask of SFMDN field.
	QSPI_SFMSDC_SFMDN_Msk = 0xf
	// Default dummy cycles for each instruction: - Fast Read Quad I/O: 6 QSPCLK - Fast Read Quad Output: 8 QSPCLK - Fast Read Dual I/O: 4 QSPCLK - Fast Read Dual Output: 8 QSPCLK - Fast Read: 8 QSPCLK
	QSPI_SFMSDC_SFMDN_0x0 = 0x0
	// 3 QSPCLK
	QSPI_SFMSDC_SFMDN_0x1 = 0x1
	// 4 QSPCLK
	QSPI_SFMSDC_SFMDN_0x2 = 0x2
	// 5 QSPCLK
	QSPI_SFMSDC_SFMDN_0x3 = 0x3
	// 6 QSPCLK
	QSPI_SFMSDC_SFMDN_0x4 = 0x4
	// 7 QSPCLK
	QSPI_SFMSDC_SFMDN_0x5 = 0x5
	// 8 QSPCLK
	QSPI_SFMSDC_SFMDN_0x6 = 0x6
	// 9 QSPCLK
	QSPI_SFMSDC_SFMDN_0x7 = 0x7
	// 10 QSPCLK
	QSPI_SFMSDC_SFMDN_0x8 = 0x8
	// 11 QSPCLK
	QSPI_SFMSDC_SFMDN_0x9 = 0x9
	// 12 QSPCLK
	QSPI_SFMSDC_SFMDN_0xA = 0xa
	// 13 QSPCLK
	QSPI_SFMSDC_SFMDN_0xB = 0xb
	// 14 QSPCLK
	QSPI_SFMSDC_SFMDN_0xC = 0xc
	// 15 QSPCLK
	QSPI_SFMSDC_SFMDN_0xD = 0xd
	// 16 QSPCLK
	QSPI_SFMSDC_SFMDN_0xE = 0xe
	// 17 QSPCLK
	QSPI_SFMSDC_SFMDN_0xF = 0xf
	// Position of SFMXST field.
	QSPI_SFMSDC_SFMXST_Pos = 0x6
	// Bit mask of SFMXST field.
	QSPI_SFMSDC_SFMXST_Msk = 0x40
	// Bit SFMXST.
	QSPI_SFMSDC_SFMXST = 0x40
	// Normal (non-XIP) mode
	QSPI_SFMSDC_SFMXST_0 = 0x0
	// XIP mode
	QSPI_SFMSDC_SFMXST_1 = 0x1
	// Position of SFMXEN field.
	QSPI_SFMSDC_SFMXEN_Pos = 0x7
	// Bit mask of SFMXEN field.
	QSPI_SFMSDC_SFMXEN_Msk = 0x80
	// Bit SFMXEN.
	QSPI_SFMSDC_SFMXEN = 0x80
	// Prohibit XIP mode
	QSPI_SFMSDC_SFMXEN_0 = 0x0
	// Permit XIP mode
	QSPI_SFMSDC_SFMXEN_1 = 0x1
	// Position of SFMXD field.
	QSPI_SFMSDC_SFMXD_Pos = 0x8
	// Bit mask of SFMXD field.
	QSPI_SFMSDC_SFMXD_Msk = 0xff00

	// SFMSPC: SPI Protocol Control Register
	// Position of SFMSPI field.
	QSPI_SFMSPC_SFMSPI_Pos = 0x0
	// Bit mask of SFMSPI field.
	QSPI_SFMSPC_SFMSPI_Msk = 0x3
	// Single SPI Protocol, Extended SPI protocol
	QSPI_SFMSPC_SFMSPI_00 = 0x0
	// Dual SPI protocol
	QSPI_SFMSPC_SFMSPI_01 = 0x1
	// Quad SPI protocol
	QSPI_SFMSPC_SFMSPI_10 = 0x2
	// Setting prohibited
	QSPI_SFMSPC_SFMSPI_11 = 0x3
	// Position of SFMSDE field.
	QSPI_SFMSPC_SFMSDE_Pos = 0x4
	// Bit mask of SFMSDE field.
	QSPI_SFMSPC_SFMSDE_Msk = 0x10
	// Bit SFMSDE.
	QSPI_SFMSPC_SFMSDE = 0x10
	// No QSPCLK extension
	QSPI_SFMSPC_SFMSDE_0 = 0x0
	// QSPCLK expansion when switching I/O direction of QIOn pin
	QSPI_SFMSPC_SFMSDE_1 = 0x1

	// SFMPMD: Port Control Register
	// Position of SFMWPL field.
	QSPI_SFMPMD_SFMWPL_Pos = 0x2
	// Bit mask of SFMWPL field.
	QSPI_SFMPMD_SFMWPL_Msk = 0x4
	// Bit SFMWPL.
	QSPI_SFMPMD_SFMWPL = 0x4
	// Low level
	QSPI_SFMPMD_SFMWPL_0 = 0x0
	// High level
	QSPI_SFMPMD_SFMWPL_1 = 0x1

	// SFMCNT1: External QSPI Address Register
	// Position of QSPI_EXT field.
	QSPI_SFMCNT1_QSPI_EXT_Pos = 0x1a
	// Bit mask of QSPI_EXT field.
	QSPI_SFMCNT1_QSPI_EXT_Msk = 0xfc000000
)
