// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from stm32l552.svd, see https://github.com/tinygo-org/stm32-svd

//go:build stm32 && stm32l552

/*
// STM32L552
*/

package stm32

import (
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	Device       = "STM32L552"
	CPU          = "CM33"
	FPUPresent   = true
	NVICPrioBits = 3
)

// Interrupt numbers.
const (
	// System window watchdog
	IRQ_WWDG = 0

	// External interrupt/event controller
	IRQ_PVD_PVM = 1

	// Real-time clock
	IRQ_RTC = 2

	// Real-time clock
	IRQ_RTC_S = 3

	// External interrupt/event controller
	IRQ_TAMP = 4

	// External interrupt/event controller
	IRQ_TAMP_S = 5

	// Flash
	IRQ_FLASH = 6

	// Flash
	IRQ_FLASH_S = 7

	// GTZC_TZIC
	IRQ_GTZC = 8

	// Reset and clock control
	IRQ_RCC = 9

	// Reset and clock control
	IRQ_RCC_S = 10

	// External interrupt/event controller
	IRQ_EXTI0 = 11

	// External interrupt/event controller
	IRQ_EXTI1 = 12

	// External interrupt/event controller
	IRQ_EXTI2 = 13

	// External interrupt/event controller
	IRQ_EXTI3 = 14

	// External interrupt/event controller
	IRQ_EXTI4 = 15

	// External interrupt/event controller
	IRQ_EXTI5 = 16

	// External interrupt/event controller
	IRQ_EXTI6 = 17

	// External interrupt/event controller
	IRQ_EXTI7 = 18

	// External interrupt/event controller
	IRQ_EXTI8 = 19

	// External interrupt/event controller
	IRQ_EXTI9 = 20

	// External interrupt/event controller
	IRQ_EXTI10 = 21

	// External interrupt/event controller
	IRQ_EXTI11 = 22

	// External interrupt/event controller
	IRQ_EXTI12 = 23

	// External interrupt/event controller
	IRQ_EXTI13 = 24

	// External interrupt/event controller
	IRQ_EXTI14 = 25

	// External interrupt/event controller
	IRQ_EXTI15 = 26

	// Direct memory access Multiplexer
	IRQ_DMAMUX1_OVR = 27

	// Direct memory access Multiplexer
	IRQ_DMAMUX1_OVR_S = 28

	// Direct memory access controller
	IRQ_DMA1_CH1 = 29

	// Direct memory access controller
	IRQ_DMA1_CH2 = 30

	// Direct memory access controller
	IRQ_DMA1_CH3 = 31

	// Direct memory access controller
	IRQ_DMA1_CH4 = 32

	// Direct memory access controller
	IRQ_DMA1_CH5 = 33

	// Direct memory access controller
	IRQ_DMA1_CH6 = 34

	// Direct memory access controller
	IRQ_DMA1_CH7 = 35

	// Direct memory access controller
	IRQ_DMA1_Channel8 = 36

	// Analog-to-Digital Converter
	IRQ_ADC1_2 = 37

	// DAC
	IRQ_DAC = 38

	// FDCAN1
	IRQ_FDCAN1_IT0 = 39

	// FDCAN1
	IRQ_FDCAN1_IT1 = 40

	// Advanced-timers
	IRQ_TIM1_BRK = 41

	// Advanced-timers
	IRQ_TIM1_UP = 42

	// Advanced-timers
	IRQ_TIM1_TRG_COM = 43

	// Advanced-timers
	IRQ_TIM1_CC = 44

	// General-purpose-timers
	IRQ_TIM2 = 45

	// General-purpose-timers
	IRQ_TIM3 = 46

	// General-purpose-timers
	IRQ_TIM4 = 47

	IRQ_TIM5 = 48

	// General-purpose-timers
	IRQ_TIM6 = 49

	// General-purpose-timers
	IRQ_TIM7 = 50

	// Advanced-timers
	IRQ_TIM8_BRK = 51

	// Advanced-timers
	IRQ_TIM8_UP = 52

	// Advanced-timers
	IRQ_TIM8_TRG_COM = 53

	// Advanced-timers
	IRQ_TIM8_CC = 54

	// Inter-integrated circuit
	IRQ_I2C1_EV = 55

	// Inter-integrated circuit
	IRQ_I2C1_ER = 56

	IRQ_I2C2_EV = 57

	IRQ_I2C2_ER = 58

	// Serial peripheral interface
	IRQ_SPI1 = 59

	IRQ_SPI2 = 60

	// Universal synchronous asynchronous receiver transmitter
	IRQ_USART1 = 61

	IRQ_USART2 = 62

	IRQ_USART3 = 63

	IRQ_UART4 = 64

	IRQ_UART5 = 65

	// Universal synchronous asynchronous receiver transmitter
	IRQ_LPUART1 = 66

	// Low power timer
	IRQ_LPTIM1 = 67

	// Low power timer
	IRQ_LPTIM2 = 68

	// General purpose timers
	IRQ_TIM15 = 69

	// General purpose timers
	IRQ_TIM16 = 70

	// General purpose timers
	IRQ_TIM17 = 71

	// Comparator
	IRQ_COMP = 72

	// Universal serial bus full-speed device interface
	IRQ_USB_FS = 73

	// Clock recovery system
	IRQ_CRS = 74

	// FMC
	IRQ_FMC = 75

	// OctoSPI
	IRQ_OCTOSPI1 = 76

	// SDMMC1
	IRQ_SDMMC1 = 78

	IRQ_DMA2_CH1 = 80

	IRQ_DMA2_CH2 = 81

	IRQ_DMA2_CH3 = 82

	IRQ_DMA2_CH4 = 83

	IRQ_DMA2_CH5 = 84

	IRQ_DMA2_CH6 = 85

	IRQ_DMA2_CH7 = 86

	IRQ_DMA2_CH8 = 87

	IRQ_I2C3_EV = 88

	IRQ_I2C3_ER = 89

	// Serial audio interface
	IRQ_SAI1 = 90

	IRQ_SAI2 = 91

	// Touch sensing controller
	IRQ_TSC = 92

	// RNG
	IRQ_RNG = 94

	// Hash processor
	IRQ_HASH = 96

	IRQ_LPTIM3 = 98

	IRQ_SPI3 = 99

	IRQ_I2C4_ER = 100

	IRQ_I2C4_EV = 101

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT0 = 102

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT1 = 103

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT2 = 104

	// Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT3 = 105

	// USB Power Delivery interface
	IRQ_UCPD1 = 106

	// ICache
	IRQ_ICACHE = 107

	// Highest interrupt number on this device.
	IRQ_max = 107
)

// Pseudo function call that is replaced by the compiler with the actual
// functions registered through interrupt.New.
//
//go:linkname callHandlers runtime/interrupt.callHandlers
func callHandlers(num int)

//export WWDG_IRQHandler
func interruptWWDG() {
	callHandlers(IRQ_WWDG)
}

//export PVD_PVM_IRQHandler
func interruptPVD_PVM() {
	callHandlers(IRQ_PVD_PVM)
}

//export RTC_IRQHandler
func interruptRTC() {
	callHandlers(IRQ_RTC)
}

//export RTC_S_IRQHandler
func interruptRTC_S() {
	callHandlers(IRQ_RTC_S)
}

//export TAMP_IRQHandler
func interruptTAMP() {
	callHandlers(IRQ_TAMP)
}

//export TAMP_S_IRQHandler
func interruptTAMP_S() {
	callHandlers(IRQ_TAMP_S)
}

//export FLASH_IRQHandler
func interruptFLASH() {
	callHandlers(IRQ_FLASH)
}

//export FLASH_S_IRQHandler
func interruptFLASH_S() {
	callHandlers(IRQ_FLASH_S)
}

//export GTZC_IRQHandler
func interruptGTZC() {
	callHandlers(IRQ_GTZC)
}

//export RCC_IRQHandler
func interruptRCC() {
	callHandlers(IRQ_RCC)
}

//export RCC_S_IRQHandler
func interruptRCC_S() {
	callHandlers(IRQ_RCC_S)
}

//export EXTI0_IRQHandler
func interruptEXTI0() {
	callHandlers(IRQ_EXTI0)
}

//export EXTI1_IRQHandler
func interruptEXTI1() {
	callHandlers(IRQ_EXTI1)
}

//export EXTI2_IRQHandler
func interruptEXTI2() {
	callHandlers(IRQ_EXTI2)
}

//export EXTI3_IRQHandler
func interruptEXTI3() {
	callHandlers(IRQ_EXTI3)
}

//export EXTI4_IRQHandler
func interruptEXTI4() {
	callHandlers(IRQ_EXTI4)
}

//export EXTI5_IRQHandler
func interruptEXTI5() {
	callHandlers(IRQ_EXTI5)
}

//export EXTI6_IRQHandler
func interruptEXTI6() {
	callHandlers(IRQ_EXTI6)
}

//export EXTI7_IRQHandler
func interruptEXTI7() {
	callHandlers(IRQ_EXTI7)
}

//export EXTI8_IRQHandler
func interruptEXTI8() {
	callHandlers(IRQ_EXTI8)
}

//export EXTI9_IRQHandler
func interruptEXTI9() {
	callHandlers(IRQ_EXTI9)
}

//export EXTI10_IRQHandler
func interruptEXTI10() {
	callHandlers(IRQ_EXTI10)
}

//export EXTI11_IRQHandler
func interruptEXTI11() {
	callHandlers(IRQ_EXTI11)
}

//export EXTI12_IRQHandler
func interruptEXTI12() {
	callHandlers(IRQ_EXTI12)
}

//export EXTI13_IRQHandler
func interruptEXTI13() {
	callHandlers(IRQ_EXTI13)
}

//export EXTI14_IRQHandler
func interruptEXTI14() {
	callHandlers(IRQ_EXTI14)
}

//export EXTI15_IRQHandler
func interruptEXTI15() {
	callHandlers(IRQ_EXTI15)
}

//export DMAMUX1_OVR_IRQHandler
func interruptDMAMUX1_OVR() {
	callHandlers(IRQ_DMAMUX1_OVR)
}

//export DMAMUX1_OVR_S_IRQHandler
func interruptDMAMUX1_OVR_S() {
	callHandlers(IRQ_DMAMUX1_OVR_S)
}

//export DMA1_CH1_IRQHandler
func interruptDMA1_CH1() {
	callHandlers(IRQ_DMA1_CH1)
}

//export DMA1_CH2_IRQHandler
func interruptDMA1_CH2() {
	callHandlers(IRQ_DMA1_CH2)
}

//export DMA1_CH3_IRQHandler
func interruptDMA1_CH3() {
	callHandlers(IRQ_DMA1_CH3)
}

//export DMA1_CH4_IRQHandler
func interruptDMA1_CH4() {
	callHandlers(IRQ_DMA1_CH4)
}

//export DMA1_CH5_IRQHandler
func interruptDMA1_CH5() {
	callHandlers(IRQ_DMA1_CH5)
}

//export DMA1_CH6_IRQHandler
func interruptDMA1_CH6() {
	callHandlers(IRQ_DMA1_CH6)
}

//export DMA1_CH7_IRQHandler
func interruptDMA1_CH7() {
	callHandlers(IRQ_DMA1_CH7)
}

//export DMA1_Channel8_IRQHandler
func interruptDMA1_Channel8() {
	callHandlers(IRQ_DMA1_Channel8)
}

//export ADC1_2_IRQHandler
func interruptADC1_2() {
	callHandlers(IRQ_ADC1_2)
}

//export DAC_IRQHandler
func interruptDAC() {
	callHandlers(IRQ_DAC)
}

//export FDCAN1_IT0_IRQHandler
func interruptFDCAN1_IT0() {
	callHandlers(IRQ_FDCAN1_IT0)
}

//export FDCAN1_IT1_IRQHandler
func interruptFDCAN1_IT1() {
	callHandlers(IRQ_FDCAN1_IT1)
}

//export TIM1_BRK_IRQHandler
func interruptTIM1_BRK() {
	callHandlers(IRQ_TIM1_BRK)
}

//export TIM1_UP_IRQHandler
func interruptTIM1_UP() {
	callHandlers(IRQ_TIM1_UP)
}

//export TIM1_TRG_COM_IRQHandler
func interruptTIM1_TRG_COM() {
	callHandlers(IRQ_TIM1_TRG_COM)
}

//export TIM1_CC_IRQHandler
func interruptTIM1_CC() {
	callHandlers(IRQ_TIM1_CC)
}

//export TIM2_IRQHandler
func interruptTIM2() {
	callHandlers(IRQ_TIM2)
}

//export TIM3_IRQHandler
func interruptTIM3() {
	callHandlers(IRQ_TIM3)
}

//export TIM4_IRQHandler
func interruptTIM4() {
	callHandlers(IRQ_TIM4)
}

//export TIM5_IRQHandler
func interruptTIM5() {
	callHandlers(IRQ_TIM5)
}

//export TIM6_IRQHandler
func interruptTIM6() {
	callHandlers(IRQ_TIM6)
}

//export TIM7_IRQHandler
func interruptTIM7() {
	callHandlers(IRQ_TIM7)
}

//export TIM8_BRK_IRQHandler
func interruptTIM8_BRK() {
	callHandlers(IRQ_TIM8_BRK)
}

//export TIM8_UP_IRQHandler
func interruptTIM8_UP() {
	callHandlers(IRQ_TIM8_UP)
}

//export TIM8_TRG_COM_IRQHandler
func interruptTIM8_TRG_COM() {
	callHandlers(IRQ_TIM8_TRG_COM)
}

//export TIM8_CC_IRQHandler
func interruptTIM8_CC() {
	callHandlers(IRQ_TIM8_CC)
}

//export I2C1_EV_IRQHandler
func interruptI2C1_EV() {
	callHandlers(IRQ_I2C1_EV)
}

//export I2C1_ER_IRQHandler
func interruptI2C1_ER() {
	callHandlers(IRQ_I2C1_ER)
}

//export I2C2_EV_IRQHandler
func interruptI2C2_EV() {
	callHandlers(IRQ_I2C2_EV)
}

//export I2C2_ER_IRQHandler
func interruptI2C2_ER() {
	callHandlers(IRQ_I2C2_ER)
}

//export SPI1_IRQHandler
func interruptSPI1() {
	callHandlers(IRQ_SPI1)
}

//export SPI2_IRQHandler
func interruptSPI2() {
	callHandlers(IRQ_SPI2)
}

//export USART1_IRQHandler
func interruptUSART1() {
	callHandlers(IRQ_USART1)
}

//export USART2_IRQHandler
func interruptUSART2() {
	callHandlers(IRQ_USART2)
}

//export USART3_IRQHandler
func interruptUSART3() {
	callHandlers(IRQ_USART3)
}

//export UART4_IRQHandler
func interruptUART4() {
	callHandlers(IRQ_UART4)
}

//export UART5_IRQHandler
func interruptUART5() {
	callHandlers(IRQ_UART5)
}

//export LPUART1_IRQHandler
func interruptLPUART1() {
	callHandlers(IRQ_LPUART1)
}

//export LPTIM1_IRQHandler
func interruptLPTIM1() {
	callHandlers(IRQ_LPTIM1)
}

//export LPTIM2_IRQHandler
func interruptLPTIM2() {
	callHandlers(IRQ_LPTIM2)
}

//export TIM15_IRQHandler
func interruptTIM15() {
	callHandlers(IRQ_TIM15)
}

//export TIM16_IRQHandler
func interruptTIM16() {
	callHandlers(IRQ_TIM16)
}

//export TIM17_IRQHandler
func interruptTIM17() {
	callHandlers(IRQ_TIM17)
}

//export COMP_IRQHandler
func interruptCOMP() {
	callHandlers(IRQ_COMP)
}

//export USB_FS_IRQHandler
func interruptUSB_FS() {
	callHandlers(IRQ_USB_FS)
}

//export CRS_IRQHandler
func interruptCRS() {
	callHandlers(IRQ_CRS)
}

//export FMC_IRQHandler
func interruptFMC() {
	callHandlers(IRQ_FMC)
}

//export OCTOSPI1_IRQHandler
func interruptOCTOSPI1() {
	callHandlers(IRQ_OCTOSPI1)
}

//export SDMMC1_IRQHandler
func interruptSDMMC1() {
	callHandlers(IRQ_SDMMC1)
}

//export DMA2_CH1_IRQHandler
func interruptDMA2_CH1() {
	callHandlers(IRQ_DMA2_CH1)
}

//export DMA2_CH2_IRQHandler
func interruptDMA2_CH2() {
	callHandlers(IRQ_DMA2_CH2)
}

//export DMA2_CH3_IRQHandler
func interruptDMA2_CH3() {
	callHandlers(IRQ_DMA2_CH3)
}

//export DMA2_CH4_IRQHandler
func interruptDMA2_CH4() {
	callHandlers(IRQ_DMA2_CH4)
}

//export DMA2_CH5_IRQHandler
func interruptDMA2_CH5() {
	callHandlers(IRQ_DMA2_CH5)
}

//export DMA2_CH6_IRQHandler
func interruptDMA2_CH6() {
	callHandlers(IRQ_DMA2_CH6)
}

//export DMA2_CH7_IRQHandler
func interruptDMA2_CH7() {
	callHandlers(IRQ_DMA2_CH7)
}

//export DMA2_CH8_IRQHandler
func interruptDMA2_CH8() {
	callHandlers(IRQ_DMA2_CH8)
}

//export I2C3_EV_IRQHandler
func interruptI2C3_EV() {
	callHandlers(IRQ_I2C3_EV)
}

//export I2C3_ER_IRQHandler
func interruptI2C3_ER() {
	callHandlers(IRQ_I2C3_ER)
}

//export SAI1_IRQHandler
func interruptSAI1() {
	callHandlers(IRQ_SAI1)
}

//export SAI2_IRQHandler
func interruptSAI2() {
	callHandlers(IRQ_SAI2)
}

//export TSC_IRQHandler
func interruptTSC() {
	callHandlers(IRQ_TSC)
}

//export RNG_IRQHandler
func interruptRNG() {
	callHandlers(IRQ_RNG)
}

//export HASH_IRQHandler
func interruptHASH() {
	callHandlers(IRQ_HASH)
}

//export LPTIM3_IRQHandler
func interruptLPTIM3() {
	callHandlers(IRQ_LPTIM3)
}

//export SPI3_IRQHandler
func interruptSPI3() {
	callHandlers(IRQ_SPI3)
}

//export I2C4_ER_IRQHandler
func interruptI2C4_ER() {
	callHandlers(IRQ_I2C4_ER)
}

//export I2C4_EV_IRQHandler
func interruptI2C4_EV() {
	callHandlers(IRQ_I2C4_EV)
}

//export DFSDM1_FLT0_IRQHandler
func interruptDFSDM1_FLT0() {
	callHandlers(IRQ_DFSDM1_FLT0)
}

//export DFSDM1_FLT1_IRQHandler
func interruptDFSDM1_FLT1() {
	callHandlers(IRQ_DFSDM1_FLT1)
}

//export DFSDM1_FLT2_IRQHandler
func interruptDFSDM1_FLT2() {
	callHandlers(IRQ_DFSDM1_FLT2)
}

//export DFSDM1_FLT3_IRQHandler
func interruptDFSDM1_FLT3() {
	callHandlers(IRQ_DFSDM1_FLT3)
}

//export UCPD1_IRQHandler
func interruptUCPD1() {
	callHandlers(IRQ_UCPD1)
}

//export ICACHE_IRQHandler
func interruptICACHE() {
	callHandlers(IRQ_ICACHE)
}

// Peripherals.
var (
	// Analog-to-Digital Converter
	ADC1 = (*ADC_Type)(unsafe.Pointer(uintptr(0x42028000)))

	// Analog-to-Digital Converter
	SEC_ADC1 = (*ADC_Type)(unsafe.Pointer(uintptr(0x52028000)))

	// Analog-to-Digital Converter
	ADC2 = (*ADC_Type)(unsafe.Pointer(uintptr(0x42028100)))

	// Analog-to-Digital Converter
	SEC_ADC2 = (*ADC_Type)(unsafe.Pointer(uintptr(0x52028100)))

	// Analog-to-Digital Converter
	ADC_Common = (*ADC_Common_Type)(unsafe.Pointer(uintptr(0x42028300)))

	// Analog-to-Digital Converter
	SEC_ADC_Common = (*ADC_Common_Type)(unsafe.Pointer(uintptr(0x52028300)))

	// Comparator
	COMP = (*COMP_Type)(unsafe.Pointer(uintptr(0x40010200)))

	// Comparator
	SEC_COMP = (*COMP_Type)(unsafe.Pointer(uintptr(0x50010200)))

	// Cyclic redundancy check calculation unit
	CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x40023000)))

	// Cyclic redundancy check calculation unit
	SEC_CRC = (*CRC_Type)(unsafe.Pointer(uintptr(0x50023000)))

	// Clock recovery system
	CRS = (*CRS_Type)(unsafe.Pointer(uintptr(0x40006000)))

	// Clock recovery system
	SEC_CRS = (*CRS_Type)(unsafe.Pointer(uintptr(0x50006000)))

	// DAC
	DAC = (*DAC_Type)(unsafe.Pointer(uintptr(0x40007400)))

	// DAC
	SEC_DAC = (*DAC_Type)(unsafe.Pointer(uintptr(0x50007400)))

	// MCU debug component
	DBGMCU = (*DBGMCU_Type)(unsafe.Pointer(uintptr(0xe0044000)))

	// Debug Control Block
	DCB = (*DCB_Type)(unsafe.Pointer(uintptr(0xe000ee08)))

	// Digital filter for sigma delta modulators
	DFSDM1 = (*DFSDM_Type)(unsafe.Pointer(uintptr(0x40016000)))

	// Digital filter for sigma delta modulators
	SEC_DFSDM1 = (*DFSDM_Type)(unsafe.Pointer(uintptr(0x50016000)))

	// Direct memory access controller
	DMA1 = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020000)))

	// Direct memory access controller
	SEC_DMA1 = (*DMA_Type)(unsafe.Pointer(uintptr(0x50020000)))

	// Direct memory access controller
	DMA2 = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020400)))

	// Direct memory access controller
	SEC_DMA2 = (*DMA_Type)(unsafe.Pointer(uintptr(0x50020400)))

	// Direct memory access Multiplexer
	DMAMUX1 = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x40020800)))

	// Direct memory access Multiplexer
	SEC_DMAMUX1 = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x50020800)))

	// External interrupt/event controller
	EXTI = (*EXTI_Type)(unsafe.Pointer(uintptr(0x4002f400)))

	// External interrupt/event controller
	SEC_EXTI = (*EXTI_Type)(unsafe.Pointer(uintptr(0x5002f400)))

	// FDCAN1
	FDCAN1 = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a400)))

	// FDCAN1
	SEC_FDCAN1 = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x5000a400)))

	// Flash
	FLASH = (*Flash_Type)(unsafe.Pointer(uintptr(0x40022000)))

	// Flash
	SEC_FLASH = (*Flash_Type)(unsafe.Pointer(uintptr(0x50022000)))

	// FMC
	FMC = (*FMC_Type)(unsafe.Pointer(uintptr(0x44020000)))

	// FMC
	SEC_FMC = (*FMC_Type)(unsafe.Pointer(uintptr(0x54020000)))

	// General-purpose I/Os
	GPIOA = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020000)))

	// General-purpose I/Os
	SEC_GPIOA = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020000)))

	// General-purpose I/Os
	GPIOB = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020400)))

	// General-purpose I/Os
	SEC_GPIOB = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020400)))

	// General-purpose I/Os
	GPIOC = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020800)))

	// General-purpose I/Os
	GPIOD = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42020c00)))

	// General-purpose I/Os
	GPIOE = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021000)))

	// General-purpose I/Os
	GPIOF = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021400)))

	// General-purpose I/Os
	GPIOG = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021800)))

	// General-purpose I/Os
	SEC_GPIOC = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020800)))

	// General-purpose I/Os
	SEC_GPIOD = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52020c00)))

	// General-purpose I/Os
	SEC_GPIOE = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021000)))

	// General-purpose I/Os
	SEC_GPIOF = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021400)))

	// General-purpose I/Os
	SEC_GPIOG = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021800)))

	// General-purpose I/Os
	GPIOH = (*GPIO_Type)(unsafe.Pointer(uintptr(0x42021c00)))

	// General-purpose I/Os
	SEC_GPIOH = (*GPIO_Type)(unsafe.Pointer(uintptr(0x52021c00)))

	// GTZC_MPCBB1
	GTZC_MPCBB1 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40032c00)))

	// SEC_GTZC_MPCBB1
	SEC_GTZC_MPCBB1 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50032c00)))

	// GTZC_MPCBB2
	GTZC_MPCBB2 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40033000)))

	// SEC_GTZC_MPCBB2
	SEC_GTZC_MPCBB2 = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50033000)))

	// GTZC_TZIC
	GTZC_TZIC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40032800)))

	// GTZC_TZIC
	SEC_GTZC_TZIC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50032800)))

	// GTZC_TZSC
	GTZC_TZSC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x40032400)))

	// GTZC_TZSC
	SEC_GTZC_TZSC = (*GTZC_Type)(unsafe.Pointer(uintptr(0x50032400)))

	// Hash processor
	HASH = (*HASH_Type)(unsafe.Pointer(uintptr(0x420c0400)))

	// Hash processor
	SEC_HASH = (*HASH_Type)(unsafe.Pointer(uintptr(0x520c0400)))

	// Inter-integrated circuit
	I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005400)))

	// Inter-integrated circuit
	I2C2 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005800)))

	// Inter-integrated circuit
	I2C3 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005c00)))

	// Inter-integrated circuit
	I2C4 = (*I2C_Type)(unsafe.Pointer(uintptr(0x40008400)))

	// Inter-integrated circuit
	SEC_I2C1 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50005400)))

	// Inter-integrated circuit
	SEC_I2C2 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50005800)))

	// Inter-integrated circuit
	SEC_I2C3 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50005c00)))

	// Inter-integrated circuit
	SEC_I2C4 = (*I2C_Type)(unsafe.Pointer(uintptr(0x50008400)))

	// ICache
	ICACHE = (*ICache_Type)(unsafe.Pointer(uintptr(0x40030400)))

	// ICache
	SEC_ICache = (*ICache_Type)(unsafe.Pointer(uintptr(0x50030400)))

	// Independent watchdog
	IWDG = (*IWDG_Type)(unsafe.Pointer(uintptr(0x40003000)))

	// Independent watchdog
	SEC_IWDG = (*IWDG_Type)(unsafe.Pointer(uintptr(0x50003000)))

	// Low power timer
	LPTIM1 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x40007c00)))

	// Low power timer
	LPTIM2 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x40009400)))

	// Low power timer
	LPTIM3 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x40009800)))

	// Low power timer
	SEC_LPTIM1 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x50007c00)))

	// Low power timer
	SEC_LPTIM2 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x50009400)))

	// Low power timer
	SEC_LPTIM3 = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x50009800)))

	// Universal synchronous asynchronous receiver transmitter
	USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x40013800)))

	// Universal synchronous asynchronous receiver transmitter
	LPUART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x40008000)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_LPUART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x50008000)))

	// OctoSPI
	OCTOSPI1 = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x44021000)))

	// OctoSPI
	SEC_OCTOSPI1 = (*OctoSPI_Type)(unsafe.Pointer(uintptr(0x54021000)))

	// Operational amplifiers
	OPAMP = (*OPAMP_Type)(unsafe.Pointer(uintptr(0x40007800)))

	// Operational amplifiers
	SEC_OPAMP = (*OPAMP_Type)(unsafe.Pointer(uintptr(0x50007800)))

	// Power control
	PWR = (*PWR_Type)(unsafe.Pointer(uintptr(0x40007000)))

	// Power control
	SEC_PWR = (*PWR_Type)(unsafe.Pointer(uintptr(0x50007000)))

	// Reset and clock control
	RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x40021000)))

	// Reset and clock control
	SEC_RCC = (*RCC_Type)(unsafe.Pointer(uintptr(0x50021000)))

	// RNG
	RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x420c0800)))

	// RNG
	SEC_RNG = (*RNG_Type)(unsafe.Pointer(uintptr(0x520c0800)))

	// Real-time clock
	RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x40002800)))

	// Real-time clock
	SEC_RTC = (*RTC_Type)(unsafe.Pointer(uintptr(0x50002800)))

	// Serial audio interface
	SAI1 = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015400)))

	// Serial audio interface
	SAI2 = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015800)))

	// Serial audio interface
	SEC_SAI1 = (*SAI_Type)(unsafe.Pointer(uintptr(0x50015400)))

	// Serial audio interface
	SEC_SAI2 = (*SAI_Type)(unsafe.Pointer(uintptr(0x50015800)))

	// SDMMC1
	SDMMC1 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x420c8000)))

	// SDMMC1
	SEC_SDMMC1 = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x520c8000)))

	// Serial peripheral interface
	SPI1 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013000)))

	// Serial peripheral interface
	SPI2 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003800)))

	// Serial peripheral interface
	SPI3 = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003c00)))

	// Serial peripheral interface
	SEC_SPI1 = (*SPI_Type)(unsafe.Pointer(uintptr(0x50013000)))

	// Serial peripheral interface
	SEC_SPI2 = (*SPI_Type)(unsafe.Pointer(uintptr(0x50003800)))

	// Serial peripheral interface
	SEC_SPI3 = (*SPI_Type)(unsafe.Pointer(uintptr(0x50003c00)))

	// System configuration controller
	SYSCFG = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x40010000)))

	// System configuration controller
	SEC_SYSCFG = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x50010000)))

	// Tamper and backup registers
	TAMP = (*TAMP_Type)(unsafe.Pointer(uintptr(0x40003400)))

	// Tamper and backup registers
	SEC_TAMP = (*TAMP_Type)(unsafe.Pointer(uintptr(0x50003400)))

	// Advanced-timers
	TIM1 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40012c00)))

	// Advanced-timers
	SEC_TIM1 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50012c00)))

	// General-purpose-timers
	TIM2 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000000)))

	// General-purpose-timers
	SEC_TIM2 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000000)))

	// General-purpose-timers
	TIM3 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000400)))

	// General-purpose-timers
	SEC_TIM3 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000400)))

	// General-purpose-timers
	TIM4 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000800)))

	// General-purpose-timers
	SEC_TIM4 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000800)))

	// General-purpose-timers
	TIM5 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000c00)))

	// General-purpose-timers
	SEC_TIM5 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50000c00)))

	// General purpose timers
	TIM15 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014000)))

	// General-purpose-timers
	TIM6 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001000)))

	// General-purpose-timers
	SEC_TIM6 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50001000)))

	// General-purpose-timers
	TIM7 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001400)))

	// General-purpose-timers
	SEC_TIM7 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50001400)))

	// Advanced-timers
	TIM8 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40013400)))

	// Advanced-timers
	SEC_TIM8 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50013400)))

	// General purpose timers
	SEC_TIM15 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50014000)))

	// General purpose timers
	TIM16 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014400)))

	// General purpose timers
	SEC_TIM16 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50014400)))

	// General purpose timers
	TIM17 = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014800)))

	// General purpose timers
	SEC_TIM17 = (*TIM_Type)(unsafe.Pointer(uintptr(0x50014800)))

	// Touch sensing controller
	TSC = (*TSC_Type)(unsafe.Pointer(uintptr(0x40024000)))

	// Touch sensing controller
	SEC_TSC = (*TSC_Type)(unsafe.Pointer(uintptr(0x50024000)))

	// Universal serial bus full-speed device interface
	USB = (*USB_Type)(unsafe.Pointer(uintptr(0x4000d400)))

	// Universal serial bus full-speed device interface
	SEC_USB = (*USB_Type)(unsafe.Pointer(uintptr(0x5000d400)))

	// USB Power Delivery interface
	UCPD1 = (*UCPD_Type)(unsafe.Pointer(uintptr(0x4000dc00)))

	// USB Power Delivery interface
	SEC_UCPD1 = (*UCPD_Type)(unsafe.Pointer(uintptr(0x5000dc00)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_USART1 = (*USART_Type)(unsafe.Pointer(uintptr(0x50013800)))

	// Universal synchronous asynchronous receiver transmitter
	USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004400)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_USART2 = (*USART_Type)(unsafe.Pointer(uintptr(0x50004400)))

	// Universal synchronous asynchronous receiver transmitter
	USART3 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004800)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_USART3 = (*USART_Type)(unsafe.Pointer(uintptr(0x50004800)))

	// Universal synchronous asynchronous receiver transmitter
	UART4 = (*USART_Type)(unsafe.Pointer(uintptr(0x40004c00)))

	// Universal synchronous asynchronous receiver transmitter
	UART5 = (*USART_Type)(unsafe.Pointer(uintptr(0x40005000)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_UART4 = (*USART_Type)(unsafe.Pointer(uintptr(0x50004c00)))

	// Universal synchronous asynchronous receiver transmitter
	SEC_UART5 = (*USART_Type)(unsafe.Pointer(uintptr(0x50005000)))

	// Voltage reference buffer
	VREFBUF = (*VREF_Type)(unsafe.Pointer(uintptr(0x40010030)))

	// Voltage reference buffer
	SEC_VREFBUF = (*VREF_Type)(unsafe.Pointer(uintptr(0x50010030)))

	// System window watchdog
	WWDG = (*WWDG_Type)(unsafe.Pointer(uintptr(0x40002c00)))

	// System window watchdog
	SEC_WWDG = (*WWDG_Type)(unsafe.Pointer(uintptr(0x50002c00)))
)

// Analog-to-Digital Converter
type ADC_Type struct {
	ISR     volatile.Register32 // 0x0
	IER     volatile.Register32 // 0x4
	CR      volatile.Register32 // 0x8
	CFGR    volatile.Register32 // 0xC
	CFGR2   volatile.Register32 // 0x10
	SMPR1   volatile.Register32 // 0x14
	SMPR2   volatile.Register32 // 0x18
	_       [4]byte
	TR1     volatile.Register32 // 0x20
	TR2     volatile.Register32 // 0x24
	TR3     volatile.Register32 // 0x28
	_       [4]byte
	SQR1    volatile.Register32 // 0x30
	SQR2    volatile.Register32 // 0x34
	SQR3    volatile.Register32 // 0x38
	SQR4    volatile.Register32 // 0x3C
	DR      volatile.Register32 // 0x40
	_       [8]byte
	JSQR    volatile.Register32 // 0x4C
	_       [16]byte
	OFR1    volatile.Register32 // 0x60
	OFR2    volatile.Register32 // 0x64
	OFR3    volatile.Register32 // 0x68
	OFR4    volatile.Register32 // 0x6C
	_       [16]byte
	JDR1    volatile.Register32 // 0x80
	JDR2    volatile.Register32 // 0x84
	JDR3    volatile.Register32 // 0x88
	JDR4    volatile.Register32 // 0x8C
	_       [16]byte
	AWD2CR  volatile.Register32 // 0xA0
	AWD3CR  volatile.Register32 // 0xA4
	_       [8]byte
	DIFSEL  volatile.Register32 // 0xB0
	CALFACT volatile.Register32 // 0xB4
}

// ADC.ISR: interrupt and status register
func (o *ADC_Type) SetISR_JQOVF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetISR_JQOVF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetISR_AWD1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetISR_AWD1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetISR_AWD2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetISR_AWD2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetISR_AWD3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetISR_AWD3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetISR_JEOS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetISR_JEOS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetISR_JEOC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetISR_JEOC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetISR_OVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetISR_OVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetISR_EOS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetISR_EOS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetISR_EOC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetISR_EOC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetISR_EOSMP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetISR_EOSMP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetISR_ADRDY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetISR_ADRDY() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// ADC.IER: interrupt enable register
func (o *ADC_Type) SetIER_JQOVFIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetIER_JQOVFIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetIER_AWD1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetIER_AWD1IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetIER_AWD2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetIER_AWD2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetIER_AWD3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetIER_AWD3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetIER_JEOSIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetIER_JEOSIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetIER_JEOCIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetIER_JEOCIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetIER_OVRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetIER_OVRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetIER_EOSIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetIER_EOSIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetIER_EOCIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetIER_EOCIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetIER_EOSMPIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetIER_EOSMPIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetIER_ADRDYIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetIER_ADRDYIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}

// ADC.CR: control register
func (o *ADC_Type) SetCR_ADCAL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetCR_ADCAL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetCR_ADCALDIF(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *ADC_Type) GetCR_ADCALDIF() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *ADC_Type) SetCR_DEEPPWD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *ADC_Type) GetCR_DEEPPWD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *ADC_Type) SetCR_ADVREGEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *ADC_Type) GetCR_ADVREGEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *ADC_Type) SetCR_ADSTP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetCR_ADSTP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetCR_JADSTP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCR_JADSTP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCR_ADSTART(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetCR_ADSTART() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetCR_JADSTART(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetCR_JADSTART() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetCR_ADDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCR_ADDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCR_ADEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCR_ADEN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// ADC.CFGR: configuration register
func (o *ADC_Type) SetCFGR_JQDIS(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetCFGR_JQDIS() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetCFGR_AWD1CH(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetCFGR_AWD1CH() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x7c000000) >> 26
}
func (o *ADC_Type) SetCFGR_JAUTO(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Type) GetCFGR_JAUTO() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x2000000) >> 25
}
func (o *ADC_Type) SetCFGR_JAWD1EN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Type) GetCFGR_JAWD1EN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Type) SetCFGR_AWD1EN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Type) GetCFGR_AWD1EN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x800000) >> 23
}
func (o *ADC_Type) SetCFGR_AWD1SGL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Type) GetCFGR_AWD1SGL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x400000) >> 22
}
func (o *ADC_Type) SetCFGR_JQM(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x200000)|value<<21)
}
func (o *ADC_Type) GetCFGR_JQM() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x200000) >> 21
}
func (o *ADC_Type) SetCFGR_JDISCEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Type) GetCFGR_JDISCEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x100000) >> 20
}
func (o *ADC_Type) SetCFGR_DISCNUM(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xe0000)|value<<17)
}
func (o *ADC_Type) GetCFGR_DISCNUM() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xe0000) >> 17
}
func (o *ADC_Type) SetCFGR_DISCEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetCFGR_DISCEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetCFGR_AUTDLY(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetCFGR_AUTDLY() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetCFGR_CONT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetCFGR_CONT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetCFGR_OVRMOD(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetCFGR_OVRMOD() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetCFGR_EXTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xc00)|value<<10)
}
func (o *ADC_Type) GetCFGR_EXTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xc00) >> 10
}
func (o *ADC_Type) SetCFGR_EXTSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x3c0)|value<<6)
}
func (o *ADC_Type) GetCFGR_EXTSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x3c0) >> 6
}
func (o *ADC_Type) SetCFGR_ALIGN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetCFGR_ALIGN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetCFGR_RES(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x18)|value<<3)
}
func (o *ADC_Type) GetCFGR_RES() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x18) >> 3
}
func (o *ADC_Type) SetCFGR_DMACFG(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCFGR_DMACFG() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCFGR_DMAEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCFGR_DMAEN() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0x1
}

// ADC.CFGR2: configuration register
func (o *ADC_Type) SetCFGR2_ROVSM(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetCFGR2_ROVSM() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetCFGR2_TOVS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetCFGR2_TOVS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetCFGR2_OVSS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1e0)|value<<5)
}
func (o *ADC_Type) GetCFGR2_OVSS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x1e0) >> 5
}
func (o *ADC_Type) SetCFGR2_OVSR(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1c)|value<<2)
}
func (o *ADC_Type) GetCFGR2_OVSR() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x1c) >> 2
}
func (o *ADC_Type) SetCFGR2_JOVSE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetCFGR2_JOVSE() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetCFGR2_ROVSE(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *ADC_Type) GetCFGR2_ROVSE() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}

// ADC.SMPR1: sample time register 1
func (o *ADC_Type) SetSMPR1_SMP0(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x38)|value<<3)
}
func (o *ADC_Type) GetSMPR1_SMP0() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x38) >> 3
}
func (o *ADC_Type) SetSMPR1_SMP1(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x1c0)|value<<6)
}
func (o *ADC_Type) GetSMPR1_SMP1() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x1c0) >> 6
}
func (o *ADC_Type) SetSMPR1_SMP2(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0xe00)|value<<9)
}
func (o *ADC_Type) GetSMPR1_SMP2() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0xe00) >> 9
}
func (o *ADC_Type) SetSMPR1_SMP3(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x7000)|value<<12)
}
func (o *ADC_Type) GetSMPR1_SMP3() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x7000) >> 12
}
func (o *ADC_Type) SetSMPR1_SMP4(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x38000)|value<<15)
}
func (o *ADC_Type) GetSMPR1_SMP4() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x38000) >> 15
}
func (o *ADC_Type) SetSMPR1_SMP5(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x1c0000)|value<<18)
}
func (o *ADC_Type) GetSMPR1_SMP5() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x1c0000) >> 18
}
func (o *ADC_Type) SetSMPR1_SMP6(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0xe00000)|value<<21)
}
func (o *ADC_Type) GetSMPR1_SMP6() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0xe00000) >> 21
}
func (o *ADC_Type) SetSMPR1_SMP7(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x7000000)|value<<24)
}
func (o *ADC_Type) GetSMPR1_SMP7() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x7000000) >> 24
}
func (o *ADC_Type) SetSMPR1_SMP8(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0x38000000)|value<<27)
}
func (o *ADC_Type) GetSMPR1_SMP8() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0x38000000) >> 27
}
func (o *ADC_Type) SetSMPR1_SMP9(value uint32) {
	volatile.StoreUint32(&o.SMPR1.Reg, volatile.LoadUint32(&o.SMPR1.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSMPR1_SMP9() uint32 {
	return (volatile.LoadUint32(&o.SMPR1.Reg) & 0xc0000000) >> 30
}

// ADC.SMPR2: sample time register 2
func (o *ADC_Type) SetSMPR2_SMP10(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x38)|value<<3)
}
func (o *ADC_Type) GetSMPR2_SMP10() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x38) >> 3
}
func (o *ADC_Type) SetSMPR2_SMP11(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x1c0)|value<<6)
}
func (o *ADC_Type) GetSMPR2_SMP11() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x1c0) >> 6
}
func (o *ADC_Type) SetSMPR2_SMP12(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0xe00)|value<<9)
}
func (o *ADC_Type) GetSMPR2_SMP12() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0xe00) >> 9
}
func (o *ADC_Type) SetSMPR2_SMP13(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x7000)|value<<12)
}
func (o *ADC_Type) GetSMPR2_SMP13() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x7000) >> 12
}
func (o *ADC_Type) SetSMPR2_SMP14(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x38000)|value<<15)
}
func (o *ADC_Type) GetSMPR2_SMP14() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x38000) >> 15
}
func (o *ADC_Type) SetSMPR2_SMP15(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x1c0000)|value<<18)
}
func (o *ADC_Type) GetSMPR2_SMP15() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x1c0000) >> 18
}
func (o *ADC_Type) SetSMPR2_SMP16(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0xe00000)|value<<21)
}
func (o *ADC_Type) GetSMPR2_SMP16() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0xe00000) >> 21
}
func (o *ADC_Type) SetSMPR2_SMP17(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x7000000)|value<<24)
}
func (o *ADC_Type) GetSMPR2_SMP17() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x7000000) >> 24
}
func (o *ADC_Type) SetSMPR2_SMP18(value uint32) {
	volatile.StoreUint32(&o.SMPR2.Reg, volatile.LoadUint32(&o.SMPR2.Reg)&^(0x38000000)|value<<27)
}
func (o *ADC_Type) GetSMPR2_SMP18() uint32 {
	return (volatile.LoadUint32(&o.SMPR2.Reg) & 0x38000000) >> 27
}

// ADC.TR1: watchdog threshold register 1
func (o *ADC_Type) SetTR1_HT1(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0xfff0000)|value<<16)
}
func (o *ADC_Type) GetTR1_HT1() uint32 {
	return (volatile.LoadUint32(&o.TR1.Reg) & 0xfff0000) >> 16
}
func (o *ADC_Type) SetTR1_LT1(value uint32) {
	volatile.StoreUint32(&o.TR1.Reg, volatile.LoadUint32(&o.TR1.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetTR1_LT1() uint32 {
	return volatile.LoadUint32(&o.TR1.Reg) & 0xfff
}

// ADC.TR2: watchdog threshold register
func (o *ADC_Type) SetTR2_HT2(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0xff0000)|value<<16)
}
func (o *ADC_Type) GetTR2_HT2() uint32 {
	return (volatile.LoadUint32(&o.TR2.Reg) & 0xff0000) >> 16
}
func (o *ADC_Type) SetTR2_LT2(value uint32) {
	volatile.StoreUint32(&o.TR2.Reg, volatile.LoadUint32(&o.TR2.Reg)&^(0xff)|value)
}
func (o *ADC_Type) GetTR2_LT2() uint32 {
	return volatile.LoadUint32(&o.TR2.Reg) & 0xff
}

// ADC.TR3: watchdog threshold register 3
func (o *ADC_Type) SetTR3_HT3(value uint32) {
	volatile.StoreUint32(&o.TR3.Reg, volatile.LoadUint32(&o.TR3.Reg)&^(0xff0000)|value<<16)
}
func (o *ADC_Type) GetTR3_HT3() uint32 {
	return (volatile.LoadUint32(&o.TR3.Reg) & 0xff0000) >> 16
}
func (o *ADC_Type) SetTR3_LT3(value uint32) {
	volatile.StoreUint32(&o.TR3.Reg, volatile.LoadUint32(&o.TR3.Reg)&^(0xff)|value)
}
func (o *ADC_Type) GetTR3_LT3() uint32 {
	return volatile.LoadUint32(&o.TR3.Reg) & 0xff
}

// ADC.SQR1: regular sequence register 1
func (o *ADC_Type) SetSQR1_SQ1(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR1_SQ1() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0x1f000) >> 12
}
func (o *ADC_Type) SetSQR1_SQ2(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0x7c0000)|value<<18)
}
func (o *ADC_Type) GetSQR1_SQ2() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0x7c0000) >> 18
}
func (o *ADC_Type) SetSQR1_SQ3(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0x1f000000)|value<<24)
}
func (o *ADC_Type) GetSQR1_SQ3() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0x1f000000) >> 24
}
func (o *ADC_Type) SetSQR1_SQ4(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSQR1_SQ4() uint32 {
	return (volatile.LoadUint32(&o.SQR1.Reg) & 0xc0000000) >> 30
}
func (o *ADC_Type) SetSQR1_L(value uint32) {
	volatile.StoreUint32(&o.SQR1.Reg, volatile.LoadUint32(&o.SQR1.Reg)&^(0xf)|value)
}
func (o *ADC_Type) GetSQR1_L() uint32 {
	return volatile.LoadUint32(&o.SQR1.Reg) & 0xf
}

// ADC.SQR2: regular sequence register 2
func (o *ADC_Type) SetSQR2_SQ5(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x7c0)|value<<6)
}
func (o *ADC_Type) GetSQR2_SQ5() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x7c0) >> 6
}
func (o *ADC_Type) SetSQR2_SQ6(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR2_SQ6() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x1f000) >> 12
}
func (o *ADC_Type) SetSQR2_SQ7(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x7c0000)|value<<18)
}
func (o *ADC_Type) GetSQR2_SQ7() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x7c0000) >> 18
}
func (o *ADC_Type) SetSQR2_SQ8(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0x1f000000)|value<<24)
}
func (o *ADC_Type) GetSQR2_SQ8() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0x1f000000) >> 24
}
func (o *ADC_Type) SetSQR2_SQ9(value uint32) {
	volatile.StoreUint32(&o.SQR2.Reg, volatile.LoadUint32(&o.SQR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSQR2_SQ9() uint32 {
	return (volatile.LoadUint32(&o.SQR2.Reg) & 0xc0000000) >> 30
}

// ADC.SQR3: regular sequence register 3
func (o *ADC_Type) SetSQR3_SQ10(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x7c0)|value<<6)
}
func (o *ADC_Type) GetSQR3_SQ10() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x7c0) >> 6
}
func (o *ADC_Type) SetSQR3_SQ11(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR3_SQ11() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x1f000) >> 12
}
func (o *ADC_Type) SetSQR3_SQ12(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x7c0000)|value<<18)
}
func (o *ADC_Type) GetSQR3_SQ12() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x7c0000) >> 18
}
func (o *ADC_Type) SetSQR3_SQ13(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0x1f000000)|value<<24)
}
func (o *ADC_Type) GetSQR3_SQ13() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0x1f000000) >> 24
}
func (o *ADC_Type) SetSQR3_SQ14(value uint32) {
	volatile.StoreUint32(&o.SQR3.Reg, volatile.LoadUint32(&o.SQR3.Reg)&^(0xc0000000)|value<<30)
}
func (o *ADC_Type) GetSQR3_SQ14() uint32 {
	return (volatile.LoadUint32(&o.SQR3.Reg) & 0xc0000000) >> 30
}

// ADC.SQR4: regular sequence register 4
func (o *ADC_Type) SetSQR4_SQ15(value uint32) {
	volatile.StoreUint32(&o.SQR4.Reg, volatile.LoadUint32(&o.SQR4.Reg)&^(0x7c0)|value<<6)
}
func (o *ADC_Type) GetSQR4_SQ15() uint32 {
	return (volatile.LoadUint32(&o.SQR4.Reg) & 0x7c0) >> 6
}
func (o *ADC_Type) SetSQR4_SQ16(value uint32) {
	volatile.StoreUint32(&o.SQR4.Reg, volatile.LoadUint32(&o.SQR4.Reg)&^(0x1f000)|value<<12)
}
func (o *ADC_Type) GetSQR4_SQ16() uint32 {
	return (volatile.LoadUint32(&o.SQR4.Reg) & 0x1f000) >> 12
}

// ADC.DR: regular Data Register
func (o *ADC_Type) SetDR_RDATA(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetDR_RDATA() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xffff
}

// ADC.JSQR: injected sequence register
func (o *ADC_Type) SetJSQR_JSQ1(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x7c000)|value<<14)
}
func (o *ADC_Type) GetJSQR_JSQ1() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x7c000) >> 14
}
func (o *ADC_Type) SetJSQR_JSQ2(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x1f00000)|value<<20)
}
func (o *ADC_Type) GetJSQR_JSQ2() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x1f00000) >> 20
}
func (o *ADC_Type) SetJSQR_JSQ3(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetJSQR_JSQ3() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x7c000000) >> 26
}
func (o *ADC_Type) SetJSQR_JSQ4(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x0)|value<<32)
}
func (o *ADC_Type) GetJSQR_JSQ4() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x0) >> 32
}
func (o *ADC_Type) SetJSQR_JEXTEN(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0xc0)|value<<6)
}
func (o *ADC_Type) GetJSQR_JEXTEN() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0xc0) >> 6
}
func (o *ADC_Type) SetJSQR_JEXTSEL(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x3c)|value<<2)
}
func (o *ADC_Type) GetJSQR_JEXTSEL() uint32 {
	return (volatile.LoadUint32(&o.JSQR.Reg) & 0x3c) >> 2
}
func (o *ADC_Type) SetJSQR_JL(value uint32) {
	volatile.StoreUint32(&o.JSQR.Reg, volatile.LoadUint32(&o.JSQR.Reg)&^(0x3)|value)
}
func (o *ADC_Type) GetJSQR_JL() uint32 {
	return volatile.LoadUint32(&o.JSQR.Reg) & 0x3
}

// ADC.OFR1: offset register %s
func (o *ADC_Type) SetOFR1_OFFSET_EN(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetOFR1_OFFSET_EN() uint32 {
	return (volatile.LoadUint32(&o.OFR1.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetOFR1_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetOFR1_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR1.Reg) & 0x7c000000) >> 26
}
func (o *ADC_Type) SetOFR1_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR1.Reg, volatile.LoadUint32(&o.OFR1.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetOFR1_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR1.Reg) & 0xfff
}

// ADC.OFR2: offset register %s
func (o *ADC_Type) SetOFR2_OFFSET_EN(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetOFR2_OFFSET_EN() uint32 {
	return (volatile.LoadUint32(&o.OFR2.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetOFR2_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetOFR2_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR2.Reg) & 0x7c000000) >> 26
}
func (o *ADC_Type) SetOFR2_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR2.Reg, volatile.LoadUint32(&o.OFR2.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetOFR2_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR2.Reg) & 0xfff
}

// ADC.OFR3: offset register %s
func (o *ADC_Type) SetOFR3_OFFSET_EN(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetOFR3_OFFSET_EN() uint32 {
	return (volatile.LoadUint32(&o.OFR3.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetOFR3_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetOFR3_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR3.Reg) & 0x7c000000) >> 26
}
func (o *ADC_Type) SetOFR3_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR3.Reg, volatile.LoadUint32(&o.OFR3.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetOFR3_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR3.Reg) & 0xfff
}

// ADC.OFR4: offset register %s
func (o *ADC_Type) SetOFR4_OFFSET_EN(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0x80000000)|value<<31)
}
func (o *ADC_Type) GetOFR4_OFFSET_EN() uint32 {
	return (volatile.LoadUint32(&o.OFR4.Reg) & 0x80000000) >> 31
}
func (o *ADC_Type) SetOFR4_OFFSET_CH(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0x7c000000)|value<<26)
}
func (o *ADC_Type) GetOFR4_OFFSET_CH() uint32 {
	return (volatile.LoadUint32(&o.OFR4.Reg) & 0x7c000000) >> 26
}
func (o *ADC_Type) SetOFR4_OFFSET(value uint32) {
	volatile.StoreUint32(&o.OFR4.Reg, volatile.LoadUint32(&o.OFR4.Reg)&^(0xfff)|value)
}
func (o *ADC_Type) GetOFR4_OFFSET() uint32 {
	return volatile.LoadUint32(&o.OFR4.Reg) & 0xfff
}

// ADC.JDR1: injected data register %s
func (o *ADC_Type) SetJDR1_JDATA(value uint32) {
	volatile.StoreUint32(&o.JDR1.Reg, volatile.LoadUint32(&o.JDR1.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetJDR1_JDATA() uint32 {
	return volatile.LoadUint32(&o.JDR1.Reg) & 0xffff
}

// ADC.JDR2: injected data register %s
func (o *ADC_Type) SetJDR2_JDATA(value uint32) {
	volatile.StoreUint32(&o.JDR2.Reg, volatile.LoadUint32(&o.JDR2.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetJDR2_JDATA() uint32 {
	return volatile.LoadUint32(&o.JDR2.Reg) & 0xffff
}

// ADC.JDR3: injected data register %s
func (o *ADC_Type) SetJDR3_JDATA(value uint32) {
	volatile.StoreUint32(&o.JDR3.Reg, volatile.LoadUint32(&o.JDR3.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetJDR3_JDATA() uint32 {
	return volatile.LoadUint32(&o.JDR3.Reg) & 0xffff
}

// ADC.JDR4: injected data register %s
func (o *ADC_Type) SetJDR4_JDATA(value uint32) {
	volatile.StoreUint32(&o.JDR4.Reg, volatile.LoadUint32(&o.JDR4.Reg)&^(0xffff)|value)
}
func (o *ADC_Type) GetJDR4_JDATA() uint32 {
	return volatile.LoadUint32(&o.JDR4.Reg) & 0xffff
}

// ADC.AWD2CR: Analog Watchdog 2 Configuration Register
func (o *ADC_Type) SetAWD2CR_AWD2CH0(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH0() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetAWD2CR_AWD2CH1(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH1() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetAWD2CR_AWD2CH2(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH2() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetAWD2CR_AWD2CH3(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH3() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetAWD2CR_AWD2CH4(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH4() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetAWD2CR_AWD2CH5(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH5() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetAWD2CR_AWD2CH6(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH6() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetAWD2CR_AWD2CH7(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH7() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetAWD2CR_AWD2CH8(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH8() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetAWD2CR_AWD2CH9(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH9() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetAWD2CR_AWD2CH10(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH10() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetAWD2CR_AWD2CH11(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH11() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetAWD2CR_AWD2CH12(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH12() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetAWD2CR_AWD2CH13(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH13() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetAWD2CR_AWD2CH14(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH14() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetAWD2CR_AWD2CH15(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH15() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetAWD2CR_AWD2CH16(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH16() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetAWD2CR_AWD2CH17(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH17() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetAWD2CR_AWD2CH18(value uint32) {
	volatile.StoreUint32(&o.AWD2CR.Reg, volatile.LoadUint32(&o.AWD2CR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetAWD2CR_AWD2CH18() uint32 {
	return (volatile.LoadUint32(&o.AWD2CR.Reg) & 0x80000) >> 19
}

// ADC.AWD3CR: Analog Watchdog 3 Configuration Register
func (o *ADC_Type) SetAWD3CR_AWD3CH0(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH0() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetAWD3CR_AWD3CH1(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH1() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetAWD3CR_AWD3CH2(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH2() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetAWD3CR_AWD3CH3(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH3() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetAWD3CR_AWD3CH4(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH4() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetAWD3CR_AWD3CH5(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH5() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetAWD3CR_AWD3CH6(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH6() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetAWD3CR_AWD3CH7(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH7() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetAWD3CR_AWD3CH8(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH8() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetAWD3CR_AWD3CH9(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH9() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetAWD3CR_AWD3CH10(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH10() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetAWD3CR_AWD3CH11(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH11() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetAWD3CR_AWD3CH12(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH12() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetAWD3CR_AWD3CH13(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH13() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetAWD3CR_AWD3CH14(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH14() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetAWD3CR_AWD3CH15(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH15() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetAWD3CR_AWD3CH16(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH16() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetAWD3CR_AWD3CH17(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH17() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetAWD3CR_AWD3CH18(value uint32) {
	volatile.StoreUint32(&o.AWD3CR.Reg, volatile.LoadUint32(&o.AWD3CR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetAWD3CR_AWD3CH18() uint32 {
	return (volatile.LoadUint32(&o.AWD3CR.Reg) & 0x80000) >> 19
}

// ADC.DIFSEL: Differential Mode Selection Register 2
func (o *ADC_Type) SetDIFSEL_DIFSEL0(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL0() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x2) >> 1
}
func (o *ADC_Type) SetDIFSEL_DIFSEL1(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL1() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x4) >> 2
}
func (o *ADC_Type) SetDIFSEL_DIFSEL2(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL2() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x8) >> 3
}
func (o *ADC_Type) SetDIFSEL_DIFSEL3(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL3() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x10) >> 4
}
func (o *ADC_Type) SetDIFSEL_DIFSEL4(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL4() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x20) >> 5
}
func (o *ADC_Type) SetDIFSEL_DIFSEL5(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL5() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x40) >> 6
}
func (o *ADC_Type) SetDIFSEL_DIFSEL6(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL6() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x80) >> 7
}
func (o *ADC_Type) SetDIFSEL_DIFSEL7(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL7() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x100) >> 8
}
func (o *ADC_Type) SetDIFSEL_DIFSEL8(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL8() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x200) >> 9
}
func (o *ADC_Type) SetDIFSEL_DIFSEL9(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL9() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x400) >> 10
}
func (o *ADC_Type) SetDIFSEL_DIFSEL10(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x800)|value<<11)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL10() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x800) >> 11
}
func (o *ADC_Type) SetDIFSEL_DIFSEL11(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x1000)|value<<12)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL11() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x1000) >> 12
}
func (o *ADC_Type) SetDIFSEL_DIFSEL12(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL12() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x2000) >> 13
}
func (o *ADC_Type) SetDIFSEL_DIFSEL13(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x4000)|value<<14)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL13() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x4000) >> 14
}
func (o *ADC_Type) SetDIFSEL_DIFSEL14(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x8000)|value<<15)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL14() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x8000) >> 15
}
func (o *ADC_Type) SetDIFSEL_DIFSEL15(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL15() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x10000) >> 16
}
func (o *ADC_Type) SetDIFSEL_DIFSEL16(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL16() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x20000) >> 17
}
func (o *ADC_Type) SetDIFSEL_DIFSEL17(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL17() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x40000) >> 18
}
func (o *ADC_Type) SetDIFSEL_DIFSEL18(value uint32) {
	volatile.StoreUint32(&o.DIFSEL.Reg, volatile.LoadUint32(&o.DIFSEL.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Type) GetDIFSEL_DIFSEL18() uint32 {
	return (volatile.LoadUint32(&o.DIFSEL.Reg) & 0x80000) >> 19
}

// ADC.CALFACT: Calibration Factors
func (o *ADC_Type) SetCALFACT_CALFACT_D(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0x7f0000)|value<<16)
}
func (o *ADC_Type) GetCALFACT_CALFACT_D() uint32 {
	return (volatile.LoadUint32(&o.CALFACT.Reg) & 0x7f0000) >> 16
}
func (o *ADC_Type) SetCALFACT_CALFACT_S(value uint32) {
	volatile.StoreUint32(&o.CALFACT.Reg, volatile.LoadUint32(&o.CALFACT.Reg)&^(0x7f)|value)
}
func (o *ADC_Type) GetCALFACT_CALFACT_S() uint32 {
	return volatile.LoadUint32(&o.CALFACT.Reg) & 0x7f
}

// Analog-to-Digital Converter
type ADC_Common_Type struct {
	CSR volatile.Register32 // 0x0
	_   [4]byte
	CCR volatile.Register32 // 0x8
	CDR volatile.Register32 // 0xC
}

// ADC_Common.CSR: ADC Common status register
func (o *ADC_Common_Type) SetCSR_ADRDY_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1)|value)
}
func (o *ADC_Common_Type) GetCSR_ADRDY_MST() uint32 {
	return volatile.LoadUint32(&o.CSR.Reg) & 0x1
}
func (o *ADC_Common_Type) SetCSR_EOSMP_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *ADC_Common_Type) GetCSR_EOSMP_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *ADC_Common_Type) SetCSR_EOC_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4)|value<<2)
}
func (o *ADC_Common_Type) GetCSR_EOC_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4) >> 2
}
func (o *ADC_Common_Type) SetCSR_EOS_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8)|value<<3)
}
func (o *ADC_Common_Type) GetCSR_EOS_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8) >> 3
}
func (o *ADC_Common_Type) SetCSR_OVR_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10)|value<<4)
}
func (o *ADC_Common_Type) GetCSR_OVR_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10) >> 4
}
func (o *ADC_Common_Type) SetCSR_JEOC_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20)|value<<5)
}
func (o *ADC_Common_Type) GetCSR_JEOC_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20) >> 5
}
func (o *ADC_Common_Type) SetCSR_JEOS_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40)|value<<6)
}
func (o *ADC_Common_Type) GetCSR_JEOS_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40) >> 6
}
func (o *ADC_Common_Type) SetCSR_AWD1_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80)|value<<7)
}
func (o *ADC_Common_Type) GetCSR_AWD1_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80) >> 7
}
func (o *ADC_Common_Type) SetCSR_AWD2_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x100)|value<<8)
}
func (o *ADC_Common_Type) GetCSR_AWD2_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x100) >> 8
}
func (o *ADC_Common_Type) SetCSR_AWD3_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x200)|value<<9)
}
func (o *ADC_Common_Type) GetCSR_AWD3_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x200) >> 9
}
func (o *ADC_Common_Type) SetCSR_JQOVF_MST(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x400)|value<<10)
}
func (o *ADC_Common_Type) GetCSR_JQOVF_MST() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x400) >> 10
}
func (o *ADC_Common_Type) SetCSR_ADRDY_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10000)|value<<16)
}
func (o *ADC_Common_Type) GetCSR_ADRDY_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10000) >> 16
}
func (o *ADC_Common_Type) SetCSR_EOSMP_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20000)|value<<17)
}
func (o *ADC_Common_Type) GetCSR_EOSMP_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20000) >> 17
}
func (o *ADC_Common_Type) SetCSR_EOC_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40000)|value<<18)
}
func (o *ADC_Common_Type) GetCSR_EOC_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40000) >> 18
}
func (o *ADC_Common_Type) SetCSR_EOS_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80000)|value<<19)
}
func (o *ADC_Common_Type) GetCSR_EOS_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80000) >> 19
}
func (o *ADC_Common_Type) SetCSR_OVR_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x100000)|value<<20)
}
func (o *ADC_Common_Type) GetCSR_OVR_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x100000) >> 20
}
func (o *ADC_Common_Type) SetCSR_JEOC_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x200000)|value<<21)
}
func (o *ADC_Common_Type) GetCSR_JEOC_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x200000) >> 21
}
func (o *ADC_Common_Type) SetCSR_JEOS_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Common_Type) GetCSR_JEOS_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x400000) >> 22
}
func (o *ADC_Common_Type) SetCSR_AWD1_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Common_Type) GetCSR_AWD1_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800000) >> 23
}
func (o *ADC_Common_Type) SetCSR_AWD2_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Common_Type) GetCSR_AWD2_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Common_Type) SetCSR_AWD3_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2000000)|value<<25)
}
func (o *ADC_Common_Type) GetCSR_AWD3_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2000000) >> 25
}
func (o *ADC_Common_Type) SetCSR_JQOVF_SLV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4000000)|value<<26)
}
func (o *ADC_Common_Type) GetCSR_JQOVF_SLV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4000000) >> 26
}

// ADC_Common.CCR: ADC common control register
func (o *ADC_Common_Type) SetCCR_CKMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x30000)|value<<16)
}
func (o *ADC_Common_Type) GetCCR_CKMODE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x30000) >> 16
}
func (o *ADC_Common_Type) SetCCR_PRESC(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x3c0000)|value<<18)
}
func (o *ADC_Common_Type) GetCCR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x3c0000) >> 18
}
func (o *ADC_Common_Type) SetCCR_VREFEN(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x400000)|value<<22)
}
func (o *ADC_Common_Type) GetCCR_VREFEN() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x400000) >> 22
}
func (o *ADC_Common_Type) SetCCR_VSENSEEN(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x800000)|value<<23)
}
func (o *ADC_Common_Type) GetCCR_VSENSEEN() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x800000) >> 23
}
func (o *ADC_Common_Type) SetCCR_VBATEN(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x1000000)|value<<24)
}
func (o *ADC_Common_Type) GetCCR_VBATEN() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x1000000) >> 24
}
func (o *ADC_Common_Type) SetCCR_MDMA(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0xc000)|value<<14)
}
func (o *ADC_Common_Type) GetCCR_MDMA() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0xc000) >> 14
}
func (o *ADC_Common_Type) SetCCR_DMACFG(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x2000)|value<<13)
}
func (o *ADC_Common_Type) GetCCR_DMACFG() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x2000) >> 13
}
func (o *ADC_Common_Type) SetCCR_DELAY(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0xf00)|value<<8)
}
func (o *ADC_Common_Type) GetCCR_DELAY() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0xf00) >> 8
}
func (o *ADC_Common_Type) SetCCR_DUAL(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x1f)|value)
}
func (o *ADC_Common_Type) GetCCR_DUAL() uint32 {
	return volatile.LoadUint32(&o.CCR.Reg) & 0x1f
}

// ADC_Common.CDR: Common regular data register for dual mode
func (o *ADC_Common_Type) SetCDR_RDATA_MST(value uint32) {
	volatile.StoreUint32(&o.CDR.Reg, volatile.LoadUint32(&o.CDR.Reg)&^(0xffff)|value)
}
func (o *ADC_Common_Type) GetCDR_RDATA_MST() uint32 {
	return volatile.LoadUint32(&o.CDR.Reg) & 0xffff
}
func (o *ADC_Common_Type) SetCDR_RDATA_SLV(value uint32) {
	volatile.StoreUint32(&o.CDR.Reg, volatile.LoadUint32(&o.CDR.Reg)&^(0xffff0000)|value<<16)
}
func (o *ADC_Common_Type) GetCDR_RDATA_SLV() uint32 {
	return (volatile.LoadUint32(&o.CDR.Reg) & 0xffff0000) >> 16
}

// Comparator
type COMP_Type struct {
	COMP1_CSR volatile.Register32 // 0x0
	COMP2_CSR volatile.Register32 // 0x4
}

// COMP.COMP1_CSR: Comparator 1 control and status register
func (o *COMP_Type) SetCOMP1_CSR_COMP1_EN(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x1)|value)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_EN() uint32 {
	return volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x1
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_PWRMODE(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0xc)|value<<2)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_PWRMODE() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0xc) >> 2
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_INMSEL(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x70)|value<<4)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_INMSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x70) >> 4
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_INPSEL(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x80)|value<<7)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_INPSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x80) >> 7
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_POLARITY(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x8000)|value<<15)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_POLARITY() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x8000) >> 15
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_HYST(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x30000)|value<<16)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_HYST() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x30000) >> 16
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_BLANKING(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x1c0000)|value<<18)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_BLANKING() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x1c0000) >> 18
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_BRGEN(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x400000)|value<<22)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_BRGEN() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x400000) >> 22
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_SCALEN(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x800000)|value<<23)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_SCALEN() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x800000) >> 23
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_VALUE(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_VALUE() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x40000000) >> 30
}
func (o *COMP_Type) SetCOMP1_CSR_COMP1_LOCK(value uint32) {
	volatile.StoreUint32(&o.COMP1_CSR.Reg, volatile.LoadUint32(&o.COMP1_CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *COMP_Type) GetCOMP1_CSR_COMP1_LOCK() uint32 {
	return (volatile.LoadUint32(&o.COMP1_CSR.Reg) & 0x80000000) >> 31
}

// COMP.COMP2_CSR: Comparator 2 control and status register
func (o *COMP_Type) SetCOMP2_CSR_COMP2_EN(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x1)|value)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_EN() uint32 {
	return volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x1
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_PWRMODE(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0xc)|value<<2)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_PWRMODE() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0xc) >> 2
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_INMSEL(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x70)|value<<4)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_INMSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x70) >> 4
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_INPSEL(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x80)|value<<7)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_INPSEL() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x80) >> 7
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_WINMODE(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x200)|value<<9)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_WINMODE() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x200) >> 9
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_POLARITY(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x8000)|value<<15)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_POLARITY() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x8000) >> 15
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_HYST(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x30000)|value<<16)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_HYST() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x30000) >> 16
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_BLANKING(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x1c0000)|value<<18)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_BLANKING() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x1c0000) >> 18
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_BRGEN(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x400000)|value<<22)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_BRGEN() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x400000) >> 22
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_SCALEN(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x800000)|value<<23)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_SCALEN() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x800000) >> 23
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_VALUE(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_VALUE() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x40000000) >> 30
}
func (o *COMP_Type) SetCOMP2_CSR_COMP2_LOCK(value uint32) {
	volatile.StoreUint32(&o.COMP2_CSR.Reg, volatile.LoadUint32(&o.COMP2_CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *COMP_Type) GetCOMP2_CSR_COMP2_LOCK() uint32 {
	return (volatile.LoadUint32(&o.COMP2_CSR.Reg) & 0x80000000) >> 31
}

// Cyclic redundancy check calculation unit
type CRC_Type struct {
	DR   volatile.Register32 // 0x0
	IDR  volatile.Register32 // 0x4
	CR   volatile.Register32 // 0x8
	_    [4]byte
	INIT volatile.Register32 // 0x10
	POL  volatile.Register32 // 0x14
}

// CRC.DR: Data register
func (o *CRC_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *CRC_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// CRC.IDR: Independent data register
func (o *CRC_Type) SetIDR(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, value)
}
func (o *CRC_Type) GetIDR() uint32 {
	return volatile.LoadUint32(&o.IDR.Reg)
}

// CRC.CR: Control register
func (o *CRC_Type) SetCR_REV_OUT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *CRC_Type) GetCR_REV_OUT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *CRC_Type) SetCR_REV_IN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x60)|value<<5)
}
func (o *CRC_Type) GetCR_REV_IN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x60) >> 5
}
func (o *CRC_Type) SetCR_POLYSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x18)|value<<3)
}
func (o *CRC_Type) GetCR_POLYSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x18) >> 3
}
func (o *CRC_Type) SetCR_RESET(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *CRC_Type) GetCR_RESET() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// CRC.INIT: Initial CRC value
func (o *CRC_Type) SetINIT(value uint32) {
	volatile.StoreUint32(&o.INIT.Reg, value)
}
func (o *CRC_Type) GetINIT() uint32 {
	return volatile.LoadUint32(&o.INIT.Reg)
}

// CRC.POL: polynomial
func (o *CRC_Type) SetPOL(value uint32) {
	volatile.StoreUint32(&o.POL.Reg, value)
}
func (o *CRC_Type) GetPOL() uint32 {
	return volatile.LoadUint32(&o.POL.Reg)
}

// Clock recovery system
type CRS_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
	ISR  volatile.Register32 // 0x8
	ICR  volatile.Register32 // 0xC
}

// CRS.CR: control register
func (o *CRS_Type) SetCR_TRIM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7f00)|value<<8)
}
func (o *CRS_Type) GetCR_TRIM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x7f00) >> 8
}
func (o *CRS_Type) SetCR_SWSYNC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *CRS_Type) GetCR_SWSYNC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *CRS_Type) SetCR_AUTOTRIMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *CRS_Type) GetCR_AUTOTRIMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *CRS_Type) SetCR_CEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *CRS_Type) GetCR_CEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *CRS_Type) SetCR_SYNCOKIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *CRS_Type) GetCR_SYNCOKIE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *CRS_Type) SetCR_ESYNCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *CRS_Type) GetCR_ESYNCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *CRS_Type) SetCR_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *CRS_Type) GetCR_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *CRS_Type) SetCR_SYNCWARNIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *CRS_Type) GetCR_SYNCWARNIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}

// CRS.CFGR: configuration register
func (o *CRS_Type) SetCFGR_SYNCPOL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x80000000)|value<<31)
}
func (o *CRS_Type) GetCFGR_SYNCPOL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x80000000) >> 31
}
func (o *CRS_Type) SetCFGR_SYNCSRC(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x30000000)|value<<28)
}
func (o *CRS_Type) GetCFGR_SYNCSRC() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x30000000) >> 28
}
func (o *CRS_Type) SetCFGR_SYNCDIV(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x7000000)|value<<24)
}
func (o *CRS_Type) GetCFGR_SYNCDIV() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x7000000) >> 24
}
func (o *CRS_Type) SetCFGR_FELIM(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xff0000)|value<<16)
}
func (o *CRS_Type) GetCFGR_FELIM() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xff0000) >> 16
}
func (o *CRS_Type) SetCFGR_RELOAD(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xffff)|value)
}
func (o *CRS_Type) GetCFGR_RELOAD() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0xffff
}

// CRS.ISR: interrupt and status register
func (o *CRS_Type) SetISR_FECAP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xffff0000)|value<<16)
}
func (o *CRS_Type) GetISR_FECAP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xffff0000) >> 16
}
func (o *CRS_Type) SetISR_FEDIR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *CRS_Type) GetISR_FEDIR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *CRS_Type) SetISR_SYNCOKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *CRS_Type) GetISR_SYNCOKF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *CRS_Type) SetISR_TRIMOVF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *CRS_Type) GetISR_TRIMOVF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *CRS_Type) SetISR_SYNCMISS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *CRS_Type) GetISR_SYNCMISS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *CRS_Type) SetISR_SYNCERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *CRS_Type) GetISR_SYNCERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *CRS_Type) SetISR_ESYNCF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *CRS_Type) GetISR_ESYNCF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *CRS_Type) SetISR_ERRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *CRS_Type) GetISR_ERRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *CRS_Type) SetISR_SYNCWARNF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *CRS_Type) GetISR_SYNCWARNF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}

// CRS.ICR: interrupt flag clear register
func (o *CRS_Type) SetICR_SYNCOKC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *CRS_Type) GetICR_SYNCOKC() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *CRS_Type) SetICR_ESYNCC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *CRS_Type) GetICR_ESYNCC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *CRS_Type) SetICR_ERRC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *CRS_Type) GetICR_ERRC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *CRS_Type) SetICR_SYNCWARNC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *CRS_Type) GetICR_SYNCWARNC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}

// DAC
type DAC_Type struct {
	CR      volatile.Register32 // 0x0
	SWTRGR  volatile.Register32 // 0x4
	DHR12R1 volatile.Register32 // 0x8
	DHR12L1 volatile.Register32 // 0xC
	DHR8R1  volatile.Register32 // 0x10
	DHR12R2 volatile.Register32 // 0x14
	DHR12L2 volatile.Register32 // 0x18
	DHR8R2  volatile.Register32 // 0x1C
	DHR12RD volatile.Register32 // 0x20
	DHR12LD volatile.Register32 // 0x24
	DHR8RD  volatile.Register32 // 0x28
	DOR1    volatile.Register32 // 0x2C
	DOR2    volatile.Register32 // 0x30
	SR      volatile.Register32 // 0x34
	CCR     volatile.Register32 // 0x38
	MCR     volatile.Register32 // 0x3C
	SHSR1   volatile.Register32 // 0x40
	SHSR2   volatile.Register32 // 0x44
	SHHR    volatile.Register32 // 0x48
	SHRR    volatile.Register32 // 0x4C
}

// DAC.CR: DAC control register
func (o *DAC_Type) SetCR_EN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *DAC_Type) GetCR_EN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *DAC_Type) SetCR_EN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetCR_EN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 32
}
func (o *DAC_Type) SetCR_TEN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *DAC_Type) GetCR_TEN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *DAC_Type) SetCR_TEN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<33)
}
func (o *DAC_Type) GetCR_TEN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 33
}
func (o *DAC_Type) SetCR_TSEL1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3c)|value<<2)
}
func (o *DAC_Type) GetCR_TSEL1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3c) >> 2
}
func (o *DAC_Type) SetCR_WAVE1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00000)|value<<22)
}
func (o *DAC_Type) GetCR_WAVE1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00000) >> 22
}
func (o *DAC_Type) SetCR_WAVE2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<38)
}
func (o *DAC_Type) GetCR_WAVE2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 38
}
func (o *DAC_Type) SetCR_MAMP1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf000000)|value<<24)
}
func (o *DAC_Type) GetCR_MAMP1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf000000) >> 24
}
func (o *DAC_Type) SetCR_MAMP2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<40)
}
func (o *DAC_Type) GetCR_MAMP2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 40
}
func (o *DAC_Type) SetCR_DMAEN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *DAC_Type) GetCR_DMAEN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *DAC_Type) SetCR_DMAEN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<44)
}
func (o *DAC_Type) GetCR_DMAEN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 44
}
func (o *DAC_Type) SetCR_DMAUDRIE1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *DAC_Type) GetCR_DMAUDRIE1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *DAC_Type) SetCR_DMAUDRIE2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<45)
}
func (o *DAC_Type) GetCR_DMAUDRIE2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 45
}
func (o *DAC_Type) SetCR_CEN1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *DAC_Type) GetCR_CEN1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *DAC_Type) SetCR_CEN2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x0)|value<<46)
}
func (o *DAC_Type) GetCR_CEN2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x0) >> 46
}
func (o *DAC_Type) SetCR_HFSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *DAC_Type) GetCR_HFSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *DAC_Type) SetCR_TSEL2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3c0000)|value<<18)
}
func (o *DAC_Type) GetCR_TSEL2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3c0000) >> 18
}

// DAC.SWTRGR: DAC software trigger register
func (o *DAC_Type) SetSWTRGR_SWTRIG1(value uint32) {
	volatile.StoreUint32(&o.SWTRGR.Reg, volatile.LoadUint32(&o.SWTRGR.Reg)&^(0x2)|value<<1)
}
func (o *DAC_Type) GetSWTRGR_SWTRIG1() uint32 {
	return (volatile.LoadUint32(&o.SWTRGR.Reg) & 0x2) >> 1
}
func (o *DAC_Type) SetSWTRGR_SWTRIG2(value uint32) {
	volatile.StoreUint32(&o.SWTRGR.Reg, volatile.LoadUint32(&o.SWTRGR.Reg)&^(0x4)|value<<2)
}
func (o *DAC_Type) GetSWTRGR_SWTRIG2() uint32 {
	return (volatile.LoadUint32(&o.SWTRGR.Reg) & 0x4) >> 2
}

// DAC.DHR12R1: channel%s 12-bit right-aligned data holding register
func (o *DAC_Type) SetDHR12R1_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12R1.Reg, volatile.LoadUint32(&o.DHR12R1.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDHR12R1_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR12R1.Reg) & 0xfff
}

// DAC.DHR12L1: channel%s 12-bit left aligned data holding register
func (o *DAC_Type) SetDHR12L1_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12L1.Reg, volatile.LoadUint32(&o.DHR12L1.Reg)&^(0xfff0)|value<<4)
}
func (o *DAC_Type) GetDHR12L1_DACCDHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12L1.Reg) & 0xfff0) >> 4
}

// DAC.DHR8R1: channel%s 8-bit right aligned data holding register
func (o *DAC_Type) SetDHR8R1_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR8R1.Reg, volatile.LoadUint32(&o.DHR8R1.Reg)&^(0xff)|value)
}
func (o *DAC_Type) GetDHR8R1_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR8R1.Reg) & 0xff
}

// DAC.DHR12R2: channel%s 12-bit right-aligned data holding register
func (o *DAC_Type) SetDHR12R2_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12R2.Reg, volatile.LoadUint32(&o.DHR12R2.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDHR12R2_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR12R2.Reg) & 0xfff
}

// DAC.DHR12L2: channel%s 12-bit left aligned data holding register
func (o *DAC_Type) SetDHR12L2_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR12L2.Reg, volatile.LoadUint32(&o.DHR12L2.Reg)&^(0xfff0)|value<<4)
}
func (o *DAC_Type) GetDHR12L2_DACCDHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12L2.Reg) & 0xfff0) >> 4
}

// DAC.DHR8R2: channel%s 8-bit right aligned data holding register
func (o *DAC_Type) SetDHR8R2_DACCDHR(value uint32) {
	volatile.StoreUint32(&o.DHR8R2.Reg, volatile.LoadUint32(&o.DHR8R2.Reg)&^(0xff)|value)
}
func (o *DAC_Type) GetDHR8R2_DACCDHR() uint32 {
	return volatile.LoadUint32(&o.DHR8R2.Reg) & 0xff
}

// DAC.DHR12RD: Dual DAC 12-bit right-aligned data holding register
func (o *DAC_Type) SetDHR12RD_DACC1DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12RD.Reg, volatile.LoadUint32(&o.DHR12RD.Reg)&^(0xfff0000)|value<<16)
}
func (o *DAC_Type) GetDHR12RD_DACC1DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12RD.Reg) & 0xfff0000) >> 16
}
func (o *DAC_Type) SetDHR12RD_DACC2DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12RD.Reg, volatile.LoadUint32(&o.DHR12RD.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetDHR12RD_DACC2DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12RD.Reg) & 0x0) >> 32
}

// DAC.DHR12LD: DUAL DAC 12-bit left aligned data holding register
func (o *DAC_Type) SetDHR12LD_DACC1DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12LD.Reg, volatile.LoadUint32(&o.DHR12LD.Reg)&^(0xfff00000)|value<<20)
}
func (o *DAC_Type) GetDHR12LD_DACC1DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12LD.Reg) & 0xfff00000) >> 20
}
func (o *DAC_Type) SetDHR12LD_DACC2DHR(value uint32) {
	volatile.StoreUint32(&o.DHR12LD.Reg, volatile.LoadUint32(&o.DHR12LD.Reg)&^(0x0)|value<<36)
}
func (o *DAC_Type) GetDHR12LD_DACC2DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR12LD.Reg) & 0x0) >> 36
}

// DAC.DHR8RD: DUAL DAC 8-bit right aligned data holding register
func (o *DAC_Type) SetDHR8RD_DACC1DHR(value uint32) {
	volatile.StoreUint32(&o.DHR8RD.Reg, volatile.LoadUint32(&o.DHR8RD.Reg)&^(0xff00)|value<<8)
}
func (o *DAC_Type) GetDHR8RD_DACC1DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR8RD.Reg) & 0xff00) >> 8
}
func (o *DAC_Type) SetDHR8RD_DACC2DHR(value uint32) {
	volatile.StoreUint32(&o.DHR8RD.Reg, volatile.LoadUint32(&o.DHR8RD.Reg)&^(0xff0000)|value<<16)
}
func (o *DAC_Type) GetDHR8RD_DACC2DHR() uint32 {
	return (volatile.LoadUint32(&o.DHR8RD.Reg) & 0xff0000) >> 16
}

// DAC.DOR1: channel%s data output register
func (o *DAC_Type) SetDOR1_DACCDOR(value uint32) {
	volatile.StoreUint32(&o.DOR1.Reg, volatile.LoadUint32(&o.DOR1.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDOR1_DACCDOR() uint32 {
	return volatile.LoadUint32(&o.DOR1.Reg) & 0xfff
}

// DAC.DOR2: channel%s data output register
func (o *DAC_Type) SetDOR2_DACCDOR(value uint32) {
	volatile.StoreUint32(&o.DOR2.Reg, volatile.LoadUint32(&o.DOR2.Reg)&^(0xfff)|value)
}
func (o *DAC_Type) GetDOR2_DACCDOR() uint32 {
	return volatile.LoadUint32(&o.DOR2.Reg) & 0xfff
}

// DAC.SR: DAC status register
func (o *DAC_Type) SetSR_DMAUDR1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000000)|value<<29)
}
func (o *DAC_Type) GetSR_DMAUDR1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000000) >> 29
}
func (o *DAC_Type) SetSR_DMAUDR2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<45)
}
func (o *DAC_Type) GetSR_DMAUDR2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 45
}
func (o *DAC_Type) SetSR_CAL_FLAG1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000000)|value<<30)
}
func (o *DAC_Type) GetSR_CAL_FLAG1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000000) >> 30
}
func (o *DAC_Type) SetSR_CAL_FLAG2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<46)
}
func (o *DAC_Type) GetSR_CAL_FLAG2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 46
}
func (o *DAC_Type) SetSR_BWST1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80000000)|value<<31)
}
func (o *DAC_Type) GetSR_BWST1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80000000) >> 31
}
func (o *DAC_Type) SetSR_BWST2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x0)|value<<47)
}
func (o *DAC_Type) GetSR_BWST2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x0) >> 47
}

// DAC.CCR: DAC calibration control register
func (o *DAC_Type) SetCCR_OTRIM1(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x1f0000)|value<<16)
}
func (o *DAC_Type) GetCCR_OTRIM1() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x1f0000) >> 16
}
func (o *DAC_Type) SetCCR_OTRIM2(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetCCR_OTRIM2() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x0) >> 32
}

// DAC.MCR: DAC mode control register
func (o *DAC_Type) SetMCR_MODE1(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x70000)|value<<16)
}
func (o *DAC_Type) GetMCR_MODE1() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x70000) >> 16
}
func (o *DAC_Type) SetMCR_MODE2(value uint32) {
	volatile.StoreUint32(&o.MCR.Reg, volatile.LoadUint32(&o.MCR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetMCR_MODE2() uint32 {
	return (volatile.LoadUint32(&o.MCR.Reg) & 0x0) >> 32
}

// DAC.SHSR1: DAC channel%s sample and hold sample time register
func (o *DAC_Type) SetSHSR1_TSAMPLE(value uint32) {
	volatile.StoreUint32(&o.SHSR1.Reg, volatile.LoadUint32(&o.SHSR1.Reg)&^(0x3ff)|value)
}
func (o *DAC_Type) GetSHSR1_TSAMPLE() uint32 {
	return volatile.LoadUint32(&o.SHSR1.Reg) & 0x3ff
}

// DAC.SHSR2: DAC channel%s sample and hold sample time register
func (o *DAC_Type) SetSHSR2_TSAMPLE(value uint32) {
	volatile.StoreUint32(&o.SHSR2.Reg, volatile.LoadUint32(&o.SHSR2.Reg)&^(0x3ff)|value)
}
func (o *DAC_Type) GetSHSR2_TSAMPLE() uint32 {
	return volatile.LoadUint32(&o.SHSR2.Reg) & 0x3ff
}

// DAC.SHHR: DAC Sample and Hold hold time register
func (o *DAC_Type) SetSHHR_THOLD1(value uint32) {
	volatile.StoreUint32(&o.SHHR.Reg, volatile.LoadUint32(&o.SHHR.Reg)&^(0x3ff0000)|value<<16)
}
func (o *DAC_Type) GetSHHR_THOLD1() uint32 {
	return (volatile.LoadUint32(&o.SHHR.Reg) & 0x3ff0000) >> 16
}
func (o *DAC_Type) SetSHHR_THOLD2(value uint32) {
	volatile.StoreUint32(&o.SHHR.Reg, volatile.LoadUint32(&o.SHHR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetSHHR_THOLD2() uint32 {
	return (volatile.LoadUint32(&o.SHHR.Reg) & 0x0) >> 32
}

// DAC.SHRR: DAC Sample and Hold refresh time register
func (o *DAC_Type) SetSHRR_TREFRESH1(value uint32) {
	volatile.StoreUint32(&o.SHRR.Reg, volatile.LoadUint32(&o.SHRR.Reg)&^(0xff0000)|value<<16)
}
func (o *DAC_Type) GetSHRR_TREFRESH1() uint32 {
	return (volatile.LoadUint32(&o.SHRR.Reg) & 0xff0000) >> 16
}
func (o *DAC_Type) SetSHRR_TREFRESH2(value uint32) {
	volatile.StoreUint32(&o.SHRR.Reg, volatile.LoadUint32(&o.SHRR.Reg)&^(0x0)|value<<32)
}
func (o *DAC_Type) GetSHRR_TREFRESH2() uint32 {
	return (volatile.LoadUint32(&o.SHRR.Reg) & 0x0) >> 32
}

// MCU debug component
type DBGMCU_Type struct {
	IDCODE   volatile.Register32 // 0x0
	CR       volatile.Register32 // 0x4
	APB1LFZR volatile.Register32 // 0x8
	APB1HFZR volatile.Register32 // 0xC
	APB2FZR  volatile.Register32 // 0x10
}

// DBGMCU.IDCODE: DBGMCU_IDCODE
func (o *DBGMCU_Type) SetIDCODE_DEV_ID(value uint32) {
	volatile.StoreUint32(&o.IDCODE.Reg, volatile.LoadUint32(&o.IDCODE.Reg)&^(0xfff)|value)
}
func (o *DBGMCU_Type) GetIDCODE_DEV_ID() uint32 {
	return volatile.LoadUint32(&o.IDCODE.Reg) & 0xfff
}
func (o *DBGMCU_Type) SetIDCODE_REV_ID(value uint32) {
	volatile.StoreUint32(&o.IDCODE.Reg, volatile.LoadUint32(&o.IDCODE.Reg)&^(0xffff0000)|value<<16)
}
func (o *DBGMCU_Type) GetIDCODE_REV_ID() uint32 {
	return (volatile.LoadUint32(&o.IDCODE.Reg) & 0xffff0000) >> 16
}

// DBGMCU.CR: Debug MCU configuration register
func (o *DBGMCU_Type) SetCR_DBG_STOP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetCR_DBG_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetCR_DBG_STANDBY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DBGMCU_Type) GetCR_DBG_STANDBY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *DBGMCU_Type) SetCR_TRACE_IOEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *DBGMCU_Type) GetCR_TRACE_IOEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *DBGMCU_Type) SetCR_TRACE_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc0)|value<<6)
}
func (o *DBGMCU_Type) GetCR_TRACE_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc0) >> 6
}
func (o *DBGMCU_Type) SetCR_TRACE_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *DBGMCU_Type) GetCR_TRACE_EN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}

// DBGMCU.APB1LFZR: Debug MCU APB1 freeze register1
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM2_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x1)|value)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM2_STOP() uint32 {
	return volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x1
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM6_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x10)|value<<4)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM6_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x10) >> 4
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM7_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x20)|value<<5)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM7_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x20) >> 5
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_RTC_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x400)|value<<10)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_RTC_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x400) >> 10
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_WWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x800)|value<<11)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_WWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x800) >> 11
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_IWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x1000)|value<<12)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_IWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x1000) >> 12
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_I2C1_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x200000)|value<<21)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_I2C1_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x200000) >> 21
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_I2C2_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x400000)|value<<22)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_I2C2_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x400000) >> 22
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_I2C3_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x800000)|value<<23)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_I2C3_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x800000) >> 23
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_LPTIM1_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x80000000)|value<<31)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_LPTIM1_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x80000000) >> 31
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM3_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM3_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM4_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x4)|value<<2)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM4_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x4) >> 2
}
func (o *DBGMCU_Type) SetAPB1LFZR_DBG_TIM5_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1LFZR.Reg, volatile.LoadUint32(&o.APB1LFZR.Reg)&^(0x8)|value<<3)
}
func (o *DBGMCU_Type) GetAPB1LFZR_DBG_TIM5_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1LFZR.Reg) & 0x8) >> 3
}

// DBGMCU.APB1HFZR: Debug MCU APB1 freeze register 2
func (o *DBGMCU_Type) SetAPB1HFZR_DBG_LPTIM2_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1HFZR.Reg, volatile.LoadUint32(&o.APB1HFZR.Reg)&^(0x20)|value<<5)
}
func (o *DBGMCU_Type) GetAPB1HFZR_DBG_LPTIM2_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1HFZR.Reg) & 0x20) >> 5
}
func (o *DBGMCU_Type) SetAPB1HFZR_DBG_I2C4_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1HFZR.Reg, volatile.LoadUint32(&o.APB1HFZR.Reg)&^(0x2)|value<<1)
}
func (o *DBGMCU_Type) GetAPB1HFZR_DBG_I2C4_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1HFZR.Reg) & 0x2) >> 1
}
func (o *DBGMCU_Type) SetAPB1HFZR_DBG_LPTIM3_STOP(value uint32) {
	volatile.StoreUint32(&o.APB1HFZR.Reg, volatile.LoadUint32(&o.APB1HFZR.Reg)&^(0x40)|value<<6)
}
func (o *DBGMCU_Type) GetAPB1HFZR_DBG_LPTIM3_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB1HFZR.Reg) & 0x40) >> 6
}

// DBGMCU.APB2FZR: Debug MCU APB2 freeze register
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM1_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x800)|value<<11)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM1_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x800) >> 11
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM15_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x10000)|value<<16)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM15_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x10000) >> 16
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM16_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x20000)|value<<17)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM16_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x20000) >> 17
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM8_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x2000)|value<<13)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM8_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x2000) >> 13
}
func (o *DBGMCU_Type) SetAPB2FZR_DBG_TIM17_STOP(value uint32) {
	volatile.StoreUint32(&o.APB2FZR.Reg, volatile.LoadUint32(&o.APB2FZR.Reg)&^(0x40000)|value<<18)
}
func (o *DBGMCU_Type) GetAPB2FZR_DBG_TIM17_STOP() uint32 {
	return (volatile.LoadUint32(&o.APB2FZR.Reg) & 0x40000) >> 18
}

// Debug Control Block
type DCB_Type struct {
	DSCSR volatile.Register32 // 0x0
}

// DCB.DSCSR: Debug Security Control and Status Register
func (o *DCB_Type) SetDSCSR_CDS(value uint32) {
	volatile.StoreUint32(&o.DSCSR.Reg, volatile.LoadUint32(&o.DSCSR.Reg)&^(0x10000)|value<<16)
}
func (o *DCB_Type) GetDSCSR_CDS() uint32 {
	return (volatile.LoadUint32(&o.DSCSR.Reg) & 0x10000) >> 16
}

// Digital filter for sigma delta modulators
type DFSDM_Type struct {
	CH  [8]DFSDM_CH_Type  // 0x0
	FLT [4]DFSDM_FLT_Type // 0x100
}

// DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers
type DFSDM_CH_Type struct {
	CFGR1  volatile.Register32 // 0x0
	CFGR2  volatile.Register32 // 0x4
	AWSCDR volatile.Register32 // 0x8
	WDATR  volatile.Register32 // 0xC
	DATINR volatile.Register32 // 0x10
	DLYR   volatile.Register32 // 0x14
	_      [8]byte
}

// DFSDM_CH.CFGR1: channel configuration y register
func (o *DFSDM_CH_Type) SetCFGR1_DFSDMEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x80000000)|value<<31)
}
func (o *DFSDM_CH_Type) GetCFGR1_DFSDMEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x80000000) >> 31
}
func (o *DFSDM_CH_Type) SetCFGR1_CKOUTSRC(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x40000000)|value<<30)
}
func (o *DFSDM_CH_Type) GetCFGR1_CKOUTSRC() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x40000000) >> 30
}
func (o *DFSDM_CH_Type) SetCFGR1_CKOUTDIV(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xff0000)|value<<16)
}
func (o *DFSDM_CH_Type) GetCFGR1_CKOUTDIV() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xff0000) >> 16
}
func (o *DFSDM_CH_Type) SetCFGR1_DATPACK(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xc000)|value<<14)
}
func (o *DFSDM_CH_Type) GetCFGR1_DATPACK() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xc000) >> 14
}
func (o *DFSDM_CH_Type) SetCFGR1_DATMPX(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3000)|value<<12)
}
func (o *DFSDM_CH_Type) GetCFGR1_DATMPX() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x3000) >> 12
}
func (o *DFSDM_CH_Type) SetCFGR1_CHINSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100)|value<<8)
}
func (o *DFSDM_CH_Type) GetCFGR1_CHINSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100) >> 8
}
func (o *DFSDM_CH_Type) SetCFGR1_CHEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x80)|value<<7)
}
func (o *DFSDM_CH_Type) GetCFGR1_CHEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x80) >> 7
}
func (o *DFSDM_CH_Type) SetCFGR1_CKABEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x40)|value<<6)
}
func (o *DFSDM_CH_Type) GetCFGR1_CKABEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x40) >> 6
}
func (o *DFSDM_CH_Type) SetCFGR1_SCDEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20)|value<<5)
}
func (o *DFSDM_CH_Type) GetCFGR1_SCDEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20) >> 5
}
func (o *DFSDM_CH_Type) SetCFGR1_SPICKSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xc)|value<<2)
}
func (o *DFSDM_CH_Type) GetCFGR1_SPICKSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xc) >> 2
}
func (o *DFSDM_CH_Type) SetCFGR1_SITP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3)|value)
}
func (o *DFSDM_CH_Type) GetCFGR1_SITP() uint32 {
	return volatile.LoadUint32(&o.CFGR1.Reg) & 0x3
}

// DFSDM_CH.CFGR2: channel configuration y register
func (o *DFSDM_CH_Type) SetCFGR2_OFFSET(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0xffffff00)|value<<8)
}
func (o *DFSDM_CH_Type) GetCFGR2_OFFSET() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0xffffff00) >> 8
}
func (o *DFSDM_CH_Type) SetCFGR2_DTRBS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0xf8)|value<<3)
}
func (o *DFSDM_CH_Type) GetCFGR2_DTRBS() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0xf8) >> 3
}

// DFSDM_CH.AWSCDR: analog watchdog and short-circuit detector register
func (o *DFSDM_CH_Type) SetAWSCDR_AWFORD(value uint32) {
	volatile.StoreUint32(&o.AWSCDR.Reg, volatile.LoadUint32(&o.AWSCDR.Reg)&^(0xc00000)|value<<22)
}
func (o *DFSDM_CH_Type) GetAWSCDR_AWFORD() uint32 {
	return (volatile.LoadUint32(&o.AWSCDR.Reg) & 0xc00000) >> 22
}
func (o *DFSDM_CH_Type) SetAWSCDR_AWFOSR(value uint32) {
	volatile.StoreUint32(&o.AWSCDR.Reg, volatile.LoadUint32(&o.AWSCDR.Reg)&^(0x1f0000)|value<<16)
}
func (o *DFSDM_CH_Type) GetAWSCDR_AWFOSR() uint32 {
	return (volatile.LoadUint32(&o.AWSCDR.Reg) & 0x1f0000) >> 16
}
func (o *DFSDM_CH_Type) SetAWSCDR_BKSCD(value uint32) {
	volatile.StoreUint32(&o.AWSCDR.Reg, volatile.LoadUint32(&o.AWSCDR.Reg)&^(0xf000)|value<<12)
}
func (o *DFSDM_CH_Type) GetAWSCDR_BKSCD() uint32 {
	return (volatile.LoadUint32(&o.AWSCDR.Reg) & 0xf000) >> 12
}
func (o *DFSDM_CH_Type) SetAWSCDR_SCDT(value uint32) {
	volatile.StoreUint32(&o.AWSCDR.Reg, volatile.LoadUint32(&o.AWSCDR.Reg)&^(0xff)|value)
}
func (o *DFSDM_CH_Type) GetAWSCDR_SCDT() uint32 {
	return volatile.LoadUint32(&o.AWSCDR.Reg) & 0xff
}

// DFSDM_CH.WDATR: channel watchdog filter data register
func (o *DFSDM_CH_Type) SetWDATR_WDATA(value uint32) {
	volatile.StoreUint32(&o.WDATR.Reg, volatile.LoadUint32(&o.WDATR.Reg)&^(0xffff)|value)
}
func (o *DFSDM_CH_Type) GetWDATR_WDATA() uint32 {
	return volatile.LoadUint32(&o.WDATR.Reg) & 0xffff
}

// DFSDM_CH.DATINR: channel data input register
func (o *DFSDM_CH_Type) SetDATINR_INDAT1(value uint32) {
	volatile.StoreUint32(&o.DATINR.Reg, volatile.LoadUint32(&o.DATINR.Reg)&^(0xffff0000)|value<<16)
}
func (o *DFSDM_CH_Type) GetDATINR_INDAT1() uint32 {
	return (volatile.LoadUint32(&o.DATINR.Reg) & 0xffff0000) >> 16
}
func (o *DFSDM_CH_Type) SetDATINR_INDAT0(value uint32) {
	volatile.StoreUint32(&o.DATINR.Reg, volatile.LoadUint32(&o.DATINR.Reg)&^(0xffff)|value)
}
func (o *DFSDM_CH_Type) GetDATINR_INDAT0() uint32 {
	return volatile.LoadUint32(&o.DATINR.Reg) & 0xffff
}

// DFSDM_CH.DLYR: DFSDM channel y delay register
func (o *DFSDM_CH_Type) SetDLYR_PLSSKP(value uint32) {
	volatile.StoreUint32(&o.DLYR.Reg, volatile.LoadUint32(&o.DLYR.Reg)&^(0x3f)|value)
}
func (o *DFSDM_CH_Type) GetDLYR_PLSSKP() uint32 {
	return volatile.LoadUint32(&o.DLYR.Reg) & 0x3f
}

// Cluster FLT%s, containing FLT?CR1, FLT?CR2, FLT?ISR, FLT?ICR, FLT?JCHGR, FLT?FCR, FLT?JDATAR, FLT?RDATAR, FLT?AWHTR, FLT?AWLTR, FLT?AWSR, FLT?AWCFR, FLT?EXMAX, FLT?EXMIN, FLT?CNVTIMR
type DFSDM_FLT_Type struct {
	CR1     volatile.Register32 // 0x100
	CR2     volatile.Register32 // 0x104
	ISR     volatile.Register32 // 0x108
	ICR     volatile.Register32 // 0x10C
	JCHGR   volatile.Register32 // 0x110
	FCR     volatile.Register32 // 0x114
	JDATAR  volatile.Register32 // 0x118
	RDATAR  volatile.Register32 // 0x11C
	AWHTR   volatile.Register32 // 0x120
	AWLTR   volatile.Register32 // 0x124
	AWSR    volatile.Register32 // 0x128
	AWCFR   volatile.Register32 // 0x12C
	EXMAX   volatile.Register32 // 0x130
	EXMIN   volatile.Register32 // 0x134
	CNVTIMR volatile.Register32 // 0x138
	_       [68]byte
}

// DFSDM_FLT.CR1: control register 1
func (o *DFSDM_FLT_Type) SetCR1_AWFSEL(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *DFSDM_FLT_Type) GetCR1_AWFSEL() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *DFSDM_FLT_Type) SetCR1_FAST(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000000)|value<<29)
}
func (o *DFSDM_FLT_Type) GetCR1_FAST() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000000) >> 29
}
func (o *DFSDM_FLT_Type) SetCR1_RCH(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x7000000)|value<<24)
}
func (o *DFSDM_FLT_Type) GetCR1_RCH() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x7000000) >> 24
}
func (o *DFSDM_FLT_Type) SetCR1_RDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200000)|value<<21)
}
func (o *DFSDM_FLT_Type) GetCR1_RDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200000) >> 21
}
func (o *DFSDM_FLT_Type) SetCR1_RSYNC(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000)|value<<19)
}
func (o *DFSDM_FLT_Type) GetCR1_RSYNC() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000) >> 19
}
func (o *DFSDM_FLT_Type) SetCR1_RCONT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *DFSDM_FLT_Type) GetCR1_RCONT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *DFSDM_FLT_Type) SetCR1_RSWSTART(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *DFSDM_FLT_Type) GetCR1_RSWSTART() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *DFSDM_FLT_Type) SetCR1_JEXTEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x6000)|value<<13)
}
func (o *DFSDM_FLT_Type) GetCR1_JEXTEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x6000) >> 13
}
func (o *DFSDM_FLT_Type) SetCR1_JEXTSEL(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1f00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetCR1_JEXTSEL() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1f00) >> 8
}
func (o *DFSDM_FLT_Type) SetCR1_JDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *DFSDM_FLT_Type) GetCR1_JDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *DFSDM_FLT_Type) SetCR1_JSCAN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetCR1_JSCAN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *DFSDM_FLT_Type) SetCR1_JSYNC(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetCR1_JSYNC() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetCR1_JSWSTART(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *DFSDM_FLT_Type) GetCR1_JSWSTART() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *DFSDM_FLT_Type) SetCR1_DFEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *DFSDM_FLT_Type) GetCR1_DFEN() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}

// DFSDM_FLT.CR2: control register 2
func (o *DFSDM_FLT_Type) SetCR2_AWDCH(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff0000)|value<<16)
}
func (o *DFSDM_FLT_Type) GetCR2_AWDCH() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff0000) >> 16
}
func (o *DFSDM_FLT_Type) SetCR2_EXCH(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetCR2_EXCH() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff00) >> 8
}
func (o *DFSDM_FLT_Type) SetCR2_CKABIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *DFSDM_FLT_Type) GetCR2_CKABIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *DFSDM_FLT_Type) SetCR2_SCDIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *DFSDM_FLT_Type) GetCR2_SCDIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *DFSDM_FLT_Type) SetCR2_AWDIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetCR2_AWDIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *DFSDM_FLT_Type) SetCR2_ROVRIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetCR2_ROVRIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetCR2_JOVRIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *DFSDM_FLT_Type) GetCR2_JOVRIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *DFSDM_FLT_Type) SetCR2_REOCIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *DFSDM_FLT_Type) GetCR2_REOCIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2) >> 1
}
func (o *DFSDM_FLT_Type) SetCR2_JEOCIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *DFSDM_FLT_Type) GetCR2_JEOCIE() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}

// DFSDM_FLT.ISR: interrupt and status register
func (o *DFSDM_FLT_Type) SetISR_SCDF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xff000000)|value<<24)
}
func (o *DFSDM_FLT_Type) GetISR_SCDF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xff000000) >> 24
}
func (o *DFSDM_FLT_Type) SetISR_CKABF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xff0000)|value<<16)
}
func (o *DFSDM_FLT_Type) GetISR_CKABF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xff0000) >> 16
}
func (o *DFSDM_FLT_Type) SetISR_RCIP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *DFSDM_FLT_Type) GetISR_RCIP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *DFSDM_FLT_Type) SetISR_JCIP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *DFSDM_FLT_Type) GetISR_JCIP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *DFSDM_FLT_Type) SetISR_AWDF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetISR_AWDF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *DFSDM_FLT_Type) SetISR_ROVRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetISR_ROVRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetISR_JOVRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *DFSDM_FLT_Type) GetISR_JOVRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *DFSDM_FLT_Type) SetISR_REOCF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *DFSDM_FLT_Type) GetISR_REOCF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *DFSDM_FLT_Type) SetISR_JEOCF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *DFSDM_FLT_Type) GetISR_JEOCF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// DFSDM_FLT.ICR: interrupt flag clear register
func (o *DFSDM_FLT_Type) SetICR_CLRSCDF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0xff000000)|value<<24)
}
func (o *DFSDM_FLT_Type) GetICR_CLRSCDF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0xff000000) >> 24
}
func (o *DFSDM_FLT_Type) SetICR_CLRCKABF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0xff0000)|value<<16)
}
func (o *DFSDM_FLT_Type) GetICR_CLRCKABF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0xff0000) >> 16
}
func (o *DFSDM_FLT_Type) SetICR_CLRROVRF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetICR_CLRROVRF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetICR_CLRJOVRF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *DFSDM_FLT_Type) GetICR_CLRJOVRF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}

// DFSDM_FLT.JCHGR: injected channel group selection register
func (o *DFSDM_FLT_Type) SetJCHGR_JCHG(value uint32) {
	volatile.StoreUint32(&o.JCHGR.Reg, volatile.LoadUint32(&o.JCHGR.Reg)&^(0xff)|value)
}
func (o *DFSDM_FLT_Type) GetJCHGR_JCHG() uint32 {
	return volatile.LoadUint32(&o.JCHGR.Reg) & 0xff
}

// DFSDM_FLT.FCR: filter control register
func (o *DFSDM_FLT_Type) SetFCR_FORD(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0xe0000000)|value<<29)
}
func (o *DFSDM_FLT_Type) GetFCR_FORD() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0xe0000000) >> 29
}
func (o *DFSDM_FLT_Type) SetFCR_FOSR(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x3ff0000)|value<<16)
}
func (o *DFSDM_FLT_Type) GetFCR_FOSR() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x3ff0000) >> 16
}
func (o *DFSDM_FLT_Type) SetFCR_IOSR(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0xff)|value)
}
func (o *DFSDM_FLT_Type) GetFCR_IOSR() uint32 {
	return volatile.LoadUint32(&o.FCR.Reg) & 0xff
}

// DFSDM_FLT.JDATAR: data register for injected group
func (o *DFSDM_FLT_Type) SetJDATAR_JDATA(value uint32) {
	volatile.StoreUint32(&o.JDATAR.Reg, volatile.LoadUint32(&o.JDATAR.Reg)&^(0xffffff00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetJDATAR_JDATA() uint32 {
	return (volatile.LoadUint32(&o.JDATAR.Reg) & 0xffffff00) >> 8
}
func (o *DFSDM_FLT_Type) SetJDATAR_JDATACH(value uint32) {
	volatile.StoreUint32(&o.JDATAR.Reg, volatile.LoadUint32(&o.JDATAR.Reg)&^(0x7)|value)
}
func (o *DFSDM_FLT_Type) GetJDATAR_JDATACH() uint32 {
	return volatile.LoadUint32(&o.JDATAR.Reg) & 0x7
}

// DFSDM_FLT.RDATAR: data register for the regular channel
func (o *DFSDM_FLT_Type) SetRDATAR_RDATA(value uint32) {
	volatile.StoreUint32(&o.RDATAR.Reg, volatile.LoadUint32(&o.RDATAR.Reg)&^(0xffffff00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetRDATAR_RDATA() uint32 {
	return (volatile.LoadUint32(&o.RDATAR.Reg) & 0xffffff00) >> 8
}
func (o *DFSDM_FLT_Type) SetRDATAR_RPEND(value uint32) {
	volatile.StoreUint32(&o.RDATAR.Reg, volatile.LoadUint32(&o.RDATAR.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetRDATAR_RPEND() uint32 {
	return (volatile.LoadUint32(&o.RDATAR.Reg) & 0x10) >> 4
}
func (o *DFSDM_FLT_Type) SetRDATAR_RDATACH(value uint32) {
	volatile.StoreUint32(&o.RDATAR.Reg, volatile.LoadUint32(&o.RDATAR.Reg)&^(0x7)|value)
}
func (o *DFSDM_FLT_Type) GetRDATAR_RDATACH() uint32 {
	return volatile.LoadUint32(&o.RDATAR.Reg) & 0x7
}

// DFSDM_FLT.AWHTR: analog watchdog high threshold register
func (o *DFSDM_FLT_Type) SetAWHTR_AWHT(value uint32) {
	volatile.StoreUint32(&o.AWHTR.Reg, volatile.LoadUint32(&o.AWHTR.Reg)&^(0xffffff00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetAWHTR_AWHT() uint32 {
	return (volatile.LoadUint32(&o.AWHTR.Reg) & 0xffffff00) >> 8
}
func (o *DFSDM_FLT_Type) SetAWHTR_BKAWH0(value uint32) {
	volatile.StoreUint32(&o.AWHTR.Reg, volatile.LoadUint32(&o.AWHTR.Reg)&^(0x2)|value<<1)
}
func (o *DFSDM_FLT_Type) GetAWHTR_BKAWH0() uint32 {
	return (volatile.LoadUint32(&o.AWHTR.Reg) & 0x2) >> 1
}
func (o *DFSDM_FLT_Type) SetAWHTR_BKAWH1(value uint32) {
	volatile.StoreUint32(&o.AWHTR.Reg, volatile.LoadUint32(&o.AWHTR.Reg)&^(0x4)|value<<2)
}
func (o *DFSDM_FLT_Type) GetAWHTR_BKAWH1() uint32 {
	return (volatile.LoadUint32(&o.AWHTR.Reg) & 0x4) >> 2
}
func (o *DFSDM_FLT_Type) SetAWHTR_BKAWH2(value uint32) {
	volatile.StoreUint32(&o.AWHTR.Reg, volatile.LoadUint32(&o.AWHTR.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetAWHTR_BKAWH2() uint32 {
	return (volatile.LoadUint32(&o.AWHTR.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetAWHTR_BKAWH3(value uint32) {
	volatile.StoreUint32(&o.AWHTR.Reg, volatile.LoadUint32(&o.AWHTR.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetAWHTR_BKAWH3() uint32 {
	return (volatile.LoadUint32(&o.AWHTR.Reg) & 0x10) >> 4
}

// DFSDM_FLT.AWLTR: analog watchdog low threshold register
func (o *DFSDM_FLT_Type) SetAWLTR_AWLT(value uint32) {
	volatile.StoreUint32(&o.AWLTR.Reg, volatile.LoadUint32(&o.AWLTR.Reg)&^(0xffffff00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetAWLTR_AWLT() uint32 {
	return (volatile.LoadUint32(&o.AWLTR.Reg) & 0xffffff00) >> 8
}
func (o *DFSDM_FLT_Type) SetAWLTR_BKAWL0(value uint32) {
	volatile.StoreUint32(&o.AWLTR.Reg, volatile.LoadUint32(&o.AWLTR.Reg)&^(0x2)|value<<1)
}
func (o *DFSDM_FLT_Type) GetAWLTR_BKAWL0() uint32 {
	return (volatile.LoadUint32(&o.AWLTR.Reg) & 0x2) >> 1
}
func (o *DFSDM_FLT_Type) SetAWLTR_BKAWL1(value uint32) {
	volatile.StoreUint32(&o.AWLTR.Reg, volatile.LoadUint32(&o.AWLTR.Reg)&^(0x4)|value<<2)
}
func (o *DFSDM_FLT_Type) GetAWLTR_BKAWL1() uint32 {
	return (volatile.LoadUint32(&o.AWLTR.Reg) & 0x4) >> 2
}
func (o *DFSDM_FLT_Type) SetAWLTR_BKAWL2(value uint32) {
	volatile.StoreUint32(&o.AWLTR.Reg, volatile.LoadUint32(&o.AWLTR.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetAWLTR_BKAWL2() uint32 {
	return (volatile.LoadUint32(&o.AWLTR.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetAWLTR_BKAWL3(value uint32) {
	volatile.StoreUint32(&o.AWLTR.Reg, volatile.LoadUint32(&o.AWLTR.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetAWLTR_BKAWL3() uint32 {
	return (volatile.LoadUint32(&o.AWLTR.Reg) & 0x10) >> 4
}

// DFSDM_FLT.AWSR: analog watchdog status register
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF0(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x200)|value<<9)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF0() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x200) >> 9
}
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF1(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x400)|value<<10)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF1() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x400) >> 10
}
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF2(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x800)|value<<11)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF2() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x800) >> 11
}
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF3(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x1000)|value<<12)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF3() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x1000) >> 12
}
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF4(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x2000)|value<<13)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF4() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x2000) >> 13
}
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF5(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x4000)|value<<14)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF5() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x4000) >> 14
}
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF6(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x8000)|value<<15)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF6() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x8000) >> 15
}
func (o *DFSDM_FLT_Type) SetAWSR_AWHTF7(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x10000)|value<<16)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWHTF7() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x10000) >> 16
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF0(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x2)|value<<1)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF0() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x2) >> 1
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF1(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x4)|value<<2)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF1() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x4) >> 2
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF2(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF2() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF3(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF3() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x10) >> 4
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF4(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x20)|value<<5)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF4() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x20) >> 5
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF5(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x40)|value<<6)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF5() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x40) >> 6
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF6(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x80)|value<<7)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF6() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x80) >> 7
}
func (o *DFSDM_FLT_Type) SetAWSR_AWLTF7(value uint32) {
	volatile.StoreUint32(&o.AWSR.Reg, volatile.LoadUint32(&o.AWSR.Reg)&^(0x100)|value<<8)
}
func (o *DFSDM_FLT_Type) GetAWSR_AWLTF7() uint32 {
	return (volatile.LoadUint32(&o.AWSR.Reg) & 0x100) >> 8
}

// DFSDM_FLT.AWCFR: analog watchdog clear flag register
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF0(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x200)|value<<9)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF0() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x200) >> 9
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF1(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x400)|value<<10)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF1() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x400) >> 10
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF2(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x800)|value<<11)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF2() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x800) >> 11
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF3(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x1000)|value<<12)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF3() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x1000) >> 12
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF4(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x2000)|value<<13)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF4() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x2000) >> 13
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF5(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x4000)|value<<14)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF5() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x4000) >> 14
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF6(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x8000)|value<<15)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF6() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x8000) >> 15
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWHTF7(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x10000)|value<<16)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWHTF7() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x10000) >> 16
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF0(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x2)|value<<1)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF0() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x2) >> 1
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF1(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x4)|value<<2)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF1() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x4) >> 2
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF2(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x8)|value<<3)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF2() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x8) >> 3
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF3(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x10)|value<<4)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF3() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x10) >> 4
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF4(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x20)|value<<5)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF4() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x20) >> 5
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF5(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x40)|value<<6)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF5() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x40) >> 6
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF6(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x80)|value<<7)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF6() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x80) >> 7
}
func (o *DFSDM_FLT_Type) SetAWCFR_CLRAWLTF7(value uint32) {
	volatile.StoreUint32(&o.AWCFR.Reg, volatile.LoadUint32(&o.AWCFR.Reg)&^(0x100)|value<<8)
}
func (o *DFSDM_FLT_Type) GetAWCFR_CLRAWLTF7() uint32 {
	return (volatile.LoadUint32(&o.AWCFR.Reg) & 0x100) >> 8
}

// DFSDM_FLT.EXMAX: Extremes detector maximum register
func (o *DFSDM_FLT_Type) SetEXMAX(value uint32) {
	volatile.StoreUint32(&o.EXMAX.Reg, volatile.LoadUint32(&o.EXMAX.Reg)&^(0xffffff00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetEXMAX() uint32 {
	return (volatile.LoadUint32(&o.EXMAX.Reg) & 0xffffff00) >> 8
}
func (o *DFSDM_FLT_Type) SetEXMAX_EXMAXCH(value uint32) {
	volatile.StoreUint32(&o.EXMAX.Reg, volatile.LoadUint32(&o.EXMAX.Reg)&^(0x7)|value)
}
func (o *DFSDM_FLT_Type) GetEXMAX_EXMAXCH() uint32 {
	return volatile.LoadUint32(&o.EXMAX.Reg) & 0x7
}

// DFSDM_FLT.EXMIN: Extremes detector minimum register
func (o *DFSDM_FLT_Type) SetEXMIN(value uint32) {
	volatile.StoreUint32(&o.EXMIN.Reg, volatile.LoadUint32(&o.EXMIN.Reg)&^(0xffffff00)|value<<8)
}
func (o *DFSDM_FLT_Type) GetEXMIN() uint32 {
	return (volatile.LoadUint32(&o.EXMIN.Reg) & 0xffffff00) >> 8
}
func (o *DFSDM_FLT_Type) SetEXMIN_EXMINCH(value uint32) {
	volatile.StoreUint32(&o.EXMIN.Reg, volatile.LoadUint32(&o.EXMIN.Reg)&^(0x7)|value)
}
func (o *DFSDM_FLT_Type) GetEXMIN_EXMINCH() uint32 {
	return volatile.LoadUint32(&o.EXMIN.Reg) & 0x7
}

// DFSDM_FLT.CNVTIMR: conversion timer register
func (o *DFSDM_FLT_Type) SetCNVTIMR_CNVCNT(value uint32) {
	volatile.StoreUint32(&o.CNVTIMR.Reg, volatile.LoadUint32(&o.CNVTIMR.Reg)&^(0xfffffff0)|value<<4)
}
func (o *DFSDM_FLT_Type) GetCNVTIMR_CNVCNT() uint32 {
	return (volatile.LoadUint32(&o.CNVTIMR.Reg) & 0xfffffff0) >> 4
}

// Direct memory access controller
type DMA_Type struct {
	ISR  volatile.Register32 // 0x0
	IFCR volatile.Register32 // 0x4
	CH   [8]DMA_CH_Type      // 0x8
}

// DMA.ISR: interrupt status register
func (o *DMA_Type) SetISR_TEIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_Type) GetISR_TEIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *DMA_Type) SetISR_TEIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *DMA_Type) GetISR_TEIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *DMA_Type) SetISR_TEIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *DMA_Type) GetISR_TEIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *DMA_Type) SetISR_TEIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *DMA_Type) GetISR_TEIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *DMA_Type) SetISR_TEIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *DMA_Type) GetISR_TEIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *DMA_Type) SetISR_TEIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *DMA_Type) GetISR_TEIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *DMA_Type) SetISR_TEIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000000)|value<<31)
}
func (o *DMA_Type) GetISR_TEIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000000) >> 31
}
func (o *DMA_Type) SetISR_TEIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<35)
}
func (o *DMA_Type) GetISR_TEIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 35
}
func (o *DMA_Type) SetISR_HTIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_Type) GetISR_HTIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *DMA_Type) SetISR_HTIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *DMA_Type) GetISR_HTIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *DMA_Type) SetISR_HTIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_Type) GetISR_HTIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *DMA_Type) SetISR_HTIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *DMA_Type) GetISR_HTIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *DMA_Type) SetISR_HTIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *DMA_Type) GetISR_HTIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *DMA_Type) SetISR_HTIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *DMA_Type) GetISR_HTIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *DMA_Type) SetISR_HTIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000000)|value<<30)
}
func (o *DMA_Type) GetISR_HTIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000000) >> 30
}
func (o *DMA_Type) SetISR_HTIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<34)
}
func (o *DMA_Type) GetISR_HTIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 34
}
func (o *DMA_Type) SetISR_TCIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_Type) GetISR_TCIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *DMA_Type) SetISR_TCIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *DMA_Type) GetISR_TCIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *DMA_Type) SetISR_TCIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *DMA_Type) GetISR_TCIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *DMA_Type) SetISR_TCIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *DMA_Type) GetISR_TCIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *DMA_Type) SetISR_TCIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA_Type) GetISR_TCIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *DMA_Type) SetISR_TCIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *DMA_Type) GetISR_TCIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *DMA_Type) SetISR_TCIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000000)|value<<29)
}
func (o *DMA_Type) GetISR_TCIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000000) >> 29
}
func (o *DMA_Type) SetISR_TCIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<33)
}
func (o *DMA_Type) GetISR_TCIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 33
}
func (o *DMA_Type) SetISR_GIF1(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_Type) GetISR_GIF1() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *DMA_Type) SetISR_GIF2(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *DMA_Type) GetISR_GIF2() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *DMA_Type) SetISR_GIF3(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *DMA_Type) GetISR_GIF3() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *DMA_Type) SetISR_GIF4(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_Type) GetISR_GIF4() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *DMA_Type) SetISR_GIF5(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA_Type) GetISR_GIF5() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100000) >> 20
}
func (o *DMA_Type) SetISR_GIF6(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *DMA_Type) GetISR_GIF6() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *DMA_Type) SetISR_GIF7(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000000)|value<<28)
}
func (o *DMA_Type) GetISR_GIF7() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000000) >> 28
}
func (o *DMA_Type) SetISR_GIF8(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x0)|value<<32)
}
func (o *DMA_Type) GetISR_GIF8() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x0) >> 32
}

// DMA.IFCR: interrupt flag clear register
func (o *DMA_Type) SetIFCR_CTEIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_Type) GetIFCR_CTEIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80) >> 7
}
func (o *DMA_Type) SetIFCR_CTEIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x800)|value<<11)
}
func (o *DMA_Type) GetIFCR_CTEIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x800) >> 11
}
func (o *DMA_Type) SetIFCR_CTEIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8000)|value<<15)
}
func (o *DMA_Type) GetIFCR_CTEIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8000) >> 15
}
func (o *DMA_Type) SetIFCR_CTEIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80000)|value<<19)
}
func (o *DMA_Type) GetIFCR_CTEIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80000) >> 19
}
func (o *DMA_Type) SetIFCR_CTEIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x800000)|value<<23)
}
func (o *DMA_Type) GetIFCR_CTEIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x800000) >> 23
}
func (o *DMA_Type) SetIFCR_CTEIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x8000000)|value<<27)
}
func (o *DMA_Type) GetIFCR_CTEIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x8000000) >> 27
}
func (o *DMA_Type) SetIFCR_CTEIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x80000000)|value<<31)
}
func (o *DMA_Type) GetIFCR_CTEIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x80000000) >> 31
}
func (o *DMA_Type) SetIFCR_CTEIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<35)
}
func (o *DMA_Type) GetIFCR_CTEIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 35
}
func (o *DMA_Type) SetIFCR_CHTIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_Type) GetIFCR_CHTIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40) >> 6
}
func (o *DMA_Type) SetIFCR_CHTIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x400)|value<<10)
}
func (o *DMA_Type) GetIFCR_CHTIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x400) >> 10
}
func (o *DMA_Type) SetIFCR_CHTIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_Type) GetIFCR_CHTIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x4000) >> 14
}
func (o *DMA_Type) SetIFCR_CHTIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40000)|value<<18)
}
func (o *DMA_Type) GetIFCR_CHTIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40000) >> 18
}
func (o *DMA_Type) SetIFCR_CHTIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x400000)|value<<22)
}
func (o *DMA_Type) GetIFCR_CHTIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x400000) >> 22
}
func (o *DMA_Type) SetIFCR_CHTIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x4000000)|value<<26)
}
func (o *DMA_Type) GetIFCR_CHTIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x4000000) >> 26
}
func (o *DMA_Type) SetIFCR_CHTIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x40000000)|value<<30)
}
func (o *DMA_Type) GetIFCR_CHTIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x40000000) >> 30
}
func (o *DMA_Type) SetIFCR_CHTIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<34)
}
func (o *DMA_Type) GetIFCR_CHTIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 34
}
func (o *DMA_Type) SetIFCR_CTCIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_Type) GetIFCR_CTCIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20) >> 5
}
func (o *DMA_Type) SetIFCR_CTCIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x200)|value<<9)
}
func (o *DMA_Type) GetIFCR_CTCIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x200) >> 9
}
func (o *DMA_Type) SetIFCR_CTCIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x2000)|value<<13)
}
func (o *DMA_Type) GetIFCR_CTCIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x2000) >> 13
}
func (o *DMA_Type) SetIFCR_CTCIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20000)|value<<17)
}
func (o *DMA_Type) GetIFCR_CTCIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20000) >> 17
}
func (o *DMA_Type) SetIFCR_CTCIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x200000)|value<<21)
}
func (o *DMA_Type) GetIFCR_CTCIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x200000) >> 21
}
func (o *DMA_Type) SetIFCR_CTCIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x2000000)|value<<25)
}
func (o *DMA_Type) GetIFCR_CTCIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x2000000) >> 25
}
func (o *DMA_Type) SetIFCR_CTCIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x20000000)|value<<29)
}
func (o *DMA_Type) GetIFCR_CTCIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x20000000) >> 29
}
func (o *DMA_Type) SetIFCR_CTCIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<33)
}
func (o *DMA_Type) GetIFCR_CTCIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 33
}
func (o *DMA_Type) SetIFCR_CGIF1(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_Type) GetIFCR_CGIF1() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10) >> 4
}
func (o *DMA_Type) SetIFCR_CGIF2(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x100)|value<<8)
}
func (o *DMA_Type) GetIFCR_CGIF2() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x100) >> 8
}
func (o *DMA_Type) SetIFCR_CGIF3(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x1000)|value<<12)
}
func (o *DMA_Type) GetIFCR_CGIF3() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x1000) >> 12
}
func (o *DMA_Type) SetIFCR_CGIF4(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_Type) GetIFCR_CGIF4() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10000) >> 16
}
func (o *DMA_Type) SetIFCR_CGIF5(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA_Type) GetIFCR_CGIF5() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x100000) >> 20
}
func (o *DMA_Type) SetIFCR_CGIF6(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x1000000)|value<<24)
}
func (o *DMA_Type) GetIFCR_CGIF6() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x1000000) >> 24
}
func (o *DMA_Type) SetIFCR_CGIF7(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x10000000)|value<<28)
}
func (o *DMA_Type) GetIFCR_CGIF7() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x10000000) >> 28
}
func (o *DMA_Type) SetIFCR_CGIF8(value uint32) {
	volatile.StoreUint32(&o.IFCR.Reg, volatile.LoadUint32(&o.IFCR.Reg)&^(0x0)|value<<32)
}
func (o *DMA_Type) GetIFCR_CGIF8() uint32 {
	return (volatile.LoadUint32(&o.IFCR.Reg) & 0x0) >> 32
}

// Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR?, and CM1AR? registers
type DMA_CH_Type struct {
	CR   volatile.Register32 // 0x8
	NDTR volatile.Register32 // 0xC
	PAR  volatile.Register32 // 0x10
	M0AR volatile.Register32 // 0x14
	M1AR volatile.Register32 // 0x18
}

// DMA_CH.CR: channel x configuration register
func (o *DMA_CH_Type) SetCR_PRIV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *DMA_CH_Type) GetCR_PRIV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *DMA_CH_Type) SetCR_DSEC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *DMA_CH_Type) GetCR_DSEC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *DMA_CH_Type) SetCR_SSEC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *DMA_CH_Type) GetCR_SSEC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *DMA_CH_Type) SetCR_SECM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *DMA_CH_Type) GetCR_SECM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *DMA_CH_Type) SetCR_CT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *DMA_CH_Type) GetCR_CT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *DMA_CH_Type) SetCR_DBM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *DMA_CH_Type) GetCR_DBM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *DMA_CH_Type) SetCR_MEM2MEM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *DMA_CH_Type) GetCR_MEM2MEM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *DMA_CH_Type) SetCR_PL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3000)|value<<12)
}
func (o *DMA_CH_Type) GetCR_PL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3000) >> 12
}
func (o *DMA_CH_Type) SetCR_PSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x300)|value<<8)
}
func (o *DMA_CH_Type) GetCR_PSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x300) >> 8
}
func (o *DMA_CH_Type) SetCR_MSIZE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00)|value<<10)
}
func (o *DMA_CH_Type) GetCR_MSIZE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00) >> 10
}
func (o *DMA_CH_Type) SetCR_PINC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *DMA_CH_Type) GetCR_PINC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *DMA_CH_Type) SetCR_MINC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *DMA_CH_Type) GetCR_MINC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *DMA_CH_Type) SetCR_CIRC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *DMA_CH_Type) GetCR_CIRC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *DMA_CH_Type) SetCR_DIR(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *DMA_CH_Type) GetCR_DIR() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *DMA_CH_Type) SetCR_TEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *DMA_CH_Type) GetCR_TEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *DMA_CH_Type) SetCR_HTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *DMA_CH_Type) GetCR_HTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *DMA_CH_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *DMA_CH_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *DMA_CH_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *DMA_CH_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// DMA_CH.NDTR: channel x number of data register
func (o *DMA_CH_Type) SetNDTR_NDT(value uint32) {
	volatile.StoreUint32(&o.NDTR.Reg, volatile.LoadUint32(&o.NDTR.Reg)&^(0x3ffff)|value)
}
func (o *DMA_CH_Type) GetNDTR_NDT() uint32 {
	return volatile.LoadUint32(&o.NDTR.Reg) & 0x3ffff
}

// DMA_CH.PAR: channel x peripheral address register
func (o *DMA_CH_Type) SetPAR(value uint32) {
	volatile.StoreUint32(&o.PAR.Reg, value)
}
func (o *DMA_CH_Type) GetPAR() uint32 {
	return volatile.LoadUint32(&o.PAR.Reg)
}

// DMA_CH.M0AR: channel x memory address register
func (o *DMA_CH_Type) SetM0AR(value uint32) {
	volatile.StoreUint32(&o.M0AR.Reg, value)
}
func (o *DMA_CH_Type) GetM0AR() uint32 {
	return volatile.LoadUint32(&o.M0AR.Reg)
}

// DMA_CH.M1AR: channel x memory address register
func (o *DMA_CH_Type) SetM1AR(value uint32) {
	volatile.StoreUint32(&o.M1AR.Reg, value)
}
func (o *DMA_CH_Type) GetM1AR() uint32 {
	return volatile.LoadUint32(&o.M1AR.Reg)
}

// Direct memory access Multiplexer
type DMAMUX_Type struct {
	CCR0  volatile.Register32 // 0x0
	CCR1  volatile.Register32 // 0x4
	CCR2  volatile.Register32 // 0x8
	CCR3  volatile.Register32 // 0xC
	CCR4  volatile.Register32 // 0x10
	CCR5  volatile.Register32 // 0x14
	CCR6  volatile.Register32 // 0x18
	CCR7  volatile.Register32 // 0x1C
	CCR8  volatile.Register32 // 0x20
	CCR9  volatile.Register32 // 0x24
	CCR10 volatile.Register32 // 0x28
	CCR11 volatile.Register32 // 0x2C
	CCR12 volatile.Register32 // 0x30
	CCR13 volatile.Register32 // 0x34
	CCR14 volatile.Register32 // 0x38
	CCR15 volatile.Register32 // 0x3C
	_     [64]byte
	CSR   volatile.Register32 // 0x80
	CCFR  volatile.Register32 // 0x84
	_     [120]byte
	RGCR0 volatile.Register32 // 0x100
	RGCR1 volatile.Register32 // 0x104
	RGCR2 volatile.Register32 // 0x108
	RGCR3 volatile.Register32 // 0x10C
	_     [48]byte
	RGSR  volatile.Register32 // 0x140
	RGCFR volatile.Register32 // 0x144
}

// DMAMUX.CCR0: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR0_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR0_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR0_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR0_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR0_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR0_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR0_SE(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR0_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR0_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR0_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR0_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR0_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR0.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR0_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR0.Reg, volatile.LoadUint32(&o.CCR0.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR0_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR0.Reg) & 0x7f
}

// DMAMUX.CCR1: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR1_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR1_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR1_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR1_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR1_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR1_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR1_SE(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR1_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR1_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR1_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR1_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR1_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR1.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR1_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR1_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0x7f
}

// DMAMUX.CCR2: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR2_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR2_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR2_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR2_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR2_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR2_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR2_SE(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR2_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR2_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR2_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR2_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR2_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR2.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR2_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR2_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0x7f
}

// DMAMUX.CCR3: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR3_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR3_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR3_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR3_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR3_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR3_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR3_SE(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR3_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR3_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR3_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR3_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR3_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR3.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR3_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR3_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR3.Reg) & 0x7f
}

// DMAMUX.CCR4: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR4_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR4_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR4_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR4_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR4_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR4_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR4_SE(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR4_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR4_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR4_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR4_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR4_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR4.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR4_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR4_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR4.Reg) & 0x7f
}

// DMAMUX.CCR5: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR5_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR5_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR5_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR5_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR5_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR5_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR5_SE(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR5_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR5_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR5_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR5_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR5_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR5_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR5_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR5.Reg) & 0x7f
}

// DMAMUX.CCR6: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR6_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR6_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR6_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR6_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR6_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR6_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR6_SE(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR6_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR6_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR6_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR6_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR6_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR6.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR6_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR6_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR6.Reg) & 0x7f
}

// DMAMUX.CCR7: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR7_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR7_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR7_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR7_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR7_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR7_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR7_SE(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR7_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR7_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR7_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR7_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR7_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR7.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR7_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR7.Reg, volatile.LoadUint32(&o.CCR7.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR7_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR7.Reg) & 0x7f
}

// DMAMUX.CCR8: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR8_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR8_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR8_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR8_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR8_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR8_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR8_SE(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR8_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR8_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR8_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR8_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR8_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR8.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR8_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR8.Reg, volatile.LoadUint32(&o.CCR8.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR8_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR8.Reg) & 0x7f
}

// DMAMUX.CCR9: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR9_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR9_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR9_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR9_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR9_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR9_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR9_SE(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR9_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR9_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR9_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR9_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR9_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR9.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR9_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR9.Reg, volatile.LoadUint32(&o.CCR9.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR9_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR9.Reg) & 0x7f
}

// DMAMUX.CCR10: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR10_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR10_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR10_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR10_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR10_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR10_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR10_SE(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR10_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR10_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR10_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR10_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR10_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR10.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR10_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR10.Reg, volatile.LoadUint32(&o.CCR10.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR10_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR10.Reg) & 0x7f
}

// DMAMUX.CCR11: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR11_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR11_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR11_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR11_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR11_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR11_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR11_SE(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR11_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR11_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR11_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR11_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR11_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR11.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR11_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR11.Reg, volatile.LoadUint32(&o.CCR11.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR11_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR11.Reg) & 0x7f
}

// DMAMUX.CCR12: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR12_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR12.Reg, volatile.LoadUint32(&o.CCR12.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR12_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR12.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR12_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR12.Reg, volatile.LoadUint32(&o.CCR12.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR12_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR12.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR12_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR12.Reg, volatile.LoadUint32(&o.CCR12.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR12_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR12.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR12_SE(value uint32) {
	volatile.StoreUint32(&o.CCR12.Reg, volatile.LoadUint32(&o.CCR12.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR12_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR12.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR12_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR12.Reg, volatile.LoadUint32(&o.CCR12.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR12_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR12.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR12_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR12.Reg, volatile.LoadUint32(&o.CCR12.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR12_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR12.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR12_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR12.Reg, volatile.LoadUint32(&o.CCR12.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR12_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR12.Reg) & 0x7f
}

// DMAMUX.CCR13: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR13_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR13.Reg, volatile.LoadUint32(&o.CCR13.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR13_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR13.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR13_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR13.Reg, volatile.LoadUint32(&o.CCR13.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR13_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR13.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR13_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR13.Reg, volatile.LoadUint32(&o.CCR13.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR13_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR13.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR13_SE(value uint32) {
	volatile.StoreUint32(&o.CCR13.Reg, volatile.LoadUint32(&o.CCR13.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR13_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR13.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR13_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR13.Reg, volatile.LoadUint32(&o.CCR13.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR13_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR13.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR13_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR13.Reg, volatile.LoadUint32(&o.CCR13.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR13_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR13.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR13_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR13.Reg, volatile.LoadUint32(&o.CCR13.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR13_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR13.Reg) & 0x7f
}

// DMAMUX.CCR14: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR14_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR14.Reg, volatile.LoadUint32(&o.CCR14.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR14_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR14.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR14_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR14.Reg, volatile.LoadUint32(&o.CCR14.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR14_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR14.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR14_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR14.Reg, volatile.LoadUint32(&o.CCR14.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR14_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR14.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR14_SE(value uint32) {
	volatile.StoreUint32(&o.CCR14.Reg, volatile.LoadUint32(&o.CCR14.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR14_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR14.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR14_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR14.Reg, volatile.LoadUint32(&o.CCR14.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR14_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR14.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR14_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR14.Reg, volatile.LoadUint32(&o.CCR14.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR14_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR14.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR14_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR14.Reg, volatile.LoadUint32(&o.CCR14.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR14_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR14.Reg) & 0x7f
}

// DMAMUX.CCR15: DMA Multiplexer Channel %s Control register
func (o *DMAMUX_Type) SetCCR15_SYNC_ID(value uint32) {
	volatile.StoreUint32(&o.CCR15.Reg, volatile.LoadUint32(&o.CCR15.Reg)&^(0x1f000000)|value<<24)
}
func (o *DMAMUX_Type) GetCCR15_SYNC_ID() uint32 {
	return (volatile.LoadUint32(&o.CCR15.Reg) & 0x1f000000) >> 24
}
func (o *DMAMUX_Type) SetCCR15_NBREQ(value uint32) {
	volatile.StoreUint32(&o.CCR15.Reg, volatile.LoadUint32(&o.CCR15.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetCCR15_NBREQ() uint32 {
	return (volatile.LoadUint32(&o.CCR15.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetCCR15_SPOL(value uint32) {
	volatile.StoreUint32(&o.CCR15.Reg, volatile.LoadUint32(&o.CCR15.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetCCR15_SPOL() uint32 {
	return (volatile.LoadUint32(&o.CCR15.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetCCR15_SE(value uint32) {
	volatile.StoreUint32(&o.CCR15.Reg, volatile.LoadUint32(&o.CCR15.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCR15_SE() uint32 {
	return (volatile.LoadUint32(&o.CCR15.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetCCR15_EGE(value uint32) {
	volatile.StoreUint32(&o.CCR15.Reg, volatile.LoadUint32(&o.CCR15.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCR15_EGE() uint32 {
	return (volatile.LoadUint32(&o.CCR15.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCR15_SOIE(value uint32) {
	volatile.StoreUint32(&o.CCR15.Reg, volatile.LoadUint32(&o.CCR15.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCR15_SOIE() uint32 {
	return (volatile.LoadUint32(&o.CCR15.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCR15_DMAREQ_ID(value uint32) {
	volatile.StoreUint32(&o.CCR15.Reg, volatile.LoadUint32(&o.CCR15.Reg)&^(0x7f)|value)
}
func (o *DMAMUX_Type) GetCCR15_DMAREQ_ID() uint32 {
	return volatile.LoadUint32(&o.CCR15.Reg) & 0x7f
}

// DMAMUX.CSR: DMA Multiplexer Channel Status register
func (o *DMAMUX_Type) SetCSR_SOF0(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetCSR_SOF0() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetCSR_SOF1(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetCSR_SOF1() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetCSR_SOF2(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetCSR_SOF2() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetCSR_SOF3(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetCSR_SOF3() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10) >> 4
}
func (o *DMAMUX_Type) SetCSR_SOF4(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20)|value<<5)
}
func (o *DMAMUX_Type) GetCSR_SOF4() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20) >> 5
}
func (o *DMAMUX_Type) SetCSR_SOF5(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40)|value<<6)
}
func (o *DMAMUX_Type) GetCSR_SOF5() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40) >> 6
}
func (o *DMAMUX_Type) SetCSR_SOF6(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80)|value<<7)
}
func (o *DMAMUX_Type) GetCSR_SOF6() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80) >> 7
}
func (o *DMAMUX_Type) SetCSR_SOF7(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCSR_SOF7() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCSR_SOF8(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCSR_SOF8() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCSR_SOF9(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x400)|value<<10)
}
func (o *DMAMUX_Type) GetCSR_SOF9() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x400) >> 10
}
func (o *DMAMUX_Type) SetCSR_SOF10(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800)|value<<11)
}
func (o *DMAMUX_Type) GetCSR_SOF10() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800) >> 11
}
func (o *DMAMUX_Type) SetCSR_SOF11(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAMUX_Type) GetCSR_SOF11() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x1000) >> 12
}
func (o *DMAMUX_Type) SetCSR_SOF12(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2000)|value<<13)
}
func (o *DMAMUX_Type) GetCSR_SOF12() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2000) >> 13
}
func (o *DMAMUX_Type) SetCSR_SOF13(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4000)|value<<14)
}
func (o *DMAMUX_Type) GetCSR_SOF13() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4000) >> 14
}
func (o *DMAMUX_Type) SetCSR_SOF14(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8000)|value<<15)
}
func (o *DMAMUX_Type) GetCSR_SOF14() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8000) >> 15
}
func (o *DMAMUX_Type) SetCSR_SOF15(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCSR_SOF15() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10000) >> 16
}

// DMAMUX.CCFR: DMA Channel Clear Flag Register
func (o *DMAMUX_Type) SetCCFR_CSOF0(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetCCFR_CSOF0() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetCCFR_CSOF1(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetCCFR_CSOF1() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetCCFR_CSOF2(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetCCFR_CSOF2() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetCCFR_CSOF3(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetCCFR_CSOF3() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x10) >> 4
}
func (o *DMAMUX_Type) SetCCFR_CSOF4(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x20)|value<<5)
}
func (o *DMAMUX_Type) GetCCFR_CSOF4() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x20) >> 5
}
func (o *DMAMUX_Type) SetCCFR_CSOF5(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x40)|value<<6)
}
func (o *DMAMUX_Type) GetCCFR_CSOF5() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x40) >> 6
}
func (o *DMAMUX_Type) SetCCFR_CSOF6(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x80)|value<<7)
}
func (o *DMAMUX_Type) GetCCFR_CSOF6() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x80) >> 7
}
func (o *DMAMUX_Type) SetCCFR_CSOF7(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetCCFR_CSOF7() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetCCFR_CSOF8(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x200)|value<<9)
}
func (o *DMAMUX_Type) GetCCFR_CSOF8() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x200) >> 9
}
func (o *DMAMUX_Type) SetCCFR_CSOF9(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x400)|value<<10)
}
func (o *DMAMUX_Type) GetCCFR_CSOF9() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x400) >> 10
}
func (o *DMAMUX_Type) SetCCFR_CSOF10(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x800)|value<<11)
}
func (o *DMAMUX_Type) GetCCFR_CSOF10() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x800) >> 11
}
func (o *DMAMUX_Type) SetCCFR_CSOF11(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x1000)|value<<12)
}
func (o *DMAMUX_Type) GetCCFR_CSOF11() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x1000) >> 12
}
func (o *DMAMUX_Type) SetCCFR_CSOF12(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x2000)|value<<13)
}
func (o *DMAMUX_Type) GetCCFR_CSOF12() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x2000) >> 13
}
func (o *DMAMUX_Type) SetCCFR_CSOF13(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x4000)|value<<14)
}
func (o *DMAMUX_Type) GetCCFR_CSOF13() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x4000) >> 14
}
func (o *DMAMUX_Type) SetCCFR_CSOF14(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x8000)|value<<15)
}
func (o *DMAMUX_Type) GetCCFR_CSOF14() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x8000) >> 15
}
func (o *DMAMUX_Type) SetCCFR_CSOF15(value uint32) {
	volatile.StoreUint32(&o.CCFR.Reg, volatile.LoadUint32(&o.CCFR.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetCCFR_CSOF15() uint32 {
	return (volatile.LoadUint32(&o.CCFR.Reg) & 0x10000) >> 16
}

// DMAMUX.RGCR0: DMA Request Generator %s Control Register
func (o *DMAMUX_Type) SetRGCR0_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR0_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetRGCR0_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR0_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR0_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR0_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR0_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR0_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR0.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR0_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR0.Reg, volatile.LoadUint32(&o.RGCR0.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR0_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR0.Reg) & 0x1f
}

// DMAMUX.RGCR1: DMA Request Generator %s Control Register
func (o *DMAMUX_Type) SetRGCR1_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR1_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetRGCR1_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR1_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR1_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR1_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR1_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR1_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR1.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR1_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR1.Reg, volatile.LoadUint32(&o.RGCR1.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR1_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR1.Reg) & 0x1f
}

// DMAMUX.RGCR2: DMA Request Generator %s Control Register
func (o *DMAMUX_Type) SetRGCR2_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR2_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetRGCR2_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR2_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR2_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR2_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR2_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR2_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR2.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR2_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR2.Reg, volatile.LoadUint32(&o.RGCR2.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR2_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR2.Reg) & 0x1f
}

// DMAMUX.RGCR3: DMA Request Generator %s Control Register
func (o *DMAMUX_Type) SetRGCR3_GNBREQ(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0xf80000)|value<<19)
}
func (o *DMAMUX_Type) GetRGCR3_GNBREQ() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0xf80000) >> 19
}
func (o *DMAMUX_Type) SetRGCR3_GPOL(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x60000)|value<<17)
}
func (o *DMAMUX_Type) GetRGCR3_GPOL() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0x60000) >> 17
}
func (o *DMAMUX_Type) SetRGCR3_GE(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x10000)|value<<16)
}
func (o *DMAMUX_Type) GetRGCR3_GE() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0x10000) >> 16
}
func (o *DMAMUX_Type) SetRGCR3_OIE(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x100)|value<<8)
}
func (o *DMAMUX_Type) GetRGCR3_OIE() uint32 {
	return (volatile.LoadUint32(&o.RGCR3.Reg) & 0x100) >> 8
}
func (o *DMAMUX_Type) SetRGCR3_SIG_ID(value uint32) {
	volatile.StoreUint32(&o.RGCR3.Reg, volatile.LoadUint32(&o.RGCR3.Reg)&^(0x1f)|value)
}
func (o *DMAMUX_Type) GetRGCR3_SIG_ID() uint32 {
	return volatile.LoadUint32(&o.RGCR3.Reg) & 0x1f
}

// DMAMUX.RGSR: DMA Request Generator Status Register
func (o *DMAMUX_Type) SetRGSR_OF0(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetRGSR_OF0() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetRGSR_OF1(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetRGSR_OF1() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetRGSR_OF2(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetRGSR_OF2() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetRGSR_OF3(value uint32) {
	volatile.StoreUint32(&o.RGSR.Reg, volatile.LoadUint32(&o.RGSR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetRGSR_OF3() uint32 {
	return (volatile.LoadUint32(&o.RGSR.Reg) & 0x10) >> 4
}

// DMAMUX.RGCFR: DMA Request Generator Clear Flag Register
func (o *DMAMUX_Type) SetRGCFR_COF0(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x2)|value<<1)
}
func (o *DMAMUX_Type) GetRGCFR_COF0() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x2) >> 1
}
func (o *DMAMUX_Type) SetRGCFR_COF1(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x4)|value<<2)
}
func (o *DMAMUX_Type) GetRGCFR_COF1() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x4) >> 2
}
func (o *DMAMUX_Type) SetRGCFR_COF2(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x8)|value<<3)
}
func (o *DMAMUX_Type) GetRGCFR_COF2() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x8) >> 3
}
func (o *DMAMUX_Type) SetRGCFR_COF3(value uint32) {
	volatile.StoreUint32(&o.RGCFR.Reg, volatile.LoadUint32(&o.RGCFR.Reg)&^(0x10)|value<<4)
}
func (o *DMAMUX_Type) GetRGCFR_COF3() uint32 {
	return (volatile.LoadUint32(&o.RGCFR.Reg) & 0x10) >> 4
}

// External interrupt/event controller
type EXTI_Type struct {
	RTSR1     volatile.Register32 // 0x0
	FTSR1     volatile.Register32 // 0x4
	SWIER1    volatile.Register32 // 0x8
	RPR1      volatile.Register32 // 0xC
	FPR1      volatile.Register32 // 0x10
	SECCFGR1  volatile.Register32 // 0x14
	PRIVCFGR1 volatile.Register32 // 0x18
	_         [4]byte
	RTSR2     volatile.Register32 // 0x20
	FTSR2     volatile.Register32 // 0x24
	SWIER2    volatile.Register32 // 0x28
	RPR2      volatile.Register32 // 0x2C
	FPR2      volatile.Register32 // 0x30
	PRIVCFGR2 volatile.Register32 // 0x34
	SECCFGR2  volatile.Register32 // 0x38
	_         [36]byte
	EXTICR1   volatile.Register32 // 0x60
	EXTICR2   volatile.Register32 // 0x64
	EXTICR3   volatile.Register32 // 0x68
	EXTICR4   volatile.Register32 // 0x6C
	LOCKRG    volatile.Register32 // 0x70
	_         [12]byte
	IMR1      volatile.Register32 // 0x80
	EMR1      volatile.Register32 // 0x84
	_         [8]byte
	IMR2      volatile.Register32 // 0x90
	EMR2      volatile.Register32 // 0x94
}

// EXTI.RTSR1: EXTI rising trigger selection register
func (o *EXTI_Type) SetRTSR1_RT0(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetRTSR1_RT0() uint32 {
	return volatile.LoadUint32(&o.RTSR1.Reg) & 0x1
}
func (o *EXTI_Type) SetRTSR1_RT1(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetRTSR1_RT1() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetRTSR1_RT2(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetRTSR1_RT2() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetRTSR1_RT3(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRTSR1_RT3() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRTSR1_RT4(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRTSR1_RT4() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRTSR1_RT5(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRTSR1_RT5() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRTSR1_RT6(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRTSR1_RT6() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetRTSR1_RT7(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetRTSR1_RT7() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetRTSR1_RT8(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetRTSR1_RT8() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetRTSR1_RT9(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetRTSR1_RT9() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetRTSR1_RT10(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetRTSR1_RT10() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetRTSR1_RT11(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetRTSR1_RT11() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetRTSR1_RT12(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetRTSR1_RT12() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetRTSR1_RT13(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetRTSR1_RT13() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetRTSR1_RT14(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetRTSR1_RT14() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetRTSR1_RT15(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetRTSR1_RT15() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetRTSR1_RT16(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetRTSR1_RT16() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetRTSR1_RT21(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetRTSR1_RT21() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetRTSR1_RT22(value uint32) {
	volatile.StoreUint32(&o.RTSR1.Reg, volatile.LoadUint32(&o.RTSR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetRTSR1_RT22() uint32 {
	return (volatile.LoadUint32(&o.RTSR1.Reg) & 0x400000) >> 22
}

// EXTI.FTSR1: EXTI falling trigger selection register
func (o *EXTI_Type) SetFTSR1_FT0(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetFTSR1_FT0() uint32 {
	return volatile.LoadUint32(&o.FTSR1.Reg) & 0x1
}
func (o *EXTI_Type) SetFTSR1_FT1(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetFTSR1_FT1() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetFTSR1_FT2(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetFTSR1_FT2() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetFTSR1_FT3(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFTSR1_FT3() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFTSR1_FT4(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFTSR1_FT4() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFTSR1_FT5(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFTSR1_FT5() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFTSR1_FT6(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFTSR1_FT6() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetFTSR1_FT7(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetFTSR1_FT7() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetFTSR1_FT8(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetFTSR1_FT8() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetFTSR1_FT9(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetFTSR1_FT9() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetFTSR1_FT10(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetFTSR1_FT10() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetFTSR1_FT11(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetFTSR1_FT11() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetFTSR1_FT12(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetFTSR1_FT12() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetFTSR1_FT13(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetFTSR1_FT13() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetFTSR1_FT14(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetFTSR1_FT14() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetFTSR1_FT15(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetFTSR1_FT15() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetFTSR1_FT16(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetFTSR1_FT16() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetFTSR1_FT21(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetFTSR1_FT21() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetFTSR1_FT22(value uint32) {
	volatile.StoreUint32(&o.FTSR1.Reg, volatile.LoadUint32(&o.FTSR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetFTSR1_FT22() uint32 {
	return (volatile.LoadUint32(&o.FTSR1.Reg) & 0x400000) >> 22
}

// EXTI.SWIER1: EXTI software interrupt event register
func (o *EXTI_Type) SetSWIER1_SWI0(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetSWIER1_SWI0() uint32 {
	return volatile.LoadUint32(&o.SWIER1.Reg) & 0x1
}
func (o *EXTI_Type) SetSWIER1_SWI1(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetSWIER1_SWI1() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetSWIER1_SWI2(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetSWIER1_SWI2() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetSWIER1_SWI3(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetSWIER1_SWI3() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetSWIER1_SWI4(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetSWIER1_SWI4() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetSWIER1_SWI5(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetSWIER1_SWI5() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetSWIER1_SWI6(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetSWIER1_SWI6() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetSWIER1_SWI7(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetSWIER1_SWI7() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetSWIER1_SWI8(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetSWIER1_SWI8() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetSWIER1_SWI9(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetSWIER1_SWI9() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetSWIER1_SWI10(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetSWIER1_SWI10() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetSWIER1_SWI11(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetSWIER1_SWI11() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetSWIER1_SWI12(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetSWIER1_SWI12() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetSWIER1_SWI13(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetSWIER1_SWI13() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetSWIER1_SWI14(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetSWIER1_SWI14() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetSWIER1_SWI15(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetSWIER1_SWI15() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetSWIER1_SWI16(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetSWIER1_SWI16() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetSWIER1_SWI21(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetSWIER1_SWI21() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetSWIER1_SWI22(value uint32) {
	volatile.StoreUint32(&o.SWIER1.Reg, volatile.LoadUint32(&o.SWIER1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetSWIER1_SWI22() uint32 {
	return (volatile.LoadUint32(&o.SWIER1.Reg) & 0x400000) >> 22
}

// EXTI.RPR1: EXTI rising edge pending register
func (o *EXTI_Type) SetRPR1_RPIF0(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetRPR1_RPIF0() uint32 {
	return volatile.LoadUint32(&o.RPR1.Reg) & 0x1
}
func (o *EXTI_Type) SetRPR1_RPIF1(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetRPR1_RPIF1() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetRPR1_RPIF2(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetRPR1_RPIF2() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetRPR1_RPIF3(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRPR1_RPIF3() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRPR1_RPIF4(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRPR1_RPIF4() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRPR1_RPIF5(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRPR1_RPIF5() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRPR1_RPIF6(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRPR1_RPIF6() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetRPR1_RPIF7(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetRPR1_RPIF7() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetRPR1_RPIF8(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetRPR1_RPIF8() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetRPR1_RPIF9(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetRPR1_RPIF9() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetRPR1_RPIF10(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetRPR1_RPIF10() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetRPR1_RPIF11(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetRPR1_RPIF11() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetRPR1_RPIF12(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetRPR1_RPIF12() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetRPR1_RPIF13(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetRPR1_RPIF13() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetRPR1_RPIF14(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetRPR1_RPIF14() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetRPR1_RPIF15(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetRPR1_RPIF15() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetRPR1_RPIF16(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetRPR1_RPIF16() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetRPR1_RPIF21(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetRPR1_RPIF21() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetRPR1_RPIF22(value uint32) {
	volatile.StoreUint32(&o.RPR1.Reg, volatile.LoadUint32(&o.RPR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetRPR1_RPIF22() uint32 {
	return (volatile.LoadUint32(&o.RPR1.Reg) & 0x400000) >> 22
}

// EXTI.FPR1: EXTI falling edge pending register
func (o *EXTI_Type) SetFPR1_FPIF0(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetFPR1_FPIF0() uint32 {
	return volatile.LoadUint32(&o.FPR1.Reg) & 0x1
}
func (o *EXTI_Type) SetFPR1_FPIF1(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetFPR1_FPIF1() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetFPR1_FPIF2(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetFPR1_FPIF2() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetFPR1_FPIF3(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFPR1_FPIF3() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFPR1_FPIF4(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFPR1_FPIF4() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFPR1_FPIF5(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFPR1_FPIF5() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFPR1_FPIF6(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFPR1_FPIF6() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetFPR1_FPIF7(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetFPR1_FPIF7() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetFPR1_FPIF8(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetFPR1_FPIF8() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetFPR1_FPIF9(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetFPR1_FPIF9() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetFPR1_FPIF10(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetFPR1_FPIF10() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetFPR1_FPIF11(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetFPR1_FPIF11() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetFPR1_FPIF12(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetFPR1_FPIF12() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetFPR1_FPIF13(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetFPR1_FPIF13() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetFPR1_FPIF14(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetFPR1_FPIF14() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetFPR1_FPIF15(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetFPR1_FPIF15() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetFPR1_FPIF16(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetFPR1_FPIF16() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetFPR1_FPIF21(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetFPR1_FPIF21() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetFPR1_FPIF22(value uint32) {
	volatile.StoreUint32(&o.FPR1.Reg, volatile.LoadUint32(&o.FPR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetFPR1_FPIF22() uint32 {
	return (volatile.LoadUint32(&o.FPR1.Reg) & 0x400000) >> 22
}

// EXTI.SECCFGR1: EXTI security configuration register
func (o *EXTI_Type) SetSECCFGR1_SEC0(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetSECCFGR1_SEC0() uint32 {
	return volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x1
}
func (o *EXTI_Type) SetSECCFGR1_SEC1(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetSECCFGR1_SEC1() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetSECCFGR1_SEC2(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetSECCFGR1_SEC2() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetSECCFGR1_SEC3(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetSECCFGR1_SEC3() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetSECCFGR1_SEC4(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetSECCFGR1_SEC4() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetSECCFGR1_SEC5(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetSECCFGR1_SEC5() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetSECCFGR1_SEC6(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetSECCFGR1_SEC6() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetSECCFGR1_SEC7(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetSECCFGR1_SEC7() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetSECCFGR1_SEC8(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetSECCFGR1_SEC8() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetSECCFGR1_SEC9(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetSECCFGR1_SEC9() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetSECCFGR1_SEC10(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetSECCFGR1_SEC10() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetSECCFGR1_SEC11(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetSECCFGR1_SEC11() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetSECCFGR1_SEC12(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetSECCFGR1_SEC12() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetSECCFGR1_SEC13(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetSECCFGR1_SEC13() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetSECCFGR1_SEC14(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetSECCFGR1_SEC14() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetSECCFGR1_SEC15(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetSECCFGR1_SEC15() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetSECCFGR1_SEC16(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetSECCFGR1_SEC16() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetSECCFGR1_SEC17(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetSECCFGR1_SEC17() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetSECCFGR1_SEC18(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetSECCFGR1_SEC18() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetSECCFGR1_SEC19(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetSECCFGR1_SEC19() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetSECCFGR1_SEC20(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetSECCFGR1_SEC20() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetSECCFGR1_SEC21(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetSECCFGR1_SEC21() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetSECCFGR1_SEC22(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetSECCFGR1_SEC22() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetSECCFGR1_SEC23(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetSECCFGR1_SEC23() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetSECCFGR1_SEC24(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetSECCFGR1_SEC24() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetSECCFGR1_SEC25(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetSECCFGR1_SEC25() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x2000000) >> 25
}
func (o *EXTI_Type) SetSECCFGR1_SEC26(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x4000000)|value<<26)
}
func (o *EXTI_Type) GetSECCFGR1_SEC26() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x4000000) >> 26
}
func (o *EXTI_Type) SetSECCFGR1_SEC27(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x8000000)|value<<27)
}
func (o *EXTI_Type) GetSECCFGR1_SEC27() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x8000000) >> 27
}
func (o *EXTI_Type) SetSECCFGR1_SEC28(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x10000000)|value<<28)
}
func (o *EXTI_Type) GetSECCFGR1_SEC28() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x10000000) >> 28
}
func (o *EXTI_Type) SetSECCFGR1_SEC29(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x20000000)|value<<29)
}
func (o *EXTI_Type) GetSECCFGR1_SEC29() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x20000000) >> 29
}
func (o *EXTI_Type) SetSECCFGR1_SEC30(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x40000000)|value<<30)
}
func (o *EXTI_Type) GetSECCFGR1_SEC30() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x40000000) >> 30
}
func (o *EXTI_Type) SetSECCFGR1_SEC31(value uint32) {
	volatile.StoreUint32(&o.SECCFGR1.Reg, volatile.LoadUint32(&o.SECCFGR1.Reg)&^(0x80000000)|value<<31)
}
func (o *EXTI_Type) GetSECCFGR1_SEC31() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR1.Reg) & 0x80000000) >> 31
}

// EXTI.PRIVCFGR1: EXTI privilege configuration register
func (o *EXTI_Type) SetPRIVCFGR1_PRIV0(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV0() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x1
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV1(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV1() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV2(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV2() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV3(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV3() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV4(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV4() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV5(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV5() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV6(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV6() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV7(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV7() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV8(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV8() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV9(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV9() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV10(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV10() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV11(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV11() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV12(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV12() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV13(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV13() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV14(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV14() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV15(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV15() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV16(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV16() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV17(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV17() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV18(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV18() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV19(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV19() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV20(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV20() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV21(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV21() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV22(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV22() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV23(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV23() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV24(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV24() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV25(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV25() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x2000000) >> 25
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV26(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x4000000)|value<<26)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV26() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x4000000) >> 26
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV27(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x8000000)|value<<27)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV27() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x8000000) >> 27
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV28(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x10000000)|value<<28)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV28() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x10000000) >> 28
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV29(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x20000000)|value<<29)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV29() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x20000000) >> 29
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV30(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x40000000)|value<<30)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV30() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x40000000) >> 30
}
func (o *EXTI_Type) SetPRIVCFGR1_PRIV31(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR1.Reg, volatile.LoadUint32(&o.PRIVCFGR1.Reg)&^(0x80000000)|value<<31)
}
func (o *EXTI_Type) GetPRIVCFGR1_PRIV31() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR1.Reg) & 0x80000000) >> 31
}

// EXTI.RTSR2: EXTI rising trigger selection register
func (o *EXTI_Type) SetRTSR2_RT35(value uint32) {
	volatile.StoreUint32(&o.RTSR2.Reg, volatile.LoadUint32(&o.RTSR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRTSR2_RT35() uint32 {
	return (volatile.LoadUint32(&o.RTSR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRTSR2_RT36(value uint32) {
	volatile.StoreUint32(&o.RTSR2.Reg, volatile.LoadUint32(&o.RTSR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRTSR2_RT36() uint32 {
	return (volatile.LoadUint32(&o.RTSR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRTSR2_RT37(value uint32) {
	volatile.StoreUint32(&o.RTSR2.Reg, volatile.LoadUint32(&o.RTSR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRTSR2_RT37() uint32 {
	return (volatile.LoadUint32(&o.RTSR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRTSR2_RT38(value uint32) {
	volatile.StoreUint32(&o.RTSR2.Reg, volatile.LoadUint32(&o.RTSR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRTSR2_RT38() uint32 {
	return (volatile.LoadUint32(&o.RTSR2.Reg) & 0x40) >> 6
}

// EXTI.FTSR2: EXTI falling trigger selection register
func (o *EXTI_Type) SetFTSR2_FT35(value uint32) {
	volatile.StoreUint32(&o.FTSR2.Reg, volatile.LoadUint32(&o.FTSR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFTSR2_FT35() uint32 {
	return (volatile.LoadUint32(&o.FTSR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFTSR2_FT36(value uint32) {
	volatile.StoreUint32(&o.FTSR2.Reg, volatile.LoadUint32(&o.FTSR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFTSR2_FT36() uint32 {
	return (volatile.LoadUint32(&o.FTSR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFTSR2_FT37(value uint32) {
	volatile.StoreUint32(&o.FTSR2.Reg, volatile.LoadUint32(&o.FTSR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFTSR2_FT37() uint32 {
	return (volatile.LoadUint32(&o.FTSR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFTSR2_FT38(value uint32) {
	volatile.StoreUint32(&o.FTSR2.Reg, volatile.LoadUint32(&o.FTSR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFTSR2_FT38() uint32 {
	return (volatile.LoadUint32(&o.FTSR2.Reg) & 0x40) >> 6
}

// EXTI.SWIER2: EXTI software interrupt event register
func (o *EXTI_Type) SetSWIER2_SWI35(value uint32) {
	volatile.StoreUint32(&o.SWIER2.Reg, volatile.LoadUint32(&o.SWIER2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetSWIER2_SWI35() uint32 {
	return (volatile.LoadUint32(&o.SWIER2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetSWIER2_SWI36(value uint32) {
	volatile.StoreUint32(&o.SWIER2.Reg, volatile.LoadUint32(&o.SWIER2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetSWIER2_SWI36() uint32 {
	return (volatile.LoadUint32(&o.SWIER2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetSWIER2_SWI37(value uint32) {
	volatile.StoreUint32(&o.SWIER2.Reg, volatile.LoadUint32(&o.SWIER2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetSWIER2_SWI37() uint32 {
	return (volatile.LoadUint32(&o.SWIER2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetSWIER2_SWI38(value uint32) {
	volatile.StoreUint32(&o.SWIER2.Reg, volatile.LoadUint32(&o.SWIER2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetSWIER2_SWI38() uint32 {
	return (volatile.LoadUint32(&o.SWIER2.Reg) & 0x40) >> 6
}

// EXTI.RPR2: EXTI rising edge pending register
func (o *EXTI_Type) SetRPR2_RPIF35(value uint32) {
	volatile.StoreUint32(&o.RPR2.Reg, volatile.LoadUint32(&o.RPR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetRPR2_RPIF35() uint32 {
	return (volatile.LoadUint32(&o.RPR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetRPR2_RPIF36(value uint32) {
	volatile.StoreUint32(&o.RPR2.Reg, volatile.LoadUint32(&o.RPR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetRPR2_RPIF36() uint32 {
	return (volatile.LoadUint32(&o.RPR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetRPR2_RPIF37(value uint32) {
	volatile.StoreUint32(&o.RPR2.Reg, volatile.LoadUint32(&o.RPR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetRPR2_RPIF37() uint32 {
	return (volatile.LoadUint32(&o.RPR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetRPR2_RPIF38(value uint32) {
	volatile.StoreUint32(&o.RPR2.Reg, volatile.LoadUint32(&o.RPR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetRPR2_RPIF38() uint32 {
	return (volatile.LoadUint32(&o.RPR2.Reg) & 0x40) >> 6
}

// EXTI.FPR2: EXTI falling edge pending register
func (o *EXTI_Type) SetFPR2_FPIF35(value uint32) {
	volatile.StoreUint32(&o.FPR2.Reg, volatile.LoadUint32(&o.FPR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetFPR2_FPIF35() uint32 {
	return (volatile.LoadUint32(&o.FPR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetFPR2_FPIF36(value uint32) {
	volatile.StoreUint32(&o.FPR2.Reg, volatile.LoadUint32(&o.FPR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetFPR2_FPIF36() uint32 {
	return (volatile.LoadUint32(&o.FPR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetFPR2_FPIF37(value uint32) {
	volatile.StoreUint32(&o.FPR2.Reg, volatile.LoadUint32(&o.FPR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetFPR2_FPIF37() uint32 {
	return (volatile.LoadUint32(&o.FPR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetFPR2_FPIF38(value uint32) {
	volatile.StoreUint32(&o.FPR2.Reg, volatile.LoadUint32(&o.FPR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetFPR2_FPIF38() uint32 {
	return (volatile.LoadUint32(&o.FPR2.Reg) & 0x40) >> 6
}

// EXTI.PRIVCFGR2: EXTI security enable register
func (o *EXTI_Type) SetPRIVCFGR2_PRIV32(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV32() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x1
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV33(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV33() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV34(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV34() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV35(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV35() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV36(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV36() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV37(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV37() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV38(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV38() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV39(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV39() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV40(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV40() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV41(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV41() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetPRIVCFGR2_PRIV42(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR2.Reg, volatile.LoadUint32(&o.PRIVCFGR2.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetPRIVCFGR2_PRIV42() uint32 {
	return (volatile.LoadUint32(&o.PRIVCFGR2.Reg) & 0x400) >> 10
}

// EXTI.SECCFGR2: EXTI security enable register
func (o *EXTI_Type) SetSECCFGR2_SEC32(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetSECCFGR2_SEC32() uint32 {
	return volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x1
}
func (o *EXTI_Type) SetSECCFGR2_SEC33(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetSECCFGR2_SEC33() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetSECCFGR2_SEC34(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetSECCFGR2_SEC34() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetSECCFGR2_SEC35(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetSECCFGR2_SEC35() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetSECCFGR2_SEC36(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetSECCFGR2_SEC36() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetSECCFGR2_SEC37(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetSECCFGR2_SEC37() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetSECCFGR2_SEC38(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetSECCFGR2_SEC38() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetSECCFGR2_SEC39(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetSECCFGR2_SEC39() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetSECCFGR2_SEC40(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetSECCFGR2_SEC40() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetSECCFGR2_SEC41(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetSECCFGR2_SEC41() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetSECCFGR2_SEC42(value uint32) {
	volatile.StoreUint32(&o.SECCFGR2.Reg, volatile.LoadUint32(&o.SECCFGR2.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetSECCFGR2_SEC42() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR2.Reg) & 0x400) >> 10
}

// EXTI.EXTICR1: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR1_EXTI0(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR1_EXTI0() uint32 {
	return volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR1_EXTI1(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR1_EXTI1() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR1_EXTI2(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR1_EXTI2() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR1_EXTI3(value uint32) {
	volatile.StoreUint32(&o.EXTICR1.Reg, volatile.LoadUint32(&o.EXTICR1.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR1_EXTI3() uint32 {
	return (volatile.LoadUint32(&o.EXTICR1.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR2: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR2_EXTI4(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR2_EXTI4() uint32 {
	return volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR2_EXTI5(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR2_EXTI5() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR2_EXTI6(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR2_EXTI6() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR2_EXTI7(value uint32) {
	volatile.StoreUint32(&o.EXTICR2.Reg, volatile.LoadUint32(&o.EXTICR2.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR2_EXTI7() uint32 {
	return (volatile.LoadUint32(&o.EXTICR2.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR3: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR3_EXTI8(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR3_EXTI8() uint32 {
	return volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR3_EXTI9(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR3_EXTI9() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR3_EXTI10(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR3_EXTI10() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR3_EXTI11(value uint32) {
	volatile.StoreUint32(&o.EXTICR3.Reg, volatile.LoadUint32(&o.EXTICR3.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR3_EXTI11() uint32 {
	return (volatile.LoadUint32(&o.EXTICR3.Reg) & 0xff000000) >> 24
}

// EXTI.EXTICR4: EXTI external interrupt selection register
func (o *EXTI_Type) SetEXTICR4_EXTI12(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff)|value)
}
func (o *EXTI_Type) GetEXTICR4_EXTI12() uint32 {
	return volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff
}
func (o *EXTI_Type) SetEXTICR4_EXTI13(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff00)|value<<8)
}
func (o *EXTI_Type) GetEXTICR4_EXTI13() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff00) >> 8
}
func (o *EXTI_Type) SetEXTICR4_EXTI14(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff0000)|value<<16)
}
func (o *EXTI_Type) GetEXTICR4_EXTI14() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff0000) >> 16
}
func (o *EXTI_Type) SetEXTICR4_EXTI15(value uint32) {
	volatile.StoreUint32(&o.EXTICR4.Reg, volatile.LoadUint32(&o.EXTICR4.Reg)&^(0xff000000)|value<<24)
}
func (o *EXTI_Type) GetEXTICR4_EXTI15() uint32 {
	return (volatile.LoadUint32(&o.EXTICR4.Reg) & 0xff000000) >> 24
}

// EXTI.LOCKRG: EXTI lock register
func (o *EXTI_Type) SetLOCKRG_LOCK(value uint32) {
	volatile.StoreUint32(&o.LOCKRG.Reg, volatile.LoadUint32(&o.LOCKRG.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetLOCKRG_LOCK() uint32 {
	return volatile.LoadUint32(&o.LOCKRG.Reg) & 0x1
}

// EXTI.IMR1: EXTI CPU wakeup with interrupt mask register
func (o *EXTI_Type) SetIMR1_IM0(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetIMR1_IM0() uint32 {
	return volatile.LoadUint32(&o.IMR1.Reg) & 0x1
}
func (o *EXTI_Type) SetIMR1_IM1(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetIMR1_IM1() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetIMR1_IM2(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetIMR1_IM2() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetIMR1_IM3(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetIMR1_IM3() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetIMR1_IM4(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetIMR1_IM4() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetIMR1_IM5(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetIMR1_IM5() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetIMR1_IM6(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetIMR1_IM6() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetIMR1_IM7(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetIMR1_IM7() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetIMR1_IM8(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetIMR1_IM8() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetIMR1_IM9(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetIMR1_IM9() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetIMR1_IM10(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetIMR1_IM10() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetIMR1_IM11(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetIMR1_IM11() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetIMR1_IM12(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetIMR1_IM12() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetIMR1_IM13(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetIMR1_IM13() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetIMR1_IM14(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetIMR1_IM14() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetIMR1_IM15(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetIMR1_IM15() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetIMR1_IM16(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetIMR1_IM16() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetIMR1_IM17(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetIMR1_IM17() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetIMR1_IM18(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetIMR1_IM18() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetIMR1_IM19(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetIMR1_IM19() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetIMR1_IM20(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetIMR1_IM20() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetIMR1_IM21(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetIMR1_IM21() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetIMR1_IM22(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetIMR1_IM22() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetIMR1_IM23(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetIMR1_IM23() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetIMR1_IM24(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetIMR1_IM24() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetIMR1_IM25(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetIMR1_IM25() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x2000000) >> 25
}
func (o *EXTI_Type) SetIMR1_IM26(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x4000000)|value<<26)
}
func (o *EXTI_Type) GetIMR1_IM26() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x4000000) >> 26
}
func (o *EXTI_Type) SetIMR1_IM27(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x8000000)|value<<27)
}
func (o *EXTI_Type) GetIMR1_IM27() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x8000000) >> 27
}
func (o *EXTI_Type) SetIMR1_IM28(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x10000000)|value<<28)
}
func (o *EXTI_Type) GetIMR1_IM28() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x10000000) >> 28
}
func (o *EXTI_Type) SetIMR1_IM29(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x20000000)|value<<29)
}
func (o *EXTI_Type) GetIMR1_IM29() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x20000000) >> 29
}
func (o *EXTI_Type) SetIMR1_IM30(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x40000000)|value<<30)
}
func (o *EXTI_Type) GetIMR1_IM30() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x40000000) >> 30
}
func (o *EXTI_Type) SetIMR1_IM31(value uint32) {
	volatile.StoreUint32(&o.IMR1.Reg, volatile.LoadUint32(&o.IMR1.Reg)&^(0x80000000)|value<<31)
}
func (o *EXTI_Type) GetIMR1_IM31() uint32 {
	return (volatile.LoadUint32(&o.IMR1.Reg) & 0x80000000) >> 31
}

// EXTI.EMR1: EXTI CPU wakeup with event mask register
func (o *EXTI_Type) SetEMR1_EM0(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetEMR1_EM0() uint32 {
	return volatile.LoadUint32(&o.EMR1.Reg) & 0x1
}
func (o *EXTI_Type) SetEMR1_EM1(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetEMR1_EM1() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetEMR1_EM2(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetEMR1_EM2() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetEMR1_EM3(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetEMR1_EM3() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetEMR1_EM4(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetEMR1_EM4() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetEMR1_EM5(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetEMR1_EM5() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetEMR1_EM6(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetEMR1_EM6() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetEMR1_EM7(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80)|value<<7)
}
func (o *EXTI_Type) GetEMR1_EM7() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80) >> 7
}
func (o *EXTI_Type) SetEMR1_EM8(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetEMR1_EM8() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetEMR1_EM9(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetEMR1_EM9() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetEMR1_EM10(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetEMR1_EM10() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x400) >> 10
}
func (o *EXTI_Type) SetEMR1_EM11(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x800)|value<<11)
}
func (o *EXTI_Type) GetEMR1_EM11() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x800) >> 11
}
func (o *EXTI_Type) SetEMR1_EM12(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1000)|value<<12)
}
func (o *EXTI_Type) GetEMR1_EM12() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x1000) >> 12
}
func (o *EXTI_Type) SetEMR1_EM13(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2000)|value<<13)
}
func (o *EXTI_Type) GetEMR1_EM13() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2000) >> 13
}
func (o *EXTI_Type) SetEMR1_EM14(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4000)|value<<14)
}
func (o *EXTI_Type) GetEMR1_EM14() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4000) >> 14
}
func (o *EXTI_Type) SetEMR1_EM15(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x8000)|value<<15)
}
func (o *EXTI_Type) GetEMR1_EM15() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x8000) >> 15
}
func (o *EXTI_Type) SetEMR1_EM16(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x10000)|value<<16)
}
func (o *EXTI_Type) GetEMR1_EM16() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x10000) >> 16
}
func (o *EXTI_Type) SetEMR1_EM17(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x20000)|value<<17)
}
func (o *EXTI_Type) GetEMR1_EM17() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x20000) >> 17
}
func (o *EXTI_Type) SetEMR1_EM18(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x40000)|value<<18)
}
func (o *EXTI_Type) GetEMR1_EM18() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x40000) >> 18
}
func (o *EXTI_Type) SetEMR1_EM19(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80000)|value<<19)
}
func (o *EXTI_Type) GetEMR1_EM19() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80000) >> 19
}
func (o *EXTI_Type) SetEMR1_EM20(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x100000)|value<<20)
}
func (o *EXTI_Type) GetEMR1_EM20() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x100000) >> 20
}
func (o *EXTI_Type) SetEMR1_EM21(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x200000)|value<<21)
}
func (o *EXTI_Type) GetEMR1_EM21() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x200000) >> 21
}
func (o *EXTI_Type) SetEMR1_EM22(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x400000)|value<<22)
}
func (o *EXTI_Type) GetEMR1_EM22() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x400000) >> 22
}
func (o *EXTI_Type) SetEMR1_EM23(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x800000)|value<<23)
}
func (o *EXTI_Type) GetEMR1_EM23() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x800000) >> 23
}
func (o *EXTI_Type) SetEMR1_EM24(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x1000000)|value<<24)
}
func (o *EXTI_Type) GetEMR1_EM24() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x1000000) >> 24
}
func (o *EXTI_Type) SetEMR1_EM25(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x2000000)|value<<25)
}
func (o *EXTI_Type) GetEMR1_EM25() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x2000000) >> 25
}
func (o *EXTI_Type) SetEMR1_EM26(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x4000000)|value<<26)
}
func (o *EXTI_Type) GetEMR1_EM26() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x4000000) >> 26
}
func (o *EXTI_Type) SetEMR1_EM27(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x8000000)|value<<27)
}
func (o *EXTI_Type) GetEMR1_EM27() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x8000000) >> 27
}
func (o *EXTI_Type) SetEMR1_EM28(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x10000000)|value<<28)
}
func (o *EXTI_Type) GetEMR1_EM28() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x10000000) >> 28
}
func (o *EXTI_Type) SetEMR1_EM29(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x20000000)|value<<29)
}
func (o *EXTI_Type) GetEMR1_EM29() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x20000000) >> 29
}
func (o *EXTI_Type) SetEMR1_EM30(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x40000000)|value<<30)
}
func (o *EXTI_Type) GetEMR1_EM30() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x40000000) >> 30
}
func (o *EXTI_Type) SetEMR1_EM31(value uint32) {
	volatile.StoreUint32(&o.EMR1.Reg, volatile.LoadUint32(&o.EMR1.Reg)&^(0x80000000)|value<<31)
}
func (o *EXTI_Type) GetEMR1_EM31() uint32 {
	return (volatile.LoadUint32(&o.EMR1.Reg) & 0x80000000) >> 31
}

// EXTI.IMR2: EXTI CPUm wakeup with interrupt mask register
func (o *EXTI_Type) SetIMR2_IM32(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetIMR2_IM32() uint32 {
	return volatile.LoadUint32(&o.IMR2.Reg) & 0x1
}
func (o *EXTI_Type) SetIMR2_IM33(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetIMR2_IM33() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetIMR2_IM34(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetIMR2_IM34() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetIMR2_IM35(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetIMR2_IM35() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetIMR2_IM36(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetIMR2_IM36() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetIMR2_IM37(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetIMR2_IM37() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetIMR2_IM38(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetIMR2_IM38() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetIMR2_IM40(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetIMR2_IM40() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetIMR2_IM41(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetIMR2_IM41() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetIMR2_IM42(value uint32) {
	volatile.StoreUint32(&o.IMR2.Reg, volatile.LoadUint32(&o.IMR2.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetIMR2_IM42() uint32 {
	return (volatile.LoadUint32(&o.IMR2.Reg) & 0x400) >> 10
}

// EXTI.EMR2: EXTI CPU wakeup with event mask register
func (o *EXTI_Type) SetEMR2_EM32(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x1)|value)
}
func (o *EXTI_Type) GetEMR2_EM32() uint32 {
	return volatile.LoadUint32(&o.EMR2.Reg) & 0x1
}
func (o *EXTI_Type) SetEMR2_EM33(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x2)|value<<1)
}
func (o *EXTI_Type) GetEMR2_EM33() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x2) >> 1
}
func (o *EXTI_Type) SetEMR2_EM34(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x4)|value<<2)
}
func (o *EXTI_Type) GetEMR2_EM34() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x4) >> 2
}
func (o *EXTI_Type) SetEMR2_EM35(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x8)|value<<3)
}
func (o *EXTI_Type) GetEMR2_EM35() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x8) >> 3
}
func (o *EXTI_Type) SetEMR2_EM36(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x10)|value<<4)
}
func (o *EXTI_Type) GetEMR2_EM36() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x10) >> 4
}
func (o *EXTI_Type) SetEMR2_EM37(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x20)|value<<5)
}
func (o *EXTI_Type) GetEMR2_EM37() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x20) >> 5
}
func (o *EXTI_Type) SetEMR2_EM38(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x40)|value<<6)
}
func (o *EXTI_Type) GetEMR2_EM38() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x40) >> 6
}
func (o *EXTI_Type) SetEMR2_EM40(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x100)|value<<8)
}
func (o *EXTI_Type) GetEMR2_EM40() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x100) >> 8
}
func (o *EXTI_Type) SetEMR2_EM41(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x200)|value<<9)
}
func (o *EXTI_Type) GetEMR2_EM41() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x200) >> 9
}
func (o *EXTI_Type) SetEMR2_EM42(value uint32) {
	volatile.StoreUint32(&o.EMR2.Reg, volatile.LoadUint32(&o.EMR2.Reg)&^(0x400)|value<<10)
}
func (o *EXTI_Type) GetEMR2_EM42() uint32 {
	return (volatile.LoadUint32(&o.EMR2.Reg) & 0x400) >> 10
}

// FDCAN1
type FDCAN_Type struct {
	CREL   volatile.Register32 // 0x0
	ENDN   volatile.Register32 // 0x4
	_      [4]byte
	DBTP   volatile.Register32 // 0xC
	TEST   volatile.Register32 // 0x10
	RWD    volatile.Register32 // 0x14
	CCCR   volatile.Register32 // 0x18
	NBTP   volatile.Register32 // 0x1C
	TSCC   volatile.Register32 // 0x20
	TSCV   volatile.Register32 // 0x24
	TOCC   volatile.Register32 // 0x28
	TOCV   volatile.Register32 // 0x2C
	_      [16]byte
	ECR    volatile.Register32 // 0x40
	PSR    volatile.Register32 // 0x44
	TDCR   volatile.Register32 // 0x48
	_      [4]byte
	IR     volatile.Register32 // 0x50
	IE     volatile.Register32 // 0x54
	ILS    volatile.Register32 // 0x58
	ILE    volatile.Register32 // 0x5C
	_      [32]byte
	RXGFC  volatile.Register32 // 0x80
	XIDAM  volatile.Register32 // 0x84
	HPMS   volatile.Register32 // 0x88
	_      [4]byte
	RXF0S  volatile.Register32 // 0x90
	RXF0A  volatile.Register32 // 0x94
	RXF1S  volatile.Register32 // 0x98
	RXF1A  volatile.Register32 // 0x9C
	_      [32]byte
	TXBC   volatile.Register32 // 0xC0
	TXFQS  volatile.Register32 // 0xC4
	TXBRP  volatile.Register32 // 0xC8
	TXBAR  volatile.Register32 // 0xCC
	TXBCR  volatile.Register32 // 0xD0
	TXBTO  volatile.Register32 // 0xD4
	TXBCF  volatile.Register32 // 0xD8
	TXBTIE volatile.Register32 // 0xDC
	TXBCIE volatile.Register32 // 0xE0
	TXEFS  volatile.Register32 // 0xE4
	TXEFA  volatile.Register32 // 0xE8
	_      [20]byte
	CKDIV  volatile.Register32 // 0x100
}

// FDCAN.CREL: FDCAN Core Release Register
func (o *FDCAN_Type) SetCREL_REL(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf0000000)|value<<28)
}
func (o *FDCAN_Type) GetCREL_REL() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf0000000) >> 28
}
func (o *FDCAN_Type) SetCREL_STEP(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf000000)|value<<24)
}
func (o *FDCAN_Type) GetCREL_STEP() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf000000) >> 24
}
func (o *FDCAN_Type) SetCREL_SUBSTEP(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf00000)|value<<20)
}
func (o *FDCAN_Type) GetCREL_SUBSTEP() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf00000) >> 20
}
func (o *FDCAN_Type) SetCREL_YEAR(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xf0000)|value<<16)
}
func (o *FDCAN_Type) GetCREL_YEAR() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xf0000) >> 16
}
func (o *FDCAN_Type) SetCREL_MON(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xff00)|value<<8)
}
func (o *FDCAN_Type) GetCREL_MON() uint32 {
	return (volatile.LoadUint32(&o.CREL.Reg) & 0xff00) >> 8
}
func (o *FDCAN_Type) SetCREL_DAY(value uint32) {
	volatile.StoreUint32(&o.CREL.Reg, volatile.LoadUint32(&o.CREL.Reg)&^(0xff)|value)
}
func (o *FDCAN_Type) GetCREL_DAY() uint32 {
	return volatile.LoadUint32(&o.CREL.Reg) & 0xff
}

// FDCAN.ENDN: FDCAN Core Release Register
func (o *FDCAN_Type) SetENDN(value uint32) {
	volatile.StoreUint32(&o.ENDN.Reg, value)
}
func (o *FDCAN_Type) GetENDN() uint32 {
	return volatile.LoadUint32(&o.ENDN.Reg)
}

// FDCAN.DBTP: FDCAN Data Bit Timing and Prescaler Register
func (o *FDCAN_Type) SetDBTP_DSJW(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetDBTP_DSJW() uint32 {
	return volatile.LoadUint32(&o.DBTP.Reg) & 0xf
}
func (o *FDCAN_Type) SetDBTP_DTSEG2(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0xf0)|value<<4)
}
func (o *FDCAN_Type) GetDBTP_DTSEG2() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0xf0) >> 4
}
func (o *FDCAN_Type) SetDBTP_DTSEG1(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0x1f00)|value<<8)
}
func (o *FDCAN_Type) GetDBTP_DTSEG1() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0x1f00) >> 8
}
func (o *FDCAN_Type) SetDBTP_DBRP(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0x1f0000)|value<<16)
}
func (o *FDCAN_Type) GetDBTP_DBRP() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0x1f0000) >> 16
}
func (o *FDCAN_Type) SetDBTP_TDC(value uint32) {
	volatile.StoreUint32(&o.DBTP.Reg, volatile.LoadUint32(&o.DBTP.Reg)&^(0x800000)|value<<23)
}
func (o *FDCAN_Type) GetDBTP_TDC() uint32 {
	return (volatile.LoadUint32(&o.DBTP.Reg) & 0x800000) >> 23
}

// FDCAN.TEST: FDCAN Test Register
func (o *FDCAN_Type) SetTEST_LBCK(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetTEST_LBCK() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetTEST_TX(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x60)|value<<5)
}
func (o *FDCAN_Type) GetTEST_TX() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x60) >> 5
}
func (o *FDCAN_Type) SetTEST_RX(value uint32) {
	volatile.StoreUint32(&o.TEST.Reg, volatile.LoadUint32(&o.TEST.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetTEST_RX() uint32 {
	return (volatile.LoadUint32(&o.TEST.Reg) & 0x80) >> 7
}

// FDCAN.RWD: FDCAN RAM Watchdog Register
func (o *FDCAN_Type) SetRWD_WDV(value uint32) {
	volatile.StoreUint32(&o.RWD.Reg, volatile.LoadUint32(&o.RWD.Reg)&^(0xff00)|value<<8)
}
func (o *FDCAN_Type) GetRWD_WDV() uint32 {
	return (volatile.LoadUint32(&o.RWD.Reg) & 0xff00) >> 8
}
func (o *FDCAN_Type) SetRWD_WDC(value uint32) {
	volatile.StoreUint32(&o.RWD.Reg, volatile.LoadUint32(&o.RWD.Reg)&^(0xff)|value)
}
func (o *FDCAN_Type) GetRWD_WDC() uint32 {
	return volatile.LoadUint32(&o.RWD.Reg) & 0xff
}

// FDCAN.CCCR: FDCAN CC Control Register
func (o *FDCAN_Type) SetCCCR_INIT(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetCCCR_INIT() uint32 {
	return volatile.LoadUint32(&o.CCCR.Reg) & 0x1
}
func (o *FDCAN_Type) SetCCCR_CCE(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetCCCR_CCE() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetCCCR_ASM(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetCCCR_ASM() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetCCCR_CSA(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetCCCR_CSA() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetCCCR_CSR(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetCCCR_CSR() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetCCCR_MON(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetCCCR_MON() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetCCCR_DAR(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetCCCR_DAR() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetCCCR_TEST(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetCCCR_TEST() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetCCCR_FDOE(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetCCCR_FDOE() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetCCCR_BSE(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetCCCR_BSE() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetCCCR_PXHD(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetCCCR_PXHD() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetCCCR_EFBI(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetCCCR_EFBI() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetCCCR_TXP(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetCCCR_TXP() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetCCCR_NISO(value uint32) {
	volatile.StoreUint32(&o.CCCR.Reg, volatile.LoadUint32(&o.CCCR.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetCCCR_NISO() uint32 {
	return (volatile.LoadUint32(&o.CCCR.Reg) & 0x8000) >> 15
}

// FDCAN.NBTP: FDCAN Nominal Bit Timing and Prescaler Register
func (o *FDCAN_Type) SetNBTP_NSJW(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0xfe000000)|value<<25)
}
func (o *FDCAN_Type) GetNBTP_NSJW() uint32 {
	return (volatile.LoadUint32(&o.NBTP.Reg) & 0xfe000000) >> 25
}
func (o *FDCAN_Type) SetNBTP_NBRP(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0x1ff0000)|value<<16)
}
func (o *FDCAN_Type) GetNBTP_NBRP() uint32 {
	return (volatile.LoadUint32(&o.NBTP.Reg) & 0x1ff0000) >> 16
}
func (o *FDCAN_Type) SetNBTP_NTSEG1(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0xff00)|value<<8)
}
func (o *FDCAN_Type) GetNBTP_NTSEG1() uint32 {
	return (volatile.LoadUint32(&o.NBTP.Reg) & 0xff00) >> 8
}
func (o *FDCAN_Type) SetNBTP_TSEG2(value uint32) {
	volatile.StoreUint32(&o.NBTP.Reg, volatile.LoadUint32(&o.NBTP.Reg)&^(0x7f)|value)
}
func (o *FDCAN_Type) GetNBTP_TSEG2() uint32 {
	return volatile.LoadUint32(&o.NBTP.Reg) & 0x7f
}

// FDCAN.TSCC: FDCAN Timestamp Counter Configuration Register
func (o *FDCAN_Type) SetTSCC_TCP(value uint32) {
	volatile.StoreUint32(&o.TSCC.Reg, volatile.LoadUint32(&o.TSCC.Reg)&^(0xf0000)|value<<16)
}
func (o *FDCAN_Type) GetTSCC_TCP() uint32 {
	return (volatile.LoadUint32(&o.TSCC.Reg) & 0xf0000) >> 16
}
func (o *FDCAN_Type) SetTSCC_TSS(value uint32) {
	volatile.StoreUint32(&o.TSCC.Reg, volatile.LoadUint32(&o.TSCC.Reg)&^(0x3)|value)
}
func (o *FDCAN_Type) GetTSCC_TSS() uint32 {
	return volatile.LoadUint32(&o.TSCC.Reg) & 0x3
}

// FDCAN.TSCV: FDCAN Timestamp Counter Value Register
func (o *FDCAN_Type) SetTSCV_TSC(value uint32) {
	volatile.StoreUint32(&o.TSCV.Reg, volatile.LoadUint32(&o.TSCV.Reg)&^(0xffff)|value)
}
func (o *FDCAN_Type) GetTSCV_TSC() uint32 {
	return volatile.LoadUint32(&o.TSCV.Reg) & 0xffff
}

// FDCAN.TOCC: FDCAN Timeout Counter Configuration Register
func (o *FDCAN_Type) SetTOCC_ETOC(value uint32) {
	volatile.StoreUint32(&o.TOCC.Reg, volatile.LoadUint32(&o.TOCC.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetTOCC_ETOC() uint32 {
	return volatile.LoadUint32(&o.TOCC.Reg) & 0x1
}
func (o *FDCAN_Type) SetTOCC_TOS(value uint32) {
	volatile.StoreUint32(&o.TOCC.Reg, volatile.LoadUint32(&o.TOCC.Reg)&^(0x6)|value<<1)
}
func (o *FDCAN_Type) GetTOCC_TOS() uint32 {
	return (volatile.LoadUint32(&o.TOCC.Reg) & 0x6) >> 1
}
func (o *FDCAN_Type) SetTOCC_TOP(value uint32) {
	volatile.StoreUint32(&o.TOCC.Reg, volatile.LoadUint32(&o.TOCC.Reg)&^(0xffff0000)|value<<16)
}
func (o *FDCAN_Type) GetTOCC_TOP() uint32 {
	return (volatile.LoadUint32(&o.TOCC.Reg) & 0xffff0000) >> 16
}

// FDCAN.TOCV: FDCAN Timeout Counter Value Register
func (o *FDCAN_Type) SetTOCV_TOC(value uint32) {
	volatile.StoreUint32(&o.TOCV.Reg, volatile.LoadUint32(&o.TOCV.Reg)&^(0xffff)|value)
}
func (o *FDCAN_Type) GetTOCV_TOC() uint32 {
	return volatile.LoadUint32(&o.TOCV.Reg) & 0xffff
}

// FDCAN.ECR: FDCAN Error Counter Register
func (o *FDCAN_Type) SetECR_CEL(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xff0000)|value<<16)
}
func (o *FDCAN_Type) GetECR_CEL() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0xff0000) >> 16
}
func (o *FDCAN_Type) SetECR_RP(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetECR_RP() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0x8000) >> 15
}
func (o *FDCAN_Type) SetECR_REC(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0x7f00)|value<<8)
}
func (o *FDCAN_Type) GetECR_REC() uint32 {
	return (volatile.LoadUint32(&o.ECR.Reg) & 0x7f00) >> 8
}
func (o *FDCAN_Type) SetECR_TEC(value uint32) {
	volatile.StoreUint32(&o.ECR.Reg, volatile.LoadUint32(&o.ECR.Reg)&^(0xff)|value)
}
func (o *FDCAN_Type) GetECR_TEC() uint32 {
	return volatile.LoadUint32(&o.ECR.Reg) & 0xff
}

// FDCAN.PSR: FDCAN Protocol Status Register
func (o *FDCAN_Type) SetPSR_LEC(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetPSR_LEC() uint32 {
	return volatile.LoadUint32(&o.PSR.Reg) & 0x7
}
func (o *FDCAN_Type) SetPSR_ACT(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x18)|value<<3)
}
func (o *FDCAN_Type) GetPSR_ACT() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x18) >> 3
}
func (o *FDCAN_Type) SetPSR_EP(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetPSR_EP() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetPSR_EW(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetPSR_EW() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetPSR_BO(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetPSR_BO() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetPSR_DLEC(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x700)|value<<8)
}
func (o *FDCAN_Type) GetPSR_DLEC() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x700) >> 8
}
func (o *FDCAN_Type) SetPSR_RESI(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x800)|value<<11)
}
func (o *FDCAN_Type) GetPSR_RESI() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x800) >> 11
}
func (o *FDCAN_Type) SetPSR_RBRS(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetPSR_RBRS() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetPSR_REDL(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetPSR_REDL() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetPSR_PXE(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetPSR_PXE() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetPSR_TDCV(value uint32) {
	volatile.StoreUint32(&o.PSR.Reg, volatile.LoadUint32(&o.PSR.Reg)&^(0x7f0000)|value<<16)
}
func (o *FDCAN_Type) GetPSR_TDCV() uint32 {
	return (volatile.LoadUint32(&o.PSR.Reg) & 0x7f0000) >> 16
}

// FDCAN.TDCR: FDCAN Transmitter Delay Compensation Register
func (o *FDCAN_Type) SetTDCR_TDCF(value uint32) {
	volatile.StoreUint32(&o.TDCR.Reg, volatile.LoadUint32(&o.TDCR.Reg)&^(0x7f)|value)
}
func (o *FDCAN_Type) GetTDCR_TDCF() uint32 {
	return volatile.LoadUint32(&o.TDCR.Reg) & 0x7f
}
func (o *FDCAN_Type) SetTDCR_TDCO(value uint32) {
	volatile.StoreUint32(&o.TDCR.Reg, volatile.LoadUint32(&o.TDCR.Reg)&^(0x7f00)|value<<8)
}
func (o *FDCAN_Type) GetTDCR_TDCO() uint32 {
	return (volatile.LoadUint32(&o.TDCR.Reg) & 0x7f00) >> 8
}

// FDCAN.IR: FDCAN Interrupt Register
func (o *FDCAN_Type) SetIR_RF0N(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetIR_RF0N() uint32 {
	return volatile.LoadUint32(&o.IR.Reg) & 0x1
}
func (o *FDCAN_Type) SetIR_RF0F(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetIR_RF0F() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetIR_RF0L(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetIR_RF0L() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetIR_RF1N(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetIR_RF1N() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetIR_RF1F(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetIR_RF1F() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetIR_RF1L(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetIR_RF1L() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetIR_HPM(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetIR_HPM() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetIR_TC(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetIR_TC() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetIR_TCF(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetIR_TCF() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetIR_TFE(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetIR_TFE() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetIR_TEFN(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x400)|value<<10)
}
func (o *FDCAN_Type) GetIR_TEFN() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x400) >> 10
}
func (o *FDCAN_Type) SetIR_TEFF(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x800)|value<<11)
}
func (o *FDCAN_Type) GetIR_TEFF() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x800) >> 11
}
func (o *FDCAN_Type) SetIR_TEFL(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetIR_TEFL() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetIR_TSW(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetIR_TSW() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetIR_MRAF(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetIR_MRAF() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetIR_TOO(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetIR_TOO() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x8000) >> 15
}
func (o *FDCAN_Type) SetIR_ELO(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x10000)|value<<16)
}
func (o *FDCAN_Type) GetIR_ELO() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x10000) >> 16
}
func (o *FDCAN_Type) SetIR_EP(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x20000)|value<<17)
}
func (o *FDCAN_Type) GetIR_EP() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x20000) >> 17
}
func (o *FDCAN_Type) SetIR_EW(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x40000)|value<<18)
}
func (o *FDCAN_Type) GetIR_EW() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x40000) >> 18
}
func (o *FDCAN_Type) SetIR_BO(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x80000)|value<<19)
}
func (o *FDCAN_Type) GetIR_BO() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x80000) >> 19
}
func (o *FDCAN_Type) SetIR_WDI(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x100000)|value<<20)
}
func (o *FDCAN_Type) GetIR_WDI() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x100000) >> 20
}
func (o *FDCAN_Type) SetIR_PEA(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x200000)|value<<21)
}
func (o *FDCAN_Type) GetIR_PEA() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x200000) >> 21
}
func (o *FDCAN_Type) SetIR_PED(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x400000)|value<<22)
}
func (o *FDCAN_Type) GetIR_PED() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x400000) >> 22
}
func (o *FDCAN_Type) SetIR_ARA(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, volatile.LoadUint32(&o.IR.Reg)&^(0x800000)|value<<23)
}
func (o *FDCAN_Type) GetIR_ARA() uint32 {
	return (volatile.LoadUint32(&o.IR.Reg) & 0x800000) >> 23
}

// FDCAN.IE: FDCAN Interrupt Enable Register
func (o *FDCAN_Type) SetIE_RF0NE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetIE_RF0NE() uint32 {
	return volatile.LoadUint32(&o.IE.Reg) & 0x1
}
func (o *FDCAN_Type) SetIE_RF0FE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetIE_RF0FE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetIE_RF0LE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetIE_RF0LE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetIE_RF1NE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetIE_RF1NE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetIE_RF1FE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetIE_RF1FE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetIE_RF1LE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetIE_RF1LE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetIE_HPME(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetIE_HPME() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x40) >> 6
}
func (o *FDCAN_Type) SetIE_TCE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x80)|value<<7)
}
func (o *FDCAN_Type) GetIE_TCE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x80) >> 7
}
func (o *FDCAN_Type) SetIE_TCFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetIE_TCFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetIE_TEFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetIE_TEFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetIE_TEFNE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x400)|value<<10)
}
func (o *FDCAN_Type) GetIE_TEFNE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x400) >> 10
}
func (o *FDCAN_Type) SetIE_TEFFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x800)|value<<11)
}
func (o *FDCAN_Type) GetIE_TEFFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x800) >> 11
}
func (o *FDCAN_Type) SetIE_TEFLE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x1000)|value<<12)
}
func (o *FDCAN_Type) GetIE_TEFLE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x1000) >> 12
}
func (o *FDCAN_Type) SetIE_MRAFE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x2000)|value<<13)
}
func (o *FDCAN_Type) GetIE_MRAFE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x2000) >> 13
}
func (o *FDCAN_Type) SetIE_TOOE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x4000)|value<<14)
}
func (o *FDCAN_Type) GetIE_TOOE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x4000) >> 14
}
func (o *FDCAN_Type) SetIE_ELOE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetIE_ELOE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x8000) >> 15
}
func (o *FDCAN_Type) SetIE_EPE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x10000)|value<<16)
}
func (o *FDCAN_Type) GetIE_EPE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x10000) >> 16
}
func (o *FDCAN_Type) SetIE_EWE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x20000)|value<<17)
}
func (o *FDCAN_Type) GetIE_EWE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x20000) >> 17
}
func (o *FDCAN_Type) SetIE_BOE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x40000)|value<<18)
}
func (o *FDCAN_Type) GetIE_BOE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x40000) >> 18
}
func (o *FDCAN_Type) SetIE_WDIE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x80000)|value<<19)
}
func (o *FDCAN_Type) GetIE_WDIE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x80000) >> 19
}
func (o *FDCAN_Type) SetIE_PEAE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x100000)|value<<20)
}
func (o *FDCAN_Type) GetIE_PEAE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x100000) >> 20
}
func (o *FDCAN_Type) SetIE_PEDE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x200000)|value<<21)
}
func (o *FDCAN_Type) GetIE_PEDE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x200000) >> 21
}
func (o *FDCAN_Type) SetIE_ARAE(value uint32) {
	volatile.StoreUint32(&o.IE.Reg, volatile.LoadUint32(&o.IE.Reg)&^(0x400000)|value<<22)
}
func (o *FDCAN_Type) GetIE_ARAE() uint32 {
	return (volatile.LoadUint32(&o.IE.Reg) & 0x400000) >> 22
}

// FDCAN.ILS: FDCAN Interrupt Line Select Register
func (o *FDCAN_Type) SetILS_RxFIFO0(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetILS_RxFIFO0() uint32 {
	return volatile.LoadUint32(&o.ILS.Reg) & 0x1
}
func (o *FDCAN_Type) SetILS_RxFIFO1(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetILS_RxFIFO1() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetILS_SMSG(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x4)|value<<2)
}
func (o *FDCAN_Type) GetILS_SMSG() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x4) >> 2
}
func (o *FDCAN_Type) SetILS_TFERR(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x8)|value<<3)
}
func (o *FDCAN_Type) GetILS_TFERR() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x8) >> 3
}
func (o *FDCAN_Type) SetILS_MISC(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x10)|value<<4)
}
func (o *FDCAN_Type) GetILS_MISC() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x10) >> 4
}
func (o *FDCAN_Type) SetILS_BERR(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x20)|value<<5)
}
func (o *FDCAN_Type) GetILS_BERR() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x20) >> 5
}
func (o *FDCAN_Type) SetILS_PERR(value uint32) {
	volatile.StoreUint32(&o.ILS.Reg, volatile.LoadUint32(&o.ILS.Reg)&^(0x40)|value<<6)
}
func (o *FDCAN_Type) GetILS_PERR() uint32 {
	return (volatile.LoadUint32(&o.ILS.Reg) & 0x40) >> 6
}

// FDCAN.ILE: FDCAN Interrupt Line Enable Register
func (o *FDCAN_Type) SetILE_EINT0(value uint32) {
	volatile.StoreUint32(&o.ILE.Reg, volatile.LoadUint32(&o.ILE.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetILE_EINT0() uint32 {
	return volatile.LoadUint32(&o.ILE.Reg) & 0x1
}
func (o *FDCAN_Type) SetILE_EINT1(value uint32) {
	volatile.StoreUint32(&o.ILE.Reg, volatile.LoadUint32(&o.ILE.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetILE_EINT1() uint32 {
	return (volatile.LoadUint32(&o.ILE.Reg) & 0x2) >> 1
}

// FDCAN.RXGFC: FDCAN Global Filter Configuration Register
func (o *FDCAN_Type) SetRXGFC_RRFE(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x1)|value)
}
func (o *FDCAN_Type) GetRXGFC_RRFE() uint32 {
	return volatile.LoadUint32(&o.RXGFC.Reg) & 0x1
}
func (o *FDCAN_Type) SetRXGFC_RRFS(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x2)|value<<1)
}
func (o *FDCAN_Type) GetRXGFC_RRFS() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x2) >> 1
}
func (o *FDCAN_Type) SetRXGFC_ANFE(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0xc)|value<<2)
}
func (o *FDCAN_Type) GetRXGFC_ANFE() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0xc) >> 2
}
func (o *FDCAN_Type) SetRXGFC_ANFS(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x30)|value<<4)
}
func (o *FDCAN_Type) GetRXGFC_ANFS() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x30) >> 4
}
func (o *FDCAN_Type) SetRXGFC_F1OM(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x100)|value<<8)
}
func (o *FDCAN_Type) GetRXGFC_F1OM() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x100) >> 8
}
func (o *FDCAN_Type) SetRXGFC_F0OM(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x200)|value<<9)
}
func (o *FDCAN_Type) GetRXGFC_F0OM() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x200) >> 9
}
func (o *FDCAN_Type) SetRXGFC_LSS(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0x1f0000)|value<<16)
}
func (o *FDCAN_Type) GetRXGFC_LSS() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0x1f0000) >> 16
}
func (o *FDCAN_Type) SetRXGFC_LSE(value uint32) {
	volatile.StoreUint32(&o.RXGFC.Reg, volatile.LoadUint32(&o.RXGFC.Reg)&^(0xf000000)|value<<24)
}
func (o *FDCAN_Type) GetRXGFC_LSE() uint32 {
	return (volatile.LoadUint32(&o.RXGFC.Reg) & 0xf000000) >> 24
}

// FDCAN.XIDAM: FDCAN Extended ID and Mask Register
func (o *FDCAN_Type) SetXIDAM_EIDM(value uint32) {
	volatile.StoreUint32(&o.XIDAM.Reg, volatile.LoadUint32(&o.XIDAM.Reg)&^(0x1fffffff)|value)
}
func (o *FDCAN_Type) GetXIDAM_EIDM() uint32 {
	return volatile.LoadUint32(&o.XIDAM.Reg) & 0x1fffffff
}

// FDCAN.HPMS: FDCAN High Priority Message Status Register
func (o *FDCAN_Type) SetHPMS_BIDX(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetHPMS_BIDX() uint32 {
	return volatile.LoadUint32(&o.HPMS.Reg) & 0x7
}
func (o *FDCAN_Type) SetHPMS_MSI(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0xc0)|value<<6)
}
func (o *FDCAN_Type) GetHPMS_MSI() uint32 {
	return (volatile.LoadUint32(&o.HPMS.Reg) & 0xc0) >> 6
}
func (o *FDCAN_Type) SetHPMS_FIDX(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0x1f00)|value<<8)
}
func (o *FDCAN_Type) GetHPMS_FIDX() uint32 {
	return (volatile.LoadUint32(&o.HPMS.Reg) & 0x1f00) >> 8
}
func (o *FDCAN_Type) SetHPMS_FLST(value uint32) {
	volatile.StoreUint32(&o.HPMS.Reg, volatile.LoadUint32(&o.HPMS.Reg)&^(0x8000)|value<<15)
}
func (o *FDCAN_Type) GetHPMS_FLST() uint32 {
	return (volatile.LoadUint32(&o.HPMS.Reg) & 0x8000) >> 15
}

// FDCAN.RXF0S: FDCAN Rx FIFO 0 Status Register
func (o *FDCAN_Type) SetRXF0S_F0FL(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetRXF0S_F0FL() uint32 {
	return volatile.LoadUint32(&o.RXF0S.Reg) & 0xf
}
func (o *FDCAN_Type) SetRXF0S_F0GI(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetRXF0S_F0GI() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetRXF0S_F0PI(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetRXF0S_F0PI() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x30000) >> 16
}
func (o *FDCAN_Type) SetRXF0S_F0F(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetRXF0S_F0F() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x1000000) >> 24
}
func (o *FDCAN_Type) SetRXF0S_RF0L(value uint32) {
	volatile.StoreUint32(&o.RXF0S.Reg, volatile.LoadUint32(&o.RXF0S.Reg)&^(0x2000000)|value<<25)
}
func (o *FDCAN_Type) GetRXF0S_RF0L() uint32 {
	return (volatile.LoadUint32(&o.RXF0S.Reg) & 0x2000000) >> 25
}

// FDCAN.RXF0A: CAN Rx FIFO 0 Acknowledge Register
func (o *FDCAN_Type) SetRXF0A_F0AI(value uint32) {
	volatile.StoreUint32(&o.RXF0A.Reg, volatile.LoadUint32(&o.RXF0A.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetRXF0A_F0AI() uint32 {
	return volatile.LoadUint32(&o.RXF0A.Reg) & 0x7
}

// FDCAN.RXF1S: FDCAN Rx FIFO 1 Status Register
func (o *FDCAN_Type) SetRXF1S_F1FL(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetRXF1S_F1FL() uint32 {
	return volatile.LoadUint32(&o.RXF1S.Reg) & 0xf
}
func (o *FDCAN_Type) SetRXF1S_F1GI(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetRXF1S_F1GI() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetRXF1S_F1PI(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetRXF1S_F1PI() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x30000) >> 16
}
func (o *FDCAN_Type) SetRXF1S_F1F(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetRXF1S_F1F() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x1000000) >> 24
}
func (o *FDCAN_Type) SetRXF1S_RF1L(value uint32) {
	volatile.StoreUint32(&o.RXF1S.Reg, volatile.LoadUint32(&o.RXF1S.Reg)&^(0x2000000)|value<<25)
}
func (o *FDCAN_Type) GetRXF1S_RF1L() uint32 {
	return (volatile.LoadUint32(&o.RXF1S.Reg) & 0x2000000) >> 25
}

// FDCAN.RXF1A: FDCAN Rx FIFO 1 Acknowledge Register
func (o *FDCAN_Type) SetRXF1A_F1AI(value uint32) {
	volatile.StoreUint32(&o.RXF1A.Reg, volatile.LoadUint32(&o.RXF1A.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetRXF1A_F1AI() uint32 {
	return volatile.LoadUint32(&o.RXF1A.Reg) & 0x7
}

// FDCAN.TXBC: FDCAN Tx buffer configuration register
func (o *FDCAN_Type) SetTXBC_TFQM(value uint32) {
	volatile.StoreUint32(&o.TXBC.Reg, volatile.LoadUint32(&o.TXBC.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetTXBC_TFQM() uint32 {
	return (volatile.LoadUint32(&o.TXBC.Reg) & 0x1000000) >> 24
}

// FDCAN.TXFQS: FDCAN Tx FIFO/Queue Status Register
func (o *FDCAN_Type) SetTXFQS_TFFL(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXFQS_TFFL() uint32 {
	return volatile.LoadUint32(&o.TXFQS.Reg) & 0x7
}
func (o *FDCAN_Type) SetTXFQS_TFGI(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetTXFQS_TFGI() uint32 {
	return (volatile.LoadUint32(&o.TXFQS.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetTXFQS_TFQPI(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetTXFQS_TFQPI() uint32 {
	return (volatile.LoadUint32(&o.TXFQS.Reg) & 0x30000) >> 16
}
func (o *FDCAN_Type) SetTXFQS_TFQF(value uint32) {
	volatile.StoreUint32(&o.TXFQS.Reg, volatile.LoadUint32(&o.TXFQS.Reg)&^(0x200000)|value<<21)
}
func (o *FDCAN_Type) GetTXFQS_TFQF() uint32 {
	return (volatile.LoadUint32(&o.TXFQS.Reg) & 0x200000) >> 21
}

// FDCAN.TXBRP: FDCAN Tx Buffer Request Pending Register
func (o *FDCAN_Type) SetTXBRP_TRP(value uint32) {
	volatile.StoreUint32(&o.TXBRP.Reg, volatile.LoadUint32(&o.TXBRP.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBRP_TRP() uint32 {
	return volatile.LoadUint32(&o.TXBRP.Reg) & 0x7
}

// FDCAN.TXBAR: FDCAN Tx Buffer Add Request Register
func (o *FDCAN_Type) SetTXBAR_AR(value uint32) {
	volatile.StoreUint32(&o.TXBAR.Reg, volatile.LoadUint32(&o.TXBAR.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBAR_AR() uint32 {
	return volatile.LoadUint32(&o.TXBAR.Reg) & 0x7
}

// FDCAN.TXBCR: FDCAN Tx Buffer Cancellation Request Register
func (o *FDCAN_Type) SetTXBCR_CR(value uint32) {
	volatile.StoreUint32(&o.TXBCR.Reg, volatile.LoadUint32(&o.TXBCR.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBCR_CR() uint32 {
	return volatile.LoadUint32(&o.TXBCR.Reg) & 0x7
}

// FDCAN.TXBTO: FDCAN Tx Buffer Transmission Occurred Register
func (o *FDCAN_Type) SetTXBTO_TO(value uint32) {
	volatile.StoreUint32(&o.TXBTO.Reg, volatile.LoadUint32(&o.TXBTO.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBTO_TO() uint32 {
	return volatile.LoadUint32(&o.TXBTO.Reg) & 0x7
}

// FDCAN.TXBCF: FDCAN Tx Buffer Cancellation Finished Register
func (o *FDCAN_Type) SetTXBCF_CF(value uint32) {
	volatile.StoreUint32(&o.TXBCF.Reg, volatile.LoadUint32(&o.TXBCF.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBCF_CF() uint32 {
	return volatile.LoadUint32(&o.TXBCF.Reg) & 0x7
}

// FDCAN.TXBTIE: FDCAN Tx Buffer Transmission Interrupt Enable Register
func (o *FDCAN_Type) SetTXBTIE_TIE(value uint32) {
	volatile.StoreUint32(&o.TXBTIE.Reg, volatile.LoadUint32(&o.TXBTIE.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBTIE_TIE() uint32 {
	return volatile.LoadUint32(&o.TXBTIE.Reg) & 0x7
}

// FDCAN.TXBCIE: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
func (o *FDCAN_Type) SetTXBCIE_CF(value uint32) {
	volatile.StoreUint32(&o.TXBCIE.Reg, volatile.LoadUint32(&o.TXBCIE.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXBCIE_CF() uint32 {
	return volatile.LoadUint32(&o.TXBCIE.Reg) & 0x7
}

// FDCAN.TXEFS: FDCAN Tx Event FIFO Status Register
func (o *FDCAN_Type) SetTXEFS_EFFL(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x7)|value)
}
func (o *FDCAN_Type) GetTXEFS_EFFL() uint32 {
	return volatile.LoadUint32(&o.TXEFS.Reg) & 0x7
}
func (o *FDCAN_Type) SetTXEFS_EFGI(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x300)|value<<8)
}
func (o *FDCAN_Type) GetTXEFS_EFGI() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x300) >> 8
}
func (o *FDCAN_Type) SetTXEFS_EFF(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x1000000)|value<<24)
}
func (o *FDCAN_Type) GetTXEFS_EFF() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x1000000) >> 24
}
func (o *FDCAN_Type) SetTXEFS_TEFL(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x2000000)|value<<25)
}
func (o *FDCAN_Type) GetTXEFS_TEFL() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x2000000) >> 25
}
func (o *FDCAN_Type) SetTXEFS_EFPI(value uint32) {
	volatile.StoreUint32(&o.TXEFS.Reg, volatile.LoadUint32(&o.TXEFS.Reg)&^(0x30000)|value<<16)
}
func (o *FDCAN_Type) GetTXEFS_EFPI() uint32 {
	return (volatile.LoadUint32(&o.TXEFS.Reg) & 0x30000) >> 16
}

// FDCAN.TXEFA: FDCAN Tx Event FIFO Acknowledge Register
func (o *FDCAN_Type) SetTXEFA_EFAI(value uint32) {
	volatile.StoreUint32(&o.TXEFA.Reg, volatile.LoadUint32(&o.TXEFA.Reg)&^(0x3)|value)
}
func (o *FDCAN_Type) GetTXEFA_EFAI() uint32 {
	return volatile.LoadUint32(&o.TXEFA.Reg) & 0x3
}

// FDCAN.CKDIV: FDCAN TT Trigger Memory Configuration Register
func (o *FDCAN_Type) SetCKDIV_PDIV(value uint32) {
	volatile.StoreUint32(&o.CKDIV.Reg, volatile.LoadUint32(&o.CKDIV.Reg)&^(0xf)|value)
}
func (o *FDCAN_Type) GetCKDIV_PDIV() uint32 {
	return volatile.LoadUint32(&o.CKDIV.Reg) & 0xf
}

// Flash
type Flash_Type struct {
	ACR          volatile.Register32 // 0x0
	PDKEYR       volatile.Register32 // 0x4
	NSKEYR       volatile.Register32 // 0x8
	SECKEYR      volatile.Register32 // 0xC
	OPTKEYR      volatile.Register32 // 0x10
	LVEKEYR      volatile.Register32 // 0x14
	_            [8]byte
	NSSR         volatile.Register32 // 0x20
	SECSR        volatile.Register32 // 0x24
	NSCR         volatile.Register32 // 0x28
	SECCR        volatile.Register32 // 0x2C
	ECCR         volatile.Register32 // 0x30
	_            [12]byte
	OPTR         volatile.Register32 // 0x40
	NSBOOTADD0R  volatile.Register32 // 0x44
	NSBOOTADD1R  volatile.Register32 // 0x48
	SECBOOTADD0R volatile.Register32 // 0x4C
	SECWM1R1     volatile.Register32 // 0x50
	SECWM1R2     volatile.Register32 // 0x54
	WRP1AR       volatile.Register32 // 0x58
	WRP1BR       volatile.Register32 // 0x5C
	SECWM2R1     volatile.Register32 // 0x60
	SECWM2R2     volatile.Register32 // 0x64
	WRP2AR       volatile.Register32 // 0x68
	WRP2BR       volatile.Register32 // 0x6C
	_            [16]byte
	SECBB1R1     volatile.Register32 // 0x80
	SECBB1R2     volatile.Register32 // 0x84
	SECBB1R3     volatile.Register32 // 0x88
	SECBB1R4     volatile.Register32 // 0x8C
	_            [16]byte
	SECBB2R1     volatile.Register32 // 0xA0
	SECBB2R2     volatile.Register32 // 0xA4
	SECBB2R3     volatile.Register32 // 0xA8
	SECBB2R4     volatile.Register32 // 0xAC
	_            [16]byte
	SECHDPCR     volatile.Register32 // 0xC0
	PRIVCFGR     volatile.Register32 // 0xC4
}

// Flash.ACR: Access control register
func (o *Flash_Type) SetACR_LATENCY(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0xf)|value)
}
func (o *Flash_Type) GetACR_LATENCY() uint32 {
	return volatile.LoadUint32(&o.ACR.Reg) & 0xf
}
func (o *Flash_Type) SetACR_RUN_PD(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetACR_RUN_PD() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetACR_SLEEP_PD(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetACR_SLEEP_PD() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetACR_LVEN(value uint32) {
	volatile.StoreUint32(&o.ACR.Reg, volatile.LoadUint32(&o.ACR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetACR_LVEN() uint32 {
	return (volatile.LoadUint32(&o.ACR.Reg) & 0x8000) >> 15
}

// Flash.PDKEYR: Power down key register
func (o *Flash_Type) SetPDKEYR(value uint32) {
	volatile.StoreUint32(&o.PDKEYR.Reg, value)
}
func (o *Flash_Type) GetPDKEYR() uint32 {
	return volatile.LoadUint32(&o.PDKEYR.Reg)
}

// Flash.NSKEYR: Flash non-secure key register
func (o *Flash_Type) SetNSKEYR(value uint32) {
	volatile.StoreUint32(&o.NSKEYR.Reg, value)
}
func (o *Flash_Type) GetNSKEYR() uint32 {
	return volatile.LoadUint32(&o.NSKEYR.Reg)
}

// Flash.SECKEYR: Flash secure key register
func (o *Flash_Type) SetSECKEYR(value uint32) {
	volatile.StoreUint32(&o.SECKEYR.Reg, value)
}
func (o *Flash_Type) GetSECKEYR() uint32 {
	return volatile.LoadUint32(&o.SECKEYR.Reg)
}

// Flash.OPTKEYR: Flash option key register
func (o *Flash_Type) SetOPTKEYR(value uint32) {
	volatile.StoreUint32(&o.OPTKEYR.Reg, value)
}
func (o *Flash_Type) GetOPTKEYR() uint32 {
	return volatile.LoadUint32(&o.OPTKEYR.Reg)
}

// Flash.LVEKEYR: Flash low voltage key register
func (o *Flash_Type) SetLVEKEYR(value uint32) {
	volatile.StoreUint32(&o.LVEKEYR.Reg, value)
}
func (o *Flash_Type) GetLVEKEYR() uint32 {
	return volatile.LoadUint32(&o.LVEKEYR.Reg)
}

// Flash.NSSR: Flash status register
func (o *Flash_Type) SetNSSR_NSEOP(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetNSSR_NSEOP() uint32 {
	return volatile.LoadUint32(&o.NSSR.Reg) & 0x1
}
func (o *Flash_Type) SetNSSR_NSOPERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetNSSR_NSOPERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetNSSR_NSPROGERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetNSSR_NSPROGERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetNSSR_NSWRPERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetNSSR_NSWRPERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetNSSR_NSPGAERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetNSSR_NSPGAERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetNSSR_NSSIZERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetNSSR_NSSIZERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetNSSR_NSPGSERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetNSSR_NSPGSERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetNSSR_OPTWERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetNSSR_OPTWERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetNSSR_OPTVERR(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetNSSR_OPTVERR() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetNSSR_NSBSY(value uint32) {
	volatile.StoreUint32(&o.NSSR.Reg, volatile.LoadUint32(&o.NSSR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetNSSR_NSBSY() uint32 {
	return (volatile.LoadUint32(&o.NSSR.Reg) & 0x10000) >> 16
}

// Flash.SECSR: Flash status register
func (o *Flash_Type) SetSECSR_SECEOP(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECSR_SECEOP() uint32 {
	return volatile.LoadUint32(&o.SECSR.Reg) & 0x1
}
func (o *Flash_Type) SetSECSR_SECOPERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSECSR_SECOPERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSECSR_SECPROGERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x8)|value<<3)
}
func (o *Flash_Type) GetSECSR_SECPROGERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x8) >> 3
}
func (o *Flash_Type) SetSECSR_SECWRPERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x10)|value<<4)
}
func (o *Flash_Type) GetSECSR_SECWRPERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x10) >> 4
}
func (o *Flash_Type) SetSECSR_SECPGAERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x20)|value<<5)
}
func (o *Flash_Type) GetSECSR_SECPGAERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x20) >> 5
}
func (o *Flash_Type) SetSECSR_SECSIZERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x40)|value<<6)
}
func (o *Flash_Type) GetSECSR_SECSIZERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x40) >> 6
}
func (o *Flash_Type) SetSECSR_SECPGSERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x80)|value<<7)
}
func (o *Flash_Type) GetSECSR_SECPGSERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x80) >> 7
}
func (o *Flash_Type) SetSECSR_SECRDERR(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetSECSR_SECRDERR() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetSECSR_SECBSY(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSECSR_SECBSY() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x10000) >> 16
}

// Flash.NSCR: Flash non-secure control register
func (o *Flash_Type) SetNSCR_NSPG(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetNSCR_NSPG() uint32 {
	return volatile.LoadUint32(&o.NSCR.Reg) & 0x1
}
func (o *Flash_Type) SetNSCR_NSPER(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetNSCR_NSPER() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetNSCR_NSMER1(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetNSCR_NSMER1() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetNSCR_NSPNB(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x3f8)|value<<3)
}
func (o *Flash_Type) GetNSCR_NSPNB() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x3f8) >> 3
}
func (o *Flash_Type) SetNSCR_NSBKER(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetNSCR_NSBKER() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetNSCR_NSMER2(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetNSCR_NSMER2() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetNSCR_NSSTRT(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetNSCR_NSSTRT() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetNSCR_OPTSTRT(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetNSCR_OPTSTRT() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetNSCR_NSEOPIE(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetNSCR_NSEOPIE() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetNSCR_NSERRIE(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetNSCR_NSERRIE() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetNSCR_OBL_LAUNCH(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetNSCR_OBL_LAUNCH() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetNSCR_OPTLOCK(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetNSCR_OPTLOCK() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetNSCR_NSLOCK(value uint32) {
	volatile.StoreUint32(&o.NSCR.Reg, volatile.LoadUint32(&o.NSCR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetNSCR_NSLOCK() uint32 {
	return (volatile.LoadUint32(&o.NSCR.Reg) & 0x80000000) >> 31
}

// Flash.SECCR: Flash secure control register
func (o *Flash_Type) SetSECCR_SECPG(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECCR_SECPG() uint32 {
	return volatile.LoadUint32(&o.SECCR.Reg) & 0x1
}
func (o *Flash_Type) SetSECCR_SECPER(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSECCR_SECPER() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x2) >> 1
}
func (o *Flash_Type) SetSECCR_SECMER1(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x4)|value<<2)
}
func (o *Flash_Type) GetSECCR_SECMER1() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x4) >> 2
}
func (o *Flash_Type) SetSECCR_SECPNB(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x3f8)|value<<3)
}
func (o *Flash_Type) GetSECCR_SECPNB() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x3f8) >> 3
}
func (o *Flash_Type) SetSECCR_SECBKER(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x800)|value<<11)
}
func (o *Flash_Type) GetSECCR_SECBKER() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x800) >> 11
}
func (o *Flash_Type) SetSECCR_SECMER2(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSECCR_SECMER2() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSECCR_SECSTRT(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetSECCR_SECSTRT() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetSECCR_SECEOPIE(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetSECCR_SECEOPIE() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetSECCR_SECERRIE(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetSECCR_SECERRIE() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetSECCR_SECRDERRIE(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetSECCR_SECRDERRIE() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetSECCR_SECINV(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetSECCR_SECINV() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetSECCR_SECLOCK(value uint32) {
	volatile.StoreUint32(&o.SECCR.Reg, volatile.LoadUint32(&o.SECCR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSECCR_SECLOCK() uint32 {
	return (volatile.LoadUint32(&o.SECCR.Reg) & 0x80000000) >> 31
}

// Flash.ECCR: Flash ECC register
func (o *Flash_Type) SetECCR_ADDR_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x7ffff)|value)
}
func (o *Flash_Type) GetECCR_ADDR_ECC() uint32 {
	return volatile.LoadUint32(&o.ECCR.Reg) & 0x7ffff
}
func (o *Flash_Type) SetECCR_BK_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetECCR_BK_ECC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetECCR_SYSF_ECC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetECCR_SYSF_ECC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetECCR_ECCIE(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetECCR_ECCIE() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetECCR_ECCC2(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetECCR_ECCC2() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetECCR_ECCD2(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x20000000)|value<<29)
}
func (o *Flash_Type) GetECCR_ECCD2() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x20000000) >> 29
}
func (o *Flash_Type) SetECCR_ECCC(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x40000000)|value<<30)
}
func (o *Flash_Type) GetECCR_ECCC() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x40000000) >> 30
}
func (o *Flash_Type) SetECCR_ECCD(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, volatile.LoadUint32(&o.ECCR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetECCR_ECCD() uint32 {
	return (volatile.LoadUint32(&o.ECCR.Reg) & 0x80000000) >> 31
}

// Flash.OPTR: Flash option register
func (o *Flash_Type) SetOPTR_RDP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0xff)|value)
}
func (o *Flash_Type) GetOPTR_RDP() uint32 {
	return volatile.LoadUint32(&o.OPTR.Reg) & 0xff
}
func (o *Flash_Type) SetOPTR_BOR_LEV(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x700)|value<<8)
}
func (o *Flash_Type) GetOPTR_BOR_LEV() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x700) >> 8
}
func (o *Flash_Type) SetOPTR_NRST_STOP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x1000)|value<<12)
}
func (o *Flash_Type) GetOPTR_NRST_STOP() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x1000) >> 12
}
func (o *Flash_Type) SetOPTR_NRST_STDBY(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x2000)|value<<13)
}
func (o *Flash_Type) GetOPTR_NRST_STDBY() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x2000) >> 13
}
func (o *Flash_Type) SetOPTR_NRST_SHDW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x4000)|value<<14)
}
func (o *Flash_Type) GetOPTR_NRST_SHDW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x4000) >> 14
}
func (o *Flash_Type) SetOPTR_IWDG_SW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x10000)|value<<16)
}
func (o *Flash_Type) GetOPTR_IWDG_SW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x10000) >> 16
}
func (o *Flash_Type) SetOPTR_IWDG_STOP(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x20000)|value<<17)
}
func (o *Flash_Type) GetOPTR_IWDG_STOP() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x20000) >> 17
}
func (o *Flash_Type) SetOPTR_IWDG_STDBY(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x40000)|value<<18)
}
func (o *Flash_Type) GetOPTR_IWDG_STDBY() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x40000) >> 18
}
func (o *Flash_Type) SetOPTR_WWDG_SW(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x80000)|value<<19)
}
func (o *Flash_Type) GetOPTR_WWDG_SW() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x80000) >> 19
}
func (o *Flash_Type) SetOPTR_SWAP_BANK(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x100000)|value<<20)
}
func (o *Flash_Type) GetOPTR_SWAP_BANK() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x100000) >> 20
}
func (o *Flash_Type) SetOPTR_DB256K(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x200000)|value<<21)
}
func (o *Flash_Type) GetOPTR_DB256K() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x200000) >> 21
}
func (o *Flash_Type) SetOPTR_DBANK(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x400000)|value<<22)
}
func (o *Flash_Type) GetOPTR_DBANK() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x400000) >> 22
}
func (o *Flash_Type) SetOPTR_SRAM2_PE(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x1000000)|value<<24)
}
func (o *Flash_Type) GetOPTR_SRAM2_PE() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x1000000) >> 24
}
func (o *Flash_Type) SetOPTR_SRAM2_RST(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x2000000)|value<<25)
}
func (o *Flash_Type) GetOPTR_SRAM2_RST() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x2000000) >> 25
}
func (o *Flash_Type) SetOPTR_NSWBOOT0(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x4000000)|value<<26)
}
func (o *Flash_Type) GetOPTR_NSWBOOT0() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x4000000) >> 26
}
func (o *Flash_Type) SetOPTR_NBOOT0(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x8000000)|value<<27)
}
func (o *Flash_Type) GetOPTR_NBOOT0() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x8000000) >> 27
}
func (o *Flash_Type) SetOPTR_PA15_PUPEN(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x10000000)|value<<28)
}
func (o *Flash_Type) GetOPTR_PA15_PUPEN() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x10000000) >> 28
}
func (o *Flash_Type) SetOPTR_TZEN(value uint32) {
	volatile.StoreUint32(&o.OPTR.Reg, volatile.LoadUint32(&o.OPTR.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetOPTR_TZEN() uint32 {
	return (volatile.LoadUint32(&o.OPTR.Reg) & 0x80000000) >> 31
}

// Flash.NSBOOTADD0R: Flash non-secure boot address 0 register
func (o *Flash_Type) SetNSBOOTADD0R_NSBOOTADD0(value uint32) {
	volatile.StoreUint32(&o.NSBOOTADD0R.Reg, volatile.LoadUint32(&o.NSBOOTADD0R.Reg)&^(0xffffff80)|value<<7)
}
func (o *Flash_Type) GetNSBOOTADD0R_NSBOOTADD0() uint32 {
	return (volatile.LoadUint32(&o.NSBOOTADD0R.Reg) & 0xffffff80) >> 7
}

// Flash.NSBOOTADD1R: Flash non-secure boot address 1 register
func (o *Flash_Type) SetNSBOOTADD1R_NSBOOTADD1(value uint32) {
	volatile.StoreUint32(&o.NSBOOTADD1R.Reg, volatile.LoadUint32(&o.NSBOOTADD1R.Reg)&^(0xffffff80)|value<<7)
}
func (o *Flash_Type) GetNSBOOTADD1R_NSBOOTADD1() uint32 {
	return (volatile.LoadUint32(&o.NSBOOTADD1R.Reg) & 0xffffff80) >> 7
}

// Flash.SECBOOTADD0R: FFlash secure boot address 0 register
func (o *Flash_Type) SetSECBOOTADD0R_BOOT_LOCK(value uint32) {
	volatile.StoreUint32(&o.SECBOOTADD0R.Reg, volatile.LoadUint32(&o.SECBOOTADD0R.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECBOOTADD0R_BOOT_LOCK() uint32 {
	return volatile.LoadUint32(&o.SECBOOTADD0R.Reg) & 0x1
}
func (o *Flash_Type) SetSECBOOTADD0R_SECBOOTADD0(value uint32) {
	volatile.StoreUint32(&o.SECBOOTADD0R.Reg, volatile.LoadUint32(&o.SECBOOTADD0R.Reg)&^(0xffffff80)|value<<7)
}
func (o *Flash_Type) GetSECBOOTADD0R_SECBOOTADD0() uint32 {
	return (volatile.LoadUint32(&o.SECBOOTADD0R.Reg) & 0xffffff80) >> 7
}

// Flash.SECWM1R1: Flash bank 1 secure watermak1 register
func (o *Flash_Type) SetSECWM1R1_SECWM1_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM1R1.Reg, volatile.LoadUint32(&o.SECWM1R1.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetSECWM1R1_SECWM1_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM1R1.Reg) & 0x7f
}
func (o *Flash_Type) SetSECWM1R1_SECWM1_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM1R1.Reg, volatile.LoadUint32(&o.SECWM1R1.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetSECWM1R1_SECWM1_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R1.Reg) & 0x7f0000) >> 16
}

// Flash.SECWM1R2: Flash secure watermak1 register 2
func (o *Flash_Type) SetSECWM1R2_PCROP1_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetSECWM1R2_PCROP1_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM1R2.Reg) & 0x7f
}
func (o *Flash_Type) SetSECWM1R2_PCROP1EN(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSECWM1R2_PCROP1EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSECWM1R2_HDP1_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetSECWM1R2_HDP1_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R2.Reg) & 0x7f0000) >> 16
}
func (o *Flash_Type) SetSECWM1R2_HDP1EN(value uint32) {
	volatile.StoreUint32(&o.SECWM1R2.Reg, volatile.LoadUint32(&o.SECWM1R2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSECWM1R2_HDP1EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM1R2.Reg) & 0x80000000) >> 31
}

// Flash.WRP1AR: Flash Bank 1 WRP area A address register
func (o *Flash_Type) SetWRP1AR_WRP1A_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP1AR.Reg, volatile.LoadUint32(&o.WRP1AR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP1AR_WRP1A_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP1AR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP1AR_WRP1A_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP1AR.Reg, volatile.LoadUint32(&o.WRP1AR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP1AR_WRP1A_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP1AR.Reg) & 0x7f0000) >> 16
}

// Flash.WRP1BR: Flash Bank 1 WRP area B address register
func (o *Flash_Type) SetWRP1BR_WRP1B_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP1BR.Reg, volatile.LoadUint32(&o.WRP1BR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP1BR_WRP1B_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP1BR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP1BR_WRP1B_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP1BR.Reg, volatile.LoadUint32(&o.WRP1BR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP1BR_WRP1B_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP1BR.Reg) & 0x7f0000) >> 16
}

// Flash.SECWM2R1: Flash secure watermak2 register
func (o *Flash_Type) SetSECWM2R1_SECWM2_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM2R1.Reg, volatile.LoadUint32(&o.SECWM2R1.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetSECWM2R1_SECWM2_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM2R1.Reg) & 0x7f
}
func (o *Flash_Type) SetSECWM2R1_SECWM2_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM2R1.Reg, volatile.LoadUint32(&o.SECWM2R1.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetSECWM2R1_SECWM2_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R1.Reg) & 0x7f0000) >> 16
}

// Flash.SECWM2R2: Flash secure watermak2 register2
func (o *Flash_Type) SetSECWM2R2_PCROP2_PSTRT(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetSECWM2R2_PCROP2_PSTRT() uint32 {
	return volatile.LoadUint32(&o.SECWM2R2.Reg) & 0x7f
}
func (o *Flash_Type) SetSECWM2R2_PCROP2EN(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0x8000)|value<<15)
}
func (o *Flash_Type) GetSECWM2R2_PCROP2EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R2.Reg) & 0x8000) >> 15
}
func (o *Flash_Type) SetSECWM2R2_HDP2_PEND(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetSECWM2R2_HDP2_PEND() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R2.Reg) & 0x7f0000) >> 16
}
func (o *Flash_Type) SetSECWM2R2_HDP2EN(value uint32) {
	volatile.StoreUint32(&o.SECWM2R2.Reg, volatile.LoadUint32(&o.SECWM2R2.Reg)&^(0x80000000)|value<<31)
}
func (o *Flash_Type) GetSECWM2R2_HDP2EN() uint32 {
	return (volatile.LoadUint32(&o.SECWM2R2.Reg) & 0x80000000) >> 31
}

// Flash.WRP2AR: Flash WPR2 area A address register
func (o *Flash_Type) SetWRP2AR_WRP2A_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP2AR.Reg, volatile.LoadUint32(&o.WRP2AR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP2AR_WRP2A_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP2AR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP2AR_WRP2A_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP2AR.Reg, volatile.LoadUint32(&o.WRP2AR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP2AR_WRP2A_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP2AR.Reg) & 0x7f0000) >> 16
}

// Flash.WRP2BR: Flash WPR2 area B address register
func (o *Flash_Type) SetWRP2BR_WRP2B_PSTRT(value uint32) {
	volatile.StoreUint32(&o.WRP2BR.Reg, volatile.LoadUint32(&o.WRP2BR.Reg)&^(0x7f)|value)
}
func (o *Flash_Type) GetWRP2BR_WRP2B_PSTRT() uint32 {
	return volatile.LoadUint32(&o.WRP2BR.Reg) & 0x7f
}
func (o *Flash_Type) SetWRP2BR_WRP2B_PEND(value uint32) {
	volatile.StoreUint32(&o.WRP2BR.Reg, volatile.LoadUint32(&o.WRP2BR.Reg)&^(0x7f0000)|value<<16)
}
func (o *Flash_Type) GetWRP2BR_WRP2B_PEND() uint32 {
	return (volatile.LoadUint32(&o.WRP2BR.Reg) & 0x7f0000) >> 16
}

// Flash.SECBB1R1: FLASH secure block based bank 1
func (o *Flash_Type) SetSECBB1R1(value uint32) {
	volatile.StoreUint32(&o.SECBB1R1.Reg, value)
}
func (o *Flash_Type) GetSECBB1R1() uint32 {
	return volatile.LoadUint32(&o.SECBB1R1.Reg)
}

// Flash.SECBB1R2: FLASH secure block based bank 1
func (o *Flash_Type) SetSECBB1R2(value uint32) {
	volatile.StoreUint32(&o.SECBB1R2.Reg, value)
}
func (o *Flash_Type) GetSECBB1R2() uint32 {
	return volatile.LoadUint32(&o.SECBB1R2.Reg)
}

// Flash.SECBB1R3: FLASH secure block based bank 1
func (o *Flash_Type) SetSECBB1R3(value uint32) {
	volatile.StoreUint32(&o.SECBB1R3.Reg, value)
}
func (o *Flash_Type) GetSECBB1R3() uint32 {
	return volatile.LoadUint32(&o.SECBB1R3.Reg)
}

// Flash.SECBB1R4: FLASH secure block based bank 1
func (o *Flash_Type) SetSECBB1R4(value uint32) {
	volatile.StoreUint32(&o.SECBB1R4.Reg, value)
}
func (o *Flash_Type) GetSECBB1R4() uint32 {
	return volatile.LoadUint32(&o.SECBB1R4.Reg)
}

// Flash.SECBB2R1: FLASH secure block based bank 2
func (o *Flash_Type) SetSECBB2R1(value uint32) {
	volatile.StoreUint32(&o.SECBB2R1.Reg, value)
}
func (o *Flash_Type) GetSECBB2R1() uint32 {
	return volatile.LoadUint32(&o.SECBB2R1.Reg)
}

// Flash.SECBB2R2: FLASH secure block based bank 2
func (o *Flash_Type) SetSECBB2R2(value uint32) {
	volatile.StoreUint32(&o.SECBB2R2.Reg, value)
}
func (o *Flash_Type) GetSECBB2R2() uint32 {
	return volatile.LoadUint32(&o.SECBB2R2.Reg)
}

// Flash.SECBB2R3: FLASH secure block based bank 2
func (o *Flash_Type) SetSECBB2R3(value uint32) {
	volatile.StoreUint32(&o.SECBB2R3.Reg, value)
}
func (o *Flash_Type) GetSECBB2R3() uint32 {
	return volatile.LoadUint32(&o.SECBB2R3.Reg)
}

// Flash.SECBB2R4: FLASH secure block based bank 2
func (o *Flash_Type) SetSECBB2R4(value uint32) {
	volatile.StoreUint32(&o.SECBB2R4.Reg, value)
}
func (o *Flash_Type) GetSECBB2R4() uint32 {
	return volatile.LoadUint32(&o.SECBB2R4.Reg)
}

// Flash.SECHDPCR: FLASH secure HDP control register
func (o *Flash_Type) SetSECHDPCR_HDP1_ACCDIS(value uint32) {
	volatile.StoreUint32(&o.SECHDPCR.Reg, volatile.LoadUint32(&o.SECHDPCR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetSECHDPCR_HDP1_ACCDIS() uint32 {
	return volatile.LoadUint32(&o.SECHDPCR.Reg) & 0x1
}
func (o *Flash_Type) SetSECHDPCR_HDP2_ACCDIS(value uint32) {
	volatile.StoreUint32(&o.SECHDPCR.Reg, volatile.LoadUint32(&o.SECHDPCR.Reg)&^(0x2)|value<<1)
}
func (o *Flash_Type) GetSECHDPCR_HDP2_ACCDIS() uint32 {
	return (volatile.LoadUint32(&o.SECHDPCR.Reg) & 0x2) >> 1
}

// Flash.PRIVCFGR: Power privilege configuration register
func (o *Flash_Type) SetPRIVCFGR_PRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x1)|value)
}
func (o *Flash_Type) GetPRIVCFGR_PRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x1
}

// FMC
type FMC_Type struct {
	BCR1    volatile.Register32 // 0x0
	BTR1    volatile.Register32 // 0x4
	BCR2    volatile.Register32 // 0x8
	BTR2    volatile.Register32 // 0xC
	BCR3    volatile.Register32 // 0x10
	BTR3    volatile.Register32 // 0x14
	BCR4    volatile.Register32 // 0x18
	BTR4    volatile.Register32 // 0x1C
	PCSCNTR volatile.Register32 // 0x20
	_       [92]byte
	PCR     volatile.Register32 // 0x80
	SR      volatile.Register32 // 0x84
	PMEM    volatile.Register32 // 0x88
	PATT    volatile.Register32 // 0x8C
	_       [4]byte
	ECCR    volatile.Register32 // 0x94
	_       [108]byte
	BWTR1   volatile.Register32 // 0x104
	_       [4]byte
	BWTR2   volatile.Register32 // 0x10C
	_       [4]byte
	BWTR3   volatile.Register32 // 0x114
	_       [4]byte
	BWTR4   volatile.Register32 // 0x11C
}

// FMC.BCR1: FMC_BCR1
func (o *FMC_Type) SetBCR1_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR1_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR1.Reg) & 0x1
}
func (o *FMC_Type) SetBCR1_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR1_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR1_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR1_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR1_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR1_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR1_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR1_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR1_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR1_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR1_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR1_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR1_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR1_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR1_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR1_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR1_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR1_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR1_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR1_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR1_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR1_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR1_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR1_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR1_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR1_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR1_CCLKEN(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x100000)|value<<20)
}
func (o *FMC_Type) GetBCR1_CCLKEN() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x100000) >> 20
}
func (o *FMC_Type) SetBCR1_WFDIS(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0x200000)|value<<21)
}
func (o *FMC_Type) GetBCR1_WFDIS() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0x200000) >> 21
}
func (o *FMC_Type) SetBCR1_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR1.Reg, volatile.LoadUint32(&o.BCR1.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR1_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR1.Reg) & 0xc00000) >> 22
}

// FMC.BTR1: SRAM/NOR-flash chip-select timing registers for bank %s
func (o *FMC_Type) SetBTR1_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR1_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR1.Reg) & 0xf
}
func (o *FMC_Type) SetBTR1_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR1_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR1_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR1_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR1_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR1_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR1_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR1_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR1_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR1_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR1_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR1_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR1_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR1.Reg, volatile.LoadUint32(&o.BTR1.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR1_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR1.Reg) & 0xc0000000) >> 30
}

// FMC.BCR2: SRAM/NOR-Flash chip-select control register %s
func (o *FMC_Type) SetBCR2_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR2_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR2.Reg) & 0x1
}
func (o *FMC_Type) SetBCR2_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR2_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR2_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR2_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR2_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR2_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR2_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR2_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR2_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR2_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR2_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR2_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR2_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR2_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR2_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR2_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR2_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR2_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR2_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR2_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR2_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR2_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR2_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR2_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR2_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR2_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR2_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR2.Reg, volatile.LoadUint32(&o.BCR2.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR2_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR2.Reg) & 0xc00000) >> 22
}

// FMC.BTR2: SRAM/NOR-flash chip-select timing registers for bank %s
func (o *FMC_Type) SetBTR2_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR2_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR2.Reg) & 0xf
}
func (o *FMC_Type) SetBTR2_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR2_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR2_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR2_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR2_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR2_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR2_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR2_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR2_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR2_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR2_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR2_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR2_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR2.Reg, volatile.LoadUint32(&o.BTR2.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR2_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR2.Reg) & 0xc0000000) >> 30
}

// FMC.BCR3: SRAM/NOR-Flash chip-select control register %s
func (o *FMC_Type) SetBCR3_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR3_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR3.Reg) & 0x1
}
func (o *FMC_Type) SetBCR3_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR3_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR3_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR3_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR3_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR3_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR3_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR3_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR3_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR3_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR3_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR3_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR3_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR3_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR3_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR3_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR3_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR3_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR3_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR3_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR3_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR3_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR3_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR3_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR3_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR3_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR3_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR3.Reg, volatile.LoadUint32(&o.BCR3.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR3_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR3.Reg) & 0xc00000) >> 22
}

// FMC.BTR3: SRAM/NOR-flash chip-select timing registers for bank %s
func (o *FMC_Type) SetBTR3_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR3_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR3.Reg) & 0xf
}
func (o *FMC_Type) SetBTR3_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR3_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR3_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR3_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR3_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR3_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR3_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR3_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR3_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR3_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR3_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR3_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR3_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR3.Reg, volatile.LoadUint32(&o.BTR3.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR3_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR3.Reg) & 0xc0000000) >> 30
}

// FMC.BCR4: SRAM/NOR-Flash chip-select control register %s
func (o *FMC_Type) SetBCR4_MBKEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetBCR4_MBKEN() uint32 {
	return volatile.LoadUint32(&o.BCR4.Reg) & 0x1
}
func (o *FMC_Type) SetBCR4_MUXEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetBCR4_MUXEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetBCR4_MTYP(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0xc)|value<<2)
}
func (o *FMC_Type) GetBCR4_MTYP() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0xc) >> 2
}
func (o *FMC_Type) SetBCR4_MWID(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetBCR4_MWID() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetBCR4_FACCEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetBCR4_FACCEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetBCR4_BURSTEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x100)|value<<8)
}
func (o *FMC_Type) GetBCR4_BURSTEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x100) >> 8
}
func (o *FMC_Type) SetBCR4_WAITPOL(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x200)|value<<9)
}
func (o *FMC_Type) GetBCR4_WAITPOL() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x200) >> 9
}
func (o *FMC_Type) SetBCR4_WAITCFG(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x800)|value<<11)
}
func (o *FMC_Type) GetBCR4_WAITCFG() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x800) >> 11
}
func (o *FMC_Type) SetBCR4_WREN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x1000)|value<<12)
}
func (o *FMC_Type) GetBCR4_WREN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x1000) >> 12
}
func (o *FMC_Type) SetBCR4_WAITEN(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x2000)|value<<13)
}
func (o *FMC_Type) GetBCR4_WAITEN() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x2000) >> 13
}
func (o *FMC_Type) SetBCR4_EXTMOD(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x4000)|value<<14)
}
func (o *FMC_Type) GetBCR4_EXTMOD() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x4000) >> 14
}
func (o *FMC_Type) SetBCR4_ASYNCWAIT(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x8000)|value<<15)
}
func (o *FMC_Type) GetBCR4_ASYNCWAIT() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x8000) >> 15
}
func (o *FMC_Type) SetBCR4_CPSIZE(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x70000)|value<<16)
}
func (o *FMC_Type) GetBCR4_CPSIZE() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x70000) >> 16
}
func (o *FMC_Type) SetBCR4_CBURSTRW(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetBCR4_CBURSTRW() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetBCR4_NBLSET(value uint32) {
	volatile.StoreUint32(&o.BCR4.Reg, volatile.LoadUint32(&o.BCR4.Reg)&^(0xc00000)|value<<22)
}
func (o *FMC_Type) GetBCR4_NBLSET() uint32 {
	return (volatile.LoadUint32(&o.BCR4.Reg) & 0xc00000) >> 22
}

// FMC.BTR4: SRAM/NOR-flash chip-select timing registers for bank %s
func (o *FMC_Type) SetBTR4_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBTR4_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BTR4.Reg) & 0xf
}
func (o *FMC_Type) SetBTR4_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBTR4_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBTR4_DATAST(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBTR4_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBTR4_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBTR4_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBTR4_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf00000)|value<<20)
}
func (o *FMC_Type) GetBTR4_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf00000) >> 20
}
func (o *FMC_Type) SetBTR4_DATLAT(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xf000000)|value<<24)
}
func (o *FMC_Type) GetBTR4_DATLAT() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xf000000) >> 24
}
func (o *FMC_Type) SetBTR4_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBTR4_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0x30000000) >> 28
}
func (o *FMC_Type) SetBTR4_DATAHLD(value uint32) {
	volatile.StoreUint32(&o.BTR4.Reg, volatile.LoadUint32(&o.BTR4.Reg)&^(0xc0000000)|value<<30)
}
func (o *FMC_Type) GetBTR4_DATAHLD() uint32 {
	return (volatile.LoadUint32(&o.BTR4.Reg) & 0xc0000000) >> 30
}

// FMC.PCSCNTR: PCSCNTR
func (o *FMC_Type) SetPCSCNTR_CSCOUNT(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0xffff)|value)
}
func (o *FMC_Type) GetPCSCNTR_CSCOUNT() uint32 {
	return volatile.LoadUint32(&o.PCSCNTR.Reg) & 0xffff
}
func (o *FMC_Type) SetPCSCNTR_CNTB1EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x20000)|value<<17)
}
func (o *FMC_Type) GetPCSCNTR_CNTB1EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x20000) >> 17
}
func (o *FMC_Type) SetPCSCNTR_CNTB2EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x40000)|value<<18)
}
func (o *FMC_Type) GetPCSCNTR_CNTB2EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x40000) >> 18
}
func (o *FMC_Type) SetPCSCNTR_CNTB3EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x80000)|value<<19)
}
func (o *FMC_Type) GetPCSCNTR_CNTB3EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x80000) >> 19
}
func (o *FMC_Type) SetPCSCNTR_CNTB4EN(value uint32) {
	volatile.StoreUint32(&o.PCSCNTR.Reg, volatile.LoadUint32(&o.PCSCNTR.Reg)&^(0x100000)|value<<20)
}
func (o *FMC_Type) GetPCSCNTR_CNTB4EN() uint32 {
	return (volatile.LoadUint32(&o.PCSCNTR.Reg) & 0x100000) >> 20
}

// FMC.PCR: NAND Flash control registers
func (o *FMC_Type) SetPCR_PWAITEN(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetPCR_PWAITEN() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetPCR_PBKEN(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x4)|value<<2)
}
func (o *FMC_Type) GetPCR_PBKEN() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x4) >> 2
}
func (o *FMC_Type) SetPCR_PTYP(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x8)|value<<3)
}
func (o *FMC_Type) GetPCR_PTYP() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x8) >> 3
}
func (o *FMC_Type) SetPCR_PWID(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x30)|value<<4)
}
func (o *FMC_Type) GetPCR_PWID() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x30) >> 4
}
func (o *FMC_Type) SetPCR_ECCEN(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetPCR_ECCEN() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x40) >> 6
}
func (o *FMC_Type) SetPCR_TCLR(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x1e00)|value<<9)
}
func (o *FMC_Type) GetPCR_TCLR() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x1e00) >> 9
}
func (o *FMC_Type) SetPCR_TAR(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0x1e000)|value<<13)
}
func (o *FMC_Type) GetPCR_TAR() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0x1e000) >> 13
}
func (o *FMC_Type) SetPCR_ECCPS(value uint32) {
	volatile.StoreUint32(&o.PCR.Reg, volatile.LoadUint32(&o.PCR.Reg)&^(0xe0000)|value<<17)
}
func (o *FMC_Type) GetPCR_ECCPS() uint32 {
	return (volatile.LoadUint32(&o.PCR.Reg) & 0xe0000) >> 17
}

// FMC.SR: This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
func (o *FMC_Type) SetSR_IRS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *FMC_Type) GetSR_IRS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *FMC_Type) SetSR_ILS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *FMC_Type) GetSR_ILS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *FMC_Type) SetSR_IFS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *FMC_Type) GetSR_IFS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *FMC_Type) SetSR_IREN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *FMC_Type) GetSR_IREN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *FMC_Type) SetSR_ILEN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *FMC_Type) GetSR_ILEN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *FMC_Type) SetSR_IFEN(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *FMC_Type) GetSR_IFEN() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *FMC_Type) SetSR_FEMPT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *FMC_Type) GetSR_FEMPT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}

// FMC.PMEM: The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
func (o *FMC_Type) SetPMEM_MEMSET(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff)|value)
}
func (o *FMC_Type) GetPMEM_MEMSET() uint32 {
	return volatile.LoadUint32(&o.PMEM.Reg) & 0xff
}
func (o *FMC_Type) SetPMEM_MEMWAIT(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetPMEM_MEMWAIT() uint32 {
	return (volatile.LoadUint32(&o.PMEM.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetPMEM_MEMHOLD(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff0000)|value<<16)
}
func (o *FMC_Type) GetPMEM_MEMHOLD() uint32 {
	return (volatile.LoadUint32(&o.PMEM.Reg) & 0xff0000) >> 16
}
func (o *FMC_Type) SetPMEM_MEMHIZ(value uint32) {
	volatile.StoreUint32(&o.PMEM.Reg, volatile.LoadUint32(&o.PMEM.Reg)&^(0xff000000)|value<<24)
}
func (o *FMC_Type) GetPMEM_MEMHIZ() uint32 {
	return (volatile.LoadUint32(&o.PMEM.Reg) & 0xff000000) >> 24
}

// FMC.PATT: The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
func (o *FMC_Type) SetPATT_ATTSET(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff)|value)
}
func (o *FMC_Type) GetPATT_ATTSET() uint32 {
	return volatile.LoadUint32(&o.PATT.Reg) & 0xff
}
func (o *FMC_Type) SetPATT_ATTWAIT(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetPATT_ATTWAIT() uint32 {
	return (volatile.LoadUint32(&o.PATT.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetPATT_ATTHOLD(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff0000)|value<<16)
}
func (o *FMC_Type) GetPATT_ATTHOLD() uint32 {
	return (volatile.LoadUint32(&o.PATT.Reg) & 0xff0000) >> 16
}
func (o *FMC_Type) SetPATT_ATTHIZ(value uint32) {
	volatile.StoreUint32(&o.PATT.Reg, volatile.LoadUint32(&o.PATT.Reg)&^(0xff000000)|value<<24)
}
func (o *FMC_Type) GetPATT_ATTHIZ() uint32 {
	return (volatile.LoadUint32(&o.PATT.Reg) & 0xff000000) >> 24
}

// FMC.ECCR: This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
func (o *FMC_Type) SetECCR(value uint32) {
	volatile.StoreUint32(&o.ECCR.Reg, value)
}
func (o *FMC_Type) GetECCR() uint32 {
	return volatile.LoadUint32(&o.ECCR.Reg)
}

// FMC.BWTR1: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
func (o *FMC_Type) SetBWTR1_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR1_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR1.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR1_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR1_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR1_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR1_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR1_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR1_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR1_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR1.Reg, volatile.LoadUint32(&o.BWTR1.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR1_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR1.Reg) & 0x30000000) >> 28
}

// FMC.BWTR2: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
func (o *FMC_Type) SetBWTR2_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR2_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR2.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR2_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR2_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR2_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR2_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR2_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR2_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR2_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR2.Reg, volatile.LoadUint32(&o.BWTR2.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR2_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR2.Reg) & 0x30000000) >> 28
}

// FMC.BWTR3: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
func (o *FMC_Type) SetBWTR3_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR3_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR3.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR3_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR3_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR3_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR3_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR3_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR3_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR3_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR3.Reg, volatile.LoadUint32(&o.BWTR3.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR3_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR3.Reg) & 0x30000000) >> 28
}

// FMC.BWTR4: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
func (o *FMC_Type) SetBWTR4_ADDSET(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xf)|value)
}
func (o *FMC_Type) GetBWTR4_ADDSET() uint32 {
	return volatile.LoadUint32(&o.BWTR4.Reg) & 0xf
}
func (o *FMC_Type) SetBWTR4_ADDHLD(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xf0)|value<<4)
}
func (o *FMC_Type) GetBWTR4_ADDHLD() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0xf0) >> 4
}
func (o *FMC_Type) SetBWTR4_DATAST(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xff00)|value<<8)
}
func (o *FMC_Type) GetBWTR4_DATAST() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0xff00) >> 8
}
func (o *FMC_Type) SetBWTR4_BUSTURN(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0xf0000)|value<<16)
}
func (o *FMC_Type) GetBWTR4_BUSTURN() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0xf0000) >> 16
}
func (o *FMC_Type) SetBWTR4_ACCMOD(value uint32) {
	volatile.StoreUint32(&o.BWTR4.Reg, volatile.LoadUint32(&o.BWTR4.Reg)&^(0x30000000)|value<<28)
}
func (o *FMC_Type) GetBWTR4_ACCMOD() uint32 {
	return (volatile.LoadUint32(&o.BWTR4.Reg) & 0x30000000) >> 28
}

// General-purpose I/Os
type GPIO_Type struct {
	MODER   volatile.Register32 // 0x0
	OTYPER  volatile.Register32 // 0x4
	OSPEEDR volatile.Register32 // 0x8
	PUPDR   volatile.Register32 // 0xC
	IDR     volatile.Register32 // 0x10
	ODR     volatile.Register32 // 0x14
	BSRR    volatile.Register32 // 0x18
	LCKR    volatile.Register32 // 0x1C
	AFRL    volatile.Register32 // 0x20
	AFRH    volatile.Register32 // 0x24
	BRR     volatile.Register32 // 0x28
	_       [4]byte
	SECCFGR volatile.Register32 // 0x30
}

// GPIO.MODER: GPIO port mode register
func (o *GPIO_Type) SetMODER_MODER0(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetMODER_MODER0() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetMODER_MODER1(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetMODER_MODER1() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetMODER_MODER2(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetMODER_MODER2() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetMODER_MODER3(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetMODER_MODER3() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetMODER_MODER4(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetMODER_MODER4() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetMODER_MODER5(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetMODER_MODER5() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetMODER_MODER6(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetMODER_MODER6() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetMODER_MODER7(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetMODER_MODER7() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetMODER_MODER8(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetMODER_MODER8() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetMODER_MODER9(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetMODER_MODER9() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetMODER_MODER10(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetMODER_MODER10() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetMODER_MODER11(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetMODER_MODER11() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetMODER_MODER12(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetMODER_MODER12() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetMODER_MODER13(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetMODER_MODER13() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetMODER_MODER14(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetMODER_MODER14() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetMODER_MODER15(value uint32) {
	volatile.StoreUint32(&o.MODER.Reg, volatile.LoadUint32(&o.MODER.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetMODER_MODER15() uint32 {
	return (volatile.LoadUint32(&o.MODER.Reg) & 0x0) >> 32
}

// GPIO.OTYPER: GPIO port output type register
func (o *GPIO_Type) SetOTYPER_OT0(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetOTYPER_OT0() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetOTYPER_OT1(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetOTYPER_OT1() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetOTYPER_OT2(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetOTYPER_OT2() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetOTYPER_OT3(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetOTYPER_OT3() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetOTYPER_OT4(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetOTYPER_OT4() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetOTYPER_OT5(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetOTYPER_OT5() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetOTYPER_OT6(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetOTYPER_OT6() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetOTYPER_OT7(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetOTYPER_OT7() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetOTYPER_OT8(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetOTYPER_OT8() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetOTYPER_OT9(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetOTYPER_OT9() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetOTYPER_OT10(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetOTYPER_OT10() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetOTYPER_OT11(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetOTYPER_OT11() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetOTYPER_OT12(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetOTYPER_OT12() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetOTYPER_OT13(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetOTYPER_OT13() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetOTYPER_OT14(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetOTYPER_OT14() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetOTYPER_OT15(value uint32) {
	volatile.StoreUint32(&o.OTYPER.Reg, volatile.LoadUint32(&o.OTYPER.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetOTYPER_OT15() uint32 {
	return (volatile.LoadUint32(&o.OTYPER.Reg) & 0x10000) >> 16
}

// GPIO.OSPEEDR: GPIO port output speed register
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR0(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR0() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR1(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR1() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR2(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR2() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR3(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR3() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR4(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR4() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR5(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR5() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR6(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR6() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR7(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR7() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR8(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR8() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR9(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR9() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR10(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR10() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR11(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR11() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR12(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR12() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR13(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR13() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR14(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR14() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetOSPEEDR_OSPEEDR15(value uint32) {
	volatile.StoreUint32(&o.OSPEEDR.Reg, volatile.LoadUint32(&o.OSPEEDR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetOSPEEDR_OSPEEDR15() uint32 {
	return (volatile.LoadUint32(&o.OSPEEDR.Reg) & 0x0) >> 32
}

// GPIO.PUPDR: GPIO port pull-up/pull-down register
func (o *GPIO_Type) SetPUPDR_PUPDR0(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc)|value<<2)
}
func (o *GPIO_Type) GetPUPDR_PUPDR0() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc) >> 2
}
func (o *GPIO_Type) SetPUPDR_PUPDR1(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30)|value<<4)
}
func (o *GPIO_Type) GetPUPDR_PUPDR1() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30) >> 4
}
func (o *GPIO_Type) SetPUPDR_PUPDR2(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0)|value<<6)
}
func (o *GPIO_Type) GetPUPDR_PUPDR2() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0) >> 6
}
func (o *GPIO_Type) SetPUPDR_PUPDR3(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300)|value<<8)
}
func (o *GPIO_Type) GetPUPDR_PUPDR3() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300) >> 8
}
func (o *GPIO_Type) SetPUPDR_PUPDR4(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00)|value<<10)
}
func (o *GPIO_Type) GetPUPDR_PUPDR4() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00) >> 10
}
func (o *GPIO_Type) SetPUPDR_PUPDR5(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000)|value<<12)
}
func (o *GPIO_Type) GetPUPDR_PUPDR5() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000) >> 12
}
func (o *GPIO_Type) SetPUPDR_PUPDR6(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc000)|value<<14)
}
func (o *GPIO_Type) GetPUPDR_PUPDR6() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc000) >> 14
}
func (o *GPIO_Type) SetPUPDR_PUPDR7(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30000)|value<<16)
}
func (o *GPIO_Type) GetPUPDR_PUPDR7() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30000) >> 16
}
func (o *GPIO_Type) SetPUPDR_PUPDR8(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0000)|value<<18)
}
func (o *GPIO_Type) GetPUPDR_PUPDR8() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0000) >> 18
}
func (o *GPIO_Type) SetPUPDR_PUPDR9(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x300000)|value<<20)
}
func (o *GPIO_Type) GetPUPDR_PUPDR9() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x300000) >> 20
}
func (o *GPIO_Type) SetPUPDR_PUPDR10(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc00000)|value<<22)
}
func (o *GPIO_Type) GetPUPDR_PUPDR10() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc00000) >> 22
}
func (o *GPIO_Type) SetPUPDR_PUPDR11(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x3000000)|value<<24)
}
func (o *GPIO_Type) GetPUPDR_PUPDR11() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x3000000) >> 24
}
func (o *GPIO_Type) SetPUPDR_PUPDR12(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc000000)|value<<26)
}
func (o *GPIO_Type) GetPUPDR_PUPDR12() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc000000) >> 26
}
func (o *GPIO_Type) SetPUPDR_PUPDR13(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x30000000)|value<<28)
}
func (o *GPIO_Type) GetPUPDR_PUPDR13() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x30000000) >> 28
}
func (o *GPIO_Type) SetPUPDR_PUPDR14(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0xc0000000)|value<<30)
}
func (o *GPIO_Type) GetPUPDR_PUPDR14() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0xc0000000) >> 30
}
func (o *GPIO_Type) SetPUPDR_PUPDR15(value uint32) {
	volatile.StoreUint32(&o.PUPDR.Reg, volatile.LoadUint32(&o.PUPDR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetPUPDR_PUPDR15() uint32 {
	return (volatile.LoadUint32(&o.PUPDR.Reg) & 0x0) >> 32
}

// GPIO.IDR: GPIO port input data register
func (o *GPIO_Type) SetIDR_IDR0(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetIDR_IDR0() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetIDR_IDR1(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetIDR_IDR1() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetIDR_IDR2(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetIDR_IDR2() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetIDR_IDR3(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetIDR_IDR3() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetIDR_IDR4(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetIDR_IDR4() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetIDR_IDR5(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetIDR_IDR5() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetIDR_IDR6(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetIDR_IDR6() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetIDR_IDR7(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetIDR_IDR7() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetIDR_IDR8(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetIDR_IDR8() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetIDR_IDR9(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetIDR_IDR9() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetIDR_IDR10(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetIDR_IDR10() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetIDR_IDR11(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetIDR_IDR11() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetIDR_IDR12(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetIDR_IDR12() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetIDR_IDR13(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetIDR_IDR13() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetIDR_IDR14(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetIDR_IDR14() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetIDR_IDR15(value uint32) {
	volatile.StoreUint32(&o.IDR.Reg, volatile.LoadUint32(&o.IDR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetIDR_IDR15() uint32 {
	return (volatile.LoadUint32(&o.IDR.Reg) & 0x10000) >> 16
}

// GPIO.ODR: GPIO port output data register
func (o *GPIO_Type) SetODR_ODR0(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetODR_ODR0() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetODR_ODR1(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetODR_ODR1() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetODR_ODR2(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetODR_ODR2() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetODR_ODR3(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetODR_ODR3() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetODR_ODR4(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetODR_ODR4() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetODR_ODR5(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetODR_ODR5() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetODR_ODR6(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetODR_ODR6() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetODR_ODR7(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetODR_ODR7() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetODR_ODR8(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetODR_ODR8() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetODR_ODR9(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetODR_ODR9() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetODR_ODR10(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetODR_ODR10() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetODR_ODR11(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetODR_ODR11() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetODR_ODR12(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetODR_ODR12() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetODR_ODR13(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetODR_ODR13() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetODR_ODR14(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetODR_ODR14() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetODR_ODR15(value uint32) {
	volatile.StoreUint32(&o.ODR.Reg, volatile.LoadUint32(&o.ODR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetODR_ODR15() uint32 {
	return (volatile.LoadUint32(&o.ODR.Reg) & 0x10000) >> 16
}

// GPIO.BSRR: GPIO port bit set/reset register
func (o *GPIO_Type) SetBSRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000)|value<<17)
}
func (o *GPIO_Type) GetBSRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000) >> 17
}
func (o *GPIO_Type) SetBSRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000)|value<<18)
}
func (o *GPIO_Type) GetBSRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000) >> 18
}
func (o *GPIO_Type) SetBSRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000)|value<<19)
}
func (o *GPIO_Type) GetBSRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000) >> 19
}
func (o *GPIO_Type) SetBSRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100000)|value<<20)
}
func (o *GPIO_Type) GetBSRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100000) >> 20
}
func (o *GPIO_Type) SetBSRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200000)|value<<21)
}
func (o *GPIO_Type) GetBSRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200000) >> 21
}
func (o *GPIO_Type) SetBSRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400000)|value<<22)
}
func (o *GPIO_Type) GetBSRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400000) >> 22
}
func (o *GPIO_Type) SetBSRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800000)|value<<23)
}
func (o *GPIO_Type) GetBSRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800000) >> 23
}
func (o *GPIO_Type) SetBSRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000000)|value<<24)
}
func (o *GPIO_Type) GetBSRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000000) >> 24
}
func (o *GPIO_Type) SetBSRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000000)|value<<25)
}
func (o *GPIO_Type) GetBSRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000000) >> 25
}
func (o *GPIO_Type) SetBSRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000000)|value<<26)
}
func (o *GPIO_Type) GetBSRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000000) >> 26
}
func (o *GPIO_Type) SetBSRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000000)|value<<27)
}
func (o *GPIO_Type) GetBSRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000000) >> 27
}
func (o *GPIO_Type) SetBSRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000000)|value<<28)
}
func (o *GPIO_Type) GetBSRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000000) >> 28
}
func (o *GPIO_Type) SetBSRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20000000)|value<<29)
}
func (o *GPIO_Type) GetBSRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20000000) >> 29
}
func (o *GPIO_Type) SetBSRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40000000)|value<<30)
}
func (o *GPIO_Type) GetBSRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40000000) >> 30
}
func (o *GPIO_Type) SetBSRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80000000)|value<<31)
}
func (o *GPIO_Type) GetBSRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80000000) >> 31
}
func (o *GPIO_Type) SetBSRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetBSRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x0) >> 32
}
func (o *GPIO_Type) SetBSRR_BS0(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBSRR_BS0() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBSRR_BS1(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBSRR_BS1() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBSRR_BS2(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBSRR_BS2() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBSRR_BS3(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBSRR_BS3() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBSRR_BS4(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBSRR_BS4() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBSRR_BS5(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBSRR_BS5() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBSRR_BS6(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBSRR_BS6() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBSRR_BS7(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBSRR_BS7() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBSRR_BS8(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBSRR_BS8() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBSRR_BS9(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBSRR_BS9() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBSRR_BS10(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBSRR_BS10() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBSRR_BS11(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBSRR_BS11() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetBSRR_BS12(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetBSRR_BS12() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetBSRR_BS13(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetBSRR_BS13() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetBSRR_BS14(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetBSRR_BS14() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetBSRR_BS15(value uint32) {
	volatile.StoreUint32(&o.BSRR.Reg, volatile.LoadUint32(&o.BSRR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetBSRR_BS15() uint32 {
	return (volatile.LoadUint32(&o.BSRR.Reg) & 0x10000) >> 16
}

// GPIO.LCKR: GPIO port configuration lock register
func (o *GPIO_Type) SetLCKR_LCKK(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetLCKR_LCKK() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10000) >> 16
}
func (o *GPIO_Type) SetLCKR_LCK0(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetLCKR_LCK0() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetLCKR_LCK1(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetLCKR_LCK1() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetLCKR_LCK2(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetLCKR_LCK2() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetLCKR_LCK3(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetLCKR_LCK3() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetLCKR_LCK4(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetLCKR_LCK4() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetLCKR_LCK5(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetLCKR_LCK5() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetLCKR_LCK6(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetLCKR_LCK6() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetLCKR_LCK7(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetLCKR_LCK7() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetLCKR_LCK8(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetLCKR_LCK8() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetLCKR_LCK9(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetLCKR_LCK9() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetLCKR_LCK10(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetLCKR_LCK10() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetLCKR_LCK11(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetLCKR_LCK11() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetLCKR_LCK12(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetLCKR_LCK12() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetLCKR_LCK13(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetLCKR_LCK13() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetLCKR_LCK14(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetLCKR_LCK14() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetLCKR_LCK15(value uint32) {
	volatile.StoreUint32(&o.LCKR.Reg, volatile.LoadUint32(&o.LCKR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetLCKR_LCK15() uint32 {
	return (volatile.LoadUint32(&o.LCKR.Reg) & 0x10000) >> 16
}

// GPIO.AFRL: GPIO alternate function low register
func (o *GPIO_Type) SetAFRL_AFREL0(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRL_AFREL0() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRL_AFREL1(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRL_AFREL1() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRL_AFREL2(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRL_AFREL2() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRL_AFREL3(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRL_AFREL3() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0000) >> 16
}
func (o *GPIO_Type) SetAFRL_AFREL4(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf00000)|value<<20)
}
func (o *GPIO_Type) GetAFRL_AFREL4() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf00000) >> 20
}
func (o *GPIO_Type) SetAFRL_AFREL5(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf000000)|value<<24)
}
func (o *GPIO_Type) GetAFRL_AFREL5() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf000000) >> 24
}
func (o *GPIO_Type) SetAFRL_AFREL6(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0xf0000000)|value<<28)
}
func (o *GPIO_Type) GetAFRL_AFREL6() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0xf0000000) >> 28
}
func (o *GPIO_Type) SetAFRL_AFREL7(value uint32) {
	volatile.StoreUint32(&o.AFRL.Reg, volatile.LoadUint32(&o.AFRL.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetAFRL_AFREL7() uint32 {
	return (volatile.LoadUint32(&o.AFRL.Reg) & 0x0) >> 32
}

// GPIO.AFRH: GPIO alternate function high register
func (o *GPIO_Type) SetAFRH_AFREL8(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0)|value<<4)
}
func (o *GPIO_Type) GetAFRH_AFREL8() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0) >> 4
}
func (o *GPIO_Type) SetAFRH_AFREL9(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf00)|value<<8)
}
func (o *GPIO_Type) GetAFRH_AFREL9() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf00) >> 8
}
func (o *GPIO_Type) SetAFRH_AFREL10(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf000)|value<<12)
}
func (o *GPIO_Type) GetAFRH_AFREL10() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf000) >> 12
}
func (o *GPIO_Type) SetAFRH_AFREL11(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0000)|value<<16)
}
func (o *GPIO_Type) GetAFRH_AFREL11() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0000) >> 16
}
func (o *GPIO_Type) SetAFRH_AFREL12(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf00000)|value<<20)
}
func (o *GPIO_Type) GetAFRH_AFREL12() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf00000) >> 20
}
func (o *GPIO_Type) SetAFRH_AFREL13(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf000000)|value<<24)
}
func (o *GPIO_Type) GetAFRH_AFREL13() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf000000) >> 24
}
func (o *GPIO_Type) SetAFRH_AFREL14(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0xf0000000)|value<<28)
}
func (o *GPIO_Type) GetAFRH_AFREL14() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0xf0000000) >> 28
}
func (o *GPIO_Type) SetAFRH_AFREL15(value uint32) {
	volatile.StoreUint32(&o.AFRH.Reg, volatile.LoadUint32(&o.AFRH.Reg)&^(0x0)|value<<32)
}
func (o *GPIO_Type) GetAFRH_AFREL15() uint32 {
	return (volatile.LoadUint32(&o.AFRH.Reg) & 0x0) >> 32
}

// GPIO.BRR: GPIO port bit reset register
func (o *GPIO_Type) SetBRR_BR0(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetBRR_BR0() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetBRR_BR1(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetBRR_BR1() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetBRR_BR2(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetBRR_BR2() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetBRR_BR3(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetBRR_BR3() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetBRR_BR4(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetBRR_BR4() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetBRR_BR5(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetBRR_BR5() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetBRR_BR6(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetBRR_BR6() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetBRR_BR7(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetBRR_BR7() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetBRR_BR8(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetBRR_BR8() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetBRR_BR9(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetBRR_BR9() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetBRR_BR10(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetBRR_BR10() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetBRR_BR11(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetBRR_BR11() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetBRR_BR12(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetBRR_BR12() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetBRR_BR13(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetBRR_BR13() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetBRR_BR14(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetBRR_BR14() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x8000) >> 15
}
func (o *GPIO_Type) SetBRR_BR15(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0x10000)|value<<16)
}
func (o *GPIO_Type) GetBRR_BR15() uint32 {
	return (volatile.LoadUint32(&o.BRR.Reg) & 0x10000) >> 16
}

// GPIO.SECCFGR: GPIO secure configuration register
func (o *GPIO_Type) SetSECCFGR_SEC0(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *GPIO_Type) GetSECCFGR_SEC0() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}
func (o *GPIO_Type) SetSECCFGR_SEC1(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *GPIO_Type) GetSECCFGR_SEC1() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *GPIO_Type) SetSECCFGR_SEC2(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *GPIO_Type) GetSECCFGR_SEC2() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *GPIO_Type) SetSECCFGR_SEC3(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *GPIO_Type) GetSECCFGR_SEC3() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *GPIO_Type) SetSECCFGR_SEC4(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *GPIO_Type) GetSECCFGR_SEC4() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}
func (o *GPIO_Type) SetSECCFGR_SEC5(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x20)|value<<5)
}
func (o *GPIO_Type) GetSECCFGR_SEC5() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x20) >> 5
}
func (o *GPIO_Type) SetSECCFGR_SEC6(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x40)|value<<6)
}
func (o *GPIO_Type) GetSECCFGR_SEC6() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x40) >> 6
}
func (o *GPIO_Type) SetSECCFGR_SEC7(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x80)|value<<7)
}
func (o *GPIO_Type) GetSECCFGR_SEC7() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x80) >> 7
}
func (o *GPIO_Type) SetSECCFGR_SEC8(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x100)|value<<8)
}
func (o *GPIO_Type) GetSECCFGR_SEC8() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x100) >> 8
}
func (o *GPIO_Type) SetSECCFGR_SEC9(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x200)|value<<9)
}
func (o *GPIO_Type) GetSECCFGR_SEC9() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x200) >> 9
}
func (o *GPIO_Type) SetSECCFGR_SEC10(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x400)|value<<10)
}
func (o *GPIO_Type) GetSECCFGR_SEC10() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x400) >> 10
}
func (o *GPIO_Type) SetSECCFGR_SEC11(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x800)|value<<11)
}
func (o *GPIO_Type) GetSECCFGR_SEC11() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x800) >> 11
}
func (o *GPIO_Type) SetSECCFGR_SEC12(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *GPIO_Type) GetSECCFGR_SEC12() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1000) >> 12
}
func (o *GPIO_Type) SetSECCFGR_SEC13(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2000)|value<<13)
}
func (o *GPIO_Type) GetSECCFGR_SEC13() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2000) >> 13
}
func (o *GPIO_Type) SetSECCFGR_SEC14(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4000)|value<<14)
}
func (o *GPIO_Type) GetSECCFGR_SEC14() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4000) >> 14
}
func (o *GPIO_Type) SetSECCFGR_SEC15(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8000)|value<<15)
}
func (o *GPIO_Type) GetSECCFGR_SEC15() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8000) >> 15
}

// GTZC_MPCBB1
type GTZC_Type struct {
	CR      volatile.Register32 // 0x0
	_       [12]byte
	LCKVTR1 volatile.Register32 // 0x10
	LCKVTR2 volatile.Register32 // 0x14
	_       [232]byte
	VCTR0   volatile.Register32 // 0x100
	VCTR1   volatile.Register32 // 0x104
	VCTR2   volatile.Register32 // 0x108
	VCTR3   volatile.Register32 // 0x10C
	VCTR4   volatile.Register32 // 0x110
	VCTR5   volatile.Register32 // 0x114
	VCTR6   volatile.Register32 // 0x118
	VCTR7   volatile.Register32 // 0x11C
	VCTR8   volatile.Register32 // 0x120
	VCTR9   volatile.Register32 // 0x124
	VCTR10  volatile.Register32 // 0x128
	VCTR11  volatile.Register32 // 0x12C
	VCTR12  volatile.Register32 // 0x130
	VCTR13  volatile.Register32 // 0x134
	VCTR14  volatile.Register32 // 0x138
	VCTR15  volatile.Register32 // 0x13C
	VCTR16  volatile.Register32 // 0x140
	VCTR17  volatile.Register32 // 0x144
	VCTR18  volatile.Register32 // 0x148
	VCTR19  volatile.Register32 // 0x14C
	VCTR20  volatile.Register32 // 0x150
	VCTR21  volatile.Register32 // 0x154
	VCTR22  volatile.Register32 // 0x158
	VCTR23  volatile.Register32 // 0x15C
	VCTR24  volatile.Register32 // 0x160
	VCTR25  volatile.Register32 // 0x164
	VCTR26  volatile.Register32 // 0x168
	VCTR27  volatile.Register32 // 0x16C
	VCTR28  volatile.Register32 // 0x170
	VCTR29  volatile.Register32 // 0x174
	VCTR30  volatile.Register32 // 0x178
	VCTR31  volatile.Register32 // 0x17C
	VCTR32  volatile.Register32 // 0x180
	VCTR33  volatile.Register32 // 0x184
	VCTR34  volatile.Register32 // 0x188
	VCTR35  volatile.Register32 // 0x18C
	VCTR36  volatile.Register32 // 0x190
	VCTR37  volatile.Register32 // 0x194
	VCTR38  volatile.Register32 // 0x198
	VCTR39  volatile.Register32 // 0x19C
	VCTR40  volatile.Register32 // 0x1A0
	VCTR41  volatile.Register32 // 0x1A4
	VCTR42  volatile.Register32 // 0x1A8
	VCTR43  volatile.Register32 // 0x1AC
	VCTR44  volatile.Register32 // 0x1B0
	VCTR45  volatile.Register32 // 0x1B4
	VCTR46  volatile.Register32 // 0x1B8
	VCTR47  volatile.Register32 // 0x1BC
	VCTR48  volatile.Register32 // 0x1C0
	VCTR49  volatile.Register32 // 0x1C4
	VCTR50  volatile.Register32 // 0x1C8
	VCTR51  volatile.Register32 // 0x1CC
	VCTR52  volatile.Register32 // 0x1D0
	VCTR53  volatile.Register32 // 0x1D4
	VCTR54  volatile.Register32 // 0x1D8
	VCTR55  volatile.Register32 // 0x1DC
	VCTR56  volatile.Register32 // 0x1E0
	VCTR57  volatile.Register32 // 0x1E4
	VCTR58  volatile.Register32 // 0x1E8
	VCTR59  volatile.Register32 // 0x1EC
	VCTR60  volatile.Register32 // 0x1F0
	VCTR61  volatile.Register32 // 0x1F4
	VCTR62  volatile.Register32 // 0x1F8
	VCTR63  volatile.Register32 // 0x1FC
}

// GTZC.CR: MPCBB control register
func (o *GTZC_Type) SetCR_LCK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetCR_LCK() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *GTZC_Type) SetCR_INVSECSTATE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetCR_INVSECSTATE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetCR_SRWILADIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetCR_SRWILADIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// GTZC.LCKVTR1: MPCBB control register
func (o *GTZC_Type) SetLCKVTR1_LCKSB0(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB0() uint32 {
	return volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x1
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB1(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB1() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB2(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB2() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB3(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB3() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB4(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB4() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB5(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB5() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB6(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB6() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB7(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB7() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB8(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB8() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB9(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB9() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB10(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB10() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB11(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB11() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB12(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB12() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB13(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB13() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB14(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB14() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB15(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB15() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB16(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB16() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB17(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB17() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB18(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB18() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB19(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB19() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB20(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB20() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB21(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB21() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB22(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB22() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB23(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB23() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB24(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB24() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB25(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB25() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB26(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB26() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB27(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB27() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB28(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB28() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB29(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB29() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB30(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB30() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetLCKVTR1_LCKSB31(value uint32) {
	volatile.StoreUint32(&o.LCKVTR1.Reg, volatile.LoadUint32(&o.LCKVTR1.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetLCKVTR1_LCKSB31() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR1.Reg) & 0x80000000) >> 31
}

// GTZC.LCKVTR2: MPCBB control register
func (o *GTZC_Type) SetLCKVTR2_LCKSB32(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB32() uint32 {
	return volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x1
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB33(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB33() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB34(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB34() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB35(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB35() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB36(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB36() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB37(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB37() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB38(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB38() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB39(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB39() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB40(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB40() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB41(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB41() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB42(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB42() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB43(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB43() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB44(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB44() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB45(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB45() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB46(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB46() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB47(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB47() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB48(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB48() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB49(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB49() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB50(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB50() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB51(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB51() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB52(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB52() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB53(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB53() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB54(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB54() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB55(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB55() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB56(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB56() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB57(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB57() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB58(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB58() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB59(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB59() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB60(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB60() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB61(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB61() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB62(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB62() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetLCKVTR2_LCKSB63(value uint32) {
	volatile.StoreUint32(&o.LCKVTR2.Reg, volatile.LoadUint32(&o.LCKVTR2.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetLCKVTR2_LCKSB63() uint32 {
	return (volatile.LoadUint32(&o.LCKVTR2.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR0: MPCBBx vector register
func (o *GTZC_Type) SetVCTR0_B0(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR0_B0() uint32 {
	return volatile.LoadUint32(&o.VCTR0.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR0_B1(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR0_B1() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR0_B2(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR0_B2() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR0_B3(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR0_B3() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR0_B4(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR0_B4() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR0_B5(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR0_B5() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR0_B6(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR0_B6() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR0_B7(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR0_B7() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR0_B8(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR0_B8() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR0_B9(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR0_B9() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR0_B10(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR0_B10() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR0_B11(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR0_B11() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR0_B12(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR0_B12() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR0_B13(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR0_B13() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR0_B14(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR0_B14() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR0_B15(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR0_B15() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR0_B16(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR0_B16() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR0_B17(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR0_B17() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR0_B18(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR0_B18() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR0_B19(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR0_B19() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR0_B20(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR0_B20() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR0_B21(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR0_B21() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR0_B22(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR0_B22() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR0_B23(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR0_B23() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR0_B24(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR0_B24() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR0_B25(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR0_B25() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR0_B26(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR0_B26() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR0_B27(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR0_B27() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR0_B28(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR0_B28() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR0_B29(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR0_B29() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR0_B30(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR0_B30() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR0_B31(value uint32) {
	volatile.StoreUint32(&o.VCTR0.Reg, volatile.LoadUint32(&o.VCTR0.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR0_B31() uint32 {
	return (volatile.LoadUint32(&o.VCTR0.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR1: MPCBBx vector register
func (o *GTZC_Type) SetVCTR1_B32(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR1_B32() uint32 {
	return volatile.LoadUint32(&o.VCTR1.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR1_B33(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR1_B33() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR1_B34(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR1_B34() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR1_B35(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR1_B35() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR1_B36(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR1_B36() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR1_B37(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR1_B37() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR1_B38(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR1_B38() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR1_B39(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR1_B39() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR1_B40(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR1_B40() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR1_B41(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR1_B41() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR1_B42(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR1_B42() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR1_B43(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR1_B43() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR1_B44(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR1_B44() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR1_B45(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR1_B45() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR1_B46(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR1_B46() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR1_B47(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR1_B47() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR1_B48(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR1_B48() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR1_B49(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR1_B49() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR1_B50(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR1_B50() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR1_B51(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR1_B51() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR1_B52(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR1_B52() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR1_B53(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR1_B53() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR1_B54(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR1_B54() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR1_B55(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR1_B55() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR1_B56(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR1_B56() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR1_B57(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR1_B57() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR1_B58(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR1_B58() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR1_B59(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR1_B59() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR1_B60(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR1_B60() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR1_B61(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR1_B61() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR1_B62(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR1_B62() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR1_B63(value uint32) {
	volatile.StoreUint32(&o.VCTR1.Reg, volatile.LoadUint32(&o.VCTR1.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR1_B63() uint32 {
	return (volatile.LoadUint32(&o.VCTR1.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR2: MPCBBx vector register
func (o *GTZC_Type) SetVCTR2_B64(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR2_B64() uint32 {
	return volatile.LoadUint32(&o.VCTR2.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR2_B65(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR2_B65() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR2_B66(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR2_B66() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR2_B67(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR2_B67() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR2_B68(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR2_B68() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR2_B69(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR2_B69() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR2_B70(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR2_B70() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR2_B71(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR2_B71() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR2_B72(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR2_B72() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR2_B73(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR2_B73() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR2_B74(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR2_B74() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR2_B75(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR2_B75() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR2_B76(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR2_B76() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR2_B77(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR2_B77() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR2_B78(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR2_B78() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR2_B79(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR2_B79() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR2_B80(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR2_B80() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR2_B81(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR2_B81() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR2_B82(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR2_B82() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR2_B83(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR2_B83() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR2_B84(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR2_B84() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR2_B85(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR2_B85() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR2_B86(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR2_B86() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR2_B87(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR2_B87() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR2_B88(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR2_B88() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR2_B89(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR2_B89() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR2_B90(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR2_B90() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR2_B91(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR2_B91() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR2_B92(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR2_B92() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR2_B93(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR2_B93() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR2_B94(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR2_B94() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR2_B95(value uint32) {
	volatile.StoreUint32(&o.VCTR2.Reg, volatile.LoadUint32(&o.VCTR2.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR2_B95() uint32 {
	return (volatile.LoadUint32(&o.VCTR2.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR3: MPCBBx vector register
func (o *GTZC_Type) SetVCTR3_B96(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR3_B96() uint32 {
	return volatile.LoadUint32(&o.VCTR3.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR3_B97(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR3_B97() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR3_B98(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR3_B98() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR3_B99(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR3_B99() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR3_B100(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR3_B100() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR3_B101(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR3_B101() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR3_B102(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR3_B102() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR3_B103(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR3_B103() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR3_B104(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR3_B104() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR3_B105(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR3_B105() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR3_B106(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR3_B106() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR3_B107(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR3_B107() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR3_B108(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR3_B108() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR3_B109(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR3_B109() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR3_B110(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR3_B110() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR3_B111(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR3_B111() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR3_B112(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR3_B112() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR3_B113(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR3_B113() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR3_B114(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR3_B114() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR3_B115(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR3_B115() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR3_B116(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR3_B116() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR3_B117(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR3_B117() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR3_B118(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR3_B118() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR3_B119(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR3_B119() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR3_B120(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR3_B120() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR3_B121(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR3_B121() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR3_B122(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR3_B122() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR3_B123(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR3_B123() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR3_B124(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR3_B124() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR3_B125(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR3_B125() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR3_B126(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR3_B126() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR3_B127(value uint32) {
	volatile.StoreUint32(&o.VCTR3.Reg, volatile.LoadUint32(&o.VCTR3.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR3_B127() uint32 {
	return (volatile.LoadUint32(&o.VCTR3.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR4: MPCBBx vector register
func (o *GTZC_Type) SetVCTR4_B128(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR4_B128() uint32 {
	return volatile.LoadUint32(&o.VCTR4.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR4_B129(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR4_B129() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR4_B130(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR4_B130() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR4_B131(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR4_B131() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR4_B132(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR4_B132() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR4_B133(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR4_B133() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR4_B134(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR4_B134() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR4_B135(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR4_B135() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR4_B136(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR4_B136() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR4_B137(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR4_B137() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR4_B138(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR4_B138() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR4_B139(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR4_B139() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR4_B140(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR4_B140() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR4_B141(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR4_B141() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR4_B142(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR4_B142() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR4_B143(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR4_B143() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR4_B144(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR4_B144() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR4_B145(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR4_B145() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR4_B146(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR4_B146() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR4_B147(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR4_B147() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR4_B148(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR4_B148() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR4_B149(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR4_B149() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR4_B150(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR4_B150() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR4_B151(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR4_B151() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR4_B152(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR4_B152() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR4_B153(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR4_B153() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR4_B154(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR4_B154() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR4_B155(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR4_B155() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR4_B156(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR4_B156() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR4_B157(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR4_B157() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR4_B158(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR4_B158() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR4_B159(value uint32) {
	volatile.StoreUint32(&o.VCTR4.Reg, volatile.LoadUint32(&o.VCTR4.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR4_B159() uint32 {
	return (volatile.LoadUint32(&o.VCTR4.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR5: MPCBBx vector register
func (o *GTZC_Type) SetVCTR5_B160(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR5_B160() uint32 {
	return volatile.LoadUint32(&o.VCTR5.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR5_B161(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR5_B161() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR5_B162(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR5_B162() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR5_B163(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR5_B163() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR5_B164(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR5_B164() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR5_B165(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR5_B165() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR5_B166(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR5_B166() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR5_B167(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR5_B167() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR5_B168(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR5_B168() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR5_B169(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR5_B169() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR5_B170(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR5_B170() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR5_B171(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR5_B171() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR5_B172(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR5_B172() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR5_B173(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR5_B173() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR5_B174(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR5_B174() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR5_B175(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR5_B175() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR5_B176(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR5_B176() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR5_B177(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR5_B177() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR5_B178(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR5_B178() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR5_B179(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR5_B179() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR5_B180(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR5_B180() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR5_B181(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR5_B181() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR5_B182(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR5_B182() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR5_B183(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR5_B183() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR5_B184(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR5_B184() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR5_B185(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR5_B185() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR5_B186(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR5_B186() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR5_B187(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR5_B187() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR5_B188(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR5_B188() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR5_B189(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR5_B189() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR5_B190(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR5_B190() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR5_B191(value uint32) {
	volatile.StoreUint32(&o.VCTR5.Reg, volatile.LoadUint32(&o.VCTR5.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR5_B191() uint32 {
	return (volatile.LoadUint32(&o.VCTR5.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR6: MPCBBx vector register
func (o *GTZC_Type) SetVCTR6_B192(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR6_B192() uint32 {
	return volatile.LoadUint32(&o.VCTR6.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR6_B193(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR6_B193() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR6_B194(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR6_B194() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR6_B195(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR6_B195() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR6_B196(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR6_B196() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR6_B197(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR6_B197() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR6_B198(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR6_B198() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR6_B199(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR6_B199() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR6_B200(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR6_B200() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR6_B201(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR6_B201() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR6_B202(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR6_B202() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR6_B203(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR6_B203() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR6_B204(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR6_B204() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR6_B205(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR6_B205() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR6_B206(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR6_B206() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR6_B207(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR6_B207() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR6_B208(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR6_B208() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR6_B209(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR6_B209() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR6_B210(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR6_B210() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR6_B211(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR6_B211() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR6_B212(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR6_B212() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR6_B213(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR6_B213() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR6_B214(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR6_B214() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR6_B215(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR6_B215() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR6_B216(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR6_B216() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR6_B217(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR6_B217() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR6_B218(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR6_B218() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR6_B219(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR6_B219() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR6_B220(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR6_B220() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR6_B221(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR6_B221() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR6_B222(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR6_B222() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR6_B223(value uint32) {
	volatile.StoreUint32(&o.VCTR6.Reg, volatile.LoadUint32(&o.VCTR6.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR6_B223() uint32 {
	return (volatile.LoadUint32(&o.VCTR6.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR7: MPCBBx vector register
func (o *GTZC_Type) SetVCTR7_B224(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR7_B224() uint32 {
	return volatile.LoadUint32(&o.VCTR7.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR7_B225(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR7_B225() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR7_B226(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR7_B226() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR7_B227(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR7_B227() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR7_B228(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR7_B228() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR7_B229(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR7_B229() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR7_B230(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR7_B230() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR7_B231(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR7_B231() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR7_B232(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR7_B232() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR7_B233(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR7_B233() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR7_B234(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR7_B234() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR7_B235(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR7_B235() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR7_B236(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR7_B236() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR7_B237(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR7_B237() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR7_B238(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR7_B238() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR7_B239(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR7_B239() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR7_B240(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR7_B240() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR7_B241(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR7_B241() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR7_B242(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR7_B242() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR7_B243(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR7_B243() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR7_B244(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR7_B244() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR7_B245(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR7_B245() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR7_B246(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR7_B246() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR7_B247(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR7_B247() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR7_B248(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR7_B248() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR7_B249(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR7_B249() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR7_B250(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR7_B250() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR7_B251(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR7_B251() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR7_B252(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR7_B252() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR7_B253(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR7_B253() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR7_B254(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR7_B254() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR7_B255(value uint32) {
	volatile.StoreUint32(&o.VCTR7.Reg, volatile.LoadUint32(&o.VCTR7.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR7_B255() uint32 {
	return (volatile.LoadUint32(&o.VCTR7.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR8: MPCBBx vector register
func (o *GTZC_Type) SetVCTR8_B256(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR8_B256() uint32 {
	return volatile.LoadUint32(&o.VCTR8.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR8_B257(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR8_B257() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR8_B258(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR8_B258() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR8_B259(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR8_B259() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR8_B260(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR8_B260() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR8_B261(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR8_B261() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR8_B262(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR8_B262() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR8_B263(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR8_B263() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR8_B264(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR8_B264() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR8_B265(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR8_B265() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR8_B266(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR8_B266() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR8_B267(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR8_B267() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR8_B268(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR8_B268() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR8_B269(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR8_B269() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR8_B270(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR8_B270() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR8_B271(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR8_B271() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR8_B272(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR8_B272() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR8_B273(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR8_B273() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR8_B274(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR8_B274() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR8_B275(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR8_B275() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR8_B276(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR8_B276() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR8_B277(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR8_B277() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR8_B278(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR8_B278() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR8_B279(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR8_B279() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR8_B280(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR8_B280() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR8_B281(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR8_B281() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR8_B282(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR8_B282() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR8_B283(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR8_B283() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR8_B284(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR8_B284() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR8_B285(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR8_B285() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR8_B286(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR8_B286() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR8_B287(value uint32) {
	volatile.StoreUint32(&o.VCTR8.Reg, volatile.LoadUint32(&o.VCTR8.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR8_B287() uint32 {
	return (volatile.LoadUint32(&o.VCTR8.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR9: MPCBBx vector register
func (o *GTZC_Type) SetVCTR9_B288(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR9_B288() uint32 {
	return volatile.LoadUint32(&o.VCTR9.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR9_B289(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR9_B289() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR9_B290(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR9_B290() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR9_B291(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR9_B291() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR9_B292(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR9_B292() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR9_B293(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR9_B293() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR9_B294(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR9_B294() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR9_B295(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR9_B295() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR9_B296(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR9_B296() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR9_B297(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR9_B297() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR9_B298(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR9_B298() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR9_B299(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR9_B299() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR9_B300(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR9_B300() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR9_B301(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR9_B301() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR9_B302(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR9_B302() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR9_B303(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR9_B303() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR9_B304(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR9_B304() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR9_B305(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR9_B305() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR9_B306(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR9_B306() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR9_B307(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR9_B307() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR9_B308(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR9_B308() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR9_B309(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR9_B309() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR9_B310(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR9_B310() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR9_B311(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR9_B311() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR9_B312(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR9_B312() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR9_B313(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR9_B313() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR9_B314(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR9_B314() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR9_B315(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR9_B315() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR9_B316(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR9_B316() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR9_B317(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR9_B317() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR9_B318(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR9_B318() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR9_B319(value uint32) {
	volatile.StoreUint32(&o.VCTR9.Reg, volatile.LoadUint32(&o.VCTR9.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR9_B319() uint32 {
	return (volatile.LoadUint32(&o.VCTR9.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR10: MPCBBx vector register
func (o *GTZC_Type) SetVCTR10_B320(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR10_B320() uint32 {
	return volatile.LoadUint32(&o.VCTR10.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR10_B321(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR10_B321() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR10_B322(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR10_B322() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR10_B323(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR10_B323() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR10_B324(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR10_B324() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR10_B325(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR10_B325() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR10_B326(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR10_B326() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR10_B327(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR10_B327() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR10_B328(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR10_B328() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR10_B329(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR10_B329() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR10_B330(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR10_B330() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR10_B331(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR10_B331() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR10_B332(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR10_B332() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR10_B333(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR10_B333() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR10_B334(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR10_B334() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR10_B335(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR10_B335() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR10_B336(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR10_B336() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR10_B337(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR10_B337() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR10_B338(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR10_B338() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR10_B339(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR10_B339() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR10_B340(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR10_B340() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR10_B341(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR10_B341() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR10_B342(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR10_B342() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR10_B343(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR10_B343() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR10_B344(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR10_B344() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR10_B345(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR10_B345() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR10_B346(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR10_B346() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR10_B347(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR10_B347() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR10_B348(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR10_B348() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR10_B349(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR10_B349() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR10_B350(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR10_B350() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR10_B351(value uint32) {
	volatile.StoreUint32(&o.VCTR10.Reg, volatile.LoadUint32(&o.VCTR10.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR10_B351() uint32 {
	return (volatile.LoadUint32(&o.VCTR10.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR11: MPCBBx vector register
func (o *GTZC_Type) SetVCTR11_B352(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR11_B352() uint32 {
	return volatile.LoadUint32(&o.VCTR11.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR11_B353(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR11_B353() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR11_B354(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR11_B354() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR11_B355(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR11_B355() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR11_B356(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR11_B356() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR11_B357(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR11_B357() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR11_B358(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR11_B358() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR11_B359(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR11_B359() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR11_B360(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR11_B360() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR11_B361(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR11_B361() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR11_B362(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR11_B362() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR11_B363(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR11_B363() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR11_B364(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR11_B364() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR11_B365(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR11_B365() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR11_B366(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR11_B366() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR11_B367(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR11_B367() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR11_B368(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR11_B368() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR11_B369(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR11_B369() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR11_B370(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR11_B370() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR11_B371(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR11_B371() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR11_B372(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR11_B372() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR11_B373(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR11_B373() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR11_B374(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR11_B374() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR11_B375(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR11_B375() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR11_B376(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR11_B376() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR11_B377(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR11_B377() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR11_B378(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR11_B378() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR11_B379(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR11_B379() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR11_B380(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR11_B380() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR11_B381(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR11_B381() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR11_B382(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR11_B382() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR11_B383(value uint32) {
	volatile.StoreUint32(&o.VCTR11.Reg, volatile.LoadUint32(&o.VCTR11.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR11_B383() uint32 {
	return (volatile.LoadUint32(&o.VCTR11.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR12: MPCBBx vector register
func (o *GTZC_Type) SetVCTR12_B384(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR12_B384() uint32 {
	return volatile.LoadUint32(&o.VCTR12.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR12_B385(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR12_B385() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR12_B386(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR12_B386() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR12_B387(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR12_B387() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR12_B388(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR12_B388() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR12_B389(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR12_B389() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR12_B390(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR12_B390() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR12_B391(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR12_B391() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR12_B392(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR12_B392() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR12_B393(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR12_B393() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR12_B394(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR12_B394() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR12_B395(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR12_B395() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR12_B396(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR12_B396() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR12_B397(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR12_B397() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR12_B398(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR12_B398() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR12_B399(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR12_B399() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR12_B400(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR12_B400() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR12_B401(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR12_B401() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR12_B402(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR12_B402() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR12_B403(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR12_B403() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR12_B404(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR12_B404() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR12_B405(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR12_B405() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR12_B406(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR12_B406() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR12_B407(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR12_B407() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR12_B408(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR12_B408() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR12_B409(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR12_B409() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR12_B410(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR12_B410() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR12_B411(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR12_B411() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR12_B412(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR12_B412() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR12_B413(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR12_B413() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR12_B414(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR12_B414() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR12_B415(value uint32) {
	volatile.StoreUint32(&o.VCTR12.Reg, volatile.LoadUint32(&o.VCTR12.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR12_B415() uint32 {
	return (volatile.LoadUint32(&o.VCTR12.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR13: MPCBBx vector register
func (o *GTZC_Type) SetVCTR13_B416(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR13_B416() uint32 {
	return volatile.LoadUint32(&o.VCTR13.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR13_B417(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR13_B417() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR13_B418(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR13_B418() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR13_B419(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR13_B419() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR13_B420(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR13_B420() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR13_B421(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR13_B421() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR13_B422(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR13_B422() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR13_B423(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR13_B423() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR13_B424(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR13_B424() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR13_B425(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR13_B425() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR13_B426(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR13_B426() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR13_B427(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR13_B427() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR13_B428(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR13_B428() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR13_B429(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR13_B429() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR13_B430(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR13_B430() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR13_B431(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR13_B431() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR13_B432(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR13_B432() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR13_B433(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR13_B433() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR13_B434(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR13_B434() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR13_B435(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR13_B435() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR13_B436(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR13_B436() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR13_B437(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR13_B437() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR13_B438(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR13_B438() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR13_B439(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR13_B439() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR13_B440(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR13_B440() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR13_B441(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR13_B441() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR13_B442(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR13_B442() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR13_B443(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR13_B443() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR13_B444(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR13_B444() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR13_B445(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR13_B445() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR13_B446(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR13_B446() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR13_B447(value uint32) {
	volatile.StoreUint32(&o.VCTR13.Reg, volatile.LoadUint32(&o.VCTR13.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR13_B447() uint32 {
	return (volatile.LoadUint32(&o.VCTR13.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR14: MPCBBx vector register
func (o *GTZC_Type) SetVCTR14_B448(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR14_B448() uint32 {
	return volatile.LoadUint32(&o.VCTR14.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR14_B449(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR14_B449() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR14_B450(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR14_B450() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR14_B451(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR14_B451() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR14_B452(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR14_B452() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR14_B453(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR14_B453() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR14_B454(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR14_B454() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR14_B455(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR14_B455() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR14_B456(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR14_B456() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR14_B457(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR14_B457() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR14_B458(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR14_B458() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR14_B459(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR14_B459() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR14_B460(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR14_B460() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR14_B461(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR14_B461() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR14_B462(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR14_B462() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR14_B463(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR14_B463() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR14_B464(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR14_B464() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR14_B465(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR14_B465() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR14_B466(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR14_B466() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR14_B467(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR14_B467() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR14_B468(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR14_B468() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR14_B469(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR14_B469() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR14_B470(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR14_B470() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR14_B471(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR14_B471() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR14_B472(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR14_B472() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR14_B473(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR14_B473() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR14_B474(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR14_B474() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR14_B475(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR14_B475() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR14_B476(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR14_B476() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR14_B477(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR14_B477() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR14_B478(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR14_B478() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR14_B479(value uint32) {
	volatile.StoreUint32(&o.VCTR14.Reg, volatile.LoadUint32(&o.VCTR14.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR14_B479() uint32 {
	return (volatile.LoadUint32(&o.VCTR14.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR15: MPCBBx vector register
func (o *GTZC_Type) SetVCTR15_B480(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR15_B480() uint32 {
	return volatile.LoadUint32(&o.VCTR15.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR15_B481(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR15_B481() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR15_B482(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR15_B482() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR15_B483(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR15_B483() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR15_B484(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR15_B484() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR15_B485(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR15_B485() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR15_B486(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR15_B486() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR15_B487(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR15_B487() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR15_B488(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR15_B488() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR15_B489(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR15_B489() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR15_B490(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR15_B490() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR15_B491(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR15_B491() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR15_B492(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR15_B492() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR15_B493(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR15_B493() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR15_B494(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR15_B494() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR15_B495(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR15_B495() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR15_B496(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR15_B496() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR15_B497(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR15_B497() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR15_B498(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR15_B498() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR15_B499(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR15_B499() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR15_B500(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR15_B500() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR15_B501(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR15_B501() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR15_B502(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR15_B502() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR15_B503(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR15_B503() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR15_B504(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR15_B504() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR15_B505(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR15_B505() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR15_B506(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR15_B506() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR15_B507(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR15_B507() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR15_B508(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR15_B508() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR15_B509(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR15_B509() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR15_B510(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR15_B510() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR15_B511(value uint32) {
	volatile.StoreUint32(&o.VCTR15.Reg, volatile.LoadUint32(&o.VCTR15.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR15_B511() uint32 {
	return (volatile.LoadUint32(&o.VCTR15.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR16: MPCBBx vector register
func (o *GTZC_Type) SetVCTR16_B512(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR16_B512() uint32 {
	return volatile.LoadUint32(&o.VCTR16.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR16_B513(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR16_B513() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR16_B514(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR16_B514() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR16_B515(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR16_B515() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR16_B516(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR16_B516() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR16_B517(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR16_B517() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR16_B518(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR16_B518() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR16_B519(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR16_B519() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR16_B520(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR16_B520() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR16_B521(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR16_B521() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR16_B522(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR16_B522() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR16_B523(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR16_B523() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR16_B524(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR16_B524() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR16_B525(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR16_B525() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR16_B526(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR16_B526() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR16_B527(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR16_B527() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR16_B528(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR16_B528() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR16_B529(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR16_B529() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR16_B530(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR16_B530() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR16_B531(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR16_B531() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR16_B532(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR16_B532() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR16_B533(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR16_B533() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR16_B534(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR16_B534() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR16_B535(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR16_B535() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR16_B536(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR16_B536() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR16_B537(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR16_B537() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR16_B538(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR16_B538() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR16_B539(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR16_B539() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR16_B540(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR16_B540() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR16_B541(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR16_B541() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR16_B542(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR16_B542() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR16_B543(value uint32) {
	volatile.StoreUint32(&o.VCTR16.Reg, volatile.LoadUint32(&o.VCTR16.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR16_B543() uint32 {
	return (volatile.LoadUint32(&o.VCTR16.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR17: MPCBBx vector register
func (o *GTZC_Type) SetVCTR17_B544(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR17_B544() uint32 {
	return volatile.LoadUint32(&o.VCTR17.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR17_B545(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR17_B545() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR17_B546(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR17_B546() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR17_B547(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR17_B547() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR17_B548(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR17_B548() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR17_B549(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR17_B549() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR17_B550(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR17_B550() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR17_B551(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR17_B551() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR17_B552(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR17_B552() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR17_B553(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR17_B553() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR17_B554(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR17_B554() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR17_B555(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR17_B555() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR17_B556(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR17_B556() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR17_B557(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR17_B557() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR17_B558(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR17_B558() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR17_B559(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR17_B559() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR17_B560(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR17_B560() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR17_B561(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR17_B561() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR17_B562(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR17_B562() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR17_B563(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR17_B563() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR17_B564(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR17_B564() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR17_B565(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR17_B565() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR17_B566(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR17_B566() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR17_B567(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR17_B567() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR17_B568(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR17_B568() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR17_B569(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR17_B569() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR17_B570(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR17_B570() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR17_B571(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR17_B571() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR17_B572(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR17_B572() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR17_B573(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR17_B573() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR17_B574(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR17_B574() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR17_B575(value uint32) {
	volatile.StoreUint32(&o.VCTR17.Reg, volatile.LoadUint32(&o.VCTR17.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR17_B575() uint32 {
	return (volatile.LoadUint32(&o.VCTR17.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR18: MPCBBx vector register
func (o *GTZC_Type) SetVCTR18_B576(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR18_B576() uint32 {
	return volatile.LoadUint32(&o.VCTR18.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR18_B577(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR18_B577() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR18_B578(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR18_B578() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR18_B579(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR18_B579() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR18_B580(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR18_B580() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR18_B581(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR18_B581() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR18_B582(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR18_B582() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR18_B583(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR18_B583() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR18_B584(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR18_B584() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR18_B585(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR18_B585() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR18_B586(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR18_B586() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR18_B587(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR18_B587() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR18_B588(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR18_B588() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR18_B589(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR18_B589() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR18_B590(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR18_B590() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR18_B591(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR18_B591() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR18_B592(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR18_B592() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR18_B593(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR18_B593() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR18_B594(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR18_B594() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR18_B595(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR18_B595() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR18_B596(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR18_B596() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR18_B597(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR18_B597() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR18_B598(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR18_B598() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR18_B599(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR18_B599() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR18_B600(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR18_B600() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR18_B601(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR18_B601() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR18_B602(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR18_B602() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR18_B603(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR18_B603() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR18_B604(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR18_B604() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR18_B605(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR18_B605() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR18_B606(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR18_B606() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR18_B607(value uint32) {
	volatile.StoreUint32(&o.VCTR18.Reg, volatile.LoadUint32(&o.VCTR18.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR18_B607() uint32 {
	return (volatile.LoadUint32(&o.VCTR18.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR19: MPCBBx vector register
func (o *GTZC_Type) SetVCTR19_B608(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR19_B608() uint32 {
	return volatile.LoadUint32(&o.VCTR19.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR19_B609(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR19_B609() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR19_B610(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR19_B610() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR19_B611(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR19_B611() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR19_B612(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR19_B612() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR19_B613(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR19_B613() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR19_B614(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR19_B614() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR19_B615(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR19_B615() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR19_B616(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR19_B616() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR19_B617(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR19_B617() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR19_B618(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR19_B618() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR19_B619(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR19_B619() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR19_B620(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR19_B620() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR19_B621(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR19_B621() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR19_B622(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR19_B622() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR19_B623(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR19_B623() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR19_B624(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR19_B624() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR19_B625(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR19_B625() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR19_B626(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR19_B626() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR19_B627(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR19_B627() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR19_B628(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR19_B628() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR19_B629(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR19_B629() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR19_B630(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR19_B630() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR19_B631(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR19_B631() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR19_B632(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR19_B632() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR19_B633(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR19_B633() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR19_B634(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR19_B634() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR19_B635(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR19_B635() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR19_B636(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR19_B636() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR19_B637(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR19_B637() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR19_B638(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR19_B638() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR19_B639(value uint32) {
	volatile.StoreUint32(&o.VCTR19.Reg, volatile.LoadUint32(&o.VCTR19.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR19_B639() uint32 {
	return (volatile.LoadUint32(&o.VCTR19.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR20: MPCBBx vector register
func (o *GTZC_Type) SetVCTR20_B640(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR20_B640() uint32 {
	return volatile.LoadUint32(&o.VCTR20.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR20_B641(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR20_B641() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR20_B642(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR20_B642() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR20_B643(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR20_B643() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR20_B644(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR20_B644() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR20_B645(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR20_B645() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR20_B646(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR20_B646() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR20_B647(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR20_B647() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR20_B648(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR20_B648() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR20_B649(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR20_B649() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR20_B650(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR20_B650() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR20_B651(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR20_B651() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR20_B652(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR20_B652() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR20_B653(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR20_B653() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR20_B654(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR20_B654() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR20_B655(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR20_B655() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR20_B656(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR20_B656() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR20_B657(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR20_B657() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR20_B658(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR20_B658() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR20_B659(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR20_B659() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR20_B660(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR20_B660() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR20_B661(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR20_B661() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR20_B662(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR20_B662() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR20_B663(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR20_B663() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR20_B664(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR20_B664() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR20_B665(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR20_B665() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR20_B666(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR20_B666() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR20_B667(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR20_B667() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR20_B668(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR20_B668() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR20_B669(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR20_B669() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR20_B670(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR20_B670() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR20_B671(value uint32) {
	volatile.StoreUint32(&o.VCTR20.Reg, volatile.LoadUint32(&o.VCTR20.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR20_B671() uint32 {
	return (volatile.LoadUint32(&o.VCTR20.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR21: MPCBBx vector register
func (o *GTZC_Type) SetVCTR21_B672(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR21_B672() uint32 {
	return volatile.LoadUint32(&o.VCTR21.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR21_B673(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR21_B673() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR21_B674(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR21_B674() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR21_B675(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR21_B675() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR21_B676(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR21_B676() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR21_B677(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR21_B677() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR21_B678(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR21_B678() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR21_B679(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR21_B679() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR21_B680(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR21_B680() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR21_B681(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR21_B681() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR21_B682(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR21_B682() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR21_B683(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR21_B683() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR21_B684(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR21_B684() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR21_B685(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR21_B685() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR21_B686(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR21_B686() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR21_B687(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR21_B687() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR21_B688(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR21_B688() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR21_B689(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR21_B689() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR21_B690(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR21_B690() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR21_B691(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR21_B691() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR21_B692(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR21_B692() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR21_B693(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR21_B693() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR21_B694(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR21_B694() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR21_B695(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR21_B695() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR21_B696(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR21_B696() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR21_B697(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR21_B697() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR21_B698(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR21_B698() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR21_B699(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR21_B699() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR21_B700(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR21_B700() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR21_B701(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR21_B701() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR21_B702(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR21_B702() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR21_B703(value uint32) {
	volatile.StoreUint32(&o.VCTR21.Reg, volatile.LoadUint32(&o.VCTR21.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR21_B703() uint32 {
	return (volatile.LoadUint32(&o.VCTR21.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR22: MPCBBx vector register
func (o *GTZC_Type) SetVCTR22_B704(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR22_B704() uint32 {
	return volatile.LoadUint32(&o.VCTR22.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR22_B705(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR22_B705() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR22_B706(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR22_B706() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR22_B707(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR22_B707() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR22_B708(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR22_B708() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR22_B709(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR22_B709() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR22_B710(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR22_B710() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR22_B711(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR22_B711() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR22_B712(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR22_B712() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR22_B713(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR22_B713() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR22_B714(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR22_B714() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR22_B715(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR22_B715() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR22_B716(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR22_B716() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR22_B717(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR22_B717() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR22_B718(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR22_B718() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR22_B719(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR22_B719() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR22_B720(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR22_B720() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR22_B721(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR22_B721() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR22_B722(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR22_B722() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR22_B723(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR22_B723() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR22_B724(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR22_B724() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR22_B725(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR22_B725() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR22_B726(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR22_B726() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR22_B727(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR22_B727() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR22_B728(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR22_B728() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR22_B729(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR22_B729() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR22_B730(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR22_B730() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR22_B731(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR22_B731() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR22_B732(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR22_B732() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR22_B733(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR22_B733() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR22_B734(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR22_B734() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR22_B735(value uint32) {
	volatile.StoreUint32(&o.VCTR22.Reg, volatile.LoadUint32(&o.VCTR22.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR22_B735() uint32 {
	return (volatile.LoadUint32(&o.VCTR22.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR23: MPCBBx vector register
func (o *GTZC_Type) SetVCTR23_B736(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR23_B736() uint32 {
	return volatile.LoadUint32(&o.VCTR23.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR23_B737(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR23_B737() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR23_B738(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR23_B738() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR23_B739(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR23_B739() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR23_B740(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR23_B740() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR23_B741(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR23_B741() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR23_B742(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR23_B742() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR23_B743(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR23_B743() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR23_B744(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR23_B744() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR23_B745(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR23_B745() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR23_B746(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR23_B746() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR23_B747(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR23_B747() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR23_B748(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR23_B748() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR23_B749(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR23_B749() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR23_B750(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR23_B750() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR23_B751(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR23_B751() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR23_B752(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR23_B752() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR23_B753(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR23_B753() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR23_B754(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR23_B754() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR23_B755(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR23_B755() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR23_B756(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR23_B756() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR23_B757(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR23_B757() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR23_B758(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR23_B758() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR23_B759(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR23_B759() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR23_B760(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR23_B760() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR23_B761(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR23_B761() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR23_B762(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR23_B762() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR23_B763(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR23_B763() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR23_B764(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR23_B764() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR23_B765(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR23_B765() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR23_B766(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR23_B766() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR23_B767(value uint32) {
	volatile.StoreUint32(&o.VCTR23.Reg, volatile.LoadUint32(&o.VCTR23.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR23_B767() uint32 {
	return (volatile.LoadUint32(&o.VCTR23.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR24: MPCBBx vector register
func (o *GTZC_Type) SetVCTR24_B768(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR24_B768() uint32 {
	return volatile.LoadUint32(&o.VCTR24.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR24_B769(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR24_B769() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR24_B770(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR24_B770() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR24_B771(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR24_B771() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR24_B772(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR24_B772() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR24_B773(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR24_B773() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR24_B774(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR24_B774() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR24_B775(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR24_B775() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR24_B776(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR24_B776() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR24_B777(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR24_B777() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR24_B778(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR24_B778() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR24_B779(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR24_B779() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR24_B780(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR24_B780() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR24_B781(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR24_B781() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR24_B782(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR24_B782() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR24_B783(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR24_B783() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR24_B784(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR24_B784() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR24_B785(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR24_B785() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR24_B786(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR24_B786() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR24_B787(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR24_B787() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR24_B788(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR24_B788() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR24_B789(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR24_B789() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR24_B790(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR24_B790() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR24_B791(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR24_B791() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR24_B792(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR24_B792() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR24_B793(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR24_B793() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR24_B794(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR24_B794() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR24_B795(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR24_B795() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR24_B796(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR24_B796() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR24_B797(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR24_B797() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR24_B798(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR24_B798() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR24_B799(value uint32) {
	volatile.StoreUint32(&o.VCTR24.Reg, volatile.LoadUint32(&o.VCTR24.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR24_B799() uint32 {
	return (volatile.LoadUint32(&o.VCTR24.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR25: MPCBBx vector register
func (o *GTZC_Type) SetVCTR25_B800(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR25_B800() uint32 {
	return volatile.LoadUint32(&o.VCTR25.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR25_B801(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR25_B801() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR25_B802(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR25_B802() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR25_B803(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR25_B803() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR25_B804(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR25_B804() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR25_B805(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR25_B805() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR25_B806(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR25_B806() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR25_B807(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR25_B807() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR25_B808(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR25_B808() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR25_B809(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR25_B809() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR25_B810(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR25_B810() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR25_B811(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR25_B811() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR25_B812(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR25_B812() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR25_B813(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR25_B813() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR25_B814(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR25_B814() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR25_B815(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR25_B815() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR25_B816(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR25_B816() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR25_B817(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR25_B817() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR25_B818(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR25_B818() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR25_B819(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR25_B819() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR25_B820(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR25_B820() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR25_B821(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR25_B821() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR25_B822(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR25_B822() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR25_B823(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR25_B823() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR25_B824(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR25_B824() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR25_B825(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR25_B825() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR25_B826(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR25_B826() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR25_B827(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR25_B827() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR25_B828(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR25_B828() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR25_B829(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR25_B829() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR25_B830(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR25_B830() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR25_B831(value uint32) {
	volatile.StoreUint32(&o.VCTR25.Reg, volatile.LoadUint32(&o.VCTR25.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR25_B831() uint32 {
	return (volatile.LoadUint32(&o.VCTR25.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR26: MPCBBx vector register
func (o *GTZC_Type) SetVCTR26_B832(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR26_B832() uint32 {
	return volatile.LoadUint32(&o.VCTR26.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR26_B833(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR26_B833() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR26_B834(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR26_B834() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR26_B835(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR26_B835() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR26_B836(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR26_B836() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR26_B837(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR26_B837() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR26_B838(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR26_B838() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR26_B839(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR26_B839() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR26_B840(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR26_B840() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR26_B841(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR26_B841() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR26_B842(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR26_B842() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR26_B843(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR26_B843() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR26_B844(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR26_B844() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR26_B845(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR26_B845() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR26_B846(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR26_B846() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR26_B847(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR26_B847() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR26_B848(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR26_B848() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR26_B849(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR26_B849() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR26_B850(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR26_B850() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR26_B851(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR26_B851() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR26_B852(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR26_B852() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR26_B853(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR26_B853() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR26_B854(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR26_B854() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR26_B855(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR26_B855() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR26_B856(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR26_B856() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR26_B857(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR26_B857() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR26_B858(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR26_B858() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR26_B859(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR26_B859() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR26_B860(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR26_B860() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR26_B861(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR26_B861() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR26_B862(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR26_B862() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR26_B863(value uint32) {
	volatile.StoreUint32(&o.VCTR26.Reg, volatile.LoadUint32(&o.VCTR26.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR26_B863() uint32 {
	return (volatile.LoadUint32(&o.VCTR26.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR27: MPCBBx vector register
func (o *GTZC_Type) SetVCTR27_B864(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR27_B864() uint32 {
	return volatile.LoadUint32(&o.VCTR27.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR27_B865(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR27_B865() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR27_B866(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR27_B866() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR27_B867(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR27_B867() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR27_B868(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR27_B868() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR27_B869(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR27_B869() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR27_B870(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR27_B870() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR27_B871(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR27_B871() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR27_B872(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR27_B872() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR27_B873(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR27_B873() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR27_B874(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR27_B874() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR27_B875(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR27_B875() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR27_B876(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR27_B876() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR27_B877(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR27_B877() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR27_B878(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR27_B878() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR27_B879(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR27_B879() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR27_B880(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR27_B880() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR27_B881(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR27_B881() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR27_B882(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR27_B882() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR27_B883(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR27_B883() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR27_B884(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR27_B884() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR27_B885(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR27_B885() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR27_B886(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR27_B886() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR27_B887(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR27_B887() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR27_B888(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR27_B888() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR27_B889(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR27_B889() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR27_B890(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR27_B890() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR27_B891(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR27_B891() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR27_B892(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR27_B892() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR27_B893(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR27_B893() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR27_B894(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR27_B894() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR27_B895(value uint32) {
	volatile.StoreUint32(&o.VCTR27.Reg, volatile.LoadUint32(&o.VCTR27.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR27_B895() uint32 {
	return (volatile.LoadUint32(&o.VCTR27.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR28: MPCBBx vector register
func (o *GTZC_Type) SetVCTR28_B896(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR28_B896() uint32 {
	return volatile.LoadUint32(&o.VCTR28.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR28_B897(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR28_B897() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR28_B898(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR28_B898() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR28_B899(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR28_B899() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR28_B900(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR28_B900() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR28_B901(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR28_B901() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR28_B902(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR28_B902() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR28_B903(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR28_B903() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR28_B904(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR28_B904() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR28_B905(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR28_B905() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR28_B906(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR28_B906() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR28_B907(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR28_B907() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR28_B908(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR28_B908() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR28_B909(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR28_B909() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR28_B910(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR28_B910() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR28_B911(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR28_B911() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR28_B912(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR28_B912() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR28_B913(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR28_B913() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR28_B914(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR28_B914() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR28_B915(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR28_B915() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR28_B916(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR28_B916() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR28_B917(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR28_B917() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR28_B918(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR28_B918() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR28_B919(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR28_B919() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR28_B920(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR28_B920() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR28_B921(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR28_B921() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR28_B922(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR28_B922() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR28_B923(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR28_B923() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR28_B924(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR28_B924() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR28_B925(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR28_B925() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR28_B926(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR28_B926() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR28_B927(value uint32) {
	volatile.StoreUint32(&o.VCTR28.Reg, volatile.LoadUint32(&o.VCTR28.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR28_B927() uint32 {
	return (volatile.LoadUint32(&o.VCTR28.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR29: MPCBBx vector register
func (o *GTZC_Type) SetVCTR29_B928(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR29_B928() uint32 {
	return volatile.LoadUint32(&o.VCTR29.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR29_B929(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR29_B929() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR29_B930(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR29_B930() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR29_B931(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR29_B931() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR29_B932(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR29_B932() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR29_B933(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR29_B933() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR29_B934(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR29_B934() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR29_B935(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR29_B935() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR29_B936(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR29_B936() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR29_B937(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR29_B937() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR29_B938(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR29_B938() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR29_B939(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR29_B939() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR29_B940(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR29_B940() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR29_B941(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR29_B941() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR29_B942(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR29_B942() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR29_B943(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR29_B943() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR29_B944(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR29_B944() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR29_B945(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR29_B945() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR29_B946(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR29_B946() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR29_B947(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR29_B947() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR29_B948(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR29_B948() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR29_B949(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR29_B949() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR29_B950(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR29_B950() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR29_B951(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR29_B951() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR29_B952(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR29_B952() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR29_B953(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR29_B953() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR29_B954(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR29_B954() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR29_B955(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR29_B955() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR29_B956(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR29_B956() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR29_B957(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR29_B957() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR29_B958(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR29_B958() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR29_B959(value uint32) {
	volatile.StoreUint32(&o.VCTR29.Reg, volatile.LoadUint32(&o.VCTR29.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR29_B959() uint32 {
	return (volatile.LoadUint32(&o.VCTR29.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR30: MPCBBx vector register
func (o *GTZC_Type) SetVCTR30_B960(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR30_B960() uint32 {
	return volatile.LoadUint32(&o.VCTR30.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR30_B961(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR30_B961() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR30_B962(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR30_B962() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR30_B963(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR30_B963() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR30_B964(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR30_B964() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR30_B965(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR30_B965() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR30_B966(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR30_B966() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR30_B967(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR30_B967() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR30_B968(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR30_B968() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR30_B969(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR30_B969() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR30_B970(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR30_B970() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR30_B971(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR30_B971() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR30_B972(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR30_B972() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR30_B973(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR30_B973() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR30_B974(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR30_B974() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR30_B975(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR30_B975() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR30_B976(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR30_B976() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR30_B977(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR30_B977() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR30_B978(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR30_B978() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR30_B979(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR30_B979() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR30_B980(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR30_B980() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR30_B981(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR30_B981() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR30_B982(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR30_B982() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR30_B983(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR30_B983() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR30_B984(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR30_B984() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR30_B985(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR30_B985() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR30_B986(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR30_B986() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR30_B987(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR30_B987() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR30_B988(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR30_B988() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR30_B989(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR30_B989() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR30_B990(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR30_B990() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR30_B991(value uint32) {
	volatile.StoreUint32(&o.VCTR30.Reg, volatile.LoadUint32(&o.VCTR30.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR30_B991() uint32 {
	return (volatile.LoadUint32(&o.VCTR30.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR31: MPCBBx vector register
func (o *GTZC_Type) SetVCTR31_B992(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR31_B992() uint32 {
	return volatile.LoadUint32(&o.VCTR31.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR31_B993(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR31_B993() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR31_B994(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR31_B994() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR31_B995(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR31_B995() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR31_B996(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR31_B996() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR31_B997(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR31_B997() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR31_B998(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR31_B998() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR31_B999(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR31_B999() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR31_B1000(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR31_B1000() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR31_B1001(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR31_B1001() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR31_B1002(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR31_B1002() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR31_B1003(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR31_B1003() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR31_B1004(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR31_B1004() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR31_B1005(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR31_B1005() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR31_B1006(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR31_B1006() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR31_B1007(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR31_B1007() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR31_B1008(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR31_B1008() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR31_B1009(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR31_B1009() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR31_B1010(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR31_B1010() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR31_B1011(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR31_B1011() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR31_B1012(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR31_B1012() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR31_B1013(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR31_B1013() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR31_B1014(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR31_B1014() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR31_B1015(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR31_B1015() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR31_B1016(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR31_B1016() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR31_B1017(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR31_B1017() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR31_B1018(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR31_B1018() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR31_B1019(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR31_B1019() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR31_B1020(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR31_B1020() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR31_B1021(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR31_B1021() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR31_B1022(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR31_B1022() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR31_B1023(value uint32) {
	volatile.StoreUint32(&o.VCTR31.Reg, volatile.LoadUint32(&o.VCTR31.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR31_B1023() uint32 {
	return (volatile.LoadUint32(&o.VCTR31.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR32: MPCBBx vector register
func (o *GTZC_Type) SetVCTR32_B1024(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR32_B1024() uint32 {
	return volatile.LoadUint32(&o.VCTR32.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR32_B1025(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR32_B1025() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR32_B1026(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR32_B1026() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR32_B1027(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR32_B1027() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR32_B1028(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR32_B1028() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR32_B1029(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR32_B1029() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR32_B1030(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR32_B1030() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR32_B1031(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR32_B1031() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR32_B1032(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR32_B1032() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR32_B1033(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR32_B1033() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR32_B1034(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR32_B1034() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR32_B1035(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR32_B1035() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR32_B1036(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR32_B1036() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR32_B1037(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR32_B1037() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR32_B1038(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR32_B1038() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR32_B1039(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR32_B1039() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR32_B1040(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR32_B1040() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR32_B1041(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR32_B1041() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR32_B1042(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR32_B1042() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR32_B1043(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR32_B1043() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR32_B1044(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR32_B1044() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR32_B1045(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR32_B1045() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR32_B1046(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR32_B1046() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR32_B1047(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR32_B1047() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR32_B1048(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR32_B1048() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR32_B1049(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR32_B1049() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR32_B1050(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR32_B1050() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR32_B1051(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR32_B1051() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR32_B1052(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR32_B1052() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR32_B1053(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR32_B1053() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR32_B1054(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR32_B1054() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR32_B1055(value uint32) {
	volatile.StoreUint32(&o.VCTR32.Reg, volatile.LoadUint32(&o.VCTR32.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR32_B1055() uint32 {
	return (volatile.LoadUint32(&o.VCTR32.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR33: MPCBBx vector register
func (o *GTZC_Type) SetVCTR33_B1056(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR33_B1056() uint32 {
	return volatile.LoadUint32(&o.VCTR33.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR33_B1057(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR33_B1057() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR33_B1058(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR33_B1058() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR33_B1059(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR33_B1059() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR33_B1060(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR33_B1060() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR33_B1061(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR33_B1061() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR33_B1062(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR33_B1062() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR33_B1063(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR33_B1063() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR33_B1064(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR33_B1064() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR33_B1065(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR33_B1065() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR33_B1066(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR33_B1066() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR33_B1067(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR33_B1067() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR33_B1068(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR33_B1068() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR33_B1069(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR33_B1069() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR33_B1070(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR33_B1070() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR33_B1071(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR33_B1071() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR33_B1072(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR33_B1072() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR33_B1073(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR33_B1073() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR33_B1074(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR33_B1074() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR33_B1075(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR33_B1075() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR33_B1076(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR33_B1076() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR33_B1077(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR33_B1077() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR33_B1078(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR33_B1078() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR33_B1079(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR33_B1079() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR33_B1080(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR33_B1080() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR33_B1081(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR33_B1081() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR33_B1082(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR33_B1082() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR33_B1083(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR33_B1083() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR33_B1084(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR33_B1084() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR33_B1085(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR33_B1085() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR33_B1086(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR33_B1086() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR33_B1087(value uint32) {
	volatile.StoreUint32(&o.VCTR33.Reg, volatile.LoadUint32(&o.VCTR33.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR33_B1087() uint32 {
	return (volatile.LoadUint32(&o.VCTR33.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR34: MPCBBx vector register
func (o *GTZC_Type) SetVCTR34_B1088(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR34_B1088() uint32 {
	return volatile.LoadUint32(&o.VCTR34.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR34_B1089(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR34_B1089() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR34_B1090(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR34_B1090() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR34_B1091(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR34_B1091() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR34_B1092(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR34_B1092() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR34_B1093(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR34_B1093() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR34_B1094(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR34_B1094() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR34_B1095(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR34_B1095() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR34_B1096(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR34_B1096() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR34_B1097(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR34_B1097() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR34_B1098(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR34_B1098() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR34_B1099(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR34_B1099() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR34_B1100(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR34_B1100() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR34_B1101(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR34_B1101() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR34_B1102(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR34_B1102() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR34_B1103(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR34_B1103() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR34_B1104(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR34_B1104() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR34_B1105(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR34_B1105() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR34_B1106(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR34_B1106() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR34_B1107(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR34_B1107() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR34_B1108(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR34_B1108() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR34_B1109(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR34_B1109() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR34_B1110(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR34_B1110() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR34_B1111(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR34_B1111() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR34_B1112(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR34_B1112() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR34_B1113(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR34_B1113() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR34_B1114(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR34_B1114() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR34_B1115(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR34_B1115() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR34_B1116(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR34_B1116() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR34_B1117(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR34_B1117() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR34_B1118(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR34_B1118() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR34_B1119(value uint32) {
	volatile.StoreUint32(&o.VCTR34.Reg, volatile.LoadUint32(&o.VCTR34.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR34_B1119() uint32 {
	return (volatile.LoadUint32(&o.VCTR34.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR35: MPCBBx vector register
func (o *GTZC_Type) SetVCTR35_B1120(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR35_B1120() uint32 {
	return volatile.LoadUint32(&o.VCTR35.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR35_B1121(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR35_B1121() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR35_B1122(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR35_B1122() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR35_B1123(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR35_B1123() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR35_B1124(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR35_B1124() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR35_B1125(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR35_B1125() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR35_B1126(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR35_B1126() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR35_B1127(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR35_B1127() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR35_B1128(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR35_B1128() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR35_B1129(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR35_B1129() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR35_B1130(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR35_B1130() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR35_B1131(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR35_B1131() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR35_B1132(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR35_B1132() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR35_B1133(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR35_B1133() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR35_B1134(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR35_B1134() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR35_B1135(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR35_B1135() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR35_B1136(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR35_B1136() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR35_B1137(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR35_B1137() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR35_B1138(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR35_B1138() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR35_B1139(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR35_B1139() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR35_B1140(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR35_B1140() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR35_B1141(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR35_B1141() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR35_B1142(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR35_B1142() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR35_B1143(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR35_B1143() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR35_B1144(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR35_B1144() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR35_B1145(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR35_B1145() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR35_B1146(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR35_B1146() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR35_B1147(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR35_B1147() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR35_B1148(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR35_B1148() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR35_B1149(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR35_B1149() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR35_B1150(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR35_B1150() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR35_B1151(value uint32) {
	volatile.StoreUint32(&o.VCTR35.Reg, volatile.LoadUint32(&o.VCTR35.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR35_B1151() uint32 {
	return (volatile.LoadUint32(&o.VCTR35.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR36: MPCBBx vector register
func (o *GTZC_Type) SetVCTR36_B1152(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR36_B1152() uint32 {
	return volatile.LoadUint32(&o.VCTR36.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR36_B1153(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR36_B1153() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR36_B1154(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR36_B1154() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR36_B1155(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR36_B1155() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR36_B1156(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR36_B1156() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR36_B1157(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR36_B1157() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR36_B1158(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR36_B1158() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR36_B1159(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR36_B1159() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR36_B1160(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR36_B1160() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR36_B1161(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR36_B1161() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR36_B1162(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR36_B1162() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR36_B1163(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR36_B1163() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR36_B1164(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR36_B1164() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR36_B1165(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR36_B1165() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR36_B1166(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR36_B1166() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR36_B1167(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR36_B1167() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR36_B1168(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR36_B1168() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR36_B1169(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR36_B1169() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR36_B1170(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR36_B1170() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR36_B1171(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR36_B1171() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR36_B1172(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR36_B1172() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR36_B1173(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR36_B1173() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR36_B1174(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR36_B1174() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR36_B1175(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR36_B1175() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR36_B1176(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR36_B1176() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR36_B1177(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR36_B1177() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR36_B1178(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR36_B1178() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR36_B1179(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR36_B1179() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR36_B1180(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR36_B1180() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR36_B1181(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR36_B1181() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR36_B1182(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR36_B1182() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR36_B1183(value uint32) {
	volatile.StoreUint32(&o.VCTR36.Reg, volatile.LoadUint32(&o.VCTR36.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR36_B1183() uint32 {
	return (volatile.LoadUint32(&o.VCTR36.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR37: MPCBBx vector register
func (o *GTZC_Type) SetVCTR37_B1184(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR37_B1184() uint32 {
	return volatile.LoadUint32(&o.VCTR37.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR37_B1185(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR37_B1185() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR37_B1186(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR37_B1186() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR37_B1187(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR37_B1187() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR37_B1188(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR37_B1188() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR37_B1189(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR37_B1189() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR37_B1190(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR37_B1190() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR37_B1191(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR37_B1191() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR37_B1192(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR37_B1192() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR37_B1193(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR37_B1193() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR37_B1194(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR37_B1194() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR37_B1195(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR37_B1195() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR37_B1196(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR37_B1196() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR37_B1197(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR37_B1197() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR37_B1198(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR37_B1198() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR37_B1199(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR37_B1199() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR37_B1200(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR37_B1200() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR37_B1201(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR37_B1201() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR37_B1202(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR37_B1202() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR37_B1203(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR37_B1203() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR37_B1204(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR37_B1204() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR37_B1205(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR37_B1205() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR37_B1206(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR37_B1206() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR37_B1207(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR37_B1207() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR37_B1208(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR37_B1208() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR37_B1209(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR37_B1209() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR37_B1210(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR37_B1210() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR37_B1211(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR37_B1211() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR37_B1212(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR37_B1212() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR37_B1213(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR37_B1213() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR37_B1214(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR37_B1214() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR37_B1215(value uint32) {
	volatile.StoreUint32(&o.VCTR37.Reg, volatile.LoadUint32(&o.VCTR37.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR37_B1215() uint32 {
	return (volatile.LoadUint32(&o.VCTR37.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR38: MPCBBx vector register
func (o *GTZC_Type) SetVCTR38_B1216(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR38_B1216() uint32 {
	return volatile.LoadUint32(&o.VCTR38.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR38_B1217(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR38_B1217() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR38_B1218(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR38_B1218() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR38_B1219(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR38_B1219() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR38_B1220(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR38_B1220() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR38_B1221(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR38_B1221() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR38_B1222(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR38_B1222() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR38_B1223(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR38_B1223() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR38_B1224(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR38_B1224() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR38_B1225(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR38_B1225() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR38_B1226(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR38_B1226() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR38_B1227(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR38_B1227() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR38_B1228(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR38_B1228() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR38_B1229(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR38_B1229() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR38_B1230(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR38_B1230() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR38_B1231(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR38_B1231() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR38_B1232(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR38_B1232() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR38_B1233(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR38_B1233() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR38_B1234(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR38_B1234() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR38_B1235(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR38_B1235() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR38_B1236(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR38_B1236() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR38_B1237(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR38_B1237() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR38_B1238(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR38_B1238() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR38_B1239(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR38_B1239() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR38_B1240(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR38_B1240() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR38_B1241(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR38_B1241() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR38_B1242(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR38_B1242() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR38_B1243(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR38_B1243() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR38_B1244(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR38_B1244() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR38_B1245(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR38_B1245() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR38_B1246(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR38_B1246() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR38_B1247(value uint32) {
	volatile.StoreUint32(&o.VCTR38.Reg, volatile.LoadUint32(&o.VCTR38.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR38_B1247() uint32 {
	return (volatile.LoadUint32(&o.VCTR38.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR39: MPCBBx vector register
func (o *GTZC_Type) SetVCTR39_B1248(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR39_B1248() uint32 {
	return volatile.LoadUint32(&o.VCTR39.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR39_B1249(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR39_B1249() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR39_B1250(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR39_B1250() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR39_B1251(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR39_B1251() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR39_B1252(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR39_B1252() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR39_B1253(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR39_B1253() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR39_B1254(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR39_B1254() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR39_B1255(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR39_B1255() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR39_B1256(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR39_B1256() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR39_B1257(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR39_B1257() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR39_B1258(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR39_B1258() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR39_B1259(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR39_B1259() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR39_B1260(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR39_B1260() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR39_B1261(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR39_B1261() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR39_B1262(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR39_B1262() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR39_B1263(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR39_B1263() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR39_B1264(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR39_B1264() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR39_B1265(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR39_B1265() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR39_B1266(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR39_B1266() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR39_B1267(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR39_B1267() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR39_B1268(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR39_B1268() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR39_B1269(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR39_B1269() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR39_B1270(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR39_B1270() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR39_B1271(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR39_B1271() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR39_B1272(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR39_B1272() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR39_B1273(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR39_B1273() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR39_B1274(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR39_B1274() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR39_B1275(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR39_B1275() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR39_B1276(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR39_B1276() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR39_B1277(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR39_B1277() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR39_B1278(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR39_B1278() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR39_B1279(value uint32) {
	volatile.StoreUint32(&o.VCTR39.Reg, volatile.LoadUint32(&o.VCTR39.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR39_B1279() uint32 {
	return (volatile.LoadUint32(&o.VCTR39.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR40: MPCBBx vector register
func (o *GTZC_Type) SetVCTR40_B1280(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR40_B1280() uint32 {
	return volatile.LoadUint32(&o.VCTR40.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR40_B1281(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR40_B1281() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR40_B1282(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR40_B1282() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR40_B1283(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR40_B1283() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR40_B1284(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR40_B1284() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR40_B1285(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR40_B1285() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR40_B1286(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR40_B1286() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR40_B1287(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR40_B1287() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR40_B1288(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR40_B1288() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR40_B1289(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR40_B1289() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR40_B1290(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR40_B1290() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR40_B1291(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR40_B1291() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR40_B1292(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR40_B1292() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR40_B1293(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR40_B1293() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR40_B1294(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR40_B1294() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR40_B1295(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR40_B1295() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR40_B1296(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR40_B1296() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR40_B1297(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR40_B1297() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR40_B1298(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR40_B1298() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR40_B1299(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR40_B1299() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR40_B1300(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR40_B1300() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR40_B1301(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR40_B1301() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR40_B1302(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR40_B1302() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR40_B1303(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR40_B1303() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR40_B1304(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR40_B1304() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR40_B1305(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR40_B1305() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR40_B1306(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR40_B1306() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR40_B1307(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR40_B1307() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR40_B1308(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR40_B1308() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR40_B1309(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR40_B1309() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR40_B1310(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR40_B1310() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR40_B1311(value uint32) {
	volatile.StoreUint32(&o.VCTR40.Reg, volatile.LoadUint32(&o.VCTR40.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR40_B1311() uint32 {
	return (volatile.LoadUint32(&o.VCTR40.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR41: MPCBBx vector register
func (o *GTZC_Type) SetVCTR41_B1312(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR41_B1312() uint32 {
	return volatile.LoadUint32(&o.VCTR41.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR41_B1313(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR41_B1313() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR41_B1314(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR41_B1314() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR41_B1315(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR41_B1315() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR41_B1316(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR41_B1316() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR41_B1317(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR41_B1317() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR41_B1318(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR41_B1318() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR41_B1319(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR41_B1319() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR41_B1320(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR41_B1320() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR41_B1321(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR41_B1321() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR41_B1322(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR41_B1322() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR41_B1323(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR41_B1323() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR41_B1324(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR41_B1324() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR41_B1325(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR41_B1325() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR41_B1326(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR41_B1326() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR41_B1327(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR41_B1327() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR41_B1328(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR41_B1328() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR41_B1329(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR41_B1329() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR41_B1330(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR41_B1330() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR41_B1331(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR41_B1331() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR41_B1332(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR41_B1332() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR41_B1333(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR41_B1333() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR41_B1334(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR41_B1334() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR41_B1335(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR41_B1335() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR41_B1336(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR41_B1336() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR41_B1337(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR41_B1337() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR41_B1338(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR41_B1338() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR41_B1339(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR41_B1339() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR41_B1340(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR41_B1340() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR41_B1341(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR41_B1341() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR41_B1342(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR41_B1342() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR41_B1343(value uint32) {
	volatile.StoreUint32(&o.VCTR41.Reg, volatile.LoadUint32(&o.VCTR41.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR41_B1343() uint32 {
	return (volatile.LoadUint32(&o.VCTR41.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR42: MPCBBx vector register
func (o *GTZC_Type) SetVCTR42_B1344(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR42_B1344() uint32 {
	return volatile.LoadUint32(&o.VCTR42.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR42_B1345(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR42_B1345() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR42_B1346(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR42_B1346() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR42_B1347(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR42_B1347() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR42_B1348(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR42_B1348() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR42_B1349(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR42_B1349() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR42_B1350(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR42_B1350() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR42_B1351(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR42_B1351() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR42_B1352(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR42_B1352() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR42_B1353(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR42_B1353() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR42_B1354(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR42_B1354() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR42_B1355(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR42_B1355() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR42_B1356(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR42_B1356() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR42_B1357(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR42_B1357() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR42_B1358(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR42_B1358() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR42_B1359(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR42_B1359() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR42_B1360(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR42_B1360() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR42_B1361(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR42_B1361() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR42_B1362(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR42_B1362() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR42_B1363(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR42_B1363() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR42_B1364(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR42_B1364() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR42_B1365(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR42_B1365() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR42_B1366(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR42_B1366() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR42_B1367(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR42_B1367() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR42_B1368(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR42_B1368() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR42_B1369(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR42_B1369() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR42_B1370(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR42_B1370() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR42_B1371(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR42_B1371() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR42_B1372(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR42_B1372() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR42_B1373(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR42_B1373() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR42_B1374(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR42_B1374() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR42_B1375(value uint32) {
	volatile.StoreUint32(&o.VCTR42.Reg, volatile.LoadUint32(&o.VCTR42.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR42_B1375() uint32 {
	return (volatile.LoadUint32(&o.VCTR42.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR43: MPCBBx vector register
func (o *GTZC_Type) SetVCTR43_B1376(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR43_B1376() uint32 {
	return volatile.LoadUint32(&o.VCTR43.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR43_B1377(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR43_B1377() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR43_B1378(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR43_B1378() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR43_B1379(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR43_B1379() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR43_B1380(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR43_B1380() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR43_B1381(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR43_B1381() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR43_B1382(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR43_B1382() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR43_B1383(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR43_B1383() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR43_B1384(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR43_B1384() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR43_B1385(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR43_B1385() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR43_B1386(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR43_B1386() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR43_B1387(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR43_B1387() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR43_B1388(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR43_B1388() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR43_B1389(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR43_B1389() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR43_B1390(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR43_B1390() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR43_B1391(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR43_B1391() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR43_B1392(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR43_B1392() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR43_B1393(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR43_B1393() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR43_B1394(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR43_B1394() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR43_B1395(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR43_B1395() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR43_B1396(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR43_B1396() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR43_B1397(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR43_B1397() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR43_B1398(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR43_B1398() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR43_B1399(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR43_B1399() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR43_B1400(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR43_B1400() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR43_B1401(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR43_B1401() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR43_B1402(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR43_B1402() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR43_B1403(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR43_B1403() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR43_B1404(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR43_B1404() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR43_B1405(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR43_B1405() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR43_B1406(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR43_B1406() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR43_B1407(value uint32) {
	volatile.StoreUint32(&o.VCTR43.Reg, volatile.LoadUint32(&o.VCTR43.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR43_B1407() uint32 {
	return (volatile.LoadUint32(&o.VCTR43.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR44: MPCBBx vector register
func (o *GTZC_Type) SetVCTR44_B1408(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR44_B1408() uint32 {
	return volatile.LoadUint32(&o.VCTR44.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR44_B1409(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR44_B1409() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR44_B1410(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR44_B1410() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR44_B1411(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR44_B1411() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR44_B1412(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR44_B1412() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR44_B1413(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR44_B1413() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR44_B1414(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR44_B1414() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR44_B1415(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR44_B1415() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR44_B1416(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR44_B1416() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR44_B1417(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR44_B1417() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR44_B1418(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR44_B1418() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR44_B1419(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR44_B1419() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR44_B1420(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR44_B1420() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR44_B1421(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR44_B1421() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR44_B1422(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR44_B1422() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR44_B1423(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR44_B1423() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR44_B1424(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR44_B1424() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR44_B1425(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR44_B1425() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR44_B1426(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR44_B1426() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR44_B1427(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR44_B1427() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR44_B1428(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR44_B1428() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR44_B1429(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR44_B1429() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR44_B1430(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR44_B1430() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR44_B1431(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR44_B1431() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR44_B1432(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR44_B1432() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR44_B1433(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR44_B1433() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR44_B1434(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR44_B1434() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR44_B1435(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR44_B1435() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR44_B1436(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR44_B1436() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR44_B1437(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR44_B1437() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR44_B1438(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR44_B1438() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR44_B1439(value uint32) {
	volatile.StoreUint32(&o.VCTR44.Reg, volatile.LoadUint32(&o.VCTR44.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR44_B1439() uint32 {
	return (volatile.LoadUint32(&o.VCTR44.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR45: MPCBBx vector register
func (o *GTZC_Type) SetVCTR45_B1440(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR45_B1440() uint32 {
	return volatile.LoadUint32(&o.VCTR45.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR45_B1441(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR45_B1441() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR45_B1442(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR45_B1442() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR45_B1443(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR45_B1443() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR45_B1444(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR45_B1444() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR45_B1445(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR45_B1445() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR45_B1446(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR45_B1446() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR45_B1447(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR45_B1447() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR45_B1448(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR45_B1448() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR45_B1449(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR45_B1449() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR45_B1450(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR45_B1450() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR45_B1451(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR45_B1451() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR45_B1452(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR45_B1452() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR45_B1453(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR45_B1453() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR45_B1454(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR45_B1454() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR45_B1455(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR45_B1455() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR45_B1456(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR45_B1456() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR45_B1457(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR45_B1457() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR45_B1458(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR45_B1458() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR45_B1459(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR45_B1459() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR45_B1460(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR45_B1460() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR45_B1461(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR45_B1461() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR45_B1462(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR45_B1462() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR45_B1463(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR45_B1463() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR45_B1464(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR45_B1464() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR45_B1465(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR45_B1465() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR45_B1466(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR45_B1466() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR45_B1467(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR45_B1467() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR45_B1468(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR45_B1468() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR45_B1469(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR45_B1469() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR45_B1470(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR45_B1470() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR45_B1471(value uint32) {
	volatile.StoreUint32(&o.VCTR45.Reg, volatile.LoadUint32(&o.VCTR45.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR45_B1471() uint32 {
	return (volatile.LoadUint32(&o.VCTR45.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR46: MPCBBx vector register
func (o *GTZC_Type) SetVCTR46_B1472(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR46_B1472() uint32 {
	return volatile.LoadUint32(&o.VCTR46.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR46_B1473(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR46_B1473() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR46_B1474(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR46_B1474() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR46_B1475(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR46_B1475() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR46_B1476(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR46_B1476() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR46_B1477(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR46_B1477() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR46_B1478(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR46_B1478() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR46_B1479(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR46_B1479() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR46_B1480(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR46_B1480() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR46_B1481(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR46_B1481() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR46_B1482(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR46_B1482() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR46_B1483(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR46_B1483() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR46_B1484(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR46_B1484() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR46_B1485(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR46_B1485() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR46_B1486(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR46_B1486() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR46_B1487(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR46_B1487() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR46_B1488(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR46_B1488() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR46_B1489(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR46_B1489() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR46_B1490(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR46_B1490() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR46_B1491(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR46_B1491() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR46_B1492(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR46_B1492() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR46_B1493(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR46_B1493() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR46_B1494(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR46_B1494() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR46_B1495(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR46_B1495() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR46_B1496(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR46_B1496() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR46_B1497(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR46_B1497() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR46_B1498(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR46_B1498() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR46_B1499(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR46_B1499() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR46_B1500(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR46_B1500() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR46_B1501(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR46_B1501() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR46_B1502(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR46_B1502() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR46_B1503(value uint32) {
	volatile.StoreUint32(&o.VCTR46.Reg, volatile.LoadUint32(&o.VCTR46.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR46_B1503() uint32 {
	return (volatile.LoadUint32(&o.VCTR46.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR47: MPCBBx vector register
func (o *GTZC_Type) SetVCTR47_B1504(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR47_B1504() uint32 {
	return volatile.LoadUint32(&o.VCTR47.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR47_B1505(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR47_B1505() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR47_B1506(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR47_B1506() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR47_B1507(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR47_B1507() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR47_B1508(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR47_B1508() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR47_B1509(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR47_B1509() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR47_B1510(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR47_B1510() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR47_B1511(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR47_B1511() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR47_B1512(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR47_B1512() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR47_B1513(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR47_B1513() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR47_B1514(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR47_B1514() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR47_B1515(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR47_B1515() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR47_B1516(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR47_B1516() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR47_B1517(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR47_B1517() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR47_B1518(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR47_B1518() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR47_B1519(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR47_B1519() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR47_B1520(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR47_B1520() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR47_B1521(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR47_B1521() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR47_B1522(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR47_B1522() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR47_B1523(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR47_B1523() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR47_B1524(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR47_B1524() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR47_B1525(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR47_B1525() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR47_B1526(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR47_B1526() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR47_B1527(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR47_B1527() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR47_B1528(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR47_B1528() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR47_B1529(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR47_B1529() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR47_B1530(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR47_B1530() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR47_B1531(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR47_B1531() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR47_B1532(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR47_B1532() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR47_B1533(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR47_B1533() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR47_B1534(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR47_B1534() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR47_B1535(value uint32) {
	volatile.StoreUint32(&o.VCTR47.Reg, volatile.LoadUint32(&o.VCTR47.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR47_B1535() uint32 {
	return (volatile.LoadUint32(&o.VCTR47.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR48: MPCBBx vector register
func (o *GTZC_Type) SetVCTR48_B1536(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR48_B1536() uint32 {
	return volatile.LoadUint32(&o.VCTR48.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR48_B1537(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR48_B1537() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR48_B1538(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR48_B1538() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR48_B1539(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR48_B1539() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR48_B1540(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR48_B1540() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR48_B1541(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR48_B1541() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR48_B1542(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR48_B1542() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR48_B1543(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR48_B1543() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR48_B1544(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR48_B1544() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR48_B1545(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR48_B1545() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR48_B1546(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR48_B1546() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR48_B1547(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR48_B1547() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR48_B1548(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR48_B1548() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR48_B1549(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR48_B1549() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR48_B1550(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR48_B1550() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR48_B1551(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR48_B1551() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR48_B1552(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR48_B1552() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR48_B1553(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR48_B1553() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR48_B1554(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR48_B1554() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR48_B1555(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR48_B1555() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR48_B1556(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR48_B1556() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR48_B1557(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR48_B1557() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR48_B1558(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR48_B1558() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR48_B1559(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR48_B1559() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR48_B1560(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR48_B1560() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR48_B1561(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR48_B1561() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR48_B1562(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR48_B1562() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR48_B1563(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR48_B1563() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR48_B1564(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR48_B1564() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR48_B1565(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR48_B1565() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR48_B1566(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR48_B1566() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR48_B1567(value uint32) {
	volatile.StoreUint32(&o.VCTR48.Reg, volatile.LoadUint32(&o.VCTR48.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR48_B1567() uint32 {
	return (volatile.LoadUint32(&o.VCTR48.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR49: MPCBBx vector register
func (o *GTZC_Type) SetVCTR49_B1568(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR49_B1568() uint32 {
	return volatile.LoadUint32(&o.VCTR49.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR49_B1569(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR49_B1569() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR49_B1570(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR49_B1570() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR49_B1571(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR49_B1571() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR49_B1572(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR49_B1572() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR49_B1573(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR49_B1573() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR49_B1574(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR49_B1574() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR49_B1575(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR49_B1575() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR49_B1576(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR49_B1576() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR49_B1577(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR49_B1577() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR49_B1578(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR49_B1578() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR49_B1579(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR49_B1579() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR49_B1580(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR49_B1580() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR49_B1581(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR49_B1581() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR49_B1582(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR49_B1582() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR49_B1583(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR49_B1583() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR49_B1584(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR49_B1584() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR49_B1585(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR49_B1585() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR49_B1586(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR49_B1586() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR49_B1587(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR49_B1587() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR49_B1588(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR49_B1588() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR49_B1589(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR49_B1589() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR49_B1590(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR49_B1590() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR49_B1591(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR49_B1591() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR49_B1592(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR49_B1592() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR49_B1593(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR49_B1593() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR49_B1594(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR49_B1594() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR49_B1595(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR49_B1595() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR49_B1596(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR49_B1596() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR49_B1597(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR49_B1597() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR49_B1598(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR49_B1598() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR49_B1599(value uint32) {
	volatile.StoreUint32(&o.VCTR49.Reg, volatile.LoadUint32(&o.VCTR49.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR49_B1599() uint32 {
	return (volatile.LoadUint32(&o.VCTR49.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR50: MPCBBx vector register
func (o *GTZC_Type) SetVCTR50_B1600(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR50_B1600() uint32 {
	return volatile.LoadUint32(&o.VCTR50.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR50_B1601(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR50_B1601() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR50_B1602(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR50_B1602() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR50_B1603(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR50_B1603() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR50_B1604(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR50_B1604() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR50_B1605(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR50_B1605() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR50_B1606(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR50_B1606() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR50_B1607(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR50_B1607() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR50_B1608(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR50_B1608() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR50_B1609(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR50_B1609() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR50_B1610(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR50_B1610() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR50_B1611(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR50_B1611() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR50_B1612(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR50_B1612() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR50_B1613(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR50_B1613() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR50_B1614(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR50_B1614() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR50_B1615(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR50_B1615() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR50_B1616(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR50_B1616() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR50_B1617(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR50_B1617() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR50_B1618(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR50_B1618() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR50_B1619(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR50_B1619() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR50_B1620(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR50_B1620() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR50_B1621(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR50_B1621() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR50_B1622(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR50_B1622() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR50_B1623(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR50_B1623() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR50_B1624(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR50_B1624() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR50_B1625(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR50_B1625() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR50_B1626(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR50_B1626() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR50_B1627(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR50_B1627() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR50_B1628(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR50_B1628() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR50_B1629(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR50_B1629() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR50_B1630(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR50_B1630() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR50_B1631(value uint32) {
	volatile.StoreUint32(&o.VCTR50.Reg, volatile.LoadUint32(&o.VCTR50.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR50_B1631() uint32 {
	return (volatile.LoadUint32(&o.VCTR50.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR51: MPCBBx vector register
func (o *GTZC_Type) SetVCTR51_B1632(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR51_B1632() uint32 {
	return volatile.LoadUint32(&o.VCTR51.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR51_B1633(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR51_B1633() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR51_B1634(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR51_B1634() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR51_B1635(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR51_B1635() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR51_B1636(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR51_B1636() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR51_B1637(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR51_B1637() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR51_B1638(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR51_B1638() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR51_B1639(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR51_B1639() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR51_B1640(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR51_B1640() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR51_B1641(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR51_B1641() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR51_B1642(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR51_B1642() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR51_B1643(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR51_B1643() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR51_B1644(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR51_B1644() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR51_B1645(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR51_B1645() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR51_B1646(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR51_B1646() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR51_B1647(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR51_B1647() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR51_B1648(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR51_B1648() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR51_B1649(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR51_B1649() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR51_B1650(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR51_B1650() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR51_B1651(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR51_B1651() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR51_B1652(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR51_B1652() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR51_B1653(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR51_B1653() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR51_B1654(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR51_B1654() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR51_B1655(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR51_B1655() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR51_B1656(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR51_B1656() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR51_B1657(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR51_B1657() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR51_B1658(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR51_B1658() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR51_B1659(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR51_B1659() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR51_B1660(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR51_B1660() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR51_B1661(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR51_B1661() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR51_B1662(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR51_B1662() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR51_B1663(value uint32) {
	volatile.StoreUint32(&o.VCTR51.Reg, volatile.LoadUint32(&o.VCTR51.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR51_B1663() uint32 {
	return (volatile.LoadUint32(&o.VCTR51.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR52: MPCBBx vector register
func (o *GTZC_Type) SetVCTR52_B1664(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR52_B1664() uint32 {
	return volatile.LoadUint32(&o.VCTR52.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR52_B1665(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR52_B1665() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR52_B1666(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR52_B1666() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR52_B1667(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR52_B1667() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR52_B1668(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR52_B1668() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR52_B1669(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR52_B1669() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR52_B1670(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR52_B1670() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR52_B1671(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR52_B1671() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR52_B1672(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR52_B1672() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR52_B1673(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR52_B1673() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR52_B1674(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR52_B1674() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR52_B1675(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR52_B1675() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR52_B1676(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR52_B1676() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR52_B1677(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR52_B1677() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR52_B1678(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR52_B1678() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR52_B1679(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR52_B1679() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR52_B1680(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR52_B1680() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR52_B1681(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR52_B1681() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR52_B1682(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR52_B1682() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR52_B1683(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR52_B1683() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR52_B1684(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR52_B1684() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR52_B1685(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR52_B1685() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR52_B1686(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR52_B1686() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR52_B1687(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR52_B1687() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR52_B1688(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR52_B1688() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR52_B1689(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR52_B1689() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR52_B1690(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR52_B1690() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR52_B1691(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR52_B1691() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR52_B1692(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR52_B1692() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR52_B1693(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR52_B1693() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR52_B1694(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR52_B1694() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR52_B1695(value uint32) {
	volatile.StoreUint32(&o.VCTR52.Reg, volatile.LoadUint32(&o.VCTR52.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR52_B1695() uint32 {
	return (volatile.LoadUint32(&o.VCTR52.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR53: MPCBBx vector register
func (o *GTZC_Type) SetVCTR53_B1696(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR53_B1696() uint32 {
	return volatile.LoadUint32(&o.VCTR53.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR53_B1697(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR53_B1697() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR53_B1698(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR53_B1698() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR53_B1699(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR53_B1699() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR53_B1700(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR53_B1700() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR53_B1701(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR53_B1701() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR53_B1702(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR53_B1702() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR53_B1703(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR53_B1703() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR53_B1704(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR53_B1704() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR53_B1705(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR53_B1705() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR53_B1706(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR53_B1706() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR53_B1707(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR53_B1707() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR53_B1708(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR53_B1708() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR53_B1709(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR53_B1709() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR53_B1710(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR53_B1710() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR53_B1711(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR53_B1711() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR53_B1712(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR53_B1712() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR53_B1713(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR53_B1713() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR53_B1714(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR53_B1714() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR53_B1715(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR53_B1715() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR53_B1716(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR53_B1716() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR53_B1717(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR53_B1717() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR53_B1718(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR53_B1718() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR53_B1719(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR53_B1719() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR53_B1720(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR53_B1720() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR53_B1721(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR53_B1721() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR53_B1722(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR53_B1722() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR53_B1723(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR53_B1723() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR53_B1724(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR53_B1724() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR53_B1725(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR53_B1725() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR53_B1726(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR53_B1726() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR53_B1727(value uint32) {
	volatile.StoreUint32(&o.VCTR53.Reg, volatile.LoadUint32(&o.VCTR53.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR53_B1727() uint32 {
	return (volatile.LoadUint32(&o.VCTR53.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR54: MPCBBx vector register
func (o *GTZC_Type) SetVCTR54_B1728(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR54_B1728() uint32 {
	return volatile.LoadUint32(&o.VCTR54.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR54_B1729(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR54_B1729() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR54_B1730(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR54_B1730() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR54_B1731(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR54_B1731() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR54_B1732(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR54_B1732() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR54_B1733(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR54_B1733() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR54_B1734(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR54_B1734() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR54_B1735(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR54_B1735() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR54_B1736(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR54_B1736() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR54_B1737(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR54_B1737() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR54_B1738(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR54_B1738() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR54_B1739(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR54_B1739() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR54_B1740(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR54_B1740() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR54_B1741(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR54_B1741() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR54_B1742(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR54_B1742() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR54_B1743(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR54_B1743() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR54_B1744(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR54_B1744() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR54_B1745(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR54_B1745() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR54_B1746(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR54_B1746() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR54_B1747(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR54_B1747() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR54_B1748(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR54_B1748() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR54_B1749(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR54_B1749() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR54_B1750(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR54_B1750() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR54_B1751(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR54_B1751() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR54_B1752(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR54_B1752() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR54_B1753(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR54_B1753() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR54_B1754(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR54_B1754() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR54_B1755(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR54_B1755() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR54_B1756(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR54_B1756() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR54_B1757(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR54_B1757() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR54_B1758(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR54_B1758() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR54_B1759(value uint32) {
	volatile.StoreUint32(&o.VCTR54.Reg, volatile.LoadUint32(&o.VCTR54.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR54_B1759() uint32 {
	return (volatile.LoadUint32(&o.VCTR54.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR55: MPCBBx vector register
func (o *GTZC_Type) SetVCTR55_B1760(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR55_B1760() uint32 {
	return volatile.LoadUint32(&o.VCTR55.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR55_B1761(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR55_B1761() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR55_B1762(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR55_B1762() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR55_B1763(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR55_B1763() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR55_B1764(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR55_B1764() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR55_B1765(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR55_B1765() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR55_B1766(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR55_B1766() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR55_B1767(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR55_B1767() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR55_B1768(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR55_B1768() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR55_B1769(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR55_B1769() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR55_B1770(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR55_B1770() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR55_B1771(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR55_B1771() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR55_B1772(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR55_B1772() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR55_B1773(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR55_B1773() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR55_B1774(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR55_B1774() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR55_B1775(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR55_B1775() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR55_B1776(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR55_B1776() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR55_B1777(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR55_B1777() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR55_B1778(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR55_B1778() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR55_B1779(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR55_B1779() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR55_B1780(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR55_B1780() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR55_B1781(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR55_B1781() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR55_B1782(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR55_B1782() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR55_B1783(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR55_B1783() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR55_B1784(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR55_B1784() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR55_B1785(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR55_B1785() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR55_B1786(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR55_B1786() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR55_B1787(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR55_B1787() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR55_B1788(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR55_B1788() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR55_B1789(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR55_B1789() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR55_B1790(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR55_B1790() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR55_B1791(value uint32) {
	volatile.StoreUint32(&o.VCTR55.Reg, volatile.LoadUint32(&o.VCTR55.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR55_B1791() uint32 {
	return (volatile.LoadUint32(&o.VCTR55.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR56: MPCBBx vector register
func (o *GTZC_Type) SetVCTR56_B1792(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR56_B1792() uint32 {
	return volatile.LoadUint32(&o.VCTR56.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR56_B1793(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR56_B1793() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR56_B1794(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR56_B1794() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR56_B1795(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR56_B1795() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR56_B1796(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR56_B1796() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR56_B1797(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR56_B1797() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR56_B1798(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR56_B1798() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR56_B1799(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR56_B1799() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR56_B1800(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR56_B1800() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR56_B1801(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR56_B1801() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR56_B1802(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR56_B1802() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR56_B1803(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR56_B1803() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR56_B1804(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR56_B1804() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR56_B1805(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR56_B1805() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR56_B1806(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR56_B1806() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR56_B1807(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR56_B1807() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR56_B1808(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR56_B1808() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR56_B1809(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR56_B1809() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR56_B1810(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR56_B1810() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR56_B1811(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR56_B1811() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR56_B1812(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR56_B1812() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR56_B1813(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR56_B1813() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR56_B1814(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR56_B1814() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR56_B1815(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR56_B1815() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR56_B1816(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR56_B1816() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR56_B1817(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR56_B1817() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR56_B1818(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR56_B1818() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR56_B1819(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR56_B1819() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR56_B1820(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR56_B1820() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR56_B1821(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR56_B1821() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR56_B1822(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR56_B1822() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR56_B1823(value uint32) {
	volatile.StoreUint32(&o.VCTR56.Reg, volatile.LoadUint32(&o.VCTR56.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR56_B1823() uint32 {
	return (volatile.LoadUint32(&o.VCTR56.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR57: MPCBBx vector register
func (o *GTZC_Type) SetVCTR57_B1824(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR57_B1824() uint32 {
	return volatile.LoadUint32(&o.VCTR57.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR57_B1825(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR57_B1825() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR57_B1826(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR57_B1826() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR57_B1827(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR57_B1827() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR57_B1828(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR57_B1828() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR57_B1829(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR57_B1829() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR57_B1830(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR57_B1830() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR57_B1831(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR57_B1831() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR57_B1832(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR57_B1832() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR57_B1833(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR57_B1833() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR57_B1834(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR57_B1834() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR57_B1835(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR57_B1835() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR57_B1836(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR57_B1836() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR57_B1837(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR57_B1837() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR57_B1838(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR57_B1838() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR57_B1839(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR57_B1839() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR57_B1840(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR57_B1840() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR57_B1841(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR57_B1841() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR57_B1842(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR57_B1842() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR57_B1843(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR57_B1843() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR57_B1844(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR57_B1844() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR57_B1845(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR57_B1845() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR57_B1846(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR57_B1846() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR57_B1847(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR57_B1847() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR57_B1848(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR57_B1848() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR57_B1849(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR57_B1849() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR57_B1850(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR57_B1850() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR57_B1851(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR57_B1851() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR57_B1852(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR57_B1852() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR57_B1853(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR57_B1853() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR57_B1854(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR57_B1854() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR57_B1855(value uint32) {
	volatile.StoreUint32(&o.VCTR57.Reg, volatile.LoadUint32(&o.VCTR57.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR57_B1855() uint32 {
	return (volatile.LoadUint32(&o.VCTR57.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR58: MPCBBx vector register
func (o *GTZC_Type) SetVCTR58_B1856(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR58_B1856() uint32 {
	return volatile.LoadUint32(&o.VCTR58.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR58_B1857(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR58_B1857() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR58_B1858(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR58_B1858() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR58_B1859(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR58_B1859() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR58_B1860(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR58_B1860() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR58_B1861(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR58_B1861() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR58_B1862(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR58_B1862() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR58_B1863(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR58_B1863() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR58_B1864(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR58_B1864() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR58_B1865(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR58_B1865() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR58_B1866(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR58_B1866() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR58_B1867(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR58_B1867() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR58_B1868(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR58_B1868() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR58_B1869(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR58_B1869() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR58_B1870(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR58_B1870() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR58_B1871(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR58_B1871() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR58_B1872(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR58_B1872() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR58_B1873(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR58_B1873() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR58_B1874(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR58_B1874() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR58_B1875(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR58_B1875() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR58_B1876(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR58_B1876() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR58_B1877(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR58_B1877() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR58_B1878(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR58_B1878() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR58_B1879(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR58_B1879() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR58_B1880(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR58_B1880() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR58_B1881(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR58_B1881() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR58_B1882(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR58_B1882() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR58_B1883(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR58_B1883() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR58_B1884(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR58_B1884() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR58_B1885(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR58_B1885() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR58_B1886(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR58_B1886() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR58_B1887(value uint32) {
	volatile.StoreUint32(&o.VCTR58.Reg, volatile.LoadUint32(&o.VCTR58.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR58_B1887() uint32 {
	return (volatile.LoadUint32(&o.VCTR58.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR59: MPCBBx vector register
func (o *GTZC_Type) SetVCTR59_B1888(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR59_B1888() uint32 {
	return volatile.LoadUint32(&o.VCTR59.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR59_B1889(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR59_B1889() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR59_B1890(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR59_B1890() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR59_B1891(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR59_B1891() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR59_B1892(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR59_B1892() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR59_B1893(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR59_B1893() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR59_B1894(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR59_B1894() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR59_B1895(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR59_B1895() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR59_B1896(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR59_B1896() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR59_B1897(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR59_B1897() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR59_B1898(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR59_B1898() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR59_B1899(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR59_B1899() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR59_B1900(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR59_B1900() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR59_B1901(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR59_B1901() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR59_B1902(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR59_B1902() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR59_B1903(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR59_B1903() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR59_B1904(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR59_B1904() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR59_B1905(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR59_B1905() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR59_B1906(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR59_B1906() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR59_B1907(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR59_B1907() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR59_B1908(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR59_B1908() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR59_B1909(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR59_B1909() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR59_B1910(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR59_B1910() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR59_B1911(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR59_B1911() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR59_B1912(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR59_B1912() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR59_B1913(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR59_B1913() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR59_B1914(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR59_B1914() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR59_B1915(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR59_B1915() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR59_B1916(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR59_B1916() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR59_B1917(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR59_B1917() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR59_B1918(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR59_B1918() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR59_B1919(value uint32) {
	volatile.StoreUint32(&o.VCTR59.Reg, volatile.LoadUint32(&o.VCTR59.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR59_B1919() uint32 {
	return (volatile.LoadUint32(&o.VCTR59.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR60: MPCBBx vector register
func (o *GTZC_Type) SetVCTR60_B1920(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR60_B1920() uint32 {
	return volatile.LoadUint32(&o.VCTR60.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR60_B1921(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR60_B1921() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR60_B1922(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR60_B1922() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR60_B1923(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR60_B1923() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR60_B1924(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR60_B1924() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR60_B1925(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR60_B1925() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR60_B1926(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR60_B1926() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR60_B1927(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR60_B1927() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR60_B1928(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR60_B1928() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR60_B1929(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR60_B1929() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR60_B1930(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR60_B1930() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR60_B1931(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR60_B1931() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR60_B1932(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR60_B1932() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR60_B1933(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR60_B1933() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR60_B1934(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR60_B1934() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR60_B1935(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR60_B1935() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR60_B1936(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR60_B1936() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR60_B1937(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR60_B1937() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR60_B1938(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR60_B1938() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR60_B1939(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR60_B1939() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR60_B1940(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR60_B1940() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR60_B1941(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR60_B1941() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR60_B1942(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR60_B1942() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR60_B1943(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR60_B1943() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR60_B1944(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR60_B1944() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR60_B1945(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR60_B1945() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR60_B1946(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR60_B1946() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR60_B1947(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR60_B1947() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR60_B1948(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR60_B1948() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR60_B1949(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR60_B1949() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR60_B1950(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR60_B1950() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR60_B1951(value uint32) {
	volatile.StoreUint32(&o.VCTR60.Reg, volatile.LoadUint32(&o.VCTR60.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR60_B1951() uint32 {
	return (volatile.LoadUint32(&o.VCTR60.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR61: MPCBBx vector register
func (o *GTZC_Type) SetVCTR61_B1952(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR61_B1952() uint32 {
	return volatile.LoadUint32(&o.VCTR61.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR61_B1953(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR61_B1953() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR61_B1954(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR61_B1954() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR61_B1955(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR61_B1955() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR61_B1956(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR61_B1956() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR61_B1957(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR61_B1957() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR61_B1958(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR61_B1958() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR61_B1959(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR61_B1959() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR61_B1960(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR61_B1960() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR61_B1961(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR61_B1961() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR61_B1962(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR61_B1962() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR61_B1963(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR61_B1963() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR61_B1964(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR61_B1964() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR61_B1965(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR61_B1965() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR61_B1966(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR61_B1966() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR61_B1967(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR61_B1967() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR61_B1968(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR61_B1968() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR61_B1969(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR61_B1969() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR61_B1970(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR61_B1970() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR61_B1971(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR61_B1971() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR61_B1972(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR61_B1972() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR61_B1973(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR61_B1973() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR61_B1974(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR61_B1974() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR61_B1975(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR61_B1975() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR61_B1976(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR61_B1976() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR61_B1977(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR61_B1977() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR61_B1978(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR61_B1978() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR61_B1979(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR61_B1979() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR61_B1980(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR61_B1980() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR61_B1981(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR61_B1981() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR61_B1982(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR61_B1982() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR61_B1983(value uint32) {
	volatile.StoreUint32(&o.VCTR61.Reg, volatile.LoadUint32(&o.VCTR61.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR61_B1983() uint32 {
	return (volatile.LoadUint32(&o.VCTR61.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR62: MPCBBx vector register
func (o *GTZC_Type) SetVCTR62_B1984(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR62_B1984() uint32 {
	return volatile.LoadUint32(&o.VCTR62.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR62_B1985(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR62_B1985() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR62_B1986(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR62_B1986() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR62_B1987(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR62_B1987() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR62_B1988(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR62_B1988() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR62_B1989(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR62_B1989() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR62_B1990(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR62_B1990() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR62_B1991(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR62_B1991() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR62_B1992(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR62_B1992() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR62_B1993(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR62_B1993() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR62_B1994(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR62_B1994() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR62_B1995(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR62_B1995() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR62_B1996(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR62_B1996() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR62_B1997(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR62_B1997() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR62_B1998(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR62_B1998() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR62_B1999(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR62_B1999() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR62_B2000(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR62_B2000() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR62_B2001(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR62_B2001() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR62_B2002(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR62_B2002() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR62_B2003(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR62_B2003() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR62_B2004(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR62_B2004() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR62_B2005(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR62_B2005() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR62_B2006(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR62_B2006() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR62_B2007(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR62_B2007() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR62_B2008(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR62_B2008() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR62_B2009(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR62_B2009() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR62_B2010(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR62_B2010() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR62_B2011(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR62_B2011() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR62_B2012(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR62_B2012() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR62_B2013(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR62_B2013() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR62_B2014(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR62_B2014() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR62_B2015(value uint32) {
	volatile.StoreUint32(&o.VCTR62.Reg, volatile.LoadUint32(&o.VCTR62.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR62_B2015() uint32 {
	return (volatile.LoadUint32(&o.VCTR62.Reg) & 0x80000000) >> 31
}

// GTZC.VCTR63: MPCBBx vector register
func (o *GTZC_Type) SetVCTR63_B2016(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x1)|value)
}
func (o *GTZC_Type) GetVCTR63_B2016() uint32 {
	return volatile.LoadUint32(&o.VCTR63.Reg) & 0x1
}
func (o *GTZC_Type) SetVCTR63_B2017(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x2)|value<<1)
}
func (o *GTZC_Type) GetVCTR63_B2017() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x2) >> 1
}
func (o *GTZC_Type) SetVCTR63_B2018(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x4)|value<<2)
}
func (o *GTZC_Type) GetVCTR63_B2018() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x4) >> 2
}
func (o *GTZC_Type) SetVCTR63_B2019(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x8)|value<<3)
}
func (o *GTZC_Type) GetVCTR63_B2019() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x8) >> 3
}
func (o *GTZC_Type) SetVCTR63_B2020(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x10)|value<<4)
}
func (o *GTZC_Type) GetVCTR63_B2020() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x10) >> 4
}
func (o *GTZC_Type) SetVCTR63_B2021(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x20)|value<<5)
}
func (o *GTZC_Type) GetVCTR63_B2021() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x20) >> 5
}
func (o *GTZC_Type) SetVCTR63_B2022(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x40)|value<<6)
}
func (o *GTZC_Type) GetVCTR63_B2022() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x40) >> 6
}
func (o *GTZC_Type) SetVCTR63_B2023(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x80)|value<<7)
}
func (o *GTZC_Type) GetVCTR63_B2023() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x80) >> 7
}
func (o *GTZC_Type) SetVCTR63_B2024(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x100)|value<<8)
}
func (o *GTZC_Type) GetVCTR63_B2024() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x100) >> 8
}
func (o *GTZC_Type) SetVCTR63_B2025(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x200)|value<<9)
}
func (o *GTZC_Type) GetVCTR63_B2025() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x200) >> 9
}
func (o *GTZC_Type) SetVCTR63_B2026(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x400)|value<<10)
}
func (o *GTZC_Type) GetVCTR63_B2026() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x400) >> 10
}
func (o *GTZC_Type) SetVCTR63_B2027(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x800)|value<<11)
}
func (o *GTZC_Type) GetVCTR63_B2027() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x800) >> 11
}
func (o *GTZC_Type) SetVCTR63_B2028(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x1000)|value<<12)
}
func (o *GTZC_Type) GetVCTR63_B2028() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x1000) >> 12
}
func (o *GTZC_Type) SetVCTR63_B2029(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x2000)|value<<13)
}
func (o *GTZC_Type) GetVCTR63_B2029() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x2000) >> 13
}
func (o *GTZC_Type) SetVCTR63_B2030(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x4000)|value<<14)
}
func (o *GTZC_Type) GetVCTR63_B2030() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x4000) >> 14
}
func (o *GTZC_Type) SetVCTR63_B2031(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x8000)|value<<15)
}
func (o *GTZC_Type) GetVCTR63_B2031() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x8000) >> 15
}
func (o *GTZC_Type) SetVCTR63_B2032(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x10000)|value<<16)
}
func (o *GTZC_Type) GetVCTR63_B2032() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x10000) >> 16
}
func (o *GTZC_Type) SetVCTR63_B2033(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x20000)|value<<17)
}
func (o *GTZC_Type) GetVCTR63_B2033() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x20000) >> 17
}
func (o *GTZC_Type) SetVCTR63_B2034(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x40000)|value<<18)
}
func (o *GTZC_Type) GetVCTR63_B2034() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x40000) >> 18
}
func (o *GTZC_Type) SetVCTR63_B2035(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x80000)|value<<19)
}
func (o *GTZC_Type) GetVCTR63_B2035() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x80000) >> 19
}
func (o *GTZC_Type) SetVCTR63_B2036(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x100000)|value<<20)
}
func (o *GTZC_Type) GetVCTR63_B2036() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x100000) >> 20
}
func (o *GTZC_Type) SetVCTR63_B2037(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x200000)|value<<21)
}
func (o *GTZC_Type) GetVCTR63_B2037() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x200000) >> 21
}
func (o *GTZC_Type) SetVCTR63_B2038(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x400000)|value<<22)
}
func (o *GTZC_Type) GetVCTR63_B2038() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x400000) >> 22
}
func (o *GTZC_Type) SetVCTR63_B2039(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x800000)|value<<23)
}
func (o *GTZC_Type) GetVCTR63_B2039() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x800000) >> 23
}
func (o *GTZC_Type) SetVCTR63_B2040(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x1000000)|value<<24)
}
func (o *GTZC_Type) GetVCTR63_B2040() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x1000000) >> 24
}
func (o *GTZC_Type) SetVCTR63_B2041(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x2000000)|value<<25)
}
func (o *GTZC_Type) GetVCTR63_B2041() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x2000000) >> 25
}
func (o *GTZC_Type) SetVCTR63_B2042(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x4000000)|value<<26)
}
func (o *GTZC_Type) GetVCTR63_B2042() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x4000000) >> 26
}
func (o *GTZC_Type) SetVCTR63_B2043(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x8000000)|value<<27)
}
func (o *GTZC_Type) GetVCTR63_B2043() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x8000000) >> 27
}
func (o *GTZC_Type) SetVCTR63_B2044(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x10000000)|value<<28)
}
func (o *GTZC_Type) GetVCTR63_B2044() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x10000000) >> 28
}
func (o *GTZC_Type) SetVCTR63_B2045(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x20000000)|value<<29)
}
func (o *GTZC_Type) GetVCTR63_B2045() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x20000000) >> 29
}
func (o *GTZC_Type) SetVCTR63_B2046(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x40000000)|value<<30)
}
func (o *GTZC_Type) GetVCTR63_B2046() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x40000000) >> 30
}
func (o *GTZC_Type) SetVCTR63_B2047(value uint32) {
	volatile.StoreUint32(&o.VCTR63.Reg, volatile.LoadUint32(&o.VCTR63.Reg)&^(0x80000000)|value<<31)
}
func (o *GTZC_Type) GetVCTR63_B2047() uint32 {
	return (volatile.LoadUint32(&o.VCTR63.Reg) & 0x80000000) >> 31
}

// Hash processor
type HASH_Type struct {
	CR    volatile.Register32 // 0x0
	DIN   volatile.Register32 // 0x4
	STR   volatile.Register32 // 0x8
	HRA0  volatile.Register32 // 0xC
	HRA1  volatile.Register32 // 0x10
	HRA2  volatile.Register32 // 0x14
	HRA3  volatile.Register32 // 0x18
	HRA4  volatile.Register32 // 0x1C
	IMR   volatile.Register32 // 0x20
	SR    volatile.Register32 // 0x24
	_     [208]byte
	CSR0  volatile.Register32 // 0xF8
	CSR1  volatile.Register32 // 0xFC
	CSR2  volatile.Register32 // 0x100
	CSR3  volatile.Register32 // 0x104
	CSR4  volatile.Register32 // 0x108
	CSR5  volatile.Register32 // 0x10C
	CSR6  volatile.Register32 // 0x110
	CSR7  volatile.Register32 // 0x114
	CSR8  volatile.Register32 // 0x118
	CSR9  volatile.Register32 // 0x11C
	CSR10 volatile.Register32 // 0x120
	CSR11 volatile.Register32 // 0x124
	CSR12 volatile.Register32 // 0x128
	CSR13 volatile.Register32 // 0x12C
	CSR14 volatile.Register32 // 0x130
	CSR15 volatile.Register32 // 0x134
	CSR16 volatile.Register32 // 0x138
	CSR17 volatile.Register32 // 0x13C
	CSR18 volatile.Register32 // 0x140
	CSR19 volatile.Register32 // 0x144
	CSR20 volatile.Register32 // 0x148
	CSR21 volatile.Register32 // 0x14C
	CSR22 volatile.Register32 // 0x150
	CSR23 volatile.Register32 // 0x154
	CSR24 volatile.Register32 // 0x158
	CSR25 volatile.Register32 // 0x15C
	CSR26 volatile.Register32 // 0x160
	CSR27 volatile.Register32 // 0x164
	CSR28 volatile.Register32 // 0x168
	CSR29 volatile.Register32 // 0x16C
	CSR30 volatile.Register32 // 0x170
	CSR31 volatile.Register32 // 0x174
	CSR32 volatile.Register32 // 0x178
	CSR33 volatile.Register32 // 0x17C
	CSR34 volatile.Register32 // 0x180
	CSR35 volatile.Register32 // 0x184
	CSR36 volatile.Register32 // 0x188
	CSR37 volatile.Register32 // 0x18C
	CSR38 volatile.Register32 // 0x190
	CSR39 volatile.Register32 // 0x194
	CSR40 volatile.Register32 // 0x198
	CSR41 volatile.Register32 // 0x19C
	CSR42 volatile.Register32 // 0x1A0
	CSR43 volatile.Register32 // 0x1A4
	CSR44 volatile.Register32 // 0x1A8
	CSR45 volatile.Register32 // 0x1AC
	CSR46 volatile.Register32 // 0x1B0
	CSR47 volatile.Register32 // 0x1B4
	CSR48 volatile.Register32 // 0x1B8
	CSR49 volatile.Register32 // 0x1BC
	CSR50 volatile.Register32 // 0x1C0
	CSR51 volatile.Register32 // 0x1C4
	CSR52 volatile.Register32 // 0x1C8
	CSR53 volatile.Register32 // 0x1CC
	_     [320]byte
	HR0   volatile.Register32 // 0x310
	HR1   volatile.Register32 // 0x314
	HR2   volatile.Register32 // 0x318
	HR3   volatile.Register32 // 0x31C
	HR4   volatile.Register32 // 0x320
	HR5   volatile.Register32 // 0x324
	HR6   volatile.Register32 // 0x328
	HR7   volatile.Register32 // 0x32C
}

// HASH.CR: control register
func (o *HASH_Type) SetCR_INIT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *HASH_Type) GetCR_INIT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *HASH_Type) SetCR_DMAE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *HASH_Type) GetCR_DMAE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *HASH_Type) SetCR_DATATYPE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x30)|value<<4)
}
func (o *HASH_Type) GetCR_DATATYPE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x30) >> 4
}
func (o *HASH_Type) SetCR_MODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *HASH_Type) GetCR_MODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *HASH_Type) SetCR_ALGO0(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *HASH_Type) GetCR_ALGO0() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *HASH_Type) SetCR_NBW(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf00)|value<<8)
}
func (o *HASH_Type) GetCR_NBW() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf00) >> 8
}
func (o *HASH_Type) SetCR_DINNE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *HASH_Type) GetCR_DINNE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *HASH_Type) SetCR_MDMAT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *HASH_Type) GetCR_MDMAT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *HASH_Type) SetCR_LKEY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *HASH_Type) GetCR_LKEY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *HASH_Type) SetCR_ALGO1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *HASH_Type) GetCR_ALGO1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}

// HASH.DIN: data input register
func (o *HASH_Type) SetDIN(value uint32) {
	volatile.StoreUint32(&o.DIN.Reg, value)
}
func (o *HASH_Type) GetDIN() uint32 {
	return volatile.LoadUint32(&o.DIN.Reg)
}

// HASH.STR: start register
func (o *HASH_Type) SetSTR_DCAL(value uint32) {
	volatile.StoreUint32(&o.STR.Reg, volatile.LoadUint32(&o.STR.Reg)&^(0x100)|value<<8)
}
func (o *HASH_Type) GetSTR_DCAL() uint32 {
	return (volatile.LoadUint32(&o.STR.Reg) & 0x100) >> 8
}
func (o *HASH_Type) SetSTR_NBLW(value uint32) {
	volatile.StoreUint32(&o.STR.Reg, volatile.LoadUint32(&o.STR.Reg)&^(0x1f)|value)
}
func (o *HASH_Type) GetSTR_NBLW() uint32 {
	return volatile.LoadUint32(&o.STR.Reg) & 0x1f
}

// HASH.HRA0: HASH aliased digest register 0
func (o *HASH_Type) SetHRA0(value uint32) {
	volatile.StoreUint32(&o.HRA0.Reg, value)
}
func (o *HASH_Type) GetHRA0() uint32 {
	return volatile.LoadUint32(&o.HRA0.Reg)
}

// HASH.HRA1: HASH aliased digest register 1
func (o *HASH_Type) SetHRA1(value uint32) {
	volatile.StoreUint32(&o.HRA1.Reg, value)
}
func (o *HASH_Type) GetHRA1() uint32 {
	return volatile.LoadUint32(&o.HRA1.Reg)
}

// HASH.HRA2: HASH aliased digest register 2
func (o *HASH_Type) SetHRA2(value uint32) {
	volatile.StoreUint32(&o.HRA2.Reg, value)
}
func (o *HASH_Type) GetHRA2() uint32 {
	return volatile.LoadUint32(&o.HRA2.Reg)
}

// HASH.HRA3: HASH aliased digest register 3
func (o *HASH_Type) SetHRA3(value uint32) {
	volatile.StoreUint32(&o.HRA3.Reg, value)
}
func (o *HASH_Type) GetHRA3() uint32 {
	return volatile.LoadUint32(&o.HRA3.Reg)
}

// HASH.HRA4: HASH aliased digest register 4
func (o *HASH_Type) SetHRA4(value uint32) {
	volatile.StoreUint32(&o.HRA4.Reg, value)
}
func (o *HASH_Type) GetHRA4() uint32 {
	return volatile.LoadUint32(&o.HRA4.Reg)
}

// HASH.IMR: interrupt enable register
func (o *HASH_Type) SetIMR_DCIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *HASH_Type) GetIMR_DCIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *HASH_Type) SetIMR_DINIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *HASH_Type) GetIMR_DINIE() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}

// HASH.SR: status register
func (o *HASH_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *HASH_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *HASH_Type) SetSR_DMAS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *HASH_Type) GetSR_DMAS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *HASH_Type) SetSR_DCIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *HASH_Type) GetSR_DCIS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *HASH_Type) SetSR_DINIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *HASH_Type) GetSR_DINIS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// HASH.CSR0: context swap registers
func (o *HASH_Type) SetCSR0(value uint32) {
	volatile.StoreUint32(&o.CSR0.Reg, value)
}
func (o *HASH_Type) GetCSR0() uint32 {
	return volatile.LoadUint32(&o.CSR0.Reg)
}

// HASH.CSR1: context swap registers
func (o *HASH_Type) SetCSR1(value uint32) {
	volatile.StoreUint32(&o.CSR1.Reg, value)
}
func (o *HASH_Type) GetCSR1() uint32 {
	return volatile.LoadUint32(&o.CSR1.Reg)
}

// HASH.CSR2: context swap registers
func (o *HASH_Type) SetCSR2(value uint32) {
	volatile.StoreUint32(&o.CSR2.Reg, value)
}
func (o *HASH_Type) GetCSR2() uint32 {
	return volatile.LoadUint32(&o.CSR2.Reg)
}

// HASH.CSR3: context swap registers
func (o *HASH_Type) SetCSR3(value uint32) {
	volatile.StoreUint32(&o.CSR3.Reg, value)
}
func (o *HASH_Type) GetCSR3() uint32 {
	return volatile.LoadUint32(&o.CSR3.Reg)
}

// HASH.CSR4: context swap registers
func (o *HASH_Type) SetCSR4(value uint32) {
	volatile.StoreUint32(&o.CSR4.Reg, value)
}
func (o *HASH_Type) GetCSR4() uint32 {
	return volatile.LoadUint32(&o.CSR4.Reg)
}

// HASH.CSR5: context swap registers
func (o *HASH_Type) SetCSR5(value uint32) {
	volatile.StoreUint32(&o.CSR5.Reg, value)
}
func (o *HASH_Type) GetCSR5() uint32 {
	return volatile.LoadUint32(&o.CSR5.Reg)
}

// HASH.CSR6: context swap registers
func (o *HASH_Type) SetCSR6(value uint32) {
	volatile.StoreUint32(&o.CSR6.Reg, value)
}
func (o *HASH_Type) GetCSR6() uint32 {
	return volatile.LoadUint32(&o.CSR6.Reg)
}

// HASH.CSR7: context swap registers
func (o *HASH_Type) SetCSR7(value uint32) {
	volatile.StoreUint32(&o.CSR7.Reg, value)
}
func (o *HASH_Type) GetCSR7() uint32 {
	return volatile.LoadUint32(&o.CSR7.Reg)
}

// HASH.CSR8: context swap registers
func (o *HASH_Type) SetCSR8(value uint32) {
	volatile.StoreUint32(&o.CSR8.Reg, value)
}
func (o *HASH_Type) GetCSR8() uint32 {
	return volatile.LoadUint32(&o.CSR8.Reg)
}

// HASH.CSR9: context swap registers
func (o *HASH_Type) SetCSR9(value uint32) {
	volatile.StoreUint32(&o.CSR9.Reg, value)
}
func (o *HASH_Type) GetCSR9() uint32 {
	return volatile.LoadUint32(&o.CSR9.Reg)
}

// HASH.CSR10: context swap registers
func (o *HASH_Type) SetCSR10(value uint32) {
	volatile.StoreUint32(&o.CSR10.Reg, value)
}
func (o *HASH_Type) GetCSR10() uint32 {
	return volatile.LoadUint32(&o.CSR10.Reg)
}

// HASH.CSR11: context swap registers
func (o *HASH_Type) SetCSR11(value uint32) {
	volatile.StoreUint32(&o.CSR11.Reg, value)
}
func (o *HASH_Type) GetCSR11() uint32 {
	return volatile.LoadUint32(&o.CSR11.Reg)
}

// HASH.CSR12: context swap registers
func (o *HASH_Type) SetCSR12(value uint32) {
	volatile.StoreUint32(&o.CSR12.Reg, value)
}
func (o *HASH_Type) GetCSR12() uint32 {
	return volatile.LoadUint32(&o.CSR12.Reg)
}

// HASH.CSR13: context swap registers
func (o *HASH_Type) SetCSR13(value uint32) {
	volatile.StoreUint32(&o.CSR13.Reg, value)
}
func (o *HASH_Type) GetCSR13() uint32 {
	return volatile.LoadUint32(&o.CSR13.Reg)
}

// HASH.CSR14: context swap registers
func (o *HASH_Type) SetCSR14(value uint32) {
	volatile.StoreUint32(&o.CSR14.Reg, value)
}
func (o *HASH_Type) GetCSR14() uint32 {
	return volatile.LoadUint32(&o.CSR14.Reg)
}

// HASH.CSR15: context swap registers
func (o *HASH_Type) SetCSR15(value uint32) {
	volatile.StoreUint32(&o.CSR15.Reg, value)
}
func (o *HASH_Type) GetCSR15() uint32 {
	return volatile.LoadUint32(&o.CSR15.Reg)
}

// HASH.CSR16: context swap registers
func (o *HASH_Type) SetCSR16(value uint32) {
	volatile.StoreUint32(&o.CSR16.Reg, value)
}
func (o *HASH_Type) GetCSR16() uint32 {
	return volatile.LoadUint32(&o.CSR16.Reg)
}

// HASH.CSR17: context swap registers
func (o *HASH_Type) SetCSR17(value uint32) {
	volatile.StoreUint32(&o.CSR17.Reg, value)
}
func (o *HASH_Type) GetCSR17() uint32 {
	return volatile.LoadUint32(&o.CSR17.Reg)
}

// HASH.CSR18: context swap registers
func (o *HASH_Type) SetCSR18(value uint32) {
	volatile.StoreUint32(&o.CSR18.Reg, value)
}
func (o *HASH_Type) GetCSR18() uint32 {
	return volatile.LoadUint32(&o.CSR18.Reg)
}

// HASH.CSR19: context swap registers
func (o *HASH_Type) SetCSR19(value uint32) {
	volatile.StoreUint32(&o.CSR19.Reg, value)
}
func (o *HASH_Type) GetCSR19() uint32 {
	return volatile.LoadUint32(&o.CSR19.Reg)
}

// HASH.CSR20: context swap registers
func (o *HASH_Type) SetCSR20(value uint32) {
	volatile.StoreUint32(&o.CSR20.Reg, value)
}
func (o *HASH_Type) GetCSR20() uint32 {
	return volatile.LoadUint32(&o.CSR20.Reg)
}

// HASH.CSR21: context swap registers
func (o *HASH_Type) SetCSR21(value uint32) {
	volatile.StoreUint32(&o.CSR21.Reg, value)
}
func (o *HASH_Type) GetCSR21() uint32 {
	return volatile.LoadUint32(&o.CSR21.Reg)
}

// HASH.CSR22: context swap registers
func (o *HASH_Type) SetCSR22(value uint32) {
	volatile.StoreUint32(&o.CSR22.Reg, value)
}
func (o *HASH_Type) GetCSR22() uint32 {
	return volatile.LoadUint32(&o.CSR22.Reg)
}

// HASH.CSR23: context swap registers
func (o *HASH_Type) SetCSR23(value uint32) {
	volatile.StoreUint32(&o.CSR23.Reg, value)
}
func (o *HASH_Type) GetCSR23() uint32 {
	return volatile.LoadUint32(&o.CSR23.Reg)
}

// HASH.CSR24: context swap registers
func (o *HASH_Type) SetCSR24(value uint32) {
	volatile.StoreUint32(&o.CSR24.Reg, value)
}
func (o *HASH_Type) GetCSR24() uint32 {
	return volatile.LoadUint32(&o.CSR24.Reg)
}

// HASH.CSR25: context swap registers
func (o *HASH_Type) SetCSR25(value uint32) {
	volatile.StoreUint32(&o.CSR25.Reg, value)
}
func (o *HASH_Type) GetCSR25() uint32 {
	return volatile.LoadUint32(&o.CSR25.Reg)
}

// HASH.CSR26: context swap registers
func (o *HASH_Type) SetCSR26(value uint32) {
	volatile.StoreUint32(&o.CSR26.Reg, value)
}
func (o *HASH_Type) GetCSR26() uint32 {
	return volatile.LoadUint32(&o.CSR26.Reg)
}

// HASH.CSR27: context swap registers
func (o *HASH_Type) SetCSR27(value uint32) {
	volatile.StoreUint32(&o.CSR27.Reg, value)
}
func (o *HASH_Type) GetCSR27() uint32 {
	return volatile.LoadUint32(&o.CSR27.Reg)
}

// HASH.CSR28: context swap registers
func (o *HASH_Type) SetCSR28(value uint32) {
	volatile.StoreUint32(&o.CSR28.Reg, value)
}
func (o *HASH_Type) GetCSR28() uint32 {
	return volatile.LoadUint32(&o.CSR28.Reg)
}

// HASH.CSR29: context swap registers
func (o *HASH_Type) SetCSR29(value uint32) {
	volatile.StoreUint32(&o.CSR29.Reg, value)
}
func (o *HASH_Type) GetCSR29() uint32 {
	return volatile.LoadUint32(&o.CSR29.Reg)
}

// HASH.CSR30: context swap registers
func (o *HASH_Type) SetCSR30(value uint32) {
	volatile.StoreUint32(&o.CSR30.Reg, value)
}
func (o *HASH_Type) GetCSR30() uint32 {
	return volatile.LoadUint32(&o.CSR30.Reg)
}

// HASH.CSR31: context swap registers
func (o *HASH_Type) SetCSR31(value uint32) {
	volatile.StoreUint32(&o.CSR31.Reg, value)
}
func (o *HASH_Type) GetCSR31() uint32 {
	return volatile.LoadUint32(&o.CSR31.Reg)
}

// HASH.CSR32: context swap registers
func (o *HASH_Type) SetCSR32(value uint32) {
	volatile.StoreUint32(&o.CSR32.Reg, value)
}
func (o *HASH_Type) GetCSR32() uint32 {
	return volatile.LoadUint32(&o.CSR32.Reg)
}

// HASH.CSR33: context swap registers
func (o *HASH_Type) SetCSR33(value uint32) {
	volatile.StoreUint32(&o.CSR33.Reg, value)
}
func (o *HASH_Type) GetCSR33() uint32 {
	return volatile.LoadUint32(&o.CSR33.Reg)
}

// HASH.CSR34: context swap registers
func (o *HASH_Type) SetCSR34(value uint32) {
	volatile.StoreUint32(&o.CSR34.Reg, value)
}
func (o *HASH_Type) GetCSR34() uint32 {
	return volatile.LoadUint32(&o.CSR34.Reg)
}

// HASH.CSR35: context swap registers
func (o *HASH_Type) SetCSR35(value uint32) {
	volatile.StoreUint32(&o.CSR35.Reg, value)
}
func (o *HASH_Type) GetCSR35() uint32 {
	return volatile.LoadUint32(&o.CSR35.Reg)
}

// HASH.CSR36: context swap registers
func (o *HASH_Type) SetCSR36(value uint32) {
	volatile.StoreUint32(&o.CSR36.Reg, value)
}
func (o *HASH_Type) GetCSR36() uint32 {
	return volatile.LoadUint32(&o.CSR36.Reg)
}

// HASH.CSR37: context swap registers
func (o *HASH_Type) SetCSR37(value uint32) {
	volatile.StoreUint32(&o.CSR37.Reg, value)
}
func (o *HASH_Type) GetCSR37() uint32 {
	return volatile.LoadUint32(&o.CSR37.Reg)
}

// HASH.CSR38: context swap registers
func (o *HASH_Type) SetCSR38(value uint32) {
	volatile.StoreUint32(&o.CSR38.Reg, value)
}
func (o *HASH_Type) GetCSR38() uint32 {
	return volatile.LoadUint32(&o.CSR38.Reg)
}

// HASH.CSR39: context swap registers
func (o *HASH_Type) SetCSR39(value uint32) {
	volatile.StoreUint32(&o.CSR39.Reg, value)
}
func (o *HASH_Type) GetCSR39() uint32 {
	return volatile.LoadUint32(&o.CSR39.Reg)
}

// HASH.CSR40: context swap registers
func (o *HASH_Type) SetCSR40(value uint32) {
	volatile.StoreUint32(&o.CSR40.Reg, value)
}
func (o *HASH_Type) GetCSR40() uint32 {
	return volatile.LoadUint32(&o.CSR40.Reg)
}

// HASH.CSR41: context swap registers
func (o *HASH_Type) SetCSR41(value uint32) {
	volatile.StoreUint32(&o.CSR41.Reg, value)
}
func (o *HASH_Type) GetCSR41() uint32 {
	return volatile.LoadUint32(&o.CSR41.Reg)
}

// HASH.CSR42: context swap registers
func (o *HASH_Type) SetCSR42(value uint32) {
	volatile.StoreUint32(&o.CSR42.Reg, value)
}
func (o *HASH_Type) GetCSR42() uint32 {
	return volatile.LoadUint32(&o.CSR42.Reg)
}

// HASH.CSR43: context swap registers
func (o *HASH_Type) SetCSR43(value uint32) {
	volatile.StoreUint32(&o.CSR43.Reg, value)
}
func (o *HASH_Type) GetCSR43() uint32 {
	return volatile.LoadUint32(&o.CSR43.Reg)
}

// HASH.CSR44: context swap registers
func (o *HASH_Type) SetCSR44(value uint32) {
	volatile.StoreUint32(&o.CSR44.Reg, value)
}
func (o *HASH_Type) GetCSR44() uint32 {
	return volatile.LoadUint32(&o.CSR44.Reg)
}

// HASH.CSR45: context swap registers
func (o *HASH_Type) SetCSR45(value uint32) {
	volatile.StoreUint32(&o.CSR45.Reg, value)
}
func (o *HASH_Type) GetCSR45() uint32 {
	return volatile.LoadUint32(&o.CSR45.Reg)
}

// HASH.CSR46: context swap registers
func (o *HASH_Type) SetCSR46(value uint32) {
	volatile.StoreUint32(&o.CSR46.Reg, value)
}
func (o *HASH_Type) GetCSR46() uint32 {
	return volatile.LoadUint32(&o.CSR46.Reg)
}

// HASH.CSR47: context swap registers
func (o *HASH_Type) SetCSR47(value uint32) {
	volatile.StoreUint32(&o.CSR47.Reg, value)
}
func (o *HASH_Type) GetCSR47() uint32 {
	return volatile.LoadUint32(&o.CSR47.Reg)
}

// HASH.CSR48: context swap registers
func (o *HASH_Type) SetCSR48(value uint32) {
	volatile.StoreUint32(&o.CSR48.Reg, value)
}
func (o *HASH_Type) GetCSR48() uint32 {
	return volatile.LoadUint32(&o.CSR48.Reg)
}

// HASH.CSR49: context swap registers
func (o *HASH_Type) SetCSR49(value uint32) {
	volatile.StoreUint32(&o.CSR49.Reg, value)
}
func (o *HASH_Type) GetCSR49() uint32 {
	return volatile.LoadUint32(&o.CSR49.Reg)
}

// HASH.CSR50: context swap registers
func (o *HASH_Type) SetCSR50(value uint32) {
	volatile.StoreUint32(&o.CSR50.Reg, value)
}
func (o *HASH_Type) GetCSR50() uint32 {
	return volatile.LoadUint32(&o.CSR50.Reg)
}

// HASH.CSR51: context swap registers
func (o *HASH_Type) SetCSR51(value uint32) {
	volatile.StoreUint32(&o.CSR51.Reg, value)
}
func (o *HASH_Type) GetCSR51() uint32 {
	return volatile.LoadUint32(&o.CSR51.Reg)
}

// HASH.CSR52: context swap registers
func (o *HASH_Type) SetCSR52(value uint32) {
	volatile.StoreUint32(&o.CSR52.Reg, value)
}
func (o *HASH_Type) GetCSR52() uint32 {
	return volatile.LoadUint32(&o.CSR52.Reg)
}

// HASH.CSR53: context swap registers
func (o *HASH_Type) SetCSR53(value uint32) {
	volatile.StoreUint32(&o.CSR53.Reg, value)
}
func (o *HASH_Type) GetCSR53() uint32 {
	return volatile.LoadUint32(&o.CSR53.Reg)
}

// HASH.HR0: digest register 0
func (o *HASH_Type) SetHR0(value uint32) {
	volatile.StoreUint32(&o.HR0.Reg, value)
}
func (o *HASH_Type) GetHR0() uint32 {
	return volatile.LoadUint32(&o.HR0.Reg)
}

// HASH.HR1: digest register 1
func (o *HASH_Type) SetHR1(value uint32) {
	volatile.StoreUint32(&o.HR1.Reg, value)
}
func (o *HASH_Type) GetHR1() uint32 {
	return volatile.LoadUint32(&o.HR1.Reg)
}

// HASH.HR2: digest register 4
func (o *HASH_Type) SetHR2(value uint32) {
	volatile.StoreUint32(&o.HR2.Reg, value)
}
func (o *HASH_Type) GetHR2() uint32 {
	return volatile.LoadUint32(&o.HR2.Reg)
}

// HASH.HR3: digest register 3
func (o *HASH_Type) SetHR3(value uint32) {
	volatile.StoreUint32(&o.HR3.Reg, value)
}
func (o *HASH_Type) GetHR3() uint32 {
	return volatile.LoadUint32(&o.HR3.Reg)
}

// HASH.HR4: digest register 4
func (o *HASH_Type) SetHR4(value uint32) {
	volatile.StoreUint32(&o.HR4.Reg, value)
}
func (o *HASH_Type) GetHR4() uint32 {
	return volatile.LoadUint32(&o.HR4.Reg)
}

// HASH.HR5: supplementary digest register 5
func (o *HASH_Type) SetHR5(value uint32) {
	volatile.StoreUint32(&o.HR5.Reg, value)
}
func (o *HASH_Type) GetHR5() uint32 {
	return volatile.LoadUint32(&o.HR5.Reg)
}

// HASH.HR6: supplementary digest register 6
func (o *HASH_Type) SetHR6(value uint32) {
	volatile.StoreUint32(&o.HR6.Reg, value)
}
func (o *HASH_Type) GetHR6() uint32 {
	return volatile.LoadUint32(&o.HR6.Reg)
}

// HASH.HR7: supplementary digest register 7
func (o *HASH_Type) SetHR7(value uint32) {
	volatile.StoreUint32(&o.HR7.Reg, value)
}
func (o *HASH_Type) GetHR7() uint32 {
	return volatile.LoadUint32(&o.HR7.Reg)
}

// Inter-integrated circuit
type I2C_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	OAR1     volatile.Register32 // 0x8
	OAR2     volatile.Register32 // 0xC
	TIMINGR  volatile.Register32 // 0x10
	TIMEOUTR volatile.Register32 // 0x14
	ISR      volatile.Register32 // 0x18
	ICR      volatile.Register32 // 0x1C
	PECR     volatile.Register32 // 0x20
	RXDR     volatile.Register32 // 0x24
	TXDR     volatile.Register32 // 0x28
}

// I2C.CR1: Control register 1
func (o *I2C_Type) SetCR1_PE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetCR1_PE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *I2C_Type) SetCR1_TXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetCR1_TXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetCR1_RXIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetCR1_RXIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetCR1_ADDRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetCR1_ADDRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetCR1_NACKIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetCR1_NACKIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetCR1_STOPIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetCR1_STOPIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetCR1_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetCR1_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetCR1_DNF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xf00)|value<<8)
}
func (o *I2C_Type) GetCR1_DNF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xf00) >> 8
}
func (o *I2C_Type) SetCR1_ANFOFF(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR1_ANFOFF() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR1_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR1_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR1_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR1_RXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR1_SBC(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetCR1_SBC() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetCR1_NOSTRETCH(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *I2C_Type) GetCR1_NOSTRETCH() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *I2C_Type) SetCR1_WUPEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *I2C_Type) GetCR1_WUPEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *I2C_Type) SetCR1_GCEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000)|value<<19)
}
func (o *I2C_Type) GetCR1_GCEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000) >> 19
}
func (o *I2C_Type) SetCR1_SMBHEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100000)|value<<20)
}
func (o *I2C_Type) GetCR1_SMBHEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100000) >> 20
}
func (o *I2C_Type) SetCR1_SMBDEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200000)|value<<21)
}
func (o *I2C_Type) GetCR1_SMBDEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200000) >> 21
}
func (o *I2C_Type) SetCR1_ALERTEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400000)|value<<22)
}
func (o *I2C_Type) GetCR1_ALERTEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400000) >> 22
}
func (o *I2C_Type) SetCR1_PECEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800000)|value<<23)
}
func (o *I2C_Type) GetCR1_PECEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800000) >> 23
}

// I2C.CR2: Control register 2
func (o *I2C_Type) SetCR2_PECBYTE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000000)|value<<26)
}
func (o *I2C_Type) GetCR2_PECBYTE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000000) >> 26
}
func (o *I2C_Type) SetCR2_AUTOEND(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *I2C_Type) GetCR2_AUTOEND() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *I2C_Type) SetCR2_RELOAD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000000)|value<<24)
}
func (o *I2C_Type) GetCR2_RELOAD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000000) >> 24
}
func (o *I2C_Type) SetCR2_NBYTES(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff0000)|value<<16)
}
func (o *I2C_Type) GetCR2_NBYTES() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff0000) >> 16
}
func (o *I2C_Type) SetCR2_NACK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetCR2_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *I2C_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *I2C_Type) SetCR2_START(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetCR2_START() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetCR2_HEAD10R(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetCR2_HEAD10R() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetCR2_ADD10(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetCR2_ADD10() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetCR2_RD_WRN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetCR2_RD_WRN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetCR2_SADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetCR2_SADD() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x3ff
}

// I2C.OAR1: Own address register 1
func (o *I2C_Type) SetOAR1_OA1(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x3ff)|value)
}
func (o *I2C_Type) GetOAR1_OA1() uint32 {
	return volatile.LoadUint32(&o.OAR1.Reg) & 0x3ff
}
func (o *I2C_Type) SetOAR1_OA1MODE(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetOAR1_OA1MODE() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetOAR1_OA1EN(value uint32) {
	volatile.StoreUint32(&o.OAR1.Reg, volatile.LoadUint32(&o.OAR1.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR1_OA1EN() uint32 {
	return (volatile.LoadUint32(&o.OAR1.Reg) & 0x8000) >> 15
}

// I2C.OAR2: Own address register 2
func (o *I2C_Type) SetOAR2_OA2(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0xfe)|value<<1)
}
func (o *I2C_Type) GetOAR2_OA2() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0xfe) >> 1
}
func (o *I2C_Type) SetOAR2_OA2MSK(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x700)|value<<8)
}
func (o *I2C_Type) GetOAR2_OA2MSK() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x700) >> 8
}
func (o *I2C_Type) SetOAR2_OA2EN(value uint32) {
	volatile.StoreUint32(&o.OAR2.Reg, volatile.LoadUint32(&o.OAR2.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetOAR2_OA2EN() uint32 {
	return (volatile.LoadUint32(&o.OAR2.Reg) & 0x8000) >> 15
}

// I2C.TIMINGR: Timing register
func (o *I2C_Type) SetTIMINGR_SCLL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTIMINGR_SCLL() uint32 {
	return volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff
}
func (o *I2C_Type) SetTIMINGR_SCLH(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xff00)|value<<8)
}
func (o *I2C_Type) GetTIMINGR_SCLH() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xff00) >> 8
}
func (o *I2C_Type) SetTIMINGR_SDADEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000)|value<<16)
}
func (o *I2C_Type) GetTIMINGR_SDADEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000) >> 16
}
func (o *I2C_Type) SetTIMINGR_SCLDEL(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf00000)|value<<20)
}
func (o *I2C_Type) GetTIMINGR_SCLDEL() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf00000) >> 20
}
func (o *I2C_Type) SetTIMINGR_PRESC(value uint32) {
	volatile.StoreUint32(&o.TIMINGR.Reg, volatile.LoadUint32(&o.TIMINGR.Reg)&^(0xf0000000)|value<<28)
}
func (o *I2C_Type) GetTIMINGR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.TIMINGR.Reg) & 0xf0000000) >> 28
}

// I2C.TIMEOUTR: Status register 1
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTA(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff)|value)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTA() uint32 {
	return volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff
}
func (o *I2C_Type) SetTIMEOUTR_TIDLE(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetTIMEOUTR_TIDLE() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetTIMEOUTR_TIMOUTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetTIMEOUTR_TIMOUTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetTIMEOUTR_TIMEOUTB(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0xfff0000)|value<<16)
}
func (o *I2C_Type) GetTIMEOUTR_TIMEOUTB() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0xfff0000) >> 16
}
func (o *I2C_Type) SetTIMEOUTR_TEXTEN(value uint32) {
	volatile.StoreUint32(&o.TIMEOUTR.Reg, volatile.LoadUint32(&o.TIMEOUTR.Reg)&^(0x80000000)|value<<31)
}
func (o *I2C_Type) GetTIMEOUTR_TEXTEN() uint32 {
	return (volatile.LoadUint32(&o.TIMEOUTR.Reg) & 0x80000000) >> 31
}

// I2C.ISR: Interrupt and Status register
func (o *I2C_Type) SetISR_ADDCODE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0xfe0000)|value<<17)
}
func (o *I2C_Type) GetISR_ADDCODE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0xfe0000) >> 17
}
func (o *I2C_Type) SetISR_DIR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *I2C_Type) GetISR_DIR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *I2C_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *I2C_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *I2C_Type) SetISR_ALERT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetISR_ALERT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetISR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetISR_TIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetISR_PECERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetISR_PECERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetISR_OVR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetISR_OVR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetISR_ARLO(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetISR_ARLO() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetISR_BERR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetISR_BERR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetISR_TCR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *I2C_Type) GetISR_TCR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *I2C_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *I2C_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *I2C_Type) SetISR_STOPF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetISR_STOPF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetISR_NACKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetISR_NACKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetISR_ADDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetISR_ADDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *I2C_Type) SetISR_RXNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *I2C_Type) GetISR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *I2C_Type) SetISR_TXIS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *I2C_Type) GetISR_TXIS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *I2C_Type) SetISR_TXE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *I2C_Type) GetISR_TXE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// I2C.ICR: Interrupt clear register
func (o *I2C_Type) SetICR_ALERTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *I2C_Type) GetICR_ALERTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}
func (o *I2C_Type) SetICR_TIMOUTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *I2C_Type) GetICR_TIMOUTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *I2C_Type) SetICR_PECCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *I2C_Type) GetICR_PECCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *I2C_Type) SetICR_OVRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *I2C_Type) GetICR_OVRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *I2C_Type) SetICR_ARLOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *I2C_Type) GetICR_ARLOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *I2C_Type) SetICR_BERRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *I2C_Type) GetICR_BERRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *I2C_Type) SetICR_STOPCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *I2C_Type) GetICR_STOPCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *I2C_Type) SetICR_NACKCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *I2C_Type) GetICR_NACKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *I2C_Type) SetICR_ADDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *I2C_Type) GetICR_ADDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}

// I2C.PECR: PEC register
func (o *I2C_Type) SetPECR_PEC(value uint32) {
	volatile.StoreUint32(&o.PECR.Reg, volatile.LoadUint32(&o.PECR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetPECR_PEC() uint32 {
	return volatile.LoadUint32(&o.PECR.Reg) & 0xff
}

// I2C.RXDR: Receive data register
func (o *I2C_Type) SetRXDR_RXDATA(value uint32) {
	volatile.StoreUint32(&o.RXDR.Reg, volatile.LoadUint32(&o.RXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetRXDR_RXDATA() uint32 {
	return volatile.LoadUint32(&o.RXDR.Reg) & 0xff
}

// I2C.TXDR: Transmit data register
func (o *I2C_Type) SetTXDR_TXDATA(value uint32) {
	volatile.StoreUint32(&o.TXDR.Reg, volatile.LoadUint32(&o.TXDR.Reg)&^(0xff)|value)
}
func (o *I2C_Type) GetTXDR_TXDATA() uint32 {
	return volatile.LoadUint32(&o.TXDR.Reg) & 0xff
}

// ICache
type ICache_Type struct {
	CR    volatile.Register32 // 0x0
	SR    volatile.Register32 // 0x4
	IER   volatile.Register32 // 0x8
	FCR   volatile.Register32 // 0xC
	HMONR volatile.Register32 // 0x10
	MMONR volatile.Register32 // 0x14
	_     [8]byte
	CRR0  volatile.Register32 // 0x20
	CRR1  volatile.Register32 // 0x24
	CRR2  volatile.Register32 // 0x28
	CRR3  volatile.Register32 // 0x2C
}

// ICache.CR: ICACHE control register
func (o *ICache_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *ICache_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *ICache_Type) SetCR_CACHEINV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetCR_CACHEINV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetCR_WAYSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetCR_WAYSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *ICache_Type) SetCR_HITMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *ICache_Type) GetCR_HITMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *ICache_Type) SetCR_MISSMEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *ICache_Type) GetCR_MISSMEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *ICache_Type) SetCR_HITMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *ICache_Type) GetCR_HITMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *ICache_Type) SetCR_MISSMRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *ICache_Type) GetCR_MISSMRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}

// ICache.SR: ICACHE status register
func (o *ICache_Type) SetSR_BUSYF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *ICache_Type) GetSR_BUSYF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *ICache_Type) SetSR_BSYENDF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetSR_BSYENDF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetSR_ERRF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetSR_ERRF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}

// ICache.IER: ICACHE interrupt enable register
func (o *ICache_Type) SetIER_BSYENDIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetIER_BSYENDIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetIER_ERRIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetIER_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}

// ICache.FCR: ICACHE flag clear register
func (o *ICache_Type) SetFCR_CBSYENDF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x2)|value<<1)
}
func (o *ICache_Type) GetFCR_CBSYENDF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x2) >> 1
}
func (o *ICache_Type) SetFCR_CERRF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x4)|value<<2)
}
func (o *ICache_Type) GetFCR_CERRF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x4) >> 2
}

// ICache.HMONR: ICACHE hit monitor register
func (o *ICache_Type) SetHMONR(value uint32) {
	volatile.StoreUint32(&o.HMONR.Reg, value)
}
func (o *ICache_Type) GetHMONR() uint32 {
	return volatile.LoadUint32(&o.HMONR.Reg)
}

// ICache.MMONR: ICACHE miss monitor register
func (o *ICache_Type) SetMMONR_MISSMON(value uint32) {
	volatile.StoreUint32(&o.MMONR.Reg, volatile.LoadUint32(&o.MMONR.Reg)&^(0xffff)|value)
}
func (o *ICache_Type) GetMMONR_MISSMON() uint32 {
	return volatile.LoadUint32(&o.MMONR.Reg) & 0xffff
}

// ICache.CRR0: ICACHE region configuration register
func (o *ICache_Type) SetCRR0_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR0_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR0.Reg) & 0xff
}
func (o *ICache_Type) SetCRR0_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR0_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR0_REN(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR0_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR0_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR0_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR0_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR0_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR0_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR0.Reg, volatile.LoadUint32(&o.CRR0.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR0_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR0.Reg) & 0x80000000) >> 31
}

// ICache.CRR1: ICACHE region configuration register
func (o *ICache_Type) SetCRR1_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR1_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR1.Reg) & 0xff
}
func (o *ICache_Type) SetCRR1_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR1_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR1_REN(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR1_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR1_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR1_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR1_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR1_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR1_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR1.Reg, volatile.LoadUint32(&o.CRR1.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR1_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR1.Reg) & 0x80000000) >> 31
}

// ICache.CRR2: ICACHE region configuration register
func (o *ICache_Type) SetCRR2_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR2_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR2.Reg) & 0xff
}
func (o *ICache_Type) SetCRR2_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR2_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR2_REN(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR2_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR2_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR2_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR2_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR2_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR2_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR2.Reg, volatile.LoadUint32(&o.CRR2.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR2_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR2.Reg) & 0x80000000) >> 31
}

// ICache.CRR3: ICACHE region configuration register
func (o *ICache_Type) SetCRR3_BASEADDR(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0xff)|value)
}
func (o *ICache_Type) GetCRR3_BASEADDR() uint32 {
	return volatile.LoadUint32(&o.CRR3.Reg) & 0xff
}
func (o *ICache_Type) SetCRR3_RSIZE(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0xe00)|value<<9)
}
func (o *ICache_Type) GetCRR3_RSIZE() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0xe00) >> 9
}
func (o *ICache_Type) SetCRR3_REN(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x8000)|value<<15)
}
func (o *ICache_Type) GetCRR3_REN() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x8000) >> 15
}
func (o *ICache_Type) SetCRR3_REMAPADDR(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x7ff0000)|value<<16)
}
func (o *ICache_Type) GetCRR3_REMAPADDR() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x7ff0000) >> 16
}
func (o *ICache_Type) SetCRR3_MSTSEL(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x10000000)|value<<28)
}
func (o *ICache_Type) GetCRR3_MSTSEL() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x10000000) >> 28
}
func (o *ICache_Type) SetCRR3_HBURST(value uint32) {
	volatile.StoreUint32(&o.CRR3.Reg, volatile.LoadUint32(&o.CRR3.Reg)&^(0x80000000)|value<<31)
}
func (o *ICache_Type) GetCRR3_HBURST() uint32 {
	return (volatile.LoadUint32(&o.CRR3.Reg) & 0x80000000) >> 31
}

// Independent watchdog
type IWDG_Type struct {
	KR   volatile.Register32 // 0x0
	PR   volatile.Register32 // 0x4
	RLR  volatile.Register32 // 0x8
	SR   volatile.Register32 // 0xC
	WINR volatile.Register32 // 0x10
}

// IWDG.KR: Key register
func (o *IWDG_Type) SetKR_KEY(value uint32) {
	volatile.StoreUint32(&o.KR.Reg, volatile.LoadUint32(&o.KR.Reg)&^(0xffff)|value)
}
func (o *IWDG_Type) GetKR_KEY() uint32 {
	return volatile.LoadUint32(&o.KR.Reg) & 0xffff
}

// IWDG.PR: Prescaler register
func (o *IWDG_Type) SetPR(value uint32) {
	volatile.StoreUint32(&o.PR.Reg, volatile.LoadUint32(&o.PR.Reg)&^(0x7)|value)
}
func (o *IWDG_Type) GetPR() uint32 {
	return volatile.LoadUint32(&o.PR.Reg) & 0x7
}

// IWDG.RLR: Reload register
func (o *IWDG_Type) SetRLR_RL(value uint32) {
	volatile.StoreUint32(&o.RLR.Reg, volatile.LoadUint32(&o.RLR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetRLR_RL() uint32 {
	return volatile.LoadUint32(&o.RLR.Reg) & 0xfff
}

// IWDG.SR: Status register
func (o *IWDG_Type) SetSR_WVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *IWDG_Type) GetSR_WVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *IWDG_Type) SetSR_RVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *IWDG_Type) GetSR_RVU() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *IWDG_Type) SetSR_PVU(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *IWDG_Type) GetSR_PVU() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// IWDG.WINR: Window register
func (o *IWDG_Type) SetWINR_WIN(value uint32) {
	volatile.StoreUint32(&o.WINR.Reg, volatile.LoadUint32(&o.WINR.Reg)&^(0xfff)|value)
}
func (o *IWDG_Type) GetWINR_WIN() uint32 {
	return volatile.LoadUint32(&o.WINR.Reg) & 0xfff
}

// Low power timer
type LPTIM_Type struct {
	ISR  volatile.Register32 // 0x0
	ICR  volatile.Register32 // 0x4
	IER  volatile.Register32 // 0x8
	CFGR volatile.Register32 // 0xC
	CR   volatile.Register32 // 0x10
	CMP  volatile.Register32 // 0x14
	ARR  volatile.Register32 // 0x18
	CNT  volatile.Register32 // 0x1C
	OR   volatile.Register32 // 0x20
	_    [4]byte
	RCR  volatile.Register32 // 0x28
}

// LPTIM.ISR: Interrupt and Status Register
func (o *LPTIM_Type) SetISR_DOWN(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *LPTIM_Type) GetISR_DOWN() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *LPTIM_Type) SetISR_UP(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *LPTIM_Type) GetISR_UP() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *LPTIM_Type) SetISR_ARROK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetISR_ARROK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetISR_CMPOK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetISR_CMPOK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *LPTIM_Type) SetISR_EXTTRIG(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetISR_EXTTRIG() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetISR_ARRM(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetISR_ARRM() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetISR_CMPM(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetISR_CMPM() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *LPTIM_Type) SetISR_UE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *LPTIM_Type) GetISR_UE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *LPTIM_Type) SetISR_REPOK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *LPTIM_Type) GetISR_REPOK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}

// LPTIM.ICR: Interrupt Clear Register
func (o *LPTIM_Type) SetICR_DOWNCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *LPTIM_Type) GetICR_DOWNCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *LPTIM_Type) SetICR_UPCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *LPTIM_Type) GetICR_UPCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *LPTIM_Type) SetICR_ARROKCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetICR_ARROKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetICR_CMPOKCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetICR_CMPOKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *LPTIM_Type) SetICR_EXTTRIGCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetICR_EXTTRIGCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetICR_ARRMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetICR_ARRMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetICR_CMPMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetICR_CMPMCF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *LPTIM_Type) SetICR_UECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x80)|value<<7)
}
func (o *LPTIM_Type) GetICR_UECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x80) >> 7
}
func (o *LPTIM_Type) SetICR_REPOKCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *LPTIM_Type) GetICR_REPOKCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}

// LPTIM.IER: Interrupt Enable Register
func (o *LPTIM_Type) SetIER_DOWNIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *LPTIM_Type) GetIER_DOWNIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *LPTIM_Type) SetIER_UPIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *LPTIM_Type) GetIER_UPIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *LPTIM_Type) SetIER_ARROKIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetIER_ARROKIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetIER_CMPOKIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetIER_CMPOKIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *LPTIM_Type) SetIER_EXTTRIGIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetIER_EXTTRIGIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetIER_ARRMIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetIER_ARRMIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetIER_CMPMIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetIER_CMPMIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *LPTIM_Type) SetIER_UEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *LPTIM_Type) GetIER_UEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *LPTIM_Type) SetIER_REPOKIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100)|value<<8)
}
func (o *LPTIM_Type) GetIER_REPOKIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100) >> 8
}

// LPTIM.CFGR: Configuration Register
func (o *LPTIM_Type) SetCFGR_ENC(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1000000)|value<<24)
}
func (o *LPTIM_Type) GetCFGR_ENC() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x1000000) >> 24
}
func (o *LPTIM_Type) SetCFGR_COUNTMODE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x800000)|value<<23)
}
func (o *LPTIM_Type) GetCFGR_COUNTMODE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x800000) >> 23
}
func (o *LPTIM_Type) SetCFGR_PRELOAD(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x400000)|value<<22)
}
func (o *LPTIM_Type) GetCFGR_PRELOAD() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x400000) >> 22
}
func (o *LPTIM_Type) SetCFGR_WAVPOL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x200000)|value<<21)
}
func (o *LPTIM_Type) GetCFGR_WAVPOL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x200000) >> 21
}
func (o *LPTIM_Type) SetCFGR_WAVE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x100000)|value<<20)
}
func (o *LPTIM_Type) GetCFGR_WAVE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x100000) >> 20
}
func (o *LPTIM_Type) SetCFGR_TIMOUT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x80000)|value<<19)
}
func (o *LPTIM_Type) GetCFGR_TIMOUT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x80000) >> 19
}
func (o *LPTIM_Type) SetCFGR_TRIGEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x60000)|value<<17)
}
func (o *LPTIM_Type) GetCFGR_TRIGEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x60000) >> 17
}
func (o *LPTIM_Type) SetCFGR_TRIGSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xe000)|value<<13)
}
func (o *LPTIM_Type) GetCFGR_TRIGSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xe000) >> 13
}
func (o *LPTIM_Type) SetCFGR_PRESC(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xe00)|value<<9)
}
func (o *LPTIM_Type) GetCFGR_PRESC() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xe00) >> 9
}
func (o *LPTIM_Type) SetCFGR_TRGFLT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xc0)|value<<6)
}
func (o *LPTIM_Type) GetCFGR_TRGFLT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xc0) >> 6
}
func (o *LPTIM_Type) SetCFGR_CKFLT(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x18)|value<<3)
}
func (o *LPTIM_Type) GetCFGR_CKFLT() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x18) >> 3
}
func (o *LPTIM_Type) SetCFGR_CKPOL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x6)|value<<1)
}
func (o *LPTIM_Type) GetCFGR_CKPOL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x6) >> 1
}
func (o *LPTIM_Type) SetCFGR_CKSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetCFGR_CKSEL() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0x1
}

// LPTIM.CR: Control Register
func (o *LPTIM_Type) SetCR_CNTSTRT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *LPTIM_Type) GetCR_CNTSTRT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *LPTIM_Type) SetCR_SNGSTRT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetCR_SNGSTRT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *LPTIM_Type) SetCR_ENABLE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetCR_ENABLE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}
func (o *LPTIM_Type) SetCR_COUNTRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *LPTIM_Type) GetCR_COUNTRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *LPTIM_Type) SetCR_RSTARE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *LPTIM_Type) GetCR_RSTARE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}

// LPTIM.CMP: Compare Register
func (o *LPTIM_Type) SetCMP(value uint32) {
	volatile.StoreUint32(&o.CMP.Reg, volatile.LoadUint32(&o.CMP.Reg)&^(0xffff)|value)
}
func (o *LPTIM_Type) GetCMP() uint32 {
	return volatile.LoadUint32(&o.CMP.Reg) & 0xffff
}

// LPTIM.ARR: Autoreload Register
func (o *LPTIM_Type) SetARR(value uint32) {
	volatile.StoreUint32(&o.ARR.Reg, volatile.LoadUint32(&o.ARR.Reg)&^(0xffff)|value)
}
func (o *LPTIM_Type) GetARR() uint32 {
	return volatile.LoadUint32(&o.ARR.Reg) & 0xffff
}

// LPTIM.CNT: Counter Register
func (o *LPTIM_Type) SetCNT(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0xffff)|value)
}
func (o *LPTIM_Type) GetCNT() uint32 {
	return volatile.LoadUint32(&o.CNT.Reg) & 0xffff
}

// LPTIM.OR: LPTIM option register
func (o *LPTIM_Type) SetOR_OR_0(value uint32) {
	volatile.StoreUint32(&o.OR.Reg, volatile.LoadUint32(&o.OR.Reg)&^(0x1)|value)
}
func (o *LPTIM_Type) GetOR_OR_0() uint32 {
	return volatile.LoadUint32(&o.OR.Reg) & 0x1
}
func (o *LPTIM_Type) SetOR_OR_1(value uint32) {
	volatile.StoreUint32(&o.OR.Reg, volatile.LoadUint32(&o.OR.Reg)&^(0x2)|value<<1)
}
func (o *LPTIM_Type) GetOR_OR_1() uint32 {
	return (volatile.LoadUint32(&o.OR.Reg) & 0x2) >> 1
}

// LPTIM.RCR: LPTIM repetition register
func (o *LPTIM_Type) SetRCR_REP(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xff)|value)
}
func (o *LPTIM_Type) GetRCR_REP() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xff
}

// Universal synchronous asynchronous receiver transmitter
type USART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// USART.CR1: Control register 1
func (o *USART_Type) SetCR1_M1(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR1_M1() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR1_EOBIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetCR1_EOBIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000000) >> 27
}
func (o *USART_Type) SetCR1_RTOIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetCR1_RTOIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetCR1_DEAT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x3e00000)|value<<21)
}
func (o *USART_Type) GetCR1_DEAT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x3e00000) >> 21
}
func (o *USART_Type) SetCR1_DEDT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *USART_Type) GetCR1_DEDT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1f0000) >> 16
}
func (o *USART_Type) SetCR1_OVER8(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR1_OVER8() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR1_CMIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR1_CMIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR1_MME(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR1_MME() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR1_M0(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR1_M0() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR1_WAKE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR1_WAKE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR1_PCE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR1_PCE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR1_PS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR1_PS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR1_PEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR1_PEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR1_TXEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR1_TXEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR1_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR1_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR1_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR1_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR1_IDLEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR1_IDLEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR1_TE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR1_TE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR1_RE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR1_RE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR1_UESM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCR1_UESM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCR1_UE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR1_UE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *USART_Type) SetCR1_FIFOEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000000)|value<<29)
}
func (o *USART_Type) GetCR1_FIFOEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000000) >> 29
}
func (o *USART_Type) SetCR1_TXFEIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000000)|value<<30)
}
func (o *USART_Type) GetCR1_TXFEIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000000) >> 30
}
func (o *USART_Type) SetCR1_RXFFIE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000000)|value<<31)
}
func (o *USART_Type) GetCR1_RXFFIE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000000) >> 31
}

// USART.CR2: Control register 2
func (o *USART_Type) SetCR2_ADD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetCR2_ADD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xff000000) >> 24
}
func (o *USART_Type) SetCR2_RTOEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR2_RTOEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR2_ABRMOD(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x600000)|value<<21)
}
func (o *USART_Type) GetCR2_ABRMOD() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x600000) >> 21
}
func (o *USART_Type) SetCR2_ABREN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetCR2_ABREN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetCR2_MSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetCR2_MSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetCR2_DATAINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetCR2_DATAINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetCR2_TXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetCR2_TXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetCR2_RXINV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetCR2_RXINV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetCR2_SWAP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR2_SWAP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR2_LINEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR2_LINEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR2_STOP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x3000)|value<<12)
}
func (o *USART_Type) GetCR2_STOP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x3000) >> 12
}
func (o *USART_Type) SetCR2_CLKEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR2_CLKEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR2_CPOL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR2_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR2_CPHA(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR2_CPHA() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR2_LBCL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR2_LBCL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR2_LBDIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR2_LBDIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR2_LBDL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR2_LBDL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR2_ADDM7(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR2_ADDM7() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR2_SLVEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR2_SLVEN() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *USART_Type) SetCR2_DIS_NSS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR2_DIS_NSS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}

// USART.CR3: Control register 3
func (o *USART_Type) SetCR3_WUFIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400000)|value<<22)
}
func (o *USART_Type) GetCR3_WUFIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400000) >> 22
}
func (o *USART_Type) SetCR3_WUS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x300000)|value<<20)
}
func (o *USART_Type) GetCR3_WUS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x300000) >> 20
}
func (o *USART_Type) SetCR3_SCARCNT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000)|value<<17)
}
func (o *USART_Type) GetCR3_SCARCNT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000) >> 17
}
func (o *USART_Type) SetCR3_DEP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetCR3_DEP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetCR3_DEM(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetCR3_DEM() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetCR3_DDRE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetCR3_DDRE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *USART_Type) SetCR3_OVRDIS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetCR3_OVRDIS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetCR3_ONEBIT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetCR3_ONEBIT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetCR3_CTSIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetCR3_CTSIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetCR3_CTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetCR3_CTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetCR3_RTSE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetCR3_RTSE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetCR3_DMAT(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetCR3_DMAT() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetCR3_DMAR(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetCR3_DMAR() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetCR3_SCEN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetCR3_SCEN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetCR3_NACK(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetCR3_NACK() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetCR3_HDSEL(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetCR3_HDSEL() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetCR3_IRLP(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetCR3_IRLP() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetCR3_IREN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetCR3_IREN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetCR3_EIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetCR3_EIE() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *USART_Type) SetCR3_TXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetCR3_TXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetCR3_TCBGTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetCR3_TCBGTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetCR3_RXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe000000)|value<<25)
}
func (o *USART_Type) GetCR3_RXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe000000) >> 25
}
func (o *USART_Type) SetCR3_RXFTIE(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10000000)|value<<28)
}
func (o *USART_Type) GetCR3_RXFTIE() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10000000) >> 28
}
func (o *USART_Type) SetCR3_TXFTCFG(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0xe0000000)|value<<29)
}
func (o *USART_Type) GetCR3_TXFTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0xe0000000) >> 29
}

// USART.BRR: Baud rate register
func (o *USART_Type) SetBRR(value uint32) {
	volatile.StoreUint32(&o.BRR.Reg, volatile.LoadUint32(&o.BRR.Reg)&^(0xffff)|value)
}
func (o *USART_Type) GetBRR() uint32 {
	return volatile.LoadUint32(&o.BRR.Reg) & 0xffff
}

// USART.GTPR: Guard time and prescaler register
func (o *USART_Type) SetGTPR_GT(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff00)|value<<8)
}
func (o *USART_Type) GetGTPR_GT() uint32 {
	return (volatile.LoadUint32(&o.GTPR.Reg) & 0xff00) >> 8
}
func (o *USART_Type) SetGTPR_PSC(value uint32) {
	volatile.StoreUint32(&o.GTPR.Reg, volatile.LoadUint32(&o.GTPR.Reg)&^(0xff)|value)
}
func (o *USART_Type) GetGTPR_PSC() uint32 {
	return volatile.LoadUint32(&o.GTPR.Reg) & 0xff
}

// USART.RTOR: Receiver timeout register
func (o *USART_Type) SetRTOR_BLEN(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xff000000)|value<<24)
}
func (o *USART_Type) GetRTOR_BLEN() uint32 {
	return (volatile.LoadUint32(&o.RTOR.Reg) & 0xff000000) >> 24
}
func (o *USART_Type) SetRTOR_RTO(value uint32) {
	volatile.StoreUint32(&o.RTOR.Reg, volatile.LoadUint32(&o.RTOR.Reg)&^(0xffffff)|value)
}
func (o *USART_Type) GetRTOR_RTO() uint32 {
	return volatile.LoadUint32(&o.RTOR.Reg) & 0xffffff
}

// USART.RQR: Request register
func (o *USART_Type) SetRQR_TXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetRQR_TXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetRQR_RXFRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetRQR_RXFRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetRQR_MMRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetRQR_MMRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetRQR_SBKRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetRQR_SBKRQ() uint32 {
	return (volatile.LoadUint32(&o.RQR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetRQR_ABRRQ(value uint32) {
	volatile.StoreUint32(&o.RQR.Reg, volatile.LoadUint32(&o.RQR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetRQR_ABRRQ() uint32 {
	return volatile.LoadUint32(&o.RQR.Reg) & 0x1
}

// USART.ISR: Interrupt & status register
func (o *USART_Type) SetISR_REACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400000)|value<<22)
}
func (o *USART_Type) GetISR_REACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400000) >> 22
}
func (o *USART_Type) SetISR_TEACK(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200000)|value<<21)
}
func (o *USART_Type) GetISR_TEACK() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200000) >> 21
}
func (o *USART_Type) SetISR_WUF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetISR_WUF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetISR_RWU(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80000)|value<<19)
}
func (o *USART_Type) GetISR_RWU() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80000) >> 19
}
func (o *USART_Type) SetISR_SBKF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40000)|value<<18)
}
func (o *USART_Type) GetISR_SBKF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40000) >> 18
}
func (o *USART_Type) SetISR_CMF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetISR_CMF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetISR_BUSY(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10000)|value<<16)
}
func (o *USART_Type) GetISR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10000) >> 16
}
func (o *USART_Type) SetISR_ABRF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000)|value<<15)
}
func (o *USART_Type) GetISR_ABRF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000) >> 15
}
func (o *USART_Type) SetISR_ABRE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000)|value<<14)
}
func (o *USART_Type) GetISR_ABRE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000) >> 14
}
func (o *USART_Type) SetISR_EOBF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetISR_EOBF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetISR_RTOF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetISR_RTOF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetISR_CTS(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x400)|value<<10)
}
func (o *USART_Type) GetISR_CTS() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x400) >> 10
}
func (o *USART_Type) SetISR_CTSIF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetISR_CTSIF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetISR_LBDF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetISR_LBDF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetISR_TXE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetISR_TXE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetISR_TC(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetISR_TC() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetISR_RXNE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetISR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetISR_IDLE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetISR_IDLE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetISR_ORE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetISR_ORE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetISR_NF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetISR_NF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetISR_FE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetISR_FE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetISR_PE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetISR_PE() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}
func (o *USART_Type) SetISR_TXFE(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x800000)|value<<23)
}
func (o *USART_Type) GetISR_TXFE() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x800000) >> 23
}
func (o *USART_Type) SetISR_RXFF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1000000)|value<<24)
}
func (o *USART_Type) GetISR_RXFF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x1000000) >> 24
}
func (o *USART_Type) SetISR_TCBGT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000000)|value<<25)
}
func (o *USART_Type) GetISR_TCBGT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000000) >> 25
}
func (o *USART_Type) SetISR_RXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x4000000)|value<<26)
}
func (o *USART_Type) GetISR_RXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x4000000) >> 26
}
func (o *USART_Type) SetISR_TXFT(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x8000000)|value<<27)
}
func (o *USART_Type) GetISR_TXFT() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x8000000) >> 27
}
func (o *USART_Type) SetISR_UDR(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetISR_UDR() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2000) >> 13
}

// USART.ICR: Interrupt flag clear register
func (o *USART_Type) SetICR_WUCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100000)|value<<20)
}
func (o *USART_Type) GetICR_WUCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100000) >> 20
}
func (o *USART_Type) SetICR_CMCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20000)|value<<17)
}
func (o *USART_Type) GetICR_CMCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20000) >> 17
}
func (o *USART_Type) SetICR_EOBCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *USART_Type) GetICR_EOBCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *USART_Type) SetICR_RTOCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *USART_Type) GetICR_RTOCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *USART_Type) SetICR_CTSCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *USART_Type) GetICR_CTSCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *USART_Type) SetICR_LBDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *USART_Type) GetICR_LBDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *USART_Type) SetICR_TCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *USART_Type) GetICR_TCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *USART_Type) SetICR_IDLECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *USART_Type) GetICR_IDLECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *USART_Type) SetICR_ORECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *USART_Type) GetICR_ORECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *USART_Type) SetICR_NCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *USART_Type) GetICR_NCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *USART_Type) SetICR_FECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *USART_Type) GetICR_FECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *USART_Type) SetICR_PECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *USART_Type) GetICR_PECF() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *USART_Type) SetICR_TXFECF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *USART_Type) GetICR_TXFECF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *USART_Type) SetICR_TCBGTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x80)|value<<7)
}
func (o *USART_Type) GetICR_TCBGTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x80) >> 7
}
func (o *USART_Type) SetICR_UDRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000)|value<<13)
}
func (o *USART_Type) GetICR_UDRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000) >> 13
}

// USART.RDR: Receive data register
func (o *USART_Type) SetRDR(value uint32) {
	volatile.StoreUint32(&o.RDR.Reg, volatile.LoadUint32(&o.RDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetRDR() uint32 {
	return volatile.LoadUint32(&o.RDR.Reg) & 0x1ff
}

// USART.TDR: Transmit data register
func (o *USART_Type) SetTDR(value uint32) {
	volatile.StoreUint32(&o.TDR.Reg, volatile.LoadUint32(&o.TDR.Reg)&^(0x1ff)|value)
}
func (o *USART_Type) GetTDR() uint32 {
	return volatile.LoadUint32(&o.TDR.Reg) & 0x1ff
}

// USART.PRESC: PRESC
func (o *USART_Type) SetPRESC_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.PRESC.Reg, volatile.LoadUint32(&o.PRESC.Reg)&^(0xf)|value)
}
func (o *USART_Type) GetPRESC_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.PRESC.Reg) & 0xf
}

// OctoSPI
type OctoSPI_Type struct {
	CR    volatile.Register32 // 0x0
	_     [4]byte
	DCR1  volatile.Register32 // 0x8
	DCR2  volatile.Register32 // 0xC
	DCR3  volatile.Register32 // 0x10
	DCR4  volatile.Register32 // 0x14
	_     [8]byte
	SR    volatile.Register32 // 0x20
	FCR   volatile.Register32 // 0x24
	_     [24]byte
	DLR   volatile.Register32 // 0x40
	_     [4]byte
	AR    volatile.Register32 // 0x48
	_     [4]byte
	DR    volatile.Register32 // 0x50
	_     [44]byte
	PSMKR volatile.Register32 // 0x80
	_     [4]byte
	PSMAR volatile.Register32 // 0x88
	_     [4]byte
	PIR   volatile.Register32 // 0x90
	_     [108]byte
	CCR   volatile.Register32 // 0x100
	_     [4]byte
	TCR   volatile.Register32 // 0x108
	_     [4]byte
	IR    volatile.Register32 // 0x110
	_     [12]byte
	ABR   volatile.Register32 // 0x120
	_     [12]byte
	LPTR  volatile.Register32 // 0x130
	_     [12]byte
	WPCCR volatile.Register32 // 0x140
	_     [4]byte
	WPTCR volatile.Register32 // 0x148
	_     [4]byte
	WPIR  volatile.Register32 // 0x150
	_     [12]byte
	WPABR volatile.Register32 // 0x160
	_     [28]byte
	WCCR  volatile.Register32 // 0x180
	_     [4]byte
	WTCR  volatile.Register32 // 0x188
	_     [4]byte
	WIR   volatile.Register32 // 0x190
	_     [12]byte
	WABR  volatile.Register32 // 0x1A0
	_     [92]byte
	HLCR  volatile.Register32 // 0x200
}

// OctoSPI.CR: control register
func (o *OctoSPI_Type) SetCR_FMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x30000000)|value<<28)
}
func (o *OctoSPI_Type) GetCR_FMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x30000000) >> 28
}
func (o *OctoSPI_Type) SetCR_PMM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800000)|value<<23)
}
func (o *OctoSPI_Type) GetCR_PMM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800000) >> 23
}
func (o *OctoSPI_Type) SetCR_APMS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400000)|value<<22)
}
func (o *OctoSPI_Type) GetCR_APMS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400000) >> 22
}
func (o *OctoSPI_Type) SetCR_TEIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *OctoSPI_Type) GetCR_TEIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *OctoSPI_Type) SetCR_TOIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *OctoSPI_Type) GetCR_TOIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *OctoSPI_Type) SetCR_SMIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetCR_SMIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetCR_FTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *OctoSPI_Type) GetCR_FTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *OctoSPI_Type) SetCR_TCIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *OctoSPI_Type) GetCR_TCIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *OctoSPI_Type) SetCR_FTHRES(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1f00)|value<<8)
}
func (o *OctoSPI_Type) GetCR_FTHRES() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1f00) >> 8
}
func (o *OctoSPI_Type) SetCR_FSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *OctoSPI_Type) GetCR_FSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *OctoSPI_Type) SetCR_DMM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *OctoSPI_Type) GetCR_DMM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *OctoSPI_Type) SetCR_TCEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetCR_TCEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetCR_DMAEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *OctoSPI_Type) GetCR_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *OctoSPI_Type) SetCR_ABORT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetCR_ABORT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetCR_EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetCR_EN() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// OctoSPI.DCR1: device configuration register
func (o *OctoSPI_Type) SetDCR1_CKMODE(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetDCR1_CKMODE() uint32 {
	return volatile.LoadUint32(&o.DCR1.Reg) & 0x1
}
func (o *OctoSPI_Type) SetDCR1_FRCK(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetDCR1_FRCK() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetDCR1_DLYBYP(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetDCR1_DLYBYP() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetDCR1_CSHT(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x700)|value<<8)
}
func (o *OctoSPI_Type) GetDCR1_CSHT() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x700) >> 8
}
func (o *OctoSPI_Type) SetDCR1_DEVSIZE(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x1f0000)|value<<16)
}
func (o *OctoSPI_Type) GetDCR1_DEVSIZE() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x1f0000) >> 16
}
func (o *OctoSPI_Type) SetDCR1_MTYP(value uint32) {
	volatile.StoreUint32(&o.DCR1.Reg, volatile.LoadUint32(&o.DCR1.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetDCR1_MTYP() uint32 {
	return (volatile.LoadUint32(&o.DCR1.Reg) & 0x7000000) >> 24
}

// OctoSPI.DCR2: device configuration register 2
func (o *OctoSPI_Type) SetDCR2_PRESCALER(value uint32) {
	volatile.StoreUint32(&o.DCR2.Reg, volatile.LoadUint32(&o.DCR2.Reg)&^(0xff)|value)
}
func (o *OctoSPI_Type) GetDCR2_PRESCALER() uint32 {
	return volatile.LoadUint32(&o.DCR2.Reg) & 0xff
}
func (o *OctoSPI_Type) SetDCR2_WRAPSIZE(value uint32) {
	volatile.StoreUint32(&o.DCR2.Reg, volatile.LoadUint32(&o.DCR2.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetDCR2_WRAPSIZE() uint32 {
	return (volatile.LoadUint32(&o.DCR2.Reg) & 0x70000) >> 16
}

// OctoSPI.DCR3: device configuration register 3
func (o *OctoSPI_Type) SetDCR3_CSBOUND(value uint32) {
	volatile.StoreUint32(&o.DCR3.Reg, volatile.LoadUint32(&o.DCR3.Reg)&^(0x1f0000)|value<<16)
}
func (o *OctoSPI_Type) GetDCR3_CSBOUND() uint32 {
	return (volatile.LoadUint32(&o.DCR3.Reg) & 0x1f0000) >> 16
}

// OctoSPI.DCR4: device configuration register 4
func (o *OctoSPI_Type) SetDCR4(value uint32) {
	volatile.StoreUint32(&o.DCR4.Reg, value)
}
func (o *OctoSPI_Type) GetDCR4() uint32 {
	return volatile.LoadUint32(&o.DCR4.Reg)
}

// OctoSPI.SR: status register
func (o *OctoSPI_Type) SetSR_TEF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetSR_TEF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *OctoSPI_Type) SetSR_TCF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetSR_TCF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetSR_FTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *OctoSPI_Type) GetSR_FTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *OctoSPI_Type) SetSR_SMF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetSR_SMF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetSR_TOF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *OctoSPI_Type) GetSR_TOF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *OctoSPI_Type) SetSR_BUSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *OctoSPI_Type) GetSR_BUSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *OctoSPI_Type) SetSR_FLEVEL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x3f00)|value<<8)
}
func (o *OctoSPI_Type) GetSR_FLEVEL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x3f00) >> 8
}

// OctoSPI.FCR: flag clear register
func (o *OctoSPI_Type) SetFCR_CTEF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetFCR_CTEF() uint32 {
	return volatile.LoadUint32(&o.FCR.Reg) & 0x1
}
func (o *OctoSPI_Type) SetFCR_CTCF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetFCR_CTCF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetFCR_CSMF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetFCR_CSMF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetFCR_CTOF(value uint32) {
	volatile.StoreUint32(&o.FCR.Reg, volatile.LoadUint32(&o.FCR.Reg)&^(0x10)|value<<4)
}
func (o *OctoSPI_Type) GetFCR_CTOF() uint32 {
	return (volatile.LoadUint32(&o.FCR.Reg) & 0x10) >> 4
}

// OctoSPI.DLR: data length register
func (o *OctoSPI_Type) SetDLR(value uint32) {
	volatile.StoreUint32(&o.DLR.Reg, value)
}
func (o *OctoSPI_Type) GetDLR() uint32 {
	return volatile.LoadUint32(&o.DLR.Reg)
}

// OctoSPI.AR: address register
func (o *OctoSPI_Type) SetAR(value uint32) {
	volatile.StoreUint32(&o.AR.Reg, value)
}
func (o *OctoSPI_Type) GetAR() uint32 {
	return volatile.LoadUint32(&o.AR.Reg)
}

// OctoSPI.DR: data register
func (o *OctoSPI_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *OctoSPI_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// OctoSPI.PSMKR: polling status mask register
func (o *OctoSPI_Type) SetPSMKR(value uint32) {
	volatile.StoreUint32(&o.PSMKR.Reg, value)
}
func (o *OctoSPI_Type) GetPSMKR() uint32 {
	return volatile.LoadUint32(&o.PSMKR.Reg)
}

// OctoSPI.PSMAR: polling status match register
func (o *OctoSPI_Type) SetPSMAR(value uint32) {
	volatile.StoreUint32(&o.PSMAR.Reg, value)
}
func (o *OctoSPI_Type) GetPSMAR() uint32 {
	return volatile.LoadUint32(&o.PSMAR.Reg)
}

// OctoSPI.PIR: polling interval register
func (o *OctoSPI_Type) SetPIR_INTERVAL(value uint32) {
	volatile.StoreUint32(&o.PIR.Reg, volatile.LoadUint32(&o.PIR.Reg)&^(0xffff)|value)
}
func (o *OctoSPI_Type) GetPIR_INTERVAL() uint32 {
	return volatile.LoadUint32(&o.PIR.Reg) & 0xffff
}

// OctoSPI.CCR: communication configuration
func (o *OctoSPI_Type) SetCCR_IMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x7)|value)
}
func (o *OctoSPI_Type) GetCCR_IMODE() uint32 {
	return volatile.LoadUint32(&o.CCR.Reg) & 0x7
}
func (o *OctoSPI_Type) SetCCR_IDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetCCR_IDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetCCR_ISIZE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x30)|value<<4)
}
func (o *OctoSPI_Type) GetCCR_ISIZE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x30) >> 4
}
func (o *OctoSPI_Type) SetCCR_ADMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x700)|value<<8)
}
func (o *OctoSPI_Type) GetCCR_ADMODE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x700) >> 8
}
func (o *OctoSPI_Type) SetCCR_ADDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x800)|value<<11)
}
func (o *OctoSPI_Type) GetCCR_ADDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x800) >> 11
}
func (o *OctoSPI_Type) SetCCR_ADSIZE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x3000)|value<<12)
}
func (o *OctoSPI_Type) GetCCR_ADSIZE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x3000) >> 12
}
func (o *OctoSPI_Type) SetCCR_ABMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetCCR_ABMODE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x70000) >> 16
}
func (o *OctoSPI_Type) SetCCR_ABDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetCCR_ABDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetCCR_ABSIZE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x300000)|value<<20)
}
func (o *OctoSPI_Type) GetCCR_ABSIZE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x300000) >> 20
}
func (o *OctoSPI_Type) SetCCR_DMODE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetCCR_DMODE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x7000000) >> 24
}
func (o *OctoSPI_Type) SetCCR_DDTR(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x8000000)|value<<27)
}
func (o *OctoSPI_Type) GetCCR_DDTR() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x8000000) >> 27
}
func (o *OctoSPI_Type) SetCCR_DQSE(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x20000000)|value<<29)
}
func (o *OctoSPI_Type) GetCCR_DQSE() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x20000000) >> 29
}
func (o *OctoSPI_Type) SetCCR_SIOO(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x80000000)|value<<31)
}
func (o *OctoSPI_Type) GetCCR_SIOO() uint32 {
	return (volatile.LoadUint32(&o.CCR.Reg) & 0x80000000) >> 31
}

// OctoSPI.TCR: timing configuration register
func (o *OctoSPI_Type) SetTCR_DCYC(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x1f)|value)
}
func (o *OctoSPI_Type) GetTCR_DCYC() uint32 {
	return volatile.LoadUint32(&o.TCR.Reg) & 0x1f
}
func (o *OctoSPI_Type) SetTCR_DHQC(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x10000000)|value<<28)
}
func (o *OctoSPI_Type) GetTCR_DHQC() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x10000000) >> 28
}
func (o *OctoSPI_Type) SetTCR_SSHIFT(value uint32) {
	volatile.StoreUint32(&o.TCR.Reg, volatile.LoadUint32(&o.TCR.Reg)&^(0x40000000)|value<<30)
}
func (o *OctoSPI_Type) GetTCR_SSHIFT() uint32 {
	return (volatile.LoadUint32(&o.TCR.Reg) & 0x40000000) >> 30
}

// OctoSPI.IR: instruction register
func (o *OctoSPI_Type) SetIR(value uint32) {
	volatile.StoreUint32(&o.IR.Reg, value)
}
func (o *OctoSPI_Type) GetIR() uint32 {
	return volatile.LoadUint32(&o.IR.Reg)
}

// OctoSPI.ABR: alternate bytes register
func (o *OctoSPI_Type) SetABR(value uint32) {
	volatile.StoreUint32(&o.ABR.Reg, value)
}
func (o *OctoSPI_Type) GetABR() uint32 {
	return volatile.LoadUint32(&o.ABR.Reg)
}

// OctoSPI.LPTR: low-power timeout register
func (o *OctoSPI_Type) SetLPTR_TIMEOUT(value uint32) {
	volatile.StoreUint32(&o.LPTR.Reg, volatile.LoadUint32(&o.LPTR.Reg)&^(0xffff)|value)
}
func (o *OctoSPI_Type) GetLPTR_TIMEOUT() uint32 {
	return volatile.LoadUint32(&o.LPTR.Reg) & 0xffff
}

// OctoSPI.WPCCR: wrap communication configuration register
func (o *OctoSPI_Type) SetWPCCR_IMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x7)|value)
}
func (o *OctoSPI_Type) GetWPCCR_IMODE() uint32 {
	return volatile.LoadUint32(&o.WPCCR.Reg) & 0x7
}
func (o *OctoSPI_Type) SetWPCCR_IDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetWPCCR_IDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetWPCCR_ISIZE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x30)|value<<4)
}
func (o *OctoSPI_Type) GetWPCCR_ISIZE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x30) >> 4
}
func (o *OctoSPI_Type) SetWPCCR_ADMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x700)|value<<8)
}
func (o *OctoSPI_Type) GetWPCCR_ADMODE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x700) >> 8
}
func (o *OctoSPI_Type) SetWPCCR_ADDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x800)|value<<11)
}
func (o *OctoSPI_Type) GetWPCCR_ADDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x800) >> 11
}
func (o *OctoSPI_Type) SetWPCCR_ADSIZE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x3000)|value<<12)
}
func (o *OctoSPI_Type) GetWPCCR_ADSIZE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x3000) >> 12
}
func (o *OctoSPI_Type) SetWPCCR_ABMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetWPCCR_ABMODE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x70000) >> 16
}
func (o *OctoSPI_Type) SetWPCCR_ABDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetWPCCR_ABDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetWPCCR_ABSIZE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x300000)|value<<20)
}
func (o *OctoSPI_Type) GetWPCCR_ABSIZE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x300000) >> 20
}
func (o *OctoSPI_Type) SetWPCCR_DMODE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetWPCCR_DMODE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x7000000) >> 24
}
func (o *OctoSPI_Type) SetWPCCR_DDTR(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x8000000)|value<<27)
}
func (o *OctoSPI_Type) GetWPCCR_DDTR() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x8000000) >> 27
}
func (o *OctoSPI_Type) SetWPCCR_DQSE(value uint32) {
	volatile.StoreUint32(&o.WPCCR.Reg, volatile.LoadUint32(&o.WPCCR.Reg)&^(0x20000000)|value<<29)
}
func (o *OctoSPI_Type) GetWPCCR_DQSE() uint32 {
	return (volatile.LoadUint32(&o.WPCCR.Reg) & 0x20000000) >> 29
}

// OctoSPI.WPTCR: wrap timing configuration register
func (o *OctoSPI_Type) SetWPTCR_DCYC(value uint32) {
	volatile.StoreUint32(&o.WPTCR.Reg, volatile.LoadUint32(&o.WPTCR.Reg)&^(0x1f)|value)
}
func (o *OctoSPI_Type) GetWPTCR_DCYC() uint32 {
	return volatile.LoadUint32(&o.WPTCR.Reg) & 0x1f
}
func (o *OctoSPI_Type) SetWPTCR_DHQC(value uint32) {
	volatile.StoreUint32(&o.WPTCR.Reg, volatile.LoadUint32(&o.WPTCR.Reg)&^(0x10000000)|value<<28)
}
func (o *OctoSPI_Type) GetWPTCR_DHQC() uint32 {
	return (volatile.LoadUint32(&o.WPTCR.Reg) & 0x10000000) >> 28
}
func (o *OctoSPI_Type) SetWPTCR_SSHIFT(value uint32) {
	volatile.StoreUint32(&o.WPTCR.Reg, volatile.LoadUint32(&o.WPTCR.Reg)&^(0x40000000)|value<<30)
}
func (o *OctoSPI_Type) GetWPTCR_SSHIFT() uint32 {
	return (volatile.LoadUint32(&o.WPTCR.Reg) & 0x40000000) >> 30
}

// OctoSPI.WPIR: wrap instruction register
func (o *OctoSPI_Type) SetWPIR(value uint32) {
	volatile.StoreUint32(&o.WPIR.Reg, value)
}
func (o *OctoSPI_Type) GetWPIR() uint32 {
	return volatile.LoadUint32(&o.WPIR.Reg)
}

// OctoSPI.WPABR: wrap alternate bytes register
func (o *OctoSPI_Type) SetWPABR(value uint32) {
	volatile.StoreUint32(&o.WPABR.Reg, value)
}
func (o *OctoSPI_Type) GetWPABR() uint32 {
	return volatile.LoadUint32(&o.WPABR.Reg)
}

// OctoSPI.WCCR: WCCR
func (o *OctoSPI_Type) SetWCCR_IMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x7)|value)
}
func (o *OctoSPI_Type) GetWCCR_IMODE() uint32 {
	return volatile.LoadUint32(&o.WCCR.Reg) & 0x7
}
func (o *OctoSPI_Type) SetWCCR_IDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x8)|value<<3)
}
func (o *OctoSPI_Type) GetWCCR_IDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x8) >> 3
}
func (o *OctoSPI_Type) SetWCCR_ISIZE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x30)|value<<4)
}
func (o *OctoSPI_Type) GetWCCR_ISIZE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x30) >> 4
}
func (o *OctoSPI_Type) SetWCCR_ADMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x700)|value<<8)
}
func (o *OctoSPI_Type) GetWCCR_ADMODE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x700) >> 8
}
func (o *OctoSPI_Type) SetWCCR_ADDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x800)|value<<11)
}
func (o *OctoSPI_Type) GetWCCR_ADDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x800) >> 11
}
func (o *OctoSPI_Type) SetWCCR_ADSIZE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x3000)|value<<12)
}
func (o *OctoSPI_Type) GetWCCR_ADSIZE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x3000) >> 12
}
func (o *OctoSPI_Type) SetWCCR_ABMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x70000)|value<<16)
}
func (o *OctoSPI_Type) GetWCCR_ABMODE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x70000) >> 16
}
func (o *OctoSPI_Type) SetWCCR_ABDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x80000)|value<<19)
}
func (o *OctoSPI_Type) GetWCCR_ABDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x80000) >> 19
}
func (o *OctoSPI_Type) SetWCCR_ABSIZE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x300000)|value<<20)
}
func (o *OctoSPI_Type) GetWCCR_ABSIZE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x300000) >> 20
}
func (o *OctoSPI_Type) SetWCCR_DMODE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x7000000)|value<<24)
}
func (o *OctoSPI_Type) GetWCCR_DMODE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x7000000) >> 24
}
func (o *OctoSPI_Type) SetWCCR_DDTR(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x8000000)|value<<27)
}
func (o *OctoSPI_Type) GetWCCR_DDTR() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x8000000) >> 27
}
func (o *OctoSPI_Type) SetWCCR_DQSE(value uint32) {
	volatile.StoreUint32(&o.WCCR.Reg, volatile.LoadUint32(&o.WCCR.Reg)&^(0x20000000)|value<<29)
}
func (o *OctoSPI_Type) GetWCCR_DQSE() uint32 {
	return (volatile.LoadUint32(&o.WCCR.Reg) & 0x20000000) >> 29
}

// OctoSPI.WTCR: WTCR
func (o *OctoSPI_Type) SetWTCR_DCYC(value uint32) {
	volatile.StoreUint32(&o.WTCR.Reg, volatile.LoadUint32(&o.WTCR.Reg)&^(0x1f)|value)
}
func (o *OctoSPI_Type) GetWTCR_DCYC() uint32 {
	return volatile.LoadUint32(&o.WTCR.Reg) & 0x1f
}

// OctoSPI.WIR: WIR
func (o *OctoSPI_Type) SetWIR(value uint32) {
	volatile.StoreUint32(&o.WIR.Reg, value)
}
func (o *OctoSPI_Type) GetWIR() uint32 {
	return volatile.LoadUint32(&o.WIR.Reg)
}

// OctoSPI.WABR: write alternate bytes register
func (o *OctoSPI_Type) SetWABR(value uint32) {
	volatile.StoreUint32(&o.WABR.Reg, value)
}
func (o *OctoSPI_Type) GetWABR() uint32 {
	return volatile.LoadUint32(&o.WABR.Reg)
}

// OctoSPI.HLCR: HyperBus latency configuration register
func (o *OctoSPI_Type) SetHLCR_LM(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0x1)|value)
}
func (o *OctoSPI_Type) GetHLCR_LM() uint32 {
	return volatile.LoadUint32(&o.HLCR.Reg) & 0x1
}
func (o *OctoSPI_Type) SetHLCR_WZL(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0x2)|value<<1)
}
func (o *OctoSPI_Type) GetHLCR_WZL() uint32 {
	return (volatile.LoadUint32(&o.HLCR.Reg) & 0x2) >> 1
}
func (o *OctoSPI_Type) SetHLCR_TACC(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0xff00)|value<<8)
}
func (o *OctoSPI_Type) GetHLCR_TACC() uint32 {
	return (volatile.LoadUint32(&o.HLCR.Reg) & 0xff00) >> 8
}
func (o *OctoSPI_Type) SetHLCR_TRWR(value uint32) {
	volatile.StoreUint32(&o.HLCR.Reg, volatile.LoadUint32(&o.HLCR.Reg)&^(0xff0000)|value<<16)
}
func (o *OctoSPI_Type) GetHLCR_TRWR() uint32 {
	return (volatile.LoadUint32(&o.HLCR.Reg) & 0xff0000) >> 16
}

// Operational amplifiers
type OPAMP_Type struct {
	OPAMP1_CSR   volatile.Register32 // 0x0
	OPAMP1_OTR   volatile.Register32 // 0x4
	OPAMP1_LPOTR volatile.Register32 // 0x8
	_            [4]byte
	OPAMP2_CRS   volatile.Register32 // 0x10
	OPAMP2_OTR   volatile.Register32 // 0x14
	OPAMP2_LPOTR volatile.Register32 // 0x18
}

// OPAMP.OPAMP1_CSR: OPAMP1 control/status register
func (o *OPAMP_Type) SetOPAMP1_CSR_OPAEN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x1)|value)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPAEN() uint32 {
	return volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x1
}
func (o *OPAMP_Type) SetOPAMP1_CSR_OPALPM(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x2)|value<<1)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPALPM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x2) >> 1
}
func (o *OPAMP_Type) SetOPAMP1_CSR_OPAMODE(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0xc)|value<<2)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPAMODE() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0xc) >> 2
}
func (o *OPAMP_Type) SetOPAMP1_CSR_PGA_GAIN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x30)|value<<4)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_PGA_GAIN() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x30) >> 4
}
func (o *OPAMP_Type) SetOPAMP1_CSR_VM_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x300)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_VM_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x300) >> 8
}
func (o *OPAMP_Type) SetOPAMP1_CSR_VP_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x400)|value<<10)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_VP_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x400) >> 10
}
func (o *OPAMP_Type) SetOPAMP1_CSR_CALON(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x1000)|value<<12)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_CALON() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x1000) >> 12
}
func (o *OPAMP_Type) SetOPAMP1_CSR_CALSEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x2000)|value<<13)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_CALSEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x2000) >> 13
}
func (o *OPAMP_Type) SetOPAMP1_CSR_USERTRIM(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x4000)|value<<14)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_USERTRIM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x4000) >> 14
}
func (o *OPAMP_Type) SetOPAMP1_CSR_CALOUT(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x8000)|value<<15)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_CALOUT() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x8000) >> 15
}
func (o *OPAMP_Type) SetOPAMP1_CSR_OPA_RANGE(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_CSR.Reg, volatile.LoadUint32(&o.OPAMP1_CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *OPAMP_Type) GetOPAMP1_CSR_OPA_RANGE() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_CSR.Reg) & 0x80000000) >> 31
}

// OPAMP.OPAMP1_OTR: OPAMP1 offset trimming register in normal mode
func (o *OPAMP_Type) SetOPAMP1_OTR_TRIMOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_OTR.Reg, volatile.LoadUint32(&o.OPAMP1_OTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP1_OTR_TRIMOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP1_OTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP1_OTR_TRIMOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_OTR.Reg, volatile.LoadUint32(&o.OPAMP1_OTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP1_OTR_TRIMOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_OTR.Reg) & 0x1f00) >> 8
}

// OPAMP.OPAMP1_LPOTR: OPAMP1 offset trimming register in low-powe mode
func (o *OPAMP_Type) SetOPAMP1_LPOTR_TRIMLPOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP1_LPOTR_TRIMLPOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP1_LPOTR_TRIMLPOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP1_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP1_LPOTR_TRIMLPOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP1_LPOTR.Reg) & 0x1f00) >> 8
}

// OPAMP.OPAMP2_CRS: OPAMP2 control/status register
func (o *OPAMP_Type) SetOPAMP2_CRS_OPAEN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x1)|value)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_OPAEN() uint32 {
	return volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x1
}
func (o *OPAMP_Type) SetOPAMP2_CRS_OPALPM(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x2)|value<<1)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_OPALPM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x2) >> 1
}
func (o *OPAMP_Type) SetOPAMP2_CRS_OPAMODE(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0xc)|value<<2)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_OPAMODE() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0xc) >> 2
}
func (o *OPAMP_Type) SetOPAMP2_CRS_PGA_GAIN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x30)|value<<4)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_PGA_GAIN() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x30) >> 4
}
func (o *OPAMP_Type) SetOPAMP2_CRS_VM_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x300)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_VM_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x300) >> 8
}
func (o *OPAMP_Type) SetOPAMP2_CRS_VP_SEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x400)|value<<10)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_VP_SEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x400) >> 10
}
func (o *OPAMP_Type) SetOPAMP2_CRS_CALON(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x1000)|value<<12)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_CALON() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x1000) >> 12
}
func (o *OPAMP_Type) SetOPAMP2_CRS_CALSEL(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x2000)|value<<13)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_CALSEL() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x2000) >> 13
}
func (o *OPAMP_Type) SetOPAMP2_CRS_USERTRIM(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x4000)|value<<14)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_USERTRIM() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x4000) >> 14
}
func (o *OPAMP_Type) SetOPAMP2_CRS_CALOUT(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_CRS.Reg, volatile.LoadUint32(&o.OPAMP2_CRS.Reg)&^(0x8000)|value<<15)
}
func (o *OPAMP_Type) GetOPAMP2_CRS_CALOUT() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_CRS.Reg) & 0x8000) >> 15
}

// OPAMP.OPAMP2_OTR: OPAMP2 offset trimming register in normal mode
func (o *OPAMP_Type) SetOPAMP2_OTR_TRIMOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_OTR.Reg, volatile.LoadUint32(&o.OPAMP2_OTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP2_OTR_TRIMOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP2_OTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP2_OTR_TRIMOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_OTR.Reg, volatile.LoadUint32(&o.OPAMP2_OTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP2_OTR_TRIMOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_OTR.Reg) & 0x1f00) >> 8
}

// OPAMP.OPAMP2_LPOTR: OPAMP2 offset trimming register in low-power mode
func (o *OPAMP_Type) SetOPAMP2_LPOTR_TRIMLPOFFSETN(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg)&^(0x1f)|value)
}
func (o *OPAMP_Type) GetOPAMP2_LPOTR_TRIMLPOFFSETN() uint32 {
	return volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg) & 0x1f
}
func (o *OPAMP_Type) SetOPAMP2_LPOTR_TRIMLPOFFSETP(value uint32) {
	volatile.StoreUint32(&o.OPAMP2_LPOTR.Reg, volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg)&^(0x1f00)|value<<8)
}
func (o *OPAMP_Type) GetOPAMP2_LPOTR_TRIMLPOFFSETP() uint32 {
	return (volatile.LoadUint32(&o.OPAMP2_LPOTR.Reg) & 0x1f00) >> 8
}

// Power control
type PWR_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	CR3      volatile.Register32 // 0x8
	CR4      volatile.Register32 // 0xC
	SR1      volatile.Register32 // 0x10
	SR2      volatile.Register32 // 0x14
	SCR      volatile.Register32 // 0x18
	_        [4]byte
	PUCRA    volatile.Register32 // 0x20
	PDCRA    volatile.Register32 // 0x24
	PUCRB    volatile.Register32 // 0x28
	PDCRB    volatile.Register32 // 0x2C
	PUCRC    volatile.Register32 // 0x30
	PDCRC    volatile.Register32 // 0x34
	PUCRD    volatile.Register32 // 0x38
	PDCRD    volatile.Register32 // 0x3C
	PUCRE    volatile.Register32 // 0x40
	PDCRE    volatile.Register32 // 0x44
	PUCRF    volatile.Register32 // 0x48
	PDCRF    volatile.Register32 // 0x4C
	PUCRG    volatile.Register32 // 0x50
	PDCRG    volatile.Register32 // 0x54
	PUCRH    volatile.Register32 // 0x58
	PDCRH    volatile.Register32 // 0x5C
	_        [24]byte
	SECCFGR  volatile.Register32 // 0x78
	_        [4]byte
	PRIVCFGR volatile.Register32 // 0x80
}

// PWR.CR1: Power control register 1
func (o *PWR_Type) SetCR1_LPR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetCR1_LPR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetCR1_VOS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x600)|value<<9)
}
func (o *PWR_Type) GetCR1_VOS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x600) >> 9
}
func (o *PWR_Type) SetCR1_DBP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetCR1_DBP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetCR1_LPMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x7)|value)
}
func (o *PWR_Type) GetCR1_LPMS() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x7
}

// PWR.CR2: Power control register 2
func (o *PWR_Type) SetCR2_USV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetCR2_USV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetCR2_IOSV(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetCR2_IOSV() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetCR2_PVME4(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetCR2_PVME4() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetCR2_PVME3(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetCR2_PVME3() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetCR2_PVME2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetCR2_PVME2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetCR2_PVME1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR2_PVME1() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR2_PLS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xe)|value<<1)
}
func (o *PWR_Type) GetCR2_PLS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xe) >> 1
}
func (o *PWR_Type) SetCR2_PVDE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetCR2_PVDE() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}

// PWR.CR3: Power control register 3
func (o *PWR_Type) SetCR3_UCPD_DBDIS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetCR3_UCPD_DBDIS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetCR3_UCPD_STDBY(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetCR3_UCPD_STDBY() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetCR3_ULPMEN(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetCR3_ULPMEN() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetCR3_APC(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetCR3_APC() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetCR3_RRS(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x300)|value<<8)
}
func (o *PWR_Type) GetCR3_RRS() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x300) >> 8
}
func (o *PWR_Type) SetCR3_EWUP5(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR3_EWUP5() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR3_EWUP4(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetCR3_EWUP4() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetCR3_EWUP3(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetCR3_EWUP3() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetCR3_EWUP2(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetCR3_EWUP2() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetCR3_EWUP1(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetCR3_EWUP1() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}

// PWR.CR4: Power control register 4
func (o *PWR_Type) SetCR4_SMPSLPEN(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetCR4_SMPSLPEN() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetCR4_SMPSFSTEN(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetCR4_SMPSFSTEN() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetCR4_EXTSMPSEN(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetCR4_EXTSMPSEN() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetCR4_SMPSBYP(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetCR4_SMPSBYP() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetCR4_VBRS(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetCR4_VBRS() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetCR4_VBE(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetCR4_VBE() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetCR4_WUPP5(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetCR4_WUPP5() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetCR4_WUPP4(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetCR4_WUPP4() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetCR4_WUPP3(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetCR4_WUPP3() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetCR4_WUPP2(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetCR4_WUPP2() uint32 {
	return (volatile.LoadUint32(&o.CR4.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetCR4_WUPP1(value uint32) {
	volatile.StoreUint32(&o.CR4.Reg, volatile.LoadUint32(&o.CR4.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetCR4_WUPP1() uint32 {
	return volatile.LoadUint32(&o.CR4.Reg) & 0x1
}

// PWR.SR1: Power status register 1
func (o *PWR_Type) SetSR1_SMPSHPRDY(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetSR1_SMPSHPRDY() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetSR1_EXTSMPSRDY(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetSR1_EXTSMPSRDY() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetSR1_SMPSBYPRDY(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetSR1_SMPSBYPRDY() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetSR1_SBF(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetSR1_SBF() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetSR1_WUF5(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSR1_WUF5() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSR1_WUF4(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetSR1_WUF4() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetSR1_WUF3(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetSR1_WUF3() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetSR1_WUF2(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSR1_WUF2() uint32 {
	return (volatile.LoadUint32(&o.SR1.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSR1_WUF1(value uint32) {
	volatile.StoreUint32(&o.SR1.Reg, volatile.LoadUint32(&o.SR1.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetSR1_WUF1() uint32 {
	return volatile.LoadUint32(&o.SR1.Reg) & 0x1
}

// PWR.SR2: Power status register 2
func (o *PWR_Type) SetSR2_PVMO4(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetSR2_PVMO4() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetSR2_PVMO3(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetSR2_PVMO3() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetSR2_PVMO2(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetSR2_PVMO2() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetSR2_PVMO1(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetSR2_PVMO1() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetSR2_PVDO(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetSR2_PVDO() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetSR2_VOSF(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetSR2_VOSF() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetSR2_REGLPF(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetSR2_REGLPF() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetSR2_REGLPS(value uint32) {
	volatile.StoreUint32(&o.SR2.Reg, volatile.LoadUint32(&o.SR2.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetSR2_REGLPS() uint32 {
	return (volatile.LoadUint32(&o.SR2.Reg) & 0x100) >> 8
}

// PWR.SCR: Power status clear register
func (o *PWR_Type) SetSCR_CSBF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetSCR_CSBF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetSCR_CWUF5(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSCR_CWUF5() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSCR_CWUF4(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetSCR_CWUF4() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetSCR_CWUF3(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetSCR_CWUF3() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetSCR_CWUF2(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSCR_CWUF2() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSCR_CWUF1(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetSCR_CWUF1() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}

// PWR.PUCRA: Power Port A pull-up control register
func (o *PWR_Type) SetPUCRA_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRA_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRA_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRA_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRA_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRA_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRA_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRA_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRA_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRA_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRA_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRA_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRA_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRA_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRA_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRA_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRA_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRA_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRA_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRA_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRA_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRA_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRA_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRA_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRA_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRA_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRA_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRA_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRA_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRA_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRA.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRA_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRA.Reg, volatile.LoadUint32(&o.PUCRA.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRA_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRA.Reg) & 0x1
}

// PWR.PDCRA: Power Port A pull-down control register
func (o *PWR_Type) SetPDCRA_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRA_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRA_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRA_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRA_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRA_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRA_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRA_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRA_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRA_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRA_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRA_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRA_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRA_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRA_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRA_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRA_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRA_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRA_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRA_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRA_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRA_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRA_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRA_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRA_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRA_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRA_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRA_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRA_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRA_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRA.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRA_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRA.Reg, volatile.LoadUint32(&o.PDCRA.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRA_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRA.Reg) & 0x1
}

// PWR.PUCRB: Power Port B pull-up control register
func (o *PWR_Type) SetPUCRB_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRB_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRB_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRB_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRB_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRB_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRB_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRB_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRB_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRB_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRB_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRB_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRB_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRB_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRB_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRB_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRB_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRB_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRB_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRB_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRB_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRB_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRB_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRB_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRB_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRB_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRB_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRB_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRB_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRB_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRB.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRB_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRB.Reg, volatile.LoadUint32(&o.PUCRB.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRB_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRB.Reg) & 0x1
}

// PWR.PDCRB: Power Port B pull-down control register
func (o *PWR_Type) SetPDCRB_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRB_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRB_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRB_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRB_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRB_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRB_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRB_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRB_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRB_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRB_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRB_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRB_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRB_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRB_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRB_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRB_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRB_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRB_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRB_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRB_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRB_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRB_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRB_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRB_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRB_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRB_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRB_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRB_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRB_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRB.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRB_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRB.Reg, volatile.LoadUint32(&o.PDCRB.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRB_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRB.Reg) & 0x1
}

// PWR.PUCRC: Power Port C pull-up control register
func (o *PWR_Type) SetPUCRC_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRC_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRC_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRC_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRC_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRC_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRC_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRC_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRC_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRC_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRC_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRC_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRC_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRC_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRC_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRC_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRC_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRC_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRC_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRC_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRC_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRC_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRC_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRC_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRC_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRC_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRC_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRC_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRC_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRC_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRC.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRC_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRC.Reg, volatile.LoadUint32(&o.PUCRC.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRC_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRC.Reg) & 0x1
}

// PWR.PDCRC: Power Port C pull-down control register
func (o *PWR_Type) SetPDCRC_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRC_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRC_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRC_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRC_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRC_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRC_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRC_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRC_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRC_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRC_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRC_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRC_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRC_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRC_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRC_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRC_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRC_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRC_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRC_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRC_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRC_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRC_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRC_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRC_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRC_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRC_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRC_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRC_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRC_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRC.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRC_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRC.Reg, volatile.LoadUint32(&o.PDCRC.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRC_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRC.Reg) & 0x1
}

// PWR.PUCRD: Power Port D pull-up control register
func (o *PWR_Type) SetPUCRD_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRD_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRD_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRD_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRD_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRD_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRD_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRD_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRD_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRD_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRD_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRD_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRD_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRD_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRD_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRD_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRD_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRD_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRD_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRD_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRD_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRD_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRD_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRD_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRD_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRD_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRD_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRD_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRD_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRD_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRD.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRD_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRD.Reg, volatile.LoadUint32(&o.PUCRD.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRD_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRD.Reg) & 0x1
}

// PWR.PDCRD: Power Port D pull-down control register
func (o *PWR_Type) SetPDCRD_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRD_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRD_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRD_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRD_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRD_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRD_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRD_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRD_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRD_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRD_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRD_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRD_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRD_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRD_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRD_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRD_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRD_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRD_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRD_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRD_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRD_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRD_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRD_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRD_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRD_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRD_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRD_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRD_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRD_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRD.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRD_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRD.Reg, volatile.LoadUint32(&o.PDCRD.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRD_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRD.Reg) & 0x1
}

// PWR.PUCRE: Power Port E pull-up control register
func (o *PWR_Type) SetPUCRE_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRE_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRE_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRE_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRE_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRE_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRE_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRE_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRE_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRE_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRE_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRE_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRE_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRE_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRE_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRE_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRE_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRE_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRE_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRE_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRE_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRE_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRE_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRE_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRE_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRE_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRE_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRE_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRE_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRE_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRE.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRE_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRE.Reg, volatile.LoadUint32(&o.PUCRE.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRE_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRE.Reg) & 0x1
}

// PWR.PDCRE: Power Port E pull-down control register
func (o *PWR_Type) SetPDCRE_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRE_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRE_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRE_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRE_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRE_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRE_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRE_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRE_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRE_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRE_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRE_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRE_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRE_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRE_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRE_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRE_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRE_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRE_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRE_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRE_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRE_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRE_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRE_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRE_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRE_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRE_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRE_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRE_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRE_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRE.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRE_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRE.Reg, volatile.LoadUint32(&o.PDCRE.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRE_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRE.Reg) & 0x1
}

// PWR.PUCRF: Power Port F pull-up control register
func (o *PWR_Type) SetPUCRF_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRF_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRF_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRF_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRF_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRF_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRF_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRF_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRF_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRF_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRF_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRF_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRF_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRF_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRF_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRF_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRF_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRF_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRF_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRF_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRF_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRF_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRF_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRF_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRF_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRF_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRF_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRF_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRF_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRF_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRF.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRF_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRF.Reg, volatile.LoadUint32(&o.PUCRF.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRF_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRF.Reg) & 0x1
}

// PWR.PDCRF: Power Port F pull-down control register
func (o *PWR_Type) SetPDCRF_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRF_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRF_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRF_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRF_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRF_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRF_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRF_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRF_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRF_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRF_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRF_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRF_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRF_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRF_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRF_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRF_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRF_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRF_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRF_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRF_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRF_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRF_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRF_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRF_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRF_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRF_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRF_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRF_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRF_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRF.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRF_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRF.Reg, volatile.LoadUint32(&o.PDCRF.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRF_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRF.Reg) & 0x1
}

// PWR.PUCRG: Power Port G pull-up control register
func (o *PWR_Type) SetPUCRG_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRG_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRG_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRG_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRG_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRG_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRG_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRG_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRG_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRG_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRG_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRG_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRG_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRG_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRG_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRG_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRG_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRG_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRG_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRG_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRG_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRG_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRG_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRG_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRG_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRG_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRG_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRG_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRG_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRG_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRG.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRG_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRG.Reg, volatile.LoadUint32(&o.PUCRG.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRG_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRG.Reg) & 0x1
}

// PWR.PDCRG: Power Port G pull-down control register
func (o *PWR_Type) SetPDCRG_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRG_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRG_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRG_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRG_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRG_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRG_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRG_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRG_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRG_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRG_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRG_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRG_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRG_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRG_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRG_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRG_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRG_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRG_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRG_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRG_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRG_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRG_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRG_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRG_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRG_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRG_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRG_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRG_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRG_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRG.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRG_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRG.Reg, volatile.LoadUint32(&o.PDCRG.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRG_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRG.Reg) & 0x1
}

// PWR.PUCRH: Power Port H pull-up control register
func (o *PWR_Type) SetPUCRH_PU15(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPUCRH_PU15() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPUCRH_PU14(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPUCRH_PU14() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPUCRH_PU13(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPUCRH_PU13() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPUCRH_PU12(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPUCRH_PU12() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPUCRH_PU11(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPUCRH_PU11() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPUCRH_PU10(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPUCRH_PU10() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPUCRH_PU9(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPUCRH_PU9() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPUCRH_PU8(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPUCRH_PU8() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPUCRH_PU7(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPUCRH_PU7() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPUCRH_PU6(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPUCRH_PU6() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPUCRH_PU5(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPUCRH_PU5() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPUCRH_PU4(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPUCRH_PU4() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPUCRH_PU3(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPUCRH_PU3() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPUCRH_PU2(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPUCRH_PU2() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPUCRH_PU1(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPUCRH_PU1() uint32 {
	return (volatile.LoadUint32(&o.PUCRH.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPUCRH_PU0(value uint32) {
	volatile.StoreUint32(&o.PUCRH.Reg, volatile.LoadUint32(&o.PUCRH.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPUCRH_PU0() uint32 {
	return volatile.LoadUint32(&o.PUCRH.Reg) & 0x1
}

// PWR.PDCRH: Power Port H pull-down control register
func (o *PWR_Type) SetPDCRH_PD15(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x8000)|value<<15)
}
func (o *PWR_Type) GetPDCRH_PD15() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x8000) >> 15
}
func (o *PWR_Type) SetPDCRH_PD14(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x4000)|value<<14)
}
func (o *PWR_Type) GetPDCRH_PD14() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x4000) >> 14
}
func (o *PWR_Type) SetPDCRH_PD13(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x2000)|value<<13)
}
func (o *PWR_Type) GetPDCRH_PD13() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x2000) >> 13
}
func (o *PWR_Type) SetPDCRH_PD12(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x1000)|value<<12)
}
func (o *PWR_Type) GetPDCRH_PD12() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x1000) >> 12
}
func (o *PWR_Type) SetPDCRH_PD11(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetPDCRH_PD11() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetPDCRH_PD10(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetPDCRH_PD10() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetPDCRH_PD9(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetPDCRH_PD9() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetPDCRH_PD8(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetPDCRH_PD8() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetPDCRH_PD7(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x80)|value<<7)
}
func (o *PWR_Type) GetPDCRH_PD7() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x80) >> 7
}
func (o *PWR_Type) SetPDCRH_PD6(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x40)|value<<6)
}
func (o *PWR_Type) GetPDCRH_PD6() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x40) >> 6
}
func (o *PWR_Type) SetPDCRH_PD5(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x20)|value<<5)
}
func (o *PWR_Type) GetPDCRH_PD5() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x20) >> 5
}
func (o *PWR_Type) SetPDCRH_PD4(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetPDCRH_PD4() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetPDCRH_PD3(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetPDCRH_PD3() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetPDCRH_PD2(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetPDCRH_PD2() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetPDCRH_PD1(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetPDCRH_PD1() uint32 {
	return (volatile.LoadUint32(&o.PDCRH.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetPDCRH_PD0(value uint32) {
	volatile.StoreUint32(&o.PDCRH.Reg, volatile.LoadUint32(&o.PDCRH.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPDCRH_PD0() uint32 {
	return volatile.LoadUint32(&o.PDCRH.Reg) & 0x1
}

// PWR.SECCFGR: Power secure configuration register
func (o *PWR_Type) SetSECCFGR_APCSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x800)|value<<11)
}
func (o *PWR_Type) GetSECCFGR_APCSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x800) >> 11
}
func (o *PWR_Type) SetSECCFGR_VBSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x400)|value<<10)
}
func (o *PWR_Type) GetSECCFGR_VBSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x400) >> 10
}
func (o *PWR_Type) SetSECCFGR_VDMSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x200)|value<<9)
}
func (o *PWR_Type) GetSECCFGR_VDMSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x200) >> 9
}
func (o *PWR_Type) SetSECCFGR_LPMSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x100)|value<<8)
}
func (o *PWR_Type) GetSECCFGR_LPMSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x100) >> 8
}
func (o *PWR_Type) SetSECCFGR_WUP5SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *PWR_Type) GetSECCFGR_WUP5SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}
func (o *PWR_Type) SetSECCFGR_WUP4SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *PWR_Type) GetSECCFGR_WUP4SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *PWR_Type) SetSECCFGR_WUP3SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *PWR_Type) GetSECCFGR_WUP3SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *PWR_Type) SetSECCFGR_WUP2SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *PWR_Type) GetSECCFGR_WUP2SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *PWR_Type) SetSECCFGR_WUP1SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetSECCFGR_WUP1SEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}

// PWR.PRIVCFGR: Power privilege configuration register
func (o *PWR_Type) SetPRIVCFGR_PRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCFGR.Reg, volatile.LoadUint32(&o.PRIVCFGR.Reg)&^(0x1)|value)
}
func (o *PWR_Type) GetPRIVCFGR_PRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCFGR.Reg) & 0x1
}

// Reset and clock control
type RCC_Type struct {
	CR          volatile.Register32 // 0x0
	ICSCR       volatile.Register32 // 0x4
	CFGR        volatile.Register32 // 0x8
	PLLCFGR     volatile.Register32 // 0xC
	PLLSAI1CFGR volatile.Register32 // 0x10
	PLLSAI2CFGR volatile.Register32 // 0x14
	CIER        volatile.Register32 // 0x18
	CIFR        volatile.Register32 // 0x1C
	CICR        volatile.Register32 // 0x20
	_           [4]byte
	AHB1RSTR    volatile.Register32 // 0x28
	AHB2RSTR    volatile.Register32 // 0x2C
	AHB3RSTR    volatile.Register32 // 0x30
	_           [4]byte
	APB1RSTR1   volatile.Register32 // 0x38
	APB1RSTR2   volatile.Register32 // 0x3C
	APB2RSTR    volatile.Register32 // 0x40
	_           [4]byte
	AHB1ENR     volatile.Register32 // 0x48
	AHB2ENR     volatile.Register32 // 0x4C
	AHB3ENR     volatile.Register32 // 0x50
	_           [4]byte
	APB1ENR1    volatile.Register32 // 0x58
	APB1ENR2    volatile.Register32 // 0x5C
	APB2ENR     volatile.Register32 // 0x60
	_           [4]byte
	AHB1SMENR   volatile.Register32 // 0x68
	AHB2SMENR   volatile.Register32 // 0x6C
	AHB3SMENR   volatile.Register32 // 0x70
	_           [4]byte
	APB1SMENR1  volatile.Register32 // 0x78
	APB1SMENR2  volatile.Register32 // 0x7C
	APB2SMENR   volatile.Register32 // 0x80
	_           [4]byte
	CCIPR1      volatile.Register32 // 0x88
	_           [4]byte
	BDCR        volatile.Register32 // 0x90
	CSR         volatile.Register32 // 0x94
	CRRCR       volatile.Register32 // 0x98
	CCIPR2      volatile.Register32 // 0x9C
	_           [24]byte
	SECCFGR     volatile.Register32 // 0xB8
	SECSR       volatile.Register32 // 0xBC
	_           [40]byte
	AHB1SECSR   volatile.Register32 // 0xE8
	AHB2SECSR   volatile.Register32 // 0xEC
	AHB3SECSR   volatile.Register32 // 0xF0
	_           [4]byte
	APB1SECSR1  volatile.Register32 // 0xF8
	APB1SECSR2  volatile.Register32 // 0xFC
	APB2SECSR   volatile.Register32 // 0x100
}

// RCC.CR: Clock control register
func (o *RCC_Type) SetCR_PRIV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetCR_PRIV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}
func (o *RCC_Type) SetCR_MSIRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCR_MSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCR_PLLSAI2RDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetCR_PLLSAI2RDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetCR_PLLSAI2ON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetCR_PLLSAI2ON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetCR_PLLSAI1RDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetCR_PLLSAI1RDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetCR_PLLSAI1ON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetCR_PLLSAI1ON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetCR_PLLRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetCR_PLLRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetCR_HSION(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCR_HSION() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCR_PLLON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetCR_PLLON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetCR_CSSON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetCR_CSSON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetCR_HSEBYP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetCR_HSEBYP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetCR_HSERDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetCR_HSERDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetCR_HSEON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetCR_HSEON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetCR_HSIASFS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetCR_HSIASFS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetCR_HSIRDY(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCR_HSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetCR_HSIKERON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCR_HSIKERON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetCR_MSIRANGE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf0)|value<<4)
}
func (o *RCC_Type) GetCR_MSIRANGE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf0) >> 4
}
func (o *RCC_Type) SetCR_MSIRGSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCR_MSIRGSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCR_MSIPLLEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCR_MSIPLLEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCR_MSION(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCR_MSION() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// RCC.ICSCR: Internal clock sources calibration register
func (o *RCC_Type) SetICSCR_HSITRIM(value uint32) {
	volatile.StoreUint32(&o.ICSCR.Reg, volatile.LoadUint32(&o.ICSCR.Reg)&^(0x7f000000)|value<<24)
}
func (o *RCC_Type) GetICSCR_HSITRIM() uint32 {
	return (volatile.LoadUint32(&o.ICSCR.Reg) & 0x7f000000) >> 24
}
func (o *RCC_Type) SetICSCR_HSICAL(value uint32) {
	volatile.StoreUint32(&o.ICSCR.Reg, volatile.LoadUint32(&o.ICSCR.Reg)&^(0xff0000)|value<<16)
}
func (o *RCC_Type) GetICSCR_HSICAL() uint32 {
	return (volatile.LoadUint32(&o.ICSCR.Reg) & 0xff0000) >> 16
}
func (o *RCC_Type) SetICSCR_MSITRIM(value uint32) {
	volatile.StoreUint32(&o.ICSCR.Reg, volatile.LoadUint32(&o.ICSCR.Reg)&^(0xff00)|value<<8)
}
func (o *RCC_Type) GetICSCR_MSITRIM() uint32 {
	return (volatile.LoadUint32(&o.ICSCR.Reg) & 0xff00) >> 8
}
func (o *RCC_Type) SetICSCR_MSICAL(value uint32) {
	volatile.StoreUint32(&o.ICSCR.Reg, volatile.LoadUint32(&o.ICSCR.Reg)&^(0xff)|value)
}
func (o *RCC_Type) GetICSCR_MSICAL() uint32 {
	return volatile.LoadUint32(&o.ICSCR.Reg) & 0xff
}

// RCC.CFGR: Clock configuration register
func (o *RCC_Type) SetCFGR_MCOPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x70000000)|value<<28)
}
func (o *RCC_Type) GetCFGR_MCOPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x70000000) >> 28
}
func (o *RCC_Type) SetCFGR_MCOSEL(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xf000000)|value<<24)
}
func (o *RCC_Type) GetCFGR_MCOSEL() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xf000000) >> 24
}
func (o *RCC_Type) SetCFGR_STOPWUCK(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetCFGR_STOPWUCK() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetCFGR_PPRE1(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x700)|value<<8)
}
func (o *RCC_Type) GetCFGR_PPRE1() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x700) >> 8
}
func (o *RCC_Type) SetCFGR_PPRE2(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x3800)|value<<11)
}
func (o *RCC_Type) GetCFGR_PPRE2() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x3800) >> 11
}
func (o *RCC_Type) SetCFGR_HPRE(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xf0)|value<<4)
}
func (o *RCC_Type) GetCFGR_HPRE() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xf0) >> 4
}
func (o *RCC_Type) SetCFGR_SWS(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetCFGR_SWS() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetCFGR_SW(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetCFGR_SW() uint32 {
	return volatile.LoadUint32(&o.CFGR.Reg) & 0x3
}

// RCC.PLLCFGR: PLL configuration register
func (o *RCC_Type) SetPLLCFGR_PLLPDIV(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0xf8000000)|value<<27)
}
func (o *RCC_Type) GetPLLCFGR_PLLPDIV() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0xf8000000) >> 27
}
func (o *RCC_Type) SetPLLCFGR_PLLR(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x6000000)|value<<25)
}
func (o *RCC_Type) GetPLLCFGR_PLLR() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x6000000) >> 25
}
func (o *RCC_Type) SetPLLCFGR_PLLREN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetPLLCFGR_PLLREN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetPLLCFGR_PLLQ(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x600000)|value<<21)
}
func (o *RCC_Type) GetPLLCFGR_PLLQ() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x600000) >> 21
}
func (o *RCC_Type) SetPLLCFGR_PLLQEN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetPLLCFGR_PLLQEN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetPLLCFGR_PLLP(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetPLLCFGR_PLLP() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetPLLCFGR_PLLPEN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetPLLCFGR_PLLPEN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetPLLCFGR_PLLN(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x7f00)|value<<8)
}
func (o *RCC_Type) GetPLLCFGR_PLLN() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x7f00) >> 8
}
func (o *RCC_Type) SetPLLCFGR_PLLM(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0xf0)|value<<4)
}
func (o *RCC_Type) GetPLLCFGR_PLLM() uint32 {
	return (volatile.LoadUint32(&o.PLLCFGR.Reg) & 0xf0) >> 4
}
func (o *RCC_Type) SetPLLCFGR_PLLSRC(value uint32) {
	volatile.StoreUint32(&o.PLLCFGR.Reg, volatile.LoadUint32(&o.PLLCFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetPLLCFGR_PLLSRC() uint32 {
	return volatile.LoadUint32(&o.PLLCFGR.Reg) & 0x3
}

// RCC.PLLSAI1CFGR: PLLSAI1 configuration register
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1PDIV(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0xf8000000)|value<<27)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1PDIV() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0xf8000000) >> 27
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1R(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x6000000)|value<<25)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1R() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x6000000) >> 25
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1REN(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1REN() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1Q(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x600000)|value<<21)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1Q() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x600000) >> 21
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1QEN(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1QEN() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1P(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1P() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1PEN(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1PEN() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1N(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x7f00)|value<<8)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1N() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x7f00) >> 8
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1M(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0xf0)|value<<4)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1M() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0xf0) >> 4
}
func (o *RCC_Type) SetPLLSAI1CFGR_PLLSAI1SRC(value uint32) {
	volatile.StoreUint32(&o.PLLSAI1CFGR.Reg, volatile.LoadUint32(&o.PLLSAI1CFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetPLLSAI1CFGR_PLLSAI1SRC() uint32 {
	return volatile.LoadUint32(&o.PLLSAI1CFGR.Reg) & 0x3
}

// RCC.PLLSAI2CFGR: PLLSAI2 configuration register
func (o *RCC_Type) SetPLLSAI2CFGR_PLLSAI2PDIV(value uint32) {
	volatile.StoreUint32(&o.PLLSAI2CFGR.Reg, volatile.LoadUint32(&o.PLLSAI2CFGR.Reg)&^(0xf8000000)|value<<27)
}
func (o *RCC_Type) GetPLLSAI2CFGR_PLLSAI2PDIV() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI2CFGR.Reg) & 0xf8000000) >> 27
}
func (o *RCC_Type) SetPLLSAI2CFGR_PLLSAI2P(value uint32) {
	volatile.StoreUint32(&o.PLLSAI2CFGR.Reg, volatile.LoadUint32(&o.PLLSAI2CFGR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetPLLSAI2CFGR_PLLSAI2P() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI2CFGR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetPLLSAI2CFGR_PLLSAI2PEN(value uint32) {
	volatile.StoreUint32(&o.PLLSAI2CFGR.Reg, volatile.LoadUint32(&o.PLLSAI2CFGR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetPLLSAI2CFGR_PLLSAI2PEN() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI2CFGR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetPLLSAI2CFGR_PLLSAI2N(value uint32) {
	volatile.StoreUint32(&o.PLLSAI2CFGR.Reg, volatile.LoadUint32(&o.PLLSAI2CFGR.Reg)&^(0x7f00)|value<<8)
}
func (o *RCC_Type) GetPLLSAI2CFGR_PLLSAI2N() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI2CFGR.Reg) & 0x7f00) >> 8
}
func (o *RCC_Type) SetPLLSAI2CFGR_PLLSAI2M(value uint32) {
	volatile.StoreUint32(&o.PLLSAI2CFGR.Reg, volatile.LoadUint32(&o.PLLSAI2CFGR.Reg)&^(0xf0)|value<<4)
}
func (o *RCC_Type) GetPLLSAI2CFGR_PLLSAI2M() uint32 {
	return (volatile.LoadUint32(&o.PLLSAI2CFGR.Reg) & 0xf0) >> 4
}
func (o *RCC_Type) SetPLLSAI2CFGR_PLLSAI2SRC(value uint32) {
	volatile.StoreUint32(&o.PLLSAI2CFGR.Reg, volatile.LoadUint32(&o.PLLSAI2CFGR.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetPLLSAI2CFGR_PLLSAI2SRC() uint32 {
	return volatile.LoadUint32(&o.PLLSAI2CFGR.Reg) & 0x3
}

// RCC.CIER: Clock interrupt enable register
func (o *RCC_Type) SetCIER_LSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIER_LSIRDYIE() uint32 {
	return volatile.LoadUint32(&o.CIER.Reg) & 0x1
}
func (o *RCC_Type) SetCIER_LSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIER_LSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIER_MSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCIER_MSIRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCIER_HSIRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIER_HSIRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIER_HSERDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIER_HSERDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIER_PLLRDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIER_PLLRDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCIER_PLLSAI1RDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCIER_PLLSAI1RDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCIER_PLLSAI2RDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCIER_PLLSAI2RDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCIER_LSECSSIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCIER_LSECSSIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetCIER_HSI48RDYIE(value uint32) {
	volatile.StoreUint32(&o.CIER.Reg, volatile.LoadUint32(&o.CIER.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCIER_HSI48RDYIE() uint32 {
	return (volatile.LoadUint32(&o.CIER.Reg) & 0x400) >> 10
}

// RCC.CIFR: Clock interrupt flag register
func (o *RCC_Type) SetCIFR_LSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCIFR_LSIRDYF() uint32 {
	return volatile.LoadUint32(&o.CIFR.Reg) & 0x1
}
func (o *RCC_Type) SetCIFR_LSERDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCIFR_LSERDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCIFR_MSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCIFR_MSIRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCIFR_HSIRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCIFR_HSIRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCIFR_HSERDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCIFR_HSERDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCIFR_PLLRDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCIFR_PLLRDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCIFR_PLLSAI1RDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCIFR_PLLSAI1RDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCIFR_PLLSAI2RDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCIFR_PLLSAI2RDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCIFR_CSSF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCIFR_CSSF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCIFR_LSECSSF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCIFR_LSECSSF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetCIFR_HSI48RDYF(value uint32) {
	volatile.StoreUint32(&o.CIFR.Reg, volatile.LoadUint32(&o.CIFR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCIFR_HSI48RDYF() uint32 {
	return (volatile.LoadUint32(&o.CIFR.Reg) & 0x400) >> 10
}

// RCC.CICR: Clock interrupt clear register
func (o *RCC_Type) SetCICR_LSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCICR_LSIRDYC() uint32 {
	return volatile.LoadUint32(&o.CICR.Reg) & 0x1
}
func (o *RCC_Type) SetCICR_LSERDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCICR_LSERDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCICR_MSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCICR_MSIRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCICR_HSIRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetCICR_HSIRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetCICR_HSERDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCICR_HSERDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCICR_PLLRDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetCICR_PLLRDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetCICR_PLLSAI1RDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetCICR_PLLSAI1RDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetCICR_PLLSAI2RDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetCICR_PLLSAI2RDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetCICR_CSSC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetCICR_CSSC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetCICR_LSECSSC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetCICR_LSECSSC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetCICR_HSI48RDYC(value uint32) {
	volatile.StoreUint32(&o.CICR.Reg, volatile.LoadUint32(&o.CICR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetCICR_HSI48RDYC() uint32 {
	return (volatile.LoadUint32(&o.CICR.Reg) & 0x400) >> 10
}

// RCC.AHB1RSTR: AHB1 peripheral reset register
func (o *RCC_Type) SetAHB1RSTR_DMA1RST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB1RSTR_DMA1RST() uint32 {
	return volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB1RSTR_DMA2RST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB1RSTR_DMA2RST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB1RSTR_DMAMUX1RST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB1RSTR_DMAMUX1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB1RSTR_FLASHRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB1RSTR_FLASHRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB1RSTR_CRCRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB1RSTR_CRCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB1RSTR_TSCRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB1RSTR_TSCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB1RSTR_GTZCRST(value uint32) {
	volatile.StoreUint32(&o.AHB1RSTR.Reg, volatile.LoadUint32(&o.AHB1RSTR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB1RSTR_GTZCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB1RSTR.Reg) & 0x400000) >> 22
}

// RCC.AHB2RSTR: AHB2 peripheral reset register
func (o *RCC_Type) SetAHB2RSTR_GPIOARST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2RSTR_GPIOARST() uint32 {
	return volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2RSTR_GPIOBRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB2RSTR_GPIOBRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB2RSTR_GPIOCRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB2RSTR_GPIOCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB2RSTR_GPIODRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB2RSTR_GPIODRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB2RSTR_GPIOERST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2RSTR_GPIOERST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2RSTR_GPIOFRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB2RSTR_GPIOFRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB2RSTR_GPIOGRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB2RSTR_GPIOGRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB2RSTR_GPIOHRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAHB2RSTR_GPIOHRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAHB2RSTR_ADCRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAHB2RSTR_ADCRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAHB2RSTR_AESRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB2RSTR_AESRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB2RSTR_HASHRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB2RSTR_HASHRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB2RSTR_RNGRST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB2RSTR_RNGRST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB2RSTR_PKARST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB2RSTR_PKARST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB2RSTR_OTFDEC1RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB2RSTR_OTFDEC1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB2RSTR_SDMMC1RST(value uint32) {
	volatile.StoreUint32(&o.AHB2RSTR.Reg, volatile.LoadUint32(&o.AHB2RSTR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB2RSTR_SDMMC1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB2RSTR.Reg) & 0x400000) >> 22
}

// RCC.AHB3RSTR: AHB3 peripheral reset register
func (o *RCC_Type) SetAHB3RSTR_FMCRST(value uint32) {
	volatile.StoreUint32(&o.AHB3RSTR.Reg, volatile.LoadUint32(&o.AHB3RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB3RSTR_FMCRST() uint32 {
	return volatile.LoadUint32(&o.AHB3RSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB3RSTR_OSPI1RST(value uint32) {
	volatile.StoreUint32(&o.AHB3RSTR.Reg, volatile.LoadUint32(&o.AHB3RSTR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB3RSTR_OSPI1RST() uint32 {
	return (volatile.LoadUint32(&o.AHB3RSTR.Reg) & 0x100) >> 8
}

// RCC.APB1RSTR1: APB1 peripheral reset register 1
func (o *RCC_Type) SetAPB1RSTR1_TIM2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM2RST() uint32 {
	return volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1RSTR1_LPTIM1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAPB1RSTR1_LPTIM1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x80000000) >> 31
}
func (o *RCC_Type) SetAPB1RSTR1_OPAMPRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAPB1RSTR1_OPAMPRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAPB1RSTR1_DAC1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetAPB1RSTR1_DAC1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetAPB1RSTR1_PWRRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAPB1RSTR1_PWRRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAPB1RSTR1_CRSRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB1RSTR1_CRSRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB1RSTR1_I2C3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1RSTR1_I2C3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAPB1RSTR1_I2C2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB1RSTR1_I2C2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB1RSTR1_I2C1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1RSTR1_I2C1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1RSTR1_UART5RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB1RSTR1_UART5RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB1RSTR1_UART4RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAPB1RSTR1_UART4RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAPB1RSTR1_USART3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB1RSTR1_USART3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB1RSTR1_USART2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB1RSTR1_USART2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB1RSTR1_SPI3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPB1RSTR1_SPI3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPB1RSTR1_SPI2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1RSTR1_SPI2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1RSTR1_TIM7RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM7RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1RSTR1_TIM6RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM6RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1RSTR1_TIM5RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM5RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAPB1RSTR1_TIM4RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM4RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB1RSTR1_TIM3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR1.Reg, volatile.LoadUint32(&o.APB1RSTR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1RSTR1_TIM3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR1.Reg) & 0x2) >> 1
}

// RCC.APB1RSTR2: APB1 peripheral reset register 2
func (o *RCC_Type) SetAPB1RSTR2_LPUART1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1RSTR2_LPUART1RST() uint32 {
	return volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1RSTR2_I2C4RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1RSTR2_I2C4RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1RSTR2_LPTIM2RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1RSTR2_LPTIM2RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1RSTR2_LPTIM3RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB1RSTR2_LPTIM3RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB1RSTR2_FDCAN1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAPB1RSTR2_FDCAN1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAPB1RSTR2_USBFSRST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1RSTR2_USBFSRST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1RSTR2_UCPD1RST(value uint32) {
	volatile.StoreUint32(&o.APB1RSTR2.Reg, volatile.LoadUint32(&o.APB1RSTR2.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1RSTR2_UCPD1RST() uint32 {
	return (volatile.LoadUint32(&o.APB1RSTR2.Reg) & 0x800000) >> 23
}

// RCC.APB2RSTR: APB2 peripheral reset register
func (o *RCC_Type) SetAPB2RSTR_SYSCFGRST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB2RSTR_SYSCFGRST() uint32 {
	return volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x1
}
func (o *RCC_Type) SetAPB2RSTR_TIM1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB2RSTR_TIM1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB2RSTR_SPI1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB2RSTR_SPI1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB2RSTR_TIM8RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB2RSTR_TIM8RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB2RSTR_USART1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB2RSTR_USART1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB2RSTR_TIM15RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPB2RSTR_TIM15RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPB2RSTR_TIM16RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB2RSTR_TIM16RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB2RSTR_TIM17RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB2RSTR_TIM17RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB2RSTR_SAI1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB2RSTR_SAI1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB2RSTR_SAI2RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB2RSTR_SAI2RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB2RSTR_DFSDM1RST(value uint32) {
	volatile.StoreUint32(&o.APB2RSTR.Reg, volatile.LoadUint32(&o.APB2RSTR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB2RSTR_DFSDM1RST() uint32 {
	return (volatile.LoadUint32(&o.APB2RSTR.Reg) & 0x1000000) >> 24
}

// RCC.AHB1ENR: AHB1 peripheral clock enable register
func (o *RCC_Type) SetAHB1ENR_DMA1EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB1ENR_DMA1EN() uint32 {
	return volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB1ENR_DMA2EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB1ENR_DMA2EN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB1ENR_DMAMUX1EN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB1ENR_DMAMUX1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB1ENR_FLASHEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB1ENR_FLASHEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB1ENR_CRCEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB1ENR_CRCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB1ENR_TSCEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB1ENR_TSCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB1ENR_GTZCEN(value uint32) {
	volatile.StoreUint32(&o.AHB1ENR.Reg, volatile.LoadUint32(&o.AHB1ENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB1ENR_GTZCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1ENR.Reg) & 0x400000) >> 22
}

// RCC.AHB2ENR: AHB2 peripheral clock enable register
func (o *RCC_Type) SetAHB2ENR_GPIOAEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2ENR_GPIOAEN() uint32 {
	return volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2ENR_GPIOBEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB2ENR_GPIOBEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB2ENR_GPIOCEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB2ENR_GPIOCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB2ENR_GPIODEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB2ENR_GPIODEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB2ENR_GPIOEEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2ENR_GPIOEEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2ENR_GPIOFEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB2ENR_GPIOFEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB2ENR_GPIOGEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB2ENR_GPIOGEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB2ENR_GPIOHEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAHB2ENR_GPIOHEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAHB2ENR_ADCEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAHB2ENR_ADCEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAHB2ENR_AESEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB2ENR_AESEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB2ENR_HASHEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB2ENR_HASHEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB2ENR_RNGEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB2ENR_RNGEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB2ENR_PKAEN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB2ENR_PKAEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB2ENR_OTFDEC1EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB2ENR_OTFDEC1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB2ENR_SDMMC1EN(value uint32) {
	volatile.StoreUint32(&o.AHB2ENR.Reg, volatile.LoadUint32(&o.AHB2ENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB2ENR_SDMMC1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB2ENR.Reg) & 0x400000) >> 22
}

// RCC.AHB3ENR: AHB3 peripheral clock enable register
func (o *RCC_Type) SetAHB3ENR_FMCEN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB3ENR_FMCEN() uint32 {
	return volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB3ENR_OSPI1EN(value uint32) {
	volatile.StoreUint32(&o.AHB3ENR.Reg, volatile.LoadUint32(&o.AHB3ENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB3ENR_OSPI1EN() uint32 {
	return (volatile.LoadUint32(&o.AHB3ENR.Reg) & 0x100) >> 8
}

// RCC.APB1ENR1: APB1ENR1
func (o *RCC_Type) SetAPB1ENR1_TIM2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1ENR1_TIM2EN() uint32 {
	return volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1ENR1_TIM3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1ENR1_TIM3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1ENR1_TIM4EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB1ENR1_TIM4EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB1ENR1_TIM5EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAPB1ENR1_TIM5EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAPB1ENR1_TIM6EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1ENR1_TIM6EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1ENR1_TIM7EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1ENR1_TIM7EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1ENR1_RTCAPBEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAPB1ENR1_RTCAPBEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAPB1ENR1_WWDGEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB1ENR1_WWDGEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB1ENR1_SPI2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1ENR1_SPI2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1ENR1_SP3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPB1ENR1_SP3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPB1ENR1_USART2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB1ENR1_USART2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB1ENR1_USART3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB1ENR1_USART3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB1ENR1_UART4EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAPB1ENR1_UART4EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAPB1ENR1_UART5EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB1ENR1_UART5EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB1ENR1_I2C1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1ENR1_I2C1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1ENR1_I2C2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB1ENR1_I2C2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB1ENR1_I2C3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1ENR1_I2C3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAPB1ENR1_CRSEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB1ENR1_CRSEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB1ENR1_PWREN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAPB1ENR1_PWREN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAPB1ENR1_DAC1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetAPB1ENR1_DAC1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetAPB1ENR1_OPAMPEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAPB1ENR1_OPAMPEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAPB1ENR1_LPTIM1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR1.Reg, volatile.LoadUint32(&o.APB1ENR1.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAPB1ENR1_LPTIM1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR1.Reg) & 0x80000000) >> 31
}

// RCC.APB1ENR2: APB1 peripheral clock enable register 2
func (o *RCC_Type) SetAPB1ENR2_LPUART1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1ENR2_LPUART1EN() uint32 {
	return volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1ENR2_I2C4EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1ENR2_I2C4EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1ENR2_LPTIM2EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1ENR2_LPTIM2EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1ENR2_LPTIM3EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB1ENR2_LPTIM3EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB1ENR2_FDCAN1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAPB1ENR2_FDCAN1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAPB1ENR2_USBFSEN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1ENR2_USBFSEN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1ENR2_UCPD1EN(value uint32) {
	volatile.StoreUint32(&o.APB1ENR2.Reg, volatile.LoadUint32(&o.APB1ENR2.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1ENR2_UCPD1EN() uint32 {
	return (volatile.LoadUint32(&o.APB1ENR2.Reg) & 0x800000) >> 23
}

// RCC.APB2ENR: APB2ENR
func (o *RCC_Type) SetAPB2ENR_SYSCFGEN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB2ENR_SYSCFGEN() uint32 {
	return volatile.LoadUint32(&o.APB2ENR.Reg) & 0x1
}
func (o *RCC_Type) SetAPB2ENR_TIM1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB2ENR_TIM1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB2ENR_SPI1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB2ENR_SPI1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB2ENR_TIM8EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB2ENR_TIM8EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB2ENR_USART1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB2ENR_USART1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB2ENR_TIM15EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPB2ENR_TIM15EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPB2ENR_TIM16EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB2ENR_TIM16EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB2ENR_TIM17EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB2ENR_TIM17EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB2ENR_SAI1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB2ENR_SAI1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB2ENR_SAI2EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB2ENR_SAI2EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB2ENR_DFSDM1EN(value uint32) {
	volatile.StoreUint32(&o.APB2ENR.Reg, volatile.LoadUint32(&o.APB2ENR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB2ENR_DFSDM1EN() uint32 {
	return (volatile.LoadUint32(&o.APB2ENR.Reg) & 0x1000000) >> 24
}

// RCC.AHB1SMENR: AHB1 peripheral clocks enable in Sleep and Stop modes register
func (o *RCC_Type) SetAHB1SMENR_DMA1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB1SMENR_DMA1SMEN() uint32 {
	return volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB1SMENR_DMA2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB1SMENR_DMA2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB1SMENR_DMAMUX1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB1SMENR_DMAMUX1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB1SMENR_FLASHSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB1SMENR_FLASHSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB1SMENR_SRAM1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB1SMENR_SRAM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB1SMENR_CRCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB1SMENR_CRCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB1SMENR_TSCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB1SMENR_TSCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB1SMENR_GTZCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB1SMENR_GTZCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAHB1SMENR_ICACHESMEN(value uint32) {
	volatile.StoreUint32(&o.AHB1SMENR.Reg, volatile.LoadUint32(&o.AHB1SMENR.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAHB1SMENR_ICACHESMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB1SMENR.Reg) & 0x800000) >> 23
}

// RCC.AHB2SMENR: AHB2 peripheral clocks enable in Sleep and Stop modes register
func (o *RCC_Type) SetAHB2SMENR_GPIOASMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2SMENR_GPIOASMEN() uint32 {
	return volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB2SMENR_GPIOBSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB2SMENR_GPIOBSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB2SMENR_GPIOCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB2SMENR_GPIOCSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB2SMENR_GPIODSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB2SMENR_GPIODSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB2SMENR_GPIOESMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2SMENR_GPIOESMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2SMENR_GPIOFSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB2SMENR_GPIOFSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB2SMENR_GPIOGSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB2SMENR_GPIOGSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB2SMENR_GPIOHSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAHB2SMENR_GPIOHSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAHB2SMENR_SRAM2SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB2SMENR_SRAM2SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB2SMENR_ADCFSSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAHB2SMENR_ADCFSSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAHB2SMENR_AESSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB2SMENR_AESSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB2SMENR_HASHSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAHB2SMENR_HASHSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAHB2SMENR_RNGSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAHB2SMENR_RNGSMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAHB2SMENR_PKASMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAHB2SMENR_PKASMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAHB2SMENR_OTFDEC1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB2SMENR_OTFDEC1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB2SMENR_SDMMC1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB2SMENR.Reg, volatile.LoadUint32(&o.AHB2SMENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB2SMENR_SDMMC1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB2SMENR.Reg) & 0x400000) >> 22
}

// RCC.AHB3SMENR: AHB3 peripheral clocks enable in Sleep and Stop modes register
func (o *RCC_Type) SetAHB3SMENR_FMCSMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB3SMENR_FMCSMEN() uint32 {
	return volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x1
}
func (o *RCC_Type) SetAHB3SMENR_OSPI1SMEN(value uint32) {
	volatile.StoreUint32(&o.AHB3SMENR.Reg, volatile.LoadUint32(&o.AHB3SMENR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB3SMENR_OSPI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.AHB3SMENR.Reg) & 0x100) >> 8
}

// RCC.APB1SMENR1: APB1SMENR1
func (o *RCC_Type) SetAPB1SMENR1_TIM2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM2SMEN() uint32 {
	return volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1SMENR1_TIM3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1SMENR1_TIM4SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM4SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB1SMENR1_TIM5SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM5SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAPB1SMENR1_TIM6SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM6SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1SMENR1_TIM7SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1SMENR1_TIM7SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1SMENR1_RTCAPBSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAPB1SMENR1_RTCAPBSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAPB1SMENR1_WWDGSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB1SMENR1_WWDGSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB1SMENR1_SPI2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1SMENR1_SPI2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1SMENR1_SP3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPB1SMENR1_SP3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPB1SMENR1_USART2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB1SMENR1_USART2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB1SMENR1_USART3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB1SMENR1_USART3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB1SMENR1_UART4SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAPB1SMENR1_UART4SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAPB1SMENR1_UART5SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB1SMENR1_UART5SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB1SMENR1_I2C1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1SMENR1_I2C1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1SMENR1_I2C2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB1SMENR1_I2C2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB1SMENR1_I2C3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1SMENR1_I2C3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAPB1SMENR1_CRSSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB1SMENR1_CRSSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB1SMENR1_PWRSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAPB1SMENR1_PWRSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAPB1SMENR1_DAC1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetAPB1SMENR1_DAC1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetAPB1SMENR1_OPAMPSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAPB1SMENR1_OPAMPSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAPB1SMENR1_LPTIM1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR1.Reg, volatile.LoadUint32(&o.APB1SMENR1.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAPB1SMENR1_LPTIM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR1.Reg) & 0x80000000) >> 31
}

// RCC.APB1SMENR2: APB1 peripheral clocks enable in Sleep and Stop modes register 2
func (o *RCC_Type) SetAPB1SMENR2_LPUART1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1SMENR2_LPUART1SMEN() uint32 {
	return volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x1
}
func (o *RCC_Type) SetAPB1SMENR2_I2C4SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1SMENR2_I2C4SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1SMENR2_LPTIM2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1SMENR2_LPTIM2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1SMENR2_LPTIM3SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB1SMENR2_LPTIM3SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB1SMENR2_FDCAN1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAPB1SMENR2_FDCAN1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAPB1SMENR2_USBFSSMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1SMENR2_USBFSSMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1SMENR2_UCPD1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB1SMENR2.Reg, volatile.LoadUint32(&o.APB1SMENR2.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1SMENR2_UCPD1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB1SMENR2.Reg) & 0x800000) >> 23
}

// RCC.APB2SMENR: APB2SMENR
func (o *RCC_Type) SetAPB2SMENR_SYSCFGSMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB2SMENR_SYSCFGSMEN() uint32 {
	return volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x1
}
func (o *RCC_Type) SetAPB2SMENR_TIM1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB2SMENR_TIM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB2SMENR_SPI1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB2SMENR_SPI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB2SMENR_TIM8SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB2SMENR_TIM8SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB2SMENR_USART1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB2SMENR_USART1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB2SMENR_TIM15SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPB2SMENR_TIM15SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPB2SMENR_TIM16SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB2SMENR_TIM16SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB2SMENR_TIM17SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB2SMENR_TIM17SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB2SMENR_SAI1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB2SMENR_SAI1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB2SMENR_SAI2SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB2SMENR_SAI2SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB2SMENR_DFSDM1SMEN(value uint32) {
	volatile.StoreUint32(&o.APB2SMENR.Reg, volatile.LoadUint32(&o.APB2SMENR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB2SMENR_DFSDM1SMEN() uint32 {
	return (volatile.LoadUint32(&o.APB2SMENR.Reg) & 0x1000000) >> 24
}

// RCC.CCIPR1: CCIPR1
func (o *RCC_Type) SetCCIPR1_ADCSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x30000000)|value<<28)
}
func (o *RCC_Type) GetCCIPR1_ADCSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x30000000) >> 28
}
func (o *RCC_Type) SetCCIPR1_CLK48MSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc000000)|value<<26)
}
func (o *RCC_Type) GetCCIPR1_CLK48MSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc000000) >> 26
}
func (o *RCC_Type) SetCCIPR1_FDCANSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x3000000)|value<<24)
}
func (o *RCC_Type) GetCCIPR1_FDCANSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x3000000) >> 24
}
func (o *RCC_Type) SetCCIPR1_LPTIM3SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc00000)|value<<22)
}
func (o *RCC_Type) GetCCIPR1_LPTIM3SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc00000) >> 22
}
func (o *RCC_Type) SetCCIPR1_LPTIM2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x300000)|value<<20)
}
func (o *RCC_Type) GetCCIPR1_LPTIM2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x300000) >> 20
}
func (o *RCC_Type) SetCCIPR1_LPTIM1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc0000)|value<<18)
}
func (o *RCC_Type) GetCCIPR1_LPTIM1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc0000) >> 18
}
func (o *RCC_Type) SetCCIPR1_I2C3SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x30000)|value<<16)
}
func (o *RCC_Type) GetCCIPR1_I2C3SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x30000) >> 16
}
func (o *RCC_Type) SetCCIPR1_I2C2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc000)|value<<14)
}
func (o *RCC_Type) GetCCIPR1_I2C2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc000) >> 14
}
func (o *RCC_Type) SetCCIPR1_I2C1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x3000)|value<<12)
}
func (o *RCC_Type) GetCCIPR1_I2C1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x3000) >> 12
}
func (o *RCC_Type) SetCCIPR1_LPUART1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc00)|value<<10)
}
func (o *RCC_Type) GetCCIPR1_LPUART1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc00) >> 10
}
func (o *RCC_Type) SetCCIPR1_UART5SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x300)|value<<8)
}
func (o *RCC_Type) GetCCIPR1_UART5SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x300) >> 8
}
func (o *RCC_Type) SetCCIPR1_UART4SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc0)|value<<6)
}
func (o *RCC_Type) GetCCIPR1_UART4SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc0) >> 6
}
func (o *RCC_Type) SetCCIPR1_USART3SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x30)|value<<4)
}
func (o *RCC_Type) GetCCIPR1_USART3SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0x30) >> 4
}
func (o *RCC_Type) SetCCIPR1_USART2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0xc)|value<<2)
}
func (o *RCC_Type) GetCCIPR1_USART2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR1.Reg) & 0xc) >> 2
}
func (o *RCC_Type) SetCCIPR1_USART1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR1.Reg, volatile.LoadUint32(&o.CCIPR1.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetCCIPR1_USART1SEL() uint32 {
	return volatile.LoadUint32(&o.CCIPR1.Reg) & 0x3
}

// RCC.BDCR: BDCR
func (o *RCC_Type) SetBDCR_LSCOSEL(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetBDCR_LSCOSEL() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetBDCR_LSCOEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetBDCR_LSCOEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetBDCR_BDRST(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetBDCR_BDRST() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetBDCR_RTCEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetBDCR_RTCEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetBDCR_LSESYSRDY(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetBDCR_LSESYSRDY() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetBDCR_RTCSEL(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x300)|value<<8)
}
func (o *RCC_Type) GetBDCR_RTCSEL() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x300) >> 8
}
func (o *RCC_Type) SetBDCR_LSESYSEN(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetBDCR_LSESYSEN() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetBDCR_LSECSSD(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetBDCR_LSECSSD() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetBDCR_LSECSSON(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetBDCR_LSECSSON() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetBDCR_LSEDRV(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x18)|value<<3)
}
func (o *RCC_Type) GetBDCR_LSEDRV() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x18) >> 3
}
func (o *RCC_Type) SetBDCR_LSEBYP(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetBDCR_LSEBYP() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetBDCR_LSERDY(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetBDCR_LSERDY() uint32 {
	return (volatile.LoadUint32(&o.BDCR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetBDCR_LSEON(value uint32) {
	volatile.StoreUint32(&o.BDCR.Reg, volatile.LoadUint32(&o.BDCR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetBDCR_LSEON() uint32 {
	return volatile.LoadUint32(&o.BDCR.Reg) & 0x1
}

// RCC.CSR: CSR
func (o *RCC_Type) SetCSR_OBLRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2000000)|value<<25)
}
func (o *RCC_Type) GetCSR_OBLRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2000000) >> 25
}
func (o *RCC_Type) SetCSR_LPWRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetCSR_LPWRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x80000000) >> 31
}
func (o *RCC_Type) SetCSR_WWDGRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetCSR_WWDGRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetCSR_IWWDGRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetCSR_IWWDGRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetCSR_SFTRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetCSR_SFTRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetCSR_BORRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8000000)|value<<27)
}
func (o *RCC_Type) GetCSR_BORRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8000000) >> 27
}
func (o *RCC_Type) SetCSR_PINRSTF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4000000)|value<<26)
}
func (o *RCC_Type) GetCSR_PINRSTF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4000000) >> 26
}
func (o *RCC_Type) SetCSR_RMVF(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetCSR_RMVF() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetCSR_MSISRANGE(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0xf00)|value<<8)
}
func (o *RCC_Type) GetCSR_MSISRANGE() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0xf00) >> 8
}
func (o *RCC_Type) SetCSR_LSIPREDIV(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetCSR_LSIPREDIV() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetCSR_LSIRDY(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCSR_LSIRDY() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCSR_LSION(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCSR_LSION() uint32 {
	return volatile.LoadUint32(&o.CSR.Reg) & 0x1
}

// RCC.CRRCR: Clock recovery RC register
func (o *RCC_Type) SetCRRCR_HSI48ON(value uint32) {
	volatile.StoreUint32(&o.CRRCR.Reg, volatile.LoadUint32(&o.CRRCR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetCRRCR_HSI48ON() uint32 {
	return volatile.LoadUint32(&o.CRRCR.Reg) & 0x1
}
func (o *RCC_Type) SetCRRCR_HSI48RDY(value uint32) {
	volatile.StoreUint32(&o.CRRCR.Reg, volatile.LoadUint32(&o.CRRCR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetCRRCR_HSI48RDY() uint32 {
	return (volatile.LoadUint32(&o.CRRCR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetCRRCR_HSI48CAL(value uint32) {
	volatile.StoreUint32(&o.CRRCR.Reg, volatile.LoadUint32(&o.CRRCR.Reg)&^(0xff80)|value<<7)
}
func (o *RCC_Type) GetCRRCR_HSI48CAL() uint32 {
	return (volatile.LoadUint32(&o.CRRCR.Reg) & 0xff80) >> 7
}

// RCC.CCIPR2: Peripherals independent clock configuration register
func (o *RCC_Type) SetCCIPR2_I2C4SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x3)|value)
}
func (o *RCC_Type) GetCCIPR2_I2C4SEL() uint32 {
	return volatile.LoadUint32(&o.CCIPR2.Reg) & 0x3
}
func (o *RCC_Type) SetCCIPR2_DFSDMSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetCCIPR2_DFSDMSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetCCIPR2_ADFSDMSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x18)|value<<3)
}
func (o *RCC_Type) GetCCIPR2_ADFSDMSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x18) >> 3
}
func (o *RCC_Type) SetCCIPR2_SAI1SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0xe0)|value<<5)
}
func (o *RCC_Type) GetCCIPR2_SAI1SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0xe0) >> 5
}
func (o *RCC_Type) SetCCIPR2_SAI2SEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x700)|value<<8)
}
func (o *RCC_Type) GetCCIPR2_SAI2SEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x700) >> 8
}
func (o *RCC_Type) SetCCIPR2_SDMMCSEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetCCIPR2_SDMMCSEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetCCIPR2_OSPISEL(value uint32) {
	volatile.StoreUint32(&o.CCIPR2.Reg, volatile.LoadUint32(&o.CCIPR2.Reg)&^(0x300000)|value<<20)
}
func (o *RCC_Type) GetCCIPR2_OSPISEL() uint32 {
	return (volatile.LoadUint32(&o.CCIPR2.Reg) & 0x300000) >> 20
}

// RCC.SECCFGR: RCC secure configuration register
func (o *RCC_Type) SetSECCFGR_HSISEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetSECCFGR_HSISEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}
func (o *RCC_Type) SetSECCFGR_HSESEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetSECCFGR_HSESEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetSECCFGR_MSISEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetSECCFGR_MSISEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetSECCFGR_LSISEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetSECCFGR_LSISEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetSECCFGR_LSESEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetSECCFGR_LSESEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetSECCFGR_SYSCLKSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetSECCFGR_SYSCLKSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetSECCFGR_PRESCSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetSECCFGR_PRESCSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetSECCFGR_PLLSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetSECCFGR_PLLSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetSECCFGR_PLLSAI1SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetSECCFGR_PLLSAI1SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetSECCFGR_PLLSAI2SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetSECCFGR_PLLSAI2SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetSECCFGR_CLK48MSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetSECCFGR_CLK48MSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetSECCFGR_HSI48SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetSECCFGR_HSI48SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetSECCFGR_RMVFSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetSECCFGR_RMVFSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1000) >> 12
}

// RCC.SECSR: RCC secure status register
func (o *RCC_Type) SetSECSR_RMVFSECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetSECSR_RMVFSECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetSECSR_HSI48SECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetSECSR_HSI48SECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetSECSR_CLK48MSECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetSECSR_CLK48MSECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetSECSR_PLLSAI2SECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetSECSR_PLLSAI2SECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetSECSR_PLLSAI1SECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetSECSR_PLLSAI1SECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetSECSR_PLLSECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetSECSR_PLLSECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetSECSR_PRESCSECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetSECSR_PRESCSECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetSECSR_SYSCLKSECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetSECSR_SYSCLKSECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetSECSR_LSESECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetSECSR_LSESECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetSECSR_LSISECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetSECSR_LSISECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetSECSR_MSISECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetSECSR_MSISECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetSECSR_HSESECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetSECSR_HSESECF() uint32 {
	return (volatile.LoadUint32(&o.SECSR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetSECSR_HSISECF(value uint32) {
	volatile.StoreUint32(&o.SECSR.Reg, volatile.LoadUint32(&o.SECSR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetSECSR_HSISECF() uint32 {
	return volatile.LoadUint32(&o.SECSR.Reg) & 0x1
}

// RCC.AHB1SECSR: RCC AHB1 security status register
func (o *RCC_Type) SetAHB1SECSR_ICACHESECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAHB1SECSR_ICACHESECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAHB1SECSR_GTZCSECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB1SECSR_GTZCSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAHB1SECSR_TSCSECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAHB1SECSR_TSCSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAHB1SECSR_CRCSECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAHB1SECSR_CRCSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAHB1SECSR_SRAM1SECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB1SECSR_SRAM1SECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB1SECSR_FLASHSECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB1SECSR_FLASHSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB1SECSR_DMAMUX1SECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB1SECSR_DMAMUX1SECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB1SECSR_DMA2SECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB1SECSR_DMA2SECF() uint32 {
	return (volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB1SECSR_DMA1SECF(value uint32) {
	volatile.StoreUint32(&o.AHB1SECSR.Reg, volatile.LoadUint32(&o.AHB1SECSR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB1SECSR_DMA1SECF() uint32 {
	return volatile.LoadUint32(&o.AHB1SECSR.Reg) & 0x1
}

// RCC.AHB2SECSR: RCC AHB2 security status register
func (o *RCC_Type) SetAHB2SECSR_SDMMC1SECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAHB2SECSR_SDMMC1SECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAHB2SECSR_OTFDEC1SECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAHB2SECSR_OTFDEC1SECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAHB2SECSR_SRAM2SECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAHB2SECSR_SRAM2SECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAHB2SECSR_GPIOHSECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x80)|value<<7)
}
func (o *RCC_Type) GetAHB2SECSR_GPIOHSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x80) >> 7
}
func (o *RCC_Type) SetAHB2SECSR_GPIOGSECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAHB2SECSR_GPIOGSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAHB2SECSR_GPIOFSECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAHB2SECSR_GPIOFSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAHB2SECSR_GPIOESECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAHB2SECSR_GPIOESECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAHB2SECSR_GPIODSECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAHB2SECSR_GPIODSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAHB2SECSR_GPIOCSECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAHB2SECSR_GPIOCSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAHB2SECSR_GPIOBSECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAHB2SECSR_GPIOBSECF() uint32 {
	return (volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAHB2SECSR_GPIOASECF(value uint32) {
	volatile.StoreUint32(&o.AHB2SECSR.Reg, volatile.LoadUint32(&o.AHB2SECSR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB2SECSR_GPIOASECF() uint32 {
	return volatile.LoadUint32(&o.AHB2SECSR.Reg) & 0x1
}

// RCC.AHB3SECSR: RCC AHB3 security status register
func (o *RCC_Type) SetAHB3SECSR_OSPI1SECF(value uint32) {
	volatile.StoreUint32(&o.AHB3SECSR.Reg, volatile.LoadUint32(&o.AHB3SECSR.Reg)&^(0x100)|value<<8)
}
func (o *RCC_Type) GetAHB3SECSR_OSPI1SECF() uint32 {
	return (volatile.LoadUint32(&o.AHB3SECSR.Reg) & 0x100) >> 8
}
func (o *RCC_Type) SetAHB3SECSR_FSMCSECF(value uint32) {
	volatile.StoreUint32(&o.AHB3SECSR.Reg, volatile.LoadUint32(&o.AHB3SECSR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAHB3SECSR_FSMCSECF() uint32 {
	return volatile.LoadUint32(&o.AHB3SECSR.Reg) & 0x1
}

// RCC.APB1SECSR1: RCC APB1 security status register 1
func (o *RCC_Type) SetAPB1SECSR1_LPTIM1SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x80000000)|value<<31)
}
func (o *RCC_Type) GetAPB1SECSR1_LPTIM1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x80000000) >> 31
}
func (o *RCC_Type) SetAPB1SECSR1_OPAMPSECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x40000000)|value<<30)
}
func (o *RCC_Type) GetAPB1SECSR1_OPAMPSECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x40000000) >> 30
}
func (o *RCC_Type) SetAPB1SECSR1_DACSECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x20000000)|value<<29)
}
func (o *RCC_Type) GetAPB1SECSR1_DACSECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x20000000) >> 29
}
func (o *RCC_Type) SetAPB1SECSR1_PWRSECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x10000000)|value<<28)
}
func (o *RCC_Type) GetAPB1SECSR1_PWRSECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x10000000) >> 28
}
func (o *RCC_Type) SetAPB1SECSR1_CRSSECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB1SECSR1_CRSSECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB1SECSR1_I2C3SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1SECSR1_I2C3SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAPB1SECSR1_I2C2SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB1SECSR1_I2C2SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB1SECSR1_I2C1SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1SECSR1_I2C1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1SECSR1_UART5SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x100000)|value<<20)
}
func (o *RCC_Type) GetAPB1SECSR1_UART5SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x100000) >> 20
}
func (o *RCC_Type) SetAPB1SECSR1_UART4SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x80000)|value<<19)
}
func (o *RCC_Type) GetAPB1SECSR1_UART4SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x80000) >> 19
}
func (o *RCC_Type) SetAPB1SECSR1_UART3SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB1SECSR1_UART3SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB1SECSR1_UART2SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB1SECSR1_UART2SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB1SECSR1_SPI3SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x8000)|value<<15)
}
func (o *RCC_Type) GetAPB1SECSR1_SPI3SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x8000) >> 15
}
func (o *RCC_Type) SetAPB1SECSR1_SPI2SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB1SECSR1_SPI2SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB1SECSR1_WWDGSECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB1SECSR1_WWDGSECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB1SECSR1_RTCAPBSECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x400)|value<<10)
}
func (o *RCC_Type) GetAPB1SECSR1_RTCAPBSECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x400) >> 10
}
func (o *RCC_Type) SetAPB1SECSR1_TIM7SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1SECSR1_TIM7SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1SECSR1_TIM6SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x10)|value<<4)
}
func (o *RCC_Type) GetAPB1SECSR1_TIM6SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x10) >> 4
}
func (o *RCC_Type) SetAPB1SECSR1_TIM5SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x8)|value<<3)
}
func (o *RCC_Type) GetAPB1SECSR1_TIM5SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x8) >> 3
}
func (o *RCC_Type) SetAPB1SECSR1_TIM4SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x4)|value<<2)
}
func (o *RCC_Type) GetAPB1SECSR1_TIM4SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x4) >> 2
}
func (o *RCC_Type) SetAPB1SECSR1_TIM3SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1SECSR1_TIM3SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1SECSR1_TIM2SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR1.Reg, volatile.LoadUint32(&o.APB1SECSR1.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1SECSR1_TIM2SECF() uint32 {
	return volatile.LoadUint32(&o.APB1SECSR1.Reg) & 0x1
}

// RCC.APB1SECSR2: RCC APB1 security status register 2
func (o *RCC_Type) SetAPB1SECSR2_UCPD1SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR2.Reg, volatile.LoadUint32(&o.APB1SECSR2.Reg)&^(0x800000)|value<<23)
}
func (o *RCC_Type) GetAPB1SECSR2_UCPD1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR2.Reg) & 0x800000) >> 23
}
func (o *RCC_Type) SetAPB1SECSR2_USBFSSECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR2.Reg, volatile.LoadUint32(&o.APB1SECSR2.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB1SECSR2_USBFSSECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR2.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB1SECSR2_FDCAN1SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR2.Reg, volatile.LoadUint32(&o.APB1SECSR2.Reg)&^(0x200)|value<<9)
}
func (o *RCC_Type) GetAPB1SECSR2_FDCAN1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR2.Reg) & 0x200) >> 9
}
func (o *RCC_Type) SetAPB1SECSR2_LPTIM3SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR2.Reg, volatile.LoadUint32(&o.APB1SECSR2.Reg)&^(0x40)|value<<6)
}
func (o *RCC_Type) GetAPB1SECSR2_LPTIM3SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR2.Reg) & 0x40) >> 6
}
func (o *RCC_Type) SetAPB1SECSR2_LPTIM2SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR2.Reg, volatile.LoadUint32(&o.APB1SECSR2.Reg)&^(0x20)|value<<5)
}
func (o *RCC_Type) GetAPB1SECSR2_LPTIM2SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR2.Reg) & 0x20) >> 5
}
func (o *RCC_Type) SetAPB1SECSR2_I2C4SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR2.Reg, volatile.LoadUint32(&o.APB1SECSR2.Reg)&^(0x2)|value<<1)
}
func (o *RCC_Type) GetAPB1SECSR2_I2C4SECF() uint32 {
	return (volatile.LoadUint32(&o.APB1SECSR2.Reg) & 0x2) >> 1
}
func (o *RCC_Type) SetAPB1SECSR2_LPUART1SECF(value uint32) {
	volatile.StoreUint32(&o.APB1SECSR2.Reg, volatile.LoadUint32(&o.APB1SECSR2.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB1SECSR2_LPUART1SECF() uint32 {
	return volatile.LoadUint32(&o.APB1SECSR2.Reg) & 0x1
}

// RCC.APB2SECSR: RCC APB2 security status register
func (o *RCC_Type) SetAPB2SECSR_DFSDM1SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x1000000)|value<<24)
}
func (o *RCC_Type) GetAPB2SECSR_DFSDM1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x1000000) >> 24
}
func (o *RCC_Type) SetAPB2SECSR_SAI2SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x400000)|value<<22)
}
func (o *RCC_Type) GetAPB2SECSR_SAI2SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x400000) >> 22
}
func (o *RCC_Type) SetAPB2SECSR_SAI1SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x200000)|value<<21)
}
func (o *RCC_Type) GetAPB2SECSR_SAI1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x200000) >> 21
}
func (o *RCC_Type) SetAPB2SECSR_TIM17SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x40000)|value<<18)
}
func (o *RCC_Type) GetAPB2SECSR_TIM17SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x40000) >> 18
}
func (o *RCC_Type) SetAPB2SECSR_TIM16SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x20000)|value<<17)
}
func (o *RCC_Type) GetAPB2SECSR_TIM16SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x20000) >> 17
}
func (o *RCC_Type) SetAPB2SECSR_TIM15SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x10000)|value<<16)
}
func (o *RCC_Type) GetAPB2SECSR_TIM15SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x10000) >> 16
}
func (o *RCC_Type) SetAPB2SECSR_USART1SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x4000)|value<<14)
}
func (o *RCC_Type) GetAPB2SECSR_USART1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x4000) >> 14
}
func (o *RCC_Type) SetAPB2SECSR_TIM8SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x2000)|value<<13)
}
func (o *RCC_Type) GetAPB2SECSR_TIM8SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x2000) >> 13
}
func (o *RCC_Type) SetAPB2SECSR_SPI1SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x1000)|value<<12)
}
func (o *RCC_Type) GetAPB2SECSR_SPI1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x1000) >> 12
}
func (o *RCC_Type) SetAPB2SECSR_TIM1SECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x800)|value<<11)
}
func (o *RCC_Type) GetAPB2SECSR_TIM1SECF() uint32 {
	return (volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x800) >> 11
}
func (o *RCC_Type) SetAPB2SECSR_SYSCFGSECF(value uint32) {
	volatile.StoreUint32(&o.APB2SECSR.Reg, volatile.LoadUint32(&o.APB2SECSR.Reg)&^(0x1)|value)
}
func (o *RCC_Type) GetAPB2SECSR_SYSCFGSECF() uint32 {
	return volatile.LoadUint32(&o.APB2SECSR.Reg) & 0x1
}

// RNG
type RNG_Type struct {
	CR   volatile.Register32 // 0x0
	SR   volatile.Register32 // 0x4
	DR   volatile.Register32 // 0x8
	_    [4]byte
	HTCR volatile.Register32 // 0x10
}

// RNG.CR: RNG control register
func (o *RNG_Type) SetCR_RNGEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *RNG_Type) GetCR_RNGEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *RNG_Type) SetCR_IE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RNG_Type) GetCR_IE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RNG_Type) SetCR_CED(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RNG_Type) GetCR_CED() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RNG_Type) SetCR_RNG_CONFIG3(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf00)|value<<8)
}
func (o *RNG_Type) GetCR_RNG_CONFIG3() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf00) >> 8
}
func (o *RNG_Type) SetCR_NISTC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000)|value<<12)
}
func (o *RNG_Type) GetCR_NISTC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000) >> 12
}
func (o *RNG_Type) SetCR_RNG_CONFIG2(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xe000)|value<<13)
}
func (o *RNG_Type) GetCR_RNG_CONFIG2() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xe000) >> 13
}
func (o *RNG_Type) SetCR_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf0000)|value<<16)
}
func (o *RNG_Type) GetCR_CLKDIV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf0000) >> 16
}
func (o *RNG_Type) SetCR_RNG_CONFIG1(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3f00000)|value<<20)
}
func (o *RNG_Type) GetCR_RNG_CONFIG1() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x3f00000) >> 20
}
func (o *RNG_Type) SetCR_CONDRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *RNG_Type) GetCR_CONDRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *RNG_Type) SetCR_CONFIGLOCK(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *RNG_Type) GetCR_CONFIGLOCK() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// RNG.SR: RNG status register
func (o *RNG_Type) SetSR_DRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *RNG_Type) GetSR_DRDY() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *RNG_Type) SetSR_CECS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *RNG_Type) GetSR_CECS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *RNG_Type) SetSR_SECS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RNG_Type) GetSR_SECS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RNG_Type) SetSR_CEIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *RNG_Type) GetSR_CEIS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *RNG_Type) SetSR_SEIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *RNG_Type) GetSR_SEIS() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}

// RNG.DR: The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.
func (o *RNG_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *RNG_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// RNG.HTCR: The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.
func (o *RNG_Type) SetHTCR(value uint32) {
	volatile.StoreUint32(&o.HTCR.Reg, value)
}
func (o *RNG_Type) GetHTCR() uint32 {
	return volatile.LoadUint32(&o.HTCR.Reg)
}

// Real-time clock
type RTC_Type struct {
	TR       volatile.Register32 // 0x0
	DR       volatile.Register32 // 0x4
	SSR      volatile.Register32 // 0x8
	ICSR     volatile.Register32 // 0xC
	PRER     volatile.Register32 // 0x10
	WUTR     volatile.Register32 // 0x14
	CR       volatile.Register32 // 0x18
	PRIVCR   volatile.Register32 // 0x1C
	SMCR     volatile.Register32 // 0x20
	WPR      volatile.Register32 // 0x24
	CALR     volatile.Register32 // 0x28
	SHIFTR   volatile.Register32 // 0x2C
	TSTR     volatile.Register32 // 0x30
	TSDR     volatile.Register32 // 0x34
	TSSSR    volatile.Register32 // 0x38
	_        [4]byte
	ALRMAR   volatile.Register32 // 0x40
	ALRMASSR volatile.Register32 // 0x44
	ALRMBR   volatile.Register32 // 0x48
	ALRMBSSR volatile.Register32 // 0x4C
	SR       volatile.Register32 // 0x50
	MISR     volatile.Register32 // 0x54
	SMISR    volatile.Register32 // 0x58
	SCR      volatile.Register32 // 0x5C
}

// RTC.TR: time register
func (o *RTC_Type) SetTR_PM(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetTR_PM() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetTR_HT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetTR_HT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetTR_HU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetTR_HU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetTR_MNT(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetTR_MNT() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetTR_MNU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetTR_MNU() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetTR_ST(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetTR_ST() uint32 {
	return (volatile.LoadUint32(&o.TR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetTR_SU(value uint32) {
	volatile.StoreUint32(&o.TR.Reg, volatile.LoadUint32(&o.TR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetTR_SU() uint32 {
	return volatile.LoadUint32(&o.TR.Reg) & 0xf
}

// RTC.DR: date register
func (o *RTC_Type) SetDR_YT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00000)|value<<20)
}
func (o *RTC_Type) GetDR_YT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00000) >> 20
}
func (o *RTC_Type) SetDR_YU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetDR_YU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetDR_WDU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xe000)|value<<13)
}
func (o *RTC_Type) GetDR_WDU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xe000) >> 13
}
func (o *RTC_Type) SetDR_MT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_Type) GetDR_MT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x1000) >> 12
}
func (o *RTC_Type) SetDR_MU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetDR_MU() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetDR_DT(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0x30)|value<<4)
}
func (o *RTC_Type) GetDR_DT() uint32 {
	return (volatile.LoadUint32(&o.DR.Reg) & 0x30) >> 4
}
func (o *RTC_Type) SetDR_DU(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetDR_DU() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xf
}

// RTC.SSR: RTC sub second register
func (o *RTC_Type) SetSSR_SS(value uint32) {
	volatile.StoreUint32(&o.SSR.Reg, volatile.LoadUint32(&o.SSR.Reg)&^(0xffff)|value)
}
func (o *RTC_Type) GetSSR_SS() uint32 {
	return volatile.LoadUint32(&o.SSR.Reg) & 0xffff
}

// RTC.ICSR: RTC initialization control and status register
func (o *RTC_Type) SetICSR_ALRAWF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetICSR_ALRAWF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetICSR_ALRBWF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetICSR_ALRBWF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetICSR_WUTWF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetICSR_WUTWF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetICSR_SHPF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetICSR_SHPF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetICSR_INITS(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetICSR_INITS() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetICSR_RSF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetICSR_RSF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetICSR_INITF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetICSR_INITF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetICSR_INIT(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetICSR_INIT() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetICSR_RECALPF(value uint32) {
	volatile.StoreUint32(&o.ICSR.Reg, volatile.LoadUint32(&o.ICSR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetICSR_RECALPF() uint32 {
	return (volatile.LoadUint32(&o.ICSR.Reg) & 0x10000) >> 16
}

// RTC.PRER: prescaler register
func (o *RTC_Type) SetPRER_PREDIV_A(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7f0000)|value<<16)
}
func (o *RTC_Type) GetPRER_PREDIV_A() uint32 {
	return (volatile.LoadUint32(&o.PRER.Reg) & 0x7f0000) >> 16
}
func (o *RTC_Type) SetPRER_PREDIV_S(value uint32) {
	volatile.StoreUint32(&o.PRER.Reg, volatile.LoadUint32(&o.PRER.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetPRER_PREDIV_S() uint32 {
	return volatile.LoadUint32(&o.PRER.Reg) & 0x7fff
}

// RTC.WUTR: wakeup timer register
func (o *RTC_Type) SetWUTR_WUT(value uint32) {
	volatile.StoreUint32(&o.WUTR.Reg, volatile.LoadUint32(&o.WUTR.Reg)&^(0xffff)|value)
}
func (o *RTC_Type) GetWUTR_WUT() uint32 {
	return volatile.LoadUint32(&o.WUTR.Reg) & 0xffff
}
func (o *RTC_Type) SetWUTR_WUTOCLR(value uint32) {
	volatile.StoreUint32(&o.WUTR.Reg, volatile.LoadUint32(&o.WUTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *RTC_Type) GetWUTR_WUTOCLR() uint32 {
	return (volatile.LoadUint32(&o.WUTR.Reg) & 0xffff0000) >> 16
}

// RTC.CR: RTC control register
func (o *RTC_Type) SetCR_WUCKSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7)|value)
}
func (o *RTC_Type) GetCR_WUCKSEL() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x7
}
func (o *RTC_Type) SetCR_TSEDGE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetCR_TSEDGE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetCR_REFCKON(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetCR_REFCKON() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetCR_BYPSHAD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetCR_BYPSHAD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *RTC_Type) SetCR_FMT(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *RTC_Type) GetCR_FMT() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *RTC_Type) SetCR_ALRAE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *RTC_Type) GetCR_ALRAE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *RTC_Type) SetCR_ALRBE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetCR_ALRBE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetCR_WUTE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x400)|value<<10)
}
func (o *RTC_Type) GetCR_WUTE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x400) >> 10
}
func (o *RTC_Type) SetCR_TSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800)|value<<11)
}
func (o *RTC_Type) GetCR_TSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800) >> 11
}
func (o *RTC_Type) SetCR_ALRAIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetCR_ALRAIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetCR_ALRBIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCR_ALRBIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCR_WUTIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCR_WUTIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCR_TSIE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetCR_TSIE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetCR_ADD1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *RTC_Type) GetCR_ADD1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *RTC_Type) SetCR_SUB1H(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *RTC_Type) GetCR_SUB1H() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *RTC_Type) SetCR_BKP(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *RTC_Type) GetCR_BKP() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *RTC_Type) SetCR_COSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000)|value<<19)
}
func (o *RTC_Type) GetCR_COSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000) >> 19
}
func (o *RTC_Type) SetCR_POL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *RTC_Type) GetCR_POL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *RTC_Type) SetCR_OSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x600000)|value<<21)
}
func (o *RTC_Type) GetCR_OSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x600000) >> 21
}
func (o *RTC_Type) SetCR_COE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetCR_COE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetCR_ITSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1000000)|value<<24)
}
func (o *RTC_Type) GetCR_ITSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x1000000) >> 24
}
func (o *RTC_Type) SetCR_TAMPTS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2000000)|value<<25)
}
func (o *RTC_Type) GetCR_TAMPTS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2000000) >> 25
}
func (o *RTC_Type) SetCR_TAMPOE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4000000)|value<<26)
}
func (o *RTC_Type) GetCR_TAMPOE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4000000) >> 26
}
func (o *RTC_Type) SetCR_TAMPALRM_PU(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000000)|value<<29)
}
func (o *RTC_Type) GetCR_TAMPALRM_PU() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000000) >> 29
}
func (o *RTC_Type) SetCR_TAMPALRM_TYPE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetCR_TAMPALRM_TYPE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetCR_OUT2EN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetCR_OUT2EN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80000000) >> 31
}

// RTC.PRIVCR: RTC privilege mode control register
func (o *RTC_Type) SetPRIVCR_PRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetPRIVCR_PRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetPRIVCR_INITPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetPRIVCR_INITPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetPRIVCR_CALPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetPRIVCR_CALPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetPRIVCR_TSPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetPRIVCR_TSPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetPRIVCR_WUTPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetPRIVCR_WUTPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetPRIVCR_ALRBPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetPRIVCR_ALRBPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetPRIVCR_ALRAPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetPRIVCR_ALRAPRIV() uint32 {
	return volatile.LoadUint32(&o.PRIVCR.Reg) & 0x1
}

// RTC.SMCR: RTC secure mode control register
func (o *RTC_Type) SetSMCR_DECPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetSMCR_DECPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetSMCR_INITDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetSMCR_INITDPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetSMCR_CALDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetSMCR_CALDPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetSMCR_TSDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSMCR_TSDPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSMCR_WUTDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSMCR_WUTDPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSMCR_ALRBDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSMCR_ALRBDPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSMCR_ALRADPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetSMCR_ALRADPROT() uint32 {
	return volatile.LoadUint32(&o.SMCR.Reg) & 0x1
}

// RTC.WPR: write protection register
func (o *RTC_Type) SetWPR_KEY(value uint32) {
	volatile.StoreUint32(&o.WPR.Reg, volatile.LoadUint32(&o.WPR.Reg)&^(0xff)|value)
}
func (o *RTC_Type) GetWPR_KEY() uint32 {
	return volatile.LoadUint32(&o.WPR.Reg) & 0xff
}

// RTC.CALR: calibration register
func (o *RTC_Type) SetCALR_CALP(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetCALR_CALP() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetCALR_CALW8(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x4000)|value<<14)
}
func (o *RTC_Type) GetCALR_CALW8() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x4000) >> 14
}
func (o *RTC_Type) SetCALR_CALW16(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x2000)|value<<13)
}
func (o *RTC_Type) GetCALR_CALW16() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x2000) >> 13
}
func (o *RTC_Type) SetCALR_LPCAL(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x1000)|value<<12)
}
func (o *RTC_Type) GetCALR_LPCAL() uint32 {
	return (volatile.LoadUint32(&o.CALR.Reg) & 0x1000) >> 12
}
func (o *RTC_Type) SetCALR_CALM(value uint32) {
	volatile.StoreUint32(&o.CALR.Reg, volatile.LoadUint32(&o.CALR.Reg)&^(0x1ff)|value)
}
func (o *RTC_Type) GetCALR_CALM() uint32 {
	return volatile.LoadUint32(&o.CALR.Reg) & 0x1ff
}

// RTC.SHIFTR: shift control register
func (o *RTC_Type) SetSHIFTR_ADD1S(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetSHIFTR_ADD1S() uint32 {
	return (volatile.LoadUint32(&o.SHIFTR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetSHIFTR_SUBFS(value uint32) {
	volatile.StoreUint32(&o.SHIFTR.Reg, volatile.LoadUint32(&o.SHIFTR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetSHIFTR_SUBFS() uint32 {
	return volatile.LoadUint32(&o.SHIFTR.Reg) & 0x7fff
}

// RTC.ALRMAR: Alarm %s register
func (o *RTC_Type) SetALRMAR_MSK1(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetALRMAR_MSK1() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetALRMAR_MSK4(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMAR_MSK4() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetALRMAR_WDSEL(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetALRMAR_WDSEL() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetALRMAR_DT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x30000000)|value<<28)
}
func (o *RTC_Type) GetALRMAR_DT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x30000000) >> 28
}
func (o *RTC_Type) SetALRMAR_DU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMAR_DU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMAR_MSK3(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetALRMAR_MSK3() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetALRMAR_PM(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetALRMAR_PM() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetALRMAR_HT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetALRMAR_HT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetALRMAR_HU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetALRMAR_HU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetALRMAR_MSK2(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetALRMAR_MSK2() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetALRMAR_MNT(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetALRMAR_MNT() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetALRMAR_MNU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetALRMAR_MNU() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetALRMAR_ST(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetALRMAR_ST() uint32 {
	return (volatile.LoadUint32(&o.ALRMAR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetALRMAR_SU(value uint32) {
	volatile.StoreUint32(&o.ALRMAR.Reg, volatile.LoadUint32(&o.ALRMAR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetALRMAR_SU() uint32 {
	return volatile.LoadUint32(&o.ALRMAR.Reg) & 0xf
}

// RTC.ALRMASSR: Alarm %s sub-second register
func (o *RTC_Type) SetALRMASSR_MASKSS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMASSR_MASKSS() uint32 {
	return (volatile.LoadUint32(&o.ALRMASSR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMASSR_SS(value uint32) {
	volatile.StoreUint32(&o.ALRMASSR.Reg, volatile.LoadUint32(&o.ALRMASSR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetALRMASSR_SS() uint32 {
	return volatile.LoadUint32(&o.ALRMASSR.Reg) & 0x7fff
}

// RTC.ALRMBR: Alarm %s register
func (o *RTC_Type) SetALRMBR_MSK1(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x80)|value<<7)
}
func (o *RTC_Type) GetALRMBR_MSK1() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x80) >> 7
}
func (o *RTC_Type) SetALRMBR_MSK4(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x80000000)|value<<31)
}
func (o *RTC_Type) GetALRMBR_MSK4() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x80000000) >> 31
}
func (o *RTC_Type) SetALRMBR_WDSEL(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x40000000)|value<<30)
}
func (o *RTC_Type) GetALRMBR_WDSEL() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x40000000) >> 30
}
func (o *RTC_Type) SetALRMBR_DT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x30000000)|value<<28)
}
func (o *RTC_Type) GetALRMBR_DT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x30000000) >> 28
}
func (o *RTC_Type) SetALRMBR_DU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMBR_DU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMBR_MSK3(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x800000)|value<<23)
}
func (o *RTC_Type) GetALRMBR_MSK3() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x800000) >> 23
}
func (o *RTC_Type) SetALRMBR_PM(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x400000)|value<<22)
}
func (o *RTC_Type) GetALRMBR_PM() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x400000) >> 22
}
func (o *RTC_Type) SetALRMBR_HT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x300000)|value<<20)
}
func (o *RTC_Type) GetALRMBR_HT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x300000) >> 20
}
func (o *RTC_Type) SetALRMBR_HU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf0000)|value<<16)
}
func (o *RTC_Type) GetALRMBR_HU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf0000) >> 16
}
func (o *RTC_Type) SetALRMBR_MSK2(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x8000)|value<<15)
}
func (o *RTC_Type) GetALRMBR_MSK2() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x8000) >> 15
}
func (o *RTC_Type) SetALRMBR_MNT(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x7000)|value<<12)
}
func (o *RTC_Type) GetALRMBR_MNT() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x7000) >> 12
}
func (o *RTC_Type) SetALRMBR_MNU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf00)|value<<8)
}
func (o *RTC_Type) GetALRMBR_MNU() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf00) >> 8
}
func (o *RTC_Type) SetALRMBR_ST(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0x70)|value<<4)
}
func (o *RTC_Type) GetALRMBR_ST() uint32 {
	return (volatile.LoadUint32(&o.ALRMBR.Reg) & 0x70) >> 4
}
func (o *RTC_Type) SetALRMBR_SU(value uint32) {
	volatile.StoreUint32(&o.ALRMBR.Reg, volatile.LoadUint32(&o.ALRMBR.Reg)&^(0xf)|value)
}
func (o *RTC_Type) GetALRMBR_SU() uint32 {
	return volatile.LoadUint32(&o.ALRMBR.Reg) & 0xf
}

// RTC.ALRMBSSR: Alarm %s sub-second register
func (o *RTC_Type) SetALRMBSSR_MASKSS(value uint32) {
	volatile.StoreUint32(&o.ALRMBSSR.Reg, volatile.LoadUint32(&o.ALRMBSSR.Reg)&^(0xf000000)|value<<24)
}
func (o *RTC_Type) GetALRMBSSR_MASKSS() uint32 {
	return (volatile.LoadUint32(&o.ALRMBSSR.Reg) & 0xf000000) >> 24
}
func (o *RTC_Type) SetALRMBSSR_SS(value uint32) {
	volatile.StoreUint32(&o.ALRMBSSR.Reg, volatile.LoadUint32(&o.ALRMBSSR.Reg)&^(0x7fff)|value)
}
func (o *RTC_Type) GetALRMBSSR_SS() uint32 {
	return volatile.LoadUint32(&o.ALRMBSSR.Reg) & 0x7fff
}

// RTC.SR: RTC status register
func (o *RTC_Type) SetSR_ALRAF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSR_ALRAF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSR_ALRBF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSR_ALRBF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSR_WUTF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSR_WUTF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSR_TSF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSR_TSF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSR_TSOVF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSR_TSOVF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSR_ITSF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSR_ITSF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}

// RTC.MISR: RTC non-secure masked interrupt status register
func (o *RTC_Type) SetMISR_ALRAMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetMISR_ALRAMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetMISR_ALRBMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetMISR_ALRBMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetMISR_WUTMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetMISR_WUTMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetMISR_TSMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetMISR_TSMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetMISR_TSOVMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetMISR_TSOVMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetMISR_ITSMF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetMISR_ITSMF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20) >> 5
}

// RTC.SMISR: RTC secure masked interrupt status register
func (o *RTC_Type) SetSMISR_ALRAMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetSMISR_ALRAMF() uint32 {
	return volatile.LoadUint32(&o.SMISR.Reg) & 0x1
}
func (o *RTC_Type) SetSMISR_ALRBMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSMISR_ALRBMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSMISR_WUTMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSMISR_WUTMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSMISR_TSMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSMISR_TSMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSMISR_TSOVMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSMISR_TSOVMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSMISR_ITSMF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSMISR_ITSMF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x20) >> 5
}

// RTC.SCR: RTC status clear register
func (o *RTC_Type) SetSCR_CALRAF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *RTC_Type) GetSCR_CALRAF() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}
func (o *RTC_Type) SetSCR_CALRBF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *RTC_Type) GetSCR_CALRBF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *RTC_Type) SetSCR_CWUTF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *RTC_Type) GetSCR_CWUTF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *RTC_Type) SetSCR_CTSF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *RTC_Type) GetSCR_CTSF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *RTC_Type) SetSCR_CTSOVF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *RTC_Type) GetSCR_CTSOVF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *RTC_Type) SetSCR_CITSF(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *RTC_Type) GetSCR_CITSF() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20) >> 5
}

// Serial audio interface
type SAI_Type struct {
	GCR    volatile.Register32 // 0x0
	CH     [2]SAI_CH_Type      // 0x4
	PDMCR  volatile.Register32 // 0x44
	PDMDLY volatile.Register32 // 0x48
}

// SAI.GCR: Global configuration register
func (o *SAI_Type) SetGCR_SYNCIN(value uint32) {
	volatile.StoreUint32(&o.GCR.Reg, volatile.LoadUint32(&o.GCR.Reg)&^(0x3)|value)
}
func (o *SAI_Type) GetGCR_SYNCIN() uint32 {
	return volatile.LoadUint32(&o.GCR.Reg) & 0x3
}
func (o *SAI_Type) SetGCR_SYNCOUT(value uint32) {
	volatile.StoreUint32(&o.GCR.Reg, volatile.LoadUint32(&o.GCR.Reg)&^(0x30)|value<<4)
}
func (o *SAI_Type) GetGCR_SYNCOUT() uint32 {
	return (volatile.LoadUint32(&o.GCR.Reg) & 0x30) >> 4
}

// SAI.PDMCR: PDM control register
func (o *SAI_Type) SetPDMCR_PDMEN(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x1)|value)
}
func (o *SAI_Type) GetPDMCR_PDMEN() uint32 {
	return volatile.LoadUint32(&o.PDMCR.Reg) & 0x1
}
func (o *SAI_Type) SetPDMCR_MICNBR(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x30)|value<<4)
}
func (o *SAI_Type) GetPDMCR_MICNBR() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x30) >> 4
}
func (o *SAI_Type) SetPDMCR_CKEN1(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x200)|value<<9)
}
func (o *SAI_Type) GetPDMCR_CKEN1() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x200) >> 9
}
func (o *SAI_Type) SetPDMCR_CKEN2(value uint32) {
	volatile.StoreUint32(&o.PDMCR.Reg, volatile.LoadUint32(&o.PDMCR.Reg)&^(0x400)|value<<10)
}
func (o *SAI_Type) GetPDMCR_CKEN2() uint32 {
	return (volatile.LoadUint32(&o.PDMCR.Reg) & 0x400) >> 10
}

// SAI.PDMDLY: PDM delay register
func (o *SAI_Type) SetPDMDLY_DLYM1L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x700)|value<<8)
}
func (o *SAI_Type) GetPDMDLY_DLYM1L() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x700) >> 8
}
func (o *SAI_Type) SetPDMDLY_DLYM2L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x70000)|value<<16)
}
func (o *SAI_Type) GetPDMDLY_DLYM2L() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x70000) >> 16
}
func (o *SAI_Type) SetPDMDLY_DLYM3L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x7000000)|value<<24)
}
func (o *SAI_Type) GetPDMDLY_DLYM3L() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x7000000) >> 24
}
func (o *SAI_Type) SetPDMDLY_DLYM4L(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x0)|value<<32)
}
func (o *SAI_Type) GetPDMDLY_DLYM4L() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x0) >> 32
}
func (o *SAI_Type) SetPDMDLY_DLYM1R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x7000)|value<<12)
}
func (o *SAI_Type) GetPDMDLY_DLYM1R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x7000) >> 12
}
func (o *SAI_Type) SetPDMDLY_DLYM2R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x700000)|value<<20)
}
func (o *SAI_Type) GetPDMDLY_DLYM2R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x700000) >> 20
}
func (o *SAI_Type) SetPDMDLY_DLYM3R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x70000000)|value<<28)
}
func (o *SAI_Type) GetPDMDLY_DLYM3R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x70000000) >> 28
}
func (o *SAI_Type) SetPDMDLY_DLYM4R(value uint32) {
	volatile.StoreUint32(&o.PDMDLY.Reg, volatile.LoadUint32(&o.PDMDLY.Reg)&^(0x0)|value<<36)
}
func (o *SAI_Type) GetPDMDLY_DLYM4R() uint32 {
	return (volatile.LoadUint32(&o.PDMDLY.Reg) & 0x0) >> 36
}

// Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR
type SAI_CH_Type struct {
	CR1   volatile.Register32 // 0x4
	CR2   volatile.Register32 // 0x8
	FRCR  volatile.Register32 // 0xC
	SLOTR volatile.Register32 // 0x10
	IM    volatile.Register32 // 0x14
	SR    volatile.Register32 // 0x18
	CLRFR volatile.Register32 // 0x1C
	DR    volatile.Register32 // 0x20
}

// SAI_CH.CR1: AConfiguration register 1
func (o *SAI_CH_Type) SetCR1_MCKDIV(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xf00000)|value<<20)
}
func (o *SAI_CH_Type) GetCR1_MCKDIV() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xf00000) >> 20
}
func (o *SAI_CH_Type) SetCR1_NODIV(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80000)|value<<19)
}
func (o *SAI_CH_Type) GetCR1_NODIV() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80000) >> 19
}
func (o *SAI_CH_Type) SetCR1_DMAEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *SAI_CH_Type) GetCR1_DMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *SAI_CH_Type) SetCR1_SAIEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *SAI_CH_Type) GetCR1_SAIEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *SAI_CH_Type) SetCR1_OUTDRIV(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *SAI_CH_Type) GetCR1_OUTDRIV() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *SAI_CH_Type) SetCR1_MONO(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *SAI_CH_Type) GetCR1_MONO() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *SAI_CH_Type) SetCR1_SYNCEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xc00)|value<<10)
}
func (o *SAI_CH_Type) GetCR1_SYNCEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xc00) >> 10
}
func (o *SAI_CH_Type) SetCR1_CKSTR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *SAI_CH_Type) GetCR1_CKSTR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *SAI_CH_Type) SetCR1_LSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *SAI_CH_Type) GetCR1_LSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *SAI_CH_Type) SetCR1_DS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xe0)|value<<5)
}
func (o *SAI_CH_Type) GetCR1_DS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xe0) >> 5
}
func (o *SAI_CH_Type) SetCR1_PRTCFG(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0xc)|value<<2)
}
func (o *SAI_CH_Type) GetCR1_PRTCFG() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0xc) >> 2
}
func (o *SAI_CH_Type) SetCR1_MODE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x3)|value)
}
func (o *SAI_CH_Type) GetCR1_MODE() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x3
}
func (o *SAI_CH_Type) SetCR1_OSR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000000)|value<<26)
}
func (o *SAI_CH_Type) GetCR1_OSR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000000) >> 26
}

// SAI_CH.CR2: AConfiguration register 2
func (o *SAI_CH_Type) SetCR2_COMP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xc000)|value<<14)
}
func (o *SAI_CH_Type) GetCR2_COMP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xc000) >> 14
}
func (o *SAI_CH_Type) SetCR2_CPL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *SAI_CH_Type) GetCR2_CPL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *SAI_CH_Type) SetCR2_MUTECNT(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1f80)|value<<7)
}
func (o *SAI_CH_Type) GetCR2_MUTECNT() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1f80) >> 7
}
func (o *SAI_CH_Type) SetCR2_MUTEVAL(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *SAI_CH_Type) GetCR2_MUTEVAL() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *SAI_CH_Type) SetCR2_MUTE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *SAI_CH_Type) GetCR2_MUTE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *SAI_CH_Type) SetCR2_TRIS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *SAI_CH_Type) GetCR2_TRIS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *SAI_CH_Type) SetCR2_FFLUSH(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *SAI_CH_Type) GetCR2_FFLUSH() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *SAI_CH_Type) SetCR2_FTH(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x7)|value)
}
func (o *SAI_CH_Type) GetCR2_FTH() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x7
}

// SAI_CH.FRCR: AFRCR
func (o *SAI_CH_Type) SetFRCR_FSOFF(value uint32) {
	volatile.StoreUint32(&o.FRCR.Reg, volatile.LoadUint32(&o.FRCR.Reg)&^(0x40000)|value<<18)
}
func (o *SAI_CH_Type) GetFRCR_FSOFF() uint32 {
	return (volatile.LoadUint32(&o.FRCR.Reg) & 0x40000) >> 18
}
func (o *SAI_CH_Type) SetFRCR_FSPOL(value uint32) {
	volatile.StoreUint32(&o.FRCR.Reg, volatile.LoadUint32(&o.FRCR.Reg)&^(0x20000)|value<<17)
}
func (o *SAI_CH_Type) GetFRCR_FSPOL() uint32 {
	return (volatile.LoadUint32(&o.FRCR.Reg) & 0x20000) >> 17
}
func (o *SAI_CH_Type) SetFRCR_FSDEF(value uint32) {
	volatile.StoreUint32(&o.FRCR.Reg, volatile.LoadUint32(&o.FRCR.Reg)&^(0x10000)|value<<16)
}
func (o *SAI_CH_Type) GetFRCR_FSDEF() uint32 {
	return (volatile.LoadUint32(&o.FRCR.Reg) & 0x10000) >> 16
}
func (o *SAI_CH_Type) SetFRCR_FSALL(value uint32) {
	volatile.StoreUint32(&o.FRCR.Reg, volatile.LoadUint32(&o.FRCR.Reg)&^(0x7f00)|value<<8)
}
func (o *SAI_CH_Type) GetFRCR_FSALL() uint32 {
	return (volatile.LoadUint32(&o.FRCR.Reg) & 0x7f00) >> 8
}
func (o *SAI_CH_Type) SetFRCR_FRL(value uint32) {
	volatile.StoreUint32(&o.FRCR.Reg, volatile.LoadUint32(&o.FRCR.Reg)&^(0xff)|value)
}
func (o *SAI_CH_Type) GetFRCR_FRL() uint32 {
	return volatile.LoadUint32(&o.FRCR.Reg) & 0xff
}

// SAI_CH.SLOTR: ASlot register
func (o *SAI_CH_Type) SetSLOTR_SLOTEN(value uint32) {
	volatile.StoreUint32(&o.SLOTR.Reg, volatile.LoadUint32(&o.SLOTR.Reg)&^(0xffff0000)|value<<16)
}
func (o *SAI_CH_Type) GetSLOTR_SLOTEN() uint32 {
	return (volatile.LoadUint32(&o.SLOTR.Reg) & 0xffff0000) >> 16
}
func (o *SAI_CH_Type) SetSLOTR_NBSLOT(value uint32) {
	volatile.StoreUint32(&o.SLOTR.Reg, volatile.LoadUint32(&o.SLOTR.Reg)&^(0xf00)|value<<8)
}
func (o *SAI_CH_Type) GetSLOTR_NBSLOT() uint32 {
	return (volatile.LoadUint32(&o.SLOTR.Reg) & 0xf00) >> 8
}
func (o *SAI_CH_Type) SetSLOTR_SLOTSZ(value uint32) {
	volatile.StoreUint32(&o.SLOTR.Reg, volatile.LoadUint32(&o.SLOTR.Reg)&^(0xc0)|value<<6)
}
func (o *SAI_CH_Type) GetSLOTR_SLOTSZ() uint32 {
	return (volatile.LoadUint32(&o.SLOTR.Reg) & 0xc0) >> 6
}
func (o *SAI_CH_Type) SetSLOTR_FBOFF(value uint32) {
	volatile.StoreUint32(&o.SLOTR.Reg, volatile.LoadUint32(&o.SLOTR.Reg)&^(0x1f)|value)
}
func (o *SAI_CH_Type) GetSLOTR_FBOFF() uint32 {
	return volatile.LoadUint32(&o.SLOTR.Reg) & 0x1f
}

// SAI_CH.IM: AInterrupt mask register2
func (o *SAI_CH_Type) SetIM_LFSDETIE(value uint32) {
	volatile.StoreUint32(&o.IM.Reg, volatile.LoadUint32(&o.IM.Reg)&^(0x40)|value<<6)
}
func (o *SAI_CH_Type) GetIM_LFSDETIE() uint32 {
	return (volatile.LoadUint32(&o.IM.Reg) & 0x40) >> 6
}
func (o *SAI_CH_Type) SetIM_AFSDETIE(value uint32) {
	volatile.StoreUint32(&o.IM.Reg, volatile.LoadUint32(&o.IM.Reg)&^(0x20)|value<<5)
}
func (o *SAI_CH_Type) GetIM_AFSDETIE() uint32 {
	return (volatile.LoadUint32(&o.IM.Reg) & 0x20) >> 5
}
func (o *SAI_CH_Type) SetIM_CNRDYIE(value uint32) {
	volatile.StoreUint32(&o.IM.Reg, volatile.LoadUint32(&o.IM.Reg)&^(0x10)|value<<4)
}
func (o *SAI_CH_Type) GetIM_CNRDYIE() uint32 {
	return (volatile.LoadUint32(&o.IM.Reg) & 0x10) >> 4
}
func (o *SAI_CH_Type) SetIM_FREQIE(value uint32) {
	volatile.StoreUint32(&o.IM.Reg, volatile.LoadUint32(&o.IM.Reg)&^(0x8)|value<<3)
}
func (o *SAI_CH_Type) GetIM_FREQIE() uint32 {
	return (volatile.LoadUint32(&o.IM.Reg) & 0x8) >> 3
}
func (o *SAI_CH_Type) SetIM_WCKCFGIE(value uint32) {
	volatile.StoreUint32(&o.IM.Reg, volatile.LoadUint32(&o.IM.Reg)&^(0x4)|value<<2)
}
func (o *SAI_CH_Type) GetIM_WCKCFGIE() uint32 {
	return (volatile.LoadUint32(&o.IM.Reg) & 0x4) >> 2
}
func (o *SAI_CH_Type) SetIM_MUTEDETIE(value uint32) {
	volatile.StoreUint32(&o.IM.Reg, volatile.LoadUint32(&o.IM.Reg)&^(0x2)|value<<1)
}
func (o *SAI_CH_Type) GetIM_MUTEDETIE() uint32 {
	return (volatile.LoadUint32(&o.IM.Reg) & 0x2) >> 1
}
func (o *SAI_CH_Type) SetIM_OVRUDRIE(value uint32) {
	volatile.StoreUint32(&o.IM.Reg, volatile.LoadUint32(&o.IM.Reg)&^(0x1)|value)
}
func (o *SAI_CH_Type) GetIM_OVRUDRIE() uint32 {
	return volatile.LoadUint32(&o.IM.Reg) & 0x1
}

// SAI_CH.SR: AStatus register
func (o *SAI_CH_Type) SetSR_FLVL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x70000)|value<<16)
}
func (o *SAI_CH_Type) GetSR_FLVL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x70000) >> 16
}
func (o *SAI_CH_Type) SetSR_LFSDET(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *SAI_CH_Type) GetSR_LFSDET() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *SAI_CH_Type) SetSR_AFSDET(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *SAI_CH_Type) GetSR_AFSDET() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *SAI_CH_Type) SetSR_CNRDY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *SAI_CH_Type) GetSR_CNRDY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *SAI_CH_Type) SetSR_FREQ(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *SAI_CH_Type) GetSR_FREQ() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *SAI_CH_Type) SetSR_WCKCFG(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *SAI_CH_Type) GetSR_WCKCFG() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *SAI_CH_Type) SetSR_MUTEDET(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SAI_CH_Type) GetSR_MUTEDET() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *SAI_CH_Type) SetSR_OVRUDR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *SAI_CH_Type) GetSR_OVRUDR() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// SAI_CH.CLRFR: AClear flag register
func (o *SAI_CH_Type) SetCLRFR_CLFSDET(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x40)|value<<6)
}
func (o *SAI_CH_Type) GetCLRFR_CLFSDET() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x40) >> 6
}
func (o *SAI_CH_Type) SetCLRFR_CAFSDET(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x20)|value<<5)
}
func (o *SAI_CH_Type) GetCLRFR_CAFSDET() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x20) >> 5
}
func (o *SAI_CH_Type) SetCLRFR_CCNRDY(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x10)|value<<4)
}
func (o *SAI_CH_Type) GetCLRFR_CCNRDY() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x10) >> 4
}
func (o *SAI_CH_Type) SetCLRFR_CWCKCFG(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x4)|value<<2)
}
func (o *SAI_CH_Type) GetCLRFR_CWCKCFG() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x4) >> 2
}
func (o *SAI_CH_Type) SetCLRFR_CMUTEDET(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x2)|value<<1)
}
func (o *SAI_CH_Type) GetCLRFR_CMUTEDET() uint32 {
	return (volatile.LoadUint32(&o.CLRFR.Reg) & 0x2) >> 1
}
func (o *SAI_CH_Type) SetCLRFR_COVRUDR(value uint32) {
	volatile.StoreUint32(&o.CLRFR.Reg, volatile.LoadUint32(&o.CLRFR.Reg)&^(0x1)|value)
}
func (o *SAI_CH_Type) GetCLRFR_COVRUDR() uint32 {
	return volatile.LoadUint32(&o.CLRFR.Reg) & 0x1
}

// SAI_CH.DR: AData register
func (o *SAI_CH_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, value)
}
func (o *SAI_CH_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg)
}

// SDMMC1
type SDMMC_Type struct {
	POWER      volatile.Register32 // 0x0
	CLKCR      volatile.Register32 // 0x4
	ARGR       volatile.Register32 // 0x8
	CMDR       volatile.Register32 // 0xC
	RESPCMDR   volatile.Register32 // 0x10
	RESP1R     volatile.Register32 // 0x14
	RESP2R     volatile.Register32 // 0x18
	RESP3R     volatile.Register32 // 0x1C
	RESP4R     volatile.Register32 // 0x20
	DTIMER     volatile.Register32 // 0x24
	DLENR      volatile.Register32 // 0x28
	DCTRL      volatile.Register32 // 0x2C
	DCNTR      volatile.Register32 // 0x30
	STAR       volatile.Register32 // 0x34
	ICR        volatile.Register32 // 0x38
	MASKR      volatile.Register32 // 0x3C
	ACKTIMER   volatile.Register32 // 0x40
	_          [12]byte
	IDMACTRLR  volatile.Register32 // 0x50
	IDMABSIZER volatile.Register32 // 0x54
	IDMABASE0R volatile.Register32 // 0x58
	IDMABASE1R volatile.Register32 // 0x5C
	_          [32]byte
	FIFOR      volatile.Register32 // 0x80
}

// SDMMC.POWER: SDMMC power control register
func (o *SDMMC_Type) SetPOWER_PWRCTRL(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x3)|value)
}
func (o *SDMMC_Type) GetPOWER_PWRCTRL() uint32 {
	return volatile.LoadUint32(&o.POWER.Reg) & 0x3
}
func (o *SDMMC_Type) SetPOWER_VSWITCH(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetPOWER_VSWITCH() uint32 {
	return (volatile.LoadUint32(&o.POWER.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetPOWER_VSWITCHEN(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetPOWER_VSWITCHEN() uint32 {
	return (volatile.LoadUint32(&o.POWER.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetPOWER_DIRPOL(value uint32) {
	volatile.StoreUint32(&o.POWER.Reg, volatile.LoadUint32(&o.POWER.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetPOWER_DIRPOL() uint32 {
	return (volatile.LoadUint32(&o.POWER.Reg) & 0x10) >> 4
}

// SDMMC.CLKCR: The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.
func (o *SDMMC_Type) SetCLKCR_CLKDIV(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x3ff)|value)
}
func (o *SDMMC_Type) GetCLKCR_CLKDIV() uint32 {
	return volatile.LoadUint32(&o.CLKCR.Reg) & 0x3ff
}
func (o *SDMMC_Type) SetCLKCR_PWRSAV(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetCLKCR_PWRSAV() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetCLKCR_WIDBUS(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0xc000)|value<<14)
}
func (o *SDMMC_Type) GetCLKCR_WIDBUS() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0xc000) >> 14
}
func (o *SDMMC_Type) SetCLKCR_NEGEDGE(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x10000)|value<<16)
}
func (o *SDMMC_Type) GetCLKCR_NEGEDGE() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x10000) >> 16
}
func (o *SDMMC_Type) SetCLKCR_HWFC_EN(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x20000)|value<<17)
}
func (o *SDMMC_Type) GetCLKCR_HWFC_EN() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x20000) >> 17
}
func (o *SDMMC_Type) SetCLKCR_DDR(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x40000)|value<<18)
}
func (o *SDMMC_Type) GetCLKCR_DDR() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x40000) >> 18
}
func (o *SDMMC_Type) SetCLKCR_BUSSPEED(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x80000)|value<<19)
}
func (o *SDMMC_Type) GetCLKCR_BUSSPEED() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x80000) >> 19
}
func (o *SDMMC_Type) SetCLKCR_SELCLKRX(value uint32) {
	volatile.StoreUint32(&o.CLKCR.Reg, volatile.LoadUint32(&o.CLKCR.Reg)&^(0x300000)|value<<20)
}
func (o *SDMMC_Type) GetCLKCR_SELCLKRX() uint32 {
	return (volatile.LoadUint32(&o.CLKCR.Reg) & 0x300000) >> 20
}

// SDMMC.ARGR: The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.
func (o *SDMMC_Type) SetARGR(value uint32) {
	volatile.StoreUint32(&o.ARGR.Reg, value)
}
func (o *SDMMC_Type) GetARGR() uint32 {
	return volatile.LoadUint32(&o.ARGR.Reg)
}

// SDMMC.CMDR: The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
func (o *SDMMC_Type) SetCMDR_CMDINDEX(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x3f)|value)
}
func (o *SDMMC_Type) GetCMDR_CMDINDEX() uint32 {
	return volatile.LoadUint32(&o.CMDR.Reg) & 0x3f
}
func (o *SDMMC_Type) SetCMDR_CMDTRANS(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetCMDR_CMDTRANS() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetCMDR_CMDSTOP(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetCMDR_CMDSTOP() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetCMDR_WAITRESP(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x300)|value<<8)
}
func (o *SDMMC_Type) GetCMDR_WAITRESP() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x300) >> 8
}
func (o *SDMMC_Type) SetCMDR_WAITINT(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetCMDR_WAITINT() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetCMDR_WAITPEND(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetCMDR_WAITPEND() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetCMDR_CPSMEN(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetCMDR_CPSMEN() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetCMDR_DTHOLD(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x2000)|value<<13)
}
func (o *SDMMC_Type) GetCMDR_DTHOLD() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x2000) >> 13
}
func (o *SDMMC_Type) SetCMDR_BOOTMODE(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x4000)|value<<14)
}
func (o *SDMMC_Type) GetCMDR_BOOTMODE() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x4000) >> 14
}
func (o *SDMMC_Type) SetCMDR_BOOTEN(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x8000)|value<<15)
}
func (o *SDMMC_Type) GetCMDR_BOOTEN() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x8000) >> 15
}
func (o *SDMMC_Type) SetCMDR_CMDSUSPEND(value uint32) {
	volatile.StoreUint32(&o.CMDR.Reg, volatile.LoadUint32(&o.CMDR.Reg)&^(0x10000)|value<<16)
}
func (o *SDMMC_Type) GetCMDR_CMDSUSPEND() uint32 {
	return (volatile.LoadUint32(&o.CMDR.Reg) & 0x10000) >> 16
}

// SDMMC.RESPCMDR: SDMMC command response register
func (o *SDMMC_Type) SetRESPCMDR_RESPCMD(value uint32) {
	volatile.StoreUint32(&o.RESPCMDR.Reg, volatile.LoadUint32(&o.RESPCMDR.Reg)&^(0x3f)|value)
}
func (o *SDMMC_Type) GetRESPCMDR_RESPCMD() uint32 {
	return volatile.LoadUint32(&o.RESPCMDR.Reg) & 0x3f
}

// SDMMC.RESP1R: SDMMC response %s register
func (o *SDMMC_Type) SetRESP1R(value uint32) {
	volatile.StoreUint32(&o.RESP1R.Reg, value)
}
func (o *SDMMC_Type) GetRESP1R() uint32 {
	return volatile.LoadUint32(&o.RESP1R.Reg)
}

// SDMMC.RESP2R: SDMMC response %s register
func (o *SDMMC_Type) SetRESP2R(value uint32) {
	volatile.StoreUint32(&o.RESP2R.Reg, value)
}
func (o *SDMMC_Type) GetRESP2R() uint32 {
	return volatile.LoadUint32(&o.RESP2R.Reg)
}

// SDMMC.RESP3R: SDMMC response %s register
func (o *SDMMC_Type) SetRESP3R(value uint32) {
	volatile.StoreUint32(&o.RESP3R.Reg, value)
}
func (o *SDMMC_Type) GetRESP3R() uint32 {
	return volatile.LoadUint32(&o.RESP3R.Reg)
}

// SDMMC.RESP4R: SDMMC response %s register
func (o *SDMMC_Type) SetRESP4R(value uint32) {
	volatile.StoreUint32(&o.RESP4R.Reg, value)
}
func (o *SDMMC_Type) GetRESP4R() uint32 {
	return volatile.LoadUint32(&o.RESP4R.Reg)
}

// SDMMC.DTIMER: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
func (o *SDMMC_Type) SetDTIMER(value uint32) {
	volatile.StoreUint32(&o.DTIMER.Reg, value)
}
func (o *SDMMC_Type) GetDTIMER() uint32 {
	return volatile.LoadUint32(&o.DTIMER.Reg)
}

// SDMMC.DLENR: The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.
func (o *SDMMC_Type) SetDLENR_DATALENGTH(value uint32) {
	volatile.StoreUint32(&o.DLENR.Reg, volatile.LoadUint32(&o.DLENR.Reg)&^(0x1ffffff)|value)
}
func (o *SDMMC_Type) GetDLENR_DATALENGTH() uint32 {
	return volatile.LoadUint32(&o.DLENR.Reg) & 0x1ffffff
}

// SDMMC.DCTRL: The SDMMC_DCTRL register control the data path state machine (DPSM).
func (o *SDMMC_Type) SetDCTRL_DTEN(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetDCTRL_DTEN() uint32 {
	return volatile.LoadUint32(&o.DCTRL.Reg) & 0x1
}
func (o *SDMMC_Type) SetDCTRL_DTDIR(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetDCTRL_DTDIR() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetDCTRL_DTMODE(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0xc)|value<<2)
}
func (o *SDMMC_Type) GetDCTRL_DTMODE() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0xc) >> 2
}
func (o *SDMMC_Type) SetDCTRL_DBLOCKSIZE(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0xf0)|value<<4)
}
func (o *SDMMC_Type) GetDCTRL_DBLOCKSIZE() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0xf0) >> 4
}
func (o *SDMMC_Type) SetDCTRL_RWSTART(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetDCTRL_RWSTART() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetDCTRL_RWSTOP(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetDCTRL_RWSTOP() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetDCTRL_RWMOD(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetDCTRL_RWMOD() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetDCTRL_SDIOEN(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetDCTRL_SDIOEN() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetDCTRL_BOOTACKEN(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetDCTRL_BOOTACKEN() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetDCTRL_FIFORST(value uint32) {
	volatile.StoreUint32(&o.DCTRL.Reg, volatile.LoadUint32(&o.DCTRL.Reg)&^(0x2000)|value<<13)
}
func (o *SDMMC_Type) GetDCTRL_FIFORST() uint32 {
	return (volatile.LoadUint32(&o.DCTRL.Reg) & 0x2000) >> 13
}

// SDMMC.DCNTR: The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.
func (o *SDMMC_Type) SetDCNTR_DATACOUNT(value uint32) {
	volatile.StoreUint32(&o.DCNTR.Reg, volatile.LoadUint32(&o.DCNTR.Reg)&^(0x1ffffff)|value)
}
func (o *SDMMC_Type) GetDCNTR_DATACOUNT() uint32 {
	return volatile.LoadUint32(&o.DCNTR.Reg) & 0x1ffffff
}

// SDMMC.STAR: The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)
func (o *SDMMC_Type) SetSTAR_CCRCFAIL(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetSTAR_CCRCFAIL() uint32 {
	return volatile.LoadUint32(&o.STAR.Reg) & 0x1
}
func (o *SDMMC_Type) SetSTAR_DCRCFAIL(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetSTAR_DCRCFAIL() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetSTAR_CTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetSTAR_CTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetSTAR_DTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetSTAR_DTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetSTAR_TXUNDERR(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetSTAR_TXUNDERR() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x10) >> 4
}
func (o *SDMMC_Type) SetSTAR_RXOVERR(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x20)|value<<5)
}
func (o *SDMMC_Type) GetSTAR_RXOVERR() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x20) >> 5
}
func (o *SDMMC_Type) SetSTAR_CMDREND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetSTAR_CMDREND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetSTAR_CMDSENT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetSTAR_CMDSENT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetSTAR_DATAEND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetSTAR_DATAEND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetSTAR_DHOLD(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetSTAR_DHOLD() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetSTAR_DBCKEND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetSTAR_DBCKEND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetSTAR_DABORT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetSTAR_DABORT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetSTAR_DPSMACT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x1000)|value<<12)
}
func (o *SDMMC_Type) GetSTAR_DPSMACT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x1000) >> 12
}
func (o *SDMMC_Type) SetSTAR_CPSMACT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x2000)|value<<13)
}
func (o *SDMMC_Type) GetSTAR_CPSMACT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x2000) >> 13
}
func (o *SDMMC_Type) SetSTAR_TXFIFOHE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x4000)|value<<14)
}
func (o *SDMMC_Type) GetSTAR_TXFIFOHE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x4000) >> 14
}
func (o *SDMMC_Type) SetSTAR_RXFIFOHF(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x8000)|value<<15)
}
func (o *SDMMC_Type) GetSTAR_RXFIFOHF() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x8000) >> 15
}
func (o *SDMMC_Type) SetSTAR_TXFIFOF(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x10000)|value<<16)
}
func (o *SDMMC_Type) GetSTAR_TXFIFOF() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x10000) >> 16
}
func (o *SDMMC_Type) SetSTAR_RXFIFOF(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x20000)|value<<17)
}
func (o *SDMMC_Type) GetSTAR_RXFIFOF() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x20000) >> 17
}
func (o *SDMMC_Type) SetSTAR_TXFIFOE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x40000)|value<<18)
}
func (o *SDMMC_Type) GetSTAR_TXFIFOE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x40000) >> 18
}
func (o *SDMMC_Type) SetSTAR_RXFIFOE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x80000)|value<<19)
}
func (o *SDMMC_Type) GetSTAR_RXFIFOE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x80000) >> 19
}
func (o *SDMMC_Type) SetSTAR_BUSYD0(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x100000)|value<<20)
}
func (o *SDMMC_Type) GetSTAR_BUSYD0() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x100000) >> 20
}
func (o *SDMMC_Type) SetSTAR_BUSYD0END(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x200000)|value<<21)
}
func (o *SDMMC_Type) GetSTAR_BUSYD0END() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x200000) >> 21
}
func (o *SDMMC_Type) SetSTAR_SDIOIT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x400000)|value<<22)
}
func (o *SDMMC_Type) GetSTAR_SDIOIT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x400000) >> 22
}
func (o *SDMMC_Type) SetSTAR_ACKFAIL(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x800000)|value<<23)
}
func (o *SDMMC_Type) GetSTAR_ACKFAIL() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x800000) >> 23
}
func (o *SDMMC_Type) SetSTAR_ACKTIMEOUT(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x1000000)|value<<24)
}
func (o *SDMMC_Type) GetSTAR_ACKTIMEOUT() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x1000000) >> 24
}
func (o *SDMMC_Type) SetSTAR_VSWEND(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x2000000)|value<<25)
}
func (o *SDMMC_Type) GetSTAR_VSWEND() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x2000000) >> 25
}
func (o *SDMMC_Type) SetSTAR_CKSTOP(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x4000000)|value<<26)
}
func (o *SDMMC_Type) GetSTAR_CKSTOP() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x4000000) >> 26
}
func (o *SDMMC_Type) SetSTAR_IDMATE(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x8000000)|value<<27)
}
func (o *SDMMC_Type) GetSTAR_IDMATE() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x8000000) >> 27
}
func (o *SDMMC_Type) SetSTAR_IDMABTC(value uint32) {
	volatile.StoreUint32(&o.STAR.Reg, volatile.LoadUint32(&o.STAR.Reg)&^(0x10000000)|value<<28)
}
func (o *SDMMC_Type) GetSTAR_IDMABTC() uint32 {
	return (volatile.LoadUint32(&o.STAR.Reg) & 0x10000000) >> 28
}

// SDMMC.ICR: The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.
func (o *SDMMC_Type) SetICR_CCRCFAILC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetICR_CCRCFAILC() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}
func (o *SDMMC_Type) SetICR_DCRCFAILC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetICR_DCRCFAILC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetICR_CTIMEOUTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetICR_CTIMEOUTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetICR_DTIMEOUTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetICR_DTIMEOUTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetICR_TXUNDERRC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetICR_TXUNDERRC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *SDMMC_Type) SetICR_RXOVERRC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *SDMMC_Type) GetICR_RXOVERRC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *SDMMC_Type) SetICR_CMDRENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetICR_CMDRENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetICR_CMDSENTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetICR_CMDSENTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetICR_DATAENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetICR_DATAENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetICR_DHOLDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetICR_DHOLDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetICR_DBCKENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetICR_DBCKENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetICR_DABORTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetICR_DABORTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetICR_BUSYD0ENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200000)|value<<21)
}
func (o *SDMMC_Type) GetICR_BUSYD0ENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200000) >> 21
}
func (o *SDMMC_Type) SetICR_SDIOITC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400000)|value<<22)
}
func (o *SDMMC_Type) GetICR_SDIOITC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400000) >> 22
}
func (o *SDMMC_Type) SetICR_ACKFAILC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800000)|value<<23)
}
func (o *SDMMC_Type) GetICR_ACKFAILC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800000) >> 23
}
func (o *SDMMC_Type) SetICR_ACKTIMEOUTC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000000)|value<<24)
}
func (o *SDMMC_Type) GetICR_ACKTIMEOUTC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000000) >> 24
}
func (o *SDMMC_Type) SetICR_VSWENDC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2000000)|value<<25)
}
func (o *SDMMC_Type) GetICR_VSWENDC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2000000) >> 25
}
func (o *SDMMC_Type) SetICR_CKSTOPC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4000000)|value<<26)
}
func (o *SDMMC_Type) GetICR_CKSTOPC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4000000) >> 26
}
func (o *SDMMC_Type) SetICR_IDMATEC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8000000)|value<<27)
}
func (o *SDMMC_Type) GetICR_IDMATEC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8000000) >> 27
}
func (o *SDMMC_Type) SetICR_IDMABTCC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10000000)|value<<28)
}
func (o *SDMMC_Type) GetICR_IDMABTCC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10000000) >> 28
}

// SDMMC.MASKR: The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
func (o *SDMMC_Type) SetMASKR_CCRCFAILIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetMASKR_CCRCFAILIE() uint32 {
	return volatile.LoadUint32(&o.MASKR.Reg) & 0x1
}
func (o *SDMMC_Type) SetMASKR_DCRCFAILIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetMASKR_DCRCFAILIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetMASKR_CTIMEOUTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetMASKR_CTIMEOUTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x4) >> 2
}
func (o *SDMMC_Type) SetMASKR_DTIMEOUTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x8)|value<<3)
}
func (o *SDMMC_Type) GetMASKR_DTIMEOUTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x8) >> 3
}
func (o *SDMMC_Type) SetMASKR_TXUNDERRIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x10)|value<<4)
}
func (o *SDMMC_Type) GetMASKR_TXUNDERRIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x10) >> 4
}
func (o *SDMMC_Type) SetMASKR_RXOVERRIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x20)|value<<5)
}
func (o *SDMMC_Type) GetMASKR_RXOVERRIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x20) >> 5
}
func (o *SDMMC_Type) SetMASKR_CMDRENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x40)|value<<6)
}
func (o *SDMMC_Type) GetMASKR_CMDRENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x40) >> 6
}
func (o *SDMMC_Type) SetMASKR_CMDSENTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x80)|value<<7)
}
func (o *SDMMC_Type) GetMASKR_CMDSENTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x80) >> 7
}
func (o *SDMMC_Type) SetMASKR_DATAENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x100)|value<<8)
}
func (o *SDMMC_Type) GetMASKR_DATAENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x100) >> 8
}
func (o *SDMMC_Type) SetMASKR_DHOLDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x200)|value<<9)
}
func (o *SDMMC_Type) GetMASKR_DHOLDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x200) >> 9
}
func (o *SDMMC_Type) SetMASKR_DBCKENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x400)|value<<10)
}
func (o *SDMMC_Type) GetMASKR_DBCKENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x400) >> 10
}
func (o *SDMMC_Type) SetMASKR_DABORTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x800)|value<<11)
}
func (o *SDMMC_Type) GetMASKR_DABORTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x800) >> 11
}
func (o *SDMMC_Type) SetMASKR_TXFIFOHEIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x4000)|value<<14)
}
func (o *SDMMC_Type) GetMASKR_TXFIFOHEIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x4000) >> 14
}
func (o *SDMMC_Type) SetMASKR_RXFIFOHFIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x8000)|value<<15)
}
func (o *SDMMC_Type) GetMASKR_RXFIFOHFIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x8000) >> 15
}
func (o *SDMMC_Type) SetMASKR_RXFIFOFIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x20000)|value<<17)
}
func (o *SDMMC_Type) GetMASKR_RXFIFOFIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x20000) >> 17
}
func (o *SDMMC_Type) SetMASKR_TXFIFOEIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x40000)|value<<18)
}
func (o *SDMMC_Type) GetMASKR_TXFIFOEIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x40000) >> 18
}
func (o *SDMMC_Type) SetMASKR_BUSYD0ENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x200000)|value<<21)
}
func (o *SDMMC_Type) GetMASKR_BUSYD0ENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x200000) >> 21
}
func (o *SDMMC_Type) SetMASKR_SDIOITIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x400000)|value<<22)
}
func (o *SDMMC_Type) GetMASKR_SDIOITIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x400000) >> 22
}
func (o *SDMMC_Type) SetMASKR_ACKFAILIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x800000)|value<<23)
}
func (o *SDMMC_Type) GetMASKR_ACKFAILIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x800000) >> 23
}
func (o *SDMMC_Type) SetMASKR_ACKTIMEOUTIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x1000000)|value<<24)
}
func (o *SDMMC_Type) GetMASKR_ACKTIMEOUTIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x1000000) >> 24
}
func (o *SDMMC_Type) SetMASKR_VSWENDIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x2000000)|value<<25)
}
func (o *SDMMC_Type) GetMASKR_VSWENDIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x2000000) >> 25
}
func (o *SDMMC_Type) SetMASKR_CKSTOPIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x4000000)|value<<26)
}
func (o *SDMMC_Type) GetMASKR_CKSTOPIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x4000000) >> 26
}
func (o *SDMMC_Type) SetMASKR_IDMABTCIE(value uint32) {
	volatile.StoreUint32(&o.MASKR.Reg, volatile.LoadUint32(&o.MASKR.Reg)&^(0x10000000)|value<<28)
}
func (o *SDMMC_Type) GetMASKR_IDMABTCIE() uint32 {
	return (volatile.LoadUint32(&o.MASKR.Reg) & 0x10000000) >> 28
}

// SDMMC.ACKTIMER: The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.
func (o *SDMMC_Type) SetACKTIMER_ACKTIME(value uint32) {
	volatile.StoreUint32(&o.ACKTIMER.Reg, volatile.LoadUint32(&o.ACKTIMER.Reg)&^(0x1ffffff)|value)
}
func (o *SDMMC_Type) GetACKTIMER_ACKTIME() uint32 {
	return volatile.LoadUint32(&o.ACKTIMER.Reg) & 0x1ffffff
}

// SDMMC.IDMACTRLR: The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
func (o *SDMMC_Type) SetIDMACTRLR_IDMAEN(value uint32) {
	volatile.StoreUint32(&o.IDMACTRLR.Reg, volatile.LoadUint32(&o.IDMACTRLR.Reg)&^(0x1)|value)
}
func (o *SDMMC_Type) GetIDMACTRLR_IDMAEN() uint32 {
	return volatile.LoadUint32(&o.IDMACTRLR.Reg) & 0x1
}
func (o *SDMMC_Type) SetIDMACTRLR_IDMABMODE(value uint32) {
	volatile.StoreUint32(&o.IDMACTRLR.Reg, volatile.LoadUint32(&o.IDMACTRLR.Reg)&^(0x2)|value<<1)
}
func (o *SDMMC_Type) GetIDMACTRLR_IDMABMODE() uint32 {
	return (volatile.LoadUint32(&o.IDMACTRLR.Reg) & 0x2) >> 1
}
func (o *SDMMC_Type) SetIDMACTRLR_IDMABACT(value uint32) {
	volatile.StoreUint32(&o.IDMACTRLR.Reg, volatile.LoadUint32(&o.IDMACTRLR.Reg)&^(0x4)|value<<2)
}
func (o *SDMMC_Type) GetIDMACTRLR_IDMABACT() uint32 {
	return (volatile.LoadUint32(&o.IDMACTRLR.Reg) & 0x4) >> 2
}

// SDMMC.IDMABSIZER: The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.
func (o *SDMMC_Type) SetIDMABSIZER_IDMABNDT(value uint32) {
	volatile.StoreUint32(&o.IDMABSIZER.Reg, volatile.LoadUint32(&o.IDMABSIZER.Reg)&^(0x1fe0)|value<<5)
}
func (o *SDMMC_Type) GetIDMABSIZER_IDMABNDT() uint32 {
	return (volatile.LoadUint32(&o.IDMABSIZER.Reg) & 0x1fe0) >> 5
}

// SDMMC.IDMABASE0R: The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.
func (o *SDMMC_Type) SetIDMABASE0R(value uint32) {
	volatile.StoreUint32(&o.IDMABASE0R.Reg, value)
}
func (o *SDMMC_Type) GetIDMABASE0R() uint32 {
	return volatile.LoadUint32(&o.IDMABASE0R.Reg)
}

// SDMMC.IDMABASE1R: The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.
func (o *SDMMC_Type) SetIDMABASE1R(value uint32) {
	volatile.StoreUint32(&o.IDMABASE1R.Reg, value)
}
func (o *SDMMC_Type) GetIDMABASE1R() uint32 {
	return volatile.LoadUint32(&o.IDMABASE1R.Reg)
}

// SDMMC.FIFOR: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
func (o *SDMMC_Type) SetFIFOR(value uint32) {
	volatile.StoreUint32(&o.FIFOR.Reg, value)
}
func (o *SDMMC_Type) GetFIFOR() uint32 {
	return volatile.LoadUint32(&o.FIFOR.Reg)
}

// Serial peripheral interface
type SPI_Type struct {
	CR1    volatile.Register32 // 0x0
	CR2    volatile.Register32 // 0x4
	SR     volatile.Register32 // 0x8
	DR     volatile.Register32 // 0xC
	CRCPR  volatile.Register32 // 0x10
	RXCRCR volatile.Register32 // 0x14
	TXCRCR volatile.Register32 // 0x18
}

// SPI.CR1: control register 1
func (o *SPI_Type) SetCR1_BIDIMODE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8000)|value<<15)
}
func (o *SPI_Type) GetCR1_BIDIMODE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8000) >> 15
}
func (o *SPI_Type) SetCR1_BIDIOE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCR1_BIDIOE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4000) >> 14
}
func (o *SPI_Type) SetCR1_CRCEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCR1_CRCEN() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCR1_CRCNEXT(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetCR1_CRCNEXT() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetCR1_CRCL(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *SPI_Type) GetCR1_CRCL() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}
func (o *SPI_Type) SetCR1_RXONLY(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x400)|value<<10)
}
func (o *SPI_Type) GetCR1_RXONLY() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x400) >> 10
}
func (o *SPI_Type) SetCR1_SSM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x200)|value<<9)
}
func (o *SPI_Type) GetCR1_SSM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x200) >> 9
}
func (o *SPI_Type) SetCR1_SSI(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetCR1_SSI() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetCR1_LSBFIRST(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetCR1_LSBFIRST() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetCR1_SPE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetCR1_SPE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetCR1_BR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x38)|value<<3)
}
func (o *SPI_Type) GetCR1_BR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x38) >> 3
}
func (o *SPI_Type) SetCR1_MSTR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetCR1_MSTR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetCR1_CPOL(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCR1_CPOL() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCR1_CPHA(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR1_CPHA() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}

// SPI.CR2: control register 2
func (o *SPI_Type) SetCR2_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetCR2_RXDMAEN() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *SPI_Type) SetCR2_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetCR2_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetCR2_SSOE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *SPI_Type) GetCR2_SSOE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *SPI_Type) SetCR2_NSSP(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *SPI_Type) GetCR2_NSSP() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *SPI_Type) SetCR2_FRF(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetCR2_FRF() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetCR2_ERRIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetCR2_ERRIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetCR2_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetCR2_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetCR2_TXEIE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetCR2_TXEIE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetCR2_DS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xf00)|value<<8)
}
func (o *SPI_Type) GetCR2_DS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xf00) >> 8
}
func (o *SPI_Type) SetCR2_FRXTH(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *SPI_Type) GetCR2_FRXTH() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *SPI_Type) SetCR2_LDMA_RX(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *SPI_Type) GetCR2_LDMA_RX() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *SPI_Type) SetCR2_LDMA_TX(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *SPI_Type) GetCR2_LDMA_TX() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}

// SPI.SR: status register
func (o *SPI_Type) SetSR_RXNE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *SPI_Type) GetSR_RXNE() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *SPI_Type) SetSR_TXE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *SPI_Type) GetSR_TXE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *SPI_Type) SetSR_CRCERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *SPI_Type) GetSR_CRCERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *SPI_Type) SetSR_MODF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *SPI_Type) GetSR_MODF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *SPI_Type) SetSR_OVR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *SPI_Type) GetSR_OVR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *SPI_Type) SetSR_BSY(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *SPI_Type) GetSR_BSY() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *SPI_Type) SetSR_TIFRFE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *SPI_Type) GetSR_TIFRFE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *SPI_Type) SetSR_FRLVL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x600)|value<<9)
}
func (o *SPI_Type) GetSR_FRLVL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x600) >> 9
}
func (o *SPI_Type) SetSR_FTLVL(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1800)|value<<11)
}
func (o *SPI_Type) GetSR_FTLVL() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1800) >> 11
}

// SPI.DR: data register
func (o *SPI_Type) SetDR(value uint32) {
	volatile.StoreUint32(&o.DR.Reg, volatile.LoadUint32(&o.DR.Reg)&^(0xffff)|value)
}
func (o *SPI_Type) GetDR() uint32 {
	return volatile.LoadUint32(&o.DR.Reg) & 0xffff
}

// SPI.CRCPR: CRC polynomial register
func (o *SPI_Type) SetCRCPR_CRCPOLY(value uint32) {
	volatile.StoreUint32(&o.CRCPR.Reg, volatile.LoadUint32(&o.CRCPR.Reg)&^(0xffff)|value)
}
func (o *SPI_Type) GetCRCPR_CRCPOLY() uint32 {
	return volatile.LoadUint32(&o.CRCPR.Reg) & 0xffff
}

// SPI.RXCRCR: RX CRC register
func (o *SPI_Type) SetRXCRCR_RxCRC(value uint32) {
	volatile.StoreUint32(&o.RXCRCR.Reg, volatile.LoadUint32(&o.RXCRCR.Reg)&^(0xffff)|value)
}
func (o *SPI_Type) GetRXCRCR_RxCRC() uint32 {
	return volatile.LoadUint32(&o.RXCRCR.Reg) & 0xffff
}

// SPI.TXCRCR: TX CRC register
func (o *SPI_Type) SetTXCRCR_TxCRC(value uint32) {
	volatile.StoreUint32(&o.TXCRCR.Reg, volatile.LoadUint32(&o.TXCRCR.Reg)&^(0xffff)|value)
}
func (o *SPI_Type) GetTXCRCR_TxCRC() uint32 {
	return volatile.LoadUint32(&o.TXCRCR.Reg) & 0xffff
}

// System configuration controller
type SYSCFG_Type struct {
	SECCFGR volatile.Register32 // 0x0
	CFGR1   volatile.Register32 // 0x4
	FPUIMR  volatile.Register32 // 0x8
	CNSLCKR volatile.Register32 // 0xC
	CSLOCKR volatile.Register32 // 0x10
	CFGR2   volatile.Register32 // 0x14
	SCSR    volatile.Register32 // 0x18
	SKR     volatile.Register32 // 0x1C
	SWPR    volatile.Register32 // 0x20
	SWPR2   volatile.Register32 // 0x24
	_       [4]byte
	RSSCMDR volatile.Register32 // 0x2C
}

// SYSCFG.SECCFGR: SYSCFG secure configuration register
func (o *SYSCFG_Type) SetSECCFGR_SRAM2SEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetSECCFGR_SRAM2SEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetSECCFGR_CLASSBSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetSECCFGR_CLASSBSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetSECCFGR_SYSCFGSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetSECCFGR_SYSCFGSEC() uint32 {
	return volatile.LoadUint32(&o.SECCFGR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetSECCFGR_FPUSEC(value uint32) {
	volatile.StoreUint32(&o.SECCFGR.Reg, volatile.LoadUint32(&o.SECCFGR.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetSECCFGR_FPUSEC() uint32 {
	return (volatile.LoadUint32(&o.SECCFGR.Reg) & 0x8) >> 3
}

// SYSCFG.CFGR1: configuration register 1
func (o *SYSCFG_Type) SetCFGR1_I2C4_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *SYSCFG_Type) GetCFGR1_I2C4_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x800000) >> 23
}
func (o *SYSCFG_Type) SetCFGR1_I2C3_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *SYSCFG_Type) GetCFGR1_I2C3_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x400000) >> 22
}
func (o *SYSCFG_Type) SetCFGR1_I2C2_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *SYSCFG_Type) GetCFGR1_I2C2_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200000) >> 21
}
func (o *SYSCFG_Type) SetCFGR1_I2C1_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *SYSCFG_Type) GetCFGR1_I2C1_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100000) >> 20
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PB9_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x80000)|value<<19)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PB9_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x80000) >> 19
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PB8_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x40000)|value<<18)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PB8_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x40000) >> 18
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PB7_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20000)|value<<17)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PB7_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20000) >> 17
}
func (o *SYSCFG_Type) SetCFGR1_I2C_PB6_FMP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10000)|value<<16)
}
func (o *SYSCFG_Type) GetCFGR1_I2C_PB6_FMP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10000) >> 16
}
func (o *SYSCFG_Type) SetCFGR1_BOOSTEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetCFGR1_BOOSTEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100) >> 8
}
func (o *SYSCFG_Type) SetCFGR1_ANASWVDD(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200)|value<<9)
}
func (o *SYSCFG_Type) GetCFGR1_ANASWVDD() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200) >> 9
}

// SYSCFG.FPUIMR: FPU interrupt mask register
func (o *SYSCFG_Type) SetFPUIMR_FPU_IE(value uint32) {
	volatile.StoreUint32(&o.FPUIMR.Reg, volatile.LoadUint32(&o.FPUIMR.Reg)&^(0x3f)|value)
}
func (o *SYSCFG_Type) GetFPUIMR_FPU_IE() uint32 {
	return volatile.LoadUint32(&o.FPUIMR.Reg) & 0x3f
}

// SYSCFG.CNSLCKR: SYSCFG CPU non-secure lock register
func (o *SYSCFG_Type) SetCNSLCKR_LOCKNSVTOR(value uint32) {
	volatile.StoreUint32(&o.CNSLCKR.Reg, volatile.LoadUint32(&o.CNSLCKR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCNSLCKR_LOCKNSVTOR() uint32 {
	return volatile.LoadUint32(&o.CNSLCKR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetCNSLCKR_LOCKNSMPU(value uint32) {
	volatile.StoreUint32(&o.CNSLCKR.Reg, volatile.LoadUint32(&o.CNSLCKR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCNSLCKR_LOCKNSMPU() uint32 {
	return (volatile.LoadUint32(&o.CNSLCKR.Reg) & 0x2) >> 1
}

// SYSCFG.CSLOCKR: SYSCFG CPU secure lock register
func (o *SYSCFG_Type) SetCSLOCKR_LOCKSVTAIRCR(value uint32) {
	volatile.StoreUint32(&o.CSLOCKR.Reg, volatile.LoadUint32(&o.CSLOCKR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCSLOCKR_LOCKSVTAIRCR() uint32 {
	return volatile.LoadUint32(&o.CSLOCKR.Reg) & 0x1
}
func (o *SYSCFG_Type) SetCSLOCKR_LOCKSMPU(value uint32) {
	volatile.StoreUint32(&o.CSLOCKR.Reg, volatile.LoadUint32(&o.CSLOCKR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCSLOCKR_LOCKSMPU() uint32 {
	return (volatile.LoadUint32(&o.CSLOCKR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetCSLOCKR_LOCKSAU(value uint32) {
	volatile.StoreUint32(&o.CSLOCKR.Reg, volatile.LoadUint32(&o.CSLOCKR.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetCSLOCKR_LOCKSAU() uint32 {
	return (volatile.LoadUint32(&o.CSLOCKR.Reg) & 0x4) >> 2
}

// SYSCFG.CFGR2: CFGR2
func (o *SYSCFG_Type) SetCFGR2_SPF(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetCFGR2_SPF() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x100) >> 8
}
func (o *SYSCFG_Type) SetCFGR2_ECCL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetCFGR2_ECCL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetCFGR2_PVDL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetCFGR2_PVDL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetCFGR2_SPL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetCFGR2_SPL() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetCFGR2_CLL(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetCFGR2_CLL() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}

// SYSCFG.SCSR: SCSR
func (o *SYSCFG_Type) SetSCSR_SRAM2BSY(value uint32) {
	volatile.StoreUint32(&o.SCSR.Reg, volatile.LoadUint32(&o.SCSR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetSCSR_SRAM2BSY() uint32 {
	return (volatile.LoadUint32(&o.SCSR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetSCSR_SRAM2ER(value uint32) {
	volatile.StoreUint32(&o.SCSR.Reg, volatile.LoadUint32(&o.SCSR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetSCSR_SRAM2ER() uint32 {
	return volatile.LoadUint32(&o.SCSR.Reg) & 0x1
}

// SYSCFG.SKR: SKR
func (o *SYSCFG_Type) SetSKR_KEY(value uint32) {
	volatile.StoreUint32(&o.SKR.Reg, volatile.LoadUint32(&o.SKR.Reg)&^(0xff)|value)
}
func (o *SYSCFG_Type) GetSKR_KEY() uint32 {
	return volatile.LoadUint32(&o.SKR.Reg) & 0xff
}

// SYSCFG.SWPR: SWPR
func (o *SYSCFG_Type) SetSWPR_P31WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSCFG_Type) GetSWPR_P31WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x80000000) >> 31
}
func (o *SYSCFG_Type) SetSWPR_P30WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSCFG_Type) GetSWPR_P30WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x40000000) >> 30
}
func (o *SYSCFG_Type) SetSWPR_P29WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSCFG_Type) GetSWPR_P29WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x20000000) >> 29
}
func (o *SYSCFG_Type) SetSWPR_P28WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSCFG_Type) GetSWPR_P28WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x10000000) >> 28
}
func (o *SYSCFG_Type) SetSWPR_P27WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x8000000)|value<<27)
}
func (o *SYSCFG_Type) GetSWPR_P27WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x8000000) >> 27
}
func (o *SYSCFG_Type) SetSWPR_P26WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x4000000)|value<<26)
}
func (o *SYSCFG_Type) GetSWPR_P26WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x4000000) >> 26
}
func (o *SYSCFG_Type) SetSWPR_P25WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x2000000)|value<<25)
}
func (o *SYSCFG_Type) GetSWPR_P25WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x2000000) >> 25
}
func (o *SYSCFG_Type) SetSWPR_P24WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x1000000)|value<<24)
}
func (o *SYSCFG_Type) GetSWPR_P24WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x1000000) >> 24
}
func (o *SYSCFG_Type) SetSWPR_P23WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x800000)|value<<23)
}
func (o *SYSCFG_Type) GetSWPR_P23WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x800000) >> 23
}
func (o *SYSCFG_Type) SetSWPR_P22WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x400000)|value<<22)
}
func (o *SYSCFG_Type) GetSWPR_P22WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x400000) >> 22
}
func (o *SYSCFG_Type) SetSWPR_P21WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x200000)|value<<21)
}
func (o *SYSCFG_Type) GetSWPR_P21WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x200000) >> 21
}
func (o *SYSCFG_Type) SetSWPR_P20WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x100000)|value<<20)
}
func (o *SYSCFG_Type) GetSWPR_P20WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x100000) >> 20
}
func (o *SYSCFG_Type) SetSWPR_P19WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x80000)|value<<19)
}
func (o *SYSCFG_Type) GetSWPR_P19WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x80000) >> 19
}
func (o *SYSCFG_Type) SetSWPR_P18WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x40000)|value<<18)
}
func (o *SYSCFG_Type) GetSWPR_P18WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x40000) >> 18
}
func (o *SYSCFG_Type) SetSWPR_P17WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x20000)|value<<17)
}
func (o *SYSCFG_Type) GetSWPR_P17WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x20000) >> 17
}
func (o *SYSCFG_Type) SetSWPR_P16WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x10000)|value<<16)
}
func (o *SYSCFG_Type) GetSWPR_P16WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x10000) >> 16
}
func (o *SYSCFG_Type) SetSWPR_P15WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x8000)|value<<15)
}
func (o *SYSCFG_Type) GetSWPR_P15WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x8000) >> 15
}
func (o *SYSCFG_Type) SetSWPR_P14WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x4000)|value<<14)
}
func (o *SYSCFG_Type) GetSWPR_P14WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x4000) >> 14
}
func (o *SYSCFG_Type) SetSWPR_P13WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x2000)|value<<13)
}
func (o *SYSCFG_Type) GetSWPR_P13WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x2000) >> 13
}
func (o *SYSCFG_Type) SetSWPR_P12WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x1000)|value<<12)
}
func (o *SYSCFG_Type) GetSWPR_P12WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x1000) >> 12
}
func (o *SYSCFG_Type) SetSWPR_P11WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x800)|value<<11)
}
func (o *SYSCFG_Type) GetSWPR_P11WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x800) >> 11
}
func (o *SYSCFG_Type) SetSWPR_P10WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x400)|value<<10)
}
func (o *SYSCFG_Type) GetSWPR_P10WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x400) >> 10
}
func (o *SYSCFG_Type) SetSWPR_P9WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x200)|value<<9)
}
func (o *SYSCFG_Type) GetSWPR_P9WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x200) >> 9
}
func (o *SYSCFG_Type) SetSWPR_P8WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetSWPR_P8WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x100) >> 8
}
func (o *SYSCFG_Type) SetSWPR_P7WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x80)|value<<7)
}
func (o *SYSCFG_Type) GetSWPR_P7WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x80) >> 7
}
func (o *SYSCFG_Type) SetSWPR_P6WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x40)|value<<6)
}
func (o *SYSCFG_Type) GetSWPR_P6WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x40) >> 6
}
func (o *SYSCFG_Type) SetSWPR_P5WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x20)|value<<5)
}
func (o *SYSCFG_Type) GetSWPR_P5WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x20) >> 5
}
func (o *SYSCFG_Type) SetSWPR_P4WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x10)|value<<4)
}
func (o *SYSCFG_Type) GetSWPR_P4WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x10) >> 4
}
func (o *SYSCFG_Type) SetSWPR_P3WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetSWPR_P3WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetSWPR_P2WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetSWPR_P2WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetSWPR_P1WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetSWPR_P1WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetSWPR_P0WP(value uint32) {
	volatile.StoreUint32(&o.SWPR.Reg, volatile.LoadUint32(&o.SWPR.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetSWPR_P0WP() uint32 {
	return volatile.LoadUint32(&o.SWPR.Reg) & 0x1
}

// SYSCFG.SWPR2: SWPR2
func (o *SYSCFG_Type) SetSWPR2_P32WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x1)|value)
}
func (o *SYSCFG_Type) GetSWPR2_P32WP() uint32 {
	return volatile.LoadUint32(&o.SWPR2.Reg) & 0x1
}
func (o *SYSCFG_Type) SetSWPR2_P33WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x2)|value<<1)
}
func (o *SYSCFG_Type) GetSWPR2_P33WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x2) >> 1
}
func (o *SYSCFG_Type) SetSWPR2_P34WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x4)|value<<2)
}
func (o *SYSCFG_Type) GetSWPR2_P34WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x4) >> 2
}
func (o *SYSCFG_Type) SetSWPR2_P35WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x8)|value<<3)
}
func (o *SYSCFG_Type) GetSWPR2_P35WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x8) >> 3
}
func (o *SYSCFG_Type) SetSWPR2_P36WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x10)|value<<4)
}
func (o *SYSCFG_Type) GetSWPR2_P36WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x10) >> 4
}
func (o *SYSCFG_Type) SetSWPR2_P37WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x20)|value<<5)
}
func (o *SYSCFG_Type) GetSWPR2_P37WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x20) >> 5
}
func (o *SYSCFG_Type) SetSWPR2_P38WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x40)|value<<6)
}
func (o *SYSCFG_Type) GetSWPR2_P38WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x40) >> 6
}
func (o *SYSCFG_Type) SetSWPR2_P39WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x80)|value<<7)
}
func (o *SYSCFG_Type) GetSWPR2_P39WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x80) >> 7
}
func (o *SYSCFG_Type) SetSWPR2_P40WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x100)|value<<8)
}
func (o *SYSCFG_Type) GetSWPR2_P40WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x100) >> 8
}
func (o *SYSCFG_Type) SetSWPR2_P41WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x200)|value<<9)
}
func (o *SYSCFG_Type) GetSWPR2_P41WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x200) >> 9
}
func (o *SYSCFG_Type) SetSWPR2_P42WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x400)|value<<10)
}
func (o *SYSCFG_Type) GetSWPR2_P42WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x400) >> 10
}
func (o *SYSCFG_Type) SetSWPR2_P43WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x800)|value<<11)
}
func (o *SYSCFG_Type) GetSWPR2_P43WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x800) >> 11
}
func (o *SYSCFG_Type) SetSWPR2_P44WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x1000)|value<<12)
}
func (o *SYSCFG_Type) GetSWPR2_P44WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x1000) >> 12
}
func (o *SYSCFG_Type) SetSWPR2_P45WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x2000)|value<<13)
}
func (o *SYSCFG_Type) GetSWPR2_P45WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x2000) >> 13
}
func (o *SYSCFG_Type) SetSWPR2_P46WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x4000)|value<<14)
}
func (o *SYSCFG_Type) GetSWPR2_P46WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x4000) >> 14
}
func (o *SYSCFG_Type) SetSWPR2_P47WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x8000)|value<<15)
}
func (o *SYSCFG_Type) GetSWPR2_P47WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x8000) >> 15
}
func (o *SYSCFG_Type) SetSWPR2_P48WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x10000)|value<<16)
}
func (o *SYSCFG_Type) GetSWPR2_P48WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x10000) >> 16
}
func (o *SYSCFG_Type) SetSWPR2_P49WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x20000)|value<<17)
}
func (o *SYSCFG_Type) GetSWPR2_P49WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x20000) >> 17
}
func (o *SYSCFG_Type) SetSWPR2_P50WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x40000)|value<<18)
}
func (o *SYSCFG_Type) GetSWPR2_P50WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x40000) >> 18
}
func (o *SYSCFG_Type) SetSWPR2_P51WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x80000)|value<<19)
}
func (o *SYSCFG_Type) GetSWPR2_P51WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x80000) >> 19
}
func (o *SYSCFG_Type) SetSWPR2_P52WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x100000)|value<<20)
}
func (o *SYSCFG_Type) GetSWPR2_P52WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x100000) >> 20
}
func (o *SYSCFG_Type) SetSWPR2_P53WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x200000)|value<<21)
}
func (o *SYSCFG_Type) GetSWPR2_P53WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x200000) >> 21
}
func (o *SYSCFG_Type) SetSWPR2_P54WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x400000)|value<<22)
}
func (o *SYSCFG_Type) GetSWPR2_P54WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x400000) >> 22
}
func (o *SYSCFG_Type) SetSWPR2_P55WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x800000)|value<<23)
}
func (o *SYSCFG_Type) GetSWPR2_P55WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x800000) >> 23
}
func (o *SYSCFG_Type) SetSWPR2_P56WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x1000000)|value<<24)
}
func (o *SYSCFG_Type) GetSWPR2_P56WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x1000000) >> 24
}
func (o *SYSCFG_Type) SetSWPR2_P57WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x2000000)|value<<25)
}
func (o *SYSCFG_Type) GetSWPR2_P57WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x2000000) >> 25
}
func (o *SYSCFG_Type) SetSWPR2_P58WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x4000000)|value<<26)
}
func (o *SYSCFG_Type) GetSWPR2_P58WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x4000000) >> 26
}
func (o *SYSCFG_Type) SetSWPR2_P59WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x8000000)|value<<27)
}
func (o *SYSCFG_Type) GetSWPR2_P59WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x8000000) >> 27
}
func (o *SYSCFG_Type) SetSWPR2_P60WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x10000000)|value<<28)
}
func (o *SYSCFG_Type) GetSWPR2_P60WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x10000000) >> 28
}
func (o *SYSCFG_Type) SetSWPR2_P61WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x20000000)|value<<29)
}
func (o *SYSCFG_Type) GetSWPR2_P61WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x20000000) >> 29
}
func (o *SYSCFG_Type) SetSWPR2_P62WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x40000000)|value<<30)
}
func (o *SYSCFG_Type) GetSWPR2_P62WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x40000000) >> 30
}
func (o *SYSCFG_Type) SetSWPR2_P63WP(value uint32) {
	volatile.StoreUint32(&o.SWPR2.Reg, volatile.LoadUint32(&o.SWPR2.Reg)&^(0x80000000)|value<<31)
}
func (o *SYSCFG_Type) GetSWPR2_P63WP() uint32 {
	return (volatile.LoadUint32(&o.SWPR2.Reg) & 0x80000000) >> 31
}

// SYSCFG.RSSCMDR: RSSCMDR
func (o *SYSCFG_Type) SetRSSCMDR_RSSCMD(value uint32) {
	volatile.StoreUint32(&o.RSSCMDR.Reg, volatile.LoadUint32(&o.RSSCMDR.Reg)&^(0xff)|value)
}
func (o *SYSCFG_Type) GetRSSCMDR_RSSCMD() uint32 {
	return volatile.LoadUint32(&o.RSSCMDR.Reg) & 0xff
}

// Tamper and backup registers
type TAMP_Type struct {
	CR1     volatile.Register32 // 0x0
	CR2     volatile.Register32 // 0x4
	CR3     volatile.Register32 // 0x8
	FLTCR   volatile.Register32 // 0xC
	ATCR1   volatile.Register32 // 0x10
	ATSEEDR volatile.Register32 // 0x14
	ATOR    volatile.Register32 // 0x18
	ATCR2   volatile.Register32 // 0x1C
	SMCR    volatile.Register32 // 0x20
	PRIVCR  volatile.Register32 // 0x24
	_       [4]byte
	IER     volatile.Register32 // 0x2C
	SR      volatile.Register32 // 0x30
	MISR    volatile.Register32 // 0x34
	SMISR   volatile.Register32 // 0x38
	SCR     volatile.Register32 // 0x3C
	COUNTR  volatile.Register32 // 0x40
	_       [12]byte
	CFGR    volatile.Register32 // 0x50
	_       [172]byte
	BKP0R   volatile.Register32 // 0x100
	BKP1R   volatile.Register32 // 0x104
	BKP2R   volatile.Register32 // 0x108
	BKP3R   volatile.Register32 // 0x10C
	BKP4R   volatile.Register32 // 0x110
	BKP5R   volatile.Register32 // 0x114
	BKP6R   volatile.Register32 // 0x118
	BKP7R   volatile.Register32 // 0x11C
	BKP8R   volatile.Register32 // 0x120
	BKP9R   volatile.Register32 // 0x124
	BKP10R  volatile.Register32 // 0x128
	BKP11R  volatile.Register32 // 0x12C
	BKP12R  volatile.Register32 // 0x130
	BKP13R  volatile.Register32 // 0x134
	BKP14R  volatile.Register32 // 0x138
	BKP15R  volatile.Register32 // 0x13C
	BKP16R  volatile.Register32 // 0x140
	BKP17R  volatile.Register32 // 0x144
	BKP18R  volatile.Register32 // 0x148
	BKP19R  volatile.Register32 // 0x14C
	BKP20R  volatile.Register32 // 0x150
	BKP21R  volatile.Register32 // 0x154
	BKP22R  volatile.Register32 // 0x158
	BKP23R  volatile.Register32 // 0x15C
	BKP24R  volatile.Register32 // 0x160
	BKP25R  volatile.Register32 // 0x164
	BKP26R  volatile.Register32 // 0x168
	BKP27R  volatile.Register32 // 0x16C
	BKP28R  volatile.Register32 // 0x170
	BKP29R  volatile.Register32 // 0x174
	BKP30R  volatile.Register32 // 0x178
	BKP31R  volatile.Register32 // 0x17C
}

// TAMP.CR1: control register 1
func (o *TAMP_Type) SetCR1_TAMP1E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR1_TAMP1E() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *TAMP_Type) SetCR1_TAMP2E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR1_TAMP2E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR1_TAMP3E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR1_TAMP3E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR1_TAMP4E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetCR1_TAMP4E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetCR1_TAMP5E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetCR1_TAMP5E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetCR1_TAMP6E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetCR1_TAMP6E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetCR1_TAMP7E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetCR1_TAMP7E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetCR1_TAMP8E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetCR1_TAMP8E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetCR1_ITAMP1E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetCR1_ITAMP1E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetCR1_ITAMP2E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetCR1_ITAMP2E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetCR1_ITAMP3E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetCR1_ITAMP3E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetCR1_ITAMP5E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetCR1_ITAMP5E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetCR1_ITAMP8E(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetCR1_ITAMP8E() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800000) >> 23
}

// TAMP.CR2: control register 2
func (o *TAMP_Type) SetCR2_TAMP1NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR2_TAMP1NOER() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *TAMP_Type) SetCR2_TAMP2NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR2_TAMP2NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR2_TAMP3NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR2_TAMP3NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR2_TAMP4NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetCR2_TAMP4NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetCR2_TAMP5NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetCR2_TAMP5NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetCR2_TAMP6NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetCR2_TAMP6NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetCR2_TAMP7NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetCR2_TAMP7NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetCR2_TAMP8NOER(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetCR2_TAMP8NOER() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetCR2_TAMP1MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetCR2_TAMP1MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetCR2_TAMP2MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetCR2_TAMP2MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetCR2_TAMP3MSK(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetCR2_TAMP3MSK() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetCR2_BKERASE(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetCR2_BKERASE() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800000) >> 23
}
func (o *TAMP_Type) SetCR2_TAMP1TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000000)|value<<24)
}
func (o *TAMP_Type) GetCR2_TAMP1TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000000) >> 24
}
func (o *TAMP_Type) SetCR2_TAMP2TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000000)|value<<25)
}
func (o *TAMP_Type) GetCR2_TAMP2TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000000) >> 25
}
func (o *TAMP_Type) SetCR2_TAMP3TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000000)|value<<26)
}
func (o *TAMP_Type) GetCR2_TAMP3TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000000) >> 26
}
func (o *TAMP_Type) SetCR2_TAMP4TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000000)|value<<27)
}
func (o *TAMP_Type) GetCR2_TAMP4TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000000) >> 27
}
func (o *TAMP_Type) SetCR2_TAMP5TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000000)|value<<28)
}
func (o *TAMP_Type) GetCR2_TAMP5TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000000) >> 28
}
func (o *TAMP_Type) SetCR2_TAMP6TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x20000000)|value<<29)
}
func (o *TAMP_Type) GetCR2_TAMP6TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x20000000) >> 29
}
func (o *TAMP_Type) SetCR2_TAMP7TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000000)|value<<30)
}
func (o *TAMP_Type) GetCR2_TAMP7TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000000) >> 30
}
func (o *TAMP_Type) SetCR2_TAMP8TRG(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetCR2_TAMP8TRG() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80000000) >> 31
}

// TAMP.CR3: control register 3
func (o *TAMP_Type) SetCR3_ITAMP1NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetCR3_ITAMP1NOER() uint32 {
	return volatile.LoadUint32(&o.CR3.Reg) & 0x1
}
func (o *TAMP_Type) SetCR3_ITAMP2NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCR3_ITAMP2NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCR3_ITAMP3NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCR3_ITAMP3NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCR3_ITAMP5NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetCR3_ITAMP5NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetCR3_ITAMP8NOER(value uint32) {
	volatile.StoreUint32(&o.CR3.Reg, volatile.LoadUint32(&o.CR3.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetCR3_ITAMP8NOER() uint32 {
	return (volatile.LoadUint32(&o.CR3.Reg) & 0x80) >> 7
}

// TAMP.FLTCR: TAMP filter control register
func (o *TAMP_Type) SetFLTCR_TAMPFREQ(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x7)|value)
}
func (o *TAMP_Type) GetFLTCR_TAMPFREQ() uint32 {
	return volatile.LoadUint32(&o.FLTCR.Reg) & 0x7
}
func (o *TAMP_Type) SetFLTCR_TAMPFLT(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x18)|value<<3)
}
func (o *TAMP_Type) GetFLTCR_TAMPFLT() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x18) >> 3
}
func (o *TAMP_Type) SetFLTCR_TAMPPRCH(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x60)|value<<5)
}
func (o *TAMP_Type) GetFLTCR_TAMPPRCH() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x60) >> 5
}
func (o *TAMP_Type) SetFLTCR_TAMPPUDIS(value uint32) {
	volatile.StoreUint32(&o.FLTCR.Reg, volatile.LoadUint32(&o.FLTCR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetFLTCR_TAMPPUDIS() uint32 {
	return (volatile.LoadUint32(&o.FLTCR.Reg) & 0x80) >> 7
}

// TAMP.ATCR1: TAMP active tamper control register 1
func (o *TAMP_Type) SetATCR1_TAMP1AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetATCR1_TAMP1AM() uint32 {
	return volatile.LoadUint32(&o.ATCR1.Reg) & 0x1
}
func (o *TAMP_Type) SetATCR1_TAMP2AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetATCR1_TAMP2AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetATCR1_TAMP3AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetATCR1_TAMP3AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetATCR1_TAMP4AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetATCR1_TAMP4AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetATCR1_TAMP5AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetATCR1_TAMP5AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetATCR1_TAMP6AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetATCR1_TAMP6AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetATCR1_TAMP7AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetATCR1_TAMP7AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetATCR1_TAMP8AM(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetATCR1_TAMP8AM() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetATCR1_ATOSEL1(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x300)|value<<8)
}
func (o *TAMP_Type) GetATCR1_ATOSEL1() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x300) >> 8
}
func (o *TAMP_Type) SetATCR1_ATOSEL2(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0xc00)|value<<10)
}
func (o *TAMP_Type) GetATCR1_ATOSEL2() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0xc00) >> 10
}
func (o *TAMP_Type) SetATCR1_ATOSEL3(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x3000)|value<<12)
}
func (o *TAMP_Type) GetATCR1_ATOSEL3() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x3000) >> 12
}
func (o *TAMP_Type) SetATCR1_ATOSEL4(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0xc000)|value<<14)
}
func (o *TAMP_Type) GetATCR1_ATOSEL4() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0xc000) >> 14
}
func (o *TAMP_Type) SetATCR1_ATCKSEL(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x30000)|value<<16)
}
func (o *TAMP_Type) GetATCR1_ATCKSEL() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x30000) >> 16
}
func (o *TAMP_Type) SetATCR1_ATPER(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x3000000)|value<<24)
}
func (o *TAMP_Type) GetATCR1_ATPER() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x3000000) >> 24
}
func (o *TAMP_Type) SetATCR1_ATOSHARE(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x40000000)|value<<30)
}
func (o *TAMP_Type) GetATCR1_ATOSHARE() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x40000000) >> 30
}
func (o *TAMP_Type) SetATCR1_FLTEN(value uint32) {
	volatile.StoreUint32(&o.ATCR1.Reg, volatile.LoadUint32(&o.ATCR1.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetATCR1_FLTEN() uint32 {
	return (volatile.LoadUint32(&o.ATCR1.Reg) & 0x80000000) >> 31
}

// TAMP.ATSEEDR: TAMP active tamper seed register
func (o *TAMP_Type) SetATSEEDR(value uint32) {
	volatile.StoreUint32(&o.ATSEEDR.Reg, value)
}
func (o *TAMP_Type) GetATSEEDR() uint32 {
	return volatile.LoadUint32(&o.ATSEEDR.Reg)
}

// TAMP.ATOR: TAMP active tamper output register
func (o *TAMP_Type) SetATOR_PRNG(value uint32) {
	volatile.StoreUint32(&o.ATOR.Reg, volatile.LoadUint32(&o.ATOR.Reg)&^(0xff)|value)
}
func (o *TAMP_Type) GetATOR_PRNG() uint32 {
	return volatile.LoadUint32(&o.ATOR.Reg) & 0xff
}
func (o *TAMP_Type) SetATOR_SEEDF(value uint32) {
	volatile.StoreUint32(&o.ATOR.Reg, volatile.LoadUint32(&o.ATOR.Reg)&^(0x4000)|value<<14)
}
func (o *TAMP_Type) GetATOR_SEEDF() uint32 {
	return (volatile.LoadUint32(&o.ATOR.Reg) & 0x4000) >> 14
}
func (o *TAMP_Type) SetATOR_INITS(value uint32) {
	volatile.StoreUint32(&o.ATOR.Reg, volatile.LoadUint32(&o.ATOR.Reg)&^(0x8000)|value<<15)
}
func (o *TAMP_Type) GetATOR_INITS() uint32 {
	return (volatile.LoadUint32(&o.ATOR.Reg) & 0x8000) >> 15
}

// TAMP.ATCR2: TAMP active tamper control register 2
func (o *TAMP_Type) SetATCR2_ATOSEL1(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x700)|value<<8)
}
func (o *TAMP_Type) GetATCR2_ATOSEL1() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x700) >> 8
}
func (o *TAMP_Type) SetATCR2_ATOSEL2(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x3800)|value<<11)
}
func (o *TAMP_Type) GetATCR2_ATOSEL2() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x3800) >> 11
}
func (o *TAMP_Type) SetATCR2_ATOSEL3(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x1c000)|value<<14)
}
func (o *TAMP_Type) GetATCR2_ATOSEL3() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x1c000) >> 14
}
func (o *TAMP_Type) SetATCR2_ATOSEL4(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0xe0000)|value<<17)
}
func (o *TAMP_Type) GetATCR2_ATOSEL4() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0xe0000) >> 17
}
func (o *TAMP_Type) SetATCR2_ATOSEL5(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x700000)|value<<20)
}
func (o *TAMP_Type) GetATCR2_ATOSEL5() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x700000) >> 20
}
func (o *TAMP_Type) SetATCR2_ATOSEL6(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x3800000)|value<<23)
}
func (o *TAMP_Type) GetATCR2_ATOSEL6() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x3800000) >> 23
}
func (o *TAMP_Type) SetATCR2_ATOSEL7(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0x1c000000)|value<<26)
}
func (o *TAMP_Type) GetATCR2_ATOSEL7() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0x1c000000) >> 26
}
func (o *TAMP_Type) SetATCR2_ATOSEL8(value uint32) {
	volatile.StoreUint32(&o.ATCR2.Reg, volatile.LoadUint32(&o.ATCR2.Reg)&^(0xe0000000)|value<<29)
}
func (o *TAMP_Type) GetATCR2_ATOSEL8() uint32 {
	return (volatile.LoadUint32(&o.ATCR2.Reg) & 0xe0000000) >> 29
}

// TAMP.SMCR: TAMP secure mode register
func (o *TAMP_Type) SetSMCR_BKPRWDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0xff)|value)
}
func (o *TAMP_Type) GetSMCR_BKPRWDPROT() uint32 {
	return volatile.LoadUint32(&o.SMCR.Reg) & 0xff
}
func (o *TAMP_Type) SetSMCR_BKPWDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0xff0000)|value<<16)
}
func (o *TAMP_Type) GetSMCR_BKPWDPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0xff0000) >> 16
}
func (o *TAMP_Type) SetSMCR_TAMPDPROT(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetSMCR_TAMPDPROT() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x80000000) >> 31
}

// TAMP.PRIVCR: TAMP privilege mode control register
func (o *TAMP_Type) SetPRIVCR_BKPRWPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TAMP_Type) GetPRIVCR_BKPRWPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x20000000) >> 29
}
func (o *TAMP_Type) SetPRIVCR_BKPWPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TAMP_Type) GetPRIVCR_BKPWPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x40000000) >> 30
}
func (o *TAMP_Type) SetPRIVCR_TAMPPRIV(value uint32) {
	volatile.StoreUint32(&o.PRIVCR.Reg, volatile.LoadUint32(&o.PRIVCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TAMP_Type) GetPRIVCR_TAMPPRIV() uint32 {
	return (volatile.LoadUint32(&o.PRIVCR.Reg) & 0x80000000) >> 31
}

// TAMP.IER: TAMP interrupt enable register
func (o *TAMP_Type) SetIER_TAMP1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetIER_TAMP1IE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}
func (o *TAMP_Type) SetIER_TAMP2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetIER_TAMP2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetIER_TAMP3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetIER_TAMP3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetIER_TAMP4IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetIER_TAMP4IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetIER_TAMP5IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetIER_TAMP5IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetIER_TAMP6IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetIER_TAMP6IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetIER_TAMP7IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetIER_TAMP7IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetIER_TAMP8IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetIER_TAMP8IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetIER_ITAMP1IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetIER_ITAMP1IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetIER_ITAMP2IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetIER_ITAMP2IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetIER_ITAMP3IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetIER_ITAMP3IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetIER_ITAMP5IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetIER_ITAMP5IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetIER_ITAMP8IE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetIER_ITAMP8IE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x800000) >> 23
}

// TAMP.SR: TAMP status register
func (o *TAMP_Type) SetSR_TAMP1F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSR_TAMP1F() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *TAMP_Type) SetSR_TAMP2F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSR_TAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSR_TAMP3F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSR_TAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSR_TAMP4F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetSR_TAMP4F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetSR_TAMP5F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetSR_TAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetSR_TAMP6F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetSR_TAMP6F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetSR_TAMP7F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetSR_TAMP7F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetSR_TAMP8F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetSR_TAMP8F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetSR_ITAMP1F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetSR_ITAMP1F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetSR_ITAMP2F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetSR_ITAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetSR_ITAMP3F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSR_ITAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSR_ITAMP5F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSR_ITAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSR_ITAMP8F(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetSR_ITAMP8F() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800000) >> 23
}

// TAMP.MISR: TAMP masked interrupt status register
func (o *TAMP_Type) SetMISR_TAMP1MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetMISR_TAMP1MF() uint32 {
	return volatile.LoadUint32(&o.MISR.Reg) & 0x1
}
func (o *TAMP_Type) SetMISR_TAMP2MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetMISR_TAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetMISR_TAMP3MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetMISR_TAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetMISR_TAMP4MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetMISR_TAMP4MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetMISR_TAMP5MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetMISR_TAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetMISR_TAMP6MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetMISR_TAMP6MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetMISR_TAMP7MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetMISR_TAMP7MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetMISR_TAMP8MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetMISR_TAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetMISR_ITAMP1MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetMISR_ITAMP1MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetMISR_ITAMP2MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetMISR_ITAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetMISR_ITAMP3MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetMISR_ITAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetMISR_ITAMP5MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetMISR_ITAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetMISR_ITAMP8MF(value uint32) {
	volatile.StoreUint32(&o.MISR.Reg, volatile.LoadUint32(&o.MISR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetMISR_ITAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.MISR.Reg) & 0x800000) >> 23
}

// TAMP.SMISR: TAMP secure masked interrupt status register
func (o *TAMP_Type) SetSMISR_TAMP1MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSMISR_TAMP1MF() uint32 {
	return volatile.LoadUint32(&o.SMISR.Reg) & 0x1
}
func (o *TAMP_Type) SetSMISR_TAMP2MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSMISR_TAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSMISR_TAMP3MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSMISR_TAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSMISR_TAMP4MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetSMISR_TAMP4MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetSMISR_TAMP5MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetSMISR_TAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetSMISR_TAMP6MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetSMISR_TAMP6MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetSMISR_TAMP7MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetSMISR_TAMP7MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetSMISR_TAMP8MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetSMISR_TAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetSMISR_ITAMP1MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetSMISR_ITAMP1MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetSMISR_ITAMP2MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetSMISR_ITAMP2MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetSMISR_ITAMP3MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSMISR_ITAMP3MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSMISR_ITAMP5MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSMISR_ITAMP5MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSMISR_ITAMP8MF(value uint32) {
	volatile.StoreUint32(&o.SMISR.Reg, volatile.LoadUint32(&o.SMISR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetSMISR_ITAMP8MF() uint32 {
	return (volatile.LoadUint32(&o.SMISR.Reg) & 0x800000) >> 23
}

// TAMP.SCR: TAMP status clear register
func (o *TAMP_Type) SetSCR_CTAMP1F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x1)|value)
}
func (o *TAMP_Type) GetSCR_CTAMP1F() uint32 {
	return volatile.LoadUint32(&o.SCR.Reg) & 0x1
}
func (o *TAMP_Type) SetSCR_CTAMP2F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetSCR_CTAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetSCR_CTAMP3F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetSCR_CTAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetSCR_CTAMP4F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetSCR_CTAMP4F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x8) >> 3
}
func (o *TAMP_Type) SetSCR_CTAMP5F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10)|value<<4)
}
func (o *TAMP_Type) GetSCR_CTAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10) >> 4
}
func (o *TAMP_Type) SetSCR_CTAMP6F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20)|value<<5)
}
func (o *TAMP_Type) GetSCR_CTAMP6F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20) >> 5
}
func (o *TAMP_Type) SetSCR_CTAMP7F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x40)|value<<6)
}
func (o *TAMP_Type) GetSCR_CTAMP7F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x40) >> 6
}
func (o *TAMP_Type) SetSCR_CTAMP8F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x80)|value<<7)
}
func (o *TAMP_Type) GetSCR_CTAMP8F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x80) >> 7
}
func (o *TAMP_Type) SetSCR_CITAMP1F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x10000)|value<<16)
}
func (o *TAMP_Type) GetSCR_CITAMP1F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x10000) >> 16
}
func (o *TAMP_Type) SetSCR_CITAMP2F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x20000)|value<<17)
}
func (o *TAMP_Type) GetSCR_CITAMP2F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x20000) >> 17
}
func (o *TAMP_Type) SetSCR_CITAMP3F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x40000)|value<<18)
}
func (o *TAMP_Type) GetSCR_CITAMP3F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x40000) >> 18
}
func (o *TAMP_Type) SetSCR_CITAMP5F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x100000)|value<<20)
}
func (o *TAMP_Type) GetSCR_CITAMP5F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x100000) >> 20
}
func (o *TAMP_Type) SetSCR_CITAMP8F(value uint32) {
	volatile.StoreUint32(&o.SCR.Reg, volatile.LoadUint32(&o.SCR.Reg)&^(0x800000)|value<<23)
}
func (o *TAMP_Type) GetSCR_CITAMP8F() uint32 {
	return (volatile.LoadUint32(&o.SCR.Reg) & 0x800000) >> 23
}

// TAMP.COUNTR: TAMP monotonic counter register
func (o *TAMP_Type) SetCOUNTR(value uint32) {
	volatile.StoreUint32(&o.COUNTR.Reg, value)
}
func (o *TAMP_Type) GetCOUNTR() uint32 {
	return volatile.LoadUint32(&o.COUNTR.Reg)
}

// TAMP.CFGR: TAMP configuration register
func (o *TAMP_Type) SetCFGR_TMONEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x2)|value<<1)
}
func (o *TAMP_Type) GetCFGR_TMONEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x2) >> 1
}
func (o *TAMP_Type) SetCFGR_VMONEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x4)|value<<2)
}
func (o *TAMP_Type) GetCFGR_VMONEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x4) >> 2
}
func (o *TAMP_Type) SetCFGR_WUTMONEN(value uint32) {
	volatile.StoreUint32(&o.CFGR.Reg, volatile.LoadUint32(&o.CFGR.Reg)&^(0x8)|value<<3)
}
func (o *TAMP_Type) GetCFGR_WUTMONEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR.Reg) & 0x8) >> 3
}

// TAMP.BKP0R: TAMP backup register
func (o *TAMP_Type) SetBKP0R(value uint32) {
	volatile.StoreUint32(&o.BKP0R.Reg, value)
}
func (o *TAMP_Type) GetBKP0R() uint32 {
	return volatile.LoadUint32(&o.BKP0R.Reg)
}

// TAMP.BKP1R: TAMP backup register
func (o *TAMP_Type) SetBKP1R(value uint32) {
	volatile.StoreUint32(&o.BKP1R.Reg, value)
}
func (o *TAMP_Type) GetBKP1R() uint32 {
	return volatile.LoadUint32(&o.BKP1R.Reg)
}

// TAMP.BKP2R: TAMP backup register
func (o *TAMP_Type) SetBKP2R(value uint32) {
	volatile.StoreUint32(&o.BKP2R.Reg, value)
}
func (o *TAMP_Type) GetBKP2R() uint32 {
	return volatile.LoadUint32(&o.BKP2R.Reg)
}

// TAMP.BKP3R: TAMP backup register
func (o *TAMP_Type) SetBKP3R(value uint32) {
	volatile.StoreUint32(&o.BKP3R.Reg, value)
}
func (o *TAMP_Type) GetBKP3R() uint32 {
	return volatile.LoadUint32(&o.BKP3R.Reg)
}

// TAMP.BKP4R: TAMP backup register
func (o *TAMP_Type) SetBKP4R(value uint32) {
	volatile.StoreUint32(&o.BKP4R.Reg, value)
}
func (o *TAMP_Type) GetBKP4R() uint32 {
	return volatile.LoadUint32(&o.BKP4R.Reg)
}

// TAMP.BKP5R: TAMP backup register
func (o *TAMP_Type) SetBKP5R(value uint32) {
	volatile.StoreUint32(&o.BKP5R.Reg, value)
}
func (o *TAMP_Type) GetBKP5R() uint32 {
	return volatile.LoadUint32(&o.BKP5R.Reg)
}

// TAMP.BKP6R: TAMP backup register
func (o *TAMP_Type) SetBKP6R(value uint32) {
	volatile.StoreUint32(&o.BKP6R.Reg, value)
}
func (o *TAMP_Type) GetBKP6R() uint32 {
	return volatile.LoadUint32(&o.BKP6R.Reg)
}

// TAMP.BKP7R: TAMP backup register
func (o *TAMP_Type) SetBKP7R(value uint32) {
	volatile.StoreUint32(&o.BKP7R.Reg, value)
}
func (o *TAMP_Type) GetBKP7R() uint32 {
	return volatile.LoadUint32(&o.BKP7R.Reg)
}

// TAMP.BKP8R: TAMP backup register
func (o *TAMP_Type) SetBKP8R(value uint32) {
	volatile.StoreUint32(&o.BKP8R.Reg, value)
}
func (o *TAMP_Type) GetBKP8R() uint32 {
	return volatile.LoadUint32(&o.BKP8R.Reg)
}

// TAMP.BKP9R: TAMP backup register
func (o *TAMP_Type) SetBKP9R(value uint32) {
	volatile.StoreUint32(&o.BKP9R.Reg, value)
}
func (o *TAMP_Type) GetBKP9R() uint32 {
	return volatile.LoadUint32(&o.BKP9R.Reg)
}

// TAMP.BKP10R: TAMP backup register
func (o *TAMP_Type) SetBKP10R(value uint32) {
	volatile.StoreUint32(&o.BKP10R.Reg, value)
}
func (o *TAMP_Type) GetBKP10R() uint32 {
	return volatile.LoadUint32(&o.BKP10R.Reg)
}

// TAMP.BKP11R: TAMP backup register
func (o *TAMP_Type) SetBKP11R(value uint32) {
	volatile.StoreUint32(&o.BKP11R.Reg, value)
}
func (o *TAMP_Type) GetBKP11R() uint32 {
	return volatile.LoadUint32(&o.BKP11R.Reg)
}

// TAMP.BKP12R: TAMP backup register
func (o *TAMP_Type) SetBKP12R(value uint32) {
	volatile.StoreUint32(&o.BKP12R.Reg, value)
}
func (o *TAMP_Type) GetBKP12R() uint32 {
	return volatile.LoadUint32(&o.BKP12R.Reg)
}

// TAMP.BKP13R: TAMP backup register
func (o *TAMP_Type) SetBKP13R(value uint32) {
	volatile.StoreUint32(&o.BKP13R.Reg, value)
}
func (o *TAMP_Type) GetBKP13R() uint32 {
	return volatile.LoadUint32(&o.BKP13R.Reg)
}

// TAMP.BKP14R: TAMP backup register
func (o *TAMP_Type) SetBKP14R(value uint32) {
	volatile.StoreUint32(&o.BKP14R.Reg, value)
}
func (o *TAMP_Type) GetBKP14R() uint32 {
	return volatile.LoadUint32(&o.BKP14R.Reg)
}

// TAMP.BKP15R: TAMP backup register
func (o *TAMP_Type) SetBKP15R(value uint32) {
	volatile.StoreUint32(&o.BKP15R.Reg, value)
}
func (o *TAMP_Type) GetBKP15R() uint32 {
	return volatile.LoadUint32(&o.BKP15R.Reg)
}

// TAMP.BKP16R: TAMP backup register
func (o *TAMP_Type) SetBKP16R(value uint32) {
	volatile.StoreUint32(&o.BKP16R.Reg, value)
}
func (o *TAMP_Type) GetBKP16R() uint32 {
	return volatile.LoadUint32(&o.BKP16R.Reg)
}

// TAMP.BKP17R: TAMP backup register
func (o *TAMP_Type) SetBKP17R(value uint32) {
	volatile.StoreUint32(&o.BKP17R.Reg, value)
}
func (o *TAMP_Type) GetBKP17R() uint32 {
	return volatile.LoadUint32(&o.BKP17R.Reg)
}

// TAMP.BKP18R: TAMP backup register
func (o *TAMP_Type) SetBKP18R(value uint32) {
	volatile.StoreUint32(&o.BKP18R.Reg, value)
}
func (o *TAMP_Type) GetBKP18R() uint32 {
	return volatile.LoadUint32(&o.BKP18R.Reg)
}

// TAMP.BKP19R: TAMP backup register
func (o *TAMP_Type) SetBKP19R(value uint32) {
	volatile.StoreUint32(&o.BKP19R.Reg, value)
}
func (o *TAMP_Type) GetBKP19R() uint32 {
	return volatile.LoadUint32(&o.BKP19R.Reg)
}

// TAMP.BKP20R: TAMP backup register
func (o *TAMP_Type) SetBKP20R(value uint32) {
	volatile.StoreUint32(&o.BKP20R.Reg, value)
}
func (o *TAMP_Type) GetBKP20R() uint32 {
	return volatile.LoadUint32(&o.BKP20R.Reg)
}

// TAMP.BKP21R: TAMP backup register
func (o *TAMP_Type) SetBKP21R(value uint32) {
	volatile.StoreUint32(&o.BKP21R.Reg, value)
}
func (o *TAMP_Type) GetBKP21R() uint32 {
	return volatile.LoadUint32(&o.BKP21R.Reg)
}

// TAMP.BKP22R: TAMP backup register
func (o *TAMP_Type) SetBKP22R(value uint32) {
	volatile.StoreUint32(&o.BKP22R.Reg, value)
}
func (o *TAMP_Type) GetBKP22R() uint32 {
	return volatile.LoadUint32(&o.BKP22R.Reg)
}

// TAMP.BKP23R: TAMP backup register
func (o *TAMP_Type) SetBKP23R(value uint32) {
	volatile.StoreUint32(&o.BKP23R.Reg, value)
}
func (o *TAMP_Type) GetBKP23R() uint32 {
	return volatile.LoadUint32(&o.BKP23R.Reg)
}

// TAMP.BKP24R: TAMP backup register
func (o *TAMP_Type) SetBKP24R(value uint32) {
	volatile.StoreUint32(&o.BKP24R.Reg, value)
}
func (o *TAMP_Type) GetBKP24R() uint32 {
	return volatile.LoadUint32(&o.BKP24R.Reg)
}

// TAMP.BKP25R: TAMP backup register
func (o *TAMP_Type) SetBKP25R(value uint32) {
	volatile.StoreUint32(&o.BKP25R.Reg, value)
}
func (o *TAMP_Type) GetBKP25R() uint32 {
	return volatile.LoadUint32(&o.BKP25R.Reg)
}

// TAMP.BKP26R: TAMP backup register
func (o *TAMP_Type) SetBKP26R(value uint32) {
	volatile.StoreUint32(&o.BKP26R.Reg, value)
}
func (o *TAMP_Type) GetBKP26R() uint32 {
	return volatile.LoadUint32(&o.BKP26R.Reg)
}

// TAMP.BKP27R: TAMP backup register
func (o *TAMP_Type) SetBKP27R(value uint32) {
	volatile.StoreUint32(&o.BKP27R.Reg, value)
}
func (o *TAMP_Type) GetBKP27R() uint32 {
	return volatile.LoadUint32(&o.BKP27R.Reg)
}

// TAMP.BKP28R: TAMP backup register
func (o *TAMP_Type) SetBKP28R(value uint32) {
	volatile.StoreUint32(&o.BKP28R.Reg, value)
}
func (o *TAMP_Type) GetBKP28R() uint32 {
	return volatile.LoadUint32(&o.BKP28R.Reg)
}

// TAMP.BKP29R: TAMP backup register
func (o *TAMP_Type) SetBKP29R(value uint32) {
	volatile.StoreUint32(&o.BKP29R.Reg, value)
}
func (o *TAMP_Type) GetBKP29R() uint32 {
	return volatile.LoadUint32(&o.BKP29R.Reg)
}

// TAMP.BKP30R: TAMP backup register
func (o *TAMP_Type) SetBKP30R(value uint32) {
	volatile.StoreUint32(&o.BKP30R.Reg, value)
}
func (o *TAMP_Type) GetBKP30R() uint32 {
	return volatile.LoadUint32(&o.BKP30R.Reg)
}

// TAMP.BKP31R: TAMP backup register
func (o *TAMP_Type) SetBKP31R(value uint32) {
	volatile.StoreUint32(&o.BKP31R.Reg, value)
}
func (o *TAMP_Type) GetBKP31R() uint32 {
	return volatile.LoadUint32(&o.BKP31R.Reg)
}

// Advanced-timers
type TIM_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	SMCR         volatile.Register32 // 0x8
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	CCMR2_Output volatile.Register32 // 0x1C
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	CCR2         volatile.Register32 // 0x38
	CCR3         volatile.Register32 // 0x3C
	CCR4         volatile.Register32 // 0x40
	BDTR         volatile.Register32 // 0x44
	DCR          volatile.Register32 // 0x48
	DMAR         volatile.Register32 // 0x4C
	OR1          volatile.Register32 // 0x50
	CCMR3_Output volatile.Register32 // 0x54
	CCR5         volatile.Register32 // 0x58
	CCR6         volatile.Register32 // 0x5C
	OR2          volatile.Register32 // 0x60
	OR3          volatile.Register32 // 0x64
}

// TIM.CR1: control register 1
func (o *TIM_Type) SetCR1_CKD(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCR1_CKD() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCR1_ARPE(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR1_ARPE() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCR1_CMS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x60)|value<<5)
}
func (o *TIM_Type) GetCR1_CMS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x60) >> 5
}
func (o *TIM_Type) SetCR1_DIR(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCR1_DIR() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCR1_OPM(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR1_OPM() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR1_URS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetCR1_URS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetCR1_UDIS(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetCR1_UDIS() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetCR1_CEN(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetCR1_CEN() uint32 {
	return volatile.LoadUint32(&o.CR1.Reg) & 0x1
}
func (o *TIM_Type) SetCR1_UIFREMAP(value uint32) {
	volatile.StoreUint32(&o.CR1.Reg, volatile.LoadUint32(&o.CR1.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCR1_UIFREMAP() uint32 {
	return (volatile.LoadUint32(&o.CR1.Reg) & 0x800) >> 11
}

// TIM.CR2: control register 2
func (o *TIM_Type) SetCR2_OIS1(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCR2_OIS1() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCR2_OIS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCR2_OIS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCR2_OIS3(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetCR2_OIS3() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetCR2_OIS4(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetCR2_OIS4() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetCR2_OIS5(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCR2_OIS5() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCR2_OIS6(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetCR2_OIS6() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetCR2_OIS1N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCR2_OIS1N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCR2_OIS2N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetCR2_OIS2N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetCR2_OIS3N(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCR2_OIS3N() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCR2_TI1S(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCR2_TI1S() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCR2_MMS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetCR2_MMS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetCR2_CCDS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetCR2_CCDS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetCR2_CCUS(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetCR2_CCUS() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetCR2_CCPC(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetCR2_CCPC() uint32 {
	return volatile.LoadUint32(&o.CR2.Reg) & 0x1
}
func (o *TIM_Type) SetCR2_MMS2(value uint32) {
	volatile.StoreUint32(&o.CR2.Reg, volatile.LoadUint32(&o.CR2.Reg)&^(0xf00000)|value<<20)
}
func (o *TIM_Type) GetCR2_MMS2() uint32 {
	return (volatile.LoadUint32(&o.CR2.Reg) & 0xf00000) >> 20
}

// TIM.SMCR: slave mode control register
func (o *TIM_Type) SetSMCR_ETP(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetSMCR_ETP() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetSMCR_ECE(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetSMCR_ECE() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetSMCR_ETPS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x3000)|value<<12)
}
func (o *TIM_Type) GetSMCR_ETPS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x3000) >> 12
}
func (o *TIM_Type) SetSMCR_ETF(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0xf00)|value<<8)
}
func (o *TIM_Type) GetSMCR_ETF() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0xf00) >> 8
}
func (o *TIM_Type) SetSMCR_MSM(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetSMCR_MSM() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetSMCR_TS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x70)|value<<4)
}
func (o *TIM_Type) GetSMCR_TS() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x70) >> 4
}
func (o *TIM_Type) SetSMCR_SMS(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x7)|value)
}
func (o *TIM_Type) GetSMCR_SMS() uint32 {
	return volatile.LoadUint32(&o.SMCR.Reg) & 0x7
}
func (o *TIM_Type) SetSMCR_SMS_3(value uint32) {
	volatile.StoreUint32(&o.SMCR.Reg, volatile.LoadUint32(&o.SMCR.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetSMCR_SMS_3() uint32 {
	return (volatile.LoadUint32(&o.SMCR.Reg) & 0x10000) >> 16
}

// TIM.DIER: DMA/Interrupt enable register
func (o *TIM_Type) SetDIER_TDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetDIER_TDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetDIER_COMDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetDIER_COMDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetDIER_CC1DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetDIER_CC1DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetDIER_CC2DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetDIER_CC2DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetDIER_CC3DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetDIER_CC3DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetDIER_CC4DE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetDIER_CC4DE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetDIER_UDE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetDIER_UDE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetDIER_TIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetDIER_TIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetDIER_CC1IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetDIER_CC1IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetDIER_CC2IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetDIER_CC2IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetDIER_CC3IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetDIER_CC3IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetDIER_CC4IE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetDIER_CC4IE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetDIER_UIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetDIER_UIE() uint32 {
	return volatile.LoadUint32(&o.DIER.Reg) & 0x1
}
func (o *TIM_Type) SetDIER_BIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetDIER_BIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetDIER_COMIE(value uint32) {
	volatile.StoreUint32(&o.DIER.Reg, volatile.LoadUint32(&o.DIER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetDIER_COMIE() uint32 {
	return (volatile.LoadUint32(&o.DIER.Reg) & 0x20) >> 5
}

// TIM.SR: status register
func (o *TIM_Type) SetSR_CC1OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetSR_CC1OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetSR_CC2OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetSR_CC2OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetSR_CC3OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetSR_CC3OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetSR_CC4OF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetSR_CC4OF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetSR_BIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetSR_BIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetSR_TIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetSR_TIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetSR_COMIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetSR_COMIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetSR_CC1IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetSR_CC1IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetSR_CC2IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetSR_CC2IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetSR_CC3IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetSR_CC3IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetSR_CC4IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetSR_CC4IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetSR_UIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetSR_UIF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *TIM_Type) SetSR_SBIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetSR_SBIF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetSR_CC5IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetSR_CC5IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetSR_CC6IF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetSR_CC6IF() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20000) >> 17
}

// TIM.EGR: event generation register
func (o *TIM_Type) SetEGR_BG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetEGR_BG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetEGR_TG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetEGR_TG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetEGR_COMG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetEGR_COMG() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetEGR_CC1G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetEGR_CC1G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetEGR_CC2G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x8)|value<<3)
}
func (o *TIM_Type) GetEGR_CC2G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x8) >> 3
}
func (o *TIM_Type) SetEGR_CC3G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetEGR_CC3G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetEGR_CC4G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetEGR_CC4G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetEGR_UG(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetEGR_UG() uint32 {
	return volatile.LoadUint32(&o.EGR.Reg) & 0x1
}
func (o *TIM_Type) SetEGR_B2G(value uint32) {
	volatile.StoreUint32(&o.EGR.Reg, volatile.LoadUint32(&o.EGR.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetEGR_B2G() uint32 {
	return (volatile.LoadUint32(&o.EGR.Reg) & 0x100) >> 8
}

// TIM.CCMR1_Output: capture/compare mode register 1 (output mode)
func (o *TIM_Type) SetCCMR1_Output_OC1CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR1_Output_OC1CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR1_Output_OC2CE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR1_Output_OC2CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR1_Output_OC1M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR1_Output_OC2M(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR1_Output_OC1PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR1_Output_OC1PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR1_Output_OC2PE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR1_Output_OC2PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR1_Output_OC1FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR1_Output_OC1FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR1_Output_OC2FE(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR1_Output_OC2FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR1_Output_CC1S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR1_Output_CC1S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR1_Output_CC2S(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR1_Output_CC2S() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x30000) >> 16
}
func (o *TIM_Type) SetCCMR1_Output_OC1M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR1_Output_OC1M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR1_Output_OC2M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR1_Output.Reg, volatile.LoadUint32(&o.CCMR1_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR1_Output_OC2M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR1_Output.Reg) & 0x0) >> 32
}

// TIM.CCMR2_Output: capture/compare mode register 2 (output mode)
func (o *TIM_Type) SetCCMR2_Output_OC3CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR2_Output_OC3CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR2_Output_OC4CE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR2_Output_OC4CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR2_Output_OC3M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR2_Output_OC4M(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR2_Output_OC3PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR2_Output_OC3PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR2_Output_OC4PE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR2_Output_OC4PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR2_Output_OC3FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR2_Output_OC3FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR2_Output_OC4FE(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR2_Output_OC4FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x40000) >> 18
}
func (o *TIM_Type) SetCCMR2_Output_CC3S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetCCMR2_Output_CC3S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetCCMR2_Output_CC4S(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x30000)|value<<16)
}
func (o *TIM_Type) GetCCMR2_Output_CC4S() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x30000) >> 16
}
func (o *TIM_Type) SetCCMR2_Output_OC3M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR2_Output_OC3M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR2_Output_OC4M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR2_Output.Reg, volatile.LoadUint32(&o.CCMR2_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR2_Output_OC4M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR2_Output.Reg) & 0x0) >> 32
}

// TIM.CCER: capture/compare enable register
func (o *TIM_Type) SetCCER_CC1P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20)|value<<5)
}
func (o *TIM_Type) GetCCER_CC1P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20) >> 5
}
func (o *TIM_Type) SetCCER_CC2P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetCCER_CC2P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetCCER_CC3P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetCCER_CC3P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetCCER_CC4P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x20000)|value<<17)
}
func (o *TIM_Type) GetCCER_CC4P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x20000) >> 17
}
func (o *TIM_Type) SetCCER_CC5P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x200000)|value<<21)
}
func (o *TIM_Type) GetCCER_CC5P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x200000) >> 21
}
func (o *TIM_Type) SetCCER_CC6P(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetCCER_CC6P() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetCCER_CC1E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetCCER_CC1E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10) >> 4
}
func (o *TIM_Type) SetCCER_CC2E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetCCER_CC2E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetCCER_CC3E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetCCER_CC3E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetCCER_CC4E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x10000)|value<<16)
}
func (o *TIM_Type) GetCCER_CC4E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x10000) >> 16
}
func (o *TIM_Type) SetCCER_CC5E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x100000)|value<<20)
}
func (o *TIM_Type) GetCCER_CC5E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x100000) >> 20
}
func (o *TIM_Type) SetCCER_CC6E(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCER_CC6E() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCER_CC1NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80)|value<<7)
}
func (o *TIM_Type) GetCCER_CC1NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80) >> 7
}
func (o *TIM_Type) SetCCER_CC2NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCER_CC2NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCER_CC3NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCER_CC3NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCER_CC4NP(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCER_CC4NP() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCER_CC1NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x40)|value<<6)
}
func (o *TIM_Type) GetCCER_CC1NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x40) >> 6
}
func (o *TIM_Type) SetCCER_CC2NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCER_CC2NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCER_CC3NE(value uint32) {
	volatile.StoreUint32(&o.CCER.Reg, volatile.LoadUint32(&o.CCER.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetCCER_CC3NE() uint32 {
	return (volatile.LoadUint32(&o.CCER.Reg) & 0x4000) >> 14
}

// TIM.CNT: counter
func (o *TIM_Type) SetCNT(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCNT() uint32 {
	return volatile.LoadUint32(&o.CNT.Reg) & 0xffff
}
func (o *TIM_Type) SetCNT_UIFCPY(value uint32) {
	volatile.StoreUint32(&o.CNT.Reg, volatile.LoadUint32(&o.CNT.Reg)&^(0x80000000)|value<<31)
}
func (o *TIM_Type) GetCNT_UIFCPY() uint32 {
	return (volatile.LoadUint32(&o.CNT.Reg) & 0x80000000) >> 31
}

// TIM.PSC: prescaler
func (o *TIM_Type) SetPSC(value uint32) {
	volatile.StoreUint32(&o.PSC.Reg, volatile.LoadUint32(&o.PSC.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetPSC() uint32 {
	return volatile.LoadUint32(&o.PSC.Reg) & 0xffff
}

// TIM.ARR: auto-reload register
func (o *TIM_Type) SetARR(value uint32) {
	volatile.StoreUint32(&o.ARR.Reg, volatile.LoadUint32(&o.ARR.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetARR() uint32 {
	return volatile.LoadUint32(&o.ARR.Reg) & 0xffff
}

// TIM.RCR: repetition counter register
func (o *TIM_Type) SetRCR_REP(value uint32) {
	volatile.StoreUint32(&o.RCR.Reg, volatile.LoadUint32(&o.RCR.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetRCR_REP() uint32 {
	return volatile.LoadUint32(&o.RCR.Reg) & 0xffff
}

// TIM.CCR1: capture/compare register
func (o *TIM_Type) SetCCR1_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR1.Reg, volatile.LoadUint32(&o.CCR1.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR1_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR1.Reg) & 0xffff
}

// TIM.CCR2: capture/compare register
func (o *TIM_Type) SetCCR2_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR2.Reg, volatile.LoadUint32(&o.CCR2.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR2_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR2.Reg) & 0xffff
}

// TIM.CCR3: capture/compare register
func (o *TIM_Type) SetCCR3_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR3.Reg, volatile.LoadUint32(&o.CCR3.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR3_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR3.Reg) & 0xffff
}

// TIM.CCR4: capture/compare register
func (o *TIM_Type) SetCCR4_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR4.Reg, volatile.LoadUint32(&o.CCR4.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR4_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR4.Reg) & 0xffff
}

// TIM.BDTR: break and dead-time register
func (o *TIM_Type) SetBDTR_MOE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetBDTR_MOE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetBDTR_AOE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x4000)|value<<14)
}
func (o *TIM_Type) GetBDTR_AOE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x4000) >> 14
}
func (o *TIM_Type) SetBDTR_BKP(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x2000)|value<<13)
}
func (o *TIM_Type) GetBDTR_BKP() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x2000) >> 13
}
func (o *TIM_Type) SetBDTR_BKE(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x1000)|value<<12)
}
func (o *TIM_Type) GetBDTR_BKE() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x1000) >> 12
}
func (o *TIM_Type) SetBDTR_OSSR(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetBDTR_OSSR() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetBDTR_OSSI(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetBDTR_OSSI() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetBDTR_LOCK(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x300)|value<<8)
}
func (o *TIM_Type) GetBDTR_LOCK() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x300) >> 8
}
func (o *TIM_Type) SetBDTR_DTG(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xff)|value)
}
func (o *TIM_Type) GetBDTR_DTG() uint32 {
	return volatile.LoadUint32(&o.BDTR.Reg) & 0xff
}
func (o *TIM_Type) SetBDTR_BKF(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xf0000)|value<<16)
}
func (o *TIM_Type) GetBDTR_BKF() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0xf0000) >> 16
}
func (o *TIM_Type) SetBDTR_BK2F(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0xf00000)|value<<20)
}
func (o *TIM_Type) GetBDTR_BK2F() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0xf00000) >> 20
}
func (o *TIM_Type) SetBDTR_BK2E(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetBDTR_BK2E() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetBDTR_BK2P(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x2000000)|value<<25)
}
func (o *TIM_Type) GetBDTR_BK2P() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x2000000) >> 25
}
func (o *TIM_Type) SetBDTR_BKDSRM(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x4000000)|value<<26)
}
func (o *TIM_Type) GetBDTR_BKDSRM() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x4000000) >> 26
}
func (o *TIM_Type) SetBDTR_BK2DSRM(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x8000000)|value<<27)
}
func (o *TIM_Type) GetBDTR_BK2DSRM() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x8000000) >> 27
}
func (o *TIM_Type) SetBDTR_BKBID(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x10000000)|value<<28)
}
func (o *TIM_Type) GetBDTR_BKBID() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x10000000) >> 28
}
func (o *TIM_Type) SetBDTR_BK2BID(value uint32) {
	volatile.StoreUint32(&o.BDTR.Reg, volatile.LoadUint32(&o.BDTR.Reg)&^(0x20000000)|value<<29)
}
func (o *TIM_Type) GetBDTR_BK2BID() uint32 {
	return (volatile.LoadUint32(&o.BDTR.Reg) & 0x20000000) >> 29
}

// TIM.DCR: DMA control register
func (o *TIM_Type) SetDCR_DBL(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f00)|value<<8)
}
func (o *TIM_Type) GetDCR_DBL() uint32 {
	return (volatile.LoadUint32(&o.DCR.Reg) & 0x1f00) >> 8
}
func (o *TIM_Type) SetDCR_DBA(value uint32) {
	volatile.StoreUint32(&o.DCR.Reg, volatile.LoadUint32(&o.DCR.Reg)&^(0x1f)|value)
}
func (o *TIM_Type) GetDCR_DBA() uint32 {
	return volatile.LoadUint32(&o.DCR.Reg) & 0x1f
}

// TIM.DMAR: DMA address for full transfer
func (o *TIM_Type) SetDMAR(value uint32) {
	volatile.StoreUint32(&o.DMAR.Reg, value)
}
func (o *TIM_Type) GetDMAR() uint32 {
	return volatile.LoadUint32(&o.DMAR.Reg)
}

// TIM.OR1: DMA address for full transfer
func (o *TIM_Type) SetOR1_ETR_ADC1_RMP(value uint32) {
	volatile.StoreUint32(&o.OR1.Reg, volatile.LoadUint32(&o.OR1.Reg)&^(0x3)|value)
}
func (o *TIM_Type) GetOR1_ETR_ADC1_RMP() uint32 {
	return volatile.LoadUint32(&o.OR1.Reg) & 0x3
}
func (o *TIM_Type) SetOR1_TI1_RMP(value uint32) {
	volatile.StoreUint32(&o.OR1.Reg, volatile.LoadUint32(&o.OR1.Reg)&^(0x10)|value<<4)
}
func (o *TIM_Type) GetOR1_TI1_RMP() uint32 {
	return (volatile.LoadUint32(&o.OR1.Reg) & 0x10) >> 4
}

// TIM.CCMR3_Output: capture/compare mode register 2 (output mode)
func (o *TIM_Type) SetCCMR3_Output_OC5M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x1000000)|value<<24)
}
func (o *TIM_Type) GetCCMR3_Output_OC5M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x1000000) >> 24
}
func (o *TIM_Type) SetCCMR3_Output_OC6M_3(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x0)|value<<32)
}
func (o *TIM_Type) GetCCMR3_Output_OC6M_3() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x0) >> 32
}
func (o *TIM_Type) SetCCMR3_Output_OC5CE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x8000)|value<<15)
}
func (o *TIM_Type) GetCCMR3_Output_OC5CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x8000) >> 15
}
func (o *TIM_Type) SetCCMR3_Output_OC6CE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x800000)|value<<23)
}
func (o *TIM_Type) GetCCMR3_Output_OC6CE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x800000) >> 23
}
func (o *TIM_Type) SetCCMR3_Output_OC5M(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x7000)|value<<12)
}
func (o *TIM_Type) GetCCMR3_Output_OC5M() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x7000) >> 12
}
func (o *TIM_Type) SetCCMR3_Output_OC6M(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x700000)|value<<20)
}
func (o *TIM_Type) GetCCMR3_Output_OC6M() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x700000) >> 20
}
func (o *TIM_Type) SetCCMR3_Output_OC5PE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetCCMR3_Output_OC5PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetCCMR3_Output_OC6PE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x80000)|value<<19)
}
func (o *TIM_Type) GetCCMR3_Output_OC6PE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x80000) >> 19
}
func (o *TIM_Type) SetCCMR3_Output_OC5FE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetCCMR3_Output_OC5FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetCCMR3_Output_OC6FE(value uint32) {
	volatile.StoreUint32(&o.CCMR3_Output.Reg, volatile.LoadUint32(&o.CCMR3_Output.Reg)&^(0x40000)|value<<18)
}
func (o *TIM_Type) GetCCMR3_Output_OC6FE() uint32 {
	return (volatile.LoadUint32(&o.CCMR3_Output.Reg) & 0x40000) >> 18
}

// TIM.CCR5: capture/compare register
func (o *TIM_Type) SetCCR5_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR5_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR5.Reg) & 0xffff
}
func (o *TIM_Type) SetCCR5_GC5C1(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x20000000)|value<<29)
}
func (o *TIM_Type) GetCCR5_GC5C1() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x20000000) >> 29
}
func (o *TIM_Type) SetCCR5_GC5C2(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x40000000)|value<<30)
}
func (o *TIM_Type) GetCCR5_GC5C2() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x40000000) >> 30
}
func (o *TIM_Type) SetCCR5_GC5C3(value uint32) {
	volatile.StoreUint32(&o.CCR5.Reg, volatile.LoadUint32(&o.CCR5.Reg)&^(0x80000000)|value<<31)
}
func (o *TIM_Type) GetCCR5_GC5C3() uint32 {
	return (volatile.LoadUint32(&o.CCR5.Reg) & 0x80000000) >> 31
}

// TIM.CCR6: capture/compare register
func (o *TIM_Type) SetCCR6_CCR(value uint32) {
	volatile.StoreUint32(&o.CCR6.Reg, volatile.LoadUint32(&o.CCR6.Reg)&^(0xffff)|value)
}
func (o *TIM_Type) GetCCR6_CCR() uint32 {
	return volatile.LoadUint32(&o.CCR6.Reg) & 0xffff
}

// TIM.OR2: DMA address for full transfer
func (o *TIM_Type) SetOR2_BKINE(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetOR2_BKINE() uint32 {
	return volatile.LoadUint32(&o.OR2.Reg) & 0x1
}
func (o *TIM_Type) SetOR2_BKCMP1E(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetOR2_BKCMP1E() uint32 {
	return (volatile.LoadUint32(&o.OR2.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetOR2_BKCMP2E(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetOR2_BKCMP2E() uint32 {
	return (volatile.LoadUint32(&o.OR2.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetOR2_BKDFBK0E(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetOR2_BKDFBK0E() uint32 {
	return (volatile.LoadUint32(&o.OR2.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetOR2_BKINP(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetOR2_BKINP() uint32 {
	return (volatile.LoadUint32(&o.OR2.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetOR2_BKCMP1P(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetOR2_BKCMP1P() uint32 {
	return (volatile.LoadUint32(&o.OR2.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetOR2_BKCMP2P(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetOR2_BKCMP2P() uint32 {
	return (volatile.LoadUint32(&o.OR2.Reg) & 0x800) >> 11
}
func (o *TIM_Type) SetOR2_ETRSEL(value uint32) {
	volatile.StoreUint32(&o.OR2.Reg, volatile.LoadUint32(&o.OR2.Reg)&^(0x1c000)|value<<14)
}
func (o *TIM_Type) GetOR2_ETRSEL() uint32 {
	return (volatile.LoadUint32(&o.OR2.Reg) & 0x1c000) >> 14
}

// TIM.OR3: DMA address for full transfer
func (o *TIM_Type) SetOR3_BK2INE(value uint32) {
	volatile.StoreUint32(&o.OR3.Reg, volatile.LoadUint32(&o.OR3.Reg)&^(0x1)|value)
}
func (o *TIM_Type) GetOR3_BK2INE() uint32 {
	return volatile.LoadUint32(&o.OR3.Reg) & 0x1
}
func (o *TIM_Type) SetOR3_BK2CMP1E(value uint32) {
	volatile.StoreUint32(&o.OR3.Reg, volatile.LoadUint32(&o.OR3.Reg)&^(0x2)|value<<1)
}
func (o *TIM_Type) GetOR3_BK2CMP1E() uint32 {
	return (volatile.LoadUint32(&o.OR3.Reg) & 0x2) >> 1
}
func (o *TIM_Type) SetOR3_BK2CMP2E(value uint32) {
	volatile.StoreUint32(&o.OR3.Reg, volatile.LoadUint32(&o.OR3.Reg)&^(0x4)|value<<2)
}
func (o *TIM_Type) GetOR3_BK2CMP2E() uint32 {
	return (volatile.LoadUint32(&o.OR3.Reg) & 0x4) >> 2
}
func (o *TIM_Type) SetOR3_BK2DFBK0E(value uint32) {
	volatile.StoreUint32(&o.OR3.Reg, volatile.LoadUint32(&o.OR3.Reg)&^(0x100)|value<<8)
}
func (o *TIM_Type) GetOR3_BK2DFBK0E() uint32 {
	return (volatile.LoadUint32(&o.OR3.Reg) & 0x100) >> 8
}
func (o *TIM_Type) SetOR3_BK2INP(value uint32) {
	volatile.StoreUint32(&o.OR3.Reg, volatile.LoadUint32(&o.OR3.Reg)&^(0x200)|value<<9)
}
func (o *TIM_Type) GetOR3_BK2INP() uint32 {
	return (volatile.LoadUint32(&o.OR3.Reg) & 0x200) >> 9
}
func (o *TIM_Type) SetOR3_BK2CMP1P(value uint32) {
	volatile.StoreUint32(&o.OR3.Reg, volatile.LoadUint32(&o.OR3.Reg)&^(0x400)|value<<10)
}
func (o *TIM_Type) GetOR3_BK2CMP1P() uint32 {
	return (volatile.LoadUint32(&o.OR3.Reg) & 0x400) >> 10
}
func (o *TIM_Type) SetOR3_BK2CMP2P(value uint32) {
	volatile.StoreUint32(&o.OR3.Reg, volatile.LoadUint32(&o.OR3.Reg)&^(0x800)|value<<11)
}
func (o *TIM_Type) GetOR3_BK2CMP2P() uint32 {
	return (volatile.LoadUint32(&o.OR3.Reg) & 0x800) >> 11
}

// Touch sensing controller
type TSC_Type struct {
	CR     volatile.Register32 // 0x0
	IER    volatile.Register32 // 0x4
	ICR    volatile.Register32 // 0x8
	ISR    volatile.Register32 // 0xC
	IOHCR  volatile.Register32 // 0x10
	_      [4]byte
	IOASCR volatile.Register32 // 0x18
	_      [4]byte
	IOSCR  volatile.Register32 // 0x20
	_      [4]byte
	IOCCR  volatile.Register32 // 0x28
	_      [4]byte
	IOGCSR volatile.Register32 // 0x30
	IOG1CR volatile.Register32 // 0x34
	IOG2CR volatile.Register32 // 0x38
	IOG3CR volatile.Register32 // 0x3C
	IOG4CR volatile.Register32 // 0x40
	IOG5CR volatile.Register32 // 0x44
	IOG6CR volatile.Register32 // 0x48
	IOG7CR volatile.Register32 // 0x4C
	IOG8CR volatile.Register32 // 0x50
}

// TSC.CR: control register
func (o *TSC_Type) SetCR_CTPH(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf0000000)|value<<28)
}
func (o *TSC_Type) GetCR_CTPH() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf0000000) >> 28
}
func (o *TSC_Type) SetCR_CTPL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xf000000)|value<<24)
}
func (o *TSC_Type) GetCR_CTPL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xf000000) >> 24
}
func (o *TSC_Type) SetCR_SSD(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xfe0000)|value<<17)
}
func (o *TSC_Type) GetCR_SSD() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xfe0000) >> 17
}
func (o *TSC_Type) SetCR_SSE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetCR_SSE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetCR_SSPSC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetCR_SSPSC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetCR_PGPSC(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7000)|value<<12)
}
func (o *TSC_Type) GetCR_PGPSC() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x7000) >> 12
}
func (o *TSC_Type) SetCR_MCV(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xe0)|value<<5)
}
func (o *TSC_Type) GetCR_MCV() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xe0) >> 5
}
func (o *TSC_Type) SetCR_IODEF(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetCR_IODEF() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetCR_SYNCPOL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *TSC_Type) GetCR_SYNCPOL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *TSC_Type) SetCR_AM(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *TSC_Type) GetCR_AM() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *TSC_Type) SetCR_START(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetCR_START() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetCR_TSCE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetCR_TSCE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x1
}

// TSC.IER: interrupt enable register
func (o *TSC_Type) SetIER_MCEIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetIER_MCEIE() uint32 {
	return (volatile.LoadUint32(&o.IER.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetIER_EOAIE(value uint32) {
	volatile.StoreUint32(&o.IER.Reg, volatile.LoadUint32(&o.IER.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetIER_EOAIE() uint32 {
	return volatile.LoadUint32(&o.IER.Reg) & 0x1
}

// TSC.ICR: interrupt clear register
func (o *TSC_Type) SetICR_MCEIC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetICR_MCEIC() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetICR_EOAIC(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetICR_EOAIC() uint32 {
	return volatile.LoadUint32(&o.ICR.Reg) & 0x1
}

// TSC.ISR: interrupt status register
func (o *TSC_Type) SetISR_MCEF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetISR_MCEF() uint32 {
	return (volatile.LoadUint32(&o.ISR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetISR_EOAF(value uint32) {
	volatile.StoreUint32(&o.ISR.Reg, volatile.LoadUint32(&o.ISR.Reg)&^(0x1)|value)
}
func (o *TSC_Type) GetISR_EOAF() uint32 {
	return volatile.LoadUint32(&o.ISR.Reg) & 0x1
}

// TSC.IOHCR: I/O hysteresis control register
func (o *TSC_Type) SetIOHCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOHCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOHCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOHCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOHCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOHCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOHCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOHCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOHCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOHCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOHCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOHCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOHCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOHCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOHCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOHCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOHCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOHCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOHCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOHCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOHCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOHCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOHCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOHCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOHCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOHCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOHCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOHCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOHCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOHCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOHCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOHCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOHCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOHCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOHCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOHCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOHCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOHCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOHCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOHCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOHCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOHCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOHCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOHCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOHCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOHCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOHCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOHCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOHCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOHCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOHCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOHCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOHCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOHCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOHCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOHCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOHCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOHCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOHCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOHCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOHCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOHCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOHCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOHCR.Reg, volatile.LoadUint32(&o.IOHCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOHCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOHCR.Reg) & 0x0) >> 33
}

// TSC.IOASCR: I/O analog switch control register
func (o *TSC_Type) SetIOASCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOASCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOASCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOASCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOASCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOASCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOASCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOASCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOASCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOASCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOASCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOASCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOASCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOASCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOASCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOASCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOASCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOASCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOASCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOASCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOASCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOASCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOASCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOASCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOASCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOASCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOASCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOASCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOASCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOASCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOASCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOASCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOASCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOASCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOASCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOASCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOASCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOASCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOASCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOASCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOASCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOASCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOASCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOASCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOASCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOASCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOASCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOASCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOASCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOASCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOASCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOASCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOASCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOASCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOASCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOASCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOASCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOASCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOASCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOASCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOASCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOASCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOASCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOASCR.Reg, volatile.LoadUint32(&o.IOASCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOASCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOASCR.Reg) & 0x0) >> 33
}

// TSC.IOSCR: I/O sampling control register
func (o *TSC_Type) SetIOSCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOSCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOSCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOSCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOSCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOSCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOSCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOSCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOSCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOSCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOSCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOSCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOSCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOSCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOSCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOSCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOSCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOSCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOSCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOSCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOSCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOSCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOSCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOSCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOSCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOSCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOSCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOSCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOSCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOSCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOSCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOSCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOSCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOSCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOSCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOSCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOSCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOSCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOSCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOSCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOSCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOSCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOSCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOSCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOSCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOSCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOSCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOSCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOSCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOSCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOSCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOSCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOSCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOSCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOSCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOSCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOSCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOSCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOSCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOSCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOSCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOSCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOSCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOSCR.Reg, volatile.LoadUint32(&o.IOSCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOSCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOSCR.Reg) & 0x0) >> 33
}

// TSC.IOCCR: I/O channel control register
func (o *TSC_Type) SetIOCCR_G1_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOCCR_G1_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOCCR_G2_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOCCR_G2_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x100) >> 8
}
func (o *TSC_Type) SetIOCCR_G3_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x1000)|value<<12)
}
func (o *TSC_Type) GetIOCCR_G3_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x1000) >> 12
}
func (o *TSC_Type) SetIOCCR_G4_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x10000)|value<<16)
}
func (o *TSC_Type) GetIOCCR_G4_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x10000) >> 16
}
func (o *TSC_Type) SetIOCCR_G5_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOCCR_G5_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOCCR_G6_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOCCR_G6_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOCCR_G7_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x10000000)|value<<28)
}
func (o *TSC_Type) GetIOCCR_G7_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x10000000) >> 28
}
func (o *TSC_Type) SetIOCCR_G8_IO1(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<32)
}
func (o *TSC_Type) GetIOCCR_G8_IO1() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 32
}
func (o *TSC_Type) SetIOCCR_G1_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOCCR_G1_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOCCR_G2_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x800)|value<<11)
}
func (o *TSC_Type) GetIOCCR_G2_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x800) >> 11
}
func (o *TSC_Type) SetIOCCR_G3_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x8000)|value<<15)
}
func (o *TSC_Type) GetIOCCR_G3_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x8000) >> 15
}
func (o *TSC_Type) SetIOCCR_G4_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOCCR_G4_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOCCR_G5_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOCCR_G5_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOCCR_G6_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x8000000)|value<<27)
}
func (o *TSC_Type) GetIOCCR_G6_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x8000000) >> 27
}
func (o *TSC_Type) SetIOCCR_G7_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x80000000)|value<<31)
}
func (o *TSC_Type) GetIOCCR_G7_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x80000000) >> 31
}
func (o *TSC_Type) SetIOCCR_G8_IO4(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<35)
}
func (o *TSC_Type) GetIOCCR_G8_IO4() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 35
}
func (o *TSC_Type) SetIOCCR_G1_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOCCR_G1_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOCCR_G2_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x400)|value<<10)
}
func (o *TSC_Type) GetIOCCR_G2_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x400) >> 10
}
func (o *TSC_Type) SetIOCCR_G3_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x4000)|value<<14)
}
func (o *TSC_Type) GetIOCCR_G3_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x4000) >> 14
}
func (o *TSC_Type) SetIOCCR_G4_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOCCR_G4_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOCCR_G5_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOCCR_G5_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOCCR_G6_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x4000000)|value<<26)
}
func (o *TSC_Type) GetIOCCR_G6_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x4000000) >> 26
}
func (o *TSC_Type) SetIOCCR_G7_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x40000000)|value<<30)
}
func (o *TSC_Type) GetIOCCR_G7_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x40000000) >> 30
}
func (o *TSC_Type) SetIOCCR_G8_IO3(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<34)
}
func (o *TSC_Type) GetIOCCR_G8_IO3() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 34
}
func (o *TSC_Type) SetIOCCR_G1_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOCCR_G1_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOCCR_G2_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x200)|value<<9)
}
func (o *TSC_Type) GetIOCCR_G2_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x200) >> 9
}
func (o *TSC_Type) SetIOCCR_G3_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x2000)|value<<13)
}
func (o *TSC_Type) GetIOCCR_G3_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x2000) >> 13
}
func (o *TSC_Type) SetIOCCR_G4_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOCCR_G4_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOCCR_G5_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOCCR_G5_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOCCR_G6_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x2000000)|value<<25)
}
func (o *TSC_Type) GetIOCCR_G6_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x2000000) >> 25
}
func (o *TSC_Type) SetIOCCR_G7_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x20000000)|value<<29)
}
func (o *TSC_Type) GetIOCCR_G7_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x20000000) >> 29
}
func (o *TSC_Type) SetIOCCR_G8_IO2(value uint32) {
	volatile.StoreUint32(&o.IOCCR.Reg, volatile.LoadUint32(&o.IOCCR.Reg)&^(0x0)|value<<33)
}
func (o *TSC_Type) GetIOCCR_G8_IO2() uint32 {
	return (volatile.LoadUint32(&o.IOCCR.Reg) & 0x0) >> 33
}

// TSC.IOGCSR: I/O group control status register
func (o *TSC_Type) SetIOGCSR_G1S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x20000)|value<<17)
}
func (o *TSC_Type) GetIOGCSR_G1S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x20000) >> 17
}
func (o *TSC_Type) SetIOGCSR_G2S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x40000)|value<<18)
}
func (o *TSC_Type) GetIOGCSR_G2S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x40000) >> 18
}
func (o *TSC_Type) SetIOGCSR_G3S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x80000)|value<<19)
}
func (o *TSC_Type) GetIOGCSR_G3S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x80000) >> 19
}
func (o *TSC_Type) SetIOGCSR_G4S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x100000)|value<<20)
}
func (o *TSC_Type) GetIOGCSR_G4S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x100000) >> 20
}
func (o *TSC_Type) SetIOGCSR_G5S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x200000)|value<<21)
}
func (o *TSC_Type) GetIOGCSR_G5S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x200000) >> 21
}
func (o *TSC_Type) SetIOGCSR_G6S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x400000)|value<<22)
}
func (o *TSC_Type) GetIOGCSR_G6S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x400000) >> 22
}
func (o *TSC_Type) SetIOGCSR_G7S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x800000)|value<<23)
}
func (o *TSC_Type) GetIOGCSR_G7S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x800000) >> 23
}
func (o *TSC_Type) SetIOGCSR_G8S(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x1000000)|value<<24)
}
func (o *TSC_Type) GetIOGCSR_G8S() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x1000000) >> 24
}
func (o *TSC_Type) SetIOGCSR_G1E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x2)|value<<1)
}
func (o *TSC_Type) GetIOGCSR_G1E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x2) >> 1
}
func (o *TSC_Type) SetIOGCSR_G2E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x4)|value<<2)
}
func (o *TSC_Type) GetIOGCSR_G2E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x4) >> 2
}
func (o *TSC_Type) SetIOGCSR_G3E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x8)|value<<3)
}
func (o *TSC_Type) GetIOGCSR_G3E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x8) >> 3
}
func (o *TSC_Type) SetIOGCSR_G4E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x10)|value<<4)
}
func (o *TSC_Type) GetIOGCSR_G4E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x10) >> 4
}
func (o *TSC_Type) SetIOGCSR_G5E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x20)|value<<5)
}
func (o *TSC_Type) GetIOGCSR_G5E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x20) >> 5
}
func (o *TSC_Type) SetIOGCSR_G6E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x40)|value<<6)
}
func (o *TSC_Type) GetIOGCSR_G6E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x40) >> 6
}
func (o *TSC_Type) SetIOGCSR_G7E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x80)|value<<7)
}
func (o *TSC_Type) GetIOGCSR_G7E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x80) >> 7
}
func (o *TSC_Type) SetIOGCSR_G8E(value uint32) {
	volatile.StoreUint32(&o.IOGCSR.Reg, volatile.LoadUint32(&o.IOGCSR.Reg)&^(0x100)|value<<8)
}
func (o *TSC_Type) GetIOGCSR_G8E() uint32 {
	return (volatile.LoadUint32(&o.IOGCSR.Reg) & 0x100) >> 8
}

// TSC.IOG1CR: I/O group x counter register
func (o *TSC_Type) SetIOG1CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG1CR.Reg, volatile.LoadUint32(&o.IOG1CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG1CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG1CR.Reg) & 0x3fff
}

// TSC.IOG2CR: I/O group x counter register
func (o *TSC_Type) SetIOG2CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG2CR.Reg, volatile.LoadUint32(&o.IOG2CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG2CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG2CR.Reg) & 0x3fff
}

// TSC.IOG3CR: I/O group x counter register
func (o *TSC_Type) SetIOG3CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG3CR.Reg, volatile.LoadUint32(&o.IOG3CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG3CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG3CR.Reg) & 0x3fff
}

// TSC.IOG4CR: I/O group x counter register
func (o *TSC_Type) SetIOG4CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG4CR.Reg, volatile.LoadUint32(&o.IOG4CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG4CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG4CR.Reg) & 0x3fff
}

// TSC.IOG5CR: I/O group x counter register
func (o *TSC_Type) SetIOG5CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG5CR.Reg, volatile.LoadUint32(&o.IOG5CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG5CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG5CR.Reg) & 0x3fff
}

// TSC.IOG6CR: I/O group x counter register
func (o *TSC_Type) SetIOG6CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG6CR.Reg, volatile.LoadUint32(&o.IOG6CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG6CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG6CR.Reg) & 0x3fff
}

// TSC.IOG7CR: I/O group x counter register
func (o *TSC_Type) SetIOG7CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG7CR.Reg, volatile.LoadUint32(&o.IOG7CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG7CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG7CR.Reg) & 0x3fff
}

// TSC.IOG8CR: I/O group x counter register
func (o *TSC_Type) SetIOG8CR_CNT(value uint32) {
	volatile.StoreUint32(&o.IOG8CR.Reg, volatile.LoadUint32(&o.IOG8CR.Reg)&^(0x3fff)|value)
}
func (o *TSC_Type) GetIOG8CR_CNT() uint32 {
	return volatile.LoadUint32(&o.IOG8CR.Reg) & 0x3fff
}

// Universal serial bus full-speed device interface
type USB_Type struct {
	EP0R   volatile.Register16 // 0x0
	_      [2]byte
	EP1R   volatile.Register16 // 0x4
	_      [2]byte
	EP2R   volatile.Register16 // 0x8
	_      [2]byte
	EP3R   volatile.Register16 // 0xC
	_      [2]byte
	EP4R   volatile.Register16 // 0x10
	_      [2]byte
	EP5R   volatile.Register16 // 0x14
	_      [2]byte
	EP6R   volatile.Register16 // 0x18
	_      [2]byte
	EP7R   volatile.Register16 // 0x1C
	_      [34]byte
	CNTR   volatile.Register16 // 0x40
	_      [2]byte
	ISTR   volatile.Register16 // 0x44
	_      [2]byte
	FNR    volatile.Register16 // 0x48
	_      [2]byte
	DADDR  volatile.Register16 // 0x4C
	_      [2]byte
	BTABLE volatile.Register16 // 0x50
	_      [2]byte
	LPMCSR volatile.Register16 // 0x54
	_      [2]byte
	BCDR   volatile.Register16 // 0x58
}

// USB.EP0R: endpoint %s register
func (o *USB_Type) SetEP0R_EA(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP0R_EA() uint16 {
	return volatile.LoadUint16(&o.EP0R.Reg) & 0xf
}
func (o *USB_Type) SetEP0R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP0R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP0R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP0R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP0R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP0R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP0R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP0R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP0R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP0R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP0R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP0R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP0R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP0R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP0R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP0R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP0R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP0R.Reg, volatile.LoadUint16(&o.EP0R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP0R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP0R.Reg) & 0x8000) >> 15
}

// USB.EP1R: endpoint %s register
func (o *USB_Type) SetEP1R_EA(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP1R_EA() uint16 {
	return volatile.LoadUint16(&o.EP1R.Reg) & 0xf
}
func (o *USB_Type) SetEP1R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP1R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP1R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP1R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP1R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP1R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP1R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP1R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP1R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP1R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP1R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP1R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP1R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP1R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP1R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP1R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP1R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP1R.Reg, volatile.LoadUint16(&o.EP1R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP1R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP1R.Reg) & 0x8000) >> 15
}

// USB.EP2R: endpoint %s register
func (o *USB_Type) SetEP2R_EA(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP2R_EA() uint16 {
	return volatile.LoadUint16(&o.EP2R.Reg) & 0xf
}
func (o *USB_Type) SetEP2R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP2R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP2R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP2R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP2R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP2R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP2R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP2R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP2R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP2R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP2R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP2R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP2R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP2R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP2R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP2R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP2R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP2R.Reg, volatile.LoadUint16(&o.EP2R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP2R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP2R.Reg) & 0x8000) >> 15
}

// USB.EP3R: endpoint %s register
func (o *USB_Type) SetEP3R_EA(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP3R_EA() uint16 {
	return volatile.LoadUint16(&o.EP3R.Reg) & 0xf
}
func (o *USB_Type) SetEP3R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP3R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP3R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP3R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP3R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP3R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP3R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP3R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP3R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP3R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP3R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP3R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP3R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP3R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP3R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP3R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP3R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP3R.Reg, volatile.LoadUint16(&o.EP3R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP3R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP3R.Reg) & 0x8000) >> 15
}

// USB.EP4R: endpoint %s register
func (o *USB_Type) SetEP4R_EA(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP4R_EA() uint16 {
	return volatile.LoadUint16(&o.EP4R.Reg) & 0xf
}
func (o *USB_Type) SetEP4R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP4R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP4R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP4R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP4R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP4R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP4R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP4R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP4R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP4R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP4R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP4R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP4R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP4R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP4R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP4R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP4R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP4R.Reg, volatile.LoadUint16(&o.EP4R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP4R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP4R.Reg) & 0x8000) >> 15
}

// USB.EP5R: endpoint %s register
func (o *USB_Type) SetEP5R_EA(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP5R_EA() uint16 {
	return volatile.LoadUint16(&o.EP5R.Reg) & 0xf
}
func (o *USB_Type) SetEP5R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP5R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP5R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP5R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP5R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP5R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP5R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP5R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP5R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP5R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP5R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP5R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP5R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP5R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP5R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP5R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP5R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP5R.Reg, volatile.LoadUint16(&o.EP5R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP5R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP5R.Reg) & 0x8000) >> 15
}

// USB.EP6R: endpoint %s register
func (o *USB_Type) SetEP6R_EA(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP6R_EA() uint16 {
	return volatile.LoadUint16(&o.EP6R.Reg) & 0xf
}
func (o *USB_Type) SetEP6R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP6R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP6R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP6R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP6R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP6R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP6R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP6R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP6R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP6R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP6R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP6R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP6R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP6R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP6R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP6R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP6R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP6R.Reg, volatile.LoadUint16(&o.EP6R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP6R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP6R.Reg) & 0x8000) >> 15
}

// USB.EP7R: endpoint %s register
func (o *USB_Type) SetEP7R_EA(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetEP7R_EA() uint16 {
	return volatile.LoadUint16(&o.EP7R.Reg) & 0xf
}
func (o *USB_Type) SetEP7R_STAT_TX(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x30)|value<<4)
}
func (o *USB_Type) GetEP7R_STAT_TX() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x30) >> 4
}
func (o *USB_Type) SetEP7R_DTOG_TX(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetEP7R_DTOG_TX() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetEP7R_CTR_TX(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetEP7R_CTR_TX() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetEP7R_EP_KIND(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetEP7R_EP_KIND() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetEP7R_EP_TYPE(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x600)|value<<9)
}
func (o *USB_Type) GetEP7R_EP_TYPE() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x600) >> 9
}
func (o *USB_Type) SetEP7R_SETUP(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetEP7R_SETUP() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetEP7R_STAT_RX(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x3000)|value<<12)
}
func (o *USB_Type) GetEP7R_STAT_RX() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x3000) >> 12
}
func (o *USB_Type) SetEP7R_DTOG_RX(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetEP7R_DTOG_RX() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetEP7R_CTR_RX(value uint16) {
	volatile.StoreUint16(&o.EP7R.Reg, volatile.LoadUint16(&o.EP7R.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetEP7R_CTR_RX() uint16 {
	return (volatile.LoadUint16(&o.EP7R.Reg) & 0x8000) >> 15
}

// USB.CNTR: control register
func (o *USB_Type) SetCNTR_FRES(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x1)|value)
}
func (o *USB_Type) GetCNTR_FRES() uint16 {
	return volatile.LoadUint16(&o.CNTR.Reg) & 0x1
}
func (o *USB_Type) SetCNTR_PDWN(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x2)|value<<1)
}
func (o *USB_Type) GetCNTR_PDWN() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x2) >> 1
}
func (o *USB_Type) SetCNTR_LPMODE(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x4)|value<<2)
}
func (o *USB_Type) GetCNTR_LPMODE() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x4) >> 2
}
func (o *USB_Type) SetCNTR_FSUSP(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x8)|value<<3)
}
func (o *USB_Type) GetCNTR_FSUSP() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x8) >> 3
}
func (o *USB_Type) SetCNTR_RESUME(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x10)|value<<4)
}
func (o *USB_Type) GetCNTR_RESUME() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x10) >> 4
}
func (o *USB_Type) SetCNTR_L1RESUME(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x20)|value<<5)
}
func (o *USB_Type) GetCNTR_L1RESUME() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x20) >> 5
}
func (o *USB_Type) SetCNTR_L1REQM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetCNTR_L1REQM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetCNTR_ESOFM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetCNTR_ESOFM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetCNTR_SOFM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x200)|value<<9)
}
func (o *USB_Type) GetCNTR_SOFM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x200) >> 9
}
func (o *USB_Type) SetCNTR_RESETM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x400)|value<<10)
}
func (o *USB_Type) GetCNTR_RESETM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x400) >> 10
}
func (o *USB_Type) SetCNTR_SUSPM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetCNTR_SUSPM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetCNTR_WKUPM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x1000)|value<<12)
}
func (o *USB_Type) GetCNTR_WKUPM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x1000) >> 12
}
func (o *USB_Type) SetCNTR_ERRM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x2000)|value<<13)
}
func (o *USB_Type) GetCNTR_ERRM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x2000) >> 13
}
func (o *USB_Type) SetCNTR_PMAOVRM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetCNTR_PMAOVRM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetCNTR_CTRM(value uint16) {
	volatile.StoreUint16(&o.CNTR.Reg, volatile.LoadUint16(&o.CNTR.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetCNTR_CTRM() uint16 {
	return (volatile.LoadUint16(&o.CNTR.Reg) & 0x8000) >> 15
}

// USB.ISTR: interrupt status register
func (o *USB_Type) SetISTR_EP_ID(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0xf)|value)
}
func (o *USB_Type) GetISTR_EP_ID() uint16 {
	return volatile.LoadUint16(&o.ISTR.Reg) & 0xf
}
func (o *USB_Type) SetISTR_DIR(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x10)|value<<4)
}
func (o *USB_Type) GetISTR_DIR() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x10) >> 4
}
func (o *USB_Type) SetISTR_L1REQ(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetISTR_L1REQ() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetISTR_ESOF(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x100)|value<<8)
}
func (o *USB_Type) GetISTR_ESOF() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x100) >> 8
}
func (o *USB_Type) SetISTR_SOF(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x200)|value<<9)
}
func (o *USB_Type) GetISTR_SOF() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x200) >> 9
}
func (o *USB_Type) SetISTR_RESET(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x400)|value<<10)
}
func (o *USB_Type) GetISTR_RESET() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x400) >> 10
}
func (o *USB_Type) SetISTR_SUSP(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x800)|value<<11)
}
func (o *USB_Type) GetISTR_SUSP() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x800) >> 11
}
func (o *USB_Type) SetISTR_WKUP(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x1000)|value<<12)
}
func (o *USB_Type) GetISTR_WKUP() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x1000) >> 12
}
func (o *USB_Type) SetISTR_ERR(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x2000)|value<<13)
}
func (o *USB_Type) GetISTR_ERR() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x2000) >> 13
}
func (o *USB_Type) SetISTR_PMAOVR(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetISTR_PMAOVR() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetISTR_CTR(value uint16) {
	volatile.StoreUint16(&o.ISTR.Reg, volatile.LoadUint16(&o.ISTR.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetISTR_CTR() uint16 {
	return (volatile.LoadUint16(&o.ISTR.Reg) & 0x8000) >> 15
}

// USB.FNR: frame number register
func (o *USB_Type) SetFNR_FN(value uint16) {
	volatile.StoreUint16(&o.FNR.Reg, volatile.LoadUint16(&o.FNR.Reg)&^(0x7ff)|value)
}
func (o *USB_Type) GetFNR_FN() uint16 {
	return volatile.LoadUint16(&o.FNR.Reg) & 0x7ff
}
func (o *USB_Type) SetFNR_LSOF(value uint16) {
	volatile.StoreUint16(&o.FNR.Reg, volatile.LoadUint16(&o.FNR.Reg)&^(0x1800)|value<<11)
}
func (o *USB_Type) GetFNR_LSOF() uint16 {
	return (volatile.LoadUint16(&o.FNR.Reg) & 0x1800) >> 11
}
func (o *USB_Type) SetFNR_LCK(value uint16) {
	volatile.StoreUint16(&o.FNR.Reg, volatile.LoadUint16(&o.FNR.Reg)&^(0x2000)|value<<13)
}
func (o *USB_Type) GetFNR_LCK() uint16 {
	return (volatile.LoadUint16(&o.FNR.Reg) & 0x2000) >> 13
}
func (o *USB_Type) SetFNR_RXDM(value uint16) {
	volatile.StoreUint16(&o.FNR.Reg, volatile.LoadUint16(&o.FNR.Reg)&^(0x4000)|value<<14)
}
func (o *USB_Type) GetFNR_RXDM() uint16 {
	return (volatile.LoadUint16(&o.FNR.Reg) & 0x4000) >> 14
}
func (o *USB_Type) SetFNR_RXDP(value uint16) {
	volatile.StoreUint16(&o.FNR.Reg, volatile.LoadUint16(&o.FNR.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetFNR_RXDP() uint16 {
	return (volatile.LoadUint16(&o.FNR.Reg) & 0x8000) >> 15
}

// USB.DADDR: device address
func (o *USB_Type) SetDADDR_ADD(value uint16) {
	volatile.StoreUint16(&o.DADDR.Reg, volatile.LoadUint16(&o.DADDR.Reg)&^(0x7f)|value)
}
func (o *USB_Type) GetDADDR_ADD() uint16 {
	return volatile.LoadUint16(&o.DADDR.Reg) & 0x7f
}
func (o *USB_Type) SetDADDR_EF(value uint16) {
	volatile.StoreUint16(&o.DADDR.Reg, volatile.LoadUint16(&o.DADDR.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetDADDR_EF() uint16 {
	return (volatile.LoadUint16(&o.DADDR.Reg) & 0x80) >> 7
}

// USB.BTABLE: Buffer table address
func (o *USB_Type) SetBTABLE(value uint16) {
	volatile.StoreUint16(&o.BTABLE.Reg, volatile.LoadUint16(&o.BTABLE.Reg)&^(0xfff8)|value<<3)
}
func (o *USB_Type) GetBTABLE() uint16 {
	return (volatile.LoadUint16(&o.BTABLE.Reg) & 0xfff8) >> 3
}

// USB.LPMCSR: LPM control and status register
func (o *USB_Type) SetLPMCSR_LPMEN(value uint16) {
	volatile.StoreUint16(&o.LPMCSR.Reg, volatile.LoadUint16(&o.LPMCSR.Reg)&^(0x1)|value)
}
func (o *USB_Type) GetLPMCSR_LPMEN() uint16 {
	return volatile.LoadUint16(&o.LPMCSR.Reg) & 0x1
}
func (o *USB_Type) SetLPMCSR_LPMACK(value uint16) {
	volatile.StoreUint16(&o.LPMCSR.Reg, volatile.LoadUint16(&o.LPMCSR.Reg)&^(0x2)|value<<1)
}
func (o *USB_Type) GetLPMCSR_LPMACK() uint16 {
	return (volatile.LoadUint16(&o.LPMCSR.Reg) & 0x2) >> 1
}
func (o *USB_Type) SetLPMCSR_REMWAKE(value uint16) {
	volatile.StoreUint16(&o.LPMCSR.Reg, volatile.LoadUint16(&o.LPMCSR.Reg)&^(0x8)|value<<3)
}
func (o *USB_Type) GetLPMCSR_REMWAKE() uint16 {
	return (volatile.LoadUint16(&o.LPMCSR.Reg) & 0x8) >> 3
}
func (o *USB_Type) SetLPMCSR_BESL(value uint16) {
	volatile.StoreUint16(&o.LPMCSR.Reg, volatile.LoadUint16(&o.LPMCSR.Reg)&^(0xf0)|value<<4)
}
func (o *USB_Type) GetLPMCSR_BESL() uint16 {
	return (volatile.LoadUint16(&o.LPMCSR.Reg) & 0xf0) >> 4
}

// USB.BCDR: Battery charging detector
func (o *USB_Type) SetBCDR_BCDEN(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x1)|value)
}
func (o *USB_Type) GetBCDR_BCDEN() uint16 {
	return volatile.LoadUint16(&o.BCDR.Reg) & 0x1
}
func (o *USB_Type) SetBCDR_DCDEN(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x2)|value<<1)
}
func (o *USB_Type) GetBCDR_DCDEN() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x2) >> 1
}
func (o *USB_Type) SetBCDR_PDEN(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x4)|value<<2)
}
func (o *USB_Type) GetBCDR_PDEN() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x4) >> 2
}
func (o *USB_Type) SetBCDR_SDEN(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x8)|value<<3)
}
func (o *USB_Type) GetBCDR_SDEN() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x8) >> 3
}
func (o *USB_Type) SetBCDR_DCDET(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x10)|value<<4)
}
func (o *USB_Type) GetBCDR_DCDET() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x10) >> 4
}
func (o *USB_Type) SetBCDR_PDET(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x20)|value<<5)
}
func (o *USB_Type) GetBCDR_PDET() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x20) >> 5
}
func (o *USB_Type) SetBCDR_SDET(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x40)|value<<6)
}
func (o *USB_Type) GetBCDR_SDET() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x40) >> 6
}
func (o *USB_Type) SetBCDR_PS2DET(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x80)|value<<7)
}
func (o *USB_Type) GetBCDR_PS2DET() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x80) >> 7
}
func (o *USB_Type) SetBCDR_DPPU(value uint16) {
	volatile.StoreUint16(&o.BCDR.Reg, volatile.LoadUint16(&o.BCDR.Reg)&^(0x8000)|value<<15)
}
func (o *USB_Type) GetBCDR_DPPU() uint16 {
	return (volatile.LoadUint16(&o.BCDR.Reg) & 0x8000) >> 15
}

// USB Power Delivery interface
type UCPD_Type struct {
	CFGR1       volatile.Register32 // 0x0
	CFGR2       volatile.Register32 // 0x4
	CFGR3       volatile.Register32 // 0x8
	CR          volatile.Register32 // 0xC
	IMR         volatile.Register32 // 0x10
	SR          volatile.Register32 // 0x14
	ICR         volatile.Register32 // 0x18
	TX_ORDSETR  volatile.Register32 // 0x1C
	TX_PAYSZR   volatile.Register32 // 0x20
	TXDR        volatile.Register32 // 0x24
	RX_ORDSETR  volatile.Register32 // 0x28
	RX_PAYSZR   volatile.Register32 // 0x2C
	RXDR        volatile.Register32 // 0x30
	RX_ORDEXTR1 volatile.Register32 // 0x34
	RX_ORDEXTR2 volatile.Register32 // 0x38
}

// UCPD.CFGR1: UCPD configuration register
func (o *UCPD_Type) SetCFGR1_HBITCLKDIV(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x3f)|value)
}
func (o *UCPD_Type) GetCFGR1_HBITCLKDIV() uint32 {
	return volatile.LoadUint32(&o.CFGR1.Reg) & 0x3f
}
func (o *UCPD_Type) SetCFGR1_IFRGAP(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x7c0)|value<<6)
}
func (o *UCPD_Type) GetCFGR1_IFRGAP() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x7c0) >> 6
}
func (o *UCPD_Type) SetCFGR1_TRANSWIN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xf800)|value<<11)
}
func (o *UCPD_Type) GetCFGR1_TRANSWIN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xf800) >> 11
}
func (o *UCPD_Type) SetCFGR1_PSC_USBPDCLK(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0xe0000)|value<<17)
}
func (o *UCPD_Type) GetCFGR1_PSC_USBPDCLK() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0xe0000) >> 17
}
func (o *UCPD_Type) SetCFGR1_TXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x20000000)|value<<29)
}
func (o *UCPD_Type) GetCFGR1_TXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x20000000) >> 29
}
func (o *UCPD_Type) SetCFGR1_RXDMAEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x40000000)|value<<30)
}
func (o *UCPD_Type) GetCFGR1_RXDMAEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x40000000) >> 30
}
func (o *UCPD_Type) SetCFGR1_UCPDEN(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x80000000)|value<<31)
}
func (o *UCPD_Type) GetCFGR1_UCPDEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x80000000) >> 31
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN0(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN0() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x100000) >> 20
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN1(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x200000)|value<<21)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN1() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x200000) >> 21
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN2(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x400000)|value<<22)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN2() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x400000) >> 22
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN3(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x800000)|value<<23)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN3() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x800000) >> 23
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN4(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x1000000)|value<<24)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN4() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x1000000) >> 24
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN5(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x2000000)|value<<25)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN5() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x2000000) >> 25
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN6(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x4000000)|value<<26)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN6() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x4000000) >> 26
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN7(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x8000000)|value<<27)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN7() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x8000000) >> 27
}
func (o *UCPD_Type) SetCFGR1_RXORDSETEN8(value uint32) {
	volatile.StoreUint32(&o.CFGR1.Reg, volatile.LoadUint32(&o.CFGR1.Reg)&^(0x10000000)|value<<28)
}
func (o *UCPD_Type) GetCFGR1_RXORDSETEN8() uint32 {
	return (volatile.LoadUint32(&o.CFGR1.Reg) & 0x10000000) >> 28
}

// UCPD.CFGR2: UCPD configuration register 2
func (o *UCPD_Type) SetCFGR2_RXFILTDIS(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x1)|value)
}
func (o *UCPD_Type) GetCFGR2_RXFILTDIS() uint32 {
	return volatile.LoadUint32(&o.CFGR2.Reg) & 0x1
}
func (o *UCPD_Type) SetCFGR2_RXFILT2N3(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetCFGR2_RXFILT2N3() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetCFGR2_FORCECLK(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetCFGR2_FORCECLK() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetCFGR2_WUPEN(value uint32) {
	volatile.StoreUint32(&o.CFGR2.Reg, volatile.LoadUint32(&o.CFGR2.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetCFGR2_WUPEN() uint32 {
	return (volatile.LoadUint32(&o.CFGR2.Reg) & 0x8) >> 3
}

// UCPD.CFGR3: UCPD configuration register 3
func (o *UCPD_Type) SetCFGR3_TRIM1_NG_CCRPD(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0xf)|value)
}
func (o *UCPD_Type) GetCFGR3_TRIM1_NG_CCRPD() uint32 {
	return volatile.LoadUint32(&o.CFGR3.Reg) & 0xf
}
func (o *UCPD_Type) SetCFGR3_TRIM1_NG_CC1A5(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x1f0)|value<<4)
}
func (o *UCPD_Type) GetCFGR3_TRIM1_NG_CC1A5() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x1f0) >> 4
}
func (o *UCPD_Type) SetCFGR3_TRIM1_NG_CC3A0(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x1e00)|value<<9)
}
func (o *UCPD_Type) GetCFGR3_TRIM1_NG_CC3A0() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x1e00) >> 9
}
func (o *UCPD_Type) SetCFGR3_TRIM2_NG_CCRPD(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0xf0000)|value<<16)
}
func (o *UCPD_Type) GetCFGR3_TRIM2_NG_CCRPD() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0xf0000) >> 16
}
func (o *UCPD_Type) SetCFGR3_TRIM2_NG_CC1A5(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x1f00000)|value<<20)
}
func (o *UCPD_Type) GetCFGR3_TRIM2_NG_CC1A5() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x1f00000) >> 20
}
func (o *UCPD_Type) SetCFGR3_TRIM2_NG_CC3A0(value uint32) {
	volatile.StoreUint32(&o.CFGR3.Reg, volatile.LoadUint32(&o.CFGR3.Reg)&^(0x1e000000)|value<<25)
}
func (o *UCPD_Type) GetCFGR3_TRIM2_NG_CC3A0() uint32 {
	return (volatile.LoadUint32(&o.CFGR3.Reg) & 0x1e000000) >> 25
}

// UCPD.CR: UCPD control register
func (o *UCPD_Type) SetCR_TXMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x3)|value)
}
func (o *UCPD_Type) GetCR_TXMODE() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x3
}
func (o *UCPD_Type) SetCR_TXSEND(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetCR_TXSEND() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetCR_TXHRST(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetCR_TXHRST() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetCR_RXMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetCR_RXMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetCR_PHYRXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetCR_PHYRXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetCR_PHYCCSEL(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetCR_PHYCCSEL() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetCR_ANASUBMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x180)|value<<7)
}
func (o *UCPD_Type) GetCR_ANASUBMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x180) >> 7
}
func (o *UCPD_Type) SetCR_ANAMODE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetCR_ANAMODE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetCR_CCENABLE(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0xc00)|value<<10)
}
func (o *UCPD_Type) GetCR_CCENABLE() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0xc00) >> 10
}
func (o *UCPD_Type) SetCR_FRSRXEN(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x10000)|value<<16)
}
func (o *UCPD_Type) GetCR_FRSRXEN() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x10000) >> 16
}
func (o *UCPD_Type) SetCR_FRSTX(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x20000)|value<<17)
}
func (o *UCPD_Type) GetCR_FRSTX() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x20000) >> 17
}
func (o *UCPD_Type) SetCR_RDCH(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x40000)|value<<18)
}
func (o *UCPD_Type) GetCR_RDCH() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x40000) >> 18
}
func (o *UCPD_Type) SetCR_CC1TCDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetCR_CC1TCDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x100000) >> 20
}
func (o *UCPD_Type) SetCR_CC2TCDIS(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x200000)|value<<21)
}
func (o *UCPD_Type) GetCR_CC2TCDIS() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x200000) >> 21
}

// UCPD.IMR: UCPD Interrupt Mask Register
func (o *UCPD_Type) SetIMR_TXISIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1)|value)
}
func (o *UCPD_Type) GetIMR_TXISIE() uint32 {
	return volatile.LoadUint32(&o.IMR.Reg) & 0x1
}
func (o *UCPD_Type) SetIMR_TXMSGDISCIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetIMR_TXMSGDISCIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetIMR_TXMSGSENTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetIMR_TXMSGSENTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetIMR_TXMSGABTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetIMR_TXMSGABTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetIMR_HRSTDISCIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetIMR_HRSTDISCIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetIMR_HRSTSENTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetIMR_HRSTSENTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetIMR_TXUNDIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetIMR_TXUNDIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetIMR_RXNEIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100)|value<<8)
}
func (o *UCPD_Type) GetIMR_RXNEIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100) >> 8
}
func (o *UCPD_Type) SetIMR_RXORDDETIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetIMR_RXORDDETIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetIMR_RXHRSTDETIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x400)|value<<10)
}
func (o *UCPD_Type) GetIMR_RXHRSTDETIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x400) >> 10
}
func (o *UCPD_Type) SetIMR_RXOVRIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x800)|value<<11)
}
func (o *UCPD_Type) GetIMR_RXOVRIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x800) >> 11
}
func (o *UCPD_Type) SetIMR_RXMSGENDIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x1000)|value<<12)
}
func (o *UCPD_Type) GetIMR_RXMSGENDIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x1000) >> 12
}
func (o *UCPD_Type) SetIMR_TYPECEVT1IE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x4000)|value<<14)
}
func (o *UCPD_Type) GetIMR_TYPECEVT1IE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x4000) >> 14
}
func (o *UCPD_Type) SetIMR_TYPECEVT2IE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x8000)|value<<15)
}
func (o *UCPD_Type) GetIMR_TYPECEVT2IE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x8000) >> 15
}
func (o *UCPD_Type) SetIMR_FRSEVTIE(value uint32) {
	volatile.StoreUint32(&o.IMR.Reg, volatile.LoadUint32(&o.IMR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetIMR_FRSEVTIE() uint32 {
	return (volatile.LoadUint32(&o.IMR.Reg) & 0x100000) >> 20
}

// UCPD.SR: UCPD Status Register
func (o *UCPD_Type) SetSR_TXIS(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *UCPD_Type) GetSR_TXIS() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}
func (o *UCPD_Type) SetSR_TXMSGDISC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetSR_TXMSGDISC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetSR_TXMSGSENT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetSR_TXMSGSENT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetSR_TXMSGABT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetSR_TXMSGABT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetSR_HRSTDISC(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetSR_HRSTDISC() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetSR_HRSTSENT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetSR_HRSTSENT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetSR_TXUND(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetSR_TXUND() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetSR_RXNE(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100)|value<<8)
}
func (o *UCPD_Type) GetSR_RXNE() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100) >> 8
}
func (o *UCPD_Type) SetSR_RXORDDET(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetSR_RXORDDET() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetSR_RXHRSTDET(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x400)|value<<10)
}
func (o *UCPD_Type) GetSR_RXHRSTDET() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x400) >> 10
}
func (o *UCPD_Type) SetSR_RXOVR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x800)|value<<11)
}
func (o *UCPD_Type) GetSR_RXOVR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x800) >> 11
}
func (o *UCPD_Type) SetSR_RXMSGEND(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1000)|value<<12)
}
func (o *UCPD_Type) GetSR_RXMSGEND() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x1000) >> 12
}
func (o *UCPD_Type) SetSR_RXERR(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x2000)|value<<13)
}
func (o *UCPD_Type) GetSR_RXERR() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x2000) >> 13
}
func (o *UCPD_Type) SetSR_TYPECEVT1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x4000)|value<<14)
}
func (o *UCPD_Type) GetSR_TYPECEVT1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x4000) >> 14
}
func (o *UCPD_Type) SetSR_TYPECEVT2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x8000)|value<<15)
}
func (o *UCPD_Type) GetSR_TYPECEVT2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x8000) >> 15
}
func (o *UCPD_Type) SetSR_TYPEC_VSTATE_CC1(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x30000)|value<<16)
}
func (o *UCPD_Type) GetSR_TYPEC_VSTATE_CC1() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x30000) >> 16
}
func (o *UCPD_Type) SetSR_TYPEC_VSTATE_CC2(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0xc0000)|value<<18)
}
func (o *UCPD_Type) GetSR_TYPEC_VSTATE_CC2() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0xc0000) >> 18
}
func (o *UCPD_Type) SetSR_FRSEVT(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetSR_FRSEVT() uint32 {
	return (volatile.LoadUint32(&o.SR.Reg) & 0x100000) >> 20
}

// UCPD.ICR: UCPD Interrupt Clear Register
func (o *UCPD_Type) SetICR_TXMSGDISCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x2)|value<<1)
}
func (o *UCPD_Type) GetICR_TXMSGDISCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x2) >> 1
}
func (o *UCPD_Type) SetICR_TXMSGSENTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4)|value<<2)
}
func (o *UCPD_Type) GetICR_TXMSGSENTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4) >> 2
}
func (o *UCPD_Type) SetICR_TXMSGABTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetICR_TXMSGABTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetICR_HRSTDISCCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x10)|value<<4)
}
func (o *UCPD_Type) GetICR_HRSTDISCCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x10) >> 4
}
func (o *UCPD_Type) SetICR_HRSTSENTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x20)|value<<5)
}
func (o *UCPD_Type) GetICR_HRSTSENTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x20) >> 5
}
func (o *UCPD_Type) SetICR_TXUNDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x40)|value<<6)
}
func (o *UCPD_Type) GetICR_TXUNDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x40) >> 6
}
func (o *UCPD_Type) SetICR_RXORDDETCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x200)|value<<9)
}
func (o *UCPD_Type) GetICR_RXORDDETCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x200) >> 9
}
func (o *UCPD_Type) SetICR_RXHRSTDETCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x400)|value<<10)
}
func (o *UCPD_Type) GetICR_RXHRSTDETCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x400) >> 10
}
func (o *UCPD_Type) SetICR_RXOVRCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x800)|value<<11)
}
func (o *UCPD_Type) GetICR_RXOVRCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x800) >> 11
}
func (o *UCPD_Type) SetICR_RXMSGENDCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x1000)|value<<12)
}
func (o *UCPD_Type) GetICR_RXMSGENDCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x1000) >> 12
}
func (o *UCPD_Type) SetICR_TYPECEVT1CF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x4000)|value<<14)
}
func (o *UCPD_Type) GetICR_TYPECEVT1CF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x4000) >> 14
}
func (o *UCPD_Type) SetICR_TYPECEVT2CF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x8000)|value<<15)
}
func (o *UCPD_Type) GetICR_TYPECEVT2CF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x8000) >> 15
}
func (o *UCPD_Type) SetICR_FRSEVTCF(value uint32) {
	volatile.StoreUint32(&o.ICR.Reg, volatile.LoadUint32(&o.ICR.Reg)&^(0x100000)|value<<20)
}
func (o *UCPD_Type) GetICR_FRSEVTCF() uint32 {
	return (volatile.LoadUint32(&o.ICR.Reg) & 0x100000) >> 20
}

// UCPD.TX_ORDSETR: UCPD Tx Ordered Set Type Register
func (o *UCPD_Type) SetTX_ORDSETR_TXORDSET(value uint32) {
	volatile.StoreUint32(&o.TX_ORDSETR.Reg, volatile.LoadUint32(&o.TX_ORDSETR.Reg)&^(0xfffff)|value)
}
func (o *UCPD_Type) GetTX_ORDSETR_TXORDSET() uint32 {
	return volatile.LoadUint32(&o.TX_ORDSETR.Reg) & 0xfffff
}

// UCPD.TX_PAYSZR: UCPD Tx Paysize Register
func (o *UCPD_Type) SetTX_PAYSZR_TXPAYSZ(value uint32) {
	volatile.StoreUint32(&o.TX_PAYSZR.Reg, volatile.LoadUint32(&o.TX_PAYSZR.Reg)&^(0x3ff)|value)
}
func (o *UCPD_Type) GetTX_PAYSZR_TXPAYSZ() uint32 {
	return volatile.LoadUint32(&o.TX_PAYSZR.Reg) & 0x3ff
}

// UCPD.TXDR: UCPD Tx Data Register
func (o *UCPD_Type) SetTXDR_TXDATA(value uint32) {
	volatile.StoreUint32(&o.TXDR.Reg, volatile.LoadUint32(&o.TXDR.Reg)&^(0xff)|value)
}
func (o *UCPD_Type) GetTXDR_TXDATA() uint32 {
	return volatile.LoadUint32(&o.TXDR.Reg) & 0xff
}

// UCPD.RX_ORDSETR: UCPD Rx Ordered Set Register
func (o *UCPD_Type) SetRX_ORDSETR_RXORDSET(value uint32) {
	volatile.StoreUint32(&o.RX_ORDSETR.Reg, volatile.LoadUint32(&o.RX_ORDSETR.Reg)&^(0x7)|value)
}
func (o *UCPD_Type) GetRX_ORDSETR_RXORDSET() uint32 {
	return volatile.LoadUint32(&o.RX_ORDSETR.Reg) & 0x7
}
func (o *UCPD_Type) SetRX_ORDSETR_RXSOP3OF4(value uint32) {
	volatile.StoreUint32(&o.RX_ORDSETR.Reg, volatile.LoadUint32(&o.RX_ORDSETR.Reg)&^(0x8)|value<<3)
}
func (o *UCPD_Type) GetRX_ORDSETR_RXSOP3OF4() uint32 {
	return (volatile.LoadUint32(&o.RX_ORDSETR.Reg) & 0x8) >> 3
}
func (o *UCPD_Type) SetRX_ORDSETR_RXSOPKINVALID(value uint32) {
	volatile.StoreUint32(&o.RX_ORDSETR.Reg, volatile.LoadUint32(&o.RX_ORDSETR.Reg)&^(0x70)|value<<4)
}
func (o *UCPD_Type) GetRX_ORDSETR_RXSOPKINVALID() uint32 {
	return (volatile.LoadUint32(&o.RX_ORDSETR.Reg) & 0x70) >> 4
}

// UCPD.RX_PAYSZR: UCPD Rx Paysize Register
func (o *UCPD_Type) SetRX_PAYSZR_RXPAYSZ(value uint32) {
	volatile.StoreUint32(&o.RX_PAYSZR.Reg, volatile.LoadUint32(&o.RX_PAYSZR.Reg)&^(0x3ff)|value)
}
func (o *UCPD_Type) GetRX_PAYSZR_RXPAYSZ() uint32 {
	return volatile.LoadUint32(&o.RX_PAYSZR.Reg) & 0x3ff
}

// UCPD.RXDR: UCPD Receive Data Register
func (o *UCPD_Type) SetRXDR_RXDATA(value uint32) {
	volatile.StoreUint32(&o.RXDR.Reg, volatile.LoadUint32(&o.RXDR.Reg)&^(0xff)|value)
}
func (o *UCPD_Type) GetRXDR_RXDATA() uint32 {
	return volatile.LoadUint32(&o.RXDR.Reg) & 0xff
}

// UCPD.RX_ORDEXTR1: UCPD Rx Ordered Set Extension Register
func (o *UCPD_Type) SetRX_ORDEXTR1_RXSOPX1(value uint32) {
	volatile.StoreUint32(&o.RX_ORDEXTR1.Reg, volatile.LoadUint32(&o.RX_ORDEXTR1.Reg)&^(0xfffff)|value)
}
func (o *UCPD_Type) GetRX_ORDEXTR1_RXSOPX1() uint32 {
	return volatile.LoadUint32(&o.RX_ORDEXTR1.Reg) & 0xfffff
}

// UCPD.RX_ORDEXTR2: UCPD Rx Ordered Set Extension Register
func (o *UCPD_Type) SetRX_ORDEXTR2_RXSOPX2(value uint32) {
	volatile.StoreUint32(&o.RX_ORDEXTR2.Reg, volatile.LoadUint32(&o.RX_ORDEXTR2.Reg)&^(0xfffff)|value)
}
func (o *UCPD_Type) GetRX_ORDEXTR2_RXSOPX2() uint32 {
	return volatile.LoadUint32(&o.RX_ORDEXTR2.Reg) & 0xfffff
}

// Voltage reference buffer
type VREF_Type struct {
	CSR volatile.Register32 // 0x0
	CCR volatile.Register32 // 0x4
}

// VREF.CSR: VREF control and status register
func (o *VREF_Type) SetCSR_ENVR(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x1)|value)
}
func (o *VREF_Type) GetCSR_ENVR() uint32 {
	return volatile.LoadUint32(&o.CSR.Reg) & 0x1
}
func (o *VREF_Type) SetCSR_HIZ(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x2)|value<<1)
}
func (o *VREF_Type) GetCSR_HIZ() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x2) >> 1
}
func (o *VREF_Type) SetCSR_VRS(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x4)|value<<2)
}
func (o *VREF_Type) GetCSR_VRS() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x4) >> 2
}
func (o *VREF_Type) SetCSR_VRR(value uint32) {
	volatile.StoreUint32(&o.CSR.Reg, volatile.LoadUint32(&o.CSR.Reg)&^(0x8)|value<<3)
}
func (o *VREF_Type) GetCSR_VRR() uint32 {
	return (volatile.LoadUint32(&o.CSR.Reg) & 0x8) >> 3
}

// VREF.CCR: calibration control register
func (o *VREF_Type) SetCCR_TRIM(value uint32) {
	volatile.StoreUint32(&o.CCR.Reg, volatile.LoadUint32(&o.CCR.Reg)&^(0x3f)|value)
}
func (o *VREF_Type) GetCCR_TRIM() uint32 {
	return volatile.LoadUint32(&o.CCR.Reg) & 0x3f
}

// System window watchdog
type WWDG_Type struct {
	CR  volatile.Register32 // 0x0
	CFR volatile.Register32 // 0x4
	SR  volatile.Register32 // 0x8
}

// WWDG.CR: Control register
func (o *WWDG_Type) SetCR_WDGA(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x80)|value<<7)
}
func (o *WWDG_Type) GetCR_WDGA() uint32 {
	return (volatile.LoadUint32(&o.CR.Reg) & 0x80) >> 7
}
func (o *WWDG_Type) SetCR_T(value uint32) {
	volatile.StoreUint32(&o.CR.Reg, volatile.LoadUint32(&o.CR.Reg)&^(0x7f)|value)
}
func (o *WWDG_Type) GetCR_T() uint32 {
	return volatile.LoadUint32(&o.CR.Reg) & 0x7f
}

// WWDG.CFR: Configuration register
func (o *WWDG_Type) SetCFR_EWI(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x200)|value<<9)
}
func (o *WWDG_Type) GetCFR_EWI() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x200) >> 9
}
func (o *WWDG_Type) SetCFR_WDGTB(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x180)|value<<7)
}
func (o *WWDG_Type) GetCFR_WDGTB() uint32 {
	return (volatile.LoadUint32(&o.CFR.Reg) & 0x180) >> 7
}
func (o *WWDG_Type) SetCFR_W(value uint32) {
	volatile.StoreUint32(&o.CFR.Reg, volatile.LoadUint32(&o.CFR.Reg)&^(0x7f)|value)
}
func (o *WWDG_Type) GetCFR_W() uint32 {
	return volatile.LoadUint32(&o.CFR.Reg) & 0x7f
}

// WWDG.SR: Status register
func (o *WWDG_Type) SetSR_EWIF(value uint32) {
	volatile.StoreUint32(&o.SR.Reg, volatile.LoadUint32(&o.SR.Reg)&^(0x1)|value)
}
func (o *WWDG_Type) GetSR_EWIF() uint32 {
	return volatile.LoadUint32(&o.SR.Reg) & 0x1
}

// Constants for ADC1: Analog-to-Digital Converter
const (
	// ISR: interrupt and status register
	// Position of JQOVF field.
	ADC_ISR_JQOVF_Pos = 0xa
	// Bit mask of JQOVF field.
	ADC_ISR_JQOVF_Msk = 0x400
	// Bit JQOVF.
	ADC_ISR_JQOVF = 0x400
	// No injected context queue overflow has occurred
	ADC_ISR_JQOVF_NoOverflow = 0x0
	// Injected context queue overflow has occurred
	ADC_ISR_JQOVF_Overflow = 0x1
	// Clear injected context queue overflow flag
	ADC_ISR_JQOVF_Clear = 0x1
	// Position of AWD1 field.
	ADC_ISR_AWD1_Pos = 0x8
	// Bit mask of AWD1 field.
	ADC_ISR_AWD1_Msk = 0x100
	// Bit AWD1.
	ADC_ISR_AWD1 = 0x100
	// No analog watchdog event occurred
	ADC_ISR_AWD1_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD1_Event = 0x1
	// Clear analog watchdog event occurred flag
	ADC_ISR_AWD1_Clear = 0x1
	// Position of AWD2 field.
	ADC_ISR_AWD2_Pos = 0x9
	// Bit mask of AWD2 field.
	ADC_ISR_AWD2_Msk = 0x200
	// Bit AWD2.
	ADC_ISR_AWD2 = 0x200
	// No analog watchdog event occurred
	ADC_ISR_AWD2_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD2_Event = 0x1
	// Clear analog watchdog event occurred flag
	ADC_ISR_AWD2_Clear = 0x1
	// Position of AWD3 field.
	ADC_ISR_AWD3_Pos = 0xa
	// Bit mask of AWD3 field.
	ADC_ISR_AWD3_Msk = 0x400
	// Bit AWD3.
	ADC_ISR_AWD3 = 0x400
	// No analog watchdog event occurred
	ADC_ISR_AWD3_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_ISR_AWD3_Event = 0x1
	// Clear analog watchdog event occurred flag
	ADC_ISR_AWD3_Clear = 0x1
	// Position of JEOS field.
	ADC_ISR_JEOS_Pos = 0x6
	// Bit mask of JEOS field.
	ADC_ISR_JEOS_Msk = 0x40
	// Bit JEOS.
	ADC_ISR_JEOS = 0x40
	// Injected sequence is not complete
	ADC_ISR_JEOS_NotComplete = 0x0
	// Injected sequence complete
	ADC_ISR_JEOS_Complete = 0x1
	// Clear Injected sequence complete flag
	ADC_ISR_JEOS_Clear = 0x1
	// Position of JEOC field.
	ADC_ISR_JEOC_Pos = 0x5
	// Bit mask of JEOC field.
	ADC_ISR_JEOC_Msk = 0x20
	// Bit JEOC.
	ADC_ISR_JEOC = 0x20
	// Injected conversion is not complete
	ADC_ISR_JEOC_NotComplete = 0x0
	// Injected conversion complete
	ADC_ISR_JEOC_Complete = 0x1
	// Clear injected conversion complete flag
	ADC_ISR_JEOC_Clear = 0x1
	// Position of OVR field.
	ADC_ISR_OVR_Pos = 0x4
	// Bit mask of OVR field.
	ADC_ISR_OVR_Msk = 0x10
	// Bit OVR.
	ADC_ISR_OVR = 0x10
	// No overrun occurred
	ADC_ISR_OVR_NoOverrun = 0x0
	// Overrun occurred
	ADC_ISR_OVR_Overrun = 0x1
	// Clear overrun occurred flag
	ADC_ISR_OVR_Clear = 0x1
	// Position of EOS field.
	ADC_ISR_EOS_Pos = 0x3
	// Bit mask of EOS field.
	ADC_ISR_EOS_Msk = 0x8
	// Bit EOS.
	ADC_ISR_EOS = 0x8
	// Regular sequence is not complete
	ADC_ISR_EOS_NotComplete = 0x0
	// Regular sequence complete
	ADC_ISR_EOS_Complete = 0x1
	// Clear regular sequence complete flag
	ADC_ISR_EOS_Clear = 0x1
	// Position of EOC field.
	ADC_ISR_EOC_Pos = 0x2
	// Bit mask of EOC field.
	ADC_ISR_EOC_Msk = 0x4
	// Bit EOC.
	ADC_ISR_EOC = 0x4
	// Regular conversion is not complete
	ADC_ISR_EOC_NotComplete = 0x0
	// Regular conversion complete
	ADC_ISR_EOC_Complete = 0x1
	// Clear regular conversion complete flag
	ADC_ISR_EOC_Clear = 0x1
	// Position of EOSMP field.
	ADC_ISR_EOSMP_Pos = 0x1
	// Bit mask of EOSMP field.
	ADC_ISR_EOSMP_Msk = 0x2
	// Bit EOSMP.
	ADC_ISR_EOSMP = 0x2
	// End of sampling phase no yet reached
	ADC_ISR_EOSMP_NotEnded = 0x0
	// End of sampling phase reached
	ADC_ISR_EOSMP_Ended = 0x1
	// Clear end of sampling phase reached flag
	ADC_ISR_EOSMP_Clear = 0x1
	// Position of ADRDY field.
	ADC_ISR_ADRDY_Pos = 0x0
	// Bit mask of ADRDY field.
	ADC_ISR_ADRDY_Msk = 0x1
	// Bit ADRDY.
	ADC_ISR_ADRDY = 0x1
	// ADC is not ready to start conversion
	ADC_ISR_ADRDY_NotReady = 0x0
	// ADC is ready to start conversion
	ADC_ISR_ADRDY_Ready = 0x1
	// Clear ADC is ready to start conversion flag
	ADC_ISR_ADRDY_Clear = 0x1

	// IER: interrupt enable register
	// Position of JQOVFIE field.
	ADC_IER_JQOVFIE_Pos = 0xa
	// Bit mask of JQOVFIE field.
	ADC_IER_JQOVFIE_Msk = 0x400
	// Bit JQOVFIE.
	ADC_IER_JQOVFIE = 0x400
	// Injected context queue overflow interrupt disabled
	ADC_IER_JQOVFIE_Disabled = 0x0
	// Injected context queue overflow interrupt enabled
	ADC_IER_JQOVFIE_Enabled = 0x1
	// Position of AWD1IE field.
	ADC_IER_AWD1IE_Pos = 0x8
	// Bit mask of AWD1IE field.
	ADC_IER_AWD1IE_Msk = 0x100
	// Bit AWD1IE.
	ADC_IER_AWD1IE = 0x100
	// Analog watchdog interrupt disabled
	ADC_IER_AWD1IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD1IE_Enabled = 0x1
	// Position of AWD2IE field.
	ADC_IER_AWD2IE_Pos = 0x9
	// Bit mask of AWD2IE field.
	ADC_IER_AWD2IE_Msk = 0x200
	// Bit AWD2IE.
	ADC_IER_AWD2IE = 0x200
	// Analog watchdog interrupt disabled
	ADC_IER_AWD2IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD2IE_Enabled = 0x1
	// Position of AWD3IE field.
	ADC_IER_AWD3IE_Pos = 0xa
	// Bit mask of AWD3IE field.
	ADC_IER_AWD3IE_Msk = 0x400
	// Bit AWD3IE.
	ADC_IER_AWD3IE = 0x400
	// Analog watchdog interrupt disabled
	ADC_IER_AWD3IE_Disabled = 0x0
	// Analog watchdog interrupt enabled
	ADC_IER_AWD3IE_Enabled = 0x1
	// Position of JEOSIE field.
	ADC_IER_JEOSIE_Pos = 0x6
	// Bit mask of JEOSIE field.
	ADC_IER_JEOSIE_Msk = 0x40
	// Bit JEOSIE.
	ADC_IER_JEOSIE = 0x40
	// End of injected sequence interrupt disabled
	ADC_IER_JEOSIE_Disabled = 0x0
	// End of injected sequence interrupt enabled
	ADC_IER_JEOSIE_Enabled = 0x1
	// Position of JEOCIE field.
	ADC_IER_JEOCIE_Pos = 0x5
	// Bit mask of JEOCIE field.
	ADC_IER_JEOCIE_Msk = 0x20
	// Bit JEOCIE.
	ADC_IER_JEOCIE = 0x20
	// End of injected conversion interrupt disabled
	ADC_IER_JEOCIE_Disabled = 0x0
	// End of injected conversion interrupt enabled
	ADC_IER_JEOCIE_Enabled = 0x1
	// Position of OVRIE field.
	ADC_IER_OVRIE_Pos = 0x4
	// Bit mask of OVRIE field.
	ADC_IER_OVRIE_Msk = 0x10
	// Bit OVRIE.
	ADC_IER_OVRIE = 0x10
	// Overrun interrupt disabled
	ADC_IER_OVRIE_Disabled = 0x0
	// Overrun interrupt enabled
	ADC_IER_OVRIE_Enabled = 0x1
	// Position of EOSIE field.
	ADC_IER_EOSIE_Pos = 0x3
	// Bit mask of EOSIE field.
	ADC_IER_EOSIE_Msk = 0x8
	// Bit EOSIE.
	ADC_IER_EOSIE = 0x8
	// End of regular sequence interrupt disabled
	ADC_IER_EOSIE_Disabled = 0x0
	// End of regular sequence interrupt enabled
	ADC_IER_EOSIE_Enabled = 0x1
	// Position of EOCIE field.
	ADC_IER_EOCIE_Pos = 0x2
	// Bit mask of EOCIE field.
	ADC_IER_EOCIE_Msk = 0x4
	// Bit EOCIE.
	ADC_IER_EOCIE = 0x4
	// End of regular conversion interrupt disabled
	ADC_IER_EOCIE_Disabled = 0x0
	// End of regular conversion interrupt enabled
	ADC_IER_EOCIE_Enabled = 0x1
	// Position of EOSMPIE field.
	ADC_IER_EOSMPIE_Pos = 0x1
	// Bit mask of EOSMPIE field.
	ADC_IER_EOSMPIE_Msk = 0x2
	// Bit EOSMPIE.
	ADC_IER_EOSMPIE = 0x2
	// End of regular conversion sampling phase interrupt disabled
	ADC_IER_EOSMPIE_Disabled = 0x0
	// End of regular conversion sampling phase interrupt enabled
	ADC_IER_EOSMPIE_Enabled = 0x1
	// Position of ADRDYIE field.
	ADC_IER_ADRDYIE_Pos = 0x0
	// Bit mask of ADRDYIE field.
	ADC_IER_ADRDYIE_Msk = 0x1
	// Bit ADRDYIE.
	ADC_IER_ADRDYIE = 0x1
	// ADC ready interrupt disabled
	ADC_IER_ADRDYIE_Disabled = 0x0
	// ADC ready interrupt enabled
	ADC_IER_ADRDYIE_Enabled = 0x1

	// CR: control register
	// Position of ADCAL field.
	ADC_CR_ADCAL_Pos = 0x1f
	// Bit mask of ADCAL field.
	ADC_CR_ADCAL_Msk = 0x80000000
	// Bit ADCAL.
	ADC_CR_ADCAL = 0x80000000
	// ADC calibration either not yet performed or completed
	ADC_CR_ADCAL_NotCalibrating = 0x0
	// ADC calibration in progress
	ADC_CR_ADCAL_Calibrating = 0x1
	// Start the ADC calibration sequence
	ADC_CR_ADCAL_StartCalibration = 0x1
	// Position of ADCALDIF field.
	ADC_CR_ADCALDIF_Pos = 0x1e
	// Bit mask of ADCALDIF field.
	ADC_CR_ADCALDIF_Msk = 0x40000000
	// Bit ADCALDIF.
	ADC_CR_ADCALDIF = 0x40000000
	// Calibration for single-ended mode
	ADC_CR_ADCALDIF_SingleEnded = 0x0
	// Calibration for differential mode
	ADC_CR_ADCALDIF_Differential = 0x1
	// Position of DEEPPWD field.
	ADC_CR_DEEPPWD_Pos = 0x1d
	// Bit mask of DEEPPWD field.
	ADC_CR_DEEPPWD_Msk = 0x20000000
	// Bit DEEPPWD.
	ADC_CR_DEEPPWD = 0x20000000
	// ADC not in Deep-power down
	ADC_CR_DEEPPWD_NotDeepPowerDown = 0x0
	// ADC in Deep-power-down (default reset state)
	ADC_CR_DEEPPWD_DeepPowerDown = 0x1
	// Position of ADVREGEN field.
	ADC_CR_ADVREGEN_Pos = 0x1c
	// Bit mask of ADVREGEN field.
	ADC_CR_ADVREGEN_Msk = 0x10000000
	// Bit ADVREGEN.
	ADC_CR_ADVREGEN = 0x10000000
	// ADC Voltage regulator disabled
	ADC_CR_ADVREGEN_Disabled = 0x0
	// ADC Voltage regulator enabled
	ADC_CR_ADVREGEN_Enabled = 0x1
	// Position of ADSTP field.
	ADC_CR_ADSTP_Pos = 0x4
	// Bit mask of ADSTP field.
	ADC_CR_ADSTP_Msk = 0x10
	// Bit ADSTP.
	ADC_CR_ADSTP = 0x10
	// No stop command active
	ADC_CR_ADSTP_NotStopping = 0x0
	// ADC stopping conversion
	ADC_CR_ADSTP_Stopping = 0x1
	// Stop the active conversion
	ADC_CR_ADSTP_StopConversion = 0x1
	// Position of JADSTP field.
	ADC_CR_JADSTP_Pos = 0x5
	// Bit mask of JADSTP field.
	ADC_CR_JADSTP_Msk = 0x20
	// Bit JADSTP.
	ADC_CR_JADSTP = 0x20
	// No stop command active
	ADC_CR_JADSTP_NotStopping = 0x0
	// ADC stopping conversion
	ADC_CR_JADSTP_Stopping = 0x1
	// Stop the active conversion
	ADC_CR_JADSTP_StopConversion = 0x1
	// Position of ADSTART field.
	ADC_CR_ADSTART_Pos = 0x2
	// Bit mask of ADSTART field.
	ADC_CR_ADSTART_Msk = 0x4
	// Bit ADSTART.
	ADC_CR_ADSTART = 0x4
	// No conversion ongoing
	ADC_CR_ADSTART_NotActive = 0x0
	// ADC operating and may be converting
	ADC_CR_ADSTART_Active = 0x1
	// Start the ADC conversion (may be delayed for hardware triggers)
	ADC_CR_ADSTART_StartConversion = 0x1
	// Position of JADSTART field.
	ADC_CR_JADSTART_Pos = 0x3
	// Bit mask of JADSTART field.
	ADC_CR_JADSTART_Msk = 0x8
	// Bit JADSTART.
	ADC_CR_JADSTART = 0x8
	// No conversion ongoing
	ADC_CR_JADSTART_NotActive = 0x0
	// ADC operating and may be converting
	ADC_CR_JADSTART_Active = 0x1
	// Start the ADC conversion (may be delayed for hardware triggers)
	ADC_CR_JADSTART_StartConversion = 0x1
	// Position of ADDIS field.
	ADC_CR_ADDIS_Pos = 0x1
	// Bit mask of ADDIS field.
	ADC_CR_ADDIS_Msk = 0x2
	// Bit ADDIS.
	ADC_CR_ADDIS = 0x2
	// No disable command active
	ADC_CR_ADDIS_NotDisabling = 0x0
	// ADC disabling
	ADC_CR_ADDIS_Disabling = 0x1
	// Disable the ADC
	ADC_CR_ADDIS_Disable = 0x1
	// Position of ADEN field.
	ADC_CR_ADEN_Pos = 0x0
	// Bit mask of ADEN field.
	ADC_CR_ADEN_Msk = 0x1
	// Bit ADEN.
	ADC_CR_ADEN = 0x1
	// ADC disabled
	ADC_CR_ADEN_Disabled = 0x0
	// ADC enabled
	ADC_CR_ADEN_Enabled = 0x1

	// CFGR: configuration register
	// Position of JQDIS field.
	ADC_CFGR_JQDIS_Pos = 0x1f
	// Bit mask of JQDIS field.
	ADC_CFGR_JQDIS_Msk = 0x80000000
	// Bit JQDIS.
	ADC_CFGR_JQDIS = 0x80000000
	// Position of AWD1CH field.
	ADC_CFGR_AWD1CH_Pos = 0x1a
	// Bit mask of AWD1CH field.
	ADC_CFGR_AWD1CH_Msk = 0x7c000000
	// Position of JAUTO field.
	ADC_CFGR_JAUTO_Pos = 0x19
	// Bit mask of JAUTO field.
	ADC_CFGR_JAUTO_Msk = 0x2000000
	// Bit JAUTO.
	ADC_CFGR_JAUTO = 0x2000000
	// Automatic injected group conversion disabled
	ADC_CFGR_JAUTO_Disabled = 0x0
	// Automatic injected group conversion enabled
	ADC_CFGR_JAUTO_Enabled = 0x1
	// Position of JAWD1EN field.
	ADC_CFGR_JAWD1EN_Pos = 0x18
	// Bit mask of JAWD1EN field.
	ADC_CFGR_JAWD1EN_Msk = 0x1000000
	// Bit JAWD1EN.
	ADC_CFGR_JAWD1EN = 0x1000000
	// Analog watchdog 1 disabled on injected channels
	ADC_CFGR_JAWD1EN_Disabled = 0x0
	// Analog watchdog 1 enabled on injected channels
	ADC_CFGR_JAWD1EN_Enabled = 0x1
	// Position of AWD1EN field.
	ADC_CFGR_AWD1EN_Pos = 0x17
	// Bit mask of AWD1EN field.
	ADC_CFGR_AWD1EN_Msk = 0x800000
	// Bit AWD1EN.
	ADC_CFGR_AWD1EN = 0x800000
	// Analog watchdog 1 disabled on regular channels
	ADC_CFGR_AWD1EN_Disabled = 0x0
	// Analog watchdog 1 enabled on regular channels
	ADC_CFGR_AWD1EN_Enabled = 0x1
	// Position of AWD1SGL field.
	ADC_CFGR_AWD1SGL_Pos = 0x16
	// Bit mask of AWD1SGL field.
	ADC_CFGR_AWD1SGL_Msk = 0x400000
	// Bit AWD1SGL.
	ADC_CFGR_AWD1SGL = 0x400000
	// Analog watchdog 1 enabled on all channels
	ADC_CFGR_AWD1SGL_All = 0x0
	// Analog watchdog 1 enabled on single channel selected in AWD1CH
	ADC_CFGR_AWD1SGL_Single = 0x1
	// Position of JQM field.
	ADC_CFGR_JQM_Pos = 0x15
	// Bit mask of JQM field.
	ADC_CFGR_JQM_Msk = 0x200000
	// Bit JQM.
	ADC_CFGR_JQM = 0x200000
	// JSQR Mode 0: Queue maintains the last written configuration into JSQR
	ADC_CFGR_JQM_Mode0 = 0x0
	// JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence
	ADC_CFGR_JQM_Mode1 = 0x1
	// Position of JDISCEN field.
	ADC_CFGR_JDISCEN_Pos = 0x14
	// Bit mask of JDISCEN field.
	ADC_CFGR_JDISCEN_Msk = 0x100000
	// Bit JDISCEN.
	ADC_CFGR_JDISCEN = 0x100000
	// Discontinuous mode on injected channels disabled
	ADC_CFGR_JDISCEN_Disabled = 0x0
	// Discontinuous mode on injected channels enabled
	ADC_CFGR_JDISCEN_Enabled = 0x1
	// Position of DISCNUM field.
	ADC_CFGR_DISCNUM_Pos = 0x11
	// Bit mask of DISCNUM field.
	ADC_CFGR_DISCNUM_Msk = 0xe0000
	// Position of DISCEN field.
	ADC_CFGR_DISCEN_Pos = 0x10
	// Bit mask of DISCEN field.
	ADC_CFGR_DISCEN_Msk = 0x10000
	// Bit DISCEN.
	ADC_CFGR_DISCEN = 0x10000
	// Discontinuous mode on regular channels disabled
	ADC_CFGR_DISCEN_Disabled = 0x0
	// Discontinuous mode on regular channels enabled
	ADC_CFGR_DISCEN_Enabled = 0x1
	// Position of AUTDLY field.
	ADC_CFGR_AUTDLY_Pos = 0xe
	// Bit mask of AUTDLY field.
	ADC_CFGR_AUTDLY_Msk = 0x4000
	// Bit AUTDLY.
	ADC_CFGR_AUTDLY = 0x4000
	// Auto delayed conversion mode off
	ADC_CFGR_AUTDLY_Off = 0x0
	// Auto delayed conversion mode on
	ADC_CFGR_AUTDLY_On = 0x1
	// Position of CONT field.
	ADC_CFGR_CONT_Pos = 0xd
	// Bit mask of CONT field.
	ADC_CFGR_CONT_Msk = 0x2000
	// Bit CONT.
	ADC_CFGR_CONT = 0x2000
	// Single conversion mode
	ADC_CFGR_CONT_Single = 0x0
	// Continuous conversion mode
	ADC_CFGR_CONT_Continuous = 0x1
	// Position of OVRMOD field.
	ADC_CFGR_OVRMOD_Pos = 0xc
	// Bit mask of OVRMOD field.
	ADC_CFGR_OVRMOD_Msk = 0x1000
	// Bit OVRMOD.
	ADC_CFGR_OVRMOD = 0x1000
	// Preserve DR register when an overrun is detected
	ADC_CFGR_OVRMOD_Preserve = 0x0
	// Overwrite DR register when an overrun is detected
	ADC_CFGR_OVRMOD_Overwrite = 0x1
	// Position of EXTEN field.
	ADC_CFGR_EXTEN_Pos = 0xa
	// Bit mask of EXTEN field.
	ADC_CFGR_EXTEN_Msk = 0xc00
	// Trigger detection disabled
	ADC_CFGR_EXTEN_Disabled = 0x0
	// Trigger detection on the rising edge
	ADC_CFGR_EXTEN_RisingEdge = 0x1
	// Trigger detection on the falling edge
	ADC_CFGR_EXTEN_FallingEdge = 0x2
	// Trigger detection on both the rising and falling edges
	ADC_CFGR_EXTEN_BothEdges = 0x3
	// Position of EXTSEL field.
	ADC_CFGR_EXTSEL_Pos = 0x6
	// Bit mask of EXTSEL field.
	ADC_CFGR_EXTSEL_Msk = 0x3c0
	// Timer 1 CC1 event
	ADC_CFGR_EXTSEL_TIM1_CC1 = 0x0
	// Timer 1 CC2 event
	ADC_CFGR_EXTSEL_TIM1_CC2 = 0x1
	// Timer 1 CC3 event
	ADC_CFGR_EXTSEL_TIM1_CC3 = 0x2
	// Timer 2 CC2 event
	ADC_CFGR_EXTSEL_TIM2_CC2 = 0x3
	// Timer 3 TRGO event
	ADC_CFGR_EXTSEL_TIM3_TRGO = 0x4
	// EXTI line 11
	ADC_CFGR_EXTSEL_EXTI11 = 0x6
	// Timer 1 TRGO event
	ADC_CFGR_EXTSEL_TIM1_TRGO = 0x9
	// Timer 1 TRGO2 event
	ADC_CFGR_EXTSEL_TIM1_TRGO2 = 0xa
	// Timer 2 TRGO event
	ADC_CFGR_EXTSEL_TIM2_TRGO = 0xb
	// Timer 6 TRGO event
	ADC_CFGR_EXTSEL_TIM6_TRGO = 0xd
	// Timer 15 TRGO event
	ADC_CFGR_EXTSEL_TIM15_TRGO = 0xe
	// Timer 3 CC4 event
	ADC_CFGR_EXTSEL_TIM3_CC4 = 0xf
	// Position of ALIGN field.
	ADC_CFGR_ALIGN_Pos = 0x5
	// Bit mask of ALIGN field.
	ADC_CFGR_ALIGN_Msk = 0x20
	// Bit ALIGN.
	ADC_CFGR_ALIGN = 0x20
	// Right alignment
	ADC_CFGR_ALIGN_Right = 0x0
	// Left alignment
	ADC_CFGR_ALIGN_Left = 0x1
	// Position of RES field.
	ADC_CFGR_RES_Pos = 0x3
	// Bit mask of RES field.
	ADC_CFGR_RES_Msk = 0x18
	// 12-bit
	ADC_CFGR_RES_Bits12 = 0x0
	// 10-bit
	ADC_CFGR_RES_Bits10 = 0x1
	// 8-bit
	ADC_CFGR_RES_Bits8 = 0x2
	// 6-bit
	ADC_CFGR_RES_Bits6 = 0x3
	// Position of DMACFG field.
	ADC_CFGR_DMACFG_Pos = 0x1
	// Bit mask of DMACFG field.
	ADC_CFGR_DMACFG_Msk = 0x2
	// Bit DMACFG.
	ADC_CFGR_DMACFG = 0x2
	// DMA One Shot mode selected
	ADC_CFGR_DMACFG_OneShot = 0x0
	// DMA Circular mode selected
	ADC_CFGR_DMACFG_Circular = 0x1
	// Position of DMAEN field.
	ADC_CFGR_DMAEN_Pos = 0x0
	// Bit mask of DMAEN field.
	ADC_CFGR_DMAEN_Msk = 0x1
	// Bit DMAEN.
	ADC_CFGR_DMAEN = 0x1
	// DMA disabled
	ADC_CFGR_DMAEN_Disabled = 0x0
	// DMA enabled
	ADC_CFGR_DMAEN_Enabled = 0x1

	// CFGR2: configuration register
	// Position of ROVSM field.
	ADC_CFGR2_ROVSM_Pos = 0xa
	// Bit mask of ROVSM field.
	ADC_CFGR2_ROVSM_Msk = 0x400
	// Bit ROVSM.
	ADC_CFGR2_ROVSM = 0x400
	// When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
	ADC_CFGR2_ROVSM_ContinuedMode = 0x0
	// When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
	ADC_CFGR2_ROVSM_ResumedMode = 0x1
	// Position of TOVS field.
	ADC_CFGR2_TOVS_Pos = 0x9
	// Bit mask of TOVS field.
	ADC_CFGR2_TOVS_Msk = 0x200
	// Bit TOVS.
	ADC_CFGR2_TOVS = 0x200
	// All oversampled conversions for a channel are done consecutively following a trigger
	ADC_CFGR2_TOVS_All = 0x0
	// Each oversampled conversion for a channel needs a new trigger
	ADC_CFGR2_TOVS_Single = 0x1
	// Position of OVSS field.
	ADC_CFGR2_OVSS_Pos = 0x5
	// Bit mask of OVSS field.
	ADC_CFGR2_OVSS_Msk = 0x1e0
	// No Shift
	ADC_CFGR2_OVSS_NoShift = 0x0
	// Shift 1-bit
	ADC_CFGR2_OVSS_Shift1Bit = 0x1
	// Shift 2-bit
	ADC_CFGR2_OVSS_Shift2Bit = 0x2
	// Shift 3-bit
	ADC_CFGR2_OVSS_Shift3Bit = 0x3
	// Shift 4-bit
	ADC_CFGR2_OVSS_Shift4Bit = 0x4
	// Shift 5-bit
	ADC_CFGR2_OVSS_Shift5Bit = 0x5
	// Shift 6-bit
	ADC_CFGR2_OVSS_Shift6Bit = 0x6
	// Shift 7-bit
	ADC_CFGR2_OVSS_Shift7Bit = 0x7
	// Shift 8-bit
	ADC_CFGR2_OVSS_Shift8Bit = 0x8
	// Position of OVSR field.
	ADC_CFGR2_OVSR_Pos = 0x2
	// Bit mask of OVSR field.
	ADC_CFGR2_OVSR_Msk = 0x1c
	// 2x
	ADC_CFGR2_OVSR_Ratio2 = 0x0
	// 4x
	ADC_CFGR2_OVSR_Ratio4 = 0x1
	// 8x
	ADC_CFGR2_OVSR_Ratio8 = 0x2
	// 16x
	ADC_CFGR2_OVSR_Ratio16 = 0x3
	// 32x
	ADC_CFGR2_OVSR_Ratio32 = 0x4
	// 64x
	ADC_CFGR2_OVSR_Ratio64 = 0x5
	// 128x
	ADC_CFGR2_OVSR_Ratio128 = 0x6
	// 256x
	ADC_CFGR2_OVSR_Ratio256 = 0x7
	// Position of JOVSE field.
	ADC_CFGR2_JOVSE_Pos = 0x1
	// Bit mask of JOVSE field.
	ADC_CFGR2_JOVSE_Msk = 0x2
	// Bit JOVSE.
	ADC_CFGR2_JOVSE = 0x2
	// Injected Oversampling disabled
	ADC_CFGR2_JOVSE_Disabled = 0x0
	// Injected Oversampling enabled
	ADC_CFGR2_JOVSE_Enabled = 0x1
	// Position of ROVSE field.
	ADC_CFGR2_ROVSE_Pos = 0x0
	// Bit mask of ROVSE field.
	ADC_CFGR2_ROVSE_Msk = 0x1
	// Bit ROVSE.
	ADC_CFGR2_ROVSE = 0x1
	// Regular Oversampling disabled
	ADC_CFGR2_ROVSE_Disabled = 0x0
	// Regular Oversampling enabled
	ADC_CFGR2_ROVSE_Enabled = 0x1

	// SMPR1: sample time register 1
	// Position of SMP0 field.
	ADC_SMPR1_SMP0_Pos = 0x3
	// Bit mask of SMP0 field.
	ADC_SMPR1_SMP0_Msk = 0x38
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP0_Cycles640_5 = 0x7
	// Position of SMP1 field.
	ADC_SMPR1_SMP1_Pos = 0x6
	// Bit mask of SMP1 field.
	ADC_SMPR1_SMP1_Msk = 0x1c0
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP1_Cycles640_5 = 0x7
	// Position of SMP2 field.
	ADC_SMPR1_SMP2_Pos = 0x9
	// Bit mask of SMP2 field.
	ADC_SMPR1_SMP2_Msk = 0xe00
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP2_Cycles640_5 = 0x7
	// Position of SMP3 field.
	ADC_SMPR1_SMP3_Pos = 0xc
	// Bit mask of SMP3 field.
	ADC_SMPR1_SMP3_Msk = 0x7000
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP3_Cycles640_5 = 0x7
	// Position of SMP4 field.
	ADC_SMPR1_SMP4_Pos = 0xf
	// Bit mask of SMP4 field.
	ADC_SMPR1_SMP4_Msk = 0x38000
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP4_Cycles640_5 = 0x7
	// Position of SMP5 field.
	ADC_SMPR1_SMP5_Pos = 0x12
	// Bit mask of SMP5 field.
	ADC_SMPR1_SMP5_Msk = 0x1c0000
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP5_Cycles640_5 = 0x7
	// Position of SMP6 field.
	ADC_SMPR1_SMP6_Pos = 0x15
	// Bit mask of SMP6 field.
	ADC_SMPR1_SMP6_Msk = 0xe00000
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP6_Cycles640_5 = 0x7
	// Position of SMP7 field.
	ADC_SMPR1_SMP7_Pos = 0x18
	// Bit mask of SMP7 field.
	ADC_SMPR1_SMP7_Msk = 0x7000000
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP7_Cycles640_5 = 0x7
	// Position of SMP8 field.
	ADC_SMPR1_SMP8_Pos = 0x1b
	// Bit mask of SMP8 field.
	ADC_SMPR1_SMP8_Msk = 0x38000000
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP8_Cycles640_5 = 0x7
	// Position of SMP9 field.
	ADC_SMPR1_SMP9_Pos = 0x1e
	// Bit mask of SMP9 field.
	ADC_SMPR1_SMP9_Msk = 0x1c0000000
	// 2.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR1_SMP9_Cycles640_5 = 0x7

	// SMPR2: sample time register 2
	// Position of SMP10 field.
	ADC_SMPR2_SMP10_Pos = 0x3
	// Bit mask of SMP10 field.
	ADC_SMPR2_SMP10_Msk = 0x38
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP10_Cycles640_5 = 0x7
	// Position of SMP11 field.
	ADC_SMPR2_SMP11_Pos = 0x6
	// Bit mask of SMP11 field.
	ADC_SMPR2_SMP11_Msk = 0x1c0
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP11_Cycles640_5 = 0x7
	// Position of SMP12 field.
	ADC_SMPR2_SMP12_Pos = 0x9
	// Bit mask of SMP12 field.
	ADC_SMPR2_SMP12_Msk = 0xe00
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP12_Cycles640_5 = 0x7
	// Position of SMP13 field.
	ADC_SMPR2_SMP13_Pos = 0xc
	// Bit mask of SMP13 field.
	ADC_SMPR2_SMP13_Msk = 0x7000
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP13_Cycles640_5 = 0x7
	// Position of SMP14 field.
	ADC_SMPR2_SMP14_Pos = 0xf
	// Bit mask of SMP14 field.
	ADC_SMPR2_SMP14_Msk = 0x38000
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP14_Cycles640_5 = 0x7
	// Position of SMP15 field.
	ADC_SMPR2_SMP15_Pos = 0x12
	// Bit mask of SMP15 field.
	ADC_SMPR2_SMP15_Msk = 0x1c0000
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP15_Cycles640_5 = 0x7
	// Position of SMP16 field.
	ADC_SMPR2_SMP16_Pos = 0x15
	// Bit mask of SMP16 field.
	ADC_SMPR2_SMP16_Msk = 0xe00000
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP16_Cycles640_5 = 0x7
	// Position of SMP17 field.
	ADC_SMPR2_SMP17_Pos = 0x18
	// Bit mask of SMP17 field.
	ADC_SMPR2_SMP17_Msk = 0x7000000
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP17_Cycles640_5 = 0x7
	// Position of SMP18 field.
	ADC_SMPR2_SMP18_Pos = 0x1b
	// Bit mask of SMP18 field.
	ADC_SMPR2_SMP18_Msk = 0x38000000
	// 2.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles2_5 = 0x0
	// 6.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles6_5 = 0x1
	// 12.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles12_5 = 0x2
	// 24.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles24_5 = 0x3
	// 47.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles47_5 = 0x4
	// 92.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles92_5 = 0x5
	// 247.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles247_5 = 0x6
	// 640.5 ADC clock cycles
	ADC_SMPR2_SMP18_Cycles640_5 = 0x7

	// TR1: watchdog threshold register 1
	// Position of HT1 field.
	ADC_TR1_HT1_Pos = 0x10
	// Bit mask of HT1 field.
	ADC_TR1_HT1_Msk = 0xfff0000
	// Position of LT1 field.
	ADC_TR1_LT1_Pos = 0x0
	// Bit mask of LT1 field.
	ADC_TR1_LT1_Msk = 0xfff

	// TR2: watchdog threshold register
	// Position of HT2 field.
	ADC_TR2_HT2_Pos = 0x10
	// Bit mask of HT2 field.
	ADC_TR2_HT2_Msk = 0xff0000
	// Position of LT2 field.
	ADC_TR2_LT2_Pos = 0x0
	// Bit mask of LT2 field.
	ADC_TR2_LT2_Msk = 0xff

	// TR3: watchdog threshold register 3
	// Position of HT3 field.
	ADC_TR3_HT3_Pos = 0x10
	// Bit mask of HT3 field.
	ADC_TR3_HT3_Msk = 0xff0000
	// Position of LT3 field.
	ADC_TR3_LT3_Pos = 0x0
	// Bit mask of LT3 field.
	ADC_TR3_LT3_Msk = 0xff

	// SQR1: regular sequence register 1
	// Position of SQ1 field.
	ADC_SQR1_SQ1_Pos = 0xc
	// Bit mask of SQ1 field.
	ADC_SQR1_SQ1_Msk = 0x1f000
	// Position of SQ2 field.
	ADC_SQR1_SQ2_Pos = 0x12
	// Bit mask of SQ2 field.
	ADC_SQR1_SQ2_Msk = 0x7c0000
	// Position of SQ3 field.
	ADC_SQR1_SQ3_Pos = 0x18
	// Bit mask of SQ3 field.
	ADC_SQR1_SQ3_Msk = 0x1f000000
	// Position of SQ4 field.
	ADC_SQR1_SQ4_Pos = 0x1e
	// Bit mask of SQ4 field.
	ADC_SQR1_SQ4_Msk = 0x7c0000000
	// Position of L field.
	ADC_SQR1_L_Pos = 0x0
	// Bit mask of L field.
	ADC_SQR1_L_Msk = 0xf

	// SQR2: regular sequence register 2
	// Position of SQ5 field.
	ADC_SQR2_SQ5_Pos = 0x6
	// Bit mask of SQ5 field.
	ADC_SQR2_SQ5_Msk = 0x7c0
	// Position of SQ6 field.
	ADC_SQR2_SQ6_Pos = 0xc
	// Bit mask of SQ6 field.
	ADC_SQR2_SQ6_Msk = 0x1f000
	// Position of SQ7 field.
	ADC_SQR2_SQ7_Pos = 0x12
	// Bit mask of SQ7 field.
	ADC_SQR2_SQ7_Msk = 0x7c0000
	// Position of SQ8 field.
	ADC_SQR2_SQ8_Pos = 0x18
	// Bit mask of SQ8 field.
	ADC_SQR2_SQ8_Msk = 0x1f000000
	// Position of SQ9 field.
	ADC_SQR2_SQ9_Pos = 0x1e
	// Bit mask of SQ9 field.
	ADC_SQR2_SQ9_Msk = 0x7c0000000

	// SQR3: regular sequence register 3
	// Position of SQ10 field.
	ADC_SQR3_SQ10_Pos = 0x6
	// Bit mask of SQ10 field.
	ADC_SQR3_SQ10_Msk = 0x7c0
	// Position of SQ11 field.
	ADC_SQR3_SQ11_Pos = 0xc
	// Bit mask of SQ11 field.
	ADC_SQR3_SQ11_Msk = 0x1f000
	// Position of SQ12 field.
	ADC_SQR3_SQ12_Pos = 0x12
	// Bit mask of SQ12 field.
	ADC_SQR3_SQ12_Msk = 0x7c0000
	// Position of SQ13 field.
	ADC_SQR3_SQ13_Pos = 0x18
	// Bit mask of SQ13 field.
	ADC_SQR3_SQ13_Msk = 0x1f000000
	// Position of SQ14 field.
	ADC_SQR3_SQ14_Pos = 0x1e
	// Bit mask of SQ14 field.
	ADC_SQR3_SQ14_Msk = 0x7c0000000

	// SQR4: regular sequence register 4
	// Position of SQ15 field.
	ADC_SQR4_SQ15_Pos = 0x6
	// Bit mask of SQ15 field.
	ADC_SQR4_SQ15_Msk = 0x7c0
	// Position of SQ16 field.
	ADC_SQR4_SQ16_Pos = 0xc
	// Bit mask of SQ16 field.
	ADC_SQR4_SQ16_Msk = 0x1f000

	// DR: regular Data Register
	// Position of RDATA field.
	ADC_DR_RDATA_Pos = 0x0
	// Bit mask of RDATA field.
	ADC_DR_RDATA_Msk = 0xffff

	// JSQR: injected sequence register
	// Position of JSQ1 field.
	ADC_JSQR_JSQ1_Pos = 0xe
	// Bit mask of JSQ1 field.
	ADC_JSQR_JSQ1_Msk = 0x7c000
	// Position of JSQ2 field.
	ADC_JSQR_JSQ2_Pos = 0x14
	// Bit mask of JSQ2 field.
	ADC_JSQR_JSQ2_Msk = 0x1f00000
	// Position of JSQ3 field.
	ADC_JSQR_JSQ3_Pos = 0x1a
	// Bit mask of JSQ3 field.
	ADC_JSQR_JSQ3_Msk = 0x7c000000
	// Position of JSQ4 field.
	ADC_JSQR_JSQ4_Pos = 0x20
	// Bit mask of JSQ4 field.
	ADC_JSQR_JSQ4_Msk = 0x1f00000000
	// Position of JEXTEN field.
	ADC_JSQR_JEXTEN_Pos = 0x6
	// Bit mask of JEXTEN field.
	ADC_JSQR_JEXTEN_Msk = 0xc0
	// Trigger detection disabled
	ADC_JSQR_JEXTEN_Disabled = 0x0
	// Trigger detection on the rising edge
	ADC_JSQR_JEXTEN_RisingEdge = 0x1
	// Trigger detection on the falling edge
	ADC_JSQR_JEXTEN_FallingEdge = 0x2
	// Trigger detection on both the rising and falling edges
	ADC_JSQR_JEXTEN_BothEdges = 0x3
	// Position of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Pos = 0x2
	// Bit mask of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Msk = 0x3c
	// Timer 1 TRGO event
	ADC_JSQR_JEXTSEL_TIM1_TRGO = 0x0
	// Timer 1 CC4 event
	ADC_JSQR_JEXTSEL_TIM1_CC4 = 0x1
	// Timer 2 TRGO event
	ADC_JSQR_JEXTSEL_TIM2_TRGO = 0x2
	// Timer 2 CC1 event
	ADC_JSQR_JEXTSEL_TIM2_CC1 = 0x3
	// Timer 3 CC4 event
	ADC_JSQR_JEXTSEL_TIM3_CC4 = 0x4
	// EXTI line 15
	ADC_JSQR_JEXTSEL_EXTI15 = 0x6
	// Timer 1 TRGO2 event
	ADC_JSQR_JEXTSEL_TIM1_TRGO2 = 0x8
	// Timer 3 CC3 event
	ADC_JSQR_JEXTSEL_TIM3_CC3 = 0xb
	// Timer 3 TRGO event
	ADC_JSQR_JEXTSEL_TIM3_TRGO = 0xc
	// Timer 3 CC1 event
	ADC_JSQR_JEXTSEL_TIM3_CC1 = 0xd
	// Timer 6 TRGO event
	ADC_JSQR_JEXTSEL_TIM6_TRGO = 0xe
	// Timer 15 TRGO event
	ADC_JSQR_JEXTSEL_TIM15_TRGO = 0xf
	// Position of JL field.
	ADC_JSQR_JL_Pos = 0x0
	// Bit mask of JL field.
	ADC_JSQR_JL_Msk = 0x3

	// OFR1: offset register %s
	// Position of OFFSET_EN field.
	ADC_OFR_OFFSET_EN_Pos = 0x1f
	// Bit mask of OFFSET_EN field.
	ADC_OFR_OFFSET_EN_Msk = 0x80000000
	// Bit OFFSET_EN.
	ADC_OFR_OFFSET_EN = 0x80000000
	// This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
	ADC_OFR_OFFSET_EN_Disabled = 0x0
	// This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
	ADC_OFR_OFFSET_EN_Enabled = 0x1
	// Position of OFFSET_CH field.
	ADC_OFR_OFFSET_CH_Pos = 0x1a
	// Bit mask of OFFSET_CH field.
	ADC_OFR_OFFSET_CH_Msk = 0x7c000000
	// Position of OFFSET field.
	ADC_OFR_OFFSET_Pos = 0x0
	// Bit mask of OFFSET field.
	ADC_OFR_OFFSET_Msk = 0xfff

	// JDR1: injected data register %s
	// Position of JDATA field.
	ADC_JDR_JDATA_Pos = 0x0
	// Bit mask of JDATA field.
	ADC_JDR_JDATA_Msk = 0xffff

	// AWD2CR: Analog Watchdog 2 Configuration Register
	// Position of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Pos = 0x1
	// Bit mask of AWD2CH0 field.
	ADC_AWD2CR_AWD2CH0_Msk = 0x2
	// Bit AWD2CH0.
	ADC_AWD2CR_AWD2CH0 = 0x2
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH0_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH0_Monitored = 0x1
	// Position of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Pos = 0x2
	// Bit mask of AWD2CH1 field.
	ADC_AWD2CR_AWD2CH1_Msk = 0x4
	// Bit AWD2CH1.
	ADC_AWD2CR_AWD2CH1 = 0x4
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH1_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH1_Monitored = 0x1
	// Position of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Pos = 0x3
	// Bit mask of AWD2CH2 field.
	ADC_AWD2CR_AWD2CH2_Msk = 0x8
	// Bit AWD2CH2.
	ADC_AWD2CR_AWD2CH2 = 0x8
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH2_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH2_Monitored = 0x1
	// Position of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Pos = 0x4
	// Bit mask of AWD2CH3 field.
	ADC_AWD2CR_AWD2CH3_Msk = 0x10
	// Bit AWD2CH3.
	ADC_AWD2CR_AWD2CH3 = 0x10
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH3_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH3_Monitored = 0x1
	// Position of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Pos = 0x5
	// Bit mask of AWD2CH4 field.
	ADC_AWD2CR_AWD2CH4_Msk = 0x20
	// Bit AWD2CH4.
	ADC_AWD2CR_AWD2CH4 = 0x20
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH4_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH4_Monitored = 0x1
	// Position of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Pos = 0x6
	// Bit mask of AWD2CH5 field.
	ADC_AWD2CR_AWD2CH5_Msk = 0x40
	// Bit AWD2CH5.
	ADC_AWD2CR_AWD2CH5 = 0x40
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH5_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH5_Monitored = 0x1
	// Position of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Pos = 0x7
	// Bit mask of AWD2CH6 field.
	ADC_AWD2CR_AWD2CH6_Msk = 0x80
	// Bit AWD2CH6.
	ADC_AWD2CR_AWD2CH6 = 0x80
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH6_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH6_Monitored = 0x1
	// Position of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Pos = 0x8
	// Bit mask of AWD2CH7 field.
	ADC_AWD2CR_AWD2CH7_Msk = 0x100
	// Bit AWD2CH7.
	ADC_AWD2CR_AWD2CH7 = 0x100
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH7_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH7_Monitored = 0x1
	// Position of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Pos = 0x9
	// Bit mask of AWD2CH8 field.
	ADC_AWD2CR_AWD2CH8_Msk = 0x200
	// Bit AWD2CH8.
	ADC_AWD2CR_AWD2CH8 = 0x200
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH8_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH8_Monitored = 0x1
	// Position of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Pos = 0xa
	// Bit mask of AWD2CH9 field.
	ADC_AWD2CR_AWD2CH9_Msk = 0x400
	// Bit AWD2CH9.
	ADC_AWD2CR_AWD2CH9 = 0x400
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH9_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH9_Monitored = 0x1
	// Position of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Pos = 0xb
	// Bit mask of AWD2CH10 field.
	ADC_AWD2CR_AWD2CH10_Msk = 0x800
	// Bit AWD2CH10.
	ADC_AWD2CR_AWD2CH10 = 0x800
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH10_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH10_Monitored = 0x1
	// Position of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Pos = 0xc
	// Bit mask of AWD2CH11 field.
	ADC_AWD2CR_AWD2CH11_Msk = 0x1000
	// Bit AWD2CH11.
	ADC_AWD2CR_AWD2CH11 = 0x1000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH11_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH11_Monitored = 0x1
	// Position of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Pos = 0xd
	// Bit mask of AWD2CH12 field.
	ADC_AWD2CR_AWD2CH12_Msk = 0x2000
	// Bit AWD2CH12.
	ADC_AWD2CR_AWD2CH12 = 0x2000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH12_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH12_Monitored = 0x1
	// Position of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Pos = 0xe
	// Bit mask of AWD2CH13 field.
	ADC_AWD2CR_AWD2CH13_Msk = 0x4000
	// Bit AWD2CH13.
	ADC_AWD2CR_AWD2CH13 = 0x4000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH13_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH13_Monitored = 0x1
	// Position of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Pos = 0xf
	// Bit mask of AWD2CH14 field.
	ADC_AWD2CR_AWD2CH14_Msk = 0x8000
	// Bit AWD2CH14.
	ADC_AWD2CR_AWD2CH14 = 0x8000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH14_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH14_Monitored = 0x1
	// Position of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Pos = 0x10
	// Bit mask of AWD2CH15 field.
	ADC_AWD2CR_AWD2CH15_Msk = 0x10000
	// Bit AWD2CH15.
	ADC_AWD2CR_AWD2CH15 = 0x10000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH15_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH15_Monitored = 0x1
	// Position of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Pos = 0x11
	// Bit mask of AWD2CH16 field.
	ADC_AWD2CR_AWD2CH16_Msk = 0x20000
	// Bit AWD2CH16.
	ADC_AWD2CR_AWD2CH16 = 0x20000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH16_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH16_Monitored = 0x1
	// Position of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Pos = 0x12
	// Bit mask of AWD2CH17 field.
	ADC_AWD2CR_AWD2CH17_Msk = 0x40000
	// Bit AWD2CH17.
	ADC_AWD2CR_AWD2CH17 = 0x40000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH17_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH17_Monitored = 0x1
	// Position of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Pos = 0x13
	// Bit mask of AWD2CH18 field.
	ADC_AWD2CR_AWD2CH18_Msk = 0x80000
	// Bit AWD2CH18.
	ADC_AWD2CR_AWD2CH18 = 0x80000
	// Input channel not monitored by AWDx
	ADC_AWD2CR_AWD2CH18_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD2CR_AWD2CH18_Monitored = 0x1

	// AWD3CR: Analog Watchdog 3 Configuration Register
	// Position of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Pos = 0x1
	// Bit mask of AWD3CH0 field.
	ADC_AWD3CR_AWD3CH0_Msk = 0x2
	// Bit AWD3CH0.
	ADC_AWD3CR_AWD3CH0 = 0x2
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH0_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH0_Monitored = 0x1
	// Position of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Pos = 0x2
	// Bit mask of AWD3CH1 field.
	ADC_AWD3CR_AWD3CH1_Msk = 0x4
	// Bit AWD3CH1.
	ADC_AWD3CR_AWD3CH1 = 0x4
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH1_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH1_Monitored = 0x1
	// Position of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Pos = 0x3
	// Bit mask of AWD3CH2 field.
	ADC_AWD3CR_AWD3CH2_Msk = 0x8
	// Bit AWD3CH2.
	ADC_AWD3CR_AWD3CH2 = 0x8
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH2_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH2_Monitored = 0x1
	// Position of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Pos = 0x4
	// Bit mask of AWD3CH3 field.
	ADC_AWD3CR_AWD3CH3_Msk = 0x10
	// Bit AWD3CH3.
	ADC_AWD3CR_AWD3CH3 = 0x10
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH3_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH3_Monitored = 0x1
	// Position of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Pos = 0x5
	// Bit mask of AWD3CH4 field.
	ADC_AWD3CR_AWD3CH4_Msk = 0x20
	// Bit AWD3CH4.
	ADC_AWD3CR_AWD3CH4 = 0x20
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH4_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH4_Monitored = 0x1
	// Position of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Pos = 0x6
	// Bit mask of AWD3CH5 field.
	ADC_AWD3CR_AWD3CH5_Msk = 0x40
	// Bit AWD3CH5.
	ADC_AWD3CR_AWD3CH5 = 0x40
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH5_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH5_Monitored = 0x1
	// Position of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Pos = 0x7
	// Bit mask of AWD3CH6 field.
	ADC_AWD3CR_AWD3CH6_Msk = 0x80
	// Bit AWD3CH6.
	ADC_AWD3CR_AWD3CH6 = 0x80
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH6_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH6_Monitored = 0x1
	// Position of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Pos = 0x8
	// Bit mask of AWD3CH7 field.
	ADC_AWD3CR_AWD3CH7_Msk = 0x100
	// Bit AWD3CH7.
	ADC_AWD3CR_AWD3CH7 = 0x100
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH7_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH7_Monitored = 0x1
	// Position of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Pos = 0x9
	// Bit mask of AWD3CH8 field.
	ADC_AWD3CR_AWD3CH8_Msk = 0x200
	// Bit AWD3CH8.
	ADC_AWD3CR_AWD3CH8 = 0x200
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH8_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH8_Monitored = 0x1
	// Position of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Pos = 0xa
	// Bit mask of AWD3CH9 field.
	ADC_AWD3CR_AWD3CH9_Msk = 0x400
	// Bit AWD3CH9.
	ADC_AWD3CR_AWD3CH9 = 0x400
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH9_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH9_Monitored = 0x1
	// Position of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Pos = 0xb
	// Bit mask of AWD3CH10 field.
	ADC_AWD3CR_AWD3CH10_Msk = 0x800
	// Bit AWD3CH10.
	ADC_AWD3CR_AWD3CH10 = 0x800
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH10_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH10_Monitored = 0x1
	// Position of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Pos = 0xc
	// Bit mask of AWD3CH11 field.
	ADC_AWD3CR_AWD3CH11_Msk = 0x1000
	// Bit AWD3CH11.
	ADC_AWD3CR_AWD3CH11 = 0x1000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH11_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH11_Monitored = 0x1
	// Position of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Pos = 0xd
	// Bit mask of AWD3CH12 field.
	ADC_AWD3CR_AWD3CH12_Msk = 0x2000
	// Bit AWD3CH12.
	ADC_AWD3CR_AWD3CH12 = 0x2000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH12_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH12_Monitored = 0x1
	// Position of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Pos = 0xe
	// Bit mask of AWD3CH13 field.
	ADC_AWD3CR_AWD3CH13_Msk = 0x4000
	// Bit AWD3CH13.
	ADC_AWD3CR_AWD3CH13 = 0x4000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH13_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH13_Monitored = 0x1
	// Position of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Pos = 0xf
	// Bit mask of AWD3CH14 field.
	ADC_AWD3CR_AWD3CH14_Msk = 0x8000
	// Bit AWD3CH14.
	ADC_AWD3CR_AWD3CH14 = 0x8000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH14_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH14_Monitored = 0x1
	// Position of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Pos = 0x10
	// Bit mask of AWD3CH15 field.
	ADC_AWD3CR_AWD3CH15_Msk = 0x10000
	// Bit AWD3CH15.
	ADC_AWD3CR_AWD3CH15 = 0x10000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH15_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH15_Monitored = 0x1
	// Position of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Pos = 0x11
	// Bit mask of AWD3CH16 field.
	ADC_AWD3CR_AWD3CH16_Msk = 0x20000
	// Bit AWD3CH16.
	ADC_AWD3CR_AWD3CH16 = 0x20000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH16_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH16_Monitored = 0x1
	// Position of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Pos = 0x12
	// Bit mask of AWD3CH17 field.
	ADC_AWD3CR_AWD3CH17_Msk = 0x40000
	// Bit AWD3CH17.
	ADC_AWD3CR_AWD3CH17 = 0x40000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH17_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH17_Monitored = 0x1
	// Position of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Pos = 0x13
	// Bit mask of AWD3CH18 field.
	ADC_AWD3CR_AWD3CH18_Msk = 0x80000
	// Bit AWD3CH18.
	ADC_AWD3CR_AWD3CH18 = 0x80000
	// Input channel not monitored by AWDx
	ADC_AWD3CR_AWD3CH18_NotMonitored = 0x0
	// Input channel monitored by AWDx
	ADC_AWD3CR_AWD3CH18_Monitored = 0x1

	// DIFSEL: Differential Mode Selection Register 2
	// Position of DIFSEL0 field.
	ADC_DIFSEL_DIFSEL0_Pos = 0x1
	// Bit mask of DIFSEL0 field.
	ADC_DIFSEL_DIFSEL0_Msk = 0x2
	// Bit DIFSEL0.
	ADC_DIFSEL_DIFSEL0 = 0x2
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL0_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL0_Differential = 0x1
	// Position of DIFSEL1 field.
	ADC_DIFSEL_DIFSEL1_Pos = 0x2
	// Bit mask of DIFSEL1 field.
	ADC_DIFSEL_DIFSEL1_Msk = 0x4
	// Bit DIFSEL1.
	ADC_DIFSEL_DIFSEL1 = 0x4
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL1_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL1_Differential = 0x1
	// Position of DIFSEL2 field.
	ADC_DIFSEL_DIFSEL2_Pos = 0x3
	// Bit mask of DIFSEL2 field.
	ADC_DIFSEL_DIFSEL2_Msk = 0x8
	// Bit DIFSEL2.
	ADC_DIFSEL_DIFSEL2 = 0x8
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL2_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL2_Differential = 0x1
	// Position of DIFSEL3 field.
	ADC_DIFSEL_DIFSEL3_Pos = 0x4
	// Bit mask of DIFSEL3 field.
	ADC_DIFSEL_DIFSEL3_Msk = 0x10
	// Bit DIFSEL3.
	ADC_DIFSEL_DIFSEL3 = 0x10
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL3_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL3_Differential = 0x1
	// Position of DIFSEL4 field.
	ADC_DIFSEL_DIFSEL4_Pos = 0x5
	// Bit mask of DIFSEL4 field.
	ADC_DIFSEL_DIFSEL4_Msk = 0x20
	// Bit DIFSEL4.
	ADC_DIFSEL_DIFSEL4 = 0x20
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL4_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL4_Differential = 0x1
	// Position of DIFSEL5 field.
	ADC_DIFSEL_DIFSEL5_Pos = 0x6
	// Bit mask of DIFSEL5 field.
	ADC_DIFSEL_DIFSEL5_Msk = 0x40
	// Bit DIFSEL5.
	ADC_DIFSEL_DIFSEL5 = 0x40
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL5_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL5_Differential = 0x1
	// Position of DIFSEL6 field.
	ADC_DIFSEL_DIFSEL6_Pos = 0x7
	// Bit mask of DIFSEL6 field.
	ADC_DIFSEL_DIFSEL6_Msk = 0x80
	// Bit DIFSEL6.
	ADC_DIFSEL_DIFSEL6 = 0x80
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL6_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL6_Differential = 0x1
	// Position of DIFSEL7 field.
	ADC_DIFSEL_DIFSEL7_Pos = 0x8
	// Bit mask of DIFSEL7 field.
	ADC_DIFSEL_DIFSEL7_Msk = 0x100
	// Bit DIFSEL7.
	ADC_DIFSEL_DIFSEL7 = 0x100
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL7_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL7_Differential = 0x1
	// Position of DIFSEL8 field.
	ADC_DIFSEL_DIFSEL8_Pos = 0x9
	// Bit mask of DIFSEL8 field.
	ADC_DIFSEL_DIFSEL8_Msk = 0x200
	// Bit DIFSEL8.
	ADC_DIFSEL_DIFSEL8 = 0x200
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL8_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL8_Differential = 0x1
	// Position of DIFSEL9 field.
	ADC_DIFSEL_DIFSEL9_Pos = 0xa
	// Bit mask of DIFSEL9 field.
	ADC_DIFSEL_DIFSEL9_Msk = 0x400
	// Bit DIFSEL9.
	ADC_DIFSEL_DIFSEL9 = 0x400
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL9_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL9_Differential = 0x1
	// Position of DIFSEL10 field.
	ADC_DIFSEL_DIFSEL10_Pos = 0xb
	// Bit mask of DIFSEL10 field.
	ADC_DIFSEL_DIFSEL10_Msk = 0x800
	// Bit DIFSEL10.
	ADC_DIFSEL_DIFSEL10 = 0x800
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL10_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL10_Differential = 0x1
	// Position of DIFSEL11 field.
	ADC_DIFSEL_DIFSEL11_Pos = 0xc
	// Bit mask of DIFSEL11 field.
	ADC_DIFSEL_DIFSEL11_Msk = 0x1000
	// Bit DIFSEL11.
	ADC_DIFSEL_DIFSEL11 = 0x1000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL11_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL11_Differential = 0x1
	// Position of DIFSEL12 field.
	ADC_DIFSEL_DIFSEL12_Pos = 0xd
	// Bit mask of DIFSEL12 field.
	ADC_DIFSEL_DIFSEL12_Msk = 0x2000
	// Bit DIFSEL12.
	ADC_DIFSEL_DIFSEL12 = 0x2000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL12_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL12_Differential = 0x1
	// Position of DIFSEL13 field.
	ADC_DIFSEL_DIFSEL13_Pos = 0xe
	// Bit mask of DIFSEL13 field.
	ADC_DIFSEL_DIFSEL13_Msk = 0x4000
	// Bit DIFSEL13.
	ADC_DIFSEL_DIFSEL13 = 0x4000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL13_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL13_Differential = 0x1
	// Position of DIFSEL14 field.
	ADC_DIFSEL_DIFSEL14_Pos = 0xf
	// Bit mask of DIFSEL14 field.
	ADC_DIFSEL_DIFSEL14_Msk = 0x8000
	// Bit DIFSEL14.
	ADC_DIFSEL_DIFSEL14 = 0x8000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL14_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL14_Differential = 0x1
	// Position of DIFSEL15 field.
	ADC_DIFSEL_DIFSEL15_Pos = 0x10
	// Bit mask of DIFSEL15 field.
	ADC_DIFSEL_DIFSEL15_Msk = 0x10000
	// Bit DIFSEL15.
	ADC_DIFSEL_DIFSEL15 = 0x10000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL15_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL15_Differential = 0x1
	// Position of DIFSEL16 field.
	ADC_DIFSEL_DIFSEL16_Pos = 0x11
	// Bit mask of DIFSEL16 field.
	ADC_DIFSEL_DIFSEL16_Msk = 0x20000
	// Bit DIFSEL16.
	ADC_DIFSEL_DIFSEL16 = 0x20000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL16_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL16_Differential = 0x1
	// Position of DIFSEL17 field.
	ADC_DIFSEL_DIFSEL17_Pos = 0x12
	// Bit mask of DIFSEL17 field.
	ADC_DIFSEL_DIFSEL17_Msk = 0x40000
	// Bit DIFSEL17.
	ADC_DIFSEL_DIFSEL17 = 0x40000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL17_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL17_Differential = 0x1
	// Position of DIFSEL18 field.
	ADC_DIFSEL_DIFSEL18_Pos = 0x13
	// Bit mask of DIFSEL18 field.
	ADC_DIFSEL_DIFSEL18_Msk = 0x80000
	// Bit DIFSEL18.
	ADC_DIFSEL_DIFSEL18 = 0x80000
	// Input channel is configured in single-ended mode
	ADC_DIFSEL_DIFSEL18_SingleEnded = 0x0
	// Input channel is configured in differential mode
	ADC_DIFSEL_DIFSEL18_Differential = 0x1

	// CALFACT: Calibration Factors
	// Position of CALFACT_D field.
	ADC_CALFACT_CALFACT_D_Pos = 0x10
	// Bit mask of CALFACT_D field.
	ADC_CALFACT_CALFACT_D_Msk = 0x7f0000
	// Position of CALFACT_S field.
	ADC_CALFACT_CALFACT_S_Pos = 0x0
	// Bit mask of CALFACT_S field.
	ADC_CALFACT_CALFACT_S_Msk = 0x7f
)

// Constants for ADC_Common: Analog-to-Digital Converter
const (
	// CSR: ADC Common status register
	// Position of ADRDY_MST field.
	ADC_Common_CSR_ADRDY_MST_Pos = 0x0
	// Bit mask of ADRDY_MST field.
	ADC_Common_CSR_ADRDY_MST_Msk = 0x1
	// Bit ADRDY_MST.
	ADC_Common_CSR_ADRDY_MST = 0x1
	// ADC is not ready to start conversion
	ADC_Common_CSR_ADRDY_MST_NotReady = 0x0
	// ADC is ready to start conversion
	ADC_Common_CSR_ADRDY_MST_Ready = 0x1
	// Position of EOSMP_MST field.
	ADC_Common_CSR_EOSMP_MST_Pos = 0x1
	// Bit mask of EOSMP_MST field.
	ADC_Common_CSR_EOSMP_MST_Msk = 0x2
	// Bit EOSMP_MST.
	ADC_Common_CSR_EOSMP_MST = 0x2
	// End of sampling phase no yet reached
	ADC_Common_CSR_EOSMP_MST_NotEnded = 0x0
	// End of sampling phase reached
	ADC_Common_CSR_EOSMP_MST_Ended = 0x1
	// Position of EOC_MST field.
	ADC_Common_CSR_EOC_MST_Pos = 0x2
	// Bit mask of EOC_MST field.
	ADC_Common_CSR_EOC_MST_Msk = 0x4
	// Bit EOC_MST.
	ADC_Common_CSR_EOC_MST = 0x4
	// Regular conversion is not complete
	ADC_Common_CSR_EOC_MST_NotComplete = 0x0
	// Regular conversion complete
	ADC_Common_CSR_EOC_MST_Complete = 0x1
	// Position of EOS_MST field.
	ADC_Common_CSR_EOS_MST_Pos = 0x3
	// Bit mask of EOS_MST field.
	ADC_Common_CSR_EOS_MST_Msk = 0x8
	// Bit EOS_MST.
	ADC_Common_CSR_EOS_MST = 0x8
	// Regular sequence is not complete
	ADC_Common_CSR_EOS_MST_NotComplete = 0x0
	// Regular sequence complete
	ADC_Common_CSR_EOS_MST_Complete = 0x1
	// Position of OVR_MST field.
	ADC_Common_CSR_OVR_MST_Pos = 0x4
	// Bit mask of OVR_MST field.
	ADC_Common_CSR_OVR_MST_Msk = 0x10
	// Bit OVR_MST.
	ADC_Common_CSR_OVR_MST = 0x10
	// No overrun occurred
	ADC_Common_CSR_OVR_MST_NoOverrun = 0x0
	// Overrun occurred
	ADC_Common_CSR_OVR_MST_Overrun = 0x1
	// Position of JEOC_MST field.
	ADC_Common_CSR_JEOC_MST_Pos = 0x5
	// Bit mask of JEOC_MST field.
	ADC_Common_CSR_JEOC_MST_Msk = 0x20
	// Bit JEOC_MST.
	ADC_Common_CSR_JEOC_MST = 0x20
	// Injected conversion is not complete
	ADC_Common_CSR_JEOC_MST_NotComplete = 0x0
	// Injected conversion complete
	ADC_Common_CSR_JEOC_MST_Complete = 0x1
	// Position of JEOS_MST field.
	ADC_Common_CSR_JEOS_MST_Pos = 0x6
	// Bit mask of JEOS_MST field.
	ADC_Common_CSR_JEOS_MST_Msk = 0x40
	// Bit JEOS_MST.
	ADC_Common_CSR_JEOS_MST = 0x40
	// Injected sequence is not complete
	ADC_Common_CSR_JEOS_MST_NotComplete = 0x0
	// Injected sequence complete
	ADC_Common_CSR_JEOS_MST_Complete = 0x1
	// Position of AWD1_MST field.
	ADC_Common_CSR_AWD1_MST_Pos = 0x7
	// Bit mask of AWD1_MST field.
	ADC_Common_CSR_AWD1_MST_Msk = 0x80
	// Bit AWD1_MST.
	ADC_Common_CSR_AWD1_MST = 0x80
	// No analog watchdog event occurred
	ADC_Common_CSR_AWD1_MST_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_Common_CSR_AWD1_MST_Event = 0x1
	// Position of AWD2_MST field.
	ADC_Common_CSR_AWD2_MST_Pos = 0x8
	// Bit mask of AWD2_MST field.
	ADC_Common_CSR_AWD2_MST_Msk = 0x100
	// Bit AWD2_MST.
	ADC_Common_CSR_AWD2_MST = 0x100
	// No analog watchdog event occurred
	ADC_Common_CSR_AWD2_MST_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_Common_CSR_AWD2_MST_Event = 0x1
	// Position of AWD3_MST field.
	ADC_Common_CSR_AWD3_MST_Pos = 0x9
	// Bit mask of AWD3_MST field.
	ADC_Common_CSR_AWD3_MST_Msk = 0x200
	// Bit AWD3_MST.
	ADC_Common_CSR_AWD3_MST = 0x200
	// No analog watchdog event occurred
	ADC_Common_CSR_AWD3_MST_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_Common_CSR_AWD3_MST_Event = 0x1
	// Position of JQOVF_MST field.
	ADC_Common_CSR_JQOVF_MST_Pos = 0xa
	// Bit mask of JQOVF_MST field.
	ADC_Common_CSR_JQOVF_MST_Msk = 0x400
	// Bit JQOVF_MST.
	ADC_Common_CSR_JQOVF_MST = 0x400
	// No injected context queue overflow has occurred
	ADC_Common_CSR_JQOVF_MST_NoOverflow = 0x0
	// Injected context queue overflow has occurred
	ADC_Common_CSR_JQOVF_MST_Overflow = 0x1
	// Position of ADRDY_SLV field.
	ADC_Common_CSR_ADRDY_SLV_Pos = 0x10
	// Bit mask of ADRDY_SLV field.
	ADC_Common_CSR_ADRDY_SLV_Msk = 0x10000
	// Bit ADRDY_SLV.
	ADC_Common_CSR_ADRDY_SLV = 0x10000
	// ADC is not ready to start conversion
	ADC_Common_CSR_ADRDY_SLV_NotReady = 0x0
	// ADC is ready to start conversion
	ADC_Common_CSR_ADRDY_SLV_Ready = 0x1
	// Position of EOSMP_SLV field.
	ADC_Common_CSR_EOSMP_SLV_Pos = 0x11
	// Bit mask of EOSMP_SLV field.
	ADC_Common_CSR_EOSMP_SLV_Msk = 0x20000
	// Bit EOSMP_SLV.
	ADC_Common_CSR_EOSMP_SLV = 0x20000
	// End of sampling phase no yet reached
	ADC_Common_CSR_EOSMP_SLV_NotEnded = 0x0
	// End of sampling phase reached
	ADC_Common_CSR_EOSMP_SLV_Ended = 0x1
	// Position of EOC_SLV field.
	ADC_Common_CSR_EOC_SLV_Pos = 0x12
	// Bit mask of EOC_SLV field.
	ADC_Common_CSR_EOC_SLV_Msk = 0x40000
	// Bit EOC_SLV.
	ADC_Common_CSR_EOC_SLV = 0x40000
	// Regular conversion is not complete
	ADC_Common_CSR_EOC_SLV_NotComplete = 0x0
	// Regular conversion complete
	ADC_Common_CSR_EOC_SLV_Complete = 0x1
	// Position of EOS_SLV field.
	ADC_Common_CSR_EOS_SLV_Pos = 0x13
	// Bit mask of EOS_SLV field.
	ADC_Common_CSR_EOS_SLV_Msk = 0x80000
	// Bit EOS_SLV.
	ADC_Common_CSR_EOS_SLV = 0x80000
	// Regular sequence is not complete
	ADC_Common_CSR_EOS_SLV_NotComplete = 0x0
	// Regular sequence complete
	ADC_Common_CSR_EOS_SLV_Complete = 0x1
	// Position of OVR_SLV field.
	ADC_Common_CSR_OVR_SLV_Pos = 0x14
	// Bit mask of OVR_SLV field.
	ADC_Common_CSR_OVR_SLV_Msk = 0x100000
	// Bit OVR_SLV.
	ADC_Common_CSR_OVR_SLV = 0x100000
	// No overrun occurred
	ADC_Common_CSR_OVR_SLV_NoOverrun = 0x0
	// Overrun occurred
	ADC_Common_CSR_OVR_SLV_Overrun = 0x1
	// Position of JEOC_SLV field.
	ADC_Common_CSR_JEOC_SLV_Pos = 0x15
	// Bit mask of JEOC_SLV field.
	ADC_Common_CSR_JEOC_SLV_Msk = 0x200000
	// Bit JEOC_SLV.
	ADC_Common_CSR_JEOC_SLV = 0x200000
	// Injected conversion is not complete
	ADC_Common_CSR_JEOC_SLV_NotComplete = 0x0
	// Injected conversion complete
	ADC_Common_CSR_JEOC_SLV_Complete = 0x1
	// Position of JEOS_SLV field.
	ADC_Common_CSR_JEOS_SLV_Pos = 0x16
	// Bit mask of JEOS_SLV field.
	ADC_Common_CSR_JEOS_SLV_Msk = 0x400000
	// Bit JEOS_SLV.
	ADC_Common_CSR_JEOS_SLV = 0x400000
	// Injected sequence is not complete
	ADC_Common_CSR_JEOS_SLV_NotComplete = 0x0
	// Injected sequence complete
	ADC_Common_CSR_JEOS_SLV_Complete = 0x1
	// Position of AWD1_SLV field.
	ADC_Common_CSR_AWD1_SLV_Pos = 0x17
	// Bit mask of AWD1_SLV field.
	ADC_Common_CSR_AWD1_SLV_Msk = 0x800000
	// Bit AWD1_SLV.
	ADC_Common_CSR_AWD1_SLV = 0x800000
	// No analog watchdog event occurred
	ADC_Common_CSR_AWD1_SLV_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_Common_CSR_AWD1_SLV_Event = 0x1
	// Position of AWD2_SLV field.
	ADC_Common_CSR_AWD2_SLV_Pos = 0x18
	// Bit mask of AWD2_SLV field.
	ADC_Common_CSR_AWD2_SLV_Msk = 0x1000000
	// Bit AWD2_SLV.
	ADC_Common_CSR_AWD2_SLV = 0x1000000
	// No analog watchdog event occurred
	ADC_Common_CSR_AWD2_SLV_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_Common_CSR_AWD2_SLV_Event = 0x1
	// Position of AWD3_SLV field.
	ADC_Common_CSR_AWD3_SLV_Pos = 0x19
	// Bit mask of AWD3_SLV field.
	ADC_Common_CSR_AWD3_SLV_Msk = 0x2000000
	// Bit AWD3_SLV.
	ADC_Common_CSR_AWD3_SLV = 0x2000000
	// No analog watchdog event occurred
	ADC_Common_CSR_AWD3_SLV_NoEvent = 0x0
	// Analog watchdog event occurred
	ADC_Common_CSR_AWD3_SLV_Event = 0x1
	// Position of JQOVF_SLV field.
	ADC_Common_CSR_JQOVF_SLV_Pos = 0x1a
	// Bit mask of JQOVF_SLV field.
	ADC_Common_CSR_JQOVF_SLV_Msk = 0x4000000
	// Bit JQOVF_SLV.
	ADC_Common_CSR_JQOVF_SLV = 0x4000000
	// No injected context queue overflow has occurred
	ADC_Common_CSR_JQOVF_SLV_NoOverflow = 0x0
	// Injected context queue overflow has occurred
	ADC_Common_CSR_JQOVF_SLV_Overflow = 0x1

	// CCR: ADC common control register
	// Position of CKMODE field.
	ADC_Common_CCR_CKMODE_Pos = 0x10
	// Bit mask of CKMODE field.
	ADC_Common_CCR_CKMODE_Msk = 0x30000
	// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
	ADC_Common_CCR_CKMODE_Asynchronous = 0x0
	// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
	ADC_Common_CCR_CKMODE_SyncDiv1 = 0x1
	// Use AHB clock rcc_hclk3 divided by 2
	ADC_Common_CCR_CKMODE_SyncDiv2 = 0x2
	// Use AHB clock rcc_hclk3 divided by 4
	ADC_Common_CCR_CKMODE_SyncDiv4 = 0x3
	// Position of PRESC field.
	ADC_Common_CCR_PRESC_Pos = 0x12
	// Bit mask of PRESC field.
	ADC_Common_CCR_PRESC_Msk = 0x3c0000
	// Input ADC clock not divided
	ADC_Common_CCR_PRESC_Div1 = 0x0
	// Input ADC clock divided by 2
	ADC_Common_CCR_PRESC_Div2 = 0x1
	// Input ADC clock divided by 4
	ADC_Common_CCR_PRESC_Div4 = 0x2
	// Input ADC clock divided by 6
	ADC_Common_CCR_PRESC_Div6 = 0x3
	// Input ADC clock divided by 8
	ADC_Common_CCR_PRESC_Div8 = 0x4
	// Input ADC clock divided by 10
	ADC_Common_CCR_PRESC_Div10 = 0x5
	// Input ADC clock divided by 12
	ADC_Common_CCR_PRESC_Div12 = 0x6
	// Input ADC clock divided by 16
	ADC_Common_CCR_PRESC_Div16 = 0x7
	// Input ADC clock divided by 32
	ADC_Common_CCR_PRESC_Div32 = 0x8
	// Input ADC clock divided by 64
	ADC_Common_CCR_PRESC_Div64 = 0x9
	// Input ADC clock divided by 128
	ADC_Common_CCR_PRESC_Div128 = 0xa
	// Input ADC clock divided by 256
	ADC_Common_CCR_PRESC_Div256 = 0xb
	// Position of VREFEN field.
	ADC_Common_CCR_VREFEN_Pos = 0x16
	// Bit mask of VREFEN field.
	ADC_Common_CCR_VREFEN_Msk = 0x400000
	// Bit VREFEN.
	ADC_Common_CCR_VREFEN = 0x400000
	// V_REFINT channel disabled
	ADC_Common_CCR_VREFEN_Disabled = 0x0
	// V_REFINT channel enabled
	ADC_Common_CCR_VREFEN_Enabled = 0x1
	// Position of VSENSEEN field.
	ADC_Common_CCR_VSENSEEN_Pos = 0x17
	// Bit mask of VSENSEEN field.
	ADC_Common_CCR_VSENSEEN_Msk = 0x800000
	// Bit VSENSEEN.
	ADC_Common_CCR_VSENSEEN = 0x800000
	// The selected ADC channel disabled
	ADC_Common_CCR_VSENSEEN_Disabled = 0x0
	// The selected ADC channel enabled
	ADC_Common_CCR_VSENSEEN_Enabled = 0x1
	// Position of VBATEN field.
	ADC_Common_CCR_VBATEN_Pos = 0x18
	// Bit mask of VBATEN field.
	ADC_Common_CCR_VBATEN_Msk = 0x1000000
	// Bit VBATEN.
	ADC_Common_CCR_VBATEN = 0x1000000
	// The selected ADC channel disabled
	ADC_Common_CCR_VBATEN_Disabled = 0x0
	// The selected ADC channel enabled
	ADC_Common_CCR_VBATEN_Enabled = 0x1
	// Position of MDMA field.
	ADC_Common_CCR_MDMA_Pos = 0xe
	// Bit mask of MDMA field.
	ADC_Common_CCR_MDMA_Msk = 0xc000
	// MDMA mode disabled
	ADC_Common_CCR_MDMA_Disabled = 0x0
	// Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width)
	ADC_Common_CCR_MDMA_Interleaved = 0x1
	// MDMA mode enabled for 12 and 10-bit resolution
	ADC_Common_CCR_MDMA_Bits12_10 = 0x2
	// MDMA mode enabled for 8 and 6-bit resolution
	ADC_Common_CCR_MDMA_Bits8_6 = 0x3
	// Position of DMACFG field.
	ADC_Common_CCR_DMACFG_Pos = 0xd
	// Bit mask of DMACFG field.
	ADC_Common_CCR_DMACFG_Msk = 0x2000
	// Bit DMACFG.
	ADC_Common_CCR_DMACFG = 0x2000
	// DMA One Shot mode selected
	ADC_Common_CCR_DMACFG_OneShotMode = 0x0
	// DMA Circular mode selected
	ADC_Common_CCR_DMACFG_CircularMode = 0x1
	// Position of DELAY field.
	ADC_Common_CCR_DELAY_Pos = 0x8
	// Bit mask of DELAY field.
	ADC_Common_CCR_DELAY_Msk = 0xf00
	// Position of DUAL field.
	ADC_Common_CCR_DUAL_Pos = 0x0
	// Bit mask of DUAL field.
	ADC_Common_CCR_DUAL_Msk = 0x1f
	// Independent mode
	ADC_Common_CCR_DUAL_Independent = 0x0
	// Dual, combined regular simultaneous + injected simultaneous mode
	ADC_Common_CCR_DUAL_DualRJ = 0x1
	// Dual, combined regular simultaneous + alternate trigger mode
	ADC_Common_CCR_DUAL_DualRA = 0x2
	// Dual, combined interleaved mode + injected simultaneous mode
	ADC_Common_CCR_DUAL_DualIJ = 0x3
	// Dual, injected simultaneous mode only
	ADC_Common_CCR_DUAL_DualJ = 0x5
	// Dual, regular simultaneous mode only
	ADC_Common_CCR_DUAL_DualR = 0x6
	// Dual, interleaved mode only
	ADC_Common_CCR_DUAL_DualI = 0x7
	// Dual, alternate trigger mode only
	ADC_Common_CCR_DUAL_DualA = 0x9

	// CDR: Common regular data register for dual mode
	// Position of RDATA_MST field.
	ADC_Common_CDR_RDATA_MST_Pos = 0x0
	// Bit mask of RDATA_MST field.
	ADC_Common_CDR_RDATA_MST_Msk = 0xffff
	// Position of RDATA_SLV field.
	ADC_Common_CDR_RDATA_SLV_Pos = 0x10
	// Bit mask of RDATA_SLV field.
	ADC_Common_CDR_RDATA_SLV_Msk = 0xffff0000
)

// Constants for COMP: Comparator
const (
	// COMP1_CSR: Comparator 1 control and status register
	// Position of COMP1_EN field.
	COMP_COMP1_CSR_COMP1_EN_Pos = 0x0
	// Bit mask of COMP1_EN field.
	COMP_COMP1_CSR_COMP1_EN_Msk = 0x1
	// Bit COMP1_EN.
	COMP_COMP1_CSR_COMP1_EN = 0x1
	// Position of COMP1_PWRMODE field.
	COMP_COMP1_CSR_COMP1_PWRMODE_Pos = 0x2
	// Bit mask of COMP1_PWRMODE field.
	COMP_COMP1_CSR_COMP1_PWRMODE_Msk = 0xc
	// Position of COMP1_INMSEL field.
	COMP_COMP1_CSR_COMP1_INMSEL_Pos = 0x4
	// Bit mask of COMP1_INMSEL field.
	COMP_COMP1_CSR_COMP1_INMSEL_Msk = 0x70
	// Position of COMP1_INPSEL field.
	COMP_COMP1_CSR_COMP1_INPSEL_Pos = 0x7
	// Bit mask of COMP1_INPSEL field.
	COMP_COMP1_CSR_COMP1_INPSEL_Msk = 0x80
	// Bit COMP1_INPSEL.
	COMP_COMP1_CSR_COMP1_INPSEL = 0x80
	// Position of COMP1_POLARITY field.
	COMP_COMP1_CSR_COMP1_POLARITY_Pos = 0xf
	// Bit mask of COMP1_POLARITY field.
	COMP_COMP1_CSR_COMP1_POLARITY_Msk = 0x8000
	// Bit COMP1_POLARITY.
	COMP_COMP1_CSR_COMP1_POLARITY = 0x8000
	// Position of COMP1_HYST field.
	COMP_COMP1_CSR_COMP1_HYST_Pos = 0x10
	// Bit mask of COMP1_HYST field.
	COMP_COMP1_CSR_COMP1_HYST_Msk = 0x30000
	// Position of COMP1_BLANKING field.
	COMP_COMP1_CSR_COMP1_BLANKING_Pos = 0x12
	// Bit mask of COMP1_BLANKING field.
	COMP_COMP1_CSR_COMP1_BLANKING_Msk = 0x1c0000
	// Position of COMP1_BRGEN field.
	COMP_COMP1_CSR_COMP1_BRGEN_Pos = 0x16
	// Bit mask of COMP1_BRGEN field.
	COMP_COMP1_CSR_COMP1_BRGEN_Msk = 0x400000
	// Bit COMP1_BRGEN.
	COMP_COMP1_CSR_COMP1_BRGEN = 0x400000
	// Position of COMP1_SCALEN field.
	COMP_COMP1_CSR_COMP1_SCALEN_Pos = 0x17
	// Bit mask of COMP1_SCALEN field.
	COMP_COMP1_CSR_COMP1_SCALEN_Msk = 0x800000
	// Bit COMP1_SCALEN.
	COMP_COMP1_CSR_COMP1_SCALEN = 0x800000
	// Position of COMP1_VALUE field.
	COMP_COMP1_CSR_COMP1_VALUE_Pos = 0x1e
	// Bit mask of COMP1_VALUE field.
	COMP_COMP1_CSR_COMP1_VALUE_Msk = 0x40000000
	// Bit COMP1_VALUE.
	COMP_COMP1_CSR_COMP1_VALUE = 0x40000000
	// Position of COMP1_LOCK field.
	COMP_COMP1_CSR_COMP1_LOCK_Pos = 0x1f
	// Bit mask of COMP1_LOCK field.
	COMP_COMP1_CSR_COMP1_LOCK_Msk = 0x80000000
	// Bit COMP1_LOCK.
	COMP_COMP1_CSR_COMP1_LOCK = 0x80000000

	// COMP2_CSR: Comparator 2 control and status register
	// Position of COMP2_EN field.
	COMP_COMP2_CSR_COMP2_EN_Pos = 0x0
	// Bit mask of COMP2_EN field.
	COMP_COMP2_CSR_COMP2_EN_Msk = 0x1
	// Bit COMP2_EN.
	COMP_COMP2_CSR_COMP2_EN = 0x1
	// Position of COMP2_PWRMODE field.
	COMP_COMP2_CSR_COMP2_PWRMODE_Pos = 0x2
	// Bit mask of COMP2_PWRMODE field.
	COMP_COMP2_CSR_COMP2_PWRMODE_Msk = 0xc
	// Position of COMP2_INMSEL field.
	COMP_COMP2_CSR_COMP2_INMSEL_Pos = 0x4
	// Bit mask of COMP2_INMSEL field.
	COMP_COMP2_CSR_COMP2_INMSEL_Msk = 0x70
	// Position of COMP2_INPSEL field.
	COMP_COMP2_CSR_COMP2_INPSEL_Pos = 0x7
	// Bit mask of COMP2_INPSEL field.
	COMP_COMP2_CSR_COMP2_INPSEL_Msk = 0x80
	// Bit COMP2_INPSEL.
	COMP_COMP2_CSR_COMP2_INPSEL = 0x80
	// Position of COMP2_WINMODE field.
	COMP_COMP2_CSR_COMP2_WINMODE_Pos = 0x9
	// Bit mask of COMP2_WINMODE field.
	COMP_COMP2_CSR_COMP2_WINMODE_Msk = 0x200
	// Bit COMP2_WINMODE.
	COMP_COMP2_CSR_COMP2_WINMODE = 0x200
	// Position of COMP2_POLARITY field.
	COMP_COMP2_CSR_COMP2_POLARITY_Pos = 0xf
	// Bit mask of COMP2_POLARITY field.
	COMP_COMP2_CSR_COMP2_POLARITY_Msk = 0x8000
	// Bit COMP2_POLARITY.
	COMP_COMP2_CSR_COMP2_POLARITY = 0x8000
	// Position of COMP2_HYST field.
	COMP_COMP2_CSR_COMP2_HYST_Pos = 0x10
	// Bit mask of COMP2_HYST field.
	COMP_COMP2_CSR_COMP2_HYST_Msk = 0x30000
	// Position of COMP2_BLANKING field.
	COMP_COMP2_CSR_COMP2_BLANKING_Pos = 0x12
	// Bit mask of COMP2_BLANKING field.
	COMP_COMP2_CSR_COMP2_BLANKING_Msk = 0x1c0000
	// Position of COMP2_BRGEN field.
	COMP_COMP2_CSR_COMP2_BRGEN_Pos = 0x16
	// Bit mask of COMP2_BRGEN field.
	COMP_COMP2_CSR_COMP2_BRGEN_Msk = 0x400000
	// Bit COMP2_BRGEN.
	COMP_COMP2_CSR_COMP2_BRGEN = 0x400000
	// Position of COMP2_SCALEN field.
	COMP_COMP2_CSR_COMP2_SCALEN_Pos = 0x17
	// Bit mask of COMP2_SCALEN field.
	COMP_COMP2_CSR_COMP2_SCALEN_Msk = 0x800000
	// Bit COMP2_SCALEN.
	COMP_COMP2_CSR_COMP2_SCALEN = 0x800000
	// Position of COMP2_VALUE field.
	COMP_COMP2_CSR_COMP2_VALUE_Pos = 0x1e
	// Bit mask of COMP2_VALUE field.
	COMP_COMP2_CSR_COMP2_VALUE_Msk = 0x40000000
	// Bit COMP2_VALUE.
	COMP_COMP2_CSR_COMP2_VALUE = 0x40000000
	// Position of COMP2_LOCK field.
	COMP_COMP2_CSR_COMP2_LOCK_Pos = 0x1f
	// Bit mask of COMP2_LOCK field.
	COMP_COMP2_CSR_COMP2_LOCK_Msk = 0x80000000
	// Bit COMP2_LOCK.
	COMP_COMP2_CSR_COMP2_LOCK = 0x80000000
)

// Constants for CRC: Cyclic redundancy check calculation unit
const (
	// DR: Data register
	// Position of DR field.
	CRC_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	CRC_DR_DR_Msk = 0xffffffff

	// DR8: Data register - byte sized
	// Position of DR8 field.
	CRC_DR8_DR8_Pos = 0x0
	// Bit mask of DR8 field.
	CRC_DR8_DR8_Msk = 0xff

	// DR16: Data register - half-word sized
	// Position of DR16 field.
	CRC_DR16_DR16_Pos = 0x0
	// Bit mask of DR16 field.
	CRC_DR16_DR16_Msk = 0xffff

	// IDR: Independent data register
	// Position of IDR field.
	CRC_IDR_IDR_Pos = 0x0
	// Bit mask of IDR field.
	CRC_IDR_IDR_Msk = 0xffffffff

	// CR: Control register
	// Position of REV_OUT field.
	CRC_CR_REV_OUT_Pos = 0x7
	// Bit mask of REV_OUT field.
	CRC_CR_REV_OUT_Msk = 0x80
	// Bit REV_OUT.
	CRC_CR_REV_OUT = 0x80
	// Bit order not affected
	CRC_CR_REV_OUT_Normal = 0x0
	// Bit reversed output
	CRC_CR_REV_OUT_Reversed = 0x1
	// Position of REV_IN field.
	CRC_CR_REV_IN_Pos = 0x5
	// Bit mask of REV_IN field.
	CRC_CR_REV_IN_Msk = 0x60
	// Bit order not affected
	CRC_CR_REV_IN_Normal = 0x0
	// Bit reversal done by byte
	CRC_CR_REV_IN_Byte = 0x1
	// Bit reversal done by half-word
	CRC_CR_REV_IN_HalfWord = 0x2
	// Bit reversal done by word
	CRC_CR_REV_IN_Word = 0x3
	// Position of POLYSIZE field.
	CRC_CR_POLYSIZE_Pos = 0x3
	// Bit mask of POLYSIZE field.
	CRC_CR_POLYSIZE_Msk = 0x18
	// 32-bit polynomial
	CRC_CR_POLYSIZE_Polysize32 = 0x0
	// 16-bit polynomial
	CRC_CR_POLYSIZE_Polysize16 = 0x1
	// 8-bit polynomial
	CRC_CR_POLYSIZE_Polysize8 = 0x2
	// 7-bit polynomial
	CRC_CR_POLYSIZE_Polysize7 = 0x3
	// Position of RESET field.
	CRC_CR_RESET_Pos = 0x0
	// Bit mask of RESET field.
	CRC_CR_RESET_Msk = 0x1
	// Bit RESET.
	CRC_CR_RESET = 0x1
	// Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
	CRC_CR_RESET_Reset = 0x1

	// INIT: Initial CRC value
	// Position of INIT field.
	CRC_INIT_INIT_Pos = 0x0
	// Bit mask of INIT field.
	CRC_INIT_INIT_Msk = 0xffffffff

	// POL: polynomial
	// Position of POL field.
	CRC_POL_POL_Pos = 0x0
	// Bit mask of POL field.
	CRC_POL_POL_Msk = 0xffffffff
)

// Constants for CRS: Clock recovery system
const (
	// CR: control register
	// Position of TRIM field.
	CRS_CR_TRIM_Pos = 0x8
	// Bit mask of TRIM field.
	CRS_CR_TRIM_Msk = 0x7f00
	// Position of SWSYNC field.
	CRS_CR_SWSYNC_Pos = 0x7
	// Bit mask of SWSYNC field.
	CRS_CR_SWSYNC_Msk = 0x80
	// Bit SWSYNC.
	CRS_CR_SWSYNC = 0x80
	// A software sync is generated
	CRS_CR_SWSYNC_Sync = 0x1
	// Position of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Pos = 0x6
	// Bit mask of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Msk = 0x40
	// Bit AUTOTRIMEN.
	CRS_CR_AUTOTRIMEN = 0x40
	// Automatic trimming disabled
	CRS_CR_AUTOTRIMEN_Disabled = 0x0
	// Automatic trimming enabled
	CRS_CR_AUTOTRIMEN_Enabled = 0x1
	// Position of CEN field.
	CRS_CR_CEN_Pos = 0x5
	// Bit mask of CEN field.
	CRS_CR_CEN_Msk = 0x20
	// Bit CEN.
	CRS_CR_CEN = 0x20
	// Frequency error counter disabled
	CRS_CR_CEN_Disabled = 0x0
	// Frequency error counter enabled
	CRS_CR_CEN_Enabled = 0x1
	// Position of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Pos = 0x0
	// Bit mask of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Msk = 0x1
	// Bit SYNCOKIE.
	CRS_CR_SYNCOKIE = 0x1
	// Interrupt disabled
	CRS_CR_SYNCOKIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_SYNCOKIE_Enabled = 0x1
	// Position of ESYNCIE field.
	CRS_CR_ESYNCIE_Pos = 0x3
	// Bit mask of ESYNCIE field.
	CRS_CR_ESYNCIE_Msk = 0x8
	// Bit ESYNCIE.
	CRS_CR_ESYNCIE = 0x8
	// Interrupt disabled
	CRS_CR_ESYNCIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_ESYNCIE_Enabled = 0x1
	// Position of ERRIE field.
	CRS_CR_ERRIE_Pos = 0x2
	// Bit mask of ERRIE field.
	CRS_CR_ERRIE_Msk = 0x4
	// Bit ERRIE.
	CRS_CR_ERRIE = 0x4
	// Interrupt disabled
	CRS_CR_ERRIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_ERRIE_Enabled = 0x1
	// Position of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Pos = 0x1
	// Bit mask of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Msk = 0x2
	// Bit SYNCWARNIE.
	CRS_CR_SYNCWARNIE = 0x2
	// Interrupt disabled
	CRS_CR_SYNCWARNIE_Disabled = 0x0
	// Interrupt enabled
	CRS_CR_SYNCWARNIE_Enabled = 0x1

	// CFGR: configuration register
	// Position of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Pos = 0x1f
	// Bit mask of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Msk = 0x80000000
	// Bit SYNCPOL.
	CRS_CFGR_SYNCPOL = 0x80000000
	// SYNC active on rising edge
	CRS_CFGR_SYNCPOL_RisingEdge = 0x0
	// SYNC active on falling edge
	CRS_CFGR_SYNCPOL_FallingEdge = 0x1
	// Position of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Pos = 0x1c
	// Bit mask of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Msk = 0x30000000
	// GPIO AF (crs_sync_in_1) selected as SYNC signal source
	CRS_CFGR_SYNCSRC_GPIO_AF = 0x0
	// LSE (crs_sync_in_2) selected as SYNC signal source
	CRS_CFGR_SYNCSRC_LSE = 0x1
	// USB SOF (crs_sync_in_3) selected as SYNC signal source
	CRS_CFGR_SYNCSRC_USB_SOF = 0x2
	// Position of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Pos = 0x18
	// Bit mask of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Msk = 0x7000000
	// SYNC not divided
	CRS_CFGR_SYNCDIV_Div1 = 0x0
	// SYNC divided by 2
	CRS_CFGR_SYNCDIV_Div2 = 0x1
	// SYNC divided by 4
	CRS_CFGR_SYNCDIV_Div4 = 0x2
	// SYNC divided by 8
	CRS_CFGR_SYNCDIV_Div8 = 0x3
	// SYNC divided by 16
	CRS_CFGR_SYNCDIV_Div16 = 0x4
	// SYNC divided by 32
	CRS_CFGR_SYNCDIV_Div32 = 0x5
	// SYNC divided by 64
	CRS_CFGR_SYNCDIV_Div64 = 0x6
	// SYNC divided by 128
	CRS_CFGR_SYNCDIV_Div128 = 0x7
	// Position of FELIM field.
	CRS_CFGR_FELIM_Pos = 0x10
	// Bit mask of FELIM field.
	CRS_CFGR_FELIM_Msk = 0xff0000
	// Position of RELOAD field.
	CRS_CFGR_RELOAD_Pos = 0x0
	// Bit mask of RELOAD field.
	CRS_CFGR_RELOAD_Msk = 0xffff

	// ISR: interrupt and status register
	// Position of FECAP field.
	CRS_ISR_FECAP_Pos = 0x10
	// Bit mask of FECAP field.
	CRS_ISR_FECAP_Msk = 0xffff0000
	// Position of FEDIR field.
	CRS_ISR_FEDIR_Pos = 0xf
	// Bit mask of FEDIR field.
	CRS_ISR_FEDIR_Msk = 0x8000
	// Bit FEDIR.
	CRS_ISR_FEDIR = 0x8000
	// Error in up-counting direction
	CRS_ISR_FEDIR_UpCounting = 0x0
	// Error in down-counting direction
	CRS_ISR_FEDIR_DownCounting = 0x1
	// Position of SYNCOKF field.
	CRS_ISR_SYNCOKF_Pos = 0x0
	// Bit mask of SYNCOKF field.
	CRS_ISR_SYNCOKF_Msk = 0x1
	// Bit SYNCOKF.
	CRS_ISR_SYNCOKF = 0x1
	// Signal not set
	CRS_ISR_SYNCOKF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCOKF_Signaled = 0x1
	// Position of TRIMOVF field.
	CRS_ISR_TRIMOVF_Pos = 0xa
	// Bit mask of TRIMOVF field.
	CRS_ISR_TRIMOVF_Msk = 0x400
	// Bit TRIMOVF.
	CRS_ISR_TRIMOVF = 0x400
	// Signal not set
	CRS_ISR_TRIMOVF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_TRIMOVF_Signaled = 0x1
	// Position of SYNCMISS field.
	CRS_ISR_SYNCMISS_Pos = 0x9
	// Bit mask of SYNCMISS field.
	CRS_ISR_SYNCMISS_Msk = 0x200
	// Bit SYNCMISS.
	CRS_ISR_SYNCMISS = 0x200
	// Signal not set
	CRS_ISR_SYNCMISS_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCMISS_Signaled = 0x1
	// Position of SYNCERR field.
	CRS_ISR_SYNCERR_Pos = 0x8
	// Bit mask of SYNCERR field.
	CRS_ISR_SYNCERR_Msk = 0x100
	// Bit SYNCERR.
	CRS_ISR_SYNCERR = 0x100
	// Signal not set
	CRS_ISR_SYNCERR_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCERR_Signaled = 0x1
	// Position of ESYNCF field.
	CRS_ISR_ESYNCF_Pos = 0x3
	// Bit mask of ESYNCF field.
	CRS_ISR_ESYNCF_Msk = 0x8
	// Bit ESYNCF.
	CRS_ISR_ESYNCF = 0x8
	// Signal not set
	CRS_ISR_ESYNCF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_ESYNCF_Signaled = 0x1
	// Position of ERRF field.
	CRS_ISR_ERRF_Pos = 0x2
	// Bit mask of ERRF field.
	CRS_ISR_ERRF_Msk = 0x4
	// Bit ERRF.
	CRS_ISR_ERRF = 0x4
	// Signal not set
	CRS_ISR_ERRF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_ERRF_Signaled = 0x1
	// Position of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Pos = 0x1
	// Bit mask of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Msk = 0x2
	// Bit SYNCWARNF.
	CRS_ISR_SYNCWARNF = 0x2
	// Signal not set
	CRS_ISR_SYNCWARNF_NotSignaled = 0x0
	// Signal set
	CRS_ISR_SYNCWARNF_Signaled = 0x1

	// ICR: interrupt flag clear register
	// Position of SYNCOKC field.
	CRS_ICR_SYNCOKC_Pos = 0x0
	// Bit mask of SYNCOKC field.
	CRS_ICR_SYNCOKC_Msk = 0x1
	// Bit SYNCOKC.
	CRS_ICR_SYNCOKC = 0x1
	// Clear flag
	CRS_ICR_SYNCOKC_Clear = 0x1
	// Position of ESYNCC field.
	CRS_ICR_ESYNCC_Pos = 0x3
	// Bit mask of ESYNCC field.
	CRS_ICR_ESYNCC_Msk = 0x8
	// Bit ESYNCC.
	CRS_ICR_ESYNCC = 0x8
	// Clear flag
	CRS_ICR_ESYNCC_Clear = 0x1
	// Position of ERRC field.
	CRS_ICR_ERRC_Pos = 0x2
	// Bit mask of ERRC field.
	CRS_ICR_ERRC_Msk = 0x4
	// Bit ERRC.
	CRS_ICR_ERRC = 0x4
	// Clear flag
	CRS_ICR_ERRC_Clear = 0x1
	// Position of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Pos = 0x1
	// Bit mask of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Msk = 0x2
	// Bit SYNCWARNC.
	CRS_ICR_SYNCWARNC = 0x2
	// Clear flag
	CRS_ICR_SYNCWARNC_Clear = 0x1
)

// Constants for DAC: DAC
const (
	// CR: DAC control register
	// Position of EN1 field.
	DAC_CR_EN1_Pos = 0x10
	// Bit mask of EN1 field.
	DAC_CR_EN1_Msk = 0x10000
	// Bit EN1.
	DAC_CR_EN1 = 0x10000
	// DAC Channel X disabled
	DAC_CR_EN1_Disabled = 0x0
	// DAC Channel X enabled
	DAC_CR_EN1_Enabled = 0x1
	// Position of EN2 field.
	DAC_CR_EN2_Pos = 0x20
	// Bit mask of EN2 field.
	DAC_CR_EN2_Msk = 0x100000000
	// Bit EN2.
	DAC_CR_EN2 = 0x100000000
	// DAC Channel X disabled
	DAC_CR_EN2_Disabled = 0x0
	// DAC Channel X enabled
	DAC_CR_EN2_Enabled = 0x1
	// Position of TEN1 field.
	DAC_CR_TEN1_Pos = 0x11
	// Bit mask of TEN1 field.
	DAC_CR_TEN1_Msk = 0x20000
	// Bit TEN1.
	DAC_CR_TEN1 = 0x20000
	// DAC Channel X trigger disabled
	DAC_CR_TEN1_Disabled = 0x0
	// DAC Channel X trigger enabled
	DAC_CR_TEN1_Enabled = 0x1
	// Position of TEN2 field.
	DAC_CR_TEN2_Pos = 0x21
	// Bit mask of TEN2 field.
	DAC_CR_TEN2_Msk = 0x200000000
	// Bit TEN2.
	DAC_CR_TEN2 = 0x200000000
	// DAC Channel X trigger disabled
	DAC_CR_TEN2_Disabled = 0x0
	// DAC Channel X trigger enabled
	DAC_CR_TEN2_Enabled = 0x1
	// Position of TSEL1 field.
	DAC_CR_TSEL1_Pos = 0x2
	// Bit mask of TSEL1 field.
	DAC_CR_TSEL1_Msk = 0x3c
	// Software trigger
	DAC_CR_TSEL1_Swtrig = 0x0
	// Timer 1 TRGO event
	DAC_CR_TSEL1_Tim1Trgo = 0x1
	// Timer 2 TRGO event
	DAC_CR_TSEL1_Tim2Trgo = 0x2
	// Timer 4 TRGO event
	DAC_CR_TSEL1_Tim4Trgo = 0x3
	// Timer 5 TRGO event
	DAC_CR_TSEL1_Tim5Trgo = 0x4
	// Timer 6 TRGO event
	DAC_CR_TSEL1_Tim6Trgo = 0x5
	// Timer 7 TRGO event
	DAC_CR_TSEL1_Tim7Trgo = 0x6
	// Timer 8 TRGO event
	DAC_CR_TSEL1_Tim8Trgo = 0x7
	// Timer 15 TRGO event
	DAC_CR_TSEL1_Tim15Trgo = 0x8
	// LPTIM1 OUT event
	DAC_CR_TSEL1_Lptim1Out = 0xb
	// LPTIM2 OUT event
	DAC_CR_TSEL1_Lptim2Out = 0xc
	// EXTI line 9
	DAC_CR_TSEL1_Exti9 = 0xd
	// Position of WAVE1 field.
	DAC_CR_WAVE1_Pos = 0x16
	// Bit mask of WAVE1 field.
	DAC_CR_WAVE1_Msk = 0xc00000
	// Wave generation disabled
	DAC_CR_WAVE1_Disabled = 0x0
	// Noise wave generation enabled
	DAC_CR_WAVE1_Noise = 0x1
	// Triangle wave generation enabled
	DAC_CR_WAVE1_Triangle = 0x2
	// Position of WAVE2 field.
	DAC_CR_WAVE2_Pos = 0x26
	// Bit mask of WAVE2 field.
	DAC_CR_WAVE2_Msk = 0xc000000000
	// Wave generation disabled
	DAC_CR_WAVE2_Disabled = 0x0
	// Noise wave generation enabled
	DAC_CR_WAVE2_Noise = 0x1
	// Triangle wave generation enabled
	DAC_CR_WAVE2_Triangle = 0x2
	// Position of MAMP1 field.
	DAC_CR_MAMP1_Pos = 0x18
	// Bit mask of MAMP1 field.
	DAC_CR_MAMP1_Msk = 0xf000000
	// Unmask bit0 of LFSR/ triangle amplitude equal to 1
	DAC_CR_MAMP1_Amp1 = 0x0
	// Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
	DAC_CR_MAMP1_Amp3 = 0x1
	// Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
	DAC_CR_MAMP1_Amp7 = 0x2
	// Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
	DAC_CR_MAMP1_Amp15 = 0x3
	// Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
	DAC_CR_MAMP1_Amp31 = 0x4
	// Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
	DAC_CR_MAMP1_Amp63 = 0x5
	// Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
	DAC_CR_MAMP1_Amp127 = 0x6
	// Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
	DAC_CR_MAMP1_Amp255 = 0x7
	// Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
	DAC_CR_MAMP1_Amp511 = 0x8
	// Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
	DAC_CR_MAMP1_Amp1023 = 0x9
	// Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
	DAC_CR_MAMP1_Amp2047 = 0xa
	// Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
	DAC_CR_MAMP1_Amp4095 = 0xb
	// Position of MAMP2 field.
	DAC_CR_MAMP2_Pos = 0x28
	// Bit mask of MAMP2 field.
	DAC_CR_MAMP2_Msk = 0xf0000000000
	// Unmask bit0 of LFSR/ triangle amplitude equal to 1
	DAC_CR_MAMP2_Amp1 = 0x0
	// Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
	DAC_CR_MAMP2_Amp3 = 0x1
	// Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
	DAC_CR_MAMP2_Amp7 = 0x2
	// Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
	DAC_CR_MAMP2_Amp15 = 0x3
	// Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
	DAC_CR_MAMP2_Amp31 = 0x4
	// Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
	DAC_CR_MAMP2_Amp63 = 0x5
	// Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
	DAC_CR_MAMP2_Amp127 = 0x6
	// Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
	DAC_CR_MAMP2_Amp255 = 0x7
	// Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
	DAC_CR_MAMP2_Amp511 = 0x8
	// Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
	DAC_CR_MAMP2_Amp1023 = 0x9
	// Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
	DAC_CR_MAMP2_Amp2047 = 0xa
	// Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
	DAC_CR_MAMP2_Amp4095 = 0xb
	// Position of DMAEN1 field.
	DAC_CR_DMAEN1_Pos = 0x1c
	// Bit mask of DMAEN1 field.
	DAC_CR_DMAEN1_Msk = 0x10000000
	// Bit DMAEN1.
	DAC_CR_DMAEN1 = 0x10000000
	// DAC Channel X DMA mode disabled
	DAC_CR_DMAEN1_Disabled = 0x0
	// DAC Channel X DMA mode enabled
	DAC_CR_DMAEN1_Enabled = 0x1
	// Position of DMAEN2 field.
	DAC_CR_DMAEN2_Pos = 0x2c
	// Bit mask of DMAEN2 field.
	DAC_CR_DMAEN2_Msk = 0x100000000000
	// Bit DMAEN2.
	DAC_CR_DMAEN2 = 0x100000000000
	// DAC Channel X DMA mode disabled
	DAC_CR_DMAEN2_Disabled = 0x0
	// DAC Channel X DMA mode enabled
	DAC_CR_DMAEN2_Enabled = 0x1
	// Position of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1_Pos = 0x1d
	// Bit mask of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1_Msk = 0x20000000
	// Bit DMAUDRIE1.
	DAC_CR_DMAUDRIE1 = 0x20000000
	// DAC channel X DMA Underrun Interrupt disabled
	DAC_CR_DMAUDRIE1_Disabled = 0x0
	// DAC channel X DMA Underrun Interrupt enabled
	DAC_CR_DMAUDRIE1_Enabled = 0x1
	// Position of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2_Pos = 0x2d
	// Bit mask of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2_Msk = 0x200000000000
	// Bit DMAUDRIE2.
	DAC_CR_DMAUDRIE2 = 0x200000000000
	// DAC channel X DMA Underrun Interrupt disabled
	DAC_CR_DMAUDRIE2_Disabled = 0x0
	// DAC channel X DMA Underrun Interrupt enabled
	DAC_CR_DMAUDRIE2_Enabled = 0x1
	// Position of CEN1 field.
	DAC_CR_CEN1_Pos = 0x1e
	// Bit mask of CEN1 field.
	DAC_CR_CEN1_Msk = 0x40000000
	// Bit CEN1.
	DAC_CR_CEN1 = 0x40000000
	// DAC Channel X Normal operating mode
	DAC_CR_CEN1_Normal = 0x0
	// DAC Channel X calibration mode
	DAC_CR_CEN1_Calibration = 0x1
	// Position of CEN2 field.
	DAC_CR_CEN2_Pos = 0x2e
	// Bit mask of CEN2 field.
	DAC_CR_CEN2_Msk = 0x400000000000
	// Bit CEN2.
	DAC_CR_CEN2 = 0x400000000000
	// DAC Channel X Normal operating mode
	DAC_CR_CEN2_Normal = 0x0
	// DAC Channel X calibration mode
	DAC_CR_CEN2_Calibration = 0x1
	// Position of HFSEL field.
	DAC_CR_HFSEL_Pos = 0xf
	// Bit mask of HFSEL field.
	DAC_CR_HFSEL_Msk = 0x8000
	// Bit HFSEL.
	DAC_CR_HFSEL = 0x8000
	// High frequency interface mode disabled
	DAC_CR_HFSEL_Disabled = 0x0
	// High frequency interface mode enabled
	DAC_CR_HFSEL_Enabled = 0x1
	// Position of TSEL2 field.
	DAC_CR_TSEL2_Pos = 0x12
	// Bit mask of TSEL2 field.
	DAC_CR_TSEL2_Msk = 0x3c0000
	// Software trigger
	DAC_CR_TSEL2_Swtrig = 0x0
	// Timer 1 TRGO event
	DAC_CR_TSEL2_Tim1Trgo = 0x1
	// Timer 2 TRGO event
	DAC_CR_TSEL2_Tim2Trgo = 0x2
	// Timer 4 TRGO event
	DAC_CR_TSEL2_Tim4Trgo = 0x3
	// Timer 5 TRGO event
	DAC_CR_TSEL2_Tim5Trgo = 0x4
	// Timer 6 TRGO event
	DAC_CR_TSEL2_Tim6Trgo = 0x5
	// Timer 7 TRGO event
	DAC_CR_TSEL2_Tim7Trgo = 0x6
	// Timer 8 TRGO event
	DAC_CR_TSEL2_Tim8Trgo = 0x7
	// Timer 15 TRGO event
	DAC_CR_TSEL2_Tim15Trgo = 0x8
	// LPTIM1 OUT event
	DAC_CR_TSEL2_Lptim1Out = 0xb
	// LPTIM2 OUT event
	DAC_CR_TSEL2_Lptim2Out = 0xc
	// EXTI line 9
	DAC_CR_TSEL2_Exti9 = 0xd

	// SWTRGR: DAC software trigger register
	// Position of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1_Pos = 0x1
	// Bit mask of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1_Msk = 0x2
	// Bit SWTRIG1.
	DAC_SWTRGR_SWTRIG1 = 0x2
	// No trigger
	DAC_SWTRGR_SWTRIG1_NoTrigger = 0x0
	// Trigger
	DAC_SWTRGR_SWTRIG1_Trigger = 0x1
	// Position of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2_Pos = 0x2
	// Bit mask of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2_Msk = 0x4
	// Bit SWTRIG2.
	DAC_SWTRGR_SWTRIG2 = 0x4
	// No trigger
	DAC_SWTRGR_SWTRIG2_NoTrigger = 0x0
	// Trigger
	DAC_SWTRGR_SWTRIG2_Trigger = 0x1

	// DHR12R1: channel%s 12-bit right-aligned data holding register
	// Position of DACCDHR field.
	DAC_DHR12R_DACCDHR_Pos = 0x0
	// Bit mask of DACCDHR field.
	DAC_DHR12R_DACCDHR_Msk = 0xfff

	// DHR12L1: channel%s 12-bit left aligned data holding register
	// Position of DACCDHR field.
	DAC_DHR12L_DACCDHR_Pos = 0x4
	// Bit mask of DACCDHR field.
	DAC_DHR12L_DACCDHR_Msk = 0xfff0

	// DHR8R1: channel%s 8-bit right aligned data holding register
	// Position of DACCDHR field.
	DAC_DHR8R_DACCDHR_Pos = 0x0
	// Bit mask of DACCDHR field.
	DAC_DHR8R_DACCDHR_Msk = 0xff

	// DHR12RD: Dual DAC 12-bit right-aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12RD_DACC1DHR_Pos = 0x10
	// Bit mask of DACC1DHR field.
	DAC_DHR12RD_DACC1DHR_Msk = 0xfff0000
	// Position of DACC2DHR field.
	DAC_DHR12RD_DACC2DHR_Pos = 0x20
	// Bit mask of DACC2DHR field.
	DAC_DHR12RD_DACC2DHR_Msk = 0xfff00000000

	// DHR12LD: DUAL DAC 12-bit left aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR12LD_DACC1DHR_Pos = 0x14
	// Bit mask of DACC1DHR field.
	DAC_DHR12LD_DACC1DHR_Msk = 0xfff00000
	// Position of DACC2DHR field.
	DAC_DHR12LD_DACC2DHR_Pos = 0x24
	// Bit mask of DACC2DHR field.
	DAC_DHR12LD_DACC2DHR_Msk = 0xfff000000000

	// DHR8RD: DUAL DAC 8-bit right aligned data holding register
	// Position of DACC1DHR field.
	DAC_DHR8RD_DACC1DHR_Pos = 0x8
	// Bit mask of DACC1DHR field.
	DAC_DHR8RD_DACC1DHR_Msk = 0xff00
	// Position of DACC2DHR field.
	DAC_DHR8RD_DACC2DHR_Pos = 0x10
	// Bit mask of DACC2DHR field.
	DAC_DHR8RD_DACC2DHR_Msk = 0xff0000

	// DOR1: channel%s data output register
	// Position of DACCDOR field.
	DAC_DOR_DACCDOR_Pos = 0x0
	// Bit mask of DACCDOR field.
	DAC_DOR_DACCDOR_Msk = 0xfff

	// SR: DAC status register
	// Position of DMAUDR1 field.
	DAC_SR_DMAUDR1_Pos = 0x1d
	// Bit mask of DMAUDR1 field.
	DAC_SR_DMAUDR1_Msk = 0x20000000
	// Bit DMAUDR1.
	DAC_SR_DMAUDR1 = 0x20000000
	// No DMA underrun error condition occurred for DAC channel x
	DAC_SR_DMAUDR1_NoUnderrun = 0x0
	// DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
	DAC_SR_DMAUDR1_Underrun = 0x1
	// Position of DMAUDR2 field.
	DAC_SR_DMAUDR2_Pos = 0x2d
	// Bit mask of DMAUDR2 field.
	DAC_SR_DMAUDR2_Msk = 0x200000000000
	// Bit DMAUDR2.
	DAC_SR_DMAUDR2 = 0x200000000000
	// No DMA underrun error condition occurred for DAC channel x
	DAC_SR_DMAUDR2_NoUnderrun = 0x0
	// DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
	DAC_SR_DMAUDR2_Underrun = 0x1
	// Position of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1_Pos = 0x1e
	// Bit mask of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1_Msk = 0x40000000
	// Bit CAL_FLAG1.
	DAC_SR_CAL_FLAG1 = 0x40000000
	// Calibration trimming value is lower than the offset correction value
	DAC_SR_CAL_FLAG1_Lower = 0x0
	// Calibration trimming value is equal or greater than the offset correction value
	DAC_SR_CAL_FLAG1_Equal_Higher = 0x1
	// Position of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2_Pos = 0x2e
	// Bit mask of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2_Msk = 0x400000000000
	// Bit CAL_FLAG2.
	DAC_SR_CAL_FLAG2 = 0x400000000000
	// Calibration trimming value is lower than the offset correction value
	DAC_SR_CAL_FLAG2_Lower = 0x0
	// Calibration trimming value is equal or greater than the offset correction value
	DAC_SR_CAL_FLAG2_Equal_Higher = 0x1
	// Position of BWST1 field.
	DAC_SR_BWST1_Pos = 0x1f
	// Bit mask of BWST1 field.
	DAC_SR_BWST1_Msk = 0x80000000
	// Bit BWST1.
	DAC_SR_BWST1 = 0x80000000
	// There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
	DAC_SR_BWST1_Idle = 0x0
	// There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
	DAC_SR_BWST1_Busy = 0x1
	// Position of BWST2 field.
	DAC_SR_BWST2_Pos = 0x2f
	// Bit mask of BWST2 field.
	DAC_SR_BWST2_Msk = 0x800000000000
	// Bit BWST2.
	DAC_SR_BWST2 = 0x800000000000
	// There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
	DAC_SR_BWST2_Idle = 0x0
	// There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
	DAC_SR_BWST2_Busy = 0x1

	// CCR: DAC calibration control register
	// Position of OTRIM1 field.
	DAC_CCR_OTRIM1_Pos = 0x10
	// Bit mask of OTRIM1 field.
	DAC_CCR_OTRIM1_Msk = 0x1f0000
	// Position of OTRIM2 field.
	DAC_CCR_OTRIM2_Pos = 0x20
	// Bit mask of OTRIM2 field.
	DAC_CCR_OTRIM2_Msk = 0x1f00000000

	// MCR: DAC mode control register
	// Position of MODE1 field.
	DAC_MCR_MODE1_Pos = 0x10
	// Bit mask of MODE1 field.
	DAC_MCR_MODE1_Msk = 0x70000
	// Normal mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE1_NormalPinBuffer = 0x0
	// Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE1_NormalPinChipBuffer = 0x1
	// Normal mode - DAC channelx is connected to external pin with Buffer disabled
	DAC_MCR_MODE1_NormalPinNoBuffer = 0x2
	// Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE1_NormalChipNoBuffer = 0x3
	// S&H mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE1_SHPinBuffer = 0x4
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE1_SHPinChipBuffer = 0x5
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
	DAC_MCR_MODE1_SHPinNoBuffer = 0x6
	// S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE1_SHChipNoBuffer = 0x7
	// Position of MODE2 field.
	DAC_MCR_MODE2_Pos = 0x20
	// Bit mask of MODE2 field.
	DAC_MCR_MODE2_Msk = 0x700000000
	// Normal mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE2_NormalPinBuffer = 0x0
	// Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE2_NormalPinChipBuffer = 0x1
	// Normal mode - DAC channelx is connected to external pin with Buffer disabled
	DAC_MCR_MODE2_NormalPinNoBuffer = 0x2
	// Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE2_NormalChipNoBuffer = 0x3
	// S&H mode - DAC channelx is connected to external pin with Buffer enabled
	DAC_MCR_MODE2_SHPinBuffer = 0x4
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
	DAC_MCR_MODE2_SHPinChipBuffer = 0x5
	// S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
	DAC_MCR_MODE2_SHPinNoBuffer = 0x6
	// S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
	DAC_MCR_MODE2_SHChipNoBuffer = 0x7

	// SHSR1: DAC channel%s sample and hold sample time register
	// Position of TSAMPLE field.
	DAC_SHSR_TSAMPLE_Pos = 0x0
	// Bit mask of TSAMPLE field.
	DAC_SHSR_TSAMPLE_Msk = 0x3ff

	// SHHR: DAC Sample and Hold hold time register
	// Position of THOLD1 field.
	DAC_SHHR_THOLD1_Pos = 0x10
	// Bit mask of THOLD1 field.
	DAC_SHHR_THOLD1_Msk = 0x3ff0000
	// Position of THOLD2 field.
	DAC_SHHR_THOLD2_Pos = 0x20
	// Bit mask of THOLD2 field.
	DAC_SHHR_THOLD2_Msk = 0x3ff00000000

	// SHRR: DAC Sample and Hold refresh time register
	// Position of TREFRESH1 field.
	DAC_SHRR_TREFRESH1_Pos = 0x10
	// Bit mask of TREFRESH1 field.
	DAC_SHRR_TREFRESH1_Msk = 0xff0000
	// Position of TREFRESH2 field.
	DAC_SHRR_TREFRESH2_Pos = 0x20
	// Bit mask of TREFRESH2 field.
	DAC_SHRR_TREFRESH2_Msk = 0xff00000000
)

// Constants for DBGMCU: MCU debug component
const (
	// IDCODE: DBGMCU_IDCODE
	// Position of DEV_ID field.
	DBGMCU_IDCODE_DEV_ID_Pos = 0x0
	// Bit mask of DEV_ID field.
	DBGMCU_IDCODE_DEV_ID_Msk = 0xfff
	// Position of REV_ID field.
	DBGMCU_IDCODE_REV_ID_Pos = 0x10
	// Bit mask of REV_ID field.
	DBGMCU_IDCODE_REV_ID_Msk = 0xffff0000

	// CR: Debug MCU configuration register
	// Position of DBG_STOP field.
	DBGMCU_CR_DBG_STOP_Pos = 0x1
	// Bit mask of DBG_STOP field.
	DBGMCU_CR_DBG_STOP_Msk = 0x2
	// Bit DBG_STOP.
	DBGMCU_CR_DBG_STOP = 0x2
	// Position of DBG_STANDBY field.
	DBGMCU_CR_DBG_STANDBY_Pos = 0x2
	// Bit mask of DBG_STANDBY field.
	DBGMCU_CR_DBG_STANDBY_Msk = 0x4
	// Bit DBG_STANDBY.
	DBGMCU_CR_DBG_STANDBY = 0x4
	// Position of TRACE_IOEN field.
	DBGMCU_CR_TRACE_IOEN_Pos = 0x4
	// Bit mask of TRACE_IOEN field.
	DBGMCU_CR_TRACE_IOEN_Msk = 0x10
	// Bit TRACE_IOEN.
	DBGMCU_CR_TRACE_IOEN = 0x10
	// Position of TRACE_MODE field.
	DBGMCU_CR_TRACE_MODE_Pos = 0x6
	// Bit mask of TRACE_MODE field.
	DBGMCU_CR_TRACE_MODE_Msk = 0xc0
	// Position of TRACE_EN field.
	DBGMCU_CR_TRACE_EN_Pos = 0x5
	// Bit mask of TRACE_EN field.
	DBGMCU_CR_TRACE_EN_Msk = 0x20
	// Bit TRACE_EN.
	DBGMCU_CR_TRACE_EN = 0x20

	// APB1LFZR: Debug MCU APB1 freeze register1
	// Position of DBG_TIM2_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos = 0x0
	// Bit mask of DBG_TIM2_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk = 0x1
	// Bit DBG_TIM2_STOP.
	DBGMCU_APB1LFZR_DBG_TIM2_STOP = 0x1
	// Position of DBG_TIM6_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM6_STOP_Pos = 0x4
	// Bit mask of DBG_TIM6_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM6_STOP_Msk = 0x10
	// Bit DBG_TIM6_STOP.
	DBGMCU_APB1LFZR_DBG_TIM6_STOP = 0x10
	// Position of DBG_TIM7_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM7_STOP_Pos = 0x5
	// Bit mask of DBG_TIM7_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM7_STOP_Msk = 0x20
	// Bit DBG_TIM7_STOP.
	DBGMCU_APB1LFZR_DBG_TIM7_STOP = 0x20
	// Position of DBG_RTC_STOP field.
	DBGMCU_APB1LFZR_DBG_RTC_STOP_Pos = 0xa
	// Bit mask of DBG_RTC_STOP field.
	DBGMCU_APB1LFZR_DBG_RTC_STOP_Msk = 0x400
	// Bit DBG_RTC_STOP.
	DBGMCU_APB1LFZR_DBG_RTC_STOP = 0x400
	// Position of DBG_WWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos = 0xb
	// Bit mask of DBG_WWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk = 0x800
	// Bit DBG_WWDG_STOP.
	DBGMCU_APB1LFZR_DBG_WWDG_STOP = 0x800
	// Position of DBG_IWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos = 0xc
	// Bit mask of DBG_IWDG_STOP field.
	DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk = 0x1000
	// Bit DBG_IWDG_STOP.
	DBGMCU_APB1LFZR_DBG_IWDG_STOP = 0x1000
	// Position of DBG_I2C1_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos = 0x15
	// Bit mask of DBG_I2C1_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk = 0x200000
	// Bit DBG_I2C1_STOP.
	DBGMCU_APB1LFZR_DBG_I2C1_STOP = 0x200000
	// Position of DBG_I2C2_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos = 0x16
	// Bit mask of DBG_I2C2_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk = 0x400000
	// Bit DBG_I2C2_STOP.
	DBGMCU_APB1LFZR_DBG_I2C2_STOP = 0x400000
	// Position of DBG_I2C3_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C3_STOP_Pos = 0x17
	// Bit mask of DBG_I2C3_STOP field.
	DBGMCU_APB1LFZR_DBG_I2C3_STOP_Msk = 0x800000
	// Bit DBG_I2C3_STOP.
	DBGMCU_APB1LFZR_DBG_I2C3_STOP = 0x800000
	// Position of DBG_LPTIM1_STOP field.
	DBGMCU_APB1LFZR_DBG_LPTIM1_STOP_Pos = 0x1f
	// Bit mask of DBG_LPTIM1_STOP field.
	DBGMCU_APB1LFZR_DBG_LPTIM1_STOP_Msk = 0x80000000
	// Bit DBG_LPTIM1_STOP.
	DBGMCU_APB1LFZR_DBG_LPTIM1_STOP = 0x80000000
	// Position of DBG_TIM3_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos = 0x1
	// Bit mask of DBG_TIM3_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk = 0x2
	// Bit DBG_TIM3_STOP.
	DBGMCU_APB1LFZR_DBG_TIM3_STOP = 0x2
	// Position of DBG_TIM4_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos = 0x2
	// Bit mask of DBG_TIM4_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk = 0x4
	// Bit DBG_TIM4_STOP.
	DBGMCU_APB1LFZR_DBG_TIM4_STOP = 0x4
	// Position of DBG_TIM5_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM5_STOP_Pos = 0x3
	// Bit mask of DBG_TIM5_STOP field.
	DBGMCU_APB1LFZR_DBG_TIM5_STOP_Msk = 0x8
	// Bit DBG_TIM5_STOP.
	DBGMCU_APB1LFZR_DBG_TIM5_STOP = 0x8

	// APB1HFZR: Debug MCU APB1 freeze register 2
	// Position of DBG_LPTIM2_STOP field.
	DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos = 0x5
	// Bit mask of DBG_LPTIM2_STOP field.
	DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk = 0x20
	// Bit DBG_LPTIM2_STOP.
	DBGMCU_APB1HFZR_DBG_LPTIM2_STOP = 0x20
	// Position of DBG_I2C4_STOP field.
	DBGMCU_APB1HFZR_DBG_I2C4_STOP_Pos = 0x1
	// Bit mask of DBG_I2C4_STOP field.
	DBGMCU_APB1HFZR_DBG_I2C4_STOP_Msk = 0x2
	// Bit DBG_I2C4_STOP.
	DBGMCU_APB1HFZR_DBG_I2C4_STOP = 0x2
	// Position of DBG_LPTIM3_STOP field.
	DBGMCU_APB1HFZR_DBG_LPTIM3_STOP_Pos = 0x6
	// Bit mask of DBG_LPTIM3_STOP field.
	DBGMCU_APB1HFZR_DBG_LPTIM3_STOP_Msk = 0x40
	// Bit DBG_LPTIM3_STOP.
	DBGMCU_APB1HFZR_DBG_LPTIM3_STOP = 0x40

	// APB2FZR: Debug MCU APB2 freeze register
	// Position of DBG_TIM1_STOP field.
	DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos = 0xb
	// Bit mask of DBG_TIM1_STOP field.
	DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk = 0x800
	// Bit DBG_TIM1_STOP.
	DBGMCU_APB2FZR_DBG_TIM1_STOP = 0x800
	// Position of DBG_TIM15_STOP field.
	DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos = 0x10
	// Bit mask of DBG_TIM15_STOP field.
	DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk = 0x10000
	// Bit DBG_TIM15_STOP.
	DBGMCU_APB2FZR_DBG_TIM15_STOP = 0x10000
	// Position of DBG_TIM16_STOP field.
	DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos = 0x11
	// Bit mask of DBG_TIM16_STOP field.
	DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk = 0x20000
	// Bit DBG_TIM16_STOP.
	DBGMCU_APB2FZR_DBG_TIM16_STOP = 0x20000
	// Position of DBG_TIM8_STOP field.
	DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos = 0xd
	// Bit mask of DBG_TIM8_STOP field.
	DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk = 0x2000
	// Bit DBG_TIM8_STOP.
	DBGMCU_APB2FZR_DBG_TIM8_STOP = 0x2000
	// Position of DBG_TIM17_STOP field.
	DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos = 0x12
	// Bit mask of DBG_TIM17_STOP field.
	DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk = 0x40000
	// Bit DBG_TIM17_STOP.
	DBGMCU_APB2FZR_DBG_TIM17_STOP = 0x40000
)

// Constants for DCB: Debug Control Block
const (
	// DSCSR: Debug Security Control and Status Register
	// Position of CDS field.
	DCB_DSCSR_CDS_Pos = 0x10
	// Bit mask of CDS field.
	DCB_DSCSR_CDS_Msk = 0x10000
	// Bit CDS.
	DCB_DSCSR_CDS = 0x10000
)

// Constants for DFSDM1: Digital filter for sigma delta modulators
const (
	// CH.CFGR1: channel configuration y register
	// Position of DFSDMEN field.
	DFSDM_CH_CFGR1_DFSDMEN_Pos = 0x1f
	// Bit mask of DFSDMEN field.
	DFSDM_CH_CFGR1_DFSDMEN_Msk = 0x80000000
	// Bit DFSDMEN.
	DFSDM_CH_CFGR1_DFSDMEN = 0x80000000
	// DFSDM interface disabled
	DFSDM_CH_CFGR1_DFSDMEN_Disabled = 0x0
	// DFSDM interface enabled
	DFSDM_CH_CFGR1_DFSDMEN_Enabled = 0x1
	// Position of CKOUTSRC field.
	DFSDM_CH_CFGR1_CKOUTSRC_Pos = 0x1e
	// Bit mask of CKOUTSRC field.
	DFSDM_CH_CFGR1_CKOUTSRC_Msk = 0x40000000
	// Bit CKOUTSRC.
	DFSDM_CH_CFGR1_CKOUTSRC = 0x40000000
	// Source for output clock is from system clock
	DFSDM_CH_CFGR1_CKOUTSRC_SYSCLK = 0x0
	// Source for output clock is from audio clock
	DFSDM_CH_CFGR1_CKOUTSRC_AUDCLK = 0x1
	// Position of CKOUTDIV field.
	DFSDM_CH_CFGR1_CKOUTDIV_Pos = 0x10
	// Bit mask of CKOUTDIV field.
	DFSDM_CH_CFGR1_CKOUTDIV_Msk = 0xff0000
	// Position of DATPACK field.
	DFSDM_CH_CFGR1_DATPACK_Pos = 0xe
	// Bit mask of DATPACK field.
	DFSDM_CH_CFGR1_DATPACK_Msk = 0xc000
	// Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y
	DFSDM_CH_CFGR1_DATPACK_Standard = 0x0
	// : Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)
	DFSDM_CH_CFGR1_DATPACK_Interleaved = 0x1
	// Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)
	DFSDM_CH_CFGR1_DATPACK_Dual = 0x2
	// Position of DATMPX field.
	DFSDM_CH_CFGR1_DATMPX_Pos = 0xc
	// Bit mask of DATMPX field.
	DFSDM_CH_CFGR1_DATMPX_Msk = 0x3000
	// Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected
	DFSDM_CH_CFGR1_DATMPX_External = 0x0
	// Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register
	DFSDM_CH_CFGR1_DATMPX_ADC = 0x1
	// Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting
	DFSDM_CH_CFGR1_DATMPX_Internal = 0x2
	// Position of CHINSEL field.
	DFSDM_CH_CFGR1_CHINSEL_Pos = 0x8
	// Bit mask of CHINSEL field.
	DFSDM_CH_CFGR1_CHINSEL_Msk = 0x100
	// Bit CHINSEL.
	DFSDM_CH_CFGR1_CHINSEL = 0x100
	// Channel inputs are taken from pins of the same channel y
	DFSDM_CH_CFGR1_CHINSEL_SameChannel = 0x0
	// Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)
	DFSDM_CH_CFGR1_CHINSEL_FollowingChannel = 0x1
	// Position of CHEN field.
	DFSDM_CH_CFGR1_CHEN_Pos = 0x7
	// Bit mask of CHEN field.
	DFSDM_CH_CFGR1_CHEN_Msk = 0x80
	// Bit CHEN.
	DFSDM_CH_CFGR1_CHEN = 0x80
	// Channel y disabled
	DFSDM_CH_CFGR1_CHEN_Disabled = 0x0
	// Channel y enabled
	DFSDM_CH_CFGR1_CHEN_Enabled = 0x1
	// Position of CKABEN field.
	DFSDM_CH_CFGR1_CKABEN_Pos = 0x6
	// Bit mask of CKABEN field.
	DFSDM_CH_CFGR1_CKABEN_Msk = 0x40
	// Bit CKABEN.
	DFSDM_CH_CFGR1_CKABEN = 0x40
	// Clock absence detector disabled on channel y
	DFSDM_CH_CFGR1_CKABEN_Disabled = 0x0
	// Clock absence detector enabled on channel y
	DFSDM_CH_CFGR1_CKABEN_Enabled = 0x1
	// Position of SCDEN field.
	DFSDM_CH_CFGR1_SCDEN_Pos = 0x5
	// Bit mask of SCDEN field.
	DFSDM_CH_CFGR1_SCDEN_Msk = 0x20
	// Bit SCDEN.
	DFSDM_CH_CFGR1_SCDEN = 0x20
	// Input channel y will not be guarded by the short-circuit detector
	DFSDM_CH_CFGR1_SCDEN_Disabled = 0x0
	// Input channel y will be continuously guarded by the short-circuit detector
	DFSDM_CH_CFGR1_SCDEN_Enabled = 0x1
	// Position of SPICKSEL field.
	DFSDM_CH_CFGR1_SPICKSEL_Pos = 0x2
	// Bit mask of SPICKSEL field.
	DFSDM_CH_CFGR1_SPICKSEL_Msk = 0xc
	// Clock coming from external CKINy input - sampling point according SITP[1:0]
	DFSDM_CH_CFGR1_SPICKSEL_CKIN = 0x0
	// Clock coming from internal CKOUT output - sampling point according SITP[1:0]
	DFSDM_CH_CFGR1_SPICKSEL_CKOUT = 0x1
	// Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge)
	DFSDM_CH_CFGR1_SPICKSEL_CKOUTSecondFalling = 0x2
	// Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge)
	DFSDM_CH_CFGR1_SPICKSEL_CKOUTSecondRising = 0x3
	// Position of SITP field.
	DFSDM_CH_CFGR1_SITP_Pos = 0x0
	// Bit mask of SITP field.
	DFSDM_CH_CFGR1_SITP_Msk = 0x3
	// SPI with rising edge to strobe data
	DFSDM_CH_CFGR1_SITP_SPIRisingEdge = 0x0
	// SPI with falling edge to strobe data
	DFSDM_CH_CFGR1_SITP_SPIFallingEdge = 0x1
	// Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
	DFSDM_CH_CFGR1_SITP_Manchester = 0x2
	// Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
	DFSDM_CH_CFGR1_SITP_ManchesterInverted = 0x3

	// CH.CFGR2: channel configuration y register
	// Position of OFFSET field.
	DFSDM_CH_CFGR2_OFFSET_Pos = 0x8
	// Bit mask of OFFSET field.
	DFSDM_CH_CFGR2_OFFSET_Msk = 0xffffff00
	// Position of DTRBS field.
	DFSDM_CH_CFGR2_DTRBS_Pos = 0x3
	// Bit mask of DTRBS field.
	DFSDM_CH_CFGR2_DTRBS_Msk = 0xf8

	// CH.AWSCDR: analog watchdog and short-circuit detector register
	// Position of AWFORD field.
	DFSDM_CH_AWSCDR_AWFORD_Pos = 0x16
	// Bit mask of AWFORD field.
	DFSDM_CH_AWSCDR_AWFORD_Msk = 0xc00000
	// FastSinc filter type
	DFSDM_CH_AWSCDR_AWFORD_FastSinc = 0x0
	// Sinc1 filter type
	DFSDM_CH_AWSCDR_AWFORD_Sinc1 = 0x1
	// Sinc2 filter type
	DFSDM_CH_AWSCDR_AWFORD_Sinc2 = 0x2
	// Sinc3 filter type
	DFSDM_CH_AWSCDR_AWFORD_Sinc3 = 0x3
	// Position of AWFOSR field.
	DFSDM_CH_AWSCDR_AWFOSR_Pos = 0x10
	// Bit mask of AWFOSR field.
	DFSDM_CH_AWSCDR_AWFOSR_Msk = 0x1f0000
	// Position of BKSCD field.
	DFSDM_CH_AWSCDR_BKSCD_Pos = 0xc
	// Bit mask of BKSCD field.
	DFSDM_CH_AWSCDR_BKSCD_Msk = 0xf000
	// Position of SCDT field.
	DFSDM_CH_AWSCDR_SCDT_Pos = 0x0
	// Bit mask of SCDT field.
	DFSDM_CH_AWSCDR_SCDT_Msk = 0xff

	// CH.WDATR: channel watchdog filter data register
	// Position of WDATA field.
	DFSDM_CH_WDATR_WDATA_Pos = 0x0
	// Bit mask of WDATA field.
	DFSDM_CH_WDATR_WDATA_Msk = 0xffff

	// CH.DATINR: channel data input register
	// Position of INDAT1 field.
	DFSDM_CH_DATINR_INDAT1_Pos = 0x10
	// Bit mask of INDAT1 field.
	DFSDM_CH_DATINR_INDAT1_Msk = 0xffff0000
	// Position of INDAT0 field.
	DFSDM_CH_DATINR_INDAT0_Pos = 0x0
	// Bit mask of INDAT0 field.
	DFSDM_CH_DATINR_INDAT0_Msk = 0xffff

	// CH.DLYR: DFSDM channel y delay register
	// Position of PLSSKP field.
	DFSDM_CH_DLYR_PLSSKP_Pos = 0x0
	// Bit mask of PLSSKP field.
	DFSDM_CH_DLYR_PLSSKP_Msk = 0x3f

	// FLT.CR1: control register 1
	// Position of AWFSEL field.
	DFSDM_FLT_CR1_AWFSEL_Pos = 0x1e
	// Bit mask of AWFSEL field.
	DFSDM_FLT_CR1_AWFSEL_Msk = 0x40000000
	// Bit AWFSEL.
	DFSDM_FLT_CR1_AWFSEL = 0x40000000
	// Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift
	DFSDM_FLT_CR1_AWFSEL_Output = 0x0
	// Analog watchdog on channel transceivers value (after watchdog filter)
	DFSDM_FLT_CR1_AWFSEL_Transceiver = 0x1
	// Position of FAST field.
	DFSDM_FLT_CR1_FAST_Pos = 0x1d
	// Bit mask of FAST field.
	DFSDM_FLT_CR1_FAST_Msk = 0x20000000
	// Bit FAST.
	DFSDM_FLT_CR1_FAST = 0x20000000
	// Fast conversion mode disabled
	DFSDM_FLT_CR1_FAST_Disabled = 0x0
	// Fast conversion mode enabled
	DFSDM_FLT_CR1_FAST_Enabled = 0x1
	// Position of RCH field.
	DFSDM_FLT_CR1_RCH_Pos = 0x18
	// Bit mask of RCH field.
	DFSDM_FLT_CR1_RCH_Msk = 0x7000000
	// Channel 0 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel0 = 0x0
	// Channel 1 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel1 = 0x1
	// Channel 2 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel2 = 0x2
	// Channel 3 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel3 = 0x3
	// Channel 4 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel4 = 0x4
	// Channel 5 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel5 = 0x5
	// Channel 6 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel6 = 0x6
	// Channel 7 is selected as regular channel
	DFSDM_FLT_CR1_RCH_Channel7 = 0x7
	// Position of RDMAEN field.
	DFSDM_FLT_CR1_RDMAEN_Pos = 0x15
	// Bit mask of RDMAEN field.
	DFSDM_FLT_CR1_RDMAEN_Msk = 0x200000
	// Bit RDMAEN.
	DFSDM_FLT_CR1_RDMAEN = 0x200000
	// The DMA channel is not enabled to read regular data
	DFSDM_FLT_CR1_RDMAEN_Disabled = 0x0
	// The DMA channel is enabled to read regular data
	DFSDM_FLT_CR1_RDMAEN_Enabled = 0x1
	// Position of RSYNC field.
	DFSDM_FLT_CR1_RSYNC_Pos = 0x13
	// Bit mask of RSYNC field.
	DFSDM_FLT_CR1_RSYNC_Msk = 0x80000
	// Bit RSYNC.
	DFSDM_FLT_CR1_RSYNC = 0x80000
	// Do not launch a regular conversion synchronously with DFSDM_FLT0
	DFSDM_FLT_CR1_RSYNC_NoLaunch = 0x0
	// Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0
	DFSDM_FLT_CR1_RSYNC_Launch = 0x1
	// Position of RCONT field.
	DFSDM_FLT_CR1_RCONT_Pos = 0x12
	// Bit mask of RCONT field.
	DFSDM_FLT_CR1_RCONT_Msk = 0x40000
	// Bit RCONT.
	DFSDM_FLT_CR1_RCONT = 0x40000
	// The regular channel is converted just once for each conversion request
	DFSDM_FLT_CR1_RCONT_Once = 0x0
	// The regular channel is converted repeatedly after each conversion request
	DFSDM_FLT_CR1_RCONT_Continuous = 0x1
	// Position of RSWSTART field.
	DFSDM_FLT_CR1_RSWSTART_Pos = 0x11
	// Bit mask of RSWSTART field.
	DFSDM_FLT_CR1_RSWSTART_Msk = 0x20000
	// Bit RSWSTART.
	DFSDM_FLT_CR1_RSWSTART = 0x20000
	// Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1
	DFSDM_FLT_CR1_RSWSTART_Start = 0x1
	// Position of JEXTEN field.
	DFSDM_FLT_CR1_JEXTEN_Pos = 0xd
	// Bit mask of JEXTEN field.
	DFSDM_FLT_CR1_JEXTEN_Msk = 0x6000
	// Trigger detection is disabled
	DFSDM_FLT_CR1_JEXTEN_Disabled = 0x0
	// Each rising edge on the selected trigger makes a request to launch an injected conversion
	DFSDM_FLT_CR1_JEXTEN_RisingEdge = 0x1
	// Each falling edge on the selected trigger makes a request to launch an injected conversion
	DFSDM_FLT_CR1_JEXTEN_FallingEdge = 0x2
	// Both rising edges and falling edges on the selected trigger make requests to launch injected conversions
	DFSDM_FLT_CR1_JEXTEN_BothEdges = 0x3
	// Position of JEXTSEL field.
	DFSDM_FLT_CR1_JEXTSEL_Pos = 0x8
	// Bit mask of JEXTSEL field.
	DFSDM_FLT_CR1_JEXTSEL_Msk = 0x1f00
	// Position of JDMAEN field.
	DFSDM_FLT_CR1_JDMAEN_Pos = 0x5
	// Bit mask of JDMAEN field.
	DFSDM_FLT_CR1_JDMAEN_Msk = 0x20
	// Bit JDMAEN.
	DFSDM_FLT_CR1_JDMAEN = 0x20
	// The DMA channel is not enabled to read injected data
	DFSDM_FLT_CR1_JDMAEN_Disabled = 0x0
	// The DMA channel is enabled to read injected data
	DFSDM_FLT_CR1_JDMAEN_Enabled = 0x1
	// Position of JSCAN field.
	DFSDM_FLT_CR1_JSCAN_Pos = 0x4
	// Bit mask of JSCAN field.
	DFSDM_FLT_CR1_JSCAN_Msk = 0x10
	// Bit JSCAN.
	DFSDM_FLT_CR1_JSCAN = 0x10
	// One channel conversion is performed from the injected channel group and next the selected channel from this group is selected
	DFSDM_FLT_CR1_JSCAN_Single = 0x0
	// The series of conversions for the injected group channels is executed, starting over with the lowest selected channel
	DFSDM_FLT_CR1_JSCAN_Series = 0x1
	// Position of JSYNC field.
	DFSDM_FLT_CR1_JSYNC_Pos = 0x3
	// Bit mask of JSYNC field.
	DFSDM_FLT_CR1_JSYNC_Msk = 0x8
	// Bit JSYNC.
	DFSDM_FLT_CR1_JSYNC = 0x8
	// Do not launch an injected conversion synchronously with DFSDM_FLT0
	DFSDM_FLT_CR1_JSYNC_Disabled = 0x0
	// Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
	DFSDM_FLT_CR1_JSYNC_Enabled = 0x1
	// Position of JSWSTART field.
	DFSDM_FLT_CR1_JSWSTART_Pos = 0x1
	// Bit mask of JSWSTART field.
	DFSDM_FLT_CR1_JSWSTART_Msk = 0x2
	// Bit JSWSTART.
	DFSDM_FLT_CR1_JSWSTART = 0x2
	// Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1
	DFSDM_FLT_CR1_JSWSTART_Start = 0x1
	// Position of DFEN field.
	DFSDM_FLT_CR1_DFEN_Pos = 0x0
	// Bit mask of DFEN field.
	DFSDM_FLT_CR1_DFEN_Msk = 0x1
	// Bit DFEN.
	DFSDM_FLT_CR1_DFEN = 0x1
	// DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped
	DFSDM_FLT_CR1_DFEN_Disabled = 0x0
	// DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting
	DFSDM_FLT_CR1_DFEN_Enabled = 0x1

	// FLT.CR2: control register 2
	// Position of AWDCH field.
	DFSDM_FLT_CR2_AWDCH_Pos = 0x10
	// Bit mask of AWDCH field.
	DFSDM_FLT_CR2_AWDCH_Msk = 0xff0000
	// Analog watchdog is disabled on channel y
	DFSDM_FLT_CR2_AWDCH_Disabled = 0x0
	// Analog watchdog is enabled on channel y
	DFSDM_FLT_CR2_AWDCH_Enabled = 0x1
	// Position of EXCH field.
	DFSDM_FLT_CR2_EXCH_Pos = 0x8
	// Bit mask of EXCH field.
	DFSDM_FLT_CR2_EXCH_Msk = 0xff00
	// Extremes detector does not accept data from channel y
	DFSDM_FLT_CR2_EXCH_Disabled = 0x0
	// Extremes detector accepts data from channel y
	DFSDM_FLT_CR2_EXCH_Enabled = 0x1
	// Position of CKABIE field.
	DFSDM_FLT_CR2_CKABIE_Pos = 0x6
	// Bit mask of CKABIE field.
	DFSDM_FLT_CR2_CKABIE_Msk = 0x40
	// Bit CKABIE.
	DFSDM_FLT_CR2_CKABIE = 0x40
	// Detection of channel input clock absence interrupt is disabled
	DFSDM_FLT_CR2_CKABIE_Disabled = 0x0
	// Detection of channel input clock absence interrupt is enabled
	DFSDM_FLT_CR2_CKABIE_Enabled = 0x1
	// Position of SCDIE field.
	DFSDM_FLT_CR2_SCDIE_Pos = 0x5
	// Bit mask of SCDIE field.
	DFSDM_FLT_CR2_SCDIE_Msk = 0x20
	// Bit SCDIE.
	DFSDM_FLT_CR2_SCDIE = 0x20
	// Short-circuit detector interrupt is disabled
	DFSDM_FLT_CR2_SCDIE_Disabled = 0x0
	// Short-circuit detector interrupt is enabled
	DFSDM_FLT_CR2_SCDIE_Enabled = 0x1
	// Position of AWDIE field.
	DFSDM_FLT_CR2_AWDIE_Pos = 0x4
	// Bit mask of AWDIE field.
	DFSDM_FLT_CR2_AWDIE_Msk = 0x10
	// Bit AWDIE.
	DFSDM_FLT_CR2_AWDIE = 0x10
	// Analog watchdog interrupt is disabled
	DFSDM_FLT_CR2_AWDIE_Disabled = 0x0
	// Analog watchdog interrupt is enabled
	DFSDM_FLT_CR2_AWDIE_Enabled = 0x1
	// Position of ROVRIE field.
	DFSDM_FLT_CR2_ROVRIE_Pos = 0x3
	// Bit mask of ROVRIE field.
	DFSDM_FLT_CR2_ROVRIE_Msk = 0x8
	// Bit ROVRIE.
	DFSDM_FLT_CR2_ROVRIE = 0x8
	// Regular data overrun interrupt is disabled
	DFSDM_FLT_CR2_ROVRIE_Disabled = 0x0
	// Regular data overrun interrupt is enabled
	DFSDM_FLT_CR2_ROVRIE_Enabled = 0x1
	// Position of JOVRIE field.
	DFSDM_FLT_CR2_JOVRIE_Pos = 0x2
	// Bit mask of JOVRIE field.
	DFSDM_FLT_CR2_JOVRIE_Msk = 0x4
	// Bit JOVRIE.
	DFSDM_FLT_CR2_JOVRIE = 0x4
	// Injected data overrun interrupt is disabled
	DFSDM_FLT_CR2_JOVRIE_Disabled = 0x0
	// Injected data overrun interrupt is enabled
	DFSDM_FLT_CR2_JOVRIE_Enabled = 0x1
	// Position of REOCIE field.
	DFSDM_FLT_CR2_REOCIE_Pos = 0x1
	// Bit mask of REOCIE field.
	DFSDM_FLT_CR2_REOCIE_Msk = 0x2
	// Bit REOCIE.
	DFSDM_FLT_CR2_REOCIE = 0x2
	// Regular end of conversion interrupt is disabled
	DFSDM_FLT_CR2_REOCIE_Disabled = 0x0
	// Regular end of conversion interrupt is enabled
	DFSDM_FLT_CR2_REOCIE_Enabled = 0x1
	// Position of JEOCIE field.
	DFSDM_FLT_CR2_JEOCIE_Pos = 0x0
	// Bit mask of JEOCIE field.
	DFSDM_FLT_CR2_JEOCIE_Msk = 0x1
	// Bit JEOCIE.
	DFSDM_FLT_CR2_JEOCIE = 0x1
	// Injected end of conversion interrupt is disabled
	DFSDM_FLT_CR2_JEOCIE_Disabled = 0x0
	// Injected end of conversion interrupt is enabled
	DFSDM_FLT_CR2_JEOCIE_Enabled = 0x1

	// FLT.ISR: interrupt and status register
	// Position of SCDF field.
	DFSDM_FLT_ISR_SCDF_Pos = 0x18
	// Bit mask of SCDF field.
	DFSDM_FLT_ISR_SCDF_Msk = 0xff000000
	// No short-circuit detector event occurred on channel y
	DFSDM_FLT_ISR_SCDF_Clear = 0x0
	// The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers
	DFSDM_FLT_ISR_SCDF_Set = 0x1
	// Position of CKABF field.
	DFSDM_FLT_ISR_CKABF_Pos = 0x10
	// Bit mask of CKABF field.
	DFSDM_FLT_ISR_CKABF_Msk = 0xff0000
	// Clock signal on channel y is present.
	DFSDM_FLT_ISR_CKABF_Clear = 0x0
	// Clock signal on channel y is not present
	DFSDM_FLT_ISR_CKABF_Set = 0x1
	// Position of RCIP field.
	DFSDM_FLT_ISR_RCIP_Pos = 0xe
	// Bit mask of RCIP field.
	DFSDM_FLT_ISR_RCIP_Msk = 0x4000
	// Bit RCIP.
	DFSDM_FLT_ISR_RCIP = 0x4000
	// No request to convert the regular channel has been issued
	DFSDM_FLT_ISR_RCIP_NotInProgress = 0x0
	// The conversion of the regular channel is in progress or a request for a regular conversion is pending
	DFSDM_FLT_ISR_RCIP_InProgress = 0x1
	// Position of JCIP field.
	DFSDM_FLT_ISR_JCIP_Pos = 0xd
	// Bit mask of JCIP field.
	DFSDM_FLT_ISR_JCIP_Msk = 0x2000
	// Bit JCIP.
	DFSDM_FLT_ISR_JCIP = 0x2000
	// No request to convert the injected channel group (neither by software nor by trigger) has been issued
	DFSDM_FLT_ISR_JCIP_NotInProgress = 0x0
	// The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection
	DFSDM_FLT_ISR_JCIP_InProgress = 0x1
	// Position of AWDF field.
	DFSDM_FLT_ISR_AWDF_Pos = 0x4
	// Bit mask of AWDF field.
	DFSDM_FLT_ISR_AWDF_Msk = 0x10
	// Bit AWDF.
	DFSDM_FLT_ISR_AWDF = 0x10
	// No Analog watchdog event occurred
	DFSDM_FLT_ISR_AWDF_Clear = 0x0
	// The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers
	DFSDM_FLT_ISR_AWDF_Set = 0x1
	// Position of ROVRF field.
	DFSDM_FLT_ISR_ROVRF_Pos = 0x3
	// Bit mask of ROVRF field.
	DFSDM_FLT_ISR_ROVRF_Msk = 0x8
	// Bit ROVRF.
	DFSDM_FLT_ISR_ROVRF = 0x8
	// No regular conversion overrun has occurred
	DFSDM_FLT_ISR_ROVRF_Clear = 0x0
	// A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns
	DFSDM_FLT_ISR_ROVRF_Set = 0x1
	// Position of JOVRF field.
	DFSDM_FLT_ISR_JOVRF_Pos = 0x2
	// Bit mask of JOVRF field.
	DFSDM_FLT_ISR_JOVRF_Msk = 0x4
	// Bit JOVRF.
	DFSDM_FLT_ISR_JOVRF = 0x4
	// No injected conversion overrun has occurred
	DFSDM_FLT_ISR_JOVRF_Clear = 0x0
	// An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns
	DFSDM_FLT_ISR_JOVRF_Set = 0x1
	// Position of REOCF field.
	DFSDM_FLT_ISR_REOCF_Pos = 0x1
	// Bit mask of REOCF field.
	DFSDM_FLT_ISR_REOCF_Msk = 0x2
	// Bit REOCF.
	DFSDM_FLT_ISR_REOCF = 0x2
	// No regular conversion has completed
	DFSDM_FLT_ISR_REOCF_Clear = 0x0
	// A regular conversion has completed and its data may be read
	DFSDM_FLT_ISR_REOCF_Set = 0x1
	// Position of JEOCF field.
	DFSDM_FLT_ISR_JEOCF_Pos = 0x0
	// Bit mask of JEOCF field.
	DFSDM_FLT_ISR_JEOCF_Msk = 0x1
	// Bit JEOCF.
	DFSDM_FLT_ISR_JEOCF = 0x1
	// No injected conversion has completed
	DFSDM_FLT_ISR_JEOCF_Clear = 0x0
	// An injected conversion has completed and its data may be read
	DFSDM_FLT_ISR_JEOCF_Set = 0x1

	// FLT.ICR: interrupt flag clear register
	// Position of CLRSCDF field.
	DFSDM_FLT_ICR_CLRSCDF_Pos = 0x18
	// Bit mask of CLRSCDF field.
	DFSDM_FLT_ICR_CLRSCDF_Msk = 0xff000000
	// Position of CLRCKABF field.
	DFSDM_FLT_ICR_CLRCKABF_Pos = 0x10
	// Bit mask of CLRCKABF field.
	DFSDM_FLT_ICR_CLRCKABF_Msk = 0xff0000
	// Position of CLRROVRF field.
	DFSDM_FLT_ICR_CLRROVRF_Pos = 0x3
	// Bit mask of CLRROVRF field.
	DFSDM_FLT_ICR_CLRROVRF_Msk = 0x8
	// Bit CLRROVRF.
	DFSDM_FLT_ICR_CLRROVRF = 0x8
	// Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register
	DFSDM_FLT_ICR_CLRROVRF_Clear = 0x1
	// Position of CLRJOVRF field.
	DFSDM_FLT_ICR_CLRJOVRF_Pos = 0x2
	// Bit mask of CLRJOVRF field.
	DFSDM_FLT_ICR_CLRJOVRF_Msk = 0x4
	// Bit CLRJOVRF.
	DFSDM_FLT_ICR_CLRJOVRF = 0x4
	// Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register
	DFSDM_FLT_ICR_CLRJOVRF_Clear = 0x1

	// FLT.JCHGR: injected channel group selection register
	// Position of JCHG field.
	DFSDM_FLT_JCHGR_JCHG_Pos = 0x0
	// Bit mask of JCHG field.
	DFSDM_FLT_JCHGR_JCHG_Msk = 0xff

	// FLT.FCR: filter control register
	// Position of FORD field.
	DFSDM_FLT_FCR_FORD_Pos = 0x1d
	// Bit mask of FORD field.
	DFSDM_FLT_FCR_FORD_Msk = 0xe0000000
	// FastSinc filter type
	DFSDM_FLT_FCR_FORD_FastSinc = 0x0
	// Sinc1 filter type
	DFSDM_FLT_FCR_FORD_Sinc1 = 0x1
	// Sinc2 filter type
	DFSDM_FLT_FCR_FORD_Sinc2 = 0x2
	// Sinc3 filter type
	DFSDM_FLT_FCR_FORD_Sinc3 = 0x3
	// Sinc4 filter type
	DFSDM_FLT_FCR_FORD_Sinc4 = 0x4
	// Sinc5 filter type
	DFSDM_FLT_FCR_FORD_Sinc5 = 0x5
	// Position of FOSR field.
	DFSDM_FLT_FCR_FOSR_Pos = 0x10
	// Bit mask of FOSR field.
	DFSDM_FLT_FCR_FOSR_Msk = 0x3ff0000
	// Position of IOSR field.
	DFSDM_FLT_FCR_IOSR_Pos = 0x0
	// Bit mask of IOSR field.
	DFSDM_FLT_FCR_IOSR_Msk = 0xff

	// FLT.JDATAR: data register for injected group
	// Position of JDATA field.
	DFSDM_FLT_JDATAR_JDATA_Pos = 0x8
	// Bit mask of JDATA field.
	DFSDM_FLT_JDATAR_JDATA_Msk = 0xffffff00
	// Position of JDATACH field.
	DFSDM_FLT_JDATAR_JDATACH_Pos = 0x0
	// Bit mask of JDATACH field.
	DFSDM_FLT_JDATAR_JDATACH_Msk = 0x7

	// FLT.RDATAR: data register for the regular channel
	// Position of RDATA field.
	DFSDM_FLT_RDATAR_RDATA_Pos = 0x8
	// Bit mask of RDATA field.
	DFSDM_FLT_RDATAR_RDATA_Msk = 0xffffff00
	// Position of RPEND field.
	DFSDM_FLT_RDATAR_RPEND_Pos = 0x4
	// Bit mask of RPEND field.
	DFSDM_FLT_RDATAR_RPEND_Msk = 0x10
	// Bit RPEND.
	DFSDM_FLT_RDATAR_RPEND = 0x10
	// Position of RDATACH field.
	DFSDM_FLT_RDATAR_RDATACH_Pos = 0x0
	// Bit mask of RDATACH field.
	DFSDM_FLT_RDATAR_RDATACH_Msk = 0x7

	// FLT.AWHTR: analog watchdog high threshold register
	// Position of AWHT field.
	DFSDM_FLT_AWHTR_AWHT_Pos = 0x8
	// Bit mask of AWHT field.
	DFSDM_FLT_AWHTR_AWHT_Msk = 0xffffff00
	// Position of BKAWH0 field.
	DFSDM_FLT_AWHTR_BKAWH0_Pos = 0x1
	// Bit mask of BKAWH0 field.
	DFSDM_FLT_AWHTR_BKAWH0_Msk = 0x2
	// Bit BKAWH0.
	DFSDM_FLT_AWHTR_BKAWH0 = 0x2
	// Break i signal is not assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH0_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH0_Assigned = 0x1
	// Position of BKAWH1 field.
	DFSDM_FLT_AWHTR_BKAWH1_Pos = 0x2
	// Bit mask of BKAWH1 field.
	DFSDM_FLT_AWHTR_BKAWH1_Msk = 0x4
	// Bit BKAWH1.
	DFSDM_FLT_AWHTR_BKAWH1 = 0x4
	// Break i signal is not assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH1_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH1_Assigned = 0x1
	// Position of BKAWH2 field.
	DFSDM_FLT_AWHTR_BKAWH2_Pos = 0x3
	// Bit mask of BKAWH2 field.
	DFSDM_FLT_AWHTR_BKAWH2_Msk = 0x8
	// Bit BKAWH2.
	DFSDM_FLT_AWHTR_BKAWH2 = 0x8
	// Break i signal is not assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH2_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH2_Assigned = 0x1
	// Position of BKAWH3 field.
	DFSDM_FLT_AWHTR_BKAWH3_Pos = 0x4
	// Bit mask of BKAWH3 field.
	DFSDM_FLT_AWHTR_BKAWH3_Msk = 0x10
	// Bit BKAWH3.
	DFSDM_FLT_AWHTR_BKAWH3 = 0x10
	// Break i signal is not assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH3_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog high threshold event
	DFSDM_FLT_AWHTR_BKAWH3_Assigned = 0x1

	// FLT.AWLTR: analog watchdog low threshold register
	// Position of AWLT field.
	DFSDM_FLT_AWLTR_AWLT_Pos = 0x8
	// Bit mask of AWLT field.
	DFSDM_FLT_AWLTR_AWLT_Msk = 0xffffff00
	// Position of BKAWL0 field.
	DFSDM_FLT_AWLTR_BKAWL0_Pos = 0x1
	// Bit mask of BKAWL0 field.
	DFSDM_FLT_AWLTR_BKAWL0_Msk = 0x2
	// Bit BKAWL0.
	DFSDM_FLT_AWLTR_BKAWL0 = 0x2
	// Break i signal is not assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL0_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL0_Assigned = 0x1
	// Position of BKAWL1 field.
	DFSDM_FLT_AWLTR_BKAWL1_Pos = 0x2
	// Bit mask of BKAWL1 field.
	DFSDM_FLT_AWLTR_BKAWL1_Msk = 0x4
	// Bit BKAWL1.
	DFSDM_FLT_AWLTR_BKAWL1 = 0x4
	// Break i signal is not assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL1_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL1_Assigned = 0x1
	// Position of BKAWL2 field.
	DFSDM_FLT_AWLTR_BKAWL2_Pos = 0x3
	// Bit mask of BKAWL2 field.
	DFSDM_FLT_AWLTR_BKAWL2_Msk = 0x8
	// Bit BKAWL2.
	DFSDM_FLT_AWLTR_BKAWL2 = 0x8
	// Break i signal is not assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL2_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL2_Assigned = 0x1
	// Position of BKAWL3 field.
	DFSDM_FLT_AWLTR_BKAWL3_Pos = 0x4
	// Bit mask of BKAWL3 field.
	DFSDM_FLT_AWLTR_BKAWL3_Msk = 0x10
	// Bit BKAWL3.
	DFSDM_FLT_AWLTR_BKAWL3 = 0x10
	// Break i signal is not assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL3_NotAssigned = 0x0
	// Break i signal is assigned to an analog watchdog low threshold event
	DFSDM_FLT_AWLTR_BKAWL3_Assigned = 0x1

	// FLT.AWSR: analog watchdog status register
	// Position of AWHTF0 field.
	DFSDM_FLT_AWSR_AWHTF0_Pos = 0x9
	// Bit mask of AWHTF0 field.
	DFSDM_FLT_AWSR_AWHTF0_Msk = 0x200
	// Bit AWHTF0.
	DFSDM_FLT_AWSR_AWHTF0 = 0x200
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF0_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF0_Error = 0x1
	// Position of AWHTF1 field.
	DFSDM_FLT_AWSR_AWHTF1_Pos = 0xa
	// Bit mask of AWHTF1 field.
	DFSDM_FLT_AWSR_AWHTF1_Msk = 0x400
	// Bit AWHTF1.
	DFSDM_FLT_AWSR_AWHTF1 = 0x400
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF1_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF1_Error = 0x1
	// Position of AWHTF2 field.
	DFSDM_FLT_AWSR_AWHTF2_Pos = 0xb
	// Bit mask of AWHTF2 field.
	DFSDM_FLT_AWSR_AWHTF2_Msk = 0x800
	// Bit AWHTF2.
	DFSDM_FLT_AWSR_AWHTF2 = 0x800
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF2_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF2_Error = 0x1
	// Position of AWHTF3 field.
	DFSDM_FLT_AWSR_AWHTF3_Pos = 0xc
	// Bit mask of AWHTF3 field.
	DFSDM_FLT_AWSR_AWHTF3_Msk = 0x1000
	// Bit AWHTF3.
	DFSDM_FLT_AWSR_AWHTF3 = 0x1000
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF3_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF3_Error = 0x1
	// Position of AWHTF4 field.
	DFSDM_FLT_AWSR_AWHTF4_Pos = 0xd
	// Bit mask of AWHTF4 field.
	DFSDM_FLT_AWSR_AWHTF4_Msk = 0x2000
	// Bit AWHTF4.
	DFSDM_FLT_AWSR_AWHTF4 = 0x2000
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF4_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF4_Error = 0x1
	// Position of AWHTF5 field.
	DFSDM_FLT_AWSR_AWHTF5_Pos = 0xe
	// Bit mask of AWHTF5 field.
	DFSDM_FLT_AWSR_AWHTF5_Msk = 0x4000
	// Bit AWHTF5.
	DFSDM_FLT_AWSR_AWHTF5 = 0x4000
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF5_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF5_Error = 0x1
	// Position of AWHTF6 field.
	DFSDM_FLT_AWSR_AWHTF6_Pos = 0xf
	// Bit mask of AWHTF6 field.
	DFSDM_FLT_AWSR_AWHTF6_Msk = 0x8000
	// Bit AWHTF6.
	DFSDM_FLT_AWSR_AWHTF6 = 0x8000
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF6_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF6_Error = 0x1
	// Position of AWHTF7 field.
	DFSDM_FLT_AWSR_AWHTF7_Pos = 0x10
	// Bit mask of AWHTF7 field.
	DFSDM_FLT_AWSR_AWHTF7_Msk = 0x10000
	// Bit AWHTF7.
	DFSDM_FLT_AWSR_AWHTF7 = 0x10000
	// No high threshold error
	DFSDM_FLT_AWSR_AWHTF7_NoError = 0x0
	// A high threshold error on channel y
	DFSDM_FLT_AWSR_AWHTF7_Error = 0x1
	// Position of AWLTF0 field.
	DFSDM_FLT_AWSR_AWLTF0_Pos = 0x1
	// Bit mask of AWLTF0 field.
	DFSDM_FLT_AWSR_AWLTF0_Msk = 0x2
	// Bit AWLTF0.
	DFSDM_FLT_AWSR_AWLTF0 = 0x2
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF0_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF0_Error = 0x1
	// Position of AWLTF1 field.
	DFSDM_FLT_AWSR_AWLTF1_Pos = 0x2
	// Bit mask of AWLTF1 field.
	DFSDM_FLT_AWSR_AWLTF1_Msk = 0x4
	// Bit AWLTF1.
	DFSDM_FLT_AWSR_AWLTF1 = 0x4
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF1_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF1_Error = 0x1
	// Position of AWLTF2 field.
	DFSDM_FLT_AWSR_AWLTF2_Pos = 0x3
	// Bit mask of AWLTF2 field.
	DFSDM_FLT_AWSR_AWLTF2_Msk = 0x8
	// Bit AWLTF2.
	DFSDM_FLT_AWSR_AWLTF2 = 0x8
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF2_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF2_Error = 0x1
	// Position of AWLTF3 field.
	DFSDM_FLT_AWSR_AWLTF3_Pos = 0x4
	// Bit mask of AWLTF3 field.
	DFSDM_FLT_AWSR_AWLTF3_Msk = 0x10
	// Bit AWLTF3.
	DFSDM_FLT_AWSR_AWLTF3 = 0x10
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF3_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF3_Error = 0x1
	// Position of AWLTF4 field.
	DFSDM_FLT_AWSR_AWLTF4_Pos = 0x5
	// Bit mask of AWLTF4 field.
	DFSDM_FLT_AWSR_AWLTF4_Msk = 0x20
	// Bit AWLTF4.
	DFSDM_FLT_AWSR_AWLTF4 = 0x20
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF4_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF4_Error = 0x1
	// Position of AWLTF5 field.
	DFSDM_FLT_AWSR_AWLTF5_Pos = 0x6
	// Bit mask of AWLTF5 field.
	DFSDM_FLT_AWSR_AWLTF5_Msk = 0x40
	// Bit AWLTF5.
	DFSDM_FLT_AWSR_AWLTF5 = 0x40
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF5_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF5_Error = 0x1
	// Position of AWLTF6 field.
	DFSDM_FLT_AWSR_AWLTF6_Pos = 0x7
	// Bit mask of AWLTF6 field.
	DFSDM_FLT_AWSR_AWLTF6_Msk = 0x80
	// Bit AWLTF6.
	DFSDM_FLT_AWSR_AWLTF6 = 0x80
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF6_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF6_Error = 0x1
	// Position of AWLTF7 field.
	DFSDM_FLT_AWSR_AWLTF7_Pos = 0x8
	// Bit mask of AWLTF7 field.
	DFSDM_FLT_AWSR_AWLTF7_Msk = 0x100
	// Bit AWLTF7.
	DFSDM_FLT_AWSR_AWLTF7 = 0x100
	// No low threshold error
	DFSDM_FLT_AWSR_AWLTF7_NoError = 0x0
	// A low threshold error on channel y
	DFSDM_FLT_AWSR_AWLTF7_Error = 0x1

	// FLT.AWCFR: analog watchdog clear flag register
	// Position of CLRAWHTF0 field.
	DFSDM_FLT_AWCFR_CLRAWHTF0_Pos = 0x9
	// Bit mask of CLRAWHTF0 field.
	DFSDM_FLT_AWCFR_CLRAWHTF0_Msk = 0x200
	// Bit CLRAWHTF0.
	DFSDM_FLT_AWCFR_CLRAWHTF0 = 0x200
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF0_Clear = 0x1
	// Position of CLRAWHTF1 field.
	DFSDM_FLT_AWCFR_CLRAWHTF1_Pos = 0xa
	// Bit mask of CLRAWHTF1 field.
	DFSDM_FLT_AWCFR_CLRAWHTF1_Msk = 0x400
	// Bit CLRAWHTF1.
	DFSDM_FLT_AWCFR_CLRAWHTF1 = 0x400
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF1_Clear = 0x1
	// Position of CLRAWHTF2 field.
	DFSDM_FLT_AWCFR_CLRAWHTF2_Pos = 0xb
	// Bit mask of CLRAWHTF2 field.
	DFSDM_FLT_AWCFR_CLRAWHTF2_Msk = 0x800
	// Bit CLRAWHTF2.
	DFSDM_FLT_AWCFR_CLRAWHTF2 = 0x800
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF2_Clear = 0x1
	// Position of CLRAWHTF3 field.
	DFSDM_FLT_AWCFR_CLRAWHTF3_Pos = 0xc
	// Bit mask of CLRAWHTF3 field.
	DFSDM_FLT_AWCFR_CLRAWHTF3_Msk = 0x1000
	// Bit CLRAWHTF3.
	DFSDM_FLT_AWCFR_CLRAWHTF3 = 0x1000
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF3_Clear = 0x1
	// Position of CLRAWHTF4 field.
	DFSDM_FLT_AWCFR_CLRAWHTF4_Pos = 0xd
	// Bit mask of CLRAWHTF4 field.
	DFSDM_FLT_AWCFR_CLRAWHTF4_Msk = 0x2000
	// Bit CLRAWHTF4.
	DFSDM_FLT_AWCFR_CLRAWHTF4 = 0x2000
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF4_Clear = 0x1
	// Position of CLRAWHTF5 field.
	DFSDM_FLT_AWCFR_CLRAWHTF5_Pos = 0xe
	// Bit mask of CLRAWHTF5 field.
	DFSDM_FLT_AWCFR_CLRAWHTF5_Msk = 0x4000
	// Bit CLRAWHTF5.
	DFSDM_FLT_AWCFR_CLRAWHTF5 = 0x4000
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF5_Clear = 0x1
	// Position of CLRAWHTF6 field.
	DFSDM_FLT_AWCFR_CLRAWHTF6_Pos = 0xf
	// Bit mask of CLRAWHTF6 field.
	DFSDM_FLT_AWCFR_CLRAWHTF6_Msk = 0x8000
	// Bit CLRAWHTF6.
	DFSDM_FLT_AWCFR_CLRAWHTF6 = 0x8000
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF6_Clear = 0x1
	// Position of CLRAWHTF7 field.
	DFSDM_FLT_AWCFR_CLRAWHTF7_Pos = 0x10
	// Bit mask of CLRAWHTF7 field.
	DFSDM_FLT_AWCFR_CLRAWHTF7_Msk = 0x10000
	// Bit CLRAWHTF7.
	DFSDM_FLT_AWCFR_CLRAWHTF7 = 0x10000
	// Clear the corresponding AWHTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWHTF7_Clear = 0x1
	// Position of CLRAWLTF0 field.
	DFSDM_FLT_AWCFR_CLRAWLTF0_Pos = 0x1
	// Bit mask of CLRAWLTF0 field.
	DFSDM_FLT_AWCFR_CLRAWLTF0_Msk = 0x2
	// Bit CLRAWLTF0.
	DFSDM_FLT_AWCFR_CLRAWLTF0 = 0x2
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF0_Clear = 0x1
	// Position of CLRAWLTF1 field.
	DFSDM_FLT_AWCFR_CLRAWLTF1_Pos = 0x2
	// Bit mask of CLRAWLTF1 field.
	DFSDM_FLT_AWCFR_CLRAWLTF1_Msk = 0x4
	// Bit CLRAWLTF1.
	DFSDM_FLT_AWCFR_CLRAWLTF1 = 0x4
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF1_Clear = 0x1
	// Position of CLRAWLTF2 field.
	DFSDM_FLT_AWCFR_CLRAWLTF2_Pos = 0x3
	// Bit mask of CLRAWLTF2 field.
	DFSDM_FLT_AWCFR_CLRAWLTF2_Msk = 0x8
	// Bit CLRAWLTF2.
	DFSDM_FLT_AWCFR_CLRAWLTF2 = 0x8
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF2_Clear = 0x1
	// Position of CLRAWLTF3 field.
	DFSDM_FLT_AWCFR_CLRAWLTF3_Pos = 0x4
	// Bit mask of CLRAWLTF3 field.
	DFSDM_FLT_AWCFR_CLRAWLTF3_Msk = 0x10
	// Bit CLRAWLTF3.
	DFSDM_FLT_AWCFR_CLRAWLTF3 = 0x10
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF3_Clear = 0x1
	// Position of CLRAWLTF4 field.
	DFSDM_FLT_AWCFR_CLRAWLTF4_Pos = 0x5
	// Bit mask of CLRAWLTF4 field.
	DFSDM_FLT_AWCFR_CLRAWLTF4_Msk = 0x20
	// Bit CLRAWLTF4.
	DFSDM_FLT_AWCFR_CLRAWLTF4 = 0x20
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF4_Clear = 0x1
	// Position of CLRAWLTF5 field.
	DFSDM_FLT_AWCFR_CLRAWLTF5_Pos = 0x6
	// Bit mask of CLRAWLTF5 field.
	DFSDM_FLT_AWCFR_CLRAWLTF5_Msk = 0x40
	// Bit CLRAWLTF5.
	DFSDM_FLT_AWCFR_CLRAWLTF5 = 0x40
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF5_Clear = 0x1
	// Position of CLRAWLTF6 field.
	DFSDM_FLT_AWCFR_CLRAWLTF6_Pos = 0x7
	// Bit mask of CLRAWLTF6 field.
	DFSDM_FLT_AWCFR_CLRAWLTF6_Msk = 0x80
	// Bit CLRAWLTF6.
	DFSDM_FLT_AWCFR_CLRAWLTF6 = 0x80
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF6_Clear = 0x1
	// Position of CLRAWLTF7 field.
	DFSDM_FLT_AWCFR_CLRAWLTF7_Pos = 0x8
	// Bit mask of CLRAWLTF7 field.
	DFSDM_FLT_AWCFR_CLRAWLTF7_Msk = 0x100
	// Bit CLRAWLTF7.
	DFSDM_FLT_AWCFR_CLRAWLTF7 = 0x100
	// Clear the corresponding AWLTF[y] bit
	DFSDM_FLT_AWCFR_CLRAWLTF7_Clear = 0x1

	// FLT.EXMAX: Extremes detector maximum register
	// Position of EXMAX field.
	DFSDM_FLT_EXMAX_EXMAX_Pos = 0x8
	// Bit mask of EXMAX field.
	DFSDM_FLT_EXMAX_EXMAX_Msk = 0xffffff00
	// Position of EXMAXCH field.
	DFSDM_FLT_EXMAX_EXMAXCH_Pos = 0x0
	// Bit mask of EXMAXCH field.
	DFSDM_FLT_EXMAX_EXMAXCH_Msk = 0x7

	// FLT.EXMIN: Extremes detector minimum register
	// Position of EXMIN field.
	DFSDM_FLT_EXMIN_EXMIN_Pos = 0x8
	// Bit mask of EXMIN field.
	DFSDM_FLT_EXMIN_EXMIN_Msk = 0xffffff00
	// Position of EXMINCH field.
	DFSDM_FLT_EXMIN_EXMINCH_Pos = 0x0
	// Bit mask of EXMINCH field.
	DFSDM_FLT_EXMIN_EXMINCH_Msk = 0x7

	// FLT.CNVTIMR: conversion timer register
	// Position of CNVCNT field.
	DFSDM_FLT_CNVTIMR_CNVCNT_Pos = 0x4
	// Bit mask of CNVCNT field.
	DFSDM_FLT_CNVTIMR_CNVCNT_Msk = 0xfffffff0
)

// Constants for DMA1: Direct memory access controller
const (
	// ISR: interrupt status register
	// Position of TEIF1 field.
	DMA_ISR_TEIF1_Pos = 0x7
	// Bit mask of TEIF1 field.
	DMA_ISR_TEIF1_Msk = 0x80
	// Bit TEIF1.
	DMA_ISR_TEIF1 = 0x80
	// No transfer error
	DMA_ISR_TEIF1_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF1_Error = 0x1
	// Position of TEIF2 field.
	DMA_ISR_TEIF2_Pos = 0xb
	// Bit mask of TEIF2 field.
	DMA_ISR_TEIF2_Msk = 0x800
	// Bit TEIF2.
	DMA_ISR_TEIF2 = 0x800
	// No transfer error
	DMA_ISR_TEIF2_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF2_Error = 0x1
	// Position of TEIF3 field.
	DMA_ISR_TEIF3_Pos = 0xf
	// Bit mask of TEIF3 field.
	DMA_ISR_TEIF3_Msk = 0x8000
	// Bit TEIF3.
	DMA_ISR_TEIF3 = 0x8000
	// No transfer error
	DMA_ISR_TEIF3_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF3_Error = 0x1
	// Position of TEIF4 field.
	DMA_ISR_TEIF4_Pos = 0x13
	// Bit mask of TEIF4 field.
	DMA_ISR_TEIF4_Msk = 0x80000
	// Bit TEIF4.
	DMA_ISR_TEIF4 = 0x80000
	// No transfer error
	DMA_ISR_TEIF4_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF4_Error = 0x1
	// Position of TEIF5 field.
	DMA_ISR_TEIF5_Pos = 0x17
	// Bit mask of TEIF5 field.
	DMA_ISR_TEIF5_Msk = 0x800000
	// Bit TEIF5.
	DMA_ISR_TEIF5 = 0x800000
	// No transfer error
	DMA_ISR_TEIF5_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF5_Error = 0x1
	// Position of TEIF6 field.
	DMA_ISR_TEIF6_Pos = 0x1b
	// Bit mask of TEIF6 field.
	DMA_ISR_TEIF6_Msk = 0x8000000
	// Bit TEIF6.
	DMA_ISR_TEIF6 = 0x8000000
	// No transfer error
	DMA_ISR_TEIF6_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF6_Error = 0x1
	// Position of TEIF7 field.
	DMA_ISR_TEIF7_Pos = 0x1f
	// Bit mask of TEIF7 field.
	DMA_ISR_TEIF7_Msk = 0x80000000
	// Bit TEIF7.
	DMA_ISR_TEIF7 = 0x80000000
	// No transfer error
	DMA_ISR_TEIF7_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF7_Error = 0x1
	// Position of TEIF8 field.
	DMA_ISR_TEIF8_Pos = 0x23
	// Bit mask of TEIF8 field.
	DMA_ISR_TEIF8_Msk = 0x800000000
	// Bit TEIF8.
	DMA_ISR_TEIF8 = 0x800000000
	// No transfer error
	DMA_ISR_TEIF8_NoError = 0x0
	// A transfer error has occured
	DMA_ISR_TEIF8_Error = 0x1
	// Position of HTIF1 field.
	DMA_ISR_HTIF1_Pos = 0x6
	// Bit mask of HTIF1 field.
	DMA_ISR_HTIF1_Msk = 0x40
	// Bit HTIF1.
	DMA_ISR_HTIF1 = 0x40
	// No half transfer event
	DMA_ISR_HTIF1_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF1_Half = 0x1
	// Position of HTIF2 field.
	DMA_ISR_HTIF2_Pos = 0xa
	// Bit mask of HTIF2 field.
	DMA_ISR_HTIF2_Msk = 0x400
	// Bit HTIF2.
	DMA_ISR_HTIF2 = 0x400
	// No half transfer event
	DMA_ISR_HTIF2_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF2_Half = 0x1
	// Position of HTIF3 field.
	DMA_ISR_HTIF3_Pos = 0xe
	// Bit mask of HTIF3 field.
	DMA_ISR_HTIF3_Msk = 0x4000
	// Bit HTIF3.
	DMA_ISR_HTIF3 = 0x4000
	// No half transfer event
	DMA_ISR_HTIF3_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF3_Half = 0x1
	// Position of HTIF4 field.
	DMA_ISR_HTIF4_Pos = 0x12
	// Bit mask of HTIF4 field.
	DMA_ISR_HTIF4_Msk = 0x40000
	// Bit HTIF4.
	DMA_ISR_HTIF4 = 0x40000
	// No half transfer event
	DMA_ISR_HTIF4_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF4_Half = 0x1
	// Position of HTIF5 field.
	DMA_ISR_HTIF5_Pos = 0x16
	// Bit mask of HTIF5 field.
	DMA_ISR_HTIF5_Msk = 0x400000
	// Bit HTIF5.
	DMA_ISR_HTIF5 = 0x400000
	// No half transfer event
	DMA_ISR_HTIF5_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF5_Half = 0x1
	// Position of HTIF6 field.
	DMA_ISR_HTIF6_Pos = 0x1a
	// Bit mask of HTIF6 field.
	DMA_ISR_HTIF6_Msk = 0x4000000
	// Bit HTIF6.
	DMA_ISR_HTIF6 = 0x4000000
	// No half transfer event
	DMA_ISR_HTIF6_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF6_Half = 0x1
	// Position of HTIF7 field.
	DMA_ISR_HTIF7_Pos = 0x1e
	// Bit mask of HTIF7 field.
	DMA_ISR_HTIF7_Msk = 0x40000000
	// Bit HTIF7.
	DMA_ISR_HTIF7 = 0x40000000
	// No half transfer event
	DMA_ISR_HTIF7_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF7_Half = 0x1
	// Position of HTIF8 field.
	DMA_ISR_HTIF8_Pos = 0x22
	// Bit mask of HTIF8 field.
	DMA_ISR_HTIF8_Msk = 0x400000000
	// Bit HTIF8.
	DMA_ISR_HTIF8 = 0x400000000
	// No half transfer event
	DMA_ISR_HTIF8_NotHalf = 0x0
	// A half transfer event has occured
	DMA_ISR_HTIF8_Half = 0x1
	// Position of TCIF1 field.
	DMA_ISR_TCIF1_Pos = 0x5
	// Bit mask of TCIF1 field.
	DMA_ISR_TCIF1_Msk = 0x20
	// Bit TCIF1.
	DMA_ISR_TCIF1 = 0x20
	// No transfer complete event
	DMA_ISR_TCIF1_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF1_Complete = 0x1
	// Position of TCIF2 field.
	DMA_ISR_TCIF2_Pos = 0x9
	// Bit mask of TCIF2 field.
	DMA_ISR_TCIF2_Msk = 0x200
	// Bit TCIF2.
	DMA_ISR_TCIF2 = 0x200
	// No transfer complete event
	DMA_ISR_TCIF2_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF2_Complete = 0x1
	// Position of TCIF3 field.
	DMA_ISR_TCIF3_Pos = 0xd
	// Bit mask of TCIF3 field.
	DMA_ISR_TCIF3_Msk = 0x2000
	// Bit TCIF3.
	DMA_ISR_TCIF3 = 0x2000
	// No transfer complete event
	DMA_ISR_TCIF3_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF3_Complete = 0x1
	// Position of TCIF4 field.
	DMA_ISR_TCIF4_Pos = 0x11
	// Bit mask of TCIF4 field.
	DMA_ISR_TCIF4_Msk = 0x20000
	// Bit TCIF4.
	DMA_ISR_TCIF4 = 0x20000
	// No transfer complete event
	DMA_ISR_TCIF4_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF4_Complete = 0x1
	// Position of TCIF5 field.
	DMA_ISR_TCIF5_Pos = 0x15
	// Bit mask of TCIF5 field.
	DMA_ISR_TCIF5_Msk = 0x200000
	// Bit TCIF5.
	DMA_ISR_TCIF5 = 0x200000
	// No transfer complete event
	DMA_ISR_TCIF5_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF5_Complete = 0x1
	// Position of TCIF6 field.
	DMA_ISR_TCIF6_Pos = 0x19
	// Bit mask of TCIF6 field.
	DMA_ISR_TCIF6_Msk = 0x2000000
	// Bit TCIF6.
	DMA_ISR_TCIF6 = 0x2000000
	// No transfer complete event
	DMA_ISR_TCIF6_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF6_Complete = 0x1
	// Position of TCIF7 field.
	DMA_ISR_TCIF7_Pos = 0x1d
	// Bit mask of TCIF7 field.
	DMA_ISR_TCIF7_Msk = 0x20000000
	// Bit TCIF7.
	DMA_ISR_TCIF7 = 0x20000000
	// No transfer complete event
	DMA_ISR_TCIF7_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF7_Complete = 0x1
	// Position of TCIF8 field.
	DMA_ISR_TCIF8_Pos = 0x21
	// Bit mask of TCIF8 field.
	DMA_ISR_TCIF8_Msk = 0x200000000
	// Bit TCIF8.
	DMA_ISR_TCIF8 = 0x200000000
	// No transfer complete event
	DMA_ISR_TCIF8_NotComplete = 0x0
	// A transfer complete event has occured
	DMA_ISR_TCIF8_Complete = 0x1
	// Position of GIF1 field.
	DMA_ISR_GIF1_Pos = 0x4
	// Bit mask of GIF1 field.
	DMA_ISR_GIF1_Msk = 0x10
	// Bit GIF1.
	DMA_ISR_GIF1 = 0x10
	// No transfer error, half event, complete event
	DMA_ISR_GIF1_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF1_Event = 0x1
	// Position of GIF2 field.
	DMA_ISR_GIF2_Pos = 0x8
	// Bit mask of GIF2 field.
	DMA_ISR_GIF2_Msk = 0x100
	// Bit GIF2.
	DMA_ISR_GIF2 = 0x100
	// No transfer error, half event, complete event
	DMA_ISR_GIF2_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF2_Event = 0x1
	// Position of GIF3 field.
	DMA_ISR_GIF3_Pos = 0xc
	// Bit mask of GIF3 field.
	DMA_ISR_GIF3_Msk = 0x1000
	// Bit GIF3.
	DMA_ISR_GIF3 = 0x1000
	// No transfer error, half event, complete event
	DMA_ISR_GIF3_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF3_Event = 0x1
	// Position of GIF4 field.
	DMA_ISR_GIF4_Pos = 0x10
	// Bit mask of GIF4 field.
	DMA_ISR_GIF4_Msk = 0x10000
	// Bit GIF4.
	DMA_ISR_GIF4 = 0x10000
	// No transfer error, half event, complete event
	DMA_ISR_GIF4_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF4_Event = 0x1
	// Position of GIF5 field.
	DMA_ISR_GIF5_Pos = 0x14
	// Bit mask of GIF5 field.
	DMA_ISR_GIF5_Msk = 0x100000
	// Bit GIF5.
	DMA_ISR_GIF5 = 0x100000
	// No transfer error, half event, complete event
	DMA_ISR_GIF5_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF5_Event = 0x1
	// Position of GIF6 field.
	DMA_ISR_GIF6_Pos = 0x18
	// Bit mask of GIF6 field.
	DMA_ISR_GIF6_Msk = 0x1000000
	// Bit GIF6.
	DMA_ISR_GIF6 = 0x1000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF6_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF6_Event = 0x1
	// Position of GIF7 field.
	DMA_ISR_GIF7_Pos = 0x1c
	// Bit mask of GIF7 field.
	DMA_ISR_GIF7_Msk = 0x10000000
	// Bit GIF7.
	DMA_ISR_GIF7 = 0x10000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF7_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF7_Event = 0x1
	// Position of GIF8 field.
	DMA_ISR_GIF8_Pos = 0x20
	// Bit mask of GIF8 field.
	DMA_ISR_GIF8_Msk = 0x100000000
	// Bit GIF8.
	DMA_ISR_GIF8 = 0x100000000
	// No transfer error, half event, complete event
	DMA_ISR_GIF8_NoEvent = 0x0
	// A transfer error, half event or complete event has occured
	DMA_ISR_GIF8_Event = 0x1

	// IFCR: interrupt flag clear register
	// Position of CTEIF1 field.
	DMA_IFCR_CTEIF1_Pos = 0x7
	// Bit mask of CTEIF1 field.
	DMA_IFCR_CTEIF1_Msk = 0x80
	// Bit CTEIF1.
	DMA_IFCR_CTEIF1 = 0x80
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF1_Clear = 0x1
	// Position of CTEIF2 field.
	DMA_IFCR_CTEIF2_Pos = 0xb
	// Bit mask of CTEIF2 field.
	DMA_IFCR_CTEIF2_Msk = 0x800
	// Bit CTEIF2.
	DMA_IFCR_CTEIF2 = 0x800
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF2_Clear = 0x1
	// Position of CTEIF3 field.
	DMA_IFCR_CTEIF3_Pos = 0xf
	// Bit mask of CTEIF3 field.
	DMA_IFCR_CTEIF3_Msk = 0x8000
	// Bit CTEIF3.
	DMA_IFCR_CTEIF3 = 0x8000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF3_Clear = 0x1
	// Position of CTEIF4 field.
	DMA_IFCR_CTEIF4_Pos = 0x13
	// Bit mask of CTEIF4 field.
	DMA_IFCR_CTEIF4_Msk = 0x80000
	// Bit CTEIF4.
	DMA_IFCR_CTEIF4 = 0x80000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF4_Clear = 0x1
	// Position of CTEIF5 field.
	DMA_IFCR_CTEIF5_Pos = 0x17
	// Bit mask of CTEIF5 field.
	DMA_IFCR_CTEIF5_Msk = 0x800000
	// Bit CTEIF5.
	DMA_IFCR_CTEIF5 = 0x800000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF5_Clear = 0x1
	// Position of CTEIF6 field.
	DMA_IFCR_CTEIF6_Pos = 0x1b
	// Bit mask of CTEIF6 field.
	DMA_IFCR_CTEIF6_Msk = 0x8000000
	// Bit CTEIF6.
	DMA_IFCR_CTEIF6 = 0x8000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF6_Clear = 0x1
	// Position of CTEIF7 field.
	DMA_IFCR_CTEIF7_Pos = 0x1f
	// Bit mask of CTEIF7 field.
	DMA_IFCR_CTEIF7_Msk = 0x80000000
	// Bit CTEIF7.
	DMA_IFCR_CTEIF7 = 0x80000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF7_Clear = 0x1
	// Position of CTEIF8 field.
	DMA_IFCR_CTEIF8_Pos = 0x23
	// Bit mask of CTEIF8 field.
	DMA_IFCR_CTEIF8_Msk = 0x800000000
	// Bit CTEIF8.
	DMA_IFCR_CTEIF8 = 0x800000000
	// Clears the TEIF flag in the ISR register
	DMA_IFCR_CTEIF8_Clear = 0x1
	// Position of CHTIF1 field.
	DMA_IFCR_CHTIF1_Pos = 0x6
	// Bit mask of CHTIF1 field.
	DMA_IFCR_CHTIF1_Msk = 0x40
	// Bit CHTIF1.
	DMA_IFCR_CHTIF1 = 0x40
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF1_Clear = 0x1
	// Position of CHTIF2 field.
	DMA_IFCR_CHTIF2_Pos = 0xa
	// Bit mask of CHTIF2 field.
	DMA_IFCR_CHTIF2_Msk = 0x400
	// Bit CHTIF2.
	DMA_IFCR_CHTIF2 = 0x400
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF2_Clear = 0x1
	// Position of CHTIF3 field.
	DMA_IFCR_CHTIF3_Pos = 0xe
	// Bit mask of CHTIF3 field.
	DMA_IFCR_CHTIF3_Msk = 0x4000
	// Bit CHTIF3.
	DMA_IFCR_CHTIF3 = 0x4000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF3_Clear = 0x1
	// Position of CHTIF4 field.
	DMA_IFCR_CHTIF4_Pos = 0x12
	// Bit mask of CHTIF4 field.
	DMA_IFCR_CHTIF4_Msk = 0x40000
	// Bit CHTIF4.
	DMA_IFCR_CHTIF4 = 0x40000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF4_Clear = 0x1
	// Position of CHTIF5 field.
	DMA_IFCR_CHTIF5_Pos = 0x16
	// Bit mask of CHTIF5 field.
	DMA_IFCR_CHTIF5_Msk = 0x400000
	// Bit CHTIF5.
	DMA_IFCR_CHTIF5 = 0x400000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF5_Clear = 0x1
	// Position of CHTIF6 field.
	DMA_IFCR_CHTIF6_Pos = 0x1a
	// Bit mask of CHTIF6 field.
	DMA_IFCR_CHTIF6_Msk = 0x4000000
	// Bit CHTIF6.
	DMA_IFCR_CHTIF6 = 0x4000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF6_Clear = 0x1
	// Position of CHTIF7 field.
	DMA_IFCR_CHTIF7_Pos = 0x1e
	// Bit mask of CHTIF7 field.
	DMA_IFCR_CHTIF7_Msk = 0x40000000
	// Bit CHTIF7.
	DMA_IFCR_CHTIF7 = 0x40000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF7_Clear = 0x1
	// Position of CHTIF8 field.
	DMA_IFCR_CHTIF8_Pos = 0x22
	// Bit mask of CHTIF8 field.
	DMA_IFCR_CHTIF8_Msk = 0x400000000
	// Bit CHTIF8.
	DMA_IFCR_CHTIF8 = 0x400000000
	// Clears the HTIF flag in the ISR register
	DMA_IFCR_CHTIF8_Clear = 0x1
	// Position of CTCIF1 field.
	DMA_IFCR_CTCIF1_Pos = 0x5
	// Bit mask of CTCIF1 field.
	DMA_IFCR_CTCIF1_Msk = 0x20
	// Bit CTCIF1.
	DMA_IFCR_CTCIF1 = 0x20
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF1_Clear = 0x1
	// Position of CTCIF2 field.
	DMA_IFCR_CTCIF2_Pos = 0x9
	// Bit mask of CTCIF2 field.
	DMA_IFCR_CTCIF2_Msk = 0x200
	// Bit CTCIF2.
	DMA_IFCR_CTCIF2 = 0x200
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF2_Clear = 0x1
	// Position of CTCIF3 field.
	DMA_IFCR_CTCIF3_Pos = 0xd
	// Bit mask of CTCIF3 field.
	DMA_IFCR_CTCIF3_Msk = 0x2000
	// Bit CTCIF3.
	DMA_IFCR_CTCIF3 = 0x2000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF3_Clear = 0x1
	// Position of CTCIF4 field.
	DMA_IFCR_CTCIF4_Pos = 0x11
	// Bit mask of CTCIF4 field.
	DMA_IFCR_CTCIF4_Msk = 0x20000
	// Bit CTCIF4.
	DMA_IFCR_CTCIF4 = 0x20000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF4_Clear = 0x1
	// Position of CTCIF5 field.
	DMA_IFCR_CTCIF5_Pos = 0x15
	// Bit mask of CTCIF5 field.
	DMA_IFCR_CTCIF5_Msk = 0x200000
	// Bit CTCIF5.
	DMA_IFCR_CTCIF5 = 0x200000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF5_Clear = 0x1
	// Position of CTCIF6 field.
	DMA_IFCR_CTCIF6_Pos = 0x19
	// Bit mask of CTCIF6 field.
	DMA_IFCR_CTCIF6_Msk = 0x2000000
	// Bit CTCIF6.
	DMA_IFCR_CTCIF6 = 0x2000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF6_Clear = 0x1
	// Position of CTCIF7 field.
	DMA_IFCR_CTCIF7_Pos = 0x1d
	// Bit mask of CTCIF7 field.
	DMA_IFCR_CTCIF7_Msk = 0x20000000
	// Bit CTCIF7.
	DMA_IFCR_CTCIF7 = 0x20000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF7_Clear = 0x1
	// Position of CTCIF8 field.
	DMA_IFCR_CTCIF8_Pos = 0x21
	// Bit mask of CTCIF8 field.
	DMA_IFCR_CTCIF8_Msk = 0x200000000
	// Bit CTCIF8.
	DMA_IFCR_CTCIF8 = 0x200000000
	// Clears the TCIF flag in the ISR register
	DMA_IFCR_CTCIF8_Clear = 0x1
	// Position of CGIF1 field.
	DMA_IFCR_CGIF1_Pos = 0x4
	// Bit mask of CGIF1 field.
	DMA_IFCR_CGIF1_Msk = 0x10
	// Bit CGIF1.
	DMA_IFCR_CGIF1 = 0x10
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF1_Clear = 0x1
	// Position of CGIF2 field.
	DMA_IFCR_CGIF2_Pos = 0x8
	// Bit mask of CGIF2 field.
	DMA_IFCR_CGIF2_Msk = 0x100
	// Bit CGIF2.
	DMA_IFCR_CGIF2 = 0x100
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF2_Clear = 0x1
	// Position of CGIF3 field.
	DMA_IFCR_CGIF3_Pos = 0xc
	// Bit mask of CGIF3 field.
	DMA_IFCR_CGIF3_Msk = 0x1000
	// Bit CGIF3.
	DMA_IFCR_CGIF3 = 0x1000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF3_Clear = 0x1
	// Position of CGIF4 field.
	DMA_IFCR_CGIF4_Pos = 0x10
	// Bit mask of CGIF4 field.
	DMA_IFCR_CGIF4_Msk = 0x10000
	// Bit CGIF4.
	DMA_IFCR_CGIF4 = 0x10000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF4_Clear = 0x1
	// Position of CGIF5 field.
	DMA_IFCR_CGIF5_Pos = 0x14
	// Bit mask of CGIF5 field.
	DMA_IFCR_CGIF5_Msk = 0x100000
	// Bit CGIF5.
	DMA_IFCR_CGIF5 = 0x100000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF5_Clear = 0x1
	// Position of CGIF6 field.
	DMA_IFCR_CGIF6_Pos = 0x18
	// Bit mask of CGIF6 field.
	DMA_IFCR_CGIF6_Msk = 0x1000000
	// Bit CGIF6.
	DMA_IFCR_CGIF6 = 0x1000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF6_Clear = 0x1
	// Position of CGIF7 field.
	DMA_IFCR_CGIF7_Pos = 0x1c
	// Bit mask of CGIF7 field.
	DMA_IFCR_CGIF7_Msk = 0x10000000
	// Bit CGIF7.
	DMA_IFCR_CGIF7 = 0x10000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF7_Clear = 0x1
	// Position of CGIF8 field.
	DMA_IFCR_CGIF8_Pos = 0x20
	// Bit mask of CGIF8 field.
	DMA_IFCR_CGIF8_Msk = 0x100000000
	// Bit CGIF8.
	DMA_IFCR_CGIF8 = 0x100000000
	// Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
	DMA_IFCR_CGIF8_Clear = 0x1

	// CH.CR: channel x configuration register
	// Position of PRIV field.
	DMA_CH_CR_PRIV_Pos = 0x14
	// Bit mask of PRIV field.
	DMA_CH_CR_PRIV_Msk = 0x100000
	// Bit PRIV.
	DMA_CH_CR_PRIV = 0x100000
	// Position of DSEC field.
	DMA_CH_CR_DSEC_Pos = 0x13
	// Bit mask of DSEC field.
	DMA_CH_CR_DSEC_Msk = 0x80000
	// Bit DSEC.
	DMA_CH_CR_DSEC = 0x80000
	// Position of SSEC field.
	DMA_CH_CR_SSEC_Pos = 0x12
	// Bit mask of SSEC field.
	DMA_CH_CR_SSEC_Msk = 0x40000
	// Bit SSEC.
	DMA_CH_CR_SSEC = 0x40000
	// Position of SECM field.
	DMA_CH_CR_SECM_Pos = 0x11
	// Bit mask of SECM field.
	DMA_CH_CR_SECM_Msk = 0x20000
	// Bit SECM.
	DMA_CH_CR_SECM = 0x20000
	// Position of CT field.
	DMA_CH_CR_CT_Pos = 0x10
	// Bit mask of CT field.
	DMA_CH_CR_CT_Msk = 0x10000
	// Bit CT.
	DMA_CH_CR_CT = 0x10000
	// Position of DBM field.
	DMA_CH_CR_DBM_Pos = 0xf
	// Bit mask of DBM field.
	DMA_CH_CR_DBM_Msk = 0x8000
	// Bit DBM.
	DMA_CH_CR_DBM = 0x8000
	// Position of MEM2MEM field.
	DMA_CH_CR_MEM2MEM_Pos = 0xe
	// Bit mask of MEM2MEM field.
	DMA_CH_CR_MEM2MEM_Msk = 0x4000
	// Bit MEM2MEM.
	DMA_CH_CR_MEM2MEM = 0x4000
	// Memory to memory mode disabled
	DMA_CH_CR_MEM2MEM_Disabled = 0x0
	// Memory to memory mode enabled
	DMA_CH_CR_MEM2MEM_Enabled = 0x1
	// Position of PL field.
	DMA_CH_CR_PL_Pos = 0xc
	// Bit mask of PL field.
	DMA_CH_CR_PL_Msk = 0x3000
	// Low priority
	DMA_CH_CR_PL_Low = 0x0
	// Medium priority
	DMA_CH_CR_PL_Medium = 0x1
	// High priority
	DMA_CH_CR_PL_High = 0x2
	// Very high priority
	DMA_CH_CR_PL_VeryHigh = 0x3
	// Position of PSIZE field.
	DMA_CH_CR_PSIZE_Pos = 0x8
	// Bit mask of PSIZE field.
	DMA_CH_CR_PSIZE_Msk = 0x300
	// 8-bit size
	DMA_CH_CR_PSIZE_Bits8 = 0x0
	// 16-bit size
	DMA_CH_CR_PSIZE_Bits16 = 0x1
	// 32-bit size
	DMA_CH_CR_PSIZE_Bits32 = 0x2
	// Position of MSIZE field.
	DMA_CH_CR_MSIZE_Pos = 0xa
	// Bit mask of MSIZE field.
	DMA_CH_CR_MSIZE_Msk = 0xc00
	// 8-bit size
	DMA_CH_CR_MSIZE_Bits8 = 0x0
	// 16-bit size
	DMA_CH_CR_MSIZE_Bits16 = 0x1
	// 32-bit size
	DMA_CH_CR_MSIZE_Bits32 = 0x2
	// Position of PINC field.
	DMA_CH_CR_PINC_Pos = 0x6
	// Bit mask of PINC field.
	DMA_CH_CR_PINC_Msk = 0x40
	// Bit PINC.
	DMA_CH_CR_PINC = 0x40
	// Increment mode disabled
	DMA_CH_CR_PINC_Disabled = 0x0
	// Increment mode enabled
	DMA_CH_CR_PINC_Enabled = 0x1
	// Position of MINC field.
	DMA_CH_CR_MINC_Pos = 0x7
	// Bit mask of MINC field.
	DMA_CH_CR_MINC_Msk = 0x80
	// Bit MINC.
	DMA_CH_CR_MINC = 0x80
	// Increment mode disabled
	DMA_CH_CR_MINC_Disabled = 0x0
	// Increment mode enabled
	DMA_CH_CR_MINC_Enabled = 0x1
	// Position of CIRC field.
	DMA_CH_CR_CIRC_Pos = 0x5
	// Bit mask of CIRC field.
	DMA_CH_CR_CIRC_Msk = 0x20
	// Bit CIRC.
	DMA_CH_CR_CIRC = 0x20
	// Circular buffer disabled
	DMA_CH_CR_CIRC_Disabled = 0x0
	// Circular buffer enabled
	DMA_CH_CR_CIRC_Enabled = 0x1
	// Position of DIR field.
	DMA_CH_CR_DIR_Pos = 0x4
	// Bit mask of DIR field.
	DMA_CH_CR_DIR_Msk = 0x10
	// Bit DIR.
	DMA_CH_CR_DIR = 0x10
	// Read from peripheral
	DMA_CH_CR_DIR_FromPeripheral = 0x0
	// Read from memory
	DMA_CH_CR_DIR_FromMemory = 0x1
	// Position of TEIE field.
	DMA_CH_CR_TEIE_Pos = 0x3
	// Bit mask of TEIE field.
	DMA_CH_CR_TEIE_Msk = 0x8
	// Bit TEIE.
	DMA_CH_CR_TEIE = 0x8
	// Transfer Error interrupt disabled
	DMA_CH_CR_TEIE_Disabled = 0x0
	// Transfer Error interrupt enabled
	DMA_CH_CR_TEIE_Enabled = 0x1
	// Position of HTIE field.
	DMA_CH_CR_HTIE_Pos = 0x2
	// Bit mask of HTIE field.
	DMA_CH_CR_HTIE_Msk = 0x4
	// Bit HTIE.
	DMA_CH_CR_HTIE = 0x4
	// Half Transfer interrupt disabled
	DMA_CH_CR_HTIE_Disabled = 0x0
	// Half Transfer interrupt enabled
	DMA_CH_CR_HTIE_Enabled = 0x1
	// Position of TCIE field.
	DMA_CH_CR_TCIE_Pos = 0x1
	// Bit mask of TCIE field.
	DMA_CH_CR_TCIE_Msk = 0x2
	// Bit TCIE.
	DMA_CH_CR_TCIE = 0x2
	// Transfer Complete interrupt disabled
	DMA_CH_CR_TCIE_Disabled = 0x0
	// Transfer Complete interrupt enabled
	DMA_CH_CR_TCIE_Enabled = 0x1
	// Position of EN field.
	DMA_CH_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	DMA_CH_CR_EN_Msk = 0x1
	// Bit EN.
	DMA_CH_CR_EN = 0x1
	// Channel disabled
	DMA_CH_CR_EN_Disabled = 0x0
	// Channel enabled
	DMA_CH_CR_EN_Enabled = 0x1

	// CH.NDTR: channel x number of data register
	// Position of NDT field.
	DMA_CH_NDTR_NDT_Pos = 0x0
	// Bit mask of NDT field.
	DMA_CH_NDTR_NDT_Msk = 0x3ffff

	// CH.PAR: channel x peripheral address register
	// Position of PA field.
	DMA_CH_PAR_PA_Pos = 0x0
	// Bit mask of PA field.
	DMA_CH_PAR_PA_Msk = 0xffffffff

	// CH.M0AR: channel x memory address register
	// Position of MA field.
	DMA_CH_M0AR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA_CH_M0AR_MA_Msk = 0xffffffff

	// CH.M1AR: channel x memory address register
	// Position of MA field.
	DMA_CH_M1AR_MA_Pos = 0x0
	// Bit mask of MA field.
	DMA_CH_M1AR_MA_Msk = 0xffffffff
)

// Constants for DMAMUX1: Direct memory access Multiplexer
const (
	// CCR0: DMA Multiplexer Channel %s Control register
	// Position of SYNC_ID field.
	DMAMUX_CCR_SYNC_ID_Pos = 0x18
	// Bit mask of SYNC_ID field.
	DMAMUX_CCR_SYNC_ID_Msk = 0x1f000000
	// Position of NBREQ field.
	DMAMUX_CCR_NBREQ_Pos = 0x13
	// Bit mask of NBREQ field.
	DMAMUX_CCR_NBREQ_Msk = 0xf80000
	// Position of SPOL field.
	DMAMUX_CCR_SPOL_Pos = 0x11
	// Bit mask of SPOL field.
	DMAMUX_CCR_SPOL_Msk = 0x60000
	// No event, i.e. no synchronization nor detection
	DMAMUX_CCR_SPOL_NoEdge = 0x0
	// Rising edge
	DMAMUX_CCR_SPOL_RisingEdge = 0x1
	// Falling edge
	DMAMUX_CCR_SPOL_FallingEdge = 0x2
	// Rising and falling edges
	DMAMUX_CCR_SPOL_BothEdges = 0x3
	// Position of SE field.
	DMAMUX_CCR_SE_Pos = 0x10
	// Bit mask of SE field.
	DMAMUX_CCR_SE_Msk = 0x10000
	// Bit SE.
	DMAMUX_CCR_SE = 0x10000
	// Synchronization disabled
	DMAMUX_CCR_SE_Disabled = 0x0
	// Synchronization enabled
	DMAMUX_CCR_SE_Enabled = 0x1
	// Position of EGE field.
	DMAMUX_CCR_EGE_Pos = 0x9
	// Bit mask of EGE field.
	DMAMUX_CCR_EGE_Msk = 0x200
	// Bit EGE.
	DMAMUX_CCR_EGE = 0x200
	// Event generation disabled
	DMAMUX_CCR_EGE_Disabled = 0x0
	// Event generation enabled
	DMAMUX_CCR_EGE_Enabled = 0x1
	// Position of SOIE field.
	DMAMUX_CCR_SOIE_Pos = 0x8
	// Bit mask of SOIE field.
	DMAMUX_CCR_SOIE_Msk = 0x100
	// Bit SOIE.
	DMAMUX_CCR_SOIE = 0x100
	// Synchronization overrun interrupt disabled
	DMAMUX_CCR_SOIE_Disabled = 0x0
	// Synchronization overrun interrupt enabled
	DMAMUX_CCR_SOIE_Enabled = 0x1
	// Position of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Pos = 0x0
	// Bit mask of DMAREQ_ID field.
	DMAMUX_CCR_DMAREQ_ID_Msk = 0x7f

	// CSR: DMA Multiplexer Channel Status register
	// Position of SOF0 field.
	DMAMUX_CSR_SOF0_Pos = 0x1
	// Bit mask of SOF0 field.
	DMAMUX_CSR_SOF0_Msk = 0x2
	// Bit SOF0.
	DMAMUX_CSR_SOF0 = 0x2
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF0_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF0_SyncEvent = 0x1
	// Position of SOF1 field.
	DMAMUX_CSR_SOF1_Pos = 0x2
	// Bit mask of SOF1 field.
	DMAMUX_CSR_SOF1_Msk = 0x4
	// Bit SOF1.
	DMAMUX_CSR_SOF1 = 0x4
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF1_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF1_SyncEvent = 0x1
	// Position of SOF2 field.
	DMAMUX_CSR_SOF2_Pos = 0x3
	// Bit mask of SOF2 field.
	DMAMUX_CSR_SOF2_Msk = 0x8
	// Bit SOF2.
	DMAMUX_CSR_SOF2 = 0x8
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF2_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF2_SyncEvent = 0x1
	// Position of SOF3 field.
	DMAMUX_CSR_SOF3_Pos = 0x4
	// Bit mask of SOF3 field.
	DMAMUX_CSR_SOF3_Msk = 0x10
	// Bit SOF3.
	DMAMUX_CSR_SOF3 = 0x10
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF3_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF3_SyncEvent = 0x1
	// Position of SOF4 field.
	DMAMUX_CSR_SOF4_Pos = 0x5
	// Bit mask of SOF4 field.
	DMAMUX_CSR_SOF4_Msk = 0x20
	// Bit SOF4.
	DMAMUX_CSR_SOF4 = 0x20
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF4_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF4_SyncEvent = 0x1
	// Position of SOF5 field.
	DMAMUX_CSR_SOF5_Pos = 0x6
	// Bit mask of SOF5 field.
	DMAMUX_CSR_SOF5_Msk = 0x40
	// Bit SOF5.
	DMAMUX_CSR_SOF5 = 0x40
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF5_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF5_SyncEvent = 0x1
	// Position of SOF6 field.
	DMAMUX_CSR_SOF6_Pos = 0x7
	// Bit mask of SOF6 field.
	DMAMUX_CSR_SOF6_Msk = 0x80
	// Bit SOF6.
	DMAMUX_CSR_SOF6 = 0x80
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF6_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF6_SyncEvent = 0x1
	// Position of SOF7 field.
	DMAMUX_CSR_SOF7_Pos = 0x8
	// Bit mask of SOF7 field.
	DMAMUX_CSR_SOF7_Msk = 0x100
	// Bit SOF7.
	DMAMUX_CSR_SOF7 = 0x100
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF7_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF7_SyncEvent = 0x1
	// Position of SOF8 field.
	DMAMUX_CSR_SOF8_Pos = 0x9
	// Bit mask of SOF8 field.
	DMAMUX_CSR_SOF8_Msk = 0x200
	// Bit SOF8.
	DMAMUX_CSR_SOF8 = 0x200
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF8_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF8_SyncEvent = 0x1
	// Position of SOF9 field.
	DMAMUX_CSR_SOF9_Pos = 0xa
	// Bit mask of SOF9 field.
	DMAMUX_CSR_SOF9_Msk = 0x400
	// Bit SOF9.
	DMAMUX_CSR_SOF9 = 0x400
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF9_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF9_SyncEvent = 0x1
	// Position of SOF10 field.
	DMAMUX_CSR_SOF10_Pos = 0xb
	// Bit mask of SOF10 field.
	DMAMUX_CSR_SOF10_Msk = 0x800
	// Bit SOF10.
	DMAMUX_CSR_SOF10 = 0x800
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF10_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF10_SyncEvent = 0x1
	// Position of SOF11 field.
	DMAMUX_CSR_SOF11_Pos = 0xc
	// Bit mask of SOF11 field.
	DMAMUX_CSR_SOF11_Msk = 0x1000
	// Bit SOF11.
	DMAMUX_CSR_SOF11 = 0x1000
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF11_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF11_SyncEvent = 0x1
	// Position of SOF12 field.
	DMAMUX_CSR_SOF12_Pos = 0xd
	// Bit mask of SOF12 field.
	DMAMUX_CSR_SOF12_Msk = 0x2000
	// Bit SOF12.
	DMAMUX_CSR_SOF12 = 0x2000
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF12_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF12_SyncEvent = 0x1
	// Position of SOF13 field.
	DMAMUX_CSR_SOF13_Pos = 0xe
	// Bit mask of SOF13 field.
	DMAMUX_CSR_SOF13_Msk = 0x4000
	// Bit SOF13.
	DMAMUX_CSR_SOF13 = 0x4000
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF13_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF13_SyncEvent = 0x1
	// Position of SOF14 field.
	DMAMUX_CSR_SOF14_Pos = 0xf
	// Bit mask of SOF14 field.
	DMAMUX_CSR_SOF14_Msk = 0x8000
	// Bit SOF14.
	DMAMUX_CSR_SOF14 = 0x8000
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF14_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF14_SyncEvent = 0x1
	// Position of SOF15 field.
	DMAMUX_CSR_SOF15_Pos = 0x10
	// Bit mask of SOF15 field.
	DMAMUX_CSR_SOF15_Msk = 0x10000
	// Bit SOF15.
	DMAMUX_CSR_SOF15 = 0x10000
	// No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF15_NoSyncEvent = 0x0
	// Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
	DMAMUX_CSR_SOF15_SyncEvent = 0x1

	// CCFR: DMA Channel Clear Flag Register
	// Position of CSOF0 field.
	DMAMUX_CCFR_CSOF0_Pos = 0x1
	// Bit mask of CSOF0 field.
	DMAMUX_CCFR_CSOF0_Msk = 0x2
	// Bit CSOF0.
	DMAMUX_CCFR_CSOF0 = 0x2
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF0_Clear = 0x1
	// Position of CSOF1 field.
	DMAMUX_CCFR_CSOF1_Pos = 0x2
	// Bit mask of CSOF1 field.
	DMAMUX_CCFR_CSOF1_Msk = 0x4
	// Bit CSOF1.
	DMAMUX_CCFR_CSOF1 = 0x4
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF1_Clear = 0x1
	// Position of CSOF2 field.
	DMAMUX_CCFR_CSOF2_Pos = 0x3
	// Bit mask of CSOF2 field.
	DMAMUX_CCFR_CSOF2_Msk = 0x8
	// Bit CSOF2.
	DMAMUX_CCFR_CSOF2 = 0x8
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF2_Clear = 0x1
	// Position of CSOF3 field.
	DMAMUX_CCFR_CSOF3_Pos = 0x4
	// Bit mask of CSOF3 field.
	DMAMUX_CCFR_CSOF3_Msk = 0x10
	// Bit CSOF3.
	DMAMUX_CCFR_CSOF3 = 0x10
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF3_Clear = 0x1
	// Position of CSOF4 field.
	DMAMUX_CCFR_CSOF4_Pos = 0x5
	// Bit mask of CSOF4 field.
	DMAMUX_CCFR_CSOF4_Msk = 0x20
	// Bit CSOF4.
	DMAMUX_CCFR_CSOF4 = 0x20
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF4_Clear = 0x1
	// Position of CSOF5 field.
	DMAMUX_CCFR_CSOF5_Pos = 0x6
	// Bit mask of CSOF5 field.
	DMAMUX_CCFR_CSOF5_Msk = 0x40
	// Bit CSOF5.
	DMAMUX_CCFR_CSOF5 = 0x40
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF5_Clear = 0x1
	// Position of CSOF6 field.
	DMAMUX_CCFR_CSOF6_Pos = 0x7
	// Bit mask of CSOF6 field.
	DMAMUX_CCFR_CSOF6_Msk = 0x80
	// Bit CSOF6.
	DMAMUX_CCFR_CSOF6 = 0x80
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF6_Clear = 0x1
	// Position of CSOF7 field.
	DMAMUX_CCFR_CSOF7_Pos = 0x8
	// Bit mask of CSOF7 field.
	DMAMUX_CCFR_CSOF7_Msk = 0x100
	// Bit CSOF7.
	DMAMUX_CCFR_CSOF7 = 0x100
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF7_Clear = 0x1
	// Position of CSOF8 field.
	DMAMUX_CCFR_CSOF8_Pos = 0x9
	// Bit mask of CSOF8 field.
	DMAMUX_CCFR_CSOF8_Msk = 0x200
	// Bit CSOF8.
	DMAMUX_CCFR_CSOF8 = 0x200
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF8_Clear = 0x1
	// Position of CSOF9 field.
	DMAMUX_CCFR_CSOF9_Pos = 0xa
	// Bit mask of CSOF9 field.
	DMAMUX_CCFR_CSOF9_Msk = 0x400
	// Bit CSOF9.
	DMAMUX_CCFR_CSOF9 = 0x400
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF9_Clear = 0x1
	// Position of CSOF10 field.
	DMAMUX_CCFR_CSOF10_Pos = 0xb
	// Bit mask of CSOF10 field.
	DMAMUX_CCFR_CSOF10_Msk = 0x800
	// Bit CSOF10.
	DMAMUX_CCFR_CSOF10 = 0x800
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF10_Clear = 0x1
	// Position of CSOF11 field.
	DMAMUX_CCFR_CSOF11_Pos = 0xc
	// Bit mask of CSOF11 field.
	DMAMUX_CCFR_CSOF11_Msk = 0x1000
	// Bit CSOF11.
	DMAMUX_CCFR_CSOF11 = 0x1000
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF11_Clear = 0x1
	// Position of CSOF12 field.
	DMAMUX_CCFR_CSOF12_Pos = 0xd
	// Bit mask of CSOF12 field.
	DMAMUX_CCFR_CSOF12_Msk = 0x2000
	// Bit CSOF12.
	DMAMUX_CCFR_CSOF12 = 0x2000
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF12_Clear = 0x1
	// Position of CSOF13 field.
	DMAMUX_CCFR_CSOF13_Pos = 0xe
	// Bit mask of CSOF13 field.
	DMAMUX_CCFR_CSOF13_Msk = 0x4000
	// Bit CSOF13.
	DMAMUX_CCFR_CSOF13 = 0x4000
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF13_Clear = 0x1
	// Position of CSOF14 field.
	DMAMUX_CCFR_CSOF14_Pos = 0xf
	// Bit mask of CSOF14 field.
	DMAMUX_CCFR_CSOF14_Msk = 0x8000
	// Bit CSOF14.
	DMAMUX_CCFR_CSOF14 = 0x8000
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF14_Clear = 0x1
	// Position of CSOF15 field.
	DMAMUX_CCFR_CSOF15_Pos = 0x10
	// Bit mask of CSOF15 field.
	DMAMUX_CCFR_CSOF15_Msk = 0x10000
	// Bit CSOF15.
	DMAMUX_CCFR_CSOF15 = 0x10000
	// Clear synchronization flag
	DMAMUX_CCFR_CSOF15_Clear = 0x1

	// RGCR0: DMA Request Generator %s Control Register
	// Position of GNBREQ field.
	DMAMUX_RGCR_GNBREQ_Pos = 0x13
	// Bit mask of GNBREQ field.
	DMAMUX_RGCR_GNBREQ_Msk = 0xf80000
	// Position of GPOL field.
	DMAMUX_RGCR_GPOL_Pos = 0x11
	// Bit mask of GPOL field.
	DMAMUX_RGCR_GPOL_Msk = 0x60000
	// No event, i.e. no detection nor generation
	DMAMUX_RGCR_GPOL_NoEdge = 0x0
	// Rising edge
	DMAMUX_RGCR_GPOL_RisingEdge = 0x1
	// Falling edge
	DMAMUX_RGCR_GPOL_FallingEdge = 0x2
	// Rising and falling edges
	DMAMUX_RGCR_GPOL_BothEdges = 0x3
	// Position of GE field.
	DMAMUX_RGCR_GE_Pos = 0x10
	// Bit mask of GE field.
	DMAMUX_RGCR_GE_Msk = 0x10000
	// Bit GE.
	DMAMUX_RGCR_GE = 0x10000
	// DMA request generation disabled
	DMAMUX_RGCR_GE_Disabled = 0x0
	// DMA request enabled
	DMAMUX_RGCR_GE_Enabled = 0x1
	// Position of OIE field.
	DMAMUX_RGCR_OIE_Pos = 0x8
	// Bit mask of OIE field.
	DMAMUX_RGCR_OIE_Msk = 0x100
	// Bit OIE.
	DMAMUX_RGCR_OIE = 0x100
	// Trigger overrun interrupt disabled
	DMAMUX_RGCR_OIE_Disabled = 0x0
	// Trigger overrun interrupt enabled
	DMAMUX_RGCR_OIE_Enabled = 0x1
	// Position of SIG_ID field.
	DMAMUX_RGCR_SIG_ID_Pos = 0x0
	// Bit mask of SIG_ID field.
	DMAMUX_RGCR_SIG_ID_Msk = 0x1f

	// RGSR: DMA Request Generator Status Register
	// Position of OF0 field.
	DMAMUX_RGSR_OF0_Pos = 0x1
	// Bit mask of OF0 field.
	DMAMUX_RGSR_OF0_Msk = 0x2
	// Bit OF0.
	DMAMUX_RGSR_OF0 = 0x2
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF0_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF0_Trigger = 0x1
	// Position of OF1 field.
	DMAMUX_RGSR_OF1_Pos = 0x2
	// Bit mask of OF1 field.
	DMAMUX_RGSR_OF1_Msk = 0x4
	// Bit OF1.
	DMAMUX_RGSR_OF1 = 0x4
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF1_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF1_Trigger = 0x1
	// Position of OF2 field.
	DMAMUX_RGSR_OF2_Pos = 0x3
	// Bit mask of OF2 field.
	DMAMUX_RGSR_OF2_Msk = 0x8
	// Bit OF2.
	DMAMUX_RGSR_OF2 = 0x8
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF2_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF2_Trigger = 0x1
	// Position of OF3 field.
	DMAMUX_RGSR_OF3_Pos = 0x4
	// Bit mask of OF3 field.
	DMAMUX_RGSR_OF3_Msk = 0x10
	// Bit OF3.
	DMAMUX_RGSR_OF3 = 0x10
	// No new trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF3_NoTrigger = 0x0
	// New trigger event occured on DMA request generator channel x, before the request counter underrun
	DMAMUX_RGSR_OF3_Trigger = 0x1

	// RGCFR: DMA Request Generator Clear Flag Register
	// Position of COF0 field.
	DMAMUX_RGCFR_COF0_Pos = 0x1
	// Bit mask of COF0 field.
	DMAMUX_RGCFR_COF0_Msk = 0x2
	// Bit COF0.
	DMAMUX_RGCFR_COF0 = 0x2
	// Clear overrun flag
	DMAMUX_RGCFR_COF0_Clear = 0x1
	// Position of COF1 field.
	DMAMUX_RGCFR_COF1_Pos = 0x2
	// Bit mask of COF1 field.
	DMAMUX_RGCFR_COF1_Msk = 0x4
	// Bit COF1.
	DMAMUX_RGCFR_COF1 = 0x4
	// Clear overrun flag
	DMAMUX_RGCFR_COF1_Clear = 0x1
	// Position of COF2 field.
	DMAMUX_RGCFR_COF2_Pos = 0x3
	// Bit mask of COF2 field.
	DMAMUX_RGCFR_COF2_Msk = 0x8
	// Bit COF2.
	DMAMUX_RGCFR_COF2 = 0x8
	// Clear overrun flag
	DMAMUX_RGCFR_COF2_Clear = 0x1
	// Position of COF3 field.
	DMAMUX_RGCFR_COF3_Pos = 0x4
	// Bit mask of COF3 field.
	DMAMUX_RGCFR_COF3_Msk = 0x10
	// Bit COF3.
	DMAMUX_RGCFR_COF3 = 0x10
	// Clear overrun flag
	DMAMUX_RGCFR_COF3_Clear = 0x1
)

// Constants for EXTI: External interrupt/event controller
const (
	// RTSR1: EXTI rising trigger selection register
	// Position of RT0 field.
	EXTI_RTSR1_RT0_Pos = 0x0
	// Bit mask of RT0 field.
	EXTI_RTSR1_RT0_Msk = 0x1
	// Bit RT0.
	EXTI_RTSR1_RT0 = 0x1
	// Position of RT1 field.
	EXTI_RTSR1_RT1_Pos = 0x1
	// Bit mask of RT1 field.
	EXTI_RTSR1_RT1_Msk = 0x2
	// Bit RT1.
	EXTI_RTSR1_RT1 = 0x2
	// Position of RT2 field.
	EXTI_RTSR1_RT2_Pos = 0x2
	// Bit mask of RT2 field.
	EXTI_RTSR1_RT2_Msk = 0x4
	// Bit RT2.
	EXTI_RTSR1_RT2 = 0x4
	// Position of RT3 field.
	EXTI_RTSR1_RT3_Pos = 0x3
	// Bit mask of RT3 field.
	EXTI_RTSR1_RT3_Msk = 0x8
	// Bit RT3.
	EXTI_RTSR1_RT3 = 0x8
	// Position of RT4 field.
	EXTI_RTSR1_RT4_Pos = 0x4
	// Bit mask of RT4 field.
	EXTI_RTSR1_RT4_Msk = 0x10
	// Bit RT4.
	EXTI_RTSR1_RT4 = 0x10
	// Position of RT5 field.
	EXTI_RTSR1_RT5_Pos = 0x5
	// Bit mask of RT5 field.
	EXTI_RTSR1_RT5_Msk = 0x20
	// Bit RT5.
	EXTI_RTSR1_RT5 = 0x20
	// Position of RT6 field.
	EXTI_RTSR1_RT6_Pos = 0x6
	// Bit mask of RT6 field.
	EXTI_RTSR1_RT6_Msk = 0x40
	// Bit RT6.
	EXTI_RTSR1_RT6 = 0x40
	// Position of RT7 field.
	EXTI_RTSR1_RT7_Pos = 0x7
	// Bit mask of RT7 field.
	EXTI_RTSR1_RT7_Msk = 0x80
	// Bit RT7.
	EXTI_RTSR1_RT7 = 0x80
	// Position of RT8 field.
	EXTI_RTSR1_RT8_Pos = 0x8
	// Bit mask of RT8 field.
	EXTI_RTSR1_RT8_Msk = 0x100
	// Bit RT8.
	EXTI_RTSR1_RT8 = 0x100
	// Position of RT9 field.
	EXTI_RTSR1_RT9_Pos = 0x9
	// Bit mask of RT9 field.
	EXTI_RTSR1_RT9_Msk = 0x200
	// Bit RT9.
	EXTI_RTSR1_RT9 = 0x200
	// Position of RT10 field.
	EXTI_RTSR1_RT10_Pos = 0xa
	// Bit mask of RT10 field.
	EXTI_RTSR1_RT10_Msk = 0x400
	// Bit RT10.
	EXTI_RTSR1_RT10 = 0x400
	// Position of RT11 field.
	EXTI_RTSR1_RT11_Pos = 0xb
	// Bit mask of RT11 field.
	EXTI_RTSR1_RT11_Msk = 0x800
	// Bit RT11.
	EXTI_RTSR1_RT11 = 0x800
	// Position of RT12 field.
	EXTI_RTSR1_RT12_Pos = 0xc
	// Bit mask of RT12 field.
	EXTI_RTSR1_RT12_Msk = 0x1000
	// Bit RT12.
	EXTI_RTSR1_RT12 = 0x1000
	// Position of RT13 field.
	EXTI_RTSR1_RT13_Pos = 0xd
	// Bit mask of RT13 field.
	EXTI_RTSR1_RT13_Msk = 0x2000
	// Bit RT13.
	EXTI_RTSR1_RT13 = 0x2000
	// Position of RT14 field.
	EXTI_RTSR1_RT14_Pos = 0xe
	// Bit mask of RT14 field.
	EXTI_RTSR1_RT14_Msk = 0x4000
	// Bit RT14.
	EXTI_RTSR1_RT14 = 0x4000
	// Position of RT15 field.
	EXTI_RTSR1_RT15_Pos = 0xf
	// Bit mask of RT15 field.
	EXTI_RTSR1_RT15_Msk = 0x8000
	// Bit RT15.
	EXTI_RTSR1_RT15 = 0x8000
	// Position of RT16 field.
	EXTI_RTSR1_RT16_Pos = 0x10
	// Bit mask of RT16 field.
	EXTI_RTSR1_RT16_Msk = 0x10000
	// Bit RT16.
	EXTI_RTSR1_RT16 = 0x10000
	// Position of RT21 field.
	EXTI_RTSR1_RT21_Pos = 0x15
	// Bit mask of RT21 field.
	EXTI_RTSR1_RT21_Msk = 0x200000
	// Bit RT21.
	EXTI_RTSR1_RT21 = 0x200000
	// Position of RT22 field.
	EXTI_RTSR1_RT22_Pos = 0x16
	// Bit mask of RT22 field.
	EXTI_RTSR1_RT22_Msk = 0x400000
	// Bit RT22.
	EXTI_RTSR1_RT22 = 0x400000

	// FTSR1: EXTI falling trigger selection register
	// Position of FT0 field.
	EXTI_FTSR1_FT0_Pos = 0x0
	// Bit mask of FT0 field.
	EXTI_FTSR1_FT0_Msk = 0x1
	// Bit FT0.
	EXTI_FTSR1_FT0 = 0x1
	// Position of FT1 field.
	EXTI_FTSR1_FT1_Pos = 0x1
	// Bit mask of FT1 field.
	EXTI_FTSR1_FT1_Msk = 0x2
	// Bit FT1.
	EXTI_FTSR1_FT1 = 0x2
	// Position of FT2 field.
	EXTI_FTSR1_FT2_Pos = 0x2
	// Bit mask of FT2 field.
	EXTI_FTSR1_FT2_Msk = 0x4
	// Bit FT2.
	EXTI_FTSR1_FT2 = 0x4
	// Position of FT3 field.
	EXTI_FTSR1_FT3_Pos = 0x3
	// Bit mask of FT3 field.
	EXTI_FTSR1_FT3_Msk = 0x8
	// Bit FT3.
	EXTI_FTSR1_FT3 = 0x8
	// Position of FT4 field.
	EXTI_FTSR1_FT4_Pos = 0x4
	// Bit mask of FT4 field.
	EXTI_FTSR1_FT4_Msk = 0x10
	// Bit FT4.
	EXTI_FTSR1_FT4 = 0x10
	// Position of FT5 field.
	EXTI_FTSR1_FT5_Pos = 0x5
	// Bit mask of FT5 field.
	EXTI_FTSR1_FT5_Msk = 0x20
	// Bit FT5.
	EXTI_FTSR1_FT5 = 0x20
	// Position of FT6 field.
	EXTI_FTSR1_FT6_Pos = 0x6
	// Bit mask of FT6 field.
	EXTI_FTSR1_FT6_Msk = 0x40
	// Bit FT6.
	EXTI_FTSR1_FT6 = 0x40
	// Position of FT7 field.
	EXTI_FTSR1_FT7_Pos = 0x7
	// Bit mask of FT7 field.
	EXTI_FTSR1_FT7_Msk = 0x80
	// Bit FT7.
	EXTI_FTSR1_FT7 = 0x80
	// Position of FT8 field.
	EXTI_FTSR1_FT8_Pos = 0x8
	// Bit mask of FT8 field.
	EXTI_FTSR1_FT8_Msk = 0x100
	// Bit FT8.
	EXTI_FTSR1_FT8 = 0x100
	// Position of FT9 field.
	EXTI_FTSR1_FT9_Pos = 0x9
	// Bit mask of FT9 field.
	EXTI_FTSR1_FT9_Msk = 0x200
	// Bit FT9.
	EXTI_FTSR1_FT9 = 0x200
	// Position of FT10 field.
	EXTI_FTSR1_FT10_Pos = 0xa
	// Bit mask of FT10 field.
	EXTI_FTSR1_FT10_Msk = 0x400
	// Bit FT10.
	EXTI_FTSR1_FT10 = 0x400
	// Position of FT11 field.
	EXTI_FTSR1_FT11_Pos = 0xb
	// Bit mask of FT11 field.
	EXTI_FTSR1_FT11_Msk = 0x800
	// Bit FT11.
	EXTI_FTSR1_FT11 = 0x800
	// Position of FT12 field.
	EXTI_FTSR1_FT12_Pos = 0xc
	// Bit mask of FT12 field.
	EXTI_FTSR1_FT12_Msk = 0x1000
	// Bit FT12.
	EXTI_FTSR1_FT12 = 0x1000
	// Position of FT13 field.
	EXTI_FTSR1_FT13_Pos = 0xd
	// Bit mask of FT13 field.
	EXTI_FTSR1_FT13_Msk = 0x2000
	// Bit FT13.
	EXTI_FTSR1_FT13 = 0x2000
	// Position of FT14 field.
	EXTI_FTSR1_FT14_Pos = 0xe
	// Bit mask of FT14 field.
	EXTI_FTSR1_FT14_Msk = 0x4000
	// Bit FT14.
	EXTI_FTSR1_FT14 = 0x4000
	// Position of FT15 field.
	EXTI_FTSR1_FT15_Pos = 0xf
	// Bit mask of FT15 field.
	EXTI_FTSR1_FT15_Msk = 0x8000
	// Bit FT15.
	EXTI_FTSR1_FT15 = 0x8000
	// Position of FT16 field.
	EXTI_FTSR1_FT16_Pos = 0x10
	// Bit mask of FT16 field.
	EXTI_FTSR1_FT16_Msk = 0x10000
	// Bit FT16.
	EXTI_FTSR1_FT16 = 0x10000
	// Position of FT21 field.
	EXTI_FTSR1_FT21_Pos = 0x15
	// Bit mask of FT21 field.
	EXTI_FTSR1_FT21_Msk = 0x200000
	// Bit FT21.
	EXTI_FTSR1_FT21 = 0x200000
	// Position of FT22 field.
	EXTI_FTSR1_FT22_Pos = 0x16
	// Bit mask of FT22 field.
	EXTI_FTSR1_FT22_Msk = 0x400000
	// Bit FT22.
	EXTI_FTSR1_FT22 = 0x400000

	// SWIER1: EXTI software interrupt event register
	// Position of SWI0 field.
	EXTI_SWIER1_SWI0_Pos = 0x0
	// Bit mask of SWI0 field.
	EXTI_SWIER1_SWI0_Msk = 0x1
	// Bit SWI0.
	EXTI_SWIER1_SWI0 = 0x1
	// Position of SWI1 field.
	EXTI_SWIER1_SWI1_Pos = 0x1
	// Bit mask of SWI1 field.
	EXTI_SWIER1_SWI1_Msk = 0x2
	// Bit SWI1.
	EXTI_SWIER1_SWI1 = 0x2
	// Position of SWI2 field.
	EXTI_SWIER1_SWI2_Pos = 0x2
	// Bit mask of SWI2 field.
	EXTI_SWIER1_SWI2_Msk = 0x4
	// Bit SWI2.
	EXTI_SWIER1_SWI2 = 0x4
	// Position of SWI3 field.
	EXTI_SWIER1_SWI3_Pos = 0x3
	// Bit mask of SWI3 field.
	EXTI_SWIER1_SWI3_Msk = 0x8
	// Bit SWI3.
	EXTI_SWIER1_SWI3 = 0x8
	// Position of SWI4 field.
	EXTI_SWIER1_SWI4_Pos = 0x4
	// Bit mask of SWI4 field.
	EXTI_SWIER1_SWI4_Msk = 0x10
	// Bit SWI4.
	EXTI_SWIER1_SWI4 = 0x10
	// Position of SWI5 field.
	EXTI_SWIER1_SWI5_Pos = 0x5
	// Bit mask of SWI5 field.
	EXTI_SWIER1_SWI5_Msk = 0x20
	// Bit SWI5.
	EXTI_SWIER1_SWI5 = 0x20
	// Position of SWI6 field.
	EXTI_SWIER1_SWI6_Pos = 0x6
	// Bit mask of SWI6 field.
	EXTI_SWIER1_SWI6_Msk = 0x40
	// Bit SWI6.
	EXTI_SWIER1_SWI6 = 0x40
	// Position of SWI7 field.
	EXTI_SWIER1_SWI7_Pos = 0x7
	// Bit mask of SWI7 field.
	EXTI_SWIER1_SWI7_Msk = 0x80
	// Bit SWI7.
	EXTI_SWIER1_SWI7 = 0x80
	// Position of SWI8 field.
	EXTI_SWIER1_SWI8_Pos = 0x8
	// Bit mask of SWI8 field.
	EXTI_SWIER1_SWI8_Msk = 0x100
	// Bit SWI8.
	EXTI_SWIER1_SWI8 = 0x100
	// Position of SWI9 field.
	EXTI_SWIER1_SWI9_Pos = 0x9
	// Bit mask of SWI9 field.
	EXTI_SWIER1_SWI9_Msk = 0x200
	// Bit SWI9.
	EXTI_SWIER1_SWI9 = 0x200
	// Position of SWI10 field.
	EXTI_SWIER1_SWI10_Pos = 0xa
	// Bit mask of SWI10 field.
	EXTI_SWIER1_SWI10_Msk = 0x400
	// Bit SWI10.
	EXTI_SWIER1_SWI10 = 0x400
	// Position of SWI11 field.
	EXTI_SWIER1_SWI11_Pos = 0xb
	// Bit mask of SWI11 field.
	EXTI_SWIER1_SWI11_Msk = 0x800
	// Bit SWI11.
	EXTI_SWIER1_SWI11 = 0x800
	// Position of SWI12 field.
	EXTI_SWIER1_SWI12_Pos = 0xc
	// Bit mask of SWI12 field.
	EXTI_SWIER1_SWI12_Msk = 0x1000
	// Bit SWI12.
	EXTI_SWIER1_SWI12 = 0x1000
	// Position of SWI13 field.
	EXTI_SWIER1_SWI13_Pos = 0xd
	// Bit mask of SWI13 field.
	EXTI_SWIER1_SWI13_Msk = 0x2000
	// Bit SWI13.
	EXTI_SWIER1_SWI13 = 0x2000
	// Position of SWI14 field.
	EXTI_SWIER1_SWI14_Pos = 0xe
	// Bit mask of SWI14 field.
	EXTI_SWIER1_SWI14_Msk = 0x4000
	// Bit SWI14.
	EXTI_SWIER1_SWI14 = 0x4000
	// Position of SWI15 field.
	EXTI_SWIER1_SWI15_Pos = 0xf
	// Bit mask of SWI15 field.
	EXTI_SWIER1_SWI15_Msk = 0x8000
	// Bit SWI15.
	EXTI_SWIER1_SWI15 = 0x8000
	// Position of SWI16 field.
	EXTI_SWIER1_SWI16_Pos = 0x10
	// Bit mask of SWI16 field.
	EXTI_SWIER1_SWI16_Msk = 0x10000
	// Bit SWI16.
	EXTI_SWIER1_SWI16 = 0x10000
	// Position of SWI21 field.
	EXTI_SWIER1_SWI21_Pos = 0x15
	// Bit mask of SWI21 field.
	EXTI_SWIER1_SWI21_Msk = 0x200000
	// Bit SWI21.
	EXTI_SWIER1_SWI21 = 0x200000
	// Position of SWI22 field.
	EXTI_SWIER1_SWI22_Pos = 0x16
	// Bit mask of SWI22 field.
	EXTI_SWIER1_SWI22_Msk = 0x400000
	// Bit SWI22.
	EXTI_SWIER1_SWI22 = 0x400000

	// RPR1: EXTI rising edge pending register
	// Position of RPIF0 field.
	EXTI_RPR1_RPIF0_Pos = 0x0
	// Bit mask of RPIF0 field.
	EXTI_RPR1_RPIF0_Msk = 0x1
	// Bit RPIF0.
	EXTI_RPR1_RPIF0 = 0x1
	// Position of RPIF1 field.
	EXTI_RPR1_RPIF1_Pos = 0x1
	// Bit mask of RPIF1 field.
	EXTI_RPR1_RPIF1_Msk = 0x2
	// Bit RPIF1.
	EXTI_RPR1_RPIF1 = 0x2
	// Position of RPIF2 field.
	EXTI_RPR1_RPIF2_Pos = 0x2
	// Bit mask of RPIF2 field.
	EXTI_RPR1_RPIF2_Msk = 0x4
	// Bit RPIF2.
	EXTI_RPR1_RPIF2 = 0x4
	// Position of RPIF3 field.
	EXTI_RPR1_RPIF3_Pos = 0x3
	// Bit mask of RPIF3 field.
	EXTI_RPR1_RPIF3_Msk = 0x8
	// Bit RPIF3.
	EXTI_RPR1_RPIF3 = 0x8
	// Position of RPIF4 field.
	EXTI_RPR1_RPIF4_Pos = 0x4
	// Bit mask of RPIF4 field.
	EXTI_RPR1_RPIF4_Msk = 0x10
	// Bit RPIF4.
	EXTI_RPR1_RPIF4 = 0x10
	// Position of RPIF5 field.
	EXTI_RPR1_RPIF5_Pos = 0x5
	// Bit mask of RPIF5 field.
	EXTI_RPR1_RPIF5_Msk = 0x20
	// Bit RPIF5.
	EXTI_RPR1_RPIF5 = 0x20
	// Position of RPIF6 field.
	EXTI_RPR1_RPIF6_Pos = 0x6
	// Bit mask of RPIF6 field.
	EXTI_RPR1_RPIF6_Msk = 0x40
	// Bit RPIF6.
	EXTI_RPR1_RPIF6 = 0x40
	// Position of RPIF7 field.
	EXTI_RPR1_RPIF7_Pos = 0x7
	// Bit mask of RPIF7 field.
	EXTI_RPR1_RPIF7_Msk = 0x80
	// Bit RPIF7.
	EXTI_RPR1_RPIF7 = 0x80
	// Position of RPIF8 field.
	EXTI_RPR1_RPIF8_Pos = 0x8
	// Bit mask of RPIF8 field.
	EXTI_RPR1_RPIF8_Msk = 0x100
	// Bit RPIF8.
	EXTI_RPR1_RPIF8 = 0x100
	// Position of RPIF9 field.
	EXTI_RPR1_RPIF9_Pos = 0x9
	// Bit mask of RPIF9 field.
	EXTI_RPR1_RPIF9_Msk = 0x200
	// Bit RPIF9.
	EXTI_RPR1_RPIF9 = 0x200
	// Position of RPIF10 field.
	EXTI_RPR1_RPIF10_Pos = 0xa
	// Bit mask of RPIF10 field.
	EXTI_RPR1_RPIF10_Msk = 0x400
	// Bit RPIF10.
	EXTI_RPR1_RPIF10 = 0x400
	// Position of RPIF11 field.
	EXTI_RPR1_RPIF11_Pos = 0xb
	// Bit mask of RPIF11 field.
	EXTI_RPR1_RPIF11_Msk = 0x800
	// Bit RPIF11.
	EXTI_RPR1_RPIF11 = 0x800
	// Position of RPIF12 field.
	EXTI_RPR1_RPIF12_Pos = 0xc
	// Bit mask of RPIF12 field.
	EXTI_RPR1_RPIF12_Msk = 0x1000
	// Bit RPIF12.
	EXTI_RPR1_RPIF12 = 0x1000
	// Position of RPIF13 field.
	EXTI_RPR1_RPIF13_Pos = 0xd
	// Bit mask of RPIF13 field.
	EXTI_RPR1_RPIF13_Msk = 0x2000
	// Bit RPIF13.
	EXTI_RPR1_RPIF13 = 0x2000
	// Position of RPIF14 field.
	EXTI_RPR1_RPIF14_Pos = 0xe
	// Bit mask of RPIF14 field.
	EXTI_RPR1_RPIF14_Msk = 0x4000
	// Bit RPIF14.
	EXTI_RPR1_RPIF14 = 0x4000
	// Position of RPIF15 field.
	EXTI_RPR1_RPIF15_Pos = 0xf
	// Bit mask of RPIF15 field.
	EXTI_RPR1_RPIF15_Msk = 0x8000
	// Bit RPIF15.
	EXTI_RPR1_RPIF15 = 0x8000
	// Position of RPIF16 field.
	EXTI_RPR1_RPIF16_Pos = 0x10
	// Bit mask of RPIF16 field.
	EXTI_RPR1_RPIF16_Msk = 0x10000
	// Bit RPIF16.
	EXTI_RPR1_RPIF16 = 0x10000
	// Position of RPIF21 field.
	EXTI_RPR1_RPIF21_Pos = 0x15
	// Bit mask of RPIF21 field.
	EXTI_RPR1_RPIF21_Msk = 0x200000
	// Bit RPIF21.
	EXTI_RPR1_RPIF21 = 0x200000
	// Position of RPIF22 field.
	EXTI_RPR1_RPIF22_Pos = 0x16
	// Bit mask of RPIF22 field.
	EXTI_RPR1_RPIF22_Msk = 0x400000
	// Bit RPIF22.
	EXTI_RPR1_RPIF22 = 0x400000

	// FPR1: EXTI falling edge pending register
	// Position of FPIF0 field.
	EXTI_FPR1_FPIF0_Pos = 0x0
	// Bit mask of FPIF0 field.
	EXTI_FPR1_FPIF0_Msk = 0x1
	// Bit FPIF0.
	EXTI_FPR1_FPIF0 = 0x1
	// Position of FPIF1 field.
	EXTI_FPR1_FPIF1_Pos = 0x1
	// Bit mask of FPIF1 field.
	EXTI_FPR1_FPIF1_Msk = 0x2
	// Bit FPIF1.
	EXTI_FPR1_FPIF1 = 0x2
	// Position of FPIF2 field.
	EXTI_FPR1_FPIF2_Pos = 0x2
	// Bit mask of FPIF2 field.
	EXTI_FPR1_FPIF2_Msk = 0x4
	// Bit FPIF2.
	EXTI_FPR1_FPIF2 = 0x4
	// Position of FPIF3 field.
	EXTI_FPR1_FPIF3_Pos = 0x3
	// Bit mask of FPIF3 field.
	EXTI_FPR1_FPIF3_Msk = 0x8
	// Bit FPIF3.
	EXTI_FPR1_FPIF3 = 0x8
	// Position of FPIF4 field.
	EXTI_FPR1_FPIF4_Pos = 0x4
	// Bit mask of FPIF4 field.
	EXTI_FPR1_FPIF4_Msk = 0x10
	// Bit FPIF4.
	EXTI_FPR1_FPIF4 = 0x10
	// Position of FPIF5 field.
	EXTI_FPR1_FPIF5_Pos = 0x5
	// Bit mask of FPIF5 field.
	EXTI_FPR1_FPIF5_Msk = 0x20
	// Bit FPIF5.
	EXTI_FPR1_FPIF5 = 0x20
	// Position of FPIF6 field.
	EXTI_FPR1_FPIF6_Pos = 0x6
	// Bit mask of FPIF6 field.
	EXTI_FPR1_FPIF6_Msk = 0x40
	// Bit FPIF6.
	EXTI_FPR1_FPIF6 = 0x40
	// Position of FPIF7 field.
	EXTI_FPR1_FPIF7_Pos = 0x7
	// Bit mask of FPIF7 field.
	EXTI_FPR1_FPIF7_Msk = 0x80
	// Bit FPIF7.
	EXTI_FPR1_FPIF7 = 0x80
	// Position of FPIF8 field.
	EXTI_FPR1_FPIF8_Pos = 0x8
	// Bit mask of FPIF8 field.
	EXTI_FPR1_FPIF8_Msk = 0x100
	// Bit FPIF8.
	EXTI_FPR1_FPIF8 = 0x100
	// Position of FPIF9 field.
	EXTI_FPR1_FPIF9_Pos = 0x9
	// Bit mask of FPIF9 field.
	EXTI_FPR1_FPIF9_Msk = 0x200
	// Bit FPIF9.
	EXTI_FPR1_FPIF9 = 0x200
	// Position of FPIF10 field.
	EXTI_FPR1_FPIF10_Pos = 0xa
	// Bit mask of FPIF10 field.
	EXTI_FPR1_FPIF10_Msk = 0x400
	// Bit FPIF10.
	EXTI_FPR1_FPIF10 = 0x400
	// Position of FPIF11 field.
	EXTI_FPR1_FPIF11_Pos = 0xb
	// Bit mask of FPIF11 field.
	EXTI_FPR1_FPIF11_Msk = 0x800
	// Bit FPIF11.
	EXTI_FPR1_FPIF11 = 0x800
	// Position of FPIF12 field.
	EXTI_FPR1_FPIF12_Pos = 0xc
	// Bit mask of FPIF12 field.
	EXTI_FPR1_FPIF12_Msk = 0x1000
	// Bit FPIF12.
	EXTI_FPR1_FPIF12 = 0x1000
	// Position of FPIF13 field.
	EXTI_FPR1_FPIF13_Pos = 0xd
	// Bit mask of FPIF13 field.
	EXTI_FPR1_FPIF13_Msk = 0x2000
	// Bit FPIF13.
	EXTI_FPR1_FPIF13 = 0x2000
	// Position of FPIF14 field.
	EXTI_FPR1_FPIF14_Pos = 0xe
	// Bit mask of FPIF14 field.
	EXTI_FPR1_FPIF14_Msk = 0x4000
	// Bit FPIF14.
	EXTI_FPR1_FPIF14 = 0x4000
	// Position of FPIF15 field.
	EXTI_FPR1_FPIF15_Pos = 0xf
	// Bit mask of FPIF15 field.
	EXTI_FPR1_FPIF15_Msk = 0x8000
	// Bit FPIF15.
	EXTI_FPR1_FPIF15 = 0x8000
	// Position of FPIF16 field.
	EXTI_FPR1_FPIF16_Pos = 0x10
	// Bit mask of FPIF16 field.
	EXTI_FPR1_FPIF16_Msk = 0x10000
	// Bit FPIF16.
	EXTI_FPR1_FPIF16 = 0x10000
	// Position of FPIF21 field.
	EXTI_FPR1_FPIF21_Pos = 0x15
	// Bit mask of FPIF21 field.
	EXTI_FPR1_FPIF21_Msk = 0x200000
	// Bit FPIF21.
	EXTI_FPR1_FPIF21 = 0x200000
	// Position of FPIF22 field.
	EXTI_FPR1_FPIF22_Pos = 0x16
	// Bit mask of FPIF22 field.
	EXTI_FPR1_FPIF22_Msk = 0x400000
	// Bit FPIF22.
	EXTI_FPR1_FPIF22 = 0x400000

	// SECCFGR1: EXTI security configuration register
	// Position of SEC0 field.
	EXTI_SECCFGR1_SEC0_Pos = 0x0
	// Bit mask of SEC0 field.
	EXTI_SECCFGR1_SEC0_Msk = 0x1
	// Bit SEC0.
	EXTI_SECCFGR1_SEC0 = 0x1
	// Position of SEC1 field.
	EXTI_SECCFGR1_SEC1_Pos = 0x1
	// Bit mask of SEC1 field.
	EXTI_SECCFGR1_SEC1_Msk = 0x2
	// Bit SEC1.
	EXTI_SECCFGR1_SEC1 = 0x2
	// Position of SEC2 field.
	EXTI_SECCFGR1_SEC2_Pos = 0x2
	// Bit mask of SEC2 field.
	EXTI_SECCFGR1_SEC2_Msk = 0x4
	// Bit SEC2.
	EXTI_SECCFGR1_SEC2 = 0x4
	// Position of SEC3 field.
	EXTI_SECCFGR1_SEC3_Pos = 0x3
	// Bit mask of SEC3 field.
	EXTI_SECCFGR1_SEC3_Msk = 0x8
	// Bit SEC3.
	EXTI_SECCFGR1_SEC3 = 0x8
	// Position of SEC4 field.
	EXTI_SECCFGR1_SEC4_Pos = 0x4
	// Bit mask of SEC4 field.
	EXTI_SECCFGR1_SEC4_Msk = 0x10
	// Bit SEC4.
	EXTI_SECCFGR1_SEC4 = 0x10
	// Position of SEC5 field.
	EXTI_SECCFGR1_SEC5_Pos = 0x5
	// Bit mask of SEC5 field.
	EXTI_SECCFGR1_SEC5_Msk = 0x20
	// Bit SEC5.
	EXTI_SECCFGR1_SEC5 = 0x20
	// Position of SEC6 field.
	EXTI_SECCFGR1_SEC6_Pos = 0x6
	// Bit mask of SEC6 field.
	EXTI_SECCFGR1_SEC6_Msk = 0x40
	// Bit SEC6.
	EXTI_SECCFGR1_SEC6 = 0x40
	// Position of SEC7 field.
	EXTI_SECCFGR1_SEC7_Pos = 0x7
	// Bit mask of SEC7 field.
	EXTI_SECCFGR1_SEC7_Msk = 0x80
	// Bit SEC7.
	EXTI_SECCFGR1_SEC7 = 0x80
	// Position of SEC8 field.
	EXTI_SECCFGR1_SEC8_Pos = 0x8
	// Bit mask of SEC8 field.
	EXTI_SECCFGR1_SEC8_Msk = 0x100
	// Bit SEC8.
	EXTI_SECCFGR1_SEC8 = 0x100
	// Position of SEC9 field.
	EXTI_SECCFGR1_SEC9_Pos = 0x9
	// Bit mask of SEC9 field.
	EXTI_SECCFGR1_SEC9_Msk = 0x200
	// Bit SEC9.
	EXTI_SECCFGR1_SEC9 = 0x200
	// Position of SEC10 field.
	EXTI_SECCFGR1_SEC10_Pos = 0xa
	// Bit mask of SEC10 field.
	EXTI_SECCFGR1_SEC10_Msk = 0x400
	// Bit SEC10.
	EXTI_SECCFGR1_SEC10 = 0x400
	// Position of SEC11 field.
	EXTI_SECCFGR1_SEC11_Pos = 0xb
	// Bit mask of SEC11 field.
	EXTI_SECCFGR1_SEC11_Msk = 0x800
	// Bit SEC11.
	EXTI_SECCFGR1_SEC11 = 0x800
	// Position of SEC12 field.
	EXTI_SECCFGR1_SEC12_Pos = 0xc
	// Bit mask of SEC12 field.
	EXTI_SECCFGR1_SEC12_Msk = 0x1000
	// Bit SEC12.
	EXTI_SECCFGR1_SEC12 = 0x1000
	// Position of SEC13 field.
	EXTI_SECCFGR1_SEC13_Pos = 0xd
	// Bit mask of SEC13 field.
	EXTI_SECCFGR1_SEC13_Msk = 0x2000
	// Bit SEC13.
	EXTI_SECCFGR1_SEC13 = 0x2000
	// Position of SEC14 field.
	EXTI_SECCFGR1_SEC14_Pos = 0xe
	// Bit mask of SEC14 field.
	EXTI_SECCFGR1_SEC14_Msk = 0x4000
	// Bit SEC14.
	EXTI_SECCFGR1_SEC14 = 0x4000
	// Position of SEC15 field.
	EXTI_SECCFGR1_SEC15_Pos = 0xf
	// Bit mask of SEC15 field.
	EXTI_SECCFGR1_SEC15_Msk = 0x8000
	// Bit SEC15.
	EXTI_SECCFGR1_SEC15 = 0x8000
	// Position of SEC16 field.
	EXTI_SECCFGR1_SEC16_Pos = 0x10
	// Bit mask of SEC16 field.
	EXTI_SECCFGR1_SEC16_Msk = 0x10000
	// Bit SEC16.
	EXTI_SECCFGR1_SEC16 = 0x10000
	// Position of SEC17 field.
	EXTI_SECCFGR1_SEC17_Pos = 0x11
	// Bit mask of SEC17 field.
	EXTI_SECCFGR1_SEC17_Msk = 0x20000
	// Bit SEC17.
	EXTI_SECCFGR1_SEC17 = 0x20000
	// Position of SEC18 field.
	EXTI_SECCFGR1_SEC18_Pos = 0x12
	// Bit mask of SEC18 field.
	EXTI_SECCFGR1_SEC18_Msk = 0x40000
	// Bit SEC18.
	EXTI_SECCFGR1_SEC18 = 0x40000
	// Position of SEC19 field.
	EXTI_SECCFGR1_SEC19_Pos = 0x13
	// Bit mask of SEC19 field.
	EXTI_SECCFGR1_SEC19_Msk = 0x80000
	// Bit SEC19.
	EXTI_SECCFGR1_SEC19 = 0x80000
	// Position of SEC20 field.
	EXTI_SECCFGR1_SEC20_Pos = 0x14
	// Bit mask of SEC20 field.
	EXTI_SECCFGR1_SEC20_Msk = 0x100000
	// Bit SEC20.
	EXTI_SECCFGR1_SEC20 = 0x100000
	// Position of SEC21 field.
	EXTI_SECCFGR1_SEC21_Pos = 0x15
	// Bit mask of SEC21 field.
	EXTI_SECCFGR1_SEC21_Msk = 0x200000
	// Bit SEC21.
	EXTI_SECCFGR1_SEC21 = 0x200000
	// Position of SEC22 field.
	EXTI_SECCFGR1_SEC22_Pos = 0x16
	// Bit mask of SEC22 field.
	EXTI_SECCFGR1_SEC22_Msk = 0x400000
	// Bit SEC22.
	EXTI_SECCFGR1_SEC22 = 0x400000
	// Position of SEC23 field.
	EXTI_SECCFGR1_SEC23_Pos = 0x17
	// Bit mask of SEC23 field.
	EXTI_SECCFGR1_SEC23_Msk = 0x800000
	// Bit SEC23.
	EXTI_SECCFGR1_SEC23 = 0x800000
	// Position of SEC24 field.
	EXTI_SECCFGR1_SEC24_Pos = 0x18
	// Bit mask of SEC24 field.
	EXTI_SECCFGR1_SEC24_Msk = 0x1000000
	// Bit SEC24.
	EXTI_SECCFGR1_SEC24 = 0x1000000
	// Position of SEC25 field.
	EXTI_SECCFGR1_SEC25_Pos = 0x19
	// Bit mask of SEC25 field.
	EXTI_SECCFGR1_SEC25_Msk = 0x2000000
	// Bit SEC25.
	EXTI_SECCFGR1_SEC25 = 0x2000000
	// Position of SEC26 field.
	EXTI_SECCFGR1_SEC26_Pos = 0x1a
	// Bit mask of SEC26 field.
	EXTI_SECCFGR1_SEC26_Msk = 0x4000000
	// Bit SEC26.
	EXTI_SECCFGR1_SEC26 = 0x4000000
	// Position of SEC27 field.
	EXTI_SECCFGR1_SEC27_Pos = 0x1b
	// Bit mask of SEC27 field.
	EXTI_SECCFGR1_SEC27_Msk = 0x8000000
	// Bit SEC27.
	EXTI_SECCFGR1_SEC27 = 0x8000000
	// Position of SEC28 field.
	EXTI_SECCFGR1_SEC28_Pos = 0x1c
	// Bit mask of SEC28 field.
	EXTI_SECCFGR1_SEC28_Msk = 0x10000000
	// Bit SEC28.
	EXTI_SECCFGR1_SEC28 = 0x10000000
	// Position of SEC29 field.
	EXTI_SECCFGR1_SEC29_Pos = 0x1d
	// Bit mask of SEC29 field.
	EXTI_SECCFGR1_SEC29_Msk = 0x20000000
	// Bit SEC29.
	EXTI_SECCFGR1_SEC29 = 0x20000000
	// Position of SEC30 field.
	EXTI_SECCFGR1_SEC30_Pos = 0x1e
	// Bit mask of SEC30 field.
	EXTI_SECCFGR1_SEC30_Msk = 0x40000000
	// Bit SEC30.
	EXTI_SECCFGR1_SEC30 = 0x40000000
	// Position of SEC31 field.
	EXTI_SECCFGR1_SEC31_Pos = 0x1f
	// Bit mask of SEC31 field.
	EXTI_SECCFGR1_SEC31_Msk = 0x80000000
	// Bit SEC31.
	EXTI_SECCFGR1_SEC31 = 0x80000000

	// PRIVCFGR1: EXTI privilege configuration register
	// Position of PRIV0 field.
	EXTI_PRIVCFGR1_PRIV0_Pos = 0x0
	// Bit mask of PRIV0 field.
	EXTI_PRIVCFGR1_PRIV0_Msk = 0x1
	// Bit PRIV0.
	EXTI_PRIVCFGR1_PRIV0 = 0x1
	// Position of PRIV1 field.
	EXTI_PRIVCFGR1_PRIV1_Pos = 0x1
	// Bit mask of PRIV1 field.
	EXTI_PRIVCFGR1_PRIV1_Msk = 0x2
	// Bit PRIV1.
	EXTI_PRIVCFGR1_PRIV1 = 0x2
	// Position of PRIV2 field.
	EXTI_PRIVCFGR1_PRIV2_Pos = 0x2
	// Bit mask of PRIV2 field.
	EXTI_PRIVCFGR1_PRIV2_Msk = 0x4
	// Bit PRIV2.
	EXTI_PRIVCFGR1_PRIV2 = 0x4
	// Position of PRIV3 field.
	EXTI_PRIVCFGR1_PRIV3_Pos = 0x3
	// Bit mask of PRIV3 field.
	EXTI_PRIVCFGR1_PRIV3_Msk = 0x8
	// Bit PRIV3.
	EXTI_PRIVCFGR1_PRIV3 = 0x8
	// Position of PRIV4 field.
	EXTI_PRIVCFGR1_PRIV4_Pos = 0x4
	// Bit mask of PRIV4 field.
	EXTI_PRIVCFGR1_PRIV4_Msk = 0x10
	// Bit PRIV4.
	EXTI_PRIVCFGR1_PRIV4 = 0x10
	// Position of PRIV5 field.
	EXTI_PRIVCFGR1_PRIV5_Pos = 0x5
	// Bit mask of PRIV5 field.
	EXTI_PRIVCFGR1_PRIV5_Msk = 0x20
	// Bit PRIV5.
	EXTI_PRIVCFGR1_PRIV5 = 0x20
	// Position of PRIV6 field.
	EXTI_PRIVCFGR1_PRIV6_Pos = 0x6
	// Bit mask of PRIV6 field.
	EXTI_PRIVCFGR1_PRIV6_Msk = 0x40
	// Bit PRIV6.
	EXTI_PRIVCFGR1_PRIV6 = 0x40
	// Position of PRIV7 field.
	EXTI_PRIVCFGR1_PRIV7_Pos = 0x7
	// Bit mask of PRIV7 field.
	EXTI_PRIVCFGR1_PRIV7_Msk = 0x80
	// Bit PRIV7.
	EXTI_PRIVCFGR1_PRIV7 = 0x80
	// Position of PRIV8 field.
	EXTI_PRIVCFGR1_PRIV8_Pos = 0x8
	// Bit mask of PRIV8 field.
	EXTI_PRIVCFGR1_PRIV8_Msk = 0x100
	// Bit PRIV8.
	EXTI_PRIVCFGR1_PRIV8 = 0x100
	// Position of PRIV9 field.
	EXTI_PRIVCFGR1_PRIV9_Pos = 0x9
	// Bit mask of PRIV9 field.
	EXTI_PRIVCFGR1_PRIV9_Msk = 0x200
	// Bit PRIV9.
	EXTI_PRIVCFGR1_PRIV9 = 0x200
	// Position of PRIV10 field.
	EXTI_PRIVCFGR1_PRIV10_Pos = 0xa
	// Bit mask of PRIV10 field.
	EXTI_PRIVCFGR1_PRIV10_Msk = 0x400
	// Bit PRIV10.
	EXTI_PRIVCFGR1_PRIV10 = 0x400
	// Position of PRIV11 field.
	EXTI_PRIVCFGR1_PRIV11_Pos = 0xb
	// Bit mask of PRIV11 field.
	EXTI_PRIVCFGR1_PRIV11_Msk = 0x800
	// Bit PRIV11.
	EXTI_PRIVCFGR1_PRIV11 = 0x800
	// Position of PRIV12 field.
	EXTI_PRIVCFGR1_PRIV12_Pos = 0xc
	// Bit mask of PRIV12 field.
	EXTI_PRIVCFGR1_PRIV12_Msk = 0x1000
	// Bit PRIV12.
	EXTI_PRIVCFGR1_PRIV12 = 0x1000
	// Position of PRIV13 field.
	EXTI_PRIVCFGR1_PRIV13_Pos = 0xd
	// Bit mask of PRIV13 field.
	EXTI_PRIVCFGR1_PRIV13_Msk = 0x2000
	// Bit PRIV13.
	EXTI_PRIVCFGR1_PRIV13 = 0x2000
	// Position of PRIV14 field.
	EXTI_PRIVCFGR1_PRIV14_Pos = 0xe
	// Bit mask of PRIV14 field.
	EXTI_PRIVCFGR1_PRIV14_Msk = 0x4000
	// Bit PRIV14.
	EXTI_PRIVCFGR1_PRIV14 = 0x4000
	// Position of PRIV15 field.
	EXTI_PRIVCFGR1_PRIV15_Pos = 0xf
	// Bit mask of PRIV15 field.
	EXTI_PRIVCFGR1_PRIV15_Msk = 0x8000
	// Bit PRIV15.
	EXTI_PRIVCFGR1_PRIV15 = 0x8000
	// Position of PRIV16 field.
	EXTI_PRIVCFGR1_PRIV16_Pos = 0x10
	// Bit mask of PRIV16 field.
	EXTI_PRIVCFGR1_PRIV16_Msk = 0x10000
	// Bit PRIV16.
	EXTI_PRIVCFGR1_PRIV16 = 0x10000
	// Position of PRIV17 field.
	EXTI_PRIVCFGR1_PRIV17_Pos = 0x11
	// Bit mask of PRIV17 field.
	EXTI_PRIVCFGR1_PRIV17_Msk = 0x20000
	// Bit PRIV17.
	EXTI_PRIVCFGR1_PRIV17 = 0x20000
	// Position of PRIV18 field.
	EXTI_PRIVCFGR1_PRIV18_Pos = 0x12
	// Bit mask of PRIV18 field.
	EXTI_PRIVCFGR1_PRIV18_Msk = 0x40000
	// Bit PRIV18.
	EXTI_PRIVCFGR1_PRIV18 = 0x40000
	// Position of PRIV19 field.
	EXTI_PRIVCFGR1_PRIV19_Pos = 0x13
	// Bit mask of PRIV19 field.
	EXTI_PRIVCFGR1_PRIV19_Msk = 0x80000
	// Bit PRIV19.
	EXTI_PRIVCFGR1_PRIV19 = 0x80000
	// Position of PRIV20 field.
	EXTI_PRIVCFGR1_PRIV20_Pos = 0x14
	// Bit mask of PRIV20 field.
	EXTI_PRIVCFGR1_PRIV20_Msk = 0x100000
	// Bit PRIV20.
	EXTI_PRIVCFGR1_PRIV20 = 0x100000
	// Position of PRIV21 field.
	EXTI_PRIVCFGR1_PRIV21_Pos = 0x15
	// Bit mask of PRIV21 field.
	EXTI_PRIVCFGR1_PRIV21_Msk = 0x200000
	// Bit PRIV21.
	EXTI_PRIVCFGR1_PRIV21 = 0x200000
	// Position of PRIV22 field.
	EXTI_PRIVCFGR1_PRIV22_Pos = 0x16
	// Bit mask of PRIV22 field.
	EXTI_PRIVCFGR1_PRIV22_Msk = 0x400000
	// Bit PRIV22.
	EXTI_PRIVCFGR1_PRIV22 = 0x400000
	// Position of PRIV23 field.
	EXTI_PRIVCFGR1_PRIV23_Pos = 0x17
	// Bit mask of PRIV23 field.
	EXTI_PRIVCFGR1_PRIV23_Msk = 0x800000
	// Bit PRIV23.
	EXTI_PRIVCFGR1_PRIV23 = 0x800000
	// Position of PRIV24 field.
	EXTI_PRIVCFGR1_PRIV24_Pos = 0x18
	// Bit mask of PRIV24 field.
	EXTI_PRIVCFGR1_PRIV24_Msk = 0x1000000
	// Bit PRIV24.
	EXTI_PRIVCFGR1_PRIV24 = 0x1000000
	// Position of PRIV25 field.
	EXTI_PRIVCFGR1_PRIV25_Pos = 0x19
	// Bit mask of PRIV25 field.
	EXTI_PRIVCFGR1_PRIV25_Msk = 0x2000000
	// Bit PRIV25.
	EXTI_PRIVCFGR1_PRIV25 = 0x2000000
	// Position of PRIV26 field.
	EXTI_PRIVCFGR1_PRIV26_Pos = 0x1a
	// Bit mask of PRIV26 field.
	EXTI_PRIVCFGR1_PRIV26_Msk = 0x4000000
	// Bit PRIV26.
	EXTI_PRIVCFGR1_PRIV26 = 0x4000000
	// Position of PRIV27 field.
	EXTI_PRIVCFGR1_PRIV27_Pos = 0x1b
	// Bit mask of PRIV27 field.
	EXTI_PRIVCFGR1_PRIV27_Msk = 0x8000000
	// Bit PRIV27.
	EXTI_PRIVCFGR1_PRIV27 = 0x8000000
	// Position of PRIV28 field.
	EXTI_PRIVCFGR1_PRIV28_Pos = 0x1c
	// Bit mask of PRIV28 field.
	EXTI_PRIVCFGR1_PRIV28_Msk = 0x10000000
	// Bit PRIV28.
	EXTI_PRIVCFGR1_PRIV28 = 0x10000000
	// Position of PRIV29 field.
	EXTI_PRIVCFGR1_PRIV29_Pos = 0x1d
	// Bit mask of PRIV29 field.
	EXTI_PRIVCFGR1_PRIV29_Msk = 0x20000000
	// Bit PRIV29.
	EXTI_PRIVCFGR1_PRIV29 = 0x20000000
	// Position of PRIV30 field.
	EXTI_PRIVCFGR1_PRIV30_Pos = 0x1e
	// Bit mask of PRIV30 field.
	EXTI_PRIVCFGR1_PRIV30_Msk = 0x40000000
	// Bit PRIV30.
	EXTI_PRIVCFGR1_PRIV30 = 0x40000000
	// Position of PRIV31 field.
	EXTI_PRIVCFGR1_PRIV31_Pos = 0x1f
	// Bit mask of PRIV31 field.
	EXTI_PRIVCFGR1_PRIV31_Msk = 0x80000000
	// Bit PRIV31.
	EXTI_PRIVCFGR1_PRIV31 = 0x80000000

	// RTSR2: EXTI rising trigger selection register
	// Position of RT35 field.
	EXTI_RTSR2_RT35_Pos = 0x3
	// Bit mask of RT35 field.
	EXTI_RTSR2_RT35_Msk = 0x8
	// Bit RT35.
	EXTI_RTSR2_RT35 = 0x8
	// Position of RT36 field.
	EXTI_RTSR2_RT36_Pos = 0x4
	// Bit mask of RT36 field.
	EXTI_RTSR2_RT36_Msk = 0x10
	// Bit RT36.
	EXTI_RTSR2_RT36 = 0x10
	// Position of RT37 field.
	EXTI_RTSR2_RT37_Pos = 0x5
	// Bit mask of RT37 field.
	EXTI_RTSR2_RT37_Msk = 0x20
	// Bit RT37.
	EXTI_RTSR2_RT37 = 0x20
	// Position of RT38 field.
	EXTI_RTSR2_RT38_Pos = 0x6
	// Bit mask of RT38 field.
	EXTI_RTSR2_RT38_Msk = 0x40
	// Bit RT38.
	EXTI_RTSR2_RT38 = 0x40

	// FTSR2: EXTI falling trigger selection register
	// Position of FT35 field.
	EXTI_FTSR2_FT35_Pos = 0x3
	// Bit mask of FT35 field.
	EXTI_FTSR2_FT35_Msk = 0x8
	// Bit FT35.
	EXTI_FTSR2_FT35 = 0x8
	// Position of FT36 field.
	EXTI_FTSR2_FT36_Pos = 0x4
	// Bit mask of FT36 field.
	EXTI_FTSR2_FT36_Msk = 0x10
	// Bit FT36.
	EXTI_FTSR2_FT36 = 0x10
	// Position of FT37 field.
	EXTI_FTSR2_FT37_Pos = 0x5
	// Bit mask of FT37 field.
	EXTI_FTSR2_FT37_Msk = 0x20
	// Bit FT37.
	EXTI_FTSR2_FT37 = 0x20
	// Position of FT38 field.
	EXTI_FTSR2_FT38_Pos = 0x6
	// Bit mask of FT38 field.
	EXTI_FTSR2_FT38_Msk = 0x40
	// Bit FT38.
	EXTI_FTSR2_FT38 = 0x40

	// SWIER2: EXTI software interrupt event register
	// Position of SWI35 field.
	EXTI_SWIER2_SWI35_Pos = 0x3
	// Bit mask of SWI35 field.
	EXTI_SWIER2_SWI35_Msk = 0x8
	// Bit SWI35.
	EXTI_SWIER2_SWI35 = 0x8
	// Position of SWI36 field.
	EXTI_SWIER2_SWI36_Pos = 0x4
	// Bit mask of SWI36 field.
	EXTI_SWIER2_SWI36_Msk = 0x10
	// Bit SWI36.
	EXTI_SWIER2_SWI36 = 0x10
	// Position of SWI37 field.
	EXTI_SWIER2_SWI37_Pos = 0x5
	// Bit mask of SWI37 field.
	EXTI_SWIER2_SWI37_Msk = 0x20
	// Bit SWI37.
	EXTI_SWIER2_SWI37 = 0x20
	// Position of SWI38 field.
	EXTI_SWIER2_SWI38_Pos = 0x6
	// Bit mask of SWI38 field.
	EXTI_SWIER2_SWI38_Msk = 0x40
	// Bit SWI38.
	EXTI_SWIER2_SWI38 = 0x40

	// RPR2: EXTI rising edge pending register
	// Position of RPIF35 field.
	EXTI_RPR2_RPIF35_Pos = 0x3
	// Bit mask of RPIF35 field.
	EXTI_RPR2_RPIF35_Msk = 0x8
	// Bit RPIF35.
	EXTI_RPR2_RPIF35 = 0x8
	// Position of RPIF36 field.
	EXTI_RPR2_RPIF36_Pos = 0x4
	// Bit mask of RPIF36 field.
	EXTI_RPR2_RPIF36_Msk = 0x10
	// Bit RPIF36.
	EXTI_RPR2_RPIF36 = 0x10
	// Position of RPIF37 field.
	EXTI_RPR2_RPIF37_Pos = 0x5
	// Bit mask of RPIF37 field.
	EXTI_RPR2_RPIF37_Msk = 0x20
	// Bit RPIF37.
	EXTI_RPR2_RPIF37 = 0x20
	// Position of RPIF38 field.
	EXTI_RPR2_RPIF38_Pos = 0x6
	// Bit mask of RPIF38 field.
	EXTI_RPR2_RPIF38_Msk = 0x40
	// Bit RPIF38.
	EXTI_RPR2_RPIF38 = 0x40

	// FPR2: EXTI falling edge pending register
	// Position of FPIF35 field.
	EXTI_FPR2_FPIF35_Pos = 0x3
	// Bit mask of FPIF35 field.
	EXTI_FPR2_FPIF35_Msk = 0x8
	// Bit FPIF35.
	EXTI_FPR2_FPIF35 = 0x8
	// Position of FPIF36 field.
	EXTI_FPR2_FPIF36_Pos = 0x4
	// Bit mask of FPIF36 field.
	EXTI_FPR2_FPIF36_Msk = 0x10
	// Bit FPIF36.
	EXTI_FPR2_FPIF36 = 0x10
	// Position of FPIF37 field.
	EXTI_FPR2_FPIF37_Pos = 0x5
	// Bit mask of FPIF37 field.
	EXTI_FPR2_FPIF37_Msk = 0x20
	// Bit FPIF37.
	EXTI_FPR2_FPIF37 = 0x20
	// Position of FPIF38 field.
	EXTI_FPR2_FPIF38_Pos = 0x6
	// Bit mask of FPIF38 field.
	EXTI_FPR2_FPIF38_Msk = 0x40
	// Bit FPIF38.
	EXTI_FPR2_FPIF38 = 0x40

	// PRIVCFGR2: EXTI security enable register
	// Position of PRIV32 field.
	EXTI_PRIVCFGR2_PRIV32_Pos = 0x0
	// Bit mask of PRIV32 field.
	EXTI_PRIVCFGR2_PRIV32_Msk = 0x1
	// Bit PRIV32.
	EXTI_PRIVCFGR2_PRIV32 = 0x1
	// Position of PRIV33 field.
	EXTI_PRIVCFGR2_PRIV33_Pos = 0x1
	// Bit mask of PRIV33 field.
	EXTI_PRIVCFGR2_PRIV33_Msk = 0x2
	// Bit PRIV33.
	EXTI_PRIVCFGR2_PRIV33 = 0x2
	// Position of PRIV34 field.
	EXTI_PRIVCFGR2_PRIV34_Pos = 0x2
	// Bit mask of PRIV34 field.
	EXTI_PRIVCFGR2_PRIV34_Msk = 0x4
	// Bit PRIV34.
	EXTI_PRIVCFGR2_PRIV34 = 0x4
	// Position of PRIV35 field.
	EXTI_PRIVCFGR2_PRIV35_Pos = 0x3
	// Bit mask of PRIV35 field.
	EXTI_PRIVCFGR2_PRIV35_Msk = 0x8
	// Bit PRIV35.
	EXTI_PRIVCFGR2_PRIV35 = 0x8
	// Position of PRIV36 field.
	EXTI_PRIVCFGR2_PRIV36_Pos = 0x4
	// Bit mask of PRIV36 field.
	EXTI_PRIVCFGR2_PRIV36_Msk = 0x10
	// Bit PRIV36.
	EXTI_PRIVCFGR2_PRIV36 = 0x10
	// Position of PRIV37 field.
	EXTI_PRIVCFGR2_PRIV37_Pos = 0x5
	// Bit mask of PRIV37 field.
	EXTI_PRIVCFGR2_PRIV37_Msk = 0x20
	// Bit PRIV37.
	EXTI_PRIVCFGR2_PRIV37 = 0x20
	// Position of PRIV38 field.
	EXTI_PRIVCFGR2_PRIV38_Pos = 0x6
	// Bit mask of PRIV38 field.
	EXTI_PRIVCFGR2_PRIV38_Msk = 0x40
	// Bit PRIV38.
	EXTI_PRIVCFGR2_PRIV38 = 0x40
	// Position of PRIV39 field.
	EXTI_PRIVCFGR2_PRIV39_Pos = 0x7
	// Bit mask of PRIV39 field.
	EXTI_PRIVCFGR2_PRIV39_Msk = 0x80
	// Bit PRIV39.
	EXTI_PRIVCFGR2_PRIV39 = 0x80
	// Position of PRIV40 field.
	EXTI_PRIVCFGR2_PRIV40_Pos = 0x8
	// Bit mask of PRIV40 field.
	EXTI_PRIVCFGR2_PRIV40_Msk = 0x100
	// Bit PRIV40.
	EXTI_PRIVCFGR2_PRIV40 = 0x100
	// Position of PRIV41 field.
	EXTI_PRIVCFGR2_PRIV41_Pos = 0x9
	// Bit mask of PRIV41 field.
	EXTI_PRIVCFGR2_PRIV41_Msk = 0x200
	// Bit PRIV41.
	EXTI_PRIVCFGR2_PRIV41 = 0x200
	// Position of PRIV42 field.
	EXTI_PRIVCFGR2_PRIV42_Pos = 0xa
	// Bit mask of PRIV42 field.
	EXTI_PRIVCFGR2_PRIV42_Msk = 0x400
	// Bit PRIV42.
	EXTI_PRIVCFGR2_PRIV42 = 0x400

	// SECCFGR2: EXTI security enable register
	// Position of SEC32 field.
	EXTI_SECCFGR2_SEC32_Pos = 0x0
	// Bit mask of SEC32 field.
	EXTI_SECCFGR2_SEC32_Msk = 0x1
	// Bit SEC32.
	EXTI_SECCFGR2_SEC32 = 0x1
	// Position of SEC33 field.
	EXTI_SECCFGR2_SEC33_Pos = 0x1
	// Bit mask of SEC33 field.
	EXTI_SECCFGR2_SEC33_Msk = 0x2
	// Bit SEC33.
	EXTI_SECCFGR2_SEC33 = 0x2
	// Position of SEC34 field.
	EXTI_SECCFGR2_SEC34_Pos = 0x2
	// Bit mask of SEC34 field.
	EXTI_SECCFGR2_SEC34_Msk = 0x4
	// Bit SEC34.
	EXTI_SECCFGR2_SEC34 = 0x4
	// Position of SEC35 field.
	EXTI_SECCFGR2_SEC35_Pos = 0x3
	// Bit mask of SEC35 field.
	EXTI_SECCFGR2_SEC35_Msk = 0x8
	// Bit SEC35.
	EXTI_SECCFGR2_SEC35 = 0x8
	// Position of SEC36 field.
	EXTI_SECCFGR2_SEC36_Pos = 0x4
	// Bit mask of SEC36 field.
	EXTI_SECCFGR2_SEC36_Msk = 0x10
	// Bit SEC36.
	EXTI_SECCFGR2_SEC36 = 0x10
	// Position of SEC37 field.
	EXTI_SECCFGR2_SEC37_Pos = 0x5
	// Bit mask of SEC37 field.
	EXTI_SECCFGR2_SEC37_Msk = 0x20
	// Bit SEC37.
	EXTI_SECCFGR2_SEC37 = 0x20
	// Position of SEC38 field.
	EXTI_SECCFGR2_SEC38_Pos = 0x6
	// Bit mask of SEC38 field.
	EXTI_SECCFGR2_SEC38_Msk = 0x40
	// Bit SEC38.
	EXTI_SECCFGR2_SEC38 = 0x40
	// Position of SEC39 field.
	EXTI_SECCFGR2_SEC39_Pos = 0x7
	// Bit mask of SEC39 field.
	EXTI_SECCFGR2_SEC39_Msk = 0x80
	// Bit SEC39.
	EXTI_SECCFGR2_SEC39 = 0x80
	// Position of SEC40 field.
	EXTI_SECCFGR2_SEC40_Pos = 0x8
	// Bit mask of SEC40 field.
	EXTI_SECCFGR2_SEC40_Msk = 0x100
	// Bit SEC40.
	EXTI_SECCFGR2_SEC40 = 0x100
	// Position of SEC41 field.
	EXTI_SECCFGR2_SEC41_Pos = 0x9
	// Bit mask of SEC41 field.
	EXTI_SECCFGR2_SEC41_Msk = 0x200
	// Bit SEC41.
	EXTI_SECCFGR2_SEC41 = 0x200
	// Position of SEC42 field.
	EXTI_SECCFGR2_SEC42_Pos = 0xa
	// Bit mask of SEC42 field.
	EXTI_SECCFGR2_SEC42_Msk = 0x400
	// Bit SEC42.
	EXTI_SECCFGR2_SEC42 = 0x400

	// EXTICR1: EXTI external interrupt selection register
	// Position of EXTI0 field.
	EXTI_EXTICR1_EXTI0_Pos = 0x0
	// Bit mask of EXTI0 field.
	EXTI_EXTICR1_EXTI0_Msk = 0xff
	// Position of EXTI1 field.
	EXTI_EXTICR1_EXTI1_Pos = 0x8
	// Bit mask of EXTI1 field.
	EXTI_EXTICR1_EXTI1_Msk = 0xff00
	// Position of EXTI2 field.
	EXTI_EXTICR1_EXTI2_Pos = 0x10
	// Bit mask of EXTI2 field.
	EXTI_EXTICR1_EXTI2_Msk = 0xff0000
	// Position of EXTI3 field.
	EXTI_EXTICR1_EXTI3_Pos = 0x18
	// Bit mask of EXTI3 field.
	EXTI_EXTICR1_EXTI3_Msk = 0xff000000

	// EXTICR2: EXTI external interrupt selection register
	// Position of EXTI4 field.
	EXTI_EXTICR2_EXTI4_Pos = 0x0
	// Bit mask of EXTI4 field.
	EXTI_EXTICR2_EXTI4_Msk = 0xff
	// Position of EXTI5 field.
	EXTI_EXTICR2_EXTI5_Pos = 0x8
	// Bit mask of EXTI5 field.
	EXTI_EXTICR2_EXTI5_Msk = 0xff00
	// Position of EXTI6 field.
	EXTI_EXTICR2_EXTI6_Pos = 0x10
	// Bit mask of EXTI6 field.
	EXTI_EXTICR2_EXTI6_Msk = 0xff0000
	// Position of EXTI7 field.
	EXTI_EXTICR2_EXTI7_Pos = 0x18
	// Bit mask of EXTI7 field.
	EXTI_EXTICR2_EXTI7_Msk = 0xff000000

	// EXTICR3: EXTI external interrupt selection register
	// Position of EXTI8 field.
	EXTI_EXTICR3_EXTI8_Pos = 0x0
	// Bit mask of EXTI8 field.
	EXTI_EXTICR3_EXTI8_Msk = 0xff
	// Position of EXTI9 field.
	EXTI_EXTICR3_EXTI9_Pos = 0x8
	// Bit mask of EXTI9 field.
	EXTI_EXTICR3_EXTI9_Msk = 0xff00
	// Position of EXTI10 field.
	EXTI_EXTICR3_EXTI10_Pos = 0x10
	// Bit mask of EXTI10 field.
	EXTI_EXTICR3_EXTI10_Msk = 0xff0000
	// Position of EXTI11 field.
	EXTI_EXTICR3_EXTI11_Pos = 0x18
	// Bit mask of EXTI11 field.
	EXTI_EXTICR3_EXTI11_Msk = 0xff000000

	// EXTICR4: EXTI external interrupt selection register
	// Position of EXTI12 field.
	EXTI_EXTICR4_EXTI12_Pos = 0x0
	// Bit mask of EXTI12 field.
	EXTI_EXTICR4_EXTI12_Msk = 0xff
	// Position of EXTI13 field.
	EXTI_EXTICR4_EXTI13_Pos = 0x8
	// Bit mask of EXTI13 field.
	EXTI_EXTICR4_EXTI13_Msk = 0xff00
	// Position of EXTI14 field.
	EXTI_EXTICR4_EXTI14_Pos = 0x10
	// Bit mask of EXTI14 field.
	EXTI_EXTICR4_EXTI14_Msk = 0xff0000
	// Position of EXTI15 field.
	EXTI_EXTICR4_EXTI15_Pos = 0x18
	// Bit mask of EXTI15 field.
	EXTI_EXTICR4_EXTI15_Msk = 0xff000000

	// LOCKRG: EXTI lock register
	// Position of LOCK field.
	EXTI_LOCKRG_LOCK_Pos = 0x0
	// Bit mask of LOCK field.
	EXTI_LOCKRG_LOCK_Msk = 0x1
	// Bit LOCK.
	EXTI_LOCKRG_LOCK = 0x1

	// IMR1: EXTI CPU wakeup with interrupt mask register
	// Position of IM0 field.
	EXTI_IMR1_IM0_Pos = 0x0
	// Bit mask of IM0 field.
	EXTI_IMR1_IM0_Msk = 0x1
	// Bit IM0.
	EXTI_IMR1_IM0 = 0x1
	// Position of IM1 field.
	EXTI_IMR1_IM1_Pos = 0x1
	// Bit mask of IM1 field.
	EXTI_IMR1_IM1_Msk = 0x2
	// Bit IM1.
	EXTI_IMR1_IM1 = 0x2
	// Position of IM2 field.
	EXTI_IMR1_IM2_Pos = 0x2
	// Bit mask of IM2 field.
	EXTI_IMR1_IM2_Msk = 0x4
	// Bit IM2.
	EXTI_IMR1_IM2 = 0x4
	// Position of IM3 field.
	EXTI_IMR1_IM3_Pos = 0x3
	// Bit mask of IM3 field.
	EXTI_IMR1_IM3_Msk = 0x8
	// Bit IM3.
	EXTI_IMR1_IM3 = 0x8
	// Position of IM4 field.
	EXTI_IMR1_IM4_Pos = 0x4
	// Bit mask of IM4 field.
	EXTI_IMR1_IM4_Msk = 0x10
	// Bit IM4.
	EXTI_IMR1_IM4 = 0x10
	// Position of IM5 field.
	EXTI_IMR1_IM5_Pos = 0x5
	// Bit mask of IM5 field.
	EXTI_IMR1_IM5_Msk = 0x20
	// Bit IM5.
	EXTI_IMR1_IM5 = 0x20
	// Position of IM6 field.
	EXTI_IMR1_IM6_Pos = 0x6
	// Bit mask of IM6 field.
	EXTI_IMR1_IM6_Msk = 0x40
	// Bit IM6.
	EXTI_IMR1_IM6 = 0x40
	// Position of IM7 field.
	EXTI_IMR1_IM7_Pos = 0x7
	// Bit mask of IM7 field.
	EXTI_IMR1_IM7_Msk = 0x80
	// Bit IM7.
	EXTI_IMR1_IM7 = 0x80
	// Position of IM8 field.
	EXTI_IMR1_IM8_Pos = 0x8
	// Bit mask of IM8 field.
	EXTI_IMR1_IM8_Msk = 0x100
	// Bit IM8.
	EXTI_IMR1_IM8 = 0x100
	// Position of IM9 field.
	EXTI_IMR1_IM9_Pos = 0x9
	// Bit mask of IM9 field.
	EXTI_IMR1_IM9_Msk = 0x200
	// Bit IM9.
	EXTI_IMR1_IM9 = 0x200
	// Position of IM10 field.
	EXTI_IMR1_IM10_Pos = 0xa
	// Bit mask of IM10 field.
	EXTI_IMR1_IM10_Msk = 0x400
	// Bit IM10.
	EXTI_IMR1_IM10 = 0x400
	// Position of IM11 field.
	EXTI_IMR1_IM11_Pos = 0xb
	// Bit mask of IM11 field.
	EXTI_IMR1_IM11_Msk = 0x800
	// Bit IM11.
	EXTI_IMR1_IM11 = 0x800
	// Position of IM12 field.
	EXTI_IMR1_IM12_Pos = 0xc
	// Bit mask of IM12 field.
	EXTI_IMR1_IM12_Msk = 0x1000
	// Bit IM12.
	EXTI_IMR1_IM12 = 0x1000
	// Position of IM13 field.
	EXTI_IMR1_IM13_Pos = 0xd
	// Bit mask of IM13 field.
	EXTI_IMR1_IM13_Msk = 0x2000
	// Bit IM13.
	EXTI_IMR1_IM13 = 0x2000
	// Position of IM14 field.
	EXTI_IMR1_IM14_Pos = 0xe
	// Bit mask of IM14 field.
	EXTI_IMR1_IM14_Msk = 0x4000
	// Bit IM14.
	EXTI_IMR1_IM14 = 0x4000
	// Position of IM15 field.
	EXTI_IMR1_IM15_Pos = 0xf
	// Bit mask of IM15 field.
	EXTI_IMR1_IM15_Msk = 0x8000
	// Bit IM15.
	EXTI_IMR1_IM15 = 0x8000
	// Position of IM16 field.
	EXTI_IMR1_IM16_Pos = 0x10
	// Bit mask of IM16 field.
	EXTI_IMR1_IM16_Msk = 0x10000
	// Bit IM16.
	EXTI_IMR1_IM16 = 0x10000
	// Position of IM17 field.
	EXTI_IMR1_IM17_Pos = 0x11
	// Bit mask of IM17 field.
	EXTI_IMR1_IM17_Msk = 0x20000
	// Bit IM17.
	EXTI_IMR1_IM17 = 0x20000
	// Position of IM18 field.
	EXTI_IMR1_IM18_Pos = 0x12
	// Bit mask of IM18 field.
	EXTI_IMR1_IM18_Msk = 0x40000
	// Bit IM18.
	EXTI_IMR1_IM18 = 0x40000
	// Position of IM19 field.
	EXTI_IMR1_IM19_Pos = 0x13
	// Bit mask of IM19 field.
	EXTI_IMR1_IM19_Msk = 0x80000
	// Bit IM19.
	EXTI_IMR1_IM19 = 0x80000
	// Position of IM20 field.
	EXTI_IMR1_IM20_Pos = 0x14
	// Bit mask of IM20 field.
	EXTI_IMR1_IM20_Msk = 0x100000
	// Bit IM20.
	EXTI_IMR1_IM20 = 0x100000
	// Position of IM21 field.
	EXTI_IMR1_IM21_Pos = 0x15
	// Bit mask of IM21 field.
	EXTI_IMR1_IM21_Msk = 0x200000
	// Bit IM21.
	EXTI_IMR1_IM21 = 0x200000
	// Position of IM22 field.
	EXTI_IMR1_IM22_Pos = 0x16
	// Bit mask of IM22 field.
	EXTI_IMR1_IM22_Msk = 0x400000
	// Bit IM22.
	EXTI_IMR1_IM22 = 0x400000
	// Position of IM23 field.
	EXTI_IMR1_IM23_Pos = 0x17
	// Bit mask of IM23 field.
	EXTI_IMR1_IM23_Msk = 0x800000
	// Bit IM23.
	EXTI_IMR1_IM23 = 0x800000
	// Position of IM24 field.
	EXTI_IMR1_IM24_Pos = 0x18
	// Bit mask of IM24 field.
	EXTI_IMR1_IM24_Msk = 0x1000000
	// Bit IM24.
	EXTI_IMR1_IM24 = 0x1000000
	// Position of IM25 field.
	EXTI_IMR1_IM25_Pos = 0x19
	// Bit mask of IM25 field.
	EXTI_IMR1_IM25_Msk = 0x2000000
	// Bit IM25.
	EXTI_IMR1_IM25 = 0x2000000
	// Position of IM26 field.
	EXTI_IMR1_IM26_Pos = 0x1a
	// Bit mask of IM26 field.
	EXTI_IMR1_IM26_Msk = 0x4000000
	// Bit IM26.
	EXTI_IMR1_IM26 = 0x4000000
	// Position of IM27 field.
	EXTI_IMR1_IM27_Pos = 0x1b
	// Bit mask of IM27 field.
	EXTI_IMR1_IM27_Msk = 0x8000000
	// Bit IM27.
	EXTI_IMR1_IM27 = 0x8000000
	// Position of IM28 field.
	EXTI_IMR1_IM28_Pos = 0x1c
	// Bit mask of IM28 field.
	EXTI_IMR1_IM28_Msk = 0x10000000
	// Bit IM28.
	EXTI_IMR1_IM28 = 0x10000000
	// Position of IM29 field.
	EXTI_IMR1_IM29_Pos = 0x1d
	// Bit mask of IM29 field.
	EXTI_IMR1_IM29_Msk = 0x20000000
	// Bit IM29.
	EXTI_IMR1_IM29 = 0x20000000
	// Position of IM30 field.
	EXTI_IMR1_IM30_Pos = 0x1e
	// Bit mask of IM30 field.
	EXTI_IMR1_IM30_Msk = 0x40000000
	// Bit IM30.
	EXTI_IMR1_IM30 = 0x40000000
	// Position of IM31 field.
	EXTI_IMR1_IM31_Pos = 0x1f
	// Bit mask of IM31 field.
	EXTI_IMR1_IM31_Msk = 0x80000000
	// Bit IM31.
	EXTI_IMR1_IM31 = 0x80000000

	// EMR1: EXTI CPU wakeup with event mask register
	// Position of EM0 field.
	EXTI_EMR1_EM0_Pos = 0x0
	// Bit mask of EM0 field.
	EXTI_EMR1_EM0_Msk = 0x1
	// Bit EM0.
	EXTI_EMR1_EM0 = 0x1
	// Position of EM1 field.
	EXTI_EMR1_EM1_Pos = 0x1
	// Bit mask of EM1 field.
	EXTI_EMR1_EM1_Msk = 0x2
	// Bit EM1.
	EXTI_EMR1_EM1 = 0x2
	// Position of EM2 field.
	EXTI_EMR1_EM2_Pos = 0x2
	// Bit mask of EM2 field.
	EXTI_EMR1_EM2_Msk = 0x4
	// Bit EM2.
	EXTI_EMR1_EM2 = 0x4
	// Position of EM3 field.
	EXTI_EMR1_EM3_Pos = 0x3
	// Bit mask of EM3 field.
	EXTI_EMR1_EM3_Msk = 0x8
	// Bit EM3.
	EXTI_EMR1_EM3 = 0x8
	// Position of EM4 field.
	EXTI_EMR1_EM4_Pos = 0x4
	// Bit mask of EM4 field.
	EXTI_EMR1_EM4_Msk = 0x10
	// Bit EM4.
	EXTI_EMR1_EM4 = 0x10
	// Position of EM5 field.
	EXTI_EMR1_EM5_Pos = 0x5
	// Bit mask of EM5 field.
	EXTI_EMR1_EM5_Msk = 0x20
	// Bit EM5.
	EXTI_EMR1_EM5 = 0x20
	// Position of EM6 field.
	EXTI_EMR1_EM6_Pos = 0x6
	// Bit mask of EM6 field.
	EXTI_EMR1_EM6_Msk = 0x40
	// Bit EM6.
	EXTI_EMR1_EM6 = 0x40
	// Position of EM7 field.
	EXTI_EMR1_EM7_Pos = 0x7
	// Bit mask of EM7 field.
	EXTI_EMR1_EM7_Msk = 0x80
	// Bit EM7.
	EXTI_EMR1_EM7 = 0x80
	// Position of EM8 field.
	EXTI_EMR1_EM8_Pos = 0x8
	// Bit mask of EM8 field.
	EXTI_EMR1_EM8_Msk = 0x100
	// Bit EM8.
	EXTI_EMR1_EM8 = 0x100
	// Position of EM9 field.
	EXTI_EMR1_EM9_Pos = 0x9
	// Bit mask of EM9 field.
	EXTI_EMR1_EM9_Msk = 0x200
	// Bit EM9.
	EXTI_EMR1_EM9 = 0x200
	// Position of EM10 field.
	EXTI_EMR1_EM10_Pos = 0xa
	// Bit mask of EM10 field.
	EXTI_EMR1_EM10_Msk = 0x400
	// Bit EM10.
	EXTI_EMR1_EM10 = 0x400
	// Position of EM11 field.
	EXTI_EMR1_EM11_Pos = 0xb
	// Bit mask of EM11 field.
	EXTI_EMR1_EM11_Msk = 0x800
	// Bit EM11.
	EXTI_EMR1_EM11 = 0x800
	// Position of EM12 field.
	EXTI_EMR1_EM12_Pos = 0xc
	// Bit mask of EM12 field.
	EXTI_EMR1_EM12_Msk = 0x1000
	// Bit EM12.
	EXTI_EMR1_EM12 = 0x1000
	// Position of EM13 field.
	EXTI_EMR1_EM13_Pos = 0xd
	// Bit mask of EM13 field.
	EXTI_EMR1_EM13_Msk = 0x2000
	// Bit EM13.
	EXTI_EMR1_EM13 = 0x2000
	// Position of EM14 field.
	EXTI_EMR1_EM14_Pos = 0xe
	// Bit mask of EM14 field.
	EXTI_EMR1_EM14_Msk = 0x4000
	// Bit EM14.
	EXTI_EMR1_EM14 = 0x4000
	// Position of EM15 field.
	EXTI_EMR1_EM15_Pos = 0xf
	// Bit mask of EM15 field.
	EXTI_EMR1_EM15_Msk = 0x8000
	// Bit EM15.
	EXTI_EMR1_EM15 = 0x8000
	// Position of EM16 field.
	EXTI_EMR1_EM16_Pos = 0x10
	// Bit mask of EM16 field.
	EXTI_EMR1_EM16_Msk = 0x10000
	// Bit EM16.
	EXTI_EMR1_EM16 = 0x10000
	// Position of EM17 field.
	EXTI_EMR1_EM17_Pos = 0x11
	// Bit mask of EM17 field.
	EXTI_EMR1_EM17_Msk = 0x20000
	// Bit EM17.
	EXTI_EMR1_EM17 = 0x20000
	// Position of EM18 field.
	EXTI_EMR1_EM18_Pos = 0x12
	// Bit mask of EM18 field.
	EXTI_EMR1_EM18_Msk = 0x40000
	// Bit EM18.
	EXTI_EMR1_EM18 = 0x40000
	// Position of EM19 field.
	EXTI_EMR1_EM19_Pos = 0x13
	// Bit mask of EM19 field.
	EXTI_EMR1_EM19_Msk = 0x80000
	// Bit EM19.
	EXTI_EMR1_EM19 = 0x80000
	// Position of EM20 field.
	EXTI_EMR1_EM20_Pos = 0x14
	// Bit mask of EM20 field.
	EXTI_EMR1_EM20_Msk = 0x100000
	// Bit EM20.
	EXTI_EMR1_EM20 = 0x100000
	// Position of EM21 field.
	EXTI_EMR1_EM21_Pos = 0x15
	// Bit mask of EM21 field.
	EXTI_EMR1_EM21_Msk = 0x200000
	// Bit EM21.
	EXTI_EMR1_EM21 = 0x200000
	// Position of EM22 field.
	EXTI_EMR1_EM22_Pos = 0x16
	// Bit mask of EM22 field.
	EXTI_EMR1_EM22_Msk = 0x400000
	// Bit EM22.
	EXTI_EMR1_EM22 = 0x400000
	// Position of EM23 field.
	EXTI_EMR1_EM23_Pos = 0x17
	// Bit mask of EM23 field.
	EXTI_EMR1_EM23_Msk = 0x800000
	// Bit EM23.
	EXTI_EMR1_EM23 = 0x800000
	// Position of EM24 field.
	EXTI_EMR1_EM24_Pos = 0x18
	// Bit mask of EM24 field.
	EXTI_EMR1_EM24_Msk = 0x1000000
	// Bit EM24.
	EXTI_EMR1_EM24 = 0x1000000
	// Position of EM25 field.
	EXTI_EMR1_EM25_Pos = 0x19
	// Bit mask of EM25 field.
	EXTI_EMR1_EM25_Msk = 0x2000000
	// Bit EM25.
	EXTI_EMR1_EM25 = 0x2000000
	// Position of EM26 field.
	EXTI_EMR1_EM26_Pos = 0x1a
	// Bit mask of EM26 field.
	EXTI_EMR1_EM26_Msk = 0x4000000
	// Bit EM26.
	EXTI_EMR1_EM26 = 0x4000000
	// Position of EM27 field.
	EXTI_EMR1_EM27_Pos = 0x1b
	// Bit mask of EM27 field.
	EXTI_EMR1_EM27_Msk = 0x8000000
	// Bit EM27.
	EXTI_EMR1_EM27 = 0x8000000
	// Position of EM28 field.
	EXTI_EMR1_EM28_Pos = 0x1c
	// Bit mask of EM28 field.
	EXTI_EMR1_EM28_Msk = 0x10000000
	// Bit EM28.
	EXTI_EMR1_EM28 = 0x10000000
	// Position of EM29 field.
	EXTI_EMR1_EM29_Pos = 0x1d
	// Bit mask of EM29 field.
	EXTI_EMR1_EM29_Msk = 0x20000000
	// Bit EM29.
	EXTI_EMR1_EM29 = 0x20000000
	// Position of EM30 field.
	EXTI_EMR1_EM30_Pos = 0x1e
	// Bit mask of EM30 field.
	EXTI_EMR1_EM30_Msk = 0x40000000
	// Bit EM30.
	EXTI_EMR1_EM30 = 0x40000000
	// Position of EM31 field.
	EXTI_EMR1_EM31_Pos = 0x1f
	// Bit mask of EM31 field.
	EXTI_EMR1_EM31_Msk = 0x80000000
	// Bit EM31.
	EXTI_EMR1_EM31 = 0x80000000

	// IMR2: EXTI CPUm wakeup with interrupt mask register
	// Position of IM32 field.
	EXTI_IMR2_IM32_Pos = 0x0
	// Bit mask of IM32 field.
	EXTI_IMR2_IM32_Msk = 0x1
	// Bit IM32.
	EXTI_IMR2_IM32 = 0x1
	// Position of IM33 field.
	EXTI_IMR2_IM33_Pos = 0x1
	// Bit mask of IM33 field.
	EXTI_IMR2_IM33_Msk = 0x2
	// Bit IM33.
	EXTI_IMR2_IM33 = 0x2
	// Position of IM34 field.
	EXTI_IMR2_IM34_Pos = 0x2
	// Bit mask of IM34 field.
	EXTI_IMR2_IM34_Msk = 0x4
	// Bit IM34.
	EXTI_IMR2_IM34 = 0x4
	// Position of IM35 field.
	EXTI_IMR2_IM35_Pos = 0x3
	// Bit mask of IM35 field.
	EXTI_IMR2_IM35_Msk = 0x8
	// Bit IM35.
	EXTI_IMR2_IM35 = 0x8
	// Position of IM36 field.
	EXTI_IMR2_IM36_Pos = 0x4
	// Bit mask of IM36 field.
	EXTI_IMR2_IM36_Msk = 0x10
	// Bit IM36.
	EXTI_IMR2_IM36 = 0x10
	// Position of IM37 field.
	EXTI_IMR2_IM37_Pos = 0x5
	// Bit mask of IM37 field.
	EXTI_IMR2_IM37_Msk = 0x20
	// Bit IM37.
	EXTI_IMR2_IM37 = 0x20
	// Position of IM38 field.
	EXTI_IMR2_IM38_Pos = 0x6
	// Bit mask of IM38 field.
	EXTI_IMR2_IM38_Msk = 0x40
	// Bit IM38.
	EXTI_IMR2_IM38 = 0x40
	// Position of IM40 field.
	EXTI_IMR2_IM40_Pos = 0x8
	// Bit mask of IM40 field.
	EXTI_IMR2_IM40_Msk = 0x100
	// Bit IM40.
	EXTI_IMR2_IM40 = 0x100
	// Position of IM41 field.
	EXTI_IMR2_IM41_Pos = 0x9
	// Bit mask of IM41 field.
	EXTI_IMR2_IM41_Msk = 0x200
	// Bit IM41.
	EXTI_IMR2_IM41 = 0x200
	// Position of IM42 field.
	EXTI_IMR2_IM42_Pos = 0xa
	// Bit mask of IM42 field.
	EXTI_IMR2_IM42_Msk = 0x400
	// Bit IM42.
	EXTI_IMR2_IM42 = 0x400

	// EMR2: EXTI CPU wakeup with event mask register
	// Position of EM32 field.
	EXTI_EMR2_EM32_Pos = 0x0
	// Bit mask of EM32 field.
	EXTI_EMR2_EM32_Msk = 0x1
	// Bit EM32.
	EXTI_EMR2_EM32 = 0x1
	// Position of EM33 field.
	EXTI_EMR2_EM33_Pos = 0x1
	// Bit mask of EM33 field.
	EXTI_EMR2_EM33_Msk = 0x2
	// Bit EM33.
	EXTI_EMR2_EM33 = 0x2
	// Position of EM34 field.
	EXTI_EMR2_EM34_Pos = 0x2
	// Bit mask of EM34 field.
	EXTI_EMR2_EM34_Msk = 0x4
	// Bit EM34.
	EXTI_EMR2_EM34 = 0x4
	// Position of EM35 field.
	EXTI_EMR2_EM35_Pos = 0x3
	// Bit mask of EM35 field.
	EXTI_EMR2_EM35_Msk = 0x8
	// Bit EM35.
	EXTI_EMR2_EM35 = 0x8
	// Position of EM36 field.
	EXTI_EMR2_EM36_Pos = 0x4
	// Bit mask of EM36 field.
	EXTI_EMR2_EM36_Msk = 0x10
	// Bit EM36.
	EXTI_EMR2_EM36 = 0x10
	// Position of EM37 field.
	EXTI_EMR2_EM37_Pos = 0x5
	// Bit mask of EM37 field.
	EXTI_EMR2_EM37_Msk = 0x20
	// Bit EM37.
	EXTI_EMR2_EM37 = 0x20
	// Position of EM38 field.
	EXTI_EMR2_EM38_Pos = 0x6
	// Bit mask of EM38 field.
	EXTI_EMR2_EM38_Msk = 0x40
	// Bit EM38.
	EXTI_EMR2_EM38 = 0x40
	// Position of EM40 field.
	EXTI_EMR2_EM40_Pos = 0x8
	// Bit mask of EM40 field.
	EXTI_EMR2_EM40_Msk = 0x100
	// Bit EM40.
	EXTI_EMR2_EM40 = 0x100
	// Position of EM41 field.
	EXTI_EMR2_EM41_Pos = 0x9
	// Bit mask of EM41 field.
	EXTI_EMR2_EM41_Msk = 0x200
	// Bit EM41.
	EXTI_EMR2_EM41 = 0x200
	// Position of EM42 field.
	EXTI_EMR2_EM42_Pos = 0xa
	// Bit mask of EM42 field.
	EXTI_EMR2_EM42_Msk = 0x400
	// Bit EM42.
	EXTI_EMR2_EM42 = 0x400
)

// Constants for FDCAN1: FDCAN1
const (
	// CREL: FDCAN Core Release Register
	// Position of REL field.
	FDCAN_CREL_REL_Pos = 0x1c
	// Bit mask of REL field.
	FDCAN_CREL_REL_Msk = 0xf0000000
	// Position of STEP field.
	FDCAN_CREL_STEP_Pos = 0x18
	// Bit mask of STEP field.
	FDCAN_CREL_STEP_Msk = 0xf000000
	// Position of SUBSTEP field.
	FDCAN_CREL_SUBSTEP_Pos = 0x14
	// Bit mask of SUBSTEP field.
	FDCAN_CREL_SUBSTEP_Msk = 0xf00000
	// Position of YEAR field.
	FDCAN_CREL_YEAR_Pos = 0x10
	// Bit mask of YEAR field.
	FDCAN_CREL_YEAR_Msk = 0xf0000
	// Position of MON field.
	FDCAN_CREL_MON_Pos = 0x8
	// Bit mask of MON field.
	FDCAN_CREL_MON_Msk = 0xff00
	// Position of DAY field.
	FDCAN_CREL_DAY_Pos = 0x0
	// Bit mask of DAY field.
	FDCAN_CREL_DAY_Msk = 0xff

	// ENDN: FDCAN Core Release Register
	// Position of ETV field.
	FDCAN_ENDN_ETV_Pos = 0x0
	// Bit mask of ETV field.
	FDCAN_ENDN_ETV_Msk = 0xffffffff

	// DBTP: FDCAN Data Bit Timing and Prescaler Register
	// Position of DSJW field.
	FDCAN_DBTP_DSJW_Pos = 0x0
	// Bit mask of DSJW field.
	FDCAN_DBTP_DSJW_Msk = 0xf
	// Position of DTSEG2 field.
	FDCAN_DBTP_DTSEG2_Pos = 0x4
	// Bit mask of DTSEG2 field.
	FDCAN_DBTP_DTSEG2_Msk = 0xf0
	// Position of DTSEG1 field.
	FDCAN_DBTP_DTSEG1_Pos = 0x8
	// Bit mask of DTSEG1 field.
	FDCAN_DBTP_DTSEG1_Msk = 0x1f00
	// Position of DBRP field.
	FDCAN_DBTP_DBRP_Pos = 0x10
	// Bit mask of DBRP field.
	FDCAN_DBTP_DBRP_Msk = 0x1f0000
	// Position of TDC field.
	FDCAN_DBTP_TDC_Pos = 0x17
	// Bit mask of TDC field.
	FDCAN_DBTP_TDC_Msk = 0x800000
	// Bit TDC.
	FDCAN_DBTP_TDC = 0x800000

	// TEST: FDCAN Test Register
	// Position of LBCK field.
	FDCAN_TEST_LBCK_Pos = 0x4
	// Bit mask of LBCK field.
	FDCAN_TEST_LBCK_Msk = 0x10
	// Bit LBCK.
	FDCAN_TEST_LBCK = 0x10
	// Position of TX field.
	FDCAN_TEST_TX_Pos = 0x5
	// Bit mask of TX field.
	FDCAN_TEST_TX_Msk = 0x60
	// Position of RX field.
	FDCAN_TEST_RX_Pos = 0x7
	// Bit mask of RX field.
	FDCAN_TEST_RX_Msk = 0x80
	// Bit RX.
	FDCAN_TEST_RX = 0x80

	// RWD: FDCAN RAM Watchdog Register
	// Position of WDV field.
	FDCAN_RWD_WDV_Pos = 0x8
	// Bit mask of WDV field.
	FDCAN_RWD_WDV_Msk = 0xff00
	// Position of WDC field.
	FDCAN_RWD_WDC_Pos = 0x0
	// Bit mask of WDC field.
	FDCAN_RWD_WDC_Msk = 0xff

	// CCCR: FDCAN CC Control Register
	// Position of INIT field.
	FDCAN_CCCR_INIT_Pos = 0x0
	// Bit mask of INIT field.
	FDCAN_CCCR_INIT_Msk = 0x1
	// Bit INIT.
	FDCAN_CCCR_INIT = 0x1
	// Position of CCE field.
	FDCAN_CCCR_CCE_Pos = 0x1
	// Bit mask of CCE field.
	FDCAN_CCCR_CCE_Msk = 0x2
	// Bit CCE.
	FDCAN_CCCR_CCE = 0x2
	// Position of ASM field.
	FDCAN_CCCR_ASM_Pos = 0x2
	// Bit mask of ASM field.
	FDCAN_CCCR_ASM_Msk = 0x4
	// Bit ASM.
	FDCAN_CCCR_ASM = 0x4
	// Position of CSA field.
	FDCAN_CCCR_CSA_Pos = 0x3
	// Bit mask of CSA field.
	FDCAN_CCCR_CSA_Msk = 0x8
	// Bit CSA.
	FDCAN_CCCR_CSA = 0x8
	// Position of CSR field.
	FDCAN_CCCR_CSR_Pos = 0x4
	// Bit mask of CSR field.
	FDCAN_CCCR_CSR_Msk = 0x10
	// Bit CSR.
	FDCAN_CCCR_CSR = 0x10
	// Position of MON field.
	FDCAN_CCCR_MON_Pos = 0x5
	// Bit mask of MON field.
	FDCAN_CCCR_MON_Msk = 0x20
	// Bit MON.
	FDCAN_CCCR_MON = 0x20
	// Position of DAR field.
	FDCAN_CCCR_DAR_Pos = 0x6
	// Bit mask of DAR field.
	FDCAN_CCCR_DAR_Msk = 0x40
	// Bit DAR.
	FDCAN_CCCR_DAR = 0x40
	// Position of TEST field.
	FDCAN_CCCR_TEST_Pos = 0x7
	// Bit mask of TEST field.
	FDCAN_CCCR_TEST_Msk = 0x80
	// Bit TEST.
	FDCAN_CCCR_TEST = 0x80
	// Position of FDOE field.
	FDCAN_CCCR_FDOE_Pos = 0x8
	// Bit mask of FDOE field.
	FDCAN_CCCR_FDOE_Msk = 0x100
	// Bit FDOE.
	FDCAN_CCCR_FDOE = 0x100
	// Position of BSE field.
	FDCAN_CCCR_BSE_Pos = 0x9
	// Bit mask of BSE field.
	FDCAN_CCCR_BSE_Msk = 0x200
	// Bit BSE.
	FDCAN_CCCR_BSE = 0x200
	// Position of PXHD field.
	FDCAN_CCCR_PXHD_Pos = 0xc
	// Bit mask of PXHD field.
	FDCAN_CCCR_PXHD_Msk = 0x1000
	// Bit PXHD.
	FDCAN_CCCR_PXHD = 0x1000
	// Position of EFBI field.
	FDCAN_CCCR_EFBI_Pos = 0xd
	// Bit mask of EFBI field.
	FDCAN_CCCR_EFBI_Msk = 0x2000
	// Bit EFBI.
	FDCAN_CCCR_EFBI = 0x2000
	// Position of TXP field.
	FDCAN_CCCR_TXP_Pos = 0xe
	// Bit mask of TXP field.
	FDCAN_CCCR_TXP_Msk = 0x4000
	// Bit TXP.
	FDCAN_CCCR_TXP = 0x4000
	// Position of NISO field.
	FDCAN_CCCR_NISO_Pos = 0xf
	// Bit mask of NISO field.
	FDCAN_CCCR_NISO_Msk = 0x8000
	// Bit NISO.
	FDCAN_CCCR_NISO = 0x8000

	// NBTP: FDCAN Nominal Bit Timing and Prescaler Register
	// Position of NSJW field.
	FDCAN_NBTP_NSJW_Pos = 0x19
	// Bit mask of NSJW field.
	FDCAN_NBTP_NSJW_Msk = 0xfe000000
	// Position of NBRP field.
	FDCAN_NBTP_NBRP_Pos = 0x10
	// Bit mask of NBRP field.
	FDCAN_NBTP_NBRP_Msk = 0x1ff0000
	// Position of NTSEG1 field.
	FDCAN_NBTP_NTSEG1_Pos = 0x8
	// Bit mask of NTSEG1 field.
	FDCAN_NBTP_NTSEG1_Msk = 0xff00
	// Position of TSEG2 field.
	FDCAN_NBTP_TSEG2_Pos = 0x0
	// Bit mask of TSEG2 field.
	FDCAN_NBTP_TSEG2_Msk = 0x7f

	// TSCC: FDCAN Timestamp Counter Configuration Register
	// Position of TCP field.
	FDCAN_TSCC_TCP_Pos = 0x10
	// Bit mask of TCP field.
	FDCAN_TSCC_TCP_Msk = 0xf0000
	// Position of TSS field.
	FDCAN_TSCC_TSS_Pos = 0x0
	// Bit mask of TSS field.
	FDCAN_TSCC_TSS_Msk = 0x3

	// TSCV: FDCAN Timestamp Counter Value Register
	// Position of TSC field.
	FDCAN_TSCV_TSC_Pos = 0x0
	// Bit mask of TSC field.
	FDCAN_TSCV_TSC_Msk = 0xffff

	// TOCC: FDCAN Timeout Counter Configuration Register
	// Position of ETOC field.
	FDCAN_TOCC_ETOC_Pos = 0x0
	// Bit mask of ETOC field.
	FDCAN_TOCC_ETOC_Msk = 0x1
	// Bit ETOC.
	FDCAN_TOCC_ETOC = 0x1
	// Position of TOS field.
	FDCAN_TOCC_TOS_Pos = 0x1
	// Bit mask of TOS field.
	FDCAN_TOCC_TOS_Msk = 0x6
	// Position of TOP field.
	FDCAN_TOCC_TOP_Pos = 0x10
	// Bit mask of TOP field.
	FDCAN_TOCC_TOP_Msk = 0xffff0000

	// TOCV: FDCAN Timeout Counter Value Register
	// Position of TOC field.
	FDCAN_TOCV_TOC_Pos = 0x0
	// Bit mask of TOC field.
	FDCAN_TOCV_TOC_Msk = 0xffff

	// ECR: FDCAN Error Counter Register
	// Position of CEL field.
	FDCAN_ECR_CEL_Pos = 0x10
	// Bit mask of CEL field.
	FDCAN_ECR_CEL_Msk = 0xff0000
	// Position of RP field.
	FDCAN_ECR_RP_Pos = 0xf
	// Bit mask of RP field.
	FDCAN_ECR_RP_Msk = 0x8000
	// Bit RP.
	FDCAN_ECR_RP = 0x8000
	// Position of REC field.
	FDCAN_ECR_REC_Pos = 0x8
	// Bit mask of REC field.
	FDCAN_ECR_REC_Msk = 0x7f00
	// Position of TEC field.
	FDCAN_ECR_TEC_Pos = 0x0
	// Bit mask of TEC field.
	FDCAN_ECR_TEC_Msk = 0xff

	// PSR: FDCAN Protocol Status Register
	// Position of LEC field.
	FDCAN_PSR_LEC_Pos = 0x0
	// Bit mask of LEC field.
	FDCAN_PSR_LEC_Msk = 0x7
	// Position of ACT field.
	FDCAN_PSR_ACT_Pos = 0x3
	// Bit mask of ACT field.
	FDCAN_PSR_ACT_Msk = 0x18
	// Position of EP field.
	FDCAN_PSR_EP_Pos = 0x5
	// Bit mask of EP field.
	FDCAN_PSR_EP_Msk = 0x20
	// Bit EP.
	FDCAN_PSR_EP = 0x20
	// Position of EW field.
	FDCAN_PSR_EW_Pos = 0x6
	// Bit mask of EW field.
	FDCAN_PSR_EW_Msk = 0x40
	// Bit EW.
	FDCAN_PSR_EW = 0x40
	// Position of BO field.
	FDCAN_PSR_BO_Pos = 0x7
	// Bit mask of BO field.
	FDCAN_PSR_BO_Msk = 0x80
	// Bit BO.
	FDCAN_PSR_BO = 0x80
	// Position of DLEC field.
	FDCAN_PSR_DLEC_Pos = 0x8
	// Bit mask of DLEC field.
	FDCAN_PSR_DLEC_Msk = 0x700
	// Position of RESI field.
	FDCAN_PSR_RESI_Pos = 0xb
	// Bit mask of RESI field.
	FDCAN_PSR_RESI_Msk = 0x800
	// Bit RESI.
	FDCAN_PSR_RESI = 0x800
	// Position of RBRS field.
	FDCAN_PSR_RBRS_Pos = 0xc
	// Bit mask of RBRS field.
	FDCAN_PSR_RBRS_Msk = 0x1000
	// Bit RBRS.
	FDCAN_PSR_RBRS = 0x1000
	// Position of REDL field.
	FDCAN_PSR_REDL_Pos = 0xd
	// Bit mask of REDL field.
	FDCAN_PSR_REDL_Msk = 0x2000
	// Bit REDL.
	FDCAN_PSR_REDL = 0x2000
	// Position of PXE field.
	FDCAN_PSR_PXE_Pos = 0xe
	// Bit mask of PXE field.
	FDCAN_PSR_PXE_Msk = 0x4000
	// Bit PXE.
	FDCAN_PSR_PXE = 0x4000
	// Position of TDCV field.
	FDCAN_PSR_TDCV_Pos = 0x10
	// Bit mask of TDCV field.
	FDCAN_PSR_TDCV_Msk = 0x7f0000

	// TDCR: FDCAN Transmitter Delay Compensation Register
	// Position of TDCF field.
	FDCAN_TDCR_TDCF_Pos = 0x0
	// Bit mask of TDCF field.
	FDCAN_TDCR_TDCF_Msk = 0x7f
	// Position of TDCO field.
	FDCAN_TDCR_TDCO_Pos = 0x8
	// Bit mask of TDCO field.
	FDCAN_TDCR_TDCO_Msk = 0x7f00

	// IR: FDCAN Interrupt Register
	// Position of RF0N field.
	FDCAN_IR_RF0N_Pos = 0x0
	// Bit mask of RF0N field.
	FDCAN_IR_RF0N_Msk = 0x1
	// Bit RF0N.
	FDCAN_IR_RF0N = 0x1
	// Position of RF0F field.
	FDCAN_IR_RF0F_Pos = 0x1
	// Bit mask of RF0F field.
	FDCAN_IR_RF0F_Msk = 0x2
	// Bit RF0F.
	FDCAN_IR_RF0F = 0x2
	// Position of RF0L field.
	FDCAN_IR_RF0L_Pos = 0x2
	// Bit mask of RF0L field.
	FDCAN_IR_RF0L_Msk = 0x4
	// Bit RF0L.
	FDCAN_IR_RF0L = 0x4
	// Position of RF1N field.
	FDCAN_IR_RF1N_Pos = 0x3
	// Bit mask of RF1N field.
	FDCAN_IR_RF1N_Msk = 0x8
	// Bit RF1N.
	FDCAN_IR_RF1N = 0x8
	// Position of RF1F field.
	FDCAN_IR_RF1F_Pos = 0x4
	// Bit mask of RF1F field.
	FDCAN_IR_RF1F_Msk = 0x10
	// Bit RF1F.
	FDCAN_IR_RF1F = 0x10
	// Position of RF1L field.
	FDCAN_IR_RF1L_Pos = 0x5
	// Bit mask of RF1L field.
	FDCAN_IR_RF1L_Msk = 0x20
	// Bit RF1L.
	FDCAN_IR_RF1L = 0x20
	// Position of HPM field.
	FDCAN_IR_HPM_Pos = 0x6
	// Bit mask of HPM field.
	FDCAN_IR_HPM_Msk = 0x40
	// Bit HPM.
	FDCAN_IR_HPM = 0x40
	// Position of TC field.
	FDCAN_IR_TC_Pos = 0x7
	// Bit mask of TC field.
	FDCAN_IR_TC_Msk = 0x80
	// Bit TC.
	FDCAN_IR_TC = 0x80
	// Position of TCF field.
	FDCAN_IR_TCF_Pos = 0x8
	// Bit mask of TCF field.
	FDCAN_IR_TCF_Msk = 0x100
	// Bit TCF.
	FDCAN_IR_TCF = 0x100
	// Position of TFE field.
	FDCAN_IR_TFE_Pos = 0x9
	// Bit mask of TFE field.
	FDCAN_IR_TFE_Msk = 0x200
	// Bit TFE.
	FDCAN_IR_TFE = 0x200
	// Position of TEFN field.
	FDCAN_IR_TEFN_Pos = 0xa
	// Bit mask of TEFN field.
	FDCAN_IR_TEFN_Msk = 0x400
	// Bit TEFN.
	FDCAN_IR_TEFN = 0x400
	// Position of TEFF field.
	FDCAN_IR_TEFF_Pos = 0xb
	// Bit mask of TEFF field.
	FDCAN_IR_TEFF_Msk = 0x800
	// Bit TEFF.
	FDCAN_IR_TEFF = 0x800
	// Position of TEFL field.
	FDCAN_IR_TEFL_Pos = 0xc
	// Bit mask of TEFL field.
	FDCAN_IR_TEFL_Msk = 0x1000
	// Bit TEFL.
	FDCAN_IR_TEFL = 0x1000
	// Position of TSW field.
	FDCAN_IR_TSW_Pos = 0xd
	// Bit mask of TSW field.
	FDCAN_IR_TSW_Msk = 0x2000
	// Bit TSW.
	FDCAN_IR_TSW = 0x2000
	// Position of MRAF field.
	FDCAN_IR_MRAF_Pos = 0xe
	// Bit mask of MRAF field.
	FDCAN_IR_MRAF_Msk = 0x4000
	// Bit MRAF.
	FDCAN_IR_MRAF = 0x4000
	// Position of TOO field.
	FDCAN_IR_TOO_Pos = 0xf
	// Bit mask of TOO field.
	FDCAN_IR_TOO_Msk = 0x8000
	// Bit TOO.
	FDCAN_IR_TOO = 0x8000
	// Position of ELO field.
	FDCAN_IR_ELO_Pos = 0x10
	// Bit mask of ELO field.
	FDCAN_IR_ELO_Msk = 0x10000
	// Bit ELO.
	FDCAN_IR_ELO = 0x10000
	// Position of EP field.
	FDCAN_IR_EP_Pos = 0x11
	// Bit mask of EP field.
	FDCAN_IR_EP_Msk = 0x20000
	// Bit EP.
	FDCAN_IR_EP = 0x20000
	// Position of EW field.
	FDCAN_IR_EW_Pos = 0x12
	// Bit mask of EW field.
	FDCAN_IR_EW_Msk = 0x40000
	// Bit EW.
	FDCAN_IR_EW = 0x40000
	// Position of BO field.
	FDCAN_IR_BO_Pos = 0x13
	// Bit mask of BO field.
	FDCAN_IR_BO_Msk = 0x80000
	// Bit BO.
	FDCAN_IR_BO = 0x80000
	// Position of WDI field.
	FDCAN_IR_WDI_Pos = 0x14
	// Bit mask of WDI field.
	FDCAN_IR_WDI_Msk = 0x100000
	// Bit WDI.
	FDCAN_IR_WDI = 0x100000
	// Position of PEA field.
	FDCAN_IR_PEA_Pos = 0x15
	// Bit mask of PEA field.
	FDCAN_IR_PEA_Msk = 0x200000
	// Bit PEA.
	FDCAN_IR_PEA = 0x200000
	// Position of PED field.
	FDCAN_IR_PED_Pos = 0x16
	// Bit mask of PED field.
	FDCAN_IR_PED_Msk = 0x400000
	// Bit PED.
	FDCAN_IR_PED = 0x400000
	// Position of ARA field.
	FDCAN_IR_ARA_Pos = 0x17
	// Bit mask of ARA field.
	FDCAN_IR_ARA_Msk = 0x800000
	// Bit ARA.
	FDCAN_IR_ARA = 0x800000

	// IE: FDCAN Interrupt Enable Register
	// Position of RF0NE field.
	FDCAN_IE_RF0NE_Pos = 0x0
	// Bit mask of RF0NE field.
	FDCAN_IE_RF0NE_Msk = 0x1
	// Bit RF0NE.
	FDCAN_IE_RF0NE = 0x1
	// Position of RF0FE field.
	FDCAN_IE_RF0FE_Pos = 0x1
	// Bit mask of RF0FE field.
	FDCAN_IE_RF0FE_Msk = 0x2
	// Bit RF0FE.
	FDCAN_IE_RF0FE = 0x2
	// Position of RF0LE field.
	FDCAN_IE_RF0LE_Pos = 0x2
	// Bit mask of RF0LE field.
	FDCAN_IE_RF0LE_Msk = 0x4
	// Bit RF0LE.
	FDCAN_IE_RF0LE = 0x4
	// Position of RF1NE field.
	FDCAN_IE_RF1NE_Pos = 0x3
	// Bit mask of RF1NE field.
	FDCAN_IE_RF1NE_Msk = 0x8
	// Bit RF1NE.
	FDCAN_IE_RF1NE = 0x8
	// Position of RF1FE field.
	FDCAN_IE_RF1FE_Pos = 0x4
	// Bit mask of RF1FE field.
	FDCAN_IE_RF1FE_Msk = 0x10
	// Bit RF1FE.
	FDCAN_IE_RF1FE = 0x10
	// Position of RF1LE field.
	FDCAN_IE_RF1LE_Pos = 0x5
	// Bit mask of RF1LE field.
	FDCAN_IE_RF1LE_Msk = 0x20
	// Bit RF1LE.
	FDCAN_IE_RF1LE = 0x20
	// Position of HPME field.
	FDCAN_IE_HPME_Pos = 0x6
	// Bit mask of HPME field.
	FDCAN_IE_HPME_Msk = 0x40
	// Bit HPME.
	FDCAN_IE_HPME = 0x40
	// Position of TCE field.
	FDCAN_IE_TCE_Pos = 0x7
	// Bit mask of TCE field.
	FDCAN_IE_TCE_Msk = 0x80
	// Bit TCE.
	FDCAN_IE_TCE = 0x80
	// Position of TCFE field.
	FDCAN_IE_TCFE_Pos = 0x8
	// Bit mask of TCFE field.
	FDCAN_IE_TCFE_Msk = 0x100
	// Bit TCFE.
	FDCAN_IE_TCFE = 0x100
	// Position of TEFE field.
	FDCAN_IE_TEFE_Pos = 0x9
	// Bit mask of TEFE field.
	FDCAN_IE_TEFE_Msk = 0x200
	// Bit TEFE.
	FDCAN_IE_TEFE = 0x200
	// Position of TEFNE field.
	FDCAN_IE_TEFNE_Pos = 0xa
	// Bit mask of TEFNE field.
	FDCAN_IE_TEFNE_Msk = 0x400
	// Bit TEFNE.
	FDCAN_IE_TEFNE = 0x400
	// Position of TEFFE field.
	FDCAN_IE_TEFFE_Pos = 0xb
	// Bit mask of TEFFE field.
	FDCAN_IE_TEFFE_Msk = 0x800
	// Bit TEFFE.
	FDCAN_IE_TEFFE = 0x800
	// Position of TEFLE field.
	FDCAN_IE_TEFLE_Pos = 0xc
	// Bit mask of TEFLE field.
	FDCAN_IE_TEFLE_Msk = 0x1000
	// Bit TEFLE.
	FDCAN_IE_TEFLE = 0x1000
	// Position of MRAFE field.
	FDCAN_IE_MRAFE_Pos = 0xd
	// Bit mask of MRAFE field.
	FDCAN_IE_MRAFE_Msk = 0x2000
	// Bit MRAFE.
	FDCAN_IE_MRAFE = 0x2000
	// Position of TOOE field.
	FDCAN_IE_TOOE_Pos = 0xe
	// Bit mask of TOOE field.
	FDCAN_IE_TOOE_Msk = 0x4000
	// Bit TOOE.
	FDCAN_IE_TOOE = 0x4000
	// Position of ELOE field.
	FDCAN_IE_ELOE_Pos = 0xf
	// Bit mask of ELOE field.
	FDCAN_IE_ELOE_Msk = 0x8000
	// Bit ELOE.
	FDCAN_IE_ELOE = 0x8000
	// Position of EPE field.
	FDCAN_IE_EPE_Pos = 0x10
	// Bit mask of EPE field.
	FDCAN_IE_EPE_Msk = 0x10000
	// Bit EPE.
	FDCAN_IE_EPE = 0x10000
	// Position of EWE field.
	FDCAN_IE_EWE_Pos = 0x11
	// Bit mask of EWE field.
	FDCAN_IE_EWE_Msk = 0x20000
	// Bit EWE.
	FDCAN_IE_EWE = 0x20000
	// Position of BOE field.
	FDCAN_IE_BOE_Pos = 0x12
	// Bit mask of BOE field.
	FDCAN_IE_BOE_Msk = 0x40000
	// Bit BOE.
	FDCAN_IE_BOE = 0x40000
	// Position of WDIE field.
	FDCAN_IE_WDIE_Pos = 0x13
	// Bit mask of WDIE field.
	FDCAN_IE_WDIE_Msk = 0x80000
	// Bit WDIE.
	FDCAN_IE_WDIE = 0x80000
	// Position of PEAE field.
	FDCAN_IE_PEAE_Pos = 0x14
	// Bit mask of PEAE field.
	FDCAN_IE_PEAE_Msk = 0x100000
	// Bit PEAE.
	FDCAN_IE_PEAE = 0x100000
	// Position of PEDE field.
	FDCAN_IE_PEDE_Pos = 0x15
	// Bit mask of PEDE field.
	FDCAN_IE_PEDE_Msk = 0x200000
	// Bit PEDE.
	FDCAN_IE_PEDE = 0x200000
	// Position of ARAE field.
	FDCAN_IE_ARAE_Pos = 0x16
	// Bit mask of ARAE field.
	FDCAN_IE_ARAE_Msk = 0x400000
	// Bit ARAE.
	FDCAN_IE_ARAE = 0x400000

	// ILS: FDCAN Interrupt Line Select Register
	// Position of RxFIFO0 field.
	FDCAN_ILS_RxFIFO0_Pos = 0x0
	// Bit mask of RxFIFO0 field.
	FDCAN_ILS_RxFIFO0_Msk = 0x1
	// Bit RxFIFO0.
	FDCAN_ILS_RxFIFO0 = 0x1
	// Position of RxFIFO1 field.
	FDCAN_ILS_RxFIFO1_Pos = 0x1
	// Bit mask of RxFIFO1 field.
	FDCAN_ILS_RxFIFO1_Msk = 0x2
	// Bit RxFIFO1.
	FDCAN_ILS_RxFIFO1 = 0x2
	// Position of SMSG field.
	FDCAN_ILS_SMSG_Pos = 0x2
	// Bit mask of SMSG field.
	FDCAN_ILS_SMSG_Msk = 0x4
	// Bit SMSG.
	FDCAN_ILS_SMSG = 0x4
	// Position of TFERR field.
	FDCAN_ILS_TFERR_Pos = 0x3
	// Bit mask of TFERR field.
	FDCAN_ILS_TFERR_Msk = 0x8
	// Bit TFERR.
	FDCAN_ILS_TFERR = 0x8
	// Position of MISC field.
	FDCAN_ILS_MISC_Pos = 0x4
	// Bit mask of MISC field.
	FDCAN_ILS_MISC_Msk = 0x10
	// Bit MISC.
	FDCAN_ILS_MISC = 0x10
	// Position of BERR field.
	FDCAN_ILS_BERR_Pos = 0x5
	// Bit mask of BERR field.
	FDCAN_ILS_BERR_Msk = 0x20
	// Bit BERR.
	FDCAN_ILS_BERR = 0x20
	// Position of PERR field.
	FDCAN_ILS_PERR_Pos = 0x6
	// Bit mask of PERR field.
	FDCAN_ILS_PERR_Msk = 0x40
	// Bit PERR.
	FDCAN_ILS_PERR = 0x40

	// ILE: FDCAN Interrupt Line Enable Register
	// Position of EINT0 field.
	FDCAN_ILE_EINT0_Pos = 0x0
	// Bit mask of EINT0 field.
	FDCAN_ILE_EINT0_Msk = 0x1
	// Bit EINT0.
	FDCAN_ILE_EINT0 = 0x1
	// Position of EINT1 field.
	FDCAN_ILE_EINT1_Pos = 0x1
	// Bit mask of EINT1 field.
	FDCAN_ILE_EINT1_Msk = 0x2
	// Bit EINT1.
	FDCAN_ILE_EINT1 = 0x2

	// RXGFC: FDCAN Global Filter Configuration Register
	// Position of RRFE field.
	FDCAN_RXGFC_RRFE_Pos = 0x0
	// Bit mask of RRFE field.
	FDCAN_RXGFC_RRFE_Msk = 0x1
	// Bit RRFE.
	FDCAN_RXGFC_RRFE = 0x1
	// Position of RRFS field.
	FDCAN_RXGFC_RRFS_Pos = 0x1
	// Bit mask of RRFS field.
	FDCAN_RXGFC_RRFS_Msk = 0x2
	// Bit RRFS.
	FDCAN_RXGFC_RRFS = 0x2
	// Position of ANFE field.
	FDCAN_RXGFC_ANFE_Pos = 0x2
	// Bit mask of ANFE field.
	FDCAN_RXGFC_ANFE_Msk = 0xc
	// Position of ANFS field.
	FDCAN_RXGFC_ANFS_Pos = 0x4
	// Bit mask of ANFS field.
	FDCAN_RXGFC_ANFS_Msk = 0x30
	// Position of F1OM field.
	FDCAN_RXGFC_F1OM_Pos = 0x8
	// Bit mask of F1OM field.
	FDCAN_RXGFC_F1OM_Msk = 0x100
	// Bit F1OM.
	FDCAN_RXGFC_F1OM = 0x100
	// Position of F0OM field.
	FDCAN_RXGFC_F0OM_Pos = 0x9
	// Bit mask of F0OM field.
	FDCAN_RXGFC_F0OM_Msk = 0x200
	// Bit F0OM.
	FDCAN_RXGFC_F0OM = 0x200
	// Position of LSS field.
	FDCAN_RXGFC_LSS_Pos = 0x10
	// Bit mask of LSS field.
	FDCAN_RXGFC_LSS_Msk = 0x1f0000
	// Position of LSE field.
	FDCAN_RXGFC_LSE_Pos = 0x18
	// Bit mask of LSE field.
	FDCAN_RXGFC_LSE_Msk = 0xf000000

	// XIDAM: FDCAN Extended ID and Mask Register
	// Position of EIDM field.
	FDCAN_XIDAM_EIDM_Pos = 0x0
	// Bit mask of EIDM field.
	FDCAN_XIDAM_EIDM_Msk = 0x1fffffff

	// HPMS: FDCAN High Priority Message Status Register
	// Position of BIDX field.
	FDCAN_HPMS_BIDX_Pos = 0x0
	// Bit mask of BIDX field.
	FDCAN_HPMS_BIDX_Msk = 0x7
	// Position of MSI field.
	FDCAN_HPMS_MSI_Pos = 0x6
	// Bit mask of MSI field.
	FDCAN_HPMS_MSI_Msk = 0xc0
	// Position of FIDX field.
	FDCAN_HPMS_FIDX_Pos = 0x8
	// Bit mask of FIDX field.
	FDCAN_HPMS_FIDX_Msk = 0x1f00
	// Position of FLST field.
	FDCAN_HPMS_FLST_Pos = 0xf
	// Bit mask of FLST field.
	FDCAN_HPMS_FLST_Msk = 0x8000
	// Bit FLST.
	FDCAN_HPMS_FLST = 0x8000

	// RXF0S: FDCAN Rx FIFO 0 Status Register
	// Position of F0FL field.
	FDCAN_RXF0S_F0FL_Pos = 0x0
	// Bit mask of F0FL field.
	FDCAN_RXF0S_F0FL_Msk = 0xf
	// Position of F0GI field.
	FDCAN_RXF0S_F0GI_Pos = 0x8
	// Bit mask of F0GI field.
	FDCAN_RXF0S_F0GI_Msk = 0x300
	// Position of F0PI field.
	FDCAN_RXF0S_F0PI_Pos = 0x10
	// Bit mask of F0PI field.
	FDCAN_RXF0S_F0PI_Msk = 0x30000
	// Position of F0F field.
	FDCAN_RXF0S_F0F_Pos = 0x18
	// Bit mask of F0F field.
	FDCAN_RXF0S_F0F_Msk = 0x1000000
	// Bit F0F.
	FDCAN_RXF0S_F0F = 0x1000000
	// Position of RF0L field.
	FDCAN_RXF0S_RF0L_Pos = 0x19
	// Bit mask of RF0L field.
	FDCAN_RXF0S_RF0L_Msk = 0x2000000
	// Bit RF0L.
	FDCAN_RXF0S_RF0L = 0x2000000

	// RXF0A: CAN Rx FIFO 0 Acknowledge Register
	// Position of F0AI field.
	FDCAN_RXF0A_F0AI_Pos = 0x0
	// Bit mask of F0AI field.
	FDCAN_RXF0A_F0AI_Msk = 0x7

	// RXF1S: FDCAN Rx FIFO 1 Status Register
	// Position of F1FL field.
	FDCAN_RXF1S_F1FL_Pos = 0x0
	// Bit mask of F1FL field.
	FDCAN_RXF1S_F1FL_Msk = 0xf
	// Position of F1GI field.
	FDCAN_RXF1S_F1GI_Pos = 0x8
	// Bit mask of F1GI field.
	FDCAN_RXF1S_F1GI_Msk = 0x300
	// Position of F1PI field.
	FDCAN_RXF1S_F1PI_Pos = 0x10
	// Bit mask of F1PI field.
	FDCAN_RXF1S_F1PI_Msk = 0x30000
	// Position of F1F field.
	FDCAN_RXF1S_F1F_Pos = 0x18
	// Bit mask of F1F field.
	FDCAN_RXF1S_F1F_Msk = 0x1000000
	// Bit F1F.
	FDCAN_RXF1S_F1F = 0x1000000
	// Position of RF1L field.
	FDCAN_RXF1S_RF1L_Pos = 0x19
	// Bit mask of RF1L field.
	FDCAN_RXF1S_RF1L_Msk = 0x2000000
	// Bit RF1L.
	FDCAN_RXF1S_RF1L = 0x2000000

	// RXF1A: FDCAN Rx FIFO 1 Acknowledge Register
	// Position of F1AI field.
	FDCAN_RXF1A_F1AI_Pos = 0x0
	// Bit mask of F1AI field.
	FDCAN_RXF1A_F1AI_Msk = 0x7

	// TXBC: FDCAN Tx buffer configuration register
	// Position of TFQM field.
	FDCAN_TXBC_TFQM_Pos = 0x18
	// Bit mask of TFQM field.
	FDCAN_TXBC_TFQM_Msk = 0x1000000
	// Bit TFQM.
	FDCAN_TXBC_TFQM = 0x1000000

	// TXFQS: FDCAN Tx FIFO/Queue Status Register
	// Position of TFFL field.
	FDCAN_TXFQS_TFFL_Pos = 0x0
	// Bit mask of TFFL field.
	FDCAN_TXFQS_TFFL_Msk = 0x7
	// Position of TFGI field.
	FDCAN_TXFQS_TFGI_Pos = 0x8
	// Bit mask of TFGI field.
	FDCAN_TXFQS_TFGI_Msk = 0x300
	// Position of TFQPI field.
	FDCAN_TXFQS_TFQPI_Pos = 0x10
	// Bit mask of TFQPI field.
	FDCAN_TXFQS_TFQPI_Msk = 0x30000
	// Position of TFQF field.
	FDCAN_TXFQS_TFQF_Pos = 0x15
	// Bit mask of TFQF field.
	FDCAN_TXFQS_TFQF_Msk = 0x200000
	// Bit TFQF.
	FDCAN_TXFQS_TFQF = 0x200000

	// TXBRP: FDCAN Tx Buffer Request Pending Register
	// Position of TRP field.
	FDCAN_TXBRP_TRP_Pos = 0x0
	// Bit mask of TRP field.
	FDCAN_TXBRP_TRP_Msk = 0x7

	// TXBAR: FDCAN Tx Buffer Add Request Register
	// Position of AR field.
	FDCAN_TXBAR_AR_Pos = 0x0
	// Bit mask of AR field.
	FDCAN_TXBAR_AR_Msk = 0x7

	// TXBCR: FDCAN Tx Buffer Cancellation Request Register
	// Position of CR field.
	FDCAN_TXBCR_CR_Pos = 0x0
	// Bit mask of CR field.
	FDCAN_TXBCR_CR_Msk = 0x7

	// TXBTO: FDCAN Tx Buffer Transmission Occurred Register
	// Position of TO field.
	FDCAN_TXBTO_TO_Pos = 0x0
	// Bit mask of TO field.
	FDCAN_TXBTO_TO_Msk = 0x7

	// TXBCF: FDCAN Tx Buffer Cancellation Finished Register
	// Position of CF field.
	FDCAN_TXBCF_CF_Pos = 0x0
	// Bit mask of CF field.
	FDCAN_TXBCF_CF_Msk = 0x7

	// TXBTIE: FDCAN Tx Buffer Transmission Interrupt Enable Register
	// Position of TIE field.
	FDCAN_TXBTIE_TIE_Pos = 0x0
	// Bit mask of TIE field.
	FDCAN_TXBTIE_TIE_Msk = 0x7

	// TXBCIE: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
	// Position of CF field.
	FDCAN_TXBCIE_CF_Pos = 0x0
	// Bit mask of CF field.
	FDCAN_TXBCIE_CF_Msk = 0x7

	// TXEFS: FDCAN Tx Event FIFO Status Register
	// Position of EFFL field.
	FDCAN_TXEFS_EFFL_Pos = 0x0
	// Bit mask of EFFL field.
	FDCAN_TXEFS_EFFL_Msk = 0x7
	// Position of EFGI field.
	FDCAN_TXEFS_EFGI_Pos = 0x8
	// Bit mask of EFGI field.
	FDCAN_TXEFS_EFGI_Msk = 0x300
	// Position of EFF field.
	FDCAN_TXEFS_EFF_Pos = 0x18
	// Bit mask of EFF field.
	FDCAN_TXEFS_EFF_Msk = 0x1000000
	// Bit EFF.
	FDCAN_TXEFS_EFF = 0x1000000
	// Position of TEFL field.
	FDCAN_TXEFS_TEFL_Pos = 0x19
	// Bit mask of TEFL field.
	FDCAN_TXEFS_TEFL_Msk = 0x2000000
	// Bit TEFL.
	FDCAN_TXEFS_TEFL = 0x2000000
	// Position of EFPI field.
	FDCAN_TXEFS_EFPI_Pos = 0x10
	// Bit mask of EFPI field.
	FDCAN_TXEFS_EFPI_Msk = 0x30000

	// TXEFA: FDCAN Tx Event FIFO Acknowledge Register
	// Position of EFAI field.
	FDCAN_TXEFA_EFAI_Pos = 0x0
	// Bit mask of EFAI field.
	FDCAN_TXEFA_EFAI_Msk = 0x3

	// CKDIV: FDCAN TT Trigger Memory Configuration Register
	// Position of PDIV field.
	FDCAN_CKDIV_PDIV_Pos = 0x0
	// Bit mask of PDIV field.
	FDCAN_CKDIV_PDIV_Msk = 0xf
)

// Constants for FLASH: Flash
const (
	// ACR: Access control register
	// Position of LATENCY field.
	Flash_ACR_LATENCY_Pos = 0x0
	// Bit mask of LATENCY field.
	Flash_ACR_LATENCY_Msk = 0xf
	// Position of RUN_PD field.
	Flash_ACR_RUN_PD_Pos = 0xd
	// Bit mask of RUN_PD field.
	Flash_ACR_RUN_PD_Msk = 0x2000
	// Bit RUN_PD.
	Flash_ACR_RUN_PD = 0x2000
	// Position of SLEEP_PD field.
	Flash_ACR_SLEEP_PD_Pos = 0xe
	// Bit mask of SLEEP_PD field.
	Flash_ACR_SLEEP_PD_Msk = 0x4000
	// Bit SLEEP_PD.
	Flash_ACR_SLEEP_PD = 0x4000
	// Position of LVEN field.
	Flash_ACR_LVEN_Pos = 0xf
	// Bit mask of LVEN field.
	Flash_ACR_LVEN_Msk = 0x8000
	// Bit LVEN.
	Flash_ACR_LVEN = 0x8000

	// PDKEYR: Power down key register
	// Position of PDKEYR field.
	Flash_PDKEYR_PDKEYR_Pos = 0x0
	// Bit mask of PDKEYR field.
	Flash_PDKEYR_PDKEYR_Msk = 0xffffffff

	// NSKEYR: Flash non-secure key register
	// Position of NSKEYR field.
	Flash_NSKEYR_NSKEYR_Pos = 0x0
	// Bit mask of NSKEYR field.
	Flash_NSKEYR_NSKEYR_Msk = 0xffffffff

	// SECKEYR: Flash secure key register
	// Position of SECKEYR field.
	Flash_SECKEYR_SECKEYR_Pos = 0x0
	// Bit mask of SECKEYR field.
	Flash_SECKEYR_SECKEYR_Msk = 0xffffffff

	// OPTKEYR: Flash option key register
	// Position of OPTKEYR field.
	Flash_OPTKEYR_OPTKEYR_Pos = 0x0
	// Bit mask of OPTKEYR field.
	Flash_OPTKEYR_OPTKEYR_Msk = 0xffffffff

	// LVEKEYR: Flash low voltage key register
	// Position of LVEKEYR field.
	Flash_LVEKEYR_LVEKEYR_Pos = 0x0
	// Bit mask of LVEKEYR field.
	Flash_LVEKEYR_LVEKEYR_Msk = 0xffffffff

	// NSSR: Flash status register
	// Position of NSEOP field.
	Flash_NSSR_NSEOP_Pos = 0x0
	// Bit mask of NSEOP field.
	Flash_NSSR_NSEOP_Msk = 0x1
	// Bit NSEOP.
	Flash_NSSR_NSEOP = 0x1
	// Position of NSOPERR field.
	Flash_NSSR_NSOPERR_Pos = 0x1
	// Bit mask of NSOPERR field.
	Flash_NSSR_NSOPERR_Msk = 0x2
	// Bit NSOPERR.
	Flash_NSSR_NSOPERR = 0x2
	// Position of NSPROGERR field.
	Flash_NSSR_NSPROGERR_Pos = 0x3
	// Bit mask of NSPROGERR field.
	Flash_NSSR_NSPROGERR_Msk = 0x8
	// Bit NSPROGERR.
	Flash_NSSR_NSPROGERR = 0x8
	// Position of NSWRPERR field.
	Flash_NSSR_NSWRPERR_Pos = 0x4
	// Bit mask of NSWRPERR field.
	Flash_NSSR_NSWRPERR_Msk = 0x10
	// Bit NSWRPERR.
	Flash_NSSR_NSWRPERR = 0x10
	// Position of NSPGAERR field.
	Flash_NSSR_NSPGAERR_Pos = 0x5
	// Bit mask of NSPGAERR field.
	Flash_NSSR_NSPGAERR_Msk = 0x20
	// Bit NSPGAERR.
	Flash_NSSR_NSPGAERR = 0x20
	// Position of NSSIZERR field.
	Flash_NSSR_NSSIZERR_Pos = 0x6
	// Bit mask of NSSIZERR field.
	Flash_NSSR_NSSIZERR_Msk = 0x40
	// Bit NSSIZERR.
	Flash_NSSR_NSSIZERR = 0x40
	// Position of NSPGSERR field.
	Flash_NSSR_NSPGSERR_Pos = 0x7
	// Bit mask of NSPGSERR field.
	Flash_NSSR_NSPGSERR_Msk = 0x80
	// Bit NSPGSERR.
	Flash_NSSR_NSPGSERR = 0x80
	// Position of OPTWERR field.
	Flash_NSSR_OPTWERR_Pos = 0xd
	// Bit mask of OPTWERR field.
	Flash_NSSR_OPTWERR_Msk = 0x2000
	// Bit OPTWERR.
	Flash_NSSR_OPTWERR = 0x2000
	// Position of OPTVERR field.
	Flash_NSSR_OPTVERR_Pos = 0xf
	// Bit mask of OPTVERR field.
	Flash_NSSR_OPTVERR_Msk = 0x8000
	// Bit OPTVERR.
	Flash_NSSR_OPTVERR = 0x8000
	// Position of NSBSY field.
	Flash_NSSR_NSBSY_Pos = 0x10
	// Bit mask of NSBSY field.
	Flash_NSSR_NSBSY_Msk = 0x10000
	// Bit NSBSY.
	Flash_NSSR_NSBSY = 0x10000

	// SECSR: Flash status register
	// Position of SECEOP field.
	Flash_SECSR_SECEOP_Pos = 0x0
	// Bit mask of SECEOP field.
	Flash_SECSR_SECEOP_Msk = 0x1
	// Bit SECEOP.
	Flash_SECSR_SECEOP = 0x1
	// Position of SECOPERR field.
	Flash_SECSR_SECOPERR_Pos = 0x1
	// Bit mask of SECOPERR field.
	Flash_SECSR_SECOPERR_Msk = 0x2
	// Bit SECOPERR.
	Flash_SECSR_SECOPERR = 0x2
	// Position of SECPROGERR field.
	Flash_SECSR_SECPROGERR_Pos = 0x3
	// Bit mask of SECPROGERR field.
	Flash_SECSR_SECPROGERR_Msk = 0x8
	// Bit SECPROGERR.
	Flash_SECSR_SECPROGERR = 0x8
	// Position of SECWRPERR field.
	Flash_SECSR_SECWRPERR_Pos = 0x4
	// Bit mask of SECWRPERR field.
	Flash_SECSR_SECWRPERR_Msk = 0x10
	// Bit SECWRPERR.
	Flash_SECSR_SECWRPERR = 0x10
	// Position of SECPGAERR field.
	Flash_SECSR_SECPGAERR_Pos = 0x5
	// Bit mask of SECPGAERR field.
	Flash_SECSR_SECPGAERR_Msk = 0x20
	// Bit SECPGAERR.
	Flash_SECSR_SECPGAERR = 0x20
	// Position of SECSIZERR field.
	Flash_SECSR_SECSIZERR_Pos = 0x6
	// Bit mask of SECSIZERR field.
	Flash_SECSR_SECSIZERR_Msk = 0x40
	// Bit SECSIZERR.
	Flash_SECSR_SECSIZERR = 0x40
	// Position of SECPGSERR field.
	Flash_SECSR_SECPGSERR_Pos = 0x7
	// Bit mask of SECPGSERR field.
	Flash_SECSR_SECPGSERR_Msk = 0x80
	// Bit SECPGSERR.
	Flash_SECSR_SECPGSERR = 0x80
	// Position of SECRDERR field.
	Flash_SECSR_SECRDERR_Pos = 0xe
	// Bit mask of SECRDERR field.
	Flash_SECSR_SECRDERR_Msk = 0x4000
	// Bit SECRDERR.
	Flash_SECSR_SECRDERR = 0x4000
	// Position of SECBSY field.
	Flash_SECSR_SECBSY_Pos = 0x10
	// Bit mask of SECBSY field.
	Flash_SECSR_SECBSY_Msk = 0x10000
	// Bit SECBSY.
	Flash_SECSR_SECBSY = 0x10000

	// NSCR: Flash non-secure control register
	// Position of NSPG field.
	Flash_NSCR_NSPG_Pos = 0x0
	// Bit mask of NSPG field.
	Flash_NSCR_NSPG_Msk = 0x1
	// Bit NSPG.
	Flash_NSCR_NSPG = 0x1
	// Position of NSPER field.
	Flash_NSCR_NSPER_Pos = 0x1
	// Bit mask of NSPER field.
	Flash_NSCR_NSPER_Msk = 0x2
	// Bit NSPER.
	Flash_NSCR_NSPER = 0x2
	// Position of NSMER1 field.
	Flash_NSCR_NSMER1_Pos = 0x2
	// Bit mask of NSMER1 field.
	Flash_NSCR_NSMER1_Msk = 0x4
	// Bit NSMER1.
	Flash_NSCR_NSMER1 = 0x4
	// Position of NSPNB field.
	Flash_NSCR_NSPNB_Pos = 0x3
	// Bit mask of NSPNB field.
	Flash_NSCR_NSPNB_Msk = 0x3f8
	// Position of NSBKER field.
	Flash_NSCR_NSBKER_Pos = 0xb
	// Bit mask of NSBKER field.
	Flash_NSCR_NSBKER_Msk = 0x800
	// Bit NSBKER.
	Flash_NSCR_NSBKER = 0x800
	// Position of NSMER2 field.
	Flash_NSCR_NSMER2_Pos = 0xf
	// Bit mask of NSMER2 field.
	Flash_NSCR_NSMER2_Msk = 0x8000
	// Bit NSMER2.
	Flash_NSCR_NSMER2 = 0x8000
	// Position of NSSTRT field.
	Flash_NSCR_NSSTRT_Pos = 0x10
	// Bit mask of NSSTRT field.
	Flash_NSCR_NSSTRT_Msk = 0x10000
	// Bit NSSTRT.
	Flash_NSCR_NSSTRT = 0x10000
	// Position of OPTSTRT field.
	Flash_NSCR_OPTSTRT_Pos = 0x11
	// Bit mask of OPTSTRT field.
	Flash_NSCR_OPTSTRT_Msk = 0x20000
	// Bit OPTSTRT.
	Flash_NSCR_OPTSTRT = 0x20000
	// Position of NSEOPIE field.
	Flash_NSCR_NSEOPIE_Pos = 0x18
	// Bit mask of NSEOPIE field.
	Flash_NSCR_NSEOPIE_Msk = 0x1000000
	// Bit NSEOPIE.
	Flash_NSCR_NSEOPIE = 0x1000000
	// Position of NSERRIE field.
	Flash_NSCR_NSERRIE_Pos = 0x19
	// Bit mask of NSERRIE field.
	Flash_NSCR_NSERRIE_Msk = 0x2000000
	// Bit NSERRIE.
	Flash_NSCR_NSERRIE = 0x2000000
	// Position of OBL_LAUNCH field.
	Flash_NSCR_OBL_LAUNCH_Pos = 0x1b
	// Bit mask of OBL_LAUNCH field.
	Flash_NSCR_OBL_LAUNCH_Msk = 0x8000000
	// Bit OBL_LAUNCH.
	Flash_NSCR_OBL_LAUNCH = 0x8000000
	// Position of OPTLOCK field.
	Flash_NSCR_OPTLOCK_Pos = 0x1e
	// Bit mask of OPTLOCK field.
	Flash_NSCR_OPTLOCK_Msk = 0x40000000
	// Bit OPTLOCK.
	Flash_NSCR_OPTLOCK = 0x40000000
	// Position of NSLOCK field.
	Flash_NSCR_NSLOCK_Pos = 0x1f
	// Bit mask of NSLOCK field.
	Flash_NSCR_NSLOCK_Msk = 0x80000000
	// Bit NSLOCK.
	Flash_NSCR_NSLOCK = 0x80000000

	// SECCR: Flash secure control register
	// Position of SECPG field.
	Flash_SECCR_SECPG_Pos = 0x0
	// Bit mask of SECPG field.
	Flash_SECCR_SECPG_Msk = 0x1
	// Bit SECPG.
	Flash_SECCR_SECPG = 0x1
	// Position of SECPER field.
	Flash_SECCR_SECPER_Pos = 0x1
	// Bit mask of SECPER field.
	Flash_SECCR_SECPER_Msk = 0x2
	// Bit SECPER.
	Flash_SECCR_SECPER = 0x2
	// Position of SECMER1 field.
	Flash_SECCR_SECMER1_Pos = 0x2
	// Bit mask of SECMER1 field.
	Flash_SECCR_SECMER1_Msk = 0x4
	// Bit SECMER1.
	Flash_SECCR_SECMER1 = 0x4
	// Position of SECPNB field.
	Flash_SECCR_SECPNB_Pos = 0x3
	// Bit mask of SECPNB field.
	Flash_SECCR_SECPNB_Msk = 0x3f8
	// Position of SECBKER field.
	Flash_SECCR_SECBKER_Pos = 0xb
	// Bit mask of SECBKER field.
	Flash_SECCR_SECBKER_Msk = 0x800
	// Bit SECBKER.
	Flash_SECCR_SECBKER = 0x800
	// Position of SECMER2 field.
	Flash_SECCR_SECMER2_Pos = 0xf
	// Bit mask of SECMER2 field.
	Flash_SECCR_SECMER2_Msk = 0x8000
	// Bit SECMER2.
	Flash_SECCR_SECMER2 = 0x8000
	// Position of SECSTRT field.
	Flash_SECCR_SECSTRT_Pos = 0x10
	// Bit mask of SECSTRT field.
	Flash_SECCR_SECSTRT_Msk = 0x10000
	// Bit SECSTRT.
	Flash_SECCR_SECSTRT = 0x10000
	// Position of SECEOPIE field.
	Flash_SECCR_SECEOPIE_Pos = 0x18
	// Bit mask of SECEOPIE field.
	Flash_SECCR_SECEOPIE_Msk = 0x1000000
	// Bit SECEOPIE.
	Flash_SECCR_SECEOPIE = 0x1000000
	// Position of SECERRIE field.
	Flash_SECCR_SECERRIE_Pos = 0x19
	// Bit mask of SECERRIE field.
	Flash_SECCR_SECERRIE_Msk = 0x2000000
	// Bit SECERRIE.
	Flash_SECCR_SECERRIE = 0x2000000
	// Position of SECRDERRIE field.
	Flash_SECCR_SECRDERRIE_Pos = 0x1a
	// Bit mask of SECRDERRIE field.
	Flash_SECCR_SECRDERRIE_Msk = 0x4000000
	// Bit SECRDERRIE.
	Flash_SECCR_SECRDERRIE = 0x4000000
	// Position of SECINV field.
	Flash_SECCR_SECINV_Pos = 0x1d
	// Bit mask of SECINV field.
	Flash_SECCR_SECINV_Msk = 0x20000000
	// Bit SECINV.
	Flash_SECCR_SECINV = 0x20000000
	// Position of SECLOCK field.
	Flash_SECCR_SECLOCK_Pos = 0x1f
	// Bit mask of SECLOCK field.
	Flash_SECCR_SECLOCK_Msk = 0x80000000
	// Bit SECLOCK.
	Flash_SECCR_SECLOCK = 0x80000000

	// ECCR: Flash ECC register
	// Position of ADDR_ECC field.
	Flash_ECCR_ADDR_ECC_Pos = 0x0
	// Bit mask of ADDR_ECC field.
	Flash_ECCR_ADDR_ECC_Msk = 0x7ffff
	// Position of BK_ECC field.
	Flash_ECCR_BK_ECC_Pos = 0x15
	// Bit mask of BK_ECC field.
	Flash_ECCR_BK_ECC_Msk = 0x200000
	// Bit BK_ECC.
	Flash_ECCR_BK_ECC = 0x200000
	// Position of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC_Pos = 0x16
	// Bit mask of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC_Msk = 0x400000
	// Bit SYSF_ECC.
	Flash_ECCR_SYSF_ECC = 0x400000
	// Position of ECCIE field.
	Flash_ECCR_ECCIE_Pos = 0x18
	// Bit mask of ECCIE field.
	Flash_ECCR_ECCIE_Msk = 0x1000000
	// Bit ECCIE.
	Flash_ECCR_ECCIE = 0x1000000
	// Position of ECCC2 field.
	Flash_ECCR_ECCC2_Pos = 0x1c
	// Bit mask of ECCC2 field.
	Flash_ECCR_ECCC2_Msk = 0x10000000
	// Bit ECCC2.
	Flash_ECCR_ECCC2 = 0x10000000
	// Position of ECCD2 field.
	Flash_ECCR_ECCD2_Pos = 0x1d
	// Bit mask of ECCD2 field.
	Flash_ECCR_ECCD2_Msk = 0x20000000
	// Bit ECCD2.
	Flash_ECCR_ECCD2 = 0x20000000
	// Position of ECCC field.
	Flash_ECCR_ECCC_Pos = 0x1e
	// Bit mask of ECCC field.
	Flash_ECCR_ECCC_Msk = 0x40000000
	// Bit ECCC.
	Flash_ECCR_ECCC = 0x40000000
	// Position of ECCD field.
	Flash_ECCR_ECCD_Pos = 0x1f
	// Bit mask of ECCD field.
	Flash_ECCR_ECCD_Msk = 0x80000000
	// Bit ECCD.
	Flash_ECCR_ECCD = 0x80000000

	// OPTR: Flash option register
	// Position of RDP field.
	Flash_OPTR_RDP_Pos = 0x0
	// Bit mask of RDP field.
	Flash_OPTR_RDP_Msk = 0xff
	// Position of BOR_LEV field.
	Flash_OPTR_BOR_LEV_Pos = 0x8
	// Bit mask of BOR_LEV field.
	Flash_OPTR_BOR_LEV_Msk = 0x700
	// Position of NRST_STOP field.
	Flash_OPTR_NRST_STOP_Pos = 0xc
	// Bit mask of NRST_STOP field.
	Flash_OPTR_NRST_STOP_Msk = 0x1000
	// Bit NRST_STOP.
	Flash_OPTR_NRST_STOP = 0x1000
	// Position of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY_Pos = 0xd
	// Bit mask of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY_Msk = 0x2000
	// Bit NRST_STDBY.
	Flash_OPTR_NRST_STDBY = 0x2000
	// Position of NRST_SHDW field.
	Flash_OPTR_NRST_SHDW_Pos = 0xe
	// Bit mask of NRST_SHDW field.
	Flash_OPTR_NRST_SHDW_Msk = 0x4000
	// Bit NRST_SHDW.
	Flash_OPTR_NRST_SHDW = 0x4000
	// Position of IWDG_SW field.
	Flash_OPTR_IWDG_SW_Pos = 0x10
	// Bit mask of IWDG_SW field.
	Flash_OPTR_IWDG_SW_Msk = 0x10000
	// Bit IWDG_SW.
	Flash_OPTR_IWDG_SW = 0x10000
	// Position of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP_Pos = 0x11
	// Bit mask of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP_Msk = 0x20000
	// Bit IWDG_STOP.
	Flash_OPTR_IWDG_STOP = 0x20000
	// Position of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY_Pos = 0x12
	// Bit mask of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY_Msk = 0x40000
	// Bit IWDG_STDBY.
	Flash_OPTR_IWDG_STDBY = 0x40000
	// Position of WWDG_SW field.
	Flash_OPTR_WWDG_SW_Pos = 0x13
	// Bit mask of WWDG_SW field.
	Flash_OPTR_WWDG_SW_Msk = 0x80000
	// Bit WWDG_SW.
	Flash_OPTR_WWDG_SW = 0x80000
	// Position of SWAP_BANK field.
	Flash_OPTR_SWAP_BANK_Pos = 0x14
	// Bit mask of SWAP_BANK field.
	Flash_OPTR_SWAP_BANK_Msk = 0x100000
	// Bit SWAP_BANK.
	Flash_OPTR_SWAP_BANK = 0x100000
	// Position of DB256K field.
	Flash_OPTR_DB256K_Pos = 0x15
	// Bit mask of DB256K field.
	Flash_OPTR_DB256K_Msk = 0x200000
	// Bit DB256K.
	Flash_OPTR_DB256K = 0x200000
	// Position of DBANK field.
	Flash_OPTR_DBANK_Pos = 0x16
	// Bit mask of DBANK field.
	Flash_OPTR_DBANK_Msk = 0x400000
	// Bit DBANK.
	Flash_OPTR_DBANK = 0x400000
	// Position of SRAM2_PE field.
	Flash_OPTR_SRAM2_PE_Pos = 0x18
	// Bit mask of SRAM2_PE field.
	Flash_OPTR_SRAM2_PE_Msk = 0x1000000
	// Bit SRAM2_PE.
	Flash_OPTR_SRAM2_PE = 0x1000000
	// Position of SRAM2_RST field.
	Flash_OPTR_SRAM2_RST_Pos = 0x19
	// Bit mask of SRAM2_RST field.
	Flash_OPTR_SRAM2_RST_Msk = 0x2000000
	// Bit SRAM2_RST.
	Flash_OPTR_SRAM2_RST = 0x2000000
	// Position of NSWBOOT0 field.
	Flash_OPTR_NSWBOOT0_Pos = 0x1a
	// Bit mask of NSWBOOT0 field.
	Flash_OPTR_NSWBOOT0_Msk = 0x4000000
	// Bit NSWBOOT0.
	Flash_OPTR_NSWBOOT0 = 0x4000000
	// Position of NBOOT0 field.
	Flash_OPTR_NBOOT0_Pos = 0x1b
	// Bit mask of NBOOT0 field.
	Flash_OPTR_NBOOT0_Msk = 0x8000000
	// Bit NBOOT0.
	Flash_OPTR_NBOOT0 = 0x8000000
	// Position of PA15_PUPEN field.
	Flash_OPTR_PA15_PUPEN_Pos = 0x1c
	// Bit mask of PA15_PUPEN field.
	Flash_OPTR_PA15_PUPEN_Msk = 0x10000000
	// Bit PA15_PUPEN.
	Flash_OPTR_PA15_PUPEN = 0x10000000
	// Position of TZEN field.
	Flash_OPTR_TZEN_Pos = 0x1f
	// Bit mask of TZEN field.
	Flash_OPTR_TZEN_Msk = 0x80000000
	// Bit TZEN.
	Flash_OPTR_TZEN = 0x80000000

	// NSBOOTADD0R: Flash non-secure boot address 0 register
	// Position of NSBOOTADD0 field.
	Flash_NSBOOTADD0R_NSBOOTADD0_Pos = 0x7
	// Bit mask of NSBOOTADD0 field.
	Flash_NSBOOTADD0R_NSBOOTADD0_Msk = 0xffffff80

	// NSBOOTADD1R: Flash non-secure boot address 1 register
	// Position of NSBOOTADD1 field.
	Flash_NSBOOTADD1R_NSBOOTADD1_Pos = 0x7
	// Bit mask of NSBOOTADD1 field.
	Flash_NSBOOTADD1R_NSBOOTADD1_Msk = 0xffffff80

	// SECBOOTADD0R: FFlash secure boot address 0 register
	// Position of BOOT_LOCK field.
	Flash_SECBOOTADD0R_BOOT_LOCK_Pos = 0x0
	// Bit mask of BOOT_LOCK field.
	Flash_SECBOOTADD0R_BOOT_LOCK_Msk = 0x1
	// Bit BOOT_LOCK.
	Flash_SECBOOTADD0R_BOOT_LOCK = 0x1
	// Position of SECBOOTADD0 field.
	Flash_SECBOOTADD0R_SECBOOTADD0_Pos = 0x7
	// Bit mask of SECBOOTADD0 field.
	Flash_SECBOOTADD0R_SECBOOTADD0_Msk = 0xffffff80

	// SECWM1R1: Flash bank 1 secure watermak1 register
	// Position of SECWM1_PSTRT field.
	Flash_SECWM1R1_SECWM1_PSTRT_Pos = 0x0
	// Bit mask of SECWM1_PSTRT field.
	Flash_SECWM1R1_SECWM1_PSTRT_Msk = 0x7f
	// Position of SECWM1_PEND field.
	Flash_SECWM1R1_SECWM1_PEND_Pos = 0x10
	// Bit mask of SECWM1_PEND field.
	Flash_SECWM1R1_SECWM1_PEND_Msk = 0x7f0000

	// SECWM1R2: Flash secure watermak1 register 2
	// Position of PCROP1_PSTRT field.
	Flash_SECWM1R2_PCROP1_PSTRT_Pos = 0x0
	// Bit mask of PCROP1_PSTRT field.
	Flash_SECWM1R2_PCROP1_PSTRT_Msk = 0x7f
	// Position of PCROP1EN field.
	Flash_SECWM1R2_PCROP1EN_Pos = 0xf
	// Bit mask of PCROP1EN field.
	Flash_SECWM1R2_PCROP1EN_Msk = 0x8000
	// Bit PCROP1EN.
	Flash_SECWM1R2_PCROP1EN = 0x8000
	// Position of HDP1_PEND field.
	Flash_SECWM1R2_HDP1_PEND_Pos = 0x10
	// Bit mask of HDP1_PEND field.
	Flash_SECWM1R2_HDP1_PEND_Msk = 0x7f0000
	// Position of HDP1EN field.
	Flash_SECWM1R2_HDP1EN_Pos = 0x1f
	// Bit mask of HDP1EN field.
	Flash_SECWM1R2_HDP1EN_Msk = 0x80000000
	// Bit HDP1EN.
	Flash_SECWM1R2_HDP1EN = 0x80000000

	// WRP1AR: Flash Bank 1 WRP area A address register
	// Position of WRP1A_PSTRT field.
	Flash_WRP1AR_WRP1A_PSTRT_Pos = 0x0
	// Bit mask of WRP1A_PSTRT field.
	Flash_WRP1AR_WRP1A_PSTRT_Msk = 0x7f
	// Position of WRP1A_PEND field.
	Flash_WRP1AR_WRP1A_PEND_Pos = 0x10
	// Bit mask of WRP1A_PEND field.
	Flash_WRP1AR_WRP1A_PEND_Msk = 0x7f0000

	// WRP1BR: Flash Bank 1 WRP area B address register
	// Position of WRP1B_PSTRT field.
	Flash_WRP1BR_WRP1B_PSTRT_Pos = 0x0
	// Bit mask of WRP1B_PSTRT field.
	Flash_WRP1BR_WRP1B_PSTRT_Msk = 0x7f
	// Position of WRP1B_PEND field.
	Flash_WRP1BR_WRP1B_PEND_Pos = 0x10
	// Bit mask of WRP1B_PEND field.
	Flash_WRP1BR_WRP1B_PEND_Msk = 0x7f0000

	// SECWM2R1: Flash secure watermak2 register
	// Position of SECWM2_PSTRT field.
	Flash_SECWM2R1_SECWM2_PSTRT_Pos = 0x0
	// Bit mask of SECWM2_PSTRT field.
	Flash_SECWM2R1_SECWM2_PSTRT_Msk = 0x7f
	// Position of SECWM2_PEND field.
	Flash_SECWM2R1_SECWM2_PEND_Pos = 0x10
	// Bit mask of SECWM2_PEND field.
	Flash_SECWM2R1_SECWM2_PEND_Msk = 0x7f0000

	// SECWM2R2: Flash secure watermak2 register2
	// Position of PCROP2_PSTRT field.
	Flash_SECWM2R2_PCROP2_PSTRT_Pos = 0x0
	// Bit mask of PCROP2_PSTRT field.
	Flash_SECWM2R2_PCROP2_PSTRT_Msk = 0x7f
	// Position of PCROP2EN field.
	Flash_SECWM2R2_PCROP2EN_Pos = 0xf
	// Bit mask of PCROP2EN field.
	Flash_SECWM2R2_PCROP2EN_Msk = 0x8000
	// Bit PCROP2EN.
	Flash_SECWM2R2_PCROP2EN = 0x8000
	// Position of HDP2_PEND field.
	Flash_SECWM2R2_HDP2_PEND_Pos = 0x10
	// Bit mask of HDP2_PEND field.
	Flash_SECWM2R2_HDP2_PEND_Msk = 0x7f0000
	// Position of HDP2EN field.
	Flash_SECWM2R2_HDP2EN_Pos = 0x1f
	// Bit mask of HDP2EN field.
	Flash_SECWM2R2_HDP2EN_Msk = 0x80000000
	// Bit HDP2EN.
	Flash_SECWM2R2_HDP2EN = 0x80000000

	// WRP2AR: Flash WPR2 area A address register
	// Position of WRP2A_PSTRT field.
	Flash_WRP2AR_WRP2A_PSTRT_Pos = 0x0
	// Bit mask of WRP2A_PSTRT field.
	Flash_WRP2AR_WRP2A_PSTRT_Msk = 0x7f
	// Position of WRP2A_PEND field.
	Flash_WRP2AR_WRP2A_PEND_Pos = 0x10
	// Bit mask of WRP2A_PEND field.
	Flash_WRP2AR_WRP2A_PEND_Msk = 0x7f0000

	// WRP2BR: Flash WPR2 area B address register
	// Position of WRP2B_PSTRT field.
	Flash_WRP2BR_WRP2B_PSTRT_Pos = 0x0
	// Bit mask of WRP2B_PSTRT field.
	Flash_WRP2BR_WRP2B_PSTRT_Msk = 0x7f
	// Position of WRP2B_PEND field.
	Flash_WRP2BR_WRP2B_PEND_Pos = 0x10
	// Bit mask of WRP2B_PEND field.
	Flash_WRP2BR_WRP2B_PEND_Msk = 0x7f0000

	// SECBB1R1: FLASH secure block based bank 1
	// Position of SECBB1 field.
	Flash_SECBB1R_SECBB1_Pos = 0x0
	// Bit mask of SECBB1 field.
	Flash_SECBB1R_SECBB1_Msk = 0xffffffff

	// SECBB2R1: FLASH secure block based bank 2
	// Position of SECBB2 field.
	Flash_SECBB2R_SECBB2_Pos = 0x0
	// Bit mask of SECBB2 field.
	Flash_SECBB2R_SECBB2_Msk = 0xffffffff

	// SECHDPCR: FLASH secure HDP control register
	// Position of HDP1_ACCDIS field.
	Flash_SECHDPCR_HDP1_ACCDIS_Pos = 0x0
	// Bit mask of HDP1_ACCDIS field.
	Flash_SECHDPCR_HDP1_ACCDIS_Msk = 0x1
	// Bit HDP1_ACCDIS.
	Flash_SECHDPCR_HDP1_ACCDIS = 0x1
	// Position of HDP2_ACCDIS field.
	Flash_SECHDPCR_HDP2_ACCDIS_Pos = 0x1
	// Bit mask of HDP2_ACCDIS field.
	Flash_SECHDPCR_HDP2_ACCDIS_Msk = 0x2
	// Bit HDP2_ACCDIS.
	Flash_SECHDPCR_HDP2_ACCDIS = 0x2

	// PRIVCFGR: Power privilege configuration register
	// Position of PRIV field.
	Flash_PRIVCFGR_PRIV_Pos = 0x0
	// Bit mask of PRIV field.
	Flash_PRIVCFGR_PRIV_Msk = 0x1
	// Bit PRIV.
	Flash_PRIVCFGR_PRIV = 0x1
)

// Constants for FMC: FMC
const (
	// BCR1: FMC_BCR1
	// Position of MBKEN field.
	FMC_BCR1_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR1_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR1_MBKEN = 0x1
	// Corresponding memory bank is disabled
	FMC_BCR1_MBKEN_Disabled = 0x0
	// Corresponding memory bank is enabled
	FMC_BCR1_MBKEN_Enabled = 0x1
	// Position of MUXEN field.
	FMC_BCR1_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR1_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR1_MUXEN = 0x2
	// Address/Data non-multiplexed
	FMC_BCR1_MUXEN_Disabled = 0x0
	// Address/Data multiplexed on databus
	FMC_BCR1_MUXEN_Enabled = 0x1
	// Position of MTYP field.
	FMC_BCR1_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR1_MTYP_Msk = 0xc
	// SRAM memory type
	FMC_BCR1_MTYP_SRAM = 0x0
	// PSRAM (CRAM) memory type
	FMC_BCR1_MTYP_PSRAM = 0x1
	// NOR Flash/OneNAND Flash
	FMC_BCR1_MTYP_Flash = 0x2
	// Position of MWID field.
	FMC_BCR1_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR1_MWID_Msk = 0x30
	// Memory data bus width 8 bits
	FMC_BCR1_MWID_Bits8 = 0x0
	// Memory data bus width 16 bits
	FMC_BCR1_MWID_Bits16 = 0x1
	// Memory data bus width 32 bits
	FMC_BCR1_MWID_Bits32 = 0x2
	// Position of FACCEN field.
	FMC_BCR1_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR1_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR1_FACCEN = 0x40
	// Corresponding NOR Flash memory access is disabled
	FMC_BCR1_FACCEN_Disabled = 0x0
	// Corresponding NOR Flash memory access is enabled
	FMC_BCR1_FACCEN_Enabled = 0x1
	// Position of BURSTEN field.
	FMC_BCR1_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR1_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR1_BURSTEN = 0x100
	// Burst mode disabled
	FMC_BCR1_BURSTEN_Disabled = 0x0
	// Burst mode enabled
	FMC_BCR1_BURSTEN_Enabled = 0x1
	// Position of WAITPOL field.
	FMC_BCR1_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR1_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR1_WAITPOL = 0x200
	// NWAIT active low
	FMC_BCR1_WAITPOL_ActiveLow = 0x0
	// NWAIT active high
	FMC_BCR1_WAITPOL_ActiveHigh = 0x1
	// Position of WAITCFG field.
	FMC_BCR1_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR1_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR1_WAITCFG = 0x800
	// NWAIT signal is active one data cycle before wait state
	FMC_BCR1_WAITCFG_BeforeWaitState = 0x0
	// NWAIT signal is active during wait state
	FMC_BCR1_WAITCFG_DuringWaitState = 0x1
	// Position of WREN field.
	FMC_BCR1_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR1_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR1_WREN = 0x1000
	// Write operations disabled for the bank by the FMC
	FMC_BCR1_WREN_Disabled = 0x0
	// Write operations enabled for the bank by the FMC
	FMC_BCR1_WREN_Enabled = 0x1
	// Position of WAITEN field.
	FMC_BCR1_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR1_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR1_WAITEN = 0x2000
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR1_WAITEN_Disabled = 0x0
	// NWAIT signal enabled
	FMC_BCR1_WAITEN_Enabled = 0x1
	// Position of EXTMOD field.
	FMC_BCR1_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR1_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR1_EXTMOD = 0x4000
	// Values inside the FMC_BWTR are not taken into account
	FMC_BCR1_EXTMOD_Disabled = 0x0
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR1_EXTMOD_Enabled = 0x1
	// Position of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR1_ASYNCWAIT = 0x8000
	// Wait signal not used in asynchronous mode
	FMC_BCR1_ASYNCWAIT_Disabled = 0x0
	// Wait signal used even in asynchronous mode
	FMC_BCR1_ASYNCWAIT_Enabled = 0x1
	// Position of CPSIZE field.
	FMC_BCR1_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR1_CPSIZE_Msk = 0x70000
	// No burst split when crossing page boundary
	FMC_BCR1_CPSIZE_NoBurstSplit = 0x0
	// 128 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes128 = 0x1
	// 256 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes256 = 0x2
	// 512 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes512 = 0x3
	// 1024 bytes CRAM page size
	FMC_BCR1_CPSIZE_Bytes1024 = 0x4
	// Position of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR1_CBURSTRW = 0x80000
	// Write operations are always performed in asynchronous mode
	FMC_BCR1_CBURSTRW_Disabled = 0x0
	// Write operations are performed in synchronous mode
	FMC_BCR1_CBURSTRW_Enabled = 0x1
	// Position of CCLKEN field.
	FMC_BCR1_CCLKEN_Pos = 0x14
	// Bit mask of CCLKEN field.
	FMC_BCR1_CCLKEN_Msk = 0x100000
	// Bit CCLKEN.
	FMC_BCR1_CCLKEN = 0x100000
	// The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set
	FMC_BCR1_CCLKEN_Disabled = 0x0
	// The FMC_CLK is only generated during the synchronous memory access (read/write transaction)
	FMC_BCR1_CCLKEN_Enabled = 0x1
	// Position of WFDIS field.
	FMC_BCR1_WFDIS_Pos = 0x15
	// Bit mask of WFDIS field.
	FMC_BCR1_WFDIS_Msk = 0x200000
	// Bit WFDIS.
	FMC_BCR1_WFDIS = 0x200000
	// Write FIFO enabled
	FMC_BCR1_WFDIS_Enabled = 0x0
	// Write FIFO disabled
	FMC_BCR1_WFDIS_Disabled = 0x1
	// Position of NBLSET field.
	FMC_BCR1_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_BCR1_NBLSET_Msk = 0xc00000

	// BTR1: SRAM/NOR-flash chip-select timing registers for bank %s
	// Position of ADDSET field.
	FMC_BTR_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BTR_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BTR_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BTR_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BTR_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BTR_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BTR_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BTR_BUSTURN_Msk = 0xf0000
	// Position of CLKDIV field.
	FMC_BTR_CLKDIV_Pos = 0x14
	// Bit mask of CLKDIV field.
	FMC_BTR_CLKDIV_Msk = 0xf00000
	// Position of DATLAT field.
	FMC_BTR_DATLAT_Pos = 0x18
	// Bit mask of DATLAT field.
	FMC_BTR_DATLAT_Msk = 0xf000000
	// Position of ACCMOD field.
	FMC_BTR_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BTR_ACCMOD_Msk = 0x30000000
	// Access mode A
	FMC_BTR_ACCMOD_A = 0x0
	// Access mode B
	FMC_BTR_ACCMOD_B = 0x1
	// Access mode C
	FMC_BTR_ACCMOD_C = 0x2
	// Access mode D
	FMC_BTR_ACCMOD_D = 0x3
	// Position of DATAHLD field.
	FMC_BTR_DATAHLD_Pos = 0x1e
	// Bit mask of DATAHLD field.
	FMC_BTR_DATAHLD_Msk = 0xc0000000

	// BCR2: SRAM/NOR-Flash chip-select control register %s
	// Position of MBKEN field.
	FMC_BCR_MBKEN_Pos = 0x0
	// Bit mask of MBKEN field.
	FMC_BCR_MBKEN_Msk = 0x1
	// Bit MBKEN.
	FMC_BCR_MBKEN = 0x1
	// Corresponding memory bank is disabled
	FMC_BCR_MBKEN_Disabled = 0x0
	// Corresponding memory bank is enabled
	FMC_BCR_MBKEN_Enabled = 0x1
	// Position of MUXEN field.
	FMC_BCR_MUXEN_Pos = 0x1
	// Bit mask of MUXEN field.
	FMC_BCR_MUXEN_Msk = 0x2
	// Bit MUXEN.
	FMC_BCR_MUXEN = 0x2
	// Address/Data non-multiplexed
	FMC_BCR_MUXEN_Disabled = 0x0
	// Address/Data multiplexed on databus
	FMC_BCR_MUXEN_Enabled = 0x1
	// Position of MTYP field.
	FMC_BCR_MTYP_Pos = 0x2
	// Bit mask of MTYP field.
	FMC_BCR_MTYP_Msk = 0xc
	// SRAM memory type
	FMC_BCR_MTYP_SRAM = 0x0
	// PSRAM (CRAM) memory type
	FMC_BCR_MTYP_PSRAM = 0x1
	// NOR Flash/OneNAND Flash
	FMC_BCR_MTYP_Flash = 0x2
	// Position of MWID field.
	FMC_BCR_MWID_Pos = 0x4
	// Bit mask of MWID field.
	FMC_BCR_MWID_Msk = 0x30
	// Memory data bus width 8 bits
	FMC_BCR_MWID_Bits8 = 0x0
	// Memory data bus width 16 bits
	FMC_BCR_MWID_Bits16 = 0x1
	// Memory data bus width 32 bits
	FMC_BCR_MWID_Bits32 = 0x2
	// Position of FACCEN field.
	FMC_BCR_FACCEN_Pos = 0x6
	// Bit mask of FACCEN field.
	FMC_BCR_FACCEN_Msk = 0x40
	// Bit FACCEN.
	FMC_BCR_FACCEN = 0x40
	// Corresponding NOR Flash memory access is disabled
	FMC_BCR_FACCEN_Disabled = 0x0
	// Corresponding NOR Flash memory access is enabled
	FMC_BCR_FACCEN_Enabled = 0x1
	// Position of BURSTEN field.
	FMC_BCR_BURSTEN_Pos = 0x8
	// Bit mask of BURSTEN field.
	FMC_BCR_BURSTEN_Msk = 0x100
	// Bit BURSTEN.
	FMC_BCR_BURSTEN = 0x100
	// Burst mode disabled
	FMC_BCR_BURSTEN_Disabled = 0x0
	// Burst mode enabled
	FMC_BCR_BURSTEN_Enabled = 0x1
	// Position of WAITPOL field.
	FMC_BCR_WAITPOL_Pos = 0x9
	// Bit mask of WAITPOL field.
	FMC_BCR_WAITPOL_Msk = 0x200
	// Bit WAITPOL.
	FMC_BCR_WAITPOL = 0x200
	// NWAIT active low
	FMC_BCR_WAITPOL_ActiveLow = 0x0
	// NWAIT active high
	FMC_BCR_WAITPOL_ActiveHigh = 0x1
	// Position of WAITCFG field.
	FMC_BCR_WAITCFG_Pos = 0xb
	// Bit mask of WAITCFG field.
	FMC_BCR_WAITCFG_Msk = 0x800
	// Bit WAITCFG.
	FMC_BCR_WAITCFG = 0x800
	// NWAIT signal is active one data cycle before wait state
	FMC_BCR_WAITCFG_BeforeWaitState = 0x0
	// NWAIT signal is active during wait state
	FMC_BCR_WAITCFG_DuringWaitState = 0x1
	// Position of WREN field.
	FMC_BCR_WREN_Pos = 0xc
	// Bit mask of WREN field.
	FMC_BCR_WREN_Msk = 0x1000
	// Bit WREN.
	FMC_BCR_WREN = 0x1000
	// Write operations disabled for the bank by the FMC
	FMC_BCR_WREN_Disabled = 0x0
	// Write operations enabled for the bank by the FMC
	FMC_BCR_WREN_Enabled = 0x1
	// Position of WAITEN field.
	FMC_BCR_WAITEN_Pos = 0xd
	// Bit mask of WAITEN field.
	FMC_BCR_WAITEN_Msk = 0x2000
	// Bit WAITEN.
	FMC_BCR_WAITEN = 0x2000
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR_WAITEN_Disabled = 0x0
	// NWAIT signal enabled
	FMC_BCR_WAITEN_Enabled = 0x1
	// Position of EXTMOD field.
	FMC_BCR_EXTMOD_Pos = 0xe
	// Bit mask of EXTMOD field.
	FMC_BCR_EXTMOD_Msk = 0x4000
	// Bit EXTMOD.
	FMC_BCR_EXTMOD = 0x4000
	// Values inside the FMC_BWTR are not taken into account
	FMC_BCR_EXTMOD_Disabled = 0x0
	// Values inside the FMC_BWTR are taken into account
	FMC_BCR_EXTMOD_Enabled = 0x1
	// Position of ASYNCWAIT field.
	FMC_BCR_ASYNCWAIT_Pos = 0xf
	// Bit mask of ASYNCWAIT field.
	FMC_BCR_ASYNCWAIT_Msk = 0x8000
	// Bit ASYNCWAIT.
	FMC_BCR_ASYNCWAIT = 0x8000
	// Wait signal not used in asynchronous mode
	FMC_BCR_ASYNCWAIT_Disabled = 0x0
	// Wait signal used even in asynchronous mode
	FMC_BCR_ASYNCWAIT_Enabled = 0x1
	// Position of CPSIZE field.
	FMC_BCR_CPSIZE_Pos = 0x10
	// Bit mask of CPSIZE field.
	FMC_BCR_CPSIZE_Msk = 0x70000
	// No burst split when crossing page boundary
	FMC_BCR_CPSIZE_NoBurstSplit = 0x0
	// 128 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes128 = 0x1
	// 256 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes256 = 0x2
	// 512 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes512 = 0x3
	// 1024 bytes CRAM page size
	FMC_BCR_CPSIZE_Bytes1024 = 0x4
	// Position of CBURSTRW field.
	FMC_BCR_CBURSTRW_Pos = 0x13
	// Bit mask of CBURSTRW field.
	FMC_BCR_CBURSTRW_Msk = 0x80000
	// Bit CBURSTRW.
	FMC_BCR_CBURSTRW = 0x80000
	// Write operations are always performed in asynchronous mode
	FMC_BCR_CBURSTRW_Disabled = 0x0
	// Write operations are performed in synchronous mode
	FMC_BCR_CBURSTRW_Enabled = 0x1
	// Position of NBLSET field.
	FMC_BCR_NBLSET_Pos = 0x16
	// Bit mask of NBLSET field.
	FMC_BCR_NBLSET_Msk = 0xc00000

	// PCSCNTR: PCSCNTR
	// Position of CSCOUNT field.
	FMC_PCSCNTR_CSCOUNT_Pos = 0x0
	// Bit mask of CSCOUNT field.
	FMC_PCSCNTR_CSCOUNT_Msk = 0xffff
	// Position of CNTB1EN field.
	FMC_PCSCNTR_CNTB1EN_Pos = 0x11
	// Bit mask of CNTB1EN field.
	FMC_PCSCNTR_CNTB1EN_Msk = 0x20000
	// Bit CNTB1EN.
	FMC_PCSCNTR_CNTB1EN = 0x20000
	// Position of CNTB2EN field.
	FMC_PCSCNTR_CNTB2EN_Pos = 0x12
	// Bit mask of CNTB2EN field.
	FMC_PCSCNTR_CNTB2EN_Msk = 0x40000
	// Bit CNTB2EN.
	FMC_PCSCNTR_CNTB2EN = 0x40000
	// Position of CNTB3EN field.
	FMC_PCSCNTR_CNTB3EN_Pos = 0x13
	// Bit mask of CNTB3EN field.
	FMC_PCSCNTR_CNTB3EN_Msk = 0x80000
	// Bit CNTB3EN.
	FMC_PCSCNTR_CNTB3EN = 0x80000
	// Position of CNTB4EN field.
	FMC_PCSCNTR_CNTB4EN_Pos = 0x14
	// Bit mask of CNTB4EN field.
	FMC_PCSCNTR_CNTB4EN_Msk = 0x100000
	// Bit CNTB4EN.
	FMC_PCSCNTR_CNTB4EN = 0x100000

	// PCR: NAND Flash control registers
	// Position of PWAITEN field.
	FMC_PCR_PWAITEN_Pos = 0x1
	// Bit mask of PWAITEN field.
	FMC_PCR_PWAITEN_Msk = 0x2
	// Bit PWAITEN.
	FMC_PCR_PWAITEN = 0x2
	// Wait feature disabled
	FMC_PCR_PWAITEN_Disabled = 0x0
	// Wait feature enabled
	FMC_PCR_PWAITEN_Enabled = 0x1
	// Position of PBKEN field.
	FMC_PCR_PBKEN_Pos = 0x2
	// Bit mask of PBKEN field.
	FMC_PCR_PBKEN_Msk = 0x4
	// Bit PBKEN.
	FMC_PCR_PBKEN = 0x4
	// Corresponding memory bank is disabled
	FMC_PCR_PBKEN_Disabled = 0x0
	// Corresponding memory bank is enabled
	FMC_PCR_PBKEN_Enabled = 0x1
	// Position of PTYP field.
	FMC_PCR_PTYP_Pos = 0x3
	// Bit mask of PTYP field.
	FMC_PCR_PTYP_Msk = 0x8
	// Bit PTYP.
	FMC_PCR_PTYP = 0x8
	// NAND Flash
	FMC_PCR_PTYP_NANDFlash = 0x1
	// Position of PWID field.
	FMC_PCR_PWID_Pos = 0x4
	// Bit mask of PWID field.
	FMC_PCR_PWID_Msk = 0x30
	// External memory device width 8 bits
	FMC_PCR_PWID_Bits8 = 0x0
	// External memory device width 16 bits
	FMC_PCR_PWID_Bits16 = 0x1
	// Position of ECCEN field.
	FMC_PCR_ECCEN_Pos = 0x6
	// Bit mask of ECCEN field.
	FMC_PCR_ECCEN_Msk = 0x40
	// Bit ECCEN.
	FMC_PCR_ECCEN = 0x40
	// ECC logic is disabled and reset
	FMC_PCR_ECCEN_Disabled = 0x0
	// ECC logic is enabled
	FMC_PCR_ECCEN_Enabled = 0x1
	// Position of TCLR field.
	FMC_PCR_TCLR_Pos = 0x9
	// Bit mask of TCLR field.
	FMC_PCR_TCLR_Msk = 0x1e00
	// Position of TAR field.
	FMC_PCR_TAR_Pos = 0xd
	// Bit mask of TAR field.
	FMC_PCR_TAR_Msk = 0x1e000
	// Position of ECCPS field.
	FMC_PCR_ECCPS_Pos = 0x11
	// Bit mask of ECCPS field.
	FMC_PCR_ECCPS_Msk = 0xe0000
	// ECC page size 256 bytes
	FMC_PCR_ECCPS_Bytes256 = 0x0
	// ECC page size 512 bytes
	FMC_PCR_ECCPS_Bytes512 = 0x1
	// ECC page size 1024 bytes
	FMC_PCR_ECCPS_Bytes1024 = 0x2
	// ECC page size 2048 bytes
	FMC_PCR_ECCPS_Bytes2048 = 0x3
	// ECC page size 4096 bytes
	FMC_PCR_ECCPS_Bytes4096 = 0x4
	// ECC page size 8192 bytes
	FMC_PCR_ECCPS_Bytes8192 = 0x5

	// SR: This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.
	// Position of IRS field.
	FMC_SR_IRS_Pos = 0x0
	// Bit mask of IRS field.
	FMC_SR_IRS_Msk = 0x1
	// Bit IRS.
	FMC_SR_IRS = 0x1
	// Interrupt rising edge did not occur
	FMC_SR_IRS_DidNotOccur = 0x0
	// Interrupt rising edge occurred
	FMC_SR_IRS_Occurred = 0x1
	// Position of ILS field.
	FMC_SR_ILS_Pos = 0x1
	// Bit mask of ILS field.
	FMC_SR_ILS_Msk = 0x2
	// Bit ILS.
	FMC_SR_ILS = 0x2
	// Interrupt high-level did not occur
	FMC_SR_ILS_DidNotOccur = 0x0
	// Interrupt high-level occurred
	FMC_SR_ILS_Occurred = 0x1
	// Position of IFS field.
	FMC_SR_IFS_Pos = 0x2
	// Bit mask of IFS field.
	FMC_SR_IFS_Msk = 0x4
	// Bit IFS.
	FMC_SR_IFS = 0x4
	// Interrupt falling edge did not occur
	FMC_SR_IFS_DidNotOccur = 0x0
	// Interrupt falling edge occurred
	FMC_SR_IFS_Occurred = 0x1
	// Position of IREN field.
	FMC_SR_IREN_Pos = 0x3
	// Bit mask of IREN field.
	FMC_SR_IREN_Msk = 0x8
	// Bit IREN.
	FMC_SR_IREN = 0x8
	// Interrupt rising edge detection request disabled
	FMC_SR_IREN_Disabled = 0x0
	// Interrupt rising edge detection request enabled
	FMC_SR_IREN_Enabled = 0x1
	// Position of ILEN field.
	FMC_SR_ILEN_Pos = 0x4
	// Bit mask of ILEN field.
	FMC_SR_ILEN_Msk = 0x10
	// Bit ILEN.
	FMC_SR_ILEN = 0x10
	// Interrupt high-level detection request disabled
	FMC_SR_ILEN_Disabled = 0x0
	// Interrupt high-level detection request enabled
	FMC_SR_ILEN_Enabled = 0x1
	// Position of IFEN field.
	FMC_SR_IFEN_Pos = 0x5
	// Bit mask of IFEN field.
	FMC_SR_IFEN_Msk = 0x20
	// Bit IFEN.
	FMC_SR_IFEN = 0x20
	// Interrupt falling edge detection request disabled
	FMC_SR_IFEN_Disabled = 0x0
	// Interrupt falling edge detection request enabled
	FMC_SR_IFEN_Enabled = 0x1
	// Position of FEMPT field.
	FMC_SR_FEMPT_Pos = 0x6
	// Bit mask of FEMPT field.
	FMC_SR_FEMPT_Msk = 0x40
	// Bit FEMPT.
	FMC_SR_FEMPT = 0x40
	// FIFO not empty
	FMC_SR_FEMPT_NotEmpty = 0x0
	// FIFO empty
	FMC_SR_FEMPT_Empty = 0x1

	// PMEM: The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.
	// Position of MEMSET field.
	FMC_PMEM_MEMSET_Pos = 0x0
	// Bit mask of MEMSET field.
	FMC_PMEM_MEMSET_Msk = 0xff
	// Position of MEMWAIT field.
	FMC_PMEM_MEMWAIT_Pos = 0x8
	// Bit mask of MEMWAIT field.
	FMC_PMEM_MEMWAIT_Msk = 0xff00
	// Position of MEMHOLD field.
	FMC_PMEM_MEMHOLD_Pos = 0x10
	// Bit mask of MEMHOLD field.
	FMC_PMEM_MEMHOLD_Msk = 0xff0000
	// Position of MEMHIZ field.
	FMC_PMEM_MEMHIZ_Pos = 0x18
	// Bit mask of MEMHIZ field.
	FMC_PMEM_MEMHIZ_Msk = 0xff000000

	// PATT: The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).
	// Position of ATTSET field.
	FMC_PATT_ATTSET_Pos = 0x0
	// Bit mask of ATTSET field.
	FMC_PATT_ATTSET_Msk = 0xff
	// Position of ATTWAIT field.
	FMC_PATT_ATTWAIT_Pos = 0x8
	// Bit mask of ATTWAIT field.
	FMC_PATT_ATTWAIT_Msk = 0xff00
	// Position of ATTHOLD field.
	FMC_PATT_ATTHOLD_Pos = 0x10
	// Bit mask of ATTHOLD field.
	FMC_PATT_ATTHOLD_Msk = 0xff0000
	// Position of ATTHIZ field.
	FMC_PATT_ATTHIZ_Pos = 0x18
	// Bit mask of ATTHIZ field.
	FMC_PATT_ATTHIZ_Msk = 0xff000000

	// ECCR: This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.
	// Position of ECC field.
	FMC_ECCR_ECC_Pos = 0x0
	// Bit mask of ECC field.
	FMC_ECCR_ECC_Msk = 0xffffffff

	// BWTR1: This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.
	// Position of ADDSET field.
	FMC_BWTR_ADDSET_Pos = 0x0
	// Bit mask of ADDSET field.
	FMC_BWTR_ADDSET_Msk = 0xf
	// Position of ADDHLD field.
	FMC_BWTR_ADDHLD_Pos = 0x4
	// Bit mask of ADDHLD field.
	FMC_BWTR_ADDHLD_Msk = 0xf0
	// Position of DATAST field.
	FMC_BWTR_DATAST_Pos = 0x8
	// Bit mask of DATAST field.
	FMC_BWTR_DATAST_Msk = 0xff00
	// Position of BUSTURN field.
	FMC_BWTR_BUSTURN_Pos = 0x10
	// Bit mask of BUSTURN field.
	FMC_BWTR_BUSTURN_Msk = 0xf0000
	// Position of ACCMOD field.
	FMC_BWTR_ACCMOD_Pos = 0x1c
	// Bit mask of ACCMOD field.
	FMC_BWTR_ACCMOD_Msk = 0x30000000
	// Access mode A
	FMC_BWTR_ACCMOD_A = 0x0
	// Access mode B
	FMC_BWTR_ACCMOD_B = 0x1
	// Access mode C
	FMC_BWTR_ACCMOD_C = 0x2
	// Access mode D
	FMC_BWTR_ACCMOD_D = 0x3
)

// Constants for GPIOA: General-purpose I/Os
const (
	// MODER: GPIO port mode register
	// Position of MODER0 field.
	GPIO_MODER_MODER0_Pos = 0x2
	// Bit mask of MODER0 field.
	GPIO_MODER_MODER0_Msk = 0xc
	// Input mode
	GPIO_MODER_MODER0_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER0_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER0_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER0_Analog = 0x3
	// Position of MODER1 field.
	GPIO_MODER_MODER1_Pos = 0x4
	// Bit mask of MODER1 field.
	GPIO_MODER_MODER1_Msk = 0x30
	// Input mode
	GPIO_MODER_MODER1_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER1_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER1_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER1_Analog = 0x3
	// Position of MODER2 field.
	GPIO_MODER_MODER2_Pos = 0x6
	// Bit mask of MODER2 field.
	GPIO_MODER_MODER2_Msk = 0xc0
	// Input mode
	GPIO_MODER_MODER2_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER2_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER2_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER2_Analog = 0x3
	// Position of MODER3 field.
	GPIO_MODER_MODER3_Pos = 0x8
	// Bit mask of MODER3 field.
	GPIO_MODER_MODER3_Msk = 0x300
	// Input mode
	GPIO_MODER_MODER3_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER3_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER3_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER3_Analog = 0x3
	// Position of MODER4 field.
	GPIO_MODER_MODER4_Pos = 0xa
	// Bit mask of MODER4 field.
	GPIO_MODER_MODER4_Msk = 0xc00
	// Input mode
	GPIO_MODER_MODER4_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER4_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER4_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER4_Analog = 0x3
	// Position of MODER5 field.
	GPIO_MODER_MODER5_Pos = 0xc
	// Bit mask of MODER5 field.
	GPIO_MODER_MODER5_Msk = 0x3000
	// Input mode
	GPIO_MODER_MODER5_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER5_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER5_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER5_Analog = 0x3
	// Position of MODER6 field.
	GPIO_MODER_MODER6_Pos = 0xe
	// Bit mask of MODER6 field.
	GPIO_MODER_MODER6_Msk = 0xc000
	// Input mode
	GPIO_MODER_MODER6_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER6_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER6_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER6_Analog = 0x3
	// Position of MODER7 field.
	GPIO_MODER_MODER7_Pos = 0x10
	// Bit mask of MODER7 field.
	GPIO_MODER_MODER7_Msk = 0x30000
	// Input mode
	GPIO_MODER_MODER7_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER7_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER7_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER7_Analog = 0x3
	// Position of MODER8 field.
	GPIO_MODER_MODER8_Pos = 0x12
	// Bit mask of MODER8 field.
	GPIO_MODER_MODER8_Msk = 0xc0000
	// Input mode
	GPIO_MODER_MODER8_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER8_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER8_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER8_Analog = 0x3
	// Position of MODER9 field.
	GPIO_MODER_MODER9_Pos = 0x14
	// Bit mask of MODER9 field.
	GPIO_MODER_MODER9_Msk = 0x300000
	// Input mode
	GPIO_MODER_MODER9_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER9_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER9_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER9_Analog = 0x3
	// Position of MODER10 field.
	GPIO_MODER_MODER10_Pos = 0x16
	// Bit mask of MODER10 field.
	GPIO_MODER_MODER10_Msk = 0xc00000
	// Input mode
	GPIO_MODER_MODER10_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER10_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER10_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER10_Analog = 0x3
	// Position of MODER11 field.
	GPIO_MODER_MODER11_Pos = 0x18
	// Bit mask of MODER11 field.
	GPIO_MODER_MODER11_Msk = 0x3000000
	// Input mode
	GPIO_MODER_MODER11_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER11_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER11_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER11_Analog = 0x3
	// Position of MODER12 field.
	GPIO_MODER_MODER12_Pos = 0x1a
	// Bit mask of MODER12 field.
	GPIO_MODER_MODER12_Msk = 0xc000000
	// Input mode
	GPIO_MODER_MODER12_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER12_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER12_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER12_Analog = 0x3
	// Position of MODER13 field.
	GPIO_MODER_MODER13_Pos = 0x1c
	// Bit mask of MODER13 field.
	GPIO_MODER_MODER13_Msk = 0x30000000
	// Input mode
	GPIO_MODER_MODER13_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER13_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER13_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER13_Analog = 0x3
	// Position of MODER14 field.
	GPIO_MODER_MODER14_Pos = 0x1e
	// Bit mask of MODER14 field.
	GPIO_MODER_MODER14_Msk = 0xc0000000
	// Input mode
	GPIO_MODER_MODER14_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER14_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER14_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER14_Analog = 0x3
	// Position of MODER15 field.
	GPIO_MODER_MODER15_Pos = 0x20
	// Bit mask of MODER15 field.
	GPIO_MODER_MODER15_Msk = 0x300000000
	// Input mode
	GPIO_MODER_MODER15_Input = 0x0
	// General purpose output mode
	GPIO_MODER_MODER15_Output = 0x1
	// Alternate function mode
	GPIO_MODER_MODER15_Alternate = 0x2
	// Analog mode
	GPIO_MODER_MODER15_Analog = 0x3

	// OTYPER: GPIO port output type register
	// Position of OT0 field.
	GPIO_OTYPER_OT0_Pos = 0x1
	// Bit mask of OT0 field.
	GPIO_OTYPER_OT0_Msk = 0x2
	// Bit OT0.
	GPIO_OTYPER_OT0 = 0x2
	// Output push-pull (reset state)
	GPIO_OTYPER_OT0_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT0_OpenDrain = 0x1
	// Position of OT1 field.
	GPIO_OTYPER_OT1_Pos = 0x2
	// Bit mask of OT1 field.
	GPIO_OTYPER_OT1_Msk = 0x4
	// Bit OT1.
	GPIO_OTYPER_OT1 = 0x4
	// Output push-pull (reset state)
	GPIO_OTYPER_OT1_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT1_OpenDrain = 0x1
	// Position of OT2 field.
	GPIO_OTYPER_OT2_Pos = 0x3
	// Bit mask of OT2 field.
	GPIO_OTYPER_OT2_Msk = 0x8
	// Bit OT2.
	GPIO_OTYPER_OT2 = 0x8
	// Output push-pull (reset state)
	GPIO_OTYPER_OT2_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT2_OpenDrain = 0x1
	// Position of OT3 field.
	GPIO_OTYPER_OT3_Pos = 0x4
	// Bit mask of OT3 field.
	GPIO_OTYPER_OT3_Msk = 0x10
	// Bit OT3.
	GPIO_OTYPER_OT3 = 0x10
	// Output push-pull (reset state)
	GPIO_OTYPER_OT3_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT3_OpenDrain = 0x1
	// Position of OT4 field.
	GPIO_OTYPER_OT4_Pos = 0x5
	// Bit mask of OT4 field.
	GPIO_OTYPER_OT4_Msk = 0x20
	// Bit OT4.
	GPIO_OTYPER_OT4 = 0x20
	// Output push-pull (reset state)
	GPIO_OTYPER_OT4_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT4_OpenDrain = 0x1
	// Position of OT5 field.
	GPIO_OTYPER_OT5_Pos = 0x6
	// Bit mask of OT5 field.
	GPIO_OTYPER_OT5_Msk = 0x40
	// Bit OT5.
	GPIO_OTYPER_OT5 = 0x40
	// Output push-pull (reset state)
	GPIO_OTYPER_OT5_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT5_OpenDrain = 0x1
	// Position of OT6 field.
	GPIO_OTYPER_OT6_Pos = 0x7
	// Bit mask of OT6 field.
	GPIO_OTYPER_OT6_Msk = 0x80
	// Bit OT6.
	GPIO_OTYPER_OT6 = 0x80
	// Output push-pull (reset state)
	GPIO_OTYPER_OT6_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT6_OpenDrain = 0x1
	// Position of OT7 field.
	GPIO_OTYPER_OT7_Pos = 0x8
	// Bit mask of OT7 field.
	GPIO_OTYPER_OT7_Msk = 0x100
	// Bit OT7.
	GPIO_OTYPER_OT7 = 0x100
	// Output push-pull (reset state)
	GPIO_OTYPER_OT7_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT7_OpenDrain = 0x1
	// Position of OT8 field.
	GPIO_OTYPER_OT8_Pos = 0x9
	// Bit mask of OT8 field.
	GPIO_OTYPER_OT8_Msk = 0x200
	// Bit OT8.
	GPIO_OTYPER_OT8 = 0x200
	// Output push-pull (reset state)
	GPIO_OTYPER_OT8_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT8_OpenDrain = 0x1
	// Position of OT9 field.
	GPIO_OTYPER_OT9_Pos = 0xa
	// Bit mask of OT9 field.
	GPIO_OTYPER_OT9_Msk = 0x400
	// Bit OT9.
	GPIO_OTYPER_OT9 = 0x400
	// Output push-pull (reset state)
	GPIO_OTYPER_OT9_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT9_OpenDrain = 0x1
	// Position of OT10 field.
	GPIO_OTYPER_OT10_Pos = 0xb
	// Bit mask of OT10 field.
	GPIO_OTYPER_OT10_Msk = 0x800
	// Bit OT10.
	GPIO_OTYPER_OT10 = 0x800
	// Output push-pull (reset state)
	GPIO_OTYPER_OT10_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT10_OpenDrain = 0x1
	// Position of OT11 field.
	GPIO_OTYPER_OT11_Pos = 0xc
	// Bit mask of OT11 field.
	GPIO_OTYPER_OT11_Msk = 0x1000
	// Bit OT11.
	GPIO_OTYPER_OT11 = 0x1000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT11_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT11_OpenDrain = 0x1
	// Position of OT12 field.
	GPIO_OTYPER_OT12_Pos = 0xd
	// Bit mask of OT12 field.
	GPIO_OTYPER_OT12_Msk = 0x2000
	// Bit OT12.
	GPIO_OTYPER_OT12 = 0x2000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT12_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT12_OpenDrain = 0x1
	// Position of OT13 field.
	GPIO_OTYPER_OT13_Pos = 0xe
	// Bit mask of OT13 field.
	GPIO_OTYPER_OT13_Msk = 0x4000
	// Bit OT13.
	GPIO_OTYPER_OT13 = 0x4000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT13_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT13_OpenDrain = 0x1
	// Position of OT14 field.
	GPIO_OTYPER_OT14_Pos = 0xf
	// Bit mask of OT14 field.
	GPIO_OTYPER_OT14_Msk = 0x8000
	// Bit OT14.
	GPIO_OTYPER_OT14 = 0x8000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT14_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT14_OpenDrain = 0x1
	// Position of OT15 field.
	GPIO_OTYPER_OT15_Pos = 0x10
	// Bit mask of OT15 field.
	GPIO_OTYPER_OT15_Msk = 0x10000
	// Bit OT15.
	GPIO_OTYPER_OT15 = 0x10000
	// Output push-pull (reset state)
	GPIO_OTYPER_OT15_PushPull = 0x0
	// Output open-drain
	GPIO_OTYPER_OT15_OpenDrain = 0x1

	// OSPEEDR: GPIO port output speed register
	// Position of OSPEEDR0 field.
	GPIO_OSPEEDR_OSPEEDR0_Pos = 0x2
	// Bit mask of OSPEEDR0 field.
	GPIO_OSPEEDR_OSPEEDR0_Msk = 0xc
	// Low speed
	GPIO_OSPEEDR_OSPEEDR0_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR0_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR0_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR0_VeryHighSpeed = 0x3
	// Position of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR1_Pos = 0x4
	// Bit mask of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR1_Msk = 0x30
	// Low speed
	GPIO_OSPEEDR_OSPEEDR1_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR1_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR1_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR1_VeryHighSpeed = 0x3
	// Position of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR2_Pos = 0x6
	// Bit mask of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR2_Msk = 0xc0
	// Low speed
	GPIO_OSPEEDR_OSPEEDR2_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR2_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR2_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR2_VeryHighSpeed = 0x3
	// Position of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR3_Pos = 0x8
	// Bit mask of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR3_Msk = 0x300
	// Low speed
	GPIO_OSPEEDR_OSPEEDR3_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR3_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR3_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR3_VeryHighSpeed = 0x3
	// Position of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR4_Pos = 0xa
	// Bit mask of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR4_Msk = 0xc00
	// Low speed
	GPIO_OSPEEDR_OSPEEDR4_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR4_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR4_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR4_VeryHighSpeed = 0x3
	// Position of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR5_Pos = 0xc
	// Bit mask of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR5_Msk = 0x3000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR5_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR5_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR5_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR5_VeryHighSpeed = 0x3
	// Position of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR6_Pos = 0xe
	// Bit mask of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR6_Msk = 0xc000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR6_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR6_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR6_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR6_VeryHighSpeed = 0x3
	// Position of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR7_Pos = 0x10
	// Bit mask of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR7_Msk = 0x30000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR7_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR7_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR7_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR7_VeryHighSpeed = 0x3
	// Position of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR8_Pos = 0x12
	// Bit mask of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR8_Msk = 0xc0000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR8_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR8_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR8_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR8_VeryHighSpeed = 0x3
	// Position of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR9_Pos = 0x14
	// Bit mask of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR9_Msk = 0x300000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR9_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR9_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR9_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR9_VeryHighSpeed = 0x3
	// Position of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR10_Pos = 0x16
	// Bit mask of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR10_Msk = 0xc00000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR10_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR10_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR10_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR10_VeryHighSpeed = 0x3
	// Position of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR11_Pos = 0x18
	// Bit mask of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR11_Msk = 0x3000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR11_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR11_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR11_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR11_VeryHighSpeed = 0x3
	// Position of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR12_Pos = 0x1a
	// Bit mask of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR12_Msk = 0xc000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR12_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR12_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR12_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR12_VeryHighSpeed = 0x3
	// Position of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR13_Pos = 0x1c
	// Bit mask of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR13_Msk = 0x30000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR13_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR13_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR13_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR13_VeryHighSpeed = 0x3
	// Position of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR14_Pos = 0x1e
	// Bit mask of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR14_Msk = 0xc0000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR14_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR14_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR14_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR14_VeryHighSpeed = 0x3
	// Position of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR15_Pos = 0x20
	// Bit mask of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR15_Msk = 0x300000000
	// Low speed
	GPIO_OSPEEDR_OSPEEDR15_LowSpeed = 0x0
	// Medium speed
	GPIO_OSPEEDR_OSPEEDR15_MediumSpeed = 0x1
	// High speed
	GPIO_OSPEEDR_OSPEEDR15_HighSpeed = 0x2
	// Very high speed
	GPIO_OSPEEDR_OSPEEDR15_VeryHighSpeed = 0x3

	// PUPDR: GPIO port pull-up/pull-down register
	// Position of PUPDR0 field.
	GPIO_PUPDR_PUPDR0_Pos = 0x2
	// Bit mask of PUPDR0 field.
	GPIO_PUPDR_PUPDR0_Msk = 0xc
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR0_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR0_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR0_PullDown = 0x2
	// Position of PUPDR1 field.
	GPIO_PUPDR_PUPDR1_Pos = 0x4
	// Bit mask of PUPDR1 field.
	GPIO_PUPDR_PUPDR1_Msk = 0x30
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR1_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR1_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR1_PullDown = 0x2
	// Position of PUPDR2 field.
	GPIO_PUPDR_PUPDR2_Pos = 0x6
	// Bit mask of PUPDR2 field.
	GPIO_PUPDR_PUPDR2_Msk = 0xc0
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR2_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR2_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR2_PullDown = 0x2
	// Position of PUPDR3 field.
	GPIO_PUPDR_PUPDR3_Pos = 0x8
	// Bit mask of PUPDR3 field.
	GPIO_PUPDR_PUPDR3_Msk = 0x300
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR3_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR3_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR3_PullDown = 0x2
	// Position of PUPDR4 field.
	GPIO_PUPDR_PUPDR4_Pos = 0xa
	// Bit mask of PUPDR4 field.
	GPIO_PUPDR_PUPDR4_Msk = 0xc00
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR4_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR4_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR4_PullDown = 0x2
	// Position of PUPDR5 field.
	GPIO_PUPDR_PUPDR5_Pos = 0xc
	// Bit mask of PUPDR5 field.
	GPIO_PUPDR_PUPDR5_Msk = 0x3000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR5_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR5_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR5_PullDown = 0x2
	// Position of PUPDR6 field.
	GPIO_PUPDR_PUPDR6_Pos = 0xe
	// Bit mask of PUPDR6 field.
	GPIO_PUPDR_PUPDR6_Msk = 0xc000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR6_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR6_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR6_PullDown = 0x2
	// Position of PUPDR7 field.
	GPIO_PUPDR_PUPDR7_Pos = 0x10
	// Bit mask of PUPDR7 field.
	GPIO_PUPDR_PUPDR7_Msk = 0x30000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR7_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR7_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR7_PullDown = 0x2
	// Position of PUPDR8 field.
	GPIO_PUPDR_PUPDR8_Pos = 0x12
	// Bit mask of PUPDR8 field.
	GPIO_PUPDR_PUPDR8_Msk = 0xc0000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR8_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR8_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR8_PullDown = 0x2
	// Position of PUPDR9 field.
	GPIO_PUPDR_PUPDR9_Pos = 0x14
	// Bit mask of PUPDR9 field.
	GPIO_PUPDR_PUPDR9_Msk = 0x300000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR9_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR9_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR9_PullDown = 0x2
	// Position of PUPDR10 field.
	GPIO_PUPDR_PUPDR10_Pos = 0x16
	// Bit mask of PUPDR10 field.
	GPIO_PUPDR_PUPDR10_Msk = 0xc00000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR10_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR10_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR10_PullDown = 0x2
	// Position of PUPDR11 field.
	GPIO_PUPDR_PUPDR11_Pos = 0x18
	// Bit mask of PUPDR11 field.
	GPIO_PUPDR_PUPDR11_Msk = 0x3000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR11_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR11_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR11_PullDown = 0x2
	// Position of PUPDR12 field.
	GPIO_PUPDR_PUPDR12_Pos = 0x1a
	// Bit mask of PUPDR12 field.
	GPIO_PUPDR_PUPDR12_Msk = 0xc000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR12_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR12_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR12_PullDown = 0x2
	// Position of PUPDR13 field.
	GPIO_PUPDR_PUPDR13_Pos = 0x1c
	// Bit mask of PUPDR13 field.
	GPIO_PUPDR_PUPDR13_Msk = 0x30000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR13_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR13_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR13_PullDown = 0x2
	// Position of PUPDR14 field.
	GPIO_PUPDR_PUPDR14_Pos = 0x1e
	// Bit mask of PUPDR14 field.
	GPIO_PUPDR_PUPDR14_Msk = 0xc0000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR14_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR14_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR14_PullDown = 0x2
	// Position of PUPDR15 field.
	GPIO_PUPDR_PUPDR15_Pos = 0x20
	// Bit mask of PUPDR15 field.
	GPIO_PUPDR_PUPDR15_Msk = 0x300000000
	// No pull-up, pull-down
	GPIO_PUPDR_PUPDR15_Floating = 0x0
	// Pull-up
	GPIO_PUPDR_PUPDR15_PullUp = 0x1
	// Pull-down
	GPIO_PUPDR_PUPDR15_PullDown = 0x2

	// IDR: GPIO port input data register
	// Position of IDR0 field.
	GPIO_IDR_IDR0_Pos = 0x1
	// Bit mask of IDR0 field.
	GPIO_IDR_IDR0_Msk = 0x2
	// Bit IDR0.
	GPIO_IDR_IDR0 = 0x2
	// Input is logic low
	GPIO_IDR_IDR0_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR0_High = 0x1
	// Position of IDR1 field.
	GPIO_IDR_IDR1_Pos = 0x2
	// Bit mask of IDR1 field.
	GPIO_IDR_IDR1_Msk = 0x4
	// Bit IDR1.
	GPIO_IDR_IDR1 = 0x4
	// Input is logic low
	GPIO_IDR_IDR1_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR1_High = 0x1
	// Position of IDR2 field.
	GPIO_IDR_IDR2_Pos = 0x3
	// Bit mask of IDR2 field.
	GPIO_IDR_IDR2_Msk = 0x8
	// Bit IDR2.
	GPIO_IDR_IDR2 = 0x8
	// Input is logic low
	GPIO_IDR_IDR2_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR2_High = 0x1
	// Position of IDR3 field.
	GPIO_IDR_IDR3_Pos = 0x4
	// Bit mask of IDR3 field.
	GPIO_IDR_IDR3_Msk = 0x10
	// Bit IDR3.
	GPIO_IDR_IDR3 = 0x10
	// Input is logic low
	GPIO_IDR_IDR3_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR3_High = 0x1
	// Position of IDR4 field.
	GPIO_IDR_IDR4_Pos = 0x5
	// Bit mask of IDR4 field.
	GPIO_IDR_IDR4_Msk = 0x20
	// Bit IDR4.
	GPIO_IDR_IDR4 = 0x20
	// Input is logic low
	GPIO_IDR_IDR4_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR4_High = 0x1
	// Position of IDR5 field.
	GPIO_IDR_IDR5_Pos = 0x6
	// Bit mask of IDR5 field.
	GPIO_IDR_IDR5_Msk = 0x40
	// Bit IDR5.
	GPIO_IDR_IDR5 = 0x40
	// Input is logic low
	GPIO_IDR_IDR5_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR5_High = 0x1
	// Position of IDR6 field.
	GPIO_IDR_IDR6_Pos = 0x7
	// Bit mask of IDR6 field.
	GPIO_IDR_IDR6_Msk = 0x80
	// Bit IDR6.
	GPIO_IDR_IDR6 = 0x80
	// Input is logic low
	GPIO_IDR_IDR6_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR6_High = 0x1
	// Position of IDR7 field.
	GPIO_IDR_IDR7_Pos = 0x8
	// Bit mask of IDR7 field.
	GPIO_IDR_IDR7_Msk = 0x100
	// Bit IDR7.
	GPIO_IDR_IDR7 = 0x100
	// Input is logic low
	GPIO_IDR_IDR7_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR7_High = 0x1
	// Position of IDR8 field.
	GPIO_IDR_IDR8_Pos = 0x9
	// Bit mask of IDR8 field.
	GPIO_IDR_IDR8_Msk = 0x200
	// Bit IDR8.
	GPIO_IDR_IDR8 = 0x200
	// Input is logic low
	GPIO_IDR_IDR8_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR8_High = 0x1
	// Position of IDR9 field.
	GPIO_IDR_IDR9_Pos = 0xa
	// Bit mask of IDR9 field.
	GPIO_IDR_IDR9_Msk = 0x400
	// Bit IDR9.
	GPIO_IDR_IDR9 = 0x400
	// Input is logic low
	GPIO_IDR_IDR9_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR9_High = 0x1
	// Position of IDR10 field.
	GPIO_IDR_IDR10_Pos = 0xb
	// Bit mask of IDR10 field.
	GPIO_IDR_IDR10_Msk = 0x800
	// Bit IDR10.
	GPIO_IDR_IDR10 = 0x800
	// Input is logic low
	GPIO_IDR_IDR10_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR10_High = 0x1
	// Position of IDR11 field.
	GPIO_IDR_IDR11_Pos = 0xc
	// Bit mask of IDR11 field.
	GPIO_IDR_IDR11_Msk = 0x1000
	// Bit IDR11.
	GPIO_IDR_IDR11 = 0x1000
	// Input is logic low
	GPIO_IDR_IDR11_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR11_High = 0x1
	// Position of IDR12 field.
	GPIO_IDR_IDR12_Pos = 0xd
	// Bit mask of IDR12 field.
	GPIO_IDR_IDR12_Msk = 0x2000
	// Bit IDR12.
	GPIO_IDR_IDR12 = 0x2000
	// Input is logic low
	GPIO_IDR_IDR12_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR12_High = 0x1
	// Position of IDR13 field.
	GPIO_IDR_IDR13_Pos = 0xe
	// Bit mask of IDR13 field.
	GPIO_IDR_IDR13_Msk = 0x4000
	// Bit IDR13.
	GPIO_IDR_IDR13 = 0x4000
	// Input is logic low
	GPIO_IDR_IDR13_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR13_High = 0x1
	// Position of IDR14 field.
	GPIO_IDR_IDR14_Pos = 0xf
	// Bit mask of IDR14 field.
	GPIO_IDR_IDR14_Msk = 0x8000
	// Bit IDR14.
	GPIO_IDR_IDR14 = 0x8000
	// Input is logic low
	GPIO_IDR_IDR14_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR14_High = 0x1
	// Position of IDR15 field.
	GPIO_IDR_IDR15_Pos = 0x10
	// Bit mask of IDR15 field.
	GPIO_IDR_IDR15_Msk = 0x10000
	// Bit IDR15.
	GPIO_IDR_IDR15 = 0x10000
	// Input is logic low
	GPIO_IDR_IDR15_Low = 0x0
	// Input is logic high
	GPIO_IDR_IDR15_High = 0x1

	// ODR: GPIO port output data register
	// Position of ODR0 field.
	GPIO_ODR_ODR0_Pos = 0x1
	// Bit mask of ODR0 field.
	GPIO_ODR_ODR0_Msk = 0x2
	// Bit ODR0.
	GPIO_ODR_ODR0 = 0x2
	// Set output to logic low
	GPIO_ODR_ODR0_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR0_High = 0x1
	// Position of ODR1 field.
	GPIO_ODR_ODR1_Pos = 0x2
	// Bit mask of ODR1 field.
	GPIO_ODR_ODR1_Msk = 0x4
	// Bit ODR1.
	GPIO_ODR_ODR1 = 0x4
	// Set output to logic low
	GPIO_ODR_ODR1_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR1_High = 0x1
	// Position of ODR2 field.
	GPIO_ODR_ODR2_Pos = 0x3
	// Bit mask of ODR2 field.
	GPIO_ODR_ODR2_Msk = 0x8
	// Bit ODR2.
	GPIO_ODR_ODR2 = 0x8
	// Set output to logic low
	GPIO_ODR_ODR2_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR2_High = 0x1
	// Position of ODR3 field.
	GPIO_ODR_ODR3_Pos = 0x4
	// Bit mask of ODR3 field.
	GPIO_ODR_ODR3_Msk = 0x10
	// Bit ODR3.
	GPIO_ODR_ODR3 = 0x10
	// Set output to logic low
	GPIO_ODR_ODR3_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR3_High = 0x1
	// Position of ODR4 field.
	GPIO_ODR_ODR4_Pos = 0x5
	// Bit mask of ODR4 field.
	GPIO_ODR_ODR4_Msk = 0x20
	// Bit ODR4.
	GPIO_ODR_ODR4 = 0x20
	// Set output to logic low
	GPIO_ODR_ODR4_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR4_High = 0x1
	// Position of ODR5 field.
	GPIO_ODR_ODR5_Pos = 0x6
	// Bit mask of ODR5 field.
	GPIO_ODR_ODR5_Msk = 0x40
	// Bit ODR5.
	GPIO_ODR_ODR5 = 0x40
	// Set output to logic low
	GPIO_ODR_ODR5_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR5_High = 0x1
	// Position of ODR6 field.
	GPIO_ODR_ODR6_Pos = 0x7
	// Bit mask of ODR6 field.
	GPIO_ODR_ODR6_Msk = 0x80
	// Bit ODR6.
	GPIO_ODR_ODR6 = 0x80
	// Set output to logic low
	GPIO_ODR_ODR6_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR6_High = 0x1
	// Position of ODR7 field.
	GPIO_ODR_ODR7_Pos = 0x8
	// Bit mask of ODR7 field.
	GPIO_ODR_ODR7_Msk = 0x100
	// Bit ODR7.
	GPIO_ODR_ODR7 = 0x100
	// Set output to logic low
	GPIO_ODR_ODR7_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR7_High = 0x1
	// Position of ODR8 field.
	GPIO_ODR_ODR8_Pos = 0x9
	// Bit mask of ODR8 field.
	GPIO_ODR_ODR8_Msk = 0x200
	// Bit ODR8.
	GPIO_ODR_ODR8 = 0x200
	// Set output to logic low
	GPIO_ODR_ODR8_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR8_High = 0x1
	// Position of ODR9 field.
	GPIO_ODR_ODR9_Pos = 0xa
	// Bit mask of ODR9 field.
	GPIO_ODR_ODR9_Msk = 0x400
	// Bit ODR9.
	GPIO_ODR_ODR9 = 0x400
	// Set output to logic low
	GPIO_ODR_ODR9_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR9_High = 0x1
	// Position of ODR10 field.
	GPIO_ODR_ODR10_Pos = 0xb
	// Bit mask of ODR10 field.
	GPIO_ODR_ODR10_Msk = 0x800
	// Bit ODR10.
	GPIO_ODR_ODR10 = 0x800
	// Set output to logic low
	GPIO_ODR_ODR10_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR10_High = 0x1
	// Position of ODR11 field.
	GPIO_ODR_ODR11_Pos = 0xc
	// Bit mask of ODR11 field.
	GPIO_ODR_ODR11_Msk = 0x1000
	// Bit ODR11.
	GPIO_ODR_ODR11 = 0x1000
	// Set output to logic low
	GPIO_ODR_ODR11_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR11_High = 0x1
	// Position of ODR12 field.
	GPIO_ODR_ODR12_Pos = 0xd
	// Bit mask of ODR12 field.
	GPIO_ODR_ODR12_Msk = 0x2000
	// Bit ODR12.
	GPIO_ODR_ODR12 = 0x2000
	// Set output to logic low
	GPIO_ODR_ODR12_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR12_High = 0x1
	// Position of ODR13 field.
	GPIO_ODR_ODR13_Pos = 0xe
	// Bit mask of ODR13 field.
	GPIO_ODR_ODR13_Msk = 0x4000
	// Bit ODR13.
	GPIO_ODR_ODR13 = 0x4000
	// Set output to logic low
	GPIO_ODR_ODR13_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR13_High = 0x1
	// Position of ODR14 field.
	GPIO_ODR_ODR14_Pos = 0xf
	// Bit mask of ODR14 field.
	GPIO_ODR_ODR14_Msk = 0x8000
	// Bit ODR14.
	GPIO_ODR_ODR14 = 0x8000
	// Set output to logic low
	GPIO_ODR_ODR14_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR14_High = 0x1
	// Position of ODR15 field.
	GPIO_ODR_ODR15_Pos = 0x10
	// Bit mask of ODR15 field.
	GPIO_ODR_ODR15_Msk = 0x10000
	// Bit ODR15.
	GPIO_ODR_ODR15 = 0x10000
	// Set output to logic low
	GPIO_ODR_ODR15_Low = 0x0
	// Set output to logic high
	GPIO_ODR_ODR15_High = 0x1

	// BSRR: GPIO port bit set/reset register
	// Position of BR0 field.
	GPIO_BSRR_BR0_Pos = 0x11
	// Bit mask of BR0 field.
	GPIO_BSRR_BR0_Msk = 0x20000
	// Bit BR0.
	GPIO_BSRR_BR0 = 0x20000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BSRR_BR1_Pos = 0x12
	// Bit mask of BR1 field.
	GPIO_BSRR_BR1_Msk = 0x40000
	// Bit BR1.
	GPIO_BSRR_BR1 = 0x40000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BSRR_BR2_Pos = 0x13
	// Bit mask of BR2 field.
	GPIO_BSRR_BR2_Msk = 0x80000
	// Bit BR2.
	GPIO_BSRR_BR2 = 0x80000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BSRR_BR3_Pos = 0x14
	// Bit mask of BR3 field.
	GPIO_BSRR_BR3_Msk = 0x100000
	// Bit BR3.
	GPIO_BSRR_BR3 = 0x100000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BSRR_BR4_Pos = 0x15
	// Bit mask of BR4 field.
	GPIO_BSRR_BR4_Msk = 0x200000
	// Bit BR4.
	GPIO_BSRR_BR4 = 0x200000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BSRR_BR5_Pos = 0x16
	// Bit mask of BR5 field.
	GPIO_BSRR_BR5_Msk = 0x400000
	// Bit BR5.
	GPIO_BSRR_BR5 = 0x400000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BSRR_BR6_Pos = 0x17
	// Bit mask of BR6 field.
	GPIO_BSRR_BR6_Msk = 0x800000
	// Bit BR6.
	GPIO_BSRR_BR6 = 0x800000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BSRR_BR7_Pos = 0x18
	// Bit mask of BR7 field.
	GPIO_BSRR_BR7_Msk = 0x1000000
	// Bit BR7.
	GPIO_BSRR_BR7 = 0x1000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BSRR_BR8_Pos = 0x19
	// Bit mask of BR8 field.
	GPIO_BSRR_BR8_Msk = 0x2000000
	// Bit BR8.
	GPIO_BSRR_BR8 = 0x2000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BSRR_BR9_Pos = 0x1a
	// Bit mask of BR9 field.
	GPIO_BSRR_BR9_Msk = 0x4000000
	// Bit BR9.
	GPIO_BSRR_BR9 = 0x4000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BSRR_BR10_Pos = 0x1b
	// Bit mask of BR10 field.
	GPIO_BSRR_BR10_Msk = 0x8000000
	// Bit BR10.
	GPIO_BSRR_BR10 = 0x8000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BSRR_BR11_Pos = 0x1c
	// Bit mask of BR11 field.
	GPIO_BSRR_BR11_Msk = 0x10000000
	// Bit BR11.
	GPIO_BSRR_BR11 = 0x10000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR11_Reset = 0x1
	// Position of BR12 field.
	GPIO_BSRR_BR12_Pos = 0x1d
	// Bit mask of BR12 field.
	GPIO_BSRR_BR12_Msk = 0x20000000
	// Bit BR12.
	GPIO_BSRR_BR12 = 0x20000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR12_Reset = 0x1
	// Position of BR13 field.
	GPIO_BSRR_BR13_Pos = 0x1e
	// Bit mask of BR13 field.
	GPIO_BSRR_BR13_Msk = 0x40000000
	// Bit BR13.
	GPIO_BSRR_BR13 = 0x40000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR13_Reset = 0x1
	// Position of BR14 field.
	GPIO_BSRR_BR14_Pos = 0x1f
	// Bit mask of BR14 field.
	GPIO_BSRR_BR14_Msk = 0x80000000
	// Bit BR14.
	GPIO_BSRR_BR14 = 0x80000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR14_Reset = 0x1
	// Position of BR15 field.
	GPIO_BSRR_BR15_Pos = 0x20
	// Bit mask of BR15 field.
	GPIO_BSRR_BR15_Msk = 0x100000000
	// Bit BR15.
	GPIO_BSRR_BR15 = 0x100000000
	// Resets the corresponding ODx bit
	GPIO_BSRR_BR15_Reset = 0x1
	// Position of BS0 field.
	GPIO_BSRR_BS0_Pos = 0x1
	// Bit mask of BS0 field.
	GPIO_BSRR_BS0_Msk = 0x2
	// Bit BS0.
	GPIO_BSRR_BS0 = 0x2
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS0_Set = 0x1
	// Position of BS1 field.
	GPIO_BSRR_BS1_Pos = 0x2
	// Bit mask of BS1 field.
	GPIO_BSRR_BS1_Msk = 0x4
	// Bit BS1.
	GPIO_BSRR_BS1 = 0x4
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS1_Set = 0x1
	// Position of BS2 field.
	GPIO_BSRR_BS2_Pos = 0x3
	// Bit mask of BS2 field.
	GPIO_BSRR_BS2_Msk = 0x8
	// Bit BS2.
	GPIO_BSRR_BS2 = 0x8
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS2_Set = 0x1
	// Position of BS3 field.
	GPIO_BSRR_BS3_Pos = 0x4
	// Bit mask of BS3 field.
	GPIO_BSRR_BS3_Msk = 0x10
	// Bit BS3.
	GPIO_BSRR_BS3 = 0x10
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS3_Set = 0x1
	// Position of BS4 field.
	GPIO_BSRR_BS4_Pos = 0x5
	// Bit mask of BS4 field.
	GPIO_BSRR_BS4_Msk = 0x20
	// Bit BS4.
	GPIO_BSRR_BS4 = 0x20
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS4_Set = 0x1
	// Position of BS5 field.
	GPIO_BSRR_BS5_Pos = 0x6
	// Bit mask of BS5 field.
	GPIO_BSRR_BS5_Msk = 0x40
	// Bit BS5.
	GPIO_BSRR_BS5 = 0x40
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS5_Set = 0x1
	// Position of BS6 field.
	GPIO_BSRR_BS6_Pos = 0x7
	// Bit mask of BS6 field.
	GPIO_BSRR_BS6_Msk = 0x80
	// Bit BS6.
	GPIO_BSRR_BS6 = 0x80
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS6_Set = 0x1
	// Position of BS7 field.
	GPIO_BSRR_BS7_Pos = 0x8
	// Bit mask of BS7 field.
	GPIO_BSRR_BS7_Msk = 0x100
	// Bit BS7.
	GPIO_BSRR_BS7 = 0x100
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS7_Set = 0x1
	// Position of BS8 field.
	GPIO_BSRR_BS8_Pos = 0x9
	// Bit mask of BS8 field.
	GPIO_BSRR_BS8_Msk = 0x200
	// Bit BS8.
	GPIO_BSRR_BS8 = 0x200
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS8_Set = 0x1
	// Position of BS9 field.
	GPIO_BSRR_BS9_Pos = 0xa
	// Bit mask of BS9 field.
	GPIO_BSRR_BS9_Msk = 0x400
	// Bit BS9.
	GPIO_BSRR_BS9 = 0x400
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS9_Set = 0x1
	// Position of BS10 field.
	GPIO_BSRR_BS10_Pos = 0xb
	// Bit mask of BS10 field.
	GPIO_BSRR_BS10_Msk = 0x800
	// Bit BS10.
	GPIO_BSRR_BS10 = 0x800
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS10_Set = 0x1
	// Position of BS11 field.
	GPIO_BSRR_BS11_Pos = 0xc
	// Bit mask of BS11 field.
	GPIO_BSRR_BS11_Msk = 0x1000
	// Bit BS11.
	GPIO_BSRR_BS11 = 0x1000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS11_Set = 0x1
	// Position of BS12 field.
	GPIO_BSRR_BS12_Pos = 0xd
	// Bit mask of BS12 field.
	GPIO_BSRR_BS12_Msk = 0x2000
	// Bit BS12.
	GPIO_BSRR_BS12 = 0x2000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS12_Set = 0x1
	// Position of BS13 field.
	GPIO_BSRR_BS13_Pos = 0xe
	// Bit mask of BS13 field.
	GPIO_BSRR_BS13_Msk = 0x4000
	// Bit BS13.
	GPIO_BSRR_BS13 = 0x4000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS13_Set = 0x1
	// Position of BS14 field.
	GPIO_BSRR_BS14_Pos = 0xf
	// Bit mask of BS14 field.
	GPIO_BSRR_BS14_Msk = 0x8000
	// Bit BS14.
	GPIO_BSRR_BS14 = 0x8000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS14_Set = 0x1
	// Position of BS15 field.
	GPIO_BSRR_BS15_Pos = 0x10
	// Bit mask of BS15 field.
	GPIO_BSRR_BS15_Msk = 0x10000
	// Bit BS15.
	GPIO_BSRR_BS15 = 0x10000
	// Sets the corresponding ODx bit
	GPIO_BSRR_BS15_Set = 0x1

	// LCKR: GPIO port configuration lock register
	// Position of LCKK field.
	GPIO_LCKR_LCKK_Pos = 0x10
	// Bit mask of LCKK field.
	GPIO_LCKR_LCKK_Msk = 0x10000
	// Bit LCKK.
	GPIO_LCKR_LCKK = 0x10000
	// Port configuration lock key not active
	GPIO_LCKR_LCKK_NotActive = 0x0
	// Port configuration lock key active
	GPIO_LCKR_LCKK_Active = 0x1
	// Position of LCK0 field.
	GPIO_LCKR_LCK0_Pos = 0x1
	// Bit mask of LCK0 field.
	GPIO_LCKR_LCK0_Msk = 0x2
	// Bit LCK0.
	GPIO_LCKR_LCK0 = 0x2
	// Port configuration not locked
	GPIO_LCKR_LCK0_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK0_Locked = 0x1
	// Position of LCK1 field.
	GPIO_LCKR_LCK1_Pos = 0x2
	// Bit mask of LCK1 field.
	GPIO_LCKR_LCK1_Msk = 0x4
	// Bit LCK1.
	GPIO_LCKR_LCK1 = 0x4
	// Port configuration not locked
	GPIO_LCKR_LCK1_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK1_Locked = 0x1
	// Position of LCK2 field.
	GPIO_LCKR_LCK2_Pos = 0x3
	// Bit mask of LCK2 field.
	GPIO_LCKR_LCK2_Msk = 0x8
	// Bit LCK2.
	GPIO_LCKR_LCK2 = 0x8
	// Port configuration not locked
	GPIO_LCKR_LCK2_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK2_Locked = 0x1
	// Position of LCK3 field.
	GPIO_LCKR_LCK3_Pos = 0x4
	// Bit mask of LCK3 field.
	GPIO_LCKR_LCK3_Msk = 0x10
	// Bit LCK3.
	GPIO_LCKR_LCK3 = 0x10
	// Port configuration not locked
	GPIO_LCKR_LCK3_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK3_Locked = 0x1
	// Position of LCK4 field.
	GPIO_LCKR_LCK4_Pos = 0x5
	// Bit mask of LCK4 field.
	GPIO_LCKR_LCK4_Msk = 0x20
	// Bit LCK4.
	GPIO_LCKR_LCK4 = 0x20
	// Port configuration not locked
	GPIO_LCKR_LCK4_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK4_Locked = 0x1
	// Position of LCK5 field.
	GPIO_LCKR_LCK5_Pos = 0x6
	// Bit mask of LCK5 field.
	GPIO_LCKR_LCK5_Msk = 0x40
	// Bit LCK5.
	GPIO_LCKR_LCK5 = 0x40
	// Port configuration not locked
	GPIO_LCKR_LCK5_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK5_Locked = 0x1
	// Position of LCK6 field.
	GPIO_LCKR_LCK6_Pos = 0x7
	// Bit mask of LCK6 field.
	GPIO_LCKR_LCK6_Msk = 0x80
	// Bit LCK6.
	GPIO_LCKR_LCK6 = 0x80
	// Port configuration not locked
	GPIO_LCKR_LCK6_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK6_Locked = 0x1
	// Position of LCK7 field.
	GPIO_LCKR_LCK7_Pos = 0x8
	// Bit mask of LCK7 field.
	GPIO_LCKR_LCK7_Msk = 0x100
	// Bit LCK7.
	GPIO_LCKR_LCK7 = 0x100
	// Port configuration not locked
	GPIO_LCKR_LCK7_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK7_Locked = 0x1
	// Position of LCK8 field.
	GPIO_LCKR_LCK8_Pos = 0x9
	// Bit mask of LCK8 field.
	GPIO_LCKR_LCK8_Msk = 0x200
	// Bit LCK8.
	GPIO_LCKR_LCK8 = 0x200
	// Port configuration not locked
	GPIO_LCKR_LCK8_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK8_Locked = 0x1
	// Position of LCK9 field.
	GPIO_LCKR_LCK9_Pos = 0xa
	// Bit mask of LCK9 field.
	GPIO_LCKR_LCK9_Msk = 0x400
	// Bit LCK9.
	GPIO_LCKR_LCK9 = 0x400
	// Port configuration not locked
	GPIO_LCKR_LCK9_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK9_Locked = 0x1
	// Position of LCK10 field.
	GPIO_LCKR_LCK10_Pos = 0xb
	// Bit mask of LCK10 field.
	GPIO_LCKR_LCK10_Msk = 0x800
	// Bit LCK10.
	GPIO_LCKR_LCK10 = 0x800
	// Port configuration not locked
	GPIO_LCKR_LCK10_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK10_Locked = 0x1
	// Position of LCK11 field.
	GPIO_LCKR_LCK11_Pos = 0xc
	// Bit mask of LCK11 field.
	GPIO_LCKR_LCK11_Msk = 0x1000
	// Bit LCK11.
	GPIO_LCKR_LCK11 = 0x1000
	// Port configuration not locked
	GPIO_LCKR_LCK11_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK11_Locked = 0x1
	// Position of LCK12 field.
	GPIO_LCKR_LCK12_Pos = 0xd
	// Bit mask of LCK12 field.
	GPIO_LCKR_LCK12_Msk = 0x2000
	// Bit LCK12.
	GPIO_LCKR_LCK12 = 0x2000
	// Port configuration not locked
	GPIO_LCKR_LCK12_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK12_Locked = 0x1
	// Position of LCK13 field.
	GPIO_LCKR_LCK13_Pos = 0xe
	// Bit mask of LCK13 field.
	GPIO_LCKR_LCK13_Msk = 0x4000
	// Bit LCK13.
	GPIO_LCKR_LCK13 = 0x4000
	// Port configuration not locked
	GPIO_LCKR_LCK13_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK13_Locked = 0x1
	// Position of LCK14 field.
	GPIO_LCKR_LCK14_Pos = 0xf
	// Bit mask of LCK14 field.
	GPIO_LCKR_LCK14_Msk = 0x8000
	// Bit LCK14.
	GPIO_LCKR_LCK14 = 0x8000
	// Port configuration not locked
	GPIO_LCKR_LCK14_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK14_Locked = 0x1
	// Position of LCK15 field.
	GPIO_LCKR_LCK15_Pos = 0x10
	// Bit mask of LCK15 field.
	GPIO_LCKR_LCK15_Msk = 0x10000
	// Bit LCK15.
	GPIO_LCKR_LCK15 = 0x10000
	// Port configuration not locked
	GPIO_LCKR_LCK15_Unlocked = 0x0
	// Port configuration locked
	GPIO_LCKR_LCK15_Locked = 0x1

	// AFRL: GPIO alternate function low register
	// Position of AFREL0 field.
	GPIO_AFRL_AFREL0_Pos = 0x4
	// Bit mask of AFREL0 field.
	GPIO_AFRL_AFREL0_Msk = 0xf0
	// AF0
	GPIO_AFRL_AFREL0_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL0_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL0_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL0_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL0_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL0_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL0_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL0_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL0_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL0_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL0_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL0_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL0_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL0_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL0_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL0_AF15 = 0xf
	// Position of AFREL1 field.
	GPIO_AFRL_AFREL1_Pos = 0x8
	// Bit mask of AFREL1 field.
	GPIO_AFRL_AFREL1_Msk = 0xf00
	// AF0
	GPIO_AFRL_AFREL1_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL1_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL1_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL1_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL1_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL1_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL1_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL1_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL1_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL1_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL1_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL1_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL1_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL1_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL1_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL1_AF15 = 0xf
	// Position of AFREL2 field.
	GPIO_AFRL_AFREL2_Pos = 0xc
	// Bit mask of AFREL2 field.
	GPIO_AFRL_AFREL2_Msk = 0xf000
	// AF0
	GPIO_AFRL_AFREL2_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL2_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL2_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL2_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL2_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL2_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL2_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL2_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL2_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL2_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL2_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL2_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL2_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL2_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL2_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL2_AF15 = 0xf
	// Position of AFREL3 field.
	GPIO_AFRL_AFREL3_Pos = 0x10
	// Bit mask of AFREL3 field.
	GPIO_AFRL_AFREL3_Msk = 0xf0000
	// AF0
	GPIO_AFRL_AFREL3_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL3_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL3_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL3_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL3_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL3_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL3_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL3_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL3_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL3_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL3_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL3_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL3_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL3_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL3_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL3_AF15 = 0xf
	// Position of AFREL4 field.
	GPIO_AFRL_AFREL4_Pos = 0x14
	// Bit mask of AFREL4 field.
	GPIO_AFRL_AFREL4_Msk = 0xf00000
	// AF0
	GPIO_AFRL_AFREL4_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL4_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL4_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL4_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL4_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL4_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL4_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL4_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL4_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL4_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL4_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL4_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL4_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL4_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL4_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL4_AF15 = 0xf
	// Position of AFREL5 field.
	GPIO_AFRL_AFREL5_Pos = 0x18
	// Bit mask of AFREL5 field.
	GPIO_AFRL_AFREL5_Msk = 0xf000000
	// AF0
	GPIO_AFRL_AFREL5_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL5_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL5_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL5_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL5_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL5_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL5_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL5_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL5_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL5_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL5_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL5_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL5_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL5_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL5_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL5_AF15 = 0xf
	// Position of AFREL6 field.
	GPIO_AFRL_AFREL6_Pos = 0x1c
	// Bit mask of AFREL6 field.
	GPIO_AFRL_AFREL6_Msk = 0xf0000000
	// AF0
	GPIO_AFRL_AFREL6_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL6_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL6_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL6_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL6_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL6_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL6_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL6_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL6_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL6_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL6_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL6_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL6_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL6_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL6_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL6_AF15 = 0xf
	// Position of AFREL7 field.
	GPIO_AFRL_AFREL7_Pos = 0x20
	// Bit mask of AFREL7 field.
	GPIO_AFRL_AFREL7_Msk = 0xf00000000
	// AF0
	GPIO_AFRL_AFREL7_AF0 = 0x0
	// AF1
	GPIO_AFRL_AFREL7_AF1 = 0x1
	// AF2
	GPIO_AFRL_AFREL7_AF2 = 0x2
	// AF3
	GPIO_AFRL_AFREL7_AF3 = 0x3
	// AF4
	GPIO_AFRL_AFREL7_AF4 = 0x4
	// AF5
	GPIO_AFRL_AFREL7_AF5 = 0x5
	// AF6
	GPIO_AFRL_AFREL7_AF6 = 0x6
	// AF7
	GPIO_AFRL_AFREL7_AF7 = 0x7
	// AF8
	GPIO_AFRL_AFREL7_AF8 = 0x8
	// AF9
	GPIO_AFRL_AFREL7_AF9 = 0x9
	// AF10
	GPIO_AFRL_AFREL7_AF10 = 0xa
	// AF11
	GPIO_AFRL_AFREL7_AF11 = 0xb
	// AF12
	GPIO_AFRL_AFREL7_AF12 = 0xc
	// AF13
	GPIO_AFRL_AFREL7_AF13 = 0xd
	// AF14
	GPIO_AFRL_AFREL7_AF14 = 0xe
	// AF15
	GPIO_AFRL_AFREL7_AF15 = 0xf

	// AFRH: GPIO alternate function high register
	// Position of AFREL8 field.
	GPIO_AFRH_AFREL8_Pos = 0x4
	// Bit mask of AFREL8 field.
	GPIO_AFRH_AFREL8_Msk = 0xf0
	// AF0
	GPIO_AFRH_AFREL8_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL8_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL8_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL8_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL8_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL8_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL8_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL8_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL8_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL8_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL8_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL8_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL8_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL8_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL8_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL8_AF15 = 0xf
	// Position of AFREL9 field.
	GPIO_AFRH_AFREL9_Pos = 0x8
	// Bit mask of AFREL9 field.
	GPIO_AFRH_AFREL9_Msk = 0xf00
	// AF0
	GPIO_AFRH_AFREL9_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL9_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL9_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL9_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL9_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL9_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL9_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL9_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL9_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL9_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL9_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL9_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL9_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL9_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL9_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL9_AF15 = 0xf
	// Position of AFREL10 field.
	GPIO_AFRH_AFREL10_Pos = 0xc
	// Bit mask of AFREL10 field.
	GPIO_AFRH_AFREL10_Msk = 0xf000
	// AF0
	GPIO_AFRH_AFREL10_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL10_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL10_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL10_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL10_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL10_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL10_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL10_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL10_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL10_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL10_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL10_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL10_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL10_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL10_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL10_AF15 = 0xf
	// Position of AFREL11 field.
	GPIO_AFRH_AFREL11_Pos = 0x10
	// Bit mask of AFREL11 field.
	GPIO_AFRH_AFREL11_Msk = 0xf0000
	// AF0
	GPIO_AFRH_AFREL11_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL11_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL11_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL11_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL11_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL11_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL11_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL11_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL11_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL11_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL11_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL11_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL11_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL11_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL11_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL11_AF15 = 0xf
	// Position of AFREL12 field.
	GPIO_AFRH_AFREL12_Pos = 0x14
	// Bit mask of AFREL12 field.
	GPIO_AFRH_AFREL12_Msk = 0xf00000
	// AF0
	GPIO_AFRH_AFREL12_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL12_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL12_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL12_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL12_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL12_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL12_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL12_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL12_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL12_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL12_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL12_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL12_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL12_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL12_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL12_AF15 = 0xf
	// Position of AFREL13 field.
	GPIO_AFRH_AFREL13_Pos = 0x18
	// Bit mask of AFREL13 field.
	GPIO_AFRH_AFREL13_Msk = 0xf000000
	// AF0
	GPIO_AFRH_AFREL13_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL13_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL13_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL13_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL13_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL13_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL13_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL13_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL13_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL13_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL13_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL13_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL13_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL13_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL13_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL13_AF15 = 0xf
	// Position of AFREL14 field.
	GPIO_AFRH_AFREL14_Pos = 0x1c
	// Bit mask of AFREL14 field.
	GPIO_AFRH_AFREL14_Msk = 0xf0000000
	// AF0
	GPIO_AFRH_AFREL14_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL14_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL14_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL14_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL14_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL14_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL14_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL14_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL14_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL14_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL14_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL14_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL14_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL14_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL14_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL14_AF15 = 0xf
	// Position of AFREL15 field.
	GPIO_AFRH_AFREL15_Pos = 0x20
	// Bit mask of AFREL15 field.
	GPIO_AFRH_AFREL15_Msk = 0xf00000000
	// AF0
	GPIO_AFRH_AFREL15_AF0 = 0x0
	// AF1
	GPIO_AFRH_AFREL15_AF1 = 0x1
	// AF2
	GPIO_AFRH_AFREL15_AF2 = 0x2
	// AF3
	GPIO_AFRH_AFREL15_AF3 = 0x3
	// AF4
	GPIO_AFRH_AFREL15_AF4 = 0x4
	// AF5
	GPIO_AFRH_AFREL15_AF5 = 0x5
	// AF6
	GPIO_AFRH_AFREL15_AF6 = 0x6
	// AF7
	GPIO_AFRH_AFREL15_AF7 = 0x7
	// AF8
	GPIO_AFRH_AFREL15_AF8 = 0x8
	// AF9
	GPIO_AFRH_AFREL15_AF9 = 0x9
	// AF10
	GPIO_AFRH_AFREL15_AF10 = 0xa
	// AF11
	GPIO_AFRH_AFREL15_AF11 = 0xb
	// AF12
	GPIO_AFRH_AFREL15_AF12 = 0xc
	// AF13
	GPIO_AFRH_AFREL15_AF13 = 0xd
	// AF14
	GPIO_AFRH_AFREL15_AF14 = 0xe
	// AF15
	GPIO_AFRH_AFREL15_AF15 = 0xf

	// BRR: GPIO port bit reset register
	// Position of BR0 field.
	GPIO_BRR_BR0_Pos = 0x1
	// Bit mask of BR0 field.
	GPIO_BRR_BR0_Msk = 0x2
	// Bit BR0.
	GPIO_BRR_BR0 = 0x2
	// No action on the corresponding ODx bit
	GPIO_BRR_BR0_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR0_Reset = 0x1
	// Position of BR1 field.
	GPIO_BRR_BR1_Pos = 0x2
	// Bit mask of BR1 field.
	GPIO_BRR_BR1_Msk = 0x4
	// Bit BR1.
	GPIO_BRR_BR1 = 0x4
	// No action on the corresponding ODx bit
	GPIO_BRR_BR1_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR1_Reset = 0x1
	// Position of BR2 field.
	GPIO_BRR_BR2_Pos = 0x3
	// Bit mask of BR2 field.
	GPIO_BRR_BR2_Msk = 0x8
	// Bit BR2.
	GPIO_BRR_BR2 = 0x8
	// No action on the corresponding ODx bit
	GPIO_BRR_BR2_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR2_Reset = 0x1
	// Position of BR3 field.
	GPIO_BRR_BR3_Pos = 0x4
	// Bit mask of BR3 field.
	GPIO_BRR_BR3_Msk = 0x10
	// Bit BR3.
	GPIO_BRR_BR3 = 0x10
	// No action on the corresponding ODx bit
	GPIO_BRR_BR3_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR3_Reset = 0x1
	// Position of BR4 field.
	GPIO_BRR_BR4_Pos = 0x5
	// Bit mask of BR4 field.
	GPIO_BRR_BR4_Msk = 0x20
	// Bit BR4.
	GPIO_BRR_BR4 = 0x20
	// No action on the corresponding ODx bit
	GPIO_BRR_BR4_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR4_Reset = 0x1
	// Position of BR5 field.
	GPIO_BRR_BR5_Pos = 0x6
	// Bit mask of BR5 field.
	GPIO_BRR_BR5_Msk = 0x40
	// Bit BR5.
	GPIO_BRR_BR5 = 0x40
	// No action on the corresponding ODx bit
	GPIO_BRR_BR5_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR5_Reset = 0x1
	// Position of BR6 field.
	GPIO_BRR_BR6_Pos = 0x7
	// Bit mask of BR6 field.
	GPIO_BRR_BR6_Msk = 0x80
	// Bit BR6.
	GPIO_BRR_BR6 = 0x80
	// No action on the corresponding ODx bit
	GPIO_BRR_BR6_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR6_Reset = 0x1
	// Position of BR7 field.
	GPIO_BRR_BR7_Pos = 0x8
	// Bit mask of BR7 field.
	GPIO_BRR_BR7_Msk = 0x100
	// Bit BR7.
	GPIO_BRR_BR7 = 0x100
	// No action on the corresponding ODx bit
	GPIO_BRR_BR7_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR7_Reset = 0x1
	// Position of BR8 field.
	GPIO_BRR_BR8_Pos = 0x9
	// Bit mask of BR8 field.
	GPIO_BRR_BR8_Msk = 0x200
	// Bit BR8.
	GPIO_BRR_BR8 = 0x200
	// No action on the corresponding ODx bit
	GPIO_BRR_BR8_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR8_Reset = 0x1
	// Position of BR9 field.
	GPIO_BRR_BR9_Pos = 0xa
	// Bit mask of BR9 field.
	GPIO_BRR_BR9_Msk = 0x400
	// Bit BR9.
	GPIO_BRR_BR9 = 0x400
	// No action on the corresponding ODx bit
	GPIO_BRR_BR9_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR9_Reset = 0x1
	// Position of BR10 field.
	GPIO_BRR_BR10_Pos = 0xb
	// Bit mask of BR10 field.
	GPIO_BRR_BR10_Msk = 0x800
	// Bit BR10.
	GPIO_BRR_BR10 = 0x800
	// No action on the corresponding ODx bit
	GPIO_BRR_BR10_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR10_Reset = 0x1
	// Position of BR11 field.
	GPIO_BRR_BR11_Pos = 0xc
	// Bit mask of BR11 field.
	GPIO_BRR_BR11_Msk = 0x1000
	// Bit BR11.
	GPIO_BRR_BR11 = 0x1000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR11_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR11_Reset = 0x1
	// Position of BR12 field.
	GPIO_BRR_BR12_Pos = 0xd
	// Bit mask of BR12 field.
	GPIO_BRR_BR12_Msk = 0x2000
	// Bit BR12.
	GPIO_BRR_BR12 = 0x2000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR12_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR12_Reset = 0x1
	// Position of BR13 field.
	GPIO_BRR_BR13_Pos = 0xe
	// Bit mask of BR13 field.
	GPIO_BRR_BR13_Msk = 0x4000
	// Bit BR13.
	GPIO_BRR_BR13 = 0x4000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR13_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR13_Reset = 0x1
	// Position of BR14 field.
	GPIO_BRR_BR14_Pos = 0xf
	// Bit mask of BR14 field.
	GPIO_BRR_BR14_Msk = 0x8000
	// Bit BR14.
	GPIO_BRR_BR14 = 0x8000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR14_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR14_Reset = 0x1
	// Position of BR15 field.
	GPIO_BRR_BR15_Pos = 0x10
	// Bit mask of BR15 field.
	GPIO_BRR_BR15_Msk = 0x10000
	// Bit BR15.
	GPIO_BRR_BR15 = 0x10000
	// No action on the corresponding ODx bit
	GPIO_BRR_BR15_NoAction = 0x0
	// Reset the ODx bit
	GPIO_BRR_BR15_Reset = 0x1

	// SECCFGR: GPIO secure configuration register
	// Position of SEC0 field.
	GPIO_SECCFGR_SEC0_Pos = 0x0
	// Bit mask of SEC0 field.
	GPIO_SECCFGR_SEC0_Msk = 0x1
	// Bit SEC0.
	GPIO_SECCFGR_SEC0 = 0x1
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC0_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC0_Secure = 0x1
	// Position of SEC1 field.
	GPIO_SECCFGR_SEC1_Pos = 0x1
	// Bit mask of SEC1 field.
	GPIO_SECCFGR_SEC1_Msk = 0x2
	// Bit SEC1.
	GPIO_SECCFGR_SEC1 = 0x2
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC1_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC1_Secure = 0x1
	// Position of SEC2 field.
	GPIO_SECCFGR_SEC2_Pos = 0x2
	// Bit mask of SEC2 field.
	GPIO_SECCFGR_SEC2_Msk = 0x4
	// Bit SEC2.
	GPIO_SECCFGR_SEC2 = 0x4
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC2_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC2_Secure = 0x1
	// Position of SEC3 field.
	GPIO_SECCFGR_SEC3_Pos = 0x3
	// Bit mask of SEC3 field.
	GPIO_SECCFGR_SEC3_Msk = 0x8
	// Bit SEC3.
	GPIO_SECCFGR_SEC3 = 0x8
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC3_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC3_Secure = 0x1
	// Position of SEC4 field.
	GPIO_SECCFGR_SEC4_Pos = 0x4
	// Bit mask of SEC4 field.
	GPIO_SECCFGR_SEC4_Msk = 0x10
	// Bit SEC4.
	GPIO_SECCFGR_SEC4 = 0x10
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC4_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC4_Secure = 0x1
	// Position of SEC5 field.
	GPIO_SECCFGR_SEC5_Pos = 0x5
	// Bit mask of SEC5 field.
	GPIO_SECCFGR_SEC5_Msk = 0x20
	// Bit SEC5.
	GPIO_SECCFGR_SEC5 = 0x20
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC5_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC5_Secure = 0x1
	// Position of SEC6 field.
	GPIO_SECCFGR_SEC6_Pos = 0x6
	// Bit mask of SEC6 field.
	GPIO_SECCFGR_SEC6_Msk = 0x40
	// Bit SEC6.
	GPIO_SECCFGR_SEC6 = 0x40
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC6_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC6_Secure = 0x1
	// Position of SEC7 field.
	GPIO_SECCFGR_SEC7_Pos = 0x7
	// Bit mask of SEC7 field.
	GPIO_SECCFGR_SEC7_Msk = 0x80
	// Bit SEC7.
	GPIO_SECCFGR_SEC7 = 0x80
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC7_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC7_Secure = 0x1
	// Position of SEC8 field.
	GPIO_SECCFGR_SEC8_Pos = 0x8
	// Bit mask of SEC8 field.
	GPIO_SECCFGR_SEC8_Msk = 0x100
	// Bit SEC8.
	GPIO_SECCFGR_SEC8 = 0x100
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC8_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC8_Secure = 0x1
	// Position of SEC9 field.
	GPIO_SECCFGR_SEC9_Pos = 0x9
	// Bit mask of SEC9 field.
	GPIO_SECCFGR_SEC9_Msk = 0x200
	// Bit SEC9.
	GPIO_SECCFGR_SEC9 = 0x200
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC9_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC9_Secure = 0x1
	// Position of SEC10 field.
	GPIO_SECCFGR_SEC10_Pos = 0xa
	// Bit mask of SEC10 field.
	GPIO_SECCFGR_SEC10_Msk = 0x400
	// Bit SEC10.
	GPIO_SECCFGR_SEC10 = 0x400
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC10_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC10_Secure = 0x1
	// Position of SEC11 field.
	GPIO_SECCFGR_SEC11_Pos = 0xb
	// Bit mask of SEC11 field.
	GPIO_SECCFGR_SEC11_Msk = 0x800
	// Bit SEC11.
	GPIO_SECCFGR_SEC11 = 0x800
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC11_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC11_Secure = 0x1
	// Position of SEC12 field.
	GPIO_SECCFGR_SEC12_Pos = 0xc
	// Bit mask of SEC12 field.
	GPIO_SECCFGR_SEC12_Msk = 0x1000
	// Bit SEC12.
	GPIO_SECCFGR_SEC12 = 0x1000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC12_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC12_Secure = 0x1
	// Position of SEC13 field.
	GPIO_SECCFGR_SEC13_Pos = 0xd
	// Bit mask of SEC13 field.
	GPIO_SECCFGR_SEC13_Msk = 0x2000
	// Bit SEC13.
	GPIO_SECCFGR_SEC13 = 0x2000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC13_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC13_Secure = 0x1
	// Position of SEC14 field.
	GPIO_SECCFGR_SEC14_Pos = 0xe
	// Bit mask of SEC14 field.
	GPIO_SECCFGR_SEC14_Msk = 0x4000
	// Bit SEC14.
	GPIO_SECCFGR_SEC14 = 0x4000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC14_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC14_Secure = 0x1
	// Position of SEC15 field.
	GPIO_SECCFGR_SEC15_Pos = 0xf
	// Bit mask of SEC15 field.
	GPIO_SECCFGR_SEC15_Msk = 0x8000
	// Bit SEC15.
	GPIO_SECCFGR_SEC15 = 0x8000
	// The I/O pin is non-secure
	GPIO_SECCFGR_SEC15_NonSecure = 0x0
	// The I/O pin is secure
	GPIO_SECCFGR_SEC15_Secure = 0x1
)

// Constants for GTZC_MPCBB1: GTZC_MPCBB1
const (
	// CR: MPCBB control register
	// Position of LCK field.
	GTZC_CR_LCK_Pos = 0x0
	// Bit mask of LCK field.
	GTZC_CR_LCK_Msk = 0x1
	// Bit LCK.
	GTZC_CR_LCK = 0x1
	// Position of INVSECSTATE field.
	GTZC_CR_INVSECSTATE_Pos = 0x1e
	// Bit mask of INVSECSTATE field.
	GTZC_CR_INVSECSTATE_Msk = 0x40000000
	// Bit INVSECSTATE.
	GTZC_CR_INVSECSTATE = 0x40000000
	// Position of SRWILADIS field.
	GTZC_CR_SRWILADIS_Pos = 0x1f
	// Bit mask of SRWILADIS field.
	GTZC_CR_SRWILADIS_Msk = 0x80000000
	// Bit SRWILADIS.
	GTZC_CR_SRWILADIS = 0x80000000

	// LCKVTR1: MPCBB control register
	// Position of LCKSB0 field.
	GTZC_LCKVTR1_LCKSB0_Pos = 0x0
	// Bit mask of LCKSB0 field.
	GTZC_LCKVTR1_LCKSB0_Msk = 0x1
	// Bit LCKSB0.
	GTZC_LCKVTR1_LCKSB0 = 0x1
	// Position of LCKSB1 field.
	GTZC_LCKVTR1_LCKSB1_Pos = 0x1
	// Bit mask of LCKSB1 field.
	GTZC_LCKVTR1_LCKSB1_Msk = 0x2
	// Bit LCKSB1.
	GTZC_LCKVTR1_LCKSB1 = 0x2
	// Position of LCKSB2 field.
	GTZC_LCKVTR1_LCKSB2_Pos = 0x2
	// Bit mask of LCKSB2 field.
	GTZC_LCKVTR1_LCKSB2_Msk = 0x4
	// Bit LCKSB2.
	GTZC_LCKVTR1_LCKSB2 = 0x4
	// Position of LCKSB3 field.
	GTZC_LCKVTR1_LCKSB3_Pos = 0x3
	// Bit mask of LCKSB3 field.
	GTZC_LCKVTR1_LCKSB3_Msk = 0x8
	// Bit LCKSB3.
	GTZC_LCKVTR1_LCKSB3 = 0x8
	// Position of LCKSB4 field.
	GTZC_LCKVTR1_LCKSB4_Pos = 0x4
	// Bit mask of LCKSB4 field.
	GTZC_LCKVTR1_LCKSB4_Msk = 0x10
	// Bit LCKSB4.
	GTZC_LCKVTR1_LCKSB4 = 0x10
	// Position of LCKSB5 field.
	GTZC_LCKVTR1_LCKSB5_Pos = 0x5
	// Bit mask of LCKSB5 field.
	GTZC_LCKVTR1_LCKSB5_Msk = 0x20
	// Bit LCKSB5.
	GTZC_LCKVTR1_LCKSB5 = 0x20
	// Position of LCKSB6 field.
	GTZC_LCKVTR1_LCKSB6_Pos = 0x6
	// Bit mask of LCKSB6 field.
	GTZC_LCKVTR1_LCKSB6_Msk = 0x40
	// Bit LCKSB6.
	GTZC_LCKVTR1_LCKSB6 = 0x40
	// Position of LCKSB7 field.
	GTZC_LCKVTR1_LCKSB7_Pos = 0x7
	// Bit mask of LCKSB7 field.
	GTZC_LCKVTR1_LCKSB7_Msk = 0x80
	// Bit LCKSB7.
	GTZC_LCKVTR1_LCKSB7 = 0x80
	// Position of LCKSB8 field.
	GTZC_LCKVTR1_LCKSB8_Pos = 0x8
	// Bit mask of LCKSB8 field.
	GTZC_LCKVTR1_LCKSB8_Msk = 0x100
	// Bit LCKSB8.
	GTZC_LCKVTR1_LCKSB8 = 0x100
	// Position of LCKSB9 field.
	GTZC_LCKVTR1_LCKSB9_Pos = 0x9
	// Bit mask of LCKSB9 field.
	GTZC_LCKVTR1_LCKSB9_Msk = 0x200
	// Bit LCKSB9.
	GTZC_LCKVTR1_LCKSB9 = 0x200
	// Position of LCKSB10 field.
	GTZC_LCKVTR1_LCKSB10_Pos = 0xa
	// Bit mask of LCKSB10 field.
	GTZC_LCKVTR1_LCKSB10_Msk = 0x400
	// Bit LCKSB10.
	GTZC_LCKVTR1_LCKSB10 = 0x400
	// Position of LCKSB11 field.
	GTZC_LCKVTR1_LCKSB11_Pos = 0xb
	// Bit mask of LCKSB11 field.
	GTZC_LCKVTR1_LCKSB11_Msk = 0x800
	// Bit LCKSB11.
	GTZC_LCKVTR1_LCKSB11 = 0x800
	// Position of LCKSB12 field.
	GTZC_LCKVTR1_LCKSB12_Pos = 0xc
	// Bit mask of LCKSB12 field.
	GTZC_LCKVTR1_LCKSB12_Msk = 0x1000
	// Bit LCKSB12.
	GTZC_LCKVTR1_LCKSB12 = 0x1000
	// Position of LCKSB13 field.
	GTZC_LCKVTR1_LCKSB13_Pos = 0xd
	// Bit mask of LCKSB13 field.
	GTZC_LCKVTR1_LCKSB13_Msk = 0x2000
	// Bit LCKSB13.
	GTZC_LCKVTR1_LCKSB13 = 0x2000
	// Position of LCKSB14 field.
	GTZC_LCKVTR1_LCKSB14_Pos = 0xe
	// Bit mask of LCKSB14 field.
	GTZC_LCKVTR1_LCKSB14_Msk = 0x4000
	// Bit LCKSB14.
	GTZC_LCKVTR1_LCKSB14 = 0x4000
	// Position of LCKSB15 field.
	GTZC_LCKVTR1_LCKSB15_Pos = 0xf
	// Bit mask of LCKSB15 field.
	GTZC_LCKVTR1_LCKSB15_Msk = 0x8000
	// Bit LCKSB15.
	GTZC_LCKVTR1_LCKSB15 = 0x8000
	// Position of LCKSB16 field.
	GTZC_LCKVTR1_LCKSB16_Pos = 0x10
	// Bit mask of LCKSB16 field.
	GTZC_LCKVTR1_LCKSB16_Msk = 0x10000
	// Bit LCKSB16.
	GTZC_LCKVTR1_LCKSB16 = 0x10000
	// Position of LCKSB17 field.
	GTZC_LCKVTR1_LCKSB17_Pos = 0x11
	// Bit mask of LCKSB17 field.
	GTZC_LCKVTR1_LCKSB17_Msk = 0x20000
	// Bit LCKSB17.
	GTZC_LCKVTR1_LCKSB17 = 0x20000
	// Position of LCKSB18 field.
	GTZC_LCKVTR1_LCKSB18_Pos = 0x12
	// Bit mask of LCKSB18 field.
	GTZC_LCKVTR1_LCKSB18_Msk = 0x40000
	// Bit LCKSB18.
	GTZC_LCKVTR1_LCKSB18 = 0x40000
	// Position of LCKSB19 field.
	GTZC_LCKVTR1_LCKSB19_Pos = 0x13
	// Bit mask of LCKSB19 field.
	GTZC_LCKVTR1_LCKSB19_Msk = 0x80000
	// Bit LCKSB19.
	GTZC_LCKVTR1_LCKSB19 = 0x80000
	// Position of LCKSB20 field.
	GTZC_LCKVTR1_LCKSB20_Pos = 0x14
	// Bit mask of LCKSB20 field.
	GTZC_LCKVTR1_LCKSB20_Msk = 0x100000
	// Bit LCKSB20.
	GTZC_LCKVTR1_LCKSB20 = 0x100000
	// Position of LCKSB21 field.
	GTZC_LCKVTR1_LCKSB21_Pos = 0x15
	// Bit mask of LCKSB21 field.
	GTZC_LCKVTR1_LCKSB21_Msk = 0x200000
	// Bit LCKSB21.
	GTZC_LCKVTR1_LCKSB21 = 0x200000
	// Position of LCKSB22 field.
	GTZC_LCKVTR1_LCKSB22_Pos = 0x16
	// Bit mask of LCKSB22 field.
	GTZC_LCKVTR1_LCKSB22_Msk = 0x400000
	// Bit LCKSB22.
	GTZC_LCKVTR1_LCKSB22 = 0x400000
	// Position of LCKSB23 field.
	GTZC_LCKVTR1_LCKSB23_Pos = 0x17
	// Bit mask of LCKSB23 field.
	GTZC_LCKVTR1_LCKSB23_Msk = 0x800000
	// Bit LCKSB23.
	GTZC_LCKVTR1_LCKSB23 = 0x800000
	// Position of LCKSB24 field.
	GTZC_LCKVTR1_LCKSB24_Pos = 0x18
	// Bit mask of LCKSB24 field.
	GTZC_LCKVTR1_LCKSB24_Msk = 0x1000000
	// Bit LCKSB24.
	GTZC_LCKVTR1_LCKSB24 = 0x1000000
	// Position of LCKSB25 field.
	GTZC_LCKVTR1_LCKSB25_Pos = 0x19
	// Bit mask of LCKSB25 field.
	GTZC_LCKVTR1_LCKSB25_Msk = 0x2000000
	// Bit LCKSB25.
	GTZC_LCKVTR1_LCKSB25 = 0x2000000
	// Position of LCKSB26 field.
	GTZC_LCKVTR1_LCKSB26_Pos = 0x1a
	// Bit mask of LCKSB26 field.
	GTZC_LCKVTR1_LCKSB26_Msk = 0x4000000
	// Bit LCKSB26.
	GTZC_LCKVTR1_LCKSB26 = 0x4000000
	// Position of LCKSB27 field.
	GTZC_LCKVTR1_LCKSB27_Pos = 0x1b
	// Bit mask of LCKSB27 field.
	GTZC_LCKVTR1_LCKSB27_Msk = 0x8000000
	// Bit LCKSB27.
	GTZC_LCKVTR1_LCKSB27 = 0x8000000
	// Position of LCKSB28 field.
	GTZC_LCKVTR1_LCKSB28_Pos = 0x1c
	// Bit mask of LCKSB28 field.
	GTZC_LCKVTR1_LCKSB28_Msk = 0x10000000
	// Bit LCKSB28.
	GTZC_LCKVTR1_LCKSB28 = 0x10000000
	// Position of LCKSB29 field.
	GTZC_LCKVTR1_LCKSB29_Pos = 0x1d
	// Bit mask of LCKSB29 field.
	GTZC_LCKVTR1_LCKSB29_Msk = 0x20000000
	// Bit LCKSB29.
	GTZC_LCKVTR1_LCKSB29 = 0x20000000
	// Position of LCKSB30 field.
	GTZC_LCKVTR1_LCKSB30_Pos = 0x1e
	// Bit mask of LCKSB30 field.
	GTZC_LCKVTR1_LCKSB30_Msk = 0x40000000
	// Bit LCKSB30.
	GTZC_LCKVTR1_LCKSB30 = 0x40000000
	// Position of LCKSB31 field.
	GTZC_LCKVTR1_LCKSB31_Pos = 0x1f
	// Bit mask of LCKSB31 field.
	GTZC_LCKVTR1_LCKSB31_Msk = 0x80000000
	// Bit LCKSB31.
	GTZC_LCKVTR1_LCKSB31 = 0x80000000

	// LCKVTR2: MPCBB control register
	// Position of LCKSB32 field.
	GTZC_LCKVTR2_LCKSB32_Pos = 0x0
	// Bit mask of LCKSB32 field.
	GTZC_LCKVTR2_LCKSB32_Msk = 0x1
	// Bit LCKSB32.
	GTZC_LCKVTR2_LCKSB32 = 0x1
	// Position of LCKSB33 field.
	GTZC_LCKVTR2_LCKSB33_Pos = 0x1
	// Bit mask of LCKSB33 field.
	GTZC_LCKVTR2_LCKSB33_Msk = 0x2
	// Bit LCKSB33.
	GTZC_LCKVTR2_LCKSB33 = 0x2
	// Position of LCKSB34 field.
	GTZC_LCKVTR2_LCKSB34_Pos = 0x2
	// Bit mask of LCKSB34 field.
	GTZC_LCKVTR2_LCKSB34_Msk = 0x4
	// Bit LCKSB34.
	GTZC_LCKVTR2_LCKSB34 = 0x4
	// Position of LCKSB35 field.
	GTZC_LCKVTR2_LCKSB35_Pos = 0x3
	// Bit mask of LCKSB35 field.
	GTZC_LCKVTR2_LCKSB35_Msk = 0x8
	// Bit LCKSB35.
	GTZC_LCKVTR2_LCKSB35 = 0x8
	// Position of LCKSB36 field.
	GTZC_LCKVTR2_LCKSB36_Pos = 0x4
	// Bit mask of LCKSB36 field.
	GTZC_LCKVTR2_LCKSB36_Msk = 0x10
	// Bit LCKSB36.
	GTZC_LCKVTR2_LCKSB36 = 0x10
	// Position of LCKSB37 field.
	GTZC_LCKVTR2_LCKSB37_Pos = 0x5
	// Bit mask of LCKSB37 field.
	GTZC_LCKVTR2_LCKSB37_Msk = 0x20
	// Bit LCKSB37.
	GTZC_LCKVTR2_LCKSB37 = 0x20
	// Position of LCKSB38 field.
	GTZC_LCKVTR2_LCKSB38_Pos = 0x6
	// Bit mask of LCKSB38 field.
	GTZC_LCKVTR2_LCKSB38_Msk = 0x40
	// Bit LCKSB38.
	GTZC_LCKVTR2_LCKSB38 = 0x40
	// Position of LCKSB39 field.
	GTZC_LCKVTR2_LCKSB39_Pos = 0x7
	// Bit mask of LCKSB39 field.
	GTZC_LCKVTR2_LCKSB39_Msk = 0x80
	// Bit LCKSB39.
	GTZC_LCKVTR2_LCKSB39 = 0x80
	// Position of LCKSB40 field.
	GTZC_LCKVTR2_LCKSB40_Pos = 0x8
	// Bit mask of LCKSB40 field.
	GTZC_LCKVTR2_LCKSB40_Msk = 0x100
	// Bit LCKSB40.
	GTZC_LCKVTR2_LCKSB40 = 0x100
	// Position of LCKSB41 field.
	GTZC_LCKVTR2_LCKSB41_Pos = 0x9
	// Bit mask of LCKSB41 field.
	GTZC_LCKVTR2_LCKSB41_Msk = 0x200
	// Bit LCKSB41.
	GTZC_LCKVTR2_LCKSB41 = 0x200
	// Position of LCKSB42 field.
	GTZC_LCKVTR2_LCKSB42_Pos = 0xa
	// Bit mask of LCKSB42 field.
	GTZC_LCKVTR2_LCKSB42_Msk = 0x400
	// Bit LCKSB42.
	GTZC_LCKVTR2_LCKSB42 = 0x400
	// Position of LCKSB43 field.
	GTZC_LCKVTR2_LCKSB43_Pos = 0xb
	// Bit mask of LCKSB43 field.
	GTZC_LCKVTR2_LCKSB43_Msk = 0x800
	// Bit LCKSB43.
	GTZC_LCKVTR2_LCKSB43 = 0x800
	// Position of LCKSB44 field.
	GTZC_LCKVTR2_LCKSB44_Pos = 0xc
	// Bit mask of LCKSB44 field.
	GTZC_LCKVTR2_LCKSB44_Msk = 0x1000
	// Bit LCKSB44.
	GTZC_LCKVTR2_LCKSB44 = 0x1000
	// Position of LCKSB45 field.
	GTZC_LCKVTR2_LCKSB45_Pos = 0xd
	// Bit mask of LCKSB45 field.
	GTZC_LCKVTR2_LCKSB45_Msk = 0x2000
	// Bit LCKSB45.
	GTZC_LCKVTR2_LCKSB45 = 0x2000
	// Position of LCKSB46 field.
	GTZC_LCKVTR2_LCKSB46_Pos = 0xe
	// Bit mask of LCKSB46 field.
	GTZC_LCKVTR2_LCKSB46_Msk = 0x4000
	// Bit LCKSB46.
	GTZC_LCKVTR2_LCKSB46 = 0x4000
	// Position of LCKSB47 field.
	GTZC_LCKVTR2_LCKSB47_Pos = 0xf
	// Bit mask of LCKSB47 field.
	GTZC_LCKVTR2_LCKSB47_Msk = 0x8000
	// Bit LCKSB47.
	GTZC_LCKVTR2_LCKSB47 = 0x8000
	// Position of LCKSB48 field.
	GTZC_LCKVTR2_LCKSB48_Pos = 0x10
	// Bit mask of LCKSB48 field.
	GTZC_LCKVTR2_LCKSB48_Msk = 0x10000
	// Bit LCKSB48.
	GTZC_LCKVTR2_LCKSB48 = 0x10000
	// Position of LCKSB49 field.
	GTZC_LCKVTR2_LCKSB49_Pos = 0x11
	// Bit mask of LCKSB49 field.
	GTZC_LCKVTR2_LCKSB49_Msk = 0x20000
	// Bit LCKSB49.
	GTZC_LCKVTR2_LCKSB49 = 0x20000
	// Position of LCKSB50 field.
	GTZC_LCKVTR2_LCKSB50_Pos = 0x12
	// Bit mask of LCKSB50 field.
	GTZC_LCKVTR2_LCKSB50_Msk = 0x40000
	// Bit LCKSB50.
	GTZC_LCKVTR2_LCKSB50 = 0x40000
	// Position of LCKSB51 field.
	GTZC_LCKVTR2_LCKSB51_Pos = 0x13
	// Bit mask of LCKSB51 field.
	GTZC_LCKVTR2_LCKSB51_Msk = 0x80000
	// Bit LCKSB51.
	GTZC_LCKVTR2_LCKSB51 = 0x80000
	// Position of LCKSB52 field.
	GTZC_LCKVTR2_LCKSB52_Pos = 0x14
	// Bit mask of LCKSB52 field.
	GTZC_LCKVTR2_LCKSB52_Msk = 0x100000
	// Bit LCKSB52.
	GTZC_LCKVTR2_LCKSB52 = 0x100000
	// Position of LCKSB53 field.
	GTZC_LCKVTR2_LCKSB53_Pos = 0x15
	// Bit mask of LCKSB53 field.
	GTZC_LCKVTR2_LCKSB53_Msk = 0x200000
	// Bit LCKSB53.
	GTZC_LCKVTR2_LCKSB53 = 0x200000
	// Position of LCKSB54 field.
	GTZC_LCKVTR2_LCKSB54_Pos = 0x16
	// Bit mask of LCKSB54 field.
	GTZC_LCKVTR2_LCKSB54_Msk = 0x400000
	// Bit LCKSB54.
	GTZC_LCKVTR2_LCKSB54 = 0x400000
	// Position of LCKSB55 field.
	GTZC_LCKVTR2_LCKSB55_Pos = 0x17
	// Bit mask of LCKSB55 field.
	GTZC_LCKVTR2_LCKSB55_Msk = 0x800000
	// Bit LCKSB55.
	GTZC_LCKVTR2_LCKSB55 = 0x800000
	// Position of LCKSB56 field.
	GTZC_LCKVTR2_LCKSB56_Pos = 0x18
	// Bit mask of LCKSB56 field.
	GTZC_LCKVTR2_LCKSB56_Msk = 0x1000000
	// Bit LCKSB56.
	GTZC_LCKVTR2_LCKSB56 = 0x1000000
	// Position of LCKSB57 field.
	GTZC_LCKVTR2_LCKSB57_Pos = 0x19
	// Bit mask of LCKSB57 field.
	GTZC_LCKVTR2_LCKSB57_Msk = 0x2000000
	// Bit LCKSB57.
	GTZC_LCKVTR2_LCKSB57 = 0x2000000
	// Position of LCKSB58 field.
	GTZC_LCKVTR2_LCKSB58_Pos = 0x1a
	// Bit mask of LCKSB58 field.
	GTZC_LCKVTR2_LCKSB58_Msk = 0x4000000
	// Bit LCKSB58.
	GTZC_LCKVTR2_LCKSB58 = 0x4000000
	// Position of LCKSB59 field.
	GTZC_LCKVTR2_LCKSB59_Pos = 0x1b
	// Bit mask of LCKSB59 field.
	GTZC_LCKVTR2_LCKSB59_Msk = 0x8000000
	// Bit LCKSB59.
	GTZC_LCKVTR2_LCKSB59 = 0x8000000
	// Position of LCKSB60 field.
	GTZC_LCKVTR2_LCKSB60_Pos = 0x1c
	// Bit mask of LCKSB60 field.
	GTZC_LCKVTR2_LCKSB60_Msk = 0x10000000
	// Bit LCKSB60.
	GTZC_LCKVTR2_LCKSB60 = 0x10000000
	// Position of LCKSB61 field.
	GTZC_LCKVTR2_LCKSB61_Pos = 0x1d
	// Bit mask of LCKSB61 field.
	GTZC_LCKVTR2_LCKSB61_Msk = 0x20000000
	// Bit LCKSB61.
	GTZC_LCKVTR2_LCKSB61 = 0x20000000
	// Position of LCKSB62 field.
	GTZC_LCKVTR2_LCKSB62_Pos = 0x1e
	// Bit mask of LCKSB62 field.
	GTZC_LCKVTR2_LCKSB62_Msk = 0x40000000
	// Bit LCKSB62.
	GTZC_LCKVTR2_LCKSB62 = 0x40000000
	// Position of LCKSB63 field.
	GTZC_LCKVTR2_LCKSB63_Pos = 0x1f
	// Bit mask of LCKSB63 field.
	GTZC_LCKVTR2_LCKSB63_Msk = 0x80000000
	// Bit LCKSB63.
	GTZC_LCKVTR2_LCKSB63 = 0x80000000

	// VCTR0: MPCBBx vector register
	// Position of B0 field.
	GTZC_VCTR0_B0_Pos = 0x0
	// Bit mask of B0 field.
	GTZC_VCTR0_B0_Msk = 0x1
	// Bit B0.
	GTZC_VCTR0_B0 = 0x1
	// Position of B1 field.
	GTZC_VCTR0_B1_Pos = 0x1
	// Bit mask of B1 field.
	GTZC_VCTR0_B1_Msk = 0x2
	// Bit B1.
	GTZC_VCTR0_B1 = 0x2
	// Position of B2 field.
	GTZC_VCTR0_B2_Pos = 0x2
	// Bit mask of B2 field.
	GTZC_VCTR0_B2_Msk = 0x4
	// Bit B2.
	GTZC_VCTR0_B2 = 0x4
	// Position of B3 field.
	GTZC_VCTR0_B3_Pos = 0x3
	// Bit mask of B3 field.
	GTZC_VCTR0_B3_Msk = 0x8
	// Bit B3.
	GTZC_VCTR0_B3 = 0x8
	// Position of B4 field.
	GTZC_VCTR0_B4_Pos = 0x4
	// Bit mask of B4 field.
	GTZC_VCTR0_B4_Msk = 0x10
	// Bit B4.
	GTZC_VCTR0_B4 = 0x10
	// Position of B5 field.
	GTZC_VCTR0_B5_Pos = 0x5
	// Bit mask of B5 field.
	GTZC_VCTR0_B5_Msk = 0x20
	// Bit B5.
	GTZC_VCTR0_B5 = 0x20
	// Position of B6 field.
	GTZC_VCTR0_B6_Pos = 0x6
	// Bit mask of B6 field.
	GTZC_VCTR0_B6_Msk = 0x40
	// Bit B6.
	GTZC_VCTR0_B6 = 0x40
	// Position of B7 field.
	GTZC_VCTR0_B7_Pos = 0x7
	// Bit mask of B7 field.
	GTZC_VCTR0_B7_Msk = 0x80
	// Bit B7.
	GTZC_VCTR0_B7 = 0x80
	// Position of B8 field.
	GTZC_VCTR0_B8_Pos = 0x8
	// Bit mask of B8 field.
	GTZC_VCTR0_B8_Msk = 0x100
	// Bit B8.
	GTZC_VCTR0_B8 = 0x100
	// Position of B9 field.
	GTZC_VCTR0_B9_Pos = 0x9
	// Bit mask of B9 field.
	GTZC_VCTR0_B9_Msk = 0x200
	// Bit B9.
	GTZC_VCTR0_B9 = 0x200
	// Position of B10 field.
	GTZC_VCTR0_B10_Pos = 0xa
	// Bit mask of B10 field.
	GTZC_VCTR0_B10_Msk = 0x400
	// Bit B10.
	GTZC_VCTR0_B10 = 0x400
	// Position of B11 field.
	GTZC_VCTR0_B11_Pos = 0xb
	// Bit mask of B11 field.
	GTZC_VCTR0_B11_Msk = 0x800
	// Bit B11.
	GTZC_VCTR0_B11 = 0x800
	// Position of B12 field.
	GTZC_VCTR0_B12_Pos = 0xc
	// Bit mask of B12 field.
	GTZC_VCTR0_B12_Msk = 0x1000
	// Bit B12.
	GTZC_VCTR0_B12 = 0x1000
	// Position of B13 field.
	GTZC_VCTR0_B13_Pos = 0xd
	// Bit mask of B13 field.
	GTZC_VCTR0_B13_Msk = 0x2000
	// Bit B13.
	GTZC_VCTR0_B13 = 0x2000
	// Position of B14 field.
	GTZC_VCTR0_B14_Pos = 0xe
	// Bit mask of B14 field.
	GTZC_VCTR0_B14_Msk = 0x4000
	// Bit B14.
	GTZC_VCTR0_B14 = 0x4000
	// Position of B15 field.
	GTZC_VCTR0_B15_Pos = 0xf
	// Bit mask of B15 field.
	GTZC_VCTR0_B15_Msk = 0x8000
	// Bit B15.
	GTZC_VCTR0_B15 = 0x8000
	// Position of B16 field.
	GTZC_VCTR0_B16_Pos = 0x10
	// Bit mask of B16 field.
	GTZC_VCTR0_B16_Msk = 0x10000
	// Bit B16.
	GTZC_VCTR0_B16 = 0x10000
	// Position of B17 field.
	GTZC_VCTR0_B17_Pos = 0x11
	// Bit mask of B17 field.
	GTZC_VCTR0_B17_Msk = 0x20000
	// Bit B17.
	GTZC_VCTR0_B17 = 0x20000
	// Position of B18 field.
	GTZC_VCTR0_B18_Pos = 0x12
	// Bit mask of B18 field.
	GTZC_VCTR0_B18_Msk = 0x40000
	// Bit B18.
	GTZC_VCTR0_B18 = 0x40000
	// Position of B19 field.
	GTZC_VCTR0_B19_Pos = 0x13
	// Bit mask of B19 field.
	GTZC_VCTR0_B19_Msk = 0x80000
	// Bit B19.
	GTZC_VCTR0_B19 = 0x80000
	// Position of B20 field.
	GTZC_VCTR0_B20_Pos = 0x14
	// Bit mask of B20 field.
	GTZC_VCTR0_B20_Msk = 0x100000
	// Bit B20.
	GTZC_VCTR0_B20 = 0x100000
	// Position of B21 field.
	GTZC_VCTR0_B21_Pos = 0x15
	// Bit mask of B21 field.
	GTZC_VCTR0_B21_Msk = 0x200000
	// Bit B21.
	GTZC_VCTR0_B21 = 0x200000
	// Position of B22 field.
	GTZC_VCTR0_B22_Pos = 0x16
	// Bit mask of B22 field.
	GTZC_VCTR0_B22_Msk = 0x400000
	// Bit B22.
	GTZC_VCTR0_B22 = 0x400000
	// Position of B23 field.
	GTZC_VCTR0_B23_Pos = 0x17
	// Bit mask of B23 field.
	GTZC_VCTR0_B23_Msk = 0x800000
	// Bit B23.
	GTZC_VCTR0_B23 = 0x800000
	// Position of B24 field.
	GTZC_VCTR0_B24_Pos = 0x18
	// Bit mask of B24 field.
	GTZC_VCTR0_B24_Msk = 0x1000000
	// Bit B24.
	GTZC_VCTR0_B24 = 0x1000000
	// Position of B25 field.
	GTZC_VCTR0_B25_Pos = 0x19
	// Bit mask of B25 field.
	GTZC_VCTR0_B25_Msk = 0x2000000
	// Bit B25.
	GTZC_VCTR0_B25 = 0x2000000
	// Position of B26 field.
	GTZC_VCTR0_B26_Pos = 0x1a
	// Bit mask of B26 field.
	GTZC_VCTR0_B26_Msk = 0x4000000
	// Bit B26.
	GTZC_VCTR0_B26 = 0x4000000
	// Position of B27 field.
	GTZC_VCTR0_B27_Pos = 0x1b
	// Bit mask of B27 field.
	GTZC_VCTR0_B27_Msk = 0x8000000
	// Bit B27.
	GTZC_VCTR0_B27 = 0x8000000
	// Position of B28 field.
	GTZC_VCTR0_B28_Pos = 0x1c
	// Bit mask of B28 field.
	GTZC_VCTR0_B28_Msk = 0x10000000
	// Bit B28.
	GTZC_VCTR0_B28 = 0x10000000
	// Position of B29 field.
	GTZC_VCTR0_B29_Pos = 0x1d
	// Bit mask of B29 field.
	GTZC_VCTR0_B29_Msk = 0x20000000
	// Bit B29.
	GTZC_VCTR0_B29 = 0x20000000
	// Position of B30 field.
	GTZC_VCTR0_B30_Pos = 0x1e
	// Bit mask of B30 field.
	GTZC_VCTR0_B30_Msk = 0x40000000
	// Bit B30.
	GTZC_VCTR0_B30 = 0x40000000
	// Position of B31 field.
	GTZC_VCTR0_B31_Pos = 0x1f
	// Bit mask of B31 field.
	GTZC_VCTR0_B31_Msk = 0x80000000
	// Bit B31.
	GTZC_VCTR0_B31 = 0x80000000

	// VCTR1: MPCBBx vector register
	// Position of B32 field.
	GTZC_VCTR1_B32_Pos = 0x0
	// Bit mask of B32 field.
	GTZC_VCTR1_B32_Msk = 0x1
	// Bit B32.
	GTZC_VCTR1_B32 = 0x1
	// Position of B33 field.
	GTZC_VCTR1_B33_Pos = 0x1
	// Bit mask of B33 field.
	GTZC_VCTR1_B33_Msk = 0x2
	// Bit B33.
	GTZC_VCTR1_B33 = 0x2
	// Position of B34 field.
	GTZC_VCTR1_B34_Pos = 0x2
	// Bit mask of B34 field.
	GTZC_VCTR1_B34_Msk = 0x4
	// Bit B34.
	GTZC_VCTR1_B34 = 0x4
	// Position of B35 field.
	GTZC_VCTR1_B35_Pos = 0x3
	// Bit mask of B35 field.
	GTZC_VCTR1_B35_Msk = 0x8
	// Bit B35.
	GTZC_VCTR1_B35 = 0x8
	// Position of B36 field.
	GTZC_VCTR1_B36_Pos = 0x4
	// Bit mask of B36 field.
	GTZC_VCTR1_B36_Msk = 0x10
	// Bit B36.
	GTZC_VCTR1_B36 = 0x10
	// Position of B37 field.
	GTZC_VCTR1_B37_Pos = 0x5
	// Bit mask of B37 field.
	GTZC_VCTR1_B37_Msk = 0x20
	// Bit B37.
	GTZC_VCTR1_B37 = 0x20
	// Position of B38 field.
	GTZC_VCTR1_B38_Pos = 0x6
	// Bit mask of B38 field.
	GTZC_VCTR1_B38_Msk = 0x40
	// Bit B38.
	GTZC_VCTR1_B38 = 0x40
	// Position of B39 field.
	GTZC_VCTR1_B39_Pos = 0x7
	// Bit mask of B39 field.
	GTZC_VCTR1_B39_Msk = 0x80
	// Bit B39.
	GTZC_VCTR1_B39 = 0x80
	// Position of B40 field.
	GTZC_VCTR1_B40_Pos = 0x8
	// Bit mask of B40 field.
	GTZC_VCTR1_B40_Msk = 0x100
	// Bit B40.
	GTZC_VCTR1_B40 = 0x100
	// Position of B41 field.
	GTZC_VCTR1_B41_Pos = 0x9
	// Bit mask of B41 field.
	GTZC_VCTR1_B41_Msk = 0x200
	// Bit B41.
	GTZC_VCTR1_B41 = 0x200
	// Position of B42 field.
	GTZC_VCTR1_B42_Pos = 0xa
	// Bit mask of B42 field.
	GTZC_VCTR1_B42_Msk = 0x400
	// Bit B42.
	GTZC_VCTR1_B42 = 0x400
	// Position of B43 field.
	GTZC_VCTR1_B43_Pos = 0xb
	// Bit mask of B43 field.
	GTZC_VCTR1_B43_Msk = 0x800
	// Bit B43.
	GTZC_VCTR1_B43 = 0x800
	// Position of B44 field.
	GTZC_VCTR1_B44_Pos = 0xc
	// Bit mask of B44 field.
	GTZC_VCTR1_B44_Msk = 0x1000
	// Bit B44.
	GTZC_VCTR1_B44 = 0x1000
	// Position of B45 field.
	GTZC_VCTR1_B45_Pos = 0xd
	// Bit mask of B45 field.
	GTZC_VCTR1_B45_Msk = 0x2000
	// Bit B45.
	GTZC_VCTR1_B45 = 0x2000
	// Position of B46 field.
	GTZC_VCTR1_B46_Pos = 0xe
	// Bit mask of B46 field.
	GTZC_VCTR1_B46_Msk = 0x4000
	// Bit B46.
	GTZC_VCTR1_B46 = 0x4000
	// Position of B47 field.
	GTZC_VCTR1_B47_Pos = 0xf
	// Bit mask of B47 field.
	GTZC_VCTR1_B47_Msk = 0x8000
	// Bit B47.
	GTZC_VCTR1_B47 = 0x8000
	// Position of B48 field.
	GTZC_VCTR1_B48_Pos = 0x10
	// Bit mask of B48 field.
	GTZC_VCTR1_B48_Msk = 0x10000
	// Bit B48.
	GTZC_VCTR1_B48 = 0x10000
	// Position of B49 field.
	GTZC_VCTR1_B49_Pos = 0x11
	// Bit mask of B49 field.
	GTZC_VCTR1_B49_Msk = 0x20000
	// Bit B49.
	GTZC_VCTR1_B49 = 0x20000
	// Position of B50 field.
	GTZC_VCTR1_B50_Pos = 0x12
	// Bit mask of B50 field.
	GTZC_VCTR1_B50_Msk = 0x40000
	// Bit B50.
	GTZC_VCTR1_B50 = 0x40000
	// Position of B51 field.
	GTZC_VCTR1_B51_Pos = 0x13
	// Bit mask of B51 field.
	GTZC_VCTR1_B51_Msk = 0x80000
	// Bit B51.
	GTZC_VCTR1_B51 = 0x80000
	// Position of B52 field.
	GTZC_VCTR1_B52_Pos = 0x14
	// Bit mask of B52 field.
	GTZC_VCTR1_B52_Msk = 0x100000
	// Bit B52.
	GTZC_VCTR1_B52 = 0x100000
	// Position of B53 field.
	GTZC_VCTR1_B53_Pos = 0x15
	// Bit mask of B53 field.
	GTZC_VCTR1_B53_Msk = 0x200000
	// Bit B53.
	GTZC_VCTR1_B53 = 0x200000
	// Position of B54 field.
	GTZC_VCTR1_B54_Pos = 0x16
	// Bit mask of B54 field.
	GTZC_VCTR1_B54_Msk = 0x400000
	// Bit B54.
	GTZC_VCTR1_B54 = 0x400000
	// Position of B55 field.
	GTZC_VCTR1_B55_Pos = 0x17
	// Bit mask of B55 field.
	GTZC_VCTR1_B55_Msk = 0x800000
	// Bit B55.
	GTZC_VCTR1_B55 = 0x800000
	// Position of B56 field.
	GTZC_VCTR1_B56_Pos = 0x18
	// Bit mask of B56 field.
	GTZC_VCTR1_B56_Msk = 0x1000000
	// Bit B56.
	GTZC_VCTR1_B56 = 0x1000000
	// Position of B57 field.
	GTZC_VCTR1_B57_Pos = 0x19
	// Bit mask of B57 field.
	GTZC_VCTR1_B57_Msk = 0x2000000
	// Bit B57.
	GTZC_VCTR1_B57 = 0x2000000
	// Position of B58 field.
	GTZC_VCTR1_B58_Pos = 0x1a
	// Bit mask of B58 field.
	GTZC_VCTR1_B58_Msk = 0x4000000
	// Bit B58.
	GTZC_VCTR1_B58 = 0x4000000
	// Position of B59 field.
	GTZC_VCTR1_B59_Pos = 0x1b
	// Bit mask of B59 field.
	GTZC_VCTR1_B59_Msk = 0x8000000
	// Bit B59.
	GTZC_VCTR1_B59 = 0x8000000
	// Position of B60 field.
	GTZC_VCTR1_B60_Pos = 0x1c
	// Bit mask of B60 field.
	GTZC_VCTR1_B60_Msk = 0x10000000
	// Bit B60.
	GTZC_VCTR1_B60 = 0x10000000
	// Position of B61 field.
	GTZC_VCTR1_B61_Pos = 0x1d
	// Bit mask of B61 field.
	GTZC_VCTR1_B61_Msk = 0x20000000
	// Bit B61.
	GTZC_VCTR1_B61 = 0x20000000
	// Position of B62 field.
	GTZC_VCTR1_B62_Pos = 0x1e
	// Bit mask of B62 field.
	GTZC_VCTR1_B62_Msk = 0x40000000
	// Bit B62.
	GTZC_VCTR1_B62 = 0x40000000
	// Position of B63 field.
	GTZC_VCTR1_B63_Pos = 0x1f
	// Bit mask of B63 field.
	GTZC_VCTR1_B63_Msk = 0x80000000
	// Bit B63.
	GTZC_VCTR1_B63 = 0x80000000

	// VCTR2: MPCBBx vector register
	// Position of B64 field.
	GTZC_VCTR2_B64_Pos = 0x0
	// Bit mask of B64 field.
	GTZC_VCTR2_B64_Msk = 0x1
	// Bit B64.
	GTZC_VCTR2_B64 = 0x1
	// Position of B65 field.
	GTZC_VCTR2_B65_Pos = 0x1
	// Bit mask of B65 field.
	GTZC_VCTR2_B65_Msk = 0x2
	// Bit B65.
	GTZC_VCTR2_B65 = 0x2
	// Position of B66 field.
	GTZC_VCTR2_B66_Pos = 0x2
	// Bit mask of B66 field.
	GTZC_VCTR2_B66_Msk = 0x4
	// Bit B66.
	GTZC_VCTR2_B66 = 0x4
	// Position of B67 field.
	GTZC_VCTR2_B67_Pos = 0x3
	// Bit mask of B67 field.
	GTZC_VCTR2_B67_Msk = 0x8
	// Bit B67.
	GTZC_VCTR2_B67 = 0x8
	// Position of B68 field.
	GTZC_VCTR2_B68_Pos = 0x4
	// Bit mask of B68 field.
	GTZC_VCTR2_B68_Msk = 0x10
	// Bit B68.
	GTZC_VCTR2_B68 = 0x10
	// Position of B69 field.
	GTZC_VCTR2_B69_Pos = 0x5
	// Bit mask of B69 field.
	GTZC_VCTR2_B69_Msk = 0x20
	// Bit B69.
	GTZC_VCTR2_B69 = 0x20
	// Position of B70 field.
	GTZC_VCTR2_B70_Pos = 0x6
	// Bit mask of B70 field.
	GTZC_VCTR2_B70_Msk = 0x40
	// Bit B70.
	GTZC_VCTR2_B70 = 0x40
	// Position of B71 field.
	GTZC_VCTR2_B71_Pos = 0x7
	// Bit mask of B71 field.
	GTZC_VCTR2_B71_Msk = 0x80
	// Bit B71.
	GTZC_VCTR2_B71 = 0x80
	// Position of B72 field.
	GTZC_VCTR2_B72_Pos = 0x8
	// Bit mask of B72 field.
	GTZC_VCTR2_B72_Msk = 0x100
	// Bit B72.
	GTZC_VCTR2_B72 = 0x100
	// Position of B73 field.
	GTZC_VCTR2_B73_Pos = 0x9
	// Bit mask of B73 field.
	GTZC_VCTR2_B73_Msk = 0x200
	// Bit B73.
	GTZC_VCTR2_B73 = 0x200
	// Position of B74 field.
	GTZC_VCTR2_B74_Pos = 0xa
	// Bit mask of B74 field.
	GTZC_VCTR2_B74_Msk = 0x400
	// Bit B74.
	GTZC_VCTR2_B74 = 0x400
	// Position of B75 field.
	GTZC_VCTR2_B75_Pos = 0xb
	// Bit mask of B75 field.
	GTZC_VCTR2_B75_Msk = 0x800
	// Bit B75.
	GTZC_VCTR2_B75 = 0x800
	// Position of B76 field.
	GTZC_VCTR2_B76_Pos = 0xc
	// Bit mask of B76 field.
	GTZC_VCTR2_B76_Msk = 0x1000
	// Bit B76.
	GTZC_VCTR2_B76 = 0x1000
	// Position of B77 field.
	GTZC_VCTR2_B77_Pos = 0xd
	// Bit mask of B77 field.
	GTZC_VCTR2_B77_Msk = 0x2000
	// Bit B77.
	GTZC_VCTR2_B77 = 0x2000
	// Position of B78 field.
	GTZC_VCTR2_B78_Pos = 0xe
	// Bit mask of B78 field.
	GTZC_VCTR2_B78_Msk = 0x4000
	// Bit B78.
	GTZC_VCTR2_B78 = 0x4000
	// Position of B79 field.
	GTZC_VCTR2_B79_Pos = 0xf
	// Bit mask of B79 field.
	GTZC_VCTR2_B79_Msk = 0x8000
	// Bit B79.
	GTZC_VCTR2_B79 = 0x8000
	// Position of B80 field.
	GTZC_VCTR2_B80_Pos = 0x10
	// Bit mask of B80 field.
	GTZC_VCTR2_B80_Msk = 0x10000
	// Bit B80.
	GTZC_VCTR2_B80 = 0x10000
	// Position of B81 field.
	GTZC_VCTR2_B81_Pos = 0x11
	// Bit mask of B81 field.
	GTZC_VCTR2_B81_Msk = 0x20000
	// Bit B81.
	GTZC_VCTR2_B81 = 0x20000
	// Position of B82 field.
	GTZC_VCTR2_B82_Pos = 0x12
	// Bit mask of B82 field.
	GTZC_VCTR2_B82_Msk = 0x40000
	// Bit B82.
	GTZC_VCTR2_B82 = 0x40000
	// Position of B83 field.
	GTZC_VCTR2_B83_Pos = 0x13
	// Bit mask of B83 field.
	GTZC_VCTR2_B83_Msk = 0x80000
	// Bit B83.
	GTZC_VCTR2_B83 = 0x80000
	// Position of B84 field.
	GTZC_VCTR2_B84_Pos = 0x14
	// Bit mask of B84 field.
	GTZC_VCTR2_B84_Msk = 0x100000
	// Bit B84.
	GTZC_VCTR2_B84 = 0x100000
	// Position of B85 field.
	GTZC_VCTR2_B85_Pos = 0x15
	// Bit mask of B85 field.
	GTZC_VCTR2_B85_Msk = 0x200000
	// Bit B85.
	GTZC_VCTR2_B85 = 0x200000
	// Position of B86 field.
	GTZC_VCTR2_B86_Pos = 0x16
	// Bit mask of B86 field.
	GTZC_VCTR2_B86_Msk = 0x400000
	// Bit B86.
	GTZC_VCTR2_B86 = 0x400000
	// Position of B87 field.
	GTZC_VCTR2_B87_Pos = 0x17
	// Bit mask of B87 field.
	GTZC_VCTR2_B87_Msk = 0x800000
	// Bit B87.
	GTZC_VCTR2_B87 = 0x800000
	// Position of B88 field.
	GTZC_VCTR2_B88_Pos = 0x18
	// Bit mask of B88 field.
	GTZC_VCTR2_B88_Msk = 0x1000000
	// Bit B88.
	GTZC_VCTR2_B88 = 0x1000000
	// Position of B89 field.
	GTZC_VCTR2_B89_Pos = 0x19
	// Bit mask of B89 field.
	GTZC_VCTR2_B89_Msk = 0x2000000
	// Bit B89.
	GTZC_VCTR2_B89 = 0x2000000
	// Position of B90 field.
	GTZC_VCTR2_B90_Pos = 0x1a
	// Bit mask of B90 field.
	GTZC_VCTR2_B90_Msk = 0x4000000
	// Bit B90.
	GTZC_VCTR2_B90 = 0x4000000
	// Position of B91 field.
	GTZC_VCTR2_B91_Pos = 0x1b
	// Bit mask of B91 field.
	GTZC_VCTR2_B91_Msk = 0x8000000
	// Bit B91.
	GTZC_VCTR2_B91 = 0x8000000
	// Position of B92 field.
	GTZC_VCTR2_B92_Pos = 0x1c
	// Bit mask of B92 field.
	GTZC_VCTR2_B92_Msk = 0x10000000
	// Bit B92.
	GTZC_VCTR2_B92 = 0x10000000
	// Position of B93 field.
	GTZC_VCTR2_B93_Pos = 0x1d
	// Bit mask of B93 field.
	GTZC_VCTR2_B93_Msk = 0x20000000
	// Bit B93.
	GTZC_VCTR2_B93 = 0x20000000
	// Position of B94 field.
	GTZC_VCTR2_B94_Pos = 0x1e
	// Bit mask of B94 field.
	GTZC_VCTR2_B94_Msk = 0x40000000
	// Bit B94.
	GTZC_VCTR2_B94 = 0x40000000
	// Position of B95 field.
	GTZC_VCTR2_B95_Pos = 0x1f
	// Bit mask of B95 field.
	GTZC_VCTR2_B95_Msk = 0x80000000
	// Bit B95.
	GTZC_VCTR2_B95 = 0x80000000

	// VCTR3: MPCBBx vector register
	// Position of B96 field.
	GTZC_VCTR3_B96_Pos = 0x0
	// Bit mask of B96 field.
	GTZC_VCTR3_B96_Msk = 0x1
	// Bit B96.
	GTZC_VCTR3_B96 = 0x1
	// Position of B97 field.
	GTZC_VCTR3_B97_Pos = 0x1
	// Bit mask of B97 field.
	GTZC_VCTR3_B97_Msk = 0x2
	// Bit B97.
	GTZC_VCTR3_B97 = 0x2
	// Position of B98 field.
	GTZC_VCTR3_B98_Pos = 0x2
	// Bit mask of B98 field.
	GTZC_VCTR3_B98_Msk = 0x4
	// Bit B98.
	GTZC_VCTR3_B98 = 0x4
	// Position of B99 field.
	GTZC_VCTR3_B99_Pos = 0x3
	// Bit mask of B99 field.
	GTZC_VCTR3_B99_Msk = 0x8
	// Bit B99.
	GTZC_VCTR3_B99 = 0x8
	// Position of B100 field.
	GTZC_VCTR3_B100_Pos = 0x4
	// Bit mask of B100 field.
	GTZC_VCTR3_B100_Msk = 0x10
	// Bit B100.
	GTZC_VCTR3_B100 = 0x10
	// Position of B101 field.
	GTZC_VCTR3_B101_Pos = 0x5
	// Bit mask of B101 field.
	GTZC_VCTR3_B101_Msk = 0x20
	// Bit B101.
	GTZC_VCTR3_B101 = 0x20
	// Position of B102 field.
	GTZC_VCTR3_B102_Pos = 0x6
	// Bit mask of B102 field.
	GTZC_VCTR3_B102_Msk = 0x40
	// Bit B102.
	GTZC_VCTR3_B102 = 0x40
	// Position of B103 field.
	GTZC_VCTR3_B103_Pos = 0x7
	// Bit mask of B103 field.
	GTZC_VCTR3_B103_Msk = 0x80
	// Bit B103.
	GTZC_VCTR3_B103 = 0x80
	// Position of B104 field.
	GTZC_VCTR3_B104_Pos = 0x8
	// Bit mask of B104 field.
	GTZC_VCTR3_B104_Msk = 0x100
	// Bit B104.
	GTZC_VCTR3_B104 = 0x100
	// Position of B105 field.
	GTZC_VCTR3_B105_Pos = 0x9
	// Bit mask of B105 field.
	GTZC_VCTR3_B105_Msk = 0x200
	// Bit B105.
	GTZC_VCTR3_B105 = 0x200
	// Position of B106 field.
	GTZC_VCTR3_B106_Pos = 0xa
	// Bit mask of B106 field.
	GTZC_VCTR3_B106_Msk = 0x400
	// Bit B106.
	GTZC_VCTR3_B106 = 0x400
	// Position of B107 field.
	GTZC_VCTR3_B107_Pos = 0xb
	// Bit mask of B107 field.
	GTZC_VCTR3_B107_Msk = 0x800
	// Bit B107.
	GTZC_VCTR3_B107 = 0x800
	// Position of B108 field.
	GTZC_VCTR3_B108_Pos = 0xc
	// Bit mask of B108 field.
	GTZC_VCTR3_B108_Msk = 0x1000
	// Bit B108.
	GTZC_VCTR3_B108 = 0x1000
	// Position of B109 field.
	GTZC_VCTR3_B109_Pos = 0xd
	// Bit mask of B109 field.
	GTZC_VCTR3_B109_Msk = 0x2000
	// Bit B109.
	GTZC_VCTR3_B109 = 0x2000
	// Position of B110 field.
	GTZC_VCTR3_B110_Pos = 0xe
	// Bit mask of B110 field.
	GTZC_VCTR3_B110_Msk = 0x4000
	// Bit B110.
	GTZC_VCTR3_B110 = 0x4000
	// Position of B111 field.
	GTZC_VCTR3_B111_Pos = 0xf
	// Bit mask of B111 field.
	GTZC_VCTR3_B111_Msk = 0x8000
	// Bit B111.
	GTZC_VCTR3_B111 = 0x8000
	// Position of B112 field.
	GTZC_VCTR3_B112_Pos = 0x10
	// Bit mask of B112 field.
	GTZC_VCTR3_B112_Msk = 0x10000
	// Bit B112.
	GTZC_VCTR3_B112 = 0x10000
	// Position of B113 field.
	GTZC_VCTR3_B113_Pos = 0x11
	// Bit mask of B113 field.
	GTZC_VCTR3_B113_Msk = 0x20000
	// Bit B113.
	GTZC_VCTR3_B113 = 0x20000
	// Position of B114 field.
	GTZC_VCTR3_B114_Pos = 0x12
	// Bit mask of B114 field.
	GTZC_VCTR3_B114_Msk = 0x40000
	// Bit B114.
	GTZC_VCTR3_B114 = 0x40000
	// Position of B115 field.
	GTZC_VCTR3_B115_Pos = 0x13
	// Bit mask of B115 field.
	GTZC_VCTR3_B115_Msk = 0x80000
	// Bit B115.
	GTZC_VCTR3_B115 = 0x80000
	// Position of B116 field.
	GTZC_VCTR3_B116_Pos = 0x14
	// Bit mask of B116 field.
	GTZC_VCTR3_B116_Msk = 0x100000
	// Bit B116.
	GTZC_VCTR3_B116 = 0x100000
	// Position of B117 field.
	GTZC_VCTR3_B117_Pos = 0x15
	// Bit mask of B117 field.
	GTZC_VCTR3_B117_Msk = 0x200000
	// Bit B117.
	GTZC_VCTR3_B117 = 0x200000
	// Position of B118 field.
	GTZC_VCTR3_B118_Pos = 0x16
	// Bit mask of B118 field.
	GTZC_VCTR3_B118_Msk = 0x400000
	// Bit B118.
	GTZC_VCTR3_B118 = 0x400000
	// Position of B119 field.
	GTZC_VCTR3_B119_Pos = 0x17
	// Bit mask of B119 field.
	GTZC_VCTR3_B119_Msk = 0x800000
	// Bit B119.
	GTZC_VCTR3_B119 = 0x800000
	// Position of B120 field.
	GTZC_VCTR3_B120_Pos = 0x18
	// Bit mask of B120 field.
	GTZC_VCTR3_B120_Msk = 0x1000000
	// Bit B120.
	GTZC_VCTR3_B120 = 0x1000000
	// Position of B121 field.
	GTZC_VCTR3_B121_Pos = 0x19
	// Bit mask of B121 field.
	GTZC_VCTR3_B121_Msk = 0x2000000
	// Bit B121.
	GTZC_VCTR3_B121 = 0x2000000
	// Position of B122 field.
	GTZC_VCTR3_B122_Pos = 0x1a
	// Bit mask of B122 field.
	GTZC_VCTR3_B122_Msk = 0x4000000
	// Bit B122.
	GTZC_VCTR3_B122 = 0x4000000
	// Position of B123 field.
	GTZC_VCTR3_B123_Pos = 0x1b
	// Bit mask of B123 field.
	GTZC_VCTR3_B123_Msk = 0x8000000
	// Bit B123.
	GTZC_VCTR3_B123 = 0x8000000
	// Position of B124 field.
	GTZC_VCTR3_B124_Pos = 0x1c
	// Bit mask of B124 field.
	GTZC_VCTR3_B124_Msk = 0x10000000
	// Bit B124.
	GTZC_VCTR3_B124 = 0x10000000
	// Position of B125 field.
	GTZC_VCTR3_B125_Pos = 0x1d
	// Bit mask of B125 field.
	GTZC_VCTR3_B125_Msk = 0x20000000
	// Bit B125.
	GTZC_VCTR3_B125 = 0x20000000
	// Position of B126 field.
	GTZC_VCTR3_B126_Pos = 0x1e
	// Bit mask of B126 field.
	GTZC_VCTR3_B126_Msk = 0x40000000
	// Bit B126.
	GTZC_VCTR3_B126 = 0x40000000
	// Position of B127 field.
	GTZC_VCTR3_B127_Pos = 0x1f
	// Bit mask of B127 field.
	GTZC_VCTR3_B127_Msk = 0x80000000
	// Bit B127.
	GTZC_VCTR3_B127 = 0x80000000

	// VCTR4: MPCBBx vector register
	// Position of B128 field.
	GTZC_VCTR4_B128_Pos = 0x0
	// Bit mask of B128 field.
	GTZC_VCTR4_B128_Msk = 0x1
	// Bit B128.
	GTZC_VCTR4_B128 = 0x1
	// Position of B129 field.
	GTZC_VCTR4_B129_Pos = 0x1
	// Bit mask of B129 field.
	GTZC_VCTR4_B129_Msk = 0x2
	// Bit B129.
	GTZC_VCTR4_B129 = 0x2
	// Position of B130 field.
	GTZC_VCTR4_B130_Pos = 0x2
	// Bit mask of B130 field.
	GTZC_VCTR4_B130_Msk = 0x4
	// Bit B130.
	GTZC_VCTR4_B130 = 0x4
	// Position of B131 field.
	GTZC_VCTR4_B131_Pos = 0x3
	// Bit mask of B131 field.
	GTZC_VCTR4_B131_Msk = 0x8
	// Bit B131.
	GTZC_VCTR4_B131 = 0x8
	// Position of B132 field.
	GTZC_VCTR4_B132_Pos = 0x4
	// Bit mask of B132 field.
	GTZC_VCTR4_B132_Msk = 0x10
	// Bit B132.
	GTZC_VCTR4_B132 = 0x10
	// Position of B133 field.
	GTZC_VCTR4_B133_Pos = 0x5
	// Bit mask of B133 field.
	GTZC_VCTR4_B133_Msk = 0x20
	// Bit B133.
	GTZC_VCTR4_B133 = 0x20
	// Position of B134 field.
	GTZC_VCTR4_B134_Pos = 0x6
	// Bit mask of B134 field.
	GTZC_VCTR4_B134_Msk = 0x40
	// Bit B134.
	GTZC_VCTR4_B134 = 0x40
	// Position of B135 field.
	GTZC_VCTR4_B135_Pos = 0x7
	// Bit mask of B135 field.
	GTZC_VCTR4_B135_Msk = 0x80
	// Bit B135.
	GTZC_VCTR4_B135 = 0x80
	// Position of B136 field.
	GTZC_VCTR4_B136_Pos = 0x8
	// Bit mask of B136 field.
	GTZC_VCTR4_B136_Msk = 0x100
	// Bit B136.
	GTZC_VCTR4_B136 = 0x100
	// Position of B137 field.
	GTZC_VCTR4_B137_Pos = 0x9
	// Bit mask of B137 field.
	GTZC_VCTR4_B137_Msk = 0x200
	// Bit B137.
	GTZC_VCTR4_B137 = 0x200
	// Position of B138 field.
	GTZC_VCTR4_B138_Pos = 0xa
	// Bit mask of B138 field.
	GTZC_VCTR4_B138_Msk = 0x400
	// Bit B138.
	GTZC_VCTR4_B138 = 0x400
	// Position of B139 field.
	GTZC_VCTR4_B139_Pos = 0xb
	// Bit mask of B139 field.
	GTZC_VCTR4_B139_Msk = 0x800
	// Bit B139.
	GTZC_VCTR4_B139 = 0x800
	// Position of B140 field.
	GTZC_VCTR4_B140_Pos = 0xc
	// Bit mask of B140 field.
	GTZC_VCTR4_B140_Msk = 0x1000
	// Bit B140.
	GTZC_VCTR4_B140 = 0x1000
	// Position of B141 field.
	GTZC_VCTR4_B141_Pos = 0xd
	// Bit mask of B141 field.
	GTZC_VCTR4_B141_Msk = 0x2000
	// Bit B141.
	GTZC_VCTR4_B141 = 0x2000
	// Position of B142 field.
	GTZC_VCTR4_B142_Pos = 0xe
	// Bit mask of B142 field.
	GTZC_VCTR4_B142_Msk = 0x4000
	// Bit B142.
	GTZC_VCTR4_B142 = 0x4000
	// Position of B143 field.
	GTZC_VCTR4_B143_Pos = 0xf
	// Bit mask of B143 field.
	GTZC_VCTR4_B143_Msk = 0x8000
	// Bit B143.
	GTZC_VCTR4_B143 = 0x8000
	// Position of B144 field.
	GTZC_VCTR4_B144_Pos = 0x10
	// Bit mask of B144 field.
	GTZC_VCTR4_B144_Msk = 0x10000
	// Bit B144.
	GTZC_VCTR4_B144 = 0x10000
	// Position of B145 field.
	GTZC_VCTR4_B145_Pos = 0x11
	// Bit mask of B145 field.
	GTZC_VCTR4_B145_Msk = 0x20000
	// Bit B145.
	GTZC_VCTR4_B145 = 0x20000
	// Position of B146 field.
	GTZC_VCTR4_B146_Pos = 0x12
	// Bit mask of B146 field.
	GTZC_VCTR4_B146_Msk = 0x40000
	// Bit B146.
	GTZC_VCTR4_B146 = 0x40000
	// Position of B147 field.
	GTZC_VCTR4_B147_Pos = 0x13
	// Bit mask of B147 field.
	GTZC_VCTR4_B147_Msk = 0x80000
	// Bit B147.
	GTZC_VCTR4_B147 = 0x80000
	// Position of B148 field.
	GTZC_VCTR4_B148_Pos = 0x14
	// Bit mask of B148 field.
	GTZC_VCTR4_B148_Msk = 0x100000
	// Bit B148.
	GTZC_VCTR4_B148 = 0x100000
	// Position of B149 field.
	GTZC_VCTR4_B149_Pos = 0x15
	// Bit mask of B149 field.
	GTZC_VCTR4_B149_Msk = 0x200000
	// Bit B149.
	GTZC_VCTR4_B149 = 0x200000
	// Position of B150 field.
	GTZC_VCTR4_B150_Pos = 0x16
	// Bit mask of B150 field.
	GTZC_VCTR4_B150_Msk = 0x400000
	// Bit B150.
	GTZC_VCTR4_B150 = 0x400000
	// Position of B151 field.
	GTZC_VCTR4_B151_Pos = 0x17
	// Bit mask of B151 field.
	GTZC_VCTR4_B151_Msk = 0x800000
	// Bit B151.
	GTZC_VCTR4_B151 = 0x800000
	// Position of B152 field.
	GTZC_VCTR4_B152_Pos = 0x18
	// Bit mask of B152 field.
	GTZC_VCTR4_B152_Msk = 0x1000000
	// Bit B152.
	GTZC_VCTR4_B152 = 0x1000000
	// Position of B153 field.
	GTZC_VCTR4_B153_Pos = 0x19
	// Bit mask of B153 field.
	GTZC_VCTR4_B153_Msk = 0x2000000
	// Bit B153.
	GTZC_VCTR4_B153 = 0x2000000
	// Position of B154 field.
	GTZC_VCTR4_B154_Pos = 0x1a
	// Bit mask of B154 field.
	GTZC_VCTR4_B154_Msk = 0x4000000
	// Bit B154.
	GTZC_VCTR4_B154 = 0x4000000
	// Position of B155 field.
	GTZC_VCTR4_B155_Pos = 0x1b
	// Bit mask of B155 field.
	GTZC_VCTR4_B155_Msk = 0x8000000
	// Bit B155.
	GTZC_VCTR4_B155 = 0x8000000
	// Position of B156 field.
	GTZC_VCTR4_B156_Pos = 0x1c
	// Bit mask of B156 field.
	GTZC_VCTR4_B156_Msk = 0x10000000
	// Bit B156.
	GTZC_VCTR4_B156 = 0x10000000
	// Position of B157 field.
	GTZC_VCTR4_B157_Pos = 0x1d
	// Bit mask of B157 field.
	GTZC_VCTR4_B157_Msk = 0x20000000
	// Bit B157.
	GTZC_VCTR4_B157 = 0x20000000
	// Position of B158 field.
	GTZC_VCTR4_B158_Pos = 0x1e
	// Bit mask of B158 field.
	GTZC_VCTR4_B158_Msk = 0x40000000
	// Bit B158.
	GTZC_VCTR4_B158 = 0x40000000
	// Position of B159 field.
	GTZC_VCTR4_B159_Pos = 0x1f
	// Bit mask of B159 field.
	GTZC_VCTR4_B159_Msk = 0x80000000
	// Bit B159.
	GTZC_VCTR4_B159 = 0x80000000

	// VCTR5: MPCBBx vector register
	// Position of B160 field.
	GTZC_VCTR5_B160_Pos = 0x0
	// Bit mask of B160 field.
	GTZC_VCTR5_B160_Msk = 0x1
	// Bit B160.
	GTZC_VCTR5_B160 = 0x1
	// Position of B161 field.
	GTZC_VCTR5_B161_Pos = 0x1
	// Bit mask of B161 field.
	GTZC_VCTR5_B161_Msk = 0x2
	// Bit B161.
	GTZC_VCTR5_B161 = 0x2
	// Position of B162 field.
	GTZC_VCTR5_B162_Pos = 0x2
	// Bit mask of B162 field.
	GTZC_VCTR5_B162_Msk = 0x4
	// Bit B162.
	GTZC_VCTR5_B162 = 0x4
	// Position of B163 field.
	GTZC_VCTR5_B163_Pos = 0x3
	// Bit mask of B163 field.
	GTZC_VCTR5_B163_Msk = 0x8
	// Bit B163.
	GTZC_VCTR5_B163 = 0x8
	// Position of B164 field.
	GTZC_VCTR5_B164_Pos = 0x4
	// Bit mask of B164 field.
	GTZC_VCTR5_B164_Msk = 0x10
	// Bit B164.
	GTZC_VCTR5_B164 = 0x10
	// Position of B165 field.
	GTZC_VCTR5_B165_Pos = 0x5
	// Bit mask of B165 field.
	GTZC_VCTR5_B165_Msk = 0x20
	// Bit B165.
	GTZC_VCTR5_B165 = 0x20
	// Position of B166 field.
	GTZC_VCTR5_B166_Pos = 0x6
	// Bit mask of B166 field.
	GTZC_VCTR5_B166_Msk = 0x40
	// Bit B166.
	GTZC_VCTR5_B166 = 0x40
	// Position of B167 field.
	GTZC_VCTR5_B167_Pos = 0x7
	// Bit mask of B167 field.
	GTZC_VCTR5_B167_Msk = 0x80
	// Bit B167.
	GTZC_VCTR5_B167 = 0x80
	// Position of B168 field.
	GTZC_VCTR5_B168_Pos = 0x8
	// Bit mask of B168 field.
	GTZC_VCTR5_B168_Msk = 0x100
	// Bit B168.
	GTZC_VCTR5_B168 = 0x100
	// Position of B169 field.
	GTZC_VCTR5_B169_Pos = 0x9
	// Bit mask of B169 field.
	GTZC_VCTR5_B169_Msk = 0x200
	// Bit B169.
	GTZC_VCTR5_B169 = 0x200
	// Position of B170 field.
	GTZC_VCTR5_B170_Pos = 0xa
	// Bit mask of B170 field.
	GTZC_VCTR5_B170_Msk = 0x400
	// Bit B170.
	GTZC_VCTR5_B170 = 0x400
	// Position of B171 field.
	GTZC_VCTR5_B171_Pos = 0xb
	// Bit mask of B171 field.
	GTZC_VCTR5_B171_Msk = 0x800
	// Bit B171.
	GTZC_VCTR5_B171 = 0x800
	// Position of B172 field.
	GTZC_VCTR5_B172_Pos = 0xc
	// Bit mask of B172 field.
	GTZC_VCTR5_B172_Msk = 0x1000
	// Bit B172.
	GTZC_VCTR5_B172 = 0x1000
	// Position of B173 field.
	GTZC_VCTR5_B173_Pos = 0xd
	// Bit mask of B173 field.
	GTZC_VCTR5_B173_Msk = 0x2000
	// Bit B173.
	GTZC_VCTR5_B173 = 0x2000
	// Position of B174 field.
	GTZC_VCTR5_B174_Pos = 0xe
	// Bit mask of B174 field.
	GTZC_VCTR5_B174_Msk = 0x4000
	// Bit B174.
	GTZC_VCTR5_B174 = 0x4000
	// Position of B175 field.
	GTZC_VCTR5_B175_Pos = 0xf
	// Bit mask of B175 field.
	GTZC_VCTR5_B175_Msk = 0x8000
	// Bit B175.
	GTZC_VCTR5_B175 = 0x8000
	// Position of B176 field.
	GTZC_VCTR5_B176_Pos = 0x10
	// Bit mask of B176 field.
	GTZC_VCTR5_B176_Msk = 0x10000
	// Bit B176.
	GTZC_VCTR5_B176 = 0x10000
	// Position of B177 field.
	GTZC_VCTR5_B177_Pos = 0x11
	// Bit mask of B177 field.
	GTZC_VCTR5_B177_Msk = 0x20000
	// Bit B177.
	GTZC_VCTR5_B177 = 0x20000
	// Position of B178 field.
	GTZC_VCTR5_B178_Pos = 0x12
	// Bit mask of B178 field.
	GTZC_VCTR5_B178_Msk = 0x40000
	// Bit B178.
	GTZC_VCTR5_B178 = 0x40000
	// Position of B179 field.
	GTZC_VCTR5_B179_Pos = 0x13
	// Bit mask of B179 field.
	GTZC_VCTR5_B179_Msk = 0x80000
	// Bit B179.
	GTZC_VCTR5_B179 = 0x80000
	// Position of B180 field.
	GTZC_VCTR5_B180_Pos = 0x14
	// Bit mask of B180 field.
	GTZC_VCTR5_B180_Msk = 0x100000
	// Bit B180.
	GTZC_VCTR5_B180 = 0x100000
	// Position of B181 field.
	GTZC_VCTR5_B181_Pos = 0x15
	// Bit mask of B181 field.
	GTZC_VCTR5_B181_Msk = 0x200000
	// Bit B181.
	GTZC_VCTR5_B181 = 0x200000
	// Position of B182 field.
	GTZC_VCTR5_B182_Pos = 0x16
	// Bit mask of B182 field.
	GTZC_VCTR5_B182_Msk = 0x400000
	// Bit B182.
	GTZC_VCTR5_B182 = 0x400000
	// Position of B183 field.
	GTZC_VCTR5_B183_Pos = 0x17
	// Bit mask of B183 field.
	GTZC_VCTR5_B183_Msk = 0x800000
	// Bit B183.
	GTZC_VCTR5_B183 = 0x800000
	// Position of B184 field.
	GTZC_VCTR5_B184_Pos = 0x18
	// Bit mask of B184 field.
	GTZC_VCTR5_B184_Msk = 0x1000000
	// Bit B184.
	GTZC_VCTR5_B184 = 0x1000000
	// Position of B185 field.
	GTZC_VCTR5_B185_Pos = 0x19
	// Bit mask of B185 field.
	GTZC_VCTR5_B185_Msk = 0x2000000
	// Bit B185.
	GTZC_VCTR5_B185 = 0x2000000
	// Position of B186 field.
	GTZC_VCTR5_B186_Pos = 0x1a
	// Bit mask of B186 field.
	GTZC_VCTR5_B186_Msk = 0x4000000
	// Bit B186.
	GTZC_VCTR5_B186 = 0x4000000
	// Position of B187 field.
	GTZC_VCTR5_B187_Pos = 0x1b
	// Bit mask of B187 field.
	GTZC_VCTR5_B187_Msk = 0x8000000
	// Bit B187.
	GTZC_VCTR5_B187 = 0x8000000
	// Position of B188 field.
	GTZC_VCTR5_B188_Pos = 0x1c
	// Bit mask of B188 field.
	GTZC_VCTR5_B188_Msk = 0x10000000
	// Bit B188.
	GTZC_VCTR5_B188 = 0x10000000
	// Position of B189 field.
	GTZC_VCTR5_B189_Pos = 0x1d
	// Bit mask of B189 field.
	GTZC_VCTR5_B189_Msk = 0x20000000
	// Bit B189.
	GTZC_VCTR5_B189 = 0x20000000
	// Position of B190 field.
	GTZC_VCTR5_B190_Pos = 0x1e
	// Bit mask of B190 field.
	GTZC_VCTR5_B190_Msk = 0x40000000
	// Bit B190.
	GTZC_VCTR5_B190 = 0x40000000
	// Position of B191 field.
	GTZC_VCTR5_B191_Pos = 0x1f
	// Bit mask of B191 field.
	GTZC_VCTR5_B191_Msk = 0x80000000
	// Bit B191.
	GTZC_VCTR5_B191 = 0x80000000

	// VCTR6: MPCBBx vector register
	// Position of B192 field.
	GTZC_VCTR6_B192_Pos = 0x0
	// Bit mask of B192 field.
	GTZC_VCTR6_B192_Msk = 0x1
	// Bit B192.
	GTZC_VCTR6_B192 = 0x1
	// Position of B193 field.
	GTZC_VCTR6_B193_Pos = 0x1
	// Bit mask of B193 field.
	GTZC_VCTR6_B193_Msk = 0x2
	// Bit B193.
	GTZC_VCTR6_B193 = 0x2
	// Position of B194 field.
	GTZC_VCTR6_B194_Pos = 0x2
	// Bit mask of B194 field.
	GTZC_VCTR6_B194_Msk = 0x4
	// Bit B194.
	GTZC_VCTR6_B194 = 0x4
	// Position of B195 field.
	GTZC_VCTR6_B195_Pos = 0x3
	// Bit mask of B195 field.
	GTZC_VCTR6_B195_Msk = 0x8
	// Bit B195.
	GTZC_VCTR6_B195 = 0x8
	// Position of B196 field.
	GTZC_VCTR6_B196_Pos = 0x4
	// Bit mask of B196 field.
	GTZC_VCTR6_B196_Msk = 0x10
	// Bit B196.
	GTZC_VCTR6_B196 = 0x10
	// Position of B197 field.
	GTZC_VCTR6_B197_Pos = 0x5
	// Bit mask of B197 field.
	GTZC_VCTR6_B197_Msk = 0x20
	// Bit B197.
	GTZC_VCTR6_B197 = 0x20
	// Position of B198 field.
	GTZC_VCTR6_B198_Pos = 0x6
	// Bit mask of B198 field.
	GTZC_VCTR6_B198_Msk = 0x40
	// Bit B198.
	GTZC_VCTR6_B198 = 0x40
	// Position of B199 field.
	GTZC_VCTR6_B199_Pos = 0x7
	// Bit mask of B199 field.
	GTZC_VCTR6_B199_Msk = 0x80
	// Bit B199.
	GTZC_VCTR6_B199 = 0x80
	// Position of B200 field.
	GTZC_VCTR6_B200_Pos = 0x8
	// Bit mask of B200 field.
	GTZC_VCTR6_B200_Msk = 0x100
	// Bit B200.
	GTZC_VCTR6_B200 = 0x100
	// Position of B201 field.
	GTZC_VCTR6_B201_Pos = 0x9
	// Bit mask of B201 field.
	GTZC_VCTR6_B201_Msk = 0x200
	// Bit B201.
	GTZC_VCTR6_B201 = 0x200
	// Position of B202 field.
	GTZC_VCTR6_B202_Pos = 0xa
	// Bit mask of B202 field.
	GTZC_VCTR6_B202_Msk = 0x400
	// Bit B202.
	GTZC_VCTR6_B202 = 0x400
	// Position of B203 field.
	GTZC_VCTR6_B203_Pos = 0xb
	// Bit mask of B203 field.
	GTZC_VCTR6_B203_Msk = 0x800
	// Bit B203.
	GTZC_VCTR6_B203 = 0x800
	// Position of B204 field.
	GTZC_VCTR6_B204_Pos = 0xc
	// Bit mask of B204 field.
	GTZC_VCTR6_B204_Msk = 0x1000
	// Bit B204.
	GTZC_VCTR6_B204 = 0x1000
	// Position of B205 field.
	GTZC_VCTR6_B205_Pos = 0xd
	// Bit mask of B205 field.
	GTZC_VCTR6_B205_Msk = 0x2000
	// Bit B205.
	GTZC_VCTR6_B205 = 0x2000
	// Position of B206 field.
	GTZC_VCTR6_B206_Pos = 0xe
	// Bit mask of B206 field.
	GTZC_VCTR6_B206_Msk = 0x4000
	// Bit B206.
	GTZC_VCTR6_B206 = 0x4000
	// Position of B207 field.
	GTZC_VCTR6_B207_Pos = 0xf
	// Bit mask of B207 field.
	GTZC_VCTR6_B207_Msk = 0x8000
	// Bit B207.
	GTZC_VCTR6_B207 = 0x8000
	// Position of B208 field.
	GTZC_VCTR6_B208_Pos = 0x10
	// Bit mask of B208 field.
	GTZC_VCTR6_B208_Msk = 0x10000
	// Bit B208.
	GTZC_VCTR6_B208 = 0x10000
	// Position of B209 field.
	GTZC_VCTR6_B209_Pos = 0x11
	// Bit mask of B209 field.
	GTZC_VCTR6_B209_Msk = 0x20000
	// Bit B209.
	GTZC_VCTR6_B209 = 0x20000
	// Position of B210 field.
	GTZC_VCTR6_B210_Pos = 0x12
	// Bit mask of B210 field.
	GTZC_VCTR6_B210_Msk = 0x40000
	// Bit B210.
	GTZC_VCTR6_B210 = 0x40000
	// Position of B211 field.
	GTZC_VCTR6_B211_Pos = 0x13
	// Bit mask of B211 field.
	GTZC_VCTR6_B211_Msk = 0x80000
	// Bit B211.
	GTZC_VCTR6_B211 = 0x80000
	// Position of B212 field.
	GTZC_VCTR6_B212_Pos = 0x14
	// Bit mask of B212 field.
	GTZC_VCTR6_B212_Msk = 0x100000
	// Bit B212.
	GTZC_VCTR6_B212 = 0x100000
	// Position of B213 field.
	GTZC_VCTR6_B213_Pos = 0x15
	// Bit mask of B213 field.
	GTZC_VCTR6_B213_Msk = 0x200000
	// Bit B213.
	GTZC_VCTR6_B213 = 0x200000
	// Position of B214 field.
	GTZC_VCTR6_B214_Pos = 0x16
	// Bit mask of B214 field.
	GTZC_VCTR6_B214_Msk = 0x400000
	// Bit B214.
	GTZC_VCTR6_B214 = 0x400000
	// Position of B215 field.
	GTZC_VCTR6_B215_Pos = 0x17
	// Bit mask of B215 field.
	GTZC_VCTR6_B215_Msk = 0x800000
	// Bit B215.
	GTZC_VCTR6_B215 = 0x800000
	// Position of B216 field.
	GTZC_VCTR6_B216_Pos = 0x18
	// Bit mask of B216 field.
	GTZC_VCTR6_B216_Msk = 0x1000000
	// Bit B216.
	GTZC_VCTR6_B216 = 0x1000000
	// Position of B217 field.
	GTZC_VCTR6_B217_Pos = 0x19
	// Bit mask of B217 field.
	GTZC_VCTR6_B217_Msk = 0x2000000
	// Bit B217.
	GTZC_VCTR6_B217 = 0x2000000
	// Position of B218 field.
	GTZC_VCTR6_B218_Pos = 0x1a
	// Bit mask of B218 field.
	GTZC_VCTR6_B218_Msk = 0x4000000
	// Bit B218.
	GTZC_VCTR6_B218 = 0x4000000
	// Position of B219 field.
	GTZC_VCTR6_B219_Pos = 0x1b
	// Bit mask of B219 field.
	GTZC_VCTR6_B219_Msk = 0x8000000
	// Bit B219.
	GTZC_VCTR6_B219 = 0x8000000
	// Position of B220 field.
	GTZC_VCTR6_B220_Pos = 0x1c
	// Bit mask of B220 field.
	GTZC_VCTR6_B220_Msk = 0x10000000
	// Bit B220.
	GTZC_VCTR6_B220 = 0x10000000
	// Position of B221 field.
	GTZC_VCTR6_B221_Pos = 0x1d
	// Bit mask of B221 field.
	GTZC_VCTR6_B221_Msk = 0x20000000
	// Bit B221.
	GTZC_VCTR6_B221 = 0x20000000
	// Position of B222 field.
	GTZC_VCTR6_B222_Pos = 0x1e
	// Bit mask of B222 field.
	GTZC_VCTR6_B222_Msk = 0x40000000
	// Bit B222.
	GTZC_VCTR6_B222 = 0x40000000
	// Position of B223 field.
	GTZC_VCTR6_B223_Pos = 0x1f
	// Bit mask of B223 field.
	GTZC_VCTR6_B223_Msk = 0x80000000
	// Bit B223.
	GTZC_VCTR6_B223 = 0x80000000

	// VCTR7: MPCBBx vector register
	// Position of B224 field.
	GTZC_VCTR7_B224_Pos = 0x0
	// Bit mask of B224 field.
	GTZC_VCTR7_B224_Msk = 0x1
	// Bit B224.
	GTZC_VCTR7_B224 = 0x1
	// Position of B225 field.
	GTZC_VCTR7_B225_Pos = 0x1
	// Bit mask of B225 field.
	GTZC_VCTR7_B225_Msk = 0x2
	// Bit B225.
	GTZC_VCTR7_B225 = 0x2
	// Position of B226 field.
	GTZC_VCTR7_B226_Pos = 0x2
	// Bit mask of B226 field.
	GTZC_VCTR7_B226_Msk = 0x4
	// Bit B226.
	GTZC_VCTR7_B226 = 0x4
	// Position of B227 field.
	GTZC_VCTR7_B227_Pos = 0x3
	// Bit mask of B227 field.
	GTZC_VCTR7_B227_Msk = 0x8
	// Bit B227.
	GTZC_VCTR7_B227 = 0x8
	// Position of B228 field.
	GTZC_VCTR7_B228_Pos = 0x4
	// Bit mask of B228 field.
	GTZC_VCTR7_B228_Msk = 0x10
	// Bit B228.
	GTZC_VCTR7_B228 = 0x10
	// Position of B229 field.
	GTZC_VCTR7_B229_Pos = 0x5
	// Bit mask of B229 field.
	GTZC_VCTR7_B229_Msk = 0x20
	// Bit B229.
	GTZC_VCTR7_B229 = 0x20
	// Position of B230 field.
	GTZC_VCTR7_B230_Pos = 0x6
	// Bit mask of B230 field.
	GTZC_VCTR7_B230_Msk = 0x40
	// Bit B230.
	GTZC_VCTR7_B230 = 0x40
	// Position of B231 field.
	GTZC_VCTR7_B231_Pos = 0x7
	// Bit mask of B231 field.
	GTZC_VCTR7_B231_Msk = 0x80
	// Bit B231.
	GTZC_VCTR7_B231 = 0x80
	// Position of B232 field.
	GTZC_VCTR7_B232_Pos = 0x8
	// Bit mask of B232 field.
	GTZC_VCTR7_B232_Msk = 0x100
	// Bit B232.
	GTZC_VCTR7_B232 = 0x100
	// Position of B233 field.
	GTZC_VCTR7_B233_Pos = 0x9
	// Bit mask of B233 field.
	GTZC_VCTR7_B233_Msk = 0x200
	// Bit B233.
	GTZC_VCTR7_B233 = 0x200
	// Position of B234 field.
	GTZC_VCTR7_B234_Pos = 0xa
	// Bit mask of B234 field.
	GTZC_VCTR7_B234_Msk = 0x400
	// Bit B234.
	GTZC_VCTR7_B234 = 0x400
	// Position of B235 field.
	GTZC_VCTR7_B235_Pos = 0xb
	// Bit mask of B235 field.
	GTZC_VCTR7_B235_Msk = 0x800
	// Bit B235.
	GTZC_VCTR7_B235 = 0x800
	// Position of B236 field.
	GTZC_VCTR7_B236_Pos = 0xc
	// Bit mask of B236 field.
	GTZC_VCTR7_B236_Msk = 0x1000
	// Bit B236.
	GTZC_VCTR7_B236 = 0x1000
	// Position of B237 field.
	GTZC_VCTR7_B237_Pos = 0xd
	// Bit mask of B237 field.
	GTZC_VCTR7_B237_Msk = 0x2000
	// Bit B237.
	GTZC_VCTR7_B237 = 0x2000
	// Position of B238 field.
	GTZC_VCTR7_B238_Pos = 0xe
	// Bit mask of B238 field.
	GTZC_VCTR7_B238_Msk = 0x4000
	// Bit B238.
	GTZC_VCTR7_B238 = 0x4000
	// Position of B239 field.
	GTZC_VCTR7_B239_Pos = 0xf
	// Bit mask of B239 field.
	GTZC_VCTR7_B239_Msk = 0x8000
	// Bit B239.
	GTZC_VCTR7_B239 = 0x8000
	// Position of B240 field.
	GTZC_VCTR7_B240_Pos = 0x10
	// Bit mask of B240 field.
	GTZC_VCTR7_B240_Msk = 0x10000
	// Bit B240.
	GTZC_VCTR7_B240 = 0x10000
	// Position of B241 field.
	GTZC_VCTR7_B241_Pos = 0x11
	// Bit mask of B241 field.
	GTZC_VCTR7_B241_Msk = 0x20000
	// Bit B241.
	GTZC_VCTR7_B241 = 0x20000
	// Position of B242 field.
	GTZC_VCTR7_B242_Pos = 0x12
	// Bit mask of B242 field.
	GTZC_VCTR7_B242_Msk = 0x40000
	// Bit B242.
	GTZC_VCTR7_B242 = 0x40000
	// Position of B243 field.
	GTZC_VCTR7_B243_Pos = 0x13
	// Bit mask of B243 field.
	GTZC_VCTR7_B243_Msk = 0x80000
	// Bit B243.
	GTZC_VCTR7_B243 = 0x80000
	// Position of B244 field.
	GTZC_VCTR7_B244_Pos = 0x14
	// Bit mask of B244 field.
	GTZC_VCTR7_B244_Msk = 0x100000
	// Bit B244.
	GTZC_VCTR7_B244 = 0x100000
	// Position of B245 field.
	GTZC_VCTR7_B245_Pos = 0x15
	// Bit mask of B245 field.
	GTZC_VCTR7_B245_Msk = 0x200000
	// Bit B245.
	GTZC_VCTR7_B245 = 0x200000
	// Position of B246 field.
	GTZC_VCTR7_B246_Pos = 0x16
	// Bit mask of B246 field.
	GTZC_VCTR7_B246_Msk = 0x400000
	// Bit B246.
	GTZC_VCTR7_B246 = 0x400000
	// Position of B247 field.
	GTZC_VCTR7_B247_Pos = 0x17
	// Bit mask of B247 field.
	GTZC_VCTR7_B247_Msk = 0x800000
	// Bit B247.
	GTZC_VCTR7_B247 = 0x800000
	// Position of B248 field.
	GTZC_VCTR7_B248_Pos = 0x18
	// Bit mask of B248 field.
	GTZC_VCTR7_B248_Msk = 0x1000000
	// Bit B248.
	GTZC_VCTR7_B248 = 0x1000000
	// Position of B249 field.
	GTZC_VCTR7_B249_Pos = 0x19
	// Bit mask of B249 field.
	GTZC_VCTR7_B249_Msk = 0x2000000
	// Bit B249.
	GTZC_VCTR7_B249 = 0x2000000
	// Position of B250 field.
	GTZC_VCTR7_B250_Pos = 0x1a
	// Bit mask of B250 field.
	GTZC_VCTR7_B250_Msk = 0x4000000
	// Bit B250.
	GTZC_VCTR7_B250 = 0x4000000
	// Position of B251 field.
	GTZC_VCTR7_B251_Pos = 0x1b
	// Bit mask of B251 field.
	GTZC_VCTR7_B251_Msk = 0x8000000
	// Bit B251.
	GTZC_VCTR7_B251 = 0x8000000
	// Position of B252 field.
	GTZC_VCTR7_B252_Pos = 0x1c
	// Bit mask of B252 field.
	GTZC_VCTR7_B252_Msk = 0x10000000
	// Bit B252.
	GTZC_VCTR7_B252 = 0x10000000
	// Position of B253 field.
	GTZC_VCTR7_B253_Pos = 0x1d
	// Bit mask of B253 field.
	GTZC_VCTR7_B253_Msk = 0x20000000
	// Bit B253.
	GTZC_VCTR7_B253 = 0x20000000
	// Position of B254 field.
	GTZC_VCTR7_B254_Pos = 0x1e
	// Bit mask of B254 field.
	GTZC_VCTR7_B254_Msk = 0x40000000
	// Bit B254.
	GTZC_VCTR7_B254 = 0x40000000
	// Position of B255 field.
	GTZC_VCTR7_B255_Pos = 0x1f
	// Bit mask of B255 field.
	GTZC_VCTR7_B255_Msk = 0x80000000
	// Bit B255.
	GTZC_VCTR7_B255 = 0x80000000

	// VCTR8: MPCBBx vector register
	// Position of B256 field.
	GTZC_VCTR8_B256_Pos = 0x0
	// Bit mask of B256 field.
	GTZC_VCTR8_B256_Msk = 0x1
	// Bit B256.
	GTZC_VCTR8_B256 = 0x1
	// Position of B257 field.
	GTZC_VCTR8_B257_Pos = 0x1
	// Bit mask of B257 field.
	GTZC_VCTR8_B257_Msk = 0x2
	// Bit B257.
	GTZC_VCTR8_B257 = 0x2
	// Position of B258 field.
	GTZC_VCTR8_B258_Pos = 0x2
	// Bit mask of B258 field.
	GTZC_VCTR8_B258_Msk = 0x4
	// Bit B258.
	GTZC_VCTR8_B258 = 0x4
	// Position of B259 field.
	GTZC_VCTR8_B259_Pos = 0x3
	// Bit mask of B259 field.
	GTZC_VCTR8_B259_Msk = 0x8
	// Bit B259.
	GTZC_VCTR8_B259 = 0x8
	// Position of B260 field.
	GTZC_VCTR8_B260_Pos = 0x4
	// Bit mask of B260 field.
	GTZC_VCTR8_B260_Msk = 0x10
	// Bit B260.
	GTZC_VCTR8_B260 = 0x10
	// Position of B261 field.
	GTZC_VCTR8_B261_Pos = 0x5
	// Bit mask of B261 field.
	GTZC_VCTR8_B261_Msk = 0x20
	// Bit B261.
	GTZC_VCTR8_B261 = 0x20
	// Position of B262 field.
	GTZC_VCTR8_B262_Pos = 0x6
	// Bit mask of B262 field.
	GTZC_VCTR8_B262_Msk = 0x40
	// Bit B262.
	GTZC_VCTR8_B262 = 0x40
	// Position of B263 field.
	GTZC_VCTR8_B263_Pos = 0x7
	// Bit mask of B263 field.
	GTZC_VCTR8_B263_Msk = 0x80
	// Bit B263.
	GTZC_VCTR8_B263 = 0x80
	// Position of B264 field.
	GTZC_VCTR8_B264_Pos = 0x8
	// Bit mask of B264 field.
	GTZC_VCTR8_B264_Msk = 0x100
	// Bit B264.
	GTZC_VCTR8_B264 = 0x100
	// Position of B265 field.
	GTZC_VCTR8_B265_Pos = 0x9
	// Bit mask of B265 field.
	GTZC_VCTR8_B265_Msk = 0x200
	// Bit B265.
	GTZC_VCTR8_B265 = 0x200
	// Position of B266 field.
	GTZC_VCTR8_B266_Pos = 0xa
	// Bit mask of B266 field.
	GTZC_VCTR8_B266_Msk = 0x400
	// Bit B266.
	GTZC_VCTR8_B266 = 0x400
	// Position of B267 field.
	GTZC_VCTR8_B267_Pos = 0xb
	// Bit mask of B267 field.
	GTZC_VCTR8_B267_Msk = 0x800
	// Bit B267.
	GTZC_VCTR8_B267 = 0x800
	// Position of B268 field.
	GTZC_VCTR8_B268_Pos = 0xc
	// Bit mask of B268 field.
	GTZC_VCTR8_B268_Msk = 0x1000
	// Bit B268.
	GTZC_VCTR8_B268 = 0x1000
	// Position of B269 field.
	GTZC_VCTR8_B269_Pos = 0xd
	// Bit mask of B269 field.
	GTZC_VCTR8_B269_Msk = 0x2000
	// Bit B269.
	GTZC_VCTR8_B269 = 0x2000
	// Position of B270 field.
	GTZC_VCTR8_B270_Pos = 0xe
	// Bit mask of B270 field.
	GTZC_VCTR8_B270_Msk = 0x4000
	// Bit B270.
	GTZC_VCTR8_B270 = 0x4000
	// Position of B271 field.
	GTZC_VCTR8_B271_Pos = 0xf
	// Bit mask of B271 field.
	GTZC_VCTR8_B271_Msk = 0x8000
	// Bit B271.
	GTZC_VCTR8_B271 = 0x8000
	// Position of B272 field.
	GTZC_VCTR8_B272_Pos = 0x10
	// Bit mask of B272 field.
	GTZC_VCTR8_B272_Msk = 0x10000
	// Bit B272.
	GTZC_VCTR8_B272 = 0x10000
	// Position of B273 field.
	GTZC_VCTR8_B273_Pos = 0x11
	// Bit mask of B273 field.
	GTZC_VCTR8_B273_Msk = 0x20000
	// Bit B273.
	GTZC_VCTR8_B273 = 0x20000
	// Position of B274 field.
	GTZC_VCTR8_B274_Pos = 0x12
	// Bit mask of B274 field.
	GTZC_VCTR8_B274_Msk = 0x40000
	// Bit B274.
	GTZC_VCTR8_B274 = 0x40000
	// Position of B275 field.
	GTZC_VCTR8_B275_Pos = 0x13
	// Bit mask of B275 field.
	GTZC_VCTR8_B275_Msk = 0x80000
	// Bit B275.
	GTZC_VCTR8_B275 = 0x80000
	// Position of B276 field.
	GTZC_VCTR8_B276_Pos = 0x14
	// Bit mask of B276 field.
	GTZC_VCTR8_B276_Msk = 0x100000
	// Bit B276.
	GTZC_VCTR8_B276 = 0x100000
	// Position of B277 field.
	GTZC_VCTR8_B277_Pos = 0x15
	// Bit mask of B277 field.
	GTZC_VCTR8_B277_Msk = 0x200000
	// Bit B277.
	GTZC_VCTR8_B277 = 0x200000
	// Position of B278 field.
	GTZC_VCTR8_B278_Pos = 0x16
	// Bit mask of B278 field.
	GTZC_VCTR8_B278_Msk = 0x400000
	// Bit B278.
	GTZC_VCTR8_B278 = 0x400000
	// Position of B279 field.
	GTZC_VCTR8_B279_Pos = 0x17
	// Bit mask of B279 field.
	GTZC_VCTR8_B279_Msk = 0x800000
	// Bit B279.
	GTZC_VCTR8_B279 = 0x800000
	// Position of B280 field.
	GTZC_VCTR8_B280_Pos = 0x18
	// Bit mask of B280 field.
	GTZC_VCTR8_B280_Msk = 0x1000000
	// Bit B280.
	GTZC_VCTR8_B280 = 0x1000000
	// Position of B281 field.
	GTZC_VCTR8_B281_Pos = 0x19
	// Bit mask of B281 field.
	GTZC_VCTR8_B281_Msk = 0x2000000
	// Bit B281.
	GTZC_VCTR8_B281 = 0x2000000
	// Position of B282 field.
	GTZC_VCTR8_B282_Pos = 0x1a
	// Bit mask of B282 field.
	GTZC_VCTR8_B282_Msk = 0x4000000
	// Bit B282.
	GTZC_VCTR8_B282 = 0x4000000
	// Position of B283 field.
	GTZC_VCTR8_B283_Pos = 0x1b
	// Bit mask of B283 field.
	GTZC_VCTR8_B283_Msk = 0x8000000
	// Bit B283.
	GTZC_VCTR8_B283 = 0x8000000
	// Position of B284 field.
	GTZC_VCTR8_B284_Pos = 0x1c
	// Bit mask of B284 field.
	GTZC_VCTR8_B284_Msk = 0x10000000
	// Bit B284.
	GTZC_VCTR8_B284 = 0x10000000
	// Position of B285 field.
	GTZC_VCTR8_B285_Pos = 0x1d
	// Bit mask of B285 field.
	GTZC_VCTR8_B285_Msk = 0x20000000
	// Bit B285.
	GTZC_VCTR8_B285 = 0x20000000
	// Position of B286 field.
	GTZC_VCTR8_B286_Pos = 0x1e
	// Bit mask of B286 field.
	GTZC_VCTR8_B286_Msk = 0x40000000
	// Bit B286.
	GTZC_VCTR8_B286 = 0x40000000
	// Position of B287 field.
	GTZC_VCTR8_B287_Pos = 0x1f
	// Bit mask of B287 field.
	GTZC_VCTR8_B287_Msk = 0x80000000
	// Bit B287.
	GTZC_VCTR8_B287 = 0x80000000

	// VCTR9: MPCBBx vector register
	// Position of B288 field.
	GTZC_VCTR9_B288_Pos = 0x0
	// Bit mask of B288 field.
	GTZC_VCTR9_B288_Msk = 0x1
	// Bit B288.
	GTZC_VCTR9_B288 = 0x1
	// Position of B289 field.
	GTZC_VCTR9_B289_Pos = 0x1
	// Bit mask of B289 field.
	GTZC_VCTR9_B289_Msk = 0x2
	// Bit B289.
	GTZC_VCTR9_B289 = 0x2
	// Position of B290 field.
	GTZC_VCTR9_B290_Pos = 0x2
	// Bit mask of B290 field.
	GTZC_VCTR9_B290_Msk = 0x4
	// Bit B290.
	GTZC_VCTR9_B290 = 0x4
	// Position of B291 field.
	GTZC_VCTR9_B291_Pos = 0x3
	// Bit mask of B291 field.
	GTZC_VCTR9_B291_Msk = 0x8
	// Bit B291.
	GTZC_VCTR9_B291 = 0x8
	// Position of B292 field.
	GTZC_VCTR9_B292_Pos = 0x4
	// Bit mask of B292 field.
	GTZC_VCTR9_B292_Msk = 0x10
	// Bit B292.
	GTZC_VCTR9_B292 = 0x10
	// Position of B293 field.
	GTZC_VCTR9_B293_Pos = 0x5
	// Bit mask of B293 field.
	GTZC_VCTR9_B293_Msk = 0x20
	// Bit B293.
	GTZC_VCTR9_B293 = 0x20
	// Position of B294 field.
	GTZC_VCTR9_B294_Pos = 0x6
	// Bit mask of B294 field.
	GTZC_VCTR9_B294_Msk = 0x40
	// Bit B294.
	GTZC_VCTR9_B294 = 0x40
	// Position of B295 field.
	GTZC_VCTR9_B295_Pos = 0x7
	// Bit mask of B295 field.
	GTZC_VCTR9_B295_Msk = 0x80
	// Bit B295.
	GTZC_VCTR9_B295 = 0x80
	// Position of B296 field.
	GTZC_VCTR9_B296_Pos = 0x8
	// Bit mask of B296 field.
	GTZC_VCTR9_B296_Msk = 0x100
	// Bit B296.
	GTZC_VCTR9_B296 = 0x100
	// Position of B297 field.
	GTZC_VCTR9_B297_Pos = 0x9
	// Bit mask of B297 field.
	GTZC_VCTR9_B297_Msk = 0x200
	// Bit B297.
	GTZC_VCTR9_B297 = 0x200
	// Position of B298 field.
	GTZC_VCTR9_B298_Pos = 0xa
	// Bit mask of B298 field.
	GTZC_VCTR9_B298_Msk = 0x400
	// Bit B298.
	GTZC_VCTR9_B298 = 0x400
	// Position of B299 field.
	GTZC_VCTR9_B299_Pos = 0xb
	// Bit mask of B299 field.
	GTZC_VCTR9_B299_Msk = 0x800
	// Bit B299.
	GTZC_VCTR9_B299 = 0x800
	// Position of B300 field.
	GTZC_VCTR9_B300_Pos = 0xc
	// Bit mask of B300 field.
	GTZC_VCTR9_B300_Msk = 0x1000
	// Bit B300.
	GTZC_VCTR9_B300 = 0x1000
	// Position of B301 field.
	GTZC_VCTR9_B301_Pos = 0xd
	// Bit mask of B301 field.
	GTZC_VCTR9_B301_Msk = 0x2000
	// Bit B301.
	GTZC_VCTR9_B301 = 0x2000
	// Position of B302 field.
	GTZC_VCTR9_B302_Pos = 0xe
	// Bit mask of B302 field.
	GTZC_VCTR9_B302_Msk = 0x4000
	// Bit B302.
	GTZC_VCTR9_B302 = 0x4000
	// Position of B303 field.
	GTZC_VCTR9_B303_Pos = 0xf
	// Bit mask of B303 field.
	GTZC_VCTR9_B303_Msk = 0x8000
	// Bit B303.
	GTZC_VCTR9_B303 = 0x8000
	// Position of B304 field.
	GTZC_VCTR9_B304_Pos = 0x10
	// Bit mask of B304 field.
	GTZC_VCTR9_B304_Msk = 0x10000
	// Bit B304.
	GTZC_VCTR9_B304 = 0x10000
	// Position of B305 field.
	GTZC_VCTR9_B305_Pos = 0x11
	// Bit mask of B305 field.
	GTZC_VCTR9_B305_Msk = 0x20000
	// Bit B305.
	GTZC_VCTR9_B305 = 0x20000
	// Position of B306 field.
	GTZC_VCTR9_B306_Pos = 0x12
	// Bit mask of B306 field.
	GTZC_VCTR9_B306_Msk = 0x40000
	// Bit B306.
	GTZC_VCTR9_B306 = 0x40000
	// Position of B307 field.
	GTZC_VCTR9_B307_Pos = 0x13
	// Bit mask of B307 field.
	GTZC_VCTR9_B307_Msk = 0x80000
	// Bit B307.
	GTZC_VCTR9_B307 = 0x80000
	// Position of B308 field.
	GTZC_VCTR9_B308_Pos = 0x14
	// Bit mask of B308 field.
	GTZC_VCTR9_B308_Msk = 0x100000
	// Bit B308.
	GTZC_VCTR9_B308 = 0x100000
	// Position of B309 field.
	GTZC_VCTR9_B309_Pos = 0x15
	// Bit mask of B309 field.
	GTZC_VCTR9_B309_Msk = 0x200000
	// Bit B309.
	GTZC_VCTR9_B309 = 0x200000
	// Position of B310 field.
	GTZC_VCTR9_B310_Pos = 0x16
	// Bit mask of B310 field.
	GTZC_VCTR9_B310_Msk = 0x400000
	// Bit B310.
	GTZC_VCTR9_B310 = 0x400000
	// Position of B311 field.
	GTZC_VCTR9_B311_Pos = 0x17
	// Bit mask of B311 field.
	GTZC_VCTR9_B311_Msk = 0x800000
	// Bit B311.
	GTZC_VCTR9_B311 = 0x800000
	// Position of B312 field.
	GTZC_VCTR9_B312_Pos = 0x18
	// Bit mask of B312 field.
	GTZC_VCTR9_B312_Msk = 0x1000000
	// Bit B312.
	GTZC_VCTR9_B312 = 0x1000000
	// Position of B313 field.
	GTZC_VCTR9_B313_Pos = 0x19
	// Bit mask of B313 field.
	GTZC_VCTR9_B313_Msk = 0x2000000
	// Bit B313.
	GTZC_VCTR9_B313 = 0x2000000
	// Position of B314 field.
	GTZC_VCTR9_B314_Pos = 0x1a
	// Bit mask of B314 field.
	GTZC_VCTR9_B314_Msk = 0x4000000
	// Bit B314.
	GTZC_VCTR9_B314 = 0x4000000
	// Position of B315 field.
	GTZC_VCTR9_B315_Pos = 0x1b
	// Bit mask of B315 field.
	GTZC_VCTR9_B315_Msk = 0x8000000
	// Bit B315.
	GTZC_VCTR9_B315 = 0x8000000
	// Position of B316 field.
	GTZC_VCTR9_B316_Pos = 0x1c
	// Bit mask of B316 field.
	GTZC_VCTR9_B316_Msk = 0x10000000
	// Bit B316.
	GTZC_VCTR9_B316 = 0x10000000
	// Position of B317 field.
	GTZC_VCTR9_B317_Pos = 0x1d
	// Bit mask of B317 field.
	GTZC_VCTR9_B317_Msk = 0x20000000
	// Bit B317.
	GTZC_VCTR9_B317 = 0x20000000
	// Position of B318 field.
	GTZC_VCTR9_B318_Pos = 0x1e
	// Bit mask of B318 field.
	GTZC_VCTR9_B318_Msk = 0x40000000
	// Bit B318.
	GTZC_VCTR9_B318 = 0x40000000
	// Position of B319 field.
	GTZC_VCTR9_B319_Pos = 0x1f
	// Bit mask of B319 field.
	GTZC_VCTR9_B319_Msk = 0x80000000
	// Bit B319.
	GTZC_VCTR9_B319 = 0x80000000

	// VCTR10: MPCBBx vector register
	// Position of B320 field.
	GTZC_VCTR10_B320_Pos = 0x0
	// Bit mask of B320 field.
	GTZC_VCTR10_B320_Msk = 0x1
	// Bit B320.
	GTZC_VCTR10_B320 = 0x1
	// Position of B321 field.
	GTZC_VCTR10_B321_Pos = 0x1
	// Bit mask of B321 field.
	GTZC_VCTR10_B321_Msk = 0x2
	// Bit B321.
	GTZC_VCTR10_B321 = 0x2
	// Position of B322 field.
	GTZC_VCTR10_B322_Pos = 0x2
	// Bit mask of B322 field.
	GTZC_VCTR10_B322_Msk = 0x4
	// Bit B322.
	GTZC_VCTR10_B322 = 0x4
	// Position of B323 field.
	GTZC_VCTR10_B323_Pos = 0x3
	// Bit mask of B323 field.
	GTZC_VCTR10_B323_Msk = 0x8
	// Bit B323.
	GTZC_VCTR10_B323 = 0x8
	// Position of B324 field.
	GTZC_VCTR10_B324_Pos = 0x4
	// Bit mask of B324 field.
	GTZC_VCTR10_B324_Msk = 0x10
	// Bit B324.
	GTZC_VCTR10_B324 = 0x10
	// Position of B325 field.
	GTZC_VCTR10_B325_Pos = 0x5
	// Bit mask of B325 field.
	GTZC_VCTR10_B325_Msk = 0x20
	// Bit B325.
	GTZC_VCTR10_B325 = 0x20
	// Position of B326 field.
	GTZC_VCTR10_B326_Pos = 0x6
	// Bit mask of B326 field.
	GTZC_VCTR10_B326_Msk = 0x40
	// Bit B326.
	GTZC_VCTR10_B326 = 0x40
	// Position of B327 field.
	GTZC_VCTR10_B327_Pos = 0x7
	// Bit mask of B327 field.
	GTZC_VCTR10_B327_Msk = 0x80
	// Bit B327.
	GTZC_VCTR10_B327 = 0x80
	// Position of B328 field.
	GTZC_VCTR10_B328_Pos = 0x8
	// Bit mask of B328 field.
	GTZC_VCTR10_B328_Msk = 0x100
	// Bit B328.
	GTZC_VCTR10_B328 = 0x100
	// Position of B329 field.
	GTZC_VCTR10_B329_Pos = 0x9
	// Bit mask of B329 field.
	GTZC_VCTR10_B329_Msk = 0x200
	// Bit B329.
	GTZC_VCTR10_B329 = 0x200
	// Position of B330 field.
	GTZC_VCTR10_B330_Pos = 0xa
	// Bit mask of B330 field.
	GTZC_VCTR10_B330_Msk = 0x400
	// Bit B330.
	GTZC_VCTR10_B330 = 0x400
	// Position of B331 field.
	GTZC_VCTR10_B331_Pos = 0xb
	// Bit mask of B331 field.
	GTZC_VCTR10_B331_Msk = 0x800
	// Bit B331.
	GTZC_VCTR10_B331 = 0x800
	// Position of B332 field.
	GTZC_VCTR10_B332_Pos = 0xc
	// Bit mask of B332 field.
	GTZC_VCTR10_B332_Msk = 0x1000
	// Bit B332.
	GTZC_VCTR10_B332 = 0x1000
	// Position of B333 field.
	GTZC_VCTR10_B333_Pos = 0xd
	// Bit mask of B333 field.
	GTZC_VCTR10_B333_Msk = 0x2000
	// Bit B333.
	GTZC_VCTR10_B333 = 0x2000
	// Position of B334 field.
	GTZC_VCTR10_B334_Pos = 0xe
	// Bit mask of B334 field.
	GTZC_VCTR10_B334_Msk = 0x4000
	// Bit B334.
	GTZC_VCTR10_B334 = 0x4000
	// Position of B335 field.
	GTZC_VCTR10_B335_Pos = 0xf
	// Bit mask of B335 field.
	GTZC_VCTR10_B335_Msk = 0x8000
	// Bit B335.
	GTZC_VCTR10_B335 = 0x8000
	// Position of B336 field.
	GTZC_VCTR10_B336_Pos = 0x10
	// Bit mask of B336 field.
	GTZC_VCTR10_B336_Msk = 0x10000
	// Bit B336.
	GTZC_VCTR10_B336 = 0x10000
	// Position of B337 field.
	GTZC_VCTR10_B337_Pos = 0x11
	// Bit mask of B337 field.
	GTZC_VCTR10_B337_Msk = 0x20000
	// Bit B337.
	GTZC_VCTR10_B337 = 0x20000
	// Position of B338 field.
	GTZC_VCTR10_B338_Pos = 0x12
	// Bit mask of B338 field.
	GTZC_VCTR10_B338_Msk = 0x40000
	// Bit B338.
	GTZC_VCTR10_B338 = 0x40000
	// Position of B339 field.
	GTZC_VCTR10_B339_Pos = 0x13
	// Bit mask of B339 field.
	GTZC_VCTR10_B339_Msk = 0x80000
	// Bit B339.
	GTZC_VCTR10_B339 = 0x80000
	// Position of B340 field.
	GTZC_VCTR10_B340_Pos = 0x14
	// Bit mask of B340 field.
	GTZC_VCTR10_B340_Msk = 0x100000
	// Bit B340.
	GTZC_VCTR10_B340 = 0x100000
	// Position of B341 field.
	GTZC_VCTR10_B341_Pos = 0x15
	// Bit mask of B341 field.
	GTZC_VCTR10_B341_Msk = 0x200000
	// Bit B341.
	GTZC_VCTR10_B341 = 0x200000
	// Position of B342 field.
	GTZC_VCTR10_B342_Pos = 0x16
	// Bit mask of B342 field.
	GTZC_VCTR10_B342_Msk = 0x400000
	// Bit B342.
	GTZC_VCTR10_B342 = 0x400000
	// Position of B343 field.
	GTZC_VCTR10_B343_Pos = 0x17
	// Bit mask of B343 field.
	GTZC_VCTR10_B343_Msk = 0x800000
	// Bit B343.
	GTZC_VCTR10_B343 = 0x800000
	// Position of B344 field.
	GTZC_VCTR10_B344_Pos = 0x18
	// Bit mask of B344 field.
	GTZC_VCTR10_B344_Msk = 0x1000000
	// Bit B344.
	GTZC_VCTR10_B344 = 0x1000000
	// Position of B345 field.
	GTZC_VCTR10_B345_Pos = 0x19
	// Bit mask of B345 field.
	GTZC_VCTR10_B345_Msk = 0x2000000
	// Bit B345.
	GTZC_VCTR10_B345 = 0x2000000
	// Position of B346 field.
	GTZC_VCTR10_B346_Pos = 0x1a
	// Bit mask of B346 field.
	GTZC_VCTR10_B346_Msk = 0x4000000
	// Bit B346.
	GTZC_VCTR10_B346 = 0x4000000
	// Position of B347 field.
	GTZC_VCTR10_B347_Pos = 0x1b
	// Bit mask of B347 field.
	GTZC_VCTR10_B347_Msk = 0x8000000
	// Bit B347.
	GTZC_VCTR10_B347 = 0x8000000
	// Position of B348 field.
	GTZC_VCTR10_B348_Pos = 0x1c
	// Bit mask of B348 field.
	GTZC_VCTR10_B348_Msk = 0x10000000
	// Bit B348.
	GTZC_VCTR10_B348 = 0x10000000
	// Position of B349 field.
	GTZC_VCTR10_B349_Pos = 0x1d
	// Bit mask of B349 field.
	GTZC_VCTR10_B349_Msk = 0x20000000
	// Bit B349.
	GTZC_VCTR10_B349 = 0x20000000
	// Position of B350 field.
	GTZC_VCTR10_B350_Pos = 0x1e
	// Bit mask of B350 field.
	GTZC_VCTR10_B350_Msk = 0x40000000
	// Bit B350.
	GTZC_VCTR10_B350 = 0x40000000
	// Position of B351 field.
	GTZC_VCTR10_B351_Pos = 0x1f
	// Bit mask of B351 field.
	GTZC_VCTR10_B351_Msk = 0x80000000
	// Bit B351.
	GTZC_VCTR10_B351 = 0x80000000

	// VCTR11: MPCBBx vector register
	// Position of B352 field.
	GTZC_VCTR11_B352_Pos = 0x0
	// Bit mask of B352 field.
	GTZC_VCTR11_B352_Msk = 0x1
	// Bit B352.
	GTZC_VCTR11_B352 = 0x1
	// Position of B353 field.
	GTZC_VCTR11_B353_Pos = 0x1
	// Bit mask of B353 field.
	GTZC_VCTR11_B353_Msk = 0x2
	// Bit B353.
	GTZC_VCTR11_B353 = 0x2
	// Position of B354 field.
	GTZC_VCTR11_B354_Pos = 0x2
	// Bit mask of B354 field.
	GTZC_VCTR11_B354_Msk = 0x4
	// Bit B354.
	GTZC_VCTR11_B354 = 0x4
	// Position of B355 field.
	GTZC_VCTR11_B355_Pos = 0x3
	// Bit mask of B355 field.
	GTZC_VCTR11_B355_Msk = 0x8
	// Bit B355.
	GTZC_VCTR11_B355 = 0x8
	// Position of B356 field.
	GTZC_VCTR11_B356_Pos = 0x4
	// Bit mask of B356 field.
	GTZC_VCTR11_B356_Msk = 0x10
	// Bit B356.
	GTZC_VCTR11_B356 = 0x10
	// Position of B357 field.
	GTZC_VCTR11_B357_Pos = 0x5
	// Bit mask of B357 field.
	GTZC_VCTR11_B357_Msk = 0x20
	// Bit B357.
	GTZC_VCTR11_B357 = 0x20
	// Position of B358 field.
	GTZC_VCTR11_B358_Pos = 0x6
	// Bit mask of B358 field.
	GTZC_VCTR11_B358_Msk = 0x40
	// Bit B358.
	GTZC_VCTR11_B358 = 0x40
	// Position of B359 field.
	GTZC_VCTR11_B359_Pos = 0x7
	// Bit mask of B359 field.
	GTZC_VCTR11_B359_Msk = 0x80
	// Bit B359.
	GTZC_VCTR11_B359 = 0x80
	// Position of B360 field.
	GTZC_VCTR11_B360_Pos = 0x8
	// Bit mask of B360 field.
	GTZC_VCTR11_B360_Msk = 0x100
	// Bit B360.
	GTZC_VCTR11_B360 = 0x100
	// Position of B361 field.
	GTZC_VCTR11_B361_Pos = 0x9
	// Bit mask of B361 field.
	GTZC_VCTR11_B361_Msk = 0x200
	// Bit B361.
	GTZC_VCTR11_B361 = 0x200
	// Position of B362 field.
	GTZC_VCTR11_B362_Pos = 0xa
	// Bit mask of B362 field.
	GTZC_VCTR11_B362_Msk = 0x400
	// Bit B362.
	GTZC_VCTR11_B362 = 0x400
	// Position of B363 field.
	GTZC_VCTR11_B363_Pos = 0xb
	// Bit mask of B363 field.
	GTZC_VCTR11_B363_Msk = 0x800
	// Bit B363.
	GTZC_VCTR11_B363 = 0x800
	// Position of B364 field.
	GTZC_VCTR11_B364_Pos = 0xc
	// Bit mask of B364 field.
	GTZC_VCTR11_B364_Msk = 0x1000
	// Bit B364.
	GTZC_VCTR11_B364 = 0x1000
	// Position of B365 field.
	GTZC_VCTR11_B365_Pos = 0xd
	// Bit mask of B365 field.
	GTZC_VCTR11_B365_Msk = 0x2000
	// Bit B365.
	GTZC_VCTR11_B365 = 0x2000
	// Position of B366 field.
	GTZC_VCTR11_B366_Pos = 0xe
	// Bit mask of B366 field.
	GTZC_VCTR11_B366_Msk = 0x4000
	// Bit B366.
	GTZC_VCTR11_B366 = 0x4000
	// Position of B367 field.
	GTZC_VCTR11_B367_Pos = 0xf
	// Bit mask of B367 field.
	GTZC_VCTR11_B367_Msk = 0x8000
	// Bit B367.
	GTZC_VCTR11_B367 = 0x8000
	// Position of B368 field.
	GTZC_VCTR11_B368_Pos = 0x10
	// Bit mask of B368 field.
	GTZC_VCTR11_B368_Msk = 0x10000
	// Bit B368.
	GTZC_VCTR11_B368 = 0x10000
	// Position of B369 field.
	GTZC_VCTR11_B369_Pos = 0x11
	// Bit mask of B369 field.
	GTZC_VCTR11_B369_Msk = 0x20000
	// Bit B369.
	GTZC_VCTR11_B369 = 0x20000
	// Position of B370 field.
	GTZC_VCTR11_B370_Pos = 0x12
	// Bit mask of B370 field.
	GTZC_VCTR11_B370_Msk = 0x40000
	// Bit B370.
	GTZC_VCTR11_B370 = 0x40000
	// Position of B371 field.
	GTZC_VCTR11_B371_Pos = 0x13
	// Bit mask of B371 field.
	GTZC_VCTR11_B371_Msk = 0x80000
	// Bit B371.
	GTZC_VCTR11_B371 = 0x80000
	// Position of B372 field.
	GTZC_VCTR11_B372_Pos = 0x14
	// Bit mask of B372 field.
	GTZC_VCTR11_B372_Msk = 0x100000
	// Bit B372.
	GTZC_VCTR11_B372 = 0x100000
	// Position of B373 field.
	GTZC_VCTR11_B373_Pos = 0x15
	// Bit mask of B373 field.
	GTZC_VCTR11_B373_Msk = 0x200000
	// Bit B373.
	GTZC_VCTR11_B373 = 0x200000
	// Position of B374 field.
	GTZC_VCTR11_B374_Pos = 0x16
	// Bit mask of B374 field.
	GTZC_VCTR11_B374_Msk = 0x400000
	// Bit B374.
	GTZC_VCTR11_B374 = 0x400000
	// Position of B375 field.
	GTZC_VCTR11_B375_Pos = 0x17
	// Bit mask of B375 field.
	GTZC_VCTR11_B375_Msk = 0x800000
	// Bit B375.
	GTZC_VCTR11_B375 = 0x800000
	// Position of B376 field.
	GTZC_VCTR11_B376_Pos = 0x18
	// Bit mask of B376 field.
	GTZC_VCTR11_B376_Msk = 0x1000000
	// Bit B376.
	GTZC_VCTR11_B376 = 0x1000000
	// Position of B377 field.
	GTZC_VCTR11_B377_Pos = 0x19
	// Bit mask of B377 field.
	GTZC_VCTR11_B377_Msk = 0x2000000
	// Bit B377.
	GTZC_VCTR11_B377 = 0x2000000
	// Position of B378 field.
	GTZC_VCTR11_B378_Pos = 0x1a
	// Bit mask of B378 field.
	GTZC_VCTR11_B378_Msk = 0x4000000
	// Bit B378.
	GTZC_VCTR11_B378 = 0x4000000
	// Position of B379 field.
	GTZC_VCTR11_B379_Pos = 0x1b
	// Bit mask of B379 field.
	GTZC_VCTR11_B379_Msk = 0x8000000
	// Bit B379.
	GTZC_VCTR11_B379 = 0x8000000
	// Position of B380 field.
	GTZC_VCTR11_B380_Pos = 0x1c
	// Bit mask of B380 field.
	GTZC_VCTR11_B380_Msk = 0x10000000
	// Bit B380.
	GTZC_VCTR11_B380 = 0x10000000
	// Position of B381 field.
	GTZC_VCTR11_B381_Pos = 0x1d
	// Bit mask of B381 field.
	GTZC_VCTR11_B381_Msk = 0x20000000
	// Bit B381.
	GTZC_VCTR11_B381 = 0x20000000
	// Position of B382 field.
	GTZC_VCTR11_B382_Pos = 0x1e
	// Bit mask of B382 field.
	GTZC_VCTR11_B382_Msk = 0x40000000
	// Bit B382.
	GTZC_VCTR11_B382 = 0x40000000
	// Position of B383 field.
	GTZC_VCTR11_B383_Pos = 0x1f
	// Bit mask of B383 field.
	GTZC_VCTR11_B383_Msk = 0x80000000
	// Bit B383.
	GTZC_VCTR11_B383 = 0x80000000

	// VCTR12: MPCBBx vector register
	// Position of B384 field.
	GTZC_VCTR12_B384_Pos = 0x0
	// Bit mask of B384 field.
	GTZC_VCTR12_B384_Msk = 0x1
	// Bit B384.
	GTZC_VCTR12_B384 = 0x1
	// Position of B385 field.
	GTZC_VCTR12_B385_Pos = 0x1
	// Bit mask of B385 field.
	GTZC_VCTR12_B385_Msk = 0x2
	// Bit B385.
	GTZC_VCTR12_B385 = 0x2
	// Position of B386 field.
	GTZC_VCTR12_B386_Pos = 0x2
	// Bit mask of B386 field.
	GTZC_VCTR12_B386_Msk = 0x4
	// Bit B386.
	GTZC_VCTR12_B386 = 0x4
	// Position of B387 field.
	GTZC_VCTR12_B387_Pos = 0x3
	// Bit mask of B387 field.
	GTZC_VCTR12_B387_Msk = 0x8
	// Bit B387.
	GTZC_VCTR12_B387 = 0x8
	// Position of B388 field.
	GTZC_VCTR12_B388_Pos = 0x4
	// Bit mask of B388 field.
	GTZC_VCTR12_B388_Msk = 0x10
	// Bit B388.
	GTZC_VCTR12_B388 = 0x10
	// Position of B389 field.
	GTZC_VCTR12_B389_Pos = 0x5
	// Bit mask of B389 field.
	GTZC_VCTR12_B389_Msk = 0x20
	// Bit B389.
	GTZC_VCTR12_B389 = 0x20
	// Position of B390 field.
	GTZC_VCTR12_B390_Pos = 0x6
	// Bit mask of B390 field.
	GTZC_VCTR12_B390_Msk = 0x40
	// Bit B390.
	GTZC_VCTR12_B390 = 0x40
	// Position of B391 field.
	GTZC_VCTR12_B391_Pos = 0x7
	// Bit mask of B391 field.
	GTZC_VCTR12_B391_Msk = 0x80
	// Bit B391.
	GTZC_VCTR12_B391 = 0x80
	// Position of B392 field.
	GTZC_VCTR12_B392_Pos = 0x8
	// Bit mask of B392 field.
	GTZC_VCTR12_B392_Msk = 0x100
	// Bit B392.
	GTZC_VCTR12_B392 = 0x100
	// Position of B393 field.
	GTZC_VCTR12_B393_Pos = 0x9
	// Bit mask of B393 field.
	GTZC_VCTR12_B393_Msk = 0x200
	// Bit B393.
	GTZC_VCTR12_B393 = 0x200
	// Position of B394 field.
	GTZC_VCTR12_B394_Pos = 0xa
	// Bit mask of B394 field.
	GTZC_VCTR12_B394_Msk = 0x400
	// Bit B394.
	GTZC_VCTR12_B394 = 0x400
	// Position of B395 field.
	GTZC_VCTR12_B395_Pos = 0xb
	// Bit mask of B395 field.
	GTZC_VCTR12_B395_Msk = 0x800
	// Bit B395.
	GTZC_VCTR12_B395 = 0x800
	// Position of B396 field.
	GTZC_VCTR12_B396_Pos = 0xc
	// Bit mask of B396 field.
	GTZC_VCTR12_B396_Msk = 0x1000
	// Bit B396.
	GTZC_VCTR12_B396 = 0x1000
	// Position of B397 field.
	GTZC_VCTR12_B397_Pos = 0xd
	// Bit mask of B397 field.
	GTZC_VCTR12_B397_Msk = 0x2000
	// Bit B397.
	GTZC_VCTR12_B397 = 0x2000
	// Position of B398 field.
	GTZC_VCTR12_B398_Pos = 0xe
	// Bit mask of B398 field.
	GTZC_VCTR12_B398_Msk = 0x4000
	// Bit B398.
	GTZC_VCTR12_B398 = 0x4000
	// Position of B399 field.
	GTZC_VCTR12_B399_Pos = 0xf
	// Bit mask of B399 field.
	GTZC_VCTR12_B399_Msk = 0x8000
	// Bit B399.
	GTZC_VCTR12_B399 = 0x8000
	// Position of B400 field.
	GTZC_VCTR12_B400_Pos = 0x10
	// Bit mask of B400 field.
	GTZC_VCTR12_B400_Msk = 0x10000
	// Bit B400.
	GTZC_VCTR12_B400 = 0x10000
	// Position of B401 field.
	GTZC_VCTR12_B401_Pos = 0x11
	// Bit mask of B401 field.
	GTZC_VCTR12_B401_Msk = 0x20000
	// Bit B401.
	GTZC_VCTR12_B401 = 0x20000
	// Position of B402 field.
	GTZC_VCTR12_B402_Pos = 0x12
	// Bit mask of B402 field.
	GTZC_VCTR12_B402_Msk = 0x40000
	// Bit B402.
	GTZC_VCTR12_B402 = 0x40000
	// Position of B403 field.
	GTZC_VCTR12_B403_Pos = 0x13
	// Bit mask of B403 field.
	GTZC_VCTR12_B403_Msk = 0x80000
	// Bit B403.
	GTZC_VCTR12_B403 = 0x80000
	// Position of B404 field.
	GTZC_VCTR12_B404_Pos = 0x14
	// Bit mask of B404 field.
	GTZC_VCTR12_B404_Msk = 0x100000
	// Bit B404.
	GTZC_VCTR12_B404 = 0x100000
	// Position of B405 field.
	GTZC_VCTR12_B405_Pos = 0x15
	// Bit mask of B405 field.
	GTZC_VCTR12_B405_Msk = 0x200000
	// Bit B405.
	GTZC_VCTR12_B405 = 0x200000
	// Position of B406 field.
	GTZC_VCTR12_B406_Pos = 0x16
	// Bit mask of B406 field.
	GTZC_VCTR12_B406_Msk = 0x400000
	// Bit B406.
	GTZC_VCTR12_B406 = 0x400000
	// Position of B407 field.
	GTZC_VCTR12_B407_Pos = 0x17
	// Bit mask of B407 field.
	GTZC_VCTR12_B407_Msk = 0x800000
	// Bit B407.
	GTZC_VCTR12_B407 = 0x800000
	// Position of B408 field.
	GTZC_VCTR12_B408_Pos = 0x18
	// Bit mask of B408 field.
	GTZC_VCTR12_B408_Msk = 0x1000000
	// Bit B408.
	GTZC_VCTR12_B408 = 0x1000000
	// Position of B409 field.
	GTZC_VCTR12_B409_Pos = 0x19
	// Bit mask of B409 field.
	GTZC_VCTR12_B409_Msk = 0x2000000
	// Bit B409.
	GTZC_VCTR12_B409 = 0x2000000
	// Position of B410 field.
	GTZC_VCTR12_B410_Pos = 0x1a
	// Bit mask of B410 field.
	GTZC_VCTR12_B410_Msk = 0x4000000
	// Bit B410.
	GTZC_VCTR12_B410 = 0x4000000
	// Position of B411 field.
	GTZC_VCTR12_B411_Pos = 0x1b
	// Bit mask of B411 field.
	GTZC_VCTR12_B411_Msk = 0x8000000
	// Bit B411.
	GTZC_VCTR12_B411 = 0x8000000
	// Position of B412 field.
	GTZC_VCTR12_B412_Pos = 0x1c
	// Bit mask of B412 field.
	GTZC_VCTR12_B412_Msk = 0x10000000
	// Bit B412.
	GTZC_VCTR12_B412 = 0x10000000
	// Position of B413 field.
	GTZC_VCTR12_B413_Pos = 0x1d
	// Bit mask of B413 field.
	GTZC_VCTR12_B413_Msk = 0x20000000
	// Bit B413.
	GTZC_VCTR12_B413 = 0x20000000
	// Position of B414 field.
	GTZC_VCTR12_B414_Pos = 0x1e
	// Bit mask of B414 field.
	GTZC_VCTR12_B414_Msk = 0x40000000
	// Bit B414.
	GTZC_VCTR12_B414 = 0x40000000
	// Position of B415 field.
	GTZC_VCTR12_B415_Pos = 0x1f
	// Bit mask of B415 field.
	GTZC_VCTR12_B415_Msk = 0x80000000
	// Bit B415.
	GTZC_VCTR12_B415 = 0x80000000

	// VCTR13: MPCBBx vector register
	// Position of B416 field.
	GTZC_VCTR13_B416_Pos = 0x0
	// Bit mask of B416 field.
	GTZC_VCTR13_B416_Msk = 0x1
	// Bit B416.
	GTZC_VCTR13_B416 = 0x1
	// Position of B417 field.
	GTZC_VCTR13_B417_Pos = 0x1
	// Bit mask of B417 field.
	GTZC_VCTR13_B417_Msk = 0x2
	// Bit B417.
	GTZC_VCTR13_B417 = 0x2
	// Position of B418 field.
	GTZC_VCTR13_B418_Pos = 0x2
	// Bit mask of B418 field.
	GTZC_VCTR13_B418_Msk = 0x4
	// Bit B418.
	GTZC_VCTR13_B418 = 0x4
	// Position of B419 field.
	GTZC_VCTR13_B419_Pos = 0x3
	// Bit mask of B419 field.
	GTZC_VCTR13_B419_Msk = 0x8
	// Bit B419.
	GTZC_VCTR13_B419 = 0x8
	// Position of B420 field.
	GTZC_VCTR13_B420_Pos = 0x4
	// Bit mask of B420 field.
	GTZC_VCTR13_B420_Msk = 0x10
	// Bit B420.
	GTZC_VCTR13_B420 = 0x10
	// Position of B421 field.
	GTZC_VCTR13_B421_Pos = 0x5
	// Bit mask of B421 field.
	GTZC_VCTR13_B421_Msk = 0x20
	// Bit B421.
	GTZC_VCTR13_B421 = 0x20
	// Position of B422 field.
	GTZC_VCTR13_B422_Pos = 0x6
	// Bit mask of B422 field.
	GTZC_VCTR13_B422_Msk = 0x40
	// Bit B422.
	GTZC_VCTR13_B422 = 0x40
	// Position of B423 field.
	GTZC_VCTR13_B423_Pos = 0x7
	// Bit mask of B423 field.
	GTZC_VCTR13_B423_Msk = 0x80
	// Bit B423.
	GTZC_VCTR13_B423 = 0x80
	// Position of B424 field.
	GTZC_VCTR13_B424_Pos = 0x8
	// Bit mask of B424 field.
	GTZC_VCTR13_B424_Msk = 0x100
	// Bit B424.
	GTZC_VCTR13_B424 = 0x100
	// Position of B425 field.
	GTZC_VCTR13_B425_Pos = 0x9
	// Bit mask of B425 field.
	GTZC_VCTR13_B425_Msk = 0x200
	// Bit B425.
	GTZC_VCTR13_B425 = 0x200
	// Position of B426 field.
	GTZC_VCTR13_B426_Pos = 0xa
	// Bit mask of B426 field.
	GTZC_VCTR13_B426_Msk = 0x400
	// Bit B426.
	GTZC_VCTR13_B426 = 0x400
	// Position of B427 field.
	GTZC_VCTR13_B427_Pos = 0xb
	// Bit mask of B427 field.
	GTZC_VCTR13_B427_Msk = 0x800
	// Bit B427.
	GTZC_VCTR13_B427 = 0x800
	// Position of B428 field.
	GTZC_VCTR13_B428_Pos = 0xc
	// Bit mask of B428 field.
	GTZC_VCTR13_B428_Msk = 0x1000
	// Bit B428.
	GTZC_VCTR13_B428 = 0x1000
	// Position of B429 field.
	GTZC_VCTR13_B429_Pos = 0xd
	// Bit mask of B429 field.
	GTZC_VCTR13_B429_Msk = 0x2000
	// Bit B429.
	GTZC_VCTR13_B429 = 0x2000
	// Position of B430 field.
	GTZC_VCTR13_B430_Pos = 0xe
	// Bit mask of B430 field.
	GTZC_VCTR13_B430_Msk = 0x4000
	// Bit B430.
	GTZC_VCTR13_B430 = 0x4000
	// Position of B431 field.
	GTZC_VCTR13_B431_Pos = 0xf
	// Bit mask of B431 field.
	GTZC_VCTR13_B431_Msk = 0x8000
	// Bit B431.
	GTZC_VCTR13_B431 = 0x8000
	// Position of B432 field.
	GTZC_VCTR13_B432_Pos = 0x10
	// Bit mask of B432 field.
	GTZC_VCTR13_B432_Msk = 0x10000
	// Bit B432.
	GTZC_VCTR13_B432 = 0x10000
	// Position of B433 field.
	GTZC_VCTR13_B433_Pos = 0x11
	// Bit mask of B433 field.
	GTZC_VCTR13_B433_Msk = 0x20000
	// Bit B433.
	GTZC_VCTR13_B433 = 0x20000
	// Position of B434 field.
	GTZC_VCTR13_B434_Pos = 0x12
	// Bit mask of B434 field.
	GTZC_VCTR13_B434_Msk = 0x40000
	// Bit B434.
	GTZC_VCTR13_B434 = 0x40000
	// Position of B435 field.
	GTZC_VCTR13_B435_Pos = 0x13
	// Bit mask of B435 field.
	GTZC_VCTR13_B435_Msk = 0x80000
	// Bit B435.
	GTZC_VCTR13_B435 = 0x80000
	// Position of B436 field.
	GTZC_VCTR13_B436_Pos = 0x14
	// Bit mask of B436 field.
	GTZC_VCTR13_B436_Msk = 0x100000
	// Bit B436.
	GTZC_VCTR13_B436 = 0x100000
	// Position of B437 field.
	GTZC_VCTR13_B437_Pos = 0x15
	// Bit mask of B437 field.
	GTZC_VCTR13_B437_Msk = 0x200000
	// Bit B437.
	GTZC_VCTR13_B437 = 0x200000
	// Position of B438 field.
	GTZC_VCTR13_B438_Pos = 0x16
	// Bit mask of B438 field.
	GTZC_VCTR13_B438_Msk = 0x400000
	// Bit B438.
	GTZC_VCTR13_B438 = 0x400000
	// Position of B439 field.
	GTZC_VCTR13_B439_Pos = 0x17
	// Bit mask of B439 field.
	GTZC_VCTR13_B439_Msk = 0x800000
	// Bit B439.
	GTZC_VCTR13_B439 = 0x800000
	// Position of B440 field.
	GTZC_VCTR13_B440_Pos = 0x18
	// Bit mask of B440 field.
	GTZC_VCTR13_B440_Msk = 0x1000000
	// Bit B440.
	GTZC_VCTR13_B440 = 0x1000000
	// Position of B441 field.
	GTZC_VCTR13_B441_Pos = 0x19
	// Bit mask of B441 field.
	GTZC_VCTR13_B441_Msk = 0x2000000
	// Bit B441.
	GTZC_VCTR13_B441 = 0x2000000
	// Position of B442 field.
	GTZC_VCTR13_B442_Pos = 0x1a
	// Bit mask of B442 field.
	GTZC_VCTR13_B442_Msk = 0x4000000
	// Bit B442.
	GTZC_VCTR13_B442 = 0x4000000
	// Position of B443 field.
	GTZC_VCTR13_B443_Pos = 0x1b
	// Bit mask of B443 field.
	GTZC_VCTR13_B443_Msk = 0x8000000
	// Bit B443.
	GTZC_VCTR13_B443 = 0x8000000
	// Position of B444 field.
	GTZC_VCTR13_B444_Pos = 0x1c
	// Bit mask of B444 field.
	GTZC_VCTR13_B444_Msk = 0x10000000
	// Bit B444.
	GTZC_VCTR13_B444 = 0x10000000
	// Position of B445 field.
	GTZC_VCTR13_B445_Pos = 0x1d
	// Bit mask of B445 field.
	GTZC_VCTR13_B445_Msk = 0x20000000
	// Bit B445.
	GTZC_VCTR13_B445 = 0x20000000
	// Position of B446 field.
	GTZC_VCTR13_B446_Pos = 0x1e
	// Bit mask of B446 field.
	GTZC_VCTR13_B446_Msk = 0x40000000
	// Bit B446.
	GTZC_VCTR13_B446 = 0x40000000
	// Position of B447 field.
	GTZC_VCTR13_B447_Pos = 0x1f
	// Bit mask of B447 field.
	GTZC_VCTR13_B447_Msk = 0x80000000
	// Bit B447.
	GTZC_VCTR13_B447 = 0x80000000

	// VCTR14: MPCBBx vector register
	// Position of B448 field.
	GTZC_VCTR14_B448_Pos = 0x0
	// Bit mask of B448 field.
	GTZC_VCTR14_B448_Msk = 0x1
	// Bit B448.
	GTZC_VCTR14_B448 = 0x1
	// Position of B449 field.
	GTZC_VCTR14_B449_Pos = 0x1
	// Bit mask of B449 field.
	GTZC_VCTR14_B449_Msk = 0x2
	// Bit B449.
	GTZC_VCTR14_B449 = 0x2
	// Position of B450 field.
	GTZC_VCTR14_B450_Pos = 0x2
	// Bit mask of B450 field.
	GTZC_VCTR14_B450_Msk = 0x4
	// Bit B450.
	GTZC_VCTR14_B450 = 0x4
	// Position of B451 field.
	GTZC_VCTR14_B451_Pos = 0x3
	// Bit mask of B451 field.
	GTZC_VCTR14_B451_Msk = 0x8
	// Bit B451.
	GTZC_VCTR14_B451 = 0x8
	// Position of B452 field.
	GTZC_VCTR14_B452_Pos = 0x4
	// Bit mask of B452 field.
	GTZC_VCTR14_B452_Msk = 0x10
	// Bit B452.
	GTZC_VCTR14_B452 = 0x10
	// Position of B453 field.
	GTZC_VCTR14_B453_Pos = 0x5
	// Bit mask of B453 field.
	GTZC_VCTR14_B453_Msk = 0x20
	// Bit B453.
	GTZC_VCTR14_B453 = 0x20
	// Position of B454 field.
	GTZC_VCTR14_B454_Pos = 0x6
	// Bit mask of B454 field.
	GTZC_VCTR14_B454_Msk = 0x40
	// Bit B454.
	GTZC_VCTR14_B454 = 0x40
	// Position of B455 field.
	GTZC_VCTR14_B455_Pos = 0x7
	// Bit mask of B455 field.
	GTZC_VCTR14_B455_Msk = 0x80
	// Bit B455.
	GTZC_VCTR14_B455 = 0x80
	// Position of B456 field.
	GTZC_VCTR14_B456_Pos = 0x8
	// Bit mask of B456 field.
	GTZC_VCTR14_B456_Msk = 0x100
	// Bit B456.
	GTZC_VCTR14_B456 = 0x100
	// Position of B457 field.
	GTZC_VCTR14_B457_Pos = 0x9
	// Bit mask of B457 field.
	GTZC_VCTR14_B457_Msk = 0x200
	// Bit B457.
	GTZC_VCTR14_B457 = 0x200
	// Position of B458 field.
	GTZC_VCTR14_B458_Pos = 0xa
	// Bit mask of B458 field.
	GTZC_VCTR14_B458_Msk = 0x400
	// Bit B458.
	GTZC_VCTR14_B458 = 0x400
	// Position of B459 field.
	GTZC_VCTR14_B459_Pos = 0xb
	// Bit mask of B459 field.
	GTZC_VCTR14_B459_Msk = 0x800
	// Bit B459.
	GTZC_VCTR14_B459 = 0x800
	// Position of B460 field.
	GTZC_VCTR14_B460_Pos = 0xc
	// Bit mask of B460 field.
	GTZC_VCTR14_B460_Msk = 0x1000
	// Bit B460.
	GTZC_VCTR14_B460 = 0x1000
	// Position of B461 field.
	GTZC_VCTR14_B461_Pos = 0xd
	// Bit mask of B461 field.
	GTZC_VCTR14_B461_Msk = 0x2000
	// Bit B461.
	GTZC_VCTR14_B461 = 0x2000
	// Position of B462 field.
	GTZC_VCTR14_B462_Pos = 0xe
	// Bit mask of B462 field.
	GTZC_VCTR14_B462_Msk = 0x4000
	// Bit B462.
	GTZC_VCTR14_B462 = 0x4000
	// Position of B463 field.
	GTZC_VCTR14_B463_Pos = 0xf
	// Bit mask of B463 field.
	GTZC_VCTR14_B463_Msk = 0x8000
	// Bit B463.
	GTZC_VCTR14_B463 = 0x8000
	// Position of B464 field.
	GTZC_VCTR14_B464_Pos = 0x10
	// Bit mask of B464 field.
	GTZC_VCTR14_B464_Msk = 0x10000
	// Bit B464.
	GTZC_VCTR14_B464 = 0x10000
	// Position of B465 field.
	GTZC_VCTR14_B465_Pos = 0x11
	// Bit mask of B465 field.
	GTZC_VCTR14_B465_Msk = 0x20000
	// Bit B465.
	GTZC_VCTR14_B465 = 0x20000
	// Position of B466 field.
	GTZC_VCTR14_B466_Pos = 0x12
	// Bit mask of B466 field.
	GTZC_VCTR14_B466_Msk = 0x40000
	// Bit B466.
	GTZC_VCTR14_B466 = 0x40000
	// Position of B467 field.
	GTZC_VCTR14_B467_Pos = 0x13
	// Bit mask of B467 field.
	GTZC_VCTR14_B467_Msk = 0x80000
	// Bit B467.
	GTZC_VCTR14_B467 = 0x80000
	// Position of B468 field.
	GTZC_VCTR14_B468_Pos = 0x14
	// Bit mask of B468 field.
	GTZC_VCTR14_B468_Msk = 0x100000
	// Bit B468.
	GTZC_VCTR14_B468 = 0x100000
	// Position of B469 field.
	GTZC_VCTR14_B469_Pos = 0x15
	// Bit mask of B469 field.
	GTZC_VCTR14_B469_Msk = 0x200000
	// Bit B469.
	GTZC_VCTR14_B469 = 0x200000
	// Position of B470 field.
	GTZC_VCTR14_B470_Pos = 0x16
	// Bit mask of B470 field.
	GTZC_VCTR14_B470_Msk = 0x400000
	// Bit B470.
	GTZC_VCTR14_B470 = 0x400000
	// Position of B471 field.
	GTZC_VCTR14_B471_Pos = 0x17
	// Bit mask of B471 field.
	GTZC_VCTR14_B471_Msk = 0x800000
	// Bit B471.
	GTZC_VCTR14_B471 = 0x800000
	// Position of B472 field.
	GTZC_VCTR14_B472_Pos = 0x18
	// Bit mask of B472 field.
	GTZC_VCTR14_B472_Msk = 0x1000000
	// Bit B472.
	GTZC_VCTR14_B472 = 0x1000000
	// Position of B473 field.
	GTZC_VCTR14_B473_Pos = 0x19
	// Bit mask of B473 field.
	GTZC_VCTR14_B473_Msk = 0x2000000
	// Bit B473.
	GTZC_VCTR14_B473 = 0x2000000
	// Position of B474 field.
	GTZC_VCTR14_B474_Pos = 0x1a
	// Bit mask of B474 field.
	GTZC_VCTR14_B474_Msk = 0x4000000
	// Bit B474.
	GTZC_VCTR14_B474 = 0x4000000
	// Position of B475 field.
	GTZC_VCTR14_B475_Pos = 0x1b
	// Bit mask of B475 field.
	GTZC_VCTR14_B475_Msk = 0x8000000
	// Bit B475.
	GTZC_VCTR14_B475 = 0x8000000
	// Position of B476 field.
	GTZC_VCTR14_B476_Pos = 0x1c
	// Bit mask of B476 field.
	GTZC_VCTR14_B476_Msk = 0x10000000
	// Bit B476.
	GTZC_VCTR14_B476 = 0x10000000
	// Position of B477 field.
	GTZC_VCTR14_B477_Pos = 0x1d
	// Bit mask of B477 field.
	GTZC_VCTR14_B477_Msk = 0x20000000
	// Bit B477.
	GTZC_VCTR14_B477 = 0x20000000
	// Position of B478 field.
	GTZC_VCTR14_B478_Pos = 0x1e
	// Bit mask of B478 field.
	GTZC_VCTR14_B478_Msk = 0x40000000
	// Bit B478.
	GTZC_VCTR14_B478 = 0x40000000
	// Position of B479 field.
	GTZC_VCTR14_B479_Pos = 0x1f
	// Bit mask of B479 field.
	GTZC_VCTR14_B479_Msk = 0x80000000
	// Bit B479.
	GTZC_VCTR14_B479 = 0x80000000

	// VCTR15: MPCBBx vector register
	// Position of B480 field.
	GTZC_VCTR15_B480_Pos = 0x0
	// Bit mask of B480 field.
	GTZC_VCTR15_B480_Msk = 0x1
	// Bit B480.
	GTZC_VCTR15_B480 = 0x1
	// Position of B481 field.
	GTZC_VCTR15_B481_Pos = 0x1
	// Bit mask of B481 field.
	GTZC_VCTR15_B481_Msk = 0x2
	// Bit B481.
	GTZC_VCTR15_B481 = 0x2
	// Position of B482 field.
	GTZC_VCTR15_B482_Pos = 0x2
	// Bit mask of B482 field.
	GTZC_VCTR15_B482_Msk = 0x4
	// Bit B482.
	GTZC_VCTR15_B482 = 0x4
	// Position of B483 field.
	GTZC_VCTR15_B483_Pos = 0x3
	// Bit mask of B483 field.
	GTZC_VCTR15_B483_Msk = 0x8
	// Bit B483.
	GTZC_VCTR15_B483 = 0x8
	// Position of B484 field.
	GTZC_VCTR15_B484_Pos = 0x4
	// Bit mask of B484 field.
	GTZC_VCTR15_B484_Msk = 0x10
	// Bit B484.
	GTZC_VCTR15_B484 = 0x10
	// Position of B485 field.
	GTZC_VCTR15_B485_Pos = 0x5
	// Bit mask of B485 field.
	GTZC_VCTR15_B485_Msk = 0x20
	// Bit B485.
	GTZC_VCTR15_B485 = 0x20
	// Position of B486 field.
	GTZC_VCTR15_B486_Pos = 0x6
	// Bit mask of B486 field.
	GTZC_VCTR15_B486_Msk = 0x40
	// Bit B486.
	GTZC_VCTR15_B486 = 0x40
	// Position of B487 field.
	GTZC_VCTR15_B487_Pos = 0x7
	// Bit mask of B487 field.
	GTZC_VCTR15_B487_Msk = 0x80
	// Bit B487.
	GTZC_VCTR15_B487 = 0x80
	// Position of B488 field.
	GTZC_VCTR15_B488_Pos = 0x8
	// Bit mask of B488 field.
	GTZC_VCTR15_B488_Msk = 0x100
	// Bit B488.
	GTZC_VCTR15_B488 = 0x100
	// Position of B489 field.
	GTZC_VCTR15_B489_Pos = 0x9
	// Bit mask of B489 field.
	GTZC_VCTR15_B489_Msk = 0x200
	// Bit B489.
	GTZC_VCTR15_B489 = 0x200
	// Position of B490 field.
	GTZC_VCTR15_B490_Pos = 0xa
	// Bit mask of B490 field.
	GTZC_VCTR15_B490_Msk = 0x400
	// Bit B490.
	GTZC_VCTR15_B490 = 0x400
	// Position of B491 field.
	GTZC_VCTR15_B491_Pos = 0xb
	// Bit mask of B491 field.
	GTZC_VCTR15_B491_Msk = 0x800
	// Bit B491.
	GTZC_VCTR15_B491 = 0x800
	// Position of B492 field.
	GTZC_VCTR15_B492_Pos = 0xc
	// Bit mask of B492 field.
	GTZC_VCTR15_B492_Msk = 0x1000
	// Bit B492.
	GTZC_VCTR15_B492 = 0x1000
	// Position of B493 field.
	GTZC_VCTR15_B493_Pos = 0xd
	// Bit mask of B493 field.
	GTZC_VCTR15_B493_Msk = 0x2000
	// Bit B493.
	GTZC_VCTR15_B493 = 0x2000
	// Position of B494 field.
	GTZC_VCTR15_B494_Pos = 0xe
	// Bit mask of B494 field.
	GTZC_VCTR15_B494_Msk = 0x4000
	// Bit B494.
	GTZC_VCTR15_B494 = 0x4000
	// Position of B495 field.
	GTZC_VCTR15_B495_Pos = 0xf
	// Bit mask of B495 field.
	GTZC_VCTR15_B495_Msk = 0x8000
	// Bit B495.
	GTZC_VCTR15_B495 = 0x8000
	// Position of B496 field.
	GTZC_VCTR15_B496_Pos = 0x10
	// Bit mask of B496 field.
	GTZC_VCTR15_B496_Msk = 0x10000
	// Bit B496.
	GTZC_VCTR15_B496 = 0x10000
	// Position of B497 field.
	GTZC_VCTR15_B497_Pos = 0x11
	// Bit mask of B497 field.
	GTZC_VCTR15_B497_Msk = 0x20000
	// Bit B497.
	GTZC_VCTR15_B497 = 0x20000
	// Position of B498 field.
	GTZC_VCTR15_B498_Pos = 0x12
	// Bit mask of B498 field.
	GTZC_VCTR15_B498_Msk = 0x40000
	// Bit B498.
	GTZC_VCTR15_B498 = 0x40000
	// Position of B499 field.
	GTZC_VCTR15_B499_Pos = 0x13
	// Bit mask of B499 field.
	GTZC_VCTR15_B499_Msk = 0x80000
	// Bit B499.
	GTZC_VCTR15_B499 = 0x80000
	// Position of B500 field.
	GTZC_VCTR15_B500_Pos = 0x14
	// Bit mask of B500 field.
	GTZC_VCTR15_B500_Msk = 0x100000
	// Bit B500.
	GTZC_VCTR15_B500 = 0x100000
	// Position of B501 field.
	GTZC_VCTR15_B501_Pos = 0x15
	// Bit mask of B501 field.
	GTZC_VCTR15_B501_Msk = 0x200000
	// Bit B501.
	GTZC_VCTR15_B501 = 0x200000
	// Position of B502 field.
	GTZC_VCTR15_B502_Pos = 0x16
	// Bit mask of B502 field.
	GTZC_VCTR15_B502_Msk = 0x400000
	// Bit B502.
	GTZC_VCTR15_B502 = 0x400000
	// Position of B503 field.
	GTZC_VCTR15_B503_Pos = 0x17
	// Bit mask of B503 field.
	GTZC_VCTR15_B503_Msk = 0x800000
	// Bit B503.
	GTZC_VCTR15_B503 = 0x800000
	// Position of B504 field.
	GTZC_VCTR15_B504_Pos = 0x18
	// Bit mask of B504 field.
	GTZC_VCTR15_B504_Msk = 0x1000000
	// Bit B504.
	GTZC_VCTR15_B504 = 0x1000000
	// Position of B505 field.
	GTZC_VCTR15_B505_Pos = 0x19
	// Bit mask of B505 field.
	GTZC_VCTR15_B505_Msk = 0x2000000
	// Bit B505.
	GTZC_VCTR15_B505 = 0x2000000
	// Position of B506 field.
	GTZC_VCTR15_B506_Pos = 0x1a
	// Bit mask of B506 field.
	GTZC_VCTR15_B506_Msk = 0x4000000
	// Bit B506.
	GTZC_VCTR15_B506 = 0x4000000
	// Position of B507 field.
	GTZC_VCTR15_B507_Pos = 0x1b
	// Bit mask of B507 field.
	GTZC_VCTR15_B507_Msk = 0x8000000
	// Bit B507.
	GTZC_VCTR15_B507 = 0x8000000
	// Position of B508 field.
	GTZC_VCTR15_B508_Pos = 0x1c
	// Bit mask of B508 field.
	GTZC_VCTR15_B508_Msk = 0x10000000
	// Bit B508.
	GTZC_VCTR15_B508 = 0x10000000
	// Position of B509 field.
	GTZC_VCTR15_B509_Pos = 0x1d
	// Bit mask of B509 field.
	GTZC_VCTR15_B509_Msk = 0x20000000
	// Bit B509.
	GTZC_VCTR15_B509 = 0x20000000
	// Position of B510 field.
	GTZC_VCTR15_B510_Pos = 0x1e
	// Bit mask of B510 field.
	GTZC_VCTR15_B510_Msk = 0x40000000
	// Bit B510.
	GTZC_VCTR15_B510 = 0x40000000
	// Position of B511 field.
	GTZC_VCTR15_B511_Pos = 0x1f
	// Bit mask of B511 field.
	GTZC_VCTR15_B511_Msk = 0x80000000
	// Bit B511.
	GTZC_VCTR15_B511 = 0x80000000

	// VCTR16: MPCBBx vector register
	// Position of B512 field.
	GTZC_VCTR16_B512_Pos = 0x0
	// Bit mask of B512 field.
	GTZC_VCTR16_B512_Msk = 0x1
	// Bit B512.
	GTZC_VCTR16_B512 = 0x1
	// Position of B513 field.
	GTZC_VCTR16_B513_Pos = 0x1
	// Bit mask of B513 field.
	GTZC_VCTR16_B513_Msk = 0x2
	// Bit B513.
	GTZC_VCTR16_B513 = 0x2
	// Position of B514 field.
	GTZC_VCTR16_B514_Pos = 0x2
	// Bit mask of B514 field.
	GTZC_VCTR16_B514_Msk = 0x4
	// Bit B514.
	GTZC_VCTR16_B514 = 0x4
	// Position of B515 field.
	GTZC_VCTR16_B515_Pos = 0x3
	// Bit mask of B515 field.
	GTZC_VCTR16_B515_Msk = 0x8
	// Bit B515.
	GTZC_VCTR16_B515 = 0x8
	// Position of B516 field.
	GTZC_VCTR16_B516_Pos = 0x4
	// Bit mask of B516 field.
	GTZC_VCTR16_B516_Msk = 0x10
	// Bit B516.
	GTZC_VCTR16_B516 = 0x10
	// Position of B517 field.
	GTZC_VCTR16_B517_Pos = 0x5
	// Bit mask of B517 field.
	GTZC_VCTR16_B517_Msk = 0x20
	// Bit B517.
	GTZC_VCTR16_B517 = 0x20
	// Position of B518 field.
	GTZC_VCTR16_B518_Pos = 0x6
	// Bit mask of B518 field.
	GTZC_VCTR16_B518_Msk = 0x40
	// Bit B518.
	GTZC_VCTR16_B518 = 0x40
	// Position of B519 field.
	GTZC_VCTR16_B519_Pos = 0x7
	// Bit mask of B519 field.
	GTZC_VCTR16_B519_Msk = 0x80
	// Bit B519.
	GTZC_VCTR16_B519 = 0x80
	// Position of B520 field.
	GTZC_VCTR16_B520_Pos = 0x8
	// Bit mask of B520 field.
	GTZC_VCTR16_B520_Msk = 0x100
	// Bit B520.
	GTZC_VCTR16_B520 = 0x100
	// Position of B521 field.
	GTZC_VCTR16_B521_Pos = 0x9
	// Bit mask of B521 field.
	GTZC_VCTR16_B521_Msk = 0x200
	// Bit B521.
	GTZC_VCTR16_B521 = 0x200
	// Position of B522 field.
	GTZC_VCTR16_B522_Pos = 0xa
	// Bit mask of B522 field.
	GTZC_VCTR16_B522_Msk = 0x400
	// Bit B522.
	GTZC_VCTR16_B522 = 0x400
	// Position of B523 field.
	GTZC_VCTR16_B523_Pos = 0xb
	// Bit mask of B523 field.
	GTZC_VCTR16_B523_Msk = 0x800
	// Bit B523.
	GTZC_VCTR16_B523 = 0x800
	// Position of B524 field.
	GTZC_VCTR16_B524_Pos = 0xc
	// Bit mask of B524 field.
	GTZC_VCTR16_B524_Msk = 0x1000
	// Bit B524.
	GTZC_VCTR16_B524 = 0x1000
	// Position of B525 field.
	GTZC_VCTR16_B525_Pos = 0xd
	// Bit mask of B525 field.
	GTZC_VCTR16_B525_Msk = 0x2000
	// Bit B525.
	GTZC_VCTR16_B525 = 0x2000
	// Position of B526 field.
	GTZC_VCTR16_B526_Pos = 0xe
	// Bit mask of B526 field.
	GTZC_VCTR16_B526_Msk = 0x4000
	// Bit B526.
	GTZC_VCTR16_B526 = 0x4000
	// Position of B527 field.
	GTZC_VCTR16_B527_Pos = 0xf
	// Bit mask of B527 field.
	GTZC_VCTR16_B527_Msk = 0x8000
	// Bit B527.
	GTZC_VCTR16_B527 = 0x8000
	// Position of B528 field.
	GTZC_VCTR16_B528_Pos = 0x10
	// Bit mask of B528 field.
	GTZC_VCTR16_B528_Msk = 0x10000
	// Bit B528.
	GTZC_VCTR16_B528 = 0x10000
	// Position of B529 field.
	GTZC_VCTR16_B529_Pos = 0x11
	// Bit mask of B529 field.
	GTZC_VCTR16_B529_Msk = 0x20000
	// Bit B529.
	GTZC_VCTR16_B529 = 0x20000
	// Position of B530 field.
	GTZC_VCTR16_B530_Pos = 0x12
	// Bit mask of B530 field.
	GTZC_VCTR16_B530_Msk = 0x40000
	// Bit B530.
	GTZC_VCTR16_B530 = 0x40000
	// Position of B531 field.
	GTZC_VCTR16_B531_Pos = 0x13
	// Bit mask of B531 field.
	GTZC_VCTR16_B531_Msk = 0x80000
	// Bit B531.
	GTZC_VCTR16_B531 = 0x80000
	// Position of B532 field.
	GTZC_VCTR16_B532_Pos = 0x14
	// Bit mask of B532 field.
	GTZC_VCTR16_B532_Msk = 0x100000
	// Bit B532.
	GTZC_VCTR16_B532 = 0x100000
	// Position of B533 field.
	GTZC_VCTR16_B533_Pos = 0x15
	// Bit mask of B533 field.
	GTZC_VCTR16_B533_Msk = 0x200000
	// Bit B533.
	GTZC_VCTR16_B533 = 0x200000
	// Position of B534 field.
	GTZC_VCTR16_B534_Pos = 0x16
	// Bit mask of B534 field.
	GTZC_VCTR16_B534_Msk = 0x400000
	// Bit B534.
	GTZC_VCTR16_B534 = 0x400000
	// Position of B535 field.
	GTZC_VCTR16_B535_Pos = 0x17
	// Bit mask of B535 field.
	GTZC_VCTR16_B535_Msk = 0x800000
	// Bit B535.
	GTZC_VCTR16_B535 = 0x800000
	// Position of B536 field.
	GTZC_VCTR16_B536_Pos = 0x18
	// Bit mask of B536 field.
	GTZC_VCTR16_B536_Msk = 0x1000000
	// Bit B536.
	GTZC_VCTR16_B536 = 0x1000000
	// Position of B537 field.
	GTZC_VCTR16_B537_Pos = 0x19
	// Bit mask of B537 field.
	GTZC_VCTR16_B537_Msk = 0x2000000
	// Bit B537.
	GTZC_VCTR16_B537 = 0x2000000
	// Position of B538 field.
	GTZC_VCTR16_B538_Pos = 0x1a
	// Bit mask of B538 field.
	GTZC_VCTR16_B538_Msk = 0x4000000
	// Bit B538.
	GTZC_VCTR16_B538 = 0x4000000
	// Position of B539 field.
	GTZC_VCTR16_B539_Pos = 0x1b
	// Bit mask of B539 field.
	GTZC_VCTR16_B539_Msk = 0x8000000
	// Bit B539.
	GTZC_VCTR16_B539 = 0x8000000
	// Position of B540 field.
	GTZC_VCTR16_B540_Pos = 0x1c
	// Bit mask of B540 field.
	GTZC_VCTR16_B540_Msk = 0x10000000
	// Bit B540.
	GTZC_VCTR16_B540 = 0x10000000
	// Position of B541 field.
	GTZC_VCTR16_B541_Pos = 0x1d
	// Bit mask of B541 field.
	GTZC_VCTR16_B541_Msk = 0x20000000
	// Bit B541.
	GTZC_VCTR16_B541 = 0x20000000
	// Position of B542 field.
	GTZC_VCTR16_B542_Pos = 0x1e
	// Bit mask of B542 field.
	GTZC_VCTR16_B542_Msk = 0x40000000
	// Bit B542.
	GTZC_VCTR16_B542 = 0x40000000
	// Position of B543 field.
	GTZC_VCTR16_B543_Pos = 0x1f
	// Bit mask of B543 field.
	GTZC_VCTR16_B543_Msk = 0x80000000
	// Bit B543.
	GTZC_VCTR16_B543 = 0x80000000

	// VCTR17: MPCBBx vector register
	// Position of B544 field.
	GTZC_VCTR17_B544_Pos = 0x0
	// Bit mask of B544 field.
	GTZC_VCTR17_B544_Msk = 0x1
	// Bit B544.
	GTZC_VCTR17_B544 = 0x1
	// Position of B545 field.
	GTZC_VCTR17_B545_Pos = 0x1
	// Bit mask of B545 field.
	GTZC_VCTR17_B545_Msk = 0x2
	// Bit B545.
	GTZC_VCTR17_B545 = 0x2
	// Position of B546 field.
	GTZC_VCTR17_B546_Pos = 0x2
	// Bit mask of B546 field.
	GTZC_VCTR17_B546_Msk = 0x4
	// Bit B546.
	GTZC_VCTR17_B546 = 0x4
	// Position of B547 field.
	GTZC_VCTR17_B547_Pos = 0x3
	// Bit mask of B547 field.
	GTZC_VCTR17_B547_Msk = 0x8
	// Bit B547.
	GTZC_VCTR17_B547 = 0x8
	// Position of B548 field.
	GTZC_VCTR17_B548_Pos = 0x4
	// Bit mask of B548 field.
	GTZC_VCTR17_B548_Msk = 0x10
	// Bit B548.
	GTZC_VCTR17_B548 = 0x10
	// Position of B549 field.
	GTZC_VCTR17_B549_Pos = 0x5
	// Bit mask of B549 field.
	GTZC_VCTR17_B549_Msk = 0x20
	// Bit B549.
	GTZC_VCTR17_B549 = 0x20
	// Position of B550 field.
	GTZC_VCTR17_B550_Pos = 0x6
	// Bit mask of B550 field.
	GTZC_VCTR17_B550_Msk = 0x40
	// Bit B550.
	GTZC_VCTR17_B550 = 0x40
	// Position of B551 field.
	GTZC_VCTR17_B551_Pos = 0x7
	// Bit mask of B551 field.
	GTZC_VCTR17_B551_Msk = 0x80
	// Bit B551.
	GTZC_VCTR17_B551 = 0x80
	// Position of B552 field.
	GTZC_VCTR17_B552_Pos = 0x8
	// Bit mask of B552 field.
	GTZC_VCTR17_B552_Msk = 0x100
	// Bit B552.
	GTZC_VCTR17_B552 = 0x100
	// Position of B553 field.
	GTZC_VCTR17_B553_Pos = 0x9
	// Bit mask of B553 field.
	GTZC_VCTR17_B553_Msk = 0x200
	// Bit B553.
	GTZC_VCTR17_B553 = 0x200
	// Position of B554 field.
	GTZC_VCTR17_B554_Pos = 0xa
	// Bit mask of B554 field.
	GTZC_VCTR17_B554_Msk = 0x400
	// Bit B554.
	GTZC_VCTR17_B554 = 0x400
	// Position of B555 field.
	GTZC_VCTR17_B555_Pos = 0xb
	// Bit mask of B555 field.
	GTZC_VCTR17_B555_Msk = 0x800
	// Bit B555.
	GTZC_VCTR17_B555 = 0x800
	// Position of B556 field.
	GTZC_VCTR17_B556_Pos = 0xc
	// Bit mask of B556 field.
	GTZC_VCTR17_B556_Msk = 0x1000
	// Bit B556.
	GTZC_VCTR17_B556 = 0x1000
	// Position of B557 field.
	GTZC_VCTR17_B557_Pos = 0xd
	// Bit mask of B557 field.
	GTZC_VCTR17_B557_Msk = 0x2000
	// Bit B557.
	GTZC_VCTR17_B557 = 0x2000
	// Position of B558 field.
	GTZC_VCTR17_B558_Pos = 0xe
	// Bit mask of B558 field.
	GTZC_VCTR17_B558_Msk = 0x4000
	// Bit B558.
	GTZC_VCTR17_B558 = 0x4000
	// Position of B559 field.
	GTZC_VCTR17_B559_Pos = 0xf
	// Bit mask of B559 field.
	GTZC_VCTR17_B559_Msk = 0x8000
	// Bit B559.
	GTZC_VCTR17_B559 = 0x8000
	// Position of B560 field.
	GTZC_VCTR17_B560_Pos = 0x10
	// Bit mask of B560 field.
	GTZC_VCTR17_B560_Msk = 0x10000
	// Bit B560.
	GTZC_VCTR17_B560 = 0x10000
	// Position of B561 field.
	GTZC_VCTR17_B561_Pos = 0x11
	// Bit mask of B561 field.
	GTZC_VCTR17_B561_Msk = 0x20000
	// Bit B561.
	GTZC_VCTR17_B561 = 0x20000
	// Position of B562 field.
	GTZC_VCTR17_B562_Pos = 0x12
	// Bit mask of B562 field.
	GTZC_VCTR17_B562_Msk = 0x40000
	// Bit B562.
	GTZC_VCTR17_B562 = 0x40000
	// Position of B563 field.
	GTZC_VCTR17_B563_Pos = 0x13
	// Bit mask of B563 field.
	GTZC_VCTR17_B563_Msk = 0x80000
	// Bit B563.
	GTZC_VCTR17_B563 = 0x80000
	// Position of B564 field.
	GTZC_VCTR17_B564_Pos = 0x14
	// Bit mask of B564 field.
	GTZC_VCTR17_B564_Msk = 0x100000
	// Bit B564.
	GTZC_VCTR17_B564 = 0x100000
	// Position of B565 field.
	GTZC_VCTR17_B565_Pos = 0x15
	// Bit mask of B565 field.
	GTZC_VCTR17_B565_Msk = 0x200000
	// Bit B565.
	GTZC_VCTR17_B565 = 0x200000
	// Position of B566 field.
	GTZC_VCTR17_B566_Pos = 0x16
	// Bit mask of B566 field.
	GTZC_VCTR17_B566_Msk = 0x400000
	// Bit B566.
	GTZC_VCTR17_B566 = 0x400000
	// Position of B567 field.
	GTZC_VCTR17_B567_Pos = 0x17
	// Bit mask of B567 field.
	GTZC_VCTR17_B567_Msk = 0x800000
	// Bit B567.
	GTZC_VCTR17_B567 = 0x800000
	// Position of B568 field.
	GTZC_VCTR17_B568_Pos = 0x18
	// Bit mask of B568 field.
	GTZC_VCTR17_B568_Msk = 0x1000000
	// Bit B568.
	GTZC_VCTR17_B568 = 0x1000000
	// Position of B569 field.
	GTZC_VCTR17_B569_Pos = 0x19
	// Bit mask of B569 field.
	GTZC_VCTR17_B569_Msk = 0x2000000
	// Bit B569.
	GTZC_VCTR17_B569 = 0x2000000
	// Position of B570 field.
	GTZC_VCTR17_B570_Pos = 0x1a
	// Bit mask of B570 field.
	GTZC_VCTR17_B570_Msk = 0x4000000
	// Bit B570.
	GTZC_VCTR17_B570 = 0x4000000
	// Position of B571 field.
	GTZC_VCTR17_B571_Pos = 0x1b
	// Bit mask of B571 field.
	GTZC_VCTR17_B571_Msk = 0x8000000
	// Bit B571.
	GTZC_VCTR17_B571 = 0x8000000
	// Position of B572 field.
	GTZC_VCTR17_B572_Pos = 0x1c
	// Bit mask of B572 field.
	GTZC_VCTR17_B572_Msk = 0x10000000
	// Bit B572.
	GTZC_VCTR17_B572 = 0x10000000
	// Position of B573 field.
	GTZC_VCTR17_B573_Pos = 0x1d
	// Bit mask of B573 field.
	GTZC_VCTR17_B573_Msk = 0x20000000
	// Bit B573.
	GTZC_VCTR17_B573 = 0x20000000
	// Position of B574 field.
	GTZC_VCTR17_B574_Pos = 0x1e
	// Bit mask of B574 field.
	GTZC_VCTR17_B574_Msk = 0x40000000
	// Bit B574.
	GTZC_VCTR17_B574 = 0x40000000
	// Position of B575 field.
	GTZC_VCTR17_B575_Pos = 0x1f
	// Bit mask of B575 field.
	GTZC_VCTR17_B575_Msk = 0x80000000
	// Bit B575.
	GTZC_VCTR17_B575 = 0x80000000

	// VCTR18: MPCBBx vector register
	// Position of B576 field.
	GTZC_VCTR18_B576_Pos = 0x0
	// Bit mask of B576 field.
	GTZC_VCTR18_B576_Msk = 0x1
	// Bit B576.
	GTZC_VCTR18_B576 = 0x1
	// Position of B577 field.
	GTZC_VCTR18_B577_Pos = 0x1
	// Bit mask of B577 field.
	GTZC_VCTR18_B577_Msk = 0x2
	// Bit B577.
	GTZC_VCTR18_B577 = 0x2
	// Position of B578 field.
	GTZC_VCTR18_B578_Pos = 0x2
	// Bit mask of B578 field.
	GTZC_VCTR18_B578_Msk = 0x4
	// Bit B578.
	GTZC_VCTR18_B578 = 0x4
	// Position of B579 field.
	GTZC_VCTR18_B579_Pos = 0x3
	// Bit mask of B579 field.
	GTZC_VCTR18_B579_Msk = 0x8
	// Bit B579.
	GTZC_VCTR18_B579 = 0x8
	// Position of B580 field.
	GTZC_VCTR18_B580_Pos = 0x4
	// Bit mask of B580 field.
	GTZC_VCTR18_B580_Msk = 0x10
	// Bit B580.
	GTZC_VCTR18_B580 = 0x10
	// Position of B581 field.
	GTZC_VCTR18_B581_Pos = 0x5
	// Bit mask of B581 field.
	GTZC_VCTR18_B581_Msk = 0x20
	// Bit B581.
	GTZC_VCTR18_B581 = 0x20
	// Position of B582 field.
	GTZC_VCTR18_B582_Pos = 0x6
	// Bit mask of B582 field.
	GTZC_VCTR18_B582_Msk = 0x40
	// Bit B582.
	GTZC_VCTR18_B582 = 0x40
	// Position of B583 field.
	GTZC_VCTR18_B583_Pos = 0x7
	// Bit mask of B583 field.
	GTZC_VCTR18_B583_Msk = 0x80
	// Bit B583.
	GTZC_VCTR18_B583 = 0x80
	// Position of B584 field.
	GTZC_VCTR18_B584_Pos = 0x8
	// Bit mask of B584 field.
	GTZC_VCTR18_B584_Msk = 0x100
	// Bit B584.
	GTZC_VCTR18_B584 = 0x100
	// Position of B585 field.
	GTZC_VCTR18_B585_Pos = 0x9
	// Bit mask of B585 field.
	GTZC_VCTR18_B585_Msk = 0x200
	// Bit B585.
	GTZC_VCTR18_B585 = 0x200
	// Position of B586 field.
	GTZC_VCTR18_B586_Pos = 0xa
	// Bit mask of B586 field.
	GTZC_VCTR18_B586_Msk = 0x400
	// Bit B586.
	GTZC_VCTR18_B586 = 0x400
	// Position of B587 field.
	GTZC_VCTR18_B587_Pos = 0xb
	// Bit mask of B587 field.
	GTZC_VCTR18_B587_Msk = 0x800
	// Bit B587.
	GTZC_VCTR18_B587 = 0x800
	// Position of B588 field.
	GTZC_VCTR18_B588_Pos = 0xc
	// Bit mask of B588 field.
	GTZC_VCTR18_B588_Msk = 0x1000
	// Bit B588.
	GTZC_VCTR18_B588 = 0x1000
	// Position of B589 field.
	GTZC_VCTR18_B589_Pos = 0xd
	// Bit mask of B589 field.
	GTZC_VCTR18_B589_Msk = 0x2000
	// Bit B589.
	GTZC_VCTR18_B589 = 0x2000
	// Position of B590 field.
	GTZC_VCTR18_B590_Pos = 0xe
	// Bit mask of B590 field.
	GTZC_VCTR18_B590_Msk = 0x4000
	// Bit B590.
	GTZC_VCTR18_B590 = 0x4000
	// Position of B591 field.
	GTZC_VCTR18_B591_Pos = 0xf
	// Bit mask of B591 field.
	GTZC_VCTR18_B591_Msk = 0x8000
	// Bit B591.
	GTZC_VCTR18_B591 = 0x8000
	// Position of B592 field.
	GTZC_VCTR18_B592_Pos = 0x10
	// Bit mask of B592 field.
	GTZC_VCTR18_B592_Msk = 0x10000
	// Bit B592.
	GTZC_VCTR18_B592 = 0x10000
	// Position of B593 field.
	GTZC_VCTR18_B593_Pos = 0x11
	// Bit mask of B593 field.
	GTZC_VCTR18_B593_Msk = 0x20000
	// Bit B593.
	GTZC_VCTR18_B593 = 0x20000
	// Position of B594 field.
	GTZC_VCTR18_B594_Pos = 0x12
	// Bit mask of B594 field.
	GTZC_VCTR18_B594_Msk = 0x40000
	// Bit B594.
	GTZC_VCTR18_B594 = 0x40000
	// Position of B595 field.
	GTZC_VCTR18_B595_Pos = 0x13
	// Bit mask of B595 field.
	GTZC_VCTR18_B595_Msk = 0x80000
	// Bit B595.
	GTZC_VCTR18_B595 = 0x80000
	// Position of B596 field.
	GTZC_VCTR18_B596_Pos = 0x14
	// Bit mask of B596 field.
	GTZC_VCTR18_B596_Msk = 0x100000
	// Bit B596.
	GTZC_VCTR18_B596 = 0x100000
	// Position of B597 field.
	GTZC_VCTR18_B597_Pos = 0x15
	// Bit mask of B597 field.
	GTZC_VCTR18_B597_Msk = 0x200000
	// Bit B597.
	GTZC_VCTR18_B597 = 0x200000
	// Position of B598 field.
	GTZC_VCTR18_B598_Pos = 0x16
	// Bit mask of B598 field.
	GTZC_VCTR18_B598_Msk = 0x400000
	// Bit B598.
	GTZC_VCTR18_B598 = 0x400000
	// Position of B599 field.
	GTZC_VCTR18_B599_Pos = 0x17
	// Bit mask of B599 field.
	GTZC_VCTR18_B599_Msk = 0x800000
	// Bit B599.
	GTZC_VCTR18_B599 = 0x800000
	// Position of B600 field.
	GTZC_VCTR18_B600_Pos = 0x18
	// Bit mask of B600 field.
	GTZC_VCTR18_B600_Msk = 0x1000000
	// Bit B600.
	GTZC_VCTR18_B600 = 0x1000000
	// Position of B601 field.
	GTZC_VCTR18_B601_Pos = 0x19
	// Bit mask of B601 field.
	GTZC_VCTR18_B601_Msk = 0x2000000
	// Bit B601.
	GTZC_VCTR18_B601 = 0x2000000
	// Position of B602 field.
	GTZC_VCTR18_B602_Pos = 0x1a
	// Bit mask of B602 field.
	GTZC_VCTR18_B602_Msk = 0x4000000
	// Bit B602.
	GTZC_VCTR18_B602 = 0x4000000
	// Position of B603 field.
	GTZC_VCTR18_B603_Pos = 0x1b
	// Bit mask of B603 field.
	GTZC_VCTR18_B603_Msk = 0x8000000
	// Bit B603.
	GTZC_VCTR18_B603 = 0x8000000
	// Position of B604 field.
	GTZC_VCTR18_B604_Pos = 0x1c
	// Bit mask of B604 field.
	GTZC_VCTR18_B604_Msk = 0x10000000
	// Bit B604.
	GTZC_VCTR18_B604 = 0x10000000
	// Position of B605 field.
	GTZC_VCTR18_B605_Pos = 0x1d
	// Bit mask of B605 field.
	GTZC_VCTR18_B605_Msk = 0x20000000
	// Bit B605.
	GTZC_VCTR18_B605 = 0x20000000
	// Position of B606 field.
	GTZC_VCTR18_B606_Pos = 0x1e
	// Bit mask of B606 field.
	GTZC_VCTR18_B606_Msk = 0x40000000
	// Bit B606.
	GTZC_VCTR18_B606 = 0x40000000
	// Position of B607 field.
	GTZC_VCTR18_B607_Pos = 0x1f
	// Bit mask of B607 field.
	GTZC_VCTR18_B607_Msk = 0x80000000
	// Bit B607.
	GTZC_VCTR18_B607 = 0x80000000

	// VCTR19: MPCBBx vector register
	// Position of B608 field.
	GTZC_VCTR19_B608_Pos = 0x0
	// Bit mask of B608 field.
	GTZC_VCTR19_B608_Msk = 0x1
	// Bit B608.
	GTZC_VCTR19_B608 = 0x1
	// Position of B609 field.
	GTZC_VCTR19_B609_Pos = 0x1
	// Bit mask of B609 field.
	GTZC_VCTR19_B609_Msk = 0x2
	// Bit B609.
	GTZC_VCTR19_B609 = 0x2
	// Position of B610 field.
	GTZC_VCTR19_B610_Pos = 0x2
	// Bit mask of B610 field.
	GTZC_VCTR19_B610_Msk = 0x4
	// Bit B610.
	GTZC_VCTR19_B610 = 0x4
	// Position of B611 field.
	GTZC_VCTR19_B611_Pos = 0x3
	// Bit mask of B611 field.
	GTZC_VCTR19_B611_Msk = 0x8
	// Bit B611.
	GTZC_VCTR19_B611 = 0x8
	// Position of B612 field.
	GTZC_VCTR19_B612_Pos = 0x4
	// Bit mask of B612 field.
	GTZC_VCTR19_B612_Msk = 0x10
	// Bit B612.
	GTZC_VCTR19_B612 = 0x10
	// Position of B613 field.
	GTZC_VCTR19_B613_Pos = 0x5
	// Bit mask of B613 field.
	GTZC_VCTR19_B613_Msk = 0x20
	// Bit B613.
	GTZC_VCTR19_B613 = 0x20
	// Position of B614 field.
	GTZC_VCTR19_B614_Pos = 0x6
	// Bit mask of B614 field.
	GTZC_VCTR19_B614_Msk = 0x40
	// Bit B614.
	GTZC_VCTR19_B614 = 0x40
	// Position of B615 field.
	GTZC_VCTR19_B615_Pos = 0x7
	// Bit mask of B615 field.
	GTZC_VCTR19_B615_Msk = 0x80
	// Bit B615.
	GTZC_VCTR19_B615 = 0x80
	// Position of B616 field.
	GTZC_VCTR19_B616_Pos = 0x8
	// Bit mask of B616 field.
	GTZC_VCTR19_B616_Msk = 0x100
	// Bit B616.
	GTZC_VCTR19_B616 = 0x100
	// Position of B617 field.
	GTZC_VCTR19_B617_Pos = 0x9
	// Bit mask of B617 field.
	GTZC_VCTR19_B617_Msk = 0x200
	// Bit B617.
	GTZC_VCTR19_B617 = 0x200
	// Position of B618 field.
	GTZC_VCTR19_B618_Pos = 0xa
	// Bit mask of B618 field.
	GTZC_VCTR19_B618_Msk = 0x400
	// Bit B618.
	GTZC_VCTR19_B618 = 0x400
	// Position of B619 field.
	GTZC_VCTR19_B619_Pos = 0xb
	// Bit mask of B619 field.
	GTZC_VCTR19_B619_Msk = 0x800
	// Bit B619.
	GTZC_VCTR19_B619 = 0x800
	// Position of B620 field.
	GTZC_VCTR19_B620_Pos = 0xc
	// Bit mask of B620 field.
	GTZC_VCTR19_B620_Msk = 0x1000
	// Bit B620.
	GTZC_VCTR19_B620 = 0x1000
	// Position of B621 field.
	GTZC_VCTR19_B621_Pos = 0xd
	// Bit mask of B621 field.
	GTZC_VCTR19_B621_Msk = 0x2000
	// Bit B621.
	GTZC_VCTR19_B621 = 0x2000
	// Position of B622 field.
	GTZC_VCTR19_B622_Pos = 0xe
	// Bit mask of B622 field.
	GTZC_VCTR19_B622_Msk = 0x4000
	// Bit B622.
	GTZC_VCTR19_B622 = 0x4000
	// Position of B623 field.
	GTZC_VCTR19_B623_Pos = 0xf
	// Bit mask of B623 field.
	GTZC_VCTR19_B623_Msk = 0x8000
	// Bit B623.
	GTZC_VCTR19_B623 = 0x8000
	// Position of B624 field.
	GTZC_VCTR19_B624_Pos = 0x10
	// Bit mask of B624 field.
	GTZC_VCTR19_B624_Msk = 0x10000
	// Bit B624.
	GTZC_VCTR19_B624 = 0x10000
	// Position of B625 field.
	GTZC_VCTR19_B625_Pos = 0x11
	// Bit mask of B625 field.
	GTZC_VCTR19_B625_Msk = 0x20000
	// Bit B625.
	GTZC_VCTR19_B625 = 0x20000
	// Position of B626 field.
	GTZC_VCTR19_B626_Pos = 0x12
	// Bit mask of B626 field.
	GTZC_VCTR19_B626_Msk = 0x40000
	// Bit B626.
	GTZC_VCTR19_B626 = 0x40000
	// Position of B627 field.
	GTZC_VCTR19_B627_Pos = 0x13
	// Bit mask of B627 field.
	GTZC_VCTR19_B627_Msk = 0x80000
	// Bit B627.
	GTZC_VCTR19_B627 = 0x80000
	// Position of B628 field.
	GTZC_VCTR19_B628_Pos = 0x14
	// Bit mask of B628 field.
	GTZC_VCTR19_B628_Msk = 0x100000
	// Bit B628.
	GTZC_VCTR19_B628 = 0x100000
	// Position of B629 field.
	GTZC_VCTR19_B629_Pos = 0x15
	// Bit mask of B629 field.
	GTZC_VCTR19_B629_Msk = 0x200000
	// Bit B629.
	GTZC_VCTR19_B629 = 0x200000
	// Position of B630 field.
	GTZC_VCTR19_B630_Pos = 0x16
	// Bit mask of B630 field.
	GTZC_VCTR19_B630_Msk = 0x400000
	// Bit B630.
	GTZC_VCTR19_B630 = 0x400000
	// Position of B631 field.
	GTZC_VCTR19_B631_Pos = 0x17
	// Bit mask of B631 field.
	GTZC_VCTR19_B631_Msk = 0x800000
	// Bit B631.
	GTZC_VCTR19_B631 = 0x800000
	// Position of B632 field.
	GTZC_VCTR19_B632_Pos = 0x18
	// Bit mask of B632 field.
	GTZC_VCTR19_B632_Msk = 0x1000000
	// Bit B632.
	GTZC_VCTR19_B632 = 0x1000000
	// Position of B633 field.
	GTZC_VCTR19_B633_Pos = 0x19
	// Bit mask of B633 field.
	GTZC_VCTR19_B633_Msk = 0x2000000
	// Bit B633.
	GTZC_VCTR19_B633 = 0x2000000
	// Position of B634 field.
	GTZC_VCTR19_B634_Pos = 0x1a
	// Bit mask of B634 field.
	GTZC_VCTR19_B634_Msk = 0x4000000
	// Bit B634.
	GTZC_VCTR19_B634 = 0x4000000
	// Position of B635 field.
	GTZC_VCTR19_B635_Pos = 0x1b
	// Bit mask of B635 field.
	GTZC_VCTR19_B635_Msk = 0x8000000
	// Bit B635.
	GTZC_VCTR19_B635 = 0x8000000
	// Position of B636 field.
	GTZC_VCTR19_B636_Pos = 0x1c
	// Bit mask of B636 field.
	GTZC_VCTR19_B636_Msk = 0x10000000
	// Bit B636.
	GTZC_VCTR19_B636 = 0x10000000
	// Position of B637 field.
	GTZC_VCTR19_B637_Pos = 0x1d
	// Bit mask of B637 field.
	GTZC_VCTR19_B637_Msk = 0x20000000
	// Bit B637.
	GTZC_VCTR19_B637 = 0x20000000
	// Position of B638 field.
	GTZC_VCTR19_B638_Pos = 0x1e
	// Bit mask of B638 field.
	GTZC_VCTR19_B638_Msk = 0x40000000
	// Bit B638.
	GTZC_VCTR19_B638 = 0x40000000
	// Position of B639 field.
	GTZC_VCTR19_B639_Pos = 0x1f
	// Bit mask of B639 field.
	GTZC_VCTR19_B639_Msk = 0x80000000
	// Bit B639.
	GTZC_VCTR19_B639 = 0x80000000

	// VCTR20: MPCBBx vector register
	// Position of B640 field.
	GTZC_VCTR20_B640_Pos = 0x0
	// Bit mask of B640 field.
	GTZC_VCTR20_B640_Msk = 0x1
	// Bit B640.
	GTZC_VCTR20_B640 = 0x1
	// Position of B641 field.
	GTZC_VCTR20_B641_Pos = 0x1
	// Bit mask of B641 field.
	GTZC_VCTR20_B641_Msk = 0x2
	// Bit B641.
	GTZC_VCTR20_B641 = 0x2
	// Position of B642 field.
	GTZC_VCTR20_B642_Pos = 0x2
	// Bit mask of B642 field.
	GTZC_VCTR20_B642_Msk = 0x4
	// Bit B642.
	GTZC_VCTR20_B642 = 0x4
	// Position of B643 field.
	GTZC_VCTR20_B643_Pos = 0x3
	// Bit mask of B643 field.
	GTZC_VCTR20_B643_Msk = 0x8
	// Bit B643.
	GTZC_VCTR20_B643 = 0x8
	// Position of B644 field.
	GTZC_VCTR20_B644_Pos = 0x4
	// Bit mask of B644 field.
	GTZC_VCTR20_B644_Msk = 0x10
	// Bit B644.
	GTZC_VCTR20_B644 = 0x10
	// Position of B645 field.
	GTZC_VCTR20_B645_Pos = 0x5
	// Bit mask of B645 field.
	GTZC_VCTR20_B645_Msk = 0x20
	// Bit B645.
	GTZC_VCTR20_B645 = 0x20
	// Position of B646 field.
	GTZC_VCTR20_B646_Pos = 0x6
	// Bit mask of B646 field.
	GTZC_VCTR20_B646_Msk = 0x40
	// Bit B646.
	GTZC_VCTR20_B646 = 0x40
	// Position of B647 field.
	GTZC_VCTR20_B647_Pos = 0x7
	// Bit mask of B647 field.
	GTZC_VCTR20_B647_Msk = 0x80
	// Bit B647.
	GTZC_VCTR20_B647 = 0x80
	// Position of B648 field.
	GTZC_VCTR20_B648_Pos = 0x8
	// Bit mask of B648 field.
	GTZC_VCTR20_B648_Msk = 0x100
	// Bit B648.
	GTZC_VCTR20_B648 = 0x100
	// Position of B649 field.
	GTZC_VCTR20_B649_Pos = 0x9
	// Bit mask of B649 field.
	GTZC_VCTR20_B649_Msk = 0x200
	// Bit B649.
	GTZC_VCTR20_B649 = 0x200
	// Position of B650 field.
	GTZC_VCTR20_B650_Pos = 0xa
	// Bit mask of B650 field.
	GTZC_VCTR20_B650_Msk = 0x400
	// Bit B650.
	GTZC_VCTR20_B650 = 0x400
	// Position of B651 field.
	GTZC_VCTR20_B651_Pos = 0xb
	// Bit mask of B651 field.
	GTZC_VCTR20_B651_Msk = 0x800
	// Bit B651.
	GTZC_VCTR20_B651 = 0x800
	// Position of B652 field.
	GTZC_VCTR20_B652_Pos = 0xc
	// Bit mask of B652 field.
	GTZC_VCTR20_B652_Msk = 0x1000
	// Bit B652.
	GTZC_VCTR20_B652 = 0x1000
	// Position of B653 field.
	GTZC_VCTR20_B653_Pos = 0xd
	// Bit mask of B653 field.
	GTZC_VCTR20_B653_Msk = 0x2000
	// Bit B653.
	GTZC_VCTR20_B653 = 0x2000
	// Position of B654 field.
	GTZC_VCTR20_B654_Pos = 0xe
	// Bit mask of B654 field.
	GTZC_VCTR20_B654_Msk = 0x4000
	// Bit B654.
	GTZC_VCTR20_B654 = 0x4000
	// Position of B655 field.
	GTZC_VCTR20_B655_Pos = 0xf
	// Bit mask of B655 field.
	GTZC_VCTR20_B655_Msk = 0x8000
	// Bit B655.
	GTZC_VCTR20_B655 = 0x8000
	// Position of B656 field.
	GTZC_VCTR20_B656_Pos = 0x10
	// Bit mask of B656 field.
	GTZC_VCTR20_B656_Msk = 0x10000
	// Bit B656.
	GTZC_VCTR20_B656 = 0x10000
	// Position of B657 field.
	GTZC_VCTR20_B657_Pos = 0x11
	// Bit mask of B657 field.
	GTZC_VCTR20_B657_Msk = 0x20000
	// Bit B657.
	GTZC_VCTR20_B657 = 0x20000
	// Position of B658 field.
	GTZC_VCTR20_B658_Pos = 0x12
	// Bit mask of B658 field.
	GTZC_VCTR20_B658_Msk = 0x40000
	// Bit B658.
	GTZC_VCTR20_B658 = 0x40000
	// Position of B659 field.
	GTZC_VCTR20_B659_Pos = 0x13
	// Bit mask of B659 field.
	GTZC_VCTR20_B659_Msk = 0x80000
	// Bit B659.
	GTZC_VCTR20_B659 = 0x80000
	// Position of B660 field.
	GTZC_VCTR20_B660_Pos = 0x14
	// Bit mask of B660 field.
	GTZC_VCTR20_B660_Msk = 0x100000
	// Bit B660.
	GTZC_VCTR20_B660 = 0x100000
	// Position of B661 field.
	GTZC_VCTR20_B661_Pos = 0x15
	// Bit mask of B661 field.
	GTZC_VCTR20_B661_Msk = 0x200000
	// Bit B661.
	GTZC_VCTR20_B661 = 0x200000
	// Position of B662 field.
	GTZC_VCTR20_B662_Pos = 0x16
	// Bit mask of B662 field.
	GTZC_VCTR20_B662_Msk = 0x400000
	// Bit B662.
	GTZC_VCTR20_B662 = 0x400000
	// Position of B663 field.
	GTZC_VCTR20_B663_Pos = 0x17
	// Bit mask of B663 field.
	GTZC_VCTR20_B663_Msk = 0x800000
	// Bit B663.
	GTZC_VCTR20_B663 = 0x800000
	// Position of B664 field.
	GTZC_VCTR20_B664_Pos = 0x18
	// Bit mask of B664 field.
	GTZC_VCTR20_B664_Msk = 0x1000000
	// Bit B664.
	GTZC_VCTR20_B664 = 0x1000000
	// Position of B665 field.
	GTZC_VCTR20_B665_Pos = 0x19
	// Bit mask of B665 field.
	GTZC_VCTR20_B665_Msk = 0x2000000
	// Bit B665.
	GTZC_VCTR20_B665 = 0x2000000
	// Position of B666 field.
	GTZC_VCTR20_B666_Pos = 0x1a
	// Bit mask of B666 field.
	GTZC_VCTR20_B666_Msk = 0x4000000
	// Bit B666.
	GTZC_VCTR20_B666 = 0x4000000
	// Position of B667 field.
	GTZC_VCTR20_B667_Pos = 0x1b
	// Bit mask of B667 field.
	GTZC_VCTR20_B667_Msk = 0x8000000
	// Bit B667.
	GTZC_VCTR20_B667 = 0x8000000
	// Position of B668 field.
	GTZC_VCTR20_B668_Pos = 0x1c
	// Bit mask of B668 field.
	GTZC_VCTR20_B668_Msk = 0x10000000
	// Bit B668.
	GTZC_VCTR20_B668 = 0x10000000
	// Position of B669 field.
	GTZC_VCTR20_B669_Pos = 0x1d
	// Bit mask of B669 field.
	GTZC_VCTR20_B669_Msk = 0x20000000
	// Bit B669.
	GTZC_VCTR20_B669 = 0x20000000
	// Position of B670 field.
	GTZC_VCTR20_B670_Pos = 0x1e
	// Bit mask of B670 field.
	GTZC_VCTR20_B670_Msk = 0x40000000
	// Bit B670.
	GTZC_VCTR20_B670 = 0x40000000
	// Position of B671 field.
	GTZC_VCTR20_B671_Pos = 0x1f
	// Bit mask of B671 field.
	GTZC_VCTR20_B671_Msk = 0x80000000
	// Bit B671.
	GTZC_VCTR20_B671 = 0x80000000

	// VCTR21: MPCBBx vector register
	// Position of B672 field.
	GTZC_VCTR21_B672_Pos = 0x0
	// Bit mask of B672 field.
	GTZC_VCTR21_B672_Msk = 0x1
	// Bit B672.
	GTZC_VCTR21_B672 = 0x1
	// Position of B673 field.
	GTZC_VCTR21_B673_Pos = 0x1
	// Bit mask of B673 field.
	GTZC_VCTR21_B673_Msk = 0x2
	// Bit B673.
	GTZC_VCTR21_B673 = 0x2
	// Position of B674 field.
	GTZC_VCTR21_B674_Pos = 0x2
	// Bit mask of B674 field.
	GTZC_VCTR21_B674_Msk = 0x4
	// Bit B674.
	GTZC_VCTR21_B674 = 0x4
	// Position of B675 field.
	GTZC_VCTR21_B675_Pos = 0x3
	// Bit mask of B675 field.
	GTZC_VCTR21_B675_Msk = 0x8
	// Bit B675.
	GTZC_VCTR21_B675 = 0x8
	// Position of B676 field.
	GTZC_VCTR21_B676_Pos = 0x4
	// Bit mask of B676 field.
	GTZC_VCTR21_B676_Msk = 0x10
	// Bit B676.
	GTZC_VCTR21_B676 = 0x10
	// Position of B677 field.
	GTZC_VCTR21_B677_Pos = 0x5
	// Bit mask of B677 field.
	GTZC_VCTR21_B677_Msk = 0x20
	// Bit B677.
	GTZC_VCTR21_B677 = 0x20
	// Position of B678 field.
	GTZC_VCTR21_B678_Pos = 0x6
	// Bit mask of B678 field.
	GTZC_VCTR21_B678_Msk = 0x40
	// Bit B678.
	GTZC_VCTR21_B678 = 0x40
	// Position of B679 field.
	GTZC_VCTR21_B679_Pos = 0x7
	// Bit mask of B679 field.
	GTZC_VCTR21_B679_Msk = 0x80
	// Bit B679.
	GTZC_VCTR21_B679 = 0x80
	// Position of B680 field.
	GTZC_VCTR21_B680_Pos = 0x8
	// Bit mask of B680 field.
	GTZC_VCTR21_B680_Msk = 0x100
	// Bit B680.
	GTZC_VCTR21_B680 = 0x100
	// Position of B681 field.
	GTZC_VCTR21_B681_Pos = 0x9
	// Bit mask of B681 field.
	GTZC_VCTR21_B681_Msk = 0x200
	// Bit B681.
	GTZC_VCTR21_B681 = 0x200
	// Position of B682 field.
	GTZC_VCTR21_B682_Pos = 0xa
	// Bit mask of B682 field.
	GTZC_VCTR21_B682_Msk = 0x400
	// Bit B682.
	GTZC_VCTR21_B682 = 0x400
	// Position of B683 field.
	GTZC_VCTR21_B683_Pos = 0xb
	// Bit mask of B683 field.
	GTZC_VCTR21_B683_Msk = 0x800
	// Bit B683.
	GTZC_VCTR21_B683 = 0x800
	// Position of B684 field.
	GTZC_VCTR21_B684_Pos = 0xc
	// Bit mask of B684 field.
	GTZC_VCTR21_B684_Msk = 0x1000
	// Bit B684.
	GTZC_VCTR21_B684 = 0x1000
	// Position of B685 field.
	GTZC_VCTR21_B685_Pos = 0xd
	// Bit mask of B685 field.
	GTZC_VCTR21_B685_Msk = 0x2000
	// Bit B685.
	GTZC_VCTR21_B685 = 0x2000
	// Position of B686 field.
	GTZC_VCTR21_B686_Pos = 0xe
	// Bit mask of B686 field.
	GTZC_VCTR21_B686_Msk = 0x4000
	// Bit B686.
	GTZC_VCTR21_B686 = 0x4000
	// Position of B687 field.
	GTZC_VCTR21_B687_Pos = 0xf
	// Bit mask of B687 field.
	GTZC_VCTR21_B687_Msk = 0x8000
	// Bit B687.
	GTZC_VCTR21_B687 = 0x8000
	// Position of B688 field.
	GTZC_VCTR21_B688_Pos = 0x10
	// Bit mask of B688 field.
	GTZC_VCTR21_B688_Msk = 0x10000
	// Bit B688.
	GTZC_VCTR21_B688 = 0x10000
	// Position of B689 field.
	GTZC_VCTR21_B689_Pos = 0x11
	// Bit mask of B689 field.
	GTZC_VCTR21_B689_Msk = 0x20000
	// Bit B689.
	GTZC_VCTR21_B689 = 0x20000
	// Position of B690 field.
	GTZC_VCTR21_B690_Pos = 0x12
	// Bit mask of B690 field.
	GTZC_VCTR21_B690_Msk = 0x40000
	// Bit B690.
	GTZC_VCTR21_B690 = 0x40000
	// Position of B691 field.
	GTZC_VCTR21_B691_Pos = 0x13
	// Bit mask of B691 field.
	GTZC_VCTR21_B691_Msk = 0x80000
	// Bit B691.
	GTZC_VCTR21_B691 = 0x80000
	// Position of B692 field.
	GTZC_VCTR21_B692_Pos = 0x14
	// Bit mask of B692 field.
	GTZC_VCTR21_B692_Msk = 0x100000
	// Bit B692.
	GTZC_VCTR21_B692 = 0x100000
	// Position of B693 field.
	GTZC_VCTR21_B693_Pos = 0x15
	// Bit mask of B693 field.
	GTZC_VCTR21_B693_Msk = 0x200000
	// Bit B693.
	GTZC_VCTR21_B693 = 0x200000
	// Position of B694 field.
	GTZC_VCTR21_B694_Pos = 0x16
	// Bit mask of B694 field.
	GTZC_VCTR21_B694_Msk = 0x400000
	// Bit B694.
	GTZC_VCTR21_B694 = 0x400000
	// Position of B695 field.
	GTZC_VCTR21_B695_Pos = 0x17
	// Bit mask of B695 field.
	GTZC_VCTR21_B695_Msk = 0x800000
	// Bit B695.
	GTZC_VCTR21_B695 = 0x800000
	// Position of B696 field.
	GTZC_VCTR21_B696_Pos = 0x18
	// Bit mask of B696 field.
	GTZC_VCTR21_B696_Msk = 0x1000000
	// Bit B696.
	GTZC_VCTR21_B696 = 0x1000000
	// Position of B697 field.
	GTZC_VCTR21_B697_Pos = 0x19
	// Bit mask of B697 field.
	GTZC_VCTR21_B697_Msk = 0x2000000
	// Bit B697.
	GTZC_VCTR21_B697 = 0x2000000
	// Position of B698 field.
	GTZC_VCTR21_B698_Pos = 0x1a
	// Bit mask of B698 field.
	GTZC_VCTR21_B698_Msk = 0x4000000
	// Bit B698.
	GTZC_VCTR21_B698 = 0x4000000
	// Position of B699 field.
	GTZC_VCTR21_B699_Pos = 0x1b
	// Bit mask of B699 field.
	GTZC_VCTR21_B699_Msk = 0x8000000
	// Bit B699.
	GTZC_VCTR21_B699 = 0x8000000
	// Position of B700 field.
	GTZC_VCTR21_B700_Pos = 0x1c
	// Bit mask of B700 field.
	GTZC_VCTR21_B700_Msk = 0x10000000
	// Bit B700.
	GTZC_VCTR21_B700 = 0x10000000
	// Position of B701 field.
	GTZC_VCTR21_B701_Pos = 0x1d
	// Bit mask of B701 field.
	GTZC_VCTR21_B701_Msk = 0x20000000
	// Bit B701.
	GTZC_VCTR21_B701 = 0x20000000
	// Position of B702 field.
	GTZC_VCTR21_B702_Pos = 0x1e
	// Bit mask of B702 field.
	GTZC_VCTR21_B702_Msk = 0x40000000
	// Bit B702.
	GTZC_VCTR21_B702 = 0x40000000
	// Position of B703 field.
	GTZC_VCTR21_B703_Pos = 0x1f
	// Bit mask of B703 field.
	GTZC_VCTR21_B703_Msk = 0x80000000
	// Bit B703.
	GTZC_VCTR21_B703 = 0x80000000

	// VCTR22: MPCBBx vector register
	// Position of B704 field.
	GTZC_VCTR22_B704_Pos = 0x0
	// Bit mask of B704 field.
	GTZC_VCTR22_B704_Msk = 0x1
	// Bit B704.
	GTZC_VCTR22_B704 = 0x1
	// Position of B705 field.
	GTZC_VCTR22_B705_Pos = 0x1
	// Bit mask of B705 field.
	GTZC_VCTR22_B705_Msk = 0x2
	// Bit B705.
	GTZC_VCTR22_B705 = 0x2
	// Position of B706 field.
	GTZC_VCTR22_B706_Pos = 0x2
	// Bit mask of B706 field.
	GTZC_VCTR22_B706_Msk = 0x4
	// Bit B706.
	GTZC_VCTR22_B706 = 0x4
	// Position of B707 field.
	GTZC_VCTR22_B707_Pos = 0x3
	// Bit mask of B707 field.
	GTZC_VCTR22_B707_Msk = 0x8
	// Bit B707.
	GTZC_VCTR22_B707 = 0x8
	// Position of B708 field.
	GTZC_VCTR22_B708_Pos = 0x4
	// Bit mask of B708 field.
	GTZC_VCTR22_B708_Msk = 0x10
	// Bit B708.
	GTZC_VCTR22_B708 = 0x10
	// Position of B709 field.
	GTZC_VCTR22_B709_Pos = 0x5
	// Bit mask of B709 field.
	GTZC_VCTR22_B709_Msk = 0x20
	// Bit B709.
	GTZC_VCTR22_B709 = 0x20
	// Position of B710 field.
	GTZC_VCTR22_B710_Pos = 0x6
	// Bit mask of B710 field.
	GTZC_VCTR22_B710_Msk = 0x40
	// Bit B710.
	GTZC_VCTR22_B710 = 0x40
	// Position of B711 field.
	GTZC_VCTR22_B711_Pos = 0x7
	// Bit mask of B711 field.
	GTZC_VCTR22_B711_Msk = 0x80
	// Bit B711.
	GTZC_VCTR22_B711 = 0x80
	// Position of B712 field.
	GTZC_VCTR22_B712_Pos = 0x8
	// Bit mask of B712 field.
	GTZC_VCTR22_B712_Msk = 0x100
	// Bit B712.
	GTZC_VCTR22_B712 = 0x100
	// Position of B713 field.
	GTZC_VCTR22_B713_Pos = 0x9
	// Bit mask of B713 field.
	GTZC_VCTR22_B713_Msk = 0x200
	// Bit B713.
	GTZC_VCTR22_B713 = 0x200
	// Position of B714 field.
	GTZC_VCTR22_B714_Pos = 0xa
	// Bit mask of B714 field.
	GTZC_VCTR22_B714_Msk = 0x400
	// Bit B714.
	GTZC_VCTR22_B714 = 0x400
	// Position of B715 field.
	GTZC_VCTR22_B715_Pos = 0xb
	// Bit mask of B715 field.
	GTZC_VCTR22_B715_Msk = 0x800
	// Bit B715.
	GTZC_VCTR22_B715 = 0x800
	// Position of B716 field.
	GTZC_VCTR22_B716_Pos = 0xc
	// Bit mask of B716 field.
	GTZC_VCTR22_B716_Msk = 0x1000
	// Bit B716.
	GTZC_VCTR22_B716 = 0x1000
	// Position of B717 field.
	GTZC_VCTR22_B717_Pos = 0xd
	// Bit mask of B717 field.
	GTZC_VCTR22_B717_Msk = 0x2000
	// Bit B717.
	GTZC_VCTR22_B717 = 0x2000
	// Position of B718 field.
	GTZC_VCTR22_B718_Pos = 0xe
	// Bit mask of B718 field.
	GTZC_VCTR22_B718_Msk = 0x4000
	// Bit B718.
	GTZC_VCTR22_B718 = 0x4000
	// Position of B719 field.
	GTZC_VCTR22_B719_Pos = 0xf
	// Bit mask of B719 field.
	GTZC_VCTR22_B719_Msk = 0x8000
	// Bit B719.
	GTZC_VCTR22_B719 = 0x8000
	// Position of B720 field.
	GTZC_VCTR22_B720_Pos = 0x10
	// Bit mask of B720 field.
	GTZC_VCTR22_B720_Msk = 0x10000
	// Bit B720.
	GTZC_VCTR22_B720 = 0x10000
	// Position of B721 field.
	GTZC_VCTR22_B721_Pos = 0x11
	// Bit mask of B721 field.
	GTZC_VCTR22_B721_Msk = 0x20000
	// Bit B721.
	GTZC_VCTR22_B721 = 0x20000
	// Position of B722 field.
	GTZC_VCTR22_B722_Pos = 0x12
	// Bit mask of B722 field.
	GTZC_VCTR22_B722_Msk = 0x40000
	// Bit B722.
	GTZC_VCTR22_B722 = 0x40000
	// Position of B723 field.
	GTZC_VCTR22_B723_Pos = 0x13
	// Bit mask of B723 field.
	GTZC_VCTR22_B723_Msk = 0x80000
	// Bit B723.
	GTZC_VCTR22_B723 = 0x80000
	// Position of B724 field.
	GTZC_VCTR22_B724_Pos = 0x14
	// Bit mask of B724 field.
	GTZC_VCTR22_B724_Msk = 0x100000
	// Bit B724.
	GTZC_VCTR22_B724 = 0x100000
	// Position of B725 field.
	GTZC_VCTR22_B725_Pos = 0x15
	// Bit mask of B725 field.
	GTZC_VCTR22_B725_Msk = 0x200000
	// Bit B725.
	GTZC_VCTR22_B725 = 0x200000
	// Position of B726 field.
	GTZC_VCTR22_B726_Pos = 0x16
	// Bit mask of B726 field.
	GTZC_VCTR22_B726_Msk = 0x400000
	// Bit B726.
	GTZC_VCTR22_B726 = 0x400000
	// Position of B727 field.
	GTZC_VCTR22_B727_Pos = 0x17
	// Bit mask of B727 field.
	GTZC_VCTR22_B727_Msk = 0x800000
	// Bit B727.
	GTZC_VCTR22_B727 = 0x800000
	// Position of B728 field.
	GTZC_VCTR22_B728_Pos = 0x18
	// Bit mask of B728 field.
	GTZC_VCTR22_B728_Msk = 0x1000000
	// Bit B728.
	GTZC_VCTR22_B728 = 0x1000000
	// Position of B729 field.
	GTZC_VCTR22_B729_Pos = 0x19
	// Bit mask of B729 field.
	GTZC_VCTR22_B729_Msk = 0x2000000
	// Bit B729.
	GTZC_VCTR22_B729 = 0x2000000
	// Position of B730 field.
	GTZC_VCTR22_B730_Pos = 0x1a
	// Bit mask of B730 field.
	GTZC_VCTR22_B730_Msk = 0x4000000
	// Bit B730.
	GTZC_VCTR22_B730 = 0x4000000
	// Position of B731 field.
	GTZC_VCTR22_B731_Pos = 0x1b
	// Bit mask of B731 field.
	GTZC_VCTR22_B731_Msk = 0x8000000
	// Bit B731.
	GTZC_VCTR22_B731 = 0x8000000
	// Position of B732 field.
	GTZC_VCTR22_B732_Pos = 0x1c
	// Bit mask of B732 field.
	GTZC_VCTR22_B732_Msk = 0x10000000
	// Bit B732.
	GTZC_VCTR22_B732 = 0x10000000
	// Position of B733 field.
	GTZC_VCTR22_B733_Pos = 0x1d
	// Bit mask of B733 field.
	GTZC_VCTR22_B733_Msk = 0x20000000
	// Bit B733.
	GTZC_VCTR22_B733 = 0x20000000
	// Position of B734 field.
	GTZC_VCTR22_B734_Pos = 0x1e
	// Bit mask of B734 field.
	GTZC_VCTR22_B734_Msk = 0x40000000
	// Bit B734.
	GTZC_VCTR22_B734 = 0x40000000
	// Position of B735 field.
	GTZC_VCTR22_B735_Pos = 0x1f
	// Bit mask of B735 field.
	GTZC_VCTR22_B735_Msk = 0x80000000
	// Bit B735.
	GTZC_VCTR22_B735 = 0x80000000

	// VCTR23: MPCBBx vector register
	// Position of B736 field.
	GTZC_VCTR23_B736_Pos = 0x0
	// Bit mask of B736 field.
	GTZC_VCTR23_B736_Msk = 0x1
	// Bit B736.
	GTZC_VCTR23_B736 = 0x1
	// Position of B737 field.
	GTZC_VCTR23_B737_Pos = 0x1
	// Bit mask of B737 field.
	GTZC_VCTR23_B737_Msk = 0x2
	// Bit B737.
	GTZC_VCTR23_B737 = 0x2
	// Position of B738 field.
	GTZC_VCTR23_B738_Pos = 0x2
	// Bit mask of B738 field.
	GTZC_VCTR23_B738_Msk = 0x4
	// Bit B738.
	GTZC_VCTR23_B738 = 0x4
	// Position of B739 field.
	GTZC_VCTR23_B739_Pos = 0x3
	// Bit mask of B739 field.
	GTZC_VCTR23_B739_Msk = 0x8
	// Bit B739.
	GTZC_VCTR23_B739 = 0x8
	// Position of B740 field.
	GTZC_VCTR23_B740_Pos = 0x4
	// Bit mask of B740 field.
	GTZC_VCTR23_B740_Msk = 0x10
	// Bit B740.
	GTZC_VCTR23_B740 = 0x10
	// Position of B741 field.
	GTZC_VCTR23_B741_Pos = 0x5
	// Bit mask of B741 field.
	GTZC_VCTR23_B741_Msk = 0x20
	// Bit B741.
	GTZC_VCTR23_B741 = 0x20
	// Position of B742 field.
	GTZC_VCTR23_B742_Pos = 0x6
	// Bit mask of B742 field.
	GTZC_VCTR23_B742_Msk = 0x40
	// Bit B742.
	GTZC_VCTR23_B742 = 0x40
	// Position of B743 field.
	GTZC_VCTR23_B743_Pos = 0x7
	// Bit mask of B743 field.
	GTZC_VCTR23_B743_Msk = 0x80
	// Bit B743.
	GTZC_VCTR23_B743 = 0x80
	// Position of B744 field.
	GTZC_VCTR23_B744_Pos = 0x8
	// Bit mask of B744 field.
	GTZC_VCTR23_B744_Msk = 0x100
	// Bit B744.
	GTZC_VCTR23_B744 = 0x100
	// Position of B745 field.
	GTZC_VCTR23_B745_Pos = 0x9
	// Bit mask of B745 field.
	GTZC_VCTR23_B745_Msk = 0x200
	// Bit B745.
	GTZC_VCTR23_B745 = 0x200
	// Position of B746 field.
	GTZC_VCTR23_B746_Pos = 0xa
	// Bit mask of B746 field.
	GTZC_VCTR23_B746_Msk = 0x400
	// Bit B746.
	GTZC_VCTR23_B746 = 0x400
	// Position of B747 field.
	GTZC_VCTR23_B747_Pos = 0xb
	// Bit mask of B747 field.
	GTZC_VCTR23_B747_Msk = 0x800
	// Bit B747.
	GTZC_VCTR23_B747 = 0x800
	// Position of B748 field.
	GTZC_VCTR23_B748_Pos = 0xc
	// Bit mask of B748 field.
	GTZC_VCTR23_B748_Msk = 0x1000
	// Bit B748.
	GTZC_VCTR23_B748 = 0x1000
	// Position of B749 field.
	GTZC_VCTR23_B749_Pos = 0xd
	// Bit mask of B749 field.
	GTZC_VCTR23_B749_Msk = 0x2000
	// Bit B749.
	GTZC_VCTR23_B749 = 0x2000
	// Position of B750 field.
	GTZC_VCTR23_B750_Pos = 0xe
	// Bit mask of B750 field.
	GTZC_VCTR23_B750_Msk = 0x4000
	// Bit B750.
	GTZC_VCTR23_B750 = 0x4000
	// Position of B751 field.
	GTZC_VCTR23_B751_Pos = 0xf
	// Bit mask of B751 field.
	GTZC_VCTR23_B751_Msk = 0x8000
	// Bit B751.
	GTZC_VCTR23_B751 = 0x8000
	// Position of B752 field.
	GTZC_VCTR23_B752_Pos = 0x10
	// Bit mask of B752 field.
	GTZC_VCTR23_B752_Msk = 0x10000
	// Bit B752.
	GTZC_VCTR23_B752 = 0x10000
	// Position of B753 field.
	GTZC_VCTR23_B753_Pos = 0x11
	// Bit mask of B753 field.
	GTZC_VCTR23_B753_Msk = 0x20000
	// Bit B753.
	GTZC_VCTR23_B753 = 0x20000
	// Position of B754 field.
	GTZC_VCTR23_B754_Pos = 0x12
	// Bit mask of B754 field.
	GTZC_VCTR23_B754_Msk = 0x40000
	// Bit B754.
	GTZC_VCTR23_B754 = 0x40000
	// Position of B755 field.
	GTZC_VCTR23_B755_Pos = 0x13
	// Bit mask of B755 field.
	GTZC_VCTR23_B755_Msk = 0x80000
	// Bit B755.
	GTZC_VCTR23_B755 = 0x80000
	// Position of B756 field.
	GTZC_VCTR23_B756_Pos = 0x14
	// Bit mask of B756 field.
	GTZC_VCTR23_B756_Msk = 0x100000
	// Bit B756.
	GTZC_VCTR23_B756 = 0x100000
	// Position of B757 field.
	GTZC_VCTR23_B757_Pos = 0x15
	// Bit mask of B757 field.
	GTZC_VCTR23_B757_Msk = 0x200000
	// Bit B757.
	GTZC_VCTR23_B757 = 0x200000
	// Position of B758 field.
	GTZC_VCTR23_B758_Pos = 0x16
	// Bit mask of B758 field.
	GTZC_VCTR23_B758_Msk = 0x400000
	// Bit B758.
	GTZC_VCTR23_B758 = 0x400000
	// Position of B759 field.
	GTZC_VCTR23_B759_Pos = 0x17
	// Bit mask of B759 field.
	GTZC_VCTR23_B759_Msk = 0x800000
	// Bit B759.
	GTZC_VCTR23_B759 = 0x800000
	// Position of B760 field.
	GTZC_VCTR23_B760_Pos = 0x18
	// Bit mask of B760 field.
	GTZC_VCTR23_B760_Msk = 0x1000000
	// Bit B760.
	GTZC_VCTR23_B760 = 0x1000000
	// Position of B761 field.
	GTZC_VCTR23_B761_Pos = 0x19
	// Bit mask of B761 field.
	GTZC_VCTR23_B761_Msk = 0x2000000
	// Bit B761.
	GTZC_VCTR23_B761 = 0x2000000
	// Position of B762 field.
	GTZC_VCTR23_B762_Pos = 0x1a
	// Bit mask of B762 field.
	GTZC_VCTR23_B762_Msk = 0x4000000
	// Bit B762.
	GTZC_VCTR23_B762 = 0x4000000
	// Position of B763 field.
	GTZC_VCTR23_B763_Pos = 0x1b
	// Bit mask of B763 field.
	GTZC_VCTR23_B763_Msk = 0x8000000
	// Bit B763.
	GTZC_VCTR23_B763 = 0x8000000
	// Position of B764 field.
	GTZC_VCTR23_B764_Pos = 0x1c
	// Bit mask of B764 field.
	GTZC_VCTR23_B764_Msk = 0x10000000
	// Bit B764.
	GTZC_VCTR23_B764 = 0x10000000
	// Position of B765 field.
	GTZC_VCTR23_B765_Pos = 0x1d
	// Bit mask of B765 field.
	GTZC_VCTR23_B765_Msk = 0x20000000
	// Bit B765.
	GTZC_VCTR23_B765 = 0x20000000
	// Position of B766 field.
	GTZC_VCTR23_B766_Pos = 0x1e
	// Bit mask of B766 field.
	GTZC_VCTR23_B766_Msk = 0x40000000
	// Bit B766.
	GTZC_VCTR23_B766 = 0x40000000
	// Position of B767 field.
	GTZC_VCTR23_B767_Pos = 0x1f
	// Bit mask of B767 field.
	GTZC_VCTR23_B767_Msk = 0x80000000
	// Bit B767.
	GTZC_VCTR23_B767 = 0x80000000

	// VCTR24: MPCBBx vector register
	// Position of B768 field.
	GTZC_VCTR24_B768_Pos = 0x0
	// Bit mask of B768 field.
	GTZC_VCTR24_B768_Msk = 0x1
	// Bit B768.
	GTZC_VCTR24_B768 = 0x1
	// Position of B769 field.
	GTZC_VCTR24_B769_Pos = 0x1
	// Bit mask of B769 field.
	GTZC_VCTR24_B769_Msk = 0x2
	// Bit B769.
	GTZC_VCTR24_B769 = 0x2
	// Position of B770 field.
	GTZC_VCTR24_B770_Pos = 0x2
	// Bit mask of B770 field.
	GTZC_VCTR24_B770_Msk = 0x4
	// Bit B770.
	GTZC_VCTR24_B770 = 0x4
	// Position of B771 field.
	GTZC_VCTR24_B771_Pos = 0x3
	// Bit mask of B771 field.
	GTZC_VCTR24_B771_Msk = 0x8
	// Bit B771.
	GTZC_VCTR24_B771 = 0x8
	// Position of B772 field.
	GTZC_VCTR24_B772_Pos = 0x4
	// Bit mask of B772 field.
	GTZC_VCTR24_B772_Msk = 0x10
	// Bit B772.
	GTZC_VCTR24_B772 = 0x10
	// Position of B773 field.
	GTZC_VCTR24_B773_Pos = 0x5
	// Bit mask of B773 field.
	GTZC_VCTR24_B773_Msk = 0x20
	// Bit B773.
	GTZC_VCTR24_B773 = 0x20
	// Position of B774 field.
	GTZC_VCTR24_B774_Pos = 0x6
	// Bit mask of B774 field.
	GTZC_VCTR24_B774_Msk = 0x40
	// Bit B774.
	GTZC_VCTR24_B774 = 0x40
	// Position of B775 field.
	GTZC_VCTR24_B775_Pos = 0x7
	// Bit mask of B775 field.
	GTZC_VCTR24_B775_Msk = 0x80
	// Bit B775.
	GTZC_VCTR24_B775 = 0x80
	// Position of B776 field.
	GTZC_VCTR24_B776_Pos = 0x8
	// Bit mask of B776 field.
	GTZC_VCTR24_B776_Msk = 0x100
	// Bit B776.
	GTZC_VCTR24_B776 = 0x100
	// Position of B777 field.
	GTZC_VCTR24_B777_Pos = 0x9
	// Bit mask of B777 field.
	GTZC_VCTR24_B777_Msk = 0x200
	// Bit B777.
	GTZC_VCTR24_B777 = 0x200
	// Position of B778 field.
	GTZC_VCTR24_B778_Pos = 0xa
	// Bit mask of B778 field.
	GTZC_VCTR24_B778_Msk = 0x400
	// Bit B778.
	GTZC_VCTR24_B778 = 0x400
	// Position of B779 field.
	GTZC_VCTR24_B779_Pos = 0xb
	// Bit mask of B779 field.
	GTZC_VCTR24_B779_Msk = 0x800
	// Bit B779.
	GTZC_VCTR24_B779 = 0x800
	// Position of B780 field.
	GTZC_VCTR24_B780_Pos = 0xc
	// Bit mask of B780 field.
	GTZC_VCTR24_B780_Msk = 0x1000
	// Bit B780.
	GTZC_VCTR24_B780 = 0x1000
	// Position of B781 field.
	GTZC_VCTR24_B781_Pos = 0xd
	// Bit mask of B781 field.
	GTZC_VCTR24_B781_Msk = 0x2000
	// Bit B781.
	GTZC_VCTR24_B781 = 0x2000
	// Position of B782 field.
	GTZC_VCTR24_B782_Pos = 0xe
	// Bit mask of B782 field.
	GTZC_VCTR24_B782_Msk = 0x4000
	// Bit B782.
	GTZC_VCTR24_B782 = 0x4000
	// Position of B783 field.
	GTZC_VCTR24_B783_Pos = 0xf
	// Bit mask of B783 field.
	GTZC_VCTR24_B783_Msk = 0x8000
	// Bit B783.
	GTZC_VCTR24_B783 = 0x8000
	// Position of B784 field.
	GTZC_VCTR24_B784_Pos = 0x10
	// Bit mask of B784 field.
	GTZC_VCTR24_B784_Msk = 0x10000
	// Bit B784.
	GTZC_VCTR24_B784 = 0x10000
	// Position of B785 field.
	GTZC_VCTR24_B785_Pos = 0x11
	// Bit mask of B785 field.
	GTZC_VCTR24_B785_Msk = 0x20000
	// Bit B785.
	GTZC_VCTR24_B785 = 0x20000
	// Position of B786 field.
	GTZC_VCTR24_B786_Pos = 0x12
	// Bit mask of B786 field.
	GTZC_VCTR24_B786_Msk = 0x40000
	// Bit B786.
	GTZC_VCTR24_B786 = 0x40000
	// Position of B787 field.
	GTZC_VCTR24_B787_Pos = 0x13
	// Bit mask of B787 field.
	GTZC_VCTR24_B787_Msk = 0x80000
	// Bit B787.
	GTZC_VCTR24_B787 = 0x80000
	// Position of B788 field.
	GTZC_VCTR24_B788_Pos = 0x14
	// Bit mask of B788 field.
	GTZC_VCTR24_B788_Msk = 0x100000
	// Bit B788.
	GTZC_VCTR24_B788 = 0x100000
	// Position of B789 field.
	GTZC_VCTR24_B789_Pos = 0x15
	// Bit mask of B789 field.
	GTZC_VCTR24_B789_Msk = 0x200000
	// Bit B789.
	GTZC_VCTR24_B789 = 0x200000
	// Position of B790 field.
	GTZC_VCTR24_B790_Pos = 0x16
	// Bit mask of B790 field.
	GTZC_VCTR24_B790_Msk = 0x400000
	// Bit B790.
	GTZC_VCTR24_B790 = 0x400000
	// Position of B791 field.
	GTZC_VCTR24_B791_Pos = 0x17
	// Bit mask of B791 field.
	GTZC_VCTR24_B791_Msk = 0x800000
	// Bit B791.
	GTZC_VCTR24_B791 = 0x800000
	// Position of B792 field.
	GTZC_VCTR24_B792_Pos = 0x18
	// Bit mask of B792 field.
	GTZC_VCTR24_B792_Msk = 0x1000000
	// Bit B792.
	GTZC_VCTR24_B792 = 0x1000000
	// Position of B793 field.
	GTZC_VCTR24_B793_Pos = 0x19
	// Bit mask of B793 field.
	GTZC_VCTR24_B793_Msk = 0x2000000
	// Bit B793.
	GTZC_VCTR24_B793 = 0x2000000
	// Position of B794 field.
	GTZC_VCTR24_B794_Pos = 0x1a
	// Bit mask of B794 field.
	GTZC_VCTR24_B794_Msk = 0x4000000
	// Bit B794.
	GTZC_VCTR24_B794 = 0x4000000
	// Position of B795 field.
	GTZC_VCTR24_B795_Pos = 0x1b
	// Bit mask of B795 field.
	GTZC_VCTR24_B795_Msk = 0x8000000
	// Bit B795.
	GTZC_VCTR24_B795 = 0x8000000
	// Position of B796 field.
	GTZC_VCTR24_B796_Pos = 0x1c
	// Bit mask of B796 field.
	GTZC_VCTR24_B796_Msk = 0x10000000
	// Bit B796.
	GTZC_VCTR24_B796 = 0x10000000
	// Position of B797 field.
	GTZC_VCTR24_B797_Pos = 0x1d
	// Bit mask of B797 field.
	GTZC_VCTR24_B797_Msk = 0x20000000
	// Bit B797.
	GTZC_VCTR24_B797 = 0x20000000
	// Position of B798 field.
	GTZC_VCTR24_B798_Pos = 0x1e
	// Bit mask of B798 field.
	GTZC_VCTR24_B798_Msk = 0x40000000
	// Bit B798.
	GTZC_VCTR24_B798 = 0x40000000
	// Position of B799 field.
	GTZC_VCTR24_B799_Pos = 0x1f
	// Bit mask of B799 field.
	GTZC_VCTR24_B799_Msk = 0x80000000
	// Bit B799.
	GTZC_VCTR24_B799 = 0x80000000

	// VCTR25: MPCBBx vector register
	// Position of B800 field.
	GTZC_VCTR25_B800_Pos = 0x0
	// Bit mask of B800 field.
	GTZC_VCTR25_B800_Msk = 0x1
	// Bit B800.
	GTZC_VCTR25_B800 = 0x1
	// Position of B801 field.
	GTZC_VCTR25_B801_Pos = 0x1
	// Bit mask of B801 field.
	GTZC_VCTR25_B801_Msk = 0x2
	// Bit B801.
	GTZC_VCTR25_B801 = 0x2
	// Position of B802 field.
	GTZC_VCTR25_B802_Pos = 0x2
	// Bit mask of B802 field.
	GTZC_VCTR25_B802_Msk = 0x4
	// Bit B802.
	GTZC_VCTR25_B802 = 0x4
	// Position of B803 field.
	GTZC_VCTR25_B803_Pos = 0x3
	// Bit mask of B803 field.
	GTZC_VCTR25_B803_Msk = 0x8
	// Bit B803.
	GTZC_VCTR25_B803 = 0x8
	// Position of B804 field.
	GTZC_VCTR25_B804_Pos = 0x4
	// Bit mask of B804 field.
	GTZC_VCTR25_B804_Msk = 0x10
	// Bit B804.
	GTZC_VCTR25_B804 = 0x10
	// Position of B805 field.
	GTZC_VCTR25_B805_Pos = 0x5
	// Bit mask of B805 field.
	GTZC_VCTR25_B805_Msk = 0x20
	// Bit B805.
	GTZC_VCTR25_B805 = 0x20
	// Position of B806 field.
	GTZC_VCTR25_B806_Pos = 0x6
	// Bit mask of B806 field.
	GTZC_VCTR25_B806_Msk = 0x40
	// Bit B806.
	GTZC_VCTR25_B806 = 0x40
	// Position of B807 field.
	GTZC_VCTR25_B807_Pos = 0x7
	// Bit mask of B807 field.
	GTZC_VCTR25_B807_Msk = 0x80
	// Bit B807.
	GTZC_VCTR25_B807 = 0x80
	// Position of B808 field.
	GTZC_VCTR25_B808_Pos = 0x8
	// Bit mask of B808 field.
	GTZC_VCTR25_B808_Msk = 0x100
	// Bit B808.
	GTZC_VCTR25_B808 = 0x100
	// Position of B809 field.
	GTZC_VCTR25_B809_Pos = 0x9
	// Bit mask of B809 field.
	GTZC_VCTR25_B809_Msk = 0x200
	// Bit B809.
	GTZC_VCTR25_B809 = 0x200
	// Position of B810 field.
	GTZC_VCTR25_B810_Pos = 0xa
	// Bit mask of B810 field.
	GTZC_VCTR25_B810_Msk = 0x400
	// Bit B810.
	GTZC_VCTR25_B810 = 0x400
	// Position of B811 field.
	GTZC_VCTR25_B811_Pos = 0xb
	// Bit mask of B811 field.
	GTZC_VCTR25_B811_Msk = 0x800
	// Bit B811.
	GTZC_VCTR25_B811 = 0x800
	// Position of B812 field.
	GTZC_VCTR25_B812_Pos = 0xc
	// Bit mask of B812 field.
	GTZC_VCTR25_B812_Msk = 0x1000
	// Bit B812.
	GTZC_VCTR25_B812 = 0x1000
	// Position of B813 field.
	GTZC_VCTR25_B813_Pos = 0xd
	// Bit mask of B813 field.
	GTZC_VCTR25_B813_Msk = 0x2000
	// Bit B813.
	GTZC_VCTR25_B813 = 0x2000
	// Position of B814 field.
	GTZC_VCTR25_B814_Pos = 0xe
	// Bit mask of B814 field.
	GTZC_VCTR25_B814_Msk = 0x4000
	// Bit B814.
	GTZC_VCTR25_B814 = 0x4000
	// Position of B815 field.
	GTZC_VCTR25_B815_Pos = 0xf
	// Bit mask of B815 field.
	GTZC_VCTR25_B815_Msk = 0x8000
	// Bit B815.
	GTZC_VCTR25_B815 = 0x8000
	// Position of B816 field.
	GTZC_VCTR25_B816_Pos = 0x10
	// Bit mask of B816 field.
	GTZC_VCTR25_B816_Msk = 0x10000
	// Bit B816.
	GTZC_VCTR25_B816 = 0x10000
	// Position of B817 field.
	GTZC_VCTR25_B817_Pos = 0x11
	// Bit mask of B817 field.
	GTZC_VCTR25_B817_Msk = 0x20000
	// Bit B817.
	GTZC_VCTR25_B817 = 0x20000
	// Position of B818 field.
	GTZC_VCTR25_B818_Pos = 0x12
	// Bit mask of B818 field.
	GTZC_VCTR25_B818_Msk = 0x40000
	// Bit B818.
	GTZC_VCTR25_B818 = 0x40000
	// Position of B819 field.
	GTZC_VCTR25_B819_Pos = 0x13
	// Bit mask of B819 field.
	GTZC_VCTR25_B819_Msk = 0x80000
	// Bit B819.
	GTZC_VCTR25_B819 = 0x80000
	// Position of B820 field.
	GTZC_VCTR25_B820_Pos = 0x14
	// Bit mask of B820 field.
	GTZC_VCTR25_B820_Msk = 0x100000
	// Bit B820.
	GTZC_VCTR25_B820 = 0x100000
	// Position of B821 field.
	GTZC_VCTR25_B821_Pos = 0x15
	// Bit mask of B821 field.
	GTZC_VCTR25_B821_Msk = 0x200000
	// Bit B821.
	GTZC_VCTR25_B821 = 0x200000
	// Position of B822 field.
	GTZC_VCTR25_B822_Pos = 0x16
	// Bit mask of B822 field.
	GTZC_VCTR25_B822_Msk = 0x400000
	// Bit B822.
	GTZC_VCTR25_B822 = 0x400000
	// Position of B823 field.
	GTZC_VCTR25_B823_Pos = 0x17
	// Bit mask of B823 field.
	GTZC_VCTR25_B823_Msk = 0x800000
	// Bit B823.
	GTZC_VCTR25_B823 = 0x800000
	// Position of B824 field.
	GTZC_VCTR25_B824_Pos = 0x18
	// Bit mask of B824 field.
	GTZC_VCTR25_B824_Msk = 0x1000000
	// Bit B824.
	GTZC_VCTR25_B824 = 0x1000000
	// Position of B825 field.
	GTZC_VCTR25_B825_Pos = 0x19
	// Bit mask of B825 field.
	GTZC_VCTR25_B825_Msk = 0x2000000
	// Bit B825.
	GTZC_VCTR25_B825 = 0x2000000
	// Position of B826 field.
	GTZC_VCTR25_B826_Pos = 0x1a
	// Bit mask of B826 field.
	GTZC_VCTR25_B826_Msk = 0x4000000
	// Bit B826.
	GTZC_VCTR25_B826 = 0x4000000
	// Position of B827 field.
	GTZC_VCTR25_B827_Pos = 0x1b
	// Bit mask of B827 field.
	GTZC_VCTR25_B827_Msk = 0x8000000
	// Bit B827.
	GTZC_VCTR25_B827 = 0x8000000
	// Position of B828 field.
	GTZC_VCTR25_B828_Pos = 0x1c
	// Bit mask of B828 field.
	GTZC_VCTR25_B828_Msk = 0x10000000
	// Bit B828.
	GTZC_VCTR25_B828 = 0x10000000
	// Position of B829 field.
	GTZC_VCTR25_B829_Pos = 0x1d
	// Bit mask of B829 field.
	GTZC_VCTR25_B829_Msk = 0x20000000
	// Bit B829.
	GTZC_VCTR25_B829 = 0x20000000
	// Position of B830 field.
	GTZC_VCTR25_B830_Pos = 0x1e
	// Bit mask of B830 field.
	GTZC_VCTR25_B830_Msk = 0x40000000
	// Bit B830.
	GTZC_VCTR25_B830 = 0x40000000
	// Position of B831 field.
	GTZC_VCTR25_B831_Pos = 0x1f
	// Bit mask of B831 field.
	GTZC_VCTR25_B831_Msk = 0x80000000
	// Bit B831.
	GTZC_VCTR25_B831 = 0x80000000

	// VCTR26: MPCBBx vector register
	// Position of B832 field.
	GTZC_VCTR26_B832_Pos = 0x0
	// Bit mask of B832 field.
	GTZC_VCTR26_B832_Msk = 0x1
	// Bit B832.
	GTZC_VCTR26_B832 = 0x1
	// Position of B833 field.
	GTZC_VCTR26_B833_Pos = 0x1
	// Bit mask of B833 field.
	GTZC_VCTR26_B833_Msk = 0x2
	// Bit B833.
	GTZC_VCTR26_B833 = 0x2
	// Position of B834 field.
	GTZC_VCTR26_B834_Pos = 0x2
	// Bit mask of B834 field.
	GTZC_VCTR26_B834_Msk = 0x4
	// Bit B834.
	GTZC_VCTR26_B834 = 0x4
	// Position of B835 field.
	GTZC_VCTR26_B835_Pos = 0x3
	// Bit mask of B835 field.
	GTZC_VCTR26_B835_Msk = 0x8
	// Bit B835.
	GTZC_VCTR26_B835 = 0x8
	// Position of B836 field.
	GTZC_VCTR26_B836_Pos = 0x4
	// Bit mask of B836 field.
	GTZC_VCTR26_B836_Msk = 0x10
	// Bit B836.
	GTZC_VCTR26_B836 = 0x10
	// Position of B837 field.
	GTZC_VCTR26_B837_Pos = 0x5
	// Bit mask of B837 field.
	GTZC_VCTR26_B837_Msk = 0x20
	// Bit B837.
	GTZC_VCTR26_B837 = 0x20
	// Position of B838 field.
	GTZC_VCTR26_B838_Pos = 0x6
	// Bit mask of B838 field.
	GTZC_VCTR26_B838_Msk = 0x40
	// Bit B838.
	GTZC_VCTR26_B838 = 0x40
	// Position of B839 field.
	GTZC_VCTR26_B839_Pos = 0x7
	// Bit mask of B839 field.
	GTZC_VCTR26_B839_Msk = 0x80
	// Bit B839.
	GTZC_VCTR26_B839 = 0x80
	// Position of B840 field.
	GTZC_VCTR26_B840_Pos = 0x8
	// Bit mask of B840 field.
	GTZC_VCTR26_B840_Msk = 0x100
	// Bit B840.
	GTZC_VCTR26_B840 = 0x100
	// Position of B841 field.
	GTZC_VCTR26_B841_Pos = 0x9
	// Bit mask of B841 field.
	GTZC_VCTR26_B841_Msk = 0x200
	// Bit B841.
	GTZC_VCTR26_B841 = 0x200
	// Position of B842 field.
	GTZC_VCTR26_B842_Pos = 0xa
	// Bit mask of B842 field.
	GTZC_VCTR26_B842_Msk = 0x400
	// Bit B842.
	GTZC_VCTR26_B842 = 0x400
	// Position of B843 field.
	GTZC_VCTR26_B843_Pos = 0xb
	// Bit mask of B843 field.
	GTZC_VCTR26_B843_Msk = 0x800
	// Bit B843.
	GTZC_VCTR26_B843 = 0x800
	// Position of B844 field.
	GTZC_VCTR26_B844_Pos = 0xc
	// Bit mask of B844 field.
	GTZC_VCTR26_B844_Msk = 0x1000
	// Bit B844.
	GTZC_VCTR26_B844 = 0x1000
	// Position of B845 field.
	GTZC_VCTR26_B845_Pos = 0xd
	// Bit mask of B845 field.
	GTZC_VCTR26_B845_Msk = 0x2000
	// Bit B845.
	GTZC_VCTR26_B845 = 0x2000
	// Position of B846 field.
	GTZC_VCTR26_B846_Pos = 0xe
	// Bit mask of B846 field.
	GTZC_VCTR26_B846_Msk = 0x4000
	// Bit B846.
	GTZC_VCTR26_B846 = 0x4000
	// Position of B847 field.
	GTZC_VCTR26_B847_Pos = 0xf
	// Bit mask of B847 field.
	GTZC_VCTR26_B847_Msk = 0x8000
	// Bit B847.
	GTZC_VCTR26_B847 = 0x8000
	// Position of B848 field.
	GTZC_VCTR26_B848_Pos = 0x10
	// Bit mask of B848 field.
	GTZC_VCTR26_B848_Msk = 0x10000
	// Bit B848.
	GTZC_VCTR26_B848 = 0x10000
	// Position of B849 field.
	GTZC_VCTR26_B849_Pos = 0x11
	// Bit mask of B849 field.
	GTZC_VCTR26_B849_Msk = 0x20000
	// Bit B849.
	GTZC_VCTR26_B849 = 0x20000
	// Position of B850 field.
	GTZC_VCTR26_B850_Pos = 0x12
	// Bit mask of B850 field.
	GTZC_VCTR26_B850_Msk = 0x40000
	// Bit B850.
	GTZC_VCTR26_B850 = 0x40000
	// Position of B851 field.
	GTZC_VCTR26_B851_Pos = 0x13
	// Bit mask of B851 field.
	GTZC_VCTR26_B851_Msk = 0x80000
	// Bit B851.
	GTZC_VCTR26_B851 = 0x80000
	// Position of B852 field.
	GTZC_VCTR26_B852_Pos = 0x14
	// Bit mask of B852 field.
	GTZC_VCTR26_B852_Msk = 0x100000
	// Bit B852.
	GTZC_VCTR26_B852 = 0x100000
	// Position of B853 field.
	GTZC_VCTR26_B853_Pos = 0x15
	// Bit mask of B853 field.
	GTZC_VCTR26_B853_Msk = 0x200000
	// Bit B853.
	GTZC_VCTR26_B853 = 0x200000
	// Position of B854 field.
	GTZC_VCTR26_B854_Pos = 0x16
	// Bit mask of B854 field.
	GTZC_VCTR26_B854_Msk = 0x400000
	// Bit B854.
	GTZC_VCTR26_B854 = 0x400000
	// Position of B855 field.
	GTZC_VCTR26_B855_Pos = 0x17
	// Bit mask of B855 field.
	GTZC_VCTR26_B855_Msk = 0x800000
	// Bit B855.
	GTZC_VCTR26_B855 = 0x800000
	// Position of B856 field.
	GTZC_VCTR26_B856_Pos = 0x18
	// Bit mask of B856 field.
	GTZC_VCTR26_B856_Msk = 0x1000000
	// Bit B856.
	GTZC_VCTR26_B856 = 0x1000000
	// Position of B857 field.
	GTZC_VCTR26_B857_Pos = 0x19
	// Bit mask of B857 field.
	GTZC_VCTR26_B857_Msk = 0x2000000
	// Bit B857.
	GTZC_VCTR26_B857 = 0x2000000
	// Position of B858 field.
	GTZC_VCTR26_B858_Pos = 0x1a
	// Bit mask of B858 field.
	GTZC_VCTR26_B858_Msk = 0x4000000
	// Bit B858.
	GTZC_VCTR26_B858 = 0x4000000
	// Position of B859 field.
	GTZC_VCTR26_B859_Pos = 0x1b
	// Bit mask of B859 field.
	GTZC_VCTR26_B859_Msk = 0x8000000
	// Bit B859.
	GTZC_VCTR26_B859 = 0x8000000
	// Position of B860 field.
	GTZC_VCTR26_B860_Pos = 0x1c
	// Bit mask of B860 field.
	GTZC_VCTR26_B860_Msk = 0x10000000
	// Bit B860.
	GTZC_VCTR26_B860 = 0x10000000
	// Position of B861 field.
	GTZC_VCTR26_B861_Pos = 0x1d
	// Bit mask of B861 field.
	GTZC_VCTR26_B861_Msk = 0x20000000
	// Bit B861.
	GTZC_VCTR26_B861 = 0x20000000
	// Position of B862 field.
	GTZC_VCTR26_B862_Pos = 0x1e
	// Bit mask of B862 field.
	GTZC_VCTR26_B862_Msk = 0x40000000
	// Bit B862.
	GTZC_VCTR26_B862 = 0x40000000
	// Position of B863 field.
	GTZC_VCTR26_B863_Pos = 0x1f
	// Bit mask of B863 field.
	GTZC_VCTR26_B863_Msk = 0x80000000
	// Bit B863.
	GTZC_VCTR26_B863 = 0x80000000

	// VCTR27: MPCBBx vector register
	// Position of B864 field.
	GTZC_VCTR27_B864_Pos = 0x0
	// Bit mask of B864 field.
	GTZC_VCTR27_B864_Msk = 0x1
	// Bit B864.
	GTZC_VCTR27_B864 = 0x1
	// Position of B865 field.
	GTZC_VCTR27_B865_Pos = 0x1
	// Bit mask of B865 field.
	GTZC_VCTR27_B865_Msk = 0x2
	// Bit B865.
	GTZC_VCTR27_B865 = 0x2
	// Position of B866 field.
	GTZC_VCTR27_B866_Pos = 0x2
	// Bit mask of B866 field.
	GTZC_VCTR27_B866_Msk = 0x4
	// Bit B866.
	GTZC_VCTR27_B866 = 0x4
	// Position of B867 field.
	GTZC_VCTR27_B867_Pos = 0x3
	// Bit mask of B867 field.
	GTZC_VCTR27_B867_Msk = 0x8
	// Bit B867.
	GTZC_VCTR27_B867 = 0x8
	// Position of B868 field.
	GTZC_VCTR27_B868_Pos = 0x4
	// Bit mask of B868 field.
	GTZC_VCTR27_B868_Msk = 0x10
	// Bit B868.
	GTZC_VCTR27_B868 = 0x10
	// Position of B869 field.
	GTZC_VCTR27_B869_Pos = 0x5
	// Bit mask of B869 field.
	GTZC_VCTR27_B869_Msk = 0x20
	// Bit B869.
	GTZC_VCTR27_B869 = 0x20
	// Position of B870 field.
	GTZC_VCTR27_B870_Pos = 0x6
	// Bit mask of B870 field.
	GTZC_VCTR27_B870_Msk = 0x40
	// Bit B870.
	GTZC_VCTR27_B870 = 0x40
	// Position of B871 field.
	GTZC_VCTR27_B871_Pos = 0x7
	// Bit mask of B871 field.
	GTZC_VCTR27_B871_Msk = 0x80
	// Bit B871.
	GTZC_VCTR27_B871 = 0x80
	// Position of B872 field.
	GTZC_VCTR27_B872_Pos = 0x8
	// Bit mask of B872 field.
	GTZC_VCTR27_B872_Msk = 0x100
	// Bit B872.
	GTZC_VCTR27_B872 = 0x100
	// Position of B873 field.
	GTZC_VCTR27_B873_Pos = 0x9
	// Bit mask of B873 field.
	GTZC_VCTR27_B873_Msk = 0x200
	// Bit B873.
	GTZC_VCTR27_B873 = 0x200
	// Position of B874 field.
	GTZC_VCTR27_B874_Pos = 0xa
	// Bit mask of B874 field.
	GTZC_VCTR27_B874_Msk = 0x400
	// Bit B874.
	GTZC_VCTR27_B874 = 0x400
	// Position of B875 field.
	GTZC_VCTR27_B875_Pos = 0xb
	// Bit mask of B875 field.
	GTZC_VCTR27_B875_Msk = 0x800
	// Bit B875.
	GTZC_VCTR27_B875 = 0x800
	// Position of B876 field.
	GTZC_VCTR27_B876_Pos = 0xc
	// Bit mask of B876 field.
	GTZC_VCTR27_B876_Msk = 0x1000
	// Bit B876.
	GTZC_VCTR27_B876 = 0x1000
	// Position of B877 field.
	GTZC_VCTR27_B877_Pos = 0xd
	// Bit mask of B877 field.
	GTZC_VCTR27_B877_Msk = 0x2000
	// Bit B877.
	GTZC_VCTR27_B877 = 0x2000
	// Position of B878 field.
	GTZC_VCTR27_B878_Pos = 0xe
	// Bit mask of B878 field.
	GTZC_VCTR27_B878_Msk = 0x4000
	// Bit B878.
	GTZC_VCTR27_B878 = 0x4000
	// Position of B879 field.
	GTZC_VCTR27_B879_Pos = 0xf
	// Bit mask of B879 field.
	GTZC_VCTR27_B879_Msk = 0x8000
	// Bit B879.
	GTZC_VCTR27_B879 = 0x8000
	// Position of B880 field.
	GTZC_VCTR27_B880_Pos = 0x10
	// Bit mask of B880 field.
	GTZC_VCTR27_B880_Msk = 0x10000
	// Bit B880.
	GTZC_VCTR27_B880 = 0x10000
	// Position of B881 field.
	GTZC_VCTR27_B881_Pos = 0x11
	// Bit mask of B881 field.
	GTZC_VCTR27_B881_Msk = 0x20000
	// Bit B881.
	GTZC_VCTR27_B881 = 0x20000
	// Position of B882 field.
	GTZC_VCTR27_B882_Pos = 0x12
	// Bit mask of B882 field.
	GTZC_VCTR27_B882_Msk = 0x40000
	// Bit B882.
	GTZC_VCTR27_B882 = 0x40000
	// Position of B883 field.
	GTZC_VCTR27_B883_Pos = 0x13
	// Bit mask of B883 field.
	GTZC_VCTR27_B883_Msk = 0x80000
	// Bit B883.
	GTZC_VCTR27_B883 = 0x80000
	// Position of B884 field.
	GTZC_VCTR27_B884_Pos = 0x14
	// Bit mask of B884 field.
	GTZC_VCTR27_B884_Msk = 0x100000
	// Bit B884.
	GTZC_VCTR27_B884 = 0x100000
	// Position of B885 field.
	GTZC_VCTR27_B885_Pos = 0x15
	// Bit mask of B885 field.
	GTZC_VCTR27_B885_Msk = 0x200000
	// Bit B885.
	GTZC_VCTR27_B885 = 0x200000
	// Position of B886 field.
	GTZC_VCTR27_B886_Pos = 0x16
	// Bit mask of B886 field.
	GTZC_VCTR27_B886_Msk = 0x400000
	// Bit B886.
	GTZC_VCTR27_B886 = 0x400000
	// Position of B887 field.
	GTZC_VCTR27_B887_Pos = 0x17
	// Bit mask of B887 field.
	GTZC_VCTR27_B887_Msk = 0x800000
	// Bit B887.
	GTZC_VCTR27_B887 = 0x800000
	// Position of B888 field.
	GTZC_VCTR27_B888_Pos = 0x18
	// Bit mask of B888 field.
	GTZC_VCTR27_B888_Msk = 0x1000000
	// Bit B888.
	GTZC_VCTR27_B888 = 0x1000000
	// Position of B889 field.
	GTZC_VCTR27_B889_Pos = 0x19
	// Bit mask of B889 field.
	GTZC_VCTR27_B889_Msk = 0x2000000
	// Bit B889.
	GTZC_VCTR27_B889 = 0x2000000
	// Position of B890 field.
	GTZC_VCTR27_B890_Pos = 0x1a
	// Bit mask of B890 field.
	GTZC_VCTR27_B890_Msk = 0x4000000
	// Bit B890.
	GTZC_VCTR27_B890 = 0x4000000
	// Position of B891 field.
	GTZC_VCTR27_B891_Pos = 0x1b
	// Bit mask of B891 field.
	GTZC_VCTR27_B891_Msk = 0x8000000
	// Bit B891.
	GTZC_VCTR27_B891 = 0x8000000
	// Position of B892 field.
	GTZC_VCTR27_B892_Pos = 0x1c
	// Bit mask of B892 field.
	GTZC_VCTR27_B892_Msk = 0x10000000
	// Bit B892.
	GTZC_VCTR27_B892 = 0x10000000
	// Position of B893 field.
	GTZC_VCTR27_B893_Pos = 0x1d
	// Bit mask of B893 field.
	GTZC_VCTR27_B893_Msk = 0x20000000
	// Bit B893.
	GTZC_VCTR27_B893 = 0x20000000
	// Position of B894 field.
	GTZC_VCTR27_B894_Pos = 0x1e
	// Bit mask of B894 field.
	GTZC_VCTR27_B894_Msk = 0x40000000
	// Bit B894.
	GTZC_VCTR27_B894 = 0x40000000
	// Position of B895 field.
	GTZC_VCTR27_B895_Pos = 0x1f
	// Bit mask of B895 field.
	GTZC_VCTR27_B895_Msk = 0x80000000
	// Bit B895.
	GTZC_VCTR27_B895 = 0x80000000

	// VCTR28: MPCBBx vector register
	// Position of B896 field.
	GTZC_VCTR28_B896_Pos = 0x0
	// Bit mask of B896 field.
	GTZC_VCTR28_B896_Msk = 0x1
	// Bit B896.
	GTZC_VCTR28_B896 = 0x1
	// Position of B897 field.
	GTZC_VCTR28_B897_Pos = 0x1
	// Bit mask of B897 field.
	GTZC_VCTR28_B897_Msk = 0x2
	// Bit B897.
	GTZC_VCTR28_B897 = 0x2
	// Position of B898 field.
	GTZC_VCTR28_B898_Pos = 0x2
	// Bit mask of B898 field.
	GTZC_VCTR28_B898_Msk = 0x4
	// Bit B898.
	GTZC_VCTR28_B898 = 0x4
	// Position of B899 field.
	GTZC_VCTR28_B899_Pos = 0x3
	// Bit mask of B899 field.
	GTZC_VCTR28_B899_Msk = 0x8
	// Bit B899.
	GTZC_VCTR28_B899 = 0x8
	// Position of B900 field.
	GTZC_VCTR28_B900_Pos = 0x4
	// Bit mask of B900 field.
	GTZC_VCTR28_B900_Msk = 0x10
	// Bit B900.
	GTZC_VCTR28_B900 = 0x10
	// Position of B901 field.
	GTZC_VCTR28_B901_Pos = 0x5
	// Bit mask of B901 field.
	GTZC_VCTR28_B901_Msk = 0x20
	// Bit B901.
	GTZC_VCTR28_B901 = 0x20
	// Position of B902 field.
	GTZC_VCTR28_B902_Pos = 0x6
	// Bit mask of B902 field.
	GTZC_VCTR28_B902_Msk = 0x40
	// Bit B902.
	GTZC_VCTR28_B902 = 0x40
	// Position of B903 field.
	GTZC_VCTR28_B903_Pos = 0x7
	// Bit mask of B903 field.
	GTZC_VCTR28_B903_Msk = 0x80
	// Bit B903.
	GTZC_VCTR28_B903 = 0x80
	// Position of B904 field.
	GTZC_VCTR28_B904_Pos = 0x8
	// Bit mask of B904 field.
	GTZC_VCTR28_B904_Msk = 0x100
	// Bit B904.
	GTZC_VCTR28_B904 = 0x100
	// Position of B905 field.
	GTZC_VCTR28_B905_Pos = 0x9
	// Bit mask of B905 field.
	GTZC_VCTR28_B905_Msk = 0x200
	// Bit B905.
	GTZC_VCTR28_B905 = 0x200
	// Position of B906 field.
	GTZC_VCTR28_B906_Pos = 0xa
	// Bit mask of B906 field.
	GTZC_VCTR28_B906_Msk = 0x400
	// Bit B906.
	GTZC_VCTR28_B906 = 0x400
	// Position of B907 field.
	GTZC_VCTR28_B907_Pos = 0xb
	// Bit mask of B907 field.
	GTZC_VCTR28_B907_Msk = 0x800
	// Bit B907.
	GTZC_VCTR28_B907 = 0x800
	// Position of B908 field.
	GTZC_VCTR28_B908_Pos = 0xc
	// Bit mask of B908 field.
	GTZC_VCTR28_B908_Msk = 0x1000
	// Bit B908.
	GTZC_VCTR28_B908 = 0x1000
	// Position of B909 field.
	GTZC_VCTR28_B909_Pos = 0xd
	// Bit mask of B909 field.
	GTZC_VCTR28_B909_Msk = 0x2000
	// Bit B909.
	GTZC_VCTR28_B909 = 0x2000
	// Position of B910 field.
	GTZC_VCTR28_B910_Pos = 0xe
	// Bit mask of B910 field.
	GTZC_VCTR28_B910_Msk = 0x4000
	// Bit B910.
	GTZC_VCTR28_B910 = 0x4000
	// Position of B911 field.
	GTZC_VCTR28_B911_Pos = 0xf
	// Bit mask of B911 field.
	GTZC_VCTR28_B911_Msk = 0x8000
	// Bit B911.
	GTZC_VCTR28_B911 = 0x8000
	// Position of B912 field.
	GTZC_VCTR28_B912_Pos = 0x10
	// Bit mask of B912 field.
	GTZC_VCTR28_B912_Msk = 0x10000
	// Bit B912.
	GTZC_VCTR28_B912 = 0x10000
	// Position of B913 field.
	GTZC_VCTR28_B913_Pos = 0x11
	// Bit mask of B913 field.
	GTZC_VCTR28_B913_Msk = 0x20000
	// Bit B913.
	GTZC_VCTR28_B913 = 0x20000
	// Position of B914 field.
	GTZC_VCTR28_B914_Pos = 0x12
	// Bit mask of B914 field.
	GTZC_VCTR28_B914_Msk = 0x40000
	// Bit B914.
	GTZC_VCTR28_B914 = 0x40000
	// Position of B915 field.
	GTZC_VCTR28_B915_Pos = 0x13
	// Bit mask of B915 field.
	GTZC_VCTR28_B915_Msk = 0x80000
	// Bit B915.
	GTZC_VCTR28_B915 = 0x80000
	// Position of B916 field.
	GTZC_VCTR28_B916_Pos = 0x14
	// Bit mask of B916 field.
	GTZC_VCTR28_B916_Msk = 0x100000
	// Bit B916.
	GTZC_VCTR28_B916 = 0x100000
	// Position of B917 field.
	GTZC_VCTR28_B917_Pos = 0x15
	// Bit mask of B917 field.
	GTZC_VCTR28_B917_Msk = 0x200000
	// Bit B917.
	GTZC_VCTR28_B917 = 0x200000
	// Position of B918 field.
	GTZC_VCTR28_B918_Pos = 0x16
	// Bit mask of B918 field.
	GTZC_VCTR28_B918_Msk = 0x400000
	// Bit B918.
	GTZC_VCTR28_B918 = 0x400000
	// Position of B919 field.
	GTZC_VCTR28_B919_Pos = 0x17
	// Bit mask of B919 field.
	GTZC_VCTR28_B919_Msk = 0x800000
	// Bit B919.
	GTZC_VCTR28_B919 = 0x800000
	// Position of B920 field.
	GTZC_VCTR28_B920_Pos = 0x18
	// Bit mask of B920 field.
	GTZC_VCTR28_B920_Msk = 0x1000000
	// Bit B920.
	GTZC_VCTR28_B920 = 0x1000000
	// Position of B921 field.
	GTZC_VCTR28_B921_Pos = 0x19
	// Bit mask of B921 field.
	GTZC_VCTR28_B921_Msk = 0x2000000
	// Bit B921.
	GTZC_VCTR28_B921 = 0x2000000
	// Position of B922 field.
	GTZC_VCTR28_B922_Pos = 0x1a
	// Bit mask of B922 field.
	GTZC_VCTR28_B922_Msk = 0x4000000
	// Bit B922.
	GTZC_VCTR28_B922 = 0x4000000
	// Position of B923 field.
	GTZC_VCTR28_B923_Pos = 0x1b
	// Bit mask of B923 field.
	GTZC_VCTR28_B923_Msk = 0x8000000
	// Bit B923.
	GTZC_VCTR28_B923 = 0x8000000
	// Position of B924 field.
	GTZC_VCTR28_B924_Pos = 0x1c
	// Bit mask of B924 field.
	GTZC_VCTR28_B924_Msk = 0x10000000
	// Bit B924.
	GTZC_VCTR28_B924 = 0x10000000
	// Position of B925 field.
	GTZC_VCTR28_B925_Pos = 0x1d
	// Bit mask of B925 field.
	GTZC_VCTR28_B925_Msk = 0x20000000
	// Bit B925.
	GTZC_VCTR28_B925 = 0x20000000
	// Position of B926 field.
	GTZC_VCTR28_B926_Pos = 0x1e
	// Bit mask of B926 field.
	GTZC_VCTR28_B926_Msk = 0x40000000
	// Bit B926.
	GTZC_VCTR28_B926 = 0x40000000
	// Position of B927 field.
	GTZC_VCTR28_B927_Pos = 0x1f
	// Bit mask of B927 field.
	GTZC_VCTR28_B927_Msk = 0x80000000
	// Bit B927.
	GTZC_VCTR28_B927 = 0x80000000

	// VCTR29: MPCBBx vector register
	// Position of B928 field.
	GTZC_VCTR29_B928_Pos = 0x0
	// Bit mask of B928 field.
	GTZC_VCTR29_B928_Msk = 0x1
	// Bit B928.
	GTZC_VCTR29_B928 = 0x1
	// Position of B929 field.
	GTZC_VCTR29_B929_Pos = 0x1
	// Bit mask of B929 field.
	GTZC_VCTR29_B929_Msk = 0x2
	// Bit B929.
	GTZC_VCTR29_B929 = 0x2
	// Position of B930 field.
	GTZC_VCTR29_B930_Pos = 0x2
	// Bit mask of B930 field.
	GTZC_VCTR29_B930_Msk = 0x4
	// Bit B930.
	GTZC_VCTR29_B930 = 0x4
	// Position of B931 field.
	GTZC_VCTR29_B931_Pos = 0x3
	// Bit mask of B931 field.
	GTZC_VCTR29_B931_Msk = 0x8
	// Bit B931.
	GTZC_VCTR29_B931 = 0x8
	// Position of B932 field.
	GTZC_VCTR29_B932_Pos = 0x4
	// Bit mask of B932 field.
	GTZC_VCTR29_B932_Msk = 0x10
	// Bit B932.
	GTZC_VCTR29_B932 = 0x10
	// Position of B933 field.
	GTZC_VCTR29_B933_Pos = 0x5
	// Bit mask of B933 field.
	GTZC_VCTR29_B933_Msk = 0x20
	// Bit B933.
	GTZC_VCTR29_B933 = 0x20
	// Position of B934 field.
	GTZC_VCTR29_B934_Pos = 0x6
	// Bit mask of B934 field.
	GTZC_VCTR29_B934_Msk = 0x40
	// Bit B934.
	GTZC_VCTR29_B934 = 0x40
	// Position of B935 field.
	GTZC_VCTR29_B935_Pos = 0x7
	// Bit mask of B935 field.
	GTZC_VCTR29_B935_Msk = 0x80
	// Bit B935.
	GTZC_VCTR29_B935 = 0x80
	// Position of B936 field.
	GTZC_VCTR29_B936_Pos = 0x8
	// Bit mask of B936 field.
	GTZC_VCTR29_B936_Msk = 0x100
	// Bit B936.
	GTZC_VCTR29_B936 = 0x100
	// Position of B937 field.
	GTZC_VCTR29_B937_Pos = 0x9
	// Bit mask of B937 field.
	GTZC_VCTR29_B937_Msk = 0x200
	// Bit B937.
	GTZC_VCTR29_B937 = 0x200
	// Position of B938 field.
	GTZC_VCTR29_B938_Pos = 0xa
	// Bit mask of B938 field.
	GTZC_VCTR29_B938_Msk = 0x400
	// Bit B938.
	GTZC_VCTR29_B938 = 0x400
	// Position of B939 field.
	GTZC_VCTR29_B939_Pos = 0xb
	// Bit mask of B939 field.
	GTZC_VCTR29_B939_Msk = 0x800
	// Bit B939.
	GTZC_VCTR29_B939 = 0x800
	// Position of B940 field.
	GTZC_VCTR29_B940_Pos = 0xc
	// Bit mask of B940 field.
	GTZC_VCTR29_B940_Msk = 0x1000
	// Bit B940.
	GTZC_VCTR29_B940 = 0x1000
	// Position of B941 field.
	GTZC_VCTR29_B941_Pos = 0xd
	// Bit mask of B941 field.
	GTZC_VCTR29_B941_Msk = 0x2000
	// Bit B941.
	GTZC_VCTR29_B941 = 0x2000
	// Position of B942 field.
	GTZC_VCTR29_B942_Pos = 0xe
	// Bit mask of B942 field.
	GTZC_VCTR29_B942_Msk = 0x4000
	// Bit B942.
	GTZC_VCTR29_B942 = 0x4000
	// Position of B943 field.
	GTZC_VCTR29_B943_Pos = 0xf
	// Bit mask of B943 field.
	GTZC_VCTR29_B943_Msk = 0x8000
	// Bit B943.
	GTZC_VCTR29_B943 = 0x8000
	// Position of B944 field.
	GTZC_VCTR29_B944_Pos = 0x10
	// Bit mask of B944 field.
	GTZC_VCTR29_B944_Msk = 0x10000
	// Bit B944.
	GTZC_VCTR29_B944 = 0x10000
	// Position of B945 field.
	GTZC_VCTR29_B945_Pos = 0x11
	// Bit mask of B945 field.
	GTZC_VCTR29_B945_Msk = 0x20000
	// Bit B945.
	GTZC_VCTR29_B945 = 0x20000
	// Position of B946 field.
	GTZC_VCTR29_B946_Pos = 0x12
	// Bit mask of B946 field.
	GTZC_VCTR29_B946_Msk = 0x40000
	// Bit B946.
	GTZC_VCTR29_B946 = 0x40000
	// Position of B947 field.
	GTZC_VCTR29_B947_Pos = 0x13
	// Bit mask of B947 field.
	GTZC_VCTR29_B947_Msk = 0x80000
	// Bit B947.
	GTZC_VCTR29_B947 = 0x80000
	// Position of B948 field.
	GTZC_VCTR29_B948_Pos = 0x14
	// Bit mask of B948 field.
	GTZC_VCTR29_B948_Msk = 0x100000
	// Bit B948.
	GTZC_VCTR29_B948 = 0x100000
	// Position of B949 field.
	GTZC_VCTR29_B949_Pos = 0x15
	// Bit mask of B949 field.
	GTZC_VCTR29_B949_Msk = 0x200000
	// Bit B949.
	GTZC_VCTR29_B949 = 0x200000
	// Position of B950 field.
	GTZC_VCTR29_B950_Pos = 0x16
	// Bit mask of B950 field.
	GTZC_VCTR29_B950_Msk = 0x400000
	// Bit B950.
	GTZC_VCTR29_B950 = 0x400000
	// Position of B951 field.
	GTZC_VCTR29_B951_Pos = 0x17
	// Bit mask of B951 field.
	GTZC_VCTR29_B951_Msk = 0x800000
	// Bit B951.
	GTZC_VCTR29_B951 = 0x800000
	// Position of B952 field.
	GTZC_VCTR29_B952_Pos = 0x18
	// Bit mask of B952 field.
	GTZC_VCTR29_B952_Msk = 0x1000000
	// Bit B952.
	GTZC_VCTR29_B952 = 0x1000000
	// Position of B953 field.
	GTZC_VCTR29_B953_Pos = 0x19
	// Bit mask of B953 field.
	GTZC_VCTR29_B953_Msk = 0x2000000
	// Bit B953.
	GTZC_VCTR29_B953 = 0x2000000
	// Position of B954 field.
	GTZC_VCTR29_B954_Pos = 0x1a
	// Bit mask of B954 field.
	GTZC_VCTR29_B954_Msk = 0x4000000
	// Bit B954.
	GTZC_VCTR29_B954 = 0x4000000
	// Position of B955 field.
	GTZC_VCTR29_B955_Pos = 0x1b
	// Bit mask of B955 field.
	GTZC_VCTR29_B955_Msk = 0x8000000
	// Bit B955.
	GTZC_VCTR29_B955 = 0x8000000
	// Position of B956 field.
	GTZC_VCTR29_B956_Pos = 0x1c
	// Bit mask of B956 field.
	GTZC_VCTR29_B956_Msk = 0x10000000
	// Bit B956.
	GTZC_VCTR29_B956 = 0x10000000
	// Position of B957 field.
	GTZC_VCTR29_B957_Pos = 0x1d
	// Bit mask of B957 field.
	GTZC_VCTR29_B957_Msk = 0x20000000
	// Bit B957.
	GTZC_VCTR29_B957 = 0x20000000
	// Position of B958 field.
	GTZC_VCTR29_B958_Pos = 0x1e
	// Bit mask of B958 field.
	GTZC_VCTR29_B958_Msk = 0x40000000
	// Bit B958.
	GTZC_VCTR29_B958 = 0x40000000
	// Position of B959 field.
	GTZC_VCTR29_B959_Pos = 0x1f
	// Bit mask of B959 field.
	GTZC_VCTR29_B959_Msk = 0x80000000
	// Bit B959.
	GTZC_VCTR29_B959 = 0x80000000

	// VCTR30: MPCBBx vector register
	// Position of B960 field.
	GTZC_VCTR30_B960_Pos = 0x0
	// Bit mask of B960 field.
	GTZC_VCTR30_B960_Msk = 0x1
	// Bit B960.
	GTZC_VCTR30_B960 = 0x1
	// Position of B961 field.
	GTZC_VCTR30_B961_Pos = 0x1
	// Bit mask of B961 field.
	GTZC_VCTR30_B961_Msk = 0x2
	// Bit B961.
	GTZC_VCTR30_B961 = 0x2
	// Position of B962 field.
	GTZC_VCTR30_B962_Pos = 0x2
	// Bit mask of B962 field.
	GTZC_VCTR30_B962_Msk = 0x4
	// Bit B962.
	GTZC_VCTR30_B962 = 0x4
	// Position of B963 field.
	GTZC_VCTR30_B963_Pos = 0x3
	// Bit mask of B963 field.
	GTZC_VCTR30_B963_Msk = 0x8
	// Bit B963.
	GTZC_VCTR30_B963 = 0x8
	// Position of B964 field.
	GTZC_VCTR30_B964_Pos = 0x4
	// Bit mask of B964 field.
	GTZC_VCTR30_B964_Msk = 0x10
	// Bit B964.
	GTZC_VCTR30_B964 = 0x10
	// Position of B965 field.
	GTZC_VCTR30_B965_Pos = 0x5
	// Bit mask of B965 field.
	GTZC_VCTR30_B965_Msk = 0x20
	// Bit B965.
	GTZC_VCTR30_B965 = 0x20
	// Position of B966 field.
	GTZC_VCTR30_B966_Pos = 0x6
	// Bit mask of B966 field.
	GTZC_VCTR30_B966_Msk = 0x40
	// Bit B966.
	GTZC_VCTR30_B966 = 0x40
	// Position of B967 field.
	GTZC_VCTR30_B967_Pos = 0x7
	// Bit mask of B967 field.
	GTZC_VCTR30_B967_Msk = 0x80
	// Bit B967.
	GTZC_VCTR30_B967 = 0x80
	// Position of B968 field.
	GTZC_VCTR30_B968_Pos = 0x8
	// Bit mask of B968 field.
	GTZC_VCTR30_B968_Msk = 0x100
	// Bit B968.
	GTZC_VCTR30_B968 = 0x100
	// Position of B969 field.
	GTZC_VCTR30_B969_Pos = 0x9
	// Bit mask of B969 field.
	GTZC_VCTR30_B969_Msk = 0x200
	// Bit B969.
	GTZC_VCTR30_B969 = 0x200
	// Position of B970 field.
	GTZC_VCTR30_B970_Pos = 0xa
	// Bit mask of B970 field.
	GTZC_VCTR30_B970_Msk = 0x400
	// Bit B970.
	GTZC_VCTR30_B970 = 0x400
	// Position of B971 field.
	GTZC_VCTR30_B971_Pos = 0xb
	// Bit mask of B971 field.
	GTZC_VCTR30_B971_Msk = 0x800
	// Bit B971.
	GTZC_VCTR30_B971 = 0x800
	// Position of B972 field.
	GTZC_VCTR30_B972_Pos = 0xc
	// Bit mask of B972 field.
	GTZC_VCTR30_B972_Msk = 0x1000
	// Bit B972.
	GTZC_VCTR30_B972 = 0x1000
	// Position of B973 field.
	GTZC_VCTR30_B973_Pos = 0xd
	// Bit mask of B973 field.
	GTZC_VCTR30_B973_Msk = 0x2000
	// Bit B973.
	GTZC_VCTR30_B973 = 0x2000
	// Position of B974 field.
	GTZC_VCTR30_B974_Pos = 0xe
	// Bit mask of B974 field.
	GTZC_VCTR30_B974_Msk = 0x4000
	// Bit B974.
	GTZC_VCTR30_B974 = 0x4000
	// Position of B975 field.
	GTZC_VCTR30_B975_Pos = 0xf
	// Bit mask of B975 field.
	GTZC_VCTR30_B975_Msk = 0x8000
	// Bit B975.
	GTZC_VCTR30_B975 = 0x8000
	// Position of B976 field.
	GTZC_VCTR30_B976_Pos = 0x10
	// Bit mask of B976 field.
	GTZC_VCTR30_B976_Msk = 0x10000
	// Bit B976.
	GTZC_VCTR30_B976 = 0x10000
	// Position of B977 field.
	GTZC_VCTR30_B977_Pos = 0x11
	// Bit mask of B977 field.
	GTZC_VCTR30_B977_Msk = 0x20000
	// Bit B977.
	GTZC_VCTR30_B977 = 0x20000
	// Position of B978 field.
	GTZC_VCTR30_B978_Pos = 0x12
	// Bit mask of B978 field.
	GTZC_VCTR30_B978_Msk = 0x40000
	// Bit B978.
	GTZC_VCTR30_B978 = 0x40000
	// Position of B979 field.
	GTZC_VCTR30_B979_Pos = 0x13
	// Bit mask of B979 field.
	GTZC_VCTR30_B979_Msk = 0x80000
	// Bit B979.
	GTZC_VCTR30_B979 = 0x80000
	// Position of B980 field.
	GTZC_VCTR30_B980_Pos = 0x14
	// Bit mask of B980 field.
	GTZC_VCTR30_B980_Msk = 0x100000
	// Bit B980.
	GTZC_VCTR30_B980 = 0x100000
	// Position of B981 field.
	GTZC_VCTR30_B981_Pos = 0x15
	// Bit mask of B981 field.
	GTZC_VCTR30_B981_Msk = 0x200000
	// Bit B981.
	GTZC_VCTR30_B981 = 0x200000
	// Position of B982 field.
	GTZC_VCTR30_B982_Pos = 0x16
	// Bit mask of B982 field.
	GTZC_VCTR30_B982_Msk = 0x400000
	// Bit B982.
	GTZC_VCTR30_B982 = 0x400000
	// Position of B983 field.
	GTZC_VCTR30_B983_Pos = 0x17
	// Bit mask of B983 field.
	GTZC_VCTR30_B983_Msk = 0x800000
	// Bit B983.
	GTZC_VCTR30_B983 = 0x800000
	// Position of B984 field.
	GTZC_VCTR30_B984_Pos = 0x18
	// Bit mask of B984 field.
	GTZC_VCTR30_B984_Msk = 0x1000000
	// Bit B984.
	GTZC_VCTR30_B984 = 0x1000000
	// Position of B985 field.
	GTZC_VCTR30_B985_Pos = 0x19
	// Bit mask of B985 field.
	GTZC_VCTR30_B985_Msk = 0x2000000
	// Bit B985.
	GTZC_VCTR30_B985 = 0x2000000
	// Position of B986 field.
	GTZC_VCTR30_B986_Pos = 0x1a
	// Bit mask of B986 field.
	GTZC_VCTR30_B986_Msk = 0x4000000
	// Bit B986.
	GTZC_VCTR30_B986 = 0x4000000
	// Position of B987 field.
	GTZC_VCTR30_B987_Pos = 0x1b
	// Bit mask of B987 field.
	GTZC_VCTR30_B987_Msk = 0x8000000
	// Bit B987.
	GTZC_VCTR30_B987 = 0x8000000
	// Position of B988 field.
	GTZC_VCTR30_B988_Pos = 0x1c
	// Bit mask of B988 field.
	GTZC_VCTR30_B988_Msk = 0x10000000
	// Bit B988.
	GTZC_VCTR30_B988 = 0x10000000
	// Position of B989 field.
	GTZC_VCTR30_B989_Pos = 0x1d
	// Bit mask of B989 field.
	GTZC_VCTR30_B989_Msk = 0x20000000
	// Bit B989.
	GTZC_VCTR30_B989 = 0x20000000
	// Position of B990 field.
	GTZC_VCTR30_B990_Pos = 0x1e
	// Bit mask of B990 field.
	GTZC_VCTR30_B990_Msk = 0x40000000
	// Bit B990.
	GTZC_VCTR30_B990 = 0x40000000
	// Position of B991 field.
	GTZC_VCTR30_B991_Pos = 0x1f
	// Bit mask of B991 field.
	GTZC_VCTR30_B991_Msk = 0x80000000
	// Bit B991.
	GTZC_VCTR30_B991 = 0x80000000

	// VCTR31: MPCBBx vector register
	// Position of B992 field.
	GTZC_VCTR31_B992_Pos = 0x0
	// Bit mask of B992 field.
	GTZC_VCTR31_B992_Msk = 0x1
	// Bit B992.
	GTZC_VCTR31_B992 = 0x1
	// Position of B993 field.
	GTZC_VCTR31_B993_Pos = 0x1
	// Bit mask of B993 field.
	GTZC_VCTR31_B993_Msk = 0x2
	// Bit B993.
	GTZC_VCTR31_B993 = 0x2
	// Position of B994 field.
	GTZC_VCTR31_B994_Pos = 0x2
	// Bit mask of B994 field.
	GTZC_VCTR31_B994_Msk = 0x4
	// Bit B994.
	GTZC_VCTR31_B994 = 0x4
	// Position of B995 field.
	GTZC_VCTR31_B995_Pos = 0x3
	// Bit mask of B995 field.
	GTZC_VCTR31_B995_Msk = 0x8
	// Bit B995.
	GTZC_VCTR31_B995 = 0x8
	// Position of B996 field.
	GTZC_VCTR31_B996_Pos = 0x4
	// Bit mask of B996 field.
	GTZC_VCTR31_B996_Msk = 0x10
	// Bit B996.
	GTZC_VCTR31_B996 = 0x10
	// Position of B997 field.
	GTZC_VCTR31_B997_Pos = 0x5
	// Bit mask of B997 field.
	GTZC_VCTR31_B997_Msk = 0x20
	// Bit B997.
	GTZC_VCTR31_B997 = 0x20
	// Position of B998 field.
	GTZC_VCTR31_B998_Pos = 0x6
	// Bit mask of B998 field.
	GTZC_VCTR31_B998_Msk = 0x40
	// Bit B998.
	GTZC_VCTR31_B998 = 0x40
	// Position of B999 field.
	GTZC_VCTR31_B999_Pos = 0x7
	// Bit mask of B999 field.
	GTZC_VCTR31_B999_Msk = 0x80
	// Bit B999.
	GTZC_VCTR31_B999 = 0x80
	// Position of B1000 field.
	GTZC_VCTR31_B1000_Pos = 0x8
	// Bit mask of B1000 field.
	GTZC_VCTR31_B1000_Msk = 0x100
	// Bit B1000.
	GTZC_VCTR31_B1000 = 0x100
	// Position of B1001 field.
	GTZC_VCTR31_B1001_Pos = 0x9
	// Bit mask of B1001 field.
	GTZC_VCTR31_B1001_Msk = 0x200
	// Bit B1001.
	GTZC_VCTR31_B1001 = 0x200
	// Position of B1002 field.
	GTZC_VCTR31_B1002_Pos = 0xa
	// Bit mask of B1002 field.
	GTZC_VCTR31_B1002_Msk = 0x400
	// Bit B1002.
	GTZC_VCTR31_B1002 = 0x400
	// Position of B1003 field.
	GTZC_VCTR31_B1003_Pos = 0xb
	// Bit mask of B1003 field.
	GTZC_VCTR31_B1003_Msk = 0x800
	// Bit B1003.
	GTZC_VCTR31_B1003 = 0x800
	// Position of B1004 field.
	GTZC_VCTR31_B1004_Pos = 0xc
	// Bit mask of B1004 field.
	GTZC_VCTR31_B1004_Msk = 0x1000
	// Bit B1004.
	GTZC_VCTR31_B1004 = 0x1000
	// Position of B1005 field.
	GTZC_VCTR31_B1005_Pos = 0xd
	// Bit mask of B1005 field.
	GTZC_VCTR31_B1005_Msk = 0x2000
	// Bit B1005.
	GTZC_VCTR31_B1005 = 0x2000
	// Position of B1006 field.
	GTZC_VCTR31_B1006_Pos = 0xe
	// Bit mask of B1006 field.
	GTZC_VCTR31_B1006_Msk = 0x4000
	// Bit B1006.
	GTZC_VCTR31_B1006 = 0x4000
	// Position of B1007 field.
	GTZC_VCTR31_B1007_Pos = 0xf
	// Bit mask of B1007 field.
	GTZC_VCTR31_B1007_Msk = 0x8000
	// Bit B1007.
	GTZC_VCTR31_B1007 = 0x8000
	// Position of B1008 field.
	GTZC_VCTR31_B1008_Pos = 0x10
	// Bit mask of B1008 field.
	GTZC_VCTR31_B1008_Msk = 0x10000
	// Bit B1008.
	GTZC_VCTR31_B1008 = 0x10000
	// Position of B1009 field.
	GTZC_VCTR31_B1009_Pos = 0x11
	// Bit mask of B1009 field.
	GTZC_VCTR31_B1009_Msk = 0x20000
	// Bit B1009.
	GTZC_VCTR31_B1009 = 0x20000
	// Position of B1010 field.
	GTZC_VCTR31_B1010_Pos = 0x12
	// Bit mask of B1010 field.
	GTZC_VCTR31_B1010_Msk = 0x40000
	// Bit B1010.
	GTZC_VCTR31_B1010 = 0x40000
	// Position of B1011 field.
	GTZC_VCTR31_B1011_Pos = 0x13
	// Bit mask of B1011 field.
	GTZC_VCTR31_B1011_Msk = 0x80000
	// Bit B1011.
	GTZC_VCTR31_B1011 = 0x80000
	// Position of B1012 field.
	GTZC_VCTR31_B1012_Pos = 0x14
	// Bit mask of B1012 field.
	GTZC_VCTR31_B1012_Msk = 0x100000
	// Bit B1012.
	GTZC_VCTR31_B1012 = 0x100000
	// Position of B1013 field.
	GTZC_VCTR31_B1013_Pos = 0x15
	// Bit mask of B1013 field.
	GTZC_VCTR31_B1013_Msk = 0x200000
	// Bit B1013.
	GTZC_VCTR31_B1013 = 0x200000
	// Position of B1014 field.
	GTZC_VCTR31_B1014_Pos = 0x16
	// Bit mask of B1014 field.
	GTZC_VCTR31_B1014_Msk = 0x400000
	// Bit B1014.
	GTZC_VCTR31_B1014 = 0x400000
	// Position of B1015 field.
	GTZC_VCTR31_B1015_Pos = 0x17
	// Bit mask of B1015 field.
	GTZC_VCTR31_B1015_Msk = 0x800000
	// Bit B1015.
	GTZC_VCTR31_B1015 = 0x800000
	// Position of B1016 field.
	GTZC_VCTR31_B1016_Pos = 0x18
	// Bit mask of B1016 field.
	GTZC_VCTR31_B1016_Msk = 0x1000000
	// Bit B1016.
	GTZC_VCTR31_B1016 = 0x1000000
	// Position of B1017 field.
	GTZC_VCTR31_B1017_Pos = 0x19
	// Bit mask of B1017 field.
	GTZC_VCTR31_B1017_Msk = 0x2000000
	// Bit B1017.
	GTZC_VCTR31_B1017 = 0x2000000
	// Position of B1018 field.
	GTZC_VCTR31_B1018_Pos = 0x1a
	// Bit mask of B1018 field.
	GTZC_VCTR31_B1018_Msk = 0x4000000
	// Bit B1018.
	GTZC_VCTR31_B1018 = 0x4000000
	// Position of B1019 field.
	GTZC_VCTR31_B1019_Pos = 0x1b
	// Bit mask of B1019 field.
	GTZC_VCTR31_B1019_Msk = 0x8000000
	// Bit B1019.
	GTZC_VCTR31_B1019 = 0x8000000
	// Position of B1020 field.
	GTZC_VCTR31_B1020_Pos = 0x1c
	// Bit mask of B1020 field.
	GTZC_VCTR31_B1020_Msk = 0x10000000
	// Bit B1020.
	GTZC_VCTR31_B1020 = 0x10000000
	// Position of B1021 field.
	GTZC_VCTR31_B1021_Pos = 0x1d
	// Bit mask of B1021 field.
	GTZC_VCTR31_B1021_Msk = 0x20000000
	// Bit B1021.
	GTZC_VCTR31_B1021 = 0x20000000
	// Position of B1022 field.
	GTZC_VCTR31_B1022_Pos = 0x1e
	// Bit mask of B1022 field.
	GTZC_VCTR31_B1022_Msk = 0x40000000
	// Bit B1022.
	GTZC_VCTR31_B1022 = 0x40000000
	// Position of B1023 field.
	GTZC_VCTR31_B1023_Pos = 0x1f
	// Bit mask of B1023 field.
	GTZC_VCTR31_B1023_Msk = 0x80000000
	// Bit B1023.
	GTZC_VCTR31_B1023 = 0x80000000

	// VCTR32: MPCBBx vector register
	// Position of B1024 field.
	GTZC_VCTR32_B1024_Pos = 0x0
	// Bit mask of B1024 field.
	GTZC_VCTR32_B1024_Msk = 0x1
	// Bit B1024.
	GTZC_VCTR32_B1024 = 0x1
	// Position of B1025 field.
	GTZC_VCTR32_B1025_Pos = 0x1
	// Bit mask of B1025 field.
	GTZC_VCTR32_B1025_Msk = 0x2
	// Bit B1025.
	GTZC_VCTR32_B1025 = 0x2
	// Position of B1026 field.
	GTZC_VCTR32_B1026_Pos = 0x2
	// Bit mask of B1026 field.
	GTZC_VCTR32_B1026_Msk = 0x4
	// Bit B1026.
	GTZC_VCTR32_B1026 = 0x4
	// Position of B1027 field.
	GTZC_VCTR32_B1027_Pos = 0x3
	// Bit mask of B1027 field.
	GTZC_VCTR32_B1027_Msk = 0x8
	// Bit B1027.
	GTZC_VCTR32_B1027 = 0x8
	// Position of B1028 field.
	GTZC_VCTR32_B1028_Pos = 0x4
	// Bit mask of B1028 field.
	GTZC_VCTR32_B1028_Msk = 0x10
	// Bit B1028.
	GTZC_VCTR32_B1028 = 0x10
	// Position of B1029 field.
	GTZC_VCTR32_B1029_Pos = 0x5
	// Bit mask of B1029 field.
	GTZC_VCTR32_B1029_Msk = 0x20
	// Bit B1029.
	GTZC_VCTR32_B1029 = 0x20
	// Position of B1030 field.
	GTZC_VCTR32_B1030_Pos = 0x6
	// Bit mask of B1030 field.
	GTZC_VCTR32_B1030_Msk = 0x40
	// Bit B1030.
	GTZC_VCTR32_B1030 = 0x40
	// Position of B1031 field.
	GTZC_VCTR32_B1031_Pos = 0x7
	// Bit mask of B1031 field.
	GTZC_VCTR32_B1031_Msk = 0x80
	// Bit B1031.
	GTZC_VCTR32_B1031 = 0x80
	// Position of B1032 field.
	GTZC_VCTR32_B1032_Pos = 0x8
	// Bit mask of B1032 field.
	GTZC_VCTR32_B1032_Msk = 0x100
	// Bit B1032.
	GTZC_VCTR32_B1032 = 0x100
	// Position of B1033 field.
	GTZC_VCTR32_B1033_Pos = 0x9
	// Bit mask of B1033 field.
	GTZC_VCTR32_B1033_Msk = 0x200
	// Bit B1033.
	GTZC_VCTR32_B1033 = 0x200
	// Position of B1034 field.
	GTZC_VCTR32_B1034_Pos = 0xa
	// Bit mask of B1034 field.
	GTZC_VCTR32_B1034_Msk = 0x400
	// Bit B1034.
	GTZC_VCTR32_B1034 = 0x400
	// Position of B1035 field.
	GTZC_VCTR32_B1035_Pos = 0xb
	// Bit mask of B1035 field.
	GTZC_VCTR32_B1035_Msk = 0x800
	// Bit B1035.
	GTZC_VCTR32_B1035 = 0x800
	// Position of B1036 field.
	GTZC_VCTR32_B1036_Pos = 0xc
	// Bit mask of B1036 field.
	GTZC_VCTR32_B1036_Msk = 0x1000
	// Bit B1036.
	GTZC_VCTR32_B1036 = 0x1000
	// Position of B1037 field.
	GTZC_VCTR32_B1037_Pos = 0xd
	// Bit mask of B1037 field.
	GTZC_VCTR32_B1037_Msk = 0x2000
	// Bit B1037.
	GTZC_VCTR32_B1037 = 0x2000
	// Position of B1038 field.
	GTZC_VCTR32_B1038_Pos = 0xe
	// Bit mask of B1038 field.
	GTZC_VCTR32_B1038_Msk = 0x4000
	// Bit B1038.
	GTZC_VCTR32_B1038 = 0x4000
	// Position of B1039 field.
	GTZC_VCTR32_B1039_Pos = 0xf
	// Bit mask of B1039 field.
	GTZC_VCTR32_B1039_Msk = 0x8000
	// Bit B1039.
	GTZC_VCTR32_B1039 = 0x8000
	// Position of B1040 field.
	GTZC_VCTR32_B1040_Pos = 0x10
	// Bit mask of B1040 field.
	GTZC_VCTR32_B1040_Msk = 0x10000
	// Bit B1040.
	GTZC_VCTR32_B1040 = 0x10000
	// Position of B1041 field.
	GTZC_VCTR32_B1041_Pos = 0x11
	// Bit mask of B1041 field.
	GTZC_VCTR32_B1041_Msk = 0x20000
	// Bit B1041.
	GTZC_VCTR32_B1041 = 0x20000
	// Position of B1042 field.
	GTZC_VCTR32_B1042_Pos = 0x12
	// Bit mask of B1042 field.
	GTZC_VCTR32_B1042_Msk = 0x40000
	// Bit B1042.
	GTZC_VCTR32_B1042 = 0x40000
	// Position of B1043 field.
	GTZC_VCTR32_B1043_Pos = 0x13
	// Bit mask of B1043 field.
	GTZC_VCTR32_B1043_Msk = 0x80000
	// Bit B1043.
	GTZC_VCTR32_B1043 = 0x80000
	// Position of B1044 field.
	GTZC_VCTR32_B1044_Pos = 0x14
	// Bit mask of B1044 field.
	GTZC_VCTR32_B1044_Msk = 0x100000
	// Bit B1044.
	GTZC_VCTR32_B1044 = 0x100000
	// Position of B1045 field.
	GTZC_VCTR32_B1045_Pos = 0x15
	// Bit mask of B1045 field.
	GTZC_VCTR32_B1045_Msk = 0x200000
	// Bit B1045.
	GTZC_VCTR32_B1045 = 0x200000
	// Position of B1046 field.
	GTZC_VCTR32_B1046_Pos = 0x16
	// Bit mask of B1046 field.
	GTZC_VCTR32_B1046_Msk = 0x400000
	// Bit B1046.
	GTZC_VCTR32_B1046 = 0x400000
	// Position of B1047 field.
	GTZC_VCTR32_B1047_Pos = 0x17
	// Bit mask of B1047 field.
	GTZC_VCTR32_B1047_Msk = 0x800000
	// Bit B1047.
	GTZC_VCTR32_B1047 = 0x800000
	// Position of B1048 field.
	GTZC_VCTR32_B1048_Pos = 0x18
	// Bit mask of B1048 field.
	GTZC_VCTR32_B1048_Msk = 0x1000000
	// Bit B1048.
	GTZC_VCTR32_B1048 = 0x1000000
	// Position of B1049 field.
	GTZC_VCTR32_B1049_Pos = 0x19
	// Bit mask of B1049 field.
	GTZC_VCTR32_B1049_Msk = 0x2000000
	// Bit B1049.
	GTZC_VCTR32_B1049 = 0x2000000
	// Position of B1050 field.
	GTZC_VCTR32_B1050_Pos = 0x1a
	// Bit mask of B1050 field.
	GTZC_VCTR32_B1050_Msk = 0x4000000
	// Bit B1050.
	GTZC_VCTR32_B1050 = 0x4000000
	// Position of B1051 field.
	GTZC_VCTR32_B1051_Pos = 0x1b
	// Bit mask of B1051 field.
	GTZC_VCTR32_B1051_Msk = 0x8000000
	// Bit B1051.
	GTZC_VCTR32_B1051 = 0x8000000
	// Position of B1052 field.
	GTZC_VCTR32_B1052_Pos = 0x1c
	// Bit mask of B1052 field.
	GTZC_VCTR32_B1052_Msk = 0x10000000
	// Bit B1052.
	GTZC_VCTR32_B1052 = 0x10000000
	// Position of B1053 field.
	GTZC_VCTR32_B1053_Pos = 0x1d
	// Bit mask of B1053 field.
	GTZC_VCTR32_B1053_Msk = 0x20000000
	// Bit B1053.
	GTZC_VCTR32_B1053 = 0x20000000
	// Position of B1054 field.
	GTZC_VCTR32_B1054_Pos = 0x1e
	// Bit mask of B1054 field.
	GTZC_VCTR32_B1054_Msk = 0x40000000
	// Bit B1054.
	GTZC_VCTR32_B1054 = 0x40000000
	// Position of B1055 field.
	GTZC_VCTR32_B1055_Pos = 0x1f
	// Bit mask of B1055 field.
	GTZC_VCTR32_B1055_Msk = 0x80000000
	// Bit B1055.
	GTZC_VCTR32_B1055 = 0x80000000

	// VCTR33: MPCBBx vector register
	// Position of B1056 field.
	GTZC_VCTR33_B1056_Pos = 0x0
	// Bit mask of B1056 field.
	GTZC_VCTR33_B1056_Msk = 0x1
	// Bit B1056.
	GTZC_VCTR33_B1056 = 0x1
	// Position of B1057 field.
	GTZC_VCTR33_B1057_Pos = 0x1
	// Bit mask of B1057 field.
	GTZC_VCTR33_B1057_Msk = 0x2
	// Bit B1057.
	GTZC_VCTR33_B1057 = 0x2
	// Position of B1058 field.
	GTZC_VCTR33_B1058_Pos = 0x2
	// Bit mask of B1058 field.
	GTZC_VCTR33_B1058_Msk = 0x4
	// Bit B1058.
	GTZC_VCTR33_B1058 = 0x4
	// Position of B1059 field.
	GTZC_VCTR33_B1059_Pos = 0x3
	// Bit mask of B1059 field.
	GTZC_VCTR33_B1059_Msk = 0x8
	// Bit B1059.
	GTZC_VCTR33_B1059 = 0x8
	// Position of B1060 field.
	GTZC_VCTR33_B1060_Pos = 0x4
	// Bit mask of B1060 field.
	GTZC_VCTR33_B1060_Msk = 0x10
	// Bit B1060.
	GTZC_VCTR33_B1060 = 0x10
	// Position of B1061 field.
	GTZC_VCTR33_B1061_Pos = 0x5
	// Bit mask of B1061 field.
	GTZC_VCTR33_B1061_Msk = 0x20
	// Bit B1061.
	GTZC_VCTR33_B1061 = 0x20
	// Position of B1062 field.
	GTZC_VCTR33_B1062_Pos = 0x6
	// Bit mask of B1062 field.
	GTZC_VCTR33_B1062_Msk = 0x40
	// Bit B1062.
	GTZC_VCTR33_B1062 = 0x40
	// Position of B1063 field.
	GTZC_VCTR33_B1063_Pos = 0x7
	// Bit mask of B1063 field.
	GTZC_VCTR33_B1063_Msk = 0x80
	// Bit B1063.
	GTZC_VCTR33_B1063 = 0x80
	// Position of B1064 field.
	GTZC_VCTR33_B1064_Pos = 0x8
	// Bit mask of B1064 field.
	GTZC_VCTR33_B1064_Msk = 0x100
	// Bit B1064.
	GTZC_VCTR33_B1064 = 0x100
	// Position of B1065 field.
	GTZC_VCTR33_B1065_Pos = 0x9
	// Bit mask of B1065 field.
	GTZC_VCTR33_B1065_Msk = 0x200
	// Bit B1065.
	GTZC_VCTR33_B1065 = 0x200
	// Position of B1066 field.
	GTZC_VCTR33_B1066_Pos = 0xa
	// Bit mask of B1066 field.
	GTZC_VCTR33_B1066_Msk = 0x400
	// Bit B1066.
	GTZC_VCTR33_B1066 = 0x400
	// Position of B1067 field.
	GTZC_VCTR33_B1067_Pos = 0xb
	// Bit mask of B1067 field.
	GTZC_VCTR33_B1067_Msk = 0x800
	// Bit B1067.
	GTZC_VCTR33_B1067 = 0x800
	// Position of B1068 field.
	GTZC_VCTR33_B1068_Pos = 0xc
	// Bit mask of B1068 field.
	GTZC_VCTR33_B1068_Msk = 0x1000
	// Bit B1068.
	GTZC_VCTR33_B1068 = 0x1000
	// Position of B1069 field.
	GTZC_VCTR33_B1069_Pos = 0xd
	// Bit mask of B1069 field.
	GTZC_VCTR33_B1069_Msk = 0x2000
	// Bit B1069.
	GTZC_VCTR33_B1069 = 0x2000
	// Position of B1070 field.
	GTZC_VCTR33_B1070_Pos = 0xe
	// Bit mask of B1070 field.
	GTZC_VCTR33_B1070_Msk = 0x4000
	// Bit B1070.
	GTZC_VCTR33_B1070 = 0x4000
	// Position of B1071 field.
	GTZC_VCTR33_B1071_Pos = 0xf
	// Bit mask of B1071 field.
	GTZC_VCTR33_B1071_Msk = 0x8000
	// Bit B1071.
	GTZC_VCTR33_B1071 = 0x8000
	// Position of B1072 field.
	GTZC_VCTR33_B1072_Pos = 0x10
	// Bit mask of B1072 field.
	GTZC_VCTR33_B1072_Msk = 0x10000
	// Bit B1072.
	GTZC_VCTR33_B1072 = 0x10000
	// Position of B1073 field.
	GTZC_VCTR33_B1073_Pos = 0x11
	// Bit mask of B1073 field.
	GTZC_VCTR33_B1073_Msk = 0x20000
	// Bit B1073.
	GTZC_VCTR33_B1073 = 0x20000
	// Position of B1074 field.
	GTZC_VCTR33_B1074_Pos = 0x12
	// Bit mask of B1074 field.
	GTZC_VCTR33_B1074_Msk = 0x40000
	// Bit B1074.
	GTZC_VCTR33_B1074 = 0x40000
	// Position of B1075 field.
	GTZC_VCTR33_B1075_Pos = 0x13
	// Bit mask of B1075 field.
	GTZC_VCTR33_B1075_Msk = 0x80000
	// Bit B1075.
	GTZC_VCTR33_B1075 = 0x80000
	// Position of B1076 field.
	GTZC_VCTR33_B1076_Pos = 0x14
	// Bit mask of B1076 field.
	GTZC_VCTR33_B1076_Msk = 0x100000
	// Bit B1076.
	GTZC_VCTR33_B1076 = 0x100000
	// Position of B1077 field.
	GTZC_VCTR33_B1077_Pos = 0x15
	// Bit mask of B1077 field.
	GTZC_VCTR33_B1077_Msk = 0x200000
	// Bit B1077.
	GTZC_VCTR33_B1077 = 0x200000
	// Position of B1078 field.
	GTZC_VCTR33_B1078_Pos = 0x16
	// Bit mask of B1078 field.
	GTZC_VCTR33_B1078_Msk = 0x400000
	// Bit B1078.
	GTZC_VCTR33_B1078 = 0x400000
	// Position of B1079 field.
	GTZC_VCTR33_B1079_Pos = 0x17
	// Bit mask of B1079 field.
	GTZC_VCTR33_B1079_Msk = 0x800000
	// Bit B1079.
	GTZC_VCTR33_B1079 = 0x800000
	// Position of B1080 field.
	GTZC_VCTR33_B1080_Pos = 0x18
	// Bit mask of B1080 field.
	GTZC_VCTR33_B1080_Msk = 0x1000000
	// Bit B1080.
	GTZC_VCTR33_B1080 = 0x1000000
	// Position of B1081 field.
	GTZC_VCTR33_B1081_Pos = 0x19
	// Bit mask of B1081 field.
	GTZC_VCTR33_B1081_Msk = 0x2000000
	// Bit B1081.
	GTZC_VCTR33_B1081 = 0x2000000
	// Position of B1082 field.
	GTZC_VCTR33_B1082_Pos = 0x1a
	// Bit mask of B1082 field.
	GTZC_VCTR33_B1082_Msk = 0x4000000
	// Bit B1082.
	GTZC_VCTR33_B1082 = 0x4000000
	// Position of B1083 field.
	GTZC_VCTR33_B1083_Pos = 0x1b
	// Bit mask of B1083 field.
	GTZC_VCTR33_B1083_Msk = 0x8000000
	// Bit B1083.
	GTZC_VCTR33_B1083 = 0x8000000
	// Position of B1084 field.
	GTZC_VCTR33_B1084_Pos = 0x1c
	// Bit mask of B1084 field.
	GTZC_VCTR33_B1084_Msk = 0x10000000
	// Bit B1084.
	GTZC_VCTR33_B1084 = 0x10000000
	// Position of B1085 field.
	GTZC_VCTR33_B1085_Pos = 0x1d
	// Bit mask of B1085 field.
	GTZC_VCTR33_B1085_Msk = 0x20000000
	// Bit B1085.
	GTZC_VCTR33_B1085 = 0x20000000
	// Position of B1086 field.
	GTZC_VCTR33_B1086_Pos = 0x1e
	// Bit mask of B1086 field.
	GTZC_VCTR33_B1086_Msk = 0x40000000
	// Bit B1086.
	GTZC_VCTR33_B1086 = 0x40000000
	// Position of B1087 field.
	GTZC_VCTR33_B1087_Pos = 0x1f
	// Bit mask of B1087 field.
	GTZC_VCTR33_B1087_Msk = 0x80000000
	// Bit B1087.
	GTZC_VCTR33_B1087 = 0x80000000

	// VCTR34: MPCBBx vector register
	// Position of B1088 field.
	GTZC_VCTR34_B1088_Pos = 0x0
	// Bit mask of B1088 field.
	GTZC_VCTR34_B1088_Msk = 0x1
	// Bit B1088.
	GTZC_VCTR34_B1088 = 0x1
	// Position of B1089 field.
	GTZC_VCTR34_B1089_Pos = 0x1
	// Bit mask of B1089 field.
	GTZC_VCTR34_B1089_Msk = 0x2
	// Bit B1089.
	GTZC_VCTR34_B1089 = 0x2
	// Position of B1090 field.
	GTZC_VCTR34_B1090_Pos = 0x2
	// Bit mask of B1090 field.
	GTZC_VCTR34_B1090_Msk = 0x4
	// Bit B1090.
	GTZC_VCTR34_B1090 = 0x4
	// Position of B1091 field.
	GTZC_VCTR34_B1091_Pos = 0x3
	// Bit mask of B1091 field.
	GTZC_VCTR34_B1091_Msk = 0x8
	// Bit B1091.
	GTZC_VCTR34_B1091 = 0x8
	// Position of B1092 field.
	GTZC_VCTR34_B1092_Pos = 0x4
	// Bit mask of B1092 field.
	GTZC_VCTR34_B1092_Msk = 0x10
	// Bit B1092.
	GTZC_VCTR34_B1092 = 0x10
	// Position of B1093 field.
	GTZC_VCTR34_B1093_Pos = 0x5
	// Bit mask of B1093 field.
	GTZC_VCTR34_B1093_Msk = 0x20
	// Bit B1093.
	GTZC_VCTR34_B1093 = 0x20
	// Position of B1094 field.
	GTZC_VCTR34_B1094_Pos = 0x6
	// Bit mask of B1094 field.
	GTZC_VCTR34_B1094_Msk = 0x40
	// Bit B1094.
	GTZC_VCTR34_B1094 = 0x40
	// Position of B1095 field.
	GTZC_VCTR34_B1095_Pos = 0x7
	// Bit mask of B1095 field.
	GTZC_VCTR34_B1095_Msk = 0x80
	// Bit B1095.
	GTZC_VCTR34_B1095 = 0x80
	// Position of B1096 field.
	GTZC_VCTR34_B1096_Pos = 0x8
	// Bit mask of B1096 field.
	GTZC_VCTR34_B1096_Msk = 0x100
	// Bit B1096.
	GTZC_VCTR34_B1096 = 0x100
	// Position of B1097 field.
	GTZC_VCTR34_B1097_Pos = 0x9
	// Bit mask of B1097 field.
	GTZC_VCTR34_B1097_Msk = 0x200
	// Bit B1097.
	GTZC_VCTR34_B1097 = 0x200
	// Position of B1098 field.
	GTZC_VCTR34_B1098_Pos = 0xa
	// Bit mask of B1098 field.
	GTZC_VCTR34_B1098_Msk = 0x400
	// Bit B1098.
	GTZC_VCTR34_B1098 = 0x400
	// Position of B1099 field.
	GTZC_VCTR34_B1099_Pos = 0xb
	// Bit mask of B1099 field.
	GTZC_VCTR34_B1099_Msk = 0x800
	// Bit B1099.
	GTZC_VCTR34_B1099 = 0x800
	// Position of B1100 field.
	GTZC_VCTR34_B1100_Pos = 0xc
	// Bit mask of B1100 field.
	GTZC_VCTR34_B1100_Msk = 0x1000
	// Bit B1100.
	GTZC_VCTR34_B1100 = 0x1000
	// Position of B1101 field.
	GTZC_VCTR34_B1101_Pos = 0xd
	// Bit mask of B1101 field.
	GTZC_VCTR34_B1101_Msk = 0x2000
	// Bit B1101.
	GTZC_VCTR34_B1101 = 0x2000
	// Position of B1102 field.
	GTZC_VCTR34_B1102_Pos = 0xe
	// Bit mask of B1102 field.
	GTZC_VCTR34_B1102_Msk = 0x4000
	// Bit B1102.
	GTZC_VCTR34_B1102 = 0x4000
	// Position of B1103 field.
	GTZC_VCTR34_B1103_Pos = 0xf
	// Bit mask of B1103 field.
	GTZC_VCTR34_B1103_Msk = 0x8000
	// Bit B1103.
	GTZC_VCTR34_B1103 = 0x8000
	// Position of B1104 field.
	GTZC_VCTR34_B1104_Pos = 0x10
	// Bit mask of B1104 field.
	GTZC_VCTR34_B1104_Msk = 0x10000
	// Bit B1104.
	GTZC_VCTR34_B1104 = 0x10000
	// Position of B1105 field.
	GTZC_VCTR34_B1105_Pos = 0x11
	// Bit mask of B1105 field.
	GTZC_VCTR34_B1105_Msk = 0x20000
	// Bit B1105.
	GTZC_VCTR34_B1105 = 0x20000
	// Position of B1106 field.
	GTZC_VCTR34_B1106_Pos = 0x12
	// Bit mask of B1106 field.
	GTZC_VCTR34_B1106_Msk = 0x40000
	// Bit B1106.
	GTZC_VCTR34_B1106 = 0x40000
	// Position of B1107 field.
	GTZC_VCTR34_B1107_Pos = 0x13
	// Bit mask of B1107 field.
	GTZC_VCTR34_B1107_Msk = 0x80000
	// Bit B1107.
	GTZC_VCTR34_B1107 = 0x80000
	// Position of B1108 field.
	GTZC_VCTR34_B1108_Pos = 0x14
	// Bit mask of B1108 field.
	GTZC_VCTR34_B1108_Msk = 0x100000
	// Bit B1108.
	GTZC_VCTR34_B1108 = 0x100000
	// Position of B1109 field.
	GTZC_VCTR34_B1109_Pos = 0x15
	// Bit mask of B1109 field.
	GTZC_VCTR34_B1109_Msk = 0x200000
	// Bit B1109.
	GTZC_VCTR34_B1109 = 0x200000
	// Position of B1110 field.
	GTZC_VCTR34_B1110_Pos = 0x16
	// Bit mask of B1110 field.
	GTZC_VCTR34_B1110_Msk = 0x400000
	// Bit B1110.
	GTZC_VCTR34_B1110 = 0x400000
	// Position of B1111 field.
	GTZC_VCTR34_B1111_Pos = 0x17
	// Bit mask of B1111 field.
	GTZC_VCTR34_B1111_Msk = 0x800000
	// Bit B1111.
	GTZC_VCTR34_B1111 = 0x800000
	// Position of B1112 field.
	GTZC_VCTR34_B1112_Pos = 0x18
	// Bit mask of B1112 field.
	GTZC_VCTR34_B1112_Msk = 0x1000000
	// Bit B1112.
	GTZC_VCTR34_B1112 = 0x1000000
	// Position of B1113 field.
	GTZC_VCTR34_B1113_Pos = 0x19
	// Bit mask of B1113 field.
	GTZC_VCTR34_B1113_Msk = 0x2000000
	// Bit B1113.
	GTZC_VCTR34_B1113 = 0x2000000
	// Position of B1114 field.
	GTZC_VCTR34_B1114_Pos = 0x1a
	// Bit mask of B1114 field.
	GTZC_VCTR34_B1114_Msk = 0x4000000
	// Bit B1114.
	GTZC_VCTR34_B1114 = 0x4000000
	// Position of B1115 field.
	GTZC_VCTR34_B1115_Pos = 0x1b
	// Bit mask of B1115 field.
	GTZC_VCTR34_B1115_Msk = 0x8000000
	// Bit B1115.
	GTZC_VCTR34_B1115 = 0x8000000
	// Position of B1116 field.
	GTZC_VCTR34_B1116_Pos = 0x1c
	// Bit mask of B1116 field.
	GTZC_VCTR34_B1116_Msk = 0x10000000
	// Bit B1116.
	GTZC_VCTR34_B1116 = 0x10000000
	// Position of B1117 field.
	GTZC_VCTR34_B1117_Pos = 0x1d
	// Bit mask of B1117 field.
	GTZC_VCTR34_B1117_Msk = 0x20000000
	// Bit B1117.
	GTZC_VCTR34_B1117 = 0x20000000
	// Position of B1118 field.
	GTZC_VCTR34_B1118_Pos = 0x1e
	// Bit mask of B1118 field.
	GTZC_VCTR34_B1118_Msk = 0x40000000
	// Bit B1118.
	GTZC_VCTR34_B1118 = 0x40000000
	// Position of B1119 field.
	GTZC_VCTR34_B1119_Pos = 0x1f
	// Bit mask of B1119 field.
	GTZC_VCTR34_B1119_Msk = 0x80000000
	// Bit B1119.
	GTZC_VCTR34_B1119 = 0x80000000

	// VCTR35: MPCBBx vector register
	// Position of B1120 field.
	GTZC_VCTR35_B1120_Pos = 0x0
	// Bit mask of B1120 field.
	GTZC_VCTR35_B1120_Msk = 0x1
	// Bit B1120.
	GTZC_VCTR35_B1120 = 0x1
	// Position of B1121 field.
	GTZC_VCTR35_B1121_Pos = 0x1
	// Bit mask of B1121 field.
	GTZC_VCTR35_B1121_Msk = 0x2
	// Bit B1121.
	GTZC_VCTR35_B1121 = 0x2
	// Position of B1122 field.
	GTZC_VCTR35_B1122_Pos = 0x2
	// Bit mask of B1122 field.
	GTZC_VCTR35_B1122_Msk = 0x4
	// Bit B1122.
	GTZC_VCTR35_B1122 = 0x4
	// Position of B1123 field.
	GTZC_VCTR35_B1123_Pos = 0x3
	// Bit mask of B1123 field.
	GTZC_VCTR35_B1123_Msk = 0x8
	// Bit B1123.
	GTZC_VCTR35_B1123 = 0x8
	// Position of B1124 field.
	GTZC_VCTR35_B1124_Pos = 0x4
	// Bit mask of B1124 field.
	GTZC_VCTR35_B1124_Msk = 0x10
	// Bit B1124.
	GTZC_VCTR35_B1124 = 0x10
	// Position of B1125 field.
	GTZC_VCTR35_B1125_Pos = 0x5
	// Bit mask of B1125 field.
	GTZC_VCTR35_B1125_Msk = 0x20
	// Bit B1125.
	GTZC_VCTR35_B1125 = 0x20
	// Position of B1126 field.
	GTZC_VCTR35_B1126_Pos = 0x6
	// Bit mask of B1126 field.
	GTZC_VCTR35_B1126_Msk = 0x40
	// Bit B1126.
	GTZC_VCTR35_B1126 = 0x40
	// Position of B1127 field.
	GTZC_VCTR35_B1127_Pos = 0x7
	// Bit mask of B1127 field.
	GTZC_VCTR35_B1127_Msk = 0x80
	// Bit B1127.
	GTZC_VCTR35_B1127 = 0x80
	// Position of B1128 field.
	GTZC_VCTR35_B1128_Pos = 0x8
	// Bit mask of B1128 field.
	GTZC_VCTR35_B1128_Msk = 0x100
	// Bit B1128.
	GTZC_VCTR35_B1128 = 0x100
	// Position of B1129 field.
	GTZC_VCTR35_B1129_Pos = 0x9
	// Bit mask of B1129 field.
	GTZC_VCTR35_B1129_Msk = 0x200
	// Bit B1129.
	GTZC_VCTR35_B1129 = 0x200
	// Position of B1130 field.
	GTZC_VCTR35_B1130_Pos = 0xa
	// Bit mask of B1130 field.
	GTZC_VCTR35_B1130_Msk = 0x400
	// Bit B1130.
	GTZC_VCTR35_B1130 = 0x400
	// Position of B1131 field.
	GTZC_VCTR35_B1131_Pos = 0xb
	// Bit mask of B1131 field.
	GTZC_VCTR35_B1131_Msk = 0x800
	// Bit B1131.
	GTZC_VCTR35_B1131 = 0x800
	// Position of B1132 field.
	GTZC_VCTR35_B1132_Pos = 0xc
	// Bit mask of B1132 field.
	GTZC_VCTR35_B1132_Msk = 0x1000
	// Bit B1132.
	GTZC_VCTR35_B1132 = 0x1000
	// Position of B1133 field.
	GTZC_VCTR35_B1133_Pos = 0xd
	// Bit mask of B1133 field.
	GTZC_VCTR35_B1133_Msk = 0x2000
	// Bit B1133.
	GTZC_VCTR35_B1133 = 0x2000
	// Position of B1134 field.
	GTZC_VCTR35_B1134_Pos = 0xe
	// Bit mask of B1134 field.
	GTZC_VCTR35_B1134_Msk = 0x4000
	// Bit B1134.
	GTZC_VCTR35_B1134 = 0x4000
	// Position of B1135 field.
	GTZC_VCTR35_B1135_Pos = 0xf
	// Bit mask of B1135 field.
	GTZC_VCTR35_B1135_Msk = 0x8000
	// Bit B1135.
	GTZC_VCTR35_B1135 = 0x8000
	// Position of B1136 field.
	GTZC_VCTR35_B1136_Pos = 0x10
	// Bit mask of B1136 field.
	GTZC_VCTR35_B1136_Msk = 0x10000
	// Bit B1136.
	GTZC_VCTR35_B1136 = 0x10000
	// Position of B1137 field.
	GTZC_VCTR35_B1137_Pos = 0x11
	// Bit mask of B1137 field.
	GTZC_VCTR35_B1137_Msk = 0x20000
	// Bit B1137.
	GTZC_VCTR35_B1137 = 0x20000
	// Position of B1138 field.
	GTZC_VCTR35_B1138_Pos = 0x12
	// Bit mask of B1138 field.
	GTZC_VCTR35_B1138_Msk = 0x40000
	// Bit B1138.
	GTZC_VCTR35_B1138 = 0x40000
	// Position of B1139 field.
	GTZC_VCTR35_B1139_Pos = 0x13
	// Bit mask of B1139 field.
	GTZC_VCTR35_B1139_Msk = 0x80000
	// Bit B1139.
	GTZC_VCTR35_B1139 = 0x80000
	// Position of B1140 field.
	GTZC_VCTR35_B1140_Pos = 0x14
	// Bit mask of B1140 field.
	GTZC_VCTR35_B1140_Msk = 0x100000
	// Bit B1140.
	GTZC_VCTR35_B1140 = 0x100000
	// Position of B1141 field.
	GTZC_VCTR35_B1141_Pos = 0x15
	// Bit mask of B1141 field.
	GTZC_VCTR35_B1141_Msk = 0x200000
	// Bit B1141.
	GTZC_VCTR35_B1141 = 0x200000
	// Position of B1142 field.
	GTZC_VCTR35_B1142_Pos = 0x16
	// Bit mask of B1142 field.
	GTZC_VCTR35_B1142_Msk = 0x400000
	// Bit B1142.
	GTZC_VCTR35_B1142 = 0x400000
	// Position of B1143 field.
	GTZC_VCTR35_B1143_Pos = 0x17
	// Bit mask of B1143 field.
	GTZC_VCTR35_B1143_Msk = 0x800000
	// Bit B1143.
	GTZC_VCTR35_B1143 = 0x800000
	// Position of B1144 field.
	GTZC_VCTR35_B1144_Pos = 0x18
	// Bit mask of B1144 field.
	GTZC_VCTR35_B1144_Msk = 0x1000000
	// Bit B1144.
	GTZC_VCTR35_B1144 = 0x1000000
	// Position of B1145 field.
	GTZC_VCTR35_B1145_Pos = 0x19
	// Bit mask of B1145 field.
	GTZC_VCTR35_B1145_Msk = 0x2000000
	// Bit B1145.
	GTZC_VCTR35_B1145 = 0x2000000
	// Position of B1146 field.
	GTZC_VCTR35_B1146_Pos = 0x1a
	// Bit mask of B1146 field.
	GTZC_VCTR35_B1146_Msk = 0x4000000
	// Bit B1146.
	GTZC_VCTR35_B1146 = 0x4000000
	// Position of B1147 field.
	GTZC_VCTR35_B1147_Pos = 0x1b
	// Bit mask of B1147 field.
	GTZC_VCTR35_B1147_Msk = 0x8000000
	// Bit B1147.
	GTZC_VCTR35_B1147 = 0x8000000
	// Position of B1148 field.
	GTZC_VCTR35_B1148_Pos = 0x1c
	// Bit mask of B1148 field.
	GTZC_VCTR35_B1148_Msk = 0x10000000
	// Bit B1148.
	GTZC_VCTR35_B1148 = 0x10000000
	// Position of B1149 field.
	GTZC_VCTR35_B1149_Pos = 0x1d
	// Bit mask of B1149 field.
	GTZC_VCTR35_B1149_Msk = 0x20000000
	// Bit B1149.
	GTZC_VCTR35_B1149 = 0x20000000
	// Position of B1150 field.
	GTZC_VCTR35_B1150_Pos = 0x1e
	// Bit mask of B1150 field.
	GTZC_VCTR35_B1150_Msk = 0x40000000
	// Bit B1150.
	GTZC_VCTR35_B1150 = 0x40000000
	// Position of B1151 field.
	GTZC_VCTR35_B1151_Pos = 0x1f
	// Bit mask of B1151 field.
	GTZC_VCTR35_B1151_Msk = 0x80000000
	// Bit B1151.
	GTZC_VCTR35_B1151 = 0x80000000

	// VCTR36: MPCBBx vector register
	// Position of B1152 field.
	GTZC_VCTR36_B1152_Pos = 0x0
	// Bit mask of B1152 field.
	GTZC_VCTR36_B1152_Msk = 0x1
	// Bit B1152.
	GTZC_VCTR36_B1152 = 0x1
	// Position of B1153 field.
	GTZC_VCTR36_B1153_Pos = 0x1
	// Bit mask of B1153 field.
	GTZC_VCTR36_B1153_Msk = 0x2
	// Bit B1153.
	GTZC_VCTR36_B1153 = 0x2
	// Position of B1154 field.
	GTZC_VCTR36_B1154_Pos = 0x2
	// Bit mask of B1154 field.
	GTZC_VCTR36_B1154_Msk = 0x4
	// Bit B1154.
	GTZC_VCTR36_B1154 = 0x4
	// Position of B1155 field.
	GTZC_VCTR36_B1155_Pos = 0x3
	// Bit mask of B1155 field.
	GTZC_VCTR36_B1155_Msk = 0x8
	// Bit B1155.
	GTZC_VCTR36_B1155 = 0x8
	// Position of B1156 field.
	GTZC_VCTR36_B1156_Pos = 0x4
	// Bit mask of B1156 field.
	GTZC_VCTR36_B1156_Msk = 0x10
	// Bit B1156.
	GTZC_VCTR36_B1156 = 0x10
	// Position of B1157 field.
	GTZC_VCTR36_B1157_Pos = 0x5
	// Bit mask of B1157 field.
	GTZC_VCTR36_B1157_Msk = 0x20
	// Bit B1157.
	GTZC_VCTR36_B1157 = 0x20
	// Position of B1158 field.
	GTZC_VCTR36_B1158_Pos = 0x6
	// Bit mask of B1158 field.
	GTZC_VCTR36_B1158_Msk = 0x40
	// Bit B1158.
	GTZC_VCTR36_B1158 = 0x40
	// Position of B1159 field.
	GTZC_VCTR36_B1159_Pos = 0x7
	// Bit mask of B1159 field.
	GTZC_VCTR36_B1159_Msk = 0x80
	// Bit B1159.
	GTZC_VCTR36_B1159 = 0x80
	// Position of B1160 field.
	GTZC_VCTR36_B1160_Pos = 0x8
	// Bit mask of B1160 field.
	GTZC_VCTR36_B1160_Msk = 0x100
	// Bit B1160.
	GTZC_VCTR36_B1160 = 0x100
	// Position of B1161 field.
	GTZC_VCTR36_B1161_Pos = 0x9
	// Bit mask of B1161 field.
	GTZC_VCTR36_B1161_Msk = 0x200
	// Bit B1161.
	GTZC_VCTR36_B1161 = 0x200
	// Position of B1162 field.
	GTZC_VCTR36_B1162_Pos = 0xa
	// Bit mask of B1162 field.
	GTZC_VCTR36_B1162_Msk = 0x400
	// Bit B1162.
	GTZC_VCTR36_B1162 = 0x400
	// Position of B1163 field.
	GTZC_VCTR36_B1163_Pos = 0xb
	// Bit mask of B1163 field.
	GTZC_VCTR36_B1163_Msk = 0x800
	// Bit B1163.
	GTZC_VCTR36_B1163 = 0x800
	// Position of B1164 field.
	GTZC_VCTR36_B1164_Pos = 0xc
	// Bit mask of B1164 field.
	GTZC_VCTR36_B1164_Msk = 0x1000
	// Bit B1164.
	GTZC_VCTR36_B1164 = 0x1000
	// Position of B1165 field.
	GTZC_VCTR36_B1165_Pos = 0xd
	// Bit mask of B1165 field.
	GTZC_VCTR36_B1165_Msk = 0x2000
	// Bit B1165.
	GTZC_VCTR36_B1165 = 0x2000
	// Position of B1166 field.
	GTZC_VCTR36_B1166_Pos = 0xe
	// Bit mask of B1166 field.
	GTZC_VCTR36_B1166_Msk = 0x4000
	// Bit B1166.
	GTZC_VCTR36_B1166 = 0x4000
	// Position of B1167 field.
	GTZC_VCTR36_B1167_Pos = 0xf
	// Bit mask of B1167 field.
	GTZC_VCTR36_B1167_Msk = 0x8000
	// Bit B1167.
	GTZC_VCTR36_B1167 = 0x8000
	// Position of B1168 field.
	GTZC_VCTR36_B1168_Pos = 0x10
	// Bit mask of B1168 field.
	GTZC_VCTR36_B1168_Msk = 0x10000
	// Bit B1168.
	GTZC_VCTR36_B1168 = 0x10000
	// Position of B1169 field.
	GTZC_VCTR36_B1169_Pos = 0x11
	// Bit mask of B1169 field.
	GTZC_VCTR36_B1169_Msk = 0x20000
	// Bit B1169.
	GTZC_VCTR36_B1169 = 0x20000
	// Position of B1170 field.
	GTZC_VCTR36_B1170_Pos = 0x12
	// Bit mask of B1170 field.
	GTZC_VCTR36_B1170_Msk = 0x40000
	// Bit B1170.
	GTZC_VCTR36_B1170 = 0x40000
	// Position of B1171 field.
	GTZC_VCTR36_B1171_Pos = 0x13
	// Bit mask of B1171 field.
	GTZC_VCTR36_B1171_Msk = 0x80000
	// Bit B1171.
	GTZC_VCTR36_B1171 = 0x80000
	// Position of B1172 field.
	GTZC_VCTR36_B1172_Pos = 0x14
	// Bit mask of B1172 field.
	GTZC_VCTR36_B1172_Msk = 0x100000
	// Bit B1172.
	GTZC_VCTR36_B1172 = 0x100000
	// Position of B1173 field.
	GTZC_VCTR36_B1173_Pos = 0x15
	// Bit mask of B1173 field.
	GTZC_VCTR36_B1173_Msk = 0x200000
	// Bit B1173.
	GTZC_VCTR36_B1173 = 0x200000
	// Position of B1174 field.
	GTZC_VCTR36_B1174_Pos = 0x16
	// Bit mask of B1174 field.
	GTZC_VCTR36_B1174_Msk = 0x400000
	// Bit B1174.
	GTZC_VCTR36_B1174 = 0x400000
	// Position of B1175 field.
	GTZC_VCTR36_B1175_Pos = 0x17
	// Bit mask of B1175 field.
	GTZC_VCTR36_B1175_Msk = 0x800000
	// Bit B1175.
	GTZC_VCTR36_B1175 = 0x800000
	// Position of B1176 field.
	GTZC_VCTR36_B1176_Pos = 0x18
	// Bit mask of B1176 field.
	GTZC_VCTR36_B1176_Msk = 0x1000000
	// Bit B1176.
	GTZC_VCTR36_B1176 = 0x1000000
	// Position of B1177 field.
	GTZC_VCTR36_B1177_Pos = 0x19
	// Bit mask of B1177 field.
	GTZC_VCTR36_B1177_Msk = 0x2000000
	// Bit B1177.
	GTZC_VCTR36_B1177 = 0x2000000
	// Position of B1178 field.
	GTZC_VCTR36_B1178_Pos = 0x1a
	// Bit mask of B1178 field.
	GTZC_VCTR36_B1178_Msk = 0x4000000
	// Bit B1178.
	GTZC_VCTR36_B1178 = 0x4000000
	// Position of B1179 field.
	GTZC_VCTR36_B1179_Pos = 0x1b
	// Bit mask of B1179 field.
	GTZC_VCTR36_B1179_Msk = 0x8000000
	// Bit B1179.
	GTZC_VCTR36_B1179 = 0x8000000
	// Position of B1180 field.
	GTZC_VCTR36_B1180_Pos = 0x1c
	// Bit mask of B1180 field.
	GTZC_VCTR36_B1180_Msk = 0x10000000
	// Bit B1180.
	GTZC_VCTR36_B1180 = 0x10000000
	// Position of B1181 field.
	GTZC_VCTR36_B1181_Pos = 0x1d
	// Bit mask of B1181 field.
	GTZC_VCTR36_B1181_Msk = 0x20000000
	// Bit B1181.
	GTZC_VCTR36_B1181 = 0x20000000
	// Position of B1182 field.
	GTZC_VCTR36_B1182_Pos = 0x1e
	// Bit mask of B1182 field.
	GTZC_VCTR36_B1182_Msk = 0x40000000
	// Bit B1182.
	GTZC_VCTR36_B1182 = 0x40000000
	// Position of B1183 field.
	GTZC_VCTR36_B1183_Pos = 0x1f
	// Bit mask of B1183 field.
	GTZC_VCTR36_B1183_Msk = 0x80000000
	// Bit B1183.
	GTZC_VCTR36_B1183 = 0x80000000

	// VCTR37: MPCBBx vector register
	// Position of B1184 field.
	GTZC_VCTR37_B1184_Pos = 0x0
	// Bit mask of B1184 field.
	GTZC_VCTR37_B1184_Msk = 0x1
	// Bit B1184.
	GTZC_VCTR37_B1184 = 0x1
	// Position of B1185 field.
	GTZC_VCTR37_B1185_Pos = 0x1
	// Bit mask of B1185 field.
	GTZC_VCTR37_B1185_Msk = 0x2
	// Bit B1185.
	GTZC_VCTR37_B1185 = 0x2
	// Position of B1186 field.
	GTZC_VCTR37_B1186_Pos = 0x2
	// Bit mask of B1186 field.
	GTZC_VCTR37_B1186_Msk = 0x4
	// Bit B1186.
	GTZC_VCTR37_B1186 = 0x4
	// Position of B1187 field.
	GTZC_VCTR37_B1187_Pos = 0x3
	// Bit mask of B1187 field.
	GTZC_VCTR37_B1187_Msk = 0x8
	// Bit B1187.
	GTZC_VCTR37_B1187 = 0x8
	// Position of B1188 field.
	GTZC_VCTR37_B1188_Pos = 0x4
	// Bit mask of B1188 field.
	GTZC_VCTR37_B1188_Msk = 0x10
	// Bit B1188.
	GTZC_VCTR37_B1188 = 0x10
	// Position of B1189 field.
	GTZC_VCTR37_B1189_Pos = 0x5
	// Bit mask of B1189 field.
	GTZC_VCTR37_B1189_Msk = 0x20
	// Bit B1189.
	GTZC_VCTR37_B1189 = 0x20
	// Position of B1190 field.
	GTZC_VCTR37_B1190_Pos = 0x6
	// Bit mask of B1190 field.
	GTZC_VCTR37_B1190_Msk = 0x40
	// Bit B1190.
	GTZC_VCTR37_B1190 = 0x40
	// Position of B1191 field.
	GTZC_VCTR37_B1191_Pos = 0x7
	// Bit mask of B1191 field.
	GTZC_VCTR37_B1191_Msk = 0x80
	// Bit B1191.
	GTZC_VCTR37_B1191 = 0x80
	// Position of B1192 field.
	GTZC_VCTR37_B1192_Pos = 0x8
	// Bit mask of B1192 field.
	GTZC_VCTR37_B1192_Msk = 0x100
	// Bit B1192.
	GTZC_VCTR37_B1192 = 0x100
	// Position of B1193 field.
	GTZC_VCTR37_B1193_Pos = 0x9
	// Bit mask of B1193 field.
	GTZC_VCTR37_B1193_Msk = 0x200
	// Bit B1193.
	GTZC_VCTR37_B1193 = 0x200
	// Position of B1194 field.
	GTZC_VCTR37_B1194_Pos = 0xa
	// Bit mask of B1194 field.
	GTZC_VCTR37_B1194_Msk = 0x400
	// Bit B1194.
	GTZC_VCTR37_B1194 = 0x400
	// Position of B1195 field.
	GTZC_VCTR37_B1195_Pos = 0xb
	// Bit mask of B1195 field.
	GTZC_VCTR37_B1195_Msk = 0x800
	// Bit B1195.
	GTZC_VCTR37_B1195 = 0x800
	// Position of B1196 field.
	GTZC_VCTR37_B1196_Pos = 0xc
	// Bit mask of B1196 field.
	GTZC_VCTR37_B1196_Msk = 0x1000
	// Bit B1196.
	GTZC_VCTR37_B1196 = 0x1000
	// Position of B1197 field.
	GTZC_VCTR37_B1197_Pos = 0xd
	// Bit mask of B1197 field.
	GTZC_VCTR37_B1197_Msk = 0x2000
	// Bit B1197.
	GTZC_VCTR37_B1197 = 0x2000
	// Position of B1198 field.
	GTZC_VCTR37_B1198_Pos = 0xe
	// Bit mask of B1198 field.
	GTZC_VCTR37_B1198_Msk = 0x4000
	// Bit B1198.
	GTZC_VCTR37_B1198 = 0x4000
	// Position of B1199 field.
	GTZC_VCTR37_B1199_Pos = 0xf
	// Bit mask of B1199 field.
	GTZC_VCTR37_B1199_Msk = 0x8000
	// Bit B1199.
	GTZC_VCTR37_B1199 = 0x8000
	// Position of B1200 field.
	GTZC_VCTR37_B1200_Pos = 0x10
	// Bit mask of B1200 field.
	GTZC_VCTR37_B1200_Msk = 0x10000
	// Bit B1200.
	GTZC_VCTR37_B1200 = 0x10000
	// Position of B1201 field.
	GTZC_VCTR37_B1201_Pos = 0x11
	// Bit mask of B1201 field.
	GTZC_VCTR37_B1201_Msk = 0x20000
	// Bit B1201.
	GTZC_VCTR37_B1201 = 0x20000
	// Position of B1202 field.
	GTZC_VCTR37_B1202_Pos = 0x12
	// Bit mask of B1202 field.
	GTZC_VCTR37_B1202_Msk = 0x40000
	// Bit B1202.
	GTZC_VCTR37_B1202 = 0x40000
	// Position of B1203 field.
	GTZC_VCTR37_B1203_Pos = 0x13
	// Bit mask of B1203 field.
	GTZC_VCTR37_B1203_Msk = 0x80000
	// Bit B1203.
	GTZC_VCTR37_B1203 = 0x80000
	// Position of B1204 field.
	GTZC_VCTR37_B1204_Pos = 0x14
	// Bit mask of B1204 field.
	GTZC_VCTR37_B1204_Msk = 0x100000
	// Bit B1204.
	GTZC_VCTR37_B1204 = 0x100000
	// Position of B1205 field.
	GTZC_VCTR37_B1205_Pos = 0x15
	// Bit mask of B1205 field.
	GTZC_VCTR37_B1205_Msk = 0x200000
	// Bit B1205.
	GTZC_VCTR37_B1205 = 0x200000
	// Position of B1206 field.
	GTZC_VCTR37_B1206_Pos = 0x16
	// Bit mask of B1206 field.
	GTZC_VCTR37_B1206_Msk = 0x400000
	// Bit B1206.
	GTZC_VCTR37_B1206 = 0x400000
	// Position of B1207 field.
	GTZC_VCTR37_B1207_Pos = 0x17
	// Bit mask of B1207 field.
	GTZC_VCTR37_B1207_Msk = 0x800000
	// Bit B1207.
	GTZC_VCTR37_B1207 = 0x800000
	// Position of B1208 field.
	GTZC_VCTR37_B1208_Pos = 0x18
	// Bit mask of B1208 field.
	GTZC_VCTR37_B1208_Msk = 0x1000000
	// Bit B1208.
	GTZC_VCTR37_B1208 = 0x1000000
	// Position of B1209 field.
	GTZC_VCTR37_B1209_Pos = 0x19
	// Bit mask of B1209 field.
	GTZC_VCTR37_B1209_Msk = 0x2000000
	// Bit B1209.
	GTZC_VCTR37_B1209 = 0x2000000
	// Position of B1210 field.
	GTZC_VCTR37_B1210_Pos = 0x1a
	// Bit mask of B1210 field.
	GTZC_VCTR37_B1210_Msk = 0x4000000
	// Bit B1210.
	GTZC_VCTR37_B1210 = 0x4000000
	// Position of B1211 field.
	GTZC_VCTR37_B1211_Pos = 0x1b
	// Bit mask of B1211 field.
	GTZC_VCTR37_B1211_Msk = 0x8000000
	// Bit B1211.
	GTZC_VCTR37_B1211 = 0x8000000
	// Position of B1212 field.
	GTZC_VCTR37_B1212_Pos = 0x1c
	// Bit mask of B1212 field.
	GTZC_VCTR37_B1212_Msk = 0x10000000
	// Bit B1212.
	GTZC_VCTR37_B1212 = 0x10000000
	// Position of B1213 field.
	GTZC_VCTR37_B1213_Pos = 0x1d
	// Bit mask of B1213 field.
	GTZC_VCTR37_B1213_Msk = 0x20000000
	// Bit B1213.
	GTZC_VCTR37_B1213 = 0x20000000
	// Position of B1214 field.
	GTZC_VCTR37_B1214_Pos = 0x1e
	// Bit mask of B1214 field.
	GTZC_VCTR37_B1214_Msk = 0x40000000
	// Bit B1214.
	GTZC_VCTR37_B1214 = 0x40000000
	// Position of B1215 field.
	GTZC_VCTR37_B1215_Pos = 0x1f
	// Bit mask of B1215 field.
	GTZC_VCTR37_B1215_Msk = 0x80000000
	// Bit B1215.
	GTZC_VCTR37_B1215 = 0x80000000

	// VCTR38: MPCBBx vector register
	// Position of B1216 field.
	GTZC_VCTR38_B1216_Pos = 0x0
	// Bit mask of B1216 field.
	GTZC_VCTR38_B1216_Msk = 0x1
	// Bit B1216.
	GTZC_VCTR38_B1216 = 0x1
	// Position of B1217 field.
	GTZC_VCTR38_B1217_Pos = 0x1
	// Bit mask of B1217 field.
	GTZC_VCTR38_B1217_Msk = 0x2
	// Bit B1217.
	GTZC_VCTR38_B1217 = 0x2
	// Position of B1218 field.
	GTZC_VCTR38_B1218_Pos = 0x2
	// Bit mask of B1218 field.
	GTZC_VCTR38_B1218_Msk = 0x4
	// Bit B1218.
	GTZC_VCTR38_B1218 = 0x4
	// Position of B1219 field.
	GTZC_VCTR38_B1219_Pos = 0x3
	// Bit mask of B1219 field.
	GTZC_VCTR38_B1219_Msk = 0x8
	// Bit B1219.
	GTZC_VCTR38_B1219 = 0x8
	// Position of B1220 field.
	GTZC_VCTR38_B1220_Pos = 0x4
	// Bit mask of B1220 field.
	GTZC_VCTR38_B1220_Msk = 0x10
	// Bit B1220.
	GTZC_VCTR38_B1220 = 0x10
	// Position of B1221 field.
	GTZC_VCTR38_B1221_Pos = 0x5
	// Bit mask of B1221 field.
	GTZC_VCTR38_B1221_Msk = 0x20
	// Bit B1221.
	GTZC_VCTR38_B1221 = 0x20
	// Position of B1222 field.
	GTZC_VCTR38_B1222_Pos = 0x6
	// Bit mask of B1222 field.
	GTZC_VCTR38_B1222_Msk = 0x40
	// Bit B1222.
	GTZC_VCTR38_B1222 = 0x40
	// Position of B1223 field.
	GTZC_VCTR38_B1223_Pos = 0x7
	// Bit mask of B1223 field.
	GTZC_VCTR38_B1223_Msk = 0x80
	// Bit B1223.
	GTZC_VCTR38_B1223 = 0x80
	// Position of B1224 field.
	GTZC_VCTR38_B1224_Pos = 0x8
	// Bit mask of B1224 field.
	GTZC_VCTR38_B1224_Msk = 0x100
	// Bit B1224.
	GTZC_VCTR38_B1224 = 0x100
	// Position of B1225 field.
	GTZC_VCTR38_B1225_Pos = 0x9
	// Bit mask of B1225 field.
	GTZC_VCTR38_B1225_Msk = 0x200
	// Bit B1225.
	GTZC_VCTR38_B1225 = 0x200
	// Position of B1226 field.
	GTZC_VCTR38_B1226_Pos = 0xa
	// Bit mask of B1226 field.
	GTZC_VCTR38_B1226_Msk = 0x400
	// Bit B1226.
	GTZC_VCTR38_B1226 = 0x400
	// Position of B1227 field.
	GTZC_VCTR38_B1227_Pos = 0xb
	// Bit mask of B1227 field.
	GTZC_VCTR38_B1227_Msk = 0x800
	// Bit B1227.
	GTZC_VCTR38_B1227 = 0x800
	// Position of B1228 field.
	GTZC_VCTR38_B1228_Pos = 0xc
	// Bit mask of B1228 field.
	GTZC_VCTR38_B1228_Msk = 0x1000
	// Bit B1228.
	GTZC_VCTR38_B1228 = 0x1000
	// Position of B1229 field.
	GTZC_VCTR38_B1229_Pos = 0xd
	// Bit mask of B1229 field.
	GTZC_VCTR38_B1229_Msk = 0x2000
	// Bit B1229.
	GTZC_VCTR38_B1229 = 0x2000
	// Position of B1230 field.
	GTZC_VCTR38_B1230_Pos = 0xe
	// Bit mask of B1230 field.
	GTZC_VCTR38_B1230_Msk = 0x4000
	// Bit B1230.
	GTZC_VCTR38_B1230 = 0x4000
	// Position of B1231 field.
	GTZC_VCTR38_B1231_Pos = 0xf
	// Bit mask of B1231 field.
	GTZC_VCTR38_B1231_Msk = 0x8000
	// Bit B1231.
	GTZC_VCTR38_B1231 = 0x8000
	// Position of B1232 field.
	GTZC_VCTR38_B1232_Pos = 0x10
	// Bit mask of B1232 field.
	GTZC_VCTR38_B1232_Msk = 0x10000
	// Bit B1232.
	GTZC_VCTR38_B1232 = 0x10000
	// Position of B1233 field.
	GTZC_VCTR38_B1233_Pos = 0x11
	// Bit mask of B1233 field.
	GTZC_VCTR38_B1233_Msk = 0x20000
	// Bit B1233.
	GTZC_VCTR38_B1233 = 0x20000
	// Position of B1234 field.
	GTZC_VCTR38_B1234_Pos = 0x12
	// Bit mask of B1234 field.
	GTZC_VCTR38_B1234_Msk = 0x40000
	// Bit B1234.
	GTZC_VCTR38_B1234 = 0x40000
	// Position of B1235 field.
	GTZC_VCTR38_B1235_Pos = 0x13
	// Bit mask of B1235 field.
	GTZC_VCTR38_B1235_Msk = 0x80000
	// Bit B1235.
	GTZC_VCTR38_B1235 = 0x80000
	// Position of B1236 field.
	GTZC_VCTR38_B1236_Pos = 0x14
	// Bit mask of B1236 field.
	GTZC_VCTR38_B1236_Msk = 0x100000
	// Bit B1236.
	GTZC_VCTR38_B1236 = 0x100000
	// Position of B1237 field.
	GTZC_VCTR38_B1237_Pos = 0x15
	// Bit mask of B1237 field.
	GTZC_VCTR38_B1237_Msk = 0x200000
	// Bit B1237.
	GTZC_VCTR38_B1237 = 0x200000
	// Position of B1238 field.
	GTZC_VCTR38_B1238_Pos = 0x16
	// Bit mask of B1238 field.
	GTZC_VCTR38_B1238_Msk = 0x400000
	// Bit B1238.
	GTZC_VCTR38_B1238 = 0x400000
	// Position of B1239 field.
	GTZC_VCTR38_B1239_Pos = 0x17
	// Bit mask of B1239 field.
	GTZC_VCTR38_B1239_Msk = 0x800000
	// Bit B1239.
	GTZC_VCTR38_B1239 = 0x800000
	// Position of B1240 field.
	GTZC_VCTR38_B1240_Pos = 0x18
	// Bit mask of B1240 field.
	GTZC_VCTR38_B1240_Msk = 0x1000000
	// Bit B1240.
	GTZC_VCTR38_B1240 = 0x1000000
	// Position of B1241 field.
	GTZC_VCTR38_B1241_Pos = 0x19
	// Bit mask of B1241 field.
	GTZC_VCTR38_B1241_Msk = 0x2000000
	// Bit B1241.
	GTZC_VCTR38_B1241 = 0x2000000
	// Position of B1242 field.
	GTZC_VCTR38_B1242_Pos = 0x1a
	// Bit mask of B1242 field.
	GTZC_VCTR38_B1242_Msk = 0x4000000
	// Bit B1242.
	GTZC_VCTR38_B1242 = 0x4000000
	// Position of B1243 field.
	GTZC_VCTR38_B1243_Pos = 0x1b
	// Bit mask of B1243 field.
	GTZC_VCTR38_B1243_Msk = 0x8000000
	// Bit B1243.
	GTZC_VCTR38_B1243 = 0x8000000
	// Position of B1244 field.
	GTZC_VCTR38_B1244_Pos = 0x1c
	// Bit mask of B1244 field.
	GTZC_VCTR38_B1244_Msk = 0x10000000
	// Bit B1244.
	GTZC_VCTR38_B1244 = 0x10000000
	// Position of B1245 field.
	GTZC_VCTR38_B1245_Pos = 0x1d
	// Bit mask of B1245 field.
	GTZC_VCTR38_B1245_Msk = 0x20000000
	// Bit B1245.
	GTZC_VCTR38_B1245 = 0x20000000
	// Position of B1246 field.
	GTZC_VCTR38_B1246_Pos = 0x1e
	// Bit mask of B1246 field.
	GTZC_VCTR38_B1246_Msk = 0x40000000
	// Bit B1246.
	GTZC_VCTR38_B1246 = 0x40000000
	// Position of B1247 field.
	GTZC_VCTR38_B1247_Pos = 0x1f
	// Bit mask of B1247 field.
	GTZC_VCTR38_B1247_Msk = 0x80000000
	// Bit B1247.
	GTZC_VCTR38_B1247 = 0x80000000

	// VCTR39: MPCBBx vector register
	// Position of B1248 field.
	GTZC_VCTR39_B1248_Pos = 0x0
	// Bit mask of B1248 field.
	GTZC_VCTR39_B1248_Msk = 0x1
	// Bit B1248.
	GTZC_VCTR39_B1248 = 0x1
	// Position of B1249 field.
	GTZC_VCTR39_B1249_Pos = 0x1
	// Bit mask of B1249 field.
	GTZC_VCTR39_B1249_Msk = 0x2
	// Bit B1249.
	GTZC_VCTR39_B1249 = 0x2
	// Position of B1250 field.
	GTZC_VCTR39_B1250_Pos = 0x2
	// Bit mask of B1250 field.
	GTZC_VCTR39_B1250_Msk = 0x4
	// Bit B1250.
	GTZC_VCTR39_B1250 = 0x4
	// Position of B1251 field.
	GTZC_VCTR39_B1251_Pos = 0x3
	// Bit mask of B1251 field.
	GTZC_VCTR39_B1251_Msk = 0x8
	// Bit B1251.
	GTZC_VCTR39_B1251 = 0x8
	// Position of B1252 field.
	GTZC_VCTR39_B1252_Pos = 0x4
	// Bit mask of B1252 field.
	GTZC_VCTR39_B1252_Msk = 0x10
	// Bit B1252.
	GTZC_VCTR39_B1252 = 0x10
	// Position of B1253 field.
	GTZC_VCTR39_B1253_Pos = 0x5
	// Bit mask of B1253 field.
	GTZC_VCTR39_B1253_Msk = 0x20
	// Bit B1253.
	GTZC_VCTR39_B1253 = 0x20
	// Position of B1254 field.
	GTZC_VCTR39_B1254_Pos = 0x6
	// Bit mask of B1254 field.
	GTZC_VCTR39_B1254_Msk = 0x40
	// Bit B1254.
	GTZC_VCTR39_B1254 = 0x40
	// Position of B1255 field.
	GTZC_VCTR39_B1255_Pos = 0x7
	// Bit mask of B1255 field.
	GTZC_VCTR39_B1255_Msk = 0x80
	// Bit B1255.
	GTZC_VCTR39_B1255 = 0x80
	// Position of B1256 field.
	GTZC_VCTR39_B1256_Pos = 0x8
	// Bit mask of B1256 field.
	GTZC_VCTR39_B1256_Msk = 0x100
	// Bit B1256.
	GTZC_VCTR39_B1256 = 0x100
	// Position of B1257 field.
	GTZC_VCTR39_B1257_Pos = 0x9
	// Bit mask of B1257 field.
	GTZC_VCTR39_B1257_Msk = 0x200
	// Bit B1257.
	GTZC_VCTR39_B1257 = 0x200
	// Position of B1258 field.
	GTZC_VCTR39_B1258_Pos = 0xa
	// Bit mask of B1258 field.
	GTZC_VCTR39_B1258_Msk = 0x400
	// Bit B1258.
	GTZC_VCTR39_B1258 = 0x400
	// Position of B1259 field.
	GTZC_VCTR39_B1259_Pos = 0xb
	// Bit mask of B1259 field.
	GTZC_VCTR39_B1259_Msk = 0x800
	// Bit B1259.
	GTZC_VCTR39_B1259 = 0x800
	// Position of B1260 field.
	GTZC_VCTR39_B1260_Pos = 0xc
	// Bit mask of B1260 field.
	GTZC_VCTR39_B1260_Msk = 0x1000
	// Bit B1260.
	GTZC_VCTR39_B1260 = 0x1000
	// Position of B1261 field.
	GTZC_VCTR39_B1261_Pos = 0xd
	// Bit mask of B1261 field.
	GTZC_VCTR39_B1261_Msk = 0x2000
	// Bit B1261.
	GTZC_VCTR39_B1261 = 0x2000
	// Position of B1262 field.
	GTZC_VCTR39_B1262_Pos = 0xe
	// Bit mask of B1262 field.
	GTZC_VCTR39_B1262_Msk = 0x4000
	// Bit B1262.
	GTZC_VCTR39_B1262 = 0x4000
	// Position of B1263 field.
	GTZC_VCTR39_B1263_Pos = 0xf
	// Bit mask of B1263 field.
	GTZC_VCTR39_B1263_Msk = 0x8000
	// Bit B1263.
	GTZC_VCTR39_B1263 = 0x8000
	// Position of B1264 field.
	GTZC_VCTR39_B1264_Pos = 0x10
	// Bit mask of B1264 field.
	GTZC_VCTR39_B1264_Msk = 0x10000
	// Bit B1264.
	GTZC_VCTR39_B1264 = 0x10000
	// Position of B1265 field.
	GTZC_VCTR39_B1265_Pos = 0x11
	// Bit mask of B1265 field.
	GTZC_VCTR39_B1265_Msk = 0x20000
	// Bit B1265.
	GTZC_VCTR39_B1265 = 0x20000
	// Position of B1266 field.
	GTZC_VCTR39_B1266_Pos = 0x12
	// Bit mask of B1266 field.
	GTZC_VCTR39_B1266_Msk = 0x40000
	// Bit B1266.
	GTZC_VCTR39_B1266 = 0x40000
	// Position of B1267 field.
	GTZC_VCTR39_B1267_Pos = 0x13
	// Bit mask of B1267 field.
	GTZC_VCTR39_B1267_Msk = 0x80000
	// Bit B1267.
	GTZC_VCTR39_B1267 = 0x80000
	// Position of B1268 field.
	GTZC_VCTR39_B1268_Pos = 0x14
	// Bit mask of B1268 field.
	GTZC_VCTR39_B1268_Msk = 0x100000
	// Bit B1268.
	GTZC_VCTR39_B1268 = 0x100000
	// Position of B1269 field.
	GTZC_VCTR39_B1269_Pos = 0x15
	// Bit mask of B1269 field.
	GTZC_VCTR39_B1269_Msk = 0x200000
	// Bit B1269.
	GTZC_VCTR39_B1269 = 0x200000
	// Position of B1270 field.
	GTZC_VCTR39_B1270_Pos = 0x16
	// Bit mask of B1270 field.
	GTZC_VCTR39_B1270_Msk = 0x400000
	// Bit B1270.
	GTZC_VCTR39_B1270 = 0x400000
	// Position of B1271 field.
	GTZC_VCTR39_B1271_Pos = 0x17
	// Bit mask of B1271 field.
	GTZC_VCTR39_B1271_Msk = 0x800000
	// Bit B1271.
	GTZC_VCTR39_B1271 = 0x800000
	// Position of B1272 field.
	GTZC_VCTR39_B1272_Pos = 0x18
	// Bit mask of B1272 field.
	GTZC_VCTR39_B1272_Msk = 0x1000000
	// Bit B1272.
	GTZC_VCTR39_B1272 = 0x1000000
	// Position of B1273 field.
	GTZC_VCTR39_B1273_Pos = 0x19
	// Bit mask of B1273 field.
	GTZC_VCTR39_B1273_Msk = 0x2000000
	// Bit B1273.
	GTZC_VCTR39_B1273 = 0x2000000
	// Position of B1274 field.
	GTZC_VCTR39_B1274_Pos = 0x1a
	// Bit mask of B1274 field.
	GTZC_VCTR39_B1274_Msk = 0x4000000
	// Bit B1274.
	GTZC_VCTR39_B1274 = 0x4000000
	// Position of B1275 field.
	GTZC_VCTR39_B1275_Pos = 0x1b
	// Bit mask of B1275 field.
	GTZC_VCTR39_B1275_Msk = 0x8000000
	// Bit B1275.
	GTZC_VCTR39_B1275 = 0x8000000
	// Position of B1276 field.
	GTZC_VCTR39_B1276_Pos = 0x1c
	// Bit mask of B1276 field.
	GTZC_VCTR39_B1276_Msk = 0x10000000
	// Bit B1276.
	GTZC_VCTR39_B1276 = 0x10000000
	// Position of B1277 field.
	GTZC_VCTR39_B1277_Pos = 0x1d
	// Bit mask of B1277 field.
	GTZC_VCTR39_B1277_Msk = 0x20000000
	// Bit B1277.
	GTZC_VCTR39_B1277 = 0x20000000
	// Position of B1278 field.
	GTZC_VCTR39_B1278_Pos = 0x1e
	// Bit mask of B1278 field.
	GTZC_VCTR39_B1278_Msk = 0x40000000
	// Bit B1278.
	GTZC_VCTR39_B1278 = 0x40000000
	// Position of B1279 field.
	GTZC_VCTR39_B1279_Pos = 0x1f
	// Bit mask of B1279 field.
	GTZC_VCTR39_B1279_Msk = 0x80000000
	// Bit B1279.
	GTZC_VCTR39_B1279 = 0x80000000

	// VCTR40: MPCBBx vector register
	// Position of B1280 field.
	GTZC_VCTR40_B1280_Pos = 0x0
	// Bit mask of B1280 field.
	GTZC_VCTR40_B1280_Msk = 0x1
	// Bit B1280.
	GTZC_VCTR40_B1280 = 0x1
	// Position of B1281 field.
	GTZC_VCTR40_B1281_Pos = 0x1
	// Bit mask of B1281 field.
	GTZC_VCTR40_B1281_Msk = 0x2
	// Bit B1281.
	GTZC_VCTR40_B1281 = 0x2
	// Position of B1282 field.
	GTZC_VCTR40_B1282_Pos = 0x2
	// Bit mask of B1282 field.
	GTZC_VCTR40_B1282_Msk = 0x4
	// Bit B1282.
	GTZC_VCTR40_B1282 = 0x4
	// Position of B1283 field.
	GTZC_VCTR40_B1283_Pos = 0x3
	// Bit mask of B1283 field.
	GTZC_VCTR40_B1283_Msk = 0x8
	// Bit B1283.
	GTZC_VCTR40_B1283 = 0x8
	// Position of B1284 field.
	GTZC_VCTR40_B1284_Pos = 0x4
	// Bit mask of B1284 field.
	GTZC_VCTR40_B1284_Msk = 0x10
	// Bit B1284.
	GTZC_VCTR40_B1284 = 0x10
	// Position of B1285 field.
	GTZC_VCTR40_B1285_Pos = 0x5
	// Bit mask of B1285 field.
	GTZC_VCTR40_B1285_Msk = 0x20
	// Bit B1285.
	GTZC_VCTR40_B1285 = 0x20
	// Position of B1286 field.
	GTZC_VCTR40_B1286_Pos = 0x6
	// Bit mask of B1286 field.
	GTZC_VCTR40_B1286_Msk = 0x40
	// Bit B1286.
	GTZC_VCTR40_B1286 = 0x40
	// Position of B1287 field.
	GTZC_VCTR40_B1287_Pos = 0x7
	// Bit mask of B1287 field.
	GTZC_VCTR40_B1287_Msk = 0x80
	// Bit B1287.
	GTZC_VCTR40_B1287 = 0x80
	// Position of B1288 field.
	GTZC_VCTR40_B1288_Pos = 0x8
	// Bit mask of B1288 field.
	GTZC_VCTR40_B1288_Msk = 0x100
	// Bit B1288.
	GTZC_VCTR40_B1288 = 0x100
	// Position of B1289 field.
	GTZC_VCTR40_B1289_Pos = 0x9
	// Bit mask of B1289 field.
	GTZC_VCTR40_B1289_Msk = 0x200
	// Bit B1289.
	GTZC_VCTR40_B1289 = 0x200
	// Position of B1290 field.
	GTZC_VCTR40_B1290_Pos = 0xa
	// Bit mask of B1290 field.
	GTZC_VCTR40_B1290_Msk = 0x400
	// Bit B1290.
	GTZC_VCTR40_B1290 = 0x400
	// Position of B1291 field.
	GTZC_VCTR40_B1291_Pos = 0xb
	// Bit mask of B1291 field.
	GTZC_VCTR40_B1291_Msk = 0x800
	// Bit B1291.
	GTZC_VCTR40_B1291 = 0x800
	// Position of B1292 field.
	GTZC_VCTR40_B1292_Pos = 0xc
	// Bit mask of B1292 field.
	GTZC_VCTR40_B1292_Msk = 0x1000
	// Bit B1292.
	GTZC_VCTR40_B1292 = 0x1000
	// Position of B1293 field.
	GTZC_VCTR40_B1293_Pos = 0xd
	// Bit mask of B1293 field.
	GTZC_VCTR40_B1293_Msk = 0x2000
	// Bit B1293.
	GTZC_VCTR40_B1293 = 0x2000
	// Position of B1294 field.
	GTZC_VCTR40_B1294_Pos = 0xe
	// Bit mask of B1294 field.
	GTZC_VCTR40_B1294_Msk = 0x4000
	// Bit B1294.
	GTZC_VCTR40_B1294 = 0x4000
	// Position of B1295 field.
	GTZC_VCTR40_B1295_Pos = 0xf
	// Bit mask of B1295 field.
	GTZC_VCTR40_B1295_Msk = 0x8000
	// Bit B1295.
	GTZC_VCTR40_B1295 = 0x8000
	// Position of B1296 field.
	GTZC_VCTR40_B1296_Pos = 0x10
	// Bit mask of B1296 field.
	GTZC_VCTR40_B1296_Msk = 0x10000
	// Bit B1296.
	GTZC_VCTR40_B1296 = 0x10000
	// Position of B1297 field.
	GTZC_VCTR40_B1297_Pos = 0x11
	// Bit mask of B1297 field.
	GTZC_VCTR40_B1297_Msk = 0x20000
	// Bit B1297.
	GTZC_VCTR40_B1297 = 0x20000
	// Position of B1298 field.
	GTZC_VCTR40_B1298_Pos = 0x12
	// Bit mask of B1298 field.
	GTZC_VCTR40_B1298_Msk = 0x40000
	// Bit B1298.
	GTZC_VCTR40_B1298 = 0x40000
	// Position of B1299 field.
	GTZC_VCTR40_B1299_Pos = 0x13
	// Bit mask of B1299 field.
	GTZC_VCTR40_B1299_Msk = 0x80000
	// Bit B1299.
	GTZC_VCTR40_B1299 = 0x80000
	// Position of B1300 field.
	GTZC_VCTR40_B1300_Pos = 0x14
	// Bit mask of B1300 field.
	GTZC_VCTR40_B1300_Msk = 0x100000
	// Bit B1300.
	GTZC_VCTR40_B1300 = 0x100000
	// Position of B1301 field.
	GTZC_VCTR40_B1301_Pos = 0x15
	// Bit mask of B1301 field.
	GTZC_VCTR40_B1301_Msk = 0x200000
	// Bit B1301.
	GTZC_VCTR40_B1301 = 0x200000
	// Position of B1302 field.
	GTZC_VCTR40_B1302_Pos = 0x16
	// Bit mask of B1302 field.
	GTZC_VCTR40_B1302_Msk = 0x400000
	// Bit B1302.
	GTZC_VCTR40_B1302 = 0x400000
	// Position of B1303 field.
	GTZC_VCTR40_B1303_Pos = 0x17
	// Bit mask of B1303 field.
	GTZC_VCTR40_B1303_Msk = 0x800000
	// Bit B1303.
	GTZC_VCTR40_B1303 = 0x800000
	// Position of B1304 field.
	GTZC_VCTR40_B1304_Pos = 0x18
	// Bit mask of B1304 field.
	GTZC_VCTR40_B1304_Msk = 0x1000000
	// Bit B1304.
	GTZC_VCTR40_B1304 = 0x1000000
	// Position of B1305 field.
	GTZC_VCTR40_B1305_Pos = 0x19
	// Bit mask of B1305 field.
	GTZC_VCTR40_B1305_Msk = 0x2000000
	// Bit B1305.
	GTZC_VCTR40_B1305 = 0x2000000
	// Position of B1306 field.
	GTZC_VCTR40_B1306_Pos = 0x1a
	// Bit mask of B1306 field.
	GTZC_VCTR40_B1306_Msk = 0x4000000
	// Bit B1306.
	GTZC_VCTR40_B1306 = 0x4000000
	// Position of B1307 field.
	GTZC_VCTR40_B1307_Pos = 0x1b
	// Bit mask of B1307 field.
	GTZC_VCTR40_B1307_Msk = 0x8000000
	// Bit B1307.
	GTZC_VCTR40_B1307 = 0x8000000
	// Position of B1308 field.
	GTZC_VCTR40_B1308_Pos = 0x1c
	// Bit mask of B1308 field.
	GTZC_VCTR40_B1308_Msk = 0x10000000
	// Bit B1308.
	GTZC_VCTR40_B1308 = 0x10000000
	// Position of B1309 field.
	GTZC_VCTR40_B1309_Pos = 0x1d
	// Bit mask of B1309 field.
	GTZC_VCTR40_B1309_Msk = 0x20000000
	// Bit B1309.
	GTZC_VCTR40_B1309 = 0x20000000
	// Position of B1310 field.
	GTZC_VCTR40_B1310_Pos = 0x1e
	// Bit mask of B1310 field.
	GTZC_VCTR40_B1310_Msk = 0x40000000
	// Bit B1310.
	GTZC_VCTR40_B1310 = 0x40000000
	// Position of B1311 field.
	GTZC_VCTR40_B1311_Pos = 0x1f
	// Bit mask of B1311 field.
	GTZC_VCTR40_B1311_Msk = 0x80000000
	// Bit B1311.
	GTZC_VCTR40_B1311 = 0x80000000

	// VCTR41: MPCBBx vector register
	// Position of B1312 field.
	GTZC_VCTR41_B1312_Pos = 0x0
	// Bit mask of B1312 field.
	GTZC_VCTR41_B1312_Msk = 0x1
	// Bit B1312.
	GTZC_VCTR41_B1312 = 0x1
	// Position of B1313 field.
	GTZC_VCTR41_B1313_Pos = 0x1
	// Bit mask of B1313 field.
	GTZC_VCTR41_B1313_Msk = 0x2
	// Bit B1313.
	GTZC_VCTR41_B1313 = 0x2
	// Position of B1314 field.
	GTZC_VCTR41_B1314_Pos = 0x2
	// Bit mask of B1314 field.
	GTZC_VCTR41_B1314_Msk = 0x4
	// Bit B1314.
	GTZC_VCTR41_B1314 = 0x4
	// Position of B1315 field.
	GTZC_VCTR41_B1315_Pos = 0x3
	// Bit mask of B1315 field.
	GTZC_VCTR41_B1315_Msk = 0x8
	// Bit B1315.
	GTZC_VCTR41_B1315 = 0x8
	// Position of B1316 field.
	GTZC_VCTR41_B1316_Pos = 0x4
	// Bit mask of B1316 field.
	GTZC_VCTR41_B1316_Msk = 0x10
	// Bit B1316.
	GTZC_VCTR41_B1316 = 0x10
	// Position of B1317 field.
	GTZC_VCTR41_B1317_Pos = 0x5
	// Bit mask of B1317 field.
	GTZC_VCTR41_B1317_Msk = 0x20
	// Bit B1317.
	GTZC_VCTR41_B1317 = 0x20
	// Position of B1318 field.
	GTZC_VCTR41_B1318_Pos = 0x6
	// Bit mask of B1318 field.
	GTZC_VCTR41_B1318_Msk = 0x40
	// Bit B1318.
	GTZC_VCTR41_B1318 = 0x40
	// Position of B1319 field.
	GTZC_VCTR41_B1319_Pos = 0x7
	// Bit mask of B1319 field.
	GTZC_VCTR41_B1319_Msk = 0x80
	// Bit B1319.
	GTZC_VCTR41_B1319 = 0x80
	// Position of B1320 field.
	GTZC_VCTR41_B1320_Pos = 0x8
	// Bit mask of B1320 field.
	GTZC_VCTR41_B1320_Msk = 0x100
	// Bit B1320.
	GTZC_VCTR41_B1320 = 0x100
	// Position of B1321 field.
	GTZC_VCTR41_B1321_Pos = 0x9
	// Bit mask of B1321 field.
	GTZC_VCTR41_B1321_Msk = 0x200
	// Bit B1321.
	GTZC_VCTR41_B1321 = 0x200
	// Position of B1322 field.
	GTZC_VCTR41_B1322_Pos = 0xa
	// Bit mask of B1322 field.
	GTZC_VCTR41_B1322_Msk = 0x400
	// Bit B1322.
	GTZC_VCTR41_B1322 = 0x400
	// Position of B1323 field.
	GTZC_VCTR41_B1323_Pos = 0xb
	// Bit mask of B1323 field.
	GTZC_VCTR41_B1323_Msk = 0x800
	// Bit B1323.
	GTZC_VCTR41_B1323 = 0x800
	// Position of B1324 field.
	GTZC_VCTR41_B1324_Pos = 0xc
	// Bit mask of B1324 field.
	GTZC_VCTR41_B1324_Msk = 0x1000
	// Bit B1324.
	GTZC_VCTR41_B1324 = 0x1000
	// Position of B1325 field.
	GTZC_VCTR41_B1325_Pos = 0xd
	// Bit mask of B1325 field.
	GTZC_VCTR41_B1325_Msk = 0x2000
	// Bit B1325.
	GTZC_VCTR41_B1325 = 0x2000
	// Position of B1326 field.
	GTZC_VCTR41_B1326_Pos = 0xe
	// Bit mask of B1326 field.
	GTZC_VCTR41_B1326_Msk = 0x4000
	// Bit B1326.
	GTZC_VCTR41_B1326 = 0x4000
	// Position of B1327 field.
	GTZC_VCTR41_B1327_Pos = 0xf
	// Bit mask of B1327 field.
	GTZC_VCTR41_B1327_Msk = 0x8000
	// Bit B1327.
	GTZC_VCTR41_B1327 = 0x8000
	// Position of B1328 field.
	GTZC_VCTR41_B1328_Pos = 0x10
	// Bit mask of B1328 field.
	GTZC_VCTR41_B1328_Msk = 0x10000
	// Bit B1328.
	GTZC_VCTR41_B1328 = 0x10000
	// Position of B1329 field.
	GTZC_VCTR41_B1329_Pos = 0x11
	// Bit mask of B1329 field.
	GTZC_VCTR41_B1329_Msk = 0x20000
	// Bit B1329.
	GTZC_VCTR41_B1329 = 0x20000
	// Position of B1330 field.
	GTZC_VCTR41_B1330_Pos = 0x12
	// Bit mask of B1330 field.
	GTZC_VCTR41_B1330_Msk = 0x40000
	// Bit B1330.
	GTZC_VCTR41_B1330 = 0x40000
	// Position of B1331 field.
	GTZC_VCTR41_B1331_Pos = 0x13
	// Bit mask of B1331 field.
	GTZC_VCTR41_B1331_Msk = 0x80000
	// Bit B1331.
	GTZC_VCTR41_B1331 = 0x80000
	// Position of B1332 field.
	GTZC_VCTR41_B1332_Pos = 0x14
	// Bit mask of B1332 field.
	GTZC_VCTR41_B1332_Msk = 0x100000
	// Bit B1332.
	GTZC_VCTR41_B1332 = 0x100000
	// Position of B1333 field.
	GTZC_VCTR41_B1333_Pos = 0x15
	// Bit mask of B1333 field.
	GTZC_VCTR41_B1333_Msk = 0x200000
	// Bit B1333.
	GTZC_VCTR41_B1333 = 0x200000
	// Position of B1334 field.
	GTZC_VCTR41_B1334_Pos = 0x16
	// Bit mask of B1334 field.
	GTZC_VCTR41_B1334_Msk = 0x400000
	// Bit B1334.
	GTZC_VCTR41_B1334 = 0x400000
	// Position of B1335 field.
	GTZC_VCTR41_B1335_Pos = 0x17
	// Bit mask of B1335 field.
	GTZC_VCTR41_B1335_Msk = 0x800000
	// Bit B1335.
	GTZC_VCTR41_B1335 = 0x800000
	// Position of B1336 field.
	GTZC_VCTR41_B1336_Pos = 0x18
	// Bit mask of B1336 field.
	GTZC_VCTR41_B1336_Msk = 0x1000000
	// Bit B1336.
	GTZC_VCTR41_B1336 = 0x1000000
	// Position of B1337 field.
	GTZC_VCTR41_B1337_Pos = 0x19
	// Bit mask of B1337 field.
	GTZC_VCTR41_B1337_Msk = 0x2000000
	// Bit B1337.
	GTZC_VCTR41_B1337 = 0x2000000
	// Position of B1338 field.
	GTZC_VCTR41_B1338_Pos = 0x1a
	// Bit mask of B1338 field.
	GTZC_VCTR41_B1338_Msk = 0x4000000
	// Bit B1338.
	GTZC_VCTR41_B1338 = 0x4000000
	// Position of B1339 field.
	GTZC_VCTR41_B1339_Pos = 0x1b
	// Bit mask of B1339 field.
	GTZC_VCTR41_B1339_Msk = 0x8000000
	// Bit B1339.
	GTZC_VCTR41_B1339 = 0x8000000
	// Position of B1340 field.
	GTZC_VCTR41_B1340_Pos = 0x1c
	// Bit mask of B1340 field.
	GTZC_VCTR41_B1340_Msk = 0x10000000
	// Bit B1340.
	GTZC_VCTR41_B1340 = 0x10000000
	// Position of B1341 field.
	GTZC_VCTR41_B1341_Pos = 0x1d
	// Bit mask of B1341 field.
	GTZC_VCTR41_B1341_Msk = 0x20000000
	// Bit B1341.
	GTZC_VCTR41_B1341 = 0x20000000
	// Position of B1342 field.
	GTZC_VCTR41_B1342_Pos = 0x1e
	// Bit mask of B1342 field.
	GTZC_VCTR41_B1342_Msk = 0x40000000
	// Bit B1342.
	GTZC_VCTR41_B1342 = 0x40000000
	// Position of B1343 field.
	GTZC_VCTR41_B1343_Pos = 0x1f
	// Bit mask of B1343 field.
	GTZC_VCTR41_B1343_Msk = 0x80000000
	// Bit B1343.
	GTZC_VCTR41_B1343 = 0x80000000

	// VCTR42: MPCBBx vector register
	// Position of B1344 field.
	GTZC_VCTR42_B1344_Pos = 0x0
	// Bit mask of B1344 field.
	GTZC_VCTR42_B1344_Msk = 0x1
	// Bit B1344.
	GTZC_VCTR42_B1344 = 0x1
	// Position of B1345 field.
	GTZC_VCTR42_B1345_Pos = 0x1
	// Bit mask of B1345 field.
	GTZC_VCTR42_B1345_Msk = 0x2
	// Bit B1345.
	GTZC_VCTR42_B1345 = 0x2
	// Position of B1346 field.
	GTZC_VCTR42_B1346_Pos = 0x2
	// Bit mask of B1346 field.
	GTZC_VCTR42_B1346_Msk = 0x4
	// Bit B1346.
	GTZC_VCTR42_B1346 = 0x4
	// Position of B1347 field.
	GTZC_VCTR42_B1347_Pos = 0x3
	// Bit mask of B1347 field.
	GTZC_VCTR42_B1347_Msk = 0x8
	// Bit B1347.
	GTZC_VCTR42_B1347 = 0x8
	// Position of B1348 field.
	GTZC_VCTR42_B1348_Pos = 0x4
	// Bit mask of B1348 field.
	GTZC_VCTR42_B1348_Msk = 0x10
	// Bit B1348.
	GTZC_VCTR42_B1348 = 0x10
	// Position of B1349 field.
	GTZC_VCTR42_B1349_Pos = 0x5
	// Bit mask of B1349 field.
	GTZC_VCTR42_B1349_Msk = 0x20
	// Bit B1349.
	GTZC_VCTR42_B1349 = 0x20
	// Position of B1350 field.
	GTZC_VCTR42_B1350_Pos = 0x6
	// Bit mask of B1350 field.
	GTZC_VCTR42_B1350_Msk = 0x40
	// Bit B1350.
	GTZC_VCTR42_B1350 = 0x40
	// Position of B1351 field.
	GTZC_VCTR42_B1351_Pos = 0x7
	// Bit mask of B1351 field.
	GTZC_VCTR42_B1351_Msk = 0x80
	// Bit B1351.
	GTZC_VCTR42_B1351 = 0x80
	// Position of B1352 field.
	GTZC_VCTR42_B1352_Pos = 0x8
	// Bit mask of B1352 field.
	GTZC_VCTR42_B1352_Msk = 0x100
	// Bit B1352.
	GTZC_VCTR42_B1352 = 0x100
	// Position of B1353 field.
	GTZC_VCTR42_B1353_Pos = 0x9
	// Bit mask of B1353 field.
	GTZC_VCTR42_B1353_Msk = 0x200
	// Bit B1353.
	GTZC_VCTR42_B1353 = 0x200
	// Position of B1354 field.
	GTZC_VCTR42_B1354_Pos = 0xa
	// Bit mask of B1354 field.
	GTZC_VCTR42_B1354_Msk = 0x400
	// Bit B1354.
	GTZC_VCTR42_B1354 = 0x400
	// Position of B1355 field.
	GTZC_VCTR42_B1355_Pos = 0xb
	// Bit mask of B1355 field.
	GTZC_VCTR42_B1355_Msk = 0x800
	// Bit B1355.
	GTZC_VCTR42_B1355 = 0x800
	// Position of B1356 field.
	GTZC_VCTR42_B1356_Pos = 0xc
	// Bit mask of B1356 field.
	GTZC_VCTR42_B1356_Msk = 0x1000
	// Bit B1356.
	GTZC_VCTR42_B1356 = 0x1000
	// Position of B1357 field.
	GTZC_VCTR42_B1357_Pos = 0xd
	// Bit mask of B1357 field.
	GTZC_VCTR42_B1357_Msk = 0x2000
	// Bit B1357.
	GTZC_VCTR42_B1357 = 0x2000
	// Position of B1358 field.
	GTZC_VCTR42_B1358_Pos = 0xe
	// Bit mask of B1358 field.
	GTZC_VCTR42_B1358_Msk = 0x4000
	// Bit B1358.
	GTZC_VCTR42_B1358 = 0x4000
	// Position of B1359 field.
	GTZC_VCTR42_B1359_Pos = 0xf
	// Bit mask of B1359 field.
	GTZC_VCTR42_B1359_Msk = 0x8000
	// Bit B1359.
	GTZC_VCTR42_B1359 = 0x8000
	// Position of B1360 field.
	GTZC_VCTR42_B1360_Pos = 0x10
	// Bit mask of B1360 field.
	GTZC_VCTR42_B1360_Msk = 0x10000
	// Bit B1360.
	GTZC_VCTR42_B1360 = 0x10000
	// Position of B1361 field.
	GTZC_VCTR42_B1361_Pos = 0x11
	// Bit mask of B1361 field.
	GTZC_VCTR42_B1361_Msk = 0x20000
	// Bit B1361.
	GTZC_VCTR42_B1361 = 0x20000
	// Position of B1362 field.
	GTZC_VCTR42_B1362_Pos = 0x12
	// Bit mask of B1362 field.
	GTZC_VCTR42_B1362_Msk = 0x40000
	// Bit B1362.
	GTZC_VCTR42_B1362 = 0x40000
	// Position of B1363 field.
	GTZC_VCTR42_B1363_Pos = 0x13
	// Bit mask of B1363 field.
	GTZC_VCTR42_B1363_Msk = 0x80000
	// Bit B1363.
	GTZC_VCTR42_B1363 = 0x80000
	// Position of B1364 field.
	GTZC_VCTR42_B1364_Pos = 0x14
	// Bit mask of B1364 field.
	GTZC_VCTR42_B1364_Msk = 0x100000
	// Bit B1364.
	GTZC_VCTR42_B1364 = 0x100000
	// Position of B1365 field.
	GTZC_VCTR42_B1365_Pos = 0x15
	// Bit mask of B1365 field.
	GTZC_VCTR42_B1365_Msk = 0x200000
	// Bit B1365.
	GTZC_VCTR42_B1365 = 0x200000
	// Position of B1366 field.
	GTZC_VCTR42_B1366_Pos = 0x16
	// Bit mask of B1366 field.
	GTZC_VCTR42_B1366_Msk = 0x400000
	// Bit B1366.
	GTZC_VCTR42_B1366 = 0x400000
	// Position of B1367 field.
	GTZC_VCTR42_B1367_Pos = 0x17
	// Bit mask of B1367 field.
	GTZC_VCTR42_B1367_Msk = 0x800000
	// Bit B1367.
	GTZC_VCTR42_B1367 = 0x800000
	// Position of B1368 field.
	GTZC_VCTR42_B1368_Pos = 0x18
	// Bit mask of B1368 field.
	GTZC_VCTR42_B1368_Msk = 0x1000000
	// Bit B1368.
	GTZC_VCTR42_B1368 = 0x1000000
	// Position of B1369 field.
	GTZC_VCTR42_B1369_Pos = 0x19
	// Bit mask of B1369 field.
	GTZC_VCTR42_B1369_Msk = 0x2000000
	// Bit B1369.
	GTZC_VCTR42_B1369 = 0x2000000
	// Position of B1370 field.
	GTZC_VCTR42_B1370_Pos = 0x1a
	// Bit mask of B1370 field.
	GTZC_VCTR42_B1370_Msk = 0x4000000
	// Bit B1370.
	GTZC_VCTR42_B1370 = 0x4000000
	// Position of B1371 field.
	GTZC_VCTR42_B1371_Pos = 0x1b
	// Bit mask of B1371 field.
	GTZC_VCTR42_B1371_Msk = 0x8000000
	// Bit B1371.
	GTZC_VCTR42_B1371 = 0x8000000
	// Position of B1372 field.
	GTZC_VCTR42_B1372_Pos = 0x1c
	// Bit mask of B1372 field.
	GTZC_VCTR42_B1372_Msk = 0x10000000
	// Bit B1372.
	GTZC_VCTR42_B1372 = 0x10000000
	// Position of B1373 field.
	GTZC_VCTR42_B1373_Pos = 0x1d
	// Bit mask of B1373 field.
	GTZC_VCTR42_B1373_Msk = 0x20000000
	// Bit B1373.
	GTZC_VCTR42_B1373 = 0x20000000
	// Position of B1374 field.
	GTZC_VCTR42_B1374_Pos = 0x1e
	// Bit mask of B1374 field.
	GTZC_VCTR42_B1374_Msk = 0x40000000
	// Bit B1374.
	GTZC_VCTR42_B1374 = 0x40000000
	// Position of B1375 field.
	GTZC_VCTR42_B1375_Pos = 0x1f
	// Bit mask of B1375 field.
	GTZC_VCTR42_B1375_Msk = 0x80000000
	// Bit B1375.
	GTZC_VCTR42_B1375 = 0x80000000

	// VCTR43: MPCBBx vector register
	// Position of B1376 field.
	GTZC_VCTR43_B1376_Pos = 0x0
	// Bit mask of B1376 field.
	GTZC_VCTR43_B1376_Msk = 0x1
	// Bit B1376.
	GTZC_VCTR43_B1376 = 0x1
	// Position of B1377 field.
	GTZC_VCTR43_B1377_Pos = 0x1
	// Bit mask of B1377 field.
	GTZC_VCTR43_B1377_Msk = 0x2
	// Bit B1377.
	GTZC_VCTR43_B1377 = 0x2
	// Position of B1378 field.
	GTZC_VCTR43_B1378_Pos = 0x2
	// Bit mask of B1378 field.
	GTZC_VCTR43_B1378_Msk = 0x4
	// Bit B1378.
	GTZC_VCTR43_B1378 = 0x4
	// Position of B1379 field.
	GTZC_VCTR43_B1379_Pos = 0x3
	// Bit mask of B1379 field.
	GTZC_VCTR43_B1379_Msk = 0x8
	// Bit B1379.
	GTZC_VCTR43_B1379 = 0x8
	// Position of B1380 field.
	GTZC_VCTR43_B1380_Pos = 0x4
	// Bit mask of B1380 field.
	GTZC_VCTR43_B1380_Msk = 0x10
	// Bit B1380.
	GTZC_VCTR43_B1380 = 0x10
	// Position of B1381 field.
	GTZC_VCTR43_B1381_Pos = 0x5
	// Bit mask of B1381 field.
	GTZC_VCTR43_B1381_Msk = 0x20
	// Bit B1381.
	GTZC_VCTR43_B1381 = 0x20
	// Position of B1382 field.
	GTZC_VCTR43_B1382_Pos = 0x6
	// Bit mask of B1382 field.
	GTZC_VCTR43_B1382_Msk = 0x40
	// Bit B1382.
	GTZC_VCTR43_B1382 = 0x40
	// Position of B1383 field.
	GTZC_VCTR43_B1383_Pos = 0x7
	// Bit mask of B1383 field.
	GTZC_VCTR43_B1383_Msk = 0x80
	// Bit B1383.
	GTZC_VCTR43_B1383 = 0x80
	// Position of B1384 field.
	GTZC_VCTR43_B1384_Pos = 0x8
	// Bit mask of B1384 field.
	GTZC_VCTR43_B1384_Msk = 0x100
	// Bit B1384.
	GTZC_VCTR43_B1384 = 0x100
	// Position of B1385 field.
	GTZC_VCTR43_B1385_Pos = 0x9
	// Bit mask of B1385 field.
	GTZC_VCTR43_B1385_Msk = 0x200
	// Bit B1385.
	GTZC_VCTR43_B1385 = 0x200
	// Position of B1386 field.
	GTZC_VCTR43_B1386_Pos = 0xa
	// Bit mask of B1386 field.
	GTZC_VCTR43_B1386_Msk = 0x400
	// Bit B1386.
	GTZC_VCTR43_B1386 = 0x400
	// Position of B1387 field.
	GTZC_VCTR43_B1387_Pos = 0xb
	// Bit mask of B1387 field.
	GTZC_VCTR43_B1387_Msk = 0x800
	// Bit B1387.
	GTZC_VCTR43_B1387 = 0x800
	// Position of B1388 field.
	GTZC_VCTR43_B1388_Pos = 0xc
	// Bit mask of B1388 field.
	GTZC_VCTR43_B1388_Msk = 0x1000
	// Bit B1388.
	GTZC_VCTR43_B1388 = 0x1000
	// Position of B1389 field.
	GTZC_VCTR43_B1389_Pos = 0xd
	// Bit mask of B1389 field.
	GTZC_VCTR43_B1389_Msk = 0x2000
	// Bit B1389.
	GTZC_VCTR43_B1389 = 0x2000
	// Position of B1390 field.
	GTZC_VCTR43_B1390_Pos = 0xe
	// Bit mask of B1390 field.
	GTZC_VCTR43_B1390_Msk = 0x4000
	// Bit B1390.
	GTZC_VCTR43_B1390 = 0x4000
	// Position of B1391 field.
	GTZC_VCTR43_B1391_Pos = 0xf
	// Bit mask of B1391 field.
	GTZC_VCTR43_B1391_Msk = 0x8000
	// Bit B1391.
	GTZC_VCTR43_B1391 = 0x8000
	// Position of B1392 field.
	GTZC_VCTR43_B1392_Pos = 0x10
	// Bit mask of B1392 field.
	GTZC_VCTR43_B1392_Msk = 0x10000
	// Bit B1392.
	GTZC_VCTR43_B1392 = 0x10000
	// Position of B1393 field.
	GTZC_VCTR43_B1393_Pos = 0x11
	// Bit mask of B1393 field.
	GTZC_VCTR43_B1393_Msk = 0x20000
	// Bit B1393.
	GTZC_VCTR43_B1393 = 0x20000
	// Position of B1394 field.
	GTZC_VCTR43_B1394_Pos = 0x12
	// Bit mask of B1394 field.
	GTZC_VCTR43_B1394_Msk = 0x40000
	// Bit B1394.
	GTZC_VCTR43_B1394 = 0x40000
	// Position of B1395 field.
	GTZC_VCTR43_B1395_Pos = 0x13
	// Bit mask of B1395 field.
	GTZC_VCTR43_B1395_Msk = 0x80000
	// Bit B1395.
	GTZC_VCTR43_B1395 = 0x80000
	// Position of B1396 field.
	GTZC_VCTR43_B1396_Pos = 0x14
	// Bit mask of B1396 field.
	GTZC_VCTR43_B1396_Msk = 0x100000
	// Bit B1396.
	GTZC_VCTR43_B1396 = 0x100000
	// Position of B1397 field.
	GTZC_VCTR43_B1397_Pos = 0x15
	// Bit mask of B1397 field.
	GTZC_VCTR43_B1397_Msk = 0x200000
	// Bit B1397.
	GTZC_VCTR43_B1397 = 0x200000
	// Position of B1398 field.
	GTZC_VCTR43_B1398_Pos = 0x16
	// Bit mask of B1398 field.
	GTZC_VCTR43_B1398_Msk = 0x400000
	// Bit B1398.
	GTZC_VCTR43_B1398 = 0x400000
	// Position of B1399 field.
	GTZC_VCTR43_B1399_Pos = 0x17
	// Bit mask of B1399 field.
	GTZC_VCTR43_B1399_Msk = 0x800000
	// Bit B1399.
	GTZC_VCTR43_B1399 = 0x800000
	// Position of B1400 field.
	GTZC_VCTR43_B1400_Pos = 0x18
	// Bit mask of B1400 field.
	GTZC_VCTR43_B1400_Msk = 0x1000000
	// Bit B1400.
	GTZC_VCTR43_B1400 = 0x1000000
	// Position of B1401 field.
	GTZC_VCTR43_B1401_Pos = 0x19
	// Bit mask of B1401 field.
	GTZC_VCTR43_B1401_Msk = 0x2000000
	// Bit B1401.
	GTZC_VCTR43_B1401 = 0x2000000
	// Position of B1402 field.
	GTZC_VCTR43_B1402_Pos = 0x1a
	// Bit mask of B1402 field.
	GTZC_VCTR43_B1402_Msk = 0x4000000
	// Bit B1402.
	GTZC_VCTR43_B1402 = 0x4000000
	// Position of B1403 field.
	GTZC_VCTR43_B1403_Pos = 0x1b
	// Bit mask of B1403 field.
	GTZC_VCTR43_B1403_Msk = 0x8000000
	// Bit B1403.
	GTZC_VCTR43_B1403 = 0x8000000
	// Position of B1404 field.
	GTZC_VCTR43_B1404_Pos = 0x1c
	// Bit mask of B1404 field.
	GTZC_VCTR43_B1404_Msk = 0x10000000
	// Bit B1404.
	GTZC_VCTR43_B1404 = 0x10000000
	// Position of B1405 field.
	GTZC_VCTR43_B1405_Pos = 0x1d
	// Bit mask of B1405 field.
	GTZC_VCTR43_B1405_Msk = 0x20000000
	// Bit B1405.
	GTZC_VCTR43_B1405 = 0x20000000
	// Position of B1406 field.
	GTZC_VCTR43_B1406_Pos = 0x1e
	// Bit mask of B1406 field.
	GTZC_VCTR43_B1406_Msk = 0x40000000
	// Bit B1406.
	GTZC_VCTR43_B1406 = 0x40000000
	// Position of B1407 field.
	GTZC_VCTR43_B1407_Pos = 0x1f
	// Bit mask of B1407 field.
	GTZC_VCTR43_B1407_Msk = 0x80000000
	// Bit B1407.
	GTZC_VCTR43_B1407 = 0x80000000

	// VCTR44: MPCBBx vector register
	// Position of B1408 field.
	GTZC_VCTR44_B1408_Pos = 0x0
	// Bit mask of B1408 field.
	GTZC_VCTR44_B1408_Msk = 0x1
	// Bit B1408.
	GTZC_VCTR44_B1408 = 0x1
	// Position of B1409 field.
	GTZC_VCTR44_B1409_Pos = 0x1
	// Bit mask of B1409 field.
	GTZC_VCTR44_B1409_Msk = 0x2
	// Bit B1409.
	GTZC_VCTR44_B1409 = 0x2
	// Position of B1410 field.
	GTZC_VCTR44_B1410_Pos = 0x2
	// Bit mask of B1410 field.
	GTZC_VCTR44_B1410_Msk = 0x4
	// Bit B1410.
	GTZC_VCTR44_B1410 = 0x4
	// Position of B1411 field.
	GTZC_VCTR44_B1411_Pos = 0x3
	// Bit mask of B1411 field.
	GTZC_VCTR44_B1411_Msk = 0x8
	// Bit B1411.
	GTZC_VCTR44_B1411 = 0x8
	// Position of B1412 field.
	GTZC_VCTR44_B1412_Pos = 0x4
	// Bit mask of B1412 field.
	GTZC_VCTR44_B1412_Msk = 0x10
	// Bit B1412.
	GTZC_VCTR44_B1412 = 0x10
	// Position of B1413 field.
	GTZC_VCTR44_B1413_Pos = 0x5
	// Bit mask of B1413 field.
	GTZC_VCTR44_B1413_Msk = 0x20
	// Bit B1413.
	GTZC_VCTR44_B1413 = 0x20
	// Position of B1414 field.
	GTZC_VCTR44_B1414_Pos = 0x6
	// Bit mask of B1414 field.
	GTZC_VCTR44_B1414_Msk = 0x40
	// Bit B1414.
	GTZC_VCTR44_B1414 = 0x40
	// Position of B1415 field.
	GTZC_VCTR44_B1415_Pos = 0x7
	// Bit mask of B1415 field.
	GTZC_VCTR44_B1415_Msk = 0x80
	// Bit B1415.
	GTZC_VCTR44_B1415 = 0x80
	// Position of B1416 field.
	GTZC_VCTR44_B1416_Pos = 0x8
	// Bit mask of B1416 field.
	GTZC_VCTR44_B1416_Msk = 0x100
	// Bit B1416.
	GTZC_VCTR44_B1416 = 0x100
	// Position of B1417 field.
	GTZC_VCTR44_B1417_Pos = 0x9
	// Bit mask of B1417 field.
	GTZC_VCTR44_B1417_Msk = 0x200
	// Bit B1417.
	GTZC_VCTR44_B1417 = 0x200
	// Position of B1418 field.
	GTZC_VCTR44_B1418_Pos = 0xa
	// Bit mask of B1418 field.
	GTZC_VCTR44_B1418_Msk = 0x400
	// Bit B1418.
	GTZC_VCTR44_B1418 = 0x400
	// Position of B1419 field.
	GTZC_VCTR44_B1419_Pos = 0xb
	// Bit mask of B1419 field.
	GTZC_VCTR44_B1419_Msk = 0x800
	// Bit B1419.
	GTZC_VCTR44_B1419 = 0x800
	// Position of B1420 field.
	GTZC_VCTR44_B1420_Pos = 0xc
	// Bit mask of B1420 field.
	GTZC_VCTR44_B1420_Msk = 0x1000
	// Bit B1420.
	GTZC_VCTR44_B1420 = 0x1000
	// Position of B1421 field.
	GTZC_VCTR44_B1421_Pos = 0xd
	// Bit mask of B1421 field.
	GTZC_VCTR44_B1421_Msk = 0x2000
	// Bit B1421.
	GTZC_VCTR44_B1421 = 0x2000
	// Position of B1422 field.
	GTZC_VCTR44_B1422_Pos = 0xe
	// Bit mask of B1422 field.
	GTZC_VCTR44_B1422_Msk = 0x4000
	// Bit B1422.
	GTZC_VCTR44_B1422 = 0x4000
	// Position of B1423 field.
	GTZC_VCTR44_B1423_Pos = 0xf
	// Bit mask of B1423 field.
	GTZC_VCTR44_B1423_Msk = 0x8000
	// Bit B1423.
	GTZC_VCTR44_B1423 = 0x8000
	// Position of B1424 field.
	GTZC_VCTR44_B1424_Pos = 0x10
	// Bit mask of B1424 field.
	GTZC_VCTR44_B1424_Msk = 0x10000
	// Bit B1424.
	GTZC_VCTR44_B1424 = 0x10000
	// Position of B1425 field.
	GTZC_VCTR44_B1425_Pos = 0x11
	// Bit mask of B1425 field.
	GTZC_VCTR44_B1425_Msk = 0x20000
	// Bit B1425.
	GTZC_VCTR44_B1425 = 0x20000
	// Position of B1426 field.
	GTZC_VCTR44_B1426_Pos = 0x12
	// Bit mask of B1426 field.
	GTZC_VCTR44_B1426_Msk = 0x40000
	// Bit B1426.
	GTZC_VCTR44_B1426 = 0x40000
	// Position of B1427 field.
	GTZC_VCTR44_B1427_Pos = 0x13
	// Bit mask of B1427 field.
	GTZC_VCTR44_B1427_Msk = 0x80000
	// Bit B1427.
	GTZC_VCTR44_B1427 = 0x80000
	// Position of B1428 field.
	GTZC_VCTR44_B1428_Pos = 0x14
	// Bit mask of B1428 field.
	GTZC_VCTR44_B1428_Msk = 0x100000
	// Bit B1428.
	GTZC_VCTR44_B1428 = 0x100000
	// Position of B1429 field.
	GTZC_VCTR44_B1429_Pos = 0x15
	// Bit mask of B1429 field.
	GTZC_VCTR44_B1429_Msk = 0x200000
	// Bit B1429.
	GTZC_VCTR44_B1429 = 0x200000
	// Position of B1430 field.
	GTZC_VCTR44_B1430_Pos = 0x16
	// Bit mask of B1430 field.
	GTZC_VCTR44_B1430_Msk = 0x400000
	// Bit B1430.
	GTZC_VCTR44_B1430 = 0x400000
	// Position of B1431 field.
	GTZC_VCTR44_B1431_Pos = 0x17
	// Bit mask of B1431 field.
	GTZC_VCTR44_B1431_Msk = 0x800000
	// Bit B1431.
	GTZC_VCTR44_B1431 = 0x800000
	// Position of B1432 field.
	GTZC_VCTR44_B1432_Pos = 0x18
	// Bit mask of B1432 field.
	GTZC_VCTR44_B1432_Msk = 0x1000000
	// Bit B1432.
	GTZC_VCTR44_B1432 = 0x1000000
	// Position of B1433 field.
	GTZC_VCTR44_B1433_Pos = 0x19
	// Bit mask of B1433 field.
	GTZC_VCTR44_B1433_Msk = 0x2000000
	// Bit B1433.
	GTZC_VCTR44_B1433 = 0x2000000
	// Position of B1434 field.
	GTZC_VCTR44_B1434_Pos = 0x1a
	// Bit mask of B1434 field.
	GTZC_VCTR44_B1434_Msk = 0x4000000
	// Bit B1434.
	GTZC_VCTR44_B1434 = 0x4000000
	// Position of B1435 field.
	GTZC_VCTR44_B1435_Pos = 0x1b
	// Bit mask of B1435 field.
	GTZC_VCTR44_B1435_Msk = 0x8000000
	// Bit B1435.
	GTZC_VCTR44_B1435 = 0x8000000
	// Position of B1436 field.
	GTZC_VCTR44_B1436_Pos = 0x1c
	// Bit mask of B1436 field.
	GTZC_VCTR44_B1436_Msk = 0x10000000
	// Bit B1436.
	GTZC_VCTR44_B1436 = 0x10000000
	// Position of B1437 field.
	GTZC_VCTR44_B1437_Pos = 0x1d
	// Bit mask of B1437 field.
	GTZC_VCTR44_B1437_Msk = 0x20000000
	// Bit B1437.
	GTZC_VCTR44_B1437 = 0x20000000
	// Position of B1438 field.
	GTZC_VCTR44_B1438_Pos = 0x1e
	// Bit mask of B1438 field.
	GTZC_VCTR44_B1438_Msk = 0x40000000
	// Bit B1438.
	GTZC_VCTR44_B1438 = 0x40000000
	// Position of B1439 field.
	GTZC_VCTR44_B1439_Pos = 0x1f
	// Bit mask of B1439 field.
	GTZC_VCTR44_B1439_Msk = 0x80000000
	// Bit B1439.
	GTZC_VCTR44_B1439 = 0x80000000

	// VCTR45: MPCBBx vector register
	// Position of B1440 field.
	GTZC_VCTR45_B1440_Pos = 0x0
	// Bit mask of B1440 field.
	GTZC_VCTR45_B1440_Msk = 0x1
	// Bit B1440.
	GTZC_VCTR45_B1440 = 0x1
	// Position of B1441 field.
	GTZC_VCTR45_B1441_Pos = 0x1
	// Bit mask of B1441 field.
	GTZC_VCTR45_B1441_Msk = 0x2
	// Bit B1441.
	GTZC_VCTR45_B1441 = 0x2
	// Position of B1442 field.
	GTZC_VCTR45_B1442_Pos = 0x2
	// Bit mask of B1442 field.
	GTZC_VCTR45_B1442_Msk = 0x4
	// Bit B1442.
	GTZC_VCTR45_B1442 = 0x4
	// Position of B1443 field.
	GTZC_VCTR45_B1443_Pos = 0x3
	// Bit mask of B1443 field.
	GTZC_VCTR45_B1443_Msk = 0x8
	// Bit B1443.
	GTZC_VCTR45_B1443 = 0x8
	// Position of B1444 field.
	GTZC_VCTR45_B1444_Pos = 0x4
	// Bit mask of B1444 field.
	GTZC_VCTR45_B1444_Msk = 0x10
	// Bit B1444.
	GTZC_VCTR45_B1444 = 0x10
	// Position of B1445 field.
	GTZC_VCTR45_B1445_Pos = 0x5
	// Bit mask of B1445 field.
	GTZC_VCTR45_B1445_Msk = 0x20
	// Bit B1445.
	GTZC_VCTR45_B1445 = 0x20
	// Position of B1446 field.
	GTZC_VCTR45_B1446_Pos = 0x6
	// Bit mask of B1446 field.
	GTZC_VCTR45_B1446_Msk = 0x40
	// Bit B1446.
	GTZC_VCTR45_B1446 = 0x40
	// Position of B1447 field.
	GTZC_VCTR45_B1447_Pos = 0x7
	// Bit mask of B1447 field.
	GTZC_VCTR45_B1447_Msk = 0x80
	// Bit B1447.
	GTZC_VCTR45_B1447 = 0x80
	// Position of B1448 field.
	GTZC_VCTR45_B1448_Pos = 0x8
	// Bit mask of B1448 field.
	GTZC_VCTR45_B1448_Msk = 0x100
	// Bit B1448.
	GTZC_VCTR45_B1448 = 0x100
	// Position of B1449 field.
	GTZC_VCTR45_B1449_Pos = 0x9
	// Bit mask of B1449 field.
	GTZC_VCTR45_B1449_Msk = 0x200
	// Bit B1449.
	GTZC_VCTR45_B1449 = 0x200
	// Position of B1450 field.
	GTZC_VCTR45_B1450_Pos = 0xa
	// Bit mask of B1450 field.
	GTZC_VCTR45_B1450_Msk = 0x400
	// Bit B1450.
	GTZC_VCTR45_B1450 = 0x400
	// Position of B1451 field.
	GTZC_VCTR45_B1451_Pos = 0xb
	// Bit mask of B1451 field.
	GTZC_VCTR45_B1451_Msk = 0x800
	// Bit B1451.
	GTZC_VCTR45_B1451 = 0x800
	// Position of B1452 field.
	GTZC_VCTR45_B1452_Pos = 0xc
	// Bit mask of B1452 field.
	GTZC_VCTR45_B1452_Msk = 0x1000
	// Bit B1452.
	GTZC_VCTR45_B1452 = 0x1000
	// Position of B1453 field.
	GTZC_VCTR45_B1453_Pos = 0xd
	// Bit mask of B1453 field.
	GTZC_VCTR45_B1453_Msk = 0x2000
	// Bit B1453.
	GTZC_VCTR45_B1453 = 0x2000
	// Position of B1454 field.
	GTZC_VCTR45_B1454_Pos = 0xe
	// Bit mask of B1454 field.
	GTZC_VCTR45_B1454_Msk = 0x4000
	// Bit B1454.
	GTZC_VCTR45_B1454 = 0x4000
	// Position of B1455 field.
	GTZC_VCTR45_B1455_Pos = 0xf
	// Bit mask of B1455 field.
	GTZC_VCTR45_B1455_Msk = 0x8000
	// Bit B1455.
	GTZC_VCTR45_B1455 = 0x8000
	// Position of B1456 field.
	GTZC_VCTR45_B1456_Pos = 0x10
	// Bit mask of B1456 field.
	GTZC_VCTR45_B1456_Msk = 0x10000
	// Bit B1456.
	GTZC_VCTR45_B1456 = 0x10000
	// Position of B1457 field.
	GTZC_VCTR45_B1457_Pos = 0x11
	// Bit mask of B1457 field.
	GTZC_VCTR45_B1457_Msk = 0x20000
	// Bit B1457.
	GTZC_VCTR45_B1457 = 0x20000
	// Position of B1458 field.
	GTZC_VCTR45_B1458_Pos = 0x12
	// Bit mask of B1458 field.
	GTZC_VCTR45_B1458_Msk = 0x40000
	// Bit B1458.
	GTZC_VCTR45_B1458 = 0x40000
	// Position of B1459 field.
	GTZC_VCTR45_B1459_Pos = 0x13
	// Bit mask of B1459 field.
	GTZC_VCTR45_B1459_Msk = 0x80000
	// Bit B1459.
	GTZC_VCTR45_B1459 = 0x80000
	// Position of B1460 field.
	GTZC_VCTR45_B1460_Pos = 0x14
	// Bit mask of B1460 field.
	GTZC_VCTR45_B1460_Msk = 0x100000
	// Bit B1460.
	GTZC_VCTR45_B1460 = 0x100000
	// Position of B1461 field.
	GTZC_VCTR45_B1461_Pos = 0x15
	// Bit mask of B1461 field.
	GTZC_VCTR45_B1461_Msk = 0x200000
	// Bit B1461.
	GTZC_VCTR45_B1461 = 0x200000
	// Position of B1462 field.
	GTZC_VCTR45_B1462_Pos = 0x16
	// Bit mask of B1462 field.
	GTZC_VCTR45_B1462_Msk = 0x400000
	// Bit B1462.
	GTZC_VCTR45_B1462 = 0x400000
	// Position of B1463 field.
	GTZC_VCTR45_B1463_Pos = 0x17
	// Bit mask of B1463 field.
	GTZC_VCTR45_B1463_Msk = 0x800000
	// Bit B1463.
	GTZC_VCTR45_B1463 = 0x800000
	// Position of B1464 field.
	GTZC_VCTR45_B1464_Pos = 0x18
	// Bit mask of B1464 field.
	GTZC_VCTR45_B1464_Msk = 0x1000000
	// Bit B1464.
	GTZC_VCTR45_B1464 = 0x1000000
	// Position of B1465 field.
	GTZC_VCTR45_B1465_Pos = 0x19
	// Bit mask of B1465 field.
	GTZC_VCTR45_B1465_Msk = 0x2000000
	// Bit B1465.
	GTZC_VCTR45_B1465 = 0x2000000
	// Position of B1466 field.
	GTZC_VCTR45_B1466_Pos = 0x1a
	// Bit mask of B1466 field.
	GTZC_VCTR45_B1466_Msk = 0x4000000
	// Bit B1466.
	GTZC_VCTR45_B1466 = 0x4000000
	// Position of B1467 field.
	GTZC_VCTR45_B1467_Pos = 0x1b
	// Bit mask of B1467 field.
	GTZC_VCTR45_B1467_Msk = 0x8000000
	// Bit B1467.
	GTZC_VCTR45_B1467 = 0x8000000
	// Position of B1468 field.
	GTZC_VCTR45_B1468_Pos = 0x1c
	// Bit mask of B1468 field.
	GTZC_VCTR45_B1468_Msk = 0x10000000
	// Bit B1468.
	GTZC_VCTR45_B1468 = 0x10000000
	// Position of B1469 field.
	GTZC_VCTR45_B1469_Pos = 0x1d
	// Bit mask of B1469 field.
	GTZC_VCTR45_B1469_Msk = 0x20000000
	// Bit B1469.
	GTZC_VCTR45_B1469 = 0x20000000
	// Position of B1470 field.
	GTZC_VCTR45_B1470_Pos = 0x1e
	// Bit mask of B1470 field.
	GTZC_VCTR45_B1470_Msk = 0x40000000
	// Bit B1470.
	GTZC_VCTR45_B1470 = 0x40000000
	// Position of B1471 field.
	GTZC_VCTR45_B1471_Pos = 0x1f
	// Bit mask of B1471 field.
	GTZC_VCTR45_B1471_Msk = 0x80000000
	// Bit B1471.
	GTZC_VCTR45_B1471 = 0x80000000

	// VCTR46: MPCBBx vector register
	// Position of B1472 field.
	GTZC_VCTR46_B1472_Pos = 0x0
	// Bit mask of B1472 field.
	GTZC_VCTR46_B1472_Msk = 0x1
	// Bit B1472.
	GTZC_VCTR46_B1472 = 0x1
	// Position of B1473 field.
	GTZC_VCTR46_B1473_Pos = 0x1
	// Bit mask of B1473 field.
	GTZC_VCTR46_B1473_Msk = 0x2
	// Bit B1473.
	GTZC_VCTR46_B1473 = 0x2
	// Position of B1474 field.
	GTZC_VCTR46_B1474_Pos = 0x2
	// Bit mask of B1474 field.
	GTZC_VCTR46_B1474_Msk = 0x4
	// Bit B1474.
	GTZC_VCTR46_B1474 = 0x4
	// Position of B1475 field.
	GTZC_VCTR46_B1475_Pos = 0x3
	// Bit mask of B1475 field.
	GTZC_VCTR46_B1475_Msk = 0x8
	// Bit B1475.
	GTZC_VCTR46_B1475 = 0x8
	// Position of B1476 field.
	GTZC_VCTR46_B1476_Pos = 0x4
	// Bit mask of B1476 field.
	GTZC_VCTR46_B1476_Msk = 0x10
	// Bit B1476.
	GTZC_VCTR46_B1476 = 0x10
	// Position of B1477 field.
	GTZC_VCTR46_B1477_Pos = 0x5
	// Bit mask of B1477 field.
	GTZC_VCTR46_B1477_Msk = 0x20
	// Bit B1477.
	GTZC_VCTR46_B1477 = 0x20
	// Position of B1478 field.
	GTZC_VCTR46_B1478_Pos = 0x6
	// Bit mask of B1478 field.
	GTZC_VCTR46_B1478_Msk = 0x40
	// Bit B1478.
	GTZC_VCTR46_B1478 = 0x40
	// Position of B1479 field.
	GTZC_VCTR46_B1479_Pos = 0x7
	// Bit mask of B1479 field.
	GTZC_VCTR46_B1479_Msk = 0x80
	// Bit B1479.
	GTZC_VCTR46_B1479 = 0x80
	// Position of B1480 field.
	GTZC_VCTR46_B1480_Pos = 0x8
	// Bit mask of B1480 field.
	GTZC_VCTR46_B1480_Msk = 0x100
	// Bit B1480.
	GTZC_VCTR46_B1480 = 0x100
	// Position of B1481 field.
	GTZC_VCTR46_B1481_Pos = 0x9
	// Bit mask of B1481 field.
	GTZC_VCTR46_B1481_Msk = 0x200
	// Bit B1481.
	GTZC_VCTR46_B1481 = 0x200
	// Position of B1482 field.
	GTZC_VCTR46_B1482_Pos = 0xa
	// Bit mask of B1482 field.
	GTZC_VCTR46_B1482_Msk = 0x400
	// Bit B1482.
	GTZC_VCTR46_B1482 = 0x400
	// Position of B1483 field.
	GTZC_VCTR46_B1483_Pos = 0xb
	// Bit mask of B1483 field.
	GTZC_VCTR46_B1483_Msk = 0x800
	// Bit B1483.
	GTZC_VCTR46_B1483 = 0x800
	// Position of B1484 field.
	GTZC_VCTR46_B1484_Pos = 0xc
	// Bit mask of B1484 field.
	GTZC_VCTR46_B1484_Msk = 0x1000
	// Bit B1484.
	GTZC_VCTR46_B1484 = 0x1000
	// Position of B1485 field.
	GTZC_VCTR46_B1485_Pos = 0xd
	// Bit mask of B1485 field.
	GTZC_VCTR46_B1485_Msk = 0x2000
	// Bit B1485.
	GTZC_VCTR46_B1485 = 0x2000
	// Position of B1486 field.
	GTZC_VCTR46_B1486_Pos = 0xe
	// Bit mask of B1486 field.
	GTZC_VCTR46_B1486_Msk = 0x4000
	// Bit B1486.
	GTZC_VCTR46_B1486 = 0x4000
	// Position of B1487 field.
	GTZC_VCTR46_B1487_Pos = 0xf
	// Bit mask of B1487 field.
	GTZC_VCTR46_B1487_Msk = 0x8000
	// Bit B1487.
	GTZC_VCTR46_B1487 = 0x8000
	// Position of B1488 field.
	GTZC_VCTR46_B1488_Pos = 0x10
	// Bit mask of B1488 field.
	GTZC_VCTR46_B1488_Msk = 0x10000
	// Bit B1488.
	GTZC_VCTR46_B1488 = 0x10000
	// Position of B1489 field.
	GTZC_VCTR46_B1489_Pos = 0x11
	// Bit mask of B1489 field.
	GTZC_VCTR46_B1489_Msk = 0x20000
	// Bit B1489.
	GTZC_VCTR46_B1489 = 0x20000
	// Position of B1490 field.
	GTZC_VCTR46_B1490_Pos = 0x12
	// Bit mask of B1490 field.
	GTZC_VCTR46_B1490_Msk = 0x40000
	// Bit B1490.
	GTZC_VCTR46_B1490 = 0x40000
	// Position of B1491 field.
	GTZC_VCTR46_B1491_Pos = 0x13
	// Bit mask of B1491 field.
	GTZC_VCTR46_B1491_Msk = 0x80000
	// Bit B1491.
	GTZC_VCTR46_B1491 = 0x80000
	// Position of B1492 field.
	GTZC_VCTR46_B1492_Pos = 0x14
	// Bit mask of B1492 field.
	GTZC_VCTR46_B1492_Msk = 0x100000
	// Bit B1492.
	GTZC_VCTR46_B1492 = 0x100000
	// Position of B1493 field.
	GTZC_VCTR46_B1493_Pos = 0x15
	// Bit mask of B1493 field.
	GTZC_VCTR46_B1493_Msk = 0x200000
	// Bit B1493.
	GTZC_VCTR46_B1493 = 0x200000
	// Position of B1494 field.
	GTZC_VCTR46_B1494_Pos = 0x16
	// Bit mask of B1494 field.
	GTZC_VCTR46_B1494_Msk = 0x400000
	// Bit B1494.
	GTZC_VCTR46_B1494 = 0x400000
	// Position of B1495 field.
	GTZC_VCTR46_B1495_Pos = 0x17
	// Bit mask of B1495 field.
	GTZC_VCTR46_B1495_Msk = 0x800000
	// Bit B1495.
	GTZC_VCTR46_B1495 = 0x800000
	// Position of B1496 field.
	GTZC_VCTR46_B1496_Pos = 0x18
	// Bit mask of B1496 field.
	GTZC_VCTR46_B1496_Msk = 0x1000000
	// Bit B1496.
	GTZC_VCTR46_B1496 = 0x1000000
	// Position of B1497 field.
	GTZC_VCTR46_B1497_Pos = 0x19
	// Bit mask of B1497 field.
	GTZC_VCTR46_B1497_Msk = 0x2000000
	// Bit B1497.
	GTZC_VCTR46_B1497 = 0x2000000
	// Position of B1498 field.
	GTZC_VCTR46_B1498_Pos = 0x1a
	// Bit mask of B1498 field.
	GTZC_VCTR46_B1498_Msk = 0x4000000
	// Bit B1498.
	GTZC_VCTR46_B1498 = 0x4000000
	// Position of B1499 field.
	GTZC_VCTR46_B1499_Pos = 0x1b
	// Bit mask of B1499 field.
	GTZC_VCTR46_B1499_Msk = 0x8000000
	// Bit B1499.
	GTZC_VCTR46_B1499 = 0x8000000
	// Position of B1500 field.
	GTZC_VCTR46_B1500_Pos = 0x1c
	// Bit mask of B1500 field.
	GTZC_VCTR46_B1500_Msk = 0x10000000
	// Bit B1500.
	GTZC_VCTR46_B1500 = 0x10000000
	// Position of B1501 field.
	GTZC_VCTR46_B1501_Pos = 0x1d
	// Bit mask of B1501 field.
	GTZC_VCTR46_B1501_Msk = 0x20000000
	// Bit B1501.
	GTZC_VCTR46_B1501 = 0x20000000
	// Position of B1502 field.
	GTZC_VCTR46_B1502_Pos = 0x1e
	// Bit mask of B1502 field.
	GTZC_VCTR46_B1502_Msk = 0x40000000
	// Bit B1502.
	GTZC_VCTR46_B1502 = 0x40000000
	// Position of B1503 field.
	GTZC_VCTR46_B1503_Pos = 0x1f
	// Bit mask of B1503 field.
	GTZC_VCTR46_B1503_Msk = 0x80000000
	// Bit B1503.
	GTZC_VCTR46_B1503 = 0x80000000

	// VCTR47: MPCBBx vector register
	// Position of B1504 field.
	GTZC_VCTR47_B1504_Pos = 0x0
	// Bit mask of B1504 field.
	GTZC_VCTR47_B1504_Msk = 0x1
	// Bit B1504.
	GTZC_VCTR47_B1504 = 0x1
	// Position of B1505 field.
	GTZC_VCTR47_B1505_Pos = 0x1
	// Bit mask of B1505 field.
	GTZC_VCTR47_B1505_Msk = 0x2
	// Bit B1505.
	GTZC_VCTR47_B1505 = 0x2
	// Position of B1506 field.
	GTZC_VCTR47_B1506_Pos = 0x2
	// Bit mask of B1506 field.
	GTZC_VCTR47_B1506_Msk = 0x4
	// Bit B1506.
	GTZC_VCTR47_B1506 = 0x4
	// Position of B1507 field.
	GTZC_VCTR47_B1507_Pos = 0x3
	// Bit mask of B1507 field.
	GTZC_VCTR47_B1507_Msk = 0x8
	// Bit B1507.
	GTZC_VCTR47_B1507 = 0x8
	// Position of B1508 field.
	GTZC_VCTR47_B1508_Pos = 0x4
	// Bit mask of B1508 field.
	GTZC_VCTR47_B1508_Msk = 0x10
	// Bit B1508.
	GTZC_VCTR47_B1508 = 0x10
	// Position of B1509 field.
	GTZC_VCTR47_B1509_Pos = 0x5
	// Bit mask of B1509 field.
	GTZC_VCTR47_B1509_Msk = 0x20
	// Bit B1509.
	GTZC_VCTR47_B1509 = 0x20
	// Position of B1510 field.
	GTZC_VCTR47_B1510_Pos = 0x6
	// Bit mask of B1510 field.
	GTZC_VCTR47_B1510_Msk = 0x40
	// Bit B1510.
	GTZC_VCTR47_B1510 = 0x40
	// Position of B1511 field.
	GTZC_VCTR47_B1511_Pos = 0x7
	// Bit mask of B1511 field.
	GTZC_VCTR47_B1511_Msk = 0x80
	// Bit B1511.
	GTZC_VCTR47_B1511 = 0x80
	// Position of B1512 field.
	GTZC_VCTR47_B1512_Pos = 0x8
	// Bit mask of B1512 field.
	GTZC_VCTR47_B1512_Msk = 0x100
	// Bit B1512.
	GTZC_VCTR47_B1512 = 0x100
	// Position of B1513 field.
	GTZC_VCTR47_B1513_Pos = 0x9
	// Bit mask of B1513 field.
	GTZC_VCTR47_B1513_Msk = 0x200
	// Bit B1513.
	GTZC_VCTR47_B1513 = 0x200
	// Position of B1514 field.
	GTZC_VCTR47_B1514_Pos = 0xa
	// Bit mask of B1514 field.
	GTZC_VCTR47_B1514_Msk = 0x400
	// Bit B1514.
	GTZC_VCTR47_B1514 = 0x400
	// Position of B1515 field.
	GTZC_VCTR47_B1515_Pos = 0xb
	// Bit mask of B1515 field.
	GTZC_VCTR47_B1515_Msk = 0x800
	// Bit B1515.
	GTZC_VCTR47_B1515 = 0x800
	// Position of B1516 field.
	GTZC_VCTR47_B1516_Pos = 0xc
	// Bit mask of B1516 field.
	GTZC_VCTR47_B1516_Msk = 0x1000
	// Bit B1516.
	GTZC_VCTR47_B1516 = 0x1000
	// Position of B1517 field.
	GTZC_VCTR47_B1517_Pos = 0xd
	// Bit mask of B1517 field.
	GTZC_VCTR47_B1517_Msk = 0x2000
	// Bit B1517.
	GTZC_VCTR47_B1517 = 0x2000
	// Position of B1518 field.
	GTZC_VCTR47_B1518_Pos = 0xe
	// Bit mask of B1518 field.
	GTZC_VCTR47_B1518_Msk = 0x4000
	// Bit B1518.
	GTZC_VCTR47_B1518 = 0x4000
	// Position of B1519 field.
	GTZC_VCTR47_B1519_Pos = 0xf
	// Bit mask of B1519 field.
	GTZC_VCTR47_B1519_Msk = 0x8000
	// Bit B1519.
	GTZC_VCTR47_B1519 = 0x8000
	// Position of B1520 field.
	GTZC_VCTR47_B1520_Pos = 0x10
	// Bit mask of B1520 field.
	GTZC_VCTR47_B1520_Msk = 0x10000
	// Bit B1520.
	GTZC_VCTR47_B1520 = 0x10000
	// Position of B1521 field.
	GTZC_VCTR47_B1521_Pos = 0x11
	// Bit mask of B1521 field.
	GTZC_VCTR47_B1521_Msk = 0x20000
	// Bit B1521.
	GTZC_VCTR47_B1521 = 0x20000
	// Position of B1522 field.
	GTZC_VCTR47_B1522_Pos = 0x12
	// Bit mask of B1522 field.
	GTZC_VCTR47_B1522_Msk = 0x40000
	// Bit B1522.
	GTZC_VCTR47_B1522 = 0x40000
	// Position of B1523 field.
	GTZC_VCTR47_B1523_Pos = 0x13
	// Bit mask of B1523 field.
	GTZC_VCTR47_B1523_Msk = 0x80000
	// Bit B1523.
	GTZC_VCTR47_B1523 = 0x80000
	// Position of B1524 field.
	GTZC_VCTR47_B1524_Pos = 0x14
	// Bit mask of B1524 field.
	GTZC_VCTR47_B1524_Msk = 0x100000
	// Bit B1524.
	GTZC_VCTR47_B1524 = 0x100000
	// Position of B1525 field.
	GTZC_VCTR47_B1525_Pos = 0x15
	// Bit mask of B1525 field.
	GTZC_VCTR47_B1525_Msk = 0x200000
	// Bit B1525.
	GTZC_VCTR47_B1525 = 0x200000
	// Position of B1526 field.
	GTZC_VCTR47_B1526_Pos = 0x16
	// Bit mask of B1526 field.
	GTZC_VCTR47_B1526_Msk = 0x400000
	// Bit B1526.
	GTZC_VCTR47_B1526 = 0x400000
	// Position of B1527 field.
	GTZC_VCTR47_B1527_Pos = 0x17
	// Bit mask of B1527 field.
	GTZC_VCTR47_B1527_Msk = 0x800000
	// Bit B1527.
	GTZC_VCTR47_B1527 = 0x800000
	// Position of B1528 field.
	GTZC_VCTR47_B1528_Pos = 0x18
	// Bit mask of B1528 field.
	GTZC_VCTR47_B1528_Msk = 0x1000000
	// Bit B1528.
	GTZC_VCTR47_B1528 = 0x1000000
	// Position of B1529 field.
	GTZC_VCTR47_B1529_Pos = 0x19
	// Bit mask of B1529 field.
	GTZC_VCTR47_B1529_Msk = 0x2000000
	// Bit B1529.
	GTZC_VCTR47_B1529 = 0x2000000
	// Position of B1530 field.
	GTZC_VCTR47_B1530_Pos = 0x1a
	// Bit mask of B1530 field.
	GTZC_VCTR47_B1530_Msk = 0x4000000
	// Bit B1530.
	GTZC_VCTR47_B1530 = 0x4000000
	// Position of B1531 field.
	GTZC_VCTR47_B1531_Pos = 0x1b
	// Bit mask of B1531 field.
	GTZC_VCTR47_B1531_Msk = 0x8000000
	// Bit B1531.
	GTZC_VCTR47_B1531 = 0x8000000
	// Position of B1532 field.
	GTZC_VCTR47_B1532_Pos = 0x1c
	// Bit mask of B1532 field.
	GTZC_VCTR47_B1532_Msk = 0x10000000
	// Bit B1532.
	GTZC_VCTR47_B1532 = 0x10000000
	// Position of B1533 field.
	GTZC_VCTR47_B1533_Pos = 0x1d
	// Bit mask of B1533 field.
	GTZC_VCTR47_B1533_Msk = 0x20000000
	// Bit B1533.
	GTZC_VCTR47_B1533 = 0x20000000
	// Position of B1534 field.
	GTZC_VCTR47_B1534_Pos = 0x1e
	// Bit mask of B1534 field.
	GTZC_VCTR47_B1534_Msk = 0x40000000
	// Bit B1534.
	GTZC_VCTR47_B1534 = 0x40000000
	// Position of B1535 field.
	GTZC_VCTR47_B1535_Pos = 0x1f
	// Bit mask of B1535 field.
	GTZC_VCTR47_B1535_Msk = 0x80000000
	// Bit B1535.
	GTZC_VCTR47_B1535 = 0x80000000

	// VCTR48: MPCBBx vector register
	// Position of B1536 field.
	GTZC_VCTR48_B1536_Pos = 0x0
	// Bit mask of B1536 field.
	GTZC_VCTR48_B1536_Msk = 0x1
	// Bit B1536.
	GTZC_VCTR48_B1536 = 0x1
	// Position of B1537 field.
	GTZC_VCTR48_B1537_Pos = 0x1
	// Bit mask of B1537 field.
	GTZC_VCTR48_B1537_Msk = 0x2
	// Bit B1537.
	GTZC_VCTR48_B1537 = 0x2
	// Position of B1538 field.
	GTZC_VCTR48_B1538_Pos = 0x2
	// Bit mask of B1538 field.
	GTZC_VCTR48_B1538_Msk = 0x4
	// Bit B1538.
	GTZC_VCTR48_B1538 = 0x4
	// Position of B1539 field.
	GTZC_VCTR48_B1539_Pos = 0x3
	// Bit mask of B1539 field.
	GTZC_VCTR48_B1539_Msk = 0x8
	// Bit B1539.
	GTZC_VCTR48_B1539 = 0x8
	// Position of B1540 field.
	GTZC_VCTR48_B1540_Pos = 0x4
	// Bit mask of B1540 field.
	GTZC_VCTR48_B1540_Msk = 0x10
	// Bit B1540.
	GTZC_VCTR48_B1540 = 0x10
	// Position of B1541 field.
	GTZC_VCTR48_B1541_Pos = 0x5
	// Bit mask of B1541 field.
	GTZC_VCTR48_B1541_Msk = 0x20
	// Bit B1541.
	GTZC_VCTR48_B1541 = 0x20
	// Position of B1542 field.
	GTZC_VCTR48_B1542_Pos = 0x6
	// Bit mask of B1542 field.
	GTZC_VCTR48_B1542_Msk = 0x40
	// Bit B1542.
	GTZC_VCTR48_B1542 = 0x40
	// Position of B1543 field.
	GTZC_VCTR48_B1543_Pos = 0x7
	// Bit mask of B1543 field.
	GTZC_VCTR48_B1543_Msk = 0x80
	// Bit B1543.
	GTZC_VCTR48_B1543 = 0x80
	// Position of B1544 field.
	GTZC_VCTR48_B1544_Pos = 0x8
	// Bit mask of B1544 field.
	GTZC_VCTR48_B1544_Msk = 0x100
	// Bit B1544.
	GTZC_VCTR48_B1544 = 0x100
	// Position of B1545 field.
	GTZC_VCTR48_B1545_Pos = 0x9
	// Bit mask of B1545 field.
	GTZC_VCTR48_B1545_Msk = 0x200
	// Bit B1545.
	GTZC_VCTR48_B1545 = 0x200
	// Position of B1546 field.
	GTZC_VCTR48_B1546_Pos = 0xa
	// Bit mask of B1546 field.
	GTZC_VCTR48_B1546_Msk = 0x400
	// Bit B1546.
	GTZC_VCTR48_B1546 = 0x400
	// Position of B1547 field.
	GTZC_VCTR48_B1547_Pos = 0xb
	// Bit mask of B1547 field.
	GTZC_VCTR48_B1547_Msk = 0x800
	// Bit B1547.
	GTZC_VCTR48_B1547 = 0x800
	// Position of B1548 field.
	GTZC_VCTR48_B1548_Pos = 0xc
	// Bit mask of B1548 field.
	GTZC_VCTR48_B1548_Msk = 0x1000
	// Bit B1548.
	GTZC_VCTR48_B1548 = 0x1000
	// Position of B1549 field.
	GTZC_VCTR48_B1549_Pos = 0xd
	// Bit mask of B1549 field.
	GTZC_VCTR48_B1549_Msk = 0x2000
	// Bit B1549.
	GTZC_VCTR48_B1549 = 0x2000
	// Position of B1550 field.
	GTZC_VCTR48_B1550_Pos = 0xe
	// Bit mask of B1550 field.
	GTZC_VCTR48_B1550_Msk = 0x4000
	// Bit B1550.
	GTZC_VCTR48_B1550 = 0x4000
	// Position of B1551 field.
	GTZC_VCTR48_B1551_Pos = 0xf
	// Bit mask of B1551 field.
	GTZC_VCTR48_B1551_Msk = 0x8000
	// Bit B1551.
	GTZC_VCTR48_B1551 = 0x8000
	// Position of B1552 field.
	GTZC_VCTR48_B1552_Pos = 0x10
	// Bit mask of B1552 field.
	GTZC_VCTR48_B1552_Msk = 0x10000
	// Bit B1552.
	GTZC_VCTR48_B1552 = 0x10000
	// Position of B1553 field.
	GTZC_VCTR48_B1553_Pos = 0x11
	// Bit mask of B1553 field.
	GTZC_VCTR48_B1553_Msk = 0x20000
	// Bit B1553.
	GTZC_VCTR48_B1553 = 0x20000
	// Position of B1554 field.
	GTZC_VCTR48_B1554_Pos = 0x12
	// Bit mask of B1554 field.
	GTZC_VCTR48_B1554_Msk = 0x40000
	// Bit B1554.
	GTZC_VCTR48_B1554 = 0x40000
	// Position of B1555 field.
	GTZC_VCTR48_B1555_Pos = 0x13
	// Bit mask of B1555 field.
	GTZC_VCTR48_B1555_Msk = 0x80000
	// Bit B1555.
	GTZC_VCTR48_B1555 = 0x80000
	// Position of B1556 field.
	GTZC_VCTR48_B1556_Pos = 0x14
	// Bit mask of B1556 field.
	GTZC_VCTR48_B1556_Msk = 0x100000
	// Bit B1556.
	GTZC_VCTR48_B1556 = 0x100000
	// Position of B1557 field.
	GTZC_VCTR48_B1557_Pos = 0x15
	// Bit mask of B1557 field.
	GTZC_VCTR48_B1557_Msk = 0x200000
	// Bit B1557.
	GTZC_VCTR48_B1557 = 0x200000
	// Position of B1558 field.
	GTZC_VCTR48_B1558_Pos = 0x16
	// Bit mask of B1558 field.
	GTZC_VCTR48_B1558_Msk = 0x400000
	// Bit B1558.
	GTZC_VCTR48_B1558 = 0x400000
	// Position of B1559 field.
	GTZC_VCTR48_B1559_Pos = 0x17
	// Bit mask of B1559 field.
	GTZC_VCTR48_B1559_Msk = 0x800000
	// Bit B1559.
	GTZC_VCTR48_B1559 = 0x800000
	// Position of B1560 field.
	GTZC_VCTR48_B1560_Pos = 0x18
	// Bit mask of B1560 field.
	GTZC_VCTR48_B1560_Msk = 0x1000000
	// Bit B1560.
	GTZC_VCTR48_B1560 = 0x1000000
	// Position of B1561 field.
	GTZC_VCTR48_B1561_Pos = 0x19
	// Bit mask of B1561 field.
	GTZC_VCTR48_B1561_Msk = 0x2000000
	// Bit B1561.
	GTZC_VCTR48_B1561 = 0x2000000
	// Position of B1562 field.
	GTZC_VCTR48_B1562_Pos = 0x1a
	// Bit mask of B1562 field.
	GTZC_VCTR48_B1562_Msk = 0x4000000
	// Bit B1562.
	GTZC_VCTR48_B1562 = 0x4000000
	// Position of B1563 field.
	GTZC_VCTR48_B1563_Pos = 0x1b
	// Bit mask of B1563 field.
	GTZC_VCTR48_B1563_Msk = 0x8000000
	// Bit B1563.
	GTZC_VCTR48_B1563 = 0x8000000
	// Position of B1564 field.
	GTZC_VCTR48_B1564_Pos = 0x1c
	// Bit mask of B1564 field.
	GTZC_VCTR48_B1564_Msk = 0x10000000
	// Bit B1564.
	GTZC_VCTR48_B1564 = 0x10000000
	// Position of B1565 field.
	GTZC_VCTR48_B1565_Pos = 0x1d
	// Bit mask of B1565 field.
	GTZC_VCTR48_B1565_Msk = 0x20000000
	// Bit B1565.
	GTZC_VCTR48_B1565 = 0x20000000
	// Position of B1566 field.
	GTZC_VCTR48_B1566_Pos = 0x1e
	// Bit mask of B1566 field.
	GTZC_VCTR48_B1566_Msk = 0x40000000
	// Bit B1566.
	GTZC_VCTR48_B1566 = 0x40000000
	// Position of B1567 field.
	GTZC_VCTR48_B1567_Pos = 0x1f
	// Bit mask of B1567 field.
	GTZC_VCTR48_B1567_Msk = 0x80000000
	// Bit B1567.
	GTZC_VCTR48_B1567 = 0x80000000

	// VCTR49: MPCBBx vector register
	// Position of B1568 field.
	GTZC_VCTR49_B1568_Pos = 0x0
	// Bit mask of B1568 field.
	GTZC_VCTR49_B1568_Msk = 0x1
	// Bit B1568.
	GTZC_VCTR49_B1568 = 0x1
	// Position of B1569 field.
	GTZC_VCTR49_B1569_Pos = 0x1
	// Bit mask of B1569 field.
	GTZC_VCTR49_B1569_Msk = 0x2
	// Bit B1569.
	GTZC_VCTR49_B1569 = 0x2
	// Position of B1570 field.
	GTZC_VCTR49_B1570_Pos = 0x2
	// Bit mask of B1570 field.
	GTZC_VCTR49_B1570_Msk = 0x4
	// Bit B1570.
	GTZC_VCTR49_B1570 = 0x4
	// Position of B1571 field.
	GTZC_VCTR49_B1571_Pos = 0x3
	// Bit mask of B1571 field.
	GTZC_VCTR49_B1571_Msk = 0x8
	// Bit B1571.
	GTZC_VCTR49_B1571 = 0x8
	// Position of B1572 field.
	GTZC_VCTR49_B1572_Pos = 0x4
	// Bit mask of B1572 field.
	GTZC_VCTR49_B1572_Msk = 0x10
	// Bit B1572.
	GTZC_VCTR49_B1572 = 0x10
	// Position of B1573 field.
	GTZC_VCTR49_B1573_Pos = 0x5
	// Bit mask of B1573 field.
	GTZC_VCTR49_B1573_Msk = 0x20
	// Bit B1573.
	GTZC_VCTR49_B1573 = 0x20
	// Position of B1574 field.
	GTZC_VCTR49_B1574_Pos = 0x6
	// Bit mask of B1574 field.
	GTZC_VCTR49_B1574_Msk = 0x40
	// Bit B1574.
	GTZC_VCTR49_B1574 = 0x40
	// Position of B1575 field.
	GTZC_VCTR49_B1575_Pos = 0x7
	// Bit mask of B1575 field.
	GTZC_VCTR49_B1575_Msk = 0x80
	// Bit B1575.
	GTZC_VCTR49_B1575 = 0x80
	// Position of B1576 field.
	GTZC_VCTR49_B1576_Pos = 0x8
	// Bit mask of B1576 field.
	GTZC_VCTR49_B1576_Msk = 0x100
	// Bit B1576.
	GTZC_VCTR49_B1576 = 0x100
	// Position of B1577 field.
	GTZC_VCTR49_B1577_Pos = 0x9
	// Bit mask of B1577 field.
	GTZC_VCTR49_B1577_Msk = 0x200
	// Bit B1577.
	GTZC_VCTR49_B1577 = 0x200
	// Position of B1578 field.
	GTZC_VCTR49_B1578_Pos = 0xa
	// Bit mask of B1578 field.
	GTZC_VCTR49_B1578_Msk = 0x400
	// Bit B1578.
	GTZC_VCTR49_B1578 = 0x400
	// Position of B1579 field.
	GTZC_VCTR49_B1579_Pos = 0xb
	// Bit mask of B1579 field.
	GTZC_VCTR49_B1579_Msk = 0x800
	// Bit B1579.
	GTZC_VCTR49_B1579 = 0x800
	// Position of B1580 field.
	GTZC_VCTR49_B1580_Pos = 0xc
	// Bit mask of B1580 field.
	GTZC_VCTR49_B1580_Msk = 0x1000
	// Bit B1580.
	GTZC_VCTR49_B1580 = 0x1000
	// Position of B1581 field.
	GTZC_VCTR49_B1581_Pos = 0xd
	// Bit mask of B1581 field.
	GTZC_VCTR49_B1581_Msk = 0x2000
	// Bit B1581.
	GTZC_VCTR49_B1581 = 0x2000
	// Position of B1582 field.
	GTZC_VCTR49_B1582_Pos = 0xe
	// Bit mask of B1582 field.
	GTZC_VCTR49_B1582_Msk = 0x4000
	// Bit B1582.
	GTZC_VCTR49_B1582 = 0x4000
	// Position of B1583 field.
	GTZC_VCTR49_B1583_Pos = 0xf
	// Bit mask of B1583 field.
	GTZC_VCTR49_B1583_Msk = 0x8000
	// Bit B1583.
	GTZC_VCTR49_B1583 = 0x8000
	// Position of B1584 field.
	GTZC_VCTR49_B1584_Pos = 0x10
	// Bit mask of B1584 field.
	GTZC_VCTR49_B1584_Msk = 0x10000
	// Bit B1584.
	GTZC_VCTR49_B1584 = 0x10000
	// Position of B1585 field.
	GTZC_VCTR49_B1585_Pos = 0x11
	// Bit mask of B1585 field.
	GTZC_VCTR49_B1585_Msk = 0x20000
	// Bit B1585.
	GTZC_VCTR49_B1585 = 0x20000
	// Position of B1586 field.
	GTZC_VCTR49_B1586_Pos = 0x12
	// Bit mask of B1586 field.
	GTZC_VCTR49_B1586_Msk = 0x40000
	// Bit B1586.
	GTZC_VCTR49_B1586 = 0x40000
	// Position of B1587 field.
	GTZC_VCTR49_B1587_Pos = 0x13
	// Bit mask of B1587 field.
	GTZC_VCTR49_B1587_Msk = 0x80000
	// Bit B1587.
	GTZC_VCTR49_B1587 = 0x80000
	// Position of B1588 field.
	GTZC_VCTR49_B1588_Pos = 0x14
	// Bit mask of B1588 field.
	GTZC_VCTR49_B1588_Msk = 0x100000
	// Bit B1588.
	GTZC_VCTR49_B1588 = 0x100000
	// Position of B1589 field.
	GTZC_VCTR49_B1589_Pos = 0x15
	// Bit mask of B1589 field.
	GTZC_VCTR49_B1589_Msk = 0x200000
	// Bit B1589.
	GTZC_VCTR49_B1589 = 0x200000
	// Position of B1590 field.
	GTZC_VCTR49_B1590_Pos = 0x16
	// Bit mask of B1590 field.
	GTZC_VCTR49_B1590_Msk = 0x400000
	// Bit B1590.
	GTZC_VCTR49_B1590 = 0x400000
	// Position of B1591 field.
	GTZC_VCTR49_B1591_Pos = 0x17
	// Bit mask of B1591 field.
	GTZC_VCTR49_B1591_Msk = 0x800000
	// Bit B1591.
	GTZC_VCTR49_B1591 = 0x800000
	// Position of B1592 field.
	GTZC_VCTR49_B1592_Pos = 0x18
	// Bit mask of B1592 field.
	GTZC_VCTR49_B1592_Msk = 0x1000000
	// Bit B1592.
	GTZC_VCTR49_B1592 = 0x1000000
	// Position of B1593 field.
	GTZC_VCTR49_B1593_Pos = 0x19
	// Bit mask of B1593 field.
	GTZC_VCTR49_B1593_Msk = 0x2000000
	// Bit B1593.
	GTZC_VCTR49_B1593 = 0x2000000
	// Position of B1594 field.
	GTZC_VCTR49_B1594_Pos = 0x1a
	// Bit mask of B1594 field.
	GTZC_VCTR49_B1594_Msk = 0x4000000
	// Bit B1594.
	GTZC_VCTR49_B1594 = 0x4000000
	// Position of B1595 field.
	GTZC_VCTR49_B1595_Pos = 0x1b
	// Bit mask of B1595 field.
	GTZC_VCTR49_B1595_Msk = 0x8000000
	// Bit B1595.
	GTZC_VCTR49_B1595 = 0x8000000
	// Position of B1596 field.
	GTZC_VCTR49_B1596_Pos = 0x1c
	// Bit mask of B1596 field.
	GTZC_VCTR49_B1596_Msk = 0x10000000
	// Bit B1596.
	GTZC_VCTR49_B1596 = 0x10000000
	// Position of B1597 field.
	GTZC_VCTR49_B1597_Pos = 0x1d
	// Bit mask of B1597 field.
	GTZC_VCTR49_B1597_Msk = 0x20000000
	// Bit B1597.
	GTZC_VCTR49_B1597 = 0x20000000
	// Position of B1598 field.
	GTZC_VCTR49_B1598_Pos = 0x1e
	// Bit mask of B1598 field.
	GTZC_VCTR49_B1598_Msk = 0x40000000
	// Bit B1598.
	GTZC_VCTR49_B1598 = 0x40000000
	// Position of B1599 field.
	GTZC_VCTR49_B1599_Pos = 0x1f
	// Bit mask of B1599 field.
	GTZC_VCTR49_B1599_Msk = 0x80000000
	// Bit B1599.
	GTZC_VCTR49_B1599 = 0x80000000

	// VCTR50: MPCBBx vector register
	// Position of B1600 field.
	GTZC_VCTR50_B1600_Pos = 0x0
	// Bit mask of B1600 field.
	GTZC_VCTR50_B1600_Msk = 0x1
	// Bit B1600.
	GTZC_VCTR50_B1600 = 0x1
	// Position of B1601 field.
	GTZC_VCTR50_B1601_Pos = 0x1
	// Bit mask of B1601 field.
	GTZC_VCTR50_B1601_Msk = 0x2
	// Bit B1601.
	GTZC_VCTR50_B1601 = 0x2
	// Position of B1602 field.
	GTZC_VCTR50_B1602_Pos = 0x2
	// Bit mask of B1602 field.
	GTZC_VCTR50_B1602_Msk = 0x4
	// Bit B1602.
	GTZC_VCTR50_B1602 = 0x4
	// Position of B1603 field.
	GTZC_VCTR50_B1603_Pos = 0x3
	// Bit mask of B1603 field.
	GTZC_VCTR50_B1603_Msk = 0x8
	// Bit B1603.
	GTZC_VCTR50_B1603 = 0x8
	// Position of B1604 field.
	GTZC_VCTR50_B1604_Pos = 0x4
	// Bit mask of B1604 field.
	GTZC_VCTR50_B1604_Msk = 0x10
	// Bit B1604.
	GTZC_VCTR50_B1604 = 0x10
	// Position of B1605 field.
	GTZC_VCTR50_B1605_Pos = 0x5
	// Bit mask of B1605 field.
	GTZC_VCTR50_B1605_Msk = 0x20
	// Bit B1605.
	GTZC_VCTR50_B1605 = 0x20
	// Position of B1606 field.
	GTZC_VCTR50_B1606_Pos = 0x6
	// Bit mask of B1606 field.
	GTZC_VCTR50_B1606_Msk = 0x40
	// Bit B1606.
	GTZC_VCTR50_B1606 = 0x40
	// Position of B1607 field.
	GTZC_VCTR50_B1607_Pos = 0x7
	// Bit mask of B1607 field.
	GTZC_VCTR50_B1607_Msk = 0x80
	// Bit B1607.
	GTZC_VCTR50_B1607 = 0x80
	// Position of B1608 field.
	GTZC_VCTR50_B1608_Pos = 0x8
	// Bit mask of B1608 field.
	GTZC_VCTR50_B1608_Msk = 0x100
	// Bit B1608.
	GTZC_VCTR50_B1608 = 0x100
	// Position of B1609 field.
	GTZC_VCTR50_B1609_Pos = 0x9
	// Bit mask of B1609 field.
	GTZC_VCTR50_B1609_Msk = 0x200
	// Bit B1609.
	GTZC_VCTR50_B1609 = 0x200
	// Position of B1610 field.
	GTZC_VCTR50_B1610_Pos = 0xa
	// Bit mask of B1610 field.
	GTZC_VCTR50_B1610_Msk = 0x400
	// Bit B1610.
	GTZC_VCTR50_B1610 = 0x400
	// Position of B1611 field.
	GTZC_VCTR50_B1611_Pos = 0xb
	// Bit mask of B1611 field.
	GTZC_VCTR50_B1611_Msk = 0x800
	// Bit B1611.
	GTZC_VCTR50_B1611 = 0x800
	// Position of B1612 field.
	GTZC_VCTR50_B1612_Pos = 0xc
	// Bit mask of B1612 field.
	GTZC_VCTR50_B1612_Msk = 0x1000
	// Bit B1612.
	GTZC_VCTR50_B1612 = 0x1000
	// Position of B1613 field.
	GTZC_VCTR50_B1613_Pos = 0xd
	// Bit mask of B1613 field.
	GTZC_VCTR50_B1613_Msk = 0x2000
	// Bit B1613.
	GTZC_VCTR50_B1613 = 0x2000
	// Position of B1614 field.
	GTZC_VCTR50_B1614_Pos = 0xe
	// Bit mask of B1614 field.
	GTZC_VCTR50_B1614_Msk = 0x4000
	// Bit B1614.
	GTZC_VCTR50_B1614 = 0x4000
	// Position of B1615 field.
	GTZC_VCTR50_B1615_Pos = 0xf
	// Bit mask of B1615 field.
	GTZC_VCTR50_B1615_Msk = 0x8000
	// Bit B1615.
	GTZC_VCTR50_B1615 = 0x8000
	// Position of B1616 field.
	GTZC_VCTR50_B1616_Pos = 0x10
	// Bit mask of B1616 field.
	GTZC_VCTR50_B1616_Msk = 0x10000
	// Bit B1616.
	GTZC_VCTR50_B1616 = 0x10000
	// Position of B1617 field.
	GTZC_VCTR50_B1617_Pos = 0x11
	// Bit mask of B1617 field.
	GTZC_VCTR50_B1617_Msk = 0x20000
	// Bit B1617.
	GTZC_VCTR50_B1617 = 0x20000
	// Position of B1618 field.
	GTZC_VCTR50_B1618_Pos = 0x12
	// Bit mask of B1618 field.
	GTZC_VCTR50_B1618_Msk = 0x40000
	// Bit B1618.
	GTZC_VCTR50_B1618 = 0x40000
	// Position of B1619 field.
	GTZC_VCTR50_B1619_Pos = 0x13
	// Bit mask of B1619 field.
	GTZC_VCTR50_B1619_Msk = 0x80000
	// Bit B1619.
	GTZC_VCTR50_B1619 = 0x80000
	// Position of B1620 field.
	GTZC_VCTR50_B1620_Pos = 0x14
	// Bit mask of B1620 field.
	GTZC_VCTR50_B1620_Msk = 0x100000
	// Bit B1620.
	GTZC_VCTR50_B1620 = 0x100000
	// Position of B1621 field.
	GTZC_VCTR50_B1621_Pos = 0x15
	// Bit mask of B1621 field.
	GTZC_VCTR50_B1621_Msk = 0x200000
	// Bit B1621.
	GTZC_VCTR50_B1621 = 0x200000
	// Position of B1622 field.
	GTZC_VCTR50_B1622_Pos = 0x16
	// Bit mask of B1622 field.
	GTZC_VCTR50_B1622_Msk = 0x400000
	// Bit B1622.
	GTZC_VCTR50_B1622 = 0x400000
	// Position of B1623 field.
	GTZC_VCTR50_B1623_Pos = 0x17
	// Bit mask of B1623 field.
	GTZC_VCTR50_B1623_Msk = 0x800000
	// Bit B1623.
	GTZC_VCTR50_B1623 = 0x800000
	// Position of B1624 field.
	GTZC_VCTR50_B1624_Pos = 0x18
	// Bit mask of B1624 field.
	GTZC_VCTR50_B1624_Msk = 0x1000000
	// Bit B1624.
	GTZC_VCTR50_B1624 = 0x1000000
	// Position of B1625 field.
	GTZC_VCTR50_B1625_Pos = 0x19
	// Bit mask of B1625 field.
	GTZC_VCTR50_B1625_Msk = 0x2000000
	// Bit B1625.
	GTZC_VCTR50_B1625 = 0x2000000
	// Position of B1626 field.
	GTZC_VCTR50_B1626_Pos = 0x1a
	// Bit mask of B1626 field.
	GTZC_VCTR50_B1626_Msk = 0x4000000
	// Bit B1626.
	GTZC_VCTR50_B1626 = 0x4000000
	// Position of B1627 field.
	GTZC_VCTR50_B1627_Pos = 0x1b
	// Bit mask of B1627 field.
	GTZC_VCTR50_B1627_Msk = 0x8000000
	// Bit B1627.
	GTZC_VCTR50_B1627 = 0x8000000
	// Position of B1628 field.
	GTZC_VCTR50_B1628_Pos = 0x1c
	// Bit mask of B1628 field.
	GTZC_VCTR50_B1628_Msk = 0x10000000
	// Bit B1628.
	GTZC_VCTR50_B1628 = 0x10000000
	// Position of B1629 field.
	GTZC_VCTR50_B1629_Pos = 0x1d
	// Bit mask of B1629 field.
	GTZC_VCTR50_B1629_Msk = 0x20000000
	// Bit B1629.
	GTZC_VCTR50_B1629 = 0x20000000
	// Position of B1630 field.
	GTZC_VCTR50_B1630_Pos = 0x1e
	// Bit mask of B1630 field.
	GTZC_VCTR50_B1630_Msk = 0x40000000
	// Bit B1630.
	GTZC_VCTR50_B1630 = 0x40000000
	// Position of B1631 field.
	GTZC_VCTR50_B1631_Pos = 0x1f
	// Bit mask of B1631 field.
	GTZC_VCTR50_B1631_Msk = 0x80000000
	// Bit B1631.
	GTZC_VCTR50_B1631 = 0x80000000

	// VCTR51: MPCBBx vector register
	// Position of B1632 field.
	GTZC_VCTR51_B1632_Pos = 0x0
	// Bit mask of B1632 field.
	GTZC_VCTR51_B1632_Msk = 0x1
	// Bit B1632.
	GTZC_VCTR51_B1632 = 0x1
	// Position of B1633 field.
	GTZC_VCTR51_B1633_Pos = 0x1
	// Bit mask of B1633 field.
	GTZC_VCTR51_B1633_Msk = 0x2
	// Bit B1633.
	GTZC_VCTR51_B1633 = 0x2
	// Position of B1634 field.
	GTZC_VCTR51_B1634_Pos = 0x2
	// Bit mask of B1634 field.
	GTZC_VCTR51_B1634_Msk = 0x4
	// Bit B1634.
	GTZC_VCTR51_B1634 = 0x4
	// Position of B1635 field.
	GTZC_VCTR51_B1635_Pos = 0x3
	// Bit mask of B1635 field.
	GTZC_VCTR51_B1635_Msk = 0x8
	// Bit B1635.
	GTZC_VCTR51_B1635 = 0x8
	// Position of B1636 field.
	GTZC_VCTR51_B1636_Pos = 0x4
	// Bit mask of B1636 field.
	GTZC_VCTR51_B1636_Msk = 0x10
	// Bit B1636.
	GTZC_VCTR51_B1636 = 0x10
	// Position of B1637 field.
	GTZC_VCTR51_B1637_Pos = 0x5
	// Bit mask of B1637 field.
	GTZC_VCTR51_B1637_Msk = 0x20
	// Bit B1637.
	GTZC_VCTR51_B1637 = 0x20
	// Position of B1638 field.
	GTZC_VCTR51_B1638_Pos = 0x6
	// Bit mask of B1638 field.
	GTZC_VCTR51_B1638_Msk = 0x40
	// Bit B1638.
	GTZC_VCTR51_B1638 = 0x40
	// Position of B1639 field.
	GTZC_VCTR51_B1639_Pos = 0x7
	// Bit mask of B1639 field.
	GTZC_VCTR51_B1639_Msk = 0x80
	// Bit B1639.
	GTZC_VCTR51_B1639 = 0x80
	// Position of B1640 field.
	GTZC_VCTR51_B1640_Pos = 0x8
	// Bit mask of B1640 field.
	GTZC_VCTR51_B1640_Msk = 0x100
	// Bit B1640.
	GTZC_VCTR51_B1640 = 0x100
	// Position of B1641 field.
	GTZC_VCTR51_B1641_Pos = 0x9
	// Bit mask of B1641 field.
	GTZC_VCTR51_B1641_Msk = 0x200
	// Bit B1641.
	GTZC_VCTR51_B1641 = 0x200
	// Position of B1642 field.
	GTZC_VCTR51_B1642_Pos = 0xa
	// Bit mask of B1642 field.
	GTZC_VCTR51_B1642_Msk = 0x400
	// Bit B1642.
	GTZC_VCTR51_B1642 = 0x400
	// Position of B1643 field.
	GTZC_VCTR51_B1643_Pos = 0xb
	// Bit mask of B1643 field.
	GTZC_VCTR51_B1643_Msk = 0x800
	// Bit B1643.
	GTZC_VCTR51_B1643 = 0x800
	// Position of B1644 field.
	GTZC_VCTR51_B1644_Pos = 0xc
	// Bit mask of B1644 field.
	GTZC_VCTR51_B1644_Msk = 0x1000
	// Bit B1644.
	GTZC_VCTR51_B1644 = 0x1000
	// Position of B1645 field.
	GTZC_VCTR51_B1645_Pos = 0xd
	// Bit mask of B1645 field.
	GTZC_VCTR51_B1645_Msk = 0x2000
	// Bit B1645.
	GTZC_VCTR51_B1645 = 0x2000
	// Position of B1646 field.
	GTZC_VCTR51_B1646_Pos = 0xe
	// Bit mask of B1646 field.
	GTZC_VCTR51_B1646_Msk = 0x4000
	// Bit B1646.
	GTZC_VCTR51_B1646 = 0x4000
	// Position of B1647 field.
	GTZC_VCTR51_B1647_Pos = 0xf
	// Bit mask of B1647 field.
	GTZC_VCTR51_B1647_Msk = 0x8000
	// Bit B1647.
	GTZC_VCTR51_B1647 = 0x8000
	// Position of B1648 field.
	GTZC_VCTR51_B1648_Pos = 0x10
	// Bit mask of B1648 field.
	GTZC_VCTR51_B1648_Msk = 0x10000
	// Bit B1648.
	GTZC_VCTR51_B1648 = 0x10000
	// Position of B1649 field.
	GTZC_VCTR51_B1649_Pos = 0x11
	// Bit mask of B1649 field.
	GTZC_VCTR51_B1649_Msk = 0x20000
	// Bit B1649.
	GTZC_VCTR51_B1649 = 0x20000
	// Position of B1650 field.
	GTZC_VCTR51_B1650_Pos = 0x12
	// Bit mask of B1650 field.
	GTZC_VCTR51_B1650_Msk = 0x40000
	// Bit B1650.
	GTZC_VCTR51_B1650 = 0x40000
	// Position of B1651 field.
	GTZC_VCTR51_B1651_Pos = 0x13
	// Bit mask of B1651 field.
	GTZC_VCTR51_B1651_Msk = 0x80000
	// Bit B1651.
	GTZC_VCTR51_B1651 = 0x80000
	// Position of B1652 field.
	GTZC_VCTR51_B1652_Pos = 0x14
	// Bit mask of B1652 field.
	GTZC_VCTR51_B1652_Msk = 0x100000
	// Bit B1652.
	GTZC_VCTR51_B1652 = 0x100000
	// Position of B1653 field.
	GTZC_VCTR51_B1653_Pos = 0x15
	// Bit mask of B1653 field.
	GTZC_VCTR51_B1653_Msk = 0x200000
	// Bit B1653.
	GTZC_VCTR51_B1653 = 0x200000
	// Position of B1654 field.
	GTZC_VCTR51_B1654_Pos = 0x16
	// Bit mask of B1654 field.
	GTZC_VCTR51_B1654_Msk = 0x400000
	// Bit B1654.
	GTZC_VCTR51_B1654 = 0x400000
	// Position of B1655 field.
	GTZC_VCTR51_B1655_Pos = 0x17
	// Bit mask of B1655 field.
	GTZC_VCTR51_B1655_Msk = 0x800000
	// Bit B1655.
	GTZC_VCTR51_B1655 = 0x800000
	// Position of B1656 field.
	GTZC_VCTR51_B1656_Pos = 0x18
	// Bit mask of B1656 field.
	GTZC_VCTR51_B1656_Msk = 0x1000000
	// Bit B1656.
	GTZC_VCTR51_B1656 = 0x1000000
	// Position of B1657 field.
	GTZC_VCTR51_B1657_Pos = 0x19
	// Bit mask of B1657 field.
	GTZC_VCTR51_B1657_Msk = 0x2000000
	// Bit B1657.
	GTZC_VCTR51_B1657 = 0x2000000
	// Position of B1658 field.
	GTZC_VCTR51_B1658_Pos = 0x1a
	// Bit mask of B1658 field.
	GTZC_VCTR51_B1658_Msk = 0x4000000
	// Bit B1658.
	GTZC_VCTR51_B1658 = 0x4000000
	// Position of B1659 field.
	GTZC_VCTR51_B1659_Pos = 0x1b
	// Bit mask of B1659 field.
	GTZC_VCTR51_B1659_Msk = 0x8000000
	// Bit B1659.
	GTZC_VCTR51_B1659 = 0x8000000
	// Position of B1660 field.
	GTZC_VCTR51_B1660_Pos = 0x1c
	// Bit mask of B1660 field.
	GTZC_VCTR51_B1660_Msk = 0x10000000
	// Bit B1660.
	GTZC_VCTR51_B1660 = 0x10000000
	// Position of B1661 field.
	GTZC_VCTR51_B1661_Pos = 0x1d
	// Bit mask of B1661 field.
	GTZC_VCTR51_B1661_Msk = 0x20000000
	// Bit B1661.
	GTZC_VCTR51_B1661 = 0x20000000
	// Position of B1662 field.
	GTZC_VCTR51_B1662_Pos = 0x1e
	// Bit mask of B1662 field.
	GTZC_VCTR51_B1662_Msk = 0x40000000
	// Bit B1662.
	GTZC_VCTR51_B1662 = 0x40000000
	// Position of B1663 field.
	GTZC_VCTR51_B1663_Pos = 0x1f
	// Bit mask of B1663 field.
	GTZC_VCTR51_B1663_Msk = 0x80000000
	// Bit B1663.
	GTZC_VCTR51_B1663 = 0x80000000

	// VCTR52: MPCBBx vector register
	// Position of B1664 field.
	GTZC_VCTR52_B1664_Pos = 0x0
	// Bit mask of B1664 field.
	GTZC_VCTR52_B1664_Msk = 0x1
	// Bit B1664.
	GTZC_VCTR52_B1664 = 0x1
	// Position of B1665 field.
	GTZC_VCTR52_B1665_Pos = 0x1
	// Bit mask of B1665 field.
	GTZC_VCTR52_B1665_Msk = 0x2
	// Bit B1665.
	GTZC_VCTR52_B1665 = 0x2
	// Position of B1666 field.
	GTZC_VCTR52_B1666_Pos = 0x2
	// Bit mask of B1666 field.
	GTZC_VCTR52_B1666_Msk = 0x4
	// Bit B1666.
	GTZC_VCTR52_B1666 = 0x4
	// Position of B1667 field.
	GTZC_VCTR52_B1667_Pos = 0x3
	// Bit mask of B1667 field.
	GTZC_VCTR52_B1667_Msk = 0x8
	// Bit B1667.
	GTZC_VCTR52_B1667 = 0x8
	// Position of B1668 field.
	GTZC_VCTR52_B1668_Pos = 0x4
	// Bit mask of B1668 field.
	GTZC_VCTR52_B1668_Msk = 0x10
	// Bit B1668.
	GTZC_VCTR52_B1668 = 0x10
	// Position of B1669 field.
	GTZC_VCTR52_B1669_Pos = 0x5
	// Bit mask of B1669 field.
	GTZC_VCTR52_B1669_Msk = 0x20
	// Bit B1669.
	GTZC_VCTR52_B1669 = 0x20
	// Position of B1670 field.
	GTZC_VCTR52_B1670_Pos = 0x6
	// Bit mask of B1670 field.
	GTZC_VCTR52_B1670_Msk = 0x40
	// Bit B1670.
	GTZC_VCTR52_B1670 = 0x40
	// Position of B1671 field.
	GTZC_VCTR52_B1671_Pos = 0x7
	// Bit mask of B1671 field.
	GTZC_VCTR52_B1671_Msk = 0x80
	// Bit B1671.
	GTZC_VCTR52_B1671 = 0x80
	// Position of B1672 field.
	GTZC_VCTR52_B1672_Pos = 0x8
	// Bit mask of B1672 field.
	GTZC_VCTR52_B1672_Msk = 0x100
	// Bit B1672.
	GTZC_VCTR52_B1672 = 0x100
	// Position of B1673 field.
	GTZC_VCTR52_B1673_Pos = 0x9
	// Bit mask of B1673 field.
	GTZC_VCTR52_B1673_Msk = 0x200
	// Bit B1673.
	GTZC_VCTR52_B1673 = 0x200
	// Position of B1674 field.
	GTZC_VCTR52_B1674_Pos = 0xa
	// Bit mask of B1674 field.
	GTZC_VCTR52_B1674_Msk = 0x400
	// Bit B1674.
	GTZC_VCTR52_B1674 = 0x400
	// Position of B1675 field.
	GTZC_VCTR52_B1675_Pos = 0xb
	// Bit mask of B1675 field.
	GTZC_VCTR52_B1675_Msk = 0x800
	// Bit B1675.
	GTZC_VCTR52_B1675 = 0x800
	// Position of B1676 field.
	GTZC_VCTR52_B1676_Pos = 0xc
	// Bit mask of B1676 field.
	GTZC_VCTR52_B1676_Msk = 0x1000
	// Bit B1676.
	GTZC_VCTR52_B1676 = 0x1000
	// Position of B1677 field.
	GTZC_VCTR52_B1677_Pos = 0xd
	// Bit mask of B1677 field.
	GTZC_VCTR52_B1677_Msk = 0x2000
	// Bit B1677.
	GTZC_VCTR52_B1677 = 0x2000
	// Position of B1678 field.
	GTZC_VCTR52_B1678_Pos = 0xe
	// Bit mask of B1678 field.
	GTZC_VCTR52_B1678_Msk = 0x4000
	// Bit B1678.
	GTZC_VCTR52_B1678 = 0x4000
	// Position of B1679 field.
	GTZC_VCTR52_B1679_Pos = 0xf
	// Bit mask of B1679 field.
	GTZC_VCTR52_B1679_Msk = 0x8000
	// Bit B1679.
	GTZC_VCTR52_B1679 = 0x8000
	// Position of B1680 field.
	GTZC_VCTR52_B1680_Pos = 0x10
	// Bit mask of B1680 field.
	GTZC_VCTR52_B1680_Msk = 0x10000
	// Bit B1680.
	GTZC_VCTR52_B1680 = 0x10000
	// Position of B1681 field.
	GTZC_VCTR52_B1681_Pos = 0x11
	// Bit mask of B1681 field.
	GTZC_VCTR52_B1681_Msk = 0x20000
	// Bit B1681.
	GTZC_VCTR52_B1681 = 0x20000
	// Position of B1682 field.
	GTZC_VCTR52_B1682_Pos = 0x12
	// Bit mask of B1682 field.
	GTZC_VCTR52_B1682_Msk = 0x40000
	// Bit B1682.
	GTZC_VCTR52_B1682 = 0x40000
	// Position of B1683 field.
	GTZC_VCTR52_B1683_Pos = 0x13
	// Bit mask of B1683 field.
	GTZC_VCTR52_B1683_Msk = 0x80000
	// Bit B1683.
	GTZC_VCTR52_B1683 = 0x80000
	// Position of B1684 field.
	GTZC_VCTR52_B1684_Pos = 0x14
	// Bit mask of B1684 field.
	GTZC_VCTR52_B1684_Msk = 0x100000
	// Bit B1684.
	GTZC_VCTR52_B1684 = 0x100000
	// Position of B1685 field.
	GTZC_VCTR52_B1685_Pos = 0x15
	// Bit mask of B1685 field.
	GTZC_VCTR52_B1685_Msk = 0x200000
	// Bit B1685.
	GTZC_VCTR52_B1685 = 0x200000
	// Position of B1686 field.
	GTZC_VCTR52_B1686_Pos = 0x16
	// Bit mask of B1686 field.
	GTZC_VCTR52_B1686_Msk = 0x400000
	// Bit B1686.
	GTZC_VCTR52_B1686 = 0x400000
	// Position of B1687 field.
	GTZC_VCTR52_B1687_Pos = 0x17
	// Bit mask of B1687 field.
	GTZC_VCTR52_B1687_Msk = 0x800000
	// Bit B1687.
	GTZC_VCTR52_B1687 = 0x800000
	// Position of B1688 field.
	GTZC_VCTR52_B1688_Pos = 0x18
	// Bit mask of B1688 field.
	GTZC_VCTR52_B1688_Msk = 0x1000000
	// Bit B1688.
	GTZC_VCTR52_B1688 = 0x1000000
	// Position of B1689 field.
	GTZC_VCTR52_B1689_Pos = 0x19
	// Bit mask of B1689 field.
	GTZC_VCTR52_B1689_Msk = 0x2000000
	// Bit B1689.
	GTZC_VCTR52_B1689 = 0x2000000
	// Position of B1690 field.
	GTZC_VCTR52_B1690_Pos = 0x1a
	// Bit mask of B1690 field.
	GTZC_VCTR52_B1690_Msk = 0x4000000
	// Bit B1690.
	GTZC_VCTR52_B1690 = 0x4000000
	// Position of B1691 field.
	GTZC_VCTR52_B1691_Pos = 0x1b
	// Bit mask of B1691 field.
	GTZC_VCTR52_B1691_Msk = 0x8000000
	// Bit B1691.
	GTZC_VCTR52_B1691 = 0x8000000
	// Position of B1692 field.
	GTZC_VCTR52_B1692_Pos = 0x1c
	// Bit mask of B1692 field.
	GTZC_VCTR52_B1692_Msk = 0x10000000
	// Bit B1692.
	GTZC_VCTR52_B1692 = 0x10000000
	// Position of B1693 field.
	GTZC_VCTR52_B1693_Pos = 0x1d
	// Bit mask of B1693 field.
	GTZC_VCTR52_B1693_Msk = 0x20000000
	// Bit B1693.
	GTZC_VCTR52_B1693 = 0x20000000
	// Position of B1694 field.
	GTZC_VCTR52_B1694_Pos = 0x1e
	// Bit mask of B1694 field.
	GTZC_VCTR52_B1694_Msk = 0x40000000
	// Bit B1694.
	GTZC_VCTR52_B1694 = 0x40000000
	// Position of B1695 field.
	GTZC_VCTR52_B1695_Pos = 0x1f
	// Bit mask of B1695 field.
	GTZC_VCTR52_B1695_Msk = 0x80000000
	// Bit B1695.
	GTZC_VCTR52_B1695 = 0x80000000

	// VCTR53: MPCBBx vector register
	// Position of B1696 field.
	GTZC_VCTR53_B1696_Pos = 0x0
	// Bit mask of B1696 field.
	GTZC_VCTR53_B1696_Msk = 0x1
	// Bit B1696.
	GTZC_VCTR53_B1696 = 0x1
	// Position of B1697 field.
	GTZC_VCTR53_B1697_Pos = 0x1
	// Bit mask of B1697 field.
	GTZC_VCTR53_B1697_Msk = 0x2
	// Bit B1697.
	GTZC_VCTR53_B1697 = 0x2
	// Position of B1698 field.
	GTZC_VCTR53_B1698_Pos = 0x2
	// Bit mask of B1698 field.
	GTZC_VCTR53_B1698_Msk = 0x4
	// Bit B1698.
	GTZC_VCTR53_B1698 = 0x4
	// Position of B1699 field.
	GTZC_VCTR53_B1699_Pos = 0x3
	// Bit mask of B1699 field.
	GTZC_VCTR53_B1699_Msk = 0x8
	// Bit B1699.
	GTZC_VCTR53_B1699 = 0x8
	// Position of B1700 field.
	GTZC_VCTR53_B1700_Pos = 0x4
	// Bit mask of B1700 field.
	GTZC_VCTR53_B1700_Msk = 0x10
	// Bit B1700.
	GTZC_VCTR53_B1700 = 0x10
	// Position of B1701 field.
	GTZC_VCTR53_B1701_Pos = 0x5
	// Bit mask of B1701 field.
	GTZC_VCTR53_B1701_Msk = 0x20
	// Bit B1701.
	GTZC_VCTR53_B1701 = 0x20
	// Position of B1702 field.
	GTZC_VCTR53_B1702_Pos = 0x6
	// Bit mask of B1702 field.
	GTZC_VCTR53_B1702_Msk = 0x40
	// Bit B1702.
	GTZC_VCTR53_B1702 = 0x40
	// Position of B1703 field.
	GTZC_VCTR53_B1703_Pos = 0x7
	// Bit mask of B1703 field.
	GTZC_VCTR53_B1703_Msk = 0x80
	// Bit B1703.
	GTZC_VCTR53_B1703 = 0x80
	// Position of B1704 field.
	GTZC_VCTR53_B1704_Pos = 0x8
	// Bit mask of B1704 field.
	GTZC_VCTR53_B1704_Msk = 0x100
	// Bit B1704.
	GTZC_VCTR53_B1704 = 0x100
	// Position of B1705 field.
	GTZC_VCTR53_B1705_Pos = 0x9
	// Bit mask of B1705 field.
	GTZC_VCTR53_B1705_Msk = 0x200
	// Bit B1705.
	GTZC_VCTR53_B1705 = 0x200
	// Position of B1706 field.
	GTZC_VCTR53_B1706_Pos = 0xa
	// Bit mask of B1706 field.
	GTZC_VCTR53_B1706_Msk = 0x400
	// Bit B1706.
	GTZC_VCTR53_B1706 = 0x400
	// Position of B1707 field.
	GTZC_VCTR53_B1707_Pos = 0xb
	// Bit mask of B1707 field.
	GTZC_VCTR53_B1707_Msk = 0x800
	// Bit B1707.
	GTZC_VCTR53_B1707 = 0x800
	// Position of B1708 field.
	GTZC_VCTR53_B1708_Pos = 0xc
	// Bit mask of B1708 field.
	GTZC_VCTR53_B1708_Msk = 0x1000
	// Bit B1708.
	GTZC_VCTR53_B1708 = 0x1000
	// Position of B1709 field.
	GTZC_VCTR53_B1709_Pos = 0xd
	// Bit mask of B1709 field.
	GTZC_VCTR53_B1709_Msk = 0x2000
	// Bit B1709.
	GTZC_VCTR53_B1709 = 0x2000
	// Position of B1710 field.
	GTZC_VCTR53_B1710_Pos = 0xe
	// Bit mask of B1710 field.
	GTZC_VCTR53_B1710_Msk = 0x4000
	// Bit B1710.
	GTZC_VCTR53_B1710 = 0x4000
	// Position of B1711 field.
	GTZC_VCTR53_B1711_Pos = 0xf
	// Bit mask of B1711 field.
	GTZC_VCTR53_B1711_Msk = 0x8000
	// Bit B1711.
	GTZC_VCTR53_B1711 = 0x8000
	// Position of B1712 field.
	GTZC_VCTR53_B1712_Pos = 0x10
	// Bit mask of B1712 field.
	GTZC_VCTR53_B1712_Msk = 0x10000
	// Bit B1712.
	GTZC_VCTR53_B1712 = 0x10000
	// Position of B1713 field.
	GTZC_VCTR53_B1713_Pos = 0x11
	// Bit mask of B1713 field.
	GTZC_VCTR53_B1713_Msk = 0x20000
	// Bit B1713.
	GTZC_VCTR53_B1713 = 0x20000
	// Position of B1714 field.
	GTZC_VCTR53_B1714_Pos = 0x12
	// Bit mask of B1714 field.
	GTZC_VCTR53_B1714_Msk = 0x40000
	// Bit B1714.
	GTZC_VCTR53_B1714 = 0x40000
	// Position of B1715 field.
	GTZC_VCTR53_B1715_Pos = 0x13
	// Bit mask of B1715 field.
	GTZC_VCTR53_B1715_Msk = 0x80000
	// Bit B1715.
	GTZC_VCTR53_B1715 = 0x80000
	// Position of B1716 field.
	GTZC_VCTR53_B1716_Pos = 0x14
	// Bit mask of B1716 field.
	GTZC_VCTR53_B1716_Msk = 0x100000
	// Bit B1716.
	GTZC_VCTR53_B1716 = 0x100000
	// Position of B1717 field.
	GTZC_VCTR53_B1717_Pos = 0x15
	// Bit mask of B1717 field.
	GTZC_VCTR53_B1717_Msk = 0x200000
	// Bit B1717.
	GTZC_VCTR53_B1717 = 0x200000
	// Position of B1718 field.
	GTZC_VCTR53_B1718_Pos = 0x16
	// Bit mask of B1718 field.
	GTZC_VCTR53_B1718_Msk = 0x400000
	// Bit B1718.
	GTZC_VCTR53_B1718 = 0x400000
	// Position of B1719 field.
	GTZC_VCTR53_B1719_Pos = 0x17
	// Bit mask of B1719 field.
	GTZC_VCTR53_B1719_Msk = 0x800000
	// Bit B1719.
	GTZC_VCTR53_B1719 = 0x800000
	// Position of B1720 field.
	GTZC_VCTR53_B1720_Pos = 0x18
	// Bit mask of B1720 field.
	GTZC_VCTR53_B1720_Msk = 0x1000000
	// Bit B1720.
	GTZC_VCTR53_B1720 = 0x1000000
	// Position of B1721 field.
	GTZC_VCTR53_B1721_Pos = 0x19
	// Bit mask of B1721 field.
	GTZC_VCTR53_B1721_Msk = 0x2000000
	// Bit B1721.
	GTZC_VCTR53_B1721 = 0x2000000
	// Position of B1722 field.
	GTZC_VCTR53_B1722_Pos = 0x1a
	// Bit mask of B1722 field.
	GTZC_VCTR53_B1722_Msk = 0x4000000
	// Bit B1722.
	GTZC_VCTR53_B1722 = 0x4000000
	// Position of B1723 field.
	GTZC_VCTR53_B1723_Pos = 0x1b
	// Bit mask of B1723 field.
	GTZC_VCTR53_B1723_Msk = 0x8000000
	// Bit B1723.
	GTZC_VCTR53_B1723 = 0x8000000
	// Position of B1724 field.
	GTZC_VCTR53_B1724_Pos = 0x1c
	// Bit mask of B1724 field.
	GTZC_VCTR53_B1724_Msk = 0x10000000
	// Bit B1724.
	GTZC_VCTR53_B1724 = 0x10000000
	// Position of B1725 field.
	GTZC_VCTR53_B1725_Pos = 0x1d
	// Bit mask of B1725 field.
	GTZC_VCTR53_B1725_Msk = 0x20000000
	// Bit B1725.
	GTZC_VCTR53_B1725 = 0x20000000
	// Position of B1726 field.
	GTZC_VCTR53_B1726_Pos = 0x1e
	// Bit mask of B1726 field.
	GTZC_VCTR53_B1726_Msk = 0x40000000
	// Bit B1726.
	GTZC_VCTR53_B1726 = 0x40000000
	// Position of B1727 field.
	GTZC_VCTR53_B1727_Pos = 0x1f
	// Bit mask of B1727 field.
	GTZC_VCTR53_B1727_Msk = 0x80000000
	// Bit B1727.
	GTZC_VCTR53_B1727 = 0x80000000

	// VCTR54: MPCBBx vector register
	// Position of B1728 field.
	GTZC_VCTR54_B1728_Pos = 0x0
	// Bit mask of B1728 field.
	GTZC_VCTR54_B1728_Msk = 0x1
	// Bit B1728.
	GTZC_VCTR54_B1728 = 0x1
	// Position of B1729 field.
	GTZC_VCTR54_B1729_Pos = 0x1
	// Bit mask of B1729 field.
	GTZC_VCTR54_B1729_Msk = 0x2
	// Bit B1729.
	GTZC_VCTR54_B1729 = 0x2
	// Position of B1730 field.
	GTZC_VCTR54_B1730_Pos = 0x2
	// Bit mask of B1730 field.
	GTZC_VCTR54_B1730_Msk = 0x4
	// Bit B1730.
	GTZC_VCTR54_B1730 = 0x4
	// Position of B1731 field.
	GTZC_VCTR54_B1731_Pos = 0x3
	// Bit mask of B1731 field.
	GTZC_VCTR54_B1731_Msk = 0x8
	// Bit B1731.
	GTZC_VCTR54_B1731 = 0x8
	// Position of B1732 field.
	GTZC_VCTR54_B1732_Pos = 0x4
	// Bit mask of B1732 field.
	GTZC_VCTR54_B1732_Msk = 0x10
	// Bit B1732.
	GTZC_VCTR54_B1732 = 0x10
	// Position of B1733 field.
	GTZC_VCTR54_B1733_Pos = 0x5
	// Bit mask of B1733 field.
	GTZC_VCTR54_B1733_Msk = 0x20
	// Bit B1733.
	GTZC_VCTR54_B1733 = 0x20
	// Position of B1734 field.
	GTZC_VCTR54_B1734_Pos = 0x6
	// Bit mask of B1734 field.
	GTZC_VCTR54_B1734_Msk = 0x40
	// Bit B1734.
	GTZC_VCTR54_B1734 = 0x40
	// Position of B1735 field.
	GTZC_VCTR54_B1735_Pos = 0x7
	// Bit mask of B1735 field.
	GTZC_VCTR54_B1735_Msk = 0x80
	// Bit B1735.
	GTZC_VCTR54_B1735 = 0x80
	// Position of B1736 field.
	GTZC_VCTR54_B1736_Pos = 0x8
	// Bit mask of B1736 field.
	GTZC_VCTR54_B1736_Msk = 0x100
	// Bit B1736.
	GTZC_VCTR54_B1736 = 0x100
	// Position of B1737 field.
	GTZC_VCTR54_B1737_Pos = 0x9
	// Bit mask of B1737 field.
	GTZC_VCTR54_B1737_Msk = 0x200
	// Bit B1737.
	GTZC_VCTR54_B1737 = 0x200
	// Position of B1738 field.
	GTZC_VCTR54_B1738_Pos = 0xa
	// Bit mask of B1738 field.
	GTZC_VCTR54_B1738_Msk = 0x400
	// Bit B1738.
	GTZC_VCTR54_B1738 = 0x400
	// Position of B1739 field.
	GTZC_VCTR54_B1739_Pos = 0xb
	// Bit mask of B1739 field.
	GTZC_VCTR54_B1739_Msk = 0x800
	// Bit B1739.
	GTZC_VCTR54_B1739 = 0x800
	// Position of B1740 field.
	GTZC_VCTR54_B1740_Pos = 0xc
	// Bit mask of B1740 field.
	GTZC_VCTR54_B1740_Msk = 0x1000
	// Bit B1740.
	GTZC_VCTR54_B1740 = 0x1000
	// Position of B1741 field.
	GTZC_VCTR54_B1741_Pos = 0xd
	// Bit mask of B1741 field.
	GTZC_VCTR54_B1741_Msk = 0x2000
	// Bit B1741.
	GTZC_VCTR54_B1741 = 0x2000
	// Position of B1742 field.
	GTZC_VCTR54_B1742_Pos = 0xe
	// Bit mask of B1742 field.
	GTZC_VCTR54_B1742_Msk = 0x4000
	// Bit B1742.
	GTZC_VCTR54_B1742 = 0x4000
	// Position of B1743 field.
	GTZC_VCTR54_B1743_Pos = 0xf
	// Bit mask of B1743 field.
	GTZC_VCTR54_B1743_Msk = 0x8000
	// Bit B1743.
	GTZC_VCTR54_B1743 = 0x8000
	// Position of B1744 field.
	GTZC_VCTR54_B1744_Pos = 0x10
	// Bit mask of B1744 field.
	GTZC_VCTR54_B1744_Msk = 0x10000
	// Bit B1744.
	GTZC_VCTR54_B1744 = 0x10000
	// Position of B1745 field.
	GTZC_VCTR54_B1745_Pos = 0x11
	// Bit mask of B1745 field.
	GTZC_VCTR54_B1745_Msk = 0x20000
	// Bit B1745.
	GTZC_VCTR54_B1745 = 0x20000
	// Position of B1746 field.
	GTZC_VCTR54_B1746_Pos = 0x12
	// Bit mask of B1746 field.
	GTZC_VCTR54_B1746_Msk = 0x40000
	// Bit B1746.
	GTZC_VCTR54_B1746 = 0x40000
	// Position of B1747 field.
	GTZC_VCTR54_B1747_Pos = 0x13
	// Bit mask of B1747 field.
	GTZC_VCTR54_B1747_Msk = 0x80000
	// Bit B1747.
	GTZC_VCTR54_B1747 = 0x80000
	// Position of B1748 field.
	GTZC_VCTR54_B1748_Pos = 0x14
	// Bit mask of B1748 field.
	GTZC_VCTR54_B1748_Msk = 0x100000
	// Bit B1748.
	GTZC_VCTR54_B1748 = 0x100000
	// Position of B1749 field.
	GTZC_VCTR54_B1749_Pos = 0x15
	// Bit mask of B1749 field.
	GTZC_VCTR54_B1749_Msk = 0x200000
	// Bit B1749.
	GTZC_VCTR54_B1749 = 0x200000
	// Position of B1750 field.
	GTZC_VCTR54_B1750_Pos = 0x16
	// Bit mask of B1750 field.
	GTZC_VCTR54_B1750_Msk = 0x400000
	// Bit B1750.
	GTZC_VCTR54_B1750 = 0x400000
	// Position of B1751 field.
	GTZC_VCTR54_B1751_Pos = 0x17
	// Bit mask of B1751 field.
	GTZC_VCTR54_B1751_Msk = 0x800000
	// Bit B1751.
	GTZC_VCTR54_B1751 = 0x800000
	// Position of B1752 field.
	GTZC_VCTR54_B1752_Pos = 0x18
	// Bit mask of B1752 field.
	GTZC_VCTR54_B1752_Msk = 0x1000000
	// Bit B1752.
	GTZC_VCTR54_B1752 = 0x1000000
	// Position of B1753 field.
	GTZC_VCTR54_B1753_Pos = 0x19
	// Bit mask of B1753 field.
	GTZC_VCTR54_B1753_Msk = 0x2000000
	// Bit B1753.
	GTZC_VCTR54_B1753 = 0x2000000
	// Position of B1754 field.
	GTZC_VCTR54_B1754_Pos = 0x1a
	// Bit mask of B1754 field.
	GTZC_VCTR54_B1754_Msk = 0x4000000
	// Bit B1754.
	GTZC_VCTR54_B1754 = 0x4000000
	// Position of B1755 field.
	GTZC_VCTR54_B1755_Pos = 0x1b
	// Bit mask of B1755 field.
	GTZC_VCTR54_B1755_Msk = 0x8000000
	// Bit B1755.
	GTZC_VCTR54_B1755 = 0x8000000
	// Position of B1756 field.
	GTZC_VCTR54_B1756_Pos = 0x1c
	// Bit mask of B1756 field.
	GTZC_VCTR54_B1756_Msk = 0x10000000
	// Bit B1756.
	GTZC_VCTR54_B1756 = 0x10000000
	// Position of B1757 field.
	GTZC_VCTR54_B1757_Pos = 0x1d
	// Bit mask of B1757 field.
	GTZC_VCTR54_B1757_Msk = 0x20000000
	// Bit B1757.
	GTZC_VCTR54_B1757 = 0x20000000
	// Position of B1758 field.
	GTZC_VCTR54_B1758_Pos = 0x1e
	// Bit mask of B1758 field.
	GTZC_VCTR54_B1758_Msk = 0x40000000
	// Bit B1758.
	GTZC_VCTR54_B1758 = 0x40000000
	// Position of B1759 field.
	GTZC_VCTR54_B1759_Pos = 0x1f
	// Bit mask of B1759 field.
	GTZC_VCTR54_B1759_Msk = 0x80000000
	// Bit B1759.
	GTZC_VCTR54_B1759 = 0x80000000

	// VCTR55: MPCBBx vector register
	// Position of B1760 field.
	GTZC_VCTR55_B1760_Pos = 0x0
	// Bit mask of B1760 field.
	GTZC_VCTR55_B1760_Msk = 0x1
	// Bit B1760.
	GTZC_VCTR55_B1760 = 0x1
	// Position of B1761 field.
	GTZC_VCTR55_B1761_Pos = 0x1
	// Bit mask of B1761 field.
	GTZC_VCTR55_B1761_Msk = 0x2
	// Bit B1761.
	GTZC_VCTR55_B1761 = 0x2
	// Position of B1762 field.
	GTZC_VCTR55_B1762_Pos = 0x2
	// Bit mask of B1762 field.
	GTZC_VCTR55_B1762_Msk = 0x4
	// Bit B1762.
	GTZC_VCTR55_B1762 = 0x4
	// Position of B1763 field.
	GTZC_VCTR55_B1763_Pos = 0x3
	// Bit mask of B1763 field.
	GTZC_VCTR55_B1763_Msk = 0x8
	// Bit B1763.
	GTZC_VCTR55_B1763 = 0x8
	// Position of B1764 field.
	GTZC_VCTR55_B1764_Pos = 0x4
	// Bit mask of B1764 field.
	GTZC_VCTR55_B1764_Msk = 0x10
	// Bit B1764.
	GTZC_VCTR55_B1764 = 0x10
	// Position of B1765 field.
	GTZC_VCTR55_B1765_Pos = 0x5
	// Bit mask of B1765 field.
	GTZC_VCTR55_B1765_Msk = 0x20
	// Bit B1765.
	GTZC_VCTR55_B1765 = 0x20
	// Position of B1766 field.
	GTZC_VCTR55_B1766_Pos = 0x6
	// Bit mask of B1766 field.
	GTZC_VCTR55_B1766_Msk = 0x40
	// Bit B1766.
	GTZC_VCTR55_B1766 = 0x40
	// Position of B1767 field.
	GTZC_VCTR55_B1767_Pos = 0x7
	// Bit mask of B1767 field.
	GTZC_VCTR55_B1767_Msk = 0x80
	// Bit B1767.
	GTZC_VCTR55_B1767 = 0x80
	// Position of B1768 field.
	GTZC_VCTR55_B1768_Pos = 0x8
	// Bit mask of B1768 field.
	GTZC_VCTR55_B1768_Msk = 0x100
	// Bit B1768.
	GTZC_VCTR55_B1768 = 0x100
	// Position of B1769 field.
	GTZC_VCTR55_B1769_Pos = 0x9
	// Bit mask of B1769 field.
	GTZC_VCTR55_B1769_Msk = 0x200
	// Bit B1769.
	GTZC_VCTR55_B1769 = 0x200
	// Position of B1770 field.
	GTZC_VCTR55_B1770_Pos = 0xa
	// Bit mask of B1770 field.
	GTZC_VCTR55_B1770_Msk = 0x400
	// Bit B1770.
	GTZC_VCTR55_B1770 = 0x400
	// Position of B1771 field.
	GTZC_VCTR55_B1771_Pos = 0xb
	// Bit mask of B1771 field.
	GTZC_VCTR55_B1771_Msk = 0x800
	// Bit B1771.
	GTZC_VCTR55_B1771 = 0x800
	// Position of B1772 field.
	GTZC_VCTR55_B1772_Pos = 0xc
	// Bit mask of B1772 field.
	GTZC_VCTR55_B1772_Msk = 0x1000
	// Bit B1772.
	GTZC_VCTR55_B1772 = 0x1000
	// Position of B1773 field.
	GTZC_VCTR55_B1773_Pos = 0xd
	// Bit mask of B1773 field.
	GTZC_VCTR55_B1773_Msk = 0x2000
	// Bit B1773.
	GTZC_VCTR55_B1773 = 0x2000
	// Position of B1774 field.
	GTZC_VCTR55_B1774_Pos = 0xe
	// Bit mask of B1774 field.
	GTZC_VCTR55_B1774_Msk = 0x4000
	// Bit B1774.
	GTZC_VCTR55_B1774 = 0x4000
	// Position of B1775 field.
	GTZC_VCTR55_B1775_Pos = 0xf
	// Bit mask of B1775 field.
	GTZC_VCTR55_B1775_Msk = 0x8000
	// Bit B1775.
	GTZC_VCTR55_B1775 = 0x8000
	// Position of B1776 field.
	GTZC_VCTR55_B1776_Pos = 0x10
	// Bit mask of B1776 field.
	GTZC_VCTR55_B1776_Msk = 0x10000
	// Bit B1776.
	GTZC_VCTR55_B1776 = 0x10000
	// Position of B1777 field.
	GTZC_VCTR55_B1777_Pos = 0x11
	// Bit mask of B1777 field.
	GTZC_VCTR55_B1777_Msk = 0x20000
	// Bit B1777.
	GTZC_VCTR55_B1777 = 0x20000
	// Position of B1778 field.
	GTZC_VCTR55_B1778_Pos = 0x12
	// Bit mask of B1778 field.
	GTZC_VCTR55_B1778_Msk = 0x40000
	// Bit B1778.
	GTZC_VCTR55_B1778 = 0x40000
	// Position of B1779 field.
	GTZC_VCTR55_B1779_Pos = 0x13
	// Bit mask of B1779 field.
	GTZC_VCTR55_B1779_Msk = 0x80000
	// Bit B1779.
	GTZC_VCTR55_B1779 = 0x80000
	// Position of B1780 field.
	GTZC_VCTR55_B1780_Pos = 0x14
	// Bit mask of B1780 field.
	GTZC_VCTR55_B1780_Msk = 0x100000
	// Bit B1780.
	GTZC_VCTR55_B1780 = 0x100000
	// Position of B1781 field.
	GTZC_VCTR55_B1781_Pos = 0x15
	// Bit mask of B1781 field.
	GTZC_VCTR55_B1781_Msk = 0x200000
	// Bit B1781.
	GTZC_VCTR55_B1781 = 0x200000
	// Position of B1782 field.
	GTZC_VCTR55_B1782_Pos = 0x16
	// Bit mask of B1782 field.
	GTZC_VCTR55_B1782_Msk = 0x400000
	// Bit B1782.
	GTZC_VCTR55_B1782 = 0x400000
	// Position of B1783 field.
	GTZC_VCTR55_B1783_Pos = 0x17
	// Bit mask of B1783 field.
	GTZC_VCTR55_B1783_Msk = 0x800000
	// Bit B1783.
	GTZC_VCTR55_B1783 = 0x800000
	// Position of B1784 field.
	GTZC_VCTR55_B1784_Pos = 0x18
	// Bit mask of B1784 field.
	GTZC_VCTR55_B1784_Msk = 0x1000000
	// Bit B1784.
	GTZC_VCTR55_B1784 = 0x1000000
	// Position of B1785 field.
	GTZC_VCTR55_B1785_Pos = 0x19
	// Bit mask of B1785 field.
	GTZC_VCTR55_B1785_Msk = 0x2000000
	// Bit B1785.
	GTZC_VCTR55_B1785 = 0x2000000
	// Position of B1786 field.
	GTZC_VCTR55_B1786_Pos = 0x1a
	// Bit mask of B1786 field.
	GTZC_VCTR55_B1786_Msk = 0x4000000
	// Bit B1786.
	GTZC_VCTR55_B1786 = 0x4000000
	// Position of B1787 field.
	GTZC_VCTR55_B1787_Pos = 0x1b
	// Bit mask of B1787 field.
	GTZC_VCTR55_B1787_Msk = 0x8000000
	// Bit B1787.
	GTZC_VCTR55_B1787 = 0x8000000
	// Position of B1788 field.
	GTZC_VCTR55_B1788_Pos = 0x1c
	// Bit mask of B1788 field.
	GTZC_VCTR55_B1788_Msk = 0x10000000
	// Bit B1788.
	GTZC_VCTR55_B1788 = 0x10000000
	// Position of B1789 field.
	GTZC_VCTR55_B1789_Pos = 0x1d
	// Bit mask of B1789 field.
	GTZC_VCTR55_B1789_Msk = 0x20000000
	// Bit B1789.
	GTZC_VCTR55_B1789 = 0x20000000
	// Position of B1790 field.
	GTZC_VCTR55_B1790_Pos = 0x1e
	// Bit mask of B1790 field.
	GTZC_VCTR55_B1790_Msk = 0x40000000
	// Bit B1790.
	GTZC_VCTR55_B1790 = 0x40000000
	// Position of B1791 field.
	GTZC_VCTR55_B1791_Pos = 0x1f
	// Bit mask of B1791 field.
	GTZC_VCTR55_B1791_Msk = 0x80000000
	// Bit B1791.
	GTZC_VCTR55_B1791 = 0x80000000

	// VCTR56: MPCBBx vector register
	// Position of B1792 field.
	GTZC_VCTR56_B1792_Pos = 0x0
	// Bit mask of B1792 field.
	GTZC_VCTR56_B1792_Msk = 0x1
	// Bit B1792.
	GTZC_VCTR56_B1792 = 0x1
	// Position of B1793 field.
	GTZC_VCTR56_B1793_Pos = 0x1
	// Bit mask of B1793 field.
	GTZC_VCTR56_B1793_Msk = 0x2
	// Bit B1793.
	GTZC_VCTR56_B1793 = 0x2
	// Position of B1794 field.
	GTZC_VCTR56_B1794_Pos = 0x2
	// Bit mask of B1794 field.
	GTZC_VCTR56_B1794_Msk = 0x4
	// Bit B1794.
	GTZC_VCTR56_B1794 = 0x4
	// Position of B1795 field.
	GTZC_VCTR56_B1795_Pos = 0x3
	// Bit mask of B1795 field.
	GTZC_VCTR56_B1795_Msk = 0x8
	// Bit B1795.
	GTZC_VCTR56_B1795 = 0x8
	// Position of B1796 field.
	GTZC_VCTR56_B1796_Pos = 0x4
	// Bit mask of B1796 field.
	GTZC_VCTR56_B1796_Msk = 0x10
	// Bit B1796.
	GTZC_VCTR56_B1796 = 0x10
	// Position of B1797 field.
	GTZC_VCTR56_B1797_Pos = 0x5
	// Bit mask of B1797 field.
	GTZC_VCTR56_B1797_Msk = 0x20
	// Bit B1797.
	GTZC_VCTR56_B1797 = 0x20
	// Position of B1798 field.
	GTZC_VCTR56_B1798_Pos = 0x6
	// Bit mask of B1798 field.
	GTZC_VCTR56_B1798_Msk = 0x40
	// Bit B1798.
	GTZC_VCTR56_B1798 = 0x40
	// Position of B1799 field.
	GTZC_VCTR56_B1799_Pos = 0x7
	// Bit mask of B1799 field.
	GTZC_VCTR56_B1799_Msk = 0x80
	// Bit B1799.
	GTZC_VCTR56_B1799 = 0x80
	// Position of B1800 field.
	GTZC_VCTR56_B1800_Pos = 0x8
	// Bit mask of B1800 field.
	GTZC_VCTR56_B1800_Msk = 0x100
	// Bit B1800.
	GTZC_VCTR56_B1800 = 0x100
	// Position of B1801 field.
	GTZC_VCTR56_B1801_Pos = 0x9
	// Bit mask of B1801 field.
	GTZC_VCTR56_B1801_Msk = 0x200
	// Bit B1801.
	GTZC_VCTR56_B1801 = 0x200
	// Position of B1802 field.
	GTZC_VCTR56_B1802_Pos = 0xa
	// Bit mask of B1802 field.
	GTZC_VCTR56_B1802_Msk = 0x400
	// Bit B1802.
	GTZC_VCTR56_B1802 = 0x400
	// Position of B1803 field.
	GTZC_VCTR56_B1803_Pos = 0xb
	// Bit mask of B1803 field.
	GTZC_VCTR56_B1803_Msk = 0x800
	// Bit B1803.
	GTZC_VCTR56_B1803 = 0x800
	// Position of B1804 field.
	GTZC_VCTR56_B1804_Pos = 0xc
	// Bit mask of B1804 field.
	GTZC_VCTR56_B1804_Msk = 0x1000
	// Bit B1804.
	GTZC_VCTR56_B1804 = 0x1000
	// Position of B1805 field.
	GTZC_VCTR56_B1805_Pos = 0xd
	// Bit mask of B1805 field.
	GTZC_VCTR56_B1805_Msk = 0x2000
	// Bit B1805.
	GTZC_VCTR56_B1805 = 0x2000
	// Position of B1806 field.
	GTZC_VCTR56_B1806_Pos = 0xe
	// Bit mask of B1806 field.
	GTZC_VCTR56_B1806_Msk = 0x4000
	// Bit B1806.
	GTZC_VCTR56_B1806 = 0x4000
	// Position of B1807 field.
	GTZC_VCTR56_B1807_Pos = 0xf
	// Bit mask of B1807 field.
	GTZC_VCTR56_B1807_Msk = 0x8000
	// Bit B1807.
	GTZC_VCTR56_B1807 = 0x8000
	// Position of B1808 field.
	GTZC_VCTR56_B1808_Pos = 0x10
	// Bit mask of B1808 field.
	GTZC_VCTR56_B1808_Msk = 0x10000
	// Bit B1808.
	GTZC_VCTR56_B1808 = 0x10000
	// Position of B1809 field.
	GTZC_VCTR56_B1809_Pos = 0x11
	// Bit mask of B1809 field.
	GTZC_VCTR56_B1809_Msk = 0x20000
	// Bit B1809.
	GTZC_VCTR56_B1809 = 0x20000
	// Position of B1810 field.
	GTZC_VCTR56_B1810_Pos = 0x12
	// Bit mask of B1810 field.
	GTZC_VCTR56_B1810_Msk = 0x40000
	// Bit B1810.
	GTZC_VCTR56_B1810 = 0x40000
	// Position of B1811 field.
	GTZC_VCTR56_B1811_Pos = 0x13
	// Bit mask of B1811 field.
	GTZC_VCTR56_B1811_Msk = 0x80000
	// Bit B1811.
	GTZC_VCTR56_B1811 = 0x80000
	// Position of B1812 field.
	GTZC_VCTR56_B1812_Pos = 0x14
	// Bit mask of B1812 field.
	GTZC_VCTR56_B1812_Msk = 0x100000
	// Bit B1812.
	GTZC_VCTR56_B1812 = 0x100000
	// Position of B1813 field.
	GTZC_VCTR56_B1813_Pos = 0x15
	// Bit mask of B1813 field.
	GTZC_VCTR56_B1813_Msk = 0x200000
	// Bit B1813.
	GTZC_VCTR56_B1813 = 0x200000
	// Position of B1814 field.
	GTZC_VCTR56_B1814_Pos = 0x16
	// Bit mask of B1814 field.
	GTZC_VCTR56_B1814_Msk = 0x400000
	// Bit B1814.
	GTZC_VCTR56_B1814 = 0x400000
	// Position of B1815 field.
	GTZC_VCTR56_B1815_Pos = 0x17
	// Bit mask of B1815 field.
	GTZC_VCTR56_B1815_Msk = 0x800000
	// Bit B1815.
	GTZC_VCTR56_B1815 = 0x800000
	// Position of B1816 field.
	GTZC_VCTR56_B1816_Pos = 0x18
	// Bit mask of B1816 field.
	GTZC_VCTR56_B1816_Msk = 0x1000000
	// Bit B1816.
	GTZC_VCTR56_B1816 = 0x1000000
	// Position of B1817 field.
	GTZC_VCTR56_B1817_Pos = 0x19
	// Bit mask of B1817 field.
	GTZC_VCTR56_B1817_Msk = 0x2000000
	// Bit B1817.
	GTZC_VCTR56_B1817 = 0x2000000
	// Position of B1818 field.
	GTZC_VCTR56_B1818_Pos = 0x1a
	// Bit mask of B1818 field.
	GTZC_VCTR56_B1818_Msk = 0x4000000
	// Bit B1818.
	GTZC_VCTR56_B1818 = 0x4000000
	// Position of B1819 field.
	GTZC_VCTR56_B1819_Pos = 0x1b
	// Bit mask of B1819 field.
	GTZC_VCTR56_B1819_Msk = 0x8000000
	// Bit B1819.
	GTZC_VCTR56_B1819 = 0x8000000
	// Position of B1820 field.
	GTZC_VCTR56_B1820_Pos = 0x1c
	// Bit mask of B1820 field.
	GTZC_VCTR56_B1820_Msk = 0x10000000
	// Bit B1820.
	GTZC_VCTR56_B1820 = 0x10000000
	// Position of B1821 field.
	GTZC_VCTR56_B1821_Pos = 0x1d
	// Bit mask of B1821 field.
	GTZC_VCTR56_B1821_Msk = 0x20000000
	// Bit B1821.
	GTZC_VCTR56_B1821 = 0x20000000
	// Position of B1822 field.
	GTZC_VCTR56_B1822_Pos = 0x1e
	// Bit mask of B1822 field.
	GTZC_VCTR56_B1822_Msk = 0x40000000
	// Bit B1822.
	GTZC_VCTR56_B1822 = 0x40000000
	// Position of B1823 field.
	GTZC_VCTR56_B1823_Pos = 0x1f
	// Bit mask of B1823 field.
	GTZC_VCTR56_B1823_Msk = 0x80000000
	// Bit B1823.
	GTZC_VCTR56_B1823 = 0x80000000

	// VCTR57: MPCBBx vector register
	// Position of B1824 field.
	GTZC_VCTR57_B1824_Pos = 0x0
	// Bit mask of B1824 field.
	GTZC_VCTR57_B1824_Msk = 0x1
	// Bit B1824.
	GTZC_VCTR57_B1824 = 0x1
	// Position of B1825 field.
	GTZC_VCTR57_B1825_Pos = 0x1
	// Bit mask of B1825 field.
	GTZC_VCTR57_B1825_Msk = 0x2
	// Bit B1825.
	GTZC_VCTR57_B1825 = 0x2
	// Position of B1826 field.
	GTZC_VCTR57_B1826_Pos = 0x2
	// Bit mask of B1826 field.
	GTZC_VCTR57_B1826_Msk = 0x4
	// Bit B1826.
	GTZC_VCTR57_B1826 = 0x4
	// Position of B1827 field.
	GTZC_VCTR57_B1827_Pos = 0x3
	// Bit mask of B1827 field.
	GTZC_VCTR57_B1827_Msk = 0x8
	// Bit B1827.
	GTZC_VCTR57_B1827 = 0x8
	// Position of B1828 field.
	GTZC_VCTR57_B1828_Pos = 0x4
	// Bit mask of B1828 field.
	GTZC_VCTR57_B1828_Msk = 0x10
	// Bit B1828.
	GTZC_VCTR57_B1828 = 0x10
	// Position of B1829 field.
	GTZC_VCTR57_B1829_Pos = 0x5
	// Bit mask of B1829 field.
	GTZC_VCTR57_B1829_Msk = 0x20
	// Bit B1829.
	GTZC_VCTR57_B1829 = 0x20
	// Position of B1830 field.
	GTZC_VCTR57_B1830_Pos = 0x6
	// Bit mask of B1830 field.
	GTZC_VCTR57_B1830_Msk = 0x40
	// Bit B1830.
	GTZC_VCTR57_B1830 = 0x40
	// Position of B1831 field.
	GTZC_VCTR57_B1831_Pos = 0x7
	// Bit mask of B1831 field.
	GTZC_VCTR57_B1831_Msk = 0x80
	// Bit B1831.
	GTZC_VCTR57_B1831 = 0x80
	// Position of B1832 field.
	GTZC_VCTR57_B1832_Pos = 0x8
	// Bit mask of B1832 field.
	GTZC_VCTR57_B1832_Msk = 0x100
	// Bit B1832.
	GTZC_VCTR57_B1832 = 0x100
	// Position of B1833 field.
	GTZC_VCTR57_B1833_Pos = 0x9
	// Bit mask of B1833 field.
	GTZC_VCTR57_B1833_Msk = 0x200
	// Bit B1833.
	GTZC_VCTR57_B1833 = 0x200
	// Position of B1834 field.
	GTZC_VCTR57_B1834_Pos = 0xa
	// Bit mask of B1834 field.
	GTZC_VCTR57_B1834_Msk = 0x400
	// Bit B1834.
	GTZC_VCTR57_B1834 = 0x400
	// Position of B1835 field.
	GTZC_VCTR57_B1835_Pos = 0xb
	// Bit mask of B1835 field.
	GTZC_VCTR57_B1835_Msk = 0x800
	// Bit B1835.
	GTZC_VCTR57_B1835 = 0x800
	// Position of B1836 field.
	GTZC_VCTR57_B1836_Pos = 0xc
	// Bit mask of B1836 field.
	GTZC_VCTR57_B1836_Msk = 0x1000
	// Bit B1836.
	GTZC_VCTR57_B1836 = 0x1000
	// Position of B1837 field.
	GTZC_VCTR57_B1837_Pos = 0xd
	// Bit mask of B1837 field.
	GTZC_VCTR57_B1837_Msk = 0x2000
	// Bit B1837.
	GTZC_VCTR57_B1837 = 0x2000
	// Position of B1838 field.
	GTZC_VCTR57_B1838_Pos = 0xe
	// Bit mask of B1838 field.
	GTZC_VCTR57_B1838_Msk = 0x4000
	// Bit B1838.
	GTZC_VCTR57_B1838 = 0x4000
	// Position of B1839 field.
	GTZC_VCTR57_B1839_Pos = 0xf
	// Bit mask of B1839 field.
	GTZC_VCTR57_B1839_Msk = 0x8000
	// Bit B1839.
	GTZC_VCTR57_B1839 = 0x8000
	// Position of B1840 field.
	GTZC_VCTR57_B1840_Pos = 0x10
	// Bit mask of B1840 field.
	GTZC_VCTR57_B1840_Msk = 0x10000
	// Bit B1840.
	GTZC_VCTR57_B1840 = 0x10000
	// Position of B1841 field.
	GTZC_VCTR57_B1841_Pos = 0x11
	// Bit mask of B1841 field.
	GTZC_VCTR57_B1841_Msk = 0x20000
	// Bit B1841.
	GTZC_VCTR57_B1841 = 0x20000
	// Position of B1842 field.
	GTZC_VCTR57_B1842_Pos = 0x12
	// Bit mask of B1842 field.
	GTZC_VCTR57_B1842_Msk = 0x40000
	// Bit B1842.
	GTZC_VCTR57_B1842 = 0x40000
	// Position of B1843 field.
	GTZC_VCTR57_B1843_Pos = 0x13
	// Bit mask of B1843 field.
	GTZC_VCTR57_B1843_Msk = 0x80000
	// Bit B1843.
	GTZC_VCTR57_B1843 = 0x80000
	// Position of B1844 field.
	GTZC_VCTR57_B1844_Pos = 0x14
	// Bit mask of B1844 field.
	GTZC_VCTR57_B1844_Msk = 0x100000
	// Bit B1844.
	GTZC_VCTR57_B1844 = 0x100000
	// Position of B1845 field.
	GTZC_VCTR57_B1845_Pos = 0x15
	// Bit mask of B1845 field.
	GTZC_VCTR57_B1845_Msk = 0x200000
	// Bit B1845.
	GTZC_VCTR57_B1845 = 0x200000
	// Position of B1846 field.
	GTZC_VCTR57_B1846_Pos = 0x16
	// Bit mask of B1846 field.
	GTZC_VCTR57_B1846_Msk = 0x400000
	// Bit B1846.
	GTZC_VCTR57_B1846 = 0x400000
	// Position of B1847 field.
	GTZC_VCTR57_B1847_Pos = 0x17
	// Bit mask of B1847 field.
	GTZC_VCTR57_B1847_Msk = 0x800000
	// Bit B1847.
	GTZC_VCTR57_B1847 = 0x800000
	// Position of B1848 field.
	GTZC_VCTR57_B1848_Pos = 0x18
	// Bit mask of B1848 field.
	GTZC_VCTR57_B1848_Msk = 0x1000000
	// Bit B1848.
	GTZC_VCTR57_B1848 = 0x1000000
	// Position of B1849 field.
	GTZC_VCTR57_B1849_Pos = 0x19
	// Bit mask of B1849 field.
	GTZC_VCTR57_B1849_Msk = 0x2000000
	// Bit B1849.
	GTZC_VCTR57_B1849 = 0x2000000
	// Position of B1850 field.
	GTZC_VCTR57_B1850_Pos = 0x1a
	// Bit mask of B1850 field.
	GTZC_VCTR57_B1850_Msk = 0x4000000
	// Bit B1850.
	GTZC_VCTR57_B1850 = 0x4000000
	// Position of B1851 field.
	GTZC_VCTR57_B1851_Pos = 0x1b
	// Bit mask of B1851 field.
	GTZC_VCTR57_B1851_Msk = 0x8000000
	// Bit B1851.
	GTZC_VCTR57_B1851 = 0x8000000
	// Position of B1852 field.
	GTZC_VCTR57_B1852_Pos = 0x1c
	// Bit mask of B1852 field.
	GTZC_VCTR57_B1852_Msk = 0x10000000
	// Bit B1852.
	GTZC_VCTR57_B1852 = 0x10000000
	// Position of B1853 field.
	GTZC_VCTR57_B1853_Pos = 0x1d
	// Bit mask of B1853 field.
	GTZC_VCTR57_B1853_Msk = 0x20000000
	// Bit B1853.
	GTZC_VCTR57_B1853 = 0x20000000
	// Position of B1854 field.
	GTZC_VCTR57_B1854_Pos = 0x1e
	// Bit mask of B1854 field.
	GTZC_VCTR57_B1854_Msk = 0x40000000
	// Bit B1854.
	GTZC_VCTR57_B1854 = 0x40000000
	// Position of B1855 field.
	GTZC_VCTR57_B1855_Pos = 0x1f
	// Bit mask of B1855 field.
	GTZC_VCTR57_B1855_Msk = 0x80000000
	// Bit B1855.
	GTZC_VCTR57_B1855 = 0x80000000

	// VCTR58: MPCBBx vector register
	// Position of B1856 field.
	GTZC_VCTR58_B1856_Pos = 0x0
	// Bit mask of B1856 field.
	GTZC_VCTR58_B1856_Msk = 0x1
	// Bit B1856.
	GTZC_VCTR58_B1856 = 0x1
	// Position of B1857 field.
	GTZC_VCTR58_B1857_Pos = 0x1
	// Bit mask of B1857 field.
	GTZC_VCTR58_B1857_Msk = 0x2
	// Bit B1857.
	GTZC_VCTR58_B1857 = 0x2
	// Position of B1858 field.
	GTZC_VCTR58_B1858_Pos = 0x2
	// Bit mask of B1858 field.
	GTZC_VCTR58_B1858_Msk = 0x4
	// Bit B1858.
	GTZC_VCTR58_B1858 = 0x4
	// Position of B1859 field.
	GTZC_VCTR58_B1859_Pos = 0x3
	// Bit mask of B1859 field.
	GTZC_VCTR58_B1859_Msk = 0x8
	// Bit B1859.
	GTZC_VCTR58_B1859 = 0x8
	// Position of B1860 field.
	GTZC_VCTR58_B1860_Pos = 0x4
	// Bit mask of B1860 field.
	GTZC_VCTR58_B1860_Msk = 0x10
	// Bit B1860.
	GTZC_VCTR58_B1860 = 0x10
	// Position of B1861 field.
	GTZC_VCTR58_B1861_Pos = 0x5
	// Bit mask of B1861 field.
	GTZC_VCTR58_B1861_Msk = 0x20
	// Bit B1861.
	GTZC_VCTR58_B1861 = 0x20
	// Position of B1862 field.
	GTZC_VCTR58_B1862_Pos = 0x6
	// Bit mask of B1862 field.
	GTZC_VCTR58_B1862_Msk = 0x40
	// Bit B1862.
	GTZC_VCTR58_B1862 = 0x40
	// Position of B1863 field.
	GTZC_VCTR58_B1863_Pos = 0x7
	// Bit mask of B1863 field.
	GTZC_VCTR58_B1863_Msk = 0x80
	// Bit B1863.
	GTZC_VCTR58_B1863 = 0x80
	// Position of B1864 field.
	GTZC_VCTR58_B1864_Pos = 0x8
	// Bit mask of B1864 field.
	GTZC_VCTR58_B1864_Msk = 0x100
	// Bit B1864.
	GTZC_VCTR58_B1864 = 0x100
	// Position of B1865 field.
	GTZC_VCTR58_B1865_Pos = 0x9
	// Bit mask of B1865 field.
	GTZC_VCTR58_B1865_Msk = 0x200
	// Bit B1865.
	GTZC_VCTR58_B1865 = 0x200
	// Position of B1866 field.
	GTZC_VCTR58_B1866_Pos = 0xa
	// Bit mask of B1866 field.
	GTZC_VCTR58_B1866_Msk = 0x400
	// Bit B1866.
	GTZC_VCTR58_B1866 = 0x400
	// Position of B1867 field.
	GTZC_VCTR58_B1867_Pos = 0xb
	// Bit mask of B1867 field.
	GTZC_VCTR58_B1867_Msk = 0x800
	// Bit B1867.
	GTZC_VCTR58_B1867 = 0x800
	// Position of B1868 field.
	GTZC_VCTR58_B1868_Pos = 0xc
	// Bit mask of B1868 field.
	GTZC_VCTR58_B1868_Msk = 0x1000
	// Bit B1868.
	GTZC_VCTR58_B1868 = 0x1000
	// Position of B1869 field.
	GTZC_VCTR58_B1869_Pos = 0xd
	// Bit mask of B1869 field.
	GTZC_VCTR58_B1869_Msk = 0x2000
	// Bit B1869.
	GTZC_VCTR58_B1869 = 0x2000
	// Position of B1870 field.
	GTZC_VCTR58_B1870_Pos = 0xe
	// Bit mask of B1870 field.
	GTZC_VCTR58_B1870_Msk = 0x4000
	// Bit B1870.
	GTZC_VCTR58_B1870 = 0x4000
	// Position of B1871 field.
	GTZC_VCTR58_B1871_Pos = 0xf
	// Bit mask of B1871 field.
	GTZC_VCTR58_B1871_Msk = 0x8000
	// Bit B1871.
	GTZC_VCTR58_B1871 = 0x8000
	// Position of B1872 field.
	GTZC_VCTR58_B1872_Pos = 0x10
	// Bit mask of B1872 field.
	GTZC_VCTR58_B1872_Msk = 0x10000
	// Bit B1872.
	GTZC_VCTR58_B1872 = 0x10000
	// Position of B1873 field.
	GTZC_VCTR58_B1873_Pos = 0x11
	// Bit mask of B1873 field.
	GTZC_VCTR58_B1873_Msk = 0x20000
	// Bit B1873.
	GTZC_VCTR58_B1873 = 0x20000
	// Position of B1874 field.
	GTZC_VCTR58_B1874_Pos = 0x12
	// Bit mask of B1874 field.
	GTZC_VCTR58_B1874_Msk = 0x40000
	// Bit B1874.
	GTZC_VCTR58_B1874 = 0x40000
	// Position of B1875 field.
	GTZC_VCTR58_B1875_Pos = 0x13
	// Bit mask of B1875 field.
	GTZC_VCTR58_B1875_Msk = 0x80000
	// Bit B1875.
	GTZC_VCTR58_B1875 = 0x80000
	// Position of B1876 field.
	GTZC_VCTR58_B1876_Pos = 0x14
	// Bit mask of B1876 field.
	GTZC_VCTR58_B1876_Msk = 0x100000
	// Bit B1876.
	GTZC_VCTR58_B1876 = 0x100000
	// Position of B1877 field.
	GTZC_VCTR58_B1877_Pos = 0x15
	// Bit mask of B1877 field.
	GTZC_VCTR58_B1877_Msk = 0x200000
	// Bit B1877.
	GTZC_VCTR58_B1877 = 0x200000
	// Position of B1878 field.
	GTZC_VCTR58_B1878_Pos = 0x16
	// Bit mask of B1878 field.
	GTZC_VCTR58_B1878_Msk = 0x400000
	// Bit B1878.
	GTZC_VCTR58_B1878 = 0x400000
	// Position of B1879 field.
	GTZC_VCTR58_B1879_Pos = 0x17
	// Bit mask of B1879 field.
	GTZC_VCTR58_B1879_Msk = 0x800000
	// Bit B1879.
	GTZC_VCTR58_B1879 = 0x800000
	// Position of B1880 field.
	GTZC_VCTR58_B1880_Pos = 0x18
	// Bit mask of B1880 field.
	GTZC_VCTR58_B1880_Msk = 0x1000000
	// Bit B1880.
	GTZC_VCTR58_B1880 = 0x1000000
	// Position of B1881 field.
	GTZC_VCTR58_B1881_Pos = 0x19
	// Bit mask of B1881 field.
	GTZC_VCTR58_B1881_Msk = 0x2000000
	// Bit B1881.
	GTZC_VCTR58_B1881 = 0x2000000
	// Position of B1882 field.
	GTZC_VCTR58_B1882_Pos = 0x1a
	// Bit mask of B1882 field.
	GTZC_VCTR58_B1882_Msk = 0x4000000
	// Bit B1882.
	GTZC_VCTR58_B1882 = 0x4000000
	// Position of B1883 field.
	GTZC_VCTR58_B1883_Pos = 0x1b
	// Bit mask of B1883 field.
	GTZC_VCTR58_B1883_Msk = 0x8000000
	// Bit B1883.
	GTZC_VCTR58_B1883 = 0x8000000
	// Position of B1884 field.
	GTZC_VCTR58_B1884_Pos = 0x1c
	// Bit mask of B1884 field.
	GTZC_VCTR58_B1884_Msk = 0x10000000
	// Bit B1884.
	GTZC_VCTR58_B1884 = 0x10000000
	// Position of B1885 field.
	GTZC_VCTR58_B1885_Pos = 0x1d
	// Bit mask of B1885 field.
	GTZC_VCTR58_B1885_Msk = 0x20000000
	// Bit B1885.
	GTZC_VCTR58_B1885 = 0x20000000
	// Position of B1886 field.
	GTZC_VCTR58_B1886_Pos = 0x1e
	// Bit mask of B1886 field.
	GTZC_VCTR58_B1886_Msk = 0x40000000
	// Bit B1886.
	GTZC_VCTR58_B1886 = 0x40000000
	// Position of B1887 field.
	GTZC_VCTR58_B1887_Pos = 0x1f
	// Bit mask of B1887 field.
	GTZC_VCTR58_B1887_Msk = 0x80000000
	// Bit B1887.
	GTZC_VCTR58_B1887 = 0x80000000

	// VCTR59: MPCBBx vector register
	// Position of B1888 field.
	GTZC_VCTR59_B1888_Pos = 0x0
	// Bit mask of B1888 field.
	GTZC_VCTR59_B1888_Msk = 0x1
	// Bit B1888.
	GTZC_VCTR59_B1888 = 0x1
	// Position of B1889 field.
	GTZC_VCTR59_B1889_Pos = 0x1
	// Bit mask of B1889 field.
	GTZC_VCTR59_B1889_Msk = 0x2
	// Bit B1889.
	GTZC_VCTR59_B1889 = 0x2
	// Position of B1890 field.
	GTZC_VCTR59_B1890_Pos = 0x2
	// Bit mask of B1890 field.
	GTZC_VCTR59_B1890_Msk = 0x4
	// Bit B1890.
	GTZC_VCTR59_B1890 = 0x4
	// Position of B1891 field.
	GTZC_VCTR59_B1891_Pos = 0x3
	// Bit mask of B1891 field.
	GTZC_VCTR59_B1891_Msk = 0x8
	// Bit B1891.
	GTZC_VCTR59_B1891 = 0x8
	// Position of B1892 field.
	GTZC_VCTR59_B1892_Pos = 0x4
	// Bit mask of B1892 field.
	GTZC_VCTR59_B1892_Msk = 0x10
	// Bit B1892.
	GTZC_VCTR59_B1892 = 0x10
	// Position of B1893 field.
	GTZC_VCTR59_B1893_Pos = 0x5
	// Bit mask of B1893 field.
	GTZC_VCTR59_B1893_Msk = 0x20
	// Bit B1893.
	GTZC_VCTR59_B1893 = 0x20
	// Position of B1894 field.
	GTZC_VCTR59_B1894_Pos = 0x6
	// Bit mask of B1894 field.
	GTZC_VCTR59_B1894_Msk = 0x40
	// Bit B1894.
	GTZC_VCTR59_B1894 = 0x40
	// Position of B1895 field.
	GTZC_VCTR59_B1895_Pos = 0x7
	// Bit mask of B1895 field.
	GTZC_VCTR59_B1895_Msk = 0x80
	// Bit B1895.
	GTZC_VCTR59_B1895 = 0x80
	// Position of B1896 field.
	GTZC_VCTR59_B1896_Pos = 0x8
	// Bit mask of B1896 field.
	GTZC_VCTR59_B1896_Msk = 0x100
	// Bit B1896.
	GTZC_VCTR59_B1896 = 0x100
	// Position of B1897 field.
	GTZC_VCTR59_B1897_Pos = 0x9
	// Bit mask of B1897 field.
	GTZC_VCTR59_B1897_Msk = 0x200
	// Bit B1897.
	GTZC_VCTR59_B1897 = 0x200
	// Position of B1898 field.
	GTZC_VCTR59_B1898_Pos = 0xa
	// Bit mask of B1898 field.
	GTZC_VCTR59_B1898_Msk = 0x400
	// Bit B1898.
	GTZC_VCTR59_B1898 = 0x400
	// Position of B1899 field.
	GTZC_VCTR59_B1899_Pos = 0xb
	// Bit mask of B1899 field.
	GTZC_VCTR59_B1899_Msk = 0x800
	// Bit B1899.
	GTZC_VCTR59_B1899 = 0x800
	// Position of B1900 field.
	GTZC_VCTR59_B1900_Pos = 0xc
	// Bit mask of B1900 field.
	GTZC_VCTR59_B1900_Msk = 0x1000
	// Bit B1900.
	GTZC_VCTR59_B1900 = 0x1000
	// Position of B1901 field.
	GTZC_VCTR59_B1901_Pos = 0xd
	// Bit mask of B1901 field.
	GTZC_VCTR59_B1901_Msk = 0x2000
	// Bit B1901.
	GTZC_VCTR59_B1901 = 0x2000
	// Position of B1902 field.
	GTZC_VCTR59_B1902_Pos = 0xe
	// Bit mask of B1902 field.
	GTZC_VCTR59_B1902_Msk = 0x4000
	// Bit B1902.
	GTZC_VCTR59_B1902 = 0x4000
	// Position of B1903 field.
	GTZC_VCTR59_B1903_Pos = 0xf
	// Bit mask of B1903 field.
	GTZC_VCTR59_B1903_Msk = 0x8000
	// Bit B1903.
	GTZC_VCTR59_B1903 = 0x8000
	// Position of B1904 field.
	GTZC_VCTR59_B1904_Pos = 0x10
	// Bit mask of B1904 field.
	GTZC_VCTR59_B1904_Msk = 0x10000
	// Bit B1904.
	GTZC_VCTR59_B1904 = 0x10000
	// Position of B1905 field.
	GTZC_VCTR59_B1905_Pos = 0x11
	// Bit mask of B1905 field.
	GTZC_VCTR59_B1905_Msk = 0x20000
	// Bit B1905.
	GTZC_VCTR59_B1905 = 0x20000
	// Position of B1906 field.
	GTZC_VCTR59_B1906_Pos = 0x12
	// Bit mask of B1906 field.
	GTZC_VCTR59_B1906_Msk = 0x40000
	// Bit B1906.
	GTZC_VCTR59_B1906 = 0x40000
	// Position of B1907 field.
	GTZC_VCTR59_B1907_Pos = 0x13
	// Bit mask of B1907 field.
	GTZC_VCTR59_B1907_Msk = 0x80000
	// Bit B1907.
	GTZC_VCTR59_B1907 = 0x80000
	// Position of B1908 field.
	GTZC_VCTR59_B1908_Pos = 0x14
	// Bit mask of B1908 field.
	GTZC_VCTR59_B1908_Msk = 0x100000
	// Bit B1908.
	GTZC_VCTR59_B1908 = 0x100000
	// Position of B1909 field.
	GTZC_VCTR59_B1909_Pos = 0x15
	// Bit mask of B1909 field.
	GTZC_VCTR59_B1909_Msk = 0x200000
	// Bit B1909.
	GTZC_VCTR59_B1909 = 0x200000
	// Position of B1910 field.
	GTZC_VCTR59_B1910_Pos = 0x16
	// Bit mask of B1910 field.
	GTZC_VCTR59_B1910_Msk = 0x400000
	// Bit B1910.
	GTZC_VCTR59_B1910 = 0x400000
	// Position of B1911 field.
	GTZC_VCTR59_B1911_Pos = 0x17
	// Bit mask of B1911 field.
	GTZC_VCTR59_B1911_Msk = 0x800000
	// Bit B1911.
	GTZC_VCTR59_B1911 = 0x800000
	// Position of B1912 field.
	GTZC_VCTR59_B1912_Pos = 0x18
	// Bit mask of B1912 field.
	GTZC_VCTR59_B1912_Msk = 0x1000000
	// Bit B1912.
	GTZC_VCTR59_B1912 = 0x1000000
	// Position of B1913 field.
	GTZC_VCTR59_B1913_Pos = 0x19
	// Bit mask of B1913 field.
	GTZC_VCTR59_B1913_Msk = 0x2000000
	// Bit B1913.
	GTZC_VCTR59_B1913 = 0x2000000
	// Position of B1914 field.
	GTZC_VCTR59_B1914_Pos = 0x1a
	// Bit mask of B1914 field.
	GTZC_VCTR59_B1914_Msk = 0x4000000
	// Bit B1914.
	GTZC_VCTR59_B1914 = 0x4000000
	// Position of B1915 field.
	GTZC_VCTR59_B1915_Pos = 0x1b
	// Bit mask of B1915 field.
	GTZC_VCTR59_B1915_Msk = 0x8000000
	// Bit B1915.
	GTZC_VCTR59_B1915 = 0x8000000
	// Position of B1916 field.
	GTZC_VCTR59_B1916_Pos = 0x1c
	// Bit mask of B1916 field.
	GTZC_VCTR59_B1916_Msk = 0x10000000
	// Bit B1916.
	GTZC_VCTR59_B1916 = 0x10000000
	// Position of B1917 field.
	GTZC_VCTR59_B1917_Pos = 0x1d
	// Bit mask of B1917 field.
	GTZC_VCTR59_B1917_Msk = 0x20000000
	// Bit B1917.
	GTZC_VCTR59_B1917 = 0x20000000
	// Position of B1918 field.
	GTZC_VCTR59_B1918_Pos = 0x1e
	// Bit mask of B1918 field.
	GTZC_VCTR59_B1918_Msk = 0x40000000
	// Bit B1918.
	GTZC_VCTR59_B1918 = 0x40000000
	// Position of B1919 field.
	GTZC_VCTR59_B1919_Pos = 0x1f
	// Bit mask of B1919 field.
	GTZC_VCTR59_B1919_Msk = 0x80000000
	// Bit B1919.
	GTZC_VCTR59_B1919 = 0x80000000

	// VCTR60: MPCBBx vector register
	// Position of B1920 field.
	GTZC_VCTR60_B1920_Pos = 0x0
	// Bit mask of B1920 field.
	GTZC_VCTR60_B1920_Msk = 0x1
	// Bit B1920.
	GTZC_VCTR60_B1920 = 0x1
	// Position of B1921 field.
	GTZC_VCTR60_B1921_Pos = 0x1
	// Bit mask of B1921 field.
	GTZC_VCTR60_B1921_Msk = 0x2
	// Bit B1921.
	GTZC_VCTR60_B1921 = 0x2
	// Position of B1922 field.
	GTZC_VCTR60_B1922_Pos = 0x2
	// Bit mask of B1922 field.
	GTZC_VCTR60_B1922_Msk = 0x4
	// Bit B1922.
	GTZC_VCTR60_B1922 = 0x4
	// Position of B1923 field.
	GTZC_VCTR60_B1923_Pos = 0x3
	// Bit mask of B1923 field.
	GTZC_VCTR60_B1923_Msk = 0x8
	// Bit B1923.
	GTZC_VCTR60_B1923 = 0x8
	// Position of B1924 field.
	GTZC_VCTR60_B1924_Pos = 0x4
	// Bit mask of B1924 field.
	GTZC_VCTR60_B1924_Msk = 0x10
	// Bit B1924.
	GTZC_VCTR60_B1924 = 0x10
	// Position of B1925 field.
	GTZC_VCTR60_B1925_Pos = 0x5
	// Bit mask of B1925 field.
	GTZC_VCTR60_B1925_Msk = 0x20
	// Bit B1925.
	GTZC_VCTR60_B1925 = 0x20
	// Position of B1926 field.
	GTZC_VCTR60_B1926_Pos = 0x6
	// Bit mask of B1926 field.
	GTZC_VCTR60_B1926_Msk = 0x40
	// Bit B1926.
	GTZC_VCTR60_B1926 = 0x40
	// Position of B1927 field.
	GTZC_VCTR60_B1927_Pos = 0x7
	// Bit mask of B1927 field.
	GTZC_VCTR60_B1927_Msk = 0x80
	// Bit B1927.
	GTZC_VCTR60_B1927 = 0x80
	// Position of B1928 field.
	GTZC_VCTR60_B1928_Pos = 0x8
	// Bit mask of B1928 field.
	GTZC_VCTR60_B1928_Msk = 0x100
	// Bit B1928.
	GTZC_VCTR60_B1928 = 0x100
	// Position of B1929 field.
	GTZC_VCTR60_B1929_Pos = 0x9
	// Bit mask of B1929 field.
	GTZC_VCTR60_B1929_Msk = 0x200
	// Bit B1929.
	GTZC_VCTR60_B1929 = 0x200
	// Position of B1930 field.
	GTZC_VCTR60_B1930_Pos = 0xa
	// Bit mask of B1930 field.
	GTZC_VCTR60_B1930_Msk = 0x400
	// Bit B1930.
	GTZC_VCTR60_B1930 = 0x400
	// Position of B1931 field.
	GTZC_VCTR60_B1931_Pos = 0xb
	// Bit mask of B1931 field.
	GTZC_VCTR60_B1931_Msk = 0x800
	// Bit B1931.
	GTZC_VCTR60_B1931 = 0x800
	// Position of B1932 field.
	GTZC_VCTR60_B1932_Pos = 0xc
	// Bit mask of B1932 field.
	GTZC_VCTR60_B1932_Msk = 0x1000
	// Bit B1932.
	GTZC_VCTR60_B1932 = 0x1000
	// Position of B1933 field.
	GTZC_VCTR60_B1933_Pos = 0xd
	// Bit mask of B1933 field.
	GTZC_VCTR60_B1933_Msk = 0x2000
	// Bit B1933.
	GTZC_VCTR60_B1933 = 0x2000
	// Position of B1934 field.
	GTZC_VCTR60_B1934_Pos = 0xe
	// Bit mask of B1934 field.
	GTZC_VCTR60_B1934_Msk = 0x4000
	// Bit B1934.
	GTZC_VCTR60_B1934 = 0x4000
	// Position of B1935 field.
	GTZC_VCTR60_B1935_Pos = 0xf
	// Bit mask of B1935 field.
	GTZC_VCTR60_B1935_Msk = 0x8000
	// Bit B1935.
	GTZC_VCTR60_B1935 = 0x8000
	// Position of B1936 field.
	GTZC_VCTR60_B1936_Pos = 0x10
	// Bit mask of B1936 field.
	GTZC_VCTR60_B1936_Msk = 0x10000
	// Bit B1936.
	GTZC_VCTR60_B1936 = 0x10000
	// Position of B1937 field.
	GTZC_VCTR60_B1937_Pos = 0x11
	// Bit mask of B1937 field.
	GTZC_VCTR60_B1937_Msk = 0x20000
	// Bit B1937.
	GTZC_VCTR60_B1937 = 0x20000
	// Position of B1938 field.
	GTZC_VCTR60_B1938_Pos = 0x12
	// Bit mask of B1938 field.
	GTZC_VCTR60_B1938_Msk = 0x40000
	// Bit B1938.
	GTZC_VCTR60_B1938 = 0x40000
	// Position of B1939 field.
	GTZC_VCTR60_B1939_Pos = 0x13
	// Bit mask of B1939 field.
	GTZC_VCTR60_B1939_Msk = 0x80000
	// Bit B1939.
	GTZC_VCTR60_B1939 = 0x80000
	// Position of B1940 field.
	GTZC_VCTR60_B1940_Pos = 0x14
	// Bit mask of B1940 field.
	GTZC_VCTR60_B1940_Msk = 0x100000
	// Bit B1940.
	GTZC_VCTR60_B1940 = 0x100000
	// Position of B1941 field.
	GTZC_VCTR60_B1941_Pos = 0x15
	// Bit mask of B1941 field.
	GTZC_VCTR60_B1941_Msk = 0x200000
	// Bit B1941.
	GTZC_VCTR60_B1941 = 0x200000
	// Position of B1942 field.
	GTZC_VCTR60_B1942_Pos = 0x16
	// Bit mask of B1942 field.
	GTZC_VCTR60_B1942_Msk = 0x400000
	// Bit B1942.
	GTZC_VCTR60_B1942 = 0x400000
	// Position of B1943 field.
	GTZC_VCTR60_B1943_Pos = 0x17
	// Bit mask of B1943 field.
	GTZC_VCTR60_B1943_Msk = 0x800000
	// Bit B1943.
	GTZC_VCTR60_B1943 = 0x800000
	// Position of B1944 field.
	GTZC_VCTR60_B1944_Pos = 0x18
	// Bit mask of B1944 field.
	GTZC_VCTR60_B1944_Msk = 0x1000000
	// Bit B1944.
	GTZC_VCTR60_B1944 = 0x1000000
	// Position of B1945 field.
	GTZC_VCTR60_B1945_Pos = 0x19
	// Bit mask of B1945 field.
	GTZC_VCTR60_B1945_Msk = 0x2000000
	// Bit B1945.
	GTZC_VCTR60_B1945 = 0x2000000
	// Position of B1946 field.
	GTZC_VCTR60_B1946_Pos = 0x1a
	// Bit mask of B1946 field.
	GTZC_VCTR60_B1946_Msk = 0x4000000
	// Bit B1946.
	GTZC_VCTR60_B1946 = 0x4000000
	// Position of B1947 field.
	GTZC_VCTR60_B1947_Pos = 0x1b
	// Bit mask of B1947 field.
	GTZC_VCTR60_B1947_Msk = 0x8000000
	// Bit B1947.
	GTZC_VCTR60_B1947 = 0x8000000
	// Position of B1948 field.
	GTZC_VCTR60_B1948_Pos = 0x1c
	// Bit mask of B1948 field.
	GTZC_VCTR60_B1948_Msk = 0x10000000
	// Bit B1948.
	GTZC_VCTR60_B1948 = 0x10000000
	// Position of B1949 field.
	GTZC_VCTR60_B1949_Pos = 0x1d
	// Bit mask of B1949 field.
	GTZC_VCTR60_B1949_Msk = 0x20000000
	// Bit B1949.
	GTZC_VCTR60_B1949 = 0x20000000
	// Position of B1950 field.
	GTZC_VCTR60_B1950_Pos = 0x1e
	// Bit mask of B1950 field.
	GTZC_VCTR60_B1950_Msk = 0x40000000
	// Bit B1950.
	GTZC_VCTR60_B1950 = 0x40000000
	// Position of B1951 field.
	GTZC_VCTR60_B1951_Pos = 0x1f
	// Bit mask of B1951 field.
	GTZC_VCTR60_B1951_Msk = 0x80000000
	// Bit B1951.
	GTZC_VCTR60_B1951 = 0x80000000

	// VCTR61: MPCBBx vector register
	// Position of B1952 field.
	GTZC_VCTR61_B1952_Pos = 0x0
	// Bit mask of B1952 field.
	GTZC_VCTR61_B1952_Msk = 0x1
	// Bit B1952.
	GTZC_VCTR61_B1952 = 0x1
	// Position of B1953 field.
	GTZC_VCTR61_B1953_Pos = 0x1
	// Bit mask of B1953 field.
	GTZC_VCTR61_B1953_Msk = 0x2
	// Bit B1953.
	GTZC_VCTR61_B1953 = 0x2
	// Position of B1954 field.
	GTZC_VCTR61_B1954_Pos = 0x2
	// Bit mask of B1954 field.
	GTZC_VCTR61_B1954_Msk = 0x4
	// Bit B1954.
	GTZC_VCTR61_B1954 = 0x4
	// Position of B1955 field.
	GTZC_VCTR61_B1955_Pos = 0x3
	// Bit mask of B1955 field.
	GTZC_VCTR61_B1955_Msk = 0x8
	// Bit B1955.
	GTZC_VCTR61_B1955 = 0x8
	// Position of B1956 field.
	GTZC_VCTR61_B1956_Pos = 0x4
	// Bit mask of B1956 field.
	GTZC_VCTR61_B1956_Msk = 0x10
	// Bit B1956.
	GTZC_VCTR61_B1956 = 0x10
	// Position of B1957 field.
	GTZC_VCTR61_B1957_Pos = 0x5
	// Bit mask of B1957 field.
	GTZC_VCTR61_B1957_Msk = 0x20
	// Bit B1957.
	GTZC_VCTR61_B1957 = 0x20
	// Position of B1958 field.
	GTZC_VCTR61_B1958_Pos = 0x6
	// Bit mask of B1958 field.
	GTZC_VCTR61_B1958_Msk = 0x40
	// Bit B1958.
	GTZC_VCTR61_B1958 = 0x40
	// Position of B1959 field.
	GTZC_VCTR61_B1959_Pos = 0x7
	// Bit mask of B1959 field.
	GTZC_VCTR61_B1959_Msk = 0x80
	// Bit B1959.
	GTZC_VCTR61_B1959 = 0x80
	// Position of B1960 field.
	GTZC_VCTR61_B1960_Pos = 0x8
	// Bit mask of B1960 field.
	GTZC_VCTR61_B1960_Msk = 0x100
	// Bit B1960.
	GTZC_VCTR61_B1960 = 0x100
	// Position of B1961 field.
	GTZC_VCTR61_B1961_Pos = 0x9
	// Bit mask of B1961 field.
	GTZC_VCTR61_B1961_Msk = 0x200
	// Bit B1961.
	GTZC_VCTR61_B1961 = 0x200
	// Position of B1962 field.
	GTZC_VCTR61_B1962_Pos = 0xa
	// Bit mask of B1962 field.
	GTZC_VCTR61_B1962_Msk = 0x400
	// Bit B1962.
	GTZC_VCTR61_B1962 = 0x400
	// Position of B1963 field.
	GTZC_VCTR61_B1963_Pos = 0xb
	// Bit mask of B1963 field.
	GTZC_VCTR61_B1963_Msk = 0x800
	// Bit B1963.
	GTZC_VCTR61_B1963 = 0x800
	// Position of B1964 field.
	GTZC_VCTR61_B1964_Pos = 0xc
	// Bit mask of B1964 field.
	GTZC_VCTR61_B1964_Msk = 0x1000
	// Bit B1964.
	GTZC_VCTR61_B1964 = 0x1000
	// Position of B1965 field.
	GTZC_VCTR61_B1965_Pos = 0xd
	// Bit mask of B1965 field.
	GTZC_VCTR61_B1965_Msk = 0x2000
	// Bit B1965.
	GTZC_VCTR61_B1965 = 0x2000
	// Position of B1966 field.
	GTZC_VCTR61_B1966_Pos = 0xe
	// Bit mask of B1966 field.
	GTZC_VCTR61_B1966_Msk = 0x4000
	// Bit B1966.
	GTZC_VCTR61_B1966 = 0x4000
	// Position of B1967 field.
	GTZC_VCTR61_B1967_Pos = 0xf
	// Bit mask of B1967 field.
	GTZC_VCTR61_B1967_Msk = 0x8000
	// Bit B1967.
	GTZC_VCTR61_B1967 = 0x8000
	// Position of B1968 field.
	GTZC_VCTR61_B1968_Pos = 0x10
	// Bit mask of B1968 field.
	GTZC_VCTR61_B1968_Msk = 0x10000
	// Bit B1968.
	GTZC_VCTR61_B1968 = 0x10000
	// Position of B1969 field.
	GTZC_VCTR61_B1969_Pos = 0x11
	// Bit mask of B1969 field.
	GTZC_VCTR61_B1969_Msk = 0x20000
	// Bit B1969.
	GTZC_VCTR61_B1969 = 0x20000
	// Position of B1970 field.
	GTZC_VCTR61_B1970_Pos = 0x12
	// Bit mask of B1970 field.
	GTZC_VCTR61_B1970_Msk = 0x40000
	// Bit B1970.
	GTZC_VCTR61_B1970 = 0x40000
	// Position of B1971 field.
	GTZC_VCTR61_B1971_Pos = 0x13
	// Bit mask of B1971 field.
	GTZC_VCTR61_B1971_Msk = 0x80000
	// Bit B1971.
	GTZC_VCTR61_B1971 = 0x80000
	// Position of B1972 field.
	GTZC_VCTR61_B1972_Pos = 0x14
	// Bit mask of B1972 field.
	GTZC_VCTR61_B1972_Msk = 0x100000
	// Bit B1972.
	GTZC_VCTR61_B1972 = 0x100000
	// Position of B1973 field.
	GTZC_VCTR61_B1973_Pos = 0x15
	// Bit mask of B1973 field.
	GTZC_VCTR61_B1973_Msk = 0x200000
	// Bit B1973.
	GTZC_VCTR61_B1973 = 0x200000
	// Position of B1974 field.
	GTZC_VCTR61_B1974_Pos = 0x16
	// Bit mask of B1974 field.
	GTZC_VCTR61_B1974_Msk = 0x400000
	// Bit B1974.
	GTZC_VCTR61_B1974 = 0x400000
	// Position of B1975 field.
	GTZC_VCTR61_B1975_Pos = 0x17
	// Bit mask of B1975 field.
	GTZC_VCTR61_B1975_Msk = 0x800000
	// Bit B1975.
	GTZC_VCTR61_B1975 = 0x800000
	// Position of B1976 field.
	GTZC_VCTR61_B1976_Pos = 0x18
	// Bit mask of B1976 field.
	GTZC_VCTR61_B1976_Msk = 0x1000000
	// Bit B1976.
	GTZC_VCTR61_B1976 = 0x1000000
	// Position of B1977 field.
	GTZC_VCTR61_B1977_Pos = 0x19
	// Bit mask of B1977 field.
	GTZC_VCTR61_B1977_Msk = 0x2000000
	// Bit B1977.
	GTZC_VCTR61_B1977 = 0x2000000
	// Position of B1978 field.
	GTZC_VCTR61_B1978_Pos = 0x1a
	// Bit mask of B1978 field.
	GTZC_VCTR61_B1978_Msk = 0x4000000
	// Bit B1978.
	GTZC_VCTR61_B1978 = 0x4000000
	// Position of B1979 field.
	GTZC_VCTR61_B1979_Pos = 0x1b
	// Bit mask of B1979 field.
	GTZC_VCTR61_B1979_Msk = 0x8000000
	// Bit B1979.
	GTZC_VCTR61_B1979 = 0x8000000
	// Position of B1980 field.
	GTZC_VCTR61_B1980_Pos = 0x1c
	// Bit mask of B1980 field.
	GTZC_VCTR61_B1980_Msk = 0x10000000
	// Bit B1980.
	GTZC_VCTR61_B1980 = 0x10000000
	// Position of B1981 field.
	GTZC_VCTR61_B1981_Pos = 0x1d
	// Bit mask of B1981 field.
	GTZC_VCTR61_B1981_Msk = 0x20000000
	// Bit B1981.
	GTZC_VCTR61_B1981 = 0x20000000
	// Position of B1982 field.
	GTZC_VCTR61_B1982_Pos = 0x1e
	// Bit mask of B1982 field.
	GTZC_VCTR61_B1982_Msk = 0x40000000
	// Bit B1982.
	GTZC_VCTR61_B1982 = 0x40000000
	// Position of B1983 field.
	GTZC_VCTR61_B1983_Pos = 0x1f
	// Bit mask of B1983 field.
	GTZC_VCTR61_B1983_Msk = 0x80000000
	// Bit B1983.
	GTZC_VCTR61_B1983 = 0x80000000

	// VCTR62: MPCBBx vector register
	// Position of B1984 field.
	GTZC_VCTR62_B1984_Pos = 0x0
	// Bit mask of B1984 field.
	GTZC_VCTR62_B1984_Msk = 0x1
	// Bit B1984.
	GTZC_VCTR62_B1984 = 0x1
	// Position of B1985 field.
	GTZC_VCTR62_B1985_Pos = 0x1
	// Bit mask of B1985 field.
	GTZC_VCTR62_B1985_Msk = 0x2
	// Bit B1985.
	GTZC_VCTR62_B1985 = 0x2
	// Position of B1986 field.
	GTZC_VCTR62_B1986_Pos = 0x2
	// Bit mask of B1986 field.
	GTZC_VCTR62_B1986_Msk = 0x4
	// Bit B1986.
	GTZC_VCTR62_B1986 = 0x4
	// Position of B1987 field.
	GTZC_VCTR62_B1987_Pos = 0x3
	// Bit mask of B1987 field.
	GTZC_VCTR62_B1987_Msk = 0x8
	// Bit B1987.
	GTZC_VCTR62_B1987 = 0x8
	// Position of B1988 field.
	GTZC_VCTR62_B1988_Pos = 0x4
	// Bit mask of B1988 field.
	GTZC_VCTR62_B1988_Msk = 0x10
	// Bit B1988.
	GTZC_VCTR62_B1988 = 0x10
	// Position of B1989 field.
	GTZC_VCTR62_B1989_Pos = 0x5
	// Bit mask of B1989 field.
	GTZC_VCTR62_B1989_Msk = 0x20
	// Bit B1989.
	GTZC_VCTR62_B1989 = 0x20
	// Position of B1990 field.
	GTZC_VCTR62_B1990_Pos = 0x6
	// Bit mask of B1990 field.
	GTZC_VCTR62_B1990_Msk = 0x40
	// Bit B1990.
	GTZC_VCTR62_B1990 = 0x40
	// Position of B1991 field.
	GTZC_VCTR62_B1991_Pos = 0x7
	// Bit mask of B1991 field.
	GTZC_VCTR62_B1991_Msk = 0x80
	// Bit B1991.
	GTZC_VCTR62_B1991 = 0x80
	// Position of B1992 field.
	GTZC_VCTR62_B1992_Pos = 0x8
	// Bit mask of B1992 field.
	GTZC_VCTR62_B1992_Msk = 0x100
	// Bit B1992.
	GTZC_VCTR62_B1992 = 0x100
	// Position of B1993 field.
	GTZC_VCTR62_B1993_Pos = 0x9
	// Bit mask of B1993 field.
	GTZC_VCTR62_B1993_Msk = 0x200
	// Bit B1993.
	GTZC_VCTR62_B1993 = 0x200
	// Position of B1994 field.
	GTZC_VCTR62_B1994_Pos = 0xa
	// Bit mask of B1994 field.
	GTZC_VCTR62_B1994_Msk = 0x400
	// Bit B1994.
	GTZC_VCTR62_B1994 = 0x400
	// Position of B1995 field.
	GTZC_VCTR62_B1995_Pos = 0xb
	// Bit mask of B1995 field.
	GTZC_VCTR62_B1995_Msk = 0x800
	// Bit B1995.
	GTZC_VCTR62_B1995 = 0x800
	// Position of B1996 field.
	GTZC_VCTR62_B1996_Pos = 0xc
	// Bit mask of B1996 field.
	GTZC_VCTR62_B1996_Msk = 0x1000
	// Bit B1996.
	GTZC_VCTR62_B1996 = 0x1000
	// Position of B1997 field.
	GTZC_VCTR62_B1997_Pos = 0xd
	// Bit mask of B1997 field.
	GTZC_VCTR62_B1997_Msk = 0x2000
	// Bit B1997.
	GTZC_VCTR62_B1997 = 0x2000
	// Position of B1998 field.
	GTZC_VCTR62_B1998_Pos = 0xe
	// Bit mask of B1998 field.
	GTZC_VCTR62_B1998_Msk = 0x4000
	// Bit B1998.
	GTZC_VCTR62_B1998 = 0x4000
	// Position of B1999 field.
	GTZC_VCTR62_B1999_Pos = 0xf
	// Bit mask of B1999 field.
	GTZC_VCTR62_B1999_Msk = 0x8000
	// Bit B1999.
	GTZC_VCTR62_B1999 = 0x8000
	// Position of B2000 field.
	GTZC_VCTR62_B2000_Pos = 0x10
	// Bit mask of B2000 field.
	GTZC_VCTR62_B2000_Msk = 0x10000
	// Bit B2000.
	GTZC_VCTR62_B2000 = 0x10000
	// Position of B2001 field.
	GTZC_VCTR62_B2001_Pos = 0x11
	// Bit mask of B2001 field.
	GTZC_VCTR62_B2001_Msk = 0x20000
	// Bit B2001.
	GTZC_VCTR62_B2001 = 0x20000
	// Position of B2002 field.
	GTZC_VCTR62_B2002_Pos = 0x12
	// Bit mask of B2002 field.
	GTZC_VCTR62_B2002_Msk = 0x40000
	// Bit B2002.
	GTZC_VCTR62_B2002 = 0x40000
	// Position of B2003 field.
	GTZC_VCTR62_B2003_Pos = 0x13
	// Bit mask of B2003 field.
	GTZC_VCTR62_B2003_Msk = 0x80000
	// Bit B2003.
	GTZC_VCTR62_B2003 = 0x80000
	// Position of B2004 field.
	GTZC_VCTR62_B2004_Pos = 0x14
	// Bit mask of B2004 field.
	GTZC_VCTR62_B2004_Msk = 0x100000
	// Bit B2004.
	GTZC_VCTR62_B2004 = 0x100000
	// Position of B2005 field.
	GTZC_VCTR62_B2005_Pos = 0x15
	// Bit mask of B2005 field.
	GTZC_VCTR62_B2005_Msk = 0x200000
	// Bit B2005.
	GTZC_VCTR62_B2005 = 0x200000
	// Position of B2006 field.
	GTZC_VCTR62_B2006_Pos = 0x16
	// Bit mask of B2006 field.
	GTZC_VCTR62_B2006_Msk = 0x400000
	// Bit B2006.
	GTZC_VCTR62_B2006 = 0x400000
	// Position of B2007 field.
	GTZC_VCTR62_B2007_Pos = 0x17
	// Bit mask of B2007 field.
	GTZC_VCTR62_B2007_Msk = 0x800000
	// Bit B2007.
	GTZC_VCTR62_B2007 = 0x800000
	// Position of B2008 field.
	GTZC_VCTR62_B2008_Pos = 0x18
	// Bit mask of B2008 field.
	GTZC_VCTR62_B2008_Msk = 0x1000000
	// Bit B2008.
	GTZC_VCTR62_B2008 = 0x1000000
	// Position of B2009 field.
	GTZC_VCTR62_B2009_Pos = 0x19
	// Bit mask of B2009 field.
	GTZC_VCTR62_B2009_Msk = 0x2000000
	// Bit B2009.
	GTZC_VCTR62_B2009 = 0x2000000
	// Position of B2010 field.
	GTZC_VCTR62_B2010_Pos = 0x1a
	// Bit mask of B2010 field.
	GTZC_VCTR62_B2010_Msk = 0x4000000
	// Bit B2010.
	GTZC_VCTR62_B2010 = 0x4000000
	// Position of B2011 field.
	GTZC_VCTR62_B2011_Pos = 0x1b
	// Bit mask of B2011 field.
	GTZC_VCTR62_B2011_Msk = 0x8000000
	// Bit B2011.
	GTZC_VCTR62_B2011 = 0x8000000
	// Position of B2012 field.
	GTZC_VCTR62_B2012_Pos = 0x1c
	// Bit mask of B2012 field.
	GTZC_VCTR62_B2012_Msk = 0x10000000
	// Bit B2012.
	GTZC_VCTR62_B2012 = 0x10000000
	// Position of B2013 field.
	GTZC_VCTR62_B2013_Pos = 0x1d
	// Bit mask of B2013 field.
	GTZC_VCTR62_B2013_Msk = 0x20000000
	// Bit B2013.
	GTZC_VCTR62_B2013 = 0x20000000
	// Position of B2014 field.
	GTZC_VCTR62_B2014_Pos = 0x1e
	// Bit mask of B2014 field.
	GTZC_VCTR62_B2014_Msk = 0x40000000
	// Bit B2014.
	GTZC_VCTR62_B2014 = 0x40000000
	// Position of B2015 field.
	GTZC_VCTR62_B2015_Pos = 0x1f
	// Bit mask of B2015 field.
	GTZC_VCTR62_B2015_Msk = 0x80000000
	// Bit B2015.
	GTZC_VCTR62_B2015 = 0x80000000

	// VCTR63: MPCBBx vector register
	// Position of B2016 field.
	GTZC_VCTR63_B2016_Pos = 0x0
	// Bit mask of B2016 field.
	GTZC_VCTR63_B2016_Msk = 0x1
	// Bit B2016.
	GTZC_VCTR63_B2016 = 0x1
	// Position of B2017 field.
	GTZC_VCTR63_B2017_Pos = 0x1
	// Bit mask of B2017 field.
	GTZC_VCTR63_B2017_Msk = 0x2
	// Bit B2017.
	GTZC_VCTR63_B2017 = 0x2
	// Position of B2018 field.
	GTZC_VCTR63_B2018_Pos = 0x2
	// Bit mask of B2018 field.
	GTZC_VCTR63_B2018_Msk = 0x4
	// Bit B2018.
	GTZC_VCTR63_B2018 = 0x4
	// Position of B2019 field.
	GTZC_VCTR63_B2019_Pos = 0x3
	// Bit mask of B2019 field.
	GTZC_VCTR63_B2019_Msk = 0x8
	// Bit B2019.
	GTZC_VCTR63_B2019 = 0x8
	// Position of B2020 field.
	GTZC_VCTR63_B2020_Pos = 0x4
	// Bit mask of B2020 field.
	GTZC_VCTR63_B2020_Msk = 0x10
	// Bit B2020.
	GTZC_VCTR63_B2020 = 0x10
	// Position of B2021 field.
	GTZC_VCTR63_B2021_Pos = 0x5
	// Bit mask of B2021 field.
	GTZC_VCTR63_B2021_Msk = 0x20
	// Bit B2021.
	GTZC_VCTR63_B2021 = 0x20
	// Position of B2022 field.
	GTZC_VCTR63_B2022_Pos = 0x6
	// Bit mask of B2022 field.
	GTZC_VCTR63_B2022_Msk = 0x40
	// Bit B2022.
	GTZC_VCTR63_B2022 = 0x40
	// Position of B2023 field.
	GTZC_VCTR63_B2023_Pos = 0x7
	// Bit mask of B2023 field.
	GTZC_VCTR63_B2023_Msk = 0x80
	// Bit B2023.
	GTZC_VCTR63_B2023 = 0x80
	// Position of B2024 field.
	GTZC_VCTR63_B2024_Pos = 0x8
	// Bit mask of B2024 field.
	GTZC_VCTR63_B2024_Msk = 0x100
	// Bit B2024.
	GTZC_VCTR63_B2024 = 0x100
	// Position of B2025 field.
	GTZC_VCTR63_B2025_Pos = 0x9
	// Bit mask of B2025 field.
	GTZC_VCTR63_B2025_Msk = 0x200
	// Bit B2025.
	GTZC_VCTR63_B2025 = 0x200
	// Position of B2026 field.
	GTZC_VCTR63_B2026_Pos = 0xa
	// Bit mask of B2026 field.
	GTZC_VCTR63_B2026_Msk = 0x400
	// Bit B2026.
	GTZC_VCTR63_B2026 = 0x400
	// Position of B2027 field.
	GTZC_VCTR63_B2027_Pos = 0xb
	// Bit mask of B2027 field.
	GTZC_VCTR63_B2027_Msk = 0x800
	// Bit B2027.
	GTZC_VCTR63_B2027 = 0x800
	// Position of B2028 field.
	GTZC_VCTR63_B2028_Pos = 0xc
	// Bit mask of B2028 field.
	GTZC_VCTR63_B2028_Msk = 0x1000
	// Bit B2028.
	GTZC_VCTR63_B2028 = 0x1000
	// Position of B2029 field.
	GTZC_VCTR63_B2029_Pos = 0xd
	// Bit mask of B2029 field.
	GTZC_VCTR63_B2029_Msk = 0x2000
	// Bit B2029.
	GTZC_VCTR63_B2029 = 0x2000
	// Position of B2030 field.
	GTZC_VCTR63_B2030_Pos = 0xe
	// Bit mask of B2030 field.
	GTZC_VCTR63_B2030_Msk = 0x4000
	// Bit B2030.
	GTZC_VCTR63_B2030 = 0x4000
	// Position of B2031 field.
	GTZC_VCTR63_B2031_Pos = 0xf
	// Bit mask of B2031 field.
	GTZC_VCTR63_B2031_Msk = 0x8000
	// Bit B2031.
	GTZC_VCTR63_B2031 = 0x8000
	// Position of B2032 field.
	GTZC_VCTR63_B2032_Pos = 0x10
	// Bit mask of B2032 field.
	GTZC_VCTR63_B2032_Msk = 0x10000
	// Bit B2032.
	GTZC_VCTR63_B2032 = 0x10000
	// Position of B2033 field.
	GTZC_VCTR63_B2033_Pos = 0x11
	// Bit mask of B2033 field.
	GTZC_VCTR63_B2033_Msk = 0x20000
	// Bit B2033.
	GTZC_VCTR63_B2033 = 0x20000
	// Position of B2034 field.
	GTZC_VCTR63_B2034_Pos = 0x12
	// Bit mask of B2034 field.
	GTZC_VCTR63_B2034_Msk = 0x40000
	// Bit B2034.
	GTZC_VCTR63_B2034 = 0x40000
	// Position of B2035 field.
	GTZC_VCTR63_B2035_Pos = 0x13
	// Bit mask of B2035 field.
	GTZC_VCTR63_B2035_Msk = 0x80000
	// Bit B2035.
	GTZC_VCTR63_B2035 = 0x80000
	// Position of B2036 field.
	GTZC_VCTR63_B2036_Pos = 0x14
	// Bit mask of B2036 field.
	GTZC_VCTR63_B2036_Msk = 0x100000
	// Bit B2036.
	GTZC_VCTR63_B2036 = 0x100000
	// Position of B2037 field.
	GTZC_VCTR63_B2037_Pos = 0x15
	// Bit mask of B2037 field.
	GTZC_VCTR63_B2037_Msk = 0x200000
	// Bit B2037.
	GTZC_VCTR63_B2037 = 0x200000
	// Position of B2038 field.
	GTZC_VCTR63_B2038_Pos = 0x16
	// Bit mask of B2038 field.
	GTZC_VCTR63_B2038_Msk = 0x400000
	// Bit B2038.
	GTZC_VCTR63_B2038 = 0x400000
	// Position of B2039 field.
	GTZC_VCTR63_B2039_Pos = 0x17
	// Bit mask of B2039 field.
	GTZC_VCTR63_B2039_Msk = 0x800000
	// Bit B2039.
	GTZC_VCTR63_B2039 = 0x800000
	// Position of B2040 field.
	GTZC_VCTR63_B2040_Pos = 0x18
	// Bit mask of B2040 field.
	GTZC_VCTR63_B2040_Msk = 0x1000000
	// Bit B2040.
	GTZC_VCTR63_B2040 = 0x1000000
	// Position of B2041 field.
	GTZC_VCTR63_B2041_Pos = 0x19
	// Bit mask of B2041 field.
	GTZC_VCTR63_B2041_Msk = 0x2000000
	// Bit B2041.
	GTZC_VCTR63_B2041 = 0x2000000
	// Position of B2042 field.
	GTZC_VCTR63_B2042_Pos = 0x1a
	// Bit mask of B2042 field.
	GTZC_VCTR63_B2042_Msk = 0x4000000
	// Bit B2042.
	GTZC_VCTR63_B2042 = 0x4000000
	// Position of B2043 field.
	GTZC_VCTR63_B2043_Pos = 0x1b
	// Bit mask of B2043 field.
	GTZC_VCTR63_B2043_Msk = 0x8000000
	// Bit B2043.
	GTZC_VCTR63_B2043 = 0x8000000
	// Position of B2044 field.
	GTZC_VCTR63_B2044_Pos = 0x1c
	// Bit mask of B2044 field.
	GTZC_VCTR63_B2044_Msk = 0x10000000
	// Bit B2044.
	GTZC_VCTR63_B2044 = 0x10000000
	// Position of B2045 field.
	GTZC_VCTR63_B2045_Pos = 0x1d
	// Bit mask of B2045 field.
	GTZC_VCTR63_B2045_Msk = 0x20000000
	// Bit B2045.
	GTZC_VCTR63_B2045 = 0x20000000
	// Position of B2046 field.
	GTZC_VCTR63_B2046_Pos = 0x1e
	// Bit mask of B2046 field.
	GTZC_VCTR63_B2046_Msk = 0x40000000
	// Bit B2046.
	GTZC_VCTR63_B2046 = 0x40000000
	// Position of B2047 field.
	GTZC_VCTR63_B2047_Pos = 0x1f
	// Bit mask of B2047 field.
	GTZC_VCTR63_B2047_Msk = 0x80000000
	// Bit B2047.
	GTZC_VCTR63_B2047 = 0x80000000
)

// Constants for HASH: Hash processor
const (
	// CR: control register
	// Position of INIT field.
	HASH_CR_INIT_Pos = 0x2
	// Bit mask of INIT field.
	HASH_CR_INIT_Msk = 0x4
	// Bit INIT.
	HASH_CR_INIT = 0x4
	// Position of DMAE field.
	HASH_CR_DMAE_Pos = 0x3
	// Bit mask of DMAE field.
	HASH_CR_DMAE_Msk = 0x8
	// Bit DMAE.
	HASH_CR_DMAE = 0x8
	// Position of DATATYPE field.
	HASH_CR_DATATYPE_Pos = 0x4
	// Bit mask of DATATYPE field.
	HASH_CR_DATATYPE_Msk = 0x30
	// Position of MODE field.
	HASH_CR_MODE_Pos = 0x6
	// Bit mask of MODE field.
	HASH_CR_MODE_Msk = 0x40
	// Bit MODE.
	HASH_CR_MODE = 0x40
	// Position of ALGO0 field.
	HASH_CR_ALGO0_Pos = 0x7
	// Bit mask of ALGO0 field.
	HASH_CR_ALGO0_Msk = 0x80
	// Bit ALGO0.
	HASH_CR_ALGO0 = 0x80
	// Position of NBW field.
	HASH_CR_NBW_Pos = 0x8
	// Bit mask of NBW field.
	HASH_CR_NBW_Msk = 0xf00
	// Position of DINNE field.
	HASH_CR_DINNE_Pos = 0xc
	// Bit mask of DINNE field.
	HASH_CR_DINNE_Msk = 0x1000
	// Bit DINNE.
	HASH_CR_DINNE = 0x1000
	// Position of MDMAT field.
	HASH_CR_MDMAT_Pos = 0xd
	// Bit mask of MDMAT field.
	HASH_CR_MDMAT_Msk = 0x2000
	// Bit MDMAT.
	HASH_CR_MDMAT = 0x2000
	// Position of LKEY field.
	HASH_CR_LKEY_Pos = 0x10
	// Bit mask of LKEY field.
	HASH_CR_LKEY_Msk = 0x10000
	// Bit LKEY.
	HASH_CR_LKEY = 0x10000
	// Position of ALGO1 field.
	HASH_CR_ALGO1_Pos = 0x12
	// Bit mask of ALGO1 field.
	HASH_CR_ALGO1_Msk = 0x40000
	// Bit ALGO1.
	HASH_CR_ALGO1 = 0x40000

	// DIN: data input register
	// Position of DATAIN field.
	HASH_DIN_DATAIN_Pos = 0x0
	// Bit mask of DATAIN field.
	HASH_DIN_DATAIN_Msk = 0xffffffff

	// STR: start register
	// Position of DCAL field.
	HASH_STR_DCAL_Pos = 0x8
	// Bit mask of DCAL field.
	HASH_STR_DCAL_Msk = 0x100
	// Bit DCAL.
	HASH_STR_DCAL = 0x100
	// Position of NBLW field.
	HASH_STR_NBLW_Pos = 0x0
	// Bit mask of NBLW field.
	HASH_STR_NBLW_Msk = 0x1f

	// HRA0: HASH aliased digest register 0
	// Position of H0 field.
	HASH_HRA0_H0_Pos = 0x0
	// Bit mask of H0 field.
	HASH_HRA0_H0_Msk = 0xffffffff

	// HRA1: HASH aliased digest register 1
	// Position of H1 field.
	HASH_HRA1_H1_Pos = 0x0
	// Bit mask of H1 field.
	HASH_HRA1_H1_Msk = 0xffffffff

	// HRA2: HASH aliased digest register 2
	// Position of H2 field.
	HASH_HRA2_H2_Pos = 0x0
	// Bit mask of H2 field.
	HASH_HRA2_H2_Msk = 0xffffffff

	// HRA3: HASH aliased digest register 3
	// Position of H3 field.
	HASH_HRA3_H3_Pos = 0x0
	// Bit mask of H3 field.
	HASH_HRA3_H3_Msk = 0xffffffff

	// HRA4: HASH aliased digest register 4
	// Position of H4 field.
	HASH_HRA4_H4_Pos = 0x0
	// Bit mask of H4 field.
	HASH_HRA4_H4_Msk = 0xffffffff

	// IMR: interrupt enable register
	// Position of DCIE field.
	HASH_IMR_DCIE_Pos = 0x1
	// Bit mask of DCIE field.
	HASH_IMR_DCIE_Msk = 0x2
	// Bit DCIE.
	HASH_IMR_DCIE = 0x2
	// Position of DINIE field.
	HASH_IMR_DINIE_Pos = 0x0
	// Bit mask of DINIE field.
	HASH_IMR_DINIE_Msk = 0x1
	// Bit DINIE.
	HASH_IMR_DINIE = 0x1

	// SR: status register
	// Position of BUSY field.
	HASH_SR_BUSY_Pos = 0x3
	// Bit mask of BUSY field.
	HASH_SR_BUSY_Msk = 0x8
	// Bit BUSY.
	HASH_SR_BUSY = 0x8
	// Position of DMAS field.
	HASH_SR_DMAS_Pos = 0x2
	// Bit mask of DMAS field.
	HASH_SR_DMAS_Msk = 0x4
	// Bit DMAS.
	HASH_SR_DMAS = 0x4
	// Position of DCIS field.
	HASH_SR_DCIS_Pos = 0x1
	// Bit mask of DCIS field.
	HASH_SR_DCIS_Msk = 0x2
	// Bit DCIS.
	HASH_SR_DCIS = 0x2
	// Position of DINIS field.
	HASH_SR_DINIS_Pos = 0x0
	// Bit mask of DINIS field.
	HASH_SR_DINIS_Msk = 0x1
	// Bit DINIS.
	HASH_SR_DINIS = 0x1

	// CSR0: context swap registers
	// Position of CSR0 field.
	HASH_CSR0_CSR0_Pos = 0x0
	// Bit mask of CSR0 field.
	HASH_CSR0_CSR0_Msk = 0xffffffff

	// CSR1: context swap registers
	// Position of CSR1 field.
	HASH_CSR1_CSR1_Pos = 0x0
	// Bit mask of CSR1 field.
	HASH_CSR1_CSR1_Msk = 0xffffffff

	// CSR2: context swap registers
	// Position of CSR2 field.
	HASH_CSR2_CSR2_Pos = 0x0
	// Bit mask of CSR2 field.
	HASH_CSR2_CSR2_Msk = 0xffffffff

	// CSR3: context swap registers
	// Position of CSR3 field.
	HASH_CSR3_CSR3_Pos = 0x0
	// Bit mask of CSR3 field.
	HASH_CSR3_CSR3_Msk = 0xffffffff

	// CSR4: context swap registers
	// Position of CSR4 field.
	HASH_CSR4_CSR4_Pos = 0x0
	// Bit mask of CSR4 field.
	HASH_CSR4_CSR4_Msk = 0xffffffff

	// CSR5: context swap registers
	// Position of CSR5 field.
	HASH_CSR5_CSR5_Pos = 0x0
	// Bit mask of CSR5 field.
	HASH_CSR5_CSR5_Msk = 0xffffffff

	// CSR6: context swap registers
	// Position of CSR6 field.
	HASH_CSR6_CSR6_Pos = 0x0
	// Bit mask of CSR6 field.
	HASH_CSR6_CSR6_Msk = 0xffffffff

	// CSR7: context swap registers
	// Position of CSR7 field.
	HASH_CSR7_CSR7_Pos = 0x0
	// Bit mask of CSR7 field.
	HASH_CSR7_CSR7_Msk = 0xffffffff

	// CSR8: context swap registers
	// Position of CSR8 field.
	HASH_CSR8_CSR8_Pos = 0x0
	// Bit mask of CSR8 field.
	HASH_CSR8_CSR8_Msk = 0xffffffff

	// CSR9: context swap registers
	// Position of CSR9 field.
	HASH_CSR9_CSR9_Pos = 0x0
	// Bit mask of CSR9 field.
	HASH_CSR9_CSR9_Msk = 0xffffffff

	// CSR10: context swap registers
	// Position of CSR10 field.
	HASH_CSR10_CSR10_Pos = 0x0
	// Bit mask of CSR10 field.
	HASH_CSR10_CSR10_Msk = 0xffffffff

	// CSR11: context swap registers
	// Position of CSR11 field.
	HASH_CSR11_CSR11_Pos = 0x0
	// Bit mask of CSR11 field.
	HASH_CSR11_CSR11_Msk = 0xffffffff

	// CSR12: context swap registers
	// Position of CSR12 field.
	HASH_CSR12_CSR12_Pos = 0x0
	// Bit mask of CSR12 field.
	HASH_CSR12_CSR12_Msk = 0xffffffff

	// CSR13: context swap registers
	// Position of CSR13 field.
	HASH_CSR13_CSR13_Pos = 0x0
	// Bit mask of CSR13 field.
	HASH_CSR13_CSR13_Msk = 0xffffffff

	// CSR14: context swap registers
	// Position of CSR14 field.
	HASH_CSR14_CSR14_Pos = 0x0
	// Bit mask of CSR14 field.
	HASH_CSR14_CSR14_Msk = 0xffffffff

	// CSR15: context swap registers
	// Position of CSR15 field.
	HASH_CSR15_CSR15_Pos = 0x0
	// Bit mask of CSR15 field.
	HASH_CSR15_CSR15_Msk = 0xffffffff

	// CSR16: context swap registers
	// Position of CSR16 field.
	HASH_CSR16_CSR16_Pos = 0x0
	// Bit mask of CSR16 field.
	HASH_CSR16_CSR16_Msk = 0xffffffff

	// CSR17: context swap registers
	// Position of CSR17 field.
	HASH_CSR17_CSR17_Pos = 0x0
	// Bit mask of CSR17 field.
	HASH_CSR17_CSR17_Msk = 0xffffffff

	// CSR18: context swap registers
	// Position of CSR18 field.
	HASH_CSR18_CSR18_Pos = 0x0
	// Bit mask of CSR18 field.
	HASH_CSR18_CSR18_Msk = 0xffffffff

	// CSR19: context swap registers
	// Position of CSR19 field.
	HASH_CSR19_CSR19_Pos = 0x0
	// Bit mask of CSR19 field.
	HASH_CSR19_CSR19_Msk = 0xffffffff

	// CSR20: context swap registers
	// Position of CSR20 field.
	HASH_CSR20_CSR20_Pos = 0x0
	// Bit mask of CSR20 field.
	HASH_CSR20_CSR20_Msk = 0xffffffff

	// CSR21: context swap registers
	// Position of CSR21 field.
	HASH_CSR21_CSR21_Pos = 0x0
	// Bit mask of CSR21 field.
	HASH_CSR21_CSR21_Msk = 0xffffffff

	// CSR22: context swap registers
	// Position of CSR22 field.
	HASH_CSR22_CSR22_Pos = 0x0
	// Bit mask of CSR22 field.
	HASH_CSR22_CSR22_Msk = 0xffffffff

	// CSR23: context swap registers
	// Position of CSR23 field.
	HASH_CSR23_CSR23_Pos = 0x0
	// Bit mask of CSR23 field.
	HASH_CSR23_CSR23_Msk = 0xffffffff

	// CSR24: context swap registers
	// Position of CSR24 field.
	HASH_CSR24_CSR24_Pos = 0x0
	// Bit mask of CSR24 field.
	HASH_CSR24_CSR24_Msk = 0xffffffff

	// CSR25: context swap registers
	// Position of CSR25 field.
	HASH_CSR25_CSR25_Pos = 0x0
	// Bit mask of CSR25 field.
	HASH_CSR25_CSR25_Msk = 0xffffffff

	// CSR26: context swap registers
	// Position of CSR26 field.
	HASH_CSR26_CSR26_Pos = 0x0
	// Bit mask of CSR26 field.
	HASH_CSR26_CSR26_Msk = 0xffffffff

	// CSR27: context swap registers
	// Position of CSR27 field.
	HASH_CSR27_CSR27_Pos = 0x0
	// Bit mask of CSR27 field.
	HASH_CSR27_CSR27_Msk = 0xffffffff

	// CSR28: context swap registers
	// Position of CSR28 field.
	HASH_CSR28_CSR28_Pos = 0x0
	// Bit mask of CSR28 field.
	HASH_CSR28_CSR28_Msk = 0xffffffff

	// CSR29: context swap registers
	// Position of CSR29 field.
	HASH_CSR29_CSR29_Pos = 0x0
	// Bit mask of CSR29 field.
	HASH_CSR29_CSR29_Msk = 0xffffffff

	// CSR30: context swap registers
	// Position of CSR30 field.
	HASH_CSR30_CSR30_Pos = 0x0
	// Bit mask of CSR30 field.
	HASH_CSR30_CSR30_Msk = 0xffffffff

	// CSR31: context swap registers
	// Position of CSR31 field.
	HASH_CSR31_CSR31_Pos = 0x0
	// Bit mask of CSR31 field.
	HASH_CSR31_CSR31_Msk = 0xffffffff

	// CSR32: context swap registers
	// Position of CSR32 field.
	HASH_CSR32_CSR32_Pos = 0x0
	// Bit mask of CSR32 field.
	HASH_CSR32_CSR32_Msk = 0xffffffff

	// CSR33: context swap registers
	// Position of CSR33 field.
	HASH_CSR33_CSR33_Pos = 0x0
	// Bit mask of CSR33 field.
	HASH_CSR33_CSR33_Msk = 0xffffffff

	// CSR34: context swap registers
	// Position of CSR34 field.
	HASH_CSR34_CSR34_Pos = 0x0
	// Bit mask of CSR34 field.
	HASH_CSR34_CSR34_Msk = 0xffffffff

	// CSR35: context swap registers
	// Position of CSR35 field.
	HASH_CSR35_CSR35_Pos = 0x0
	// Bit mask of CSR35 field.
	HASH_CSR35_CSR35_Msk = 0xffffffff

	// CSR36: context swap registers
	// Position of CSR36 field.
	HASH_CSR36_CSR36_Pos = 0x0
	// Bit mask of CSR36 field.
	HASH_CSR36_CSR36_Msk = 0xffffffff

	// CSR37: context swap registers
	// Position of CSR37 field.
	HASH_CSR37_CSR37_Pos = 0x0
	// Bit mask of CSR37 field.
	HASH_CSR37_CSR37_Msk = 0xffffffff

	// CSR38: context swap registers
	// Position of CSR38 field.
	HASH_CSR38_CSR38_Pos = 0x0
	// Bit mask of CSR38 field.
	HASH_CSR38_CSR38_Msk = 0xffffffff

	// CSR39: context swap registers
	// Position of CSR39 field.
	HASH_CSR39_CSR39_Pos = 0x0
	// Bit mask of CSR39 field.
	HASH_CSR39_CSR39_Msk = 0xffffffff

	// CSR40: context swap registers
	// Position of CSR40 field.
	HASH_CSR40_CSR40_Pos = 0x0
	// Bit mask of CSR40 field.
	HASH_CSR40_CSR40_Msk = 0xffffffff

	// CSR41: context swap registers
	// Position of CSR41 field.
	HASH_CSR41_CSR41_Pos = 0x0
	// Bit mask of CSR41 field.
	HASH_CSR41_CSR41_Msk = 0xffffffff

	// CSR42: context swap registers
	// Position of CSR42 field.
	HASH_CSR42_CSR42_Pos = 0x0
	// Bit mask of CSR42 field.
	HASH_CSR42_CSR42_Msk = 0xffffffff

	// CSR43: context swap registers
	// Position of CSR43 field.
	HASH_CSR43_CSR43_Pos = 0x0
	// Bit mask of CSR43 field.
	HASH_CSR43_CSR43_Msk = 0xffffffff

	// CSR44: context swap registers
	// Position of CSR44 field.
	HASH_CSR44_CSR44_Pos = 0x0
	// Bit mask of CSR44 field.
	HASH_CSR44_CSR44_Msk = 0xffffffff

	// CSR45: context swap registers
	// Position of CSR45 field.
	HASH_CSR45_CSR45_Pos = 0x0
	// Bit mask of CSR45 field.
	HASH_CSR45_CSR45_Msk = 0xffffffff

	// CSR46: context swap registers
	// Position of CSR46 field.
	HASH_CSR46_CSR46_Pos = 0x0
	// Bit mask of CSR46 field.
	HASH_CSR46_CSR46_Msk = 0xffffffff

	// CSR47: context swap registers
	// Position of CSR47 field.
	HASH_CSR47_CSR47_Pos = 0x0
	// Bit mask of CSR47 field.
	HASH_CSR47_CSR47_Msk = 0xffffffff

	// CSR48: context swap registers
	// Position of CSR48 field.
	HASH_CSR48_CSR48_Pos = 0x0
	// Bit mask of CSR48 field.
	HASH_CSR48_CSR48_Msk = 0xffffffff

	// CSR49: context swap registers
	// Position of CSR49 field.
	HASH_CSR49_CSR49_Pos = 0x0
	// Bit mask of CSR49 field.
	HASH_CSR49_CSR49_Msk = 0xffffffff

	// CSR50: context swap registers
	// Position of CSR50 field.
	HASH_CSR50_CSR50_Pos = 0x0
	// Bit mask of CSR50 field.
	HASH_CSR50_CSR50_Msk = 0xffffffff

	// CSR51: context swap registers
	// Position of CSR51 field.
	HASH_CSR51_CSR51_Pos = 0x0
	// Bit mask of CSR51 field.
	HASH_CSR51_CSR51_Msk = 0xffffffff

	// CSR52: context swap registers
	// Position of CSR52 field.
	HASH_CSR52_CSR52_Pos = 0x0
	// Bit mask of CSR52 field.
	HASH_CSR52_CSR52_Msk = 0xffffffff

	// CSR53: context swap registers
	// Position of CSR53 field.
	HASH_CSR53_CSR53_Pos = 0x0
	// Bit mask of CSR53 field.
	HASH_CSR53_CSR53_Msk = 0xffffffff

	// HR0: digest register 0
	// Position of H0 field.
	HASH_HR0_H0_Pos = 0x0
	// Bit mask of H0 field.
	HASH_HR0_H0_Msk = 0xffffffff

	// HR1: digest register 1
	// Position of H1 field.
	HASH_HR1_H1_Pos = 0x0
	// Bit mask of H1 field.
	HASH_HR1_H1_Msk = 0xffffffff

	// HR2: digest register 4
	// Position of H2 field.
	HASH_HR2_H2_Pos = 0x0
	// Bit mask of H2 field.
	HASH_HR2_H2_Msk = 0xffffffff

	// HR3: digest register 3
	// Position of H3 field.
	HASH_HR3_H3_Pos = 0x0
	// Bit mask of H3 field.
	HASH_HR3_H3_Msk = 0xffffffff

	// HR4: digest register 4
	// Position of H4 field.
	HASH_HR4_H4_Pos = 0x0
	// Bit mask of H4 field.
	HASH_HR4_H4_Msk = 0xffffffff

	// HR5: supplementary digest register 5
	// Position of H5 field.
	HASH_HR5_H5_Pos = 0x0
	// Bit mask of H5 field.
	HASH_HR5_H5_Msk = 0xffffffff

	// HR6: supplementary digest register 6
	// Position of H6 field.
	HASH_HR6_H6_Pos = 0x0
	// Bit mask of H6 field.
	HASH_HR6_H6_Msk = 0xffffffff

	// HR7: supplementary digest register 7
	// Position of H7 field.
	HASH_HR7_H7_Pos = 0x0
	// Bit mask of H7 field.
	HASH_HR7_H7_Msk = 0xffffffff
)

// Constants for I2C1: Inter-integrated circuit
const (
	// CR1: Control register 1
	// Position of PE field.
	I2C_CR1_PE_Pos = 0x0
	// Bit mask of PE field.
	I2C_CR1_PE_Msk = 0x1
	// Bit PE.
	I2C_CR1_PE = 0x1
	// Position of TXIE field.
	I2C_CR1_TXIE_Pos = 0x1
	// Bit mask of TXIE field.
	I2C_CR1_TXIE_Msk = 0x2
	// Bit TXIE.
	I2C_CR1_TXIE = 0x2
	// Position of RXIE field.
	I2C_CR1_RXIE_Pos = 0x2
	// Bit mask of RXIE field.
	I2C_CR1_RXIE_Msk = 0x4
	// Bit RXIE.
	I2C_CR1_RXIE = 0x4
	// Position of ADDRIE field.
	I2C_CR1_ADDRIE_Pos = 0x3
	// Bit mask of ADDRIE field.
	I2C_CR1_ADDRIE_Msk = 0x8
	// Bit ADDRIE.
	I2C_CR1_ADDRIE = 0x8
	// Position of NACKIE field.
	I2C_CR1_NACKIE_Pos = 0x4
	// Bit mask of NACKIE field.
	I2C_CR1_NACKIE_Msk = 0x10
	// Bit NACKIE.
	I2C_CR1_NACKIE = 0x10
	// Position of STOPIE field.
	I2C_CR1_STOPIE_Pos = 0x5
	// Bit mask of STOPIE field.
	I2C_CR1_STOPIE_Msk = 0x20
	// Bit STOPIE.
	I2C_CR1_STOPIE = 0x20
	// Position of TCIE field.
	I2C_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	I2C_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	I2C_CR1_TCIE = 0x40
	// Position of ERRIE field.
	I2C_CR1_ERRIE_Pos = 0x7
	// Bit mask of ERRIE field.
	I2C_CR1_ERRIE_Msk = 0x80
	// Bit ERRIE.
	I2C_CR1_ERRIE = 0x80
	// Position of DNF field.
	I2C_CR1_DNF_Pos = 0x8
	// Bit mask of DNF field.
	I2C_CR1_DNF_Msk = 0xf00
	// Position of ANFOFF field.
	I2C_CR1_ANFOFF_Pos = 0xc
	// Bit mask of ANFOFF field.
	I2C_CR1_ANFOFF_Msk = 0x1000
	// Bit ANFOFF.
	I2C_CR1_ANFOFF = 0x1000
	// Position of TXDMAEN field.
	I2C_CR1_TXDMAEN_Pos = 0xe
	// Bit mask of TXDMAEN field.
	I2C_CR1_TXDMAEN_Msk = 0x4000
	// Bit TXDMAEN.
	I2C_CR1_TXDMAEN = 0x4000
	// Position of RXDMAEN field.
	I2C_CR1_RXDMAEN_Pos = 0xf
	// Bit mask of RXDMAEN field.
	I2C_CR1_RXDMAEN_Msk = 0x8000
	// Bit RXDMAEN.
	I2C_CR1_RXDMAEN = 0x8000
	// Position of SBC field.
	I2C_CR1_SBC_Pos = 0x10
	// Bit mask of SBC field.
	I2C_CR1_SBC_Msk = 0x10000
	// Bit SBC.
	I2C_CR1_SBC = 0x10000
	// Position of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Pos = 0x11
	// Bit mask of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Msk = 0x20000
	// Bit NOSTRETCH.
	I2C_CR1_NOSTRETCH = 0x20000
	// Position of WUPEN field.
	I2C_CR1_WUPEN_Pos = 0x12
	// Bit mask of WUPEN field.
	I2C_CR1_WUPEN_Msk = 0x40000
	// Bit WUPEN.
	I2C_CR1_WUPEN = 0x40000
	// Position of GCEN field.
	I2C_CR1_GCEN_Pos = 0x13
	// Bit mask of GCEN field.
	I2C_CR1_GCEN_Msk = 0x80000
	// Bit GCEN.
	I2C_CR1_GCEN = 0x80000
	// Position of SMBHEN field.
	I2C_CR1_SMBHEN_Pos = 0x14
	// Bit mask of SMBHEN field.
	I2C_CR1_SMBHEN_Msk = 0x100000
	// Bit SMBHEN.
	I2C_CR1_SMBHEN = 0x100000
	// Position of SMBDEN field.
	I2C_CR1_SMBDEN_Pos = 0x15
	// Bit mask of SMBDEN field.
	I2C_CR1_SMBDEN_Msk = 0x200000
	// Bit SMBDEN.
	I2C_CR1_SMBDEN = 0x200000
	// Position of ALERTEN field.
	I2C_CR1_ALERTEN_Pos = 0x16
	// Bit mask of ALERTEN field.
	I2C_CR1_ALERTEN_Msk = 0x400000
	// Bit ALERTEN.
	I2C_CR1_ALERTEN = 0x400000
	// Position of PECEN field.
	I2C_CR1_PECEN_Pos = 0x17
	// Bit mask of PECEN field.
	I2C_CR1_PECEN_Msk = 0x800000
	// Bit PECEN.
	I2C_CR1_PECEN = 0x800000

	// CR2: Control register 2
	// Position of PECBYTE field.
	I2C_CR2_PECBYTE_Pos = 0x1a
	// Bit mask of PECBYTE field.
	I2C_CR2_PECBYTE_Msk = 0x4000000
	// Bit PECBYTE.
	I2C_CR2_PECBYTE = 0x4000000
	// Position of AUTOEND field.
	I2C_CR2_AUTOEND_Pos = 0x19
	// Bit mask of AUTOEND field.
	I2C_CR2_AUTOEND_Msk = 0x2000000
	// Bit AUTOEND.
	I2C_CR2_AUTOEND = 0x2000000
	// Position of RELOAD field.
	I2C_CR2_RELOAD_Pos = 0x18
	// Bit mask of RELOAD field.
	I2C_CR2_RELOAD_Msk = 0x1000000
	// Bit RELOAD.
	I2C_CR2_RELOAD = 0x1000000
	// Position of NBYTES field.
	I2C_CR2_NBYTES_Pos = 0x10
	// Bit mask of NBYTES field.
	I2C_CR2_NBYTES_Msk = 0xff0000
	// Position of NACK field.
	I2C_CR2_NACK_Pos = 0xf
	// Bit mask of NACK field.
	I2C_CR2_NACK_Msk = 0x8000
	// Bit NACK.
	I2C_CR2_NACK = 0x8000
	// Position of STOP field.
	I2C_CR2_STOP_Pos = 0xe
	// Bit mask of STOP field.
	I2C_CR2_STOP_Msk = 0x4000
	// Bit STOP.
	I2C_CR2_STOP = 0x4000
	// Position of START field.
	I2C_CR2_START_Pos = 0xd
	// Bit mask of START field.
	I2C_CR2_START_Msk = 0x2000
	// Bit START.
	I2C_CR2_START = 0x2000
	// Position of HEAD10R field.
	I2C_CR2_HEAD10R_Pos = 0xc
	// Bit mask of HEAD10R field.
	I2C_CR2_HEAD10R_Msk = 0x1000
	// Bit HEAD10R.
	I2C_CR2_HEAD10R = 0x1000
	// Position of ADD10 field.
	I2C_CR2_ADD10_Pos = 0xb
	// Bit mask of ADD10 field.
	I2C_CR2_ADD10_Msk = 0x800
	// Bit ADD10.
	I2C_CR2_ADD10 = 0x800
	// Position of RD_WRN field.
	I2C_CR2_RD_WRN_Pos = 0xa
	// Bit mask of RD_WRN field.
	I2C_CR2_RD_WRN_Msk = 0x400
	// Bit RD_WRN.
	I2C_CR2_RD_WRN = 0x400
	// Position of SADD field.
	I2C_CR2_SADD_Pos = 0x0
	// Bit mask of SADD field.
	I2C_CR2_SADD_Msk = 0x3ff

	// OAR1: Own address register 1
	// Position of OA1 field.
	I2C_OAR1_OA1_Pos = 0x0
	// Bit mask of OA1 field.
	I2C_OAR1_OA1_Msk = 0x3ff
	// Position of OA1MODE field.
	I2C_OAR1_OA1MODE_Pos = 0xa
	// Bit mask of OA1MODE field.
	I2C_OAR1_OA1MODE_Msk = 0x400
	// Bit OA1MODE.
	I2C_OAR1_OA1MODE = 0x400
	// Position of OA1EN field.
	I2C_OAR1_OA1EN_Pos = 0xf
	// Bit mask of OA1EN field.
	I2C_OAR1_OA1EN_Msk = 0x8000
	// Bit OA1EN.
	I2C_OAR1_OA1EN = 0x8000

	// OAR2: Own address register 2
	// Position of OA2 field.
	I2C_OAR2_OA2_Pos = 0x1
	// Bit mask of OA2 field.
	I2C_OAR2_OA2_Msk = 0xfe
	// Position of OA2MSK field.
	I2C_OAR2_OA2MSK_Pos = 0x8
	// Bit mask of OA2MSK field.
	I2C_OAR2_OA2MSK_Msk = 0x700
	// Position of OA2EN field.
	I2C_OAR2_OA2EN_Pos = 0xf
	// Bit mask of OA2EN field.
	I2C_OAR2_OA2EN_Msk = 0x8000
	// Bit OA2EN.
	I2C_OAR2_OA2EN = 0x8000

	// TIMINGR: Timing register
	// Position of SCLL field.
	I2C_TIMINGR_SCLL_Pos = 0x0
	// Bit mask of SCLL field.
	I2C_TIMINGR_SCLL_Msk = 0xff
	// Position of SCLH field.
	I2C_TIMINGR_SCLH_Pos = 0x8
	// Bit mask of SCLH field.
	I2C_TIMINGR_SCLH_Msk = 0xff00
	// Position of SDADEL field.
	I2C_TIMINGR_SDADEL_Pos = 0x10
	// Bit mask of SDADEL field.
	I2C_TIMINGR_SDADEL_Msk = 0xf0000
	// Position of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Pos = 0x14
	// Bit mask of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Msk = 0xf00000
	// Position of PRESC field.
	I2C_TIMINGR_PRESC_Pos = 0x1c
	// Bit mask of PRESC field.
	I2C_TIMINGR_PRESC_Msk = 0xf0000000

	// TIMEOUTR: Status register 1
	// Position of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0
	// Bit mask of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff
	// Position of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Pos = 0xc
	// Bit mask of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Msk = 0x1000
	// Bit TIDLE.
	I2C_TIMEOUTR_TIDLE = 0x1000
	// Position of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf
	// Bit mask of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000
	// Bit TIMOUTEN.
	I2C_TIMEOUTR_TIMOUTEN = 0x8000
	// Position of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10
	// Bit mask of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000
	// Position of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Pos = 0x1f
	// Bit mask of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Msk = 0x80000000
	// Bit TEXTEN.
	I2C_TIMEOUTR_TEXTEN = 0x80000000

	// ISR: Interrupt and Status register
	// Position of ADDCODE field.
	I2C_ISR_ADDCODE_Pos = 0x11
	// Bit mask of ADDCODE field.
	I2C_ISR_ADDCODE_Msk = 0xfe0000
	// Position of DIR field.
	I2C_ISR_DIR_Pos = 0x10
	// Bit mask of DIR field.
	I2C_ISR_DIR_Msk = 0x10000
	// Bit DIR.
	I2C_ISR_DIR = 0x10000
	// Position of BUSY field.
	I2C_ISR_BUSY_Pos = 0xf
	// Bit mask of BUSY field.
	I2C_ISR_BUSY_Msk = 0x8000
	// Bit BUSY.
	I2C_ISR_BUSY = 0x8000
	// Position of ALERT field.
	I2C_ISR_ALERT_Pos = 0xd
	// Bit mask of ALERT field.
	I2C_ISR_ALERT_Msk = 0x2000
	// Bit ALERT.
	I2C_ISR_ALERT = 0x2000
	// Position of TIMEOUT field.
	I2C_ISR_TIMEOUT_Pos = 0xc
	// Bit mask of TIMEOUT field.
	I2C_ISR_TIMEOUT_Msk = 0x1000
	// Bit TIMEOUT.
	I2C_ISR_TIMEOUT = 0x1000
	// Position of PECERR field.
	I2C_ISR_PECERR_Pos = 0xb
	// Bit mask of PECERR field.
	I2C_ISR_PECERR_Msk = 0x800
	// Bit PECERR.
	I2C_ISR_PECERR = 0x800
	// Position of OVR field.
	I2C_ISR_OVR_Pos = 0xa
	// Bit mask of OVR field.
	I2C_ISR_OVR_Msk = 0x400
	// Bit OVR.
	I2C_ISR_OVR = 0x400
	// Position of ARLO field.
	I2C_ISR_ARLO_Pos = 0x9
	// Bit mask of ARLO field.
	I2C_ISR_ARLO_Msk = 0x200
	// Bit ARLO.
	I2C_ISR_ARLO = 0x200
	// Position of BERR field.
	I2C_ISR_BERR_Pos = 0x8
	// Bit mask of BERR field.
	I2C_ISR_BERR_Msk = 0x100
	// Bit BERR.
	I2C_ISR_BERR = 0x100
	// Position of TCR field.
	I2C_ISR_TCR_Pos = 0x7
	// Bit mask of TCR field.
	I2C_ISR_TCR_Msk = 0x80
	// Bit TCR.
	I2C_ISR_TCR = 0x80
	// Position of TC field.
	I2C_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	I2C_ISR_TC_Msk = 0x40
	// Bit TC.
	I2C_ISR_TC = 0x40
	// Position of STOPF field.
	I2C_ISR_STOPF_Pos = 0x5
	// Bit mask of STOPF field.
	I2C_ISR_STOPF_Msk = 0x20
	// Bit STOPF.
	I2C_ISR_STOPF = 0x20
	// Position of NACKF field.
	I2C_ISR_NACKF_Pos = 0x4
	// Bit mask of NACKF field.
	I2C_ISR_NACKF_Msk = 0x10
	// Bit NACKF.
	I2C_ISR_NACKF = 0x10
	// Position of ADDR field.
	I2C_ISR_ADDR_Pos = 0x3
	// Bit mask of ADDR field.
	I2C_ISR_ADDR_Msk = 0x8
	// Bit ADDR.
	I2C_ISR_ADDR = 0x8
	// Position of RXNE field.
	I2C_ISR_RXNE_Pos = 0x2
	// Bit mask of RXNE field.
	I2C_ISR_RXNE_Msk = 0x4
	// Bit RXNE.
	I2C_ISR_RXNE = 0x4
	// Position of TXIS field.
	I2C_ISR_TXIS_Pos = 0x1
	// Bit mask of TXIS field.
	I2C_ISR_TXIS_Msk = 0x2
	// Bit TXIS.
	I2C_ISR_TXIS = 0x2
	// Position of TXE field.
	I2C_ISR_TXE_Pos = 0x0
	// Bit mask of TXE field.
	I2C_ISR_TXE_Msk = 0x1
	// Bit TXE.
	I2C_ISR_TXE = 0x1

	// ICR: Interrupt clear register
	// Position of ALERTCF field.
	I2C_ICR_ALERTCF_Pos = 0xd
	// Bit mask of ALERTCF field.
	I2C_ICR_ALERTCF_Msk = 0x2000
	// Bit ALERTCF.
	I2C_ICR_ALERTCF = 0x2000
	// Position of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Pos = 0xc
	// Bit mask of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Msk = 0x1000
	// Bit TIMOUTCF.
	I2C_ICR_TIMOUTCF = 0x1000
	// Position of PECCF field.
	I2C_ICR_PECCF_Pos = 0xb
	// Bit mask of PECCF field.
	I2C_ICR_PECCF_Msk = 0x800
	// Bit PECCF.
	I2C_ICR_PECCF = 0x800
	// Position of OVRCF field.
	I2C_ICR_OVRCF_Pos = 0xa
	// Bit mask of OVRCF field.
	I2C_ICR_OVRCF_Msk = 0x400
	// Bit OVRCF.
	I2C_ICR_OVRCF = 0x400
	// Position of ARLOCF field.
	I2C_ICR_ARLOCF_Pos = 0x9
	// Bit mask of ARLOCF field.
	I2C_ICR_ARLOCF_Msk = 0x200
	// Bit ARLOCF.
	I2C_ICR_ARLOCF = 0x200
	// Position of BERRCF field.
	I2C_ICR_BERRCF_Pos = 0x8
	// Bit mask of BERRCF field.
	I2C_ICR_BERRCF_Msk = 0x100
	// Bit BERRCF.
	I2C_ICR_BERRCF = 0x100
	// Position of STOPCF field.
	I2C_ICR_STOPCF_Pos = 0x5
	// Bit mask of STOPCF field.
	I2C_ICR_STOPCF_Msk = 0x20
	// Bit STOPCF.
	I2C_ICR_STOPCF = 0x20
	// Position of NACKCF field.
	I2C_ICR_NACKCF_Pos = 0x4
	// Bit mask of NACKCF field.
	I2C_ICR_NACKCF_Msk = 0x10
	// Bit NACKCF.
	I2C_ICR_NACKCF = 0x10
	// Position of ADDRCF field.
	I2C_ICR_ADDRCF_Pos = 0x3
	// Bit mask of ADDRCF field.
	I2C_ICR_ADDRCF_Msk = 0x8
	// Bit ADDRCF.
	I2C_ICR_ADDRCF = 0x8

	// PECR: PEC register
	// Position of PEC field.
	I2C_PECR_PEC_Pos = 0x0
	// Bit mask of PEC field.
	I2C_PECR_PEC_Msk = 0xff

	// RXDR: Receive data register
	// Position of RXDATA field.
	I2C_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	I2C_RXDR_RXDATA_Msk = 0xff

	// TXDR: Transmit data register
	// Position of TXDATA field.
	I2C_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	I2C_TXDR_TXDATA_Msk = 0xff
)

// Constants for ICACHE: ICache
const (
	// CR: ICACHE control register
	// Position of EN field.
	ICache_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	ICache_CR_EN_Msk = 0x1
	// Bit EN.
	ICache_CR_EN = 0x1
	// Position of CACHEINV field.
	ICache_CR_CACHEINV_Pos = 0x1
	// Bit mask of CACHEINV field.
	ICache_CR_CACHEINV_Msk = 0x2
	// Bit CACHEINV.
	ICache_CR_CACHEINV = 0x2
	// Position of WAYSEL field.
	ICache_CR_WAYSEL_Pos = 0x2
	// Bit mask of WAYSEL field.
	ICache_CR_WAYSEL_Msk = 0x4
	// Bit WAYSEL.
	ICache_CR_WAYSEL = 0x4
	// Position of HITMEN field.
	ICache_CR_HITMEN_Pos = 0x10
	// Bit mask of HITMEN field.
	ICache_CR_HITMEN_Msk = 0x10000
	// Bit HITMEN.
	ICache_CR_HITMEN = 0x10000
	// Position of MISSMEN field.
	ICache_CR_MISSMEN_Pos = 0x11
	// Bit mask of MISSMEN field.
	ICache_CR_MISSMEN_Msk = 0x20000
	// Bit MISSMEN.
	ICache_CR_MISSMEN = 0x20000
	// Position of HITMRST field.
	ICache_CR_HITMRST_Pos = 0x12
	// Bit mask of HITMRST field.
	ICache_CR_HITMRST_Msk = 0x40000
	// Bit HITMRST.
	ICache_CR_HITMRST = 0x40000
	// Position of MISSMRST field.
	ICache_CR_MISSMRST_Pos = 0x13
	// Bit mask of MISSMRST field.
	ICache_CR_MISSMRST_Msk = 0x80000
	// Bit MISSMRST.
	ICache_CR_MISSMRST = 0x80000

	// SR: ICACHE status register
	// Position of BUSYF field.
	ICache_SR_BUSYF_Pos = 0x0
	// Bit mask of BUSYF field.
	ICache_SR_BUSYF_Msk = 0x1
	// Bit BUSYF.
	ICache_SR_BUSYF = 0x1
	// Position of BSYENDF field.
	ICache_SR_BSYENDF_Pos = 0x1
	// Bit mask of BSYENDF field.
	ICache_SR_BSYENDF_Msk = 0x2
	// Bit BSYENDF.
	ICache_SR_BSYENDF = 0x2
	// Position of ERRF field.
	ICache_SR_ERRF_Pos = 0x2
	// Bit mask of ERRF field.
	ICache_SR_ERRF_Msk = 0x4
	// Bit ERRF.
	ICache_SR_ERRF = 0x4

	// IER: ICACHE interrupt enable register
	// Position of BSYENDIE field.
	ICache_IER_BSYENDIE_Pos = 0x1
	// Bit mask of BSYENDIE field.
	ICache_IER_BSYENDIE_Msk = 0x2
	// Bit BSYENDIE.
	ICache_IER_BSYENDIE = 0x2
	// Position of ERRIE field.
	ICache_IER_ERRIE_Pos = 0x2
	// Bit mask of ERRIE field.
	ICache_IER_ERRIE_Msk = 0x4
	// Bit ERRIE.
	ICache_IER_ERRIE = 0x4

	// FCR: ICACHE flag clear register
	// Position of CBSYENDF field.
	ICache_FCR_CBSYENDF_Pos = 0x1
	// Bit mask of CBSYENDF field.
	ICache_FCR_CBSYENDF_Msk = 0x2
	// Bit CBSYENDF.
	ICache_FCR_CBSYENDF = 0x2
	// Position of CERRF field.
	ICache_FCR_CERRF_Pos = 0x2
	// Bit mask of CERRF field.
	ICache_FCR_CERRF_Msk = 0x4
	// Bit CERRF.
	ICache_FCR_CERRF = 0x4

	// HMONR: ICACHE hit monitor register
	// Position of HITMON field.
	ICache_HMONR_HITMON_Pos = 0x0
	// Bit mask of HITMON field.
	ICache_HMONR_HITMON_Msk = 0xffffffff

	// MMONR: ICACHE miss monitor register
	// Position of MISSMON field.
	ICache_MMONR_MISSMON_Pos = 0x0
	// Bit mask of MISSMON field.
	ICache_MMONR_MISSMON_Msk = 0xffff

	// CRR0: ICACHE region configuration register
	// Position of BASEADDR field.
	ICache_CRR_BASEADDR_Pos = 0x0
	// Bit mask of BASEADDR field.
	ICache_CRR_BASEADDR_Msk = 0xff
	// Position of RSIZE field.
	ICache_CRR_RSIZE_Pos = 0x9
	// Bit mask of RSIZE field.
	ICache_CRR_RSIZE_Msk = 0xe00
	// Position of REN field.
	ICache_CRR_REN_Pos = 0xf
	// Bit mask of REN field.
	ICache_CRR_REN_Msk = 0x8000
	// Bit REN.
	ICache_CRR_REN = 0x8000
	// Position of REMAPADDR field.
	ICache_CRR_REMAPADDR_Pos = 0x10
	// Bit mask of REMAPADDR field.
	ICache_CRR_REMAPADDR_Msk = 0x7ff0000
	// Position of MSTSEL field.
	ICache_CRR_MSTSEL_Pos = 0x1c
	// Bit mask of MSTSEL field.
	ICache_CRR_MSTSEL_Msk = 0x10000000
	// Bit MSTSEL.
	ICache_CRR_MSTSEL = 0x10000000
	// Position of HBURST field.
	ICache_CRR_HBURST_Pos = 0x1f
	// Bit mask of HBURST field.
	ICache_CRR_HBURST_Msk = 0x80000000
	// Bit HBURST.
	ICache_CRR_HBURST = 0x80000000
)

// Constants for IWDG: Independent watchdog
const (
	// KR: Key register
	// Position of KEY field.
	IWDG_KR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	IWDG_KR_KEY_Msk = 0xffff

	// PR: Prescaler register
	// Position of PR field.
	IWDG_PR_PR_Pos = 0x0
	// Bit mask of PR field.
	IWDG_PR_PR_Msk = 0x7

	// RLR: Reload register
	// Position of RL field.
	IWDG_RLR_RL_Pos = 0x0
	// Bit mask of RL field.
	IWDG_RLR_RL_Msk = 0xfff

	// SR: Status register
	// Position of WVU field.
	IWDG_SR_WVU_Pos = 0x2
	// Bit mask of WVU field.
	IWDG_SR_WVU_Msk = 0x4
	// Bit WVU.
	IWDG_SR_WVU = 0x4
	// Position of RVU field.
	IWDG_SR_RVU_Pos = 0x1
	// Bit mask of RVU field.
	IWDG_SR_RVU_Msk = 0x2
	// Bit RVU.
	IWDG_SR_RVU = 0x2
	// Position of PVU field.
	IWDG_SR_PVU_Pos = 0x0
	// Bit mask of PVU field.
	IWDG_SR_PVU_Msk = 0x1
	// Bit PVU.
	IWDG_SR_PVU = 0x1

	// WINR: Window register
	// Position of WIN field.
	IWDG_WINR_WIN_Pos = 0x0
	// Bit mask of WIN field.
	IWDG_WINR_WIN_Msk = 0xfff
)

// Constants for LPTIM1: Low power timer
const (
	// ISR: Interrupt and Status Register
	// Position of DOWN field.
	LPTIM_ISR_DOWN_Pos = 0x6
	// Bit mask of DOWN field.
	LPTIM_ISR_DOWN_Msk = 0x40
	// Bit DOWN.
	LPTIM_ISR_DOWN = 0x40
	// Counter direction change up to down
	LPTIM_ISR_DOWN_Set = 0x1
	// Position of UP field.
	LPTIM_ISR_UP_Pos = 0x5
	// Bit mask of UP field.
	LPTIM_ISR_UP_Msk = 0x20
	// Bit UP.
	LPTIM_ISR_UP = 0x20
	// Counter direction change down to up
	LPTIM_ISR_UP_Set = 0x1
	// Position of ARROK field.
	LPTIM_ISR_ARROK_Pos = 0x4
	// Bit mask of ARROK field.
	LPTIM_ISR_ARROK_Msk = 0x10
	// Bit ARROK.
	LPTIM_ISR_ARROK = 0x10
	// Autoreload register update OK
	LPTIM_ISR_ARROK_Set = 0x1
	// Position of CMPOK field.
	LPTIM_ISR_CMPOK_Pos = 0x3
	// Bit mask of CMPOK field.
	LPTIM_ISR_CMPOK_Msk = 0x8
	// Bit CMPOK.
	LPTIM_ISR_CMPOK = 0x8
	// Compare register update OK
	LPTIM_ISR_CMPOK_Set = 0x1
	// Position of EXTTRIG field.
	LPTIM_ISR_EXTTRIG_Pos = 0x2
	// Bit mask of EXTTRIG field.
	LPTIM_ISR_EXTTRIG_Msk = 0x4
	// Bit EXTTRIG.
	LPTIM_ISR_EXTTRIG = 0x4
	// External trigger edge event
	LPTIM_ISR_EXTTRIG_Set = 0x1
	// Position of ARRM field.
	LPTIM_ISR_ARRM_Pos = 0x1
	// Bit mask of ARRM field.
	LPTIM_ISR_ARRM_Msk = 0x2
	// Bit ARRM.
	LPTIM_ISR_ARRM = 0x2
	// Autoreload match
	LPTIM_ISR_ARRM_Set = 0x1
	// Position of CMPM field.
	LPTIM_ISR_CMPM_Pos = 0x0
	// Bit mask of CMPM field.
	LPTIM_ISR_CMPM_Msk = 0x1
	// Bit CMPM.
	LPTIM_ISR_CMPM = 0x1
	// Compare match
	LPTIM_ISR_CMPM_Set = 0x1
	// Position of UE field.
	LPTIM_ISR_UE_Pos = 0x7
	// Bit mask of UE field.
	LPTIM_ISR_UE_Msk = 0x80
	// Bit UE.
	LPTIM_ISR_UE = 0x80
	// LPTIM update event occurred
	LPTIM_ISR_UE_Set = 0x1
	// Position of REPOK field.
	LPTIM_ISR_REPOK_Pos = 0x8
	// Bit mask of REPOK field.
	LPTIM_ISR_REPOK_Msk = 0x100
	// Bit REPOK.
	LPTIM_ISR_REPOK = 0x100
	// Repetition register update OK
	LPTIM_ISR_REPOK_Set = 0x1

	// ICR: Interrupt Clear Register
	// Position of DOWNCF field.
	LPTIM_ICR_DOWNCF_Pos = 0x6
	// Bit mask of DOWNCF field.
	LPTIM_ICR_DOWNCF_Msk = 0x40
	// Bit DOWNCF.
	LPTIM_ICR_DOWNCF = 0x40
	// Direction change to down Clear Flag
	LPTIM_ICR_DOWNCF_Clear = 0x1
	// Position of UPCF field.
	LPTIM_ICR_UPCF_Pos = 0x5
	// Bit mask of UPCF field.
	LPTIM_ICR_UPCF_Msk = 0x20
	// Bit UPCF.
	LPTIM_ICR_UPCF = 0x20
	// Direction change to up Clear Flag
	LPTIM_ICR_UPCF_Clear = 0x1
	// Position of ARROKCF field.
	LPTIM_ICR_ARROKCF_Pos = 0x4
	// Bit mask of ARROKCF field.
	LPTIM_ICR_ARROKCF_Msk = 0x10
	// Bit ARROKCF.
	LPTIM_ICR_ARROKCF = 0x10
	// Autoreload register update OK Clear Flag
	LPTIM_ICR_ARROKCF_Clear = 0x1
	// Position of CMPOKCF field.
	LPTIM_ICR_CMPOKCF_Pos = 0x3
	// Bit mask of CMPOKCF field.
	LPTIM_ICR_CMPOKCF_Msk = 0x8
	// Bit CMPOKCF.
	LPTIM_ICR_CMPOKCF = 0x8
	// Compare register update OK Clear Flag
	LPTIM_ICR_CMPOKCF_Clear = 0x1
	// Position of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF_Pos = 0x2
	// Bit mask of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF_Msk = 0x4
	// Bit EXTTRIGCF.
	LPTIM_ICR_EXTTRIGCF = 0x4
	// External trigger valid edge Clear Flag
	LPTIM_ICR_EXTTRIGCF_Clear = 0x1
	// Position of ARRMCF field.
	LPTIM_ICR_ARRMCF_Pos = 0x1
	// Bit mask of ARRMCF field.
	LPTIM_ICR_ARRMCF_Msk = 0x2
	// Bit ARRMCF.
	LPTIM_ICR_ARRMCF = 0x2
	// Autoreload match Clear Flag
	LPTIM_ICR_ARRMCF_Clear = 0x1
	// Position of CMPMCF field.
	LPTIM_ICR_CMPMCF_Pos = 0x0
	// Bit mask of CMPMCF field.
	LPTIM_ICR_CMPMCF_Msk = 0x1
	// Bit CMPMCF.
	LPTIM_ICR_CMPMCF = 0x1
	// Compare match Clear Flag
	LPTIM_ICR_CMPMCF_Clear = 0x1
	// Position of UECF field.
	LPTIM_ICR_UECF_Pos = 0x7
	// Bit mask of UECF field.
	LPTIM_ICR_UECF_Msk = 0x80
	// Bit UECF.
	LPTIM_ICR_UECF = 0x80
	// Clear update event flag
	LPTIM_ICR_UECF_Clear = 0x1
	// Position of REPOKCF field.
	LPTIM_ICR_REPOKCF_Pos = 0x8
	// Bit mask of REPOKCF field.
	LPTIM_ICR_REPOKCF_Msk = 0x100
	// Bit REPOKCF.
	LPTIM_ICR_REPOKCF = 0x100
	// Clear REPOK flag
	LPTIM_ICR_REPOKCF_Clear = 0x1

	// IER: Interrupt Enable Register
	// Position of DOWNIE field.
	LPTIM_IER_DOWNIE_Pos = 0x6
	// Bit mask of DOWNIE field.
	LPTIM_IER_DOWNIE_Msk = 0x40
	// Bit DOWNIE.
	LPTIM_IER_DOWNIE = 0x40
	// DOWN interrupt disabled
	LPTIM_IER_DOWNIE_Disabled = 0x0
	// DOWN interrupt enabled
	LPTIM_IER_DOWNIE_Enabled = 0x1
	// Position of UPIE field.
	LPTIM_IER_UPIE_Pos = 0x5
	// Bit mask of UPIE field.
	LPTIM_IER_UPIE_Msk = 0x20
	// Bit UPIE.
	LPTIM_IER_UPIE = 0x20
	// UP interrupt disabled
	LPTIM_IER_UPIE_Disabled = 0x0
	// UP interrupt enabled
	LPTIM_IER_UPIE_Enabled = 0x1
	// Position of ARROKIE field.
	LPTIM_IER_ARROKIE_Pos = 0x4
	// Bit mask of ARROKIE field.
	LPTIM_IER_ARROKIE_Msk = 0x10
	// Bit ARROKIE.
	LPTIM_IER_ARROKIE = 0x10
	// ARROK interrupt disabled
	LPTIM_IER_ARROKIE_Disabled = 0x0
	// ARROK interrupt enabled
	LPTIM_IER_ARROKIE_Enabled = 0x1
	// Position of CMPOKIE field.
	LPTIM_IER_CMPOKIE_Pos = 0x3
	// Bit mask of CMPOKIE field.
	LPTIM_IER_CMPOKIE_Msk = 0x8
	// Bit CMPOKIE.
	LPTIM_IER_CMPOKIE = 0x8
	// CMPOK interrupt disabled
	LPTIM_IER_CMPOKIE_Disabled = 0x0
	// CMPOK interrupt enabled
	LPTIM_IER_CMPOKIE_Enabled = 0x1
	// Position of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE_Pos = 0x2
	// Bit mask of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE_Msk = 0x4
	// Bit EXTTRIGIE.
	LPTIM_IER_EXTTRIGIE = 0x4
	// EXTTRIG interrupt disabled
	LPTIM_IER_EXTTRIGIE_Disabled = 0x0
	// EXTTRIG interrupt enabled
	LPTIM_IER_EXTTRIGIE_Enabled = 0x1
	// Position of ARRMIE field.
	LPTIM_IER_ARRMIE_Pos = 0x1
	// Bit mask of ARRMIE field.
	LPTIM_IER_ARRMIE_Msk = 0x2
	// Bit ARRMIE.
	LPTIM_IER_ARRMIE = 0x2
	// ARRM interrupt disabled
	LPTIM_IER_ARRMIE_Disabled = 0x0
	// ARRM interrupt enabled
	LPTIM_IER_ARRMIE_Enabled = 0x1
	// Position of CMPMIE field.
	LPTIM_IER_CMPMIE_Pos = 0x0
	// Bit mask of CMPMIE field.
	LPTIM_IER_CMPMIE_Msk = 0x1
	// Bit CMPMIE.
	LPTIM_IER_CMPMIE = 0x1
	// CMPM interrupt disabled
	LPTIM_IER_CMPMIE_Disabled = 0x0
	// CMPM interrupt enabled
	LPTIM_IER_CMPMIE_Enabled = 0x1
	// Position of UEIE field.
	LPTIM_IER_UEIE_Pos = 0x7
	// Bit mask of UEIE field.
	LPTIM_IER_UEIE_Msk = 0x80
	// Bit UEIE.
	LPTIM_IER_UEIE = 0x80
	// Update event interrupt disabled
	LPTIM_IER_UEIE_Disabled = 0x0
	// Update event interrupt enabled
	LPTIM_IER_UEIE_Enabled = 0x1
	// Position of REPOKIE field.
	LPTIM_IER_REPOKIE_Pos = 0x8
	// Bit mask of REPOKIE field.
	LPTIM_IER_REPOKIE_Msk = 0x100
	// Bit REPOKIE.
	LPTIM_IER_REPOKIE = 0x100
	// Repetition register update OK interrupt disabled
	LPTIM_IER_REPOKIE_Disabled = 0x0
	// Repetition register update OK interrupt enabled
	LPTIM_IER_REPOKIE_Enabled = 0x1

	// CFGR: Configuration Register
	// Position of ENC field.
	LPTIM_CFGR_ENC_Pos = 0x18
	// Bit mask of ENC field.
	LPTIM_CFGR_ENC_Msk = 0x1000000
	// Bit ENC.
	LPTIM_CFGR_ENC = 0x1000000
	// Encoder mode disabled
	LPTIM_CFGR_ENC_Disabled = 0x0
	// Encoder mode enabled
	LPTIM_CFGR_ENC_Enabled = 0x1
	// Position of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Pos = 0x17
	// Bit mask of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Msk = 0x800000
	// Bit COUNTMODE.
	LPTIM_CFGR_COUNTMODE = 0x800000
	// The counter is incremented following each internal clock pulse
	LPTIM_CFGR_COUNTMODE_Internal = 0x0
	// The counter is incremented following each valid clock pulse on the LPTIM external Input1
	LPTIM_CFGR_COUNTMODE_External = 0x1
	// Position of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Pos = 0x16
	// Bit mask of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Msk = 0x400000
	// Bit PRELOAD.
	LPTIM_CFGR_PRELOAD = 0x400000
	// Registers are updated after each APB bus write access
	LPTIM_CFGR_PRELOAD_Immediate = 0x0
	// Registers are updated at the end of the current LPTIM period
	LPTIM_CFGR_PRELOAD_EndOfPeriod = 0x1
	// Position of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Pos = 0x15
	// Bit mask of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Msk = 0x200000
	// Bit WAVPOL.
	LPTIM_CFGR_WAVPOL = 0x200000
	// The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers
	LPTIM_CFGR_WAVPOL_Positive = 0x0
	// The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers
	LPTIM_CFGR_WAVPOL_Negative = 0x1
	// Position of WAVE field.
	LPTIM_CFGR_WAVE_Pos = 0x14
	// Bit mask of WAVE field.
	LPTIM_CFGR_WAVE_Msk = 0x100000
	// Bit WAVE.
	LPTIM_CFGR_WAVE = 0x100000
	// Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)
	LPTIM_CFGR_WAVE_Inactive = 0x0
	// Activate the Set-once mode
	LPTIM_CFGR_WAVE_Active = 0x1
	// Position of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Pos = 0x13
	// Bit mask of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Msk = 0x80000
	// Bit TIMOUT.
	LPTIM_CFGR_TIMOUT = 0x80000
	// A trigger event arriving when the timer is already started will be ignored
	LPTIM_CFGR_TIMOUT_Disabled = 0x0
	// A trigger event arriving when the timer is already started will reset and restart the counter
	LPTIM_CFGR_TIMOUT_Enabled = 0x1
	// Position of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Pos = 0x11
	// Bit mask of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Msk = 0x60000
	// Software trigger (counting start is initiated by software)
	LPTIM_CFGR_TRIGEN_SW = 0x0
	// Rising edge is the active edge
	LPTIM_CFGR_TRIGEN_RisingEdge = 0x1
	// Falling edge is the active edge
	LPTIM_CFGR_TRIGEN_FallingEdge = 0x2
	// Both edges are active edges
	LPTIM_CFGR_TRIGEN_BothEdges = 0x3
	// Position of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Pos = 0xd
	// Bit mask of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Msk = 0xe000
	// lptim_ext_trig0
	LPTIM_CFGR_TRIGSEL_Trig0 = 0x0
	// lptim_ext_trig1
	LPTIM_CFGR_TRIGSEL_Trig1 = 0x1
	// lptim_ext_trig2
	LPTIM_CFGR_TRIGSEL_Trig2 = 0x2
	// lptim_ext_trig3
	LPTIM_CFGR_TRIGSEL_Trig3 = 0x3
	// lptim_ext_trig4
	LPTIM_CFGR_TRIGSEL_Trig4 = 0x4
	// lptim_ext_trig5
	LPTIM_CFGR_TRIGSEL_Trig5 = 0x5
	// lptim_ext_trig6
	LPTIM_CFGR_TRIGSEL_Trig6 = 0x6
	// lptim_ext_trig7
	LPTIM_CFGR_TRIGSEL_Trig7 = 0x7
	// Position of PRESC field.
	LPTIM_CFGR_PRESC_Pos = 0x9
	// Bit mask of PRESC field.
	LPTIM_CFGR_PRESC_Msk = 0xe00
	// /1
	LPTIM_CFGR_PRESC_Div1 = 0x0
	// /2
	LPTIM_CFGR_PRESC_Div2 = 0x1
	// /4
	LPTIM_CFGR_PRESC_Div4 = 0x2
	// /8
	LPTIM_CFGR_PRESC_Div8 = 0x3
	// /16
	LPTIM_CFGR_PRESC_Div16 = 0x4
	// /32
	LPTIM_CFGR_PRESC_Div32 = 0x5
	// /64
	LPTIM_CFGR_PRESC_Div64 = 0x6
	// /128
	LPTIM_CFGR_PRESC_Div128 = 0x7
	// Position of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Pos = 0x6
	// Bit mask of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Msk = 0xc0
	// Any trigger active level change is considered as a valid trigger
	LPTIM_CFGR_TRGFLT_Immediate = 0x0
	// Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger
	LPTIM_CFGR_TRGFLT_Clocks2 = 0x1
	// Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger
	LPTIM_CFGR_TRGFLT_Clocks4 = 0x2
	// Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger
	LPTIM_CFGR_TRGFLT_Clocks8 = 0x3
	// Position of CKFLT field.
	LPTIM_CFGR_CKFLT_Pos = 0x3
	// Bit mask of CKFLT field.
	LPTIM_CFGR_CKFLT_Msk = 0x18
	// Any external clock signal level change is considered as a valid transition
	LPTIM_CFGR_CKFLT_Immediate = 0x0
	// External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition
	LPTIM_CFGR_CKFLT_Clocks2 = 0x1
	// External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition
	LPTIM_CFGR_CKFLT_Clocks4 = 0x2
	// External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition
	LPTIM_CFGR_CKFLT_Clocks8 = 0x3
	// Position of CKPOL field.
	LPTIM_CFGR_CKPOL_Pos = 0x1
	// Bit mask of CKPOL field.
	LPTIM_CFGR_CKPOL_Msk = 0x6
	// The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.
	LPTIM_CFGR_CKPOL_RisingEdge = 0x0
	// The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.
	LPTIM_CFGR_CKPOL_FallingEdge = 0x1
	// Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active.
	LPTIM_CFGR_CKPOL_BothEdges = 0x2
	// Position of CKSEL field.
	LPTIM_CFGR_CKSEL_Pos = 0x0
	// Bit mask of CKSEL field.
	LPTIM_CFGR_CKSEL_Msk = 0x1
	// Bit CKSEL.
	LPTIM_CFGR_CKSEL = 0x1
	// LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
	LPTIM_CFGR_CKSEL_Internal = 0x0
	// LPTIM is clocked by an external clock source through the LPTIM external Input1
	LPTIM_CFGR_CKSEL_External = 0x1

	// CR: Control Register
	// Position of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Pos = 0x2
	// Bit mask of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Msk = 0x4
	// Bit CNTSTRT.
	LPTIM_CR_CNTSTRT = 0x4
	// Timer start in Continuous mode
	LPTIM_CR_CNTSTRT_Start = 0x1
	// Position of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Pos = 0x1
	// Bit mask of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Msk = 0x2
	// Bit SNGSTRT.
	LPTIM_CR_SNGSTRT = 0x2
	// LPTIM start in Single mode
	LPTIM_CR_SNGSTRT_Start = 0x1
	// Position of ENABLE field.
	LPTIM_CR_ENABLE_Pos = 0x0
	// Bit mask of ENABLE field.
	LPTIM_CR_ENABLE_Msk = 0x1
	// Bit ENABLE.
	LPTIM_CR_ENABLE = 0x1
	// LPTIM is disabled
	LPTIM_CR_ENABLE_Disabled = 0x0
	// LPTIM is enabled
	LPTIM_CR_ENABLE_Enabled = 0x1
	// Position of COUNTRST field.
	LPTIM_CR_COUNTRST_Pos = 0x4
	// Bit mask of COUNTRST field.
	LPTIM_CR_COUNTRST_Msk = 0x10
	// Bit COUNTRST.
	LPTIM_CR_COUNTRST = 0x10
	// Triggering of reset is possible
	LPTIM_CR_COUNTRST_Idle = 0x0
	// Reset in progress, do not write 1 to this field
	LPTIM_CR_COUNTRST_Busy = 0x1
	// Trigger synchronous reset of CNT (3 LPTimer core clock cycles)
	LPTIM_CR_COUNTRST_Reset = 0x1
	// Position of RSTARE field.
	LPTIM_CR_RSTARE_Pos = 0x3
	// Bit mask of RSTARE field.
	LPTIM_CR_RSTARE_Msk = 0x8
	// Bit RSTARE.
	LPTIM_CR_RSTARE = 0x8
	// CNT Register reads do not trigger reset
	LPTIM_CR_RSTARE_Disabled = 0x0
	// CNT Register reads trigger reset of LPTIM
	LPTIM_CR_RSTARE_Enabled = 0x1

	// CMP: Compare Register
	// Position of CMP field.
	LPTIM_CMP_CMP_Pos = 0x0
	// Bit mask of CMP field.
	LPTIM_CMP_CMP_Msk = 0xffff

	// ARR: Autoreload Register
	// Position of ARR field.
	LPTIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	LPTIM_ARR_ARR_Msk = 0xffff

	// CNT: Counter Register
	// Position of CNT field.
	LPTIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	LPTIM_CNT_CNT_Msk = 0xffff

	// OR: LPTIM option register
	// Position of OR_0 field.
	LPTIM_OR_OR_0_Pos = 0x0
	// Bit mask of OR_0 field.
	LPTIM_OR_OR_0_Msk = 0x1
	// Bit OR_0.
	LPTIM_OR_OR_0 = 0x1
	// Position of OR_1 field.
	LPTIM_OR_OR_1_Pos = 0x1
	// Bit mask of OR_1 field.
	LPTIM_OR_OR_1_Msk = 0x2
	// Bit OR_1.
	LPTIM_OR_OR_1 = 0x2

	// RCR: LPTIM repetition register
	// Position of REP field.
	LPTIM_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	LPTIM_RCR_REP_Msk = 0xff
)

// Constants for USART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	// Position of M1 field.
	USART_CR1_M1_Pos = 0x1c
	// Bit mask of M1 field.
	USART_CR1_M1_Msk = 0x10000000
	// Bit M1.
	USART_CR1_M1 = 0x10000000
	// Use M0 to set the data bits
	USART_CR1_M1_M0 = 0x0
	// 1 start bit, 7 data bits, n stop bits
	USART_CR1_M1_Bit7 = 0x1
	// Position of EOBIE field.
	USART_CR1_EOBIE_Pos = 0x1b
	// Bit mask of EOBIE field.
	USART_CR1_EOBIE_Msk = 0x8000000
	// Bit EOBIE.
	USART_CR1_EOBIE = 0x8000000
	// Interrupt is inhibited
	USART_CR1_EOBIE_Disabled = 0x0
	// A USART interrupt is generated when the EOBF flag is set in the ISR register
	USART_CR1_EOBIE_Enabled = 0x1
	// Position of RTOIE field.
	USART_CR1_RTOIE_Pos = 0x1a
	// Bit mask of RTOIE field.
	USART_CR1_RTOIE_Msk = 0x4000000
	// Bit RTOIE.
	USART_CR1_RTOIE = 0x4000000
	// Interrupt is inhibited
	USART_CR1_RTOIE_Disabled = 0x0
	// An USART interrupt is generated when the RTOF bit is set in the ISR register
	USART_CR1_RTOIE_Enabled = 0x1
	// Position of DEAT field.
	USART_CR1_DEAT_Pos = 0x15
	// Bit mask of DEAT field.
	USART_CR1_DEAT_Msk = 0x3e00000
	// Position of DEDT field.
	USART_CR1_DEDT_Pos = 0x10
	// Bit mask of DEDT field.
	USART_CR1_DEDT_Msk = 0x1f0000
	// Position of OVER8 field.
	USART_CR1_OVER8_Pos = 0xf
	// Bit mask of OVER8 field.
	USART_CR1_OVER8_Msk = 0x8000
	// Bit OVER8.
	USART_CR1_OVER8 = 0x8000
	// Oversampling by 16
	USART_CR1_OVER8_Oversampling16 = 0x0
	// Oversampling by 8
	USART_CR1_OVER8_Oversampling8 = 0x1
	// Position of CMIE field.
	USART_CR1_CMIE_Pos = 0xe
	// Bit mask of CMIE field.
	USART_CR1_CMIE_Msk = 0x4000
	// Bit CMIE.
	USART_CR1_CMIE = 0x4000
	// Interrupt is disabled
	USART_CR1_CMIE_Disabled = 0x0
	// Interrupt is generated when the CMF bit is set in the ISR register
	USART_CR1_CMIE_Enabled = 0x1
	// Position of MME field.
	USART_CR1_MME_Pos = 0xd
	// Bit mask of MME field.
	USART_CR1_MME_Msk = 0x2000
	// Bit MME.
	USART_CR1_MME = 0x2000
	// Receiver in active mode permanently
	USART_CR1_MME_Disabled = 0x0
	// Receiver can switch between mute mode and active mode
	USART_CR1_MME_Enabled = 0x1
	// Position of M0 field.
	USART_CR1_M0_Pos = 0xc
	// Bit mask of M0 field.
	USART_CR1_M0_Msk = 0x1000
	// Bit M0.
	USART_CR1_M0 = 0x1000
	// 1 start bit, 8 data bits, n stop bits
	USART_CR1_M0_Bit8 = 0x0
	// 1 start bit, 9 data bits, n stop bits
	USART_CR1_M0_Bit9 = 0x1
	// Position of WAKE field.
	USART_CR1_WAKE_Pos = 0xb
	// Bit mask of WAKE field.
	USART_CR1_WAKE_Msk = 0x800
	// Bit WAKE.
	USART_CR1_WAKE = 0x800
	// Idle line
	USART_CR1_WAKE_Idle = 0x0
	// Address mask
	USART_CR1_WAKE_Address = 0x1
	// Position of PCE field.
	USART_CR1_PCE_Pos = 0xa
	// Bit mask of PCE field.
	USART_CR1_PCE_Msk = 0x400
	// Bit PCE.
	USART_CR1_PCE = 0x400
	// Parity control disabled
	USART_CR1_PCE_Disabled = 0x0
	// Parity control enabled
	USART_CR1_PCE_Enabled = 0x1
	// Position of PS field.
	USART_CR1_PS_Pos = 0x9
	// Bit mask of PS field.
	USART_CR1_PS_Msk = 0x200
	// Bit PS.
	USART_CR1_PS = 0x200
	// Even parity
	USART_CR1_PS_Even = 0x0
	// Odd parity
	USART_CR1_PS_Odd = 0x1
	// Position of PEIE field.
	USART_CR1_PEIE_Pos = 0x8
	// Bit mask of PEIE field.
	USART_CR1_PEIE_Msk = 0x100
	// Bit PEIE.
	USART_CR1_PEIE = 0x100
	// Interrupt is disabled
	USART_CR1_PEIE_Disabled = 0x0
	// Interrupt is generated whenever PE=1 in the ISR register
	USART_CR1_PEIE_Enabled = 0x1
	// Position of TXEIE field.
	USART_CR1_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	USART_CR1_TXEIE_Msk = 0x80
	// Bit TXEIE.
	USART_CR1_TXEIE = 0x80
	// Interrupt is disabled
	USART_CR1_TXEIE_Disabled = 0x0
	// Interrupt is generated whenever TXE=1 in the ISR register
	USART_CR1_TXEIE_Enabled = 0x1
	// Position of TCIE field.
	USART_CR1_TCIE_Pos = 0x6
	// Bit mask of TCIE field.
	USART_CR1_TCIE_Msk = 0x40
	// Bit TCIE.
	USART_CR1_TCIE = 0x40
	// Interrupt is disabled
	USART_CR1_TCIE_Disabled = 0x0
	// Interrupt is generated whenever TC=1 in the ISR register
	USART_CR1_TCIE_Enabled = 0x1
	// Position of RXNEIE field.
	USART_CR1_RXNEIE_Pos = 0x5
	// Bit mask of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20
	// Bit RXNEIE.
	USART_CR1_RXNEIE = 0x20
	// Interrupt is disabled
	USART_CR1_RXNEIE_Disabled = 0x0
	// Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
	USART_CR1_RXNEIE_Enabled = 0x1
	// Position of IDLEIE field.
	USART_CR1_IDLEIE_Pos = 0x4
	// Bit mask of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10
	// Bit IDLEIE.
	USART_CR1_IDLEIE = 0x10
	// Interrupt is disabled
	USART_CR1_IDLEIE_Disabled = 0x0
	// Interrupt is generated whenever IDLE=1 in the ISR register
	USART_CR1_IDLEIE_Enabled = 0x1
	// Position of TE field.
	USART_CR1_TE_Pos = 0x3
	// Bit mask of TE field.
	USART_CR1_TE_Msk = 0x8
	// Bit TE.
	USART_CR1_TE = 0x8
	// Transmitter is disabled
	USART_CR1_TE_Disabled = 0x0
	// Transmitter is enabled
	USART_CR1_TE_Enabled = 0x1
	// Position of RE field.
	USART_CR1_RE_Pos = 0x2
	// Bit mask of RE field.
	USART_CR1_RE_Msk = 0x4
	// Bit RE.
	USART_CR1_RE = 0x4
	// Receiver is disabled
	USART_CR1_RE_Disabled = 0x0
	// Receiver is enabled
	USART_CR1_RE_Enabled = 0x1
	// Position of UESM field.
	USART_CR1_UESM_Pos = 0x1
	// Bit mask of UESM field.
	USART_CR1_UESM_Msk = 0x2
	// Bit UESM.
	USART_CR1_UESM = 0x2
	// USART not able to wake up the MCU from Stop mode
	USART_CR1_UESM_Disabled = 0x0
	// USART able to wake up the MCU from Stop mode
	USART_CR1_UESM_Enabled = 0x1
	// Position of UE field.
	USART_CR1_UE_Pos = 0x0
	// Bit mask of UE field.
	USART_CR1_UE_Msk = 0x1
	// Bit UE.
	USART_CR1_UE = 0x1
	// UART is disabled
	USART_CR1_UE_Disabled = 0x0
	// UART is enabled
	USART_CR1_UE_Enabled = 0x1
	// Position of FIFOEN field.
	USART_CR1_FIFOEN_Pos = 0x1d
	// Bit mask of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000
	// Bit FIFOEN.
	USART_CR1_FIFOEN = 0x20000000
	// FIFO mode is disabled
	USART_CR1_FIFOEN_Disabled = 0x0
	// FIFO mode is enabled
	USART_CR1_FIFOEN_Enabled = 0x1
	// Position of TXFEIE field.
	USART_CR1_TXFEIE_Pos = 0x1e
	// Bit mask of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000
	// Bit TXFEIE.
	USART_CR1_TXFEIE = 0x40000000
	// Interrupt inhibited
	USART_CR1_TXFEIE_Disabled = 0x0
	// USART interrupt generated when TXFE = 1 in the USART_ISR register
	USART_CR1_TXFEIE_Enabled = 0x1
	// Position of RXFFIE field.
	USART_CR1_RXFFIE_Pos = 0x1f
	// Bit mask of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000
	// Bit RXFFIE.
	USART_CR1_RXFFIE = 0x80000000
	// Interrupt inhibited
	USART_CR1_RXFFIE_Disabled = 0x0
	// USART interrupt generated when RXFF = 1 in the USART_ISR register
	USART_CR1_RXFFIE_Enabled = 0x1

	// CR2: Control register 2
	// Position of ADD field.
	USART_CR2_ADD_Pos = 0x18
	// Bit mask of ADD field.
	USART_CR2_ADD_Msk = 0xff000000
	// Position of RTOEN field.
	USART_CR2_RTOEN_Pos = 0x17
	// Bit mask of RTOEN field.
	USART_CR2_RTOEN_Msk = 0x800000
	// Bit RTOEN.
	USART_CR2_RTOEN = 0x800000
	// Receiver timeout feature disabled
	USART_CR2_RTOEN_Disabled = 0x0
	// Receiver timeout feature enabled
	USART_CR2_RTOEN_Enabled = 0x1
	// Position of ABRMOD field.
	USART_CR2_ABRMOD_Pos = 0x15
	// Bit mask of ABRMOD field.
	USART_CR2_ABRMOD_Msk = 0x600000
	// Measurement of the start bit is used to detect the baud rate
	USART_CR2_ABRMOD_Start = 0x0
	// Falling edge to falling edge measurement
	USART_CR2_ABRMOD_Edge = 0x1
	// 0x7F frame detection
	USART_CR2_ABRMOD_Frame7F = 0x2
	// 0x55 frame detection
	USART_CR2_ABRMOD_Frame55 = 0x3
	// Position of ABREN field.
	USART_CR2_ABREN_Pos = 0x14
	// Bit mask of ABREN field.
	USART_CR2_ABREN_Msk = 0x100000
	// Bit ABREN.
	USART_CR2_ABREN = 0x100000
	// Auto baud rate detection is disabled
	USART_CR2_ABREN_Disabled = 0x0
	// Auto baud rate detection is enabled
	USART_CR2_ABREN_Enabled = 0x1
	// Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Pos = 0x13
	// Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000
	// Bit MSBFIRST.
	USART_CR2_MSBFIRST = 0x80000
	// data is transmitted/received with data bit 0 first, following the start bit
	USART_CR2_MSBFIRST_LSB = 0x0
	// data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
	USART_CR2_MSBFIRST_MSB = 0x1
	// Position of DATAINV field.
	USART_CR2_DATAINV_Pos = 0x12
	// Bit mask of DATAINV field.
	USART_CR2_DATAINV_Msk = 0x40000
	// Bit DATAINV.
	USART_CR2_DATAINV = 0x40000
	// Logical data from the data register are send/received in positive/direct logic
	USART_CR2_DATAINV_Positive = 0x0
	// Logical data from the data register are send/received in negative/inverse logic
	USART_CR2_DATAINV_Negative = 0x1
	// Position of TXINV field.
	USART_CR2_TXINV_Pos = 0x11
	// Bit mask of TXINV field.
	USART_CR2_TXINV_Msk = 0x20000
	// Bit TXINV.
	USART_CR2_TXINV = 0x20000
	// TX pin signal works using the standard logic levels
	USART_CR2_TXINV_Standard = 0x0
	// TX pin signal values are inverted
	USART_CR2_TXINV_Inverted = 0x1
	// Position of RXINV field.
	USART_CR2_RXINV_Pos = 0x10
	// Bit mask of RXINV field.
	USART_CR2_RXINV_Msk = 0x10000
	// Bit RXINV.
	USART_CR2_RXINV = 0x10000
	// RX pin signal works using the standard logic levels
	USART_CR2_RXINV_Standard = 0x0
	// RX pin signal values are inverted
	USART_CR2_RXINV_Inverted = 0x1
	// Position of SWAP field.
	USART_CR2_SWAP_Pos = 0xf
	// Bit mask of SWAP field.
	USART_CR2_SWAP_Msk = 0x8000
	// Bit SWAP.
	USART_CR2_SWAP = 0x8000
	// TX/RX pins are used as defined in standard pinout
	USART_CR2_SWAP_Standard = 0x0
	// The TX and RX pins functions are swapped
	USART_CR2_SWAP_Swapped = 0x1
	// Position of LINEN field.
	USART_CR2_LINEN_Pos = 0xe
	// Bit mask of LINEN field.
	USART_CR2_LINEN_Msk = 0x4000
	// Bit LINEN.
	USART_CR2_LINEN = 0x4000
	// LIN mode disabled
	USART_CR2_LINEN_Disabled = 0x0
	// LIN mode enabled
	USART_CR2_LINEN_Enabled = 0x1
	// Position of STOP field.
	USART_CR2_STOP_Pos = 0xc
	// Bit mask of STOP field.
	USART_CR2_STOP_Msk = 0x3000
	// 1 stop bit
	USART_CR2_STOP_Stop1 = 0x0
	// 0.5 stop bit
	USART_CR2_STOP_Stop0p5 = 0x1
	// 2 stop bit
	USART_CR2_STOP_Stop2 = 0x2
	// 1.5 stop bit
	USART_CR2_STOP_Stop1p5 = 0x3
	// Position of CLKEN field.
	USART_CR2_CLKEN_Pos = 0xb
	// Bit mask of CLKEN field.
	USART_CR2_CLKEN_Msk = 0x800
	// Bit CLKEN.
	USART_CR2_CLKEN = 0x800
	// CK pin disabled
	USART_CR2_CLKEN_Disabled = 0x0
	// CK pin enabled
	USART_CR2_CLKEN_Enabled = 0x1
	// Position of CPOL field.
	USART_CR2_CPOL_Pos = 0xa
	// Bit mask of CPOL field.
	USART_CR2_CPOL_Msk = 0x400
	// Bit CPOL.
	USART_CR2_CPOL = 0x400
	// Steady low value on CK pin outside transmission window
	USART_CR2_CPOL_Low = 0x0
	// Steady high value on CK pin outside transmission window
	USART_CR2_CPOL_High = 0x1
	// Position of CPHA field.
	USART_CR2_CPHA_Pos = 0x9
	// Bit mask of CPHA field.
	USART_CR2_CPHA_Msk = 0x200
	// Bit CPHA.
	USART_CR2_CPHA = 0x200
	// The first clock transition is the first data capture edge
	USART_CR2_CPHA_First = 0x0
	// The second clock transition is the first data capture edge
	USART_CR2_CPHA_Second = 0x1
	// Position of LBCL field.
	USART_CR2_LBCL_Pos = 0x8
	// Bit mask of LBCL field.
	USART_CR2_LBCL_Msk = 0x100
	// Bit LBCL.
	USART_CR2_LBCL = 0x100
	// The clock pulse of the last data bit is not output to the CK pin
	USART_CR2_LBCL_NotOutput = 0x0
	// The clock pulse of the last data bit is output to the CK pin
	USART_CR2_LBCL_Output = 0x1
	// Position of LBDIE field.
	USART_CR2_LBDIE_Pos = 0x6
	// Bit mask of LBDIE field.
	USART_CR2_LBDIE_Msk = 0x40
	// Bit LBDIE.
	USART_CR2_LBDIE = 0x40
	// Interrupt is inhibited
	USART_CR2_LBDIE_Disabled = 0x0
	// An interrupt is generated whenever LBDF=1 in the ISR register
	USART_CR2_LBDIE_Enabled = 0x1
	// Position of LBDL field.
	USART_CR2_LBDL_Pos = 0x5
	// Bit mask of LBDL field.
	USART_CR2_LBDL_Msk = 0x20
	// Bit LBDL.
	USART_CR2_LBDL = 0x20
	// 10-bit break detection
	USART_CR2_LBDL_Bit10 = 0x0
	// 11-bit break detection
	USART_CR2_LBDL_Bit11 = 0x1
	// Position of ADDM7 field.
	USART_CR2_ADDM7_Pos = 0x4
	// Bit mask of ADDM7 field.
	USART_CR2_ADDM7_Msk = 0x10
	// Bit ADDM7.
	USART_CR2_ADDM7 = 0x10
	// 4-bit address detection
	USART_CR2_ADDM7_Bit4 = 0x0
	// 7-bit address detection
	USART_CR2_ADDM7_Bit7 = 0x1
	// Position of SLVEN field.
	USART_CR2_SLVEN_Pos = 0x0
	// Bit mask of SLVEN field.
	USART_CR2_SLVEN_Msk = 0x1
	// Bit SLVEN.
	USART_CR2_SLVEN = 0x1
	// Slave mode disabled
	USART_CR2_SLVEN_Disabled = 0x0
	// Slave mode enabled
	USART_CR2_SLVEN_Enabled = 0x1
	// Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Pos = 0x3
	// Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk = 0x8
	// Bit DIS_NSS.
	USART_CR2_DIS_NSS = 0x8
	// SPI slave selection depends on NSS input pin
	USART_CR2_DIS_NSS_Disabled = 0x0
	// SPI slave is always selected and NSS input pin is ignored
	USART_CR2_DIS_NSS_Enabled = 0x1

	// CR3: Control register 3
	// Position of WUFIE field.
	USART_CR3_WUFIE_Pos = 0x16
	// Bit mask of WUFIE field.
	USART_CR3_WUFIE_Msk = 0x400000
	// Bit WUFIE.
	USART_CR3_WUFIE = 0x400000
	// Interrupt is inhibited
	USART_CR3_WUFIE_Disabled = 0x0
	// An USART interrupt is generated whenever WUF=1 in the ISR register
	USART_CR3_WUFIE_Enabled = 0x1
	// Position of WUS field.
	USART_CR3_WUS_Pos = 0x14
	// Bit mask of WUS field.
	USART_CR3_WUS_Msk = 0x300000
	// WUF active on address match
	USART_CR3_WUS_Address = 0x0
	// WuF active on Start bit detection
	USART_CR3_WUS_Start = 0x2
	// WUF active on RXNE
	USART_CR3_WUS_RXNE = 0x3
	// Position of SCARCNT field.
	USART_CR3_SCARCNT_Pos = 0x11
	// Bit mask of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000
	// Position of DEP field.
	USART_CR3_DEP_Pos = 0xf
	// Bit mask of DEP field.
	USART_CR3_DEP_Msk = 0x8000
	// Bit DEP.
	USART_CR3_DEP = 0x8000
	// DE signal is active high
	USART_CR3_DEP_High = 0x0
	// DE signal is active low
	USART_CR3_DEP_Low = 0x1
	// Position of DEM field.
	USART_CR3_DEM_Pos = 0xe
	// Bit mask of DEM field.
	USART_CR3_DEM_Msk = 0x4000
	// Bit DEM.
	USART_CR3_DEM = 0x4000
	// DE function is disabled
	USART_CR3_DEM_Disabled = 0x0
	// The DE signal is output on the RTS pin
	USART_CR3_DEM_Enabled = 0x1
	// Position of DDRE field.
	USART_CR3_DDRE_Pos = 0xd
	// Bit mask of DDRE field.
	USART_CR3_DDRE_Msk = 0x2000
	// Bit DDRE.
	USART_CR3_DDRE = 0x2000
	// DMA is not disabled in case of reception error
	USART_CR3_DDRE_NotDisabled = 0x0
	// DMA is disabled following a reception error
	USART_CR3_DDRE_Disabled = 0x1
	// Position of OVRDIS field.
	USART_CR3_OVRDIS_Pos = 0xc
	// Bit mask of OVRDIS field.
	USART_CR3_OVRDIS_Msk = 0x1000
	// Bit OVRDIS.
	USART_CR3_OVRDIS = 0x1000
	// Overrun Error Flag, ORE, is set when received data is not read before receiving new data
	USART_CR3_OVRDIS_Enabled = 0x0
	// Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
	USART_CR3_OVRDIS_Disabled = 0x1
	// Position of ONEBIT field.
	USART_CR3_ONEBIT_Pos = 0xb
	// Bit mask of ONEBIT field.
	USART_CR3_ONEBIT_Msk = 0x800
	// Bit ONEBIT.
	USART_CR3_ONEBIT = 0x800
	// Three sample bit method
	USART_CR3_ONEBIT_Sample3 = 0x0
	// One sample bit method
	USART_CR3_ONEBIT_Sample1 = 0x1
	// Position of CTSIE field.
	USART_CR3_CTSIE_Pos = 0xa
	// Bit mask of CTSIE field.
	USART_CR3_CTSIE_Msk = 0x400
	// Bit CTSIE.
	USART_CR3_CTSIE = 0x400
	// Interrupt is inhibited
	USART_CR3_CTSIE_Disabled = 0x0
	// An interrupt is generated whenever CTSIF=1 in the ISR register
	USART_CR3_CTSIE_Enabled = 0x1
	// Position of CTSE field.
	USART_CR3_CTSE_Pos = 0x9
	// Bit mask of CTSE field.
	USART_CR3_CTSE_Msk = 0x200
	// Bit CTSE.
	USART_CR3_CTSE = 0x200
	// CTS hardware flow control disabled
	USART_CR3_CTSE_Disabled = 0x0
	// CTS mode enabled, data is only transmitted when the CTS input is asserted
	USART_CR3_CTSE_Enabled = 0x1
	// Position of RTSE field.
	USART_CR3_RTSE_Pos = 0x8
	// Bit mask of RTSE field.
	USART_CR3_RTSE_Msk = 0x100
	// Bit RTSE.
	USART_CR3_RTSE = 0x100
	// RTS hardware flow control disabled
	USART_CR3_RTSE_Disabled = 0x0
	// RTS output enabled, data is only requested when there is space in the receive buffer
	USART_CR3_RTSE_Enabled = 0x1
	// Position of DMAT field.
	USART_CR3_DMAT_Pos = 0x7
	// Bit mask of DMAT field.
	USART_CR3_DMAT_Msk = 0x80
	// Bit DMAT.
	USART_CR3_DMAT = 0x80
	// DMA mode is disabled for transmission
	USART_CR3_DMAT_Disabled = 0x0
	// DMA mode is enabled for transmission
	USART_CR3_DMAT_Enabled = 0x1
	// Position of DMAR field.
	USART_CR3_DMAR_Pos = 0x6
	// Bit mask of DMAR field.
	USART_CR3_DMAR_Msk = 0x40
	// Bit DMAR.
	USART_CR3_DMAR = 0x40
	// DMA mode is disabled for reception
	USART_CR3_DMAR_Disabled = 0x0
	// DMA mode is enabled for reception
	USART_CR3_DMAR_Enabled = 0x1
	// Position of SCEN field.
	USART_CR3_SCEN_Pos = 0x5
	// Bit mask of SCEN field.
	USART_CR3_SCEN_Msk = 0x20
	// Bit SCEN.
	USART_CR3_SCEN = 0x20
	// Smartcard Mode disabled
	USART_CR3_SCEN_Disabled = 0x0
	// Smartcard Mode enabled
	USART_CR3_SCEN_Enabled = 0x1
	// Position of NACK field.
	USART_CR3_NACK_Pos = 0x4
	// Bit mask of NACK field.
	USART_CR3_NACK_Msk = 0x10
	// Bit NACK.
	USART_CR3_NACK = 0x10
	// NACK transmission in case of parity error is disabled
	USART_CR3_NACK_Disabled = 0x0
	// NACK transmission during parity error is enabled
	USART_CR3_NACK_Enabled = 0x1
	// Position of HDSEL field.
	USART_CR3_HDSEL_Pos = 0x3
	// Bit mask of HDSEL field.
	USART_CR3_HDSEL_Msk = 0x8
	// Bit HDSEL.
	USART_CR3_HDSEL = 0x8
	// Half duplex mode is not selected
	USART_CR3_HDSEL_NotSelected = 0x0
	// Half duplex mode is selected
	USART_CR3_HDSEL_Selected = 0x1
	// Position of IRLP field.
	USART_CR3_IRLP_Pos = 0x2
	// Bit mask of IRLP field.
	USART_CR3_IRLP_Msk = 0x4
	// Bit IRLP.
	USART_CR3_IRLP = 0x4
	// Normal mode
	USART_CR3_IRLP_Normal = 0x0
	// Low-power mode
	USART_CR3_IRLP_LowPower = 0x1
	// Position of IREN field.
	USART_CR3_IREN_Pos = 0x1
	// Bit mask of IREN field.
	USART_CR3_IREN_Msk = 0x2
	// Bit IREN.
	USART_CR3_IREN = 0x2
	// IrDA disabled
	USART_CR3_IREN_Disabled = 0x0
	// IrDA enabled
	USART_CR3_IREN_Enabled = 0x1
	// Position of EIE field.
	USART_CR3_EIE_Pos = 0x0
	// Bit mask of EIE field.
	USART_CR3_EIE_Msk = 0x1
	// Bit EIE.
	USART_CR3_EIE = 0x1
	// Interrupt is inhibited
	USART_CR3_EIE_Disabled = 0x0
	// An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
	USART_CR3_EIE_Enabled = 0x1
	// Position of TXFTIE field.
	USART_CR3_TXFTIE_Pos = 0x17
	// Bit mask of TXFTIE field.
	USART_CR3_TXFTIE_Msk = 0x800000
	// Bit TXFTIE.
	USART_CR3_TXFTIE = 0x800000
	// Interrupt inhibited
	USART_CR3_TXFTIE_Disabled = 0x0
	// USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
	USART_CR3_TXFTIE_Enabled = 0x1
	// Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Pos = 0x18
	// Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000
	// Bit TCBGTIE.
	USART_CR3_TCBGTIE = 0x1000000
	// Interrupt inhibited
	USART_CR3_TCBGTIE_Disabled = 0x0
	// USART interrupt generated whenever TCBGT=1 in the USART_ISR register
	USART_CR3_TCBGTIE_Enabled = 0x1
	// Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Pos = 0x19
	// Bit mask of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000
	// RXFIFO reaches 1/8 of its depth
	USART_CR3_RXFTCFG_Depth_1_8 = 0x0
	// RXFIFO reaches 1/4 of its depth
	USART_CR3_RXFTCFG_Depth_1_4 = 0x1
	// RXFIFO reaches 1/2 of its depth
	USART_CR3_RXFTCFG_Depth_1_2 = 0x2
	// RXFIFO reaches 3/4 of its depth
	USART_CR3_RXFTCFG_Depth_3_4 = 0x3
	// RXFIFO reaches 7/8 of its depth
	USART_CR3_RXFTCFG_Depth_7_8 = 0x4
	// RXFIFO becomes full
	USART_CR3_RXFTCFG_Full = 0x5
	// Position of RXFTIE field.
	USART_CR3_RXFTIE_Pos = 0x1c
	// Bit mask of RXFTIE field.
	USART_CR3_RXFTIE_Msk = 0x10000000
	// Bit RXFTIE.
	USART_CR3_RXFTIE = 0x10000000
	// Interrupt inhibited
	USART_CR3_RXFTIE_Disabled = 0x0
	// USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
	USART_CR3_RXFTIE_Enabled = 0x1
	// Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Pos = 0x1d
	// Bit mask of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000
	// TXFIFO reaches 1/8 of its depth
	USART_CR3_TXFTCFG_Depth_1_8 = 0x0
	// TXFIFO reaches 1/4 of its depth
	USART_CR3_TXFTCFG_Depth_1_4 = 0x1
	// TXFIFO reaches 1/2 of its depth
	USART_CR3_TXFTCFG_Depth_1_2 = 0x2
	// TXFIFO reaches 3/4 of its depth
	USART_CR3_TXFTCFG_Depth_3_4 = 0x3
	// TXFIFO reaches 7/8 of its depth
	USART_CR3_TXFTCFG_Depth_7_8 = 0x4
	// TXFIFO becomes empty
	USART_CR3_TXFTCFG_Empty = 0x5

	// BRR: Baud rate register
	// Position of BRR field.
	USART_BRR_BRR_Pos = 0x0
	// Bit mask of BRR field.
	USART_BRR_BRR_Msk = 0xffff

	// GTPR: Guard time and prescaler register
	// Position of GT field.
	USART_GTPR_GT_Pos = 0x8
	// Bit mask of GT field.
	USART_GTPR_GT_Msk = 0xff00
	// Position of PSC field.
	USART_GTPR_PSC_Pos = 0x0
	// Bit mask of PSC field.
	USART_GTPR_PSC_Msk = 0xff

	// RTOR: Receiver timeout register
	// Position of BLEN field.
	USART_RTOR_BLEN_Pos = 0x18
	// Bit mask of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000
	// Position of RTO field.
	USART_RTOR_RTO_Pos = 0x0
	// Bit mask of RTO field.
	USART_RTOR_RTO_Msk = 0xffffff

	// RQR: Request register
	// Position of TXFRQ field.
	USART_RQR_TXFRQ_Pos = 0x4
	// Bit mask of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10
	// Bit TXFRQ.
	USART_RQR_TXFRQ = 0x10
	// Set the TXE flags. This allows to discard the transmit data
	USART_RQR_TXFRQ_Discard = 0x1
	// Position of RXFRQ field.
	USART_RQR_RXFRQ_Pos = 0x3
	// Bit mask of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8
	// Bit RXFRQ.
	USART_RQR_RXFRQ = 0x8
	// clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
	USART_RQR_RXFRQ_Discard = 0x1
	// Position of MMRQ field.
	USART_RQR_MMRQ_Pos = 0x2
	// Bit mask of MMRQ field.
	USART_RQR_MMRQ_Msk = 0x4
	// Bit MMRQ.
	USART_RQR_MMRQ = 0x4
	// Puts the USART in mute mode and sets the RWU flag
	USART_RQR_MMRQ_Mute = 0x1
	// Position of SBKRQ field.
	USART_RQR_SBKRQ_Pos = 0x1
	// Bit mask of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2
	// Bit SBKRQ.
	USART_RQR_SBKRQ = 0x2
	// sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
	USART_RQR_SBKRQ_Break = 0x1
	// Position of ABRRQ field.
	USART_RQR_ABRRQ_Pos = 0x0
	// Bit mask of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1
	// Bit ABRRQ.
	USART_RQR_ABRRQ = 0x1
	// resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
	USART_RQR_ABRRQ_Request = 0x1

	// ISR: Interrupt & status register
	// Position of REACK field.
	USART_ISR_REACK_Pos = 0x16
	// Bit mask of REACK field.
	USART_ISR_REACK_Msk = 0x400000
	// Bit REACK.
	USART_ISR_REACK = 0x400000
	// Position of TEACK field.
	USART_ISR_TEACK_Pos = 0x15
	// Bit mask of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000
	// Bit TEACK.
	USART_ISR_TEACK = 0x200000
	// Position of WUF field.
	USART_ISR_WUF_Pos = 0x14
	// Bit mask of WUF field.
	USART_ISR_WUF_Msk = 0x100000
	// Bit WUF.
	USART_ISR_WUF = 0x100000
	// Position of RWU field.
	USART_ISR_RWU_Pos = 0x13
	// Bit mask of RWU field.
	USART_ISR_RWU_Msk = 0x80000
	// Bit RWU.
	USART_ISR_RWU = 0x80000
	// Receiver in Active mode
	USART_ISR_RWU_Active = 0x0
	// Receiver in Mute mode
	USART_ISR_RWU_Mute = 0x1
	// Position of SBKF field.
	USART_ISR_SBKF_Pos = 0x12
	// Bit mask of SBKF field.
	USART_ISR_SBKF_Msk = 0x40000
	// Bit SBKF.
	USART_ISR_SBKF = 0x40000
	// No break character transmitted
	USART_ISR_SBKF_NoBreak = 0x0
	// Break character transmitted
	USART_ISR_SBKF_Break = 0x1
	// Position of CMF field.
	USART_ISR_CMF_Pos = 0x11
	// Bit mask of CMF field.
	USART_ISR_CMF_Msk = 0x20000
	// Bit CMF.
	USART_ISR_CMF = 0x20000
	// No Character match detected
	USART_ISR_CMF_NoMatch = 0x0
	// Character match detected
	USART_ISR_CMF_Match = 0x1
	// Position of BUSY field.
	USART_ISR_BUSY_Pos = 0x10
	// Bit mask of BUSY field.
	USART_ISR_BUSY_Msk = 0x10000
	// Bit BUSY.
	USART_ISR_BUSY = 0x10000
	// USART is idle (no reception)
	USART_ISR_BUSY_Idle = 0x0
	// Reception on going
	USART_ISR_BUSY_Busy = 0x1
	// Position of ABRF field.
	USART_ISR_ABRF_Pos = 0xf
	// Bit mask of ABRF field.
	USART_ISR_ABRF_Msk = 0x8000
	// Bit ABRF.
	USART_ISR_ABRF = 0x8000
	// Position of ABRE field.
	USART_ISR_ABRE_Pos = 0xe
	// Bit mask of ABRE field.
	USART_ISR_ABRE_Msk = 0x4000
	// Bit ABRE.
	USART_ISR_ABRE = 0x4000
	// Position of EOBF field.
	USART_ISR_EOBF_Pos = 0xc
	// Bit mask of EOBF field.
	USART_ISR_EOBF_Msk = 0x1000
	// Bit EOBF.
	USART_ISR_EOBF = 0x1000
	// End of Block not reached
	USART_ISR_EOBF_NotReached = 0x0
	// End of Block (number of characters) reached
	USART_ISR_EOBF_Reached = 0x1
	// Position of RTOF field.
	USART_ISR_RTOF_Pos = 0xb
	// Bit mask of RTOF field.
	USART_ISR_RTOF_Msk = 0x800
	// Bit RTOF.
	USART_ISR_RTOF = 0x800
	// Timeout value not reached
	USART_ISR_RTOF_NotReached = 0x0
	// Timeout value reached without any data reception
	USART_ISR_RTOF_Reached = 0x1
	// Position of CTS field.
	USART_ISR_CTS_Pos = 0xa
	// Bit mask of CTS field.
	USART_ISR_CTS_Msk = 0x400
	// Bit CTS.
	USART_ISR_CTS = 0x400
	// CTS line set
	USART_ISR_CTS_Set = 0x0
	// CTS line reset
	USART_ISR_CTS_Reset = 0x1
	// Position of CTSIF field.
	USART_ISR_CTSIF_Pos = 0x9
	// Bit mask of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200
	// Bit CTSIF.
	USART_ISR_CTSIF = 0x200
	// No change occurred on the CTS status line
	USART_ISR_CTSIF_NotChanged = 0x0
	// A change occurred on the CTS status line
	USART_ISR_CTSIF_Changed = 0x1
	// Position of LBDF field.
	USART_ISR_LBDF_Pos = 0x8
	// Bit mask of LBDF field.
	USART_ISR_LBDF_Msk = 0x100
	// Bit LBDF.
	USART_ISR_LBDF = 0x100
	// LIN break not detected
	USART_ISR_LBDF_NotDetected = 0x0
	// LIN break detected
	USART_ISR_LBDF_Detected = 0x1
	// Position of TXE field.
	USART_ISR_TXE_Pos = 0x7
	// Bit mask of TXE field.
	USART_ISR_TXE_Msk = 0x80
	// Bit TXE.
	USART_ISR_TXE = 0x80
	// Bit TXFNF. (added by gen-device-svd)
	USART_ISR_TXFNF = 0x80
	// Transmit FIFO is full
	USART_ISR_TXE_Full = 0x0
	// Transmit FIFO is not full
	USART_ISR_TXE_NotFull = 0x1
	// Position of TC field.
	USART_ISR_TC_Pos = 0x6
	// Bit mask of TC field.
	USART_ISR_TC_Msk = 0x40
	// Bit TC.
	USART_ISR_TC = 0x40
	// Transmission is not complete
	USART_ISR_TC_TxNotComplete = 0x0
	// Transmission is complete
	USART_ISR_TC_TxComplete = 0x1
	// Position of RXNE field.
	USART_ISR_RXNE_Pos = 0x5
	// Bit mask of RXNE field.
	USART_ISR_RXNE_Msk = 0x20
	// Bit RXNE.
	USART_ISR_RXNE = 0x20
	// Data is not received
	USART_ISR_RXNE_NoData = 0x0
	// Received data is ready to be read
	USART_ISR_RXNE_DataReady = 0x1
	// Position of IDLE field.
	USART_ISR_IDLE_Pos = 0x4
	// Bit mask of IDLE field.
	USART_ISR_IDLE_Msk = 0x10
	// Bit IDLE.
	USART_ISR_IDLE = 0x10
	// No Idle Line is detected
	USART_ISR_IDLE_NoIdle = 0x0
	// Idle Line is detected
	USART_ISR_IDLE_Idle = 0x1
	// Position of ORE field.
	USART_ISR_ORE_Pos = 0x3
	// Bit mask of ORE field.
	USART_ISR_ORE_Msk = 0x8
	// Bit ORE.
	USART_ISR_ORE = 0x8
	// No Overrun error
	USART_ISR_ORE_NoOverrun = 0x0
	// Overrun error is detected
	USART_ISR_ORE_Overrun = 0x1
	// Position of NF field.
	USART_ISR_NF_Pos = 0x2
	// Bit mask of NF field.
	USART_ISR_NF_Msk = 0x4
	// Bit NF.
	USART_ISR_NF = 0x4
	// No noise is detected
	USART_ISR_NF_NoNoise = 0x0
	// Noise is detected
	USART_ISR_NF_Noise = 0x1
	// Position of FE field.
	USART_ISR_FE_Pos = 0x1
	// Bit mask of FE field.
	USART_ISR_FE_Msk = 0x2
	// Bit FE.
	USART_ISR_FE = 0x2
	// No Framing error is detected
	USART_ISR_FE_NoError = 0x0
	// Framing error or break character is detected
	USART_ISR_FE_Error = 0x1
	// Position of PE field.
	USART_ISR_PE_Pos = 0x0
	// Bit mask of PE field.
	USART_ISR_PE_Msk = 0x1
	// Bit PE.
	USART_ISR_PE = 0x1
	// No parity error
	USART_ISR_PE_NoError = 0x0
	// Parity error
	USART_ISR_PE_Error = 0x1
	// Position of TXFE field.
	USART_ISR_TXFE_Pos = 0x17
	// Bit mask of TXFE field.
	USART_ISR_TXFE_Msk = 0x800000
	// Bit TXFE.
	USART_ISR_TXFE = 0x800000
	// TXFIFO not empty.
	USART_ISR_TXFE_NotEmpty = 0x0
	// TXFIFO empty.
	USART_ISR_TXFE_Empty = 0x1
	// Position of RXFF field.
	USART_ISR_RXFF_Pos = 0x18
	// Bit mask of RXFF field.
	USART_ISR_RXFF_Msk = 0x1000000
	// Bit RXFF.
	USART_ISR_RXFF = 0x1000000
	// RXFIFO not full.
	USART_ISR_RXFF_NotFull = 0x0
	// RXFIFO Full.
	USART_ISR_RXFF_Full = 0x1
	// Position of TCBGT field.
	USART_ISR_TCBGT_Pos = 0x19
	// Bit mask of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000
	// Bit TCBGT.
	USART_ISR_TCBGT = 0x2000000
	// Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
	USART_ISR_TCBGT_NotCompleted = 0x0
	// Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
	USART_ISR_TCBGT_Completed = 0x1
	// Position of RXFT field.
	USART_ISR_RXFT_Pos = 0x1a
	// Bit mask of RXFT field.
	USART_ISR_RXFT_Msk = 0x4000000
	// Bit RXFT.
	USART_ISR_RXFT = 0x4000000
	// Receive FIFO does not reach the programmed threshold.
	USART_ISR_RXFT_NotReached = 0x0
	// Receive FIFO reached the programmed threshold.
	USART_ISR_RXFT_Reached = 0x1
	// Position of TXFT field.
	USART_ISR_TXFT_Pos = 0x1b
	// Bit mask of TXFT field.
	USART_ISR_TXFT_Msk = 0x8000000
	// Bit TXFT.
	USART_ISR_TXFT = 0x8000000
	// TXFIFO does not reach the programmed threshold.
	USART_ISR_TXFT_NotReached = 0x0
	// TXFIFO reached the programmed threshold.
	USART_ISR_TXFT_Reached = 0x1
	// Position of UDR field.
	USART_ISR_UDR_Pos = 0xd
	// Bit mask of UDR field.
	USART_ISR_UDR_Msk = 0x2000
	// Bit UDR.
	USART_ISR_UDR = 0x2000
	// No underrun error
	USART_ISR_UDR_NoUnderrun = 0x0
	// underrun error
	USART_ISR_UDR_Underrun = 0x1

	// ICR: Interrupt flag clear register
	// Position of WUCF field.
	USART_ICR_WUCF_Pos = 0x14
	// Bit mask of WUCF field.
	USART_ICR_WUCF_Msk = 0x100000
	// Bit WUCF.
	USART_ICR_WUCF = 0x100000
	// Clears the WUF flag in the ISR register
	USART_ICR_WUCF_Clear = 0x1
	// Position of CMCF field.
	USART_ICR_CMCF_Pos = 0x11
	// Bit mask of CMCF field.
	USART_ICR_CMCF_Msk = 0x20000
	// Bit CMCF.
	USART_ICR_CMCF = 0x20000
	// Clears the CMF flag in the ISR register
	USART_ICR_CMCF_Clear = 0x1
	// Position of EOBCF field.
	USART_ICR_EOBCF_Pos = 0xc
	// Bit mask of EOBCF field.
	USART_ICR_EOBCF_Msk = 0x1000
	// Bit EOBCF.
	USART_ICR_EOBCF = 0x1000
	// Clears the EOBF flag in the ISR register
	USART_ICR_EOBCF_Clear = 0x1
	// Position of RTOCF field.
	USART_ICR_RTOCF_Pos = 0xb
	// Bit mask of RTOCF field.
	USART_ICR_RTOCF_Msk = 0x800
	// Bit RTOCF.
	USART_ICR_RTOCF = 0x800
	// Clears the RTOF flag in the ISR register
	USART_ICR_RTOCF_Clear = 0x1
	// Position of CTSCF field.
	USART_ICR_CTSCF_Pos = 0x9
	// Bit mask of CTSCF field.
	USART_ICR_CTSCF_Msk = 0x200
	// Bit CTSCF.
	USART_ICR_CTSCF = 0x200
	// Clears the CTSIF flag in the ISR register
	USART_ICR_CTSCF_Clear = 0x1
	// Position of LBDCF field.
	USART_ICR_LBDCF_Pos = 0x8
	// Bit mask of LBDCF field.
	USART_ICR_LBDCF_Msk = 0x100
	// Bit LBDCF.
	USART_ICR_LBDCF = 0x100
	// Clears the LBDF flag in the ISR register
	USART_ICR_LBDCF_Clear = 0x1
	// Position of TCCF field.
	USART_ICR_TCCF_Pos = 0x6
	// Bit mask of TCCF field.
	USART_ICR_TCCF_Msk = 0x40
	// Bit TCCF.
	USART_ICR_TCCF = 0x40
	// Clears the TC flag in the ISR register
	USART_ICR_TCCF_Clear = 0x1
	// Position of IDLECF field.
	USART_ICR_IDLECF_Pos = 0x4
	// Bit mask of IDLECF field.
	USART_ICR_IDLECF_Msk = 0x10
	// Bit IDLECF.
	USART_ICR_IDLECF = 0x10
	// Clears the IDLE flag in the ISR register
	USART_ICR_IDLECF_Clear = 0x1
	// Position of ORECF field.
	USART_ICR_ORECF_Pos = 0x3
	// Bit mask of ORECF field.
	USART_ICR_ORECF_Msk = 0x8
	// Bit ORECF.
	USART_ICR_ORECF = 0x8
	// Clears the ORE flag in the ISR register
	USART_ICR_ORECF_Clear = 0x1
	// Position of NCF field.
	USART_ICR_NCF_Pos = 0x2
	// Bit mask of NCF field.
	USART_ICR_NCF_Msk = 0x4
	// Bit NCF.
	USART_ICR_NCF = 0x4
	// Clears the NF flag in the ISR register
	USART_ICR_NCF_Clear = 0x1
	// Position of FECF field.
	USART_ICR_FECF_Pos = 0x1
	// Bit mask of FECF field.
	USART_ICR_FECF_Msk = 0x2
	// Bit FECF.
	USART_ICR_FECF = 0x2
	// Clears the FE flag in the ISR register
	USART_ICR_FECF_Clear = 0x1
	// Position of PECF field.
	USART_ICR_PECF_Pos = 0x0
	// Bit mask of PECF field.
	USART_ICR_PECF_Msk = 0x1
	// Bit PECF.
	USART_ICR_PECF = 0x1
	// Clears the PE flag in the ISR register
	USART_ICR_PECF_Clear = 0x1
	// Position of TXFECF field.
	USART_ICR_TXFECF_Pos = 0x5
	// Bit mask of TXFECF field.
	USART_ICR_TXFECF_Msk = 0x20
	// Bit TXFECF.
	USART_ICR_TXFECF = 0x20
	// Clear the TXFE flag in the ISR register
	USART_ICR_TXFECF_Clear = 0x1
	// Position of TCBGTCF field.
	USART_ICR_TCBGTCF_Pos = 0x7
	// Bit mask of TCBGTCF field.
	USART_ICR_TCBGTCF_Msk = 0x80
	// Bit TCBGTCF.
	USART_ICR_TCBGTCF = 0x80
	// Clear the TCBGT flag in the ISR register
	USART_ICR_TCBGTCF_Clear = 0x1
	// Position of UDRCF field.
	USART_ICR_UDRCF_Pos = 0xd
	// Bit mask of UDRCF field.
	USART_ICR_UDRCF_Msk = 0x2000
	// Bit UDRCF.
	USART_ICR_UDRCF = 0x2000
	// Clear the UDR flag in the ISR register
	USART_ICR_UDRCF_Clear = 0x1

	// RDR: Receive data register
	// Position of RDR field.
	USART_RDR_RDR_Pos = 0x0
	// Bit mask of RDR field.
	USART_RDR_RDR_Msk = 0x1ff

	// TDR: Transmit data register
	// Position of TDR field.
	USART_TDR_TDR_Pos = 0x0
	// Bit mask of TDR field.
	USART_TDR_TDR_Msk = 0x1ff

	// PRESC: PRESC
	// Position of PRESCALER field.
	USART_PRESC_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf
	// Input clock divided by 1
	USART_PRESC_PRESCALER_Div1 = 0x0
	// Input clock divided by 2
	USART_PRESC_PRESCALER_Div2 = 0x1
	// Input clock divided by 4
	USART_PRESC_PRESCALER_Div4 = 0x2
	// Input clock divided by 6
	USART_PRESC_PRESCALER_Div6 = 0x3
	// Input clock divided by 8
	USART_PRESC_PRESCALER_Div8 = 0x4
	// Input clock divided by 10
	USART_PRESC_PRESCALER_Div10 = 0x5
	// Input clock divided by 12
	USART_PRESC_PRESCALER_Div12 = 0x6
	// Input clock divided by 16
	USART_PRESC_PRESCALER_Div16 = 0x7
	// Input clock divided by 32
	USART_PRESC_PRESCALER_Div32 = 0x8
	// Input clock divided by 64
	USART_PRESC_PRESCALER_Div64 = 0x9
	// Input clock divided by 128
	USART_PRESC_PRESCALER_Div128 = 0xa
	// Input clock divided by 256
	USART_PRESC_PRESCALER_Div256 = 0xb
)

// Constants for OCTOSPI1: OctoSPI
const (
	// CR: control register
	// Position of FMODE field.
	OctoSPI_CR_FMODE_Pos = 0x1c
	// Bit mask of FMODE field.
	OctoSPI_CR_FMODE_Msk = 0x30000000
	// Indirect-write mode
	OctoSPI_CR_FMODE_IndirectWrite = 0x0
	// Indirect-read mode
	OctoSPI_CR_FMODE_IndirectRead = 0x1
	// Automatic status-polling mode
	OctoSPI_CR_FMODE_AutomaticPolling = 0x2
	// Memory-mapped mode
	OctoSPI_CR_FMODE_MemoryMapped = 0x3
	// Position of PMM field.
	OctoSPI_CR_PMM_Pos = 0x17
	// Bit mask of PMM field.
	OctoSPI_CR_PMM_Msk = 0x800000
	// Bit PMM.
	OctoSPI_CR_PMM = 0x800000
	// AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register
	OctoSPI_CR_PMM_ANDMatchMode = 0x0
	// OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register
	OctoSPI_CR_PMM_ORMatchmode = 0x1
	// Position of APMS field.
	OctoSPI_CR_APMS_Pos = 0x16
	// Bit mask of APMS field.
	OctoSPI_CR_APMS_Msk = 0x400000
	// Bit APMS.
	OctoSPI_CR_APMS = 0x400000
	// Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI
	OctoSPI_CR_APMS_Running = 0x0
	// Automatic status-polling mode stops as soon as there is a match
	OctoSPI_CR_APMS_StopMatch = 0x1
	// Position of TEIE field.
	OctoSPI_CR_TEIE_Pos = 0x10
	// Bit mask of TEIE field.
	OctoSPI_CR_TEIE_Msk = 0x10000
	// Bit TEIE.
	OctoSPI_CR_TEIE = 0x10000
	// Interrupt disabled
	OctoSPI_CR_TEIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_TEIE_Enabled = 0x1
	// Position of TOIE field.
	OctoSPI_CR_TOIE_Pos = 0x14
	// Bit mask of TOIE field.
	OctoSPI_CR_TOIE_Msk = 0x100000
	// Bit TOIE.
	OctoSPI_CR_TOIE = 0x100000
	// Interrupt disabled
	OctoSPI_CR_TOIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_TOIE_Enabled = 0x1
	// Position of SMIE field.
	OctoSPI_CR_SMIE_Pos = 0x13
	// Bit mask of SMIE field.
	OctoSPI_CR_SMIE_Msk = 0x80000
	// Bit SMIE.
	OctoSPI_CR_SMIE = 0x80000
	// Interrupt disabled
	OctoSPI_CR_SMIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_SMIE_Enabled = 0x1
	// Position of FTIE field.
	OctoSPI_CR_FTIE_Pos = 0x12
	// Bit mask of FTIE field.
	OctoSPI_CR_FTIE_Msk = 0x40000
	// Bit FTIE.
	OctoSPI_CR_FTIE = 0x40000
	// Interrupt disabled
	OctoSPI_CR_FTIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_FTIE_Enabled = 0x1
	// Position of TCIE field.
	OctoSPI_CR_TCIE_Pos = 0x11
	// Bit mask of TCIE field.
	OctoSPI_CR_TCIE_Msk = 0x20000
	// Bit TCIE.
	OctoSPI_CR_TCIE = 0x20000
	// Interrupt disabled
	OctoSPI_CR_TCIE_Disabled = 0x0
	// Interrupt enabled
	OctoSPI_CR_TCIE_Enabled = 0x1
	// Position of FTHRES field.
	OctoSPI_CR_FTHRES_Pos = 0x8
	// Bit mask of FTHRES field.
	OctoSPI_CR_FTHRES_Msk = 0x1f00
	// Position of FSEL field.
	OctoSPI_CR_FSEL_Pos = 0x7
	// Bit mask of FSEL field.
	OctoSPI_CR_FSEL_Msk = 0x80
	// Bit FSEL.
	OctoSPI_CR_FSEL = 0x80
	// FLASH 1 selected (data exchanged over IO[3:0])
	OctoSPI_CR_FSEL_FLASH1 = 0x0
	// FLASH 2 selected (data exchanged over IO[7:4])
	OctoSPI_CR_FSEL_FLASH2 = 0x1
	// Position of DMM field.
	OctoSPI_CR_DMM_Pos = 0x6
	// Bit mask of DMM field.
	OctoSPI_CR_DMM_Msk = 0x40
	// Bit DMM.
	OctoSPI_CR_DMM = 0x40
	// Dual-quad configuration disabled
	OctoSPI_CR_DMM_Disabled = 0x0
	// Dual-quad configuration enabled
	OctoSPI_CR_DMM_Enabled = 0x1
	// Position of TCEN field.
	OctoSPI_CR_TCEN_Pos = 0x3
	// Bit mask of TCEN field.
	OctoSPI_CR_TCEN_Msk = 0x8
	// Bit TCEN.
	OctoSPI_CR_TCEN = 0x8
	// Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode
	OctoSPI_CR_TCEN_Disabled = 0x0
	// Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity
	OctoSPI_CR_TCEN_Enabled = 0x1
	// Position of DMAEN field.
	OctoSPI_CR_DMAEN_Pos = 0x2
	// Bit mask of DMAEN field.
	OctoSPI_CR_DMAEN_Msk = 0x4
	// Bit DMAEN.
	OctoSPI_CR_DMAEN = 0x4
	// DMA disabled for Indirect mode
	OctoSPI_CR_DMAEN_Disabled = 0x0
	// DMA enabled for Indirect mode
	OctoSPI_CR_DMAEN_Enabled = 0x1
	// Position of ABORT field.
	OctoSPI_CR_ABORT_Pos = 0x1
	// Bit mask of ABORT field.
	OctoSPI_CR_ABORT_Msk = 0x2
	// Bit ABORT.
	OctoSPI_CR_ABORT = 0x2
	// No abort requested
	OctoSPI_CR_ABORT_NotRequested = 0x0
	// Abort requested
	OctoSPI_CR_ABORT_Requested = 0x1
	// Position of EN field.
	OctoSPI_CR_EN_Pos = 0x0
	// Bit mask of EN field.
	OctoSPI_CR_EN_Msk = 0x1
	// Bit EN.
	OctoSPI_CR_EN = 0x1
	// OCTOSPI disabled
	OctoSPI_CR_EN_Disabled = 0x0
	// OCTOSPI enabled
	OctoSPI_CR_EN_Enabled = 0x1

	// DCR1: device configuration register
	// Position of CKMODE field.
	OctoSPI_DCR1_CKMODE_Pos = 0x0
	// Bit mask of CKMODE field.
	OctoSPI_DCR1_CKMODE_Msk = 0x1
	// Bit CKMODE.
	OctoSPI_DCR1_CKMODE = 0x1
	// CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0
	OctoSPI_DCR1_CKMODE_Mode0 = 0x0
	// CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3
	OctoSPI_DCR1_CKMODE_Mode3 = 0x1
	// Position of FRCK field.
	OctoSPI_DCR1_FRCK_Pos = 0x1
	// Bit mask of FRCK field.
	OctoSPI_DCR1_FRCK_Msk = 0x2
	// Bit FRCK.
	OctoSPI_DCR1_FRCK = 0x2
	// CLK is not free running
	OctoSPI_DCR1_FRCK_Disabled = 0x0
	// CLK is free running (always provided)
	OctoSPI_DCR1_FRCK_Enabled = 0x1
	// Position of DLYBYP field.
	OctoSPI_DCR1_DLYBYP_Pos = 0x3
	// Bit mask of DLYBYP field.
	OctoSPI_DCR1_DLYBYP_Msk = 0x8
	// Bit DLYBYP.
	OctoSPI_DCR1_DLYBYP = 0x8
	// The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral)
	OctoSPI_DCR1_DLYBYP_DelayBlockEnabled = 0x0
	// The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block
	OctoSPI_DCR1_DLYBYP_DelayBlockBypassed = 0x1
	// Position of CSHT field.
	OctoSPI_DCR1_CSHT_Pos = 0x8
	// Bit mask of CSHT field.
	OctoSPI_DCR1_CSHT_Msk = 0x700
	// Position of DEVSIZE field.
	OctoSPI_DCR1_DEVSIZE_Pos = 0x10
	// Bit mask of DEVSIZE field.
	OctoSPI_DCR1_DEVSIZE_Msk = 0x1f0000
	// Position of MTYP field.
	OctoSPI_DCR1_MTYP_Pos = 0x18
	// Bit mask of MTYP field.
	OctoSPI_DCR1_MTYP_Msk = 0x7000000
	// Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes
	OctoSPI_DCR1_MTYP_MicronMode = 0x0
	// Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes
	OctoSPI_DCR1_MTYP_MacronixMode = 0x1
	// Standard Mode
	OctoSPI_DCR1_MTYP_StandardMode = 0x2
	// Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping
	OctoSPI_DCR1_MTYP_MacronixRamMode = 0x3
	// HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected
	OctoSPI_DCR1_MTYP_HyperBusMemoryMode = 0x4
	// HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used
	OctoSPI_DCR1_MTYP_HyperBusMode = 0x5

	// DCR2: device configuration register 2
	// Position of PRESCALER field.
	OctoSPI_DCR2_PRESCALER_Pos = 0x0
	// Bit mask of PRESCALER field.
	OctoSPI_DCR2_PRESCALER_Msk = 0xff
	// Position of WRAPSIZE field.
	OctoSPI_DCR2_WRAPSIZE_Pos = 0x10
	// Bit mask of WRAPSIZE field.
	OctoSPI_DCR2_WRAPSIZE_Msk = 0x70000
	// Wrapped reads are not supported by the memory
	OctoSPI_DCR2_WRAPSIZE_NoWrappingSupport = 0x0
	// External memory supports wrap size of 16 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize16 = 0x2
	// External memory supports wrap size of 32 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize32 = 0x3
	// External memory supports wrap size of 64 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize64 = 0x4
	// External memory supports wrap size of 128 bytes
	OctoSPI_DCR2_WRAPSIZE_WrappingSize128 = 0x5

	// DCR3: device configuration register 3
	// Position of CSBOUND field.
	OctoSPI_DCR3_CSBOUND_Pos = 0x10
	// Bit mask of CSBOUND field.
	OctoSPI_DCR3_CSBOUND_Msk = 0x1f0000

	// DCR4: device configuration register 4
	// Position of REFRESH field.
	OctoSPI_DCR4_REFRESH_Pos = 0x0
	// Bit mask of REFRESH field.
	OctoSPI_DCR4_REFRESH_Msk = 0xffffffff

	// SR: status register
	// Position of TEF field.
	OctoSPI_SR_TEF_Pos = 0x0
	// Bit mask of TEF field.
	OctoSPI_SR_TEF_Msk = 0x1
	// Bit TEF.
	OctoSPI_SR_TEF = 0x1
	// This bit is cleared by writing 1 to CTEF
	OctoSPI_SR_TEF_Cleared = 0x0
	// This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode
	OctoSPI_SR_TEF_InvalidAddressAccessed = 0x1
	// Position of TCF field.
	OctoSPI_SR_TCF_Pos = 0x1
	// Bit mask of TCF field.
	OctoSPI_SR_TCF_Msk = 0x2
	// Bit TCF.
	OctoSPI_SR_TCF = 0x2
	// This bit is cleared by writing 1 to CTCF
	OctoSPI_SR_TCF_Cleared = 0x0
	// This bit is set when the programmed number of data has been transferred
	OctoSPI_SR_TCF_TransferCompleted = 0x1
	// Position of FTF field.
	OctoSPI_SR_FTF_Pos = 0x2
	// Bit mask of FTF field.
	OctoSPI_SR_FTF_Msk = 0x4
	// Bit FTF.
	OctoSPI_SR_FTF = 0x4
	// It is cleared automatically as soon as the threshold condition is no longer true
	OctoSPI_SR_FTF_Cleared = 0x0
	// This bit is set when the FIFO threshold has been reached
	OctoSPI_SR_FTF_ThresholdReached = 0x1
	// Position of SMF field.
	OctoSPI_SR_SMF_Pos = 0x3
	// Bit mask of SMF field.
	OctoSPI_SR_SMF_Msk = 0x8
	// Bit SMF.
	OctoSPI_SR_SMF = 0x8
	// It is cleared by writing 1 to CSMF
	OctoSPI_SR_SMF_Cleared = 0x0
	// This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR)
	OctoSPI_SR_SMF_Matched = 0x1
	// Position of TOF field.
	OctoSPI_SR_TOF_Pos = 0x4
	// Bit mask of TOF field.
	OctoSPI_SR_TOF_Msk = 0x10
	// Bit TOF.
	OctoSPI_SR_TOF = 0x10
	// This bit is cleared by writing 1 to CTOF
	OctoSPI_SR_TOF_Cleared = 0x0
	// This bit is set when timeout occurs
	OctoSPI_SR_TOF_Timeout = 0x1
	// Position of BUSY field.
	OctoSPI_SR_BUSY_Pos = 0x5
	// Bit mask of BUSY field.
	OctoSPI_SR_BUSY_Msk = 0x20
	// Bit BUSY.
	OctoSPI_SR_BUSY = 0x20
	// This bit is cleared automatically when the operation with the external device is finished and the FIFO is empty
	OctoSPI_SR_BUSY_Cleared = 0x0
	// This bit is set when an operation is ongoing
	OctoSPI_SR_BUSY_Busy = 0x1
	// Position of FLEVEL field.
	OctoSPI_SR_FLEVEL_Pos = 0x8
	// Bit mask of FLEVEL field.
	OctoSPI_SR_FLEVEL_Msk = 0x3f00

	// FCR: flag clear register
	// Position of CTEF field.
	OctoSPI_FCR_CTEF_Pos = 0x0
	// Bit mask of CTEF field.
	OctoSPI_FCR_CTEF_Msk = 0x1
	// Bit CTEF.
	OctoSPI_FCR_CTEF = 0x1
	// Writing 1 clears the TEF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CTEF_Clear = 0x1
	// Position of CTCF field.
	OctoSPI_FCR_CTCF_Pos = 0x1
	// Bit mask of CTCF field.
	OctoSPI_FCR_CTCF_Msk = 0x2
	// Bit CTCF.
	OctoSPI_FCR_CTCF = 0x2
	// Writing 1 clears the TCF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CTCF_Clear = 0x1
	// Position of CSMF field.
	OctoSPI_FCR_CSMF_Pos = 0x3
	// Bit mask of CSMF field.
	OctoSPI_FCR_CSMF_Msk = 0x8
	// Bit CSMF.
	OctoSPI_FCR_CSMF = 0x8
	// Writing 1 clears the SMF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CSMF_Clear = 0x1
	// Position of CTOF field.
	OctoSPI_FCR_CTOF_Pos = 0x4
	// Bit mask of CTOF field.
	OctoSPI_FCR_CTOF_Msk = 0x10
	// Bit CTOF.
	OctoSPI_FCR_CTOF = 0x10
	// Writing 1 clears the TOF flag in the OCTOSPI_SR register
	OctoSPI_FCR_CTOF_Clear = 0x1

	// DLR: data length register
	// Position of DL field.
	OctoSPI_DLR_DL_Pos = 0x0
	// Bit mask of DL field.
	OctoSPI_DLR_DL_Msk = 0xffffffff

	// AR: address register
	// Position of ADDRESS field.
	OctoSPI_AR_ADDRESS_Pos = 0x0
	// Bit mask of ADDRESS field.
	OctoSPI_AR_ADDRESS_Msk = 0xffffffff

	// DR: data register
	// Position of DATA field.
	OctoSPI_DR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	OctoSPI_DR_DATA_Msk = 0xffffffff

	// PSMKR: polling status mask register
	// Position of MASK field.
	OctoSPI_PSMKR_MASK_Pos = 0x0
	// Bit mask of MASK field.
	OctoSPI_PSMKR_MASK_Msk = 0xffffffff

	// PSMAR: polling status match register
	// Position of MATCH field.
	OctoSPI_PSMAR_MATCH_Pos = 0x0
	// Bit mask of MATCH field.
	OctoSPI_PSMAR_MATCH_Msk = 0xffffffff

	// PIR: polling interval register
	// Position of INTERVAL field.
	OctoSPI_PIR_INTERVAL_Pos = 0x0
	// Bit mask of INTERVAL field.
	OctoSPI_PIR_INTERVAL_Msk = 0xffff

	// CCR: communication configuration
	// Position of IMODE field.
	OctoSPI_CCR_IMODE_Pos = 0x0
	// Bit mask of IMODE field.
	OctoSPI_CCR_IMODE_Msk = 0x7
	// No instruction
	OctoSPI_CCR_IMODE_NoInstruction = 0x0
	// Instruction on a single line
	OctoSPI_CCR_IMODE_SingleLine = 0x1
	// Instruction on two lines
	OctoSPI_CCR_IMODE_TwoLines = 0x2
	// Instruction on four lines
	OctoSPI_CCR_IMODE_FourLines = 0x3
	// Instruction on eight lines
	OctoSPI_CCR_IMODE_EightLines = 0x4
	// Position of IDTR field.
	OctoSPI_CCR_IDTR_Pos = 0x3
	// Bit mask of IDTR field.
	OctoSPI_CCR_IDTR_Msk = 0x8
	// Bit IDTR.
	OctoSPI_CCR_IDTR = 0x8
	// DTR mode disabled for instruction phase
	OctoSPI_CCR_IDTR_Disabled = 0x0
	// DTR mode enabled for instruction phase
	OctoSPI_CCR_IDTR_Enabled = 0x1
	// Position of ISIZE field.
	OctoSPI_CCR_ISIZE_Pos = 0x4
	// Bit mask of ISIZE field.
	OctoSPI_CCR_ISIZE_Msk = 0x30
	// 8-bit instruction
	OctoSPI_CCR_ISIZE_Bits8 = 0x0
	// 16-bit instruction
	OctoSPI_CCR_ISIZE_Bits16 = 0x1
	// 24-bit instruction
	OctoSPI_CCR_ISIZE_Bits24 = 0x2
	// 32-bit instruction
	OctoSPI_CCR_ISIZE_Bits32 = 0x3
	// Position of ADMODE field.
	OctoSPI_CCR_ADMODE_Pos = 0x8
	// Bit mask of ADMODE field.
	OctoSPI_CCR_ADMODE_Msk = 0x700
	// No address
	OctoSPI_CCR_ADMODE_NoAddress = 0x0
	// Address on a single line
	OctoSPI_CCR_ADMODE_SingleLine = 0x1
	// Address on two lines
	OctoSPI_CCR_ADMODE_TwoLines = 0x2
	// Address on four lines
	OctoSPI_CCR_ADMODE_FourLines = 0x3
	// Address on eight lines
	OctoSPI_CCR_ADMODE_EightLines = 0x4
	// Position of ADDTR field.
	OctoSPI_CCR_ADDTR_Pos = 0xb
	// Bit mask of ADDTR field.
	OctoSPI_CCR_ADDTR_Msk = 0x800
	// Bit ADDTR.
	OctoSPI_CCR_ADDTR = 0x800
	// DTR mode disabled for address phase
	OctoSPI_CCR_ADDTR_Disabled = 0x0
	// DTR mode enabled for address phase
	OctoSPI_CCR_ADDTR_Enabled = 0x1
	// Position of ADSIZE field.
	OctoSPI_CCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	OctoSPI_CCR_ADSIZE_Msk = 0x3000
	// 8-bit address
	OctoSPI_CCR_ADSIZE_Bits8 = 0x0
	// 16-bit address
	OctoSPI_CCR_ADSIZE_Bits16 = 0x1
	// 24-bit address
	OctoSPI_CCR_ADSIZE_Bits24 = 0x2
	// 32-bit address
	OctoSPI_CCR_ADSIZE_Bits32 = 0x3
	// Position of ABMODE field.
	OctoSPI_CCR_ABMODE_Pos = 0x10
	// Bit mask of ABMODE field.
	OctoSPI_CCR_ABMODE_Msk = 0x70000
	// No alternate bytes
	OctoSPI_CCR_ABMODE_NoAlternateBytes = 0x0
	// Alternate bytes on a single line
	OctoSPI_CCR_ABMODE_SingleLine = 0x1
	// Alternate bytes on two lines
	OctoSPI_CCR_ABMODE_TwoLines = 0x2
	// Alternate bytes on four lines
	OctoSPI_CCR_ABMODE_FourLines = 0x3
	// Alternate bytes on eight lines
	OctoSPI_CCR_ABMODE_EightLines = 0x4
	// Position of ABDTR field.
	OctoSPI_CCR_ABDTR_Pos = 0x13
	// Bit mask of ABDTR field.
	OctoSPI_CCR_ABDTR_Msk = 0x80000
	// Bit ABDTR.
	OctoSPI_CCR_ABDTR = 0x80000
	// DTR mode disabled for alternate bytes phase
	OctoSPI_CCR_ABDTR_Disabled = 0x0
	// DTR mode enabled for alternate bytes phase
	OctoSPI_CCR_ABDTR_Enabled = 0x1
	// Position of ABSIZE field.
	OctoSPI_CCR_ABSIZE_Pos = 0x14
	// Bit mask of ABSIZE field.
	OctoSPI_CCR_ABSIZE_Msk = 0x300000
	// 8-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits8 = 0x0
	// 16-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits16 = 0x1
	// 24-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits24 = 0x2
	// 32-bit alternate bytes
	OctoSPI_CCR_ABSIZE_Bits32 = 0x3
	// Position of DMODE field.
	OctoSPI_CCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	OctoSPI_CCR_DMODE_Msk = 0x7000000
	// No data
	OctoSPI_CCR_DMODE_NoData = 0x0
	// Data on a single line
	OctoSPI_CCR_DMODE_SingleLine = 0x1
	// Data on two lines
	OctoSPI_CCR_DMODE_TwoLines = 0x2
	// Data on four lines
	OctoSPI_CCR_DMODE_FourLines = 0x3
	// Data on eight lines
	OctoSPI_CCR_DMODE_EightLines = 0x4
	// Position of DDTR field.
	OctoSPI_CCR_DDTR_Pos = 0x1b
	// Bit mask of DDTR field.
	OctoSPI_CCR_DDTR_Msk = 0x8000000
	// Bit DDTR.
	OctoSPI_CCR_DDTR = 0x8000000
	// DTR mode disabled for data phase
	OctoSPI_CCR_DDTR_Disabled = 0x0
	// DTR mode enabled for data phase
	OctoSPI_CCR_DDTR_Enabled = 0x1
	// Position of DQSE field.
	OctoSPI_CCR_DQSE_Pos = 0x1d
	// Bit mask of DQSE field.
	OctoSPI_CCR_DQSE_Msk = 0x20000000
	// Bit DQSE.
	OctoSPI_CCR_DQSE = 0x20000000
	// DQS disabled
	OctoSPI_CCR_DQSE_Disabled = 0x0
	// DQS enabled
	OctoSPI_CCR_DQSE_Enabled = 0x1
	// Position of SIOO field.
	OctoSPI_CCR_SIOO_Pos = 0x1f
	// Bit mask of SIOO field.
	OctoSPI_CCR_SIOO_Msk = 0x80000000
	// Bit SIOO.
	OctoSPI_CCR_SIOO = 0x80000000
	// Send instruction on every transaction
	OctoSPI_CCR_SIOO_SendEveryTransaction = 0x0
	// Send instruction only for the first command
	OctoSPI_CCR_SIOO_SendOnlyFirstCmd = 0x1

	// TCR: timing configuration register
	// Position of DCYC field.
	OctoSPI_TCR_DCYC_Pos = 0x0
	// Bit mask of DCYC field.
	OctoSPI_TCR_DCYC_Msk = 0x1f
	// Position of DHQC field.
	OctoSPI_TCR_DHQC_Pos = 0x1c
	// Bit mask of DHQC field.
	OctoSPI_TCR_DHQC_Msk = 0x10000000
	// Bit DHQC.
	OctoSPI_TCR_DHQC = 0x10000000
	// No delay hold
	OctoSPI_TCR_DHQC_NoDelay = 0x0
	// 1/4 cycle hold
	OctoSPI_TCR_DHQC_QuarterCycleHold = 0x1
	// Position of SSHIFT field.
	OctoSPI_TCR_SSHIFT_Pos = 0x1e
	// Bit mask of SSHIFT field.
	OctoSPI_TCR_SSHIFT_Msk = 0x40000000
	// Bit SSHIFT.
	OctoSPI_TCR_SSHIFT = 0x40000000
	// No shift
	OctoSPI_TCR_SSHIFT_NoShift = 0x0
	// 1/2 cycle shift
	OctoSPI_TCR_SSHIFT_HalfCycleShift = 0x1

	// IR: instruction register
	// Position of INSTRUCTION field.
	OctoSPI_IR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	OctoSPI_IR_INSTRUCTION_Msk = 0xffffffff

	// ABR: alternate bytes register
	// Position of ALTERNATE field.
	OctoSPI_ABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	OctoSPI_ABR_ALTERNATE_Msk = 0xffffffff

	// LPTR: low-power timeout register
	// Position of TIMEOUT field.
	OctoSPI_LPTR_TIMEOUT_Pos = 0x0
	// Bit mask of TIMEOUT field.
	OctoSPI_LPTR_TIMEOUT_Msk = 0xffff

	// WPCCR: wrap communication configuration register
	// Position of IMODE field.
	OctoSPI_WPCCR_IMODE_Pos = 0x0
	// Bit mask of IMODE field.
	OctoSPI_WPCCR_IMODE_Msk = 0x7
	// No instruction
	OctoSPI_WPCCR_IMODE_NoInstruction = 0x0
	// Instruction on a single line
	OctoSPI_WPCCR_IMODE_SingleLine = 0x1
	// Instruction on two lines
	OctoSPI_WPCCR_IMODE_TwoLines = 0x2
	// Instruction on four lines
	OctoSPI_WPCCR_IMODE_FourLines = 0x3
	// Instruction on eight lines
	OctoSPI_WPCCR_IMODE_EightLines = 0x4
	// Position of IDTR field.
	OctoSPI_WPCCR_IDTR_Pos = 0x3
	// Bit mask of IDTR field.
	OctoSPI_WPCCR_IDTR_Msk = 0x8
	// Bit IDTR.
	OctoSPI_WPCCR_IDTR = 0x8
	// DTR mode disabled for instruction phase
	OctoSPI_WPCCR_IDTR_Disabled = 0x0
	// DTR mode enabled for instruction phase
	OctoSPI_WPCCR_IDTR_Enabled = 0x1
	// Position of ISIZE field.
	OctoSPI_WPCCR_ISIZE_Pos = 0x4
	// Bit mask of ISIZE field.
	OctoSPI_WPCCR_ISIZE_Msk = 0x30
	// 8-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits8 = 0x0
	// 16-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits16 = 0x1
	// 24-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits24 = 0x2
	// 32-bit instruction
	OctoSPI_WPCCR_ISIZE_Bits32 = 0x3
	// Position of ADMODE field.
	OctoSPI_WPCCR_ADMODE_Pos = 0x8
	// Bit mask of ADMODE field.
	OctoSPI_WPCCR_ADMODE_Msk = 0x700
	// No address
	OctoSPI_WPCCR_ADMODE_NoAddress = 0x0
	// Address on a single line
	OctoSPI_WPCCR_ADMODE_SingleLine = 0x1
	// Address on two lines
	OctoSPI_WPCCR_ADMODE_TwoLines = 0x2
	// Address on four lines
	OctoSPI_WPCCR_ADMODE_FourLines = 0x3
	// Address on eight lines
	OctoSPI_WPCCR_ADMODE_EightLines = 0x4
	// Position of ADDTR field.
	OctoSPI_WPCCR_ADDTR_Pos = 0xb
	// Bit mask of ADDTR field.
	OctoSPI_WPCCR_ADDTR_Msk = 0x800
	// Bit ADDTR.
	OctoSPI_WPCCR_ADDTR = 0x800
	// DTR mode disabled for address phase
	OctoSPI_WPCCR_ADDTR_Disabled = 0x0
	// DTR mode enabled for address phase
	OctoSPI_WPCCR_ADDTR_Enabled = 0x1
	// Position of ADSIZE field.
	OctoSPI_WPCCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	OctoSPI_WPCCR_ADSIZE_Msk = 0x3000
	// 8-bit address
	OctoSPI_WPCCR_ADSIZE_Bits8 = 0x0
	// 16-bit address
	OctoSPI_WPCCR_ADSIZE_Bits16 = 0x1
	// 24-bit address
	OctoSPI_WPCCR_ADSIZE_Bits24 = 0x2
	// 32-bit address
	OctoSPI_WPCCR_ADSIZE_Bits32 = 0x3
	// Position of ABMODE field.
	OctoSPI_WPCCR_ABMODE_Pos = 0x10
	// Bit mask of ABMODE field.
	OctoSPI_WPCCR_ABMODE_Msk = 0x70000
	// No alternate bytes
	OctoSPI_WPCCR_ABMODE_NoAlternateBytes = 0x0
	// Alternate bytes on a single line
	OctoSPI_WPCCR_ABMODE_SingleLine = 0x1
	// Alternate bytes on two lines
	OctoSPI_WPCCR_ABMODE_TwoLines = 0x2
	// Alternate bytes on four lines
	OctoSPI_WPCCR_ABMODE_FourLines = 0x3
	// Alternate bytes on eight lines
	OctoSPI_WPCCR_ABMODE_EightLines = 0x4
	// Position of ABDTR field.
	OctoSPI_WPCCR_ABDTR_Pos = 0x13
	// Bit mask of ABDTR field.
	OctoSPI_WPCCR_ABDTR_Msk = 0x80000
	// Bit ABDTR.
	OctoSPI_WPCCR_ABDTR = 0x80000
	// DTR mode disabled for alternate bytes phase
	OctoSPI_WPCCR_ABDTR_Disabled = 0x0
	// DTR mode enabled for alternate bytes phase
	OctoSPI_WPCCR_ABDTR_Enabled = 0x1
	// Position of ABSIZE field.
	OctoSPI_WPCCR_ABSIZE_Pos = 0x14
	// Bit mask of ABSIZE field.
	OctoSPI_WPCCR_ABSIZE_Msk = 0x300000
	// 8-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits8 = 0x0
	// 16-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits16 = 0x1
	// 24-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits24 = 0x2
	// 32-bit alternate bytes
	OctoSPI_WPCCR_ABSIZE_Bits32 = 0x3
	// Position of DMODE field.
	OctoSPI_WPCCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	OctoSPI_WPCCR_DMODE_Msk = 0x7000000
	// No data
	OctoSPI_WPCCR_DMODE_NoData = 0x0
	// Data on a single line
	OctoSPI_WPCCR_DMODE_SingleLine = 0x1
	// Data on two lines
	OctoSPI_WPCCR_DMODE_TwoLines = 0x2
	// Data on four lines
	OctoSPI_WPCCR_DMODE_FourLines = 0x3
	// Data on eight lines
	OctoSPI_WPCCR_DMODE_EightLines = 0x4
	// Position of DDTR field.
	OctoSPI_WPCCR_DDTR_Pos = 0x1b
	// Bit mask of DDTR field.
	OctoSPI_WPCCR_DDTR_Msk = 0x8000000
	// Bit DDTR.
	OctoSPI_WPCCR_DDTR = 0x8000000
	// DTR mode disabled for data phase
	OctoSPI_WPCCR_DDTR_Disabled = 0x0
	// DTR mode enabled for data phase
	OctoSPI_WPCCR_DDTR_Enabled = 0x1
	// Position of DQSE field.
	OctoSPI_WPCCR_DQSE_Pos = 0x1d
	// Bit mask of DQSE field.
	OctoSPI_WPCCR_DQSE_Msk = 0x20000000
	// Bit DQSE.
	OctoSPI_WPCCR_DQSE = 0x20000000
	// DQS disabled
	OctoSPI_WPCCR_DQSE_Disabled = 0x0
	// DQS enabled
	OctoSPI_WPCCR_DQSE_Enabled = 0x1

	// WPTCR: wrap timing configuration register
	// Position of DCYC field.
	OctoSPI_WPTCR_DCYC_Pos = 0x0
	// Bit mask of DCYC field.
	OctoSPI_WPTCR_DCYC_Msk = 0x1f
	// Position of DHQC field.
	OctoSPI_WPTCR_DHQC_Pos = 0x1c
	// Bit mask of DHQC field.
	OctoSPI_WPTCR_DHQC_Msk = 0x10000000
	// Bit DHQC.
	OctoSPI_WPTCR_DHQC = 0x10000000
	// No delay hold
	OctoSPI_WPTCR_DHQC_NoDelay = 0x0
	// 1/4 cycle hold
	OctoSPI_WPTCR_DHQC_QuarterCycleHold = 0x1
	// Position of SSHIFT field.
	OctoSPI_WPTCR_SSHIFT_Pos = 0x1e
	// Bit mask of SSHIFT field.
	OctoSPI_WPTCR_SSHIFT_Msk = 0x40000000
	// Bit SSHIFT.
	OctoSPI_WPTCR_SSHIFT = 0x40000000
	// No shift
	OctoSPI_WPTCR_SSHIFT_NoShift = 0x0
	// 1/2 cycle shift
	OctoSPI_WPTCR_SSHIFT_HalfCycleShift = 0x1

	// WPIR: wrap instruction register
	// Position of INSTRUCTION field.
	OctoSPI_WPIR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	OctoSPI_WPIR_INSTRUCTION_Msk = 0xffffffff

	// WPABR: wrap alternate bytes register
	// Position of ALTERNATE field.
	OctoSPI_WPABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	OctoSPI_WPABR_ALTERNATE_Msk = 0xffffffff

	// WCCR: WCCR
	// Position of IMODE field.
	OctoSPI_WCCR_IMODE_Pos = 0x0
	// Bit mask of IMODE field.
	OctoSPI_WCCR_IMODE_Msk = 0x7
	// No instruction
	OctoSPI_WCCR_IMODE_NoInstruction = 0x0
	// Instruction on a single line
	OctoSPI_WCCR_IMODE_SingleLine = 0x1
	// Instruction on two lines
	OctoSPI_WCCR_IMODE_TwoLines = 0x2
	// Instruction on four lines
	OctoSPI_WCCR_IMODE_FourLines = 0x3
	// Instruction on eight lines
	OctoSPI_WCCR_IMODE_EightLines = 0x4
	// Position of IDTR field.
	OctoSPI_WCCR_IDTR_Pos = 0x3
	// Bit mask of IDTR field.
	OctoSPI_WCCR_IDTR_Msk = 0x8
	// Bit IDTR.
	OctoSPI_WCCR_IDTR = 0x8
	// DTR mode disabled for instruction phase
	OctoSPI_WCCR_IDTR_Disabled = 0x0
	// DTR mode enabled for instruction phase
	OctoSPI_WCCR_IDTR_Enabled = 0x1
	// Position of ISIZE field.
	OctoSPI_WCCR_ISIZE_Pos = 0x4
	// Bit mask of ISIZE field.
	OctoSPI_WCCR_ISIZE_Msk = 0x30
	// 8-bit instruction
	OctoSPI_WCCR_ISIZE_Bits8 = 0x0
	// 16-bit instruction
	OctoSPI_WCCR_ISIZE_Bits16 = 0x1
	// 24-bit instruction
	OctoSPI_WCCR_ISIZE_Bits24 = 0x2
	// 32-bit instruction
	OctoSPI_WCCR_ISIZE_Bits32 = 0x3
	// Position of ADMODE field.
	OctoSPI_WCCR_ADMODE_Pos = 0x8
	// Bit mask of ADMODE field.
	OctoSPI_WCCR_ADMODE_Msk = 0x700
	// No address
	OctoSPI_WCCR_ADMODE_NoAddress = 0x0
	// Address on a single line
	OctoSPI_WCCR_ADMODE_SingleLine = 0x1
	// Address on two lines
	OctoSPI_WCCR_ADMODE_TwoLines = 0x2
	// Address on four lines
	OctoSPI_WCCR_ADMODE_FourLines = 0x3
	// Address on eight lines
	OctoSPI_WCCR_ADMODE_EightLines = 0x4
	// Position of ADDTR field.
	OctoSPI_WCCR_ADDTR_Pos = 0xb
	// Bit mask of ADDTR field.
	OctoSPI_WCCR_ADDTR_Msk = 0x800
	// Bit ADDTR.
	OctoSPI_WCCR_ADDTR = 0x800
	// DTR mode disabled for address phase
	OctoSPI_WCCR_ADDTR_Disabled = 0x0
	// DTR mode enabled for address phase
	OctoSPI_WCCR_ADDTR_Enabled = 0x1
	// Position of ADSIZE field.
	OctoSPI_WCCR_ADSIZE_Pos = 0xc
	// Bit mask of ADSIZE field.
	OctoSPI_WCCR_ADSIZE_Msk = 0x3000
	// 8-bit address
	OctoSPI_WCCR_ADSIZE_Bits8 = 0x0
	// 16-bit address
	OctoSPI_WCCR_ADSIZE_Bits16 = 0x1
	// 24-bit address
	OctoSPI_WCCR_ADSIZE_Bits24 = 0x2
	// 32-bit address
	OctoSPI_WCCR_ADSIZE_Bits32 = 0x3
	// Position of ABMODE field.
	OctoSPI_WCCR_ABMODE_Pos = 0x10
	// Bit mask of ABMODE field.
	OctoSPI_WCCR_ABMODE_Msk = 0x70000
	// No alternate bytes
	OctoSPI_WCCR_ABMODE_NoAlternateBytes = 0x0
	// Alternate bytes on a single line
	OctoSPI_WCCR_ABMODE_SingleLine = 0x1
	// Alternate bytes on two lines
	OctoSPI_WCCR_ABMODE_TwoLines = 0x2
	// Alternate bytes on four lines
	OctoSPI_WCCR_ABMODE_FourLines = 0x3
	// Alternate bytes on eight lines
	OctoSPI_WCCR_ABMODE_EightLines = 0x4
	// Position of ABDTR field.
	OctoSPI_WCCR_ABDTR_Pos = 0x13
	// Bit mask of ABDTR field.
	OctoSPI_WCCR_ABDTR_Msk = 0x80000
	// Bit ABDTR.
	OctoSPI_WCCR_ABDTR = 0x80000
	// DTR mode disabled for alternate bytes phase
	OctoSPI_WCCR_ABDTR_Disabled = 0x0
	// DTR mode enabled for alternate bytes phase
	OctoSPI_WCCR_ABDTR_Enabled = 0x1
	// Position of ABSIZE field.
	OctoSPI_WCCR_ABSIZE_Pos = 0x14
	// Bit mask of ABSIZE field.
	OctoSPI_WCCR_ABSIZE_Msk = 0x300000
	// 8-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits8 = 0x0
	// 16-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits16 = 0x1
	// 24-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits24 = 0x2
	// 32-bit alternate bytes
	OctoSPI_WCCR_ABSIZE_Bits32 = 0x3
	// Position of DMODE field.
	OctoSPI_WCCR_DMODE_Pos = 0x18
	// Bit mask of DMODE field.
	OctoSPI_WCCR_DMODE_Msk = 0x7000000
	// No data
	OctoSPI_WCCR_DMODE_NoData = 0x0
	// Data on a single line
	OctoSPI_WCCR_DMODE_SingleLine = 0x1
	// Data on two lines
	OctoSPI_WCCR_DMODE_TwoLines = 0x2
	// Data on four lines
	OctoSPI_WCCR_DMODE_FourLines = 0x3
	// Data on eight lines
	OctoSPI_WCCR_DMODE_EightLines = 0x4
	// Position of DDTR field.
	OctoSPI_WCCR_DDTR_Pos = 0x1b
	// Bit mask of DDTR field.
	OctoSPI_WCCR_DDTR_Msk = 0x8000000
	// Bit DDTR.
	OctoSPI_WCCR_DDTR = 0x8000000
	// DTR mode disabled for data phase
	OctoSPI_WCCR_DDTR_Disabled = 0x0
	// DTR mode enabled for data phase
	OctoSPI_WCCR_DDTR_Enabled = 0x1
	// Position of DQSE field.
	OctoSPI_WCCR_DQSE_Pos = 0x1d
	// Bit mask of DQSE field.
	OctoSPI_WCCR_DQSE_Msk = 0x20000000
	// Bit DQSE.
	OctoSPI_WCCR_DQSE = 0x20000000
	// DQS disabled
	OctoSPI_WCCR_DQSE_Disabled = 0x0
	// DQS enabled
	OctoSPI_WCCR_DQSE_Enabled = 0x1

	// WTCR: WTCR
	// Position of DCYC field.
	OctoSPI_WTCR_DCYC_Pos = 0x0
	// Bit mask of DCYC field.
	OctoSPI_WTCR_DCYC_Msk = 0x1f

	// WIR: WIR
	// Position of INSTRUCTION field.
	OctoSPI_WIR_INSTRUCTION_Pos = 0x0
	// Bit mask of INSTRUCTION field.
	OctoSPI_WIR_INSTRUCTION_Msk = 0xffffffff

	// WABR: write alternate bytes register
	// Position of ALTERNATE field.
	OctoSPI_WABR_ALTERNATE_Pos = 0x0
	// Bit mask of ALTERNATE field.
	OctoSPI_WABR_ALTERNATE_Msk = 0xffffffff

	// HLCR: HyperBus latency configuration register
	// Position of LM field.
	OctoSPI_HLCR_LM_Pos = 0x0
	// Bit mask of LM field.
	OctoSPI_HLCR_LM_Msk = 0x1
	// Bit LM.
	OctoSPI_HLCR_LM = 0x1
	// Variable initial latency
	OctoSPI_HLCR_LM_Variable = 0x0
	// Fixed latency
	OctoSPI_HLCR_LM_Fixed = 0x1
	// Position of WZL field.
	OctoSPI_HLCR_WZL_Pos = 0x1
	// Bit mask of WZL field.
	OctoSPI_HLCR_WZL_Msk = 0x2
	// Bit WZL.
	OctoSPI_HLCR_WZL = 0x2
	// Latency on write accesses
	OctoSPI_HLCR_WZL_Disabled = 0x0
	// No latency on write accesses
	OctoSPI_HLCR_WZL_Enabled = 0x1
	// Position of TACC field.
	OctoSPI_HLCR_TACC_Pos = 0x8
	// Bit mask of TACC field.
	OctoSPI_HLCR_TACC_Msk = 0xff00
	// Position of TRWR field.
	OctoSPI_HLCR_TRWR_Pos = 0x10
	// Bit mask of TRWR field.
	OctoSPI_HLCR_TRWR_Msk = 0xff0000
)

// Constants for OPAMP: Operational amplifiers
const (
	// OPAMP1_CSR: OPAMP1 control/status register
	// Position of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Pos = 0x0
	// Bit mask of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Msk = 0x1
	// Bit OPAEN.
	OPAMP_OPAMP1_CSR_OPAEN = 0x1
	// Position of OPALPM field.
	OPAMP_OPAMP1_CSR_OPALPM_Pos = 0x1
	// Bit mask of OPALPM field.
	OPAMP_OPAMP1_CSR_OPALPM_Msk = 0x2
	// Bit OPALPM.
	OPAMP_OPAMP1_CSR_OPALPM = 0x2
	// Position of OPAMODE field.
	OPAMP_OPAMP1_CSR_OPAMODE_Pos = 0x2
	// Bit mask of OPAMODE field.
	OPAMP_OPAMP1_CSR_OPAMODE_Msk = 0xc
	// Position of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Pos = 0x4
	// Bit mask of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Msk = 0x30
	// Position of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Pos = 0x8
	// Bit mask of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Msk = 0x300
	// Position of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Pos = 0xa
	// Bit mask of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Msk = 0x400
	// Bit VP_SEL.
	OPAMP_OPAMP1_CSR_VP_SEL = 0x400
	// Position of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Pos = 0xc
	// Bit mask of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Msk = 0x1000
	// Bit CALON.
	OPAMP_OPAMP1_CSR_CALON = 0x1000
	// Position of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Pos = 0xd
	// Bit mask of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Msk = 0x2000
	// Bit CALSEL.
	OPAMP_OPAMP1_CSR_CALSEL = 0x2000
	// Position of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Pos = 0xe
	// Bit mask of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Msk = 0x4000
	// Bit USERTRIM.
	OPAMP_OPAMP1_CSR_USERTRIM = 0x4000
	// Position of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Pos = 0xf
	// Bit mask of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Msk = 0x8000
	// Bit CALOUT.
	OPAMP_OPAMP1_CSR_CALOUT = 0x8000
	// Position of OPA_RANGE field.
	OPAMP_OPAMP1_CSR_OPA_RANGE_Pos = 0x1f
	// Bit mask of OPA_RANGE field.
	OPAMP_OPAMP1_CSR_OPA_RANGE_Msk = 0x80000000
	// Bit OPA_RANGE.
	OPAMP_OPAMP1_CSR_OPA_RANGE = 0x80000000

	// OPAMP1_OTR: OPAMP1 offset trimming register in normal mode
	// Position of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Pos = 0x0
	// Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Msk = 0x1f
	// Position of TRIMOFFSETP field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Pos = 0x8
	// Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Msk = 0x1f00

	// OPAMP1_LPOTR: OPAMP1 offset trimming register in low-powe mode
	// Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETN_Pos = 0x0
	// Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETN_Msk = 0x1f
	// Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETP_Pos = 0x8
	// Bit mask of TRIMLPOFFSETP field.
	OPAMP_OPAMP1_LPOTR_TRIMLPOFFSETP_Msk = 0x1f00

	// OPAMP2_CRS: OPAMP2 control/status register
	// Position of OPAEN field.
	OPAMP_OPAMP2_CRS_OPAEN_Pos = 0x0
	// Bit mask of OPAEN field.
	OPAMP_OPAMP2_CRS_OPAEN_Msk = 0x1
	// Bit OPAEN.
	OPAMP_OPAMP2_CRS_OPAEN = 0x1
	// Position of OPALPM field.
	OPAMP_OPAMP2_CRS_OPALPM_Pos = 0x1
	// Bit mask of OPALPM field.
	OPAMP_OPAMP2_CRS_OPALPM_Msk = 0x2
	// Bit OPALPM.
	OPAMP_OPAMP2_CRS_OPALPM = 0x2
	// Position of OPAMODE field.
	OPAMP_OPAMP2_CRS_OPAMODE_Pos = 0x2
	// Bit mask of OPAMODE field.
	OPAMP_OPAMP2_CRS_OPAMODE_Msk = 0xc
	// Position of PGA_GAIN field.
	OPAMP_OPAMP2_CRS_PGA_GAIN_Pos = 0x4
	// Bit mask of PGA_GAIN field.
	OPAMP_OPAMP2_CRS_PGA_GAIN_Msk = 0x30
	// Position of VM_SEL field.
	OPAMP_OPAMP2_CRS_VM_SEL_Pos = 0x8
	// Bit mask of VM_SEL field.
	OPAMP_OPAMP2_CRS_VM_SEL_Msk = 0x300
	// Position of VP_SEL field.
	OPAMP_OPAMP2_CRS_VP_SEL_Pos = 0xa
	// Bit mask of VP_SEL field.
	OPAMP_OPAMP2_CRS_VP_SEL_Msk = 0x400
	// Bit VP_SEL.
	OPAMP_OPAMP2_CRS_VP_SEL = 0x400
	// Position of CALON field.
	OPAMP_OPAMP2_CRS_CALON_Pos = 0xc
	// Bit mask of CALON field.
	OPAMP_OPAMP2_CRS_CALON_Msk = 0x1000
	// Bit CALON.
	OPAMP_OPAMP2_CRS_CALON = 0x1000
	// Position of CALSEL field.
	OPAMP_OPAMP2_CRS_CALSEL_Pos = 0xd
	// Bit mask of CALSEL field.
	OPAMP_OPAMP2_CRS_CALSEL_Msk = 0x2000
	// Bit CALSEL.
	OPAMP_OPAMP2_CRS_CALSEL = 0x2000
	// Position of USERTRIM field.
	OPAMP_OPAMP2_CRS_USERTRIM_Pos = 0xe
	// Bit mask of USERTRIM field.
	OPAMP_OPAMP2_CRS_USERTRIM_Msk = 0x4000
	// Bit USERTRIM.
	OPAMP_OPAMP2_CRS_USERTRIM = 0x4000
	// Position of CALOUT field.
	OPAMP_OPAMP2_CRS_CALOUT_Pos = 0xf
	// Bit mask of CALOUT field.
	OPAMP_OPAMP2_CRS_CALOUT_Msk = 0x8000
	// Bit CALOUT.
	OPAMP_OPAMP2_CRS_CALOUT = 0x8000

	// OPAMP2_OTR: OPAMP2 offset trimming register in normal mode
	// Position of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Pos = 0x0
	// Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Msk = 0x1f
	// Position of TRIMOFFSETP field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Pos = 0x8
	// Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Msk = 0x1f00

	// OPAMP2_LPOTR: OPAMP2 offset trimming register in low-power mode
	// Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETN_Pos = 0x0
	// Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETN_Msk = 0x1f
	// Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETP_Pos = 0x8
	// Bit mask of TRIMLPOFFSETP field.
	OPAMP_OPAMP2_LPOTR_TRIMLPOFFSETP_Msk = 0x1f00
)

// Constants for PWR: Power control
const (
	// CR1: Power control register 1
	// Position of LPR field.
	PWR_CR1_LPR_Pos = 0xe
	// Bit mask of LPR field.
	PWR_CR1_LPR_Msk = 0x4000
	// Bit LPR.
	PWR_CR1_LPR = 0x4000
	// Position of VOS field.
	PWR_CR1_VOS_Pos = 0x9
	// Bit mask of VOS field.
	PWR_CR1_VOS_Msk = 0x600
	// Position of DBP field.
	PWR_CR1_DBP_Pos = 0x8
	// Bit mask of DBP field.
	PWR_CR1_DBP_Msk = 0x100
	// Bit DBP.
	PWR_CR1_DBP = 0x100
	// Position of LPMS field.
	PWR_CR1_LPMS_Pos = 0x0
	// Bit mask of LPMS field.
	PWR_CR1_LPMS_Msk = 0x7

	// CR2: Power control register 2
	// Position of USV field.
	PWR_CR2_USV_Pos = 0xa
	// Bit mask of USV field.
	PWR_CR2_USV_Msk = 0x400
	// Bit USV.
	PWR_CR2_USV = 0x400
	// Position of IOSV field.
	PWR_CR2_IOSV_Pos = 0x9
	// Bit mask of IOSV field.
	PWR_CR2_IOSV_Msk = 0x200
	// Bit IOSV.
	PWR_CR2_IOSV = 0x200
	// Position of PVME4 field.
	PWR_CR2_PVME4_Pos = 0x7
	// Bit mask of PVME4 field.
	PWR_CR2_PVME4_Msk = 0x80
	// Bit PVME4.
	PWR_CR2_PVME4 = 0x80
	// Position of PVME3 field.
	PWR_CR2_PVME3_Pos = 0x6
	// Bit mask of PVME3 field.
	PWR_CR2_PVME3_Msk = 0x40
	// Bit PVME3.
	PWR_CR2_PVME3 = 0x40
	// Position of PVME2 field.
	PWR_CR2_PVME2_Pos = 0x5
	// Bit mask of PVME2 field.
	PWR_CR2_PVME2_Msk = 0x20
	// Bit PVME2.
	PWR_CR2_PVME2 = 0x20
	// Position of PVME1 field.
	PWR_CR2_PVME1_Pos = 0x4
	// Bit mask of PVME1 field.
	PWR_CR2_PVME1_Msk = 0x10
	// Bit PVME1.
	PWR_CR2_PVME1 = 0x10
	// Position of PLS field.
	PWR_CR2_PLS_Pos = 0x1
	// Bit mask of PLS field.
	PWR_CR2_PLS_Msk = 0xe
	// Position of PVDE field.
	PWR_CR2_PVDE_Pos = 0x0
	// Bit mask of PVDE field.
	PWR_CR2_PVDE_Msk = 0x1
	// Bit PVDE.
	PWR_CR2_PVDE = 0x1

	// CR3: Power control register 3
	// Position of UCPD_DBDIS field.
	PWR_CR3_UCPD_DBDIS_Pos = 0xe
	// Bit mask of UCPD_DBDIS field.
	PWR_CR3_UCPD_DBDIS_Msk = 0x4000
	// Bit UCPD_DBDIS.
	PWR_CR3_UCPD_DBDIS = 0x4000
	// Position of UCPD_STDBY field.
	PWR_CR3_UCPD_STDBY_Pos = 0xd
	// Bit mask of UCPD_STDBY field.
	PWR_CR3_UCPD_STDBY_Msk = 0x2000
	// Bit UCPD_STDBY.
	PWR_CR3_UCPD_STDBY = 0x2000
	// Position of ULPMEN field.
	PWR_CR3_ULPMEN_Pos = 0xb
	// Bit mask of ULPMEN field.
	PWR_CR3_ULPMEN_Msk = 0x800
	// Bit ULPMEN.
	PWR_CR3_ULPMEN = 0x800
	// Position of APC field.
	PWR_CR3_APC_Pos = 0xa
	// Bit mask of APC field.
	PWR_CR3_APC_Msk = 0x400
	// Bit APC.
	PWR_CR3_APC = 0x400
	// Position of RRS field.
	PWR_CR3_RRS_Pos = 0x8
	// Bit mask of RRS field.
	PWR_CR3_RRS_Msk = 0x300
	// Position of EWUP5 field.
	PWR_CR3_EWUP5_Pos = 0x4
	// Bit mask of EWUP5 field.
	PWR_CR3_EWUP5_Msk = 0x10
	// Bit EWUP5.
	PWR_CR3_EWUP5 = 0x10
	// Position of EWUP4 field.
	PWR_CR3_EWUP4_Pos = 0x3
	// Bit mask of EWUP4 field.
	PWR_CR3_EWUP4_Msk = 0x8
	// Bit EWUP4.
	PWR_CR3_EWUP4 = 0x8
	// Position of EWUP3 field.
	PWR_CR3_EWUP3_Pos = 0x2
	// Bit mask of EWUP3 field.
	PWR_CR3_EWUP3_Msk = 0x4
	// Bit EWUP3.
	PWR_CR3_EWUP3 = 0x4
	// Position of EWUP2 field.
	PWR_CR3_EWUP2_Pos = 0x1
	// Bit mask of EWUP2 field.
	PWR_CR3_EWUP2_Msk = 0x2
	// Bit EWUP2.
	PWR_CR3_EWUP2 = 0x2
	// Position of EWUP1 field.
	PWR_CR3_EWUP1_Pos = 0x0
	// Bit mask of EWUP1 field.
	PWR_CR3_EWUP1_Msk = 0x1
	// Bit EWUP1.
	PWR_CR3_EWUP1 = 0x1

	// CR4: Power control register 4
	// Position of SMPSLPEN field.
	PWR_CR4_SMPSLPEN_Pos = 0xf
	// Bit mask of SMPSLPEN field.
	PWR_CR4_SMPSLPEN_Msk = 0x8000
	// Bit SMPSLPEN.
	PWR_CR4_SMPSLPEN = 0x8000
	// Position of SMPSFSTEN field.
	PWR_CR4_SMPSFSTEN_Pos = 0xe
	// Bit mask of SMPSFSTEN field.
	PWR_CR4_SMPSFSTEN_Msk = 0x4000
	// Bit SMPSFSTEN.
	PWR_CR4_SMPSFSTEN = 0x4000
	// Position of EXTSMPSEN field.
	PWR_CR4_EXTSMPSEN_Pos = 0xd
	// Bit mask of EXTSMPSEN field.
	PWR_CR4_EXTSMPSEN_Msk = 0x2000
	// Bit EXTSMPSEN.
	PWR_CR4_EXTSMPSEN = 0x2000
	// Position of SMPSBYP field.
	PWR_CR4_SMPSBYP_Pos = 0xc
	// Bit mask of SMPSBYP field.
	PWR_CR4_SMPSBYP_Msk = 0x1000
	// Bit SMPSBYP.
	PWR_CR4_SMPSBYP = 0x1000
	// Position of VBRS field.
	PWR_CR4_VBRS_Pos = 0x9
	// Bit mask of VBRS field.
	PWR_CR4_VBRS_Msk = 0x200
	// Bit VBRS.
	PWR_CR4_VBRS = 0x200
	// Position of VBE field.
	PWR_CR4_VBE_Pos = 0x8
	// Bit mask of VBE field.
	PWR_CR4_VBE_Msk = 0x100
	// Bit VBE.
	PWR_CR4_VBE = 0x100
	// Position of WUPP5 field.
	PWR_CR4_WUPP5_Pos = 0x4
	// Bit mask of WUPP5 field.
	PWR_CR4_WUPP5_Msk = 0x10
	// Bit WUPP5.
	PWR_CR4_WUPP5 = 0x10
	// Position of WUPP4 field.
	PWR_CR4_WUPP4_Pos = 0x3
	// Bit mask of WUPP4 field.
	PWR_CR4_WUPP4_Msk = 0x8
	// Bit WUPP4.
	PWR_CR4_WUPP4 = 0x8
	// Position of WUPP3 field.
	PWR_CR4_WUPP3_Pos = 0x2
	// Bit mask of WUPP3 field.
	PWR_CR4_WUPP3_Msk = 0x4
	// Bit WUPP3.
	PWR_CR4_WUPP3 = 0x4
	// Position of WUPP2 field.
	PWR_CR4_WUPP2_Pos = 0x1
	// Bit mask of WUPP2 field.
	PWR_CR4_WUPP2_Msk = 0x2
	// Bit WUPP2.
	PWR_CR4_WUPP2 = 0x2
	// Position of WUPP1 field.
	PWR_CR4_WUPP1_Pos = 0x0
	// Bit mask of WUPP1 field.
	PWR_CR4_WUPP1_Msk = 0x1
	// Bit WUPP1.
	PWR_CR4_WUPP1 = 0x1

	// SR1: Power status register 1
	// Position of SMPSHPRDY field.
	PWR_SR1_SMPSHPRDY_Pos = 0xf
	// Bit mask of SMPSHPRDY field.
	PWR_SR1_SMPSHPRDY_Msk = 0x8000
	// Bit SMPSHPRDY.
	PWR_SR1_SMPSHPRDY = 0x8000
	// Position of EXTSMPSRDY field.
	PWR_SR1_EXTSMPSRDY_Pos = 0xd
	// Bit mask of EXTSMPSRDY field.
	PWR_SR1_EXTSMPSRDY_Msk = 0x2000
	// Bit EXTSMPSRDY.
	PWR_SR1_EXTSMPSRDY = 0x2000
	// Position of SMPSBYPRDY field.
	PWR_SR1_SMPSBYPRDY_Pos = 0xc
	// Bit mask of SMPSBYPRDY field.
	PWR_SR1_SMPSBYPRDY_Msk = 0x1000
	// Bit SMPSBYPRDY.
	PWR_SR1_SMPSBYPRDY = 0x1000
	// Position of SBF field.
	PWR_SR1_SBF_Pos = 0x8
	// Bit mask of SBF field.
	PWR_SR1_SBF_Msk = 0x100
	// Bit SBF.
	PWR_SR1_SBF = 0x100
	// Position of WUF5 field.
	PWR_SR1_WUF5_Pos = 0x4
	// Bit mask of WUF5 field.
	PWR_SR1_WUF5_Msk = 0x10
	// Bit WUF5.
	PWR_SR1_WUF5 = 0x10
	// Position of WUF4 field.
	PWR_SR1_WUF4_Pos = 0x3
	// Bit mask of WUF4 field.
	PWR_SR1_WUF4_Msk = 0x8
	// Bit WUF4.
	PWR_SR1_WUF4 = 0x8
	// Position of WUF3 field.
	PWR_SR1_WUF3_Pos = 0x2
	// Bit mask of WUF3 field.
	PWR_SR1_WUF3_Msk = 0x4
	// Bit WUF3.
	PWR_SR1_WUF3 = 0x4
	// Position of WUF2 field.
	PWR_SR1_WUF2_Pos = 0x1
	// Bit mask of WUF2 field.
	PWR_SR1_WUF2_Msk = 0x2
	// Bit WUF2.
	PWR_SR1_WUF2 = 0x2
	// Position of WUF1 field.
	PWR_SR1_WUF1_Pos = 0x0
	// Bit mask of WUF1 field.
	PWR_SR1_WUF1_Msk = 0x1
	// Bit WUF1.
	PWR_SR1_WUF1 = 0x1

	// SR2: Power status register 2
	// Position of PVMO4 field.
	PWR_SR2_PVMO4_Pos = 0xf
	// Bit mask of PVMO4 field.
	PWR_SR2_PVMO4_Msk = 0x8000
	// Bit PVMO4.
	PWR_SR2_PVMO4 = 0x8000
	// Position of PVMO3 field.
	PWR_SR2_PVMO3_Pos = 0xe
	// Bit mask of PVMO3 field.
	PWR_SR2_PVMO3_Msk = 0x4000
	// Bit PVMO3.
	PWR_SR2_PVMO3 = 0x4000
	// Position of PVMO2 field.
	PWR_SR2_PVMO2_Pos = 0xd
	// Bit mask of PVMO2 field.
	PWR_SR2_PVMO2_Msk = 0x2000
	// Bit PVMO2.
	PWR_SR2_PVMO2 = 0x2000
	// Position of PVMO1 field.
	PWR_SR2_PVMO1_Pos = 0xc
	// Bit mask of PVMO1 field.
	PWR_SR2_PVMO1_Msk = 0x1000
	// Bit PVMO1.
	PWR_SR2_PVMO1 = 0x1000
	// Position of PVDO field.
	PWR_SR2_PVDO_Pos = 0xb
	// Bit mask of PVDO field.
	PWR_SR2_PVDO_Msk = 0x800
	// Bit PVDO.
	PWR_SR2_PVDO = 0x800
	// Position of VOSF field.
	PWR_SR2_VOSF_Pos = 0xa
	// Bit mask of VOSF field.
	PWR_SR2_VOSF_Msk = 0x400
	// Bit VOSF.
	PWR_SR2_VOSF = 0x400
	// Position of REGLPF field.
	PWR_SR2_REGLPF_Pos = 0x9
	// Bit mask of REGLPF field.
	PWR_SR2_REGLPF_Msk = 0x200
	// Bit REGLPF.
	PWR_SR2_REGLPF = 0x200
	// Position of REGLPS field.
	PWR_SR2_REGLPS_Pos = 0x8
	// Bit mask of REGLPS field.
	PWR_SR2_REGLPS_Msk = 0x100
	// Bit REGLPS.
	PWR_SR2_REGLPS = 0x100

	// SCR: Power status clear register
	// Position of CSBF field.
	PWR_SCR_CSBF_Pos = 0x8
	// Bit mask of CSBF field.
	PWR_SCR_CSBF_Msk = 0x100
	// Bit CSBF.
	PWR_SCR_CSBF = 0x100
	// Position of CWUF5 field.
	PWR_SCR_CWUF5_Pos = 0x4
	// Bit mask of CWUF5 field.
	PWR_SCR_CWUF5_Msk = 0x10
	// Bit CWUF5.
	PWR_SCR_CWUF5 = 0x10
	// Position of CWUF4 field.
	PWR_SCR_CWUF4_Pos = 0x3
	// Bit mask of CWUF4 field.
	PWR_SCR_CWUF4_Msk = 0x8
	// Bit CWUF4.
	PWR_SCR_CWUF4 = 0x8
	// Position of CWUF3 field.
	PWR_SCR_CWUF3_Pos = 0x2
	// Bit mask of CWUF3 field.
	PWR_SCR_CWUF3_Msk = 0x4
	// Bit CWUF3.
	PWR_SCR_CWUF3 = 0x4
	// Position of CWUF2 field.
	PWR_SCR_CWUF2_Pos = 0x1
	// Bit mask of CWUF2 field.
	PWR_SCR_CWUF2_Msk = 0x2
	// Bit CWUF2.
	PWR_SCR_CWUF2 = 0x2
	// Position of CWUF1 field.
	PWR_SCR_CWUF1_Pos = 0x0
	// Bit mask of CWUF1 field.
	PWR_SCR_CWUF1_Msk = 0x1
	// Bit CWUF1.
	PWR_SCR_CWUF1 = 0x1

	// PUCRA: Power Port A pull-up control register
	// Position of PU15 field.
	PWR_PUCRA_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRA_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRA_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRA_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRA_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRA_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRA_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRA_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRA_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRA_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRA_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRA_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRA_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRA_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRA_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRA_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRA_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRA_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRA_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRA_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRA_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRA_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRA_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRA_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRA_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRA_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRA_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRA_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRA_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRA_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRA_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRA_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRA_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRA_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRA_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRA_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRA_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRA_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRA_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRA_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRA_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRA_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRA_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRA_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRA_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRA_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRA_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRA_PU0 = 0x1

	// PDCRA: Power Port A pull-down control register
	// Position of PD15 field.
	PWR_PDCRA_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRA_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRA_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRA_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRA_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRA_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRA_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRA_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRA_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRA_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRA_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRA_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRA_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRA_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRA_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRA_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRA_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRA_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRA_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRA_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRA_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRA_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRA_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRA_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRA_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRA_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRA_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRA_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRA_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRA_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRA_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRA_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRA_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRA_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRA_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRA_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRA_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRA_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRA_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRA_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRA_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRA_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRA_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRA_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRA_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRA_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRA_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRA_PD0 = 0x1

	// PUCRB: Power Port B pull-up control register
	// Position of PU15 field.
	PWR_PUCRB_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRB_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRB_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRB_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRB_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRB_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRB_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRB_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRB_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRB_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRB_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRB_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRB_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRB_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRB_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRB_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRB_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRB_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRB_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRB_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRB_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRB_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRB_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRB_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRB_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRB_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRB_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRB_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRB_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRB_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRB_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRB_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRB_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRB_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRB_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRB_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRB_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRB_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRB_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRB_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRB_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRB_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRB_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRB_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRB_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRB_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRB_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRB_PU0 = 0x1

	// PDCRB: Power Port B pull-down control register
	// Position of PD15 field.
	PWR_PDCRB_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRB_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRB_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRB_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRB_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRB_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRB_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRB_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRB_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRB_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRB_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRB_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRB_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRB_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRB_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRB_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRB_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRB_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRB_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRB_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRB_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRB_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRB_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRB_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRB_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRB_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRB_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRB_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRB_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRB_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRB_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRB_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRB_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRB_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRB_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRB_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRB_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRB_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRB_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRB_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRB_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRB_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRB_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRB_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRB_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRB_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRB_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRB_PD0 = 0x1

	// PUCRC: Power Port C pull-up control register
	// Position of PU15 field.
	PWR_PUCRC_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRC_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRC_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRC_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRC_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRC_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRC_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRC_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRC_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRC_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRC_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRC_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRC_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRC_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRC_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRC_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRC_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRC_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRC_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRC_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRC_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRC_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRC_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRC_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRC_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRC_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRC_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRC_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRC_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRC_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRC_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRC_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRC_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRC_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRC_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRC_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRC_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRC_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRC_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRC_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRC_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRC_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRC_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRC_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRC_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRC_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRC_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRC_PU0 = 0x1

	// PDCRC: Power Port C pull-down control register
	// Position of PD15 field.
	PWR_PDCRC_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRC_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRC_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRC_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRC_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRC_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRC_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRC_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRC_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRC_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRC_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRC_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRC_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRC_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRC_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRC_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRC_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRC_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRC_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRC_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRC_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRC_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRC_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRC_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRC_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRC_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRC_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRC_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRC_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRC_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRC_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRC_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRC_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRC_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRC_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRC_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRC_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRC_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRC_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRC_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRC_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRC_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRC_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRC_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRC_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRC_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRC_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRC_PD0 = 0x1

	// PUCRD: Power Port D pull-up control register
	// Position of PU15 field.
	PWR_PUCRD_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRD_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRD_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRD_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRD_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRD_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRD_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRD_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRD_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRD_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRD_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRD_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRD_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRD_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRD_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRD_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRD_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRD_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRD_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRD_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRD_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRD_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRD_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRD_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRD_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRD_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRD_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRD_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRD_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRD_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRD_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRD_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRD_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRD_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRD_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRD_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRD_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRD_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRD_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRD_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRD_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRD_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRD_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRD_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRD_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRD_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRD_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRD_PU0 = 0x1

	// PDCRD: Power Port D pull-down control register
	// Position of PD15 field.
	PWR_PDCRD_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRD_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRD_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRD_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRD_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRD_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRD_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRD_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRD_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRD_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRD_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRD_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRD_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRD_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRD_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRD_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRD_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRD_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRD_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRD_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRD_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRD_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRD_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRD_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRD_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRD_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRD_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRD_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRD_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRD_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRD_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRD_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRD_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRD_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRD_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRD_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRD_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRD_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRD_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRD_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRD_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRD_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRD_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRD_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRD_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRD_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRD_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRD_PD0 = 0x1

	// PUCRE: Power Port E pull-up control register
	// Position of PU15 field.
	PWR_PUCRE_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRE_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRE_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRE_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRE_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRE_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRE_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRE_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRE_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRE_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRE_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRE_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRE_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRE_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRE_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRE_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRE_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRE_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRE_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRE_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRE_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRE_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRE_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRE_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRE_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRE_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRE_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRE_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRE_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRE_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRE_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRE_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRE_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRE_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRE_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRE_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRE_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRE_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRE_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRE_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRE_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRE_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRE_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRE_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRE_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRE_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRE_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRE_PU0 = 0x1

	// PDCRE: Power Port E pull-down control register
	// Position of PD15 field.
	PWR_PDCRE_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRE_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRE_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRE_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRE_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRE_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRE_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRE_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRE_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRE_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRE_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRE_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRE_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRE_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRE_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRE_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRE_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRE_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRE_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRE_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRE_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRE_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRE_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRE_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRE_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRE_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRE_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRE_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRE_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRE_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRE_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRE_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRE_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRE_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRE_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRE_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRE_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRE_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRE_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRE_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRE_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRE_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRE_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRE_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRE_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRE_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRE_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRE_PD0 = 0x1

	// PUCRF: Power Port F pull-up control register
	// Position of PU15 field.
	PWR_PUCRF_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRF_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRF_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRF_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRF_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRF_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRF_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRF_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRF_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRF_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRF_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRF_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRF_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRF_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRF_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRF_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRF_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRF_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRF_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRF_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRF_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRF_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRF_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRF_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRF_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRF_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRF_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRF_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRF_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRF_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRF_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRF_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRF_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRF_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRF_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRF_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRF_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRF_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRF_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRF_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRF_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRF_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRF_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRF_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRF_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRF_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRF_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRF_PU0 = 0x1

	// PDCRF: Power Port F pull-down control register
	// Position of PD15 field.
	PWR_PDCRF_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRF_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRF_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRF_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRF_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRF_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRF_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRF_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRF_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRF_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRF_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRF_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRF_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRF_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRF_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRF_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRF_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRF_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRF_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRF_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRF_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRF_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRF_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRF_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRF_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRF_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRF_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRF_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRF_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRF_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRF_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRF_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRF_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRF_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRF_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRF_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRF_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRF_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRF_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRF_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRF_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRF_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRF_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRF_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRF_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRF_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRF_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRF_PD0 = 0x1

	// PUCRG: Power Port G pull-up control register
	// Position of PU15 field.
	PWR_PUCRG_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRG_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRG_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRG_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRG_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRG_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRG_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRG_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRG_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRG_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRG_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRG_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRG_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRG_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRG_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRG_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRG_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRG_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRG_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRG_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRG_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRG_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRG_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRG_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRG_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRG_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRG_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRG_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRG_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRG_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRG_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRG_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRG_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRG_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRG_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRG_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRG_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRG_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRG_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRG_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRG_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRG_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRG_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRG_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRG_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRG_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRG_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRG_PU0 = 0x1

	// PDCRG: Power Port G pull-down control register
	// Position of PD15 field.
	PWR_PDCRG_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRG_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRG_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRG_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRG_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRG_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRG_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRG_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRG_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRG_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRG_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRG_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRG_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRG_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRG_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRG_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRG_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRG_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRG_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRG_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRG_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRG_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRG_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRG_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRG_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRG_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRG_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRG_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRG_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRG_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRG_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRG_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRG_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRG_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRG_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRG_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRG_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRG_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRG_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRG_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRG_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRG_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRG_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRG_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRG_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRG_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRG_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRG_PD0 = 0x1

	// PUCRH: Power Port H pull-up control register
	// Position of PU15 field.
	PWR_PUCRH_PU15_Pos = 0xf
	// Bit mask of PU15 field.
	PWR_PUCRH_PU15_Msk = 0x8000
	// Bit PU15.
	PWR_PUCRH_PU15 = 0x8000
	// Position of PU14 field.
	PWR_PUCRH_PU14_Pos = 0xe
	// Bit mask of PU14 field.
	PWR_PUCRH_PU14_Msk = 0x4000
	// Bit PU14.
	PWR_PUCRH_PU14 = 0x4000
	// Position of PU13 field.
	PWR_PUCRH_PU13_Pos = 0xd
	// Bit mask of PU13 field.
	PWR_PUCRH_PU13_Msk = 0x2000
	// Bit PU13.
	PWR_PUCRH_PU13 = 0x2000
	// Position of PU12 field.
	PWR_PUCRH_PU12_Pos = 0xc
	// Bit mask of PU12 field.
	PWR_PUCRH_PU12_Msk = 0x1000
	// Bit PU12.
	PWR_PUCRH_PU12 = 0x1000
	// Position of PU11 field.
	PWR_PUCRH_PU11_Pos = 0xb
	// Bit mask of PU11 field.
	PWR_PUCRH_PU11_Msk = 0x800
	// Bit PU11.
	PWR_PUCRH_PU11 = 0x800
	// Position of PU10 field.
	PWR_PUCRH_PU10_Pos = 0xa
	// Bit mask of PU10 field.
	PWR_PUCRH_PU10_Msk = 0x400
	// Bit PU10.
	PWR_PUCRH_PU10 = 0x400
	// Position of PU9 field.
	PWR_PUCRH_PU9_Pos = 0x9
	// Bit mask of PU9 field.
	PWR_PUCRH_PU9_Msk = 0x200
	// Bit PU9.
	PWR_PUCRH_PU9 = 0x200
	// Position of PU8 field.
	PWR_PUCRH_PU8_Pos = 0x8
	// Bit mask of PU8 field.
	PWR_PUCRH_PU8_Msk = 0x100
	// Bit PU8.
	PWR_PUCRH_PU8 = 0x100
	// Position of PU7 field.
	PWR_PUCRH_PU7_Pos = 0x7
	// Bit mask of PU7 field.
	PWR_PUCRH_PU7_Msk = 0x80
	// Bit PU7.
	PWR_PUCRH_PU7 = 0x80
	// Position of PU6 field.
	PWR_PUCRH_PU6_Pos = 0x6
	// Bit mask of PU6 field.
	PWR_PUCRH_PU6_Msk = 0x40
	// Bit PU6.
	PWR_PUCRH_PU6 = 0x40
	// Position of PU5 field.
	PWR_PUCRH_PU5_Pos = 0x5
	// Bit mask of PU5 field.
	PWR_PUCRH_PU5_Msk = 0x20
	// Bit PU5.
	PWR_PUCRH_PU5 = 0x20
	// Position of PU4 field.
	PWR_PUCRH_PU4_Pos = 0x4
	// Bit mask of PU4 field.
	PWR_PUCRH_PU4_Msk = 0x10
	// Bit PU4.
	PWR_PUCRH_PU4 = 0x10
	// Position of PU3 field.
	PWR_PUCRH_PU3_Pos = 0x3
	// Bit mask of PU3 field.
	PWR_PUCRH_PU3_Msk = 0x8
	// Bit PU3.
	PWR_PUCRH_PU3 = 0x8
	// Position of PU2 field.
	PWR_PUCRH_PU2_Pos = 0x2
	// Bit mask of PU2 field.
	PWR_PUCRH_PU2_Msk = 0x4
	// Bit PU2.
	PWR_PUCRH_PU2 = 0x4
	// Position of PU1 field.
	PWR_PUCRH_PU1_Pos = 0x1
	// Bit mask of PU1 field.
	PWR_PUCRH_PU1_Msk = 0x2
	// Bit PU1.
	PWR_PUCRH_PU1 = 0x2
	// Position of PU0 field.
	PWR_PUCRH_PU0_Pos = 0x0
	// Bit mask of PU0 field.
	PWR_PUCRH_PU0_Msk = 0x1
	// Bit PU0.
	PWR_PUCRH_PU0 = 0x1

	// PDCRH: Power Port H pull-down control register
	// Position of PD15 field.
	PWR_PDCRH_PD15_Pos = 0xf
	// Bit mask of PD15 field.
	PWR_PDCRH_PD15_Msk = 0x8000
	// Bit PD15.
	PWR_PDCRH_PD15 = 0x8000
	// Position of PD14 field.
	PWR_PDCRH_PD14_Pos = 0xe
	// Bit mask of PD14 field.
	PWR_PDCRH_PD14_Msk = 0x4000
	// Bit PD14.
	PWR_PDCRH_PD14 = 0x4000
	// Position of PD13 field.
	PWR_PDCRH_PD13_Pos = 0xd
	// Bit mask of PD13 field.
	PWR_PDCRH_PD13_Msk = 0x2000
	// Bit PD13.
	PWR_PDCRH_PD13 = 0x2000
	// Position of PD12 field.
	PWR_PDCRH_PD12_Pos = 0xc
	// Bit mask of PD12 field.
	PWR_PDCRH_PD12_Msk = 0x1000
	// Bit PD12.
	PWR_PDCRH_PD12 = 0x1000
	// Position of PD11 field.
	PWR_PDCRH_PD11_Pos = 0xb
	// Bit mask of PD11 field.
	PWR_PDCRH_PD11_Msk = 0x800
	// Bit PD11.
	PWR_PDCRH_PD11 = 0x800
	// Position of PD10 field.
	PWR_PDCRH_PD10_Pos = 0xa
	// Bit mask of PD10 field.
	PWR_PDCRH_PD10_Msk = 0x400
	// Bit PD10.
	PWR_PDCRH_PD10 = 0x400
	// Position of PD9 field.
	PWR_PDCRH_PD9_Pos = 0x9
	// Bit mask of PD9 field.
	PWR_PDCRH_PD9_Msk = 0x200
	// Bit PD9.
	PWR_PDCRH_PD9 = 0x200
	// Position of PD8 field.
	PWR_PDCRH_PD8_Pos = 0x8
	// Bit mask of PD8 field.
	PWR_PDCRH_PD8_Msk = 0x100
	// Bit PD8.
	PWR_PDCRH_PD8 = 0x100
	// Position of PD7 field.
	PWR_PDCRH_PD7_Pos = 0x7
	// Bit mask of PD7 field.
	PWR_PDCRH_PD7_Msk = 0x80
	// Bit PD7.
	PWR_PDCRH_PD7 = 0x80
	// Position of PD6 field.
	PWR_PDCRH_PD6_Pos = 0x6
	// Bit mask of PD6 field.
	PWR_PDCRH_PD6_Msk = 0x40
	// Bit PD6.
	PWR_PDCRH_PD6 = 0x40
	// Position of PD5 field.
	PWR_PDCRH_PD5_Pos = 0x5
	// Bit mask of PD5 field.
	PWR_PDCRH_PD5_Msk = 0x20
	// Bit PD5.
	PWR_PDCRH_PD5 = 0x20
	// Position of PD4 field.
	PWR_PDCRH_PD4_Pos = 0x4
	// Bit mask of PD4 field.
	PWR_PDCRH_PD4_Msk = 0x10
	// Bit PD4.
	PWR_PDCRH_PD4 = 0x10
	// Position of PD3 field.
	PWR_PDCRH_PD3_Pos = 0x3
	// Bit mask of PD3 field.
	PWR_PDCRH_PD3_Msk = 0x8
	// Bit PD3.
	PWR_PDCRH_PD3 = 0x8
	// Position of PD2 field.
	PWR_PDCRH_PD2_Pos = 0x2
	// Bit mask of PD2 field.
	PWR_PDCRH_PD2_Msk = 0x4
	// Bit PD2.
	PWR_PDCRH_PD2 = 0x4
	// Position of PD1 field.
	PWR_PDCRH_PD1_Pos = 0x1
	// Bit mask of PD1 field.
	PWR_PDCRH_PD1_Msk = 0x2
	// Bit PD1.
	PWR_PDCRH_PD1 = 0x2
	// Position of PD0 field.
	PWR_PDCRH_PD0_Pos = 0x0
	// Bit mask of PD0 field.
	PWR_PDCRH_PD0_Msk = 0x1
	// Bit PD0.
	PWR_PDCRH_PD0 = 0x1

	// SECCFGR: Power secure configuration register
	// Position of APCSEC field.
	PWR_SECCFGR_APCSEC_Pos = 0xb
	// Bit mask of APCSEC field.
	PWR_SECCFGR_APCSEC_Msk = 0x800
	// Bit APCSEC.
	PWR_SECCFGR_APCSEC = 0x800
	// Position of VBSEC field.
	PWR_SECCFGR_VBSEC_Pos = 0xa
	// Bit mask of VBSEC field.
	PWR_SECCFGR_VBSEC_Msk = 0x400
	// Bit VBSEC.
	PWR_SECCFGR_VBSEC = 0x400
	// Position of VDMSEC field.
	PWR_SECCFGR_VDMSEC_Pos = 0x9
	// Bit mask of VDMSEC field.
	PWR_SECCFGR_VDMSEC_Msk = 0x200
	// Bit VDMSEC.
	PWR_SECCFGR_VDMSEC = 0x200
	// Position of LPMSEC field.
	PWR_SECCFGR_LPMSEC_Pos = 0x8
	// Bit mask of LPMSEC field.
	PWR_SECCFGR_LPMSEC_Msk = 0x100
	// Bit LPMSEC.
	PWR_SECCFGR_LPMSEC = 0x100
	// Position of WUP5SEC field.
	PWR_SECCFGR_WUP5SEC_Pos = 0x4
	// Bit mask of WUP5SEC field.
	PWR_SECCFGR_WUP5SEC_Msk = 0x10
	// Bit WUP5SEC.
	PWR_SECCFGR_WUP5SEC = 0x10
	// Position of WUP4SEC field.
	PWR_SECCFGR_WUP4SEC_Pos = 0x3
	// Bit mask of WUP4SEC field.
	PWR_SECCFGR_WUP4SEC_Msk = 0x8
	// Bit WUP4SEC.
	PWR_SECCFGR_WUP4SEC = 0x8
	// Position of WUP3SEC field.
	PWR_SECCFGR_WUP3SEC_Pos = 0x2
	// Bit mask of WUP3SEC field.
	PWR_SECCFGR_WUP3SEC_Msk = 0x4
	// Bit WUP3SEC.
	PWR_SECCFGR_WUP3SEC = 0x4
	// Position of WUP2SEC field.
	PWR_SECCFGR_WUP2SEC_Pos = 0x1
	// Bit mask of WUP2SEC field.
	PWR_SECCFGR_WUP2SEC_Msk = 0x2
	// Bit WUP2SEC.
	PWR_SECCFGR_WUP2SEC = 0x2
	// Position of WUP1SEC field.
	PWR_SECCFGR_WUP1SEC_Pos = 0x0
	// Bit mask of WUP1SEC field.
	PWR_SECCFGR_WUP1SEC_Msk = 0x1
	// Bit WUP1SEC.
	PWR_SECCFGR_WUP1SEC = 0x1

	// PRIVCFGR: Power privilege configuration register
	// Position of PRIV field.
	PWR_PRIVCFGR_PRIV_Pos = 0x0
	// Bit mask of PRIV field.
	PWR_PRIVCFGR_PRIV_Msk = 0x1
	// Bit PRIV.
	PWR_PRIVCFGR_PRIV = 0x1
)

// Constants for RCC: Reset and clock control
const (
	// CR: Clock control register
	// Position of PRIV field.
	RCC_CR_PRIV_Pos = 0x1f
	// Bit mask of PRIV field.
	RCC_CR_PRIV_Msk = 0x80000000
	// Bit PRIV.
	RCC_CR_PRIV = 0x80000000
	// Position of MSIRDY field.
	RCC_CR_MSIRDY_Pos = 0x1
	// Bit mask of MSIRDY field.
	RCC_CR_MSIRDY_Msk = 0x2
	// Bit MSIRDY.
	RCC_CR_MSIRDY = 0x2
	// Clock not ready
	RCC_CR_MSIRDY_NotReady = 0x0
	// Clock ready
	RCC_CR_MSIRDY_Ready = 0x1
	// Position of PLLSAI2RDY field.
	RCC_CR_PLLSAI2RDY_Pos = 0x1d
	// Bit mask of PLLSAI2RDY field.
	RCC_CR_PLLSAI2RDY_Msk = 0x20000000
	// Bit PLLSAI2RDY.
	RCC_CR_PLLSAI2RDY = 0x20000000
	// Clock not ready
	RCC_CR_PLLSAI2RDY_NotReady = 0x0
	// Clock ready
	RCC_CR_PLLSAI2RDY_Ready = 0x1
	// Position of PLLSAI2ON field.
	RCC_CR_PLLSAI2ON_Pos = 0x1c
	// Bit mask of PLLSAI2ON field.
	RCC_CR_PLLSAI2ON_Msk = 0x10000000
	// Bit PLLSAI2ON.
	RCC_CR_PLLSAI2ON = 0x10000000
	// Position of PLLSAI1RDY field.
	RCC_CR_PLLSAI1RDY_Pos = 0x1b
	// Bit mask of PLLSAI1RDY field.
	RCC_CR_PLLSAI1RDY_Msk = 0x8000000
	// Bit PLLSAI1RDY.
	RCC_CR_PLLSAI1RDY = 0x8000000
	// Clock not ready
	RCC_CR_PLLSAI1RDY_NotReady = 0x0
	// Clock ready
	RCC_CR_PLLSAI1RDY_Ready = 0x1
	// Position of PLLSAI1ON field.
	RCC_CR_PLLSAI1ON_Pos = 0x1a
	// Bit mask of PLLSAI1ON field.
	RCC_CR_PLLSAI1ON_Msk = 0x4000000
	// Bit PLLSAI1ON.
	RCC_CR_PLLSAI1ON = 0x4000000
	// Position of PLLRDY field.
	RCC_CR_PLLRDY_Pos = 0x19
	// Bit mask of PLLRDY field.
	RCC_CR_PLLRDY_Msk = 0x2000000
	// Bit PLLRDY.
	RCC_CR_PLLRDY = 0x2000000
	// Clock not ready
	RCC_CR_PLLRDY_NotReady = 0x0
	// Clock ready
	RCC_CR_PLLRDY_Ready = 0x1
	// Position of HSION field.
	RCC_CR_HSION_Pos = 0x8
	// Bit mask of HSION field.
	RCC_CR_HSION_Msk = 0x100
	// Bit HSION.
	RCC_CR_HSION = 0x100
	// Clock Off
	RCC_CR_HSION_Off = 0x0
	// Clock On
	RCC_CR_HSION_On = 0x1
	// Position of PLLON field.
	RCC_CR_PLLON_Pos = 0x18
	// Bit mask of PLLON field.
	RCC_CR_PLLON_Msk = 0x1000000
	// Bit PLLON.
	RCC_CR_PLLON = 0x1000000
	// Clock Off
	RCC_CR_PLLON_Off = 0x0
	// Clock On
	RCC_CR_PLLON_On = 0x1
	// Position of CSSON field.
	RCC_CR_CSSON_Pos = 0x13
	// Bit mask of CSSON field.
	RCC_CR_CSSON_Msk = 0x80000
	// Bit CSSON.
	RCC_CR_CSSON = 0x80000
	// Clock security system disabled (clock detector OFF)
	RCC_CR_CSSON_Off = 0x0
	// Clock security system enable (clock detector ON if the HSE is ready, OFF if not)
	RCC_CR_CSSON_On = 0x1
	// Position of HSEBYP field.
	RCC_CR_HSEBYP_Pos = 0x12
	// Bit mask of HSEBYP field.
	RCC_CR_HSEBYP_Msk = 0x40000
	// Bit HSEBYP.
	RCC_CR_HSEBYP = 0x40000
	// HSE crystal oscillator not bypassed
	RCC_CR_HSEBYP_NotBypassed = 0x0
	// HSE crystal oscillator bypassed with external clock
	RCC_CR_HSEBYP_Bypassed = 0x1
	// Position of HSERDY field.
	RCC_CR_HSERDY_Pos = 0x11
	// Bit mask of HSERDY field.
	RCC_CR_HSERDY_Msk = 0x20000
	// Bit HSERDY.
	RCC_CR_HSERDY = 0x20000
	// Clock not ready
	RCC_CR_HSERDY_NotReady = 0x0
	// Clock ready
	RCC_CR_HSERDY_Ready = 0x1
	// Position of HSEON field.
	RCC_CR_HSEON_Pos = 0x10
	// Bit mask of HSEON field.
	RCC_CR_HSEON_Msk = 0x10000
	// Bit HSEON.
	RCC_CR_HSEON = 0x10000
	// Clock Off
	RCC_CR_HSEON_Off = 0x0
	// Clock On
	RCC_CR_HSEON_On = 0x1
	// Position of HSIASFS field.
	RCC_CR_HSIASFS_Pos = 0xb
	// Bit mask of HSIASFS field.
	RCC_CR_HSIASFS_Msk = 0x800
	// Bit HSIASFS.
	RCC_CR_HSIASFS = 0x800
	// Position of HSIRDY field.
	RCC_CR_HSIRDY_Pos = 0xa
	// Bit mask of HSIRDY field.
	RCC_CR_HSIRDY_Msk = 0x400
	// Bit HSIRDY.
	RCC_CR_HSIRDY = 0x400
	// Clock not ready
	RCC_CR_HSIRDY_NotReady = 0x0
	// Clock ready
	RCC_CR_HSIRDY_Ready = 0x1
	// Position of HSIKERON field.
	RCC_CR_HSIKERON_Pos = 0x9
	// Bit mask of HSIKERON field.
	RCC_CR_HSIKERON_Msk = 0x200
	// Bit HSIKERON.
	RCC_CR_HSIKERON = 0x200
	// Position of MSIRANGE field.
	RCC_CR_MSIRANGE_Pos = 0x4
	// Bit mask of MSIRANGE field.
	RCC_CR_MSIRANGE_Msk = 0xf0
	// Position of MSIRGSEL field.
	RCC_CR_MSIRGSEL_Pos = 0x3
	// Bit mask of MSIRGSEL field.
	RCC_CR_MSIRGSEL_Msk = 0x8
	// Bit MSIRGSEL.
	RCC_CR_MSIRGSEL = 0x8
	// Position of MSIPLLEN field.
	RCC_CR_MSIPLLEN_Pos = 0x2
	// Bit mask of MSIPLLEN field.
	RCC_CR_MSIPLLEN_Msk = 0x4
	// Bit MSIPLLEN.
	RCC_CR_MSIPLLEN = 0x4
	// Position of MSION field.
	RCC_CR_MSION_Pos = 0x0
	// Bit mask of MSION field.
	RCC_CR_MSION_Msk = 0x1
	// Bit MSION.
	RCC_CR_MSION = 0x1

	// ICSCR: Internal clock sources calibration register
	// Position of HSITRIM field.
	RCC_ICSCR_HSITRIM_Pos = 0x18
	// Bit mask of HSITRIM field.
	RCC_ICSCR_HSITRIM_Msk = 0x7f000000
	// Position of HSICAL field.
	RCC_ICSCR_HSICAL_Pos = 0x10
	// Bit mask of HSICAL field.
	RCC_ICSCR_HSICAL_Msk = 0xff0000
	// Position of MSITRIM field.
	RCC_ICSCR_MSITRIM_Pos = 0x8
	// Bit mask of MSITRIM field.
	RCC_ICSCR_MSITRIM_Msk = 0xff00
	// Position of MSICAL field.
	RCC_ICSCR_MSICAL_Pos = 0x0
	// Bit mask of MSICAL field.
	RCC_ICSCR_MSICAL_Msk = 0xff

	// CFGR: Clock configuration register
	// Position of MCOPRE field.
	RCC_CFGR_MCOPRE_Pos = 0x1c
	// Bit mask of MCOPRE field.
	RCC_CFGR_MCOPRE_Msk = 0x70000000
	// MCO divided by 1
	RCC_CFGR_MCOPRE_Div1 = 0x0
	// MCO divided by 2
	RCC_CFGR_MCOPRE_Div2 = 0x1
	// MCO divided by 4
	RCC_CFGR_MCOPRE_Div4 = 0x2
	// MCO divided by 8
	RCC_CFGR_MCOPRE_Div8 = 0x3
	// MCO divided by 16
	RCC_CFGR_MCOPRE_Div16 = 0x4
	// Position of MCOSEL field.
	RCC_CFGR_MCOSEL_Pos = 0x18
	// Bit mask of MCOSEL field.
	RCC_CFGR_MCOSEL_Msk = 0xf000000
	// MCO output disabled, no clock on MCO
	RCC_CFGR_MCOSEL_None = 0x0
	// SYSCLK system clock selected
	RCC_CFGR_MCOSEL_SYSCLK = 0x1
	// MSI clock selected
	RCC_CFGR_MCOSEL_MSI = 0x2
	// HSI clock selected
	RCC_CFGR_MCOSEL_HSI = 0x3
	// HSE clock selected
	RCC_CFGR_MCOSEL_HSE = 0x4
	// Main PLL clock selected
	RCC_CFGR_MCOSEL_PLL = 0x5
	// LSI clock selected
	RCC_CFGR_MCOSEL_LSI = 0x6
	// LSE clock selected
	RCC_CFGR_MCOSEL_LSE = 0x7
	// Internal HSI48 clock selected
	RCC_CFGR_MCOSEL_HSI48 = 0x8
	// Position of STOPWUCK field.
	RCC_CFGR_STOPWUCK_Pos = 0xf
	// Bit mask of STOPWUCK field.
	RCC_CFGR_STOPWUCK_Msk = 0x8000
	// Bit STOPWUCK.
	RCC_CFGR_STOPWUCK = 0x8000
	// MSI oscillator selected as wakeup from stop clock and CSS backup clock
	RCC_CFGR_STOPWUCK_MSI = 0x0
	// HSI oscillator selected as wakeup from stop clock and CSS backup clock
	RCC_CFGR_STOPWUCK_HSI = 0x1
	// Position of PPRE1 field.
	RCC_CFGR_PPRE1_Pos = 0x8
	// Bit mask of PPRE1 field.
	RCC_CFGR_PPRE1_Msk = 0x700
	// HCLK not divided
	RCC_CFGR_PPRE1_Div1 = 0x0
	// HCLK divided by 2
	RCC_CFGR_PPRE1_Div2 = 0x4
	// HCLK divided by 4
	RCC_CFGR_PPRE1_Div4 = 0x5
	// HCLK divided by 8
	RCC_CFGR_PPRE1_Div8 = 0x6
	// HCLK divided by 16
	RCC_CFGR_PPRE1_Div16 = 0x7
	// Position of PPRE2 field.
	RCC_CFGR_PPRE2_Pos = 0xb
	// Bit mask of PPRE2 field.
	RCC_CFGR_PPRE2_Msk = 0x3800
	// HCLK not divided
	RCC_CFGR_PPRE2_Div1 = 0x0
	// HCLK divided by 2
	RCC_CFGR_PPRE2_Div2 = 0x4
	// HCLK divided by 4
	RCC_CFGR_PPRE2_Div4 = 0x5
	// HCLK divided by 8
	RCC_CFGR_PPRE2_Div8 = 0x6
	// HCLK divided by 16
	RCC_CFGR_PPRE2_Div16 = 0x7
	// Position of HPRE field.
	RCC_CFGR_HPRE_Pos = 0x4
	// Bit mask of HPRE field.
	RCC_CFGR_HPRE_Msk = 0xf0
	// SYSCLK not divided
	RCC_CFGR_HPRE_Div1 = 0x0
	// SYSCLK divided by 2
	RCC_CFGR_HPRE_Div2 = 0x8
	// SYSCLK divided by 4
	RCC_CFGR_HPRE_Div4 = 0x9
	// SYSCLK divided by 8
	RCC_CFGR_HPRE_Div8 = 0xa
	// SYSCLK divided by 16
	RCC_CFGR_HPRE_Div16 = 0xb
	// SYSCLK divided by 64
	RCC_CFGR_HPRE_Div64 = 0xc
	// SYSCLK divided by 128
	RCC_CFGR_HPRE_Div128 = 0xd
	// SYSCLK divided by 256
	RCC_CFGR_HPRE_Div256 = 0xe
	// SYSCLK divided by 512
	RCC_CFGR_HPRE_Div512 = 0xf
	// Position of SWS field.
	RCC_CFGR_SWS_Pos = 0x2
	// Bit mask of SWS field.
	RCC_CFGR_SWS_Msk = 0xc
	// MSI oscillator used as system clock
	RCC_CFGR_SWS_MSI = 0x0
	// HSI oscillator used as system clock
	RCC_CFGR_SWS_HSI = 0x1
	// HSE used as system clock
	RCC_CFGR_SWS_HSE = 0x2
	// PLL used as system clock
	RCC_CFGR_SWS_PLL = 0x3
	// Position of SW field.
	RCC_CFGR_SW_Pos = 0x0
	// Bit mask of SW field.
	RCC_CFGR_SW_Msk = 0x3
	// MSI selected as system clock
	RCC_CFGR_SW_MSI = 0x0
	// HSI selected as system clock
	RCC_CFGR_SW_HSI = 0x1
	// HSE selected as system clock
	RCC_CFGR_SW_HSE = 0x2
	// PLL selected as system clock
	RCC_CFGR_SW_PLL = 0x3

	// PLLCFGR: PLL configuration register
	// Position of PLLPDIV field.
	RCC_PLLCFGR_PLLPDIV_Pos = 0x1b
	// Bit mask of PLLPDIV field.
	RCC_PLLCFGR_PLLPDIV_Msk = 0xf8000000
	// Position of PLLR field.
	RCC_PLLCFGR_PLLR_Pos = 0x19
	// Bit mask of PLLR field.
	RCC_PLLCFGR_PLLR_Msk = 0x6000000
	// Position of PLLREN field.
	RCC_PLLCFGR_PLLREN_Pos = 0x18
	// Bit mask of PLLREN field.
	RCC_PLLCFGR_PLLREN_Msk = 0x1000000
	// Bit PLLREN.
	RCC_PLLCFGR_PLLREN = 0x1000000
	// Position of PLLQ field.
	RCC_PLLCFGR_PLLQ_Pos = 0x15
	// Bit mask of PLLQ field.
	RCC_PLLCFGR_PLLQ_Msk = 0x600000
	// Position of PLLQEN field.
	RCC_PLLCFGR_PLLQEN_Pos = 0x14
	// Bit mask of PLLQEN field.
	RCC_PLLCFGR_PLLQEN_Msk = 0x100000
	// Bit PLLQEN.
	RCC_PLLCFGR_PLLQEN = 0x100000
	// Position of PLLP field.
	RCC_PLLCFGR_PLLP_Pos = 0x11
	// Bit mask of PLLP field.
	RCC_PLLCFGR_PLLP_Msk = 0x20000
	// Bit PLLP.
	RCC_PLLCFGR_PLLP = 0x20000
	// Position of PLLPEN field.
	RCC_PLLCFGR_PLLPEN_Pos = 0x10
	// Bit mask of PLLPEN field.
	RCC_PLLCFGR_PLLPEN_Msk = 0x10000
	// Bit PLLPEN.
	RCC_PLLCFGR_PLLPEN = 0x10000
	// Position of PLLN field.
	RCC_PLLCFGR_PLLN_Pos = 0x8
	// Bit mask of PLLN field.
	RCC_PLLCFGR_PLLN_Msk = 0x7f00
	// Position of PLLM field.
	RCC_PLLCFGR_PLLM_Pos = 0x4
	// Bit mask of PLLM field.
	RCC_PLLCFGR_PLLM_Msk = 0xf0
	// Position of PLLSRC field.
	RCC_PLLCFGR_PLLSRC_Pos = 0x0
	// Bit mask of PLLSRC field.
	RCC_PLLCFGR_PLLSRC_Msk = 0x3

	// PLLSAI1CFGR: PLLSAI1 configuration register
	// Position of PLLSAI1PDIV field.
	RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos = 0x1b
	// Bit mask of PLLSAI1PDIV field.
	RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk = 0xf8000000
	// Position of PLLSAI1R field.
	RCC_PLLSAI1CFGR_PLLSAI1R_Pos = 0x19
	// Bit mask of PLLSAI1R field.
	RCC_PLLSAI1CFGR_PLLSAI1R_Msk = 0x6000000
	// Position of PLLSAI1REN field.
	RCC_PLLSAI1CFGR_PLLSAI1REN_Pos = 0x18
	// Bit mask of PLLSAI1REN field.
	RCC_PLLSAI1CFGR_PLLSAI1REN_Msk = 0x1000000
	// Bit PLLSAI1REN.
	RCC_PLLSAI1CFGR_PLLSAI1REN = 0x1000000
	// Position of PLLSAI1Q field.
	RCC_PLLSAI1CFGR_PLLSAI1Q_Pos = 0x15
	// Bit mask of PLLSAI1Q field.
	RCC_PLLSAI1CFGR_PLLSAI1Q_Msk = 0x600000
	// Position of PLLSAI1QEN field.
	RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos = 0x14
	// Bit mask of PLLSAI1QEN field.
	RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk = 0x100000
	// Bit PLLSAI1QEN.
	RCC_PLLSAI1CFGR_PLLSAI1QEN = 0x100000
	// Position of PLLSAI1P field.
	RCC_PLLSAI1CFGR_PLLSAI1P_Pos = 0x11
	// Bit mask of PLLSAI1P field.
	RCC_PLLSAI1CFGR_PLLSAI1P_Msk = 0x20000
	// Bit PLLSAI1P.
	RCC_PLLSAI1CFGR_PLLSAI1P = 0x20000
	// Position of PLLSAI1PEN field.
	RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos = 0x10
	// Bit mask of PLLSAI1PEN field.
	RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk = 0x10000
	// Bit PLLSAI1PEN.
	RCC_PLLSAI1CFGR_PLLSAI1PEN = 0x10000
	// Position of PLLSAI1N field.
	RCC_PLLSAI1CFGR_PLLSAI1N_Pos = 0x8
	// Bit mask of PLLSAI1N field.
	RCC_PLLSAI1CFGR_PLLSAI1N_Msk = 0x7f00
	// Position of PLLSAI1M field.
	RCC_PLLSAI1CFGR_PLLSAI1M_Pos = 0x4
	// Bit mask of PLLSAI1M field.
	RCC_PLLSAI1CFGR_PLLSAI1M_Msk = 0xf0
	// Position of PLLSAI1SRC field.
	RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos = 0x0
	// Bit mask of PLLSAI1SRC field.
	RCC_PLLSAI1CFGR_PLLSAI1SRC_Msk = 0x3

	// PLLSAI2CFGR: PLLSAI2 configuration register
	// Position of PLLSAI2PDIV field.
	RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos = 0x1b
	// Bit mask of PLLSAI2PDIV field.
	RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk = 0xf8000000
	// Position of PLLSAI2P field.
	RCC_PLLSAI2CFGR_PLLSAI2P_Pos = 0x11
	// Bit mask of PLLSAI2P field.
	RCC_PLLSAI2CFGR_PLLSAI2P_Msk = 0x20000
	// Bit PLLSAI2P.
	RCC_PLLSAI2CFGR_PLLSAI2P = 0x20000
	// Position of PLLSAI2PEN field.
	RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos = 0x10
	// Bit mask of PLLSAI2PEN field.
	RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk = 0x10000
	// Bit PLLSAI2PEN.
	RCC_PLLSAI2CFGR_PLLSAI2PEN = 0x10000
	// Position of PLLSAI2N field.
	RCC_PLLSAI2CFGR_PLLSAI2N_Pos = 0x8
	// Bit mask of PLLSAI2N field.
	RCC_PLLSAI2CFGR_PLLSAI2N_Msk = 0x7f00
	// Position of PLLSAI2M field.
	RCC_PLLSAI2CFGR_PLLSAI2M_Pos = 0x4
	// Bit mask of PLLSAI2M field.
	RCC_PLLSAI2CFGR_PLLSAI2M_Msk = 0xf0
	// Position of PLLSAI2SRC field.
	RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos = 0x0
	// Bit mask of PLLSAI2SRC field.
	RCC_PLLSAI2CFGR_PLLSAI2SRC_Msk = 0x3

	// CIER: Clock interrupt enable register
	// Position of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Pos = 0x0
	// Bit mask of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Msk = 0x1
	// Bit LSIRDYIE.
	RCC_CIER_LSIRDYIE = 0x1
	// Position of LSERDYIE field.
	RCC_CIER_LSERDYIE_Pos = 0x1
	// Bit mask of LSERDYIE field.
	RCC_CIER_LSERDYIE_Msk = 0x2
	// Bit LSERDYIE.
	RCC_CIER_LSERDYIE = 0x2
	// Position of MSIRDYIE field.
	RCC_CIER_MSIRDYIE_Pos = 0x2
	// Bit mask of MSIRDYIE field.
	RCC_CIER_MSIRDYIE_Msk = 0x4
	// Bit MSIRDYIE.
	RCC_CIER_MSIRDYIE = 0x4
	// Position of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Pos = 0x3
	// Bit mask of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Msk = 0x8
	// Bit HSIRDYIE.
	RCC_CIER_HSIRDYIE = 0x8
	// Position of HSERDYIE field.
	RCC_CIER_HSERDYIE_Pos = 0x4
	// Bit mask of HSERDYIE field.
	RCC_CIER_HSERDYIE_Msk = 0x10
	// Bit HSERDYIE.
	RCC_CIER_HSERDYIE = 0x10
	// Position of PLLRDYIE field.
	RCC_CIER_PLLRDYIE_Pos = 0x5
	// Bit mask of PLLRDYIE field.
	RCC_CIER_PLLRDYIE_Msk = 0x20
	// Bit PLLRDYIE.
	RCC_CIER_PLLRDYIE = 0x20
	// Position of PLLSAI1RDYIE field.
	RCC_CIER_PLLSAI1RDYIE_Pos = 0x6
	// Bit mask of PLLSAI1RDYIE field.
	RCC_CIER_PLLSAI1RDYIE_Msk = 0x40
	// Bit PLLSAI1RDYIE.
	RCC_CIER_PLLSAI1RDYIE = 0x40
	// Position of PLLSAI2RDYIE field.
	RCC_CIER_PLLSAI2RDYIE_Pos = 0x7
	// Bit mask of PLLSAI2RDYIE field.
	RCC_CIER_PLLSAI2RDYIE_Msk = 0x80
	// Bit PLLSAI2RDYIE.
	RCC_CIER_PLLSAI2RDYIE = 0x80
	// Position of LSECSSIE field.
	RCC_CIER_LSECSSIE_Pos = 0x9
	// Bit mask of LSECSSIE field.
	RCC_CIER_LSECSSIE_Msk = 0x200
	// Bit LSECSSIE.
	RCC_CIER_LSECSSIE = 0x200
	// Position of HSI48RDYIE field.
	RCC_CIER_HSI48RDYIE_Pos = 0xa
	// Bit mask of HSI48RDYIE field.
	RCC_CIER_HSI48RDYIE_Msk = 0x400
	// Bit HSI48RDYIE.
	RCC_CIER_HSI48RDYIE = 0x400

	// CIFR: Clock interrupt flag register
	// Position of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Pos = 0x0
	// Bit mask of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Msk = 0x1
	// Bit LSIRDYF.
	RCC_CIFR_LSIRDYF = 0x1
	// Position of LSERDYF field.
	RCC_CIFR_LSERDYF_Pos = 0x1
	// Bit mask of LSERDYF field.
	RCC_CIFR_LSERDYF_Msk = 0x2
	// Bit LSERDYF.
	RCC_CIFR_LSERDYF = 0x2
	// Position of MSIRDYF field.
	RCC_CIFR_MSIRDYF_Pos = 0x2
	// Bit mask of MSIRDYF field.
	RCC_CIFR_MSIRDYF_Msk = 0x4
	// Bit MSIRDYF.
	RCC_CIFR_MSIRDYF = 0x4
	// Position of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Pos = 0x3
	// Bit mask of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Msk = 0x8
	// Bit HSIRDYF.
	RCC_CIFR_HSIRDYF = 0x8
	// Position of HSERDYF field.
	RCC_CIFR_HSERDYF_Pos = 0x4
	// Bit mask of HSERDYF field.
	RCC_CIFR_HSERDYF_Msk = 0x10
	// Bit HSERDYF.
	RCC_CIFR_HSERDYF = 0x10
	// Position of PLLRDYF field.
	RCC_CIFR_PLLRDYF_Pos = 0x5
	// Bit mask of PLLRDYF field.
	RCC_CIFR_PLLRDYF_Msk = 0x20
	// Bit PLLRDYF.
	RCC_CIFR_PLLRDYF = 0x20
	// Position of PLLSAI1RDYF field.
	RCC_CIFR_PLLSAI1RDYF_Pos = 0x6
	// Bit mask of PLLSAI1RDYF field.
	RCC_CIFR_PLLSAI1RDYF_Msk = 0x40
	// Bit PLLSAI1RDYF.
	RCC_CIFR_PLLSAI1RDYF = 0x40
	// Position of PLLSAI2RDYF field.
	RCC_CIFR_PLLSAI2RDYF_Pos = 0x7
	// Bit mask of PLLSAI2RDYF field.
	RCC_CIFR_PLLSAI2RDYF_Msk = 0x80
	// Bit PLLSAI2RDYF.
	RCC_CIFR_PLLSAI2RDYF = 0x80
	// Position of CSSF field.
	RCC_CIFR_CSSF_Pos = 0x8
	// Bit mask of CSSF field.
	RCC_CIFR_CSSF_Msk = 0x100
	// Bit CSSF.
	RCC_CIFR_CSSF = 0x100
	// Position of LSECSSF field.
	RCC_CIFR_LSECSSF_Pos = 0x9
	// Bit mask of LSECSSF field.
	RCC_CIFR_LSECSSF_Msk = 0x200
	// Bit LSECSSF.
	RCC_CIFR_LSECSSF = 0x200
	// Position of HSI48RDYF field.
	RCC_CIFR_HSI48RDYF_Pos = 0xa
	// Bit mask of HSI48RDYF field.
	RCC_CIFR_HSI48RDYF_Msk = 0x400
	// Bit HSI48RDYF.
	RCC_CIFR_HSI48RDYF = 0x400

	// CICR: Clock interrupt clear register
	// Position of LSIRDYC field.
	RCC_CICR_LSIRDYC_Pos = 0x0
	// Bit mask of LSIRDYC field.
	RCC_CICR_LSIRDYC_Msk = 0x1
	// Bit LSIRDYC.
	RCC_CICR_LSIRDYC = 0x1
	// Position of LSERDYC field.
	RCC_CICR_LSERDYC_Pos = 0x1
	// Bit mask of LSERDYC field.
	RCC_CICR_LSERDYC_Msk = 0x2
	// Bit LSERDYC.
	RCC_CICR_LSERDYC = 0x2
	// Position of MSIRDYC field.
	RCC_CICR_MSIRDYC_Pos = 0x2
	// Bit mask of MSIRDYC field.
	RCC_CICR_MSIRDYC_Msk = 0x4
	// Bit MSIRDYC.
	RCC_CICR_MSIRDYC = 0x4
	// Position of HSIRDYC field.
	RCC_CICR_HSIRDYC_Pos = 0x3
	// Bit mask of HSIRDYC field.
	RCC_CICR_HSIRDYC_Msk = 0x8
	// Bit HSIRDYC.
	RCC_CICR_HSIRDYC = 0x8
	// Position of HSERDYC field.
	RCC_CICR_HSERDYC_Pos = 0x4
	// Bit mask of HSERDYC field.
	RCC_CICR_HSERDYC_Msk = 0x10
	// Bit HSERDYC.
	RCC_CICR_HSERDYC = 0x10
	// Position of PLLRDYC field.
	RCC_CICR_PLLRDYC_Pos = 0x5
	// Bit mask of PLLRDYC field.
	RCC_CICR_PLLRDYC_Msk = 0x20
	// Bit PLLRDYC.
	RCC_CICR_PLLRDYC = 0x20
	// Position of PLLSAI1RDYC field.
	RCC_CICR_PLLSAI1RDYC_Pos = 0x6
	// Bit mask of PLLSAI1RDYC field.
	RCC_CICR_PLLSAI1RDYC_Msk = 0x40
	// Bit PLLSAI1RDYC.
	RCC_CICR_PLLSAI1RDYC = 0x40
	// Position of PLLSAI2RDYC field.
	RCC_CICR_PLLSAI2RDYC_Pos = 0x7
	// Bit mask of PLLSAI2RDYC field.
	RCC_CICR_PLLSAI2RDYC_Msk = 0x80
	// Bit PLLSAI2RDYC.
	RCC_CICR_PLLSAI2RDYC = 0x80
	// Position of CSSC field.
	RCC_CICR_CSSC_Pos = 0x8
	// Bit mask of CSSC field.
	RCC_CICR_CSSC_Msk = 0x100
	// Bit CSSC.
	RCC_CICR_CSSC = 0x100
	// Position of LSECSSC field.
	RCC_CICR_LSECSSC_Pos = 0x9
	// Bit mask of LSECSSC field.
	RCC_CICR_LSECSSC_Msk = 0x200
	// Bit LSECSSC.
	RCC_CICR_LSECSSC = 0x200
	// Position of HSI48RDYC field.
	RCC_CICR_HSI48RDYC_Pos = 0xa
	// Bit mask of HSI48RDYC field.
	RCC_CICR_HSI48RDYC_Msk = 0x400
	// Bit HSI48RDYC.
	RCC_CICR_HSI48RDYC = 0x400

	// AHB1RSTR: AHB1 peripheral reset register
	// Position of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST_Pos = 0x0
	// Bit mask of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST_Msk = 0x1
	// Bit DMA1RST.
	RCC_AHB1RSTR_DMA1RST = 0x1
	// Reset the selected module
	RCC_AHB1RSTR_DMA1RST_Reset = 0x1
	// Position of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST_Pos = 0x1
	// Bit mask of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST_Msk = 0x2
	// Bit DMA2RST.
	RCC_AHB1RSTR_DMA2RST = 0x2
	// Reset the selected module
	RCC_AHB1RSTR_DMA2RST_Reset = 0x1
	// Position of DMAMUX1RST field.
	RCC_AHB1RSTR_DMAMUX1RST_Pos = 0x2
	// Bit mask of DMAMUX1RST field.
	RCC_AHB1RSTR_DMAMUX1RST_Msk = 0x4
	// Bit DMAMUX1RST.
	RCC_AHB1RSTR_DMAMUX1RST = 0x4
	// Reset the selected module
	RCC_AHB1RSTR_DMAMUX1RST_Reset = 0x1
	// Position of FLASHRST field.
	RCC_AHB1RSTR_FLASHRST_Pos = 0x8
	// Bit mask of FLASHRST field.
	RCC_AHB1RSTR_FLASHRST_Msk = 0x100
	// Bit FLASHRST.
	RCC_AHB1RSTR_FLASHRST = 0x100
	// Reset the selected module
	RCC_AHB1RSTR_FLASHRST_Reset = 0x1
	// Position of CRCRST field.
	RCC_AHB1RSTR_CRCRST_Pos = 0xc
	// Bit mask of CRCRST field.
	RCC_AHB1RSTR_CRCRST_Msk = 0x1000
	// Bit CRCRST.
	RCC_AHB1RSTR_CRCRST = 0x1000
	// Reset the selected module
	RCC_AHB1RSTR_CRCRST_Reset = 0x1
	// Position of TSCRST field.
	RCC_AHB1RSTR_TSCRST_Pos = 0x10
	// Bit mask of TSCRST field.
	RCC_AHB1RSTR_TSCRST_Msk = 0x10000
	// Bit TSCRST.
	RCC_AHB1RSTR_TSCRST = 0x10000
	// Reset the selected module
	RCC_AHB1RSTR_TSCRST_Reset = 0x1
	// Position of GTZCRST field.
	RCC_AHB1RSTR_GTZCRST_Pos = 0x16
	// Bit mask of GTZCRST field.
	RCC_AHB1RSTR_GTZCRST_Msk = 0x400000
	// Bit GTZCRST.
	RCC_AHB1RSTR_GTZCRST = 0x400000
	// Reset the selected module
	RCC_AHB1RSTR_GTZCRST_Reset = 0x1

	// AHB2RSTR: AHB2 peripheral reset register
	// Position of GPIOARST field.
	RCC_AHB2RSTR_GPIOARST_Pos = 0x0
	// Bit mask of GPIOARST field.
	RCC_AHB2RSTR_GPIOARST_Msk = 0x1
	// Bit GPIOARST.
	RCC_AHB2RSTR_GPIOARST = 0x1
	// Reset the selected module
	RCC_AHB2RSTR_GPIOARST_Reset = 0x1
	// Position of GPIOBRST field.
	RCC_AHB2RSTR_GPIOBRST_Pos = 0x1
	// Bit mask of GPIOBRST field.
	RCC_AHB2RSTR_GPIOBRST_Msk = 0x2
	// Bit GPIOBRST.
	RCC_AHB2RSTR_GPIOBRST = 0x2
	// Reset the selected module
	RCC_AHB2RSTR_GPIOBRST_Reset = 0x1
	// Position of GPIOCRST field.
	RCC_AHB2RSTR_GPIOCRST_Pos = 0x2
	// Bit mask of GPIOCRST field.
	RCC_AHB2RSTR_GPIOCRST_Msk = 0x4
	// Bit GPIOCRST.
	RCC_AHB2RSTR_GPIOCRST = 0x4
	// Reset the selected module
	RCC_AHB2RSTR_GPIOCRST_Reset = 0x1
	// Position of GPIODRST field.
	RCC_AHB2RSTR_GPIODRST_Pos = 0x3
	// Bit mask of GPIODRST field.
	RCC_AHB2RSTR_GPIODRST_Msk = 0x8
	// Bit GPIODRST.
	RCC_AHB2RSTR_GPIODRST = 0x8
	// Reset the selected module
	RCC_AHB2RSTR_GPIODRST_Reset = 0x1
	// Position of GPIOERST field.
	RCC_AHB2RSTR_GPIOERST_Pos = 0x4
	// Bit mask of GPIOERST field.
	RCC_AHB2RSTR_GPIOERST_Msk = 0x10
	// Bit GPIOERST.
	RCC_AHB2RSTR_GPIOERST = 0x10
	// Reset the selected module
	RCC_AHB2RSTR_GPIOERST_Reset = 0x1
	// Position of GPIOFRST field.
	RCC_AHB2RSTR_GPIOFRST_Pos = 0x5
	// Bit mask of GPIOFRST field.
	RCC_AHB2RSTR_GPIOFRST_Msk = 0x20
	// Bit GPIOFRST.
	RCC_AHB2RSTR_GPIOFRST = 0x20
	// Reset the selected module
	RCC_AHB2RSTR_GPIOFRST_Reset = 0x1
	// Position of GPIOGRST field.
	RCC_AHB2RSTR_GPIOGRST_Pos = 0x6
	// Bit mask of GPIOGRST field.
	RCC_AHB2RSTR_GPIOGRST_Msk = 0x40
	// Bit GPIOGRST.
	RCC_AHB2RSTR_GPIOGRST = 0x40
	// Reset the selected module
	RCC_AHB2RSTR_GPIOGRST_Reset = 0x1
	// Position of GPIOHRST field.
	RCC_AHB2RSTR_GPIOHRST_Pos = 0x7
	// Bit mask of GPIOHRST field.
	RCC_AHB2RSTR_GPIOHRST_Msk = 0x80
	// Bit GPIOHRST.
	RCC_AHB2RSTR_GPIOHRST = 0x80
	// Reset the selected module
	RCC_AHB2RSTR_GPIOHRST_Reset = 0x1
	// Position of ADCRST field.
	RCC_AHB2RSTR_ADCRST_Pos = 0xd
	// Bit mask of ADCRST field.
	RCC_AHB2RSTR_ADCRST_Msk = 0x2000
	// Bit ADCRST.
	RCC_AHB2RSTR_ADCRST = 0x2000
	// Reset the selected module
	RCC_AHB2RSTR_ADCRST_Reset = 0x1
	// Position of AESRST field.
	RCC_AHB2RSTR_AESRST_Pos = 0x10
	// Bit mask of AESRST field.
	RCC_AHB2RSTR_AESRST_Msk = 0x10000
	// Bit AESRST.
	RCC_AHB2RSTR_AESRST = 0x10000
	// Reset the selected module
	RCC_AHB2RSTR_AESRST_Reset = 0x1
	// Position of HASHRST field.
	RCC_AHB2RSTR_HASHRST_Pos = 0x11
	// Bit mask of HASHRST field.
	RCC_AHB2RSTR_HASHRST_Msk = 0x20000
	// Bit HASHRST.
	RCC_AHB2RSTR_HASHRST = 0x20000
	// Reset the selected module
	RCC_AHB2RSTR_HASHRST_Reset = 0x1
	// Position of RNGRST field.
	RCC_AHB2RSTR_RNGRST_Pos = 0x12
	// Bit mask of RNGRST field.
	RCC_AHB2RSTR_RNGRST_Msk = 0x40000
	// Bit RNGRST.
	RCC_AHB2RSTR_RNGRST = 0x40000
	// Reset the selected module
	RCC_AHB2RSTR_RNGRST_Reset = 0x1
	// Position of PKARST field.
	RCC_AHB2RSTR_PKARST_Pos = 0x13
	// Bit mask of PKARST field.
	RCC_AHB2RSTR_PKARST_Msk = 0x80000
	// Bit PKARST.
	RCC_AHB2RSTR_PKARST = 0x80000
	// Reset the selected module
	RCC_AHB2RSTR_PKARST_Reset = 0x1
	// Position of OTFDEC1RST field.
	RCC_AHB2RSTR_OTFDEC1RST_Pos = 0x15
	// Bit mask of OTFDEC1RST field.
	RCC_AHB2RSTR_OTFDEC1RST_Msk = 0x200000
	// Bit OTFDEC1RST.
	RCC_AHB2RSTR_OTFDEC1RST = 0x200000
	// Reset the selected module
	RCC_AHB2RSTR_OTFDEC1RST_Reset = 0x1
	// Position of SDMMC1RST field.
	RCC_AHB2RSTR_SDMMC1RST_Pos = 0x16
	// Bit mask of SDMMC1RST field.
	RCC_AHB2RSTR_SDMMC1RST_Msk = 0x400000
	// Bit SDMMC1RST.
	RCC_AHB2RSTR_SDMMC1RST = 0x400000
	// Reset the selected module
	RCC_AHB2RSTR_SDMMC1RST_Reset = 0x1

	// AHB3RSTR: AHB3 peripheral reset register
	// Position of FMCRST field.
	RCC_AHB3RSTR_FMCRST_Pos = 0x0
	// Bit mask of FMCRST field.
	RCC_AHB3RSTR_FMCRST_Msk = 0x1
	// Bit FMCRST.
	RCC_AHB3RSTR_FMCRST = 0x1
	// Reset the selected module
	RCC_AHB3RSTR_FMCRST_Reset = 0x1
	// Position of OSPI1RST field.
	RCC_AHB3RSTR_OSPI1RST_Pos = 0x8
	// Bit mask of OSPI1RST field.
	RCC_AHB3RSTR_OSPI1RST_Msk = 0x100
	// Bit OSPI1RST.
	RCC_AHB3RSTR_OSPI1RST = 0x100
	// Reset the selected module
	RCC_AHB3RSTR_OSPI1RST_Reset = 0x1

	// APB1RSTR1: APB1 peripheral reset register 1
	// Position of TIM2RST field.
	RCC_APB1RSTR1_TIM2RST_Pos = 0x0
	// Bit mask of TIM2RST field.
	RCC_APB1RSTR1_TIM2RST_Msk = 0x1
	// Bit TIM2RST.
	RCC_APB1RSTR1_TIM2RST = 0x1
	// Reset the selected module
	RCC_APB1RSTR1_TIM2RST_Reset = 0x1
	// Position of LPTIM1RST field.
	RCC_APB1RSTR1_LPTIM1RST_Pos = 0x1f
	// Bit mask of LPTIM1RST field.
	RCC_APB1RSTR1_LPTIM1RST_Msk = 0x80000000
	// Bit LPTIM1RST.
	RCC_APB1RSTR1_LPTIM1RST = 0x80000000
	// Reset the selected module
	RCC_APB1RSTR1_LPTIM1RST_Reset = 0x1
	// Position of OPAMPRST field.
	RCC_APB1RSTR1_OPAMPRST_Pos = 0x1e
	// Bit mask of OPAMPRST field.
	RCC_APB1RSTR1_OPAMPRST_Msk = 0x40000000
	// Bit OPAMPRST.
	RCC_APB1RSTR1_OPAMPRST = 0x40000000
	// Reset the selected module
	RCC_APB1RSTR1_OPAMPRST_Reset = 0x1
	// Position of DAC1RST field.
	RCC_APB1RSTR1_DAC1RST_Pos = 0x1d
	// Bit mask of DAC1RST field.
	RCC_APB1RSTR1_DAC1RST_Msk = 0x20000000
	// Bit DAC1RST.
	RCC_APB1RSTR1_DAC1RST = 0x20000000
	// Reset the selected module
	RCC_APB1RSTR1_DAC1RST_Reset = 0x1
	// Position of PWRRST field.
	RCC_APB1RSTR1_PWRRST_Pos = 0x1c
	// Bit mask of PWRRST field.
	RCC_APB1RSTR1_PWRRST_Msk = 0x10000000
	// Bit PWRRST.
	RCC_APB1RSTR1_PWRRST = 0x10000000
	// Reset the selected module
	RCC_APB1RSTR1_PWRRST_Reset = 0x1
	// Position of CRSRST field.
	RCC_APB1RSTR1_CRSRST_Pos = 0x18
	// Bit mask of CRSRST field.
	RCC_APB1RSTR1_CRSRST_Msk = 0x1000000
	// Bit CRSRST.
	RCC_APB1RSTR1_CRSRST = 0x1000000
	// Reset the selected module
	RCC_APB1RSTR1_CRSRST_Reset = 0x1
	// Position of I2C3RST field.
	RCC_APB1RSTR1_I2C3RST_Pos = 0x17
	// Bit mask of I2C3RST field.
	RCC_APB1RSTR1_I2C3RST_Msk = 0x800000
	// Bit I2C3RST.
	RCC_APB1RSTR1_I2C3RST = 0x800000
	// Reset the selected module
	RCC_APB1RSTR1_I2C3RST_Reset = 0x1
	// Position of I2C2RST field.
	RCC_APB1RSTR1_I2C2RST_Pos = 0x16
	// Bit mask of I2C2RST field.
	RCC_APB1RSTR1_I2C2RST_Msk = 0x400000
	// Bit I2C2RST.
	RCC_APB1RSTR1_I2C2RST = 0x400000
	// Reset the selected module
	RCC_APB1RSTR1_I2C2RST_Reset = 0x1
	// Position of I2C1RST field.
	RCC_APB1RSTR1_I2C1RST_Pos = 0x15
	// Bit mask of I2C1RST field.
	RCC_APB1RSTR1_I2C1RST_Msk = 0x200000
	// Bit I2C1RST.
	RCC_APB1RSTR1_I2C1RST = 0x200000
	// Reset the selected module
	RCC_APB1RSTR1_I2C1RST_Reset = 0x1
	// Position of UART5RST field.
	RCC_APB1RSTR1_UART5RST_Pos = 0x14
	// Bit mask of UART5RST field.
	RCC_APB1RSTR1_UART5RST_Msk = 0x100000
	// Bit UART5RST.
	RCC_APB1RSTR1_UART5RST = 0x100000
	// Reset the selected module
	RCC_APB1RSTR1_UART5RST_Reset = 0x1
	// Position of UART4RST field.
	RCC_APB1RSTR1_UART4RST_Pos = 0x13
	// Bit mask of UART4RST field.
	RCC_APB1RSTR1_UART4RST_Msk = 0x80000
	// Bit UART4RST.
	RCC_APB1RSTR1_UART4RST = 0x80000
	// Reset the selected module
	RCC_APB1RSTR1_UART4RST_Reset = 0x1
	// Position of USART3RST field.
	RCC_APB1RSTR1_USART3RST_Pos = 0x12
	// Bit mask of USART3RST field.
	RCC_APB1RSTR1_USART3RST_Msk = 0x40000
	// Bit USART3RST.
	RCC_APB1RSTR1_USART3RST = 0x40000
	// Reset the selected module
	RCC_APB1RSTR1_USART3RST_Reset = 0x1
	// Position of USART2RST field.
	RCC_APB1RSTR1_USART2RST_Pos = 0x11
	// Bit mask of USART2RST field.
	RCC_APB1RSTR1_USART2RST_Msk = 0x20000
	// Bit USART2RST.
	RCC_APB1RSTR1_USART2RST = 0x20000
	// Reset the selected module
	RCC_APB1RSTR1_USART2RST_Reset = 0x1
	// Position of SPI3RST field.
	RCC_APB1RSTR1_SPI3RST_Pos = 0xf
	// Bit mask of SPI3RST field.
	RCC_APB1RSTR1_SPI3RST_Msk = 0x8000
	// Bit SPI3RST.
	RCC_APB1RSTR1_SPI3RST = 0x8000
	// Reset the selected module
	RCC_APB1RSTR1_SPI3RST_Reset = 0x1
	// Position of SPI2RST field.
	RCC_APB1RSTR1_SPI2RST_Pos = 0xe
	// Bit mask of SPI2RST field.
	RCC_APB1RSTR1_SPI2RST_Msk = 0x4000
	// Bit SPI2RST.
	RCC_APB1RSTR1_SPI2RST = 0x4000
	// Reset the selected module
	RCC_APB1RSTR1_SPI2RST_Reset = 0x1
	// Position of TIM7RST field.
	RCC_APB1RSTR1_TIM7RST_Pos = 0x5
	// Bit mask of TIM7RST field.
	RCC_APB1RSTR1_TIM7RST_Msk = 0x20
	// Bit TIM7RST.
	RCC_APB1RSTR1_TIM7RST = 0x20
	// Reset the selected module
	RCC_APB1RSTR1_TIM7RST_Reset = 0x1
	// Position of TIM6RST field.
	RCC_APB1RSTR1_TIM6RST_Pos = 0x4
	// Bit mask of TIM6RST field.
	RCC_APB1RSTR1_TIM6RST_Msk = 0x10
	// Bit TIM6RST.
	RCC_APB1RSTR1_TIM6RST = 0x10
	// Reset the selected module
	RCC_APB1RSTR1_TIM6RST_Reset = 0x1
	// Position of TIM5RST field.
	RCC_APB1RSTR1_TIM5RST_Pos = 0x3
	// Bit mask of TIM5RST field.
	RCC_APB1RSTR1_TIM5RST_Msk = 0x8
	// Bit TIM5RST.
	RCC_APB1RSTR1_TIM5RST = 0x8
	// Reset the selected module
	RCC_APB1RSTR1_TIM5RST_Reset = 0x1
	// Position of TIM4RST field.
	RCC_APB1RSTR1_TIM4RST_Pos = 0x2
	// Bit mask of TIM4RST field.
	RCC_APB1RSTR1_TIM4RST_Msk = 0x4
	// Bit TIM4RST.
	RCC_APB1RSTR1_TIM4RST = 0x4
	// Reset the selected module
	RCC_APB1RSTR1_TIM4RST_Reset = 0x1
	// Position of TIM3RST field.
	RCC_APB1RSTR1_TIM3RST_Pos = 0x1
	// Bit mask of TIM3RST field.
	RCC_APB1RSTR1_TIM3RST_Msk = 0x2
	// Bit TIM3RST.
	RCC_APB1RSTR1_TIM3RST = 0x2
	// Reset the selected module
	RCC_APB1RSTR1_TIM3RST_Reset = 0x1

	// APB1RSTR2: APB1 peripheral reset register 2
	// Position of LPUART1RST field.
	RCC_APB1RSTR2_LPUART1RST_Pos = 0x0
	// Bit mask of LPUART1RST field.
	RCC_APB1RSTR2_LPUART1RST_Msk = 0x1
	// Bit LPUART1RST.
	RCC_APB1RSTR2_LPUART1RST = 0x1
	// Reset the selected module
	RCC_APB1RSTR2_LPUART1RST_Reset = 0x1
	// Position of I2C4RST field.
	RCC_APB1RSTR2_I2C4RST_Pos = 0x1
	// Bit mask of I2C4RST field.
	RCC_APB1RSTR2_I2C4RST_Msk = 0x2
	// Bit I2C4RST.
	RCC_APB1RSTR2_I2C4RST = 0x2
	// Reset the selected module
	RCC_APB1RSTR2_I2C4RST_Reset = 0x1
	// Position of LPTIM2RST field.
	RCC_APB1RSTR2_LPTIM2RST_Pos = 0x5
	// Bit mask of LPTIM2RST field.
	RCC_APB1RSTR2_LPTIM2RST_Msk = 0x20
	// Bit LPTIM2RST.
	RCC_APB1RSTR2_LPTIM2RST = 0x20
	// Reset the selected module
	RCC_APB1RSTR2_LPTIM2RST_Reset = 0x1
	// Position of LPTIM3RST field.
	RCC_APB1RSTR2_LPTIM3RST_Pos = 0x6
	// Bit mask of LPTIM3RST field.
	RCC_APB1RSTR2_LPTIM3RST_Msk = 0x40
	// Bit LPTIM3RST.
	RCC_APB1RSTR2_LPTIM3RST = 0x40
	// Reset the selected module
	RCC_APB1RSTR2_LPTIM3RST_Reset = 0x1
	// Position of FDCAN1RST field.
	RCC_APB1RSTR2_FDCAN1RST_Pos = 0x9
	// Bit mask of FDCAN1RST field.
	RCC_APB1RSTR2_FDCAN1RST_Msk = 0x200
	// Bit FDCAN1RST.
	RCC_APB1RSTR2_FDCAN1RST = 0x200
	// Reset the selected module
	RCC_APB1RSTR2_FDCAN1RST_Reset = 0x1
	// Position of USBFSRST field.
	RCC_APB1RSTR2_USBFSRST_Pos = 0x15
	// Bit mask of USBFSRST field.
	RCC_APB1RSTR2_USBFSRST_Msk = 0x200000
	// Bit USBFSRST.
	RCC_APB1RSTR2_USBFSRST = 0x200000
	// Reset the selected module
	RCC_APB1RSTR2_USBFSRST_Reset = 0x1
	// Position of UCPD1RST field.
	RCC_APB1RSTR2_UCPD1RST_Pos = 0x17
	// Bit mask of UCPD1RST field.
	RCC_APB1RSTR2_UCPD1RST_Msk = 0x800000
	// Bit UCPD1RST.
	RCC_APB1RSTR2_UCPD1RST = 0x800000
	// Reset the selected module
	RCC_APB1RSTR2_UCPD1RST_Reset = 0x1

	// APB2RSTR: APB2 peripheral reset register
	// Position of SYSCFGRST field.
	RCC_APB2RSTR_SYSCFGRST_Pos = 0x0
	// Bit mask of SYSCFGRST field.
	RCC_APB2RSTR_SYSCFGRST_Msk = 0x1
	// Bit SYSCFGRST.
	RCC_APB2RSTR_SYSCFGRST = 0x1
	// Reset the selected module
	RCC_APB2RSTR_SYSCFGRST_Reset = 0x1
	// Position of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Pos = 0xb
	// Bit mask of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Msk = 0x800
	// Bit TIM1RST.
	RCC_APB2RSTR_TIM1RST = 0x800
	// Reset the selected module
	RCC_APB2RSTR_TIM1RST_Reset = 0x1
	// Position of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Pos = 0xc
	// Bit mask of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Msk = 0x1000
	// Bit SPI1RST.
	RCC_APB2RSTR_SPI1RST = 0x1000
	// Reset the selected module
	RCC_APB2RSTR_SPI1RST_Reset = 0x1
	// Position of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Pos = 0xd
	// Bit mask of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Msk = 0x2000
	// Bit TIM8RST.
	RCC_APB2RSTR_TIM8RST = 0x2000
	// Reset the selected module
	RCC_APB2RSTR_TIM8RST_Reset = 0x1
	// Position of USART1RST field.
	RCC_APB2RSTR_USART1RST_Pos = 0xe
	// Bit mask of USART1RST field.
	RCC_APB2RSTR_USART1RST_Msk = 0x4000
	// Bit USART1RST.
	RCC_APB2RSTR_USART1RST = 0x4000
	// Reset the selected module
	RCC_APB2RSTR_USART1RST_Reset = 0x1
	// Position of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Pos = 0x10
	// Bit mask of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Msk = 0x10000
	// Bit TIM15RST.
	RCC_APB2RSTR_TIM15RST = 0x10000
	// Reset the selected module
	RCC_APB2RSTR_TIM15RST_Reset = 0x1
	// Position of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Pos = 0x11
	// Bit mask of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Msk = 0x20000
	// Bit TIM16RST.
	RCC_APB2RSTR_TIM16RST = 0x20000
	// Reset the selected module
	RCC_APB2RSTR_TIM16RST_Reset = 0x1
	// Position of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Pos = 0x12
	// Bit mask of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Msk = 0x40000
	// Bit TIM17RST.
	RCC_APB2RSTR_TIM17RST = 0x40000
	// Reset the selected module
	RCC_APB2RSTR_TIM17RST_Reset = 0x1
	// Position of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Pos = 0x15
	// Bit mask of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Msk = 0x200000
	// Bit SAI1RST.
	RCC_APB2RSTR_SAI1RST = 0x200000
	// Reset the selected module
	RCC_APB2RSTR_SAI1RST_Reset = 0x1
	// Position of SAI2RST field.
	RCC_APB2RSTR_SAI2RST_Pos = 0x16
	// Bit mask of SAI2RST field.
	RCC_APB2RSTR_SAI2RST_Msk = 0x400000
	// Bit SAI2RST.
	RCC_APB2RSTR_SAI2RST = 0x400000
	// Reset the selected module
	RCC_APB2RSTR_SAI2RST_Reset = 0x1
	// Position of DFSDM1RST field.
	RCC_APB2RSTR_DFSDM1RST_Pos = 0x18
	// Bit mask of DFSDM1RST field.
	RCC_APB2RSTR_DFSDM1RST_Msk = 0x1000000
	// Bit DFSDM1RST.
	RCC_APB2RSTR_DFSDM1RST = 0x1000000
	// Reset the selected module
	RCC_APB2RSTR_DFSDM1RST_Reset = 0x1

	// AHB1ENR: AHB1 peripheral clock enable register
	// Position of DMA1EN field.
	RCC_AHB1ENR_DMA1EN_Pos = 0x0
	// Bit mask of DMA1EN field.
	RCC_AHB1ENR_DMA1EN_Msk = 0x1
	// Bit DMA1EN.
	RCC_AHB1ENR_DMA1EN = 0x1
	// The selected clock is disabled
	RCC_AHB1ENR_DMA1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_DMA1EN_Enabled = 0x1
	// Position of DMA2EN field.
	RCC_AHB1ENR_DMA2EN_Pos = 0x1
	// Bit mask of DMA2EN field.
	RCC_AHB1ENR_DMA2EN_Msk = 0x2
	// Bit DMA2EN.
	RCC_AHB1ENR_DMA2EN = 0x2
	// The selected clock is disabled
	RCC_AHB1ENR_DMA2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_DMA2EN_Enabled = 0x1
	// Position of DMAMUX1EN field.
	RCC_AHB1ENR_DMAMUX1EN_Pos = 0x2
	// Bit mask of DMAMUX1EN field.
	RCC_AHB1ENR_DMAMUX1EN_Msk = 0x4
	// Bit DMAMUX1EN.
	RCC_AHB1ENR_DMAMUX1EN = 0x4
	// The selected clock is disabled
	RCC_AHB1ENR_DMAMUX1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_DMAMUX1EN_Enabled = 0x1
	// Position of FLASHEN field.
	RCC_AHB1ENR_FLASHEN_Pos = 0x8
	// Bit mask of FLASHEN field.
	RCC_AHB1ENR_FLASHEN_Msk = 0x100
	// Bit FLASHEN.
	RCC_AHB1ENR_FLASHEN = 0x100
	// The selected clock is disabled
	RCC_AHB1ENR_FLASHEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_FLASHEN_Enabled = 0x1
	// Position of CRCEN field.
	RCC_AHB1ENR_CRCEN_Pos = 0xc
	// Bit mask of CRCEN field.
	RCC_AHB1ENR_CRCEN_Msk = 0x1000
	// Bit CRCEN.
	RCC_AHB1ENR_CRCEN = 0x1000
	// The selected clock is disabled
	RCC_AHB1ENR_CRCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_CRCEN_Enabled = 0x1
	// Position of TSCEN field.
	RCC_AHB1ENR_TSCEN_Pos = 0x10
	// Bit mask of TSCEN field.
	RCC_AHB1ENR_TSCEN_Msk = 0x10000
	// Bit TSCEN.
	RCC_AHB1ENR_TSCEN = 0x10000
	// The selected clock is disabled
	RCC_AHB1ENR_TSCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_TSCEN_Enabled = 0x1
	// Position of GTZCEN field.
	RCC_AHB1ENR_GTZCEN_Pos = 0x16
	// Bit mask of GTZCEN field.
	RCC_AHB1ENR_GTZCEN_Msk = 0x400000
	// Bit GTZCEN.
	RCC_AHB1ENR_GTZCEN = 0x400000
	// The selected clock is disabled
	RCC_AHB1ENR_GTZCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB1ENR_GTZCEN_Enabled = 0x1

	// AHB2ENR: AHB2 peripheral clock enable register
	// Position of GPIOAEN field.
	RCC_AHB2ENR_GPIOAEN_Pos = 0x0
	// Bit mask of GPIOAEN field.
	RCC_AHB2ENR_GPIOAEN_Msk = 0x1
	// Bit GPIOAEN.
	RCC_AHB2ENR_GPIOAEN = 0x1
	// The selected clock is disabled
	RCC_AHB2ENR_GPIOAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIOAEN_Enabled = 0x1
	// Position of GPIOBEN field.
	RCC_AHB2ENR_GPIOBEN_Pos = 0x1
	// Bit mask of GPIOBEN field.
	RCC_AHB2ENR_GPIOBEN_Msk = 0x2
	// Bit GPIOBEN.
	RCC_AHB2ENR_GPIOBEN = 0x2
	// The selected clock is disabled
	RCC_AHB2ENR_GPIOBEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIOBEN_Enabled = 0x1
	// Position of GPIOCEN field.
	RCC_AHB2ENR_GPIOCEN_Pos = 0x2
	// Bit mask of GPIOCEN field.
	RCC_AHB2ENR_GPIOCEN_Msk = 0x4
	// Bit GPIOCEN.
	RCC_AHB2ENR_GPIOCEN = 0x4
	// The selected clock is disabled
	RCC_AHB2ENR_GPIOCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIOCEN_Enabled = 0x1
	// Position of GPIODEN field.
	RCC_AHB2ENR_GPIODEN_Pos = 0x3
	// Bit mask of GPIODEN field.
	RCC_AHB2ENR_GPIODEN_Msk = 0x8
	// Bit GPIODEN.
	RCC_AHB2ENR_GPIODEN = 0x8
	// The selected clock is disabled
	RCC_AHB2ENR_GPIODEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIODEN_Enabled = 0x1
	// Position of GPIOEEN field.
	RCC_AHB2ENR_GPIOEEN_Pos = 0x4
	// Bit mask of GPIOEEN field.
	RCC_AHB2ENR_GPIOEEN_Msk = 0x10
	// Bit GPIOEEN.
	RCC_AHB2ENR_GPIOEEN = 0x10
	// The selected clock is disabled
	RCC_AHB2ENR_GPIOEEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIOEEN_Enabled = 0x1
	// Position of GPIOFEN field.
	RCC_AHB2ENR_GPIOFEN_Pos = 0x5
	// Bit mask of GPIOFEN field.
	RCC_AHB2ENR_GPIOFEN_Msk = 0x20
	// Bit GPIOFEN.
	RCC_AHB2ENR_GPIOFEN = 0x20
	// The selected clock is disabled
	RCC_AHB2ENR_GPIOFEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIOFEN_Enabled = 0x1
	// Position of GPIOGEN field.
	RCC_AHB2ENR_GPIOGEN_Pos = 0x6
	// Bit mask of GPIOGEN field.
	RCC_AHB2ENR_GPIOGEN_Msk = 0x40
	// Bit GPIOGEN.
	RCC_AHB2ENR_GPIOGEN = 0x40
	// The selected clock is disabled
	RCC_AHB2ENR_GPIOGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIOGEN_Enabled = 0x1
	// Position of GPIOHEN field.
	RCC_AHB2ENR_GPIOHEN_Pos = 0x7
	// Bit mask of GPIOHEN field.
	RCC_AHB2ENR_GPIOHEN_Msk = 0x80
	// Bit GPIOHEN.
	RCC_AHB2ENR_GPIOHEN = 0x80
	// The selected clock is disabled
	RCC_AHB2ENR_GPIOHEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_GPIOHEN_Enabled = 0x1
	// Position of ADCEN field.
	RCC_AHB2ENR_ADCEN_Pos = 0xd
	// Bit mask of ADCEN field.
	RCC_AHB2ENR_ADCEN_Msk = 0x2000
	// Bit ADCEN.
	RCC_AHB2ENR_ADCEN = 0x2000
	// The selected clock is disabled
	RCC_AHB2ENR_ADCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_ADCEN_Enabled = 0x1
	// Position of AESEN field.
	RCC_AHB2ENR_AESEN_Pos = 0x10
	// Bit mask of AESEN field.
	RCC_AHB2ENR_AESEN_Msk = 0x10000
	// Bit AESEN.
	RCC_AHB2ENR_AESEN = 0x10000
	// The selected clock is disabled
	RCC_AHB2ENR_AESEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_AESEN_Enabled = 0x1
	// Position of HASHEN field.
	RCC_AHB2ENR_HASHEN_Pos = 0x11
	// Bit mask of HASHEN field.
	RCC_AHB2ENR_HASHEN_Msk = 0x20000
	// Bit HASHEN.
	RCC_AHB2ENR_HASHEN = 0x20000
	// The selected clock is disabled
	RCC_AHB2ENR_HASHEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_HASHEN_Enabled = 0x1
	// Position of RNGEN field.
	RCC_AHB2ENR_RNGEN_Pos = 0x12
	// Bit mask of RNGEN field.
	RCC_AHB2ENR_RNGEN_Msk = 0x40000
	// Bit RNGEN.
	RCC_AHB2ENR_RNGEN = 0x40000
	// The selected clock is disabled
	RCC_AHB2ENR_RNGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_RNGEN_Enabled = 0x1
	// Position of PKAEN field.
	RCC_AHB2ENR_PKAEN_Pos = 0x13
	// Bit mask of PKAEN field.
	RCC_AHB2ENR_PKAEN_Msk = 0x80000
	// Bit PKAEN.
	RCC_AHB2ENR_PKAEN = 0x80000
	// The selected clock is disabled
	RCC_AHB2ENR_PKAEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_PKAEN_Enabled = 0x1
	// Position of OTFDEC1EN field.
	RCC_AHB2ENR_OTFDEC1EN_Pos = 0x15
	// Bit mask of OTFDEC1EN field.
	RCC_AHB2ENR_OTFDEC1EN_Msk = 0x200000
	// Bit OTFDEC1EN.
	RCC_AHB2ENR_OTFDEC1EN = 0x200000
	// The selected clock is disabled
	RCC_AHB2ENR_OTFDEC1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_OTFDEC1EN_Enabled = 0x1
	// Position of SDMMC1EN field.
	RCC_AHB2ENR_SDMMC1EN_Pos = 0x16
	// Bit mask of SDMMC1EN field.
	RCC_AHB2ENR_SDMMC1EN_Msk = 0x400000
	// Bit SDMMC1EN.
	RCC_AHB2ENR_SDMMC1EN = 0x400000
	// The selected clock is disabled
	RCC_AHB2ENR_SDMMC1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB2ENR_SDMMC1EN_Enabled = 0x1

	// AHB3ENR: AHB3 peripheral clock enable register
	// Position of FMCEN field.
	RCC_AHB3ENR_FMCEN_Pos = 0x0
	// Bit mask of FMCEN field.
	RCC_AHB3ENR_FMCEN_Msk = 0x1
	// Bit FMCEN.
	RCC_AHB3ENR_FMCEN = 0x1
	// The selected clock is disabled
	RCC_AHB3ENR_FMCEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_FMCEN_Enabled = 0x1
	// Position of OSPI1EN field.
	RCC_AHB3ENR_OSPI1EN_Pos = 0x8
	// Bit mask of OSPI1EN field.
	RCC_AHB3ENR_OSPI1EN_Msk = 0x100
	// Bit OSPI1EN.
	RCC_AHB3ENR_OSPI1EN = 0x100
	// The selected clock is disabled
	RCC_AHB3ENR_OSPI1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_AHB3ENR_OSPI1EN_Enabled = 0x1

	// APB1ENR1: APB1ENR1
	// Position of TIM2EN field.
	RCC_APB1ENR1_TIM2EN_Pos = 0x0
	// Bit mask of TIM2EN field.
	RCC_APB1ENR1_TIM2EN_Msk = 0x1
	// Bit TIM2EN.
	RCC_APB1ENR1_TIM2EN = 0x1
	// The selected clock is disabled
	RCC_APB1ENR1_TIM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_TIM2EN_Enabled = 0x1
	// Position of TIM3EN field.
	RCC_APB1ENR1_TIM3EN_Pos = 0x1
	// Bit mask of TIM3EN field.
	RCC_APB1ENR1_TIM3EN_Msk = 0x2
	// Bit TIM3EN.
	RCC_APB1ENR1_TIM3EN = 0x2
	// The selected clock is disabled
	RCC_APB1ENR1_TIM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_TIM3EN_Enabled = 0x1
	// Position of TIM4EN field.
	RCC_APB1ENR1_TIM4EN_Pos = 0x2
	// Bit mask of TIM4EN field.
	RCC_APB1ENR1_TIM4EN_Msk = 0x4
	// Bit TIM4EN.
	RCC_APB1ENR1_TIM4EN = 0x4
	// The selected clock is disabled
	RCC_APB1ENR1_TIM4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_TIM4EN_Enabled = 0x1
	// Position of TIM5EN field.
	RCC_APB1ENR1_TIM5EN_Pos = 0x3
	// Bit mask of TIM5EN field.
	RCC_APB1ENR1_TIM5EN_Msk = 0x8
	// Bit TIM5EN.
	RCC_APB1ENR1_TIM5EN = 0x8
	// The selected clock is disabled
	RCC_APB1ENR1_TIM5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_TIM5EN_Enabled = 0x1
	// Position of TIM6EN field.
	RCC_APB1ENR1_TIM6EN_Pos = 0x4
	// Bit mask of TIM6EN field.
	RCC_APB1ENR1_TIM6EN_Msk = 0x10
	// Bit TIM6EN.
	RCC_APB1ENR1_TIM6EN = 0x10
	// The selected clock is disabled
	RCC_APB1ENR1_TIM6EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_TIM6EN_Enabled = 0x1
	// Position of TIM7EN field.
	RCC_APB1ENR1_TIM7EN_Pos = 0x5
	// Bit mask of TIM7EN field.
	RCC_APB1ENR1_TIM7EN_Msk = 0x20
	// Bit TIM7EN.
	RCC_APB1ENR1_TIM7EN = 0x20
	// The selected clock is disabled
	RCC_APB1ENR1_TIM7EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_TIM7EN_Enabled = 0x1
	// Position of RTCAPBEN field.
	RCC_APB1ENR1_RTCAPBEN_Pos = 0xa
	// Bit mask of RTCAPBEN field.
	RCC_APB1ENR1_RTCAPBEN_Msk = 0x400
	// Bit RTCAPBEN.
	RCC_APB1ENR1_RTCAPBEN = 0x400
	// The selected clock is disabled
	RCC_APB1ENR1_RTCAPBEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_RTCAPBEN_Enabled = 0x1
	// Position of WWDGEN field.
	RCC_APB1ENR1_WWDGEN_Pos = 0xb
	// Bit mask of WWDGEN field.
	RCC_APB1ENR1_WWDGEN_Msk = 0x800
	// Bit WWDGEN.
	RCC_APB1ENR1_WWDGEN = 0x800
	// The selected clock is disabled
	RCC_APB1ENR1_WWDGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_WWDGEN_Enabled = 0x1
	// Position of SPI2EN field.
	RCC_APB1ENR1_SPI2EN_Pos = 0xe
	// Bit mask of SPI2EN field.
	RCC_APB1ENR1_SPI2EN_Msk = 0x4000
	// Bit SPI2EN.
	RCC_APB1ENR1_SPI2EN = 0x4000
	// The selected clock is disabled
	RCC_APB1ENR1_SPI2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_SPI2EN_Enabled = 0x1
	// Position of SP3EN field.
	RCC_APB1ENR1_SP3EN_Pos = 0xf
	// Bit mask of SP3EN field.
	RCC_APB1ENR1_SP3EN_Msk = 0x8000
	// Bit SP3EN.
	RCC_APB1ENR1_SP3EN = 0x8000
	// The selected clock is disabled
	RCC_APB1ENR1_SP3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_SP3EN_Enabled = 0x1
	// Position of USART2EN field.
	RCC_APB1ENR1_USART2EN_Pos = 0x11
	// Bit mask of USART2EN field.
	RCC_APB1ENR1_USART2EN_Msk = 0x20000
	// Bit USART2EN.
	RCC_APB1ENR1_USART2EN = 0x20000
	// The selected clock is disabled
	RCC_APB1ENR1_USART2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_USART2EN_Enabled = 0x1
	// Position of USART3EN field.
	RCC_APB1ENR1_USART3EN_Pos = 0x12
	// Bit mask of USART3EN field.
	RCC_APB1ENR1_USART3EN_Msk = 0x40000
	// Bit USART3EN.
	RCC_APB1ENR1_USART3EN = 0x40000
	// The selected clock is disabled
	RCC_APB1ENR1_USART3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_USART3EN_Enabled = 0x1
	// Position of UART4EN field.
	RCC_APB1ENR1_UART4EN_Pos = 0x13
	// Bit mask of UART4EN field.
	RCC_APB1ENR1_UART4EN_Msk = 0x80000
	// Bit UART4EN.
	RCC_APB1ENR1_UART4EN = 0x80000
	// The selected clock is disabled
	RCC_APB1ENR1_UART4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_UART4EN_Enabled = 0x1
	// Position of UART5EN field.
	RCC_APB1ENR1_UART5EN_Pos = 0x14
	// Bit mask of UART5EN field.
	RCC_APB1ENR1_UART5EN_Msk = 0x100000
	// Bit UART5EN.
	RCC_APB1ENR1_UART5EN = 0x100000
	// The selected clock is disabled
	RCC_APB1ENR1_UART5EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_UART5EN_Enabled = 0x1
	// Position of I2C1EN field.
	RCC_APB1ENR1_I2C1EN_Pos = 0x15
	// Bit mask of I2C1EN field.
	RCC_APB1ENR1_I2C1EN_Msk = 0x200000
	// Bit I2C1EN.
	RCC_APB1ENR1_I2C1EN = 0x200000
	// The selected clock is disabled
	RCC_APB1ENR1_I2C1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_I2C1EN_Enabled = 0x1
	// Position of I2C2EN field.
	RCC_APB1ENR1_I2C2EN_Pos = 0x16
	// Bit mask of I2C2EN field.
	RCC_APB1ENR1_I2C2EN_Msk = 0x400000
	// Bit I2C2EN.
	RCC_APB1ENR1_I2C2EN = 0x400000
	// The selected clock is disabled
	RCC_APB1ENR1_I2C2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_I2C2EN_Enabled = 0x1
	// Position of I2C3EN field.
	RCC_APB1ENR1_I2C3EN_Pos = 0x17
	// Bit mask of I2C3EN field.
	RCC_APB1ENR1_I2C3EN_Msk = 0x800000
	// Bit I2C3EN.
	RCC_APB1ENR1_I2C3EN = 0x800000
	// The selected clock is disabled
	RCC_APB1ENR1_I2C3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_I2C3EN_Enabled = 0x1
	// Position of CRSEN field.
	RCC_APB1ENR1_CRSEN_Pos = 0x18
	// Bit mask of CRSEN field.
	RCC_APB1ENR1_CRSEN_Msk = 0x1000000
	// Bit CRSEN.
	RCC_APB1ENR1_CRSEN = 0x1000000
	// The selected clock is disabled
	RCC_APB1ENR1_CRSEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_CRSEN_Enabled = 0x1
	// Position of PWREN field.
	RCC_APB1ENR1_PWREN_Pos = 0x1c
	// Bit mask of PWREN field.
	RCC_APB1ENR1_PWREN_Msk = 0x10000000
	// Bit PWREN.
	RCC_APB1ENR1_PWREN = 0x10000000
	// The selected clock is disabled
	RCC_APB1ENR1_PWREN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_PWREN_Enabled = 0x1
	// Position of DAC1EN field.
	RCC_APB1ENR1_DAC1EN_Pos = 0x1d
	// Bit mask of DAC1EN field.
	RCC_APB1ENR1_DAC1EN_Msk = 0x20000000
	// Bit DAC1EN.
	RCC_APB1ENR1_DAC1EN = 0x20000000
	// The selected clock is disabled
	RCC_APB1ENR1_DAC1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_DAC1EN_Enabled = 0x1
	// Position of OPAMPEN field.
	RCC_APB1ENR1_OPAMPEN_Pos = 0x1e
	// Bit mask of OPAMPEN field.
	RCC_APB1ENR1_OPAMPEN_Msk = 0x40000000
	// Bit OPAMPEN.
	RCC_APB1ENR1_OPAMPEN = 0x40000000
	// The selected clock is disabled
	RCC_APB1ENR1_OPAMPEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_OPAMPEN_Enabled = 0x1
	// Position of LPTIM1EN field.
	RCC_APB1ENR1_LPTIM1EN_Pos = 0x1f
	// Bit mask of LPTIM1EN field.
	RCC_APB1ENR1_LPTIM1EN_Msk = 0x80000000
	// Bit LPTIM1EN.
	RCC_APB1ENR1_LPTIM1EN = 0x80000000
	// The selected clock is disabled
	RCC_APB1ENR1_LPTIM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR1_LPTIM1EN_Enabled = 0x1

	// APB1ENR2: APB1 peripheral clock enable register 2
	// Position of LPUART1EN field.
	RCC_APB1ENR2_LPUART1EN_Pos = 0x0
	// Bit mask of LPUART1EN field.
	RCC_APB1ENR2_LPUART1EN_Msk = 0x1
	// Bit LPUART1EN.
	RCC_APB1ENR2_LPUART1EN = 0x1
	// The selected clock is disabled
	RCC_APB1ENR2_LPUART1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR2_LPUART1EN_Enabled = 0x1
	// Position of I2C4EN field.
	RCC_APB1ENR2_I2C4EN_Pos = 0x1
	// Bit mask of I2C4EN field.
	RCC_APB1ENR2_I2C4EN_Msk = 0x2
	// Bit I2C4EN.
	RCC_APB1ENR2_I2C4EN = 0x2
	// The selected clock is disabled
	RCC_APB1ENR2_I2C4EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR2_I2C4EN_Enabled = 0x1
	// Position of LPTIM2EN field.
	RCC_APB1ENR2_LPTIM2EN_Pos = 0x5
	// Bit mask of LPTIM2EN field.
	RCC_APB1ENR2_LPTIM2EN_Msk = 0x20
	// Bit LPTIM2EN.
	RCC_APB1ENR2_LPTIM2EN = 0x20
	// The selected clock is disabled
	RCC_APB1ENR2_LPTIM2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR2_LPTIM2EN_Enabled = 0x1
	// Position of LPTIM3EN field.
	RCC_APB1ENR2_LPTIM3EN_Pos = 0x6
	// Bit mask of LPTIM3EN field.
	RCC_APB1ENR2_LPTIM3EN_Msk = 0x40
	// Bit LPTIM3EN.
	RCC_APB1ENR2_LPTIM3EN = 0x40
	// The selected clock is disabled
	RCC_APB1ENR2_LPTIM3EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR2_LPTIM3EN_Enabled = 0x1
	// Position of FDCAN1EN field.
	RCC_APB1ENR2_FDCAN1EN_Pos = 0x9
	// Bit mask of FDCAN1EN field.
	RCC_APB1ENR2_FDCAN1EN_Msk = 0x200
	// Bit FDCAN1EN.
	RCC_APB1ENR2_FDCAN1EN = 0x200
	// The selected clock is disabled
	RCC_APB1ENR2_FDCAN1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR2_FDCAN1EN_Enabled = 0x1
	// Position of USBFSEN field.
	RCC_APB1ENR2_USBFSEN_Pos = 0x15
	// Bit mask of USBFSEN field.
	RCC_APB1ENR2_USBFSEN_Msk = 0x200000
	// Bit USBFSEN.
	RCC_APB1ENR2_USBFSEN = 0x200000
	// The selected clock is disabled
	RCC_APB1ENR2_USBFSEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR2_USBFSEN_Enabled = 0x1
	// Position of UCPD1EN field.
	RCC_APB1ENR2_UCPD1EN_Pos = 0x17
	// Bit mask of UCPD1EN field.
	RCC_APB1ENR2_UCPD1EN_Msk = 0x800000
	// Bit UCPD1EN.
	RCC_APB1ENR2_UCPD1EN = 0x800000
	// The selected clock is disabled
	RCC_APB1ENR2_UCPD1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB1ENR2_UCPD1EN_Enabled = 0x1

	// APB2ENR: APB2ENR
	// Position of SYSCFGEN field.
	RCC_APB2ENR_SYSCFGEN_Pos = 0x0
	// Bit mask of SYSCFGEN field.
	RCC_APB2ENR_SYSCFGEN_Msk = 0x1
	// Bit SYSCFGEN.
	RCC_APB2ENR_SYSCFGEN = 0x1
	// The selected clock is disabled
	RCC_APB2ENR_SYSCFGEN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SYSCFGEN_Enabled = 0x1
	// Position of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Pos = 0xb
	// Bit mask of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Msk = 0x800
	// Bit TIM1EN.
	RCC_APB2ENR_TIM1EN = 0x800
	// The selected clock is disabled
	RCC_APB2ENR_TIM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM1EN_Enabled = 0x1
	// Position of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Pos = 0xc
	// Bit mask of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Msk = 0x1000
	// Bit SPI1EN.
	RCC_APB2ENR_SPI1EN = 0x1000
	// The selected clock is disabled
	RCC_APB2ENR_SPI1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SPI1EN_Enabled = 0x1
	// Position of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Pos = 0xd
	// Bit mask of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Msk = 0x2000
	// Bit TIM8EN.
	RCC_APB2ENR_TIM8EN = 0x2000
	// The selected clock is disabled
	RCC_APB2ENR_TIM8EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM8EN_Enabled = 0x1
	// Position of USART1EN field.
	RCC_APB2ENR_USART1EN_Pos = 0xe
	// Bit mask of USART1EN field.
	RCC_APB2ENR_USART1EN_Msk = 0x4000
	// Bit USART1EN.
	RCC_APB2ENR_USART1EN = 0x4000
	// The selected clock is disabled
	RCC_APB2ENR_USART1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_USART1EN_Enabled = 0x1
	// Position of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Pos = 0x10
	// Bit mask of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Msk = 0x10000
	// Bit TIM15EN.
	RCC_APB2ENR_TIM15EN = 0x10000
	// The selected clock is disabled
	RCC_APB2ENR_TIM15EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM15EN_Enabled = 0x1
	// Position of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Pos = 0x11
	// Bit mask of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Msk = 0x20000
	// Bit TIM16EN.
	RCC_APB2ENR_TIM16EN = 0x20000
	// The selected clock is disabled
	RCC_APB2ENR_TIM16EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM16EN_Enabled = 0x1
	// Position of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Pos = 0x12
	// Bit mask of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Msk = 0x40000
	// Bit TIM17EN.
	RCC_APB2ENR_TIM17EN = 0x40000
	// The selected clock is disabled
	RCC_APB2ENR_TIM17EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_TIM17EN_Enabled = 0x1
	// Position of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Pos = 0x15
	// Bit mask of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Msk = 0x200000
	// Bit SAI1EN.
	RCC_APB2ENR_SAI1EN = 0x200000
	// The selected clock is disabled
	RCC_APB2ENR_SAI1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SAI1EN_Enabled = 0x1
	// Position of SAI2EN field.
	RCC_APB2ENR_SAI2EN_Pos = 0x16
	// Bit mask of SAI2EN field.
	RCC_APB2ENR_SAI2EN_Msk = 0x400000
	// Bit SAI2EN.
	RCC_APB2ENR_SAI2EN = 0x400000
	// The selected clock is disabled
	RCC_APB2ENR_SAI2EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_SAI2EN_Enabled = 0x1
	// Position of DFSDM1EN field.
	RCC_APB2ENR_DFSDM1EN_Pos = 0x18
	// Bit mask of DFSDM1EN field.
	RCC_APB2ENR_DFSDM1EN_Msk = 0x1000000
	// Bit DFSDM1EN.
	RCC_APB2ENR_DFSDM1EN = 0x1000000
	// The selected clock is disabled
	RCC_APB2ENR_DFSDM1EN_Disabled = 0x0
	// The selected clock is enabled
	RCC_APB2ENR_DFSDM1EN_Enabled = 0x1

	// AHB1SMENR: AHB1 peripheral clocks enable in Sleep and Stop modes register
	// Position of DMA1SMEN field.
	RCC_AHB1SMENR_DMA1SMEN_Pos = 0x0
	// Bit mask of DMA1SMEN field.
	RCC_AHB1SMENR_DMA1SMEN_Msk = 0x1
	// Bit DMA1SMEN.
	RCC_AHB1SMENR_DMA1SMEN = 0x1
	// Position of DMA2SMEN field.
	RCC_AHB1SMENR_DMA2SMEN_Pos = 0x1
	// Bit mask of DMA2SMEN field.
	RCC_AHB1SMENR_DMA2SMEN_Msk = 0x2
	// Bit DMA2SMEN.
	RCC_AHB1SMENR_DMA2SMEN = 0x2
	// Position of DMAMUX1SMEN field.
	RCC_AHB1SMENR_DMAMUX1SMEN_Pos = 0x2
	// Bit mask of DMAMUX1SMEN field.
	RCC_AHB1SMENR_DMAMUX1SMEN_Msk = 0x4
	// Bit DMAMUX1SMEN.
	RCC_AHB1SMENR_DMAMUX1SMEN = 0x4
	// Position of FLASHSMEN field.
	RCC_AHB1SMENR_FLASHSMEN_Pos = 0x8
	// Bit mask of FLASHSMEN field.
	RCC_AHB1SMENR_FLASHSMEN_Msk = 0x100
	// Bit FLASHSMEN.
	RCC_AHB1SMENR_FLASHSMEN = 0x100
	// Position of SRAM1SMEN field.
	RCC_AHB1SMENR_SRAM1SMEN_Pos = 0x9
	// Bit mask of SRAM1SMEN field.
	RCC_AHB1SMENR_SRAM1SMEN_Msk = 0x200
	// Bit SRAM1SMEN.
	RCC_AHB1SMENR_SRAM1SMEN = 0x200
	// Position of CRCSMEN field.
	RCC_AHB1SMENR_CRCSMEN_Pos = 0xc
	// Bit mask of CRCSMEN field.
	RCC_AHB1SMENR_CRCSMEN_Msk = 0x1000
	// Bit CRCSMEN.
	RCC_AHB1SMENR_CRCSMEN = 0x1000
	// Position of TSCSMEN field.
	RCC_AHB1SMENR_TSCSMEN_Pos = 0x10
	// Bit mask of TSCSMEN field.
	RCC_AHB1SMENR_TSCSMEN_Msk = 0x10000
	// Bit TSCSMEN.
	RCC_AHB1SMENR_TSCSMEN = 0x10000
	// Position of GTZCSMEN field.
	RCC_AHB1SMENR_GTZCSMEN_Pos = 0x16
	// Bit mask of GTZCSMEN field.
	RCC_AHB1SMENR_GTZCSMEN_Msk = 0x400000
	// Bit GTZCSMEN.
	RCC_AHB1SMENR_GTZCSMEN = 0x400000
	// Position of ICACHESMEN field.
	RCC_AHB1SMENR_ICACHESMEN_Pos = 0x17
	// Bit mask of ICACHESMEN field.
	RCC_AHB1SMENR_ICACHESMEN_Msk = 0x800000
	// Bit ICACHESMEN.
	RCC_AHB1SMENR_ICACHESMEN = 0x800000

	// AHB2SMENR: AHB2 peripheral clocks enable in Sleep and Stop modes register
	// Position of GPIOASMEN field.
	RCC_AHB2SMENR_GPIOASMEN_Pos = 0x0
	// Bit mask of GPIOASMEN field.
	RCC_AHB2SMENR_GPIOASMEN_Msk = 0x1
	// Bit GPIOASMEN.
	RCC_AHB2SMENR_GPIOASMEN = 0x1
	// Position of GPIOBSMEN field.
	RCC_AHB2SMENR_GPIOBSMEN_Pos = 0x1
	// Bit mask of GPIOBSMEN field.
	RCC_AHB2SMENR_GPIOBSMEN_Msk = 0x2
	// Bit GPIOBSMEN.
	RCC_AHB2SMENR_GPIOBSMEN = 0x2
	// Position of GPIOCSMEN field.
	RCC_AHB2SMENR_GPIOCSMEN_Pos = 0x2
	// Bit mask of GPIOCSMEN field.
	RCC_AHB2SMENR_GPIOCSMEN_Msk = 0x4
	// Bit GPIOCSMEN.
	RCC_AHB2SMENR_GPIOCSMEN = 0x4
	// Position of GPIODSMEN field.
	RCC_AHB2SMENR_GPIODSMEN_Pos = 0x3
	// Bit mask of GPIODSMEN field.
	RCC_AHB2SMENR_GPIODSMEN_Msk = 0x8
	// Bit GPIODSMEN.
	RCC_AHB2SMENR_GPIODSMEN = 0x8
	// Position of GPIOESMEN field.
	RCC_AHB2SMENR_GPIOESMEN_Pos = 0x4
	// Bit mask of GPIOESMEN field.
	RCC_AHB2SMENR_GPIOESMEN_Msk = 0x10
	// Bit GPIOESMEN.
	RCC_AHB2SMENR_GPIOESMEN = 0x10
	// Position of GPIOFSMEN field.
	RCC_AHB2SMENR_GPIOFSMEN_Pos = 0x5
	// Bit mask of GPIOFSMEN field.
	RCC_AHB2SMENR_GPIOFSMEN_Msk = 0x20
	// Bit GPIOFSMEN.
	RCC_AHB2SMENR_GPIOFSMEN = 0x20
	// Position of GPIOGSMEN field.
	RCC_AHB2SMENR_GPIOGSMEN_Pos = 0x6
	// Bit mask of GPIOGSMEN field.
	RCC_AHB2SMENR_GPIOGSMEN_Msk = 0x40
	// Bit GPIOGSMEN.
	RCC_AHB2SMENR_GPIOGSMEN = 0x40
	// Position of GPIOHSMEN field.
	RCC_AHB2SMENR_GPIOHSMEN_Pos = 0x7
	// Bit mask of GPIOHSMEN field.
	RCC_AHB2SMENR_GPIOHSMEN_Msk = 0x80
	// Bit GPIOHSMEN.
	RCC_AHB2SMENR_GPIOHSMEN = 0x80
	// Position of SRAM2SMEN field.
	RCC_AHB2SMENR_SRAM2SMEN_Pos = 0x9
	// Bit mask of SRAM2SMEN field.
	RCC_AHB2SMENR_SRAM2SMEN_Msk = 0x200
	// Bit SRAM2SMEN.
	RCC_AHB2SMENR_SRAM2SMEN = 0x200
	// Position of ADCFSSMEN field.
	RCC_AHB2SMENR_ADCFSSMEN_Pos = 0xd
	// Bit mask of ADCFSSMEN field.
	RCC_AHB2SMENR_ADCFSSMEN_Msk = 0x2000
	// Bit ADCFSSMEN.
	RCC_AHB2SMENR_ADCFSSMEN = 0x2000
	// Position of AESSMEN field.
	RCC_AHB2SMENR_AESSMEN_Pos = 0x10
	// Bit mask of AESSMEN field.
	RCC_AHB2SMENR_AESSMEN_Msk = 0x10000
	// Bit AESSMEN.
	RCC_AHB2SMENR_AESSMEN = 0x10000
	// Position of HASHSMEN field.
	RCC_AHB2SMENR_HASHSMEN_Pos = 0x11
	// Bit mask of HASHSMEN field.
	RCC_AHB2SMENR_HASHSMEN_Msk = 0x20000
	// Bit HASHSMEN.
	RCC_AHB2SMENR_HASHSMEN = 0x20000
	// Position of RNGSMEN field.
	RCC_AHB2SMENR_RNGSMEN_Pos = 0x12
	// Bit mask of RNGSMEN field.
	RCC_AHB2SMENR_RNGSMEN_Msk = 0x40000
	// Bit RNGSMEN.
	RCC_AHB2SMENR_RNGSMEN = 0x40000
	// Position of PKASMEN field.
	RCC_AHB2SMENR_PKASMEN_Pos = 0x13
	// Bit mask of PKASMEN field.
	RCC_AHB2SMENR_PKASMEN_Msk = 0x80000
	// Bit PKASMEN.
	RCC_AHB2SMENR_PKASMEN = 0x80000
	// Position of OTFDEC1SMEN field.
	RCC_AHB2SMENR_OTFDEC1SMEN_Pos = 0x15
	// Bit mask of OTFDEC1SMEN field.
	RCC_AHB2SMENR_OTFDEC1SMEN_Msk = 0x200000
	// Bit OTFDEC1SMEN.
	RCC_AHB2SMENR_OTFDEC1SMEN = 0x200000
	// Position of SDMMC1SMEN field.
	RCC_AHB2SMENR_SDMMC1SMEN_Pos = 0x16
	// Bit mask of SDMMC1SMEN field.
	RCC_AHB2SMENR_SDMMC1SMEN_Msk = 0x400000
	// Bit SDMMC1SMEN.
	RCC_AHB2SMENR_SDMMC1SMEN = 0x400000

	// AHB3SMENR: AHB3 peripheral clocks enable in Sleep and Stop modes register
	// Position of FMCSMEN field.
	RCC_AHB3SMENR_FMCSMEN_Pos = 0x0
	// Bit mask of FMCSMEN field.
	RCC_AHB3SMENR_FMCSMEN_Msk = 0x1
	// Bit FMCSMEN.
	RCC_AHB3SMENR_FMCSMEN = 0x1
	// Position of OSPI1SMEN field.
	RCC_AHB3SMENR_OSPI1SMEN_Pos = 0x8
	// Bit mask of OSPI1SMEN field.
	RCC_AHB3SMENR_OSPI1SMEN_Msk = 0x100
	// Bit OSPI1SMEN.
	RCC_AHB3SMENR_OSPI1SMEN = 0x100

	// APB1SMENR1: APB1SMENR1
	// Position of TIM2SMEN field.
	RCC_APB1SMENR1_TIM2SMEN_Pos = 0x0
	// Bit mask of TIM2SMEN field.
	RCC_APB1SMENR1_TIM2SMEN_Msk = 0x1
	// Bit TIM2SMEN.
	RCC_APB1SMENR1_TIM2SMEN = 0x1
	// Position of TIM3SMEN field.
	RCC_APB1SMENR1_TIM3SMEN_Pos = 0x1
	// Bit mask of TIM3SMEN field.
	RCC_APB1SMENR1_TIM3SMEN_Msk = 0x2
	// Bit TIM3SMEN.
	RCC_APB1SMENR1_TIM3SMEN = 0x2
	// Position of TIM4SMEN field.
	RCC_APB1SMENR1_TIM4SMEN_Pos = 0x2
	// Bit mask of TIM4SMEN field.
	RCC_APB1SMENR1_TIM4SMEN_Msk = 0x4
	// Bit TIM4SMEN.
	RCC_APB1SMENR1_TIM4SMEN = 0x4
	// Position of TIM5SMEN field.
	RCC_APB1SMENR1_TIM5SMEN_Pos = 0x3
	// Bit mask of TIM5SMEN field.
	RCC_APB1SMENR1_TIM5SMEN_Msk = 0x8
	// Bit TIM5SMEN.
	RCC_APB1SMENR1_TIM5SMEN = 0x8
	// Position of TIM6SMEN field.
	RCC_APB1SMENR1_TIM6SMEN_Pos = 0x4
	// Bit mask of TIM6SMEN field.
	RCC_APB1SMENR1_TIM6SMEN_Msk = 0x10
	// Bit TIM6SMEN.
	RCC_APB1SMENR1_TIM6SMEN = 0x10
	// Position of TIM7SMEN field.
	RCC_APB1SMENR1_TIM7SMEN_Pos = 0x5
	// Bit mask of TIM7SMEN field.
	RCC_APB1SMENR1_TIM7SMEN_Msk = 0x20
	// Bit TIM7SMEN.
	RCC_APB1SMENR1_TIM7SMEN = 0x20
	// Position of RTCAPBSMEN field.
	RCC_APB1SMENR1_RTCAPBSMEN_Pos = 0xa
	// Bit mask of RTCAPBSMEN field.
	RCC_APB1SMENR1_RTCAPBSMEN_Msk = 0x400
	// Bit RTCAPBSMEN.
	RCC_APB1SMENR1_RTCAPBSMEN = 0x400
	// Position of WWDGSMEN field.
	RCC_APB1SMENR1_WWDGSMEN_Pos = 0xb
	// Bit mask of WWDGSMEN field.
	RCC_APB1SMENR1_WWDGSMEN_Msk = 0x800
	// Bit WWDGSMEN.
	RCC_APB1SMENR1_WWDGSMEN = 0x800
	// Position of SPI2SMEN field.
	RCC_APB1SMENR1_SPI2SMEN_Pos = 0xe
	// Bit mask of SPI2SMEN field.
	RCC_APB1SMENR1_SPI2SMEN_Msk = 0x4000
	// Bit SPI2SMEN.
	RCC_APB1SMENR1_SPI2SMEN = 0x4000
	// Position of SP3SMEN field.
	RCC_APB1SMENR1_SP3SMEN_Pos = 0xf
	// Bit mask of SP3SMEN field.
	RCC_APB1SMENR1_SP3SMEN_Msk = 0x8000
	// Bit SP3SMEN.
	RCC_APB1SMENR1_SP3SMEN = 0x8000
	// Position of USART2SMEN field.
	RCC_APB1SMENR1_USART2SMEN_Pos = 0x11
	// Bit mask of USART2SMEN field.
	RCC_APB1SMENR1_USART2SMEN_Msk = 0x20000
	// Bit USART2SMEN.
	RCC_APB1SMENR1_USART2SMEN = 0x20000
	// Position of USART3SMEN field.
	RCC_APB1SMENR1_USART3SMEN_Pos = 0x12
	// Bit mask of USART3SMEN field.
	RCC_APB1SMENR1_USART3SMEN_Msk = 0x40000
	// Bit USART3SMEN.
	RCC_APB1SMENR1_USART3SMEN = 0x40000
	// Position of UART4SMEN field.
	RCC_APB1SMENR1_UART4SMEN_Pos = 0x13
	// Bit mask of UART4SMEN field.
	RCC_APB1SMENR1_UART4SMEN_Msk = 0x80000
	// Bit UART4SMEN.
	RCC_APB1SMENR1_UART4SMEN = 0x80000
	// Position of UART5SMEN field.
	RCC_APB1SMENR1_UART5SMEN_Pos = 0x14
	// Bit mask of UART5SMEN field.
	RCC_APB1SMENR1_UART5SMEN_Msk = 0x100000
	// Bit UART5SMEN.
	RCC_APB1SMENR1_UART5SMEN = 0x100000
	// Position of I2C1SMEN field.
	RCC_APB1SMENR1_I2C1SMEN_Pos = 0x15
	// Bit mask of I2C1SMEN field.
	RCC_APB1SMENR1_I2C1SMEN_Msk = 0x200000
	// Bit I2C1SMEN.
	RCC_APB1SMENR1_I2C1SMEN = 0x200000
	// Position of I2C2SMEN field.
	RCC_APB1SMENR1_I2C2SMEN_Pos = 0x16
	// Bit mask of I2C2SMEN field.
	RCC_APB1SMENR1_I2C2SMEN_Msk = 0x400000
	// Bit I2C2SMEN.
	RCC_APB1SMENR1_I2C2SMEN = 0x400000
	// Position of I2C3SMEN field.
	RCC_APB1SMENR1_I2C3SMEN_Pos = 0x17
	// Bit mask of I2C3SMEN field.
	RCC_APB1SMENR1_I2C3SMEN_Msk = 0x800000
	// Bit I2C3SMEN.
	RCC_APB1SMENR1_I2C3SMEN = 0x800000
	// Position of CRSSMEN field.
	RCC_APB1SMENR1_CRSSMEN_Pos = 0x18
	// Bit mask of CRSSMEN field.
	RCC_APB1SMENR1_CRSSMEN_Msk = 0x1000000
	// Bit CRSSMEN.
	RCC_APB1SMENR1_CRSSMEN = 0x1000000
	// Position of PWRSMEN field.
	RCC_APB1SMENR1_PWRSMEN_Pos = 0x1c
	// Bit mask of PWRSMEN field.
	RCC_APB1SMENR1_PWRSMEN_Msk = 0x10000000
	// Bit PWRSMEN.
	RCC_APB1SMENR1_PWRSMEN = 0x10000000
	// Position of DAC1SMEN field.
	RCC_APB1SMENR1_DAC1SMEN_Pos = 0x1d
	// Bit mask of DAC1SMEN field.
	RCC_APB1SMENR1_DAC1SMEN_Msk = 0x20000000
	// Bit DAC1SMEN.
	RCC_APB1SMENR1_DAC1SMEN = 0x20000000
	// Position of OPAMPSMEN field.
	RCC_APB1SMENR1_OPAMPSMEN_Pos = 0x1e
	// Bit mask of OPAMPSMEN field.
	RCC_APB1SMENR1_OPAMPSMEN_Msk = 0x40000000
	// Bit OPAMPSMEN.
	RCC_APB1SMENR1_OPAMPSMEN = 0x40000000
	// Position of LPTIM1SMEN field.
	RCC_APB1SMENR1_LPTIM1SMEN_Pos = 0x1f
	// Bit mask of LPTIM1SMEN field.
	RCC_APB1SMENR1_LPTIM1SMEN_Msk = 0x80000000
	// Bit LPTIM1SMEN.
	RCC_APB1SMENR1_LPTIM1SMEN = 0x80000000

	// APB1SMENR2: APB1 peripheral clocks enable in Sleep and Stop modes register 2
	// Position of LPUART1SMEN field.
	RCC_APB1SMENR2_LPUART1SMEN_Pos = 0x0
	// Bit mask of LPUART1SMEN field.
	RCC_APB1SMENR2_LPUART1SMEN_Msk = 0x1
	// Bit LPUART1SMEN.
	RCC_APB1SMENR2_LPUART1SMEN = 0x1
	// Position of I2C4SMEN field.
	RCC_APB1SMENR2_I2C4SMEN_Pos = 0x1
	// Bit mask of I2C4SMEN field.
	RCC_APB1SMENR2_I2C4SMEN_Msk = 0x2
	// Bit I2C4SMEN.
	RCC_APB1SMENR2_I2C4SMEN = 0x2
	// Position of LPTIM2SMEN field.
	RCC_APB1SMENR2_LPTIM2SMEN_Pos = 0x5
	// Bit mask of LPTIM2SMEN field.
	RCC_APB1SMENR2_LPTIM2SMEN_Msk = 0x20
	// Bit LPTIM2SMEN.
	RCC_APB1SMENR2_LPTIM2SMEN = 0x20
	// Position of LPTIM3SMEN field.
	RCC_APB1SMENR2_LPTIM3SMEN_Pos = 0x6
	// Bit mask of LPTIM3SMEN field.
	RCC_APB1SMENR2_LPTIM3SMEN_Msk = 0x40
	// Bit LPTIM3SMEN.
	RCC_APB1SMENR2_LPTIM3SMEN = 0x40
	// Position of FDCAN1SMEN field.
	RCC_APB1SMENR2_FDCAN1SMEN_Pos = 0x9
	// Bit mask of FDCAN1SMEN field.
	RCC_APB1SMENR2_FDCAN1SMEN_Msk = 0x200
	// Bit FDCAN1SMEN.
	RCC_APB1SMENR2_FDCAN1SMEN = 0x200
	// Position of USBFSSMEN field.
	RCC_APB1SMENR2_USBFSSMEN_Pos = 0x15
	// Bit mask of USBFSSMEN field.
	RCC_APB1SMENR2_USBFSSMEN_Msk = 0x200000
	// Bit USBFSSMEN.
	RCC_APB1SMENR2_USBFSSMEN = 0x200000
	// Position of UCPD1SMEN field.
	RCC_APB1SMENR2_UCPD1SMEN_Pos = 0x17
	// Bit mask of UCPD1SMEN field.
	RCC_APB1SMENR2_UCPD1SMEN_Msk = 0x800000
	// Bit UCPD1SMEN.
	RCC_APB1SMENR2_UCPD1SMEN = 0x800000

	// APB2SMENR: APB2SMENR
	// Position of SYSCFGSMEN field.
	RCC_APB2SMENR_SYSCFGSMEN_Pos = 0x0
	// Bit mask of SYSCFGSMEN field.
	RCC_APB2SMENR_SYSCFGSMEN_Msk = 0x1
	// Bit SYSCFGSMEN.
	RCC_APB2SMENR_SYSCFGSMEN = 0x1
	// Position of TIM1SMEN field.
	RCC_APB2SMENR_TIM1SMEN_Pos = 0xb
	// Bit mask of TIM1SMEN field.
	RCC_APB2SMENR_TIM1SMEN_Msk = 0x800
	// Bit TIM1SMEN.
	RCC_APB2SMENR_TIM1SMEN = 0x800
	// Position of SPI1SMEN field.
	RCC_APB2SMENR_SPI1SMEN_Pos = 0xc
	// Bit mask of SPI1SMEN field.
	RCC_APB2SMENR_SPI1SMEN_Msk = 0x1000
	// Bit SPI1SMEN.
	RCC_APB2SMENR_SPI1SMEN = 0x1000
	// Position of TIM8SMEN field.
	RCC_APB2SMENR_TIM8SMEN_Pos = 0xd
	// Bit mask of TIM8SMEN field.
	RCC_APB2SMENR_TIM8SMEN_Msk = 0x2000
	// Bit TIM8SMEN.
	RCC_APB2SMENR_TIM8SMEN = 0x2000
	// Position of USART1SMEN field.
	RCC_APB2SMENR_USART1SMEN_Pos = 0xe
	// Bit mask of USART1SMEN field.
	RCC_APB2SMENR_USART1SMEN_Msk = 0x4000
	// Bit USART1SMEN.
	RCC_APB2SMENR_USART1SMEN = 0x4000
	// Position of TIM15SMEN field.
	RCC_APB2SMENR_TIM15SMEN_Pos = 0x10
	// Bit mask of TIM15SMEN field.
	RCC_APB2SMENR_TIM15SMEN_Msk = 0x10000
	// Bit TIM15SMEN.
	RCC_APB2SMENR_TIM15SMEN = 0x10000
	// Position of TIM16SMEN field.
	RCC_APB2SMENR_TIM16SMEN_Pos = 0x11
	// Bit mask of TIM16SMEN field.
	RCC_APB2SMENR_TIM16SMEN_Msk = 0x20000
	// Bit TIM16SMEN.
	RCC_APB2SMENR_TIM16SMEN = 0x20000
	// Position of TIM17SMEN field.
	RCC_APB2SMENR_TIM17SMEN_Pos = 0x12
	// Bit mask of TIM17SMEN field.
	RCC_APB2SMENR_TIM17SMEN_Msk = 0x40000
	// Bit TIM17SMEN.
	RCC_APB2SMENR_TIM17SMEN = 0x40000
	// Position of SAI1SMEN field.
	RCC_APB2SMENR_SAI1SMEN_Pos = 0x15
	// Bit mask of SAI1SMEN field.
	RCC_APB2SMENR_SAI1SMEN_Msk = 0x200000
	// Bit SAI1SMEN.
	RCC_APB2SMENR_SAI1SMEN = 0x200000
	// Position of SAI2SMEN field.
	RCC_APB2SMENR_SAI2SMEN_Pos = 0x16
	// Bit mask of SAI2SMEN field.
	RCC_APB2SMENR_SAI2SMEN_Msk = 0x400000
	// Bit SAI2SMEN.
	RCC_APB2SMENR_SAI2SMEN = 0x400000
	// Position of DFSDM1SMEN field.
	RCC_APB2SMENR_DFSDM1SMEN_Pos = 0x18
	// Bit mask of DFSDM1SMEN field.
	RCC_APB2SMENR_DFSDM1SMEN_Msk = 0x1000000
	// Bit DFSDM1SMEN.
	RCC_APB2SMENR_DFSDM1SMEN = 0x1000000

	// CCIPR1: CCIPR1
	// Position of ADCSEL field.
	RCC_CCIPR1_ADCSEL_Pos = 0x1c
	// Bit mask of ADCSEL field.
	RCC_CCIPR1_ADCSEL_Msk = 0x30000000
	// Position of CLK48MSEL field.
	RCC_CCIPR1_CLK48MSEL_Pos = 0x1a
	// Bit mask of CLK48MSEL field.
	RCC_CCIPR1_CLK48MSEL_Msk = 0xc000000
	// Position of FDCANSEL field.
	RCC_CCIPR1_FDCANSEL_Pos = 0x18
	// Bit mask of FDCANSEL field.
	RCC_CCIPR1_FDCANSEL_Msk = 0x3000000
	// Position of LPTIM3SEL field.
	RCC_CCIPR1_LPTIM3SEL_Pos = 0x16
	// Bit mask of LPTIM3SEL field.
	RCC_CCIPR1_LPTIM3SEL_Msk = 0xc00000
	// Position of LPTIM2SEL field.
	RCC_CCIPR1_LPTIM2SEL_Pos = 0x14
	// Bit mask of LPTIM2SEL field.
	RCC_CCIPR1_LPTIM2SEL_Msk = 0x300000
	// Position of LPTIM1SEL field.
	RCC_CCIPR1_LPTIM1SEL_Pos = 0x12
	// Bit mask of LPTIM1SEL field.
	RCC_CCIPR1_LPTIM1SEL_Msk = 0xc0000
	// Position of I2C3SEL field.
	RCC_CCIPR1_I2C3SEL_Pos = 0x10
	// Bit mask of I2C3SEL field.
	RCC_CCIPR1_I2C3SEL_Msk = 0x30000
	// Position of I2C2SEL field.
	RCC_CCIPR1_I2C2SEL_Pos = 0xe
	// Bit mask of I2C2SEL field.
	RCC_CCIPR1_I2C2SEL_Msk = 0xc000
	// Position of I2C1SEL field.
	RCC_CCIPR1_I2C1SEL_Pos = 0xc
	// Bit mask of I2C1SEL field.
	RCC_CCIPR1_I2C1SEL_Msk = 0x3000
	// Position of LPUART1SEL field.
	RCC_CCIPR1_LPUART1SEL_Pos = 0xa
	// Bit mask of LPUART1SEL field.
	RCC_CCIPR1_LPUART1SEL_Msk = 0xc00
	// Position of UART5SEL field.
	RCC_CCIPR1_UART5SEL_Pos = 0x8
	// Bit mask of UART5SEL field.
	RCC_CCIPR1_UART5SEL_Msk = 0x300
	// Position of UART4SEL field.
	RCC_CCIPR1_UART4SEL_Pos = 0x6
	// Bit mask of UART4SEL field.
	RCC_CCIPR1_UART4SEL_Msk = 0xc0
	// Position of USART3SEL field.
	RCC_CCIPR1_USART3SEL_Pos = 0x4
	// Bit mask of USART3SEL field.
	RCC_CCIPR1_USART3SEL_Msk = 0x30
	// Position of USART2SEL field.
	RCC_CCIPR1_USART2SEL_Pos = 0x2
	// Bit mask of USART2SEL field.
	RCC_CCIPR1_USART2SEL_Msk = 0xc
	// Position of USART1SEL field.
	RCC_CCIPR1_USART1SEL_Pos = 0x0
	// Bit mask of USART1SEL field.
	RCC_CCIPR1_USART1SEL_Msk = 0x3

	// BDCR: BDCR
	// Position of LSCOSEL field.
	RCC_BDCR_LSCOSEL_Pos = 0x19
	// Bit mask of LSCOSEL field.
	RCC_BDCR_LSCOSEL_Msk = 0x2000000
	// Bit LSCOSEL.
	RCC_BDCR_LSCOSEL = 0x2000000
	// LSI clock selected"
	RCC_BDCR_LSCOSEL_LSI = 0x0
	// LSE clock selected
	RCC_BDCR_LSCOSEL_LSE = 0x1
	// Position of LSCOEN field.
	RCC_BDCR_LSCOEN_Pos = 0x18
	// Bit mask of LSCOEN field.
	RCC_BDCR_LSCOEN_Msk = 0x1000000
	// Bit LSCOEN.
	RCC_BDCR_LSCOEN = 0x1000000
	// LSCO disabled
	RCC_BDCR_LSCOEN_Disabled = 0x0
	// LSCO enabled
	RCC_BDCR_LSCOEN_Enabled = 0x1
	// Position of BDRST field.
	RCC_BDCR_BDRST_Pos = 0x10
	// Bit mask of BDRST field.
	RCC_BDCR_BDRST_Msk = 0x10000
	// Bit BDRST.
	RCC_BDCR_BDRST = 0x10000
	// Reset not activated
	RCC_BDCR_BDRST_Disabled = 0x0
	// Reset the entire RTC domain
	RCC_BDCR_BDRST_Enabled = 0x1
	// Position of RTCEN field.
	RCC_BDCR_RTCEN_Pos = 0xf
	// Bit mask of RTCEN field.
	RCC_BDCR_RTCEN_Msk = 0x8000
	// Bit RTCEN.
	RCC_BDCR_RTCEN = 0x8000
	// RTC clock disabled
	RCC_BDCR_RTCEN_Disabled = 0x0
	// RTC clock enabled
	RCC_BDCR_RTCEN_Enabled = 0x1
	// Position of LSESYSRDY field.
	RCC_BDCR_LSESYSRDY_Pos = 0xb
	// Bit mask of LSESYSRDY field.
	RCC_BDCR_LSESYSRDY_Msk = 0x800
	// Bit LSESYSRDY.
	RCC_BDCR_LSESYSRDY = 0x800
	// LSESYS clock not ready
	RCC_BDCR_LSESYSRDY_NotReady = 0x0
	// LSESYS clock ready
	RCC_BDCR_LSESYSRDY_Ready = 0x1
	// Position of RTCSEL field.
	RCC_BDCR_RTCSEL_Pos = 0x8
	// Bit mask of RTCSEL field.
	RCC_BDCR_RTCSEL_Msk = 0x300
	// No clock
	RCC_BDCR_RTCSEL_NoClock = 0x0
	// LSE oscillator clock used as RTC clock
	RCC_BDCR_RTCSEL_LSE = 0x1
	// LSI oscillator clock used as RTC clock
	RCC_BDCR_RTCSEL_LSI = 0x2
	// HSE oscillator clock divided by a prescaler used as RTC clock
	RCC_BDCR_RTCSEL_HSE = 0x3
	// Position of LSESYSEN field.
	RCC_BDCR_LSESYSEN_Pos = 0x7
	// Bit mask of LSESYSEN field.
	RCC_BDCR_LSESYSEN_Msk = 0x80
	// Bit LSESYSEN.
	RCC_BDCR_LSESYSEN = 0x80
	// LSESYS only enabled when requested by a peripheral or system function
	RCC_BDCR_LSESYSEN_Disabled = 0x0
	// LSESYS enabled always generated by RCC
	RCC_BDCR_LSESYSEN_Enabled = 0x1
	// Position of LSECSSD field.
	RCC_BDCR_LSECSSD_Pos = 0x6
	// Bit mask of LSECSSD field.
	RCC_BDCR_LSECSSD_Msk = 0x40
	// Bit LSECSSD.
	RCC_BDCR_LSECSSD = 0x40
	// No failure detected on LSE (32 kHz oscillator)
	RCC_BDCR_LSECSSD_NoFailure = 0x0
	// Failure detected on LSE (32 kHz oscillator)
	RCC_BDCR_LSECSSD_Failure = 0x1
	// Position of LSECSSON field.
	RCC_BDCR_LSECSSON_Pos = 0x5
	// Bit mask of LSECSSON field.
	RCC_BDCR_LSECSSON_Msk = 0x20
	// Bit LSECSSON.
	RCC_BDCR_LSECSSON = 0x20
	// CSS on LSE (32 kHz external oscillator) OFF
	RCC_BDCR_LSECSSON_Off = 0x0
	// CSS on LSE (32 kHz external oscillator) ON
	RCC_BDCR_LSECSSON_On = 0x1
	// Position of LSEDRV field.
	RCC_BDCR_LSEDRV_Pos = 0x3
	// Bit mask of LSEDRV field.
	RCC_BDCR_LSEDRV_Msk = 0x18
	// 'Xtal mode' lower driving capability
	RCC_BDCR_LSEDRV_Lower = 0x0
	// 'Xtal mode' medium low driving capability
	RCC_BDCR_LSEDRV_MediumLow = 0x1
	// 'Xtal mode' medium high driving capability
	RCC_BDCR_LSEDRV_MediumHigh = 0x2
	// 'Xtal mode' higher driving capability
	RCC_BDCR_LSEDRV_Higher = 0x3
	// Position of LSEBYP field.
	RCC_BDCR_LSEBYP_Pos = 0x2
	// Bit mask of LSEBYP field.
	RCC_BDCR_LSEBYP_Msk = 0x4
	// Bit LSEBYP.
	RCC_BDCR_LSEBYP = 0x4
	// LSE crystal oscillator not bypassed
	RCC_BDCR_LSEBYP_NotBypassed = 0x0
	// LSE crystal oscillator bypassed with external clock
	RCC_BDCR_LSEBYP_Bypassed = 0x1
	// Position of LSERDY field.
	RCC_BDCR_LSERDY_Pos = 0x1
	// Bit mask of LSERDY field.
	RCC_BDCR_LSERDY_Msk = 0x2
	// Bit LSERDY.
	RCC_BDCR_LSERDY = 0x2
	// LSE oscillator not ready
	RCC_BDCR_LSERDY_NotReady = 0x0
	// LSE oscillator ready
	RCC_BDCR_LSERDY_Ready = 0x1
	// Position of LSEON field.
	RCC_BDCR_LSEON_Pos = 0x0
	// Bit mask of LSEON field.
	RCC_BDCR_LSEON_Msk = 0x1
	// Bit LSEON.
	RCC_BDCR_LSEON = 0x1
	// LSE oscillator Off
	RCC_BDCR_LSEON_Off = 0x0
	// LSE oscillator On
	RCC_BDCR_LSEON_On = 0x1

	// CSR: CSR
	// Position of OBLRSTF field.
	RCC_CSR_OBLRSTF_Pos = 0x19
	// Bit mask of OBLRSTF field.
	RCC_CSR_OBLRSTF_Msk = 0x2000000
	// Bit OBLRSTF.
	RCC_CSR_OBLRSTF = 0x2000000
	// No reset has occured
	RCC_CSR_OBLRSTF_NoReset = 0x0
	// A reset has occured
	RCC_CSR_OBLRSTF_Reset = 0x1
	// Position of LPWRSTF field.
	RCC_CSR_LPWRSTF_Pos = 0x1f
	// Bit mask of LPWRSTF field.
	RCC_CSR_LPWRSTF_Msk = 0x80000000
	// Bit LPWRSTF.
	RCC_CSR_LPWRSTF = 0x80000000
	// No reset has occured
	RCC_CSR_LPWRSTF_NoReset = 0x0
	// A reset has occured
	RCC_CSR_LPWRSTF_Reset = 0x1
	// Position of WWDGRSTF field.
	RCC_CSR_WWDGRSTF_Pos = 0x1e
	// Bit mask of WWDGRSTF field.
	RCC_CSR_WWDGRSTF_Msk = 0x40000000
	// Bit WWDGRSTF.
	RCC_CSR_WWDGRSTF = 0x40000000
	// No reset has occured
	RCC_CSR_WWDGRSTF_NoReset = 0x0
	// A reset has occured
	RCC_CSR_WWDGRSTF_Reset = 0x1
	// Position of IWWDGRSTF field.
	RCC_CSR_IWWDGRSTF_Pos = 0x1d
	// Bit mask of IWWDGRSTF field.
	RCC_CSR_IWWDGRSTF_Msk = 0x20000000
	// Bit IWWDGRSTF.
	RCC_CSR_IWWDGRSTF = 0x20000000
	// No reset has occured
	RCC_CSR_IWWDGRSTF_NoReset = 0x0
	// A reset has occured
	RCC_CSR_IWWDGRSTF_Reset = 0x1
	// Position of SFTRSTF field.
	RCC_CSR_SFTRSTF_Pos = 0x1c
	// Bit mask of SFTRSTF field.
	RCC_CSR_SFTRSTF_Msk = 0x10000000
	// Bit SFTRSTF.
	RCC_CSR_SFTRSTF = 0x10000000
	// No reset has occured
	RCC_CSR_SFTRSTF_NoReset = 0x0
	// A reset has occured
	RCC_CSR_SFTRSTF_Reset = 0x1
	// Position of BORRSTF field.
	RCC_CSR_BORRSTF_Pos = 0x1b
	// Bit mask of BORRSTF field.
	RCC_CSR_BORRSTF_Msk = 0x8000000
	// Bit BORRSTF.
	RCC_CSR_BORRSTF = 0x8000000
	// No reset has occured
	RCC_CSR_BORRSTF_NoReset = 0x0
	// A reset has occured
	RCC_CSR_BORRSTF_Reset = 0x1
	// Position of PINRSTF field.
	RCC_CSR_PINRSTF_Pos = 0x1a
	// Bit mask of PINRSTF field.
	RCC_CSR_PINRSTF_Msk = 0x4000000
	// Bit PINRSTF.
	RCC_CSR_PINRSTF = 0x4000000
	// No reset has occured
	RCC_CSR_PINRSTF_NoReset = 0x0
	// A reset has occured
	RCC_CSR_PINRSTF_Reset = 0x1
	// Position of RMVF field.
	RCC_CSR_RMVF_Pos = 0x17
	// Bit mask of RMVF field.
	RCC_CSR_RMVF_Msk = 0x800000
	// Bit RMVF.
	RCC_CSR_RMVF = 0x800000
	// Clears the reset flag
	RCC_CSR_RMVF_Clear = 0x1
	// Position of MSISRANGE field.
	RCC_CSR_MSISRANGE_Pos = 0x8
	// Bit mask of MSISRANGE field.
	RCC_CSR_MSISRANGE_Msk = 0xf00
	// Position of LSIPREDIV field.
	RCC_CSR_LSIPREDIV_Pos = 0x4
	// Bit mask of LSIPREDIV field.
	RCC_CSR_LSIPREDIV_Msk = 0x10
	// Bit LSIPREDIV.
	RCC_CSR_LSIPREDIV = 0x10
	// Position of LSIRDY field.
	RCC_CSR_LSIRDY_Pos = 0x1
	// Bit mask of LSIRDY field.
	RCC_CSR_LSIRDY_Msk = 0x2
	// Bit LSIRDY.
	RCC_CSR_LSIRDY = 0x2
	// LSI oscillator not ready
	RCC_CSR_LSIRDY_NotReady = 0x0
	// LSI oscillator ready
	RCC_CSR_LSIRDY_Ready = 0x1
	// Position of LSION field.
	RCC_CSR_LSION_Pos = 0x0
	// Bit mask of LSION field.
	RCC_CSR_LSION_Msk = 0x1
	// Bit LSION.
	RCC_CSR_LSION = 0x1
	// LSI oscillator Off
	RCC_CSR_LSION_Off = 0x0
	// LSI oscillator On
	RCC_CSR_LSION_On = 0x1

	// CRRCR: Clock recovery RC register
	// Position of HSI48ON field.
	RCC_CRRCR_HSI48ON_Pos = 0x0
	// Bit mask of HSI48ON field.
	RCC_CRRCR_HSI48ON_Msk = 0x1
	// Bit HSI48ON.
	RCC_CRRCR_HSI48ON = 0x1
	// Position of HSI48RDY field.
	RCC_CRRCR_HSI48RDY_Pos = 0x1
	// Bit mask of HSI48RDY field.
	RCC_CRRCR_HSI48RDY_Msk = 0x2
	// Bit HSI48RDY.
	RCC_CRRCR_HSI48RDY = 0x2
	// Position of HSI48CAL field.
	RCC_CRRCR_HSI48CAL_Pos = 0x7
	// Bit mask of HSI48CAL field.
	RCC_CRRCR_HSI48CAL_Msk = 0xff80

	// CCIPR2: Peripherals independent clock configuration register
	// Position of I2C4SEL field.
	RCC_CCIPR2_I2C4SEL_Pos = 0x0
	// Bit mask of I2C4SEL field.
	RCC_CCIPR2_I2C4SEL_Msk = 0x3
	// Position of DFSDMSEL field.
	RCC_CCIPR2_DFSDMSEL_Pos = 0x2
	// Bit mask of DFSDMSEL field.
	RCC_CCIPR2_DFSDMSEL_Msk = 0x4
	// Bit DFSDMSEL.
	RCC_CCIPR2_DFSDMSEL = 0x4
	// Position of ADFSDMSEL field.
	RCC_CCIPR2_ADFSDMSEL_Pos = 0x3
	// Bit mask of ADFSDMSEL field.
	RCC_CCIPR2_ADFSDMSEL_Msk = 0x18
	// Position of SAI1SEL field.
	RCC_CCIPR2_SAI1SEL_Pos = 0x5
	// Bit mask of SAI1SEL field.
	RCC_CCIPR2_SAI1SEL_Msk = 0xe0
	// Position of SAI2SEL field.
	RCC_CCIPR2_SAI2SEL_Pos = 0x8
	// Bit mask of SAI2SEL field.
	RCC_CCIPR2_SAI2SEL_Msk = 0x700
	// Position of SDMMCSEL field.
	RCC_CCIPR2_SDMMCSEL_Pos = 0xe
	// Bit mask of SDMMCSEL field.
	RCC_CCIPR2_SDMMCSEL_Msk = 0x4000
	// Bit SDMMCSEL.
	RCC_CCIPR2_SDMMCSEL = 0x4000
	// Position of OSPISEL field.
	RCC_CCIPR2_OSPISEL_Pos = 0x14
	// Bit mask of OSPISEL field.
	RCC_CCIPR2_OSPISEL_Msk = 0x300000

	// SECCFGR: RCC secure configuration register
	// Position of HSISEC field.
	RCC_SECCFGR_HSISEC_Pos = 0x0
	// Bit mask of HSISEC field.
	RCC_SECCFGR_HSISEC_Msk = 0x1
	// Bit HSISEC.
	RCC_SECCFGR_HSISEC = 0x1
	// Position of HSESEC field.
	RCC_SECCFGR_HSESEC_Pos = 0x1
	// Bit mask of HSESEC field.
	RCC_SECCFGR_HSESEC_Msk = 0x2
	// Bit HSESEC.
	RCC_SECCFGR_HSESEC = 0x2
	// Position of MSISEC field.
	RCC_SECCFGR_MSISEC_Pos = 0x2
	// Bit mask of MSISEC field.
	RCC_SECCFGR_MSISEC_Msk = 0x4
	// Bit MSISEC.
	RCC_SECCFGR_MSISEC = 0x4
	// Position of LSISEC field.
	RCC_SECCFGR_LSISEC_Pos = 0x3
	// Bit mask of LSISEC field.
	RCC_SECCFGR_LSISEC_Msk = 0x8
	// Bit LSISEC.
	RCC_SECCFGR_LSISEC = 0x8
	// Position of LSESEC field.
	RCC_SECCFGR_LSESEC_Pos = 0x4
	// Bit mask of LSESEC field.
	RCC_SECCFGR_LSESEC_Msk = 0x10
	// Bit LSESEC.
	RCC_SECCFGR_LSESEC = 0x10
	// Position of SYSCLKSEC field.
	RCC_SECCFGR_SYSCLKSEC_Pos = 0x5
	// Bit mask of SYSCLKSEC field.
	RCC_SECCFGR_SYSCLKSEC_Msk = 0x20
	// Bit SYSCLKSEC.
	RCC_SECCFGR_SYSCLKSEC = 0x20
	// Position of PRESCSEC field.
	RCC_SECCFGR_PRESCSEC_Pos = 0x6
	// Bit mask of PRESCSEC field.
	RCC_SECCFGR_PRESCSEC_Msk = 0x40
	// Bit PRESCSEC.
	RCC_SECCFGR_PRESCSEC = 0x40
	// Position of PLLSEC field.
	RCC_SECCFGR_PLLSEC_Pos = 0x7
	// Bit mask of PLLSEC field.
	RCC_SECCFGR_PLLSEC_Msk = 0x80
	// Bit PLLSEC.
	RCC_SECCFGR_PLLSEC = 0x80
	// Position of PLLSAI1SEC field.
	RCC_SECCFGR_PLLSAI1SEC_Pos = 0x8
	// Bit mask of PLLSAI1SEC field.
	RCC_SECCFGR_PLLSAI1SEC_Msk = 0x100
	// Bit PLLSAI1SEC.
	RCC_SECCFGR_PLLSAI1SEC = 0x100
	// Position of PLLSAI2SEC field.
	RCC_SECCFGR_PLLSAI2SEC_Pos = 0x9
	// Bit mask of PLLSAI2SEC field.
	RCC_SECCFGR_PLLSAI2SEC_Msk = 0x200
	// Bit PLLSAI2SEC.
	RCC_SECCFGR_PLLSAI2SEC = 0x200
	// Position of CLK48MSEC field.
	RCC_SECCFGR_CLK48MSEC_Pos = 0xa
	// Bit mask of CLK48MSEC field.
	RCC_SECCFGR_CLK48MSEC_Msk = 0x400
	// Bit CLK48MSEC.
	RCC_SECCFGR_CLK48MSEC = 0x400
	// Position of HSI48SEC field.
	RCC_SECCFGR_HSI48SEC_Pos = 0xb
	// Bit mask of HSI48SEC field.
	RCC_SECCFGR_HSI48SEC_Msk = 0x800
	// Bit HSI48SEC.
	RCC_SECCFGR_HSI48SEC = 0x800
	// Position of RMVFSEC field.
	RCC_SECCFGR_RMVFSEC_Pos = 0xc
	// Bit mask of RMVFSEC field.
	RCC_SECCFGR_RMVFSEC_Msk = 0x1000
	// Bit RMVFSEC.
	RCC_SECCFGR_RMVFSEC = 0x1000

	// SECSR: RCC secure status register
	// Position of RMVFSECF field.
	RCC_SECSR_RMVFSECF_Pos = 0xc
	// Bit mask of RMVFSECF field.
	RCC_SECSR_RMVFSECF_Msk = 0x1000
	// Bit RMVFSECF.
	RCC_SECSR_RMVFSECF = 0x1000
	// Position of HSI48SECF field.
	RCC_SECSR_HSI48SECF_Pos = 0xb
	// Bit mask of HSI48SECF field.
	RCC_SECSR_HSI48SECF_Msk = 0x800
	// Bit HSI48SECF.
	RCC_SECSR_HSI48SECF = 0x800
	// Position of CLK48MSECF field.
	RCC_SECSR_CLK48MSECF_Pos = 0xa
	// Bit mask of CLK48MSECF field.
	RCC_SECSR_CLK48MSECF_Msk = 0x400
	// Bit CLK48MSECF.
	RCC_SECSR_CLK48MSECF = 0x400
	// Position of PLLSAI2SECF field.
	RCC_SECSR_PLLSAI2SECF_Pos = 0x9
	// Bit mask of PLLSAI2SECF field.
	RCC_SECSR_PLLSAI2SECF_Msk = 0x200
	// Bit PLLSAI2SECF.
	RCC_SECSR_PLLSAI2SECF = 0x200
	// Position of PLLSAI1SECF field.
	RCC_SECSR_PLLSAI1SECF_Pos = 0x8
	// Bit mask of PLLSAI1SECF field.
	RCC_SECSR_PLLSAI1SECF_Msk = 0x100
	// Bit PLLSAI1SECF.
	RCC_SECSR_PLLSAI1SECF = 0x100
	// Position of PLLSECF field.
	RCC_SECSR_PLLSECF_Pos = 0x7
	// Bit mask of PLLSECF field.
	RCC_SECSR_PLLSECF_Msk = 0x80
	// Bit PLLSECF.
	RCC_SECSR_PLLSECF = 0x80
	// Position of PRESCSECF field.
	RCC_SECSR_PRESCSECF_Pos = 0x6
	// Bit mask of PRESCSECF field.
	RCC_SECSR_PRESCSECF_Msk = 0x40
	// Bit PRESCSECF.
	RCC_SECSR_PRESCSECF = 0x40
	// Position of SYSCLKSECF field.
	RCC_SECSR_SYSCLKSECF_Pos = 0x5
	// Bit mask of SYSCLKSECF field.
	RCC_SECSR_SYSCLKSECF_Msk = 0x20
	// Bit SYSCLKSECF.
	RCC_SECSR_SYSCLKSECF = 0x20
	// Position of LSESECF field.
	RCC_SECSR_LSESECF_Pos = 0x4
	// Bit mask of LSESECF field.
	RCC_SECSR_LSESECF_Msk = 0x10
	// Bit LSESECF.
	RCC_SECSR_LSESECF = 0x10
	// Position of LSISECF field.
	RCC_SECSR_LSISECF_Pos = 0x3
	// Bit mask of LSISECF field.
	RCC_SECSR_LSISECF_Msk = 0x8
	// Bit LSISECF.
	RCC_SECSR_LSISECF = 0x8
	// Position of MSISECF field.
	RCC_SECSR_MSISECF_Pos = 0x2
	// Bit mask of MSISECF field.
	RCC_SECSR_MSISECF_Msk = 0x4
	// Bit MSISECF.
	RCC_SECSR_MSISECF = 0x4
	// Position of HSESECF field.
	RCC_SECSR_HSESECF_Pos = 0x1
	// Bit mask of HSESECF field.
	RCC_SECSR_HSESECF_Msk = 0x2
	// Bit HSESECF.
	RCC_SECSR_HSESECF = 0x2
	// Position of HSISECF field.
	RCC_SECSR_HSISECF_Pos = 0x0
	// Bit mask of HSISECF field.
	RCC_SECSR_HSISECF_Msk = 0x1
	// Bit HSISECF.
	RCC_SECSR_HSISECF = 0x1

	// AHB1SECSR: RCC AHB1 security status register
	// Position of ICACHESECF field.
	RCC_AHB1SECSR_ICACHESECF_Pos = 0x17
	// Bit mask of ICACHESECF field.
	RCC_AHB1SECSR_ICACHESECF_Msk = 0x800000
	// Bit ICACHESECF.
	RCC_AHB1SECSR_ICACHESECF = 0x800000
	// Position of GTZCSECF field.
	RCC_AHB1SECSR_GTZCSECF_Pos = 0x16
	// Bit mask of GTZCSECF field.
	RCC_AHB1SECSR_GTZCSECF_Msk = 0x400000
	// Bit GTZCSECF.
	RCC_AHB1SECSR_GTZCSECF = 0x400000
	// Position of TSCSECF field.
	RCC_AHB1SECSR_TSCSECF_Pos = 0x10
	// Bit mask of TSCSECF field.
	RCC_AHB1SECSR_TSCSECF_Msk = 0x10000
	// Bit TSCSECF.
	RCC_AHB1SECSR_TSCSECF = 0x10000
	// Position of CRCSECF field.
	RCC_AHB1SECSR_CRCSECF_Pos = 0xc
	// Bit mask of CRCSECF field.
	RCC_AHB1SECSR_CRCSECF_Msk = 0x1000
	// Bit CRCSECF.
	RCC_AHB1SECSR_CRCSECF = 0x1000
	// Position of SRAM1SECF field.
	RCC_AHB1SECSR_SRAM1SECF_Pos = 0x9
	// Bit mask of SRAM1SECF field.
	RCC_AHB1SECSR_SRAM1SECF_Msk = 0x200
	// Bit SRAM1SECF.
	RCC_AHB1SECSR_SRAM1SECF = 0x200
	// Position of FLASHSECF field.
	RCC_AHB1SECSR_FLASHSECF_Pos = 0x8
	// Bit mask of FLASHSECF field.
	RCC_AHB1SECSR_FLASHSECF_Msk = 0x100
	// Bit FLASHSECF.
	RCC_AHB1SECSR_FLASHSECF = 0x100
	// Position of DMAMUX1SECF field.
	RCC_AHB1SECSR_DMAMUX1SECF_Pos = 0x2
	// Bit mask of DMAMUX1SECF field.
	RCC_AHB1SECSR_DMAMUX1SECF_Msk = 0x4
	// Bit DMAMUX1SECF.
	RCC_AHB1SECSR_DMAMUX1SECF = 0x4
	// Position of DMA2SECF field.
	RCC_AHB1SECSR_DMA2SECF_Pos = 0x1
	// Bit mask of DMA2SECF field.
	RCC_AHB1SECSR_DMA2SECF_Msk = 0x2
	// Bit DMA2SECF.
	RCC_AHB1SECSR_DMA2SECF = 0x2
	// Position of DMA1SECF field.
	RCC_AHB1SECSR_DMA1SECF_Pos = 0x0
	// Bit mask of DMA1SECF field.
	RCC_AHB1SECSR_DMA1SECF_Msk = 0x1
	// Bit DMA1SECF.
	RCC_AHB1SECSR_DMA1SECF = 0x1

	// AHB2SECSR: RCC AHB2 security status register
	// Position of SDMMC1SECF field.
	RCC_AHB2SECSR_SDMMC1SECF_Pos = 0x16
	// Bit mask of SDMMC1SECF field.
	RCC_AHB2SECSR_SDMMC1SECF_Msk = 0x400000
	// Bit SDMMC1SECF.
	RCC_AHB2SECSR_SDMMC1SECF = 0x400000
	// Position of OTFDEC1SECF field.
	RCC_AHB2SECSR_OTFDEC1SECF_Pos = 0x15
	// Bit mask of OTFDEC1SECF field.
	RCC_AHB2SECSR_OTFDEC1SECF_Msk = 0x200000
	// Bit OTFDEC1SECF.
	RCC_AHB2SECSR_OTFDEC1SECF = 0x200000
	// Position of SRAM2SECF field.
	RCC_AHB2SECSR_SRAM2SECF_Pos = 0x9
	// Bit mask of SRAM2SECF field.
	RCC_AHB2SECSR_SRAM2SECF_Msk = 0x200
	// Bit SRAM2SECF.
	RCC_AHB2SECSR_SRAM2SECF = 0x200
	// Position of GPIOHSECF field.
	RCC_AHB2SECSR_GPIOHSECF_Pos = 0x7
	// Bit mask of GPIOHSECF field.
	RCC_AHB2SECSR_GPIOHSECF_Msk = 0x80
	// Bit GPIOHSECF.
	RCC_AHB2SECSR_GPIOHSECF = 0x80
	// Position of GPIOGSECF field.
	RCC_AHB2SECSR_GPIOGSECF_Pos = 0x6
	// Bit mask of GPIOGSECF field.
	RCC_AHB2SECSR_GPIOGSECF_Msk = 0x40
	// Bit GPIOGSECF.
	RCC_AHB2SECSR_GPIOGSECF = 0x40
	// Position of GPIOFSECF field.
	RCC_AHB2SECSR_GPIOFSECF_Pos = 0x5
	// Bit mask of GPIOFSECF field.
	RCC_AHB2SECSR_GPIOFSECF_Msk = 0x20
	// Bit GPIOFSECF.
	RCC_AHB2SECSR_GPIOFSECF = 0x20
	// Position of GPIOESECF field.
	RCC_AHB2SECSR_GPIOESECF_Pos = 0x4
	// Bit mask of GPIOESECF field.
	RCC_AHB2SECSR_GPIOESECF_Msk = 0x10
	// Bit GPIOESECF.
	RCC_AHB2SECSR_GPIOESECF = 0x10
	// Position of GPIODSECF field.
	RCC_AHB2SECSR_GPIODSECF_Pos = 0x3
	// Bit mask of GPIODSECF field.
	RCC_AHB2SECSR_GPIODSECF_Msk = 0x8
	// Bit GPIODSECF.
	RCC_AHB2SECSR_GPIODSECF = 0x8
	// Position of GPIOCSECF field.
	RCC_AHB2SECSR_GPIOCSECF_Pos = 0x2
	// Bit mask of GPIOCSECF field.
	RCC_AHB2SECSR_GPIOCSECF_Msk = 0x4
	// Bit GPIOCSECF.
	RCC_AHB2SECSR_GPIOCSECF = 0x4
	// Position of GPIOBSECF field.
	RCC_AHB2SECSR_GPIOBSECF_Pos = 0x1
	// Bit mask of GPIOBSECF field.
	RCC_AHB2SECSR_GPIOBSECF_Msk = 0x2
	// Bit GPIOBSECF.
	RCC_AHB2SECSR_GPIOBSECF = 0x2
	// Position of GPIOASECF field.
	RCC_AHB2SECSR_GPIOASECF_Pos = 0x0
	// Bit mask of GPIOASECF field.
	RCC_AHB2SECSR_GPIOASECF_Msk = 0x1
	// Bit GPIOASECF.
	RCC_AHB2SECSR_GPIOASECF = 0x1

	// AHB3SECSR: RCC AHB3 security status register
	// Position of OSPI1SECF field.
	RCC_AHB3SECSR_OSPI1SECF_Pos = 0x8
	// Bit mask of OSPI1SECF field.
	RCC_AHB3SECSR_OSPI1SECF_Msk = 0x100
	// Bit OSPI1SECF.
	RCC_AHB3SECSR_OSPI1SECF = 0x100
	// Position of FSMCSECF field.
	RCC_AHB3SECSR_FSMCSECF_Pos = 0x0
	// Bit mask of FSMCSECF field.
	RCC_AHB3SECSR_FSMCSECF_Msk = 0x1
	// Bit FSMCSECF.
	RCC_AHB3SECSR_FSMCSECF = 0x1

	// APB1SECSR1: RCC APB1 security status register 1
	// Position of LPTIM1SECF field.
	RCC_APB1SECSR1_LPTIM1SECF_Pos = 0x1f
	// Bit mask of LPTIM1SECF field.
	RCC_APB1SECSR1_LPTIM1SECF_Msk = 0x80000000
	// Bit LPTIM1SECF.
	RCC_APB1SECSR1_LPTIM1SECF = 0x80000000
	// Position of OPAMPSECF field.
	RCC_APB1SECSR1_OPAMPSECF_Pos = 0x1e
	// Bit mask of OPAMPSECF field.
	RCC_APB1SECSR1_OPAMPSECF_Msk = 0x40000000
	// Bit OPAMPSECF.
	RCC_APB1SECSR1_OPAMPSECF = 0x40000000
	// Position of DACSECF field.
	RCC_APB1SECSR1_DACSECF_Pos = 0x1d
	// Bit mask of DACSECF field.
	RCC_APB1SECSR1_DACSECF_Msk = 0x20000000
	// Bit DACSECF.
	RCC_APB1SECSR1_DACSECF = 0x20000000
	// Position of PWRSECF field.
	RCC_APB1SECSR1_PWRSECF_Pos = 0x1c
	// Bit mask of PWRSECF field.
	RCC_APB1SECSR1_PWRSECF_Msk = 0x10000000
	// Bit PWRSECF.
	RCC_APB1SECSR1_PWRSECF = 0x10000000
	// Position of CRSSECF field.
	RCC_APB1SECSR1_CRSSECF_Pos = 0x18
	// Bit mask of CRSSECF field.
	RCC_APB1SECSR1_CRSSECF_Msk = 0x1000000
	// Bit CRSSECF.
	RCC_APB1SECSR1_CRSSECF = 0x1000000
	// Position of I2C3SECF field.
	RCC_APB1SECSR1_I2C3SECF_Pos = 0x17
	// Bit mask of I2C3SECF field.
	RCC_APB1SECSR1_I2C3SECF_Msk = 0x800000
	// Bit I2C3SECF.
	RCC_APB1SECSR1_I2C3SECF = 0x800000
	// Position of I2C2SECF field.
	RCC_APB1SECSR1_I2C2SECF_Pos = 0x16
	// Bit mask of I2C2SECF field.
	RCC_APB1SECSR1_I2C2SECF_Msk = 0x400000
	// Bit I2C2SECF.
	RCC_APB1SECSR1_I2C2SECF = 0x400000
	// Position of I2C1SECF field.
	RCC_APB1SECSR1_I2C1SECF_Pos = 0x15
	// Bit mask of I2C1SECF field.
	RCC_APB1SECSR1_I2C1SECF_Msk = 0x200000
	// Bit I2C1SECF.
	RCC_APB1SECSR1_I2C1SECF = 0x200000
	// Position of UART5SECF field.
	RCC_APB1SECSR1_UART5SECF_Pos = 0x14
	// Bit mask of UART5SECF field.
	RCC_APB1SECSR1_UART5SECF_Msk = 0x100000
	// Bit UART5SECF.
	RCC_APB1SECSR1_UART5SECF = 0x100000
	// Position of UART4SECF field.
	RCC_APB1SECSR1_UART4SECF_Pos = 0x13
	// Bit mask of UART4SECF field.
	RCC_APB1SECSR1_UART4SECF_Msk = 0x80000
	// Bit UART4SECF.
	RCC_APB1SECSR1_UART4SECF = 0x80000
	// Position of UART3SECF field.
	RCC_APB1SECSR1_UART3SECF_Pos = 0x12
	// Bit mask of UART3SECF field.
	RCC_APB1SECSR1_UART3SECF_Msk = 0x40000
	// Bit UART3SECF.
	RCC_APB1SECSR1_UART3SECF = 0x40000
	// Position of UART2SECF field.
	RCC_APB1SECSR1_UART2SECF_Pos = 0x11
	// Bit mask of UART2SECF field.
	RCC_APB1SECSR1_UART2SECF_Msk = 0x20000
	// Bit UART2SECF.
	RCC_APB1SECSR1_UART2SECF = 0x20000
	// Position of SPI3SECF field.
	RCC_APB1SECSR1_SPI3SECF_Pos = 0xf
	// Bit mask of SPI3SECF field.
	RCC_APB1SECSR1_SPI3SECF_Msk = 0x8000
	// Bit SPI3SECF.
	RCC_APB1SECSR1_SPI3SECF = 0x8000
	// Position of SPI2SECF field.
	RCC_APB1SECSR1_SPI2SECF_Pos = 0xe
	// Bit mask of SPI2SECF field.
	RCC_APB1SECSR1_SPI2SECF_Msk = 0x4000
	// Bit SPI2SECF.
	RCC_APB1SECSR1_SPI2SECF = 0x4000
	// Position of WWDGSECF field.
	RCC_APB1SECSR1_WWDGSECF_Pos = 0xb
	// Bit mask of WWDGSECF field.
	RCC_APB1SECSR1_WWDGSECF_Msk = 0x800
	// Bit WWDGSECF.
	RCC_APB1SECSR1_WWDGSECF = 0x800
	// Position of RTCAPBSECF field.
	RCC_APB1SECSR1_RTCAPBSECF_Pos = 0xa
	// Bit mask of RTCAPBSECF field.
	RCC_APB1SECSR1_RTCAPBSECF_Msk = 0x400
	// Bit RTCAPBSECF.
	RCC_APB1SECSR1_RTCAPBSECF = 0x400
	// Position of TIM7SECF field.
	RCC_APB1SECSR1_TIM7SECF_Pos = 0x5
	// Bit mask of TIM7SECF field.
	RCC_APB1SECSR1_TIM7SECF_Msk = 0x20
	// Bit TIM7SECF.
	RCC_APB1SECSR1_TIM7SECF = 0x20
	// Position of TIM6SECF field.
	RCC_APB1SECSR1_TIM6SECF_Pos = 0x4
	// Bit mask of TIM6SECF field.
	RCC_APB1SECSR1_TIM6SECF_Msk = 0x10
	// Bit TIM6SECF.
	RCC_APB1SECSR1_TIM6SECF = 0x10
	// Position of TIM5SECF field.
	RCC_APB1SECSR1_TIM5SECF_Pos = 0x3
	// Bit mask of TIM5SECF field.
	RCC_APB1SECSR1_TIM5SECF_Msk = 0x8
	// Bit TIM5SECF.
	RCC_APB1SECSR1_TIM5SECF = 0x8
	// Position of TIM4SECF field.
	RCC_APB1SECSR1_TIM4SECF_Pos = 0x2
	// Bit mask of TIM4SECF field.
	RCC_APB1SECSR1_TIM4SECF_Msk = 0x4
	// Bit TIM4SECF.
	RCC_APB1SECSR1_TIM4SECF = 0x4
	// Position of TIM3SECF field.
	RCC_APB1SECSR1_TIM3SECF_Pos = 0x1
	// Bit mask of TIM3SECF field.
	RCC_APB1SECSR1_TIM3SECF_Msk = 0x2
	// Bit TIM3SECF.
	RCC_APB1SECSR1_TIM3SECF = 0x2
	// Position of TIM2SECF field.
	RCC_APB1SECSR1_TIM2SECF_Pos = 0x0
	// Bit mask of TIM2SECF field.
	RCC_APB1SECSR1_TIM2SECF_Msk = 0x1
	// Bit TIM2SECF.
	RCC_APB1SECSR1_TIM2SECF = 0x1

	// APB1SECSR2: RCC APB1 security status register 2
	// Position of UCPD1SECF field.
	RCC_APB1SECSR2_UCPD1SECF_Pos = 0x17
	// Bit mask of UCPD1SECF field.
	RCC_APB1SECSR2_UCPD1SECF_Msk = 0x800000
	// Bit UCPD1SECF.
	RCC_APB1SECSR2_UCPD1SECF = 0x800000
	// Position of USBFSSECF field.
	RCC_APB1SECSR2_USBFSSECF_Pos = 0x15
	// Bit mask of USBFSSECF field.
	RCC_APB1SECSR2_USBFSSECF_Msk = 0x200000
	// Bit USBFSSECF.
	RCC_APB1SECSR2_USBFSSECF = 0x200000
	// Position of FDCAN1SECF field.
	RCC_APB1SECSR2_FDCAN1SECF_Pos = 0x9
	// Bit mask of FDCAN1SECF field.
	RCC_APB1SECSR2_FDCAN1SECF_Msk = 0x200
	// Bit FDCAN1SECF.
	RCC_APB1SECSR2_FDCAN1SECF = 0x200
	// Position of LPTIM3SECF field.
	RCC_APB1SECSR2_LPTIM3SECF_Pos = 0x6
	// Bit mask of LPTIM3SECF field.
	RCC_APB1SECSR2_LPTIM3SECF_Msk = 0x40
	// Bit LPTIM3SECF.
	RCC_APB1SECSR2_LPTIM3SECF = 0x40
	// Position of LPTIM2SECF field.
	RCC_APB1SECSR2_LPTIM2SECF_Pos = 0x5
	// Bit mask of LPTIM2SECF field.
	RCC_APB1SECSR2_LPTIM2SECF_Msk = 0x20
	// Bit LPTIM2SECF.
	RCC_APB1SECSR2_LPTIM2SECF = 0x20
	// Position of I2C4SECF field.
	RCC_APB1SECSR2_I2C4SECF_Pos = 0x1
	// Bit mask of I2C4SECF field.
	RCC_APB1SECSR2_I2C4SECF_Msk = 0x2
	// Bit I2C4SECF.
	RCC_APB1SECSR2_I2C4SECF = 0x2
	// Position of LPUART1SECF field.
	RCC_APB1SECSR2_LPUART1SECF_Pos = 0x0
	// Bit mask of LPUART1SECF field.
	RCC_APB1SECSR2_LPUART1SECF_Msk = 0x1
	// Bit LPUART1SECF.
	RCC_APB1SECSR2_LPUART1SECF = 0x1

	// APB2SECSR: RCC APB2 security status register
	// Position of DFSDM1SECF field.
	RCC_APB2SECSR_DFSDM1SECF_Pos = 0x18
	// Bit mask of DFSDM1SECF field.
	RCC_APB2SECSR_DFSDM1SECF_Msk = 0x1000000
	// Bit DFSDM1SECF.
	RCC_APB2SECSR_DFSDM1SECF = 0x1000000
	// Position of SAI2SECF field.
	RCC_APB2SECSR_SAI2SECF_Pos = 0x16
	// Bit mask of SAI2SECF field.
	RCC_APB2SECSR_SAI2SECF_Msk = 0x400000
	// Bit SAI2SECF.
	RCC_APB2SECSR_SAI2SECF = 0x400000
	// Position of SAI1SECF field.
	RCC_APB2SECSR_SAI1SECF_Pos = 0x15
	// Bit mask of SAI1SECF field.
	RCC_APB2SECSR_SAI1SECF_Msk = 0x200000
	// Bit SAI1SECF.
	RCC_APB2SECSR_SAI1SECF = 0x200000
	// Position of TIM17SECF field.
	RCC_APB2SECSR_TIM17SECF_Pos = 0x12
	// Bit mask of TIM17SECF field.
	RCC_APB2SECSR_TIM17SECF_Msk = 0x40000
	// Bit TIM17SECF.
	RCC_APB2SECSR_TIM17SECF = 0x40000
	// Position of TIM16SECF field.
	RCC_APB2SECSR_TIM16SECF_Pos = 0x11
	// Bit mask of TIM16SECF field.
	RCC_APB2SECSR_TIM16SECF_Msk = 0x20000
	// Bit TIM16SECF.
	RCC_APB2SECSR_TIM16SECF = 0x20000
	// Position of TIM15SECF field.
	RCC_APB2SECSR_TIM15SECF_Pos = 0x10
	// Bit mask of TIM15SECF field.
	RCC_APB2SECSR_TIM15SECF_Msk = 0x10000
	// Bit TIM15SECF.
	RCC_APB2SECSR_TIM15SECF = 0x10000
	// Position of USART1SECF field.
	RCC_APB2SECSR_USART1SECF_Pos = 0xe
	// Bit mask of USART1SECF field.
	RCC_APB2SECSR_USART1SECF_Msk = 0x4000
	// Bit USART1SECF.
	RCC_APB2SECSR_USART1SECF = 0x4000
	// Position of TIM8SECF field.
	RCC_APB2SECSR_TIM8SECF_Pos = 0xd
	// Bit mask of TIM8SECF field.
	RCC_APB2SECSR_TIM8SECF_Msk = 0x2000
	// Bit TIM8SECF.
	RCC_APB2SECSR_TIM8SECF = 0x2000
	// Position of SPI1SECF field.
	RCC_APB2SECSR_SPI1SECF_Pos = 0xc
	// Bit mask of SPI1SECF field.
	RCC_APB2SECSR_SPI1SECF_Msk = 0x1000
	// Bit SPI1SECF.
	RCC_APB2SECSR_SPI1SECF = 0x1000
	// Position of TIM1SECF field.
	RCC_APB2SECSR_TIM1SECF_Pos = 0xb
	// Bit mask of TIM1SECF field.
	RCC_APB2SECSR_TIM1SECF_Msk = 0x800
	// Bit TIM1SECF.
	RCC_APB2SECSR_TIM1SECF = 0x800
	// Position of SYSCFGSECF field.
	RCC_APB2SECSR_SYSCFGSECF_Pos = 0x0
	// Bit mask of SYSCFGSECF field.
	RCC_APB2SECSR_SYSCFGSECF_Msk = 0x1
	// Bit SYSCFGSECF.
	RCC_APB2SECSR_SYSCFGSECF = 0x1
)

// Constants for RNG: RNG
const (
	// CR: RNG control register
	// Position of RNGEN field.
	RNG_CR_RNGEN_Pos = 0x2
	// Bit mask of RNGEN field.
	RNG_CR_RNGEN_Msk = 0x4
	// Bit RNGEN.
	RNG_CR_RNGEN = 0x4
	// Random number generator is disabled
	RNG_CR_RNGEN_Disabled = 0x0
	// Random number generator is enabled
	RNG_CR_RNGEN_Enabled = 0x1
	// Position of IE field.
	RNG_CR_IE_Pos = 0x3
	// Bit mask of IE field.
	RNG_CR_IE_Msk = 0x8
	// Bit IE.
	RNG_CR_IE = 0x8
	// RNG interrupt is disabled
	RNG_CR_IE_Disabled = 0x0
	// RNG interrupt is enabled
	RNG_CR_IE_Enabled = 0x1
	// Position of CED field.
	RNG_CR_CED_Pos = 0x5
	// Bit mask of CED field.
	RNG_CR_CED_Msk = 0x20
	// Bit CED.
	RNG_CR_CED = 0x20
	// Clock error detection is enabled
	RNG_CR_CED_Enabled = 0x0
	// Clock error detection is disabled
	RNG_CR_CED_Disabled = 0x1
	// Position of RNG_CONFIG3 field.
	RNG_CR_RNG_CONFIG3_Pos = 0x8
	// Bit mask of RNG_CONFIG3 field.
	RNG_CR_RNG_CONFIG3_Msk = 0xf00
	// Recommended value for config B (not NIST certifiable)
	RNG_CR_RNG_CONFIG3_ConfigB = 0x0
	// Recommended value for config A (NIST certifiable)
	RNG_CR_RNG_CONFIG3_ConfigA = 0xd
	// Position of NISTC field.
	RNG_CR_NISTC_Pos = 0xc
	// Bit mask of NISTC field.
	RNG_CR_NISTC_Msk = 0x1000
	// Bit NISTC.
	RNG_CR_NISTC = 0x1000
	// Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used
	RNG_CR_NISTC_Default = 0x0
	// Custom values for NIST compliant RNG
	RNG_CR_NISTC_Custom = 0x1
	// Position of RNG_CONFIG2 field.
	RNG_CR_RNG_CONFIG2_Pos = 0xd
	// Bit mask of RNG_CONFIG2 field.
	RNG_CR_RNG_CONFIG2_Msk = 0xe000
	// Recommended value for config A and B
	RNG_CR_RNG_CONFIG2_ConfigA_B = 0x0
	// Position of CLKDIV field.
	RNG_CR_CLKDIV_Pos = 0x10
	// Bit mask of CLKDIV field.
	RNG_CR_CLKDIV_Msk = 0xf0000
	// Internal RNG clock after divider is similar to incoming RNG clock
	RNG_CR_CLKDIV_Div1 = 0x0
	// Divide RNG clock by 2^1
	RNG_CR_CLKDIV_Div2 = 0x1
	// Divide RNG clock by 2^2
	RNG_CR_CLKDIV_Div4 = 0x2
	// Divide RNG clock by 2^3
	RNG_CR_CLKDIV_Div8 = 0x3
	// Divide RNG clock by 2^4
	RNG_CR_CLKDIV_Div16 = 0x4
	// Divide RNG clock by 2^5
	RNG_CR_CLKDIV_Div32 = 0x5
	// Divide RNG clock by 2^6
	RNG_CR_CLKDIV_Div64 = 0x6
	// Divide RNG clock by 2^7
	RNG_CR_CLKDIV_Div128 = 0x7
	// Divide RNG clock by 2^8
	RNG_CR_CLKDIV_Div256 = 0x8
	// Divide RNG clock by 2^9
	RNG_CR_CLKDIV_Div512 = 0x9
	// Divide RNG clock by 2^10
	RNG_CR_CLKDIV_Div1024 = 0xa
	// Divide RNG clock by 2^11
	RNG_CR_CLKDIV_Div2048 = 0xb
	// Divide RNG clock by 2^12
	RNG_CR_CLKDIV_Div4096 = 0xc
	// Divide RNG clock by 2^13
	RNG_CR_CLKDIV_Div8192 = 0xd
	// Divide RNG clock by 2^14
	RNG_CR_CLKDIV_Div16384 = 0xe
	// Divide RNG clock by 2^15
	RNG_CR_CLKDIV_Div32768 = 0xf
	// Position of RNG_CONFIG1 field.
	RNG_CR_RNG_CONFIG1_Pos = 0x14
	// Bit mask of RNG_CONFIG1 field.
	RNG_CR_RNG_CONFIG1_Msk = 0x3f00000
	// Recommended value for config A (NIST certifiable)
	RNG_CR_RNG_CONFIG1_ConfigA = 0xf
	// Recommended value for config B (not NIST certifiable)
	RNG_CR_RNG_CONFIG1_ConfigB = 0x18
	// Position of CONDRST field.
	RNG_CR_CONDRST_Pos = 0x1e
	// Bit mask of CONDRST field.
	RNG_CR_CONDRST_Msk = 0x40000000
	// Bit CONDRST.
	RNG_CR_CONDRST = 0x40000000
	// Position of CONFIGLOCK field.
	RNG_CR_CONFIGLOCK_Pos = 0x1f
	// Bit mask of CONFIGLOCK field.
	RNG_CR_CONFIGLOCK_Msk = 0x80000000
	// Bit CONFIGLOCK.
	RNG_CR_CONFIGLOCK = 0x80000000
	// Writes to the RNG_CR configuration bits [29:4] are allowed
	RNG_CR_CONFIGLOCK_Enabled = 0x0
	// Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset
	RNG_CR_CONFIGLOCK_Disabled = 0x1

	// SR: RNG status register
	// Position of DRDY field.
	RNG_SR_DRDY_Pos = 0x0
	// Bit mask of DRDY field.
	RNG_SR_DRDY_Msk = 0x1
	// Bit DRDY.
	RNG_SR_DRDY = 0x1
	// The RNG_DR register is not yet valid, no random data is available
	RNG_SR_DRDY_Invalid = 0x0
	// The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated.
	RNG_SR_DRDY_Valid = 0x1
	// Position of CECS field.
	RNG_SR_CECS_Pos = 0x1
	// Bit mask of CECS field.
	RNG_SR_CECS_Msk = 0x2
	// Bit CECS.
	RNG_SR_CECS = 0x2
	// The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
	RNG_SR_CECS_Correct = 0x0
	// The RNG clock is too slow
	RNG_SR_CECS_Slow = 0x1
	// Position of SECS field.
	RNG_SR_SECS_Pos = 0x2
	// Bit mask of SECS field.
	RNG_SR_SECS_Msk = 0x4
	// Bit SECS.
	RNG_SR_SECS = 0x4
	// No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.
	RNG_SR_SECS_NoFault = 0x0
	// At least one faulty sequence has been detected - see ref manual for details
	RNG_SR_SECS_Fault = 0x1
	// Position of CEIS field.
	RNG_SR_CEIS_Pos = 0x5
	// Bit mask of CEIS field.
	RNG_SR_CEIS_Msk = 0x20
	// Bit CEIS.
	RNG_SR_CEIS = 0x20
	// Clear flag
	RNG_SR_CEIS_Clear = 0x0
	// The RNG clock is correct
	RNG_SR_CEIS_Correct = 0x0
	// The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register
	RNG_SR_CEIS_Slow = 0x1
	// Position of SEIS field.
	RNG_SR_SEIS_Pos = 0x6
	// Bit mask of SEIS field.
	RNG_SR_SEIS_Msk = 0x40
	// Bit SEIS.
	RNG_SR_SEIS = 0x40
	// Clear flag
	RNG_SR_SEIS_Clear = 0x0
	// No faulty sequence detected
	RNG_SR_SEIS_NoFault = 0x0
	// At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register.
	RNG_SR_SEIS_Fault = 0x1

	// DR: The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.
	// Position of RNDATA field.
	RNG_DR_RNDATA_Pos = 0x0
	// Bit mask of RNDATA field.
	RNG_DR_RNDATA_Msk = 0xffffffff

	// HTCR: The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.
	// Position of HTCFG field.
	RNG_HTCR_HTCFG_Pos = 0x0
	// Bit mask of HTCFG field.
	RNG_HTCR_HTCFG_Msk = 0xffffffff
	// Recommended value for RNG certification (0x0000_AA74)
	RNG_HTCR_HTCFG_Recommended = 0xaa74
	// Magic number to be written before any write (0x1759_0ABC)
	RNG_HTCR_HTCFG_Magic = 0x17590abc
)

// Constants for RTC: Real-time clock
const (
	// TR: time register
	// Position of PM field.
	RTC_TR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_TR_PM_Msk = 0x400000
	// Bit PM.
	RTC_TR_PM = 0x400000
	// AM or 24-hour format
	RTC_TR_PM_AM = 0x0
	// PM
	RTC_TR_PM_PM = 0x1
	// Position of HT field.
	RTC_TR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_TR_HT_Msk = 0x300000
	// Position of HU field.
	RTC_TR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_TR_HU_Msk = 0xf0000
	// Position of MNT field.
	RTC_TR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_TR_MNT_Msk = 0x7000
	// Position of MNU field.
	RTC_TR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_TR_MNU_Msk = 0xf00
	// Position of ST field.
	RTC_TR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_TR_ST_Msk = 0x70
	// Position of SU field.
	RTC_TR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_TR_SU_Msk = 0xf

	// DR: date register
	// Position of YT field.
	RTC_DR_YT_Pos = 0x14
	// Bit mask of YT field.
	RTC_DR_YT_Msk = 0xf00000
	// Position of YU field.
	RTC_DR_YU_Pos = 0x10
	// Bit mask of YU field.
	RTC_DR_YU_Msk = 0xf0000
	// Position of WDU field.
	RTC_DR_WDU_Pos = 0xd
	// Bit mask of WDU field.
	RTC_DR_WDU_Msk = 0xe000
	// Position of MT field.
	RTC_DR_MT_Pos = 0xc
	// Bit mask of MT field.
	RTC_DR_MT_Msk = 0x1000
	// Bit MT.
	RTC_DR_MT = 0x1000
	// Position of MU field.
	RTC_DR_MU_Pos = 0x8
	// Bit mask of MU field.
	RTC_DR_MU_Msk = 0xf00
	// Position of DT field.
	RTC_DR_DT_Pos = 0x4
	// Bit mask of DT field.
	RTC_DR_DT_Msk = 0x30
	// Position of DU field.
	RTC_DR_DU_Pos = 0x0
	// Bit mask of DU field.
	RTC_DR_DU_Msk = 0xf

	// SSR: RTC sub second register
	// Position of SS field.
	RTC_SSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_SSR_SS_Msk = 0xffff

	// ICSR: RTC initialization control and status register
	// Position of ALRAWF field.
	RTC_ICSR_ALRAWF_Pos = 0x1
	// Bit mask of ALRAWF field.
	RTC_ICSR_ALRAWF_Msk = 0x2
	// Bit ALRAWF.
	RTC_ICSR_ALRAWF = 0x2
	// Position of ALRBWF field.
	RTC_ICSR_ALRBWF_Pos = 0x2
	// Bit mask of ALRBWF field.
	RTC_ICSR_ALRBWF_Msk = 0x4
	// Bit ALRBWF.
	RTC_ICSR_ALRBWF = 0x4
	// Position of WUTWF field.
	RTC_ICSR_WUTWF_Pos = 0x2
	// Bit mask of WUTWF field.
	RTC_ICSR_WUTWF_Msk = 0x4
	// Bit WUTWF.
	RTC_ICSR_WUTWF = 0x4
	// Wakeup timer configuration update not allowed
	RTC_ICSR_WUTWF_UpdateNotAllowed = 0x0
	// Wakeup timer configuration update allowed
	RTC_ICSR_WUTWF_UpdateAllowed = 0x1
	// Position of SHPF field.
	RTC_ICSR_SHPF_Pos = 0x3
	// Bit mask of SHPF field.
	RTC_ICSR_SHPF_Msk = 0x8
	// Bit SHPF.
	RTC_ICSR_SHPF = 0x8
	// No shift operation is pending
	RTC_ICSR_SHPF_NoShiftPending = 0x0
	// A shift operation is pending
	RTC_ICSR_SHPF_ShiftPending = 0x1
	// Position of INITS field.
	RTC_ICSR_INITS_Pos = 0x4
	// Bit mask of INITS field.
	RTC_ICSR_INITS_Msk = 0x10
	// Bit INITS.
	RTC_ICSR_INITS = 0x10
	// Calendar has not been initialized
	RTC_ICSR_INITS_NotInitalized = 0x0
	// Calendar has been initialized
	RTC_ICSR_INITS_Initalized = 0x1
	// Position of RSF field.
	RTC_ICSR_RSF_Pos = 0x5
	// Bit mask of RSF field.
	RTC_ICSR_RSF_Msk = 0x20
	// Bit RSF.
	RTC_ICSR_RSF = 0x20
	// Calendar shadow registers not yet synchronized
	RTC_ICSR_RSF_NotSynced = 0x0
	// Calendar shadow registers synchronized
	RTC_ICSR_RSF_Synced = 0x1
	// This flag is cleared by software by writing 0
	RTC_ICSR_RSF_Clear = 0x0
	// Position of INITF field.
	RTC_ICSR_INITF_Pos = 0x6
	// Bit mask of INITF field.
	RTC_ICSR_INITF_Msk = 0x40
	// Bit INITF.
	RTC_ICSR_INITF = 0x40
	// Calendar registers update is not allowed
	RTC_ICSR_INITF_NotAllowed = 0x0
	// Calendar registers update is allowed
	RTC_ICSR_INITF_Allowed = 0x1
	// Position of INIT field.
	RTC_ICSR_INIT_Pos = 0x7
	// Bit mask of INIT field.
	RTC_ICSR_INIT_Msk = 0x80
	// Bit INIT.
	RTC_ICSR_INIT = 0x80
	// Free running mode
	RTC_ICSR_INIT_FreeRunningMode = 0x0
	// Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
	RTC_ICSR_INIT_InitMode = 0x1
	// Position of RECALPF field.
	RTC_ICSR_RECALPF_Pos = 0x10
	// Bit mask of RECALPF field.
	RTC_ICSR_RECALPF_Msk = 0x10000
	// Bit RECALPF.
	RTC_ICSR_RECALPF = 0x10000
	// The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
	RTC_ICSR_RECALPF_Pending = 0x1

	// PRER: prescaler register
	// Position of PREDIV_A field.
	RTC_PRER_PREDIV_A_Pos = 0x10
	// Bit mask of PREDIV_A field.
	RTC_PRER_PREDIV_A_Msk = 0x7f0000
	// Position of PREDIV_S field.
	RTC_PRER_PREDIV_S_Pos = 0x0
	// Bit mask of PREDIV_S field.
	RTC_PRER_PREDIV_S_Msk = 0x7fff

	// WUTR: wakeup timer register
	// Position of WUT field.
	RTC_WUTR_WUT_Pos = 0x0
	// Bit mask of WUT field.
	RTC_WUTR_WUT_Msk = 0xffff
	// Position of WUTOCLR field.
	RTC_WUTR_WUTOCLR_Pos = 0x10
	// Bit mask of WUTOCLR field.
	RTC_WUTR_WUTOCLR_Msk = 0xffff0000

	// CR: RTC control register
	// Position of WUCKSEL field.
	RTC_CR_WUCKSEL_Pos = 0x0
	// Bit mask of WUCKSEL field.
	RTC_CR_WUCKSEL_Msk = 0x7
	// RTC/16 clock is selected
	RTC_CR_WUCKSEL_Div16 = 0x0
	// RTC/8 clock is selected
	RTC_CR_WUCKSEL_Div8 = 0x1
	// RTC/4 clock is selected
	RTC_CR_WUCKSEL_Div4 = 0x2
	// RTC/2 clock is selected
	RTC_CR_WUCKSEL_Div2 = 0x3
	// ck_spre (usually 1 Hz) clock is selected
	RTC_CR_WUCKSEL_ClockSpare = 0x4
	// ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
	RTC_CR_WUCKSEL_ClockSpareWithOffset = 0x6
	// Position of TSEDGE field.
	RTC_CR_TSEDGE_Pos = 0x3
	// Bit mask of TSEDGE field.
	RTC_CR_TSEDGE_Msk = 0x8
	// Bit TSEDGE.
	RTC_CR_TSEDGE = 0x8
	// RTC_TS input rising edge generates a time-stamp event
	RTC_CR_TSEDGE_RisingEdge = 0x0
	// RTC_TS input falling edge generates a time-stamp event
	RTC_CR_TSEDGE_FallingEdge = 0x1
	// Position of REFCKON field.
	RTC_CR_REFCKON_Pos = 0x4
	// Bit mask of REFCKON field.
	RTC_CR_REFCKON_Msk = 0x10
	// Bit REFCKON.
	RTC_CR_REFCKON = 0x10
	// RTC_REFIN detection disabled
	RTC_CR_REFCKON_Disabled = 0x0
	// RTC_REFIN detection enabled
	RTC_CR_REFCKON_Enabled = 0x1
	// Position of BYPSHAD field.
	RTC_CR_BYPSHAD_Pos = 0x5
	// Bit mask of BYPSHAD field.
	RTC_CR_BYPSHAD_Msk = 0x20
	// Bit BYPSHAD.
	RTC_CR_BYPSHAD = 0x20
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
	RTC_CR_BYPSHAD_ShadowReg = 0x0
	// Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
	RTC_CR_BYPSHAD_BypassShadowReg = 0x1
	// Position of FMT field.
	RTC_CR_FMT_Pos = 0x6
	// Bit mask of FMT field.
	RTC_CR_FMT_Msk = 0x40
	// Bit FMT.
	RTC_CR_FMT = 0x40
	// 24 hour/day format
	RTC_CR_FMT_TwentyFourHour = 0x0
	// AM/PM hour format
	RTC_CR_FMT_AmPm = 0x1
	// Position of ALRAE field.
	RTC_CR_ALRAE_Pos = 0x9
	// Bit mask of ALRAE field.
	RTC_CR_ALRAE_Msk = 0x200
	// Bit ALRAE.
	RTC_CR_ALRAE = 0x200
	// Alarm disabled
	RTC_CR_ALRAE_Disabled = 0x0
	// Alarm enabled
	RTC_CR_ALRAE_Enabled = 0x1
	// Position of ALRBE field.
	RTC_CR_ALRBE_Pos = 0xa
	// Bit mask of ALRBE field.
	RTC_CR_ALRBE_Msk = 0x400
	// Bit ALRBE.
	RTC_CR_ALRBE = 0x400
	// Alarm disabled
	RTC_CR_ALRBE_Disabled = 0x0
	// Alarm enabled
	RTC_CR_ALRBE_Enabled = 0x1
	// Position of WUTE field.
	RTC_CR_WUTE_Pos = 0xa
	// Bit mask of WUTE field.
	RTC_CR_WUTE_Msk = 0x400
	// Bit WUTE.
	RTC_CR_WUTE = 0x400
	// Wakeup timer disabled
	RTC_CR_WUTE_Disabled = 0x0
	// Wakeup timer enabled
	RTC_CR_WUTE_Enabled = 0x1
	// Position of TSE field.
	RTC_CR_TSE_Pos = 0xb
	// Bit mask of TSE field.
	RTC_CR_TSE_Msk = 0x800
	// Bit TSE.
	RTC_CR_TSE = 0x800
	// Timestamp disabled
	RTC_CR_TSE_Disabled = 0x0
	// Timestamp enabled
	RTC_CR_TSE_Enabled = 0x1
	// Position of ALRAIE field.
	RTC_CR_ALRAIE_Pos = 0xd
	// Bit mask of ALRAIE field.
	RTC_CR_ALRAIE_Msk = 0x2000
	// Bit ALRAIE.
	RTC_CR_ALRAIE = 0x2000
	// Alarm Interrupt disabled
	RTC_CR_ALRAIE_Disabled = 0x0
	// Alarm Interrupt enabled
	RTC_CR_ALRAIE_Enabled = 0x1
	// Position of ALRBIE field.
	RTC_CR_ALRBIE_Pos = 0xe
	// Bit mask of ALRBIE field.
	RTC_CR_ALRBIE_Msk = 0x4000
	// Bit ALRBIE.
	RTC_CR_ALRBIE = 0x4000
	// Alarm Interrupt disabled
	RTC_CR_ALRBIE_Disabled = 0x0
	// Alarm Interrupt enabled
	RTC_CR_ALRBIE_Enabled = 0x1
	// Position of WUTIE field.
	RTC_CR_WUTIE_Pos = 0xe
	// Bit mask of WUTIE field.
	RTC_CR_WUTIE_Msk = 0x4000
	// Bit WUTIE.
	RTC_CR_WUTIE = 0x4000
	// Wakeup timer interrupt disabled
	RTC_CR_WUTIE_Disabled = 0x0
	// Wakeup timer interrupt enabled
	RTC_CR_WUTIE_Enabled = 0x1
	// Position of TSIE field.
	RTC_CR_TSIE_Pos = 0xf
	// Bit mask of TSIE field.
	RTC_CR_TSIE_Msk = 0x8000
	// Bit TSIE.
	RTC_CR_TSIE = 0x8000
	// Time-stamp Interrupt disabled
	RTC_CR_TSIE_Disabled = 0x0
	// Time-stamp Interrupt enabled
	RTC_CR_TSIE_Enabled = 0x1
	// Position of ADD1H field.
	RTC_CR_ADD1H_Pos = 0x10
	// Bit mask of ADD1H field.
	RTC_CR_ADD1H_Msk = 0x10000
	// Bit ADD1H.
	RTC_CR_ADD1H = 0x10000
	// Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
	RTC_CR_ADD1H_Add1 = 0x1
	// Position of SUB1H field.
	RTC_CR_SUB1H_Pos = 0x11
	// Bit mask of SUB1H field.
	RTC_CR_SUB1H_Msk = 0x20000
	// Bit SUB1H.
	RTC_CR_SUB1H = 0x20000
	// Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
	RTC_CR_SUB1H_Sub1 = 0x1
	// Position of BKP field.
	RTC_CR_BKP_Pos = 0x12
	// Bit mask of BKP field.
	RTC_CR_BKP_Msk = 0x40000
	// Bit BKP.
	RTC_CR_BKP = 0x40000
	// Daylight Saving Time change has not been performed
	RTC_CR_BKP_DSTNotChanged = 0x0
	// Daylight Saving Time change has been performed
	RTC_CR_BKP_DSTChanged = 0x1
	// Position of COSEL field.
	RTC_CR_COSEL_Pos = 0x13
	// Bit mask of COSEL field.
	RTC_CR_COSEL_Msk = 0x80000
	// Bit COSEL.
	RTC_CR_COSEL = 0x80000
	// Calibration output is 512 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_512Hz = 0x0
	// Calibration output is 1 Hz (with default prescaler setting)
	RTC_CR_COSEL_CalFreq_1Hz = 0x1
	// Position of POL field.
	RTC_CR_POL_Pos = 0x14
	// Bit mask of POL field.
	RTC_CR_POL_Msk = 0x100000
	// Bit POL.
	RTC_CR_POL = 0x100000
	// The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_High = 0x0
	// The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
	RTC_CR_POL_Low = 0x1
	// Position of OSEL field.
	RTC_CR_OSEL_Pos = 0x15
	// Bit mask of OSEL field.
	RTC_CR_OSEL_Msk = 0x600000
	// Output disabled
	RTC_CR_OSEL_Disabled = 0x0
	// Alarm A output enabled
	RTC_CR_OSEL_AlarmA = 0x1
	// Alarm B output enabled
	RTC_CR_OSEL_AlarmB = 0x2
	// Wakeup output enabled
	RTC_CR_OSEL_Wakeup = 0x3
	// Position of COE field.
	RTC_CR_COE_Pos = 0x17
	// Bit mask of COE field.
	RTC_CR_COE_Msk = 0x800000
	// Bit COE.
	RTC_CR_COE = 0x800000
	// Calibration output disabled
	RTC_CR_COE_Disabled = 0x0
	// Calibration output enabled
	RTC_CR_COE_Enabled = 0x1
	// Position of ITSE field.
	RTC_CR_ITSE_Pos = 0x18
	// Bit mask of ITSE field.
	RTC_CR_ITSE_Msk = 0x1000000
	// Bit ITSE.
	RTC_CR_ITSE = 0x1000000
	// Internal event timestamp disabled
	RTC_CR_ITSE_Disabled = 0x0
	// Internal event timestamp enabled
	RTC_CR_ITSE_Enabled = 0x1
	// Position of TAMPTS field.
	RTC_CR_TAMPTS_Pos = 0x19
	// Bit mask of TAMPTS field.
	RTC_CR_TAMPTS_Msk = 0x2000000
	// Bit TAMPTS.
	RTC_CR_TAMPTS = 0x2000000
	// Tamper detection event does not cause a RTC timestamp to be saved
	RTC_CR_TAMPTS_Disabled = 0x0
	// Save RTC timestamp on tamper detection event
	RTC_CR_TAMPTS_Enabled = 0x1
	// Position of TAMPOE field.
	RTC_CR_TAMPOE_Pos = 0x1a
	// Bit mask of TAMPOE field.
	RTC_CR_TAMPOE_Msk = 0x4000000
	// Bit TAMPOE.
	RTC_CR_TAMPOE = 0x4000000
	// The tamper flag is not routed on TAMPALRM
	RTC_CR_TAMPOE_Disabled = 0x0
	// The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL
	RTC_CR_TAMPOE_Enabled = 0x1
	// Position of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU_Pos = 0x1d
	// Bit mask of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU_Msk = 0x20000000
	// Bit TAMPALRM_PU.
	RTC_CR_TAMPALRM_PU = 0x20000000
	// No pull-up is applied on TAMPALRM output
	RTC_CR_TAMPALRM_PU_NoPullUp = 0x0
	// A pull-up is applied on TAMPALRM output
	RTC_CR_TAMPALRM_PU_PullUp = 0x1
	// Position of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE_Pos = 0x1e
	// Bit mask of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE_Msk = 0x40000000
	// Bit TAMPALRM_TYPE.
	RTC_CR_TAMPALRM_TYPE = 0x40000000
	// TAMPALRM is push-pull output
	RTC_CR_TAMPALRM_TYPE_PushPull = 0x0
	// TAMPALRM is open-drain output
	RTC_CR_TAMPALRM_TYPE_OpenDrain = 0x1
	// Position of OUT2EN field.
	RTC_CR_OUT2EN_Pos = 0x1f
	// Bit mask of OUT2EN field.
	RTC_CR_OUT2EN_Msk = 0x80000000
	// Bit OUT2EN.
	RTC_CR_OUT2EN = 0x80000000
	// RTC output 2 disable
	RTC_CR_OUT2EN_Disabled = 0x0
	// RTC output 2 enable
	RTC_CR_OUT2EN_Enabled = 0x1

	// PRIVCR: RTC privilege mode control register
	// Position of PRIV field.
	RTC_PRIVCR_PRIV_Pos = 0xf
	// Bit mask of PRIV field.
	RTC_PRIVCR_PRIV_Msk = 0x8000
	// Bit PRIV.
	RTC_PRIVCR_PRIV = 0x8000
	// Position of INITPRIV field.
	RTC_PRIVCR_INITPRIV_Pos = 0xe
	// Bit mask of INITPRIV field.
	RTC_PRIVCR_INITPRIV_Msk = 0x4000
	// Bit INITPRIV.
	RTC_PRIVCR_INITPRIV = 0x4000
	// Position of CALPRIV field.
	RTC_PRIVCR_CALPRIV_Pos = 0xd
	// Bit mask of CALPRIV field.
	RTC_PRIVCR_CALPRIV_Msk = 0x2000
	// Bit CALPRIV.
	RTC_PRIVCR_CALPRIV = 0x2000
	// Position of TSPRIV field.
	RTC_PRIVCR_TSPRIV_Pos = 0x3
	// Bit mask of TSPRIV field.
	RTC_PRIVCR_TSPRIV_Msk = 0x8
	// Bit TSPRIV.
	RTC_PRIVCR_TSPRIV = 0x8
	// Position of WUTPRIV field.
	RTC_PRIVCR_WUTPRIV_Pos = 0x2
	// Bit mask of WUTPRIV field.
	RTC_PRIVCR_WUTPRIV_Msk = 0x4
	// Bit WUTPRIV.
	RTC_PRIVCR_WUTPRIV = 0x4
	// Position of ALRBPRIV field.
	RTC_PRIVCR_ALRBPRIV_Pos = 0x1
	// Bit mask of ALRBPRIV field.
	RTC_PRIVCR_ALRBPRIV_Msk = 0x2
	// Bit ALRBPRIV.
	RTC_PRIVCR_ALRBPRIV = 0x2
	// Position of ALRAPRIV field.
	RTC_PRIVCR_ALRAPRIV_Pos = 0x0
	// Bit mask of ALRAPRIV field.
	RTC_PRIVCR_ALRAPRIV_Msk = 0x1
	// Bit ALRAPRIV.
	RTC_PRIVCR_ALRAPRIV = 0x1

	// SMCR: RTC secure mode control register
	// Position of DECPROT field.
	RTC_SMCR_DECPROT_Pos = 0xf
	// Bit mask of DECPROT field.
	RTC_SMCR_DECPROT_Msk = 0x8000
	// Bit DECPROT.
	RTC_SMCR_DECPROT = 0x8000
	// Position of INITDPROT field.
	RTC_SMCR_INITDPROT_Pos = 0xe
	// Bit mask of INITDPROT field.
	RTC_SMCR_INITDPROT_Msk = 0x4000
	// Bit INITDPROT.
	RTC_SMCR_INITDPROT = 0x4000
	// Position of CALDPROT field.
	RTC_SMCR_CALDPROT_Pos = 0xd
	// Bit mask of CALDPROT field.
	RTC_SMCR_CALDPROT_Msk = 0x2000
	// Bit CALDPROT.
	RTC_SMCR_CALDPROT = 0x2000
	// Position of TSDPROT field.
	RTC_SMCR_TSDPROT_Pos = 0x3
	// Bit mask of TSDPROT field.
	RTC_SMCR_TSDPROT_Msk = 0x8
	// Bit TSDPROT.
	RTC_SMCR_TSDPROT = 0x8
	// Position of WUTDPROT field.
	RTC_SMCR_WUTDPROT_Pos = 0x2
	// Bit mask of WUTDPROT field.
	RTC_SMCR_WUTDPROT_Msk = 0x4
	// Bit WUTDPROT.
	RTC_SMCR_WUTDPROT = 0x4
	// Position of ALRBDPROT field.
	RTC_SMCR_ALRBDPROT_Pos = 0x1
	// Bit mask of ALRBDPROT field.
	RTC_SMCR_ALRBDPROT_Msk = 0x2
	// Bit ALRBDPROT.
	RTC_SMCR_ALRBDPROT = 0x2
	// Position of ALRADPROT field.
	RTC_SMCR_ALRADPROT_Pos = 0x0
	// Bit mask of ALRADPROT field.
	RTC_SMCR_ALRADPROT_Msk = 0x1
	// Bit ALRADPROT.
	RTC_SMCR_ALRADPROT = 0x1

	// WPR: write protection register
	// Position of KEY field.
	RTC_WPR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	RTC_WPR_KEY_Msk = 0xff
	// Activate write protection (any value that is not the keys)
	RTC_WPR_KEY_Activate = 0x0
	// Key 2
	RTC_WPR_KEY_Deactivate2 = 0x53
	// Key 1
	RTC_WPR_KEY_Deactivate1 = 0xca

	// CALR: calibration register
	// Position of CALP field.
	RTC_CALR_CALP_Pos = 0xf
	// Bit mask of CALP field.
	RTC_CALR_CALP_Msk = 0x8000
	// Bit CALP.
	RTC_CALR_CALP = 0x8000
	// No RTCCLK pulses are added
	RTC_CALR_CALP_NoChange = 0x0
	// One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
	RTC_CALR_CALP_IncreaseFreq = 0x1
	// Position of CALW8 field.
	RTC_CALR_CALW8_Pos = 0xe
	// Bit mask of CALW8 field.
	RTC_CALR_CALW8_Msk = 0x4000
	// Bit CALW8.
	RTC_CALR_CALW8 = 0x4000
	// When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
	RTC_CALR_CALW8_EightSeconds = 0x1
	// Position of CALW16 field.
	RTC_CALR_CALW16_Pos = 0xd
	// Bit mask of CALW16 field.
	RTC_CALR_CALW16_Msk = 0x2000
	// Bit CALW16.
	RTC_CALR_CALW16 = 0x2000
	// When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
	RTC_CALR_CALW16_SixteenSeconds = 0x1
	// Position of LPCAL field.
	RTC_CALR_LPCAL_Pos = 0xc
	// Bit mask of LPCAL field.
	RTC_CALR_LPCAL_Msk = 0x1000
	// Bit LPCAL.
	RTC_CALR_LPCAL = 0x1000
	// Position of CALM field.
	RTC_CALR_CALM_Pos = 0x0
	// Bit mask of CALM field.
	RTC_CALR_CALM_Msk = 0x1ff

	// SHIFTR: shift control register
	// Position of ADD1S field.
	RTC_SHIFTR_ADD1S_Pos = 0x1f
	// Bit mask of ADD1S field.
	RTC_SHIFTR_ADD1S_Msk = 0x80000000
	// Bit ADD1S.
	RTC_SHIFTR_ADD1S = 0x80000000
	// Add one second to the clock/calendar
	RTC_SHIFTR_ADD1S_Add1 = 0x1
	// Position of SUBFS field.
	RTC_SHIFTR_SUBFS_Pos = 0x0
	// Bit mask of SUBFS field.
	RTC_SHIFTR_SUBFS_Msk = 0x7fff

	// ALRMAR: Alarm %s register
	// Position of MSK1 field.
	RTC_ALRMR_MSK1_Pos = 0x7
	// Bit mask of MSK1 field.
	RTC_ALRMR_MSK1_Msk = 0x80
	// Bit MSK1.
	RTC_ALRMR_MSK1 = 0x80
	// Alarm set if the date/day match
	RTC_ALRMR_MSK1_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK1_NotMask = 0x1
	// Position of MSK4 field.
	RTC_ALRMR_MSK4_Pos = 0x1f
	// Bit mask of MSK4 field.
	RTC_ALRMR_MSK4_Msk = 0x80000000
	// Bit MSK4.
	RTC_ALRMR_MSK4 = 0x80000000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK4_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK4_NotMask = 0x1
	// Position of WDSEL field.
	RTC_ALRMR_WDSEL_Pos = 0x1e
	// Bit mask of WDSEL field.
	RTC_ALRMR_WDSEL_Msk = 0x40000000
	// Bit WDSEL.
	RTC_ALRMR_WDSEL = 0x40000000
	// DU[3:0] represents the date units
	RTC_ALRMR_WDSEL_DateUnits = 0x0
	// DU[3:0] represents the week day. DT[1:0] is don’t care.
	RTC_ALRMR_WDSEL_WeekDay = 0x1
	// Position of DT field.
	RTC_ALRMR_DT_Pos = 0x1c
	// Bit mask of DT field.
	RTC_ALRMR_DT_Msk = 0x30000000
	// Position of DU field.
	RTC_ALRMR_DU_Pos = 0x18
	// Bit mask of DU field.
	RTC_ALRMR_DU_Msk = 0xf000000
	// Position of MSK3 field.
	RTC_ALRMR_MSK3_Pos = 0x17
	// Bit mask of MSK3 field.
	RTC_ALRMR_MSK3_Msk = 0x800000
	// Bit MSK3.
	RTC_ALRMR_MSK3 = 0x800000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK3_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK3_NotMask = 0x1
	// Position of PM field.
	RTC_ALRMR_PM_Pos = 0x16
	// Bit mask of PM field.
	RTC_ALRMR_PM_Msk = 0x400000
	// Bit PM.
	RTC_ALRMR_PM = 0x400000
	// AM or 24-hour format
	RTC_ALRMR_PM_AM = 0x0
	// PM
	RTC_ALRMR_PM_PM = 0x1
	// Position of HT field.
	RTC_ALRMR_HT_Pos = 0x14
	// Bit mask of HT field.
	RTC_ALRMR_HT_Msk = 0x300000
	// Position of HU field.
	RTC_ALRMR_HU_Pos = 0x10
	// Bit mask of HU field.
	RTC_ALRMR_HU_Msk = 0xf0000
	// Position of MSK2 field.
	RTC_ALRMR_MSK2_Pos = 0xf
	// Bit mask of MSK2 field.
	RTC_ALRMR_MSK2_Msk = 0x8000
	// Bit MSK2.
	RTC_ALRMR_MSK2 = 0x8000
	// Alarm set if the date/day match
	RTC_ALRMR_MSK2_Mask = 0x0
	// Date/day don’t care in Alarm comparison
	RTC_ALRMR_MSK2_NotMask = 0x1
	// Position of MNT field.
	RTC_ALRMR_MNT_Pos = 0xc
	// Bit mask of MNT field.
	RTC_ALRMR_MNT_Msk = 0x7000
	// Position of MNU field.
	RTC_ALRMR_MNU_Pos = 0x8
	// Bit mask of MNU field.
	RTC_ALRMR_MNU_Msk = 0xf00
	// Position of ST field.
	RTC_ALRMR_ST_Pos = 0x4
	// Bit mask of ST field.
	RTC_ALRMR_ST_Msk = 0x70
	// Position of SU field.
	RTC_ALRMR_SU_Pos = 0x0
	// Bit mask of SU field.
	RTC_ALRMR_SU_Msk = 0xf

	// ALRMASSR: Alarm %s sub-second register
	// Position of MASKSS field.
	RTC_ALRMSSR_MASKSS_Pos = 0x18
	// Bit mask of MASKSS field.
	RTC_ALRMSSR_MASKSS_Msk = 0xf000000
	// Position of SS field.
	RTC_ALRMSSR_SS_Pos = 0x0
	// Bit mask of SS field.
	RTC_ALRMSSR_SS_Msk = 0x7fff

	// SR: RTC status register
	// Position of ALRAF field.
	RTC_SR_ALRAF_Pos = 0x1
	// Bit mask of ALRAF field.
	RTC_SR_ALRAF_Msk = 0x2
	// Bit ALRAF.
	RTC_SR_ALRAF = 0x2
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)
	RTC_SR_ALRAF_Match = 0x1
	// Position of ALRBF field.
	RTC_SR_ALRBF_Pos = 0x2
	// Bit mask of ALRBF field.
	RTC_SR_ALRBF_Msk = 0x4
	// Bit ALRBF.
	RTC_SR_ALRBF = 0x4
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)
	RTC_SR_ALRBF_Match = 0x1
	// Position of WUTF field.
	RTC_SR_WUTF_Pos = 0x2
	// Bit mask of WUTF field.
	RTC_SR_WUTF_Msk = 0x4
	// Bit WUTF.
	RTC_SR_WUTF = 0x4
	// This flag is set by hardware when the wakeup auto-reload counter reaches 0
	RTC_SR_WUTF_Zero = 0x1
	// Position of TSF field.
	RTC_SR_TSF_Pos = 0x3
	// Bit mask of TSF field.
	RTC_SR_TSF_Msk = 0x8
	// Bit TSF.
	RTC_SR_TSF = 0x8
	// This flag is set by hardware when a time-stamp event occurs
	RTC_SR_TSF_TimestampEvent = 0x1
	// Position of TSOVF field.
	RTC_SR_TSOVF_Pos = 0x4
	// Bit mask of TSOVF field.
	RTC_SR_TSOVF_Msk = 0x10
	// Bit TSOVF.
	RTC_SR_TSOVF = 0x10
	// This flag is set by hardware when a time-stamp event occurs while TSF is already set
	RTC_SR_TSOVF_Overflow = 0x1
	// Position of ITSF field.
	RTC_SR_ITSF_Pos = 0x5
	// Bit mask of ITSF field.
	RTC_SR_ITSF_Msk = 0x20
	// Bit ITSF.
	RTC_SR_ITSF = 0x20
	// This flag is set by hardware when a timestamp on the internal event occurs
	RTC_SR_ITSF_TimestampEvent = 0x1

	// MISR: RTC non-secure masked interrupt status register
	// Position of ALRAMF field.
	RTC_MISR_ALRAMF_Pos = 0x1
	// Bit mask of ALRAMF field.
	RTC_MISR_ALRAMF_Msk = 0x2
	// Bit ALRAMF.
	RTC_MISR_ALRAMF = 0x2
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
	RTC_MISR_ALRAMF_Match = 0x1
	// Position of ALRBMF field.
	RTC_MISR_ALRBMF_Pos = 0x2
	// Bit mask of ALRBMF field.
	RTC_MISR_ALRBMF_Msk = 0x4
	// Bit ALRBMF.
	RTC_MISR_ALRBMF = 0x4
	// This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
	RTC_MISR_ALRBMF_Match = 0x1
	// Position of WUTMF field.
	RTC_MISR_WUTMF_Pos = 0x2
	// Bit mask of WUTMF field.
	RTC_MISR_WUTMF_Msk = 0x4
	// Bit WUTMF.
	RTC_MISR_WUTMF = 0x4
	// This flag is set by hardware when the wakeup auto-reload counter reaches 0
	RTC_MISR_WUTMF_Zero = 0x1
	// Position of TSMF field.
	RTC_MISR_TSMF_Pos = 0x3
	// Bit mask of TSMF field.
	RTC_MISR_TSMF_Msk = 0x8
	// Bit TSMF.
	RTC_MISR_TSMF = 0x8
	// This flag is set by hardware when a time-stamp event occurs
	RTC_MISR_TSMF_TimestampEvent = 0x1
	// Position of TSOVMF field.
	RTC_MISR_TSOVMF_Pos = 0x4
	// Bit mask of TSOVMF field.
	RTC_MISR_TSOVMF_Msk = 0x10
	// Bit TSOVMF.
	RTC_MISR_TSOVMF = 0x10
	// This flag is set by hardware when a time-stamp event occurs while TSF is already set
	RTC_MISR_TSOVMF_Overflow = 0x1
	// Position of ITSMF field.
	RTC_MISR_ITSMF_Pos = 0x5
	// Bit mask of ITSMF field.
	RTC_MISR_ITSMF_Msk = 0x20
	// Bit ITSMF.
	RTC_MISR_ITSMF = 0x20
	// This flag is set by hardware when a timestamp on the internal event occurs
	RTC_MISR_ITSMF_TimestampEvent = 0x1

	// SMISR: RTC secure masked interrupt status register
	// Position of ALRAMF field.
	RTC_SMISR_ALRAMF_Pos = 0x0
	// Bit mask of ALRAMF field.
	RTC_SMISR_ALRAMF_Msk = 0x1
	// Bit ALRAMF.
	RTC_SMISR_ALRAMF = 0x1
	// Position of ALRBMF field.
	RTC_SMISR_ALRBMF_Pos = 0x1
	// Bit mask of ALRBMF field.
	RTC_SMISR_ALRBMF_Msk = 0x2
	// Bit ALRBMF.
	RTC_SMISR_ALRBMF = 0x2
	// Position of WUTMF field.
	RTC_SMISR_WUTMF_Pos = 0x2
	// Bit mask of WUTMF field.
	RTC_SMISR_WUTMF_Msk = 0x4
	// Bit WUTMF.
	RTC_SMISR_WUTMF = 0x4
	// Position of TSMF field.
	RTC_SMISR_TSMF_Pos = 0x3
	// Bit mask of TSMF field.
	RTC_SMISR_TSMF_Msk = 0x8
	// Bit TSMF.
	RTC_SMISR_TSMF = 0x8
	// Position of TSOVMF field.
	RTC_SMISR_TSOVMF_Pos = 0x4
	// Bit mask of TSOVMF field.
	RTC_SMISR_TSOVMF_Msk = 0x10
	// Bit TSOVMF.
	RTC_SMISR_TSOVMF = 0x10
	// Position of ITSMF field.
	RTC_SMISR_ITSMF_Pos = 0x5
	// Bit mask of ITSMF field.
	RTC_SMISR_ITSMF_Msk = 0x20
	// Bit ITSMF.
	RTC_SMISR_ITSMF = 0x20

	// SCR: RTC status clear register
	// Position of CALRAF field.
	RTC_SCR_CALRAF_Pos = 0x0
	// Bit mask of CALRAF field.
	RTC_SCR_CALRAF_Msk = 0x1
	// Bit CALRAF.
	RTC_SCR_CALRAF = 0x1
	// Clear interrupt flag
	RTC_SCR_CALRAF_Clear = 0x1
	// Position of CALRBF field.
	RTC_SCR_CALRBF_Pos = 0x1
	// Bit mask of CALRBF field.
	RTC_SCR_CALRBF_Msk = 0x2
	// Bit CALRBF.
	RTC_SCR_CALRBF = 0x2
	// Clear interrupt flag
	RTC_SCR_CALRBF_Clear = 0x1
	// Position of CWUTF field.
	RTC_SCR_CWUTF_Pos = 0x2
	// Bit mask of CWUTF field.
	RTC_SCR_CWUTF_Msk = 0x4
	// Bit CWUTF.
	RTC_SCR_CWUTF = 0x4
	// Clear interrupt flag
	RTC_SCR_CWUTF_Clear = 0x1
	// Position of CTSF field.
	RTC_SCR_CTSF_Pos = 0x3
	// Bit mask of CTSF field.
	RTC_SCR_CTSF_Msk = 0x8
	// Bit CTSF.
	RTC_SCR_CTSF = 0x8
	// Clear interrupt flag
	RTC_SCR_CTSF_Clear = 0x1
	// Position of CTSOVF field.
	RTC_SCR_CTSOVF_Pos = 0x4
	// Bit mask of CTSOVF field.
	RTC_SCR_CTSOVF_Msk = 0x10
	// Bit CTSOVF.
	RTC_SCR_CTSOVF = 0x10
	// Clear interrupt flag
	RTC_SCR_CTSOVF_Clear = 0x1
	// Position of CITSF field.
	RTC_SCR_CITSF_Pos = 0x5
	// Bit mask of CITSF field.
	RTC_SCR_CITSF_Msk = 0x20
	// Bit CITSF.
	RTC_SCR_CITSF = 0x20
	// Clear interrupt flag
	RTC_SCR_CITSF_Clear = 0x1
)

// Constants for SAI1: Serial audio interface
const (
	// GCR: Global configuration register
	// Position of SYNCIN field.
	SAI_GCR_SYNCIN_Pos = 0x0
	// Bit mask of SYNCIN field.
	SAI_GCR_SYNCIN_Msk = 0x3
	// Position of SYNCOUT field.
	SAI_GCR_SYNCOUT_Pos = 0x4
	// Bit mask of SYNCOUT field.
	SAI_GCR_SYNCOUT_Msk = 0x30

	// CH.CR1: AConfiguration register 1
	// Position of MCKDIV field.
	SAI_CH_CR1_MCKDIV_Pos = 0x14
	// Bit mask of MCKDIV field.
	SAI_CH_CR1_MCKDIV_Msk = 0xf00000
	// Position of NODIV field.
	SAI_CH_CR1_NODIV_Pos = 0x13
	// Bit mask of NODIV field.
	SAI_CH_CR1_NODIV_Msk = 0x80000
	// Bit NODIV.
	SAI_CH_CR1_NODIV = 0x80000
	// MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
	SAI_CH_CR1_NODIV_MasterClock = 0x0
	// MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.
	SAI_CH_CR1_NODIV_NoDiv = 0x1
	// Position of DMAEN field.
	SAI_CH_CR1_DMAEN_Pos = 0x11
	// Bit mask of DMAEN field.
	SAI_CH_CR1_DMAEN_Msk = 0x20000
	// Bit DMAEN.
	SAI_CH_CR1_DMAEN = 0x20000
	// DMA disabled
	SAI_CH_CR1_DMAEN_Disabled = 0x0
	// DMA enabled
	SAI_CH_CR1_DMAEN_Enabled = 0x1
	// Position of SAIEN field.
	SAI_CH_CR1_SAIEN_Pos = 0x10
	// Bit mask of SAIEN field.
	SAI_CH_CR1_SAIEN_Msk = 0x10000
	// Bit SAIEN.
	SAI_CH_CR1_SAIEN = 0x10000
	// SAI audio block disabled
	SAI_CH_CR1_SAIEN_Disabled = 0x0
	// SAI audio block enabled
	SAI_CH_CR1_SAIEN_Enabled = 0x1
	// Position of OUTDRIV field.
	SAI_CH_CR1_OUTDRIV_Pos = 0xd
	// Bit mask of OUTDRIV field.
	SAI_CH_CR1_OUTDRIV_Msk = 0x2000
	// Bit OUTDRIV.
	SAI_CH_CR1_OUTDRIV = 0x2000
	// Audio block output driven when SAIEN is set
	SAI_CH_CR1_OUTDRIV_OnStart = 0x0
	// Audio block output driven immediately after the setting of this bit
	SAI_CH_CR1_OUTDRIV_Immediately = 0x1
	// Position of MONO field.
	SAI_CH_CR1_MONO_Pos = 0xc
	// Bit mask of MONO field.
	SAI_CH_CR1_MONO_Msk = 0x1000
	// Bit MONO.
	SAI_CH_CR1_MONO = 0x1000
	// Stereo mode
	SAI_CH_CR1_MONO_Stereo = 0x0
	// Mono mode
	SAI_CH_CR1_MONO_Mono = 0x1
	// Position of SYNCEN field.
	SAI_CH_CR1_SYNCEN_Pos = 0xa
	// Bit mask of SYNCEN field.
	SAI_CH_CR1_SYNCEN_Msk = 0xc00
	// audio sub-block in asynchronous mode
	SAI_CH_CR1_SYNCEN_Asynchronous = 0x0
	// audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
	SAI_CH_CR1_SYNCEN_Internal = 0x1
	// audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
	SAI_CH_CR1_SYNCEN_External = 0x2
	// Position of CKSTR field.
	SAI_CH_CR1_CKSTR_Pos = 0x9
	// Bit mask of CKSTR field.
	SAI_CH_CR1_CKSTR_Msk = 0x200
	// Bit CKSTR.
	SAI_CH_CR1_CKSTR = 0x200
	// Data strobing edge is falling edge of SCK
	SAI_CH_CR1_CKSTR_FallingEdge = 0x0
	// Data strobing edge is rising edge of SCK
	SAI_CH_CR1_CKSTR_RisingEdge = 0x1
	// Position of LSBFIRST field.
	SAI_CH_CR1_LSBFIRST_Pos = 0x8
	// Bit mask of LSBFIRST field.
	SAI_CH_CR1_LSBFIRST_Msk = 0x100
	// Bit LSBFIRST.
	SAI_CH_CR1_LSBFIRST = 0x100
	// Data are transferred with MSB first
	SAI_CH_CR1_LSBFIRST_MsbFirst = 0x0
	// Data are transferred with LSB first
	SAI_CH_CR1_LSBFIRST_LsbFirst = 0x1
	// Position of DS field.
	SAI_CH_CR1_DS_Pos = 0x5
	// Bit mask of DS field.
	SAI_CH_CR1_DS_Msk = 0xe0
	// 8 bits
	SAI_CH_CR1_DS_Bit8 = 0x2
	// 10 bits
	SAI_CH_CR1_DS_Bit10 = 0x3
	// 16 bits
	SAI_CH_CR1_DS_Bit16 = 0x4
	// 20 bits
	SAI_CH_CR1_DS_Bit20 = 0x5
	// 24 bits
	SAI_CH_CR1_DS_Bit24 = 0x6
	// 32 bits
	SAI_CH_CR1_DS_Bit32 = 0x7
	// Position of PRTCFG field.
	SAI_CH_CR1_PRTCFG_Pos = 0x2
	// Bit mask of PRTCFG field.
	SAI_CH_CR1_PRTCFG_Msk = 0xc
	// Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
	SAI_CH_CR1_PRTCFG_Free = 0x0
	// SPDIF protocol
	SAI_CH_CR1_PRTCFG_Spdif = 0x1
	// AC’97 protocol
	SAI_CH_CR1_PRTCFG_Ac97 = 0x2
	// Position of MODE field.
	SAI_CH_CR1_MODE_Pos = 0x0
	// Bit mask of MODE field.
	SAI_CH_CR1_MODE_Msk = 0x3
	// Master transmitter
	SAI_CH_CR1_MODE_MasterTx = 0x0
	// Master receiver
	SAI_CH_CR1_MODE_MasterRx = 0x1
	// Slave transmitter
	SAI_CH_CR1_MODE_SlaveTx = 0x2
	// Slave receiver
	SAI_CH_CR1_MODE_SlaveRx = 0x3
	// Position of OSR field.
	SAI_CH_CR1_OSR_Pos = 0x1a
	// Bit mask of OSR field.
	SAI_CH_CR1_OSR_Msk = 0x4000000
	// Bit OSR.
	SAI_CH_CR1_OSR = 0x4000000

	// CH.CR2: AConfiguration register 2
	// Position of COMP field.
	SAI_CH_CR2_COMP_Pos = 0xe
	// Bit mask of COMP field.
	SAI_CH_CR2_COMP_Msk = 0xc000
	// No companding algorithm
	SAI_CH_CR2_COMP_NoCompanding = 0x0
	// μ-Law algorithm
	SAI_CH_CR2_COMP_MuLaw = 0x2
	// A-Law algorithm
	SAI_CH_CR2_COMP_ALaw = 0x3
	// Position of CPL field.
	SAI_CH_CR2_CPL_Pos = 0xd
	// Bit mask of CPL field.
	SAI_CH_CR2_CPL_Msk = 0x2000
	// Bit CPL.
	SAI_CH_CR2_CPL = 0x2000
	// 1’s complement representation
	SAI_CH_CR2_CPL_OnesComplement = 0x0
	// 2’s complement representation
	SAI_CH_CR2_CPL_TwosComplement = 0x1
	// Position of MUTECNT field.
	SAI_CH_CR2_MUTECNT_Pos = 0x7
	// Bit mask of MUTECNT field.
	SAI_CH_CR2_MUTECNT_Msk = 0x1f80
	// Position of MUTEVAL field.
	SAI_CH_CR2_MUTEVAL_Pos = 0x6
	// Bit mask of MUTEVAL field.
	SAI_CH_CR2_MUTEVAL_Msk = 0x40
	// Bit MUTEVAL.
	SAI_CH_CR2_MUTEVAL = 0x40
	// Bit value 0 is sent during the mute mode
	SAI_CH_CR2_MUTEVAL_SendZero = 0x0
	// Last values are sent during the mute mode
	SAI_CH_CR2_MUTEVAL_SendLast = 0x1
	// Position of MUTE field.
	SAI_CH_CR2_MUTE_Pos = 0x5
	// Bit mask of MUTE field.
	SAI_CH_CR2_MUTE_Msk = 0x20
	// Bit MUTE.
	SAI_CH_CR2_MUTE = 0x20
	// No mute mode
	SAI_CH_CR2_MUTE_Disabled = 0x0
	// Mute mode enabled
	SAI_CH_CR2_MUTE_Enabled = 0x1
	// Position of TRIS field.
	SAI_CH_CR2_TRIS_Pos = 0x4
	// Bit mask of TRIS field.
	SAI_CH_CR2_TRIS_Msk = 0x10
	// Bit TRIS.
	SAI_CH_CR2_TRIS = 0x10
	// Position of FFLUSH field.
	SAI_CH_CR2_FFLUSH_Pos = 0x3
	// Bit mask of FFLUSH field.
	SAI_CH_CR2_FFLUSH_Msk = 0x8
	// Bit FFLUSH.
	SAI_CH_CR2_FFLUSH = 0x8
	// No FIFO flush
	SAI_CH_CR2_FFLUSH_NoFlush = 0x0
	// FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
	SAI_CH_CR2_FFLUSH_Flush = 0x1
	// Position of FTH field.
	SAI_CH_CR2_FTH_Pos = 0x0
	// Bit mask of FTH field.
	SAI_CH_CR2_FTH_Msk = 0x7
	// FIFO empty
	SAI_CH_CR2_FTH_Empty = 0x0
	// 1⁄4 FIFO
	SAI_CH_CR2_FTH_Quarter1 = 0x1
	// 1⁄2 FIFO
	SAI_CH_CR2_FTH_Quarter2 = 0x2
	// 3⁄4 FIFO
	SAI_CH_CR2_FTH_Quarter3 = 0x3
	// FIFO full
	SAI_CH_CR2_FTH_Full = 0x4

	// CH.FRCR: AFRCR
	// Position of FSOFF field.
	SAI_CH_FRCR_FSOFF_Pos = 0x12
	// Bit mask of FSOFF field.
	SAI_CH_FRCR_FSOFF_Msk = 0x40000
	// Bit FSOFF.
	SAI_CH_FRCR_FSOFF = 0x40000
	// FS is asserted on the first bit of the slot 0
	SAI_CH_FRCR_FSOFF_OnFirst = 0x0
	// FS is asserted one bit before the first bit of the slot 0
	SAI_CH_FRCR_FSOFF_BeforeFirst = 0x1
	// Position of FSPOL field.
	SAI_CH_FRCR_FSPOL_Pos = 0x11
	// Bit mask of FSPOL field.
	SAI_CH_FRCR_FSPOL_Msk = 0x20000
	// Bit FSPOL.
	SAI_CH_FRCR_FSPOL = 0x20000
	// FS is active low (falling edge)
	SAI_CH_FRCR_FSPOL_FallingEdge = 0x0
	// FS is active high (rising edge)
	SAI_CH_FRCR_FSPOL_RisingEdge = 0x1
	// Position of FSDEF field.
	SAI_CH_FRCR_FSDEF_Pos = 0x10
	// Bit mask of FSDEF field.
	SAI_CH_FRCR_FSDEF_Msk = 0x10000
	// Bit FSDEF.
	SAI_CH_FRCR_FSDEF = 0x10000
	// Position of FSALL field.
	SAI_CH_FRCR_FSALL_Pos = 0x8
	// Bit mask of FSALL field.
	SAI_CH_FRCR_FSALL_Msk = 0x7f00
	// Position of FRL field.
	SAI_CH_FRCR_FRL_Pos = 0x0
	// Bit mask of FRL field.
	SAI_CH_FRCR_FRL_Msk = 0xff

	// CH.SLOTR: ASlot register
	// Position of SLOTEN field.
	SAI_CH_SLOTR_SLOTEN_Pos = 0x10
	// Bit mask of SLOTEN field.
	SAI_CH_SLOTR_SLOTEN_Msk = 0xffff0000
	// Inactive slot
	SAI_CH_SLOTR_SLOTEN_Inactive = 0x0
	// Active slot
	SAI_CH_SLOTR_SLOTEN_Active = 0x1
	// Position of NBSLOT field.
	SAI_CH_SLOTR_NBSLOT_Pos = 0x8
	// Bit mask of NBSLOT field.
	SAI_CH_SLOTR_NBSLOT_Msk = 0xf00
	// Position of SLOTSZ field.
	SAI_CH_SLOTR_SLOTSZ_Pos = 0x6
	// Bit mask of SLOTSZ field.
	SAI_CH_SLOTR_SLOTSZ_Msk = 0xc0
	// The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
	SAI_CH_SLOTR_SLOTSZ_DataSize = 0x0
	// 16-bit
	SAI_CH_SLOTR_SLOTSZ_Bit16 = 0x1
	// 32-bit
	SAI_CH_SLOTR_SLOTSZ_Bit32 = 0x2
	// Position of FBOFF field.
	SAI_CH_SLOTR_FBOFF_Pos = 0x0
	// Bit mask of FBOFF field.
	SAI_CH_SLOTR_FBOFF_Msk = 0x1f

	// CH.IM: AInterrupt mask register2
	// Position of LFSDETIE field.
	SAI_CH_IM_LFSDETIE_Pos = 0x6
	// Bit mask of LFSDETIE field.
	SAI_CH_IM_LFSDETIE_Msk = 0x40
	// Bit LFSDETIE.
	SAI_CH_IM_LFSDETIE = 0x40
	// Interrupt is disabled
	SAI_CH_IM_LFSDETIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_LFSDETIE_Enabled = 0x1
	// Position of AFSDETIE field.
	SAI_CH_IM_AFSDETIE_Pos = 0x5
	// Bit mask of AFSDETIE field.
	SAI_CH_IM_AFSDETIE_Msk = 0x20
	// Bit AFSDETIE.
	SAI_CH_IM_AFSDETIE = 0x20
	// Interrupt is disabled
	SAI_CH_IM_AFSDETIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_AFSDETIE_Enabled = 0x1
	// Position of CNRDYIE field.
	SAI_CH_IM_CNRDYIE_Pos = 0x4
	// Bit mask of CNRDYIE field.
	SAI_CH_IM_CNRDYIE_Msk = 0x10
	// Bit CNRDYIE.
	SAI_CH_IM_CNRDYIE = 0x10
	// Interrupt is disabled
	SAI_CH_IM_CNRDYIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_CNRDYIE_Enabled = 0x1
	// Position of FREQIE field.
	SAI_CH_IM_FREQIE_Pos = 0x3
	// Bit mask of FREQIE field.
	SAI_CH_IM_FREQIE_Msk = 0x8
	// Bit FREQIE.
	SAI_CH_IM_FREQIE = 0x8
	// Interrupt is disabled
	SAI_CH_IM_FREQIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_FREQIE_Enabled = 0x1
	// Position of WCKCFGIE field.
	SAI_CH_IM_WCKCFGIE_Pos = 0x2
	// Bit mask of WCKCFGIE field.
	SAI_CH_IM_WCKCFGIE_Msk = 0x4
	// Bit WCKCFGIE.
	SAI_CH_IM_WCKCFGIE = 0x4
	// Interrupt is disabled
	SAI_CH_IM_WCKCFGIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_WCKCFGIE_Enabled = 0x1
	// Position of MUTEDETIE field.
	SAI_CH_IM_MUTEDETIE_Pos = 0x1
	// Bit mask of MUTEDETIE field.
	SAI_CH_IM_MUTEDETIE_Msk = 0x2
	// Bit MUTEDETIE.
	SAI_CH_IM_MUTEDETIE = 0x2
	// Interrupt is disabled
	SAI_CH_IM_MUTEDETIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_MUTEDETIE_Enabled = 0x1
	// Position of OVRUDRIE field.
	SAI_CH_IM_OVRUDRIE_Pos = 0x0
	// Bit mask of OVRUDRIE field.
	SAI_CH_IM_OVRUDRIE_Msk = 0x1
	// Bit OVRUDRIE.
	SAI_CH_IM_OVRUDRIE = 0x1
	// Interrupt is disabled
	SAI_CH_IM_OVRUDRIE_Disabled = 0x0
	// Interrupt is enabled
	SAI_CH_IM_OVRUDRIE_Enabled = 0x1

	// CH.SR: AStatus register
	// Position of FLVL field.
	SAI_CH_SR_FLVL_Pos = 0x10
	// Bit mask of FLVL field.
	SAI_CH_SR_FLVL_Msk = 0x70000
	// FIFO empty
	SAI_CH_SR_FLVL_Empty = 0x0
	// FIFO <= 1⁄4 but not empty
	SAI_CH_SR_FLVL_Quarter1 = 0x1
	// 1⁄4 < FIFO <= 1⁄2
	SAI_CH_SR_FLVL_Quarter2 = 0x2
	// 1⁄2 < FIFO <= 3⁄4
	SAI_CH_SR_FLVL_Quarter3 = 0x3
	// 3⁄4 < FIFO but not full
	SAI_CH_SR_FLVL_Quarter4 = 0x4
	// FIFO full
	SAI_CH_SR_FLVL_Full = 0x5
	// Position of LFSDET field.
	SAI_CH_SR_LFSDET_Pos = 0x6
	// Bit mask of LFSDET field.
	SAI_CH_SR_LFSDET_Msk = 0x40
	// Bit LFSDET.
	SAI_CH_SR_LFSDET = 0x40
	// No error
	SAI_CH_SR_LFSDET_NoError = 0x0
	// Frame synchronization signal is not present at the right time
	SAI_CH_SR_LFSDET_NoSync = 0x1
	// Position of AFSDET field.
	SAI_CH_SR_AFSDET_Pos = 0x5
	// Bit mask of AFSDET field.
	SAI_CH_SR_AFSDET_Msk = 0x20
	// Bit AFSDET.
	SAI_CH_SR_AFSDET = 0x20
	// No error
	SAI_CH_SR_AFSDET_NoError = 0x0
	// Frame synchronization signal is detected earlier than expected
	SAI_CH_SR_AFSDET_EarlySync = 0x1
	// Position of CNRDY field.
	SAI_CH_SR_CNRDY_Pos = 0x4
	// Bit mask of CNRDY field.
	SAI_CH_SR_CNRDY_Msk = 0x10
	// Bit CNRDY.
	SAI_CH_SR_CNRDY = 0x10
	// External AC’97 Codec is ready
	SAI_CH_SR_CNRDY_Ready = 0x0
	// External AC’97 Codec is not ready
	SAI_CH_SR_CNRDY_NotReady = 0x1
	// Position of FREQ field.
	SAI_CH_SR_FREQ_Pos = 0x3
	// Bit mask of FREQ field.
	SAI_CH_SR_FREQ_Msk = 0x8
	// Bit FREQ.
	SAI_CH_SR_FREQ = 0x8
	// No FIFO request
	SAI_CH_SR_FREQ_NoRequest = 0x0
	// FIFO request to read or to write the SAI_xDR
	SAI_CH_SR_FREQ_Request = 0x1
	// Position of WCKCFG field.
	SAI_CH_SR_WCKCFG_Pos = 0x2
	// Bit mask of WCKCFG field.
	SAI_CH_SR_WCKCFG_Msk = 0x4
	// Bit WCKCFG.
	SAI_CH_SR_WCKCFG = 0x4
	// Clock configuration is correct
	SAI_CH_SR_WCKCFG_Correct = 0x0
	// Clock configuration does not respect the rule concerning the frame length specification
	SAI_CH_SR_WCKCFG_Wrong = 0x1
	// Position of MUTEDET field.
	SAI_CH_SR_MUTEDET_Pos = 0x1
	// Bit mask of MUTEDET field.
	SAI_CH_SR_MUTEDET_Msk = 0x2
	// Bit MUTEDET.
	SAI_CH_SR_MUTEDET = 0x2
	// No MUTE detection on the SD input line
	SAI_CH_SR_MUTEDET_NoMute = 0x0
	// MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
	SAI_CH_SR_MUTEDET_Mute = 0x1
	// Position of OVRUDR field.
	SAI_CH_SR_OVRUDR_Pos = 0x0
	// Bit mask of OVRUDR field.
	SAI_CH_SR_OVRUDR_Msk = 0x1
	// Bit OVRUDR.
	SAI_CH_SR_OVRUDR = 0x1
	// No overrun/underrun error
	SAI_CH_SR_OVRUDR_NoError = 0x0
	// Overrun/underrun error detection
	SAI_CH_SR_OVRUDR_Overrun = 0x1

	// CH.CLRFR: AClear flag register
	// Position of CLFSDET field.
	SAI_CH_CLRFR_CLFSDET_Pos = 0x6
	// Bit mask of CLFSDET field.
	SAI_CH_CLRFR_CLFSDET_Msk = 0x40
	// Bit CLFSDET.
	SAI_CH_CLRFR_CLFSDET = 0x40
	// Clears the LFSDET flag
	SAI_CH_CLRFR_CLFSDET_Clear = 0x1
	// Position of CAFSDET field.
	SAI_CH_CLRFR_CAFSDET_Pos = 0x5
	// Bit mask of CAFSDET field.
	SAI_CH_CLRFR_CAFSDET_Msk = 0x20
	// Bit CAFSDET.
	SAI_CH_CLRFR_CAFSDET = 0x20
	// Clears the AFSDET flag
	SAI_CH_CLRFR_CAFSDET_Clear = 0x1
	// Position of CCNRDY field.
	SAI_CH_CLRFR_CCNRDY_Pos = 0x4
	// Bit mask of CCNRDY field.
	SAI_CH_CLRFR_CCNRDY_Msk = 0x10
	// Bit CCNRDY.
	SAI_CH_CLRFR_CCNRDY = 0x10
	// Clears the CNRDY flag
	SAI_CH_CLRFR_CCNRDY_Clear = 0x1
	// Position of CWCKCFG field.
	SAI_CH_CLRFR_CWCKCFG_Pos = 0x2
	// Bit mask of CWCKCFG field.
	SAI_CH_CLRFR_CWCKCFG_Msk = 0x4
	// Bit CWCKCFG.
	SAI_CH_CLRFR_CWCKCFG = 0x4
	// Clears the WCKCFG flag
	SAI_CH_CLRFR_CWCKCFG_Clear = 0x1
	// Position of CMUTEDET field.
	SAI_CH_CLRFR_CMUTEDET_Pos = 0x1
	// Bit mask of CMUTEDET field.
	SAI_CH_CLRFR_CMUTEDET_Msk = 0x2
	// Bit CMUTEDET.
	SAI_CH_CLRFR_CMUTEDET = 0x2
	// Clears the MUTEDET flag
	SAI_CH_CLRFR_CMUTEDET_Clear = 0x1
	// Position of COVRUDR field.
	SAI_CH_CLRFR_COVRUDR_Pos = 0x0
	// Bit mask of COVRUDR field.
	SAI_CH_CLRFR_COVRUDR_Msk = 0x1
	// Bit COVRUDR.
	SAI_CH_CLRFR_COVRUDR = 0x1
	// Clears the OVRUDR flag
	SAI_CH_CLRFR_COVRUDR_Clear = 0x1

	// CH.DR: AData register
	// Position of DATA field.
	SAI_CH_DR_DATA_Pos = 0x0
	// Bit mask of DATA field.
	SAI_CH_DR_DATA_Msk = 0xffffffff

	// PDMCR: PDM control register
	// Position of PDMEN field.
	SAI_PDMCR_PDMEN_Pos = 0x0
	// Bit mask of PDMEN field.
	SAI_PDMCR_PDMEN_Msk = 0x1
	// Bit PDMEN.
	SAI_PDMCR_PDMEN = 0x1
	// Position of MICNBR field.
	SAI_PDMCR_MICNBR_Pos = 0x4
	// Bit mask of MICNBR field.
	SAI_PDMCR_MICNBR_Msk = 0x30
	// Position of CKEN1 field.
	SAI_PDMCR_CKEN1_Pos = 0x9
	// Bit mask of CKEN1 field.
	SAI_PDMCR_CKEN1_Msk = 0x200
	// Bit CKEN1.
	SAI_PDMCR_CKEN1 = 0x200
	// Position of CKEN2 field.
	SAI_PDMCR_CKEN2_Pos = 0xa
	// Bit mask of CKEN2 field.
	SAI_PDMCR_CKEN2_Msk = 0x400
	// Bit CKEN2.
	SAI_PDMCR_CKEN2 = 0x400

	// PDMDLY: PDM delay register
	// Position of DLYM1L field.
	SAI_PDMDLY_DLYM1L_Pos = 0x8
	// Bit mask of DLYM1L field.
	SAI_PDMDLY_DLYM1L_Msk = 0x700
	// Position of DLYM2L field.
	SAI_PDMDLY_DLYM2L_Pos = 0x10
	// Bit mask of DLYM2L field.
	SAI_PDMDLY_DLYM2L_Msk = 0x70000
	// Position of DLYM3L field.
	SAI_PDMDLY_DLYM3L_Pos = 0x18
	// Bit mask of DLYM3L field.
	SAI_PDMDLY_DLYM3L_Msk = 0x7000000
	// Position of DLYM4L field.
	SAI_PDMDLY_DLYM4L_Pos = 0x20
	// Bit mask of DLYM4L field.
	SAI_PDMDLY_DLYM4L_Msk = 0x700000000
	// Position of DLYM1R field.
	SAI_PDMDLY_DLYM1R_Pos = 0xc
	// Bit mask of DLYM1R field.
	SAI_PDMDLY_DLYM1R_Msk = 0x7000
	// Position of DLYM2R field.
	SAI_PDMDLY_DLYM2R_Pos = 0x14
	// Bit mask of DLYM2R field.
	SAI_PDMDLY_DLYM2R_Msk = 0x700000
	// Position of DLYM3R field.
	SAI_PDMDLY_DLYM3R_Pos = 0x1c
	// Bit mask of DLYM3R field.
	SAI_PDMDLY_DLYM3R_Msk = 0x70000000
	// Position of DLYM4R field.
	SAI_PDMDLY_DLYM4R_Pos = 0x24
	// Bit mask of DLYM4R field.
	SAI_PDMDLY_DLYM4R_Msk = 0x7000000000
)

// Constants for SDMMC1: SDMMC1
const (
	// POWER: SDMMC power control register
	// Position of PWRCTRL field.
	SDMMC_POWER_PWRCTRL_Pos = 0x0
	// Bit mask of PWRCTRL field.
	SDMMC_POWER_PWRCTRL_Msk = 0x3
	// Position of VSWITCH field.
	SDMMC_POWER_VSWITCH_Pos = 0x2
	// Bit mask of VSWITCH field.
	SDMMC_POWER_VSWITCH_Msk = 0x4
	// Bit VSWITCH.
	SDMMC_POWER_VSWITCH = 0x4
	// Position of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN_Pos = 0x3
	// Bit mask of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN_Msk = 0x8
	// Bit VSWITCHEN.
	SDMMC_POWER_VSWITCHEN = 0x8
	// Position of DIRPOL field.
	SDMMC_POWER_DIRPOL_Pos = 0x4
	// Bit mask of DIRPOL field.
	SDMMC_POWER_DIRPOL_Msk = 0x10
	// Bit DIRPOL.
	SDMMC_POWER_DIRPOL = 0x10

	// CLKCR: The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.
	// Position of CLKDIV field.
	SDMMC_CLKCR_CLKDIV_Pos = 0x0
	// Bit mask of CLKDIV field.
	SDMMC_CLKCR_CLKDIV_Msk = 0x3ff
	// Position of PWRSAV field.
	SDMMC_CLKCR_PWRSAV_Pos = 0xc
	// Bit mask of PWRSAV field.
	SDMMC_CLKCR_PWRSAV_Msk = 0x1000
	// Bit PWRSAV.
	SDMMC_CLKCR_PWRSAV = 0x1000
	// Position of WIDBUS field.
	SDMMC_CLKCR_WIDBUS_Pos = 0xe
	// Bit mask of WIDBUS field.
	SDMMC_CLKCR_WIDBUS_Msk = 0xc000
	// Position of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE_Pos = 0x10
	// Bit mask of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE_Msk = 0x10000
	// Bit NEGEDGE.
	SDMMC_CLKCR_NEGEDGE = 0x10000
	// Position of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN_Pos = 0x11
	// Bit mask of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN_Msk = 0x20000
	// Bit HWFC_EN.
	SDMMC_CLKCR_HWFC_EN = 0x20000
	// Position of DDR field.
	SDMMC_CLKCR_DDR_Pos = 0x12
	// Bit mask of DDR field.
	SDMMC_CLKCR_DDR_Msk = 0x40000
	// Bit DDR.
	SDMMC_CLKCR_DDR = 0x40000
	// Position of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED_Pos = 0x13
	// Bit mask of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED_Msk = 0x80000
	// Bit BUSSPEED.
	SDMMC_CLKCR_BUSSPEED = 0x80000
	// Position of SELCLKRX field.
	SDMMC_CLKCR_SELCLKRX_Pos = 0x14
	// Bit mask of SELCLKRX field.
	SDMMC_CLKCR_SELCLKRX_Msk = 0x300000

	// ARGR: The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.
	// Position of CMDARG field.
	SDMMC_ARGR_CMDARG_Pos = 0x0
	// Bit mask of CMDARG field.
	SDMMC_ARGR_CMDARG_Msk = 0xffffffff

	// CMDR: The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
	// Position of CMDINDEX field.
	SDMMC_CMDR_CMDINDEX_Pos = 0x0
	// Bit mask of CMDINDEX field.
	SDMMC_CMDR_CMDINDEX_Msk = 0x3f
	// Position of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS_Pos = 0x6
	// Bit mask of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS_Msk = 0x40
	// Bit CMDTRANS.
	SDMMC_CMDR_CMDTRANS = 0x40
	// Position of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP_Pos = 0x7
	// Bit mask of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP_Msk = 0x80
	// Bit CMDSTOP.
	SDMMC_CMDR_CMDSTOP = 0x80
	// Position of WAITRESP field.
	SDMMC_CMDR_WAITRESP_Pos = 0x8
	// Bit mask of WAITRESP field.
	SDMMC_CMDR_WAITRESP_Msk = 0x300
	// Position of WAITINT field.
	SDMMC_CMDR_WAITINT_Pos = 0xa
	// Bit mask of WAITINT field.
	SDMMC_CMDR_WAITINT_Msk = 0x400
	// Bit WAITINT.
	SDMMC_CMDR_WAITINT = 0x400
	// Position of WAITPEND field.
	SDMMC_CMDR_WAITPEND_Pos = 0xb
	// Bit mask of WAITPEND field.
	SDMMC_CMDR_WAITPEND_Msk = 0x800
	// Bit WAITPEND.
	SDMMC_CMDR_WAITPEND = 0x800
	// Position of CPSMEN field.
	SDMMC_CMDR_CPSMEN_Pos = 0xc
	// Bit mask of CPSMEN field.
	SDMMC_CMDR_CPSMEN_Msk = 0x1000
	// Bit CPSMEN.
	SDMMC_CMDR_CPSMEN = 0x1000
	// Position of DTHOLD field.
	SDMMC_CMDR_DTHOLD_Pos = 0xd
	// Bit mask of DTHOLD field.
	SDMMC_CMDR_DTHOLD_Msk = 0x2000
	// Bit DTHOLD.
	SDMMC_CMDR_DTHOLD = 0x2000
	// Position of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE_Pos = 0xe
	// Bit mask of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE_Msk = 0x4000
	// Bit BOOTMODE.
	SDMMC_CMDR_BOOTMODE = 0x4000
	// Position of BOOTEN field.
	SDMMC_CMDR_BOOTEN_Pos = 0xf
	// Bit mask of BOOTEN field.
	SDMMC_CMDR_BOOTEN_Msk = 0x8000
	// Bit BOOTEN.
	SDMMC_CMDR_BOOTEN = 0x8000
	// Position of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND_Pos = 0x10
	// Bit mask of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND_Msk = 0x10000
	// Bit CMDSUSPEND.
	SDMMC_CMDR_CMDSUSPEND = 0x10000

	// RESPCMDR: SDMMC command response register
	// Position of RESPCMD field.
	SDMMC_RESPCMDR_RESPCMD_Pos = 0x0
	// Bit mask of RESPCMD field.
	SDMMC_RESPCMDR_RESPCMD_Msk = 0x3f

	// RESP1R: SDMMC response %s register
	// Position of CARDSTATUS field.
	SDMMC_RESPR_CARDSTATUS_Pos = 0x0
	// Bit mask of CARDSTATUS field.
	SDMMC_RESPR_CARDSTATUS_Msk = 0xffffffff

	// DTIMER: The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.
	// Position of DATATIME field.
	SDMMC_DTIMER_DATATIME_Pos = 0x0
	// Bit mask of DATATIME field.
	SDMMC_DTIMER_DATATIME_Msk = 0xffffffff

	// DLENR: The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.
	// Position of DATALENGTH field.
	SDMMC_DLENR_DATALENGTH_Pos = 0x0
	// Bit mask of DATALENGTH field.
	SDMMC_DLENR_DATALENGTH_Msk = 0x1ffffff

	// DCTRL: The SDMMC_DCTRL register control the data path state machine (DPSM).
	// Position of DTEN field.
	SDMMC_DCTRL_DTEN_Pos = 0x0
	// Bit mask of DTEN field.
	SDMMC_DCTRL_DTEN_Msk = 0x1
	// Bit DTEN.
	SDMMC_DCTRL_DTEN = 0x1
	// Position of DTDIR field.
	SDMMC_DCTRL_DTDIR_Pos = 0x1
	// Bit mask of DTDIR field.
	SDMMC_DCTRL_DTDIR_Msk = 0x2
	// Bit DTDIR.
	SDMMC_DCTRL_DTDIR = 0x2
	// Position of DTMODE field.
	SDMMC_DCTRL_DTMODE_Pos = 0x2
	// Bit mask of DTMODE field.
	SDMMC_DCTRL_DTMODE_Msk = 0xc
	// Position of DBLOCKSIZE field.
	SDMMC_DCTRL_DBLOCKSIZE_Pos = 0x4
	// Bit mask of DBLOCKSIZE field.
	SDMMC_DCTRL_DBLOCKSIZE_Msk = 0xf0
	// Position of RWSTART field.
	SDMMC_DCTRL_RWSTART_Pos = 0x8
	// Bit mask of RWSTART field.
	SDMMC_DCTRL_RWSTART_Msk = 0x100
	// Bit RWSTART.
	SDMMC_DCTRL_RWSTART = 0x100
	// Position of RWSTOP field.
	SDMMC_DCTRL_RWSTOP_Pos = 0x9
	// Bit mask of RWSTOP field.
	SDMMC_DCTRL_RWSTOP_Msk = 0x200
	// Bit RWSTOP.
	SDMMC_DCTRL_RWSTOP = 0x200
	// Position of RWMOD field.
	SDMMC_DCTRL_RWMOD_Pos = 0xa
	// Bit mask of RWMOD field.
	SDMMC_DCTRL_RWMOD_Msk = 0x400
	// Bit RWMOD.
	SDMMC_DCTRL_RWMOD = 0x400
	// Position of SDIOEN field.
	SDMMC_DCTRL_SDIOEN_Pos = 0xb
	// Bit mask of SDIOEN field.
	SDMMC_DCTRL_SDIOEN_Msk = 0x800
	// Bit SDIOEN.
	SDMMC_DCTRL_SDIOEN = 0x800
	// Position of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN_Pos = 0xc
	// Bit mask of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN_Msk = 0x1000
	// Bit BOOTACKEN.
	SDMMC_DCTRL_BOOTACKEN = 0x1000
	// Position of FIFORST field.
	SDMMC_DCTRL_FIFORST_Pos = 0xd
	// Bit mask of FIFORST field.
	SDMMC_DCTRL_FIFORST_Msk = 0x2000
	// Bit FIFORST.
	SDMMC_DCTRL_FIFORST = 0x2000

	// DCNTR: The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.
	// Position of DATACOUNT field.
	SDMMC_DCNTR_DATACOUNT_Pos = 0x0
	// Bit mask of DATACOUNT field.
	SDMMC_DCNTR_DATACOUNT_Msk = 0x1ffffff

	// STAR: The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)
	// Position of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL_Pos = 0x0
	// Bit mask of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL_Msk = 0x1
	// Bit CCRCFAIL.
	SDMMC_STAR_CCRCFAIL = 0x1
	// Position of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL_Pos = 0x1
	// Bit mask of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL_Msk = 0x2
	// Bit DCRCFAIL.
	SDMMC_STAR_DCRCFAIL = 0x2
	// Position of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT_Pos = 0x2
	// Bit mask of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT_Msk = 0x4
	// Bit CTIMEOUT.
	SDMMC_STAR_CTIMEOUT = 0x4
	// Position of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT_Pos = 0x3
	// Bit mask of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT_Msk = 0x8
	// Bit DTIMEOUT.
	SDMMC_STAR_DTIMEOUT = 0x8
	// Position of TXUNDERR field.
	SDMMC_STAR_TXUNDERR_Pos = 0x4
	// Bit mask of TXUNDERR field.
	SDMMC_STAR_TXUNDERR_Msk = 0x10
	// Bit TXUNDERR.
	SDMMC_STAR_TXUNDERR = 0x10
	// Position of RXOVERR field.
	SDMMC_STAR_RXOVERR_Pos = 0x5
	// Bit mask of RXOVERR field.
	SDMMC_STAR_RXOVERR_Msk = 0x20
	// Bit RXOVERR.
	SDMMC_STAR_RXOVERR = 0x20
	// Position of CMDREND field.
	SDMMC_STAR_CMDREND_Pos = 0x6
	// Bit mask of CMDREND field.
	SDMMC_STAR_CMDREND_Msk = 0x40
	// Bit CMDREND.
	SDMMC_STAR_CMDREND = 0x40
	// Position of CMDSENT field.
	SDMMC_STAR_CMDSENT_Pos = 0x7
	// Bit mask of CMDSENT field.
	SDMMC_STAR_CMDSENT_Msk = 0x80
	// Bit CMDSENT.
	SDMMC_STAR_CMDSENT = 0x80
	// Position of DATAEND field.
	SDMMC_STAR_DATAEND_Pos = 0x8
	// Bit mask of DATAEND field.
	SDMMC_STAR_DATAEND_Msk = 0x100
	// Bit DATAEND.
	SDMMC_STAR_DATAEND = 0x100
	// Position of DHOLD field.
	SDMMC_STAR_DHOLD_Pos = 0x9
	// Bit mask of DHOLD field.
	SDMMC_STAR_DHOLD_Msk = 0x200
	// Bit DHOLD.
	SDMMC_STAR_DHOLD = 0x200
	// Position of DBCKEND field.
	SDMMC_STAR_DBCKEND_Pos = 0xa
	// Bit mask of DBCKEND field.
	SDMMC_STAR_DBCKEND_Msk = 0x400
	// Bit DBCKEND.
	SDMMC_STAR_DBCKEND = 0x400
	// Position of DABORT field.
	SDMMC_STAR_DABORT_Pos = 0xb
	// Bit mask of DABORT field.
	SDMMC_STAR_DABORT_Msk = 0x800
	// Bit DABORT.
	SDMMC_STAR_DABORT = 0x800
	// Position of DPSMACT field.
	SDMMC_STAR_DPSMACT_Pos = 0xc
	// Bit mask of DPSMACT field.
	SDMMC_STAR_DPSMACT_Msk = 0x1000
	// Bit DPSMACT.
	SDMMC_STAR_DPSMACT = 0x1000
	// Position of CPSMACT field.
	SDMMC_STAR_CPSMACT_Pos = 0xd
	// Bit mask of CPSMACT field.
	SDMMC_STAR_CPSMACT_Msk = 0x2000
	// Bit CPSMACT.
	SDMMC_STAR_CPSMACT = 0x2000
	// Position of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE_Pos = 0xe
	// Bit mask of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE_Msk = 0x4000
	// Bit TXFIFOHE.
	SDMMC_STAR_TXFIFOHE = 0x4000
	// Position of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF_Pos = 0xf
	// Bit mask of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF_Msk = 0x8000
	// Bit RXFIFOHF.
	SDMMC_STAR_RXFIFOHF = 0x8000
	// Position of TXFIFOF field.
	SDMMC_STAR_TXFIFOF_Pos = 0x10
	// Bit mask of TXFIFOF field.
	SDMMC_STAR_TXFIFOF_Msk = 0x10000
	// Bit TXFIFOF.
	SDMMC_STAR_TXFIFOF = 0x10000
	// Position of RXFIFOF field.
	SDMMC_STAR_RXFIFOF_Pos = 0x11
	// Bit mask of RXFIFOF field.
	SDMMC_STAR_RXFIFOF_Msk = 0x20000
	// Bit RXFIFOF.
	SDMMC_STAR_RXFIFOF = 0x20000
	// Position of TXFIFOE field.
	SDMMC_STAR_TXFIFOE_Pos = 0x12
	// Bit mask of TXFIFOE field.
	SDMMC_STAR_TXFIFOE_Msk = 0x40000
	// Bit TXFIFOE.
	SDMMC_STAR_TXFIFOE = 0x40000
	// Position of RXFIFOE field.
	SDMMC_STAR_RXFIFOE_Pos = 0x13
	// Bit mask of RXFIFOE field.
	SDMMC_STAR_RXFIFOE_Msk = 0x80000
	// Bit RXFIFOE.
	SDMMC_STAR_RXFIFOE = 0x80000
	// Position of BUSYD0 field.
	SDMMC_STAR_BUSYD0_Pos = 0x14
	// Bit mask of BUSYD0 field.
	SDMMC_STAR_BUSYD0_Msk = 0x100000
	// Bit BUSYD0.
	SDMMC_STAR_BUSYD0 = 0x100000
	// Position of BUSYD0END field.
	SDMMC_STAR_BUSYD0END_Pos = 0x15
	// Bit mask of BUSYD0END field.
	SDMMC_STAR_BUSYD0END_Msk = 0x200000
	// Bit BUSYD0END.
	SDMMC_STAR_BUSYD0END = 0x200000
	// Position of SDIOIT field.
	SDMMC_STAR_SDIOIT_Pos = 0x16
	// Bit mask of SDIOIT field.
	SDMMC_STAR_SDIOIT_Msk = 0x400000
	// Bit SDIOIT.
	SDMMC_STAR_SDIOIT = 0x400000
	// Position of ACKFAIL field.
	SDMMC_STAR_ACKFAIL_Pos = 0x17
	// Bit mask of ACKFAIL field.
	SDMMC_STAR_ACKFAIL_Msk = 0x800000
	// Bit ACKFAIL.
	SDMMC_STAR_ACKFAIL = 0x800000
	// Position of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT_Pos = 0x18
	// Bit mask of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT_Msk = 0x1000000
	// Bit ACKTIMEOUT.
	SDMMC_STAR_ACKTIMEOUT = 0x1000000
	// Position of VSWEND field.
	SDMMC_STAR_VSWEND_Pos = 0x19
	// Bit mask of VSWEND field.
	SDMMC_STAR_VSWEND_Msk = 0x2000000
	// Bit VSWEND.
	SDMMC_STAR_VSWEND = 0x2000000
	// Position of CKSTOP field.
	SDMMC_STAR_CKSTOP_Pos = 0x1a
	// Bit mask of CKSTOP field.
	SDMMC_STAR_CKSTOP_Msk = 0x4000000
	// Bit CKSTOP.
	SDMMC_STAR_CKSTOP = 0x4000000
	// Position of IDMATE field.
	SDMMC_STAR_IDMATE_Pos = 0x1b
	// Bit mask of IDMATE field.
	SDMMC_STAR_IDMATE_Msk = 0x8000000
	// Bit IDMATE.
	SDMMC_STAR_IDMATE = 0x8000000
	// Position of IDMABTC field.
	SDMMC_STAR_IDMABTC_Pos = 0x1c
	// Bit mask of IDMABTC field.
	SDMMC_STAR_IDMABTC_Msk = 0x10000000
	// Bit IDMABTC.
	SDMMC_STAR_IDMABTC = 0x10000000

	// ICR: The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.
	// Position of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC_Pos = 0x0
	// Bit mask of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC_Msk = 0x1
	// Bit CCRCFAILC.
	SDMMC_ICR_CCRCFAILC = 0x1
	// Position of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC_Pos = 0x1
	// Bit mask of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC_Msk = 0x2
	// Bit DCRCFAILC.
	SDMMC_ICR_DCRCFAILC = 0x2
	// Position of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC_Pos = 0x2
	// Bit mask of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC_Msk = 0x4
	// Bit CTIMEOUTC.
	SDMMC_ICR_CTIMEOUTC = 0x4
	// Position of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC_Pos = 0x3
	// Bit mask of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC_Msk = 0x8
	// Bit DTIMEOUTC.
	SDMMC_ICR_DTIMEOUTC = 0x8
	// Position of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC_Pos = 0x4
	// Bit mask of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC_Msk = 0x10
	// Bit TXUNDERRC.
	SDMMC_ICR_TXUNDERRC = 0x10
	// Position of RXOVERRC field.
	SDMMC_ICR_RXOVERRC_Pos = 0x5
	// Bit mask of RXOVERRC field.
	SDMMC_ICR_RXOVERRC_Msk = 0x20
	// Bit RXOVERRC.
	SDMMC_ICR_RXOVERRC = 0x20
	// Position of CMDRENDC field.
	SDMMC_ICR_CMDRENDC_Pos = 0x6
	// Bit mask of CMDRENDC field.
	SDMMC_ICR_CMDRENDC_Msk = 0x40
	// Bit CMDRENDC.
	SDMMC_ICR_CMDRENDC = 0x40
	// Position of CMDSENTC field.
	SDMMC_ICR_CMDSENTC_Pos = 0x7
	// Bit mask of CMDSENTC field.
	SDMMC_ICR_CMDSENTC_Msk = 0x80
	// Bit CMDSENTC.
	SDMMC_ICR_CMDSENTC = 0x80
	// Position of DATAENDC field.
	SDMMC_ICR_DATAENDC_Pos = 0x8
	// Bit mask of DATAENDC field.
	SDMMC_ICR_DATAENDC_Msk = 0x100
	// Bit DATAENDC.
	SDMMC_ICR_DATAENDC = 0x100
	// Position of DHOLDC field.
	SDMMC_ICR_DHOLDC_Pos = 0x9
	// Bit mask of DHOLDC field.
	SDMMC_ICR_DHOLDC_Msk = 0x200
	// Bit DHOLDC.
	SDMMC_ICR_DHOLDC = 0x200
	// Position of DBCKENDC field.
	SDMMC_ICR_DBCKENDC_Pos = 0xa
	// Bit mask of DBCKENDC field.
	SDMMC_ICR_DBCKENDC_Msk = 0x400
	// Bit DBCKENDC.
	SDMMC_ICR_DBCKENDC = 0x400
	// Position of DABORTC field.
	SDMMC_ICR_DABORTC_Pos = 0xb
	// Bit mask of DABORTC field.
	SDMMC_ICR_DABORTC_Msk = 0x800
	// Bit DABORTC.
	SDMMC_ICR_DABORTC = 0x800
	// Position of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC_Pos = 0x15
	// Bit mask of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC_Msk = 0x200000
	// Bit BUSYD0ENDC.
	SDMMC_ICR_BUSYD0ENDC = 0x200000
	// Position of SDIOITC field.
	SDMMC_ICR_SDIOITC_Pos = 0x16
	// Bit mask of SDIOITC field.
	SDMMC_ICR_SDIOITC_Msk = 0x400000
	// Bit SDIOITC.
	SDMMC_ICR_SDIOITC = 0x400000
	// Position of ACKFAILC field.
	SDMMC_ICR_ACKFAILC_Pos = 0x17
	// Bit mask of ACKFAILC field.
	SDMMC_ICR_ACKFAILC_Msk = 0x800000
	// Bit ACKFAILC.
	SDMMC_ICR_ACKFAILC = 0x800000
	// Position of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC_Pos = 0x18
	// Bit mask of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC_Msk = 0x1000000
	// Bit ACKTIMEOUTC.
	SDMMC_ICR_ACKTIMEOUTC = 0x1000000
	// Position of VSWENDC field.
	SDMMC_ICR_VSWENDC_Pos = 0x19
	// Bit mask of VSWENDC field.
	SDMMC_ICR_VSWENDC_Msk = 0x2000000
	// Bit VSWENDC.
	SDMMC_ICR_VSWENDC = 0x2000000
	// Position of CKSTOPC field.
	SDMMC_ICR_CKSTOPC_Pos = 0x1a
	// Bit mask of CKSTOPC field.
	SDMMC_ICR_CKSTOPC_Msk = 0x4000000
	// Bit CKSTOPC.
	SDMMC_ICR_CKSTOPC = 0x4000000
	// Position of IDMATEC field.
	SDMMC_ICR_IDMATEC_Pos = 0x1b
	// Bit mask of IDMATEC field.
	SDMMC_ICR_IDMATEC_Msk = 0x8000000
	// Bit IDMATEC.
	SDMMC_ICR_IDMATEC = 0x8000000
	// Position of IDMABTCC field.
	SDMMC_ICR_IDMABTCC_Pos = 0x1c
	// Bit mask of IDMABTCC field.
	SDMMC_ICR_IDMABTCC_Msk = 0x10000000
	// Bit IDMABTCC.
	SDMMC_ICR_IDMABTCC = 0x10000000

	// MASKR: The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.
	// Position of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE_Pos = 0x0
	// Bit mask of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE_Msk = 0x1
	// Bit CCRCFAILIE.
	SDMMC_MASKR_CCRCFAILIE = 0x1
	// Position of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE_Pos = 0x1
	// Bit mask of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE_Msk = 0x2
	// Bit DCRCFAILIE.
	SDMMC_MASKR_DCRCFAILIE = 0x2
	// Position of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE_Pos = 0x2
	// Bit mask of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE_Msk = 0x4
	// Bit CTIMEOUTIE.
	SDMMC_MASKR_CTIMEOUTIE = 0x4
	// Position of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE_Pos = 0x3
	// Bit mask of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE_Msk = 0x8
	// Bit DTIMEOUTIE.
	SDMMC_MASKR_DTIMEOUTIE = 0x8
	// Position of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE_Pos = 0x4
	// Bit mask of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE_Msk = 0x10
	// Bit TXUNDERRIE.
	SDMMC_MASKR_TXUNDERRIE = 0x10
	// Position of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE_Pos = 0x5
	// Bit mask of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE_Msk = 0x20
	// Bit RXOVERRIE.
	SDMMC_MASKR_RXOVERRIE = 0x20
	// Position of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE_Pos = 0x6
	// Bit mask of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE_Msk = 0x40
	// Bit CMDRENDIE.
	SDMMC_MASKR_CMDRENDIE = 0x40
	// Position of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE_Pos = 0x7
	// Bit mask of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE_Msk = 0x80
	// Bit CMDSENTIE.
	SDMMC_MASKR_CMDSENTIE = 0x80
	// Position of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE_Pos = 0x8
	// Bit mask of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE_Msk = 0x100
	// Bit DATAENDIE.
	SDMMC_MASKR_DATAENDIE = 0x100
	// Position of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE_Pos = 0x9
	// Bit mask of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE_Msk = 0x200
	// Bit DHOLDIE.
	SDMMC_MASKR_DHOLDIE = 0x200
	// Position of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE_Pos = 0xa
	// Bit mask of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE_Msk = 0x400
	// Bit DBCKENDIE.
	SDMMC_MASKR_DBCKENDIE = 0x400
	// Position of DABORTIE field.
	SDMMC_MASKR_DABORTIE_Pos = 0xb
	// Bit mask of DABORTIE field.
	SDMMC_MASKR_DABORTIE_Msk = 0x800
	// Bit DABORTIE.
	SDMMC_MASKR_DABORTIE = 0x800
	// Position of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE_Pos = 0xe
	// Bit mask of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE_Msk = 0x4000
	// Bit TXFIFOHEIE.
	SDMMC_MASKR_TXFIFOHEIE = 0x4000
	// Position of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE_Pos = 0xf
	// Bit mask of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE_Msk = 0x8000
	// Bit RXFIFOHFIE.
	SDMMC_MASKR_RXFIFOHFIE = 0x8000
	// Position of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE_Pos = 0x11
	// Bit mask of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE_Msk = 0x20000
	// Bit RXFIFOFIE.
	SDMMC_MASKR_RXFIFOFIE = 0x20000
	// Position of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE_Pos = 0x12
	// Bit mask of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE_Msk = 0x40000
	// Bit TXFIFOEIE.
	SDMMC_MASKR_TXFIFOEIE = 0x40000
	// Position of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE_Pos = 0x15
	// Bit mask of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE_Msk = 0x200000
	// Bit BUSYD0ENDIE.
	SDMMC_MASKR_BUSYD0ENDIE = 0x200000
	// Position of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE_Pos = 0x16
	// Bit mask of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE_Msk = 0x400000
	// Bit SDIOITIE.
	SDMMC_MASKR_SDIOITIE = 0x400000
	// Position of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE_Pos = 0x17
	// Bit mask of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE_Msk = 0x800000
	// Bit ACKFAILIE.
	SDMMC_MASKR_ACKFAILIE = 0x800000
	// Position of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE_Pos = 0x18
	// Bit mask of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE_Msk = 0x1000000
	// Bit ACKTIMEOUTIE.
	SDMMC_MASKR_ACKTIMEOUTIE = 0x1000000
	// Position of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE_Pos = 0x19
	// Bit mask of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE_Msk = 0x2000000
	// Bit VSWENDIE.
	SDMMC_MASKR_VSWENDIE = 0x2000000
	// Position of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE_Pos = 0x1a
	// Bit mask of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE_Msk = 0x4000000
	// Bit CKSTOPIE.
	SDMMC_MASKR_CKSTOPIE = 0x4000000
	// Position of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE_Pos = 0x1c
	// Bit mask of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE_Msk = 0x10000000
	// Bit IDMABTCIE.
	SDMMC_MASKR_IDMABTCIE = 0x10000000

	// ACKTIMER: The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.
	// Position of ACKTIME field.
	SDMMC_ACKTIMER_ACKTIME_Pos = 0x0
	// Bit mask of ACKTIME field.
	SDMMC_ACKTIMER_ACKTIME_Msk = 0x1ffffff

	// IDMACTRLR: The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
	// Position of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN_Pos = 0x0
	// Bit mask of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN_Msk = 0x1
	// Bit IDMAEN.
	SDMMC_IDMACTRLR_IDMAEN = 0x1
	// Position of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE_Pos = 0x1
	// Bit mask of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE_Msk = 0x2
	// Bit IDMABMODE.
	SDMMC_IDMACTRLR_IDMABMODE = 0x2
	// Position of IDMABACT field.
	SDMMC_IDMACTRLR_IDMABACT_Pos = 0x2
	// Bit mask of IDMABACT field.
	SDMMC_IDMACTRLR_IDMABACT_Msk = 0x4
	// Bit IDMABACT.
	SDMMC_IDMACTRLR_IDMABACT = 0x4

	// IDMABSIZER: The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.
	// Position of IDMABNDT field.
	SDMMC_IDMABSIZER_IDMABNDT_Pos = 0x5
	// Bit mask of IDMABNDT field.
	SDMMC_IDMABSIZER_IDMABNDT_Msk = 0x1fe0

	// IDMABASE0R: The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.
	// Position of IDMABASE0 field.
	SDMMC_IDMABASE0R_IDMABASE0_Pos = 0x0
	// Bit mask of IDMABASE0 field.
	SDMMC_IDMABASE0R_IDMABASE0_Msk = 0xffffffff

	// IDMABASE1R: The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.
	// Position of IDMABASE1 field.
	SDMMC_IDMABASE1R_IDMABASE1_Pos = 0x0
	// Bit mask of IDMABASE1 field.
	SDMMC_IDMABASE1R_IDMABASE1_Msk = 0xffffffff

	// FIFOR: The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.
	// Position of FIFODATA field.
	SDMMC_FIFOR_FIFODATA_Pos = 0x0
	// Bit mask of FIFODATA field.
	SDMMC_FIFOR_FIFODATA_Msk = 0xffffffff
)

// Constants for SPI1: Serial peripheral interface
const (
	// CR1: control register 1
	// Position of BIDIMODE field.
	SPI_CR1_BIDIMODE_Pos = 0xf
	// Bit mask of BIDIMODE field.
	SPI_CR1_BIDIMODE_Msk = 0x8000
	// Bit BIDIMODE.
	SPI_CR1_BIDIMODE = 0x8000
	// 2-line unidirectional data mode selected
	SPI_CR1_BIDIMODE_Unidirectional = 0x0
	// 1-line bidirectional data mode selected
	SPI_CR1_BIDIMODE_Bidirectional = 0x1
	// Position of BIDIOE field.
	SPI_CR1_BIDIOE_Pos = 0xe
	// Bit mask of BIDIOE field.
	SPI_CR1_BIDIOE_Msk = 0x4000
	// Bit BIDIOE.
	SPI_CR1_BIDIOE = 0x4000
	// Output disabled (receive-only mode)
	SPI_CR1_BIDIOE_OutputDisabled = 0x0
	// Output enabled (transmit-only mode)
	SPI_CR1_BIDIOE_OutputEnabled = 0x1
	// Position of CRCEN field.
	SPI_CR1_CRCEN_Pos = 0xd
	// Bit mask of CRCEN field.
	SPI_CR1_CRCEN_Msk = 0x2000
	// Bit CRCEN.
	SPI_CR1_CRCEN = 0x2000
	// CRC calculation disabled
	SPI_CR1_CRCEN_Disabled = 0x0
	// CRC calculation enabled
	SPI_CR1_CRCEN_Enabled = 0x1
	// Position of CRCNEXT field.
	SPI_CR1_CRCNEXT_Pos = 0xc
	// Bit mask of CRCNEXT field.
	SPI_CR1_CRCNEXT_Msk = 0x1000
	// Bit CRCNEXT.
	SPI_CR1_CRCNEXT = 0x1000
	// Next transmit value is from Tx buffer
	SPI_CR1_CRCNEXT_TxBuffer = 0x0
	// Next transmit value is from Tx CRC register
	SPI_CR1_CRCNEXT_CRC = 0x1
	// Position of CRCL field.
	SPI_CR1_CRCL_Pos = 0xb
	// Bit mask of CRCL field.
	SPI_CR1_CRCL_Msk = 0x800
	// Bit CRCL.
	SPI_CR1_CRCL = 0x800
	// Position of RXONLY field.
	SPI_CR1_RXONLY_Pos = 0xa
	// Bit mask of RXONLY field.
	SPI_CR1_RXONLY_Msk = 0x400
	// Bit RXONLY.
	SPI_CR1_RXONLY = 0x400
	// Full duplex (Transmit and receive)
	SPI_CR1_RXONLY_FullDuplex = 0x0
	// Output disabled (Receive-only mode)
	SPI_CR1_RXONLY_OutputDisabled = 0x1
	// Position of SSM field.
	SPI_CR1_SSM_Pos = 0x9
	// Bit mask of SSM field.
	SPI_CR1_SSM_Msk = 0x200
	// Bit SSM.
	SPI_CR1_SSM = 0x200
	// Software slave management disabled
	SPI_CR1_SSM_Disabled = 0x0
	// Software slave management enabled
	SPI_CR1_SSM_Enabled = 0x1
	// Position of SSI field.
	SPI_CR1_SSI_Pos = 0x8
	// Bit mask of SSI field.
	SPI_CR1_SSI_Msk = 0x100
	// Bit SSI.
	SPI_CR1_SSI = 0x100
	// 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
	SPI_CR1_SSI_SlaveSelected = 0x0
	// 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
	SPI_CR1_SSI_SlaveNotSelected = 0x1
	// Position of LSBFIRST field.
	SPI_CR1_LSBFIRST_Pos = 0x7
	// Bit mask of LSBFIRST field.
	SPI_CR1_LSBFIRST_Msk = 0x80
	// Bit LSBFIRST.
	SPI_CR1_LSBFIRST = 0x80
	// Data is transmitted/received with the MSB first
	SPI_CR1_LSBFIRST_MSBFirst = 0x0
	// Data is transmitted/received with the LSB first
	SPI_CR1_LSBFIRST_LSBFirst = 0x1
	// Position of SPE field.
	SPI_CR1_SPE_Pos = 0x6
	// Bit mask of SPE field.
	SPI_CR1_SPE_Msk = 0x40
	// Bit SPE.
	SPI_CR1_SPE = 0x40
	// Peripheral disabled
	SPI_CR1_SPE_Disabled = 0x0
	// Peripheral enabled
	SPI_CR1_SPE_Enabled = 0x1
	// Position of BR field.
	SPI_CR1_BR_Pos = 0x3
	// Bit mask of BR field.
	SPI_CR1_BR_Msk = 0x38
	// f_PCLK / 2
	SPI_CR1_BR_Div2 = 0x0
	// f_PCLK / 4
	SPI_CR1_BR_Div4 = 0x1
	// f_PCLK / 8
	SPI_CR1_BR_Div8 = 0x2
	// f_PCLK / 16
	SPI_CR1_BR_Div16 = 0x3
	// f_PCLK / 32
	SPI_CR1_BR_Div32 = 0x4
	// f_PCLK / 64
	SPI_CR1_BR_Div64 = 0x5
	// f_PCLK / 128
	SPI_CR1_BR_Div128 = 0x6
	// f_PCLK / 256
	SPI_CR1_BR_Div256 = 0x7
	// Position of MSTR field.
	SPI_CR1_MSTR_Pos = 0x2
	// Bit mask of MSTR field.
	SPI_CR1_MSTR_Msk = 0x4
	// Bit MSTR.
	SPI_CR1_MSTR = 0x4
	// Slave configuration
	SPI_CR1_MSTR_Slave = 0x0
	// Master configuration
	SPI_CR1_MSTR_Master = 0x1
	// Position of CPOL field.
	SPI_CR1_CPOL_Pos = 0x1
	// Bit mask of CPOL field.
	SPI_CR1_CPOL_Msk = 0x2
	// Bit CPOL.
	SPI_CR1_CPOL = 0x2
	// CK to 0 when idle
	SPI_CR1_CPOL_IdleLow = 0x0
	// CK to 1 when idle
	SPI_CR1_CPOL_IdleHigh = 0x1
	// Position of CPHA field.
	SPI_CR1_CPHA_Pos = 0x0
	// Bit mask of CPHA field.
	SPI_CR1_CPHA_Msk = 0x1
	// Bit CPHA.
	SPI_CR1_CPHA = 0x1
	// The first clock transition is the first data capture edge
	SPI_CR1_CPHA_FirstEdge = 0x0
	// The second clock transition is the first data capture edge
	SPI_CR1_CPHA_SecondEdge = 0x1

	// CR2: control register 2
	// Position of RXDMAEN field.
	SPI_CR2_RXDMAEN_Pos = 0x0
	// Bit mask of RXDMAEN field.
	SPI_CR2_RXDMAEN_Msk = 0x1
	// Bit RXDMAEN.
	SPI_CR2_RXDMAEN = 0x1
	// Rx buffer DMA disabled
	SPI_CR2_RXDMAEN_Disabled = 0x0
	// Rx buffer DMA enabled
	SPI_CR2_RXDMAEN_Enabled = 0x1
	// Position of TXDMAEN field.
	SPI_CR2_TXDMAEN_Pos = 0x1
	// Bit mask of TXDMAEN field.
	SPI_CR2_TXDMAEN_Msk = 0x2
	// Bit TXDMAEN.
	SPI_CR2_TXDMAEN = 0x2
	// Tx buffer DMA disabled
	SPI_CR2_TXDMAEN_Disabled = 0x0
	// Tx buffer DMA enabled
	SPI_CR2_TXDMAEN_Enabled = 0x1
	// Position of SSOE field.
	SPI_CR2_SSOE_Pos = 0x2
	// Bit mask of SSOE field.
	SPI_CR2_SSOE_Msk = 0x4
	// Bit SSOE.
	SPI_CR2_SSOE = 0x4
	// SS output is disabled in master mode
	SPI_CR2_SSOE_Disabled = 0x0
	// SS output is enabled in master mode
	SPI_CR2_SSOE_Enabled = 0x1
	// Position of NSSP field.
	SPI_CR2_NSSP_Pos = 0x3
	// Bit mask of NSSP field.
	SPI_CR2_NSSP_Msk = 0x8
	// Bit NSSP.
	SPI_CR2_NSSP = 0x8
	// Position of FRF field.
	SPI_CR2_FRF_Pos = 0x4
	// Bit mask of FRF field.
	SPI_CR2_FRF_Msk = 0x10
	// Bit FRF.
	SPI_CR2_FRF = 0x10
	// Position of ERRIE field.
	SPI_CR2_ERRIE_Pos = 0x5
	// Bit mask of ERRIE field.
	SPI_CR2_ERRIE_Msk = 0x20
	// Bit ERRIE.
	SPI_CR2_ERRIE = 0x20
	// Error interrupt masked
	SPI_CR2_ERRIE_Masked = 0x0
	// Error interrupt not masked
	SPI_CR2_ERRIE_NotMasked = 0x1
	// Position of RXNEIE field.
	SPI_CR2_RXNEIE_Pos = 0x6
	// Bit mask of RXNEIE field.
	SPI_CR2_RXNEIE_Msk = 0x40
	// Bit RXNEIE.
	SPI_CR2_RXNEIE = 0x40
	// RXE interrupt masked
	SPI_CR2_RXNEIE_Masked = 0x0
	// RXE interrupt not masked
	SPI_CR2_RXNEIE_NotMasked = 0x1
	// Position of TXEIE field.
	SPI_CR2_TXEIE_Pos = 0x7
	// Bit mask of TXEIE field.
	SPI_CR2_TXEIE_Msk = 0x80
	// Bit TXEIE.
	SPI_CR2_TXEIE = 0x80
	// TXE interrupt masked
	SPI_CR2_TXEIE_Masked = 0x0
	// TXE interrupt not masked
	SPI_CR2_TXEIE_NotMasked = 0x1
	// Position of DS field.
	SPI_CR2_DS_Pos = 0x8
	// Bit mask of DS field.
	SPI_CR2_DS_Msk = 0xf00
	// Position of FRXTH field.
	SPI_CR2_FRXTH_Pos = 0xc
	// Bit mask of FRXTH field.
	SPI_CR2_FRXTH_Msk = 0x1000
	// Bit FRXTH.
	SPI_CR2_FRXTH = 0x1000
	// Position of LDMA_RX field.
	SPI_CR2_LDMA_RX_Pos = 0xd
	// Bit mask of LDMA_RX field.
	SPI_CR2_LDMA_RX_Msk = 0x2000
	// Bit LDMA_RX.
	SPI_CR2_LDMA_RX = 0x2000
	// Position of LDMA_TX field.
	SPI_CR2_LDMA_TX_Pos = 0xe
	// Bit mask of LDMA_TX field.
	SPI_CR2_LDMA_TX_Msk = 0x4000
	// Bit LDMA_TX.
	SPI_CR2_LDMA_TX = 0x4000

	// SR: status register
	// Position of RXNE field.
	SPI_SR_RXNE_Pos = 0x0
	// Bit mask of RXNE field.
	SPI_SR_RXNE_Msk = 0x1
	// Bit RXNE.
	SPI_SR_RXNE = 0x1
	// Rx buffer empty
	SPI_SR_RXNE_Empty = 0x0
	// Rx buffer not empty
	SPI_SR_RXNE_NotEmpty = 0x1
	// Position of TXE field.
	SPI_SR_TXE_Pos = 0x1
	// Bit mask of TXE field.
	SPI_SR_TXE_Msk = 0x2
	// Bit TXE.
	SPI_SR_TXE = 0x2
	// Tx buffer not empty
	SPI_SR_TXE_NotEmpty = 0x0
	// Tx buffer empty
	SPI_SR_TXE_Empty = 0x1
	// Position of CRCERR field.
	SPI_SR_CRCERR_Pos = 0x4
	// Bit mask of CRCERR field.
	SPI_SR_CRCERR_Msk = 0x10
	// Bit CRCERR.
	SPI_SR_CRCERR = 0x10
	// CRC value received matches the SPIx_RXCRCR value
	SPI_SR_CRCERR_Match = 0x0
	// CRC value received does not match the SPIx_RXCRCR value
	SPI_SR_CRCERR_NoMatch = 0x1
	// Clear flag
	SPI_SR_CRCERR_Clear = 0x0
	// Position of MODF field.
	SPI_SR_MODF_Pos = 0x5
	// Bit mask of MODF field.
	SPI_SR_MODF_Msk = 0x20
	// Bit MODF.
	SPI_SR_MODF = 0x20
	// No mode fault occurred
	SPI_SR_MODF_NoFault = 0x0
	// Mode fault occurred
	SPI_SR_MODF_Fault = 0x1
	// Position of OVR field.
	SPI_SR_OVR_Pos = 0x6
	// Bit mask of OVR field.
	SPI_SR_OVR_Msk = 0x40
	// Bit OVR.
	SPI_SR_OVR = 0x40
	// No overrun occurred
	SPI_SR_OVR_NoOverrun = 0x0
	// Overrun occurred
	SPI_SR_OVR_Overrun = 0x1
	// Position of BSY field.
	SPI_SR_BSY_Pos = 0x7
	// Bit mask of BSY field.
	SPI_SR_BSY_Msk = 0x80
	// Bit BSY.
	SPI_SR_BSY = 0x80
	// SPI not busy
	SPI_SR_BSY_NotBusy = 0x0
	// SPI busy
	SPI_SR_BSY_Busy = 0x1
	// Position of TIFRFE field.
	SPI_SR_TIFRFE_Pos = 0x8
	// Bit mask of TIFRFE field.
	SPI_SR_TIFRFE_Msk = 0x100
	// Bit TIFRFE.
	SPI_SR_TIFRFE = 0x100
	// Position of FRLVL field.
	SPI_SR_FRLVL_Pos = 0x9
	// Bit mask of FRLVL field.
	SPI_SR_FRLVL_Msk = 0x600
	// Position of FTLVL field.
	SPI_SR_FTLVL_Pos = 0xb
	// Bit mask of FTLVL field.
	SPI_SR_FTLVL_Msk = 0x1800

	// DR: data register
	// Position of DR field.
	SPI_DR_DR_Pos = 0x0
	// Bit mask of DR field.
	SPI_DR_DR_Msk = 0xffff

	// DR8: Direct 8-bit access to data register
	// Position of DR field.
	SPI_DR8_DR_Pos = 0x0
	// Bit mask of DR field.
	SPI_DR8_DR_Msk = 0xff

	// CRCPR: CRC polynomial register
	// Position of CRCPOLY field.
	SPI_CRCPR_CRCPOLY_Pos = 0x0
	// Bit mask of CRCPOLY field.
	SPI_CRCPR_CRCPOLY_Msk = 0xffff

	// RXCRCR: RX CRC register
	// Position of RxCRC field.
	SPI_RXCRCR_RxCRC_Pos = 0x0
	// Bit mask of RxCRC field.
	SPI_RXCRCR_RxCRC_Msk = 0xffff

	// TXCRCR: TX CRC register
	// Position of TxCRC field.
	SPI_TXCRCR_TxCRC_Pos = 0x0
	// Bit mask of TxCRC field.
	SPI_TXCRCR_TxCRC_Msk = 0xffff
)

// Constants for SYSCFG: System configuration controller
const (
	// SECCFGR: SYSCFG secure configuration register
	// Position of SRAM2SEC field.
	SYSCFG_SECCFGR_SRAM2SEC_Pos = 0x2
	// Bit mask of SRAM2SEC field.
	SYSCFG_SECCFGR_SRAM2SEC_Msk = 0x4
	// Bit SRAM2SEC.
	SYSCFG_SECCFGR_SRAM2SEC = 0x4
	// Position of CLASSBSEC field.
	SYSCFG_SECCFGR_CLASSBSEC_Pos = 0x1
	// Bit mask of CLASSBSEC field.
	SYSCFG_SECCFGR_CLASSBSEC_Msk = 0x2
	// Bit CLASSBSEC.
	SYSCFG_SECCFGR_CLASSBSEC = 0x2
	// Position of SYSCFGSEC field.
	SYSCFG_SECCFGR_SYSCFGSEC_Pos = 0x0
	// Bit mask of SYSCFGSEC field.
	SYSCFG_SECCFGR_SYSCFGSEC_Msk = 0x1
	// Bit SYSCFGSEC.
	SYSCFG_SECCFGR_SYSCFGSEC = 0x1
	// Position of FPUSEC field.
	SYSCFG_SECCFGR_FPUSEC_Pos = 0x3
	// Bit mask of FPUSEC field.
	SYSCFG_SECCFGR_FPUSEC_Msk = 0x8
	// Bit FPUSEC.
	SYSCFG_SECCFGR_FPUSEC = 0x8

	// CFGR1: configuration register 1
	// Position of I2C4_FMP field.
	SYSCFG_CFGR1_I2C4_FMP_Pos = 0x17
	// Bit mask of I2C4_FMP field.
	SYSCFG_CFGR1_I2C4_FMP_Msk = 0x800000
	// Bit I2C4_FMP.
	SYSCFG_CFGR1_I2C4_FMP = 0x800000
	// Position of I2C3_FMP field.
	SYSCFG_CFGR1_I2C3_FMP_Pos = 0x16
	// Bit mask of I2C3_FMP field.
	SYSCFG_CFGR1_I2C3_FMP_Msk = 0x400000
	// Bit I2C3_FMP.
	SYSCFG_CFGR1_I2C3_FMP = 0x400000
	// Position of I2C2_FMP field.
	SYSCFG_CFGR1_I2C2_FMP_Pos = 0x15
	// Bit mask of I2C2_FMP field.
	SYSCFG_CFGR1_I2C2_FMP_Msk = 0x200000
	// Bit I2C2_FMP.
	SYSCFG_CFGR1_I2C2_FMP = 0x200000
	// Position of I2C1_FMP field.
	SYSCFG_CFGR1_I2C1_FMP_Pos = 0x14
	// Bit mask of I2C1_FMP field.
	SYSCFG_CFGR1_I2C1_FMP_Msk = 0x100000
	// Bit I2C1_FMP.
	SYSCFG_CFGR1_I2C1_FMP = 0x100000
	// Position of I2C_PB9_FMP field.
	SYSCFG_CFGR1_I2C_PB9_FMP_Pos = 0x13
	// Bit mask of I2C_PB9_FMP field.
	SYSCFG_CFGR1_I2C_PB9_FMP_Msk = 0x80000
	// Bit I2C_PB9_FMP.
	SYSCFG_CFGR1_I2C_PB9_FMP = 0x80000
	// Position of I2C_PB8_FMP field.
	SYSCFG_CFGR1_I2C_PB8_FMP_Pos = 0x12
	// Bit mask of I2C_PB8_FMP field.
	SYSCFG_CFGR1_I2C_PB8_FMP_Msk = 0x40000
	// Bit I2C_PB8_FMP.
	SYSCFG_CFGR1_I2C_PB8_FMP = 0x40000
	// Position of I2C_PB7_FMP field.
	SYSCFG_CFGR1_I2C_PB7_FMP_Pos = 0x11
	// Bit mask of I2C_PB7_FMP field.
	SYSCFG_CFGR1_I2C_PB7_FMP_Msk = 0x20000
	// Bit I2C_PB7_FMP.
	SYSCFG_CFGR1_I2C_PB7_FMP = 0x20000
	// Position of I2C_PB6_FMP field.
	SYSCFG_CFGR1_I2C_PB6_FMP_Pos = 0x10
	// Bit mask of I2C_PB6_FMP field.
	SYSCFG_CFGR1_I2C_PB6_FMP_Msk = 0x10000
	// Bit I2C_PB6_FMP.
	SYSCFG_CFGR1_I2C_PB6_FMP = 0x10000
	// Position of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN_Pos = 0x8
	// Bit mask of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN_Msk = 0x100
	// Bit BOOSTEN.
	SYSCFG_CFGR1_BOOSTEN = 0x100
	// Position of ANASWVDD field.
	SYSCFG_CFGR1_ANASWVDD_Pos = 0x9
	// Bit mask of ANASWVDD field.
	SYSCFG_CFGR1_ANASWVDD_Msk = 0x200
	// Bit ANASWVDD.
	SYSCFG_CFGR1_ANASWVDD = 0x200

	// FPUIMR: FPU interrupt mask register
	// Position of FPU_IE field.
	SYSCFG_FPUIMR_FPU_IE_Pos = 0x0
	// Bit mask of FPU_IE field.
	SYSCFG_FPUIMR_FPU_IE_Msk = 0x3f

	// CNSLCKR: SYSCFG CPU non-secure lock register
	// Position of LOCKNSVTOR field.
	SYSCFG_CNSLCKR_LOCKNSVTOR_Pos = 0x0
	// Bit mask of LOCKNSVTOR field.
	SYSCFG_CNSLCKR_LOCKNSVTOR_Msk = 0x1
	// Bit LOCKNSVTOR.
	SYSCFG_CNSLCKR_LOCKNSVTOR = 0x1
	// Position of LOCKNSMPU field.
	SYSCFG_CNSLCKR_LOCKNSMPU_Pos = 0x1
	// Bit mask of LOCKNSMPU field.
	SYSCFG_CNSLCKR_LOCKNSMPU_Msk = 0x2
	// Bit LOCKNSMPU.
	SYSCFG_CNSLCKR_LOCKNSMPU = 0x2

	// CSLOCKR: SYSCFG CPU secure lock register
	// Position of LOCKSVTAIRCR field.
	SYSCFG_CSLOCKR_LOCKSVTAIRCR_Pos = 0x0
	// Bit mask of LOCKSVTAIRCR field.
	SYSCFG_CSLOCKR_LOCKSVTAIRCR_Msk = 0x1
	// Bit LOCKSVTAIRCR.
	SYSCFG_CSLOCKR_LOCKSVTAIRCR = 0x1
	// Position of LOCKSMPU field.
	SYSCFG_CSLOCKR_LOCKSMPU_Pos = 0x1
	// Bit mask of LOCKSMPU field.
	SYSCFG_CSLOCKR_LOCKSMPU_Msk = 0x2
	// Bit LOCKSMPU.
	SYSCFG_CSLOCKR_LOCKSMPU = 0x2
	// Position of LOCKSAU field.
	SYSCFG_CSLOCKR_LOCKSAU_Pos = 0x2
	// Bit mask of LOCKSAU field.
	SYSCFG_CSLOCKR_LOCKSAU_Msk = 0x4
	// Bit LOCKSAU.
	SYSCFG_CSLOCKR_LOCKSAU = 0x4

	// CFGR2: CFGR2
	// Position of SPF field.
	SYSCFG_CFGR2_SPF_Pos = 0x8
	// Bit mask of SPF field.
	SYSCFG_CFGR2_SPF_Msk = 0x100
	// Bit SPF.
	SYSCFG_CFGR2_SPF = 0x100
	// Position of ECCL field.
	SYSCFG_CFGR2_ECCL_Pos = 0x3
	// Bit mask of ECCL field.
	SYSCFG_CFGR2_ECCL_Msk = 0x8
	// Bit ECCL.
	SYSCFG_CFGR2_ECCL = 0x8
	// Position of PVDL field.
	SYSCFG_CFGR2_PVDL_Pos = 0x2
	// Bit mask of PVDL field.
	SYSCFG_CFGR2_PVDL_Msk = 0x4
	// Bit PVDL.
	SYSCFG_CFGR2_PVDL = 0x4
	// Position of SPL field.
	SYSCFG_CFGR2_SPL_Pos = 0x1
	// Bit mask of SPL field.
	SYSCFG_CFGR2_SPL_Msk = 0x2
	// Bit SPL.
	SYSCFG_CFGR2_SPL = 0x2
	// Position of CLL field.
	SYSCFG_CFGR2_CLL_Pos = 0x0
	// Bit mask of CLL field.
	SYSCFG_CFGR2_CLL_Msk = 0x1
	// Bit CLL.
	SYSCFG_CFGR2_CLL = 0x1

	// SCSR: SCSR
	// Position of SRAM2BSY field.
	SYSCFG_SCSR_SRAM2BSY_Pos = 0x1
	// Bit mask of SRAM2BSY field.
	SYSCFG_SCSR_SRAM2BSY_Msk = 0x2
	// Bit SRAM2BSY.
	SYSCFG_SCSR_SRAM2BSY = 0x2
	// Position of SRAM2ER field.
	SYSCFG_SCSR_SRAM2ER_Pos = 0x0
	// Bit mask of SRAM2ER field.
	SYSCFG_SCSR_SRAM2ER_Msk = 0x1
	// Bit SRAM2ER.
	SYSCFG_SCSR_SRAM2ER = 0x1

	// SKR: SKR
	// Position of KEY field.
	SYSCFG_SKR_KEY_Pos = 0x0
	// Bit mask of KEY field.
	SYSCFG_SKR_KEY_Msk = 0xff

	// SWPR: SWPR
	// Position of P31WP field.
	SYSCFG_SWPR_P31WP_Pos = 0x1f
	// Bit mask of P31WP field.
	SYSCFG_SWPR_P31WP_Msk = 0x80000000
	// Bit P31WP.
	SYSCFG_SWPR_P31WP = 0x80000000
	// Position of P30WP field.
	SYSCFG_SWPR_P30WP_Pos = 0x1e
	// Bit mask of P30WP field.
	SYSCFG_SWPR_P30WP_Msk = 0x40000000
	// Bit P30WP.
	SYSCFG_SWPR_P30WP = 0x40000000
	// Position of P29WP field.
	SYSCFG_SWPR_P29WP_Pos = 0x1d
	// Bit mask of P29WP field.
	SYSCFG_SWPR_P29WP_Msk = 0x20000000
	// Bit P29WP.
	SYSCFG_SWPR_P29WP = 0x20000000
	// Position of P28WP field.
	SYSCFG_SWPR_P28WP_Pos = 0x1c
	// Bit mask of P28WP field.
	SYSCFG_SWPR_P28WP_Msk = 0x10000000
	// Bit P28WP.
	SYSCFG_SWPR_P28WP = 0x10000000
	// Position of P27WP field.
	SYSCFG_SWPR_P27WP_Pos = 0x1b
	// Bit mask of P27WP field.
	SYSCFG_SWPR_P27WP_Msk = 0x8000000
	// Bit P27WP.
	SYSCFG_SWPR_P27WP = 0x8000000
	// Position of P26WP field.
	SYSCFG_SWPR_P26WP_Pos = 0x1a
	// Bit mask of P26WP field.
	SYSCFG_SWPR_P26WP_Msk = 0x4000000
	// Bit P26WP.
	SYSCFG_SWPR_P26WP = 0x4000000
	// Position of P25WP field.
	SYSCFG_SWPR_P25WP_Pos = 0x19
	// Bit mask of P25WP field.
	SYSCFG_SWPR_P25WP_Msk = 0x2000000
	// Bit P25WP.
	SYSCFG_SWPR_P25WP = 0x2000000
	// Position of P24WP field.
	SYSCFG_SWPR_P24WP_Pos = 0x18
	// Bit mask of P24WP field.
	SYSCFG_SWPR_P24WP_Msk = 0x1000000
	// Bit P24WP.
	SYSCFG_SWPR_P24WP = 0x1000000
	// Position of P23WP field.
	SYSCFG_SWPR_P23WP_Pos = 0x17
	// Bit mask of P23WP field.
	SYSCFG_SWPR_P23WP_Msk = 0x800000
	// Bit P23WP.
	SYSCFG_SWPR_P23WP = 0x800000
	// Position of P22WP field.
	SYSCFG_SWPR_P22WP_Pos = 0x16
	// Bit mask of P22WP field.
	SYSCFG_SWPR_P22WP_Msk = 0x400000
	// Bit P22WP.
	SYSCFG_SWPR_P22WP = 0x400000
	// Position of P21WP field.
	SYSCFG_SWPR_P21WP_Pos = 0x15
	// Bit mask of P21WP field.
	SYSCFG_SWPR_P21WP_Msk = 0x200000
	// Bit P21WP.
	SYSCFG_SWPR_P21WP = 0x200000
	// Position of P20WP field.
	SYSCFG_SWPR_P20WP_Pos = 0x14
	// Bit mask of P20WP field.
	SYSCFG_SWPR_P20WP_Msk = 0x100000
	// Bit P20WP.
	SYSCFG_SWPR_P20WP = 0x100000
	// Position of P19WP field.
	SYSCFG_SWPR_P19WP_Pos = 0x13
	// Bit mask of P19WP field.
	SYSCFG_SWPR_P19WP_Msk = 0x80000
	// Bit P19WP.
	SYSCFG_SWPR_P19WP = 0x80000
	// Position of P18WP field.
	SYSCFG_SWPR_P18WP_Pos = 0x12
	// Bit mask of P18WP field.
	SYSCFG_SWPR_P18WP_Msk = 0x40000
	// Bit P18WP.
	SYSCFG_SWPR_P18WP = 0x40000
	// Position of P17WP field.
	SYSCFG_SWPR_P17WP_Pos = 0x11
	// Bit mask of P17WP field.
	SYSCFG_SWPR_P17WP_Msk = 0x20000
	// Bit P17WP.
	SYSCFG_SWPR_P17WP = 0x20000
	// Position of P16WP field.
	SYSCFG_SWPR_P16WP_Pos = 0x10
	// Bit mask of P16WP field.
	SYSCFG_SWPR_P16WP_Msk = 0x10000
	// Bit P16WP.
	SYSCFG_SWPR_P16WP = 0x10000
	// Position of P15WP field.
	SYSCFG_SWPR_P15WP_Pos = 0xf
	// Bit mask of P15WP field.
	SYSCFG_SWPR_P15WP_Msk = 0x8000
	// Bit P15WP.
	SYSCFG_SWPR_P15WP = 0x8000
	// Position of P14WP field.
	SYSCFG_SWPR_P14WP_Pos = 0xe
	// Bit mask of P14WP field.
	SYSCFG_SWPR_P14WP_Msk = 0x4000
	// Bit P14WP.
	SYSCFG_SWPR_P14WP = 0x4000
	// Position of P13WP field.
	SYSCFG_SWPR_P13WP_Pos = 0xd
	// Bit mask of P13WP field.
	SYSCFG_SWPR_P13WP_Msk = 0x2000
	// Bit P13WP.
	SYSCFG_SWPR_P13WP = 0x2000
	// Position of P12WP field.
	SYSCFG_SWPR_P12WP_Pos = 0xc
	// Bit mask of P12WP field.
	SYSCFG_SWPR_P12WP_Msk = 0x1000
	// Bit P12WP.
	SYSCFG_SWPR_P12WP = 0x1000
	// Position of P11WP field.
	SYSCFG_SWPR_P11WP_Pos = 0xb
	// Bit mask of P11WP field.
	SYSCFG_SWPR_P11WP_Msk = 0x800
	// Bit P11WP.
	SYSCFG_SWPR_P11WP = 0x800
	// Position of P10WP field.
	SYSCFG_SWPR_P10WP_Pos = 0xa
	// Bit mask of P10WP field.
	SYSCFG_SWPR_P10WP_Msk = 0x400
	// Bit P10WP.
	SYSCFG_SWPR_P10WP = 0x400
	// Position of P9WP field.
	SYSCFG_SWPR_P9WP_Pos = 0x9
	// Bit mask of P9WP field.
	SYSCFG_SWPR_P9WP_Msk = 0x200
	// Bit P9WP.
	SYSCFG_SWPR_P9WP = 0x200
	// Position of P8WP field.
	SYSCFG_SWPR_P8WP_Pos = 0x8
	// Bit mask of P8WP field.
	SYSCFG_SWPR_P8WP_Msk = 0x100
	// Bit P8WP.
	SYSCFG_SWPR_P8WP = 0x100
	// Position of P7WP field.
	SYSCFG_SWPR_P7WP_Pos = 0x7
	// Bit mask of P7WP field.
	SYSCFG_SWPR_P7WP_Msk = 0x80
	// Bit P7WP.
	SYSCFG_SWPR_P7WP = 0x80
	// Position of P6WP field.
	SYSCFG_SWPR_P6WP_Pos = 0x6
	// Bit mask of P6WP field.
	SYSCFG_SWPR_P6WP_Msk = 0x40
	// Bit P6WP.
	SYSCFG_SWPR_P6WP = 0x40
	// Position of P5WP field.
	SYSCFG_SWPR_P5WP_Pos = 0x5
	// Bit mask of P5WP field.
	SYSCFG_SWPR_P5WP_Msk = 0x20
	// Bit P5WP.
	SYSCFG_SWPR_P5WP = 0x20
	// Position of P4WP field.
	SYSCFG_SWPR_P4WP_Pos = 0x4
	// Bit mask of P4WP field.
	SYSCFG_SWPR_P4WP_Msk = 0x10
	// Bit P4WP.
	SYSCFG_SWPR_P4WP = 0x10
	// Position of P3WP field.
	SYSCFG_SWPR_P3WP_Pos = 0x3
	// Bit mask of P3WP field.
	SYSCFG_SWPR_P3WP_Msk = 0x8
	// Bit P3WP.
	SYSCFG_SWPR_P3WP = 0x8
	// Position of P2WP field.
	SYSCFG_SWPR_P2WP_Pos = 0x2
	// Bit mask of P2WP field.
	SYSCFG_SWPR_P2WP_Msk = 0x4
	// Bit P2WP.
	SYSCFG_SWPR_P2WP = 0x4
	// Position of P1WP field.
	SYSCFG_SWPR_P1WP_Pos = 0x1
	// Bit mask of P1WP field.
	SYSCFG_SWPR_P1WP_Msk = 0x2
	// Bit P1WP.
	SYSCFG_SWPR_P1WP = 0x2
	// Position of P0WP field.
	SYSCFG_SWPR_P0WP_Pos = 0x0
	// Bit mask of P0WP field.
	SYSCFG_SWPR_P0WP_Msk = 0x1
	// Bit P0WP.
	SYSCFG_SWPR_P0WP = 0x1

	// SWPR2: SWPR2
	// Position of P32WP field.
	SYSCFG_SWPR2_P32WP_Pos = 0x0
	// Bit mask of P32WP field.
	SYSCFG_SWPR2_P32WP_Msk = 0x1
	// Bit P32WP.
	SYSCFG_SWPR2_P32WP = 0x1
	// Position of P33WP field.
	SYSCFG_SWPR2_P33WP_Pos = 0x1
	// Bit mask of P33WP field.
	SYSCFG_SWPR2_P33WP_Msk = 0x2
	// Bit P33WP.
	SYSCFG_SWPR2_P33WP = 0x2
	// Position of P34WP field.
	SYSCFG_SWPR2_P34WP_Pos = 0x2
	// Bit mask of P34WP field.
	SYSCFG_SWPR2_P34WP_Msk = 0x4
	// Bit P34WP.
	SYSCFG_SWPR2_P34WP = 0x4
	// Position of P35WP field.
	SYSCFG_SWPR2_P35WP_Pos = 0x3
	// Bit mask of P35WP field.
	SYSCFG_SWPR2_P35WP_Msk = 0x8
	// Bit P35WP.
	SYSCFG_SWPR2_P35WP = 0x8
	// Position of P36WP field.
	SYSCFG_SWPR2_P36WP_Pos = 0x4
	// Bit mask of P36WP field.
	SYSCFG_SWPR2_P36WP_Msk = 0x10
	// Bit P36WP.
	SYSCFG_SWPR2_P36WP = 0x10
	// Position of P37WP field.
	SYSCFG_SWPR2_P37WP_Pos = 0x5
	// Bit mask of P37WP field.
	SYSCFG_SWPR2_P37WP_Msk = 0x20
	// Bit P37WP.
	SYSCFG_SWPR2_P37WP = 0x20
	// Position of P38WP field.
	SYSCFG_SWPR2_P38WP_Pos = 0x6
	// Bit mask of P38WP field.
	SYSCFG_SWPR2_P38WP_Msk = 0x40
	// Bit P38WP.
	SYSCFG_SWPR2_P38WP = 0x40
	// Position of P39WP field.
	SYSCFG_SWPR2_P39WP_Pos = 0x7
	// Bit mask of P39WP field.
	SYSCFG_SWPR2_P39WP_Msk = 0x80
	// Bit P39WP.
	SYSCFG_SWPR2_P39WP = 0x80
	// Position of P40WP field.
	SYSCFG_SWPR2_P40WP_Pos = 0x8
	// Bit mask of P40WP field.
	SYSCFG_SWPR2_P40WP_Msk = 0x100
	// Bit P40WP.
	SYSCFG_SWPR2_P40WP = 0x100
	// Position of P41WP field.
	SYSCFG_SWPR2_P41WP_Pos = 0x9
	// Bit mask of P41WP field.
	SYSCFG_SWPR2_P41WP_Msk = 0x200
	// Bit P41WP.
	SYSCFG_SWPR2_P41WP = 0x200
	// Position of P42WP field.
	SYSCFG_SWPR2_P42WP_Pos = 0xa
	// Bit mask of P42WP field.
	SYSCFG_SWPR2_P42WP_Msk = 0x400
	// Bit P42WP.
	SYSCFG_SWPR2_P42WP = 0x400
	// Position of P43WP field.
	SYSCFG_SWPR2_P43WP_Pos = 0xb
	// Bit mask of P43WP field.
	SYSCFG_SWPR2_P43WP_Msk = 0x800
	// Bit P43WP.
	SYSCFG_SWPR2_P43WP = 0x800
	// Position of P44WP field.
	SYSCFG_SWPR2_P44WP_Pos = 0xc
	// Bit mask of P44WP field.
	SYSCFG_SWPR2_P44WP_Msk = 0x1000
	// Bit P44WP.
	SYSCFG_SWPR2_P44WP = 0x1000
	// Position of P45WP field.
	SYSCFG_SWPR2_P45WP_Pos = 0xd
	// Bit mask of P45WP field.
	SYSCFG_SWPR2_P45WP_Msk = 0x2000
	// Bit P45WP.
	SYSCFG_SWPR2_P45WP = 0x2000
	// Position of P46WP field.
	SYSCFG_SWPR2_P46WP_Pos = 0xe
	// Bit mask of P46WP field.
	SYSCFG_SWPR2_P46WP_Msk = 0x4000
	// Bit P46WP.
	SYSCFG_SWPR2_P46WP = 0x4000
	// Position of P47WP field.
	SYSCFG_SWPR2_P47WP_Pos = 0xf
	// Bit mask of P47WP field.
	SYSCFG_SWPR2_P47WP_Msk = 0x8000
	// Bit P47WP.
	SYSCFG_SWPR2_P47WP = 0x8000
	// Position of P48WP field.
	SYSCFG_SWPR2_P48WP_Pos = 0x10
	// Bit mask of P48WP field.
	SYSCFG_SWPR2_P48WP_Msk = 0x10000
	// Bit P48WP.
	SYSCFG_SWPR2_P48WP = 0x10000
	// Position of P49WP field.
	SYSCFG_SWPR2_P49WP_Pos = 0x11
	// Bit mask of P49WP field.
	SYSCFG_SWPR2_P49WP_Msk = 0x20000
	// Bit P49WP.
	SYSCFG_SWPR2_P49WP = 0x20000
	// Position of P50WP field.
	SYSCFG_SWPR2_P50WP_Pos = 0x12
	// Bit mask of P50WP field.
	SYSCFG_SWPR2_P50WP_Msk = 0x40000
	// Bit P50WP.
	SYSCFG_SWPR2_P50WP = 0x40000
	// Position of P51WP field.
	SYSCFG_SWPR2_P51WP_Pos = 0x13
	// Bit mask of P51WP field.
	SYSCFG_SWPR2_P51WP_Msk = 0x80000
	// Bit P51WP.
	SYSCFG_SWPR2_P51WP = 0x80000
	// Position of P52WP field.
	SYSCFG_SWPR2_P52WP_Pos = 0x14
	// Bit mask of P52WP field.
	SYSCFG_SWPR2_P52WP_Msk = 0x100000
	// Bit P52WP.
	SYSCFG_SWPR2_P52WP = 0x100000
	// Position of P53WP field.
	SYSCFG_SWPR2_P53WP_Pos = 0x15
	// Bit mask of P53WP field.
	SYSCFG_SWPR2_P53WP_Msk = 0x200000
	// Bit P53WP.
	SYSCFG_SWPR2_P53WP = 0x200000
	// Position of P54WP field.
	SYSCFG_SWPR2_P54WP_Pos = 0x16
	// Bit mask of P54WP field.
	SYSCFG_SWPR2_P54WP_Msk = 0x400000
	// Bit P54WP.
	SYSCFG_SWPR2_P54WP = 0x400000
	// Position of P55WP field.
	SYSCFG_SWPR2_P55WP_Pos = 0x17
	// Bit mask of P55WP field.
	SYSCFG_SWPR2_P55WP_Msk = 0x800000
	// Bit P55WP.
	SYSCFG_SWPR2_P55WP = 0x800000
	// Position of P56WP field.
	SYSCFG_SWPR2_P56WP_Pos = 0x18
	// Bit mask of P56WP field.
	SYSCFG_SWPR2_P56WP_Msk = 0x1000000
	// Bit P56WP.
	SYSCFG_SWPR2_P56WP = 0x1000000
	// Position of P57WP field.
	SYSCFG_SWPR2_P57WP_Pos = 0x19
	// Bit mask of P57WP field.
	SYSCFG_SWPR2_P57WP_Msk = 0x2000000
	// Bit P57WP.
	SYSCFG_SWPR2_P57WP = 0x2000000
	// Position of P58WP field.
	SYSCFG_SWPR2_P58WP_Pos = 0x1a
	// Bit mask of P58WP field.
	SYSCFG_SWPR2_P58WP_Msk = 0x4000000
	// Bit P58WP.
	SYSCFG_SWPR2_P58WP = 0x4000000
	// Position of P59WP field.
	SYSCFG_SWPR2_P59WP_Pos = 0x1b
	// Bit mask of P59WP field.
	SYSCFG_SWPR2_P59WP_Msk = 0x8000000
	// Bit P59WP.
	SYSCFG_SWPR2_P59WP = 0x8000000
	// Position of P60WP field.
	SYSCFG_SWPR2_P60WP_Pos = 0x1c
	// Bit mask of P60WP field.
	SYSCFG_SWPR2_P60WP_Msk = 0x10000000
	// Bit P60WP.
	SYSCFG_SWPR2_P60WP = 0x10000000
	// Position of P61WP field.
	SYSCFG_SWPR2_P61WP_Pos = 0x1d
	// Bit mask of P61WP field.
	SYSCFG_SWPR2_P61WP_Msk = 0x20000000
	// Bit P61WP.
	SYSCFG_SWPR2_P61WP = 0x20000000
	// Position of P62WP field.
	SYSCFG_SWPR2_P62WP_Pos = 0x1e
	// Bit mask of P62WP field.
	SYSCFG_SWPR2_P62WP_Msk = 0x40000000
	// Bit P62WP.
	SYSCFG_SWPR2_P62WP = 0x40000000
	// Position of P63WP field.
	SYSCFG_SWPR2_P63WP_Pos = 0x1f
	// Bit mask of P63WP field.
	SYSCFG_SWPR2_P63WP_Msk = 0x80000000
	// Bit P63WP.
	SYSCFG_SWPR2_P63WP = 0x80000000

	// RSSCMDR: RSSCMDR
	// Position of RSSCMD field.
	SYSCFG_RSSCMDR_RSSCMD_Pos = 0x0
	// Bit mask of RSSCMD field.
	SYSCFG_RSSCMDR_RSSCMD_Msk = 0xff
)

// Constants for TAMP: Tamper and backup registers
const (
	// CR1: control register 1
	// Position of TAMP1E field.
	TAMP_CR1_TAMP1E_Pos = 0x0
	// Bit mask of TAMP1E field.
	TAMP_CR1_TAMP1E_Msk = 0x1
	// Bit TAMP1E.
	TAMP_CR1_TAMP1E = 0x1
	// Position of TAMP2E field.
	TAMP_CR1_TAMP2E_Pos = 0x1
	// Bit mask of TAMP2E field.
	TAMP_CR1_TAMP2E_Msk = 0x2
	// Bit TAMP2E.
	TAMP_CR1_TAMP2E = 0x2
	// Position of TAMP3E field.
	TAMP_CR1_TAMP3E_Pos = 0x2
	// Bit mask of TAMP3E field.
	TAMP_CR1_TAMP3E_Msk = 0x4
	// Bit TAMP3E.
	TAMP_CR1_TAMP3E = 0x4
	// Position of TAMP4E field.
	TAMP_CR1_TAMP4E_Pos = 0x3
	// Bit mask of TAMP4E field.
	TAMP_CR1_TAMP4E_Msk = 0x8
	// Bit TAMP4E.
	TAMP_CR1_TAMP4E = 0x8
	// Position of TAMP5E field.
	TAMP_CR1_TAMP5E_Pos = 0x4
	// Bit mask of TAMP5E field.
	TAMP_CR1_TAMP5E_Msk = 0x10
	// Bit TAMP5E.
	TAMP_CR1_TAMP5E = 0x10
	// Position of TAMP6E field.
	TAMP_CR1_TAMP6E_Pos = 0x5
	// Bit mask of TAMP6E field.
	TAMP_CR1_TAMP6E_Msk = 0x20
	// Bit TAMP6E.
	TAMP_CR1_TAMP6E = 0x20
	// Position of TAMP7E field.
	TAMP_CR1_TAMP7E_Pos = 0x6
	// Bit mask of TAMP7E field.
	TAMP_CR1_TAMP7E_Msk = 0x40
	// Bit TAMP7E.
	TAMP_CR1_TAMP7E = 0x40
	// Position of TAMP8E field.
	TAMP_CR1_TAMP8E_Pos = 0x7
	// Bit mask of TAMP8E field.
	TAMP_CR1_TAMP8E_Msk = 0x80
	// Bit TAMP8E.
	TAMP_CR1_TAMP8E = 0x80
	// Position of ITAMP1E field.
	TAMP_CR1_ITAMP1E_Pos = 0x10
	// Bit mask of ITAMP1E field.
	TAMP_CR1_ITAMP1E_Msk = 0x10000
	// Bit ITAMP1E.
	TAMP_CR1_ITAMP1E = 0x10000
	// Position of ITAMP2E field.
	TAMP_CR1_ITAMP2E_Pos = 0x11
	// Bit mask of ITAMP2E field.
	TAMP_CR1_ITAMP2E_Msk = 0x20000
	// Bit ITAMP2E.
	TAMP_CR1_ITAMP2E = 0x20000
	// Position of ITAMP3E field.
	TAMP_CR1_ITAMP3E_Pos = 0x12
	// Bit mask of ITAMP3E field.
	TAMP_CR1_ITAMP3E_Msk = 0x40000
	// Bit ITAMP3E.
	TAMP_CR1_ITAMP3E = 0x40000
	// Position of ITAMP5E field.
	TAMP_CR1_ITAMP5E_Pos = 0x14
	// Bit mask of ITAMP5E field.
	TAMP_CR1_ITAMP5E_Msk = 0x100000
	// Bit ITAMP5E.
	TAMP_CR1_ITAMP5E = 0x100000
	// Position of ITAMP8E field.
	TAMP_CR1_ITAMP8E_Pos = 0x17
	// Bit mask of ITAMP8E field.
	TAMP_CR1_ITAMP8E_Msk = 0x800000
	// Bit ITAMP8E.
	TAMP_CR1_ITAMP8E = 0x800000

	// CR2: control register 2
	// Position of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER_Pos = 0x0
	// Bit mask of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER_Msk = 0x1
	// Bit TAMP1NOER.
	TAMP_CR2_TAMP1NOER = 0x1
	// Position of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER_Pos = 0x1
	// Bit mask of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER_Msk = 0x2
	// Bit TAMP2NOER.
	TAMP_CR2_TAMP2NOER = 0x2
	// Position of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER_Pos = 0x2
	// Bit mask of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER_Msk = 0x4
	// Bit TAMP3NOER.
	TAMP_CR2_TAMP3NOER = 0x4
	// Position of TAMP4NOER field.
	TAMP_CR2_TAMP4NOER_Pos = 0x3
	// Bit mask of TAMP4NOER field.
	TAMP_CR2_TAMP4NOER_Msk = 0x8
	// Bit TAMP4NOER.
	TAMP_CR2_TAMP4NOER = 0x8
	// Position of TAMP5NOER field.
	TAMP_CR2_TAMP5NOER_Pos = 0x4
	// Bit mask of TAMP5NOER field.
	TAMP_CR2_TAMP5NOER_Msk = 0x10
	// Bit TAMP5NOER.
	TAMP_CR2_TAMP5NOER = 0x10
	// Position of TAMP6NOER field.
	TAMP_CR2_TAMP6NOER_Pos = 0x5
	// Bit mask of TAMP6NOER field.
	TAMP_CR2_TAMP6NOER_Msk = 0x20
	// Bit TAMP6NOER.
	TAMP_CR2_TAMP6NOER = 0x20
	// Position of TAMP7NOER field.
	TAMP_CR2_TAMP7NOER_Pos = 0x6
	// Bit mask of TAMP7NOER field.
	TAMP_CR2_TAMP7NOER_Msk = 0x40
	// Bit TAMP7NOER.
	TAMP_CR2_TAMP7NOER = 0x40
	// Position of TAMP8NOER field.
	TAMP_CR2_TAMP8NOER_Pos = 0x7
	// Bit mask of TAMP8NOER field.
	TAMP_CR2_TAMP8NOER_Msk = 0x80
	// Bit TAMP8NOER.
	TAMP_CR2_TAMP8NOER = 0x80
	// Position of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK_Pos = 0x10
	// Bit mask of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK_Msk = 0x10000
	// Bit TAMP1MSK.
	TAMP_CR2_TAMP1MSK = 0x10000
	// Position of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK_Pos = 0x11
	// Bit mask of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK_Msk = 0x20000
	// Bit TAMP2MSK.
	TAMP_CR2_TAMP2MSK = 0x20000
	// Position of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK_Pos = 0x12
	// Bit mask of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK_Msk = 0x40000
	// Bit TAMP3MSK.
	TAMP_CR2_TAMP3MSK = 0x40000
	// Position of BKERASE field.
	TAMP_CR2_BKERASE_Pos = 0x17
	// Bit mask of BKERASE field.
	TAMP_CR2_BKERASE_Msk = 0x800000
	// Bit BKERASE.
	TAMP_CR2_BKERASE = 0x800000
	// Position of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG_Pos = 0x18
	// Bit mask of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG_Msk = 0x1000000
	// Bit TAMP1TRG.
	TAMP_CR2_TAMP1TRG = 0x1000000
	// Position of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG_Pos = 0x19
	// Bit mask of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG_Msk = 0x2000000
	// Bit TAMP2TRG.
	TAMP_CR2_TAMP2TRG = 0x2000000
	// Position of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG_Pos = 0x1a
	// Bit mask of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG_Msk = 0x4000000
	// Bit TAMP3TRG.
	TAMP_CR2_TAMP3TRG = 0x4000000
	// Position of TAMP4TRG field.
	TAMP_CR2_TAMP4TRG_Pos = 0x1b
	// Bit mask of TAMP4TRG field.
	TAMP_CR2_TAMP4TRG_Msk = 0x8000000
	// Bit TAMP4TRG.
	TAMP_CR2_TAMP4TRG = 0x8000000
	// Position of TAMP5TRG field.
	TAMP_CR2_TAMP5TRG_Pos = 0x1c
	// Bit mask of TAMP5TRG field.
	TAMP_CR2_TAMP5TRG_Msk = 0x10000000
	// Bit TAMP5TRG.
	TAMP_CR2_TAMP5TRG = 0x10000000
	// Position of TAMP6TRG field.
	TAMP_CR2_TAMP6TRG_Pos = 0x1d
	// Bit mask of TAMP6TRG field.
	TAMP_CR2_TAMP6TRG_Msk = 0x20000000
	// Bit TAMP6TRG.
	TAMP_CR2_TAMP6TRG = 0x20000000
	// Position of TAMP7TRG field.
	TAMP_CR2_TAMP7TRG_Pos = 0x1e
	// Bit mask of TAMP7TRG field.
	TAMP_CR2_TAMP7TRG_Msk = 0x40000000
	// Bit TAMP7TRG.
	TAMP_CR2_TAMP7TRG = 0x40000000
	// Position of TAMP8TRG field.
	TAMP_CR2_TAMP8TRG_Pos = 0x1f
	// Bit mask of TAMP8TRG field.
	TAMP_CR2_TAMP8TRG_Msk = 0x80000000
	// Bit TAMP8TRG.
	TAMP_CR2_TAMP8TRG = 0x80000000

	// CR3: control register 3
	// Position of ITAMP1NOER field.
	TAMP_CR3_ITAMP1NOER_Pos = 0x0
	// Bit mask of ITAMP1NOER field.
	TAMP_CR3_ITAMP1NOER_Msk = 0x1
	// Bit ITAMP1NOER.
	TAMP_CR3_ITAMP1NOER = 0x1
	// Position of ITAMP2NOER field.
	TAMP_CR3_ITAMP2NOER_Pos = 0x1
	// Bit mask of ITAMP2NOER field.
	TAMP_CR3_ITAMP2NOER_Msk = 0x2
	// Bit ITAMP2NOER.
	TAMP_CR3_ITAMP2NOER = 0x2
	// Position of ITAMP3NOER field.
	TAMP_CR3_ITAMP3NOER_Pos = 0x2
	// Bit mask of ITAMP3NOER field.
	TAMP_CR3_ITAMP3NOER_Msk = 0x4
	// Bit ITAMP3NOER.
	TAMP_CR3_ITAMP3NOER = 0x4
	// Position of ITAMP5NOER field.
	TAMP_CR3_ITAMP5NOER_Pos = 0x4
	// Bit mask of ITAMP5NOER field.
	TAMP_CR3_ITAMP5NOER_Msk = 0x10
	// Bit ITAMP5NOER.
	TAMP_CR3_ITAMP5NOER = 0x10
	// Position of ITAMP8NOER field.
	TAMP_CR3_ITAMP8NOER_Pos = 0x7
	// Bit mask of ITAMP8NOER field.
	TAMP_CR3_ITAMP8NOER_Msk = 0x80
	// Bit ITAMP8NOER.
	TAMP_CR3_ITAMP8NOER = 0x80

	// FLTCR: TAMP filter control register
	// Position of TAMPFREQ field.
	TAMP_FLTCR_TAMPFREQ_Pos = 0x0
	// Bit mask of TAMPFREQ field.
	TAMP_FLTCR_TAMPFREQ_Msk = 0x7
	// Position of TAMPFLT field.
	TAMP_FLTCR_TAMPFLT_Pos = 0x3
	// Bit mask of TAMPFLT field.
	TAMP_FLTCR_TAMPFLT_Msk = 0x18
	// Position of TAMPPRCH field.
	TAMP_FLTCR_TAMPPRCH_Pos = 0x5
	// Bit mask of TAMPPRCH field.
	TAMP_FLTCR_TAMPPRCH_Msk = 0x60
	// Position of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS_Pos = 0x7
	// Bit mask of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS_Msk = 0x80
	// Bit TAMPPUDIS.
	TAMP_FLTCR_TAMPPUDIS = 0x80

	// ATCR1: TAMP active tamper control register 1
	// Position of TAMP1AM field.
	TAMP_ATCR1_TAMP1AM_Pos = 0x0
	// Bit mask of TAMP1AM field.
	TAMP_ATCR1_TAMP1AM_Msk = 0x1
	// Bit TAMP1AM.
	TAMP_ATCR1_TAMP1AM = 0x1
	// Position of TAMP2AM field.
	TAMP_ATCR1_TAMP2AM_Pos = 0x1
	// Bit mask of TAMP2AM field.
	TAMP_ATCR1_TAMP2AM_Msk = 0x2
	// Bit TAMP2AM.
	TAMP_ATCR1_TAMP2AM = 0x2
	// Position of TAMP3AM field.
	TAMP_ATCR1_TAMP3AM_Pos = 0x2
	// Bit mask of TAMP3AM field.
	TAMP_ATCR1_TAMP3AM_Msk = 0x4
	// Bit TAMP3AM.
	TAMP_ATCR1_TAMP3AM = 0x4
	// Position of TAMP4AM field.
	TAMP_ATCR1_TAMP4AM_Pos = 0x3
	// Bit mask of TAMP4AM field.
	TAMP_ATCR1_TAMP4AM_Msk = 0x8
	// Bit TAMP4AM.
	TAMP_ATCR1_TAMP4AM = 0x8
	// Position of TAMP5AM field.
	TAMP_ATCR1_TAMP5AM_Pos = 0x4
	// Bit mask of TAMP5AM field.
	TAMP_ATCR1_TAMP5AM_Msk = 0x10
	// Bit TAMP5AM.
	TAMP_ATCR1_TAMP5AM = 0x10
	// Position of TAMP6AM field.
	TAMP_ATCR1_TAMP6AM_Pos = 0x5
	// Bit mask of TAMP6AM field.
	TAMP_ATCR1_TAMP6AM_Msk = 0x20
	// Bit TAMP6AM.
	TAMP_ATCR1_TAMP6AM = 0x20
	// Position of TAMP7AM field.
	TAMP_ATCR1_TAMP7AM_Pos = 0x6
	// Bit mask of TAMP7AM field.
	TAMP_ATCR1_TAMP7AM_Msk = 0x40
	// Bit TAMP7AM.
	TAMP_ATCR1_TAMP7AM = 0x40
	// Position of TAMP8AM field.
	TAMP_ATCR1_TAMP8AM_Pos = 0x7
	// Bit mask of TAMP8AM field.
	TAMP_ATCR1_TAMP8AM_Msk = 0x80
	// Bit TAMP8AM.
	TAMP_ATCR1_TAMP8AM = 0x80
	// Position of ATOSEL1 field.
	TAMP_ATCR1_ATOSEL1_Pos = 0x8
	// Bit mask of ATOSEL1 field.
	TAMP_ATCR1_ATOSEL1_Msk = 0x300
	// Position of ATOSEL2 field.
	TAMP_ATCR1_ATOSEL2_Pos = 0xa
	// Bit mask of ATOSEL2 field.
	TAMP_ATCR1_ATOSEL2_Msk = 0xc00
	// Position of ATOSEL3 field.
	TAMP_ATCR1_ATOSEL3_Pos = 0xc
	// Bit mask of ATOSEL3 field.
	TAMP_ATCR1_ATOSEL3_Msk = 0x3000
	// Position of ATOSEL4 field.
	TAMP_ATCR1_ATOSEL4_Pos = 0xe
	// Bit mask of ATOSEL4 field.
	TAMP_ATCR1_ATOSEL4_Msk = 0xc000
	// Position of ATCKSEL field.
	TAMP_ATCR1_ATCKSEL_Pos = 0x10
	// Bit mask of ATCKSEL field.
	TAMP_ATCR1_ATCKSEL_Msk = 0x30000
	// Position of ATPER field.
	TAMP_ATCR1_ATPER_Pos = 0x18
	// Bit mask of ATPER field.
	TAMP_ATCR1_ATPER_Msk = 0x3000000
	// Position of ATOSHARE field.
	TAMP_ATCR1_ATOSHARE_Pos = 0x1e
	// Bit mask of ATOSHARE field.
	TAMP_ATCR1_ATOSHARE_Msk = 0x40000000
	// Bit ATOSHARE.
	TAMP_ATCR1_ATOSHARE = 0x40000000
	// Position of FLTEN field.
	TAMP_ATCR1_FLTEN_Pos = 0x1f
	// Bit mask of FLTEN field.
	TAMP_ATCR1_FLTEN_Msk = 0x80000000
	// Bit FLTEN.
	TAMP_ATCR1_FLTEN = 0x80000000

	// ATSEEDR: TAMP active tamper seed register
	// Position of SEED field.
	TAMP_ATSEEDR_SEED_Pos = 0x0
	// Bit mask of SEED field.
	TAMP_ATSEEDR_SEED_Msk = 0xffffffff

	// ATOR: TAMP active tamper output register
	// Position of PRNG field.
	TAMP_ATOR_PRNG_Pos = 0x0
	// Bit mask of PRNG field.
	TAMP_ATOR_PRNG_Msk = 0xff
	// Position of SEEDF field.
	TAMP_ATOR_SEEDF_Pos = 0xe
	// Bit mask of SEEDF field.
	TAMP_ATOR_SEEDF_Msk = 0x4000
	// Bit SEEDF.
	TAMP_ATOR_SEEDF = 0x4000
	// Position of INITS field.
	TAMP_ATOR_INITS_Pos = 0xf
	// Bit mask of INITS field.
	TAMP_ATOR_INITS_Msk = 0x8000
	// Bit INITS.
	TAMP_ATOR_INITS = 0x8000

	// ATCR2: TAMP active tamper control register 2
	// Position of ATOSEL1 field.
	TAMP_ATCR2_ATOSEL1_Pos = 0x8
	// Bit mask of ATOSEL1 field.
	TAMP_ATCR2_ATOSEL1_Msk = 0x700
	// Position of ATOSEL2 field.
	TAMP_ATCR2_ATOSEL2_Pos = 0xb
	// Bit mask of ATOSEL2 field.
	TAMP_ATCR2_ATOSEL2_Msk = 0x3800
	// Position of ATOSEL3 field.
	TAMP_ATCR2_ATOSEL3_Pos = 0xe
	// Bit mask of ATOSEL3 field.
	TAMP_ATCR2_ATOSEL3_Msk = 0x1c000
	// Position of ATOSEL4 field.
	TAMP_ATCR2_ATOSEL4_Pos = 0x11
	// Bit mask of ATOSEL4 field.
	TAMP_ATCR2_ATOSEL4_Msk = 0xe0000
	// Position of ATOSEL5 field.
	TAMP_ATCR2_ATOSEL5_Pos = 0x14
	// Bit mask of ATOSEL5 field.
	TAMP_ATCR2_ATOSEL5_Msk = 0x700000
	// Position of ATOSEL6 field.
	TAMP_ATCR2_ATOSEL6_Pos = 0x17
	// Bit mask of ATOSEL6 field.
	TAMP_ATCR2_ATOSEL6_Msk = 0x3800000
	// Position of ATOSEL7 field.
	TAMP_ATCR2_ATOSEL7_Pos = 0x1a
	// Bit mask of ATOSEL7 field.
	TAMP_ATCR2_ATOSEL7_Msk = 0x1c000000
	// Position of ATOSEL8 field.
	TAMP_ATCR2_ATOSEL8_Pos = 0x1d
	// Bit mask of ATOSEL8 field.
	TAMP_ATCR2_ATOSEL8_Msk = 0xe0000000

	// SMCR: TAMP secure mode register
	// Position of BKPRWDPROT field.
	TAMP_SMCR_BKPRWDPROT_Pos = 0x0
	// Bit mask of BKPRWDPROT field.
	TAMP_SMCR_BKPRWDPROT_Msk = 0xff
	// Position of BKPWDPROT field.
	TAMP_SMCR_BKPWDPROT_Pos = 0x10
	// Bit mask of BKPWDPROT field.
	TAMP_SMCR_BKPWDPROT_Msk = 0xff0000
	// Position of TAMPDPROT field.
	TAMP_SMCR_TAMPDPROT_Pos = 0x1f
	// Bit mask of TAMPDPROT field.
	TAMP_SMCR_TAMPDPROT_Msk = 0x80000000
	// Bit TAMPDPROT.
	TAMP_SMCR_TAMPDPROT = 0x80000000

	// PRIVCR: TAMP privilege mode control register
	// Position of BKPRWPRIV field.
	TAMP_PRIVCR_BKPRWPRIV_Pos = 0x1d
	// Bit mask of BKPRWPRIV field.
	TAMP_PRIVCR_BKPRWPRIV_Msk = 0x20000000
	// Bit BKPRWPRIV.
	TAMP_PRIVCR_BKPRWPRIV = 0x20000000
	// Position of BKPWPRIV field.
	TAMP_PRIVCR_BKPWPRIV_Pos = 0x1e
	// Bit mask of BKPWPRIV field.
	TAMP_PRIVCR_BKPWPRIV_Msk = 0x40000000
	// Bit BKPWPRIV.
	TAMP_PRIVCR_BKPWPRIV = 0x40000000
	// Position of TAMPPRIV field.
	TAMP_PRIVCR_TAMPPRIV_Pos = 0x1f
	// Bit mask of TAMPPRIV field.
	TAMP_PRIVCR_TAMPPRIV_Msk = 0x80000000
	// Bit TAMPPRIV.
	TAMP_PRIVCR_TAMPPRIV = 0x80000000

	// IER: TAMP interrupt enable register
	// Position of TAMP1IE field.
	TAMP_IER_TAMP1IE_Pos = 0x0
	// Bit mask of TAMP1IE field.
	TAMP_IER_TAMP1IE_Msk = 0x1
	// Bit TAMP1IE.
	TAMP_IER_TAMP1IE = 0x1
	// Position of TAMP2IE field.
	TAMP_IER_TAMP2IE_Pos = 0x1
	// Bit mask of TAMP2IE field.
	TAMP_IER_TAMP2IE_Msk = 0x2
	// Bit TAMP2IE.
	TAMP_IER_TAMP2IE = 0x2
	// Position of TAMP3IE field.
	TAMP_IER_TAMP3IE_Pos = 0x2
	// Bit mask of TAMP3IE field.
	TAMP_IER_TAMP3IE_Msk = 0x4
	// Bit TAMP3IE.
	TAMP_IER_TAMP3IE = 0x4
	// Position of TAMP4IE field.
	TAMP_IER_TAMP4IE_Pos = 0x3
	// Bit mask of TAMP4IE field.
	TAMP_IER_TAMP4IE_Msk = 0x8
	// Bit TAMP4IE.
	TAMP_IER_TAMP4IE = 0x8
	// Position of TAMP5IE field.
	TAMP_IER_TAMP5IE_Pos = 0x4
	// Bit mask of TAMP5IE field.
	TAMP_IER_TAMP5IE_Msk = 0x10
	// Bit TAMP5IE.
	TAMP_IER_TAMP5IE = 0x10
	// Position of TAMP6IE field.
	TAMP_IER_TAMP6IE_Pos = 0x5
	// Bit mask of TAMP6IE field.
	TAMP_IER_TAMP6IE_Msk = 0x20
	// Bit TAMP6IE.
	TAMP_IER_TAMP6IE = 0x20
	// Position of TAMP7IE field.
	TAMP_IER_TAMP7IE_Pos = 0x6
	// Bit mask of TAMP7IE field.
	TAMP_IER_TAMP7IE_Msk = 0x40
	// Bit TAMP7IE.
	TAMP_IER_TAMP7IE = 0x40
	// Position of TAMP8IE field.
	TAMP_IER_TAMP8IE_Pos = 0x7
	// Bit mask of TAMP8IE field.
	TAMP_IER_TAMP8IE_Msk = 0x80
	// Bit TAMP8IE.
	TAMP_IER_TAMP8IE = 0x80
	// Position of ITAMP1IE field.
	TAMP_IER_ITAMP1IE_Pos = 0x10
	// Bit mask of ITAMP1IE field.
	TAMP_IER_ITAMP1IE_Msk = 0x10000
	// Bit ITAMP1IE.
	TAMP_IER_ITAMP1IE = 0x10000
	// Position of ITAMP2IE field.
	TAMP_IER_ITAMP2IE_Pos = 0x11
	// Bit mask of ITAMP2IE field.
	TAMP_IER_ITAMP2IE_Msk = 0x20000
	// Bit ITAMP2IE.
	TAMP_IER_ITAMP2IE = 0x20000
	// Position of ITAMP3IE field.
	TAMP_IER_ITAMP3IE_Pos = 0x12
	// Bit mask of ITAMP3IE field.
	TAMP_IER_ITAMP3IE_Msk = 0x40000
	// Bit ITAMP3IE.
	TAMP_IER_ITAMP3IE = 0x40000
	// Position of ITAMP5IE field.
	TAMP_IER_ITAMP5IE_Pos = 0x14
	// Bit mask of ITAMP5IE field.
	TAMP_IER_ITAMP5IE_Msk = 0x100000
	// Bit ITAMP5IE.
	TAMP_IER_ITAMP5IE = 0x100000
	// Position of ITAMP8IE field.
	TAMP_IER_ITAMP8IE_Pos = 0x17
	// Bit mask of ITAMP8IE field.
	TAMP_IER_ITAMP8IE_Msk = 0x800000
	// Bit ITAMP8IE.
	TAMP_IER_ITAMP8IE = 0x800000

	// SR: TAMP status register
	// Position of TAMP1F field.
	TAMP_SR_TAMP1F_Pos = 0x0
	// Bit mask of TAMP1F field.
	TAMP_SR_TAMP1F_Msk = 0x1
	// Bit TAMP1F.
	TAMP_SR_TAMP1F = 0x1
	// Position of TAMP2F field.
	TAMP_SR_TAMP2F_Pos = 0x1
	// Bit mask of TAMP2F field.
	TAMP_SR_TAMP2F_Msk = 0x2
	// Bit TAMP2F.
	TAMP_SR_TAMP2F = 0x2
	// Position of TAMP3F field.
	TAMP_SR_TAMP3F_Pos = 0x2
	// Bit mask of TAMP3F field.
	TAMP_SR_TAMP3F_Msk = 0x4
	// Bit TAMP3F.
	TAMP_SR_TAMP3F = 0x4
	// Position of TAMP4F field.
	TAMP_SR_TAMP4F_Pos = 0x3
	// Bit mask of TAMP4F field.
	TAMP_SR_TAMP4F_Msk = 0x8
	// Bit TAMP4F.
	TAMP_SR_TAMP4F = 0x8
	// Position of TAMP5F field.
	TAMP_SR_TAMP5F_Pos = 0x4
	// Bit mask of TAMP5F field.
	TAMP_SR_TAMP5F_Msk = 0x10
	// Bit TAMP5F.
	TAMP_SR_TAMP5F = 0x10
	// Position of TAMP6F field.
	TAMP_SR_TAMP6F_Pos = 0x5
	// Bit mask of TAMP6F field.
	TAMP_SR_TAMP6F_Msk = 0x20
	// Bit TAMP6F.
	TAMP_SR_TAMP6F = 0x20
	// Position of TAMP7F field.
	TAMP_SR_TAMP7F_Pos = 0x6
	// Bit mask of TAMP7F field.
	TAMP_SR_TAMP7F_Msk = 0x40
	// Bit TAMP7F.
	TAMP_SR_TAMP7F = 0x40
	// Position of TAMP8F field.
	TAMP_SR_TAMP8F_Pos = 0x7
	// Bit mask of TAMP8F field.
	TAMP_SR_TAMP8F_Msk = 0x80
	// Bit TAMP8F.
	TAMP_SR_TAMP8F = 0x80
	// Position of ITAMP1F field.
	TAMP_SR_ITAMP1F_Pos = 0x10
	// Bit mask of ITAMP1F field.
	TAMP_SR_ITAMP1F_Msk = 0x10000
	// Bit ITAMP1F.
	TAMP_SR_ITAMP1F = 0x10000
	// Position of ITAMP2F field.
	TAMP_SR_ITAMP2F_Pos = 0x11
	// Bit mask of ITAMP2F field.
	TAMP_SR_ITAMP2F_Msk = 0x20000
	// Bit ITAMP2F.
	TAMP_SR_ITAMP2F = 0x20000
	// Position of ITAMP3F field.
	TAMP_SR_ITAMP3F_Pos = 0x12
	// Bit mask of ITAMP3F field.
	TAMP_SR_ITAMP3F_Msk = 0x40000
	// Bit ITAMP3F.
	TAMP_SR_ITAMP3F = 0x40000
	// Position of ITAMP5F field.
	TAMP_SR_ITAMP5F_Pos = 0x14
	// Bit mask of ITAMP5F field.
	TAMP_SR_ITAMP5F_Msk = 0x100000
	// Bit ITAMP5F.
	TAMP_SR_ITAMP5F = 0x100000
	// Position of ITAMP8F field.
	TAMP_SR_ITAMP8F_Pos = 0x17
	// Bit mask of ITAMP8F field.
	TAMP_SR_ITAMP8F_Msk = 0x800000
	// Bit ITAMP8F.
	TAMP_SR_ITAMP8F = 0x800000

	// MISR: TAMP masked interrupt status register
	// Position of TAMP1MF field.
	TAMP_MISR_TAMP1MF_Pos = 0x0
	// Bit mask of TAMP1MF field.
	TAMP_MISR_TAMP1MF_Msk = 0x1
	// Bit TAMP1MF.
	TAMP_MISR_TAMP1MF = 0x1
	// Position of TAMP2MF field.
	TAMP_MISR_TAMP2MF_Pos = 0x1
	// Bit mask of TAMP2MF field.
	TAMP_MISR_TAMP2MF_Msk = 0x2
	// Bit TAMP2MF.
	TAMP_MISR_TAMP2MF = 0x2
	// Position of TAMP3MF field.
	TAMP_MISR_TAMP3MF_Pos = 0x2
	// Bit mask of TAMP3MF field.
	TAMP_MISR_TAMP3MF_Msk = 0x4
	// Bit TAMP3MF.
	TAMP_MISR_TAMP3MF = 0x4
	// Position of TAMP4MF field.
	TAMP_MISR_TAMP4MF_Pos = 0x3
	// Bit mask of TAMP4MF field.
	TAMP_MISR_TAMP4MF_Msk = 0x8
	// Bit TAMP4MF.
	TAMP_MISR_TAMP4MF = 0x8
	// Position of TAMP5MF field.
	TAMP_MISR_TAMP5MF_Pos = 0x4
	// Bit mask of TAMP5MF field.
	TAMP_MISR_TAMP5MF_Msk = 0x10
	// Bit TAMP5MF.
	TAMP_MISR_TAMP5MF = 0x10
	// Position of TAMP6MF field.
	TAMP_MISR_TAMP6MF_Pos = 0x5
	// Bit mask of TAMP6MF field.
	TAMP_MISR_TAMP6MF_Msk = 0x20
	// Bit TAMP6MF.
	TAMP_MISR_TAMP6MF = 0x20
	// Position of TAMP7MF field.
	TAMP_MISR_TAMP7MF_Pos = 0x6
	// Bit mask of TAMP7MF field.
	TAMP_MISR_TAMP7MF_Msk = 0x40
	// Bit TAMP7MF.
	TAMP_MISR_TAMP7MF = 0x40
	// Position of TAMP8MF field.
	TAMP_MISR_TAMP8MF_Pos = 0x7
	// Bit mask of TAMP8MF field.
	TAMP_MISR_TAMP8MF_Msk = 0x80
	// Bit TAMP8MF.
	TAMP_MISR_TAMP8MF = 0x80
	// Position of ITAMP1MF field.
	TAMP_MISR_ITAMP1MF_Pos = 0x10
	// Bit mask of ITAMP1MF field.
	TAMP_MISR_ITAMP1MF_Msk = 0x10000
	// Bit ITAMP1MF.
	TAMP_MISR_ITAMP1MF = 0x10000
	// Position of ITAMP2MF field.
	TAMP_MISR_ITAMP2MF_Pos = 0x11
	// Bit mask of ITAMP2MF field.
	TAMP_MISR_ITAMP2MF_Msk = 0x20000
	// Bit ITAMP2MF.
	TAMP_MISR_ITAMP2MF = 0x20000
	// Position of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF_Pos = 0x12
	// Bit mask of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF_Msk = 0x40000
	// Bit ITAMP3MF.
	TAMP_MISR_ITAMP3MF = 0x40000
	// Position of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF_Pos = 0x14
	// Bit mask of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF_Msk = 0x100000
	// Bit ITAMP5MF.
	TAMP_MISR_ITAMP5MF = 0x100000
	// Position of ITAMP8MF field.
	TAMP_MISR_ITAMP8MF_Pos = 0x17
	// Bit mask of ITAMP8MF field.
	TAMP_MISR_ITAMP8MF_Msk = 0x800000
	// Bit ITAMP8MF.
	TAMP_MISR_ITAMP8MF = 0x800000

	// SMISR: TAMP secure masked interrupt status register
	// Position of TAMP1MF field.
	TAMP_SMISR_TAMP1MF_Pos = 0x0
	// Bit mask of TAMP1MF field.
	TAMP_SMISR_TAMP1MF_Msk = 0x1
	// Bit TAMP1MF.
	TAMP_SMISR_TAMP1MF = 0x1
	// Position of TAMP2MF field.
	TAMP_SMISR_TAMP2MF_Pos = 0x1
	// Bit mask of TAMP2MF field.
	TAMP_SMISR_TAMP2MF_Msk = 0x2
	// Bit TAMP2MF.
	TAMP_SMISR_TAMP2MF = 0x2
	// Position of TAMP3MF field.
	TAMP_SMISR_TAMP3MF_Pos = 0x2
	// Bit mask of TAMP3MF field.
	TAMP_SMISR_TAMP3MF_Msk = 0x4
	// Bit TAMP3MF.
	TAMP_SMISR_TAMP3MF = 0x4
	// Position of TAMP4MF field.
	TAMP_SMISR_TAMP4MF_Pos = 0x3
	// Bit mask of TAMP4MF field.
	TAMP_SMISR_TAMP4MF_Msk = 0x8
	// Bit TAMP4MF.
	TAMP_SMISR_TAMP4MF = 0x8
	// Position of TAMP5MF field.
	TAMP_SMISR_TAMP5MF_Pos = 0x4
	// Bit mask of TAMP5MF field.
	TAMP_SMISR_TAMP5MF_Msk = 0x10
	// Bit TAMP5MF.
	TAMP_SMISR_TAMP5MF = 0x10
	// Position of TAMP6MF field.
	TAMP_SMISR_TAMP6MF_Pos = 0x5
	// Bit mask of TAMP6MF field.
	TAMP_SMISR_TAMP6MF_Msk = 0x20
	// Bit TAMP6MF.
	TAMP_SMISR_TAMP6MF = 0x20
	// Position of TAMP7MF field.
	TAMP_SMISR_TAMP7MF_Pos = 0x6
	// Bit mask of TAMP7MF field.
	TAMP_SMISR_TAMP7MF_Msk = 0x40
	// Bit TAMP7MF.
	TAMP_SMISR_TAMP7MF = 0x40
	// Position of TAMP8MF field.
	TAMP_SMISR_TAMP8MF_Pos = 0x7
	// Bit mask of TAMP8MF field.
	TAMP_SMISR_TAMP8MF_Msk = 0x80
	// Bit TAMP8MF.
	TAMP_SMISR_TAMP8MF = 0x80
	// Position of ITAMP1MF field.
	TAMP_SMISR_ITAMP1MF_Pos = 0x10
	// Bit mask of ITAMP1MF field.
	TAMP_SMISR_ITAMP1MF_Msk = 0x10000
	// Bit ITAMP1MF.
	TAMP_SMISR_ITAMP1MF = 0x10000
	// Position of ITAMP2MF field.
	TAMP_SMISR_ITAMP2MF_Pos = 0x11
	// Bit mask of ITAMP2MF field.
	TAMP_SMISR_ITAMP2MF_Msk = 0x20000
	// Bit ITAMP2MF.
	TAMP_SMISR_ITAMP2MF = 0x20000
	// Position of ITAMP3MF field.
	TAMP_SMISR_ITAMP3MF_Pos = 0x12
	// Bit mask of ITAMP3MF field.
	TAMP_SMISR_ITAMP3MF_Msk = 0x40000
	// Bit ITAMP3MF.
	TAMP_SMISR_ITAMP3MF = 0x40000
	// Position of ITAMP5MF field.
	TAMP_SMISR_ITAMP5MF_Pos = 0x14
	// Bit mask of ITAMP5MF field.
	TAMP_SMISR_ITAMP5MF_Msk = 0x100000
	// Bit ITAMP5MF.
	TAMP_SMISR_ITAMP5MF = 0x100000
	// Position of ITAMP8MF field.
	TAMP_SMISR_ITAMP8MF_Pos = 0x17
	// Bit mask of ITAMP8MF field.
	TAMP_SMISR_ITAMP8MF_Msk = 0x800000
	// Bit ITAMP8MF.
	TAMP_SMISR_ITAMP8MF = 0x800000

	// SCR: TAMP status clear register
	// Position of CTAMP1F field.
	TAMP_SCR_CTAMP1F_Pos = 0x0
	// Bit mask of CTAMP1F field.
	TAMP_SCR_CTAMP1F_Msk = 0x1
	// Bit CTAMP1F.
	TAMP_SCR_CTAMP1F = 0x1
	// Position of CTAMP2F field.
	TAMP_SCR_CTAMP2F_Pos = 0x1
	// Bit mask of CTAMP2F field.
	TAMP_SCR_CTAMP2F_Msk = 0x2
	// Bit CTAMP2F.
	TAMP_SCR_CTAMP2F = 0x2
	// Position of CTAMP3F field.
	TAMP_SCR_CTAMP3F_Pos = 0x2
	// Bit mask of CTAMP3F field.
	TAMP_SCR_CTAMP3F_Msk = 0x4
	// Bit CTAMP3F.
	TAMP_SCR_CTAMP3F = 0x4
	// Position of CTAMP4F field.
	TAMP_SCR_CTAMP4F_Pos = 0x3
	// Bit mask of CTAMP4F field.
	TAMP_SCR_CTAMP4F_Msk = 0x8
	// Bit CTAMP4F.
	TAMP_SCR_CTAMP4F = 0x8
	// Position of CTAMP5F field.
	TAMP_SCR_CTAMP5F_Pos = 0x4
	// Bit mask of CTAMP5F field.
	TAMP_SCR_CTAMP5F_Msk = 0x10
	// Bit CTAMP5F.
	TAMP_SCR_CTAMP5F = 0x10
	// Position of CTAMP6F field.
	TAMP_SCR_CTAMP6F_Pos = 0x5
	// Bit mask of CTAMP6F field.
	TAMP_SCR_CTAMP6F_Msk = 0x20
	// Bit CTAMP6F.
	TAMP_SCR_CTAMP6F = 0x20
	// Position of CTAMP7F field.
	TAMP_SCR_CTAMP7F_Pos = 0x6
	// Bit mask of CTAMP7F field.
	TAMP_SCR_CTAMP7F_Msk = 0x40
	// Bit CTAMP7F.
	TAMP_SCR_CTAMP7F = 0x40
	// Position of CTAMP8F field.
	TAMP_SCR_CTAMP8F_Pos = 0x7
	// Bit mask of CTAMP8F field.
	TAMP_SCR_CTAMP8F_Msk = 0x80
	// Bit CTAMP8F.
	TAMP_SCR_CTAMP8F = 0x80
	// Position of CITAMP1F field.
	TAMP_SCR_CITAMP1F_Pos = 0x10
	// Bit mask of CITAMP1F field.
	TAMP_SCR_CITAMP1F_Msk = 0x10000
	// Bit CITAMP1F.
	TAMP_SCR_CITAMP1F = 0x10000
	// Position of CITAMP2F field.
	TAMP_SCR_CITAMP2F_Pos = 0x11
	// Bit mask of CITAMP2F field.
	TAMP_SCR_CITAMP2F_Msk = 0x20000
	// Bit CITAMP2F.
	TAMP_SCR_CITAMP2F = 0x20000
	// Position of CITAMP3F field.
	TAMP_SCR_CITAMP3F_Pos = 0x12
	// Bit mask of CITAMP3F field.
	TAMP_SCR_CITAMP3F_Msk = 0x40000
	// Bit CITAMP3F.
	TAMP_SCR_CITAMP3F = 0x40000
	// Position of CITAMP5F field.
	TAMP_SCR_CITAMP5F_Pos = 0x14
	// Bit mask of CITAMP5F field.
	TAMP_SCR_CITAMP5F_Msk = 0x100000
	// Bit CITAMP5F.
	TAMP_SCR_CITAMP5F = 0x100000
	// Position of CITAMP8F field.
	TAMP_SCR_CITAMP8F_Pos = 0x17
	// Bit mask of CITAMP8F field.
	TAMP_SCR_CITAMP8F_Msk = 0x800000
	// Bit CITAMP8F.
	TAMP_SCR_CITAMP8F = 0x800000

	// COUNTR: TAMP monotonic counter register
	// Position of COUNT field.
	TAMP_COUNTR_COUNT_Pos = 0x0
	// Bit mask of COUNT field.
	TAMP_COUNTR_COUNT_Msk = 0xffffffff

	// CFGR: TAMP configuration register
	// Position of TMONEN field.
	TAMP_CFGR_TMONEN_Pos = 0x1
	// Bit mask of TMONEN field.
	TAMP_CFGR_TMONEN_Msk = 0x2
	// Bit TMONEN.
	TAMP_CFGR_TMONEN = 0x2
	// Position of VMONEN field.
	TAMP_CFGR_VMONEN_Pos = 0x2
	// Bit mask of VMONEN field.
	TAMP_CFGR_VMONEN_Msk = 0x4
	// Bit VMONEN.
	TAMP_CFGR_VMONEN = 0x4
	// Position of WUTMONEN field.
	TAMP_CFGR_WUTMONEN_Pos = 0x3
	// Bit mask of WUTMONEN field.
	TAMP_CFGR_WUTMONEN_Msk = 0x8
	// Bit WUTMONEN.
	TAMP_CFGR_WUTMONEN = 0x8

	// BKP0R: TAMP backup register
	// Position of BKP field.
	TAMP_BKPR_BKP_Pos = 0x0
	// Bit mask of BKP field.
	TAMP_BKPR_BKP_Msk = 0xffffffff
)

// Constants for TIM1: Advanced-timers
const (
	// CR1: control register 1
	// Position of CKD field.
	TIM_CR1_CKD_Pos = 0x8
	// Bit mask of CKD field.
	TIM_CR1_CKD_Msk = 0x300
	// t_DTS = t_CK_INT
	TIM_CR1_CKD_Div1 = 0x0
	// t_DTS = 2 × t_CK_INT
	TIM_CR1_CKD_Div2 = 0x1
	// t_DTS = 4 × t_CK_INT
	TIM_CR1_CKD_Div4 = 0x2
	// Position of ARPE field.
	TIM_CR1_ARPE_Pos = 0x7
	// Bit mask of ARPE field.
	TIM_CR1_ARPE_Msk = 0x80
	// Bit ARPE.
	TIM_CR1_ARPE = 0x80
	// TIMx_APRR register is not buffered
	TIM_CR1_ARPE_Disabled = 0x0
	// TIMx_APRR register is buffered
	TIM_CR1_ARPE_Enabled = 0x1
	// Position of CMS field.
	TIM_CR1_CMS_Pos = 0x5
	// Bit mask of CMS field.
	TIM_CR1_CMS_Msk = 0x60
	// The counter counts up or down depending on the direction bit
	TIM_CR1_CMS_EdgeAligned = 0x0
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
	TIM_CR1_CMS_CenterAligned1 = 0x1
	// The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
	TIM_CR1_CMS_CenterAligned2 = 0x2
	// The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
	TIM_CR1_CMS_CenterAligned3 = 0x3
	// Position of DIR field.
	TIM_CR1_DIR_Pos = 0x4
	// Bit mask of DIR field.
	TIM_CR1_DIR_Msk = 0x10
	// Bit DIR.
	TIM_CR1_DIR = 0x10
	// Counter used as upcounter
	TIM_CR1_DIR_Up = 0x0
	// Counter used as downcounter
	TIM_CR1_DIR_Down = 0x1
	// Position of OPM field.
	TIM_CR1_OPM_Pos = 0x3
	// Bit mask of OPM field.
	TIM_CR1_OPM_Msk = 0x8
	// Bit OPM.
	TIM_CR1_OPM = 0x8
	// Counter is not stopped at update event
	TIM_CR1_OPM_Disabled = 0x0
	// Counter stops counting at the next update event (clearing the CEN bit)
	TIM_CR1_OPM_Enabled = 0x1
	// Position of URS field.
	TIM_CR1_URS_Pos = 0x2
	// Bit mask of URS field.
	TIM_CR1_URS_Msk = 0x4
	// Bit URS.
	TIM_CR1_URS = 0x4
	// Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
	TIM_CR1_URS_AnyEvent = 0x0
	// Only counter overflow/underflow generates an update interrupt or DMA request
	TIM_CR1_URS_CounterOnly = 0x1
	// Position of UDIS field.
	TIM_CR1_UDIS_Pos = 0x1
	// Bit mask of UDIS field.
	TIM_CR1_UDIS_Msk = 0x2
	// Bit UDIS.
	TIM_CR1_UDIS = 0x2
	// Update event enabled
	TIM_CR1_UDIS_Enabled = 0x0
	// Update event disabled
	TIM_CR1_UDIS_Disabled = 0x1
	// Position of CEN field.
	TIM_CR1_CEN_Pos = 0x0
	// Bit mask of CEN field.
	TIM_CR1_CEN_Msk = 0x1
	// Bit CEN.
	TIM_CR1_CEN = 0x1
	// Counter disabled
	TIM_CR1_CEN_Disabled = 0x0
	// Counter enabled
	TIM_CR1_CEN_Enabled = 0x1
	// Position of UIFREMAP field.
	TIM_CR1_UIFREMAP_Pos = 0xb
	// Bit mask of UIFREMAP field.
	TIM_CR1_UIFREMAP_Msk = 0x800
	// Bit UIFREMAP.
	TIM_CR1_UIFREMAP = 0x800

	// CR2: control register 2
	// Position of OIS1 field.
	TIM_CR2_OIS1_Pos = 0xa
	// Bit mask of OIS1 field.
	TIM_CR2_OIS1_Msk = 0x400
	// Bit OIS1.
	TIM_CR2_OIS1 = 0x400
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS1_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS1_Set = 0x1
	// Position of OIS2 field.
	TIM_CR2_OIS2_Pos = 0xc
	// Bit mask of OIS2 field.
	TIM_CR2_OIS2_Msk = 0x1000
	// Bit OIS2.
	TIM_CR2_OIS2 = 0x1000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS2_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS2_Set = 0x1
	// Position of OIS3 field.
	TIM_CR2_OIS3_Pos = 0xe
	// Bit mask of OIS3 field.
	TIM_CR2_OIS3_Msk = 0x4000
	// Bit OIS3.
	TIM_CR2_OIS3 = 0x4000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS3_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS3_Set = 0x1
	// Position of OIS4 field.
	TIM_CR2_OIS4_Pos = 0x10
	// Bit mask of OIS4 field.
	TIM_CR2_OIS4_Msk = 0x10000
	// Bit OIS4.
	TIM_CR2_OIS4 = 0x10000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS4_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS4_Set = 0x1
	// Position of OIS5 field.
	TIM_CR2_OIS5_Pos = 0x12
	// Bit mask of OIS5 field.
	TIM_CR2_OIS5_Msk = 0x40000
	// Bit OIS5.
	TIM_CR2_OIS5 = 0x40000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS5_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS5_Set = 0x1
	// Position of OIS6 field.
	TIM_CR2_OIS6_Pos = 0x14
	// Bit mask of OIS6 field.
	TIM_CR2_OIS6_Msk = 0x100000
	// Bit OIS6.
	TIM_CR2_OIS6 = 0x100000
	// OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS6_Reset = 0x0
	// OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
	TIM_CR2_OIS6_Set = 0x1
	// Position of OIS1N field.
	TIM_CR2_OIS1N_Pos = 0xb
	// Bit mask of OIS1N field.
	TIM_CR2_OIS1N_Msk = 0x800
	// Bit OIS1N.
	TIM_CR2_OIS1N = 0x800
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS1N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS1N_Set = 0x1
	// Position of OIS2N field.
	TIM_CR2_OIS2N_Pos = 0xd
	// Bit mask of OIS2N field.
	TIM_CR2_OIS2N_Msk = 0x2000
	// Bit OIS2N.
	TIM_CR2_OIS2N = 0x2000
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS2N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS2N_Set = 0x1
	// Position of OIS3N field.
	TIM_CR2_OIS3N_Pos = 0xf
	// Bit mask of OIS3N field.
	TIM_CR2_OIS3N_Msk = 0x8000
	// Bit OIS3N.
	TIM_CR2_OIS3N = 0x8000
	// OCxN=0 after a dead-time when MOE=0
	TIM_CR2_OIS3N_Reset = 0x0
	// OCxN=1 after a dead-time when MOE=0
	TIM_CR2_OIS3N_Set = 0x1
	// Position of TI1S field.
	TIM_CR2_TI1S_Pos = 0x7
	// Bit mask of TI1S field.
	TIM_CR2_TI1S_Msk = 0x80
	// Bit TI1S.
	TIM_CR2_TI1S = 0x80
	// The TIMx_CH1 pin is connected to TI1 input
	TIM_CR2_TI1S_Normal = 0x0
	// The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
	TIM_CR2_TI1S_XOR = 0x1
	// Position of MMS field.
	TIM_CR2_MMS_Pos = 0x4
	// Bit mask of MMS field.
	TIM_CR2_MMS_Msk = 0x70
	// Position of CCDS field.
	TIM_CR2_CCDS_Pos = 0x3
	// Bit mask of CCDS field.
	TIM_CR2_CCDS_Msk = 0x8
	// Bit CCDS.
	TIM_CR2_CCDS = 0x8
	// CCx DMA request sent when CCx event occurs
	TIM_CR2_CCDS_OnCompare = 0x0
	// CCx DMA request sent when update event occurs
	TIM_CR2_CCDS_OnUpdate = 0x1
	// Position of CCUS field.
	TIM_CR2_CCUS_Pos = 0x2
	// Bit mask of CCUS field.
	TIM_CR2_CCUS_Msk = 0x4
	// Bit CCUS.
	TIM_CR2_CCUS = 0x4
	// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
	TIM_CR2_CCUS_Sw = 0x0
	// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
	TIM_CR2_CCUS_SwOrEdge = 0x1
	// Position of CCPC field.
	TIM_CR2_CCPC_Pos = 0x0
	// Bit mask of CCPC field.
	TIM_CR2_CCPC_Msk = 0x1
	// Bit CCPC.
	TIM_CR2_CCPC = 0x1
	// CCxE, CCxNE and OCxM bits are not preloaded
	TIM_CR2_CCPC_NotPreloaded = 0x0
	// CCxE, CCxNE and OCxM bits are preloaded
	TIM_CR2_CCPC_Preloaded = 0x1
	// Position of MMS2 field.
	TIM_CR2_MMS2_Pos = 0x14
	// Bit mask of MMS2 field.
	TIM_CR2_MMS2_Msk = 0xf00000

	// SMCR: slave mode control register
	// Position of ETP field.
	TIM_SMCR_ETP_Pos = 0xf
	// Bit mask of ETP field.
	TIM_SMCR_ETP_Msk = 0x8000
	// Bit ETP.
	TIM_SMCR_ETP = 0x8000
	// ETR is noninverted, active at high level or rising edge
	TIM_SMCR_ETP_NotInverted = 0x0
	// ETR is inverted, active at low level or falling edge
	TIM_SMCR_ETP_Inverted = 0x1
	// Position of ECE field.
	TIM_SMCR_ECE_Pos = 0xe
	// Bit mask of ECE field.
	TIM_SMCR_ECE_Msk = 0x4000
	// Bit ECE.
	TIM_SMCR_ECE = 0x4000
	// External clock mode 2 disabled
	TIM_SMCR_ECE_Disabled = 0x0
	// External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
	TIM_SMCR_ECE_Enabled = 0x1
	// Position of ETPS field.
	TIM_SMCR_ETPS_Pos = 0xc
	// Bit mask of ETPS field.
	TIM_SMCR_ETPS_Msk = 0x3000
	// Prescaler OFF
	TIM_SMCR_ETPS_Div1 = 0x0
	// ETRP frequency divided by 2
	TIM_SMCR_ETPS_Div2 = 0x1
	// ETRP frequency divided by 4
	TIM_SMCR_ETPS_Div4 = 0x2
	// ETRP frequency divided by 8
	TIM_SMCR_ETPS_Div8 = 0x3
	// Position of ETF field.
	TIM_SMCR_ETF_Pos = 0x8
	// Bit mask of ETF field.
	TIM_SMCR_ETF_Msk = 0xf00
	// No filter, sampling is done at fDTS
	TIM_SMCR_ETF_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_SMCR_ETF_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_SMCR_ETF_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_SMCR_ETF_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_SMCR_ETF_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_SMCR_ETF_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_SMCR_ETF_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_SMCR_ETF_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_SMCR_ETF_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_SMCR_ETF_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_SMCR_ETF_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_SMCR_ETF_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_SMCR_ETF_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_SMCR_ETF_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_SMCR_ETF_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_SMCR_ETF_FDTS_Div32_N8 = 0xf
	// Position of MSM field.
	TIM_SMCR_MSM_Pos = 0x7
	// Bit mask of MSM field.
	TIM_SMCR_MSM_Msk = 0x80
	// Bit MSM.
	TIM_SMCR_MSM = 0x80
	// No action
	TIM_SMCR_MSM_NoSync = 0x0
	// The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
	TIM_SMCR_MSM_Sync = 0x1
	// Position of TS field.
	TIM_SMCR_TS_Pos = 0x4
	// Bit mask of TS field.
	TIM_SMCR_TS_Msk = 0x70
	// Position of SMS field.
	TIM_SMCR_SMS_Pos = 0x0
	// Bit mask of SMS field.
	TIM_SMCR_SMS_Msk = 0x7
	// Position of SMS_3 field.
	TIM_SMCR_SMS_3_Pos = 0x10
	// Bit mask of SMS_3 field.
	TIM_SMCR_SMS_3_Msk = 0x10000
	// Bit SMS_3.
	TIM_SMCR_SMS_3 = 0x10000

	// DIER: DMA/Interrupt enable register
	// Position of TDE field.
	TIM_DIER_TDE_Pos = 0xe
	// Bit mask of TDE field.
	TIM_DIER_TDE_Msk = 0x4000
	// Bit TDE.
	TIM_DIER_TDE = 0x4000
	// Trigger DMA request disabled
	TIM_DIER_TDE_Disabled = 0x0
	// Trigger DMA request enabled
	TIM_DIER_TDE_Enabled = 0x1
	// Position of COMDE field.
	TIM_DIER_COMDE_Pos = 0xd
	// Bit mask of COMDE field.
	TIM_DIER_COMDE_Msk = 0x2000
	// Bit COMDE.
	TIM_DIER_COMDE = 0x2000
	// COM DMA request disabled
	TIM_DIER_COMDE_Disabled = 0x0
	// COM DMA request enabled
	TIM_DIER_COMDE_Enabled = 0x1
	// Position of CC1DE field.
	TIM_DIER_CC1DE_Pos = 0xa
	// Bit mask of CC1DE field.
	TIM_DIER_CC1DE_Msk = 0x400
	// Bit CC1DE.
	TIM_DIER_CC1DE = 0x400
	// CCx DMA request disabled
	TIM_DIER_CC1DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC1DE_Enabled = 0x1
	// Position of CC2DE field.
	TIM_DIER_CC2DE_Pos = 0xb
	// Bit mask of CC2DE field.
	TIM_DIER_CC2DE_Msk = 0x800
	// Bit CC2DE.
	TIM_DIER_CC2DE = 0x800
	// CCx DMA request disabled
	TIM_DIER_CC2DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC2DE_Enabled = 0x1
	// Position of CC3DE field.
	TIM_DIER_CC3DE_Pos = 0xc
	// Bit mask of CC3DE field.
	TIM_DIER_CC3DE_Msk = 0x1000
	// Bit CC3DE.
	TIM_DIER_CC3DE = 0x1000
	// CCx DMA request disabled
	TIM_DIER_CC3DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC3DE_Enabled = 0x1
	// Position of CC4DE field.
	TIM_DIER_CC4DE_Pos = 0xd
	// Bit mask of CC4DE field.
	TIM_DIER_CC4DE_Msk = 0x2000
	// Bit CC4DE.
	TIM_DIER_CC4DE = 0x2000
	// CCx DMA request disabled
	TIM_DIER_CC4DE_Disabled = 0x0
	// CCx DMA request enabled
	TIM_DIER_CC4DE_Enabled = 0x1
	// Position of UDE field.
	TIM_DIER_UDE_Pos = 0x8
	// Bit mask of UDE field.
	TIM_DIER_UDE_Msk = 0x100
	// Bit UDE.
	TIM_DIER_UDE = 0x100
	// Update DMA request disabled
	TIM_DIER_UDE_Disabled = 0x0
	// Update DMA request enabled
	TIM_DIER_UDE_Enabled = 0x1
	// Position of TIE field.
	TIM_DIER_TIE_Pos = 0x6
	// Bit mask of TIE field.
	TIM_DIER_TIE_Msk = 0x40
	// Bit TIE.
	TIM_DIER_TIE = 0x40
	// Trigger interrupt disabled
	TIM_DIER_TIE_Disabled = 0x0
	// Trigger interrupt enabled
	TIM_DIER_TIE_Enabled = 0x1
	// Position of CC1IE field.
	TIM_DIER_CC1IE_Pos = 0x2
	// Bit mask of CC1IE field.
	TIM_DIER_CC1IE_Msk = 0x4
	// Bit CC1IE.
	TIM_DIER_CC1IE = 0x4
	// CCx interrupt disabled
	TIM_DIER_CC1IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC1IE_Enabled = 0x1
	// Position of CC2IE field.
	TIM_DIER_CC2IE_Pos = 0x3
	// Bit mask of CC2IE field.
	TIM_DIER_CC2IE_Msk = 0x8
	// Bit CC2IE.
	TIM_DIER_CC2IE = 0x8
	// CCx interrupt disabled
	TIM_DIER_CC2IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC2IE_Enabled = 0x1
	// Position of CC3IE field.
	TIM_DIER_CC3IE_Pos = 0x4
	// Bit mask of CC3IE field.
	TIM_DIER_CC3IE_Msk = 0x10
	// Bit CC3IE.
	TIM_DIER_CC3IE = 0x10
	// CCx interrupt disabled
	TIM_DIER_CC3IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC3IE_Enabled = 0x1
	// Position of CC4IE field.
	TIM_DIER_CC4IE_Pos = 0x5
	// Bit mask of CC4IE field.
	TIM_DIER_CC4IE_Msk = 0x20
	// Bit CC4IE.
	TIM_DIER_CC4IE = 0x20
	// CCx interrupt disabled
	TIM_DIER_CC4IE_Disabled = 0x0
	// CCx interrupt enabled
	TIM_DIER_CC4IE_Enabled = 0x1
	// Position of UIE field.
	TIM_DIER_UIE_Pos = 0x0
	// Bit mask of UIE field.
	TIM_DIER_UIE_Msk = 0x1
	// Bit UIE.
	TIM_DIER_UIE = 0x1
	// Update interrupt disabled
	TIM_DIER_UIE_Disabled = 0x0
	// Update interrupt enabled
	TIM_DIER_UIE_Enabled = 0x1
	// Position of BIE field.
	TIM_DIER_BIE_Pos = 0x7
	// Bit mask of BIE field.
	TIM_DIER_BIE_Msk = 0x80
	// Bit BIE.
	TIM_DIER_BIE = 0x80
	// Break interrupt disabled
	TIM_DIER_BIE_Disabled = 0x0
	// Break interrupt enabled
	TIM_DIER_BIE_Enabled = 0x1
	// Position of COMIE field.
	TIM_DIER_COMIE_Pos = 0x5
	// Bit mask of COMIE field.
	TIM_DIER_COMIE_Msk = 0x20
	// Bit COMIE.
	TIM_DIER_COMIE = 0x20
	// COM interrupt disabled
	TIM_DIER_COMIE_Disabled = 0x0
	// COM interrupt enabled
	TIM_DIER_COMIE_Enabled = 0x1

	// SR: status register
	// Position of CC1OF field.
	TIM_SR_CC1OF_Pos = 0xa
	// Bit mask of CC1OF field.
	TIM_SR_CC1OF_Msk = 0x400
	// Bit CC1OF.
	TIM_SR_CC1OF = 0x400
	// No overcapture has been detected
	TIM_SR_CC1OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC1OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC1OF_Clear = 0x0
	// Position of CC2OF field.
	TIM_SR_CC2OF_Pos = 0xb
	// Bit mask of CC2OF field.
	TIM_SR_CC2OF_Msk = 0x800
	// Bit CC2OF.
	TIM_SR_CC2OF = 0x800
	// No overcapture has been detected
	TIM_SR_CC2OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC2OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC2OF_Clear = 0x0
	// Position of CC3OF field.
	TIM_SR_CC3OF_Pos = 0xc
	// Bit mask of CC3OF field.
	TIM_SR_CC3OF_Msk = 0x1000
	// Bit CC3OF.
	TIM_SR_CC3OF = 0x1000
	// No overcapture has been detected
	TIM_SR_CC3OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC3OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC3OF_Clear = 0x0
	// Position of CC4OF field.
	TIM_SR_CC4OF_Pos = 0xd
	// Bit mask of CC4OF field.
	TIM_SR_CC4OF_Msk = 0x2000
	// Bit CC4OF.
	TIM_SR_CC4OF = 0x2000
	// No overcapture has been detected
	TIM_SR_CC4OF_NoOvercapture = 0x0
	// The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
	TIM_SR_CC4OF_Overcapture = 0x1
	// Clear flag
	TIM_SR_CC4OF_Clear = 0x0
	// Position of BIF field.
	TIM_SR_BIF_Pos = 0x7
	// Bit mask of BIF field.
	TIM_SR_BIF_Msk = 0x80
	// Bit BIF.
	TIM_SR_BIF = 0x80
	// No break event occurred
	TIM_SR_BIF_NoTrigger = 0x0
	// An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_BIF_Trigger = 0x1
	// Clear flag
	TIM_SR_BIF_Clear = 0x0
	// Position of TIF field.
	TIM_SR_TIF_Pos = 0x6
	// Bit mask of TIF field.
	TIM_SR_TIF_Msk = 0x40
	// Bit TIF.
	TIM_SR_TIF = 0x40
	// No trigger event occurred
	TIM_SR_TIF_NoTrigger = 0x0
	// Trigger interrupt pending
	TIM_SR_TIF_Trigger = 0x1
	// Clear flag
	TIM_SR_TIF_Clear = 0x0
	// Position of COMIF field.
	TIM_SR_COMIF_Pos = 0x5
	// Bit mask of COMIF field.
	TIM_SR_COMIF_Msk = 0x20
	// Bit COMIF.
	TIM_SR_COMIF = 0x20
	// No COM event occurred
	TIM_SR_COMIF_NoCOM = 0x0
	// COM interrupt pending
	TIM_SR_COMIF_COM = 0x1
	// Clear flag
	TIM_SR_COMIF_Clear = 0x0
	// Position of CC1IF field.
	TIM_SR_CC1IF_Pos = 0x2
	// Bit mask of CC1IF field.
	TIM_SR_CC1IF_Msk = 0x4
	// Bit CC1IF.
	TIM_SR_CC1IF = 0x4
	// No campture/compare has been detected
	TIM_SR_CC1IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC1IF_Match = 0x1
	// Clear flag
	TIM_SR_CC1IF_Clear = 0x0
	// Position of CC2IF field.
	TIM_SR_CC2IF_Pos = 0x3
	// Bit mask of CC2IF field.
	TIM_SR_CC2IF_Msk = 0x8
	// Bit CC2IF.
	TIM_SR_CC2IF = 0x8
	// No campture/compare has been detected
	TIM_SR_CC2IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC2IF_Match = 0x1
	// Clear flag
	TIM_SR_CC2IF_Clear = 0x0
	// Position of CC3IF field.
	TIM_SR_CC3IF_Pos = 0x4
	// Bit mask of CC3IF field.
	TIM_SR_CC3IF_Msk = 0x10
	// Bit CC3IF.
	TIM_SR_CC3IF = 0x10
	// No campture/compare has been detected
	TIM_SR_CC3IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC3IF_Match = 0x1
	// Clear flag
	TIM_SR_CC3IF_Clear = 0x0
	// Position of CC4IF field.
	TIM_SR_CC4IF_Pos = 0x5
	// Bit mask of CC4IF field.
	TIM_SR_CC4IF_Msk = 0x20
	// Bit CC4IF.
	TIM_SR_CC4IF = 0x20
	// No campture/compare has been detected
	TIM_SR_CC4IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC4IF_Match = 0x1
	// Clear flag
	TIM_SR_CC4IF_Clear = 0x0
	// Position of UIF field.
	TIM_SR_UIF_Pos = 0x0
	// Bit mask of UIF field.
	TIM_SR_UIF_Msk = 0x1
	// Bit UIF.
	TIM_SR_UIF = 0x1
	// No update occurred
	TIM_SR_UIF_NoUpdateOccurred = 0x0
	// Update interrupt pending
	TIM_SR_UIF_UpdatePending = 0x1
	// Clear flag
	TIM_SR_UIF_Clear = 0x0
	// Position of SBIF field.
	TIM_SR_SBIF_Pos = 0xd
	// Bit mask of SBIF field.
	TIM_SR_SBIF_Msk = 0x2000
	// Bit SBIF.
	TIM_SR_SBIF = 0x2000
	// No break event occurred
	TIM_SR_SBIF_NoTrigger = 0x0
	// An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
	TIM_SR_SBIF_Trigger = 0x1
	// Clear flag
	TIM_SR_SBIF_Clear = 0x0
	// Position of CC5IF field.
	TIM_SR_CC5IF_Pos = 0x10
	// Bit mask of CC5IF field.
	TIM_SR_CC5IF_Msk = 0x10000
	// Bit CC5IF.
	TIM_SR_CC5IF = 0x10000
	// No campture/compare has been detected
	TIM_SR_CC5IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC5IF_Match = 0x1
	// Clear flag
	TIM_SR_CC5IF_Clear = 0x0
	// Position of CC6IF field.
	TIM_SR_CC6IF_Pos = 0x11
	// Bit mask of CC6IF field.
	TIM_SR_CC6IF_Msk = 0x20000
	// Bit CC6IF.
	TIM_SR_CC6IF = 0x20000
	// No campture/compare has been detected
	TIM_SR_CC6IF_NoMatch = 0x0
	// If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
	TIM_SR_CC6IF_Match = 0x1
	// Clear flag
	TIM_SR_CC6IF_Clear = 0x0

	// EGR: event generation register
	// Position of BG field.
	TIM_EGR_BG_Pos = 0x7
	// Bit mask of BG field.
	TIM_EGR_BG_Msk = 0x80
	// Bit BG.
	TIM_EGR_BG = 0x80
	// A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
	TIM_EGR_BG_Trigger = 0x1
	// Position of TG field.
	TIM_EGR_TG_Pos = 0x6
	// Bit mask of TG field.
	TIM_EGR_TG_Msk = 0x40
	// Bit TG.
	TIM_EGR_TG = 0x40
	// The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
	TIM_EGR_TG_Trigger = 0x1
	// Position of COMG field.
	TIM_EGR_COMG_Pos = 0x5
	// Bit mask of COMG field.
	TIM_EGR_COMG_Msk = 0x20
	// Bit COMG.
	TIM_EGR_COMG = 0x20
	// When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
	TIM_EGR_COMG_Trigger = 0x1
	// Position of CC1G field.
	TIM_EGR_CC1G_Pos = 0x2
	// Bit mask of CC1G field.
	TIM_EGR_CC1G_Msk = 0x4
	// Bit CC1G.
	TIM_EGR_CC1G = 0x4
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC1G_Trigger = 0x1
	// Position of CC2G field.
	TIM_EGR_CC2G_Pos = 0x3
	// Bit mask of CC2G field.
	TIM_EGR_CC2G_Msk = 0x8
	// Bit CC2G.
	TIM_EGR_CC2G = 0x8
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC2G_Trigger = 0x1
	// Position of CC3G field.
	TIM_EGR_CC3G_Pos = 0x4
	// Bit mask of CC3G field.
	TIM_EGR_CC3G_Msk = 0x10
	// Bit CC3G.
	TIM_EGR_CC3G = 0x10
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC3G_Trigger = 0x1
	// Position of CC4G field.
	TIM_EGR_CC4G_Pos = 0x5
	// Bit mask of CC4G field.
	TIM_EGR_CC4G_Msk = 0x20
	// Bit CC4G.
	TIM_EGR_CC4G = 0x20
	// If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
	TIM_EGR_CC4G_Trigger = 0x1
	// Position of UG field.
	TIM_EGR_UG_Pos = 0x0
	// Bit mask of UG field.
	TIM_EGR_UG_Msk = 0x1
	// Bit UG.
	TIM_EGR_UG = 0x1
	// Re-initializes the timer counter and generates an update of the registers.
	TIM_EGR_UG_Update = 0x1
	// Position of B2G field.
	TIM_EGR_B2G_Pos = 0x8
	// Bit mask of B2G field.
	TIM_EGR_B2G_Msk = 0x100
	// Bit B2G.
	TIM_EGR_B2G = 0x100
	// A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled
	TIM_EGR_B2G_Trigger = 0x1

	// CCMR1_Output: capture/compare mode register 1 (output mode)
	// Position of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Pos = 0xf
	// Bit mask of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Msk = 0x8000
	// Bit OC1CE.
	TIM_CCMR1_Output_OC1CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR1_Output_OC1CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR1_Output_OC1CE_Enabled = 0x1
	// Position of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Pos = 0x17
	// Bit mask of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Msk = 0x800000
	// Bit OC2CE.
	TIM_CCMR1_Output_OC2CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR1_Output_OC2CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR1_Output_OC2CE_Enabled = 0x1
	// Position of OC1M field.
	TIM_CCMR1_Output_OC1M_Pos = 0xc
	// Bit mask of OC1M field.
	TIM_CCMR1_Output_OC1M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC1M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC1M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC1M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC1M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC1M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC1M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC1M_PwmMode2 = 0x7
	// Position of OC2M field.
	TIM_CCMR1_Output_OC2M_Pos = 0x14
	// Bit mask of OC2M field.
	TIM_CCMR1_Output_OC2M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR1_Output_OC2M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR1_Output_OC2M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR1_Output_OC2M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR1_Output_OC2M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR1_Output_OC2M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR1_Output_OC2M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR1_Output_OC2M_PwmMode2 = 0x7
	// Position of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Pos = 0xb
	// Bit mask of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Msk = 0x800
	// Bit OC1PE.
	TIM_CCMR1_Output_OC1PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC1PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC1PE_Enabled = 0x1
	// Position of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Pos = 0x13
	// Bit mask of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Msk = 0x80000
	// Bit OC2PE.
	TIM_CCMR1_Output_OC2PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR1_Output_OC2PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR1_Output_OC2PE_Enabled = 0x1
	// Position of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Pos = 0xa
	// Bit mask of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Msk = 0x400
	// Bit OC1FE.
	TIM_CCMR1_Output_OC1FE = 0x400
	// Fast output disabled
	TIM_CCMR1_Output_OC1FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC1FE_Enabled = 0x1
	// Position of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Pos = 0x12
	// Bit mask of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Msk = 0x40000
	// Bit OC2FE.
	TIM_CCMR1_Output_OC2FE = 0x40000
	// Fast output disabled
	TIM_CCMR1_Output_OC2FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR1_Output_OC2FE_Enabled = 0x1
	// Position of CC1S field.
	TIM_CCMR1_Output_CC1S_Pos = 0x8
	// Bit mask of CC1S field.
	TIM_CCMR1_Output_CC1S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC1S_Output = 0x0
	// Position of CC2S field.
	TIM_CCMR1_Output_CC2S_Pos = 0x10
	// Bit mask of CC2S field.
	TIM_CCMR1_Output_CC2S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR1_Output_CC2S_Output = 0x0
	// Position of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Pos = 0x18
	// Bit mask of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Msk = 0x1000000
	// Bit OC1M_3.
	TIM_CCMR1_Output_OC1M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC1M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC1M_3_Extended = 0x1
	// Position of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Pos = 0x20
	// Bit mask of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Msk = 0x100000000
	// Bit OC2M_3.
	TIM_CCMR1_Output_OC2M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR1_Output_OC2M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR1_Output_OC2M_3_Extended = 0x1

	// CCMR1_Input: capture/compare mode register 1 (input mode)
	// Position of IC1F field.
	TIM_CCMR1_Input_IC1F_Pos = 0xc
	// Bit mask of IC1F field.
	TIM_CCMR1_Input_IC1F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC1F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC1F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC1F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC1F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC1F_FDTS_Div32_N8 = 0xf
	// Position of IC2F field.
	TIM_CCMR1_Input_IC2F_Pos = 0x14
	// Bit mask of IC2F field.
	TIM_CCMR1_Input_IC2F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR1_Input_IC2F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR1_Input_IC2F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR1_Input_IC2F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR1_Input_IC2F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR1_Input_IC2F_FDTS_Div32_N8 = 0xf
	// Position of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Pos = 0xa
	// Bit mask of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC1PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC1PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC1PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC1PSC_EightEvents = 0x3
	// Position of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Pos = 0x12
	// Bit mask of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR1_Input_IC2PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR1_Input_IC2PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR1_Input_IC2PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR1_Input_IC2PSC_EightEvents = 0x3
	// Position of CC2S field.
	TIM_CCMR1_Input_CC2S_Pos = 0x8
	// Bit mask of CC2S field.
	TIM_CCMR1_Input_CC2S_Msk = 0x300
	// CC2 channel is configured as input, IC2 is mapped on TI2
	TIM_CCMR1_Input_CC2S_TI2 = 0x1
	// CC2 channel is configured as input, IC2 is mapped on TI1
	TIM_CCMR1_Input_CC2S_TI1 = 0x2
	// CC2 channel is configured as input, IC2 is mapped on TRC
	TIM_CCMR1_Input_CC2S_TRC = 0x3
	// Position of CC1S field.
	TIM_CCMR1_Input_CC1S_Pos = 0x0
	// Bit mask of CC1S field.
	TIM_CCMR1_Input_CC1S_Msk = 0x3
	// CC1 channel is configured as input, IC1 is mapped on TI1
	TIM_CCMR1_Input_CC1S_TI1 = 0x1
	// CC1 channel is configured as input, IC1 is mapped on TI2
	TIM_CCMR1_Input_CC1S_TI2 = 0x2
	// CC1 channel is configured as input, IC1 is mapped on TRC
	TIM_CCMR1_Input_CC1S_TRC = 0x3

	// CCMR2_Output: capture/compare mode register 2 (output mode)
	// Position of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Pos = 0xf
	// Bit mask of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Msk = 0x8000
	// Bit OC3CE.
	TIM_CCMR2_Output_OC3CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR2_Output_OC3CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR2_Output_OC3CE_Enabled = 0x1
	// Position of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Pos = 0x17
	// Bit mask of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Msk = 0x800000
	// Bit OC4CE.
	TIM_CCMR2_Output_OC4CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR2_Output_OC4CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR2_Output_OC4CE_Enabled = 0x1
	// Position of OC3M field.
	TIM_CCMR2_Output_OC3M_Pos = 0xc
	// Bit mask of OC3M field.
	TIM_CCMR2_Output_OC3M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC3M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC3M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC3M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC3M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC3M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC3M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC3M_PwmMode2 = 0x7
	// Position of OC4M field.
	TIM_CCMR2_Output_OC4M_Pos = 0x14
	// Bit mask of OC4M field.
	TIM_CCMR2_Output_OC4M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR2_Output_OC4M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR2_Output_OC4M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR2_Output_OC4M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR2_Output_OC4M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR2_Output_OC4M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR2_Output_OC4M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR2_Output_OC4M_PwmMode2 = 0x7
	// Position of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Pos = 0xb
	// Bit mask of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Msk = 0x800
	// Bit OC3PE.
	TIM_CCMR2_Output_OC3PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC3PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC3PE_Enabled = 0x1
	// Position of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Pos = 0x13
	// Bit mask of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Msk = 0x80000
	// Bit OC4PE.
	TIM_CCMR2_Output_OC4PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR2_Output_OC4PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR2_Output_OC4PE_Enabled = 0x1
	// Position of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Pos = 0xa
	// Bit mask of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Msk = 0x400
	// Bit OC3FE.
	TIM_CCMR2_Output_OC3FE = 0x400
	// Fast output disabled
	TIM_CCMR2_Output_OC3FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC3FE_Enabled = 0x1
	// Position of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Pos = 0x12
	// Bit mask of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Msk = 0x40000
	// Bit OC4FE.
	TIM_CCMR2_Output_OC4FE = 0x40000
	// Fast output disabled
	TIM_CCMR2_Output_OC4FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR2_Output_OC4FE_Enabled = 0x1
	// Position of CC3S field.
	TIM_CCMR2_Output_CC3S_Pos = 0x8
	// Bit mask of CC3S field.
	TIM_CCMR2_Output_CC3S_Msk = 0x300
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC3S_Output = 0x0
	// Position of CC4S field.
	TIM_CCMR2_Output_CC4S_Pos = 0x10
	// Bit mask of CC4S field.
	TIM_CCMR2_Output_CC4S_Msk = 0x30000
	// CCx channel is configured as output
	TIM_CCMR2_Output_CC4S_Output = 0x0
	// Position of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Pos = 0x18
	// Bit mask of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Msk = 0x1000000
	// Bit OC3M_3.
	TIM_CCMR2_Output_OC3M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC3M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC3M_3_Extended = 0x1
	// Position of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Pos = 0x20
	// Bit mask of OC4M_3 field.
	TIM_CCMR2_Output_OC4M_3_Msk = 0x100000000
	// Bit OC4M_3.
	TIM_CCMR2_Output_OC4M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR2_Output_OC4M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR2_Output_OC4M_3_Extended = 0x1

	// CCMR2_Input: capture/compare mode register 2 (input mode)
	// Position of IC3F field.
	TIM_CCMR2_Input_IC3F_Pos = 0xc
	// Bit mask of IC3F field.
	TIM_CCMR2_Input_IC3F_Msk = 0xf000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC3F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC3F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC3F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC3F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC3F_FDTS_Div32_N8 = 0xf
	// Position of IC4F field.
	TIM_CCMR2_Input_IC4F_Pos = 0x14
	// Bit mask of IC4F field.
	TIM_CCMR2_Input_IC4F_Msk = 0xf00000
	// No filter, sampling is done at fDTS
	TIM_CCMR2_Input_IC4F_NoFilter = 0x0
	// fSAMPLING=fCK_INT, N=2
	TIM_CCMR2_Input_IC4F_FCK_INT_N2 = 0x1
	// fSAMPLING=fCK_INT, N=4
	TIM_CCMR2_Input_IC4F_FCK_INT_N4 = 0x2
	// fSAMPLING=fCK_INT, N=8
	TIM_CCMR2_Input_IC4F_FCK_INT_N8 = 0x3
	// fSAMPLING=fDTS/2, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N6 = 0x4
	// fSAMPLING=fDTS/2, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div2_N8 = 0x5
	// fSAMPLING=fDTS/4, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N6 = 0x6
	// fSAMPLING=fDTS/4, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div4_N8 = 0x7
	// fSAMPLING=fDTS/8, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N6 = 0x8
	// fSAMPLING=fDTS/8, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div8_N8 = 0x9
	// fSAMPLING=fDTS/16, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N5 = 0xa
	// fSAMPLING=fDTS/16, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N6 = 0xb
	// fSAMPLING=fDTS/16, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div16_N8 = 0xc
	// fSAMPLING=fDTS/32, N=5
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N5 = 0xd
	// fSAMPLING=fDTS/32, N=6
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N6 = 0xe
	// fSAMPLING=fDTS/32, N=8
	TIM_CCMR2_Input_IC4F_FDTS_Div32_N8 = 0xf
	// Position of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Pos = 0xa
	// Bit mask of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Msk = 0xc00
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC3PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC3PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC3PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC3PSC_EightEvents = 0x3
	// Position of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Pos = 0x12
	// Bit mask of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Msk = 0xc0000
	// No prescaler, capture is done each time an edge is detected on the capture input
	TIM_CCMR2_Input_IC4PSC_NoPrescaler = 0x0
	// Capture is done once every 2 events
	TIM_CCMR2_Input_IC4PSC_TwoEvents = 0x1
	// Capture is done once every 4 events
	TIM_CCMR2_Input_IC4PSC_FourEvents = 0x2
	// Capture is done once every 8 events
	TIM_CCMR2_Input_IC4PSC_EightEvents = 0x3
	// Position of CC4S field.
	TIM_CCMR2_Input_CC4S_Pos = 0x8
	// Bit mask of CC4S field.
	TIM_CCMR2_Input_CC4S_Msk = 0x300
	// CC4 channel is configured as input, IC4 is mapped on TI4
	TIM_CCMR2_Input_CC4S_TI4 = 0x1
	// CC4 channel is configured as input, IC4 is mapped on TI3
	TIM_CCMR2_Input_CC4S_TI3 = 0x2
	// CC4 channel is configured as input, IC4 is mapped on TRC
	TIM_CCMR2_Input_CC4S_TRC = 0x3
	// Position of CC3S field.
	TIM_CCMR2_Input_CC3S_Pos = 0x0
	// Bit mask of CC3S field.
	TIM_CCMR2_Input_CC3S_Msk = 0x3
	// CC3 channel is configured as input, IC3 is mapped on TI3
	TIM_CCMR2_Input_CC3S_TI3 = 0x1
	// CC3 channel is configured as input, IC3 is mapped on TI4
	TIM_CCMR2_Input_CC3S_TI4 = 0x2
	// CC3 channel is configured as input, IC3 is mapped on TRC
	TIM_CCMR2_Input_CC3S_TRC = 0x3

	// CCER: capture/compare enable register
	// Position of CC1P field.
	TIM_CCER_CC1P_Pos = 0x5
	// Bit mask of CC1P field.
	TIM_CCER_CC1P_Msk = 0x20
	// Bit CC1P.
	TIM_CCER_CC1P = 0x20
	// Noninverted/rising edge
	TIM_CCER_CC1P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC1P_FallingEdge = 0x1
	// Position of CC2P field.
	TIM_CCER_CC2P_Pos = 0x9
	// Bit mask of CC2P field.
	TIM_CCER_CC2P_Msk = 0x200
	// Bit CC2P.
	TIM_CCER_CC2P = 0x200
	// Noninverted/rising edge
	TIM_CCER_CC2P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC2P_FallingEdge = 0x1
	// Position of CC3P field.
	TIM_CCER_CC3P_Pos = 0xd
	// Bit mask of CC3P field.
	TIM_CCER_CC3P_Msk = 0x2000
	// Bit CC3P.
	TIM_CCER_CC3P = 0x2000
	// Noninverted/rising edge
	TIM_CCER_CC3P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC3P_FallingEdge = 0x1
	// Position of CC4P field.
	TIM_CCER_CC4P_Pos = 0x11
	// Bit mask of CC4P field.
	TIM_CCER_CC4P_Msk = 0x20000
	// Bit CC4P.
	TIM_CCER_CC4P = 0x20000
	// Noninverted/rising edge
	TIM_CCER_CC4P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC4P_FallingEdge = 0x1
	// Position of CC5P field.
	TIM_CCER_CC5P_Pos = 0x15
	// Bit mask of CC5P field.
	TIM_CCER_CC5P_Msk = 0x200000
	// Bit CC5P.
	TIM_CCER_CC5P = 0x200000
	// Noninverted/rising edge
	TIM_CCER_CC5P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC5P_FallingEdge = 0x1
	// Position of CC6P field.
	TIM_CCER_CC6P_Pos = 0x19
	// Bit mask of CC6P field.
	TIM_CCER_CC6P_Msk = 0x2000000
	// Bit CC6P.
	TIM_CCER_CC6P = 0x2000000
	// Noninverted/rising edge
	TIM_CCER_CC6P_RisingEdge = 0x0
	// Inverted/falling edge
	TIM_CCER_CC6P_FallingEdge = 0x1
	// Position of CC1E field.
	TIM_CCER_CC1E_Pos = 0x4
	// Bit mask of CC1E field.
	TIM_CCER_CC1E_Msk = 0x10
	// Bit CC1E.
	TIM_CCER_CC1E = 0x10
	// Capture disabled
	TIM_CCER_CC1E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC1E_Enabled = 0x1
	// Position of CC2E field.
	TIM_CCER_CC2E_Pos = 0x8
	// Bit mask of CC2E field.
	TIM_CCER_CC2E_Msk = 0x100
	// Bit CC2E.
	TIM_CCER_CC2E = 0x100
	// Capture disabled
	TIM_CCER_CC2E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC2E_Enabled = 0x1
	// Position of CC3E field.
	TIM_CCER_CC3E_Pos = 0xc
	// Bit mask of CC3E field.
	TIM_CCER_CC3E_Msk = 0x1000
	// Bit CC3E.
	TIM_CCER_CC3E = 0x1000
	// Capture disabled
	TIM_CCER_CC3E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC3E_Enabled = 0x1
	// Position of CC4E field.
	TIM_CCER_CC4E_Pos = 0x10
	// Bit mask of CC4E field.
	TIM_CCER_CC4E_Msk = 0x10000
	// Bit CC4E.
	TIM_CCER_CC4E = 0x10000
	// Capture disabled
	TIM_CCER_CC4E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC4E_Enabled = 0x1
	// Position of CC5E field.
	TIM_CCER_CC5E_Pos = 0x14
	// Bit mask of CC5E field.
	TIM_CCER_CC5E_Msk = 0x100000
	// Bit CC5E.
	TIM_CCER_CC5E = 0x100000
	// Capture disabled
	TIM_CCER_CC5E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC5E_Enabled = 0x1
	// Position of CC6E field.
	TIM_CCER_CC6E_Pos = 0x18
	// Bit mask of CC6E field.
	TIM_CCER_CC6E_Msk = 0x1000000
	// Bit CC6E.
	TIM_CCER_CC6E = 0x1000000
	// Capture disabled
	TIM_CCER_CC6E_Disabled = 0x0
	// Capture enabled
	TIM_CCER_CC6E_Enabled = 0x1
	// Position of CC1NP field.
	TIM_CCER_CC1NP_Pos = 0x7
	// Bit mask of CC1NP field.
	TIM_CCER_CC1NP_Msk = 0x80
	// Bit CC1NP.
	TIM_CCER_CC1NP = 0x80
	// OCxN active high
	TIM_CCER_CC1NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC1NP_ActiveLow = 0x1
	// Position of CC2NP field.
	TIM_CCER_CC2NP_Pos = 0xb
	// Bit mask of CC2NP field.
	TIM_CCER_CC2NP_Msk = 0x800
	// Bit CC2NP.
	TIM_CCER_CC2NP = 0x800
	// OCxN active high
	TIM_CCER_CC2NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC2NP_ActiveLow = 0x1
	// Position of CC3NP field.
	TIM_CCER_CC3NP_Pos = 0xf
	// Bit mask of CC3NP field.
	TIM_CCER_CC3NP_Msk = 0x8000
	// Bit CC3NP.
	TIM_CCER_CC3NP = 0x8000
	// OCxN active high
	TIM_CCER_CC3NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC3NP_ActiveLow = 0x1
	// Position of CC4NP field.
	TIM_CCER_CC4NP_Pos = 0x13
	// Bit mask of CC4NP field.
	TIM_CCER_CC4NP_Msk = 0x80000
	// Bit CC4NP.
	TIM_CCER_CC4NP = 0x80000
	// OCxN active high
	TIM_CCER_CC4NP_ActiveHigh = 0x0
	// OCxN active low
	TIM_CCER_CC4NP_ActiveLow = 0x1
	// Position of CC1NE field.
	TIM_CCER_CC1NE_Pos = 0x6
	// Bit mask of CC1NE field.
	TIM_CCER_CC1NE_Msk = 0x40
	// Bit CC1NE.
	TIM_CCER_CC1NE = 0x40
	// Complementary output disabled
	TIM_CCER_CC1NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC1NE_Enabled = 0x1
	// Position of CC2NE field.
	TIM_CCER_CC2NE_Pos = 0xa
	// Bit mask of CC2NE field.
	TIM_CCER_CC2NE_Msk = 0x400
	// Bit CC2NE.
	TIM_CCER_CC2NE = 0x400
	// Complementary output disabled
	TIM_CCER_CC2NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC2NE_Enabled = 0x1
	// Position of CC3NE field.
	TIM_CCER_CC3NE_Pos = 0xe
	// Bit mask of CC3NE field.
	TIM_CCER_CC3NE_Msk = 0x4000
	// Bit CC3NE.
	TIM_CCER_CC3NE = 0x4000
	// Complementary output disabled
	TIM_CCER_CC3NE_Disabled = 0x0
	// Complementary output enabled
	TIM_CCER_CC3NE_Enabled = 0x1

	// CNT: counter
	// Position of CNT field.
	TIM_CNT_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT_CNT_Msk = 0xffff
	// Position of UIFCPY field.
	TIM_CNT_UIFCPY_Pos = 0x1f
	// Bit mask of UIFCPY field.
	TIM_CNT_UIFCPY_Msk = 0x80000000
	// Bit UIFCPY.
	TIM_CNT_UIFCPY = 0x80000000

	// CNT16: 16-bit counter register
	// Position of CNT field.
	TIM_CNT16_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TIM_CNT16_CNT_Msk = 0xffff

	// PSC: prescaler
	// Position of PSC field.
	TIM_PSC_PSC_Pos = 0x0
	// Bit mask of PSC field.
	TIM_PSC_PSC_Msk = 0xffff

	// ARR: auto-reload register
	// Position of ARR field.
	TIM_ARR_ARR_Pos = 0x0
	// Bit mask of ARR field.
	TIM_ARR_ARR_Msk = 0xffff

	// RCR: repetition counter register
	// Position of REP field.
	TIM_RCR_REP_Pos = 0x0
	// Bit mask of REP field.
	TIM_RCR_REP_Msk = 0xffff

	// CCR1: capture/compare register
	// Position of CCR field.
	TIM_CCR_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR_CCR_Msk = 0xffff

	// BDTR: break and dead-time register
	// Position of MOE field.
	TIM_BDTR_MOE_Pos = 0xf
	// Bit mask of MOE field.
	TIM_BDTR_MOE_Msk = 0x8000
	// Bit MOE.
	TIM_BDTR_MOE = 0x8000
	// OC/OCN are disabled or forced idle depending on OSSI
	TIM_BDTR_MOE_DisabledIdle = 0x0
	// OC/OCN are enabled if CCxE/CCxNE are set
	TIM_BDTR_MOE_Enabled = 0x1
	// Position of AOE field.
	TIM_BDTR_AOE_Pos = 0xe
	// Bit mask of AOE field.
	TIM_BDTR_AOE_Msk = 0x4000
	// Bit AOE.
	TIM_BDTR_AOE = 0x4000
	// MOE can be set only by software
	TIM_BDTR_AOE_Manual = 0x0
	// MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
	TIM_BDTR_AOE_Automatic = 0x1
	// Position of BKP field.
	TIM_BDTR_BKP_Pos = 0xd
	// Bit mask of BKP field.
	TIM_BDTR_BKP_Msk = 0x2000
	// Bit BKP.
	TIM_BDTR_BKP = 0x2000
	// Break input BRKx is active low
	TIM_BDTR_BKP_ActiveLow = 0x0
	// Break input BRKx is active high
	TIM_BDTR_BKP_ActiveHigh = 0x1
	// Position of BKE field.
	TIM_BDTR_BKE_Pos = 0xc
	// Bit mask of BKE field.
	TIM_BDTR_BKE_Msk = 0x1000
	// Bit BKE.
	TIM_BDTR_BKE = 0x1000
	// Break function x disabled
	TIM_BDTR_BKE_Disabled = 0x0
	// Break function x enabled
	TIM_BDTR_BKE_Enabled = 0x1
	// Position of OSSR field.
	TIM_BDTR_OSSR_Pos = 0xb
	// Bit mask of OSSR field.
	TIM_BDTR_OSSR_Msk = 0x800
	// Bit OSSR.
	TIM_BDTR_OSSR = 0x800
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSR_HiZ = 0x0
	// When inactive, OC/OCN outputs are enabled with their inactive level
	TIM_BDTR_OSSR_IdleLevel = 0x1
	// Position of OSSI field.
	TIM_BDTR_OSSI_Pos = 0xa
	// Bit mask of OSSI field.
	TIM_BDTR_OSSI_Msk = 0x400
	// Bit OSSI.
	TIM_BDTR_OSSI = 0x400
	// When inactive, OC/OCN outputs are disabled
	TIM_BDTR_OSSI_HiZ = 0x0
	// When inactive, OC/OCN outputs are forced to idle level
	TIM_BDTR_OSSI_IdleLevel = 0x1
	// Position of LOCK field.
	TIM_BDTR_LOCK_Pos = 0x8
	// Bit mask of LOCK field.
	TIM_BDTR_LOCK_Msk = 0x300
	// No bit is write protected
	TIM_BDTR_LOCK_Off = 0x0
	// Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
	TIM_BDTR_LOCK_Level1 = 0x1
	// LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
	TIM_BDTR_LOCK_Level2 = 0x2
	// LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
	TIM_BDTR_LOCK_Level3 = 0x3
	// Position of DTG field.
	TIM_BDTR_DTG_Pos = 0x0
	// Bit mask of DTG field.
	TIM_BDTR_DTG_Msk = 0xff
	// Position of BKF field.
	TIM_BDTR_BKF_Pos = 0x10
	// Bit mask of BKF field.
	TIM_BDTR_BKF_Msk = 0xf0000
	// Position of BK2F field.
	TIM_BDTR_BK2F_Pos = 0x14
	// Bit mask of BK2F field.
	TIM_BDTR_BK2F_Msk = 0xf00000
	// Position of BK2E field.
	TIM_BDTR_BK2E_Pos = 0x18
	// Bit mask of BK2E field.
	TIM_BDTR_BK2E_Msk = 0x1000000
	// Bit BK2E.
	TIM_BDTR_BK2E = 0x1000000
	// Break function x disabled
	TIM_BDTR_BK2E_Disabled = 0x0
	// Break function x enabled
	TIM_BDTR_BK2E_Enabled = 0x1
	// Position of BK2P field.
	TIM_BDTR_BK2P_Pos = 0x19
	// Bit mask of BK2P field.
	TIM_BDTR_BK2P_Msk = 0x2000000
	// Bit BK2P.
	TIM_BDTR_BK2P = 0x2000000
	// Break input BRKx is active low
	TIM_BDTR_BK2P_ActiveLow = 0x0
	// Break input BRKx is active high
	TIM_BDTR_BK2P_ActiveHigh = 0x1
	// Position of BKDSRM field.
	TIM_BDTR_BKDSRM_Pos = 0x1a
	// Bit mask of BKDSRM field.
	TIM_BDTR_BKDSRM_Msk = 0x4000000
	// Bit BKDSRM.
	TIM_BDTR_BKDSRM = 0x4000000
	// Position of BK2DSRM field.
	TIM_BDTR_BK2DSRM_Pos = 0x1b
	// Bit mask of BK2DSRM field.
	TIM_BDTR_BK2DSRM_Msk = 0x8000000
	// Bit BK2DSRM.
	TIM_BDTR_BK2DSRM = 0x8000000
	// Position of BKBID field.
	TIM_BDTR_BKBID_Pos = 0x1c
	// Bit mask of BKBID field.
	TIM_BDTR_BKBID_Msk = 0x10000000
	// Bit BKBID.
	TIM_BDTR_BKBID = 0x10000000
	// Position of BK2BID field.
	TIM_BDTR_BK2BID_Pos = 0x1d
	// Bit mask of BK2BID field.
	TIM_BDTR_BK2BID_Msk = 0x20000000
	// Bit BK2BID.
	TIM_BDTR_BK2BID = 0x20000000

	// DCR: DMA control register
	// Position of DBL field.
	TIM_DCR_DBL_Pos = 0x8
	// Bit mask of DBL field.
	TIM_DCR_DBL_Msk = 0x1f00
	// Position of DBA field.
	TIM_DCR_DBA_Pos = 0x0
	// Bit mask of DBA field.
	TIM_DCR_DBA_Msk = 0x1f

	// DMAR: DMA address for full transfer
	// Position of DMAB field.
	TIM_DMAR_DMAB_Pos = 0x0
	// Bit mask of DMAB field.
	TIM_DMAR_DMAB_Msk = 0xffffffff

	// OR1: DMA address for full transfer
	// Position of ETR_ADC1_RMP field.
	TIM_OR1_ETR_ADC1_RMP_Pos = 0x0
	// Bit mask of ETR_ADC1_RMP field.
	TIM_OR1_ETR_ADC1_RMP_Msk = 0x3
	// Position of TI1_RMP field.
	TIM_OR1_TI1_RMP_Pos = 0x4
	// Bit mask of TI1_RMP field.
	TIM_OR1_TI1_RMP_Msk = 0x10
	// Bit TI1_RMP.
	TIM_OR1_TI1_RMP = 0x10

	// CCMR3_Output: capture/compare mode register 2 (output mode)
	// Position of OC5M_3 field.
	TIM_CCMR3_Output_OC5M_3_Pos = 0x18
	// Bit mask of OC5M_3 field.
	TIM_CCMR3_Output_OC5M_3_Msk = 0x1000000
	// Bit OC5M_3.
	TIM_CCMR3_Output_OC5M_3 = 0x1000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR3_Output_OC5M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR3_Output_OC5M_3_Extended = 0x1
	// Position of OC6M_3 field.
	TIM_CCMR3_Output_OC6M_3_Pos = 0x20
	// Bit mask of OC6M_3 field.
	TIM_CCMR3_Output_OC6M_3_Msk = 0x100000000
	// Bit OC6M_3.
	TIM_CCMR3_Output_OC6M_3 = 0x100000000
	// Normal output compare mode (modes 0-7)
	TIM_CCMR3_Output_OC6M_3_Normal = 0x0
	// Extended output compare mode (modes 7-15)
	TIM_CCMR3_Output_OC6M_3_Extended = 0x1
	// Position of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Pos = 0xf
	// Bit mask of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Msk = 0x8000
	// Bit OC5CE.
	TIM_CCMR3_Output_OC5CE = 0x8000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR3_Output_OC5CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR3_Output_OC5CE_Enabled = 0x1
	// Position of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Pos = 0x17
	// Bit mask of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Msk = 0x800000
	// Bit OC6CE.
	TIM_CCMR3_Output_OC6CE = 0x800000
	// OCxRef is not affected by the ETRF signal
	TIM_CCMR3_Output_OC6CE_Disabled = 0x0
	// OCxRef is cleared as soon as a High level is detected on ETRF signal
	TIM_CCMR3_Output_OC6CE_Enabled = 0x1
	// Position of OC5M field.
	TIM_CCMR3_Output_OC5M_Pos = 0xc
	// Bit mask of OC5M field.
	TIM_CCMR3_Output_OC5M_Msk = 0x7000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR3_Output_OC5M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR3_Output_OC5M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR3_Output_OC5M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR3_Output_OC5M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR3_Output_OC5M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR3_Output_OC5M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR3_Output_OC5M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR3_Output_OC5M_PwmMode2 = 0x7
	// Position of OC6M field.
	TIM_CCMR3_Output_OC6M_Pos = 0x14
	// Bit mask of OC6M field.
	TIM_CCMR3_Output_OC6M_Msk = 0x700000
	// The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
	TIM_CCMR3_Output_OC6M_Frozen = 0x0
	// Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
	TIM_CCMR3_Output_OC6M_ActiveOnMatch = 0x1
	// Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
	TIM_CCMR3_Output_OC6M_InactiveOnMatch = 0x2
	// OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
	TIM_CCMR3_Output_OC6M_Toggle = 0x3
	// OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
	TIM_CCMR3_Output_OC6M_ForceInactive = 0x4
	// OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
	TIM_CCMR3_Output_OC6M_ForceActive = 0x5
	// In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
	TIM_CCMR3_Output_OC6M_PwmMode1 = 0x6
	// Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
	TIM_CCMR3_Output_OC6M_PwmMode2 = 0x7
	// Position of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Pos = 0xb
	// Bit mask of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Msk = 0x800
	// Bit OC5PE.
	TIM_CCMR3_Output_OC5PE = 0x800
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR3_Output_OC5PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR3_Output_OC5PE_Enabled = 0x1
	// Position of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Pos = 0x13
	// Bit mask of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Msk = 0x80000
	// Bit OC6PE.
	TIM_CCMR3_Output_OC6PE = 0x80000
	// Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
	TIM_CCMR3_Output_OC6PE_Disabled = 0x0
	// Preload register on CCRx enabled. Preload value is loaded into active register on each update event
	TIM_CCMR3_Output_OC6PE_Enabled = 0x1
	// Position of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Pos = 0xa
	// Bit mask of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Msk = 0x400
	// Bit OC5FE.
	TIM_CCMR3_Output_OC5FE = 0x400
	// Fast output disabled
	TIM_CCMR3_Output_OC5FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR3_Output_OC5FE_Enabled = 0x1
	// Position of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Pos = 0x12
	// Bit mask of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Msk = 0x40000
	// Bit OC6FE.
	TIM_CCMR3_Output_OC6FE = 0x40000
	// Fast output disabled
	TIM_CCMR3_Output_OC6FE_Disabled = 0x0
	// Fast output enabled
	TIM_CCMR3_Output_OC6FE_Enabled = 0x1

	// CCR5: capture/compare register
	// Position of CCR field.
	TIM_CCR5_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR5_CCR_Msk = 0xffff
	// Position of GC5C1 field.
	TIM_CCR5_GC5C1_Pos = 0x1d
	// Bit mask of GC5C1 field.
	TIM_CCR5_GC5C1_Msk = 0x20000000
	// Bit GC5C1.
	TIM_CCR5_GC5C1 = 0x20000000
	// Position of GC5C2 field.
	TIM_CCR5_GC5C2_Pos = 0x1e
	// Bit mask of GC5C2 field.
	TIM_CCR5_GC5C2_Msk = 0x40000000
	// Bit GC5C2.
	TIM_CCR5_GC5C2 = 0x40000000
	// Position of GC5C3 field.
	TIM_CCR5_GC5C3_Pos = 0x1f
	// Bit mask of GC5C3 field.
	TIM_CCR5_GC5C3_Msk = 0x80000000
	// Bit GC5C3.
	TIM_CCR5_GC5C3 = 0x80000000

	// CCR6: capture/compare register
	// Position of CCR field.
	TIM_CCR6_CCR_Pos = 0x0
	// Bit mask of CCR field.
	TIM_CCR6_CCR_Msk = 0xffff

	// OR2: DMA address for full transfer
	// Position of BKINE field.
	TIM_OR2_BKINE_Pos = 0x0
	// Bit mask of BKINE field.
	TIM_OR2_BKINE_Msk = 0x1
	// Bit BKINE.
	TIM_OR2_BKINE = 0x1
	// Position of BKCMP1E field.
	TIM_OR2_BKCMP1E_Pos = 0x1
	// Bit mask of BKCMP1E field.
	TIM_OR2_BKCMP1E_Msk = 0x2
	// Bit BKCMP1E.
	TIM_OR2_BKCMP1E = 0x2
	// Position of BKCMP2E field.
	TIM_OR2_BKCMP2E_Pos = 0x2
	// Bit mask of BKCMP2E field.
	TIM_OR2_BKCMP2E_Msk = 0x4
	// Bit BKCMP2E.
	TIM_OR2_BKCMP2E = 0x4
	// Position of BKDFBK0E field.
	TIM_OR2_BKDFBK0E_Pos = 0x8
	// Bit mask of BKDFBK0E field.
	TIM_OR2_BKDFBK0E_Msk = 0x100
	// Bit BKDFBK0E.
	TIM_OR2_BKDFBK0E = 0x100
	// Position of BKINP field.
	TIM_OR2_BKINP_Pos = 0x9
	// Bit mask of BKINP field.
	TIM_OR2_BKINP_Msk = 0x200
	// Bit BKINP.
	TIM_OR2_BKINP = 0x200
	// Position of BKCMP1P field.
	TIM_OR2_BKCMP1P_Pos = 0xa
	// Bit mask of BKCMP1P field.
	TIM_OR2_BKCMP1P_Msk = 0x400
	// Bit BKCMP1P.
	TIM_OR2_BKCMP1P = 0x400
	// Position of BKCMP2P field.
	TIM_OR2_BKCMP2P_Pos = 0xb
	// Bit mask of BKCMP2P field.
	TIM_OR2_BKCMP2P_Msk = 0x800
	// Bit BKCMP2P.
	TIM_OR2_BKCMP2P = 0x800
	// Position of ETRSEL field.
	TIM_OR2_ETRSEL_Pos = 0xe
	// Bit mask of ETRSEL field.
	TIM_OR2_ETRSEL_Msk = 0x1c000

	// OR3: DMA address for full transfer
	// Position of BK2INE field.
	TIM_OR3_BK2INE_Pos = 0x0
	// Bit mask of BK2INE field.
	TIM_OR3_BK2INE_Msk = 0x1
	// Bit BK2INE.
	TIM_OR3_BK2INE = 0x1
	// Position of BK2CMP1E field.
	TIM_OR3_BK2CMP1E_Pos = 0x1
	// Bit mask of BK2CMP1E field.
	TIM_OR3_BK2CMP1E_Msk = 0x2
	// Bit BK2CMP1E.
	TIM_OR3_BK2CMP1E = 0x2
	// Position of BK2CMP2E field.
	TIM_OR3_BK2CMP2E_Pos = 0x2
	// Bit mask of BK2CMP2E field.
	TIM_OR3_BK2CMP2E_Msk = 0x4
	// Bit BK2CMP2E.
	TIM_OR3_BK2CMP2E = 0x4
	// Position of BK2DFBK0E field.
	TIM_OR3_BK2DFBK0E_Pos = 0x8
	// Bit mask of BK2DFBK0E field.
	TIM_OR3_BK2DFBK0E_Msk = 0x100
	// Bit BK2DFBK0E.
	TIM_OR3_BK2DFBK0E = 0x100
	// Position of BK2INP field.
	TIM_OR3_BK2INP_Pos = 0x9
	// Bit mask of BK2INP field.
	TIM_OR3_BK2INP_Msk = 0x200
	// Bit BK2INP.
	TIM_OR3_BK2INP = 0x200
	// Position of BK2CMP1P field.
	TIM_OR3_BK2CMP1P_Pos = 0xa
	// Bit mask of BK2CMP1P field.
	TIM_OR3_BK2CMP1P_Msk = 0x400
	// Bit BK2CMP1P.
	TIM_OR3_BK2CMP1P = 0x400
	// Position of BK2CMP2P field.
	TIM_OR3_BK2CMP2P_Pos = 0xb
	// Bit mask of BK2CMP2P field.
	TIM_OR3_BK2CMP2P_Msk = 0x800
	// Bit BK2CMP2P.
	TIM_OR3_BK2CMP2P = 0x800
)

// Constants for TSC: Touch sensing controller
const (
	// CR: control register
	// Position of CTPH field.
	TSC_CR_CTPH_Pos = 0x1c
	// Bit mask of CTPH field.
	TSC_CR_CTPH_Msk = 0xf0000000
	// Position of CTPL field.
	TSC_CR_CTPL_Pos = 0x18
	// Bit mask of CTPL field.
	TSC_CR_CTPL_Msk = 0xf000000
	// Position of SSD field.
	TSC_CR_SSD_Pos = 0x11
	// Bit mask of SSD field.
	TSC_CR_SSD_Msk = 0xfe0000
	// Position of SSE field.
	TSC_CR_SSE_Pos = 0x10
	// Bit mask of SSE field.
	TSC_CR_SSE_Msk = 0x10000
	// Bit SSE.
	TSC_CR_SSE = 0x10000
	// Spread spectrum disabled
	TSC_CR_SSE_Disabled = 0x0
	// Spread spectrum enabled
	TSC_CR_SSE_Enabled = 0x1
	// Position of SSPSC field.
	TSC_CR_SSPSC_Pos = 0xf
	// Bit mask of SSPSC field.
	TSC_CR_SSPSC_Msk = 0x8000
	// Bit SSPSC.
	TSC_CR_SSPSC = 0x8000
	// Position of PGPSC field.
	TSC_CR_PGPSC_Pos = 0xc
	// Bit mask of PGPSC field.
	TSC_CR_PGPSC_Msk = 0x7000
	// Position of MCV field.
	TSC_CR_MCV_Pos = 0x5
	// Bit mask of MCV field.
	TSC_CR_MCV_Msk = 0xe0
	// Position of IODEF field.
	TSC_CR_IODEF_Pos = 0x4
	// Bit mask of IODEF field.
	TSC_CR_IODEF_Msk = 0x10
	// Bit IODEF.
	TSC_CR_IODEF = 0x10
	// I/Os are forced to output push-pull low
	TSC_CR_IODEF_PushPull = 0x0
	// I/Os are in input floating
	TSC_CR_IODEF_Floating = 0x1
	// Position of SYNCPOL field.
	TSC_CR_SYNCPOL_Pos = 0x3
	// Bit mask of SYNCPOL field.
	TSC_CR_SYNCPOL_Msk = 0x8
	// Bit SYNCPOL.
	TSC_CR_SYNCPOL = 0x8
	// Falling edge only
	TSC_CR_SYNCPOL_FallingEdge = 0x0
	// Rising edge and high level
	TSC_CR_SYNCPOL_RisingEdge = 0x1
	// Position of AM field.
	TSC_CR_AM_Pos = 0x2
	// Bit mask of AM field.
	TSC_CR_AM_Msk = 0x4
	// Bit AM.
	TSC_CR_AM = 0x4
	// Normal acquisition mode (acquisition starts as soon as START bit is set)
	TSC_CR_AM_Normal = 0x0
	// Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin)
	TSC_CR_AM_Synchronized = 0x1
	// Position of START field.
	TSC_CR_START_Pos = 0x1
	// Bit mask of START field.
	TSC_CR_START_Msk = 0x2
	// Bit START.
	TSC_CR_START = 0x2
	// Acquisition not started
	TSC_CR_START_NoStarted = 0x0
	// Start a new acquisition
	TSC_CR_START_Started = 0x1
	// Position of TSCE field.
	TSC_CR_TSCE_Pos = 0x0
	// Bit mask of TSCE field.
	TSC_CR_TSCE_Msk = 0x1
	// Bit TSCE.
	TSC_CR_TSCE = 0x1
	// Touch sensing controller disabled
	TSC_CR_TSCE_Disabled = 0x0
	// Touch sensing controller enabled
	TSC_CR_TSCE_Enabled = 0x1

	// IER: interrupt enable register
	// Position of MCEIE field.
	TSC_IER_MCEIE_Pos = 0x1
	// Bit mask of MCEIE field.
	TSC_IER_MCEIE_Msk = 0x2
	// Bit MCEIE.
	TSC_IER_MCEIE = 0x2
	// Max count error interrupt disabled
	TSC_IER_MCEIE_Disabled = 0x0
	// Max count error interrupt enabled
	TSC_IER_MCEIE_Enabled = 0x1
	// Position of EOAIE field.
	TSC_IER_EOAIE_Pos = 0x0
	// Bit mask of EOAIE field.
	TSC_IER_EOAIE_Msk = 0x1
	// Bit EOAIE.
	TSC_IER_EOAIE = 0x1
	// End of acquisition interrupt disabled
	TSC_IER_EOAIE_Disabled = 0x0
	// End of acquisition interrupt enabled
	TSC_IER_EOAIE_Enabled = 0x1

	// ICR: interrupt clear register
	// Position of MCEIC field.
	TSC_ICR_MCEIC_Pos = 0x1
	// Bit mask of MCEIC field.
	TSC_ICR_MCEIC_Msk = 0x2
	// Bit MCEIC.
	TSC_ICR_MCEIC = 0x2
	// Position of EOAIC field.
	TSC_ICR_EOAIC_Pos = 0x0
	// Bit mask of EOAIC field.
	TSC_ICR_EOAIC_Msk = 0x1
	// Bit EOAIC.
	TSC_ICR_EOAIC = 0x1

	// ISR: interrupt status register
	// Position of MCEF field.
	TSC_ISR_MCEF_Pos = 0x1
	// Bit mask of MCEF field.
	TSC_ISR_MCEF_Msk = 0x2
	// Bit MCEF.
	TSC_ISR_MCEF = 0x2
	// Position of EOAF field.
	TSC_ISR_EOAF_Pos = 0x0
	// Bit mask of EOAF field.
	TSC_ISR_EOAF_Msk = 0x1
	// Bit EOAF.
	TSC_ISR_EOAF = 0x1

	// IOHCR: I/O hysteresis control register
	// Position of G1_IO1 field.
	TSC_IOHCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOHCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOHCR_G1_IO1 = 0x10
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOHCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOHCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOHCR_G2_IO1 = 0x100
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOHCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOHCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOHCR_G3_IO1 = 0x1000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOHCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOHCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOHCR_G4_IO1 = 0x10000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOHCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOHCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOHCR_G5_IO1 = 0x100000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOHCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOHCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOHCR_G6_IO1 = 0x1000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOHCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOHCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOHCR_G7_IO1 = 0x10000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOHCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOHCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOHCR_G8_IO1 = 0x100000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO1_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOHCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOHCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOHCR_G1_IO4 = 0x80
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOHCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOHCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOHCR_G2_IO4 = 0x800
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOHCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOHCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOHCR_G3_IO4 = 0x8000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOHCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOHCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOHCR_G4_IO4 = 0x80000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOHCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOHCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOHCR_G5_IO4 = 0x800000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOHCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOHCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOHCR_G6_IO4 = 0x8000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOHCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOHCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOHCR_G7_IO4 = 0x80000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOHCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOHCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOHCR_G8_IO4 = 0x800000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO4_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOHCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOHCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOHCR_G1_IO3 = 0x40
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOHCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOHCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOHCR_G2_IO3 = 0x400
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOHCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOHCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOHCR_G3_IO3 = 0x4000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOHCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOHCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOHCR_G4_IO3 = 0x40000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOHCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOHCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOHCR_G5_IO3 = 0x400000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOHCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOHCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOHCR_G6_IO3 = 0x4000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOHCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOHCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOHCR_G7_IO3 = 0x40000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOHCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOHCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOHCR_G8_IO3 = 0x400000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO3_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOHCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOHCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOHCR_G1_IO2 = 0x20
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G1_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOHCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOHCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOHCR_G2_IO2 = 0x200
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G2_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOHCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOHCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOHCR_G3_IO2 = 0x2000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G3_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOHCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOHCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOHCR_G4_IO2 = 0x20000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G4_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOHCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOHCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOHCR_G5_IO2 = 0x200000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G5_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOHCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOHCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOHCR_G6_IO2 = 0x2000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G6_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOHCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOHCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOHCR_G7_IO2 = 0x20000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G7_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOHCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOHCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOHCR_G8_IO2 = 0x200000000
	// Gx_IOy Schmitt trigger hysteresis disabled
	TSC_IOHCR_G8_IO2_Disabled = 0x0
	// Gx_IOy Schmitt trigger hysteresis enabled
	TSC_IOHCR_G8_IO2_Enabled = 0x1

	// IOASCR: I/O analog switch control register
	// Position of G1_IO1 field.
	TSC_IOASCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOASCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOASCR_G1_IO1 = 0x10
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOASCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOASCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOASCR_G2_IO1 = 0x100
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOASCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOASCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOASCR_G3_IO1 = 0x1000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOASCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOASCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOASCR_G4_IO1 = 0x10000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOASCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOASCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOASCR_G5_IO1 = 0x100000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOASCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOASCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOASCR_G6_IO1 = 0x1000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOASCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOASCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOASCR_G7_IO1 = 0x10000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOASCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOASCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOASCR_G8_IO1 = 0x100000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO1_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOASCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOASCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOASCR_G1_IO4 = 0x80
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOASCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOASCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOASCR_G2_IO4 = 0x800
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOASCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOASCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOASCR_G3_IO4 = 0x8000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOASCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOASCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOASCR_G4_IO4 = 0x80000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOASCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOASCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOASCR_G5_IO4 = 0x800000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOASCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOASCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOASCR_G6_IO4 = 0x8000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOASCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOASCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOASCR_G7_IO4 = 0x80000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOASCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOASCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOASCR_G8_IO4 = 0x800000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO4_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOASCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOASCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOASCR_G1_IO3 = 0x40
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOASCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOASCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOASCR_G2_IO3 = 0x400
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOASCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOASCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOASCR_G3_IO3 = 0x4000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOASCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOASCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOASCR_G4_IO3 = 0x40000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOASCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOASCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOASCR_G5_IO3 = 0x400000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOASCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOASCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOASCR_G6_IO3 = 0x4000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOASCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOASCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOASCR_G7_IO3 = 0x40000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOASCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOASCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOASCR_G8_IO3 = 0x400000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO3_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOASCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOASCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOASCR_G1_IO2 = 0x20
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G1_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOASCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOASCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOASCR_G2_IO2 = 0x200
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G2_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOASCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOASCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOASCR_G3_IO2 = 0x2000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G3_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOASCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOASCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOASCR_G4_IO2 = 0x20000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G4_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOASCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOASCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOASCR_G5_IO2 = 0x200000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G5_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOASCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOASCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOASCR_G6_IO2 = 0x2000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G6_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOASCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOASCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOASCR_G7_IO2 = 0x20000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G7_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOASCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOASCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOASCR_G8_IO2 = 0x200000000
	// Gx_IOy analog switch disabled (opened)
	TSC_IOASCR_G8_IO2_Disabled = 0x0
	// Gx_IOy analog switch enabled (closed)
	TSC_IOASCR_G8_IO2_Enabled = 0x1

	// IOSCR: I/O sampling control register
	// Position of G1_IO1 field.
	TSC_IOSCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOSCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOSCR_G1_IO1 = 0x10
	// Gx_IOy unused
	TSC_IOSCR_G1_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOSCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOSCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOSCR_G2_IO1 = 0x100
	// Gx_IOy unused
	TSC_IOSCR_G2_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOSCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOSCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOSCR_G3_IO1 = 0x1000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOSCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOSCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOSCR_G4_IO1 = 0x10000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOSCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOSCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOSCR_G5_IO1 = 0x100000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOSCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOSCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOSCR_G6_IO1 = 0x1000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOSCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOSCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOSCR_G7_IO1 = 0x10000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOSCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOSCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOSCR_G8_IO1 = 0x100000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO1_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOSCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOSCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOSCR_G1_IO4 = 0x80
	// Gx_IOy unused
	TSC_IOSCR_G1_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOSCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOSCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOSCR_G2_IO4 = 0x800
	// Gx_IOy unused
	TSC_IOSCR_G2_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOSCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOSCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOSCR_G3_IO4 = 0x8000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOSCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOSCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOSCR_G4_IO4 = 0x80000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOSCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOSCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOSCR_G5_IO4 = 0x800000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOSCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOSCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOSCR_G6_IO4 = 0x8000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOSCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOSCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOSCR_G7_IO4 = 0x80000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOSCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOSCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOSCR_G8_IO4 = 0x800000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO4_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOSCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOSCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOSCR_G1_IO3 = 0x40
	// Gx_IOy unused
	TSC_IOSCR_G1_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOSCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOSCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOSCR_G2_IO3 = 0x400
	// Gx_IOy unused
	TSC_IOSCR_G2_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOSCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOSCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOSCR_G3_IO3 = 0x4000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOSCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOSCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOSCR_G4_IO3 = 0x40000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOSCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOSCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOSCR_G5_IO3 = 0x400000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOSCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOSCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOSCR_G6_IO3 = 0x4000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOSCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOSCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOSCR_G7_IO3 = 0x40000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOSCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOSCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOSCR_G8_IO3 = 0x400000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO3_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOSCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOSCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOSCR_G1_IO2 = 0x20
	// Gx_IOy unused
	TSC_IOSCR_G1_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOSCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOSCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOSCR_G2_IO2 = 0x200
	// Gx_IOy unused
	TSC_IOSCR_G2_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOSCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOSCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOSCR_G3_IO2 = 0x2000
	// Gx_IOy unused
	TSC_IOSCR_G3_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOSCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOSCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOSCR_G4_IO2 = 0x20000
	// Gx_IOy unused
	TSC_IOSCR_G4_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOSCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOSCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOSCR_G5_IO2 = 0x200000
	// Gx_IOy unused
	TSC_IOSCR_G5_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOSCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOSCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOSCR_G6_IO2 = 0x2000000
	// Gx_IOy unused
	TSC_IOSCR_G6_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOSCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOSCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOSCR_G7_IO2 = 0x20000000
	// Gx_IOy unused
	TSC_IOSCR_G7_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOSCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOSCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOSCR_G8_IO2 = 0x200000000
	// Gx_IOy unused
	TSC_IOSCR_G8_IO2_Disabled = 0x0
	// Gx_IOy used as sampling capacitor
	TSC_IOSCR_G8_IO2_Enabled = 0x1

	// IOCCR: I/O channel control register
	// Position of G1_IO1 field.
	TSC_IOCCR_G1_IO1_Pos = 0x4
	// Bit mask of G1_IO1 field.
	TSC_IOCCR_G1_IO1_Msk = 0x10
	// Bit G1_IO1.
	TSC_IOCCR_G1_IO1 = 0x10
	// Gx_IOy unused
	TSC_IOCCR_G1_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO1_Enabled = 0x1
	// Position of G2_IO1 field.
	TSC_IOCCR_G2_IO1_Pos = 0x8
	// Bit mask of G2_IO1 field.
	TSC_IOCCR_G2_IO1_Msk = 0x100
	// Bit G2_IO1.
	TSC_IOCCR_G2_IO1 = 0x100
	// Gx_IOy unused
	TSC_IOCCR_G2_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO1_Enabled = 0x1
	// Position of G3_IO1 field.
	TSC_IOCCR_G3_IO1_Pos = 0xc
	// Bit mask of G3_IO1 field.
	TSC_IOCCR_G3_IO1_Msk = 0x1000
	// Bit G3_IO1.
	TSC_IOCCR_G3_IO1 = 0x1000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO1_Enabled = 0x1
	// Position of G4_IO1 field.
	TSC_IOCCR_G4_IO1_Pos = 0x10
	// Bit mask of G4_IO1 field.
	TSC_IOCCR_G4_IO1_Msk = 0x10000
	// Bit G4_IO1.
	TSC_IOCCR_G4_IO1 = 0x10000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO1_Enabled = 0x1
	// Position of G5_IO1 field.
	TSC_IOCCR_G5_IO1_Pos = 0x14
	// Bit mask of G5_IO1 field.
	TSC_IOCCR_G5_IO1_Msk = 0x100000
	// Bit G5_IO1.
	TSC_IOCCR_G5_IO1 = 0x100000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO1_Enabled = 0x1
	// Position of G6_IO1 field.
	TSC_IOCCR_G6_IO1_Pos = 0x18
	// Bit mask of G6_IO1 field.
	TSC_IOCCR_G6_IO1_Msk = 0x1000000
	// Bit G6_IO1.
	TSC_IOCCR_G6_IO1 = 0x1000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO1_Enabled = 0x1
	// Position of G7_IO1 field.
	TSC_IOCCR_G7_IO1_Pos = 0x1c
	// Bit mask of G7_IO1 field.
	TSC_IOCCR_G7_IO1_Msk = 0x10000000
	// Bit G7_IO1.
	TSC_IOCCR_G7_IO1 = 0x10000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO1_Enabled = 0x1
	// Position of G8_IO1 field.
	TSC_IOCCR_G8_IO1_Pos = 0x20
	// Bit mask of G8_IO1 field.
	TSC_IOCCR_G8_IO1_Msk = 0x100000000
	// Bit G8_IO1.
	TSC_IOCCR_G8_IO1 = 0x100000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO1_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO1_Enabled = 0x1
	// Position of G1_IO4 field.
	TSC_IOCCR_G1_IO4_Pos = 0x7
	// Bit mask of G1_IO4 field.
	TSC_IOCCR_G1_IO4_Msk = 0x80
	// Bit G1_IO4.
	TSC_IOCCR_G1_IO4 = 0x80
	// Gx_IOy unused
	TSC_IOCCR_G1_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO4_Enabled = 0x1
	// Position of G2_IO4 field.
	TSC_IOCCR_G2_IO4_Pos = 0xb
	// Bit mask of G2_IO4 field.
	TSC_IOCCR_G2_IO4_Msk = 0x800
	// Bit G2_IO4.
	TSC_IOCCR_G2_IO4 = 0x800
	// Gx_IOy unused
	TSC_IOCCR_G2_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO4_Enabled = 0x1
	// Position of G3_IO4 field.
	TSC_IOCCR_G3_IO4_Pos = 0xf
	// Bit mask of G3_IO4 field.
	TSC_IOCCR_G3_IO4_Msk = 0x8000
	// Bit G3_IO4.
	TSC_IOCCR_G3_IO4 = 0x8000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO4_Enabled = 0x1
	// Position of G4_IO4 field.
	TSC_IOCCR_G4_IO4_Pos = 0x13
	// Bit mask of G4_IO4 field.
	TSC_IOCCR_G4_IO4_Msk = 0x80000
	// Bit G4_IO4.
	TSC_IOCCR_G4_IO4 = 0x80000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO4_Enabled = 0x1
	// Position of G5_IO4 field.
	TSC_IOCCR_G5_IO4_Pos = 0x17
	// Bit mask of G5_IO4 field.
	TSC_IOCCR_G5_IO4_Msk = 0x800000
	// Bit G5_IO4.
	TSC_IOCCR_G5_IO4 = 0x800000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO4_Enabled = 0x1
	// Position of G6_IO4 field.
	TSC_IOCCR_G6_IO4_Pos = 0x1b
	// Bit mask of G6_IO4 field.
	TSC_IOCCR_G6_IO4_Msk = 0x8000000
	// Bit G6_IO4.
	TSC_IOCCR_G6_IO4 = 0x8000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO4_Enabled = 0x1
	// Position of G7_IO4 field.
	TSC_IOCCR_G7_IO4_Pos = 0x1f
	// Bit mask of G7_IO4 field.
	TSC_IOCCR_G7_IO4_Msk = 0x80000000
	// Bit G7_IO4.
	TSC_IOCCR_G7_IO4 = 0x80000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO4_Enabled = 0x1
	// Position of G8_IO4 field.
	TSC_IOCCR_G8_IO4_Pos = 0x23
	// Bit mask of G8_IO4 field.
	TSC_IOCCR_G8_IO4_Msk = 0x800000000
	// Bit G8_IO4.
	TSC_IOCCR_G8_IO4 = 0x800000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO4_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO4_Enabled = 0x1
	// Position of G1_IO3 field.
	TSC_IOCCR_G1_IO3_Pos = 0x6
	// Bit mask of G1_IO3 field.
	TSC_IOCCR_G1_IO3_Msk = 0x40
	// Bit G1_IO3.
	TSC_IOCCR_G1_IO3 = 0x40
	// Gx_IOy unused
	TSC_IOCCR_G1_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO3_Enabled = 0x1
	// Position of G2_IO3 field.
	TSC_IOCCR_G2_IO3_Pos = 0xa
	// Bit mask of G2_IO3 field.
	TSC_IOCCR_G2_IO3_Msk = 0x400
	// Bit G2_IO3.
	TSC_IOCCR_G2_IO3 = 0x400
	// Gx_IOy unused
	TSC_IOCCR_G2_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO3_Enabled = 0x1
	// Position of G3_IO3 field.
	TSC_IOCCR_G3_IO3_Pos = 0xe
	// Bit mask of G3_IO3 field.
	TSC_IOCCR_G3_IO3_Msk = 0x4000
	// Bit G3_IO3.
	TSC_IOCCR_G3_IO3 = 0x4000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO3_Enabled = 0x1
	// Position of G4_IO3 field.
	TSC_IOCCR_G4_IO3_Pos = 0x12
	// Bit mask of G4_IO3 field.
	TSC_IOCCR_G4_IO3_Msk = 0x40000
	// Bit G4_IO3.
	TSC_IOCCR_G4_IO3 = 0x40000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO3_Enabled = 0x1
	// Position of G5_IO3 field.
	TSC_IOCCR_G5_IO3_Pos = 0x16
	// Bit mask of G5_IO3 field.
	TSC_IOCCR_G5_IO3_Msk = 0x400000
	// Bit G5_IO3.
	TSC_IOCCR_G5_IO3 = 0x400000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO3_Enabled = 0x1
	// Position of G6_IO3 field.
	TSC_IOCCR_G6_IO3_Pos = 0x1a
	// Bit mask of G6_IO3 field.
	TSC_IOCCR_G6_IO3_Msk = 0x4000000
	// Bit G6_IO3.
	TSC_IOCCR_G6_IO3 = 0x4000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO3_Enabled = 0x1
	// Position of G7_IO3 field.
	TSC_IOCCR_G7_IO3_Pos = 0x1e
	// Bit mask of G7_IO3 field.
	TSC_IOCCR_G7_IO3_Msk = 0x40000000
	// Bit G7_IO3.
	TSC_IOCCR_G7_IO3 = 0x40000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO3_Enabled = 0x1
	// Position of G8_IO3 field.
	TSC_IOCCR_G8_IO3_Pos = 0x22
	// Bit mask of G8_IO3 field.
	TSC_IOCCR_G8_IO3_Msk = 0x400000000
	// Bit G8_IO3.
	TSC_IOCCR_G8_IO3 = 0x400000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO3_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO3_Enabled = 0x1
	// Position of G1_IO2 field.
	TSC_IOCCR_G1_IO2_Pos = 0x5
	// Bit mask of G1_IO2 field.
	TSC_IOCCR_G1_IO2_Msk = 0x20
	// Bit G1_IO2.
	TSC_IOCCR_G1_IO2 = 0x20
	// Gx_IOy unused
	TSC_IOCCR_G1_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G1_IO2_Enabled = 0x1
	// Position of G2_IO2 field.
	TSC_IOCCR_G2_IO2_Pos = 0x9
	// Bit mask of G2_IO2 field.
	TSC_IOCCR_G2_IO2_Msk = 0x200
	// Bit G2_IO2.
	TSC_IOCCR_G2_IO2 = 0x200
	// Gx_IOy unused
	TSC_IOCCR_G2_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G2_IO2_Enabled = 0x1
	// Position of G3_IO2 field.
	TSC_IOCCR_G3_IO2_Pos = 0xd
	// Bit mask of G3_IO2 field.
	TSC_IOCCR_G3_IO2_Msk = 0x2000
	// Bit G3_IO2.
	TSC_IOCCR_G3_IO2 = 0x2000
	// Gx_IOy unused
	TSC_IOCCR_G3_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G3_IO2_Enabled = 0x1
	// Position of G4_IO2 field.
	TSC_IOCCR_G4_IO2_Pos = 0x11
	// Bit mask of G4_IO2 field.
	TSC_IOCCR_G4_IO2_Msk = 0x20000
	// Bit G4_IO2.
	TSC_IOCCR_G4_IO2 = 0x20000
	// Gx_IOy unused
	TSC_IOCCR_G4_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G4_IO2_Enabled = 0x1
	// Position of G5_IO2 field.
	TSC_IOCCR_G5_IO2_Pos = 0x15
	// Bit mask of G5_IO2 field.
	TSC_IOCCR_G5_IO2_Msk = 0x200000
	// Bit G5_IO2.
	TSC_IOCCR_G5_IO2 = 0x200000
	// Gx_IOy unused
	TSC_IOCCR_G5_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G5_IO2_Enabled = 0x1
	// Position of G6_IO2 field.
	TSC_IOCCR_G6_IO2_Pos = 0x19
	// Bit mask of G6_IO2 field.
	TSC_IOCCR_G6_IO2_Msk = 0x2000000
	// Bit G6_IO2.
	TSC_IOCCR_G6_IO2 = 0x2000000
	// Gx_IOy unused
	TSC_IOCCR_G6_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G6_IO2_Enabled = 0x1
	// Position of G7_IO2 field.
	TSC_IOCCR_G7_IO2_Pos = 0x1d
	// Bit mask of G7_IO2 field.
	TSC_IOCCR_G7_IO2_Msk = 0x20000000
	// Bit G7_IO2.
	TSC_IOCCR_G7_IO2 = 0x20000000
	// Gx_IOy unused
	TSC_IOCCR_G7_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G7_IO2_Enabled = 0x1
	// Position of G8_IO2 field.
	TSC_IOCCR_G8_IO2_Pos = 0x21
	// Bit mask of G8_IO2 field.
	TSC_IOCCR_G8_IO2_Msk = 0x200000000
	// Bit G8_IO2.
	TSC_IOCCR_G8_IO2 = 0x200000000
	// Gx_IOy unused
	TSC_IOCCR_G8_IO2_Disabled = 0x0
	// Gx_IOy used as channel
	TSC_IOCCR_G8_IO2_Enabled = 0x1

	// IOGCSR: I/O group control status register
	// Position of G1S field.
	TSC_IOGCSR_G1S_Pos = 0x11
	// Bit mask of G1S field.
	TSC_IOGCSR_G1S_Msk = 0x20000
	// Bit G1S.
	TSC_IOGCSR_G1S = 0x20000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G1S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G1S_Complete = 0x1
	// Position of G2S field.
	TSC_IOGCSR_G2S_Pos = 0x12
	// Bit mask of G2S field.
	TSC_IOGCSR_G2S_Msk = 0x40000
	// Bit G2S.
	TSC_IOGCSR_G2S = 0x40000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G2S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G2S_Complete = 0x1
	// Position of G3S field.
	TSC_IOGCSR_G3S_Pos = 0x13
	// Bit mask of G3S field.
	TSC_IOGCSR_G3S_Msk = 0x80000
	// Bit G3S.
	TSC_IOGCSR_G3S = 0x80000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G3S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G3S_Complete = 0x1
	// Position of G4S field.
	TSC_IOGCSR_G4S_Pos = 0x14
	// Bit mask of G4S field.
	TSC_IOGCSR_G4S_Msk = 0x100000
	// Bit G4S.
	TSC_IOGCSR_G4S = 0x100000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G4S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G4S_Complete = 0x1
	// Position of G5S field.
	TSC_IOGCSR_G5S_Pos = 0x15
	// Bit mask of G5S field.
	TSC_IOGCSR_G5S_Msk = 0x200000
	// Bit G5S.
	TSC_IOGCSR_G5S = 0x200000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G5S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G5S_Complete = 0x1
	// Position of G6S field.
	TSC_IOGCSR_G6S_Pos = 0x16
	// Bit mask of G6S field.
	TSC_IOGCSR_G6S_Msk = 0x400000
	// Bit G6S.
	TSC_IOGCSR_G6S = 0x400000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G6S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G6S_Complete = 0x1
	// Position of G7S field.
	TSC_IOGCSR_G7S_Pos = 0x17
	// Bit mask of G7S field.
	TSC_IOGCSR_G7S_Msk = 0x800000
	// Bit G7S.
	TSC_IOGCSR_G7S = 0x800000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G7S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G7S_Complete = 0x1
	// Position of G8S field.
	TSC_IOGCSR_G8S_Pos = 0x18
	// Bit mask of G8S field.
	TSC_IOGCSR_G8S_Msk = 0x1000000
	// Bit G8S.
	TSC_IOGCSR_G8S = 0x1000000
	// Acquisition on analog I/O group x is ongoing or not started
	TSC_IOGCSR_G8S_Ongoing = 0x0
	// Acquisition on analog I/O group x is complete
	TSC_IOGCSR_G8S_Complete = 0x1
	// Position of G1E field.
	TSC_IOGCSR_G1E_Pos = 0x1
	// Bit mask of G1E field.
	TSC_IOGCSR_G1E_Msk = 0x2
	// Bit G1E.
	TSC_IOGCSR_G1E = 0x2
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G1E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G1E_Enabled = 0x1
	// Position of G2E field.
	TSC_IOGCSR_G2E_Pos = 0x2
	// Bit mask of G2E field.
	TSC_IOGCSR_G2E_Msk = 0x4
	// Bit G2E.
	TSC_IOGCSR_G2E = 0x4
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G2E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G2E_Enabled = 0x1
	// Position of G3E field.
	TSC_IOGCSR_G3E_Pos = 0x3
	// Bit mask of G3E field.
	TSC_IOGCSR_G3E_Msk = 0x8
	// Bit G3E.
	TSC_IOGCSR_G3E = 0x8
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G3E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G3E_Enabled = 0x1
	// Position of G4E field.
	TSC_IOGCSR_G4E_Pos = 0x4
	// Bit mask of G4E field.
	TSC_IOGCSR_G4E_Msk = 0x10
	// Bit G4E.
	TSC_IOGCSR_G4E = 0x10
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G4E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G4E_Enabled = 0x1
	// Position of G5E field.
	TSC_IOGCSR_G5E_Pos = 0x5
	// Bit mask of G5E field.
	TSC_IOGCSR_G5E_Msk = 0x20
	// Bit G5E.
	TSC_IOGCSR_G5E = 0x20
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G5E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G5E_Enabled = 0x1
	// Position of G6E field.
	TSC_IOGCSR_G6E_Pos = 0x6
	// Bit mask of G6E field.
	TSC_IOGCSR_G6E_Msk = 0x40
	// Bit G6E.
	TSC_IOGCSR_G6E = 0x40
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G6E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G6E_Enabled = 0x1
	// Position of G7E field.
	TSC_IOGCSR_G7E_Pos = 0x7
	// Bit mask of G7E field.
	TSC_IOGCSR_G7E_Msk = 0x80
	// Bit G7E.
	TSC_IOGCSR_G7E = 0x80
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G7E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G7E_Enabled = 0x1
	// Position of G8E field.
	TSC_IOGCSR_G8E_Pos = 0x8
	// Bit mask of G8E field.
	TSC_IOGCSR_G8E_Msk = 0x100
	// Bit G8E.
	TSC_IOGCSR_G8E = 0x100
	// Acquisition on analog I/O group x disabled
	TSC_IOGCSR_G8E_Disabled = 0x0
	// Acquisition on analog I/O group x enabled
	TSC_IOGCSR_G8E_Enabled = 0x1

	// IOG1CR: I/O group x counter register
	// Position of CNT field.
	TSC_IOGCR_CNT_Pos = 0x0
	// Bit mask of CNT field.
	TSC_IOGCR_CNT_Msk = 0x3fff
)

// Constants for USB: Universal serial bus full-speed device interface
const (
	// EP0R: endpoint %s register
	// Position of EA field.
	USB_EPR_EA_Pos = 0x0
	// Bit mask of EA field.
	USB_EPR_EA_Msk = 0xf
	// Position of STAT_TX field.
	USB_EPR_STAT_TX_Pos = 0x4
	// Bit mask of STAT_TX field.
	USB_EPR_STAT_TX_Msk = 0x30
	// all transmission requests addressed to this endpoint are ignored
	USB_EPR_STAT_TX_Disabled = 0x0
	// the endpoint is stalled and all transmission requests result in a STALL handshake
	USB_EPR_STAT_TX_Stall = 0x1
	// the endpoint is naked and all transmission requests result in a NAK handshake
	USB_EPR_STAT_TX_Nak = 0x2
	// this endpoint is enabled for transmission
	USB_EPR_STAT_TX_Valid = 0x3
	// Position of DTOG_TX field.
	USB_EPR_DTOG_TX_Pos = 0x6
	// Bit mask of DTOG_TX field.
	USB_EPR_DTOG_TX_Msk = 0x40
	// Bit DTOG_TX.
	USB_EPR_DTOG_TX = 0x40
	// Position of CTR_TX field.
	USB_EPR_CTR_TX_Pos = 0x7
	// Bit mask of CTR_TX field.
	USB_EPR_CTR_TX_Msk = 0x80
	// Bit CTR_TX.
	USB_EPR_CTR_TX = 0x80
	// Position of EP_KIND field.
	USB_EPR_EP_KIND_Pos = 0x8
	// Bit mask of EP_KIND field.
	USB_EPR_EP_KIND_Msk = 0x100
	// Bit EP_KIND.
	USB_EPR_EP_KIND = 0x100
	// Position of EP_TYPE field.
	USB_EPR_EP_TYPE_Pos = 0x9
	// Bit mask of EP_TYPE field.
	USB_EPR_EP_TYPE_Msk = 0x600
	// Bulk endpoint
	USB_EPR_EP_TYPE_Bulk = 0x0
	// Control endpoint
	USB_EPR_EP_TYPE_Control = 0x1
	// Iso endpoint
	USB_EPR_EP_TYPE_Iso = 0x2
	// Interrupt endpoint
	USB_EPR_EP_TYPE_Interrupt = 0x3
	// Position of SETUP field.
	USB_EPR_SETUP_Pos = 0xb
	// Bit mask of SETUP field.
	USB_EPR_SETUP_Msk = 0x800
	// Bit SETUP.
	USB_EPR_SETUP = 0x800
	// Position of STAT_RX field.
	USB_EPR_STAT_RX_Pos = 0xc
	// Bit mask of STAT_RX field.
	USB_EPR_STAT_RX_Msk = 0x3000
	// all reception requests addressed to this endpoint are ignored
	USB_EPR_STAT_RX_Disabled = 0x0
	// the endpoint is stalled and all reception requests result in a STALL handshake
	USB_EPR_STAT_RX_Stall = 0x1
	// the endpoint is naked and all reception requests result in a NAK handshake
	USB_EPR_STAT_RX_Nak = 0x2
	// this endpoint is enabled for reception
	USB_EPR_STAT_RX_Valid = 0x3
	// Position of DTOG_RX field.
	USB_EPR_DTOG_RX_Pos = 0xe
	// Bit mask of DTOG_RX field.
	USB_EPR_DTOG_RX_Msk = 0x4000
	// Bit DTOG_RX.
	USB_EPR_DTOG_RX = 0x4000
	// Position of CTR_RX field.
	USB_EPR_CTR_RX_Pos = 0xf
	// Bit mask of CTR_RX field.
	USB_EPR_CTR_RX_Msk = 0x8000
	// Bit CTR_RX.
	USB_EPR_CTR_RX = 0x8000

	// CNTR: control register
	// Position of FRES field.
	USB_CNTR_FRES_Pos = 0x0
	// Bit mask of FRES field.
	USB_CNTR_FRES_Msk = 0x1
	// Bit FRES.
	USB_CNTR_FRES = 0x1
	// Clear USB reset
	USB_CNTR_FRES_NoReset = 0x0
	// Force a reset of the USB peripheral, exactly like a RESET signaling on the USB
	USB_CNTR_FRES_Reset = 0x1
	// Position of PDWN field.
	USB_CNTR_PDWN_Pos = 0x1
	// Bit mask of PDWN field.
	USB_CNTR_PDWN_Msk = 0x2
	// Bit PDWN.
	USB_CNTR_PDWN = 0x2
	// No power down
	USB_CNTR_PDWN_Disabled = 0x0
	// Enter power down mode
	USB_CNTR_PDWN_Enabled = 0x1
	// Position of LPMODE field.
	USB_CNTR_LPMODE_Pos = 0x2
	// Bit mask of LPMODE field.
	USB_CNTR_LPMODE_Msk = 0x4
	// Bit LPMODE.
	USB_CNTR_LPMODE = 0x4
	// No low-power mode
	USB_CNTR_LPMODE_Disabled = 0x0
	// Enter low-power mode
	USB_CNTR_LPMODE_Enabled = 0x1
	// Position of FSUSP field.
	USB_CNTR_FSUSP_Pos = 0x3
	// Bit mask of FSUSP field.
	USB_CNTR_FSUSP_Msk = 0x8
	// Bit FSUSP.
	USB_CNTR_FSUSP = 0x8
	// No effect
	USB_CNTR_FSUSP_NoEffect = 0x0
	// Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected
	USB_CNTR_FSUSP_Suspend = 0x1
	// Position of RESUME field.
	USB_CNTR_RESUME_Pos = 0x4
	// Bit mask of RESUME field.
	USB_CNTR_RESUME_Msk = 0x10
	// Bit RESUME.
	USB_CNTR_RESUME = 0x10
	// Resume requested
	USB_CNTR_RESUME_Requested = 0x1
	// Position of L1RESUME field.
	USB_CNTR_L1RESUME_Pos = 0x5
	// Bit mask of L1RESUME field.
	USB_CNTR_L1RESUME_Msk = 0x20
	// Bit L1RESUME.
	USB_CNTR_L1RESUME = 0x20
	// LPM L1 request requested
	USB_CNTR_L1RESUME_Requested = 0x1
	// Position of L1REQM field.
	USB_CNTR_L1REQM_Pos = 0x7
	// Bit mask of L1REQM field.
	USB_CNTR_L1REQM_Msk = 0x80
	// Bit L1REQM.
	USB_CNTR_L1REQM = 0x80
	// L1REQ Interrupt disabled
	USB_CNTR_L1REQM_Disabled = 0x0
	// L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_L1REQM_Enabled = 0x1
	// Position of ESOFM field.
	USB_CNTR_ESOFM_Pos = 0x8
	// Bit mask of ESOFM field.
	USB_CNTR_ESOFM_Msk = 0x100
	// Bit ESOFM.
	USB_CNTR_ESOFM = 0x100
	// ESOF Interrupt disabled
	USB_CNTR_ESOFM_Disabled = 0x0
	// ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_ESOFM_Enabled = 0x1
	// Position of SOFM field.
	USB_CNTR_SOFM_Pos = 0x9
	// Bit mask of SOFM field.
	USB_CNTR_SOFM_Msk = 0x200
	// Bit SOFM.
	USB_CNTR_SOFM = 0x200
	// SOF Interrupt disabled
	USB_CNTR_SOFM_Disabled = 0x0
	// SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_SOFM_Enabled = 0x1
	// Position of RESETM field.
	USB_CNTR_RESETM_Pos = 0xa
	// Bit mask of RESETM field.
	USB_CNTR_RESETM_Msk = 0x400
	// Bit RESETM.
	USB_CNTR_RESETM = 0x400
	// RESET Interrupt disabled
	USB_CNTR_RESETM_Disabled = 0x0
	// RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_RESETM_Enabled = 0x1
	// Position of SUSPM field.
	USB_CNTR_SUSPM_Pos = 0xb
	// Bit mask of SUSPM field.
	USB_CNTR_SUSPM_Msk = 0x800
	// Bit SUSPM.
	USB_CNTR_SUSPM = 0x800
	// Suspend Mode Request SUSP Interrupt disabled
	USB_CNTR_SUSPM_Disabled = 0x0
	// SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_SUSPM_Enabled = 0x1
	// Position of WKUPM field.
	USB_CNTR_WKUPM_Pos = 0xc
	// Bit mask of WKUPM field.
	USB_CNTR_WKUPM_Msk = 0x1000
	// Bit WKUPM.
	USB_CNTR_WKUPM = 0x1000
	// WKUP Interrupt disabled
	USB_CNTR_WKUPM_Disabled = 0x0
	// WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_WKUPM_Enabled = 0x1
	// Position of ERRM field.
	USB_CNTR_ERRM_Pos = 0xd
	// Bit mask of ERRM field.
	USB_CNTR_ERRM_Msk = 0x2000
	// Bit ERRM.
	USB_CNTR_ERRM = 0x2000
	// ERR Interrupt disabled
	USB_CNTR_ERRM_Disabled = 0x0
	// ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_ERRM_Enabled = 0x1
	// Position of PMAOVRM field.
	USB_CNTR_PMAOVRM_Pos = 0xe
	// Bit mask of PMAOVRM field.
	USB_CNTR_PMAOVRM_Msk = 0x4000
	// Bit PMAOVRM.
	USB_CNTR_PMAOVRM = 0x4000
	// PMAOVR Interrupt disabled
	USB_CNTR_PMAOVRM_Disabled = 0x0
	// PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_PMAOVRM_Enabled = 0x1
	// Position of CTRM field.
	USB_CNTR_CTRM_Pos = 0xf
	// Bit mask of CTRM field.
	USB_CNTR_CTRM_Msk = 0x8000
	// Bit CTRM.
	USB_CNTR_CTRM = 0x8000
	// Correct Transfer (CTR) Interrupt disabled
	USB_CNTR_CTRM_Disabled = 0x0
	// CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set
	USB_CNTR_CTRM_Enabled = 0x1

	// ISTR: interrupt status register
	// Position of EP_ID field.
	USB_ISTR_EP_ID_Pos = 0x0
	// Bit mask of EP_ID field.
	USB_ISTR_EP_ID_Msk = 0xf
	// Position of DIR field.
	USB_ISTR_DIR_Pos = 0x4
	// Bit mask of DIR field.
	USB_ISTR_DIR_Msk = 0x10
	// Bit DIR.
	USB_ISTR_DIR = 0x10
	// Data transmitted by the USB peripheral to the host PC
	USB_ISTR_DIR_To = 0x0
	// Data received by the USB peripheral from the host PC
	USB_ISTR_DIR_From = 0x1
	// Position of L1REQ field.
	USB_ISTR_L1REQ_Pos = 0x7
	// Bit mask of L1REQ field.
	USB_ISTR_L1REQ_Msk = 0x80
	// Bit L1REQ.
	USB_ISTR_L1REQ = 0x80
	// LPM command to enter the L1 state is not received
	USB_ISTR_L1REQ_NotReceived = 0x0
	// LPM command to enter the L1 state is successfully received and acknowledged
	USB_ISTR_L1REQ_Received = 0x1
	// Clear flag
	USB_ISTR_L1REQ_Clear = 0x0
	// Position of ESOF field.
	USB_ISTR_ESOF_Pos = 0x8
	// Bit mask of ESOF field.
	USB_ISTR_ESOF_Msk = 0x100
	// Bit ESOF.
	USB_ISTR_ESOF = 0x100
	// NotExpectedStartOfFrame
	USB_ISTR_ESOF_NotExpectedStartOfFrame = 0x0
	// An SOF packet is expected but not received
	USB_ISTR_ESOF_ExpectedStartOfFrame = 0x1
	// Clear flag
	USB_ISTR_ESOF_Clear = 0x0
	// Position of SOF field.
	USB_ISTR_SOF_Pos = 0x9
	// Bit mask of SOF field.
	USB_ISTR_SOF_Msk = 0x200
	// Bit SOF.
	USB_ISTR_SOF = 0x200
	// NotStartOfFrame
	USB_ISTR_SOF_NotStartOfFrame = 0x0
	// Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus
	USB_ISTR_SOF_StartOfFrame = 0x1
	// Clear flag
	USB_ISTR_SOF_Clear = 0x0
	// Position of RESET field.
	USB_ISTR_RESET_Pos = 0xa
	// Bit mask of RESET field.
	USB_ISTR_RESET_Msk = 0x400
	// Bit RESET.
	USB_ISTR_RESET = 0x400
	// NotReset
	USB_ISTR_RESET_NotReset = 0x0
	// Peripheral detects an active USB RESET signal at its inputs
	USB_ISTR_RESET_Reset = 0x1
	// Clear flag
	USB_ISTR_RESET_Clear = 0x0
	// Position of SUSP field.
	USB_ISTR_SUSP_Pos = 0xb
	// Bit mask of SUSP field.
	USB_ISTR_SUSP_Msk = 0x800
	// Bit SUSP.
	USB_ISTR_SUSP = 0x800
	// NotSuspend
	USB_ISTR_SUSP_NotSuspend = 0x0
	// No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus
	USB_ISTR_SUSP_Suspend = 0x1
	// Clear flag
	USB_ISTR_SUSP_Clear = 0x0
	// Position of WKUP field.
	USB_ISTR_WKUP_Pos = 0xc
	// Bit mask of WKUP field.
	USB_ISTR_WKUP_Msk = 0x1000
	// Bit WKUP.
	USB_ISTR_WKUP = 0x1000
	// NotWakeup
	USB_ISTR_WKUP_NotWakeup = 0x0
	// Activity is detected that wakes up the USB peripheral
	USB_ISTR_WKUP_Wakeup = 0x1
	// Clear flag
	USB_ISTR_WKUP_Clear = 0x0
	// Position of ERR field.
	USB_ISTR_ERR_Pos = 0xd
	// Bit mask of ERR field.
	USB_ISTR_ERR_Msk = 0x2000
	// Bit ERR.
	USB_ISTR_ERR = 0x2000
	// Errors are not occurred
	USB_ISTR_ERR_NotOverrun = 0x0
	// One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred
	USB_ISTR_ERR_Error = 0x1
	// Clear flag
	USB_ISTR_ERR_Clear = 0x0
	// Position of PMAOVR field.
	USB_ISTR_PMAOVR_Pos = 0xe
	// Bit mask of PMAOVR field.
	USB_ISTR_PMAOVR_Msk = 0x4000
	// Bit PMAOVR.
	USB_ISTR_PMAOVR = 0x4000
	// Overrun is not occurred
	USB_ISTR_PMAOVR_NotOverrun = 0x0
	// Microcontroller has not been able to respond in time to an USB memory request
	USB_ISTR_PMAOVR_Overrun = 0x1
	// Clear flag
	USB_ISTR_PMAOVR_Clear = 0x0
	// Position of CTR field.
	USB_ISTR_CTR_Pos = 0xf
	// Bit mask of CTR field.
	USB_ISTR_CTR_Msk = 0x8000
	// Bit CTR.
	USB_ISTR_CTR = 0x8000
	// Endpoint has successfully completed a transaction
	USB_ISTR_CTR_Completed = 0x1

	// FNR: frame number register
	// Position of FN field.
	USB_FNR_FN_Pos = 0x0
	// Bit mask of FN field.
	USB_FNR_FN_Msk = 0x7ff
	// Position of LSOF field.
	USB_FNR_LSOF_Pos = 0xb
	// Bit mask of LSOF field.
	USB_FNR_LSOF_Msk = 0x1800
	// Position of LCK field.
	USB_FNR_LCK_Pos = 0xd
	// Bit mask of LCK field.
	USB_FNR_LCK_Msk = 0x2000
	// Bit LCK.
	USB_FNR_LCK = 0x2000
	// the frame timer remains in this state until an USB reset or USB suspend event occurs
	USB_FNR_LCK_Locked = 0x1
	// Position of RXDM field.
	USB_FNR_RXDM_Pos = 0xe
	// Bit mask of RXDM field.
	USB_FNR_RXDM_Msk = 0x4000
	// Bit RXDM.
	USB_FNR_RXDM = 0x4000
	// received data minus upstream port data line
	USB_FNR_RXDM_Received = 0x1
	// Position of RXDP field.
	USB_FNR_RXDP_Pos = 0xf
	// Bit mask of RXDP field.
	USB_FNR_RXDP_Msk = 0x8000
	// Bit RXDP.
	USB_FNR_RXDP = 0x8000
	// received data plus upstream port data line
	USB_FNR_RXDP_Received = 0x1

	// DADDR: device address
	// Position of ADD field.
	USB_DADDR_ADD_Pos = 0x0
	// Bit mask of ADD field.
	USB_DADDR_ADD_Msk = 0x7f
	// Position of EF field.
	USB_DADDR_EF_Pos = 0x7
	// Bit mask of EF field.
	USB_DADDR_EF_Msk = 0x80
	// Bit EF.
	USB_DADDR_EF = 0x80
	// USB device disabled
	USB_DADDR_EF_Disabled = 0x0
	// USB device enabled
	USB_DADDR_EF_Enabled = 0x1

	// BTABLE: Buffer table address
	// Position of BTABLE field.
	USB_BTABLE_BTABLE_Pos = 0x3
	// Bit mask of BTABLE field.
	USB_BTABLE_BTABLE_Msk = 0xfff8

	// LPMCSR: LPM control and status register
	// Position of LPMEN field.
	USB_LPMCSR_LPMEN_Pos = 0x0
	// Bit mask of LPMEN field.
	USB_LPMCSR_LPMEN_Msk = 0x1
	// Bit LPMEN.
	USB_LPMCSR_LPMEN = 0x1
	// No LPM transactions are handled
	USB_LPMCSR_LPMEN_Disabled = 0x0
	// Enable the LPM support within the USB device
	USB_LPMCSR_LPMEN_Enabled = 0x1
	// Position of LPMACK field.
	USB_LPMCSR_LPMACK_Pos = 0x1
	// Bit mask of LPMACK field.
	USB_LPMCSR_LPMACK_Msk = 0x2
	// Bit LPMACK.
	USB_LPMCSR_LPMACK = 0x2
	// The valid LPM Token will be NYET
	USB_LPMCSR_LPMACK_Nyet = 0x0
	// The valid LPM Token will be ACK
	USB_LPMCSR_LPMACK_Ack = 0x1
	// Position of REMWAKE field.
	USB_LPMCSR_REMWAKE_Pos = 0x3
	// Bit mask of REMWAKE field.
	USB_LPMCSR_REMWAKE_Msk = 0x8
	// Bit REMWAKE.
	USB_LPMCSR_REMWAKE = 0x8
	// Position of BESL field.
	USB_LPMCSR_BESL_Pos = 0x4
	// Bit mask of BESL field.
	USB_LPMCSR_BESL_Msk = 0xf0

	// BCDR: Battery charging detector
	// Position of BCDEN field.
	USB_BCDR_BCDEN_Pos = 0x0
	// Bit mask of BCDEN field.
	USB_BCDR_BCDEN_Msk = 0x1
	// Bit BCDEN.
	USB_BCDR_BCDEN = 0x1
	// disable the BCD support
	USB_BCDR_BCDEN_Disabled = 0x0
	// enable the BCD support within the USB device
	USB_BCDR_BCDEN_Enabled = 0x1
	// Position of DCDEN field.
	USB_BCDR_DCDEN_Pos = 0x1
	// Bit mask of DCDEN field.
	USB_BCDR_DCDEN_Msk = 0x2
	// Bit DCDEN.
	USB_BCDR_DCDEN = 0x2
	// Data contact detection (DCD) mode disabled
	USB_BCDR_DCDEN_Disabled = 0x0
	// Data contact detection (DCD) mode enabled
	USB_BCDR_DCDEN_Enabled = 0x1
	// Position of PDEN field.
	USB_BCDR_PDEN_Pos = 0x2
	// Bit mask of PDEN field.
	USB_BCDR_PDEN_Msk = 0x4
	// Bit PDEN.
	USB_BCDR_PDEN = 0x4
	// Primary detection (PD) mode disabled
	USB_BCDR_PDEN_Disabled = 0x0
	// Primary detection (PD) mode enabled
	USB_BCDR_PDEN_Enabled = 0x1
	// Position of SDEN field.
	USB_BCDR_SDEN_Pos = 0x3
	// Bit mask of SDEN field.
	USB_BCDR_SDEN_Msk = 0x8
	// Bit SDEN.
	USB_BCDR_SDEN = 0x8
	// Secondary detection (SD) mode disabled
	USB_BCDR_SDEN_Disabled = 0x0
	// Secondary detection (SD) mode enabled
	USB_BCDR_SDEN_Enabled = 0x1
	// Position of DCDET field.
	USB_BCDR_DCDET_Pos = 0x4
	// Bit mask of DCDET field.
	USB_BCDR_DCDET_Msk = 0x10
	// Bit DCDET.
	USB_BCDR_DCDET = 0x10
	// data lines contact not detected
	USB_BCDR_DCDET_NotDetected = 0x0
	// data lines contact detected
	USB_BCDR_DCDET_Detected = 0x1
	// Position of PDET field.
	USB_BCDR_PDET_Pos = 0x5
	// Bit mask of PDET field.
	USB_BCDR_PDET_Msk = 0x20
	// Bit PDET.
	USB_BCDR_PDET = 0x20
	// no BCD support detected
	USB_BCDR_PDET_NoBCD = 0x0
	// BCD support detected
	USB_BCDR_PDET_BCD = 0x1
	// Position of SDET field.
	USB_BCDR_SDET_Pos = 0x6
	// Bit mask of SDET field.
	USB_BCDR_SDET_Msk = 0x40
	// Bit SDET.
	USB_BCDR_SDET = 0x40
	// CDP detected
	USB_BCDR_SDET_CDP = 0x0
	// DCP detected
	USB_BCDR_SDET_DCP = 0x1
	// Position of PS2DET field.
	USB_BCDR_PS2DET_Pos = 0x7
	// Bit mask of PS2DET field.
	USB_BCDR_PS2DET_Msk = 0x80
	// Bit PS2DET.
	USB_BCDR_PS2DET = 0x80
	// Normal port detected
	USB_BCDR_PS2DET_Normal = 0x0
	// PS2 port or proprietary charger detected
	USB_BCDR_PS2DET_PS2 = 0x1
	// Position of DPPU field.
	USB_BCDR_DPPU_Pos = 0xf
	// Bit mask of DPPU field.
	USB_BCDR_DPPU_Msk = 0x8000
	// Bit DPPU.
	USB_BCDR_DPPU = 0x8000
	// signalize disconnect to the host when needed by the user software
	USB_BCDR_DPPU_Disabled = 0x0
	// enable the embedded pull-up on the DP line
	USB_BCDR_DPPU_Enabled = 0x1
)

// Constants for UCPD1: USB Power Delivery interface
const (
	// CFGR1: UCPD configuration register
	// Position of HBITCLKDIV field.
	UCPD_CFGR1_HBITCLKDIV_Pos = 0x0
	// Bit mask of HBITCLKDIV field.
	UCPD_CFGR1_HBITCLKDIV_Msk = 0x3f
	// Position of IFRGAP field.
	UCPD_CFGR1_IFRGAP_Pos = 0x6
	// Bit mask of IFRGAP field.
	UCPD_CFGR1_IFRGAP_Msk = 0x7c0
	// Position of TRANSWIN field.
	UCPD_CFGR1_TRANSWIN_Pos = 0xb
	// Bit mask of TRANSWIN field.
	UCPD_CFGR1_TRANSWIN_Msk = 0xf800
	// Position of PSC_USBPDCLK field.
	UCPD_CFGR1_PSC_USBPDCLK_Pos = 0x11
	// Bit mask of PSC_USBPDCLK field.
	UCPD_CFGR1_PSC_USBPDCLK_Msk = 0xe0000
	// Divide by 1
	UCPD_CFGR1_PSC_USBPDCLK_Div1 = 0x0
	// Divide by 2
	UCPD_CFGR1_PSC_USBPDCLK_Div2 = 0x1
	// Divide by 4
	UCPD_CFGR1_PSC_USBPDCLK_Div4 = 0x2
	// Divide by 8
	UCPD_CFGR1_PSC_USBPDCLK_Div8 = 0x3
	// Divide by 16
	UCPD_CFGR1_PSC_USBPDCLK_Div16 = 0x4
	// Position of TXDMAEN field.
	UCPD_CFGR1_TXDMAEN_Pos = 0x1d
	// Bit mask of TXDMAEN field.
	UCPD_CFGR1_TXDMAEN_Msk = 0x20000000
	// Bit TXDMAEN.
	UCPD_CFGR1_TXDMAEN = 0x20000000
	// DMA mode for transmission disabled
	UCPD_CFGR1_TXDMAEN_Disabled = 0x0
	// DMA mode for transmission enabled
	UCPD_CFGR1_TXDMAEN_Enabled = 0x1
	// Position of RXDMAEN field.
	UCPD_CFGR1_RXDMAEN_Pos = 0x1e
	// Bit mask of RXDMAEN field.
	UCPD_CFGR1_RXDMAEN_Msk = 0x40000000
	// Bit RXDMAEN.
	UCPD_CFGR1_RXDMAEN = 0x40000000
	// DMA mode for reception disabled
	UCPD_CFGR1_RXDMAEN_Disabled = 0x0
	// DMA mode for reception enabled
	UCPD_CFGR1_RXDMAEN_Enabled = 0x1
	// Position of UCPDEN field.
	UCPD_CFGR1_UCPDEN_Pos = 0x1f
	// Bit mask of UCPDEN field.
	UCPD_CFGR1_UCPDEN_Msk = 0x80000000
	// Bit UCPDEN.
	UCPD_CFGR1_UCPDEN = 0x80000000
	// UCPD peripheral disabled
	UCPD_CFGR1_UCPDEN_Disabled = 0x0
	// UCPD peripheral enabled
	UCPD_CFGR1_UCPDEN_Enabled = 0x1
	// Position of RXORDSETEN0 field.
	UCPD_CFGR1_RXORDSETEN0_Pos = 0x14
	// Bit mask of RXORDSETEN0 field.
	UCPD_CFGR1_RXORDSETEN0_Msk = 0x100000
	// Bit RXORDSETEN0.
	UCPD_CFGR1_RXORDSETEN0 = 0x100000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN0_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN0_Enabled = 0x1
	// Position of RXORDSETEN1 field.
	UCPD_CFGR1_RXORDSETEN1_Pos = 0x15
	// Bit mask of RXORDSETEN1 field.
	UCPD_CFGR1_RXORDSETEN1_Msk = 0x200000
	// Bit RXORDSETEN1.
	UCPD_CFGR1_RXORDSETEN1 = 0x200000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN1_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN1_Enabled = 0x1
	// Position of RXORDSETEN2 field.
	UCPD_CFGR1_RXORDSETEN2_Pos = 0x16
	// Bit mask of RXORDSETEN2 field.
	UCPD_CFGR1_RXORDSETEN2_Msk = 0x400000
	// Bit RXORDSETEN2.
	UCPD_CFGR1_RXORDSETEN2 = 0x400000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN2_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN2_Enabled = 0x1
	// Position of RXORDSETEN3 field.
	UCPD_CFGR1_RXORDSETEN3_Pos = 0x17
	// Bit mask of RXORDSETEN3 field.
	UCPD_CFGR1_RXORDSETEN3_Msk = 0x800000
	// Bit RXORDSETEN3.
	UCPD_CFGR1_RXORDSETEN3 = 0x800000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN3_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN3_Enabled = 0x1
	// Position of RXORDSETEN4 field.
	UCPD_CFGR1_RXORDSETEN4_Pos = 0x18
	// Bit mask of RXORDSETEN4 field.
	UCPD_CFGR1_RXORDSETEN4_Msk = 0x1000000
	// Bit RXORDSETEN4.
	UCPD_CFGR1_RXORDSETEN4 = 0x1000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN4_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN4_Enabled = 0x1
	// Position of RXORDSETEN5 field.
	UCPD_CFGR1_RXORDSETEN5_Pos = 0x19
	// Bit mask of RXORDSETEN5 field.
	UCPD_CFGR1_RXORDSETEN5_Msk = 0x2000000
	// Bit RXORDSETEN5.
	UCPD_CFGR1_RXORDSETEN5 = 0x2000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN5_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN5_Enabled = 0x1
	// Position of RXORDSETEN6 field.
	UCPD_CFGR1_RXORDSETEN6_Pos = 0x1a
	// Bit mask of RXORDSETEN6 field.
	UCPD_CFGR1_RXORDSETEN6_Msk = 0x4000000
	// Bit RXORDSETEN6.
	UCPD_CFGR1_RXORDSETEN6 = 0x4000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN6_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN6_Enabled = 0x1
	// Position of RXORDSETEN7 field.
	UCPD_CFGR1_RXORDSETEN7_Pos = 0x1b
	// Bit mask of RXORDSETEN7 field.
	UCPD_CFGR1_RXORDSETEN7_Msk = 0x8000000
	// Bit RXORDSETEN7.
	UCPD_CFGR1_RXORDSETEN7 = 0x8000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN7_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN7_Enabled = 0x1
	// Position of RXORDSETEN8 field.
	UCPD_CFGR1_RXORDSETEN8_Pos = 0x1c
	// Bit mask of RXORDSETEN8 field.
	UCPD_CFGR1_RXORDSETEN8_Msk = 0x10000000
	// Bit RXORDSETEN8.
	UCPD_CFGR1_RXORDSETEN8 = 0x10000000
	// Flag disabled
	UCPD_CFGR1_RXORDSETEN8_Disabled = 0x0
	// Flag enabled
	UCPD_CFGR1_RXORDSETEN8_Enabled = 0x1

	// CFGR2: UCPD configuration register 2
	// Position of RXFILTDIS field.
	UCPD_CFGR2_RXFILTDIS_Pos = 0x0
	// Bit mask of RXFILTDIS field.
	UCPD_CFGR2_RXFILTDIS_Msk = 0x1
	// Bit RXFILTDIS.
	UCPD_CFGR2_RXFILTDIS = 0x1
	// Rx pre-filter enabled
	UCPD_CFGR2_RXFILTDIS_Enabled = 0x0
	// Rx pre-filter disabled
	UCPD_CFGR2_RXFILTDIS_Disabled = 0x1
	// Position of RXFILT2N3 field.
	UCPD_CFGR2_RXFILT2N3_Pos = 0x1
	// Bit mask of RXFILT2N3 field.
	UCPD_CFGR2_RXFILT2N3_Msk = 0x2
	// Bit RXFILT2N3.
	UCPD_CFGR2_RXFILT2N3 = 0x2
	// 3 samples
	UCPD_CFGR2_RXFILT2N3_Samp3 = 0x0
	// 2 samples
	UCPD_CFGR2_RXFILT2N3_Samp2 = 0x1
	// Position of FORCECLK field.
	UCPD_CFGR2_FORCECLK_Pos = 0x2
	// Bit mask of FORCECLK field.
	UCPD_CFGR2_FORCECLK_Msk = 0x4
	// Bit FORCECLK.
	UCPD_CFGR2_FORCECLK = 0x4
	// Do not force clock request
	UCPD_CFGR2_FORCECLK_NoForce = 0x0
	// Force clock request
	UCPD_CFGR2_FORCECLK_Force = 0x1
	// Position of WUPEN field.
	UCPD_CFGR2_WUPEN_Pos = 0x3
	// Bit mask of WUPEN field.
	UCPD_CFGR2_WUPEN_Msk = 0x8
	// Bit WUPEN.
	UCPD_CFGR2_WUPEN = 0x8
	// Disabled
	UCPD_CFGR2_WUPEN_Disabled = 0x0
	// Enabled
	UCPD_CFGR2_WUPEN_Enabled = 0x1

	// CFGR3: UCPD configuration register 3
	// Position of TRIM1_NG_CCRPD field.
	UCPD_CFGR3_TRIM1_NG_CCRPD_Pos = 0x0
	// Bit mask of TRIM1_NG_CCRPD field.
	UCPD_CFGR3_TRIM1_NG_CCRPD_Msk = 0xf
	// Position of TRIM1_NG_CC1A5 field.
	UCPD_CFGR3_TRIM1_NG_CC1A5_Pos = 0x4
	// Bit mask of TRIM1_NG_CC1A5 field.
	UCPD_CFGR3_TRIM1_NG_CC1A5_Msk = 0x1f0
	// Position of TRIM1_NG_CC3A0 field.
	UCPD_CFGR3_TRIM1_NG_CC3A0_Pos = 0x9
	// Bit mask of TRIM1_NG_CC3A0 field.
	UCPD_CFGR3_TRIM1_NG_CC3A0_Msk = 0x1e00
	// Position of TRIM2_NG_CCRPD field.
	UCPD_CFGR3_TRIM2_NG_CCRPD_Pos = 0x10
	// Bit mask of TRIM2_NG_CCRPD field.
	UCPD_CFGR3_TRIM2_NG_CCRPD_Msk = 0xf0000
	// Position of TRIM2_NG_CC1A5 field.
	UCPD_CFGR3_TRIM2_NG_CC1A5_Pos = 0x14
	// Bit mask of TRIM2_NG_CC1A5 field.
	UCPD_CFGR3_TRIM2_NG_CC1A5_Msk = 0x1f00000
	// Position of TRIM2_NG_CC3A0 field.
	UCPD_CFGR3_TRIM2_NG_CC3A0_Pos = 0x19
	// Bit mask of TRIM2_NG_CC3A0 field.
	UCPD_CFGR3_TRIM2_NG_CC3A0_Msk = 0x1e000000

	// CR: UCPD control register
	// Position of TXMODE field.
	UCPD_CR_TXMODE_Pos = 0x0
	// Bit mask of TXMODE field.
	UCPD_CR_TXMODE_Msk = 0x3
	// Transmission of Tx packet previously defined in other registers
	UCPD_CR_TXMODE_RegisterSet = 0x0
	// Cable Reset sequence
	UCPD_CR_TXMODE_CableReset = 0x1
	// BIST test sequence (BIST Carrier Mode 2)
	UCPD_CR_TXMODE_BISTTest = 0x2
	// Position of TXSEND field.
	UCPD_CR_TXSEND_Pos = 0x2
	// Bit mask of TXSEND field.
	UCPD_CR_TXSEND_Msk = 0x4
	// Bit TXSEND.
	UCPD_CR_TXSEND = 0x4
	// No effect
	UCPD_CR_TXSEND_NoEffect = 0x0
	// Start Tx packet transmission
	UCPD_CR_TXSEND_Start = 0x1
	// Position of TXHRST field.
	UCPD_CR_TXHRST_Pos = 0x3
	// Bit mask of TXHRST field.
	UCPD_CR_TXHRST_Msk = 0x8
	// Bit TXHRST.
	UCPD_CR_TXHRST = 0x8
	// No effect
	UCPD_CR_TXHRST_NoEffect = 0x0
	// Start Tx Hard Reset message
	UCPD_CR_TXHRST_Start = 0x1
	// Position of RXMODE field.
	UCPD_CR_RXMODE_Pos = 0x4
	// Bit mask of RXMODE field.
	UCPD_CR_RXMODE_Msk = 0x10
	// Bit RXMODE.
	UCPD_CR_RXMODE = 0x10
	// Normal receive mode
	UCPD_CR_RXMODE_Normal = 0x0
	// BIST receive mode (BIST test data mode)
	UCPD_CR_RXMODE_BIST = 0x1
	// Position of PHYRXEN field.
	UCPD_CR_PHYRXEN_Pos = 0x5
	// Bit mask of PHYRXEN field.
	UCPD_CR_PHYRXEN_Msk = 0x20
	// Bit PHYRXEN.
	UCPD_CR_PHYRXEN = 0x20
	// USB Power Delivery receiver disabled
	UCPD_CR_PHYRXEN_Disabled = 0x0
	// USB Power Delivery receiver enabled
	UCPD_CR_PHYRXEN_Enabled = 0x1
	// Position of PHYCCSEL field.
	UCPD_CR_PHYCCSEL_Pos = 0x6
	// Bit mask of PHYCCSEL field.
	UCPD_CR_PHYCCSEL_Msk = 0x40
	// Bit PHYCCSEL.
	UCPD_CR_PHYCCSEL = 0x40
	// Use CC1 IO for Power Delivery communication
	UCPD_CR_PHYCCSEL_CC1 = 0x0
	// Use CC2 IO for Power Delivery communication
	UCPD_CR_PHYCCSEL_CC2 = 0x1
	// Position of ANASUBMODE field.
	UCPD_CR_ANASUBMODE_Pos = 0x7
	// Bit mask of ANASUBMODE field.
	UCPD_CR_ANASUBMODE_Msk = 0x180
	// Disabled
	UCPD_CR_ANASUBMODE_Disabled = 0x0
	// Default USB Rp
	UCPD_CR_ANASUBMODE_Rp_DefaultUSB = 0x1
	// 1.5A Rp
	UCPD_CR_ANASUBMODE_Rp_1_5A = 0x2
	// 3A Rp
	UCPD_CR_ANASUBMODE_Rp_3A = 0x3
	// Position of ANAMODE field.
	UCPD_CR_ANAMODE_Pos = 0x9
	// Bit mask of ANAMODE field.
	UCPD_CR_ANAMODE_Msk = 0x200
	// Bit ANAMODE.
	UCPD_CR_ANAMODE = 0x200
	// Source
	UCPD_CR_ANAMODE_Source = 0x0
	// Sink
	UCPD_CR_ANAMODE_Sink = 0x1
	// Position of CCENABLE field.
	UCPD_CR_CCENABLE_Pos = 0xa
	// Bit mask of CCENABLE field.
	UCPD_CR_CCENABLE_Msk = 0xc00
	// Both PHYs disabled
	UCPD_CR_CCENABLE_Disabled = 0x0
	// CC1 PHY enabled
	UCPD_CR_CCENABLE_CC1Enabled = 0x1
	// CC2 PHY enabled
	UCPD_CR_CCENABLE_CC2Enabled = 0x2
	// CC1 and CC2 PHYs enabled
	UCPD_CR_CCENABLE_BothEnabled = 0x3
	// Position of FRSRXEN field.
	UCPD_CR_FRSRXEN_Pos = 0x10
	// Bit mask of FRSRXEN field.
	UCPD_CR_FRSRXEN_Msk = 0x10000
	// Bit FRSRXEN.
	UCPD_CR_FRSRXEN = 0x10000
	// FRS Rx event detection disabled
	UCPD_CR_FRSRXEN_Disabled = 0x0
	// FRS Rx event detection enabled
	UCPD_CR_FRSRXEN_Enabled = 0x1
	// Position of FRSTX field.
	UCPD_CR_FRSTX_Pos = 0x11
	// Bit mask of FRSTX field.
	UCPD_CR_FRSTX_Msk = 0x20000
	// Bit FRSTX.
	UCPD_CR_FRSTX = 0x20000
	// No effect
	UCPD_CR_FRSTX_NoEffect = 0x0
	// FRS Tx signaling enabled
	UCPD_CR_FRSTX_Enabled = 0x1
	// Position of RDCH field.
	UCPD_CR_RDCH_Pos = 0x12
	// Bit mask of RDCH field.
	UCPD_CR_RDCH_Msk = 0x40000
	// Bit RDCH.
	UCPD_CR_RDCH = 0x40000
	// No effect
	UCPD_CR_RDCH_NoEffect = 0x0
	// Rdch condition drive
	UCPD_CR_RDCH_ConditionDrive = 0x1
	// Position of CC1TCDIS field.
	UCPD_CR_CC1TCDIS_Pos = 0x14
	// Bit mask of CC1TCDIS field.
	UCPD_CR_CC1TCDIS_Msk = 0x100000
	// Bit CC1TCDIS.
	UCPD_CR_CC1TCDIS = 0x100000
	// Type-C detector on the CCx line enabled
	UCPD_CR_CC1TCDIS_Enabled = 0x0
	// Type-C detector on the CCx line disabled
	UCPD_CR_CC1TCDIS_Disabled = 0x1
	// Position of CC2TCDIS field.
	UCPD_CR_CC2TCDIS_Pos = 0x15
	// Bit mask of CC2TCDIS field.
	UCPD_CR_CC2TCDIS_Msk = 0x200000
	// Bit CC2TCDIS.
	UCPD_CR_CC2TCDIS = 0x200000
	// Type-C detector on the CCx line enabled
	UCPD_CR_CC2TCDIS_Enabled = 0x0
	// Type-C detector on the CCx line disabled
	UCPD_CR_CC2TCDIS_Disabled = 0x1

	// IMR: UCPD Interrupt Mask Register
	// Position of TXISIE field.
	UCPD_IMR_TXISIE_Pos = 0x0
	// Bit mask of TXISIE field.
	UCPD_IMR_TXISIE_Msk = 0x1
	// Bit TXISIE.
	UCPD_IMR_TXISIE = 0x1
	// Interrupt disabled
	UCPD_IMR_TXISIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXISIE_Enabled = 0x1
	// Position of TXMSGDISCIE field.
	UCPD_IMR_TXMSGDISCIE_Pos = 0x1
	// Bit mask of TXMSGDISCIE field.
	UCPD_IMR_TXMSGDISCIE_Msk = 0x2
	// Bit TXMSGDISCIE.
	UCPD_IMR_TXMSGDISCIE = 0x2
	// Interrupt disabled
	UCPD_IMR_TXMSGDISCIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXMSGDISCIE_Enabled = 0x1
	// Position of TXMSGSENTIE field.
	UCPD_IMR_TXMSGSENTIE_Pos = 0x2
	// Bit mask of TXMSGSENTIE field.
	UCPD_IMR_TXMSGSENTIE_Msk = 0x4
	// Bit TXMSGSENTIE.
	UCPD_IMR_TXMSGSENTIE = 0x4
	// Interrupt disabled
	UCPD_IMR_TXMSGSENTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXMSGSENTIE_Enabled = 0x1
	// Position of TXMSGABTIE field.
	UCPD_IMR_TXMSGABTIE_Pos = 0x3
	// Bit mask of TXMSGABTIE field.
	UCPD_IMR_TXMSGABTIE_Msk = 0x8
	// Bit TXMSGABTIE.
	UCPD_IMR_TXMSGABTIE = 0x8
	// Interrupt disabled
	UCPD_IMR_TXMSGABTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXMSGABTIE_Enabled = 0x1
	// Position of HRSTDISCIE field.
	UCPD_IMR_HRSTDISCIE_Pos = 0x4
	// Bit mask of HRSTDISCIE field.
	UCPD_IMR_HRSTDISCIE_Msk = 0x10
	// Bit HRSTDISCIE.
	UCPD_IMR_HRSTDISCIE = 0x10
	// Interrupt disabled
	UCPD_IMR_HRSTDISCIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_HRSTDISCIE_Enabled = 0x1
	// Position of HRSTSENTIE field.
	UCPD_IMR_HRSTSENTIE_Pos = 0x5
	// Bit mask of HRSTSENTIE field.
	UCPD_IMR_HRSTSENTIE_Msk = 0x20
	// Bit HRSTSENTIE.
	UCPD_IMR_HRSTSENTIE = 0x20
	// Interrupt disabled
	UCPD_IMR_HRSTSENTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_HRSTSENTIE_Enabled = 0x1
	// Position of TXUNDIE field.
	UCPD_IMR_TXUNDIE_Pos = 0x6
	// Bit mask of TXUNDIE field.
	UCPD_IMR_TXUNDIE_Msk = 0x40
	// Bit TXUNDIE.
	UCPD_IMR_TXUNDIE = 0x40
	// Interrupt disabled
	UCPD_IMR_TXUNDIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TXUNDIE_Enabled = 0x1
	// Position of RXNEIE field.
	UCPD_IMR_RXNEIE_Pos = 0x8
	// Bit mask of RXNEIE field.
	UCPD_IMR_RXNEIE_Msk = 0x100
	// Bit RXNEIE.
	UCPD_IMR_RXNEIE = 0x100
	// Interrupt disabled
	UCPD_IMR_RXNEIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXNEIE_Enabled = 0x1
	// Position of RXORDDETIE field.
	UCPD_IMR_RXORDDETIE_Pos = 0x9
	// Bit mask of RXORDDETIE field.
	UCPD_IMR_RXORDDETIE_Msk = 0x200
	// Bit RXORDDETIE.
	UCPD_IMR_RXORDDETIE = 0x200
	// Interrupt disabled
	UCPD_IMR_RXORDDETIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXORDDETIE_Enabled = 0x1
	// Position of RXHRSTDETIE field.
	UCPD_IMR_RXHRSTDETIE_Pos = 0xa
	// Bit mask of RXHRSTDETIE field.
	UCPD_IMR_RXHRSTDETIE_Msk = 0x400
	// Bit RXHRSTDETIE.
	UCPD_IMR_RXHRSTDETIE = 0x400
	// Interrupt disabled
	UCPD_IMR_RXHRSTDETIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXHRSTDETIE_Enabled = 0x1
	// Position of RXOVRIE field.
	UCPD_IMR_RXOVRIE_Pos = 0xb
	// Bit mask of RXOVRIE field.
	UCPD_IMR_RXOVRIE_Msk = 0x800
	// Bit RXOVRIE.
	UCPD_IMR_RXOVRIE = 0x800
	// Interrupt disabled
	UCPD_IMR_RXOVRIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXOVRIE_Enabled = 0x1
	// Position of RXMSGENDIE field.
	UCPD_IMR_RXMSGENDIE_Pos = 0xc
	// Bit mask of RXMSGENDIE field.
	UCPD_IMR_RXMSGENDIE_Msk = 0x1000
	// Bit RXMSGENDIE.
	UCPD_IMR_RXMSGENDIE = 0x1000
	// Interrupt disabled
	UCPD_IMR_RXMSGENDIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_RXMSGENDIE_Enabled = 0x1
	// Position of TYPECEVT1IE field.
	UCPD_IMR_TYPECEVT1IE_Pos = 0xe
	// Bit mask of TYPECEVT1IE field.
	UCPD_IMR_TYPECEVT1IE_Msk = 0x4000
	// Bit TYPECEVT1IE.
	UCPD_IMR_TYPECEVT1IE = 0x4000
	// Interrupt disabled
	UCPD_IMR_TYPECEVT1IE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TYPECEVT1IE_Enabled = 0x1
	// Position of TYPECEVT2IE field.
	UCPD_IMR_TYPECEVT2IE_Pos = 0xf
	// Bit mask of TYPECEVT2IE field.
	UCPD_IMR_TYPECEVT2IE_Msk = 0x8000
	// Bit TYPECEVT2IE.
	UCPD_IMR_TYPECEVT2IE = 0x8000
	// Interrupt disabled
	UCPD_IMR_TYPECEVT2IE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_TYPECEVT2IE_Enabled = 0x1
	// Position of FRSEVTIE field.
	UCPD_IMR_FRSEVTIE_Pos = 0x14
	// Bit mask of FRSEVTIE field.
	UCPD_IMR_FRSEVTIE_Msk = 0x100000
	// Bit FRSEVTIE.
	UCPD_IMR_FRSEVTIE = 0x100000
	// Interrupt disabled
	UCPD_IMR_FRSEVTIE_Disabled = 0x0
	// Interrupt enabled
	UCPD_IMR_FRSEVTIE_Enabled = 0x1

	// SR: UCPD Status Register
	// Position of TXIS field.
	UCPD_SR_TXIS_Pos = 0x0
	// Bit mask of TXIS field.
	UCPD_SR_TXIS_Msk = 0x1
	// Bit TXIS.
	UCPD_SR_TXIS = 0x1
	// New Tx data write not required
	UCPD_SR_TXIS_NotRequired = 0x0
	// New Tx data write required
	UCPD_SR_TXIS_Required = 0x1
	// Position of TXMSGDISC field.
	UCPD_SR_TXMSGDISC_Pos = 0x1
	// Bit mask of TXMSGDISC field.
	UCPD_SR_TXMSGDISC_Msk = 0x2
	// Bit TXMSGDISC.
	UCPD_SR_TXMSGDISC = 0x2
	// No Tx message discarded
	UCPD_SR_TXMSGDISC_NotDiscarded = 0x0
	// Tx message discarded
	UCPD_SR_TXMSGDISC_Discarded = 0x1
	// Position of TXMSGSENT field.
	UCPD_SR_TXMSGSENT_Pos = 0x2
	// Bit mask of TXMSGSENT field.
	UCPD_SR_TXMSGSENT_Msk = 0x4
	// Bit TXMSGSENT.
	UCPD_SR_TXMSGSENT = 0x4
	// No Tx message completed
	UCPD_SR_TXMSGSENT_NotCompleted = 0x0
	// Tx message completed
	UCPD_SR_TXMSGSENT_Completed = 0x1
	// Position of TXMSGABT field.
	UCPD_SR_TXMSGABT_Pos = 0x3
	// Bit mask of TXMSGABT field.
	UCPD_SR_TXMSGABT_Msk = 0x8
	// Bit TXMSGABT.
	UCPD_SR_TXMSGABT = 0x8
	// No transmit message abort
	UCPD_SR_TXMSGABT_NoAbort = 0x0
	// Transmit message abort
	UCPD_SR_TXMSGABT_Abort = 0x1
	// Position of HRSTDISC field.
	UCPD_SR_HRSTDISC_Pos = 0x4
	// Bit mask of HRSTDISC field.
	UCPD_SR_HRSTDISC_Msk = 0x10
	// Bit HRSTDISC.
	UCPD_SR_HRSTDISC = 0x10
	// No Hard Reset discarded
	UCPD_SR_HRSTDISC_NotDiscarded = 0x0
	// Hard Reset discarded
	UCPD_SR_HRSTDISC_Discarded = 0x1
	// Position of HRSTSENT field.
	UCPD_SR_HRSTSENT_Pos = 0x5
	// Bit mask of HRSTSENT field.
	UCPD_SR_HRSTSENT_Msk = 0x20
	// Bit HRSTSENT.
	UCPD_SR_HRSTSENT = 0x20
	// No Hard Reset message sent
	UCPD_SR_HRSTSENT_NotSent = 0x0
	// Hard Reset message sent
	UCPD_SR_HRSTSENT_Sent = 0x1
	// Position of TXUND field.
	UCPD_SR_TXUND_Pos = 0x6
	// Bit mask of TXUND field.
	UCPD_SR_TXUND_Msk = 0x40
	// Bit TXUND.
	UCPD_SR_TXUND = 0x40
	// No Tx data underrun detected
	UCPD_SR_TXUND_NoUnderrun = 0x0
	// Tx data underrun detected
	UCPD_SR_TXUND_Underrun = 0x1
	// Position of RXNE field.
	UCPD_SR_RXNE_Pos = 0x8
	// Bit mask of RXNE field.
	UCPD_SR_RXNE_Msk = 0x100
	// Bit RXNE.
	UCPD_SR_RXNE = 0x100
	// Rx data register empty
	UCPD_SR_RXNE_Empty = 0x0
	// Rx data register not empty
	UCPD_SR_RXNE_NotEmpty = 0x1
	// Position of RXORDDET field.
	UCPD_SR_RXORDDET_Pos = 0x9
	// Bit mask of RXORDDET field.
	UCPD_SR_RXORDDET_Msk = 0x200
	// Bit RXORDDET.
	UCPD_SR_RXORDDET = 0x200
	// No ordered set detected
	UCPD_SR_RXORDDET_NoOrderedSet = 0x0
	// Ordered set detected
	UCPD_SR_RXORDDET_OrderedSet = 0x1
	// Position of RXHRSTDET field.
	UCPD_SR_RXHRSTDET_Pos = 0xa
	// Bit mask of RXHRSTDET field.
	UCPD_SR_RXHRSTDET_Msk = 0x400
	// Bit RXHRSTDET.
	UCPD_SR_RXHRSTDET = 0x400
	// Hard Reset not received
	UCPD_SR_RXHRSTDET_NoHardReset = 0x0
	// Hard Reset received
	UCPD_SR_RXHRSTDET_HardReset = 0x1
	// Position of RXOVR field.
	UCPD_SR_RXOVR_Pos = 0xb
	// Bit mask of RXOVR field.
	UCPD_SR_RXOVR_Msk = 0x800
	// Bit RXOVR.
	UCPD_SR_RXOVR = 0x800
	// No overflow
	UCPD_SR_RXOVR_NoOverflow = 0x0
	// Overflow
	UCPD_SR_RXOVR_Overflow = 0x1
	// Position of RXMSGEND field.
	UCPD_SR_RXMSGEND_Pos = 0xc
	// Bit mask of RXMSGEND field.
	UCPD_SR_RXMSGEND_Msk = 0x1000
	// Bit RXMSGEND.
	UCPD_SR_RXMSGEND = 0x1000
	// No new Rx message received
	UCPD_SR_RXMSGEND_NoNewMessage = 0x0
	// A new Rx message received
	UCPD_SR_RXMSGEND_NewMessage = 0x1
	// Position of RXERR field.
	UCPD_SR_RXERR_Pos = 0xd
	// Bit mask of RXERR field.
	UCPD_SR_RXERR_Msk = 0x2000
	// Bit RXERR.
	UCPD_SR_RXERR = 0x2000
	// No error detected
	UCPD_SR_RXERR_NoError = 0x0
	// Error(s) detected
	UCPD_SR_RXERR_Error = 0x1
	// Position of TYPECEVT1 field.
	UCPD_SR_TYPECEVT1_Pos = 0xe
	// Bit mask of TYPECEVT1 field.
	UCPD_SR_TYPECEVT1_Msk = 0x4000
	// Bit TYPECEVT1.
	UCPD_SR_TYPECEVT1 = 0x4000
	// No new event
	UCPD_SR_TYPECEVT1_NoNewEvent = 0x0
	// A new Type-C event occurred
	UCPD_SR_TYPECEVT1_NewEvent = 0x1
	// Position of TYPECEVT2 field.
	UCPD_SR_TYPECEVT2_Pos = 0xf
	// Bit mask of TYPECEVT2 field.
	UCPD_SR_TYPECEVT2_Msk = 0x8000
	// Bit TYPECEVT2.
	UCPD_SR_TYPECEVT2 = 0x8000
	// No new event
	UCPD_SR_TYPECEVT2_NoNewEvent = 0x0
	// A new Type-C event occurred
	UCPD_SR_TYPECEVT2_NewEvent = 0x1
	// Position of TYPEC_VSTATE_CC1 field.
	UCPD_SR_TYPEC_VSTATE_CC1_Pos = 0x10
	// Bit mask of TYPEC_VSTATE_CC1 field.
	UCPD_SR_TYPEC_VSTATE_CC1_Msk = 0x30000
	// Lowest
	UCPD_SR_TYPEC_VSTATE_CC1_Lowest = 0x0
	// Low
	UCPD_SR_TYPEC_VSTATE_CC1_Low = 0x1
	// High
	UCPD_SR_TYPEC_VSTATE_CC1_High = 0x2
	// Highest
	UCPD_SR_TYPEC_VSTATE_CC1_Highest = 0x3
	// Position of TYPEC_VSTATE_CC2 field.
	UCPD_SR_TYPEC_VSTATE_CC2_Pos = 0x12
	// Bit mask of TYPEC_VSTATE_CC2 field.
	UCPD_SR_TYPEC_VSTATE_CC2_Msk = 0xc0000
	// Lowest
	UCPD_SR_TYPEC_VSTATE_CC2_Lowest = 0x0
	// Low
	UCPD_SR_TYPEC_VSTATE_CC2_Low = 0x1
	// High
	UCPD_SR_TYPEC_VSTATE_CC2_High = 0x2
	// Highest
	UCPD_SR_TYPEC_VSTATE_CC2_Highest = 0x3
	// Position of FRSEVT field.
	UCPD_SR_FRSEVT_Pos = 0x14
	// Bit mask of FRSEVT field.
	UCPD_SR_FRSEVT_Msk = 0x100000
	// Bit FRSEVT.
	UCPD_SR_FRSEVT = 0x100000
	// No new event
	UCPD_SR_FRSEVT_NoNewEvent = 0x0
	// New FRS receive event occurred
	UCPD_SR_FRSEVT_NewEvent = 0x1

	// ICR: UCPD Interrupt Clear Register
	// Position of TXMSGDISCCF field.
	UCPD_ICR_TXMSGDISCCF_Pos = 0x1
	// Bit mask of TXMSGDISCCF field.
	UCPD_ICR_TXMSGDISCCF_Msk = 0x2
	// Bit TXMSGDISCCF.
	UCPD_ICR_TXMSGDISCCF = 0x2
	// Clear flag in UCPD_SR
	UCPD_ICR_TXMSGDISCCF_Clear = 0x1
	// Position of TXMSGSENTCF field.
	UCPD_ICR_TXMSGSENTCF_Pos = 0x2
	// Bit mask of TXMSGSENTCF field.
	UCPD_ICR_TXMSGSENTCF_Msk = 0x4
	// Bit TXMSGSENTCF.
	UCPD_ICR_TXMSGSENTCF = 0x4
	// Clear flag in UCPD_SR
	UCPD_ICR_TXMSGSENTCF_Clear = 0x1
	// Position of TXMSGABTCF field.
	UCPD_ICR_TXMSGABTCF_Pos = 0x3
	// Bit mask of TXMSGABTCF field.
	UCPD_ICR_TXMSGABTCF_Msk = 0x8
	// Bit TXMSGABTCF.
	UCPD_ICR_TXMSGABTCF = 0x8
	// Clear flag in UCPD_SR
	UCPD_ICR_TXMSGABTCF_Clear = 0x1
	// Position of HRSTDISCCF field.
	UCPD_ICR_HRSTDISCCF_Pos = 0x4
	// Bit mask of HRSTDISCCF field.
	UCPD_ICR_HRSTDISCCF_Msk = 0x10
	// Bit HRSTDISCCF.
	UCPD_ICR_HRSTDISCCF = 0x10
	// Clear flag in UCPD_SR
	UCPD_ICR_HRSTDISCCF_Clear = 0x1
	// Position of HRSTSENTCF field.
	UCPD_ICR_HRSTSENTCF_Pos = 0x5
	// Bit mask of HRSTSENTCF field.
	UCPD_ICR_HRSTSENTCF_Msk = 0x20
	// Bit HRSTSENTCF.
	UCPD_ICR_HRSTSENTCF = 0x20
	// Clear flag in UCPD_SR
	UCPD_ICR_HRSTSENTCF_Clear = 0x1
	// Position of TXUNDCF field.
	UCPD_ICR_TXUNDCF_Pos = 0x6
	// Bit mask of TXUNDCF field.
	UCPD_ICR_TXUNDCF_Msk = 0x40
	// Bit TXUNDCF.
	UCPD_ICR_TXUNDCF = 0x40
	// Clear flag in UCPD_SR
	UCPD_ICR_TXUNDCF_Clear = 0x1
	// Position of RXORDDETCF field.
	UCPD_ICR_RXORDDETCF_Pos = 0x9
	// Bit mask of RXORDDETCF field.
	UCPD_ICR_RXORDDETCF_Msk = 0x200
	// Bit RXORDDETCF.
	UCPD_ICR_RXORDDETCF = 0x200
	// Clear flag in UCPD_SR
	UCPD_ICR_RXORDDETCF_Clear = 0x1
	// Position of RXHRSTDETCF field.
	UCPD_ICR_RXHRSTDETCF_Pos = 0xa
	// Bit mask of RXHRSTDETCF field.
	UCPD_ICR_RXHRSTDETCF_Msk = 0x400
	// Bit RXHRSTDETCF.
	UCPD_ICR_RXHRSTDETCF = 0x400
	// Clear flag in UCPD_SR
	UCPD_ICR_RXHRSTDETCF_Clear = 0x1
	// Position of RXOVRCF field.
	UCPD_ICR_RXOVRCF_Pos = 0xb
	// Bit mask of RXOVRCF field.
	UCPD_ICR_RXOVRCF_Msk = 0x800
	// Bit RXOVRCF.
	UCPD_ICR_RXOVRCF = 0x800
	// Clear flag in UCPD_SR
	UCPD_ICR_RXOVRCF_Clear = 0x1
	// Position of RXMSGENDCF field.
	UCPD_ICR_RXMSGENDCF_Pos = 0xc
	// Bit mask of RXMSGENDCF field.
	UCPD_ICR_RXMSGENDCF_Msk = 0x1000
	// Bit RXMSGENDCF.
	UCPD_ICR_RXMSGENDCF = 0x1000
	// Clear flag in UCPD_SR
	UCPD_ICR_RXMSGENDCF_Clear = 0x1
	// Position of TYPECEVT1CF field.
	UCPD_ICR_TYPECEVT1CF_Pos = 0xe
	// Bit mask of TYPECEVT1CF field.
	UCPD_ICR_TYPECEVT1CF_Msk = 0x4000
	// Bit TYPECEVT1CF.
	UCPD_ICR_TYPECEVT1CF = 0x4000
	// Clear flag in UCPD_SR
	UCPD_ICR_TYPECEVT1CF_Clear = 0x1
	// Position of TYPECEVT2CF field.
	UCPD_ICR_TYPECEVT2CF_Pos = 0xf
	// Bit mask of TYPECEVT2CF field.
	UCPD_ICR_TYPECEVT2CF_Msk = 0x8000
	// Bit TYPECEVT2CF.
	UCPD_ICR_TYPECEVT2CF = 0x8000
	// Clear flag in UCPD_SR
	UCPD_ICR_TYPECEVT2CF_Clear = 0x1
	// Position of FRSEVTCF field.
	UCPD_ICR_FRSEVTCF_Pos = 0x14
	// Bit mask of FRSEVTCF field.
	UCPD_ICR_FRSEVTCF_Msk = 0x100000
	// Bit FRSEVTCF.
	UCPD_ICR_FRSEVTCF = 0x100000
	// Clear flag in UCPD_SR
	UCPD_ICR_FRSEVTCF_Clear = 0x1

	// TX_ORDSETR: UCPD Tx Ordered Set Type Register
	// Position of TXORDSET field.
	UCPD_TX_ORDSETR_TXORDSET_Pos = 0x0
	// Bit mask of TXORDSET field.
	UCPD_TX_ORDSETR_TXORDSET_Msk = 0xfffff

	// TX_PAYSZR: UCPD Tx Paysize Register
	// Position of TXPAYSZ field.
	UCPD_TX_PAYSZR_TXPAYSZ_Pos = 0x0
	// Bit mask of TXPAYSZ field.
	UCPD_TX_PAYSZR_TXPAYSZ_Msk = 0x3ff

	// TXDR: UCPD Tx Data Register
	// Position of TXDATA field.
	UCPD_TXDR_TXDATA_Pos = 0x0
	// Bit mask of TXDATA field.
	UCPD_TXDR_TXDATA_Msk = 0xff

	// RX_ORDSETR: UCPD Rx Ordered Set Register
	// Position of RXORDSET field.
	UCPD_RX_ORDSETR_RXORDSET_Pos = 0x0
	// Bit mask of RXORDSET field.
	UCPD_RX_ORDSETR_RXORDSET_Msk = 0x7
	// SOP code detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOP = 0x0
	// SOP' code detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPPrime = 0x1
	// SOP'' code detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPDoublePrime = 0x2
	// SOP'_Debug detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPPrimeDebug = 0x3
	// SOP''_Debug detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPDoublePrimeDebug = 0x4
	// Cable Reset detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_CableReset = 0x5
	// SOP extension #1 detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPExtension1 = 0x6
	// SOP extension #2 detected in receiver
	UCPD_RX_ORDSETR_RXORDSET_SOPExtension2 = 0x7
	// Position of RXSOP3OF4 field.
	UCPD_RX_ORDSETR_RXSOP3OF4_Pos = 0x3
	// Bit mask of RXSOP3OF4 field.
	UCPD_RX_ORDSETR_RXSOP3OF4_Msk = 0x8
	// Bit RXSOP3OF4.
	UCPD_RX_ORDSETR_RXSOP3OF4 = 0x8
	// 4 correct K-codes out of 4
	UCPD_RX_ORDSETR_RXSOP3OF4_AllCorrect = 0x0
	// 3 correct K-codes out of 4
	UCPD_RX_ORDSETR_RXSOP3OF4_OneIncorrect = 0x1
	// Position of RXSOPKINVALID field.
	UCPD_RX_ORDSETR_RXSOPKINVALID_Pos = 0x4
	// Bit mask of RXSOPKINVALID field.
	UCPD_RX_ORDSETR_RXSOPKINVALID_Msk = 0x70
	// No K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_Valid = 0x0
	// First K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_FirstCorrupted = 0x1
	// Second K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_SecondCorrupted = 0x2
	// Third K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_ThirdCorrupted = 0x3
	// Fourth K-code corrupted
	UCPD_RX_ORDSETR_RXSOPKINVALID_FourthCorrupted = 0x4

	// RX_PAYSZR: UCPD Rx Paysize Register
	// Position of RXPAYSZ field.
	UCPD_RX_PAYSZR_RXPAYSZ_Pos = 0x0
	// Bit mask of RXPAYSZ field.
	UCPD_RX_PAYSZR_RXPAYSZ_Msk = 0x3ff

	// RXDR: UCPD Receive Data Register
	// Position of RXDATA field.
	UCPD_RXDR_RXDATA_Pos = 0x0
	// Bit mask of RXDATA field.
	UCPD_RXDR_RXDATA_Msk = 0xff

	// RX_ORDEXTR1: UCPD Rx Ordered Set Extension Register
	// Position of RXSOPX1 field.
	UCPD_RX_ORDEXTR1_RXSOPX1_Pos = 0x0
	// Bit mask of RXSOPX1 field.
	UCPD_RX_ORDEXTR1_RXSOPX1_Msk = 0xfffff

	// RX_ORDEXTR2: UCPD Rx Ordered Set Extension Register
	// Position of RXSOPX2 field.
	UCPD_RX_ORDEXTR2_RXSOPX2_Pos = 0x0
	// Bit mask of RXSOPX2 field.
	UCPD_RX_ORDEXTR2_RXSOPX2_Msk = 0xfffff
)

// Constants for VREFBUF: Voltage reference buffer
const (
	// CSR: VREF control and status register
	// Position of ENVR field.
	VREF_CSR_ENVR_Pos = 0x0
	// Bit mask of ENVR field.
	VREF_CSR_ENVR_Msk = 0x1
	// Bit ENVR.
	VREF_CSR_ENVR = 0x1
	// Position of HIZ field.
	VREF_CSR_HIZ_Pos = 0x1
	// Bit mask of HIZ field.
	VREF_CSR_HIZ_Msk = 0x2
	// Bit HIZ.
	VREF_CSR_HIZ = 0x2
	// Position of VRS field.
	VREF_CSR_VRS_Pos = 0x2
	// Bit mask of VRS field.
	VREF_CSR_VRS_Msk = 0x4
	// Bit VRS.
	VREF_CSR_VRS = 0x4
	// Position of VRR field.
	VREF_CSR_VRR_Pos = 0x3
	// Bit mask of VRR field.
	VREF_CSR_VRR_Msk = 0x8
	// Bit VRR.
	VREF_CSR_VRR = 0x8

	// CCR: calibration control register
	// Position of TRIM field.
	VREF_CCR_TRIM_Pos = 0x0
	// Bit mask of TRIM field.
	VREF_CCR_TRIM_Msk = 0x3f
)

// Constants for WWDG: System window watchdog
const (
	// CR: Control register
	// Position of WDGA field.
	WWDG_CR_WDGA_Pos = 0x7
	// Bit mask of WDGA field.
	WWDG_CR_WDGA_Msk = 0x80
	// Bit WDGA.
	WWDG_CR_WDGA = 0x80
	// Watchdog disabled
	WWDG_CR_WDGA_Disabled = 0x0
	// Watchdog enabled
	WWDG_CR_WDGA_Enabled = 0x1
	// Position of T field.
	WWDG_CR_T_Pos = 0x0
	// Bit mask of T field.
	WWDG_CR_T_Msk = 0x7f

	// CFR: Configuration register
	// Position of EWI field.
	WWDG_CFR_EWI_Pos = 0x9
	// Bit mask of EWI field.
	WWDG_CFR_EWI_Msk = 0x200
	// Bit EWI.
	WWDG_CFR_EWI = 0x200
	// interrupt occurs whenever the counter reaches the value 0x40
	WWDG_CFR_EWI_Enable = 0x1
	// Position of WDGTB field.
	WWDG_CFR_WDGTB_Pos = 0x7
	// Bit mask of WDGTB field.
	WWDG_CFR_WDGTB_Msk = 0x180
	// Counter clock (PCLK1 div 4096) div 1
	WWDG_CFR_WDGTB_Div1 = 0x0
	// Counter clock (PCLK1 div 4096) div 2
	WWDG_CFR_WDGTB_Div2 = 0x1
	// Counter clock (PCLK1 div 4096) div 4
	WWDG_CFR_WDGTB_Div4 = 0x2
	// Counter clock (PCLK1 div 4096) div 8
	WWDG_CFR_WDGTB_Div8 = 0x3
	// Position of W field.
	WWDG_CFR_W_Pos = 0x0
	// Bit mask of W field.
	WWDG_CFR_W_Msk = 0x7f

	// SR: Status register
	// Position of EWIF field.
	WWDG_SR_EWIF_Pos = 0x0
	// Bit mask of EWIF field.
	WWDG_SR_EWIF_Msk = 0x1
	// Bit EWIF.
	WWDG_SR_EWIF = 0x1
	// The EWI Interrupt Service Routine has been serviced
	WWDG_SR_EWIF_Finished = 0x0
	// The EWI Interrupt Service Routine has been triggered
	WWDG_SR_EWIF_Pending = 0x1
)
